T1040
Contents
1. GMII SEL 061 RCW EC2 0500 FMan MACS RCW EC2 0501 FMan 10 freescale External Use 30 T1 T2 compatible Serdes Configurations 2 FMAN item amp MACS 0x40 sg m1 2 RGMII FMAN 1 25 amp MACS 0 5 RGMII OxAA 0 RGMII e T1 T2 compatible SerDes Configurations continue T2081 SRDS PRTCL S1 OxF2 2 FMAN SG10 PEX4 MAC3 amp 1 25 8 5 2 5 OxF8 2 FMAN SG10 SG1 MAC3 amp MAC4 1 25 3 125 59 53 59 51 59 52 59 56 59 54 59 55 1 25 1 25 1 25 1 25 1 25 1 25 OxCA 1 RGMII FMAN SATA1 0xDE 2 RGMII FMAN SATA2 SATA1 PEX4 2 RGMII FMAN 8 5 2 5 MAC3 amp MAC4 10 freescale Reset Configuration Word RCW are mostly compatible Detail listed in T1040 and T2080 reference manual 10 15 176 177 190 191 242 321 418 419 420 421 v 2 freescale MEM_PLL_CFG SRDS_DIV_PEX DDR_FDBK_ MUL SYS_PLL_SPD UC1_CTSB_ CDB_SEL 1 2 External Use 33 Reserved Reserved Reserved Cutoff frequencies for the T1 and T2 differ 24 1 async mode setting is available for T1 T1 00 Train up to 5G T2 00 Train up to 8G Using different MAC T1 MAC 4 and 2 T2 MAC 3 Using different MAC T1 MAC 5 T2 MAC 4 10 Difference in driver To limit2. DAT 1 3 CLK CD In DDR mode all the input signals are sampled DIR with respect tc Other signals should be left NC SYNC OUT should be pulled down with a weak resistor or the pin should be configured for alternate functionality Voltage translator is not needed for 1 8V MMC 4 e freescale External Use 18 MMC 1 8V Connections for T1 T2 Compatibility DDR Mode SDHC_CLK_SYNC_OUT SDHC_CLK_SYNC_IN lt 4 CMD DAT 0 DAT 1 7 CLK CD Other signals should be left NC freescale External Use 19 TEST SEL B Pin The requirement is different for T1040 and T2081 T1040 T1042 Pull up to O1TVDD T1020 T1022 Pull down to GND T2081 Pull up to OVDD freescale External Use 20 Sense Pins If the sense pins are used for the regulators SENSEVDD should be used SENSEVDDC can be left floating Ball Location T2081 T1040 G19 SENSEVDD SENSEVDD AB9 RSVD28 SENSEVDDC ZAS freescale External Use 21 Power sequencing requirements 1040 requires its power rails to rampup a specific sequence whereas T2081 has no such requirement Common board should follow T1040 hardware specification for the Power sequencing requirements Case Power ON otep 1 I O supplies should ramp up 1 8V 2 5V 3 3V PORESET should be asserted when VDDC VDD rampup Step 2 Core supplies 1 0V USB SVDD I O power should ramp before core power ot
3. FREESCALE TECHNOLOGY FORUM 2014 FTF Design with the QorlQ T2081 and 11040 Processor Families FTF NET F0140 Xiaobo Xie Chun Chang Application Engineer MAY 2014 e 9 2 freescale arn traciereatus of Serricondacter ic offer product or sereta ace property of eet respects 7014 Freancaim Sermeconductor ge Session Introduction This session is relevant for customers designing with Freescale T2081 and T1040 family of QorlQ processors Details the commonalities and differences Examines the problems and solutions of common board design and migration from T1040 to T2081 Provides practical examples based on existing Freescale designs Nw freescale External Use 1 Session Objectives After completing this session you will be able to Identify the design collateral that exists to assist with T1040 and T2081 designs Recognize the major design issues for the common board design and how they can be overcome Use our design tips for high speed interface design eSDHC and SerDes Know where to go for assistance m freescale External Use 2 Agenda ii 1040 and T2081 Overview Hardware Compatibility Software Compatibility e Pinout Comparison e Supporting Tools Reference Documentation freescale External Use 3 Agenda ii e 1040 and T2081 Overview 1040 Block Diagr
4. Switching 1MB L3 platform cache w ECC 2 64b DDR4 up to 2 4GT s A high performance datapath designed Data with software developers in mind Center New datapath hardware and abstracted acceleration that is called via standard Linux objects 40 Gbps Packet processing performance with Wireless 20Gbps acceleration crypto Pattern Access Match RegEx Data Compression Management complex provides all init setup teardown tasks Leading network I O integration Unprecedented performance and 8x1 10GbE 8x1G MACSec on up to 1 10GbE ease of use for smarter more Integrated L2 switching capability for cost savings 4 PCle controllers 1 with SR IOV support 2x SATA 3 0 2 x USB 3 0 with PHY capable networks m freescale External Use 51 See the LS2 Family First in the Tech Lab 4 new demos built on QorlQ LS2 processors 6 Performance Analysis Made Easy Leave the Packet Processing Us d Combining Ease of Use with Performance Tools for Every Step of Your Design N e e freescale External Use 52 Designing with Freescale 2014 seminar topics include QorlQ product family update e Kinetis K L E V series MCU product training freescale 2 freescale www Freescale com 2014 Freescale Semiconductor Inc External Use Use a Common Board e With the introduction of the T1040 T2081 customers can now create common b
5. Connections for T1 T2 Compatibility DS and HS Modes Voltage Translator T1040 T2081 lt DAT 0 DAT 1 3 CLK CD B WP e Other signals should be left NC e SYNC OUT should be pulled down with a weak resistor or the pin should be configured for alternate functionality 4 freescale External Use 15 SD Connections for T1 T2 Compatibility SDR12 25 50 104 and DDR50 Modes Voltage Voltage Regulator Regulator 1 8V 3 3V Voltage Select SDHC_VS Smart 3 3V 1 8V Voltage Translator 3 3V 1 8V SD CARD work 1 8V SDHC CLK SYNC IN lt 4 CMD DAT 0 DAT 1 3 CD B WP j gt DIR Other signals should be left NC SYNC OUT should be pulled down with a weak resistor or the pin should be configured for alternate functionality T gt gt freescale External Use 16 MMC Card Connections for T1 T2 Compatibility DS HS HS200 Modes T1040 T2081 lt Translator lt gt CMD DAT O DAT 1 7 CLK CD e Other signals should be left NC e SYNC OUT should be pulled down with a weak resistor or the pin should be configured for alternate functionality e Voltage translator is not needed for 1 8V MMC v freescale External Use 17 MMC 3 3V Connections for T1 T2 Compatibility DDR Mode Voltage Translator 3 3V 1 8V T1040 T2081 MMC 3 3V SDHC_CLK_SYNC_IN lt gt CMD
6. KB 2MB Banked L2 Datapath Acceleration SEC crypto acceleration 10Gbps DCE Data Compression Engine 17 5Gbps PME Pattern Matching Engine to 10Gbps 22 freescale 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB D Cachef Cache DAEN Cache D Cachef MESI 512KB Platform Parse Classify Distribute 8ch 8ch DMA DCB 8 Lane 10GHz SERDES External Use 6 8ch DMA PCle Watchpoint Cross Trigger Perf Monitor CoreNet Trace Processor 4x 6500 646 1 5 1 8GHz Dual threaded with 128b AltiVec 2MB shared L2 256KB per thread Memory Subsystem 512KB Platform Cache w ECC 1x DDR3 3L Controllers up to 2 1 GHz Upto 1TB addressability 40 bit physical addressing HW Data Pre fetching Switch Fabric High Speed Serial IO 4 PCle Controllers one at Gen3 three at Gen2 1 with SR IOV support x8 Gen2 2USB 2 0 with PHY Network IO Up to 25Gbps Simple PCD each direction 8 MACs multiplexed over 2x 10GE 2x 2 5Gb s SGMII 7x GE XFI 10GBase KR SGMII RGMII 1000Base KX Device TSMC 28HPM Process 23x23mm 780pins 0 8mm pitch pin compatible with T1042 Power estimated at 18 7 24 4W thermal depending on frequency Schedule samples 2H 2014 qual Q1 15 Device Comparison T1040 and T2081 FMan Realtime ify eSPI distribute Watch point Buffer cross 2 x DUART trigger CoreNe
7. single source clocking option Do not use for common board freescale External Use 42 Agenda ii 1040 and T2081 Overview e Hardware Compatibility Software Compatibility e Pinout Comparision e Supporting Tools freescale External Use 43 T1040 T2081 Software amp Tools at a Glance Two Reference Design Boards T1040RDB T1042RDB e Software Support Yocto based SDK SDK support includes Legacy features refer SDK 1 4 release notes New features FMAN and microcode Linux based QE drivers for TDM UART and HDLC e QorlQ Configuration Suite CodeWarrior based debugger flash programmer 4 gt gt freescale External Use 44 T1040 T2081 RDB System freescale External Use 45 T1040 T2081 RDB Block Diagram POR cfg Clocking QE connector for PMC plug in card USB TypeA x 2 SATA sara 1040 2081 Realtek RJ45 Moo RJ45 Realtek RJ4F Vitesse SDXC Vitesse JAG SDXC Card Gard freescale External Use 46 USB2 0 USB2 0 LX 810d 80d 80d N Q 42 z a Agenda ii 1040 and T2081 Overview Hardware Compatibility Software Compatibility e Pinout Comparision e Supporting Tools Reference Documentation freescale External Use 47 Reference Documentation v T10
8. 40 Hardware Specification and Reference Manual v T2081 Hardware Specification and Reference Manual v Application Note AN4733 T1040 to T2081 Migration Guide v T1040 T2081 Design Checklist v T1040 RDB User Manual v T1040 RDB Schematic freescale External Use 48 Session Closing By now you should be able to Use Freescale s design collateral to aid your own T1040 and T2081 designs Understand the commonalities and differences between these devices Understand the unique challenges facing 11040 and T2081 common design and the solutions to overcome them m freescale External Use 49 Breakthrough software defined Groundbreaking flexible architecture that abstracts hardware complexity and approach to advance enables customers to focus their resources on innovation at the application level the world s new virtualized networks Balanced integration of CPU performance with network I O and C programmable datapath acceleration that is right sized power performance cost to deliver advanced SoC technology for the SDN era Built on the ARM Cortex8 A57 architecture with integrated L2 switch enabling interconnect and peripherals to provide a complete system on chip solution freescale 50 9 QorlQ LS2 Family Key Features High performance cores with leading interconnect and memory bandwidth SDN NFV 8x Cortex A57 cores 2 0GHz 4MB L2 cache w Neon SIMD
9. 5 IIC4_SCL GPIO4_02 EVT5_B DIU_HSYNC Additional DIU functionality is available in T1040 over 2 pins AB3 4 SDA GPIO4 03 EVT6 IIC4 SDA GPIO4 03 EVT6 B DIU VSYNC freescale External Use 40 Pinout Comparison QE DIU pins T1040 Compatible connection RSVD15 CLKO9 GPIO4 15 BRGO2 DIU D10 QE and DIU are only available on T1040 If d configure the pi RSVD14 CLK10 GPIO4 22 BRGO3 DIU D11 Hc a RSVD13 CLK11 GPIO4 16 BRG04 DIU DE RSVD12 CLK12 GPIO4 23 BRG01 DIU CLK OUT RSVD17 RQ GPIO4 14 DIU D4 UC1 CDB RXER Ui RSVD23 RSYNC GPIO4 11 DIU D1 UC1 CT SB RXDV U2 RSVD24 RXD GPIO4 10 DIU Do UC1 RXD7 EN TDMA TSYNC GPIO4 13 UC1 RTSB TXE D3 RSVD20 TXD GPIO4 12 UC1 TXD7 DIU D2 EN RSVD19 TDMB RO GPIO4 21 DIU D9 UC3 RXER T3 RSVD21 TDMB RSYNC GPIO4 18 DIU D6 UC3 CT SB RXDV RSVD25 TDMB_RXD GPIO4_17 DIU_D5 UC3_RXD7 RSVD18 TDMB TSYNC GPIO4 20 UC3 RTSB TXE Da RSVD22 TDMB TXD GPIO4 19 UC3 TXD7 DIU D7 2 freescale External Use 41 Pinout Comparison LP_Trust pin R LP TMP DETECTB TMP DETECT B RSVDIS LP_Trust is only supported by T2081 Loo LP TMP DETECT a RSVD13 OVDD through a 10K resistor Pull up through a 10K resistor to 1 0V RSVD28 SENSEVppc Use SENSEVpp and SENSEGND RSVD29 SENSEGNDC por_config pins 013 IFC WEO B eng 0 Used in T1040 for selection of
10. SPI 1 8V 1 8V SDHC_DAT 4 7 3 3V Use OVpp supply for SDHC DAT 0 3 SDHC CMD Common eSDHC 1 8V and SDHC CLK are the signals See Note on EVpp supply in T1040 These signals are on OVpp supply in T2081 See OV pp supply for details G1Vpp 1 5 1 35V Use G1Vpp at 1 35V Use DDR3L only Common DDR3L 1 35V 1 2V T1040 DDR4 T2081 DDR3 L1Vpp 3 3V Use Single regulator for LVpp Use RGMII interface at 2 5V only Common GPIO 2 5V L1Vpp on T1040 RGMII 2 5V 1 8V It can support 2 5V or 1 8V T1040 Mil RGMII 1 8V LVpp 2 5V 3 3V 1 8V 2 5V 1 8V z freescale External Use 24 Clocking Difference T1040 supports the differential pair of SYSCLK the common board design leaves it as floating or connect through 10K Ohm resistor to GND Clocking scheme Recommendation Single Reference clock mode No Yes T1040 Supported through DIFF SYSCLK DIFF SYSCLK B clock input pair Multiple reference clock mode Yes Yes Through separate oscillators for SYSCLK DDRCLK USBCLK SDREF CLKn inputs Recommended mode for common board design ER CAS freescale External Use 25 Exceptions PCle Mil Starlite TDM EC1 T1040 4Gen2 Yes Yes Yes T2081 1 Gens NO NO NO Gen 2 N 2 freescale External Use 26 Yes NO Yes NO No Yes Yes NO Yes NO Yes NO Agenda ii e 1040 and T2081 Overview e Hardware Compa
11. am 2081 Block Diagram Device Comparison Commonalities and Differences 4 freescale 4 T1040 Processor Power Architecture 5500 64b up to 1 4GHz 22200 Each with 256KB backside L2 cache 32 KB 32 KB 256KB Shared Platform Cache w ECC 256KB m Cache Supports up to 64GB addressability 36 bit physical addressing Co al Memory Subsystem 32 646 DDR3L 4 Controller up to 1600MHz CoreNet Switch Fabric ao High Speed Serial IO Watchpoint Cross ss ae Trigger 4x PCle Gen2 5Gbps Controllers EE 2x SATA 2 0 3Gbps o o Perf 2 U Monitor 2x USB 2 0 with PHY Network Gaeta canta FMan packet Parse Classify Distribute Device Datapath Acceleration Lossless Flow Control IEEE 1588 780 pin FC PBGA package e SEC crypto acceleration Up to 4x 10 100 1000 Ethernet Controllers e 23x23mm 0 8mm pitch sA PME Reg ex Pattern 8 Port Gigabit Ethernet Switch Power targets 9 QUICC Engine Enable Convection cooled HDLC 2 TDM system design Green Energy Operation Fanless operation quad core 1 4GHz Packet lossless deepsleep Programmable wake on packet Wake on timer GPIO USB IRQ vA freescale 1 QorlQ T2081 Block Diagram Power Power 6500 e6500 Power Power 6500 e6500 32 KB D Cache 32
12. driver configuration issues take the following actions to simplifying the driver configuration Number of cores T1040 4 single threaded e5500 cores running at 1000 2 1200 2 1400 2 12080 4 dual threaded e6500 cores 8 virtual cores running at 1200MHz 1533MHz 1800MHz Using 1200 2 for both core CPC size T1040 256 Kbyte 8 way set associative 64 byte coherency granule T2080 512 Kbyte 16 way set associative 64 byte coherency granule Use 256 Kbyte 8 way set associative 64 byte coherency granule L2 size 11040 256KB per e5500 core total 1MB T2080 2MB shared by 4 e6500 cores Use 256KB per thread 2 freescale External Use 34 Difference in driver continue DDR T1040 one 32 64 bit DDR3L DDR4 SDRAM memory controller with ECC and interleaving support T2080 one 32 64 bit DDR3 3L SDRAM memory controller with ECC and interleaving support and Memory pre fetch engine Select cfg dram type 1 to choose DDR3L Ethernet Mace 4 MACs from FMan and 8 MAC from Ethernet Switch It supports two RGMII ports using MAC4 amp 5 T2080 8 MACs from FMan four 1G and four 1 2 5 10G running with various combinations with different SerDes procotols Two RGMII ports using MAC3 amp 4 ports using 9 10 1 2 Using RGMII requires the software driver to remap the different MACs between T1 and 2 choose a pin compatible configuration for SerDes o
13. ep 3 DDR supplies G1VDD X1VDD VDD should ramp before G1VDD M N oe freescale External Use 22 Power Supply for Core Core Power Island Requirements T1040 has VDD VDDC power domains for core and platform 2081 has only VDD power domain for core and platform The common board design should use a single rail for VDD and VDDC in T1040 VDD VDD VDDC VDD and VDD should be connected to a common rail M CAS 2 freescale External Use 23 Power Supply for I O Supply T2081 T1040 Recommendation for Interface wise recommendation Interfaces common board design OtVpp 18V Use Single regulator for OVpp eSDHC interface of T2081 ison Common MPIC GPIO and O1Vpp on T1040 at 1 8V OVpp supply while IO power System Control Debug OVpp 18V 18V supply of eSDHC in T1040 is fed Clocks JTAG l O IFC by EVpp If eSDHC is used EVpp RTC and power and OVpp should be connectedto management l O s 1 8V On board level shifters are T2081 only eSDHC required to support SD 3 0 modes DVpp 2 5V 3 3V Use2 5V or 1 8V only for DVpp DIU and TDM are supported at Common DUART 2 1 8V 2 5V supply 3 3V so voltage translators may DMA MPIC 1 8V be required on a common board QE interface is supported at 2 5V T1040 only and 3 3V restricting DVppto 2 5V DIU for common board CVpp 2 5V 3 3V Use 1 8V for CVpp supply Common e
14. oards for both devices 11040 and 12081 are pin compatible One common board design would reduce design time and save cost Make migration much faster and easier Nw freescale External Use 55 2 freescale www Freescale com 2014 Freescale Semiconductor Inc External Use
15. ption PCle T1040 four PCI Express 2 0 controllers ports running at up to 2 5 5GHz T2080 two PCI Express 2 0 running at 2 5 5GHz and two PCI Express 3 0 controllers ports running at 2 5 5 8GHz Using 2 5 5GHz only freescale External Use 35 Difference in driver continue SATA 11040 and T2080 have same two SATA controllers supporting 1 5 and 3 0 Gbps operation there is no defference in software configuration QE T1040 support QE with two TDM interfaces u boot doesn t support TDM T2080 no support DIU T1040 support LCD and HDMI interface DIU with 12 bit dual data rate T2080 no support m freescale External Use 36 Difference in driver continue PAMU no changes in S W DMA T2081 vs 2 in T1040 e GE switch if used on board add if config only for T1040 e IFC same so no changes Single Source Clocking USB considerations only for T1040 Deep sleep only for T1040 N freescale External Use 37 Agenda i 1040 and T2081 Overview Hardware Compatibility Software Compatibility e Pinout Comparision e Supporting Tools Reference Documentation freescale External Use 38 Pinout Comparison This table details the differences in pinout between the T2081 and T1040 processor family and how to resolve this difference Unless explicitly stated otherwi
16. se the pins on the T2081 can be connected as if T1040 is populated C 22 RN inte Ethernet Cont 1 pins RSVD34 Interface T1040 also supports interface see Section 3 8 Ethernet MACs options This output pin can be left floating if not used AC2 25 033 ECLRXER RX Tie low 2 10 kohm resistor if TL NENNEN COL EN De Differential SYSCLK pins see Section 4 Internal clocking differences RSVDo7 DIFF SYSCLK Differential SYSCLK input is available only T1040 These can be left floating RSVDos DIFF SYSCLK B or connected to GND if unused freescale External Use 39 Pinout Comparison DMA TDM pins DMA1 DACKO B GIPIO4 05 DMA1 DACKO B GIPIO4 05 TDM TFS Additional TDM functionality is available in T1040 over DMA pins When used DMA1 DDONEO BIGPIO4 06 DMA1 DDONEO B GPIO4 06 TDM software needs to manage the interface PS DMA1 DREQO B GPIO4 04 DMA1 DREQO B GPIO4 04 TDM TXD on T2081 AAS DMA2 DACKO B GIPIO4 o8 E DMA2 DACKO B GIPIO4 08 EVT7 B TDM VT7 B _RFS DMA2 DDONEO 4_09 DMA2 DDONEO B GPIO4 09 EVT8 B TD EVT8 B M RCK DMA2 B GPIO4 07 DMA2 DREQO B GPIO4 07 TDM 12 3 4 4 pins IIC3 SCL GPIO4 00 SCL GPIO4 00 0 511 STROBEO Additional QE functionality is available in T1040 over I2C pins SDA GPIO4 01 SDA GPIO4 01 QE SH STROBE1 4 SCL GPIO4 02 EVT
17. supported YSCLK B supported Power Management Deep Sleep Supported Supported Package 780 FC PBGA 23 mm x 23 mm 23 mm x 23 mm 23 mm x 23 mm Nw freescale External Use 10 Agenda e 1040 and T2081 Overview e Hardware Compatibility Identical Interfaces DDR Controller eSDHC Controller TEST SEL B pin Sense Pins Power Sequencing Power Supply Clock Difference gt gt freescale External Use 11 Identical Interfaces The following interfaces are identical between the T2081 and T1040 v Integrated Flash Controller IFC v Enhanced SPI Controller eSPI v DUART Controller v USB Controller freescale External Use 12 DDR Controller T2081 supports DD3 3L DDR controller 11040 supports DDR3L 4 As DDR3L is common to both devices it should be used for the common board design DDR Calibration Resistor Values NENNEN NN T1040 162 ohm 1 162 ohm 1 T2081 187 ohm 196 187 ohm 196 N freescale External Use 13 eSDHC Controller eSDHC Controller Recommendations Both T1 and T2 supports SD 3 0 specification introducing higher capacity up to 2 TB and frequency up to 208 MHz A dynamic switching of I O voltage from 3 3 V to 1 8V is required 2081 doesn t support the dynamic switch so the board level shifters are required for common board design freescale External Use 14 SD Card
18. t 1GE 8 88 Monitor trace Fc 1GE 6 2 USB2 0 w PHY wr 8 lanes Serdes 2 om Figure 3 Device compatibility between T2081 and T1040 chip packages e freescale External Use 7 Commonalities and Differences Features T2081 T1040 T1042 Cores Number of cores 4 x 6500 dual 4 x e5500 Power 4 x 5500 Power threaded Power Architecture Architecture Architecture Memory Size Maximum size of main 32 GB 1Gbit x8 32 GB 1Gbit x8 32 GB 1Gbit x8 memory device device device freescale Commonalities and Differences contd Features Ethernet controllers 2x 2x 5Gbps QSGMII 1Gbps SGMII 6x SGMII 6x 1Gbps SGMII 2x 2 5Gbps SGMII 2 2 5Gbps SGMII 2x RGMII 2x RGMII 2x RGMII 1x 1x SerDes lanes 8 lanes at up to 10GHz 8 lanes at up to 5 GHz 8 lanes at up to 5 GHz PCI Express 3 x Gen 2 0 controllers 4 x Gen 2 0 controllers 4 x Gen 2 0 controllers controllers 1 x Gen 3 0 controllers SATA 2 x SATA controllers TDM Full duplex serial CoreNet 600MHz at 128 bits Ethernet switch None freescale m Commonalities and Differences contd Features T2081 T1040 T1042 Integrated Flash 8 16 bit data width 8 16 bit data width 8 16 bit data width Controller IFC 32 bit address width 32 bit address width 32 bit address width Clocking Single source clocking None Diff SYSCLK DIFF S Diff SYSCLK DIFF S YSCLK B
19. tibility Software Compatibility e6500 and e5500 Compatibility RGMII SerDes Configuration RCW Difference In driver freescale External Use 27 e6500 and e5500 Compatibility User code runs equally well on 6500 or e5500 Interrupts per thread Soft reset per thread hard reset per core only Debug state per thread Changes are hidden by OS L2 initialization uses a different register Cache locking controlled differently Additional enablement for new features not present on e5500 646 drowsy power manager Altivec m freescale External Use 28 5500 6500 Caching Structure Differences ENL CEN L1 32KB Can lock per core 32kB Can lock per core e6500 doesn t lock per thread L2 128KB per core 2MB shared There will be a somewhat different latency profile overall improved for e6500 L3 256KB 512kB Cache changes are transparent to user application e L1 locking is less granular in e6500 m freescale External Use 29 RGMII The two interfaces are pin compatible the configurations for mode are different between the T2081 and T1040 devices 1040 also supports MII interface on EC1 Interface When using MII interface L1VDD and LVDD are restricted to 3 3V and RGMII cannot be supported on EC1 or EC2 RGMII assignment Configuration T2081 T1040 ROW EC1 0600 FMan 2 GMII SEL
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