MPC7400 Part Number Specification
Contents
1. CPU Package Type Er Process Mask Code Frequency oe Atal MHz 360 HIP5P 89J87W 400MHz XPC7400RX400PK CBGA or 450MHz XPC7400RX450PK 89K62D f So0MHz XPC7400RX500PK 1 10 1 Part Marking Parts are marked as the example shown in Figure A MPC7400 Part Number Specifications PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc A MoTOROLA XPC7400 RX500PK MMMMMM ATWLYYWWA BGA Notes MMMMM NM is the 6 digit mask number ATWLYYWWA is the traceability code CCCCC is the country of assembly this space is left blank if parts are assembled in the United States Figure A Motorola Part Marking for BGA Device MPC7400 Part Number Specifications PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for2. Table 11 L2 Bus Interface AC Timing Specifications At Vdd AVdd L2AVdd 2 15V 50mV 0 lt Tj lt 65 C L2OVdd 3 3V 165mV or L2OVdd 2 5V 100mV or L2OVdd 1 8V 100mV 400 MHz 450 MHz 500 MHz Parameter Symbol Unit Notes Min Max Min Max Min Max L2SYNC_IN rise and fall time tlocr amp tlocr 1 0 E 1 0 1 0 ns 1 Setup Times ns 2 Data and parity tpytocH 1 5 1 3 1 0 Input Hold Times ns 2 Data and parity tDXL2CH 0 0 0 0 0 0 Valid Times tL2CHOV ns 3 4 All outputs when L2CR 14 15 00 2 5 2 4 2 3 All outputs when L2CR 14 15 01 3 0 3 All outputs when L2CR 14 15 10 3 5 9 All outputs when L2CR 14 15 11 4 0 2 Output Hold Times TL2CHOX ns 3 All outputs when L2CR 14 15 00 0 4 z 0 3 0 2 s All outputs when L2CR 14 15 01 1 0 7 z z All outputs when L2CR 14 15 10 1 4 All outputs when L2CR 14 15 11 1 8 5 L2SYNC_IN to high impedance tL2CHOZ ns All outputs when L2CR 14 15 00 2 0 2 0 2 0 All outputs when L2CR 14 15 01 2 5 2 5 2 5 All outputs when L2CR 14 15 10 3 0 3 0 3 0 All outputs when L2CR 14 15 11 z 3 5 3 5 3 5 Notes See General Hardware Specification 1 10 Ordering Information Table B provides the ordering information for the MPC7400 part described in this Part Number Specification Table B Ordering Information for the MPC7400 Microprocessor
3. 0 6 TS ABB DBB tkHTSv 3 0 Data tkHDV 3 5 7 Data Parity tkHDPV om 3 5 7 ARTRY SHDO SHD1 tkKHARV 2 3 a All Other Outputs tkHov 3 0 9 Output Hold Times ns 13 Address Transfer Attribute tkHAX 0 75 6 TS ABB DBB tkHTSx 0 75 Data Data Parity tkHDx 0 6 7 ARTRY SHDO SHD1 tk HARX 0 75 All Other Outputs tkHOX 0 75 9 4 MPC7400 Part Number Specifications PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 9 Processor Bus AC Timing Specifications Continued At Vdd AVdd 2 15V 50mV 0 lt Tj lt 65 C OVdd 3 3V 165mV or OVdd 2 5V 100mV or OVdd 1 8V 100mV 400 450 500 Mhz Parameter Symbol Unit Notes Min Max SYSCLK to Output Enable tkHOE 0 5 ns 14 SYSCLK to Output High Impedance all except tkHoz _ 3 5 ns 15 TS ABB AMON 0 ARTRY SHD DBB DMON 0 SYSCLK to TS ABB AMON 0 DBB DMON 0 tkHABPZ 1 0 toysa 4 15 High Impedance after precharge 16 17 Maximum Delay to ARTRY SHDO SHD1 tkHARP _ 1 tsyscik 4 17 Precharge SYSCLK to ARTRY SHDO SHD1 High tkHARPZ 2 t ysclk 4 17 Impedance After Precharge Notes 1 These values apply for all valid processor bus and L2 bus ratios The values do not include I O Supply Power OVdd and L2OVdd or PLL DLL supply power AVdd and L2AVdd OVdd and L2OVdd power is system dependent but is t
4. 400 350 450 350 500 MHz VCO frequency fvco 700 800 700 900 700 1000 MHz SYSCLK frequency fsyscLkK 33 100 33 100 33 100 MHz 1 SYSCLK cycle time tsysc_k 10 30 10 30 10 30 ns SYSCLK rise and fall time tke amp tke 1 0 1 0 1 0 ns 2 0 5 0 5 F 0 5 ns 3 SYSCLK duty cycle measured tkHkL tSYSCLK 40 60 40 60 40 60 4 at OVdd 2 SYSCLK jitter 150 150 150 ps 5 Internal PLL relock time 100 100 100 us 6 Notes See General hardware specification 1 4 2 2 Processor Bus AC Specifications Table 9 provides the processor bus AC timing specifications for the MPC7400 part described in this Part Number Specification Table 9 Processor Bus AC Timing Specifications At Vdd AVdd 2 15V 50mV 0 lt Tj lt 65 C OVdd 3 3V 165mV or OVdd 2 5V 100mV or OVdd 1 8V 100mV 400 450 500 Mhz Parameter Symbol Unit Notes Min Max Mode select input setup to HRESET MVRH 8 _ teysclk 2 3 4 5 HRESET to mode select input hold MXRH 0 _ ns 2 3 5 Setup Times ns 10 Address Transfer Attribute tAvkH 1 4 6 Transfer Start TS ttsvKH 1 4 _ Data Data Parity tpvKH 1 4 7 ARTRY SHDO SHD1 taRVKH 1 4 All Other Inputs tivKH 1 4 8 Input Hold Times ns 11 Address Transfer Attribute taxkH 0 _ 6 Transfer Start TS ttsxkH 0 Data Data Parity DXKH 0 7 ARTRY SHDO SHD1 taRXKH 0 a All Other Inputs tixkH 0 8 Valid Times ns 12 Address Transfer Attribute tkHav 3
5. Freescale Semiconductor Inc Y aft MPC7400_K PNS 000626 P SW CF amp Motorola Part Numbers Affected XPC7400RX400PK XPC7400RX450PK Application Specific Information pl rA00RXSO0PK MPC7400 Part Number Specification This document describes part number specific changes to recommended operating conditions and revised electrical specifications as applicable from those described in the general MPC7400 Hardware Specifications Specifications provided in this Part Number Specification supersede those in the MPC7400 Hardware Specifications dated 9 99 order MPC7400EC D for these part numbers only specifications not addressed herein are unchanged This document is frequently updated refer to the website at http www mot com SPS PowerPC for the latest version Note that headings and table numbers in this data sheet are not consecutively numbered They are intended to correspond to the heading or table affected in the general hardware specification Part numbers addressed in this document are listed in Table A For more detailed ordering information see Table B Table A Part Numbers Addressed by this Data Sheet Operating Conditions Motorola Part Number Significant Differences from Hardware Specification CPU Frequency Vdd Ty C XPC7400RX400PK 400 MHz 2 15V 50mV 0to65 Modified Voltage amp Temperature Specification to achieve 400Mhz frequency XPC7400RX450PK 450 MHz 2 15V 50mV 0to65 Modified Voltage am
6. any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and D are registered trademarks of Motorola Inc Motorola Inc is an Equa
7. l Opportunity Affirmative Action Employer IBM is a registered trademark of International Business Machines Corporation The PowerPC name and the PowerPC logotype are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation International Business Machines Corporation is an Equal Opportunity Affirmative Action Employer For More Information On This Product Go to www freescale com
8. n Impact Work Around 1 Incorrect value was When running ABIST after POR Running ABIST after Insert an ISYNC written to the MSR after the renames remained valid caus POR instruction at the running POR ABIST ing MSR to be updated with the interrupt vector incorrect value OxFFFO_0100 The PowerPC name and the PowerPC logotyp are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation This document contains information on a new product under development by Motorola Motorola reserves the right to change or discontinue this product without notice Motorola Inc 1999 All rights reserved For More Information On This Product AA Go to www freescale com Freescale Semiconductor Inc Problem Description Impact Work Around 2 Not all GPRs and FPRs are initialized after ABIST Not all GPRs and FPRs are ini tialized after ABIST due to invalid instructions in the instruc tion buffers GPRs and FPRs may not be initialized during ABIST if the contents of the instruction buffers can be decoded to non zero GPR or FPR desti nation addresses None 3 Asserting TEA and ARTRY together may cause loss of data Asserting TEA and ARTRY together in the first cycle of the snoop response window may cause loss of iside data Any system that permits the aggressive timing of TEA in the first cycle of the snoo
9. ns Proper device operation outside of these conditions is not guaranteed Table 7 provides the power consumption for the MPC7400 part at the frequencies described herein Table 7 Power Consumption for MPC7400 Processor Processor Processor CPU CPU CPU Frequency Frequency Frequency Unit Notes 400Mhz 450Mhz 500Mhz Full On Mode Typical 7 56 8 51 9 45 WwW 1 3 Maximum 15 1 17 0 18 9 W 1 2 4 Doze Mode Maximum 6 7 7 5 8 3 W 1 2 Nap Mode Maximum 2 7 3 0 3 3 WwW 1 2 Sleep Mode Maximum 2 7 3 0 3 3 WwW 1 2 Sleep Mode PLL and DLL Disabled Typical 600 600 600 mW 1 3 Maximum 1 0 1 0 1 0 Ww 1 2 Notes See General hardware specification 4 These values are with Altivec Without Altivec estimate a 25 decrease 1 4 2 1 Clock AC Specifications Table 8 provides the additional clock AC timing specifications described in this Part Number Specification Refer to the MPC7400 MPC7400 Part Number Specifications PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Specification for the remaining frequencies Table 8 Clock AC Timing Specifications At recommended operating conditions See Table 3 400 MHz 450 MHz 500MHz Characteristic Symbol SCS tt Notes Min Max Min Max Min Max Processor frequency feore 350
10. number of outstanding transac tions from a secondary bus to 5 in system logic or 2 Mark the memory space on the secondary bus as guarded and avoid DST ST T and LMW instructions 1 2 General This section summarizes changes to the features of the MPC7400 described in the MPC7400 Hardware Specifications None 1 4 1 DC Electrical Characteristics Table 3 provides the recommended operating conditions for the MPC7400 part numbers described herein Table 3 Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage Symbol Recommended Value Unit Vdd 2 15V 50mV AVdd 2 15V 50mV L2AVdd 2 15V 50mV MPC7400 Part Number Specifications PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 Recommended Operating Conditions Continued Characteristic Symbol Recommended Value Unit Processor bus supply voltage BVSEL 0 OVdd 1 8V 100mV Vv BVSEL HRESET OVdd 2 5V 100mV V BVSEL 1 OVdd 3 3V 165mV V L2 bus supply voltage L2VSEL 0 L2OVdd 1 8V 100mV v L2VSEL HRESET L20Vdd 2 5V 100mV v L2VSEL 1 L2OVdd 3 3V 165mV V Input voltage Processor bus Vin GND to OVdd V L2 Bus Vin GND to L2OVdd V JTAG Signals Vin GND to OVdd V Die junction temperature Tj 0 65 C Note These are the recommended and tested operating conditio
11. p Temperature Specification to achieve 450Mhz frequency XPC7400RX500PK 500 MHz 2 15V 50mV 0to65 Modified Voltage amp Temperature Specification to achieve 500Mhz frequency Note The X prefix in a Motorola PowerPC part number designates a Pilot Production Prototype as defined by Motorola SOP 3 13 These are from a limited production volume of prototypes manufactured tested and Q A inspected on a qualified technology to simulate normal production These parts have only preliminary reliability and characterization data Before pilot production prototypes may be shipped written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes Errata This section summarizes design defects or errors errata that are known to exist for these parts There may be additional errata that are not known or are not yet documented here which may cause the part to deviate from the functional description provided in the MPC7400 RISC Microprocessor User s Manual order MPC7400UM AD Rev 0 Refer to the website at http www mot com SPS PowerPC for the latest version of this Part Number Specification or to your local Motorola sales office for later and or more detailed description of the errata The known errata as of the date of this document are summarized below Problem Descriptio
12. p response win dow Delay assertion of TEA until the second cycle of the snoop response win dow or later 4 Incorrect condition code on mismatched LWARX STWCX pair A STWCX instruction may be performed without setting the condition code if the store hits in the L2 and the LWARX instruc tion that set the reservation is to another coherency granule Any code which uses mismatched LWARX STWCX address pairs 1 Avoid mismatched LWARX STWCX address pairs or 2 Turn off the L2 5 TLBSYNC may hang in the presence of a DST The MPC7400 may not make forward progress if a DST has caused an MMU tablewalk that MMU tablewalk was marked by a TLBIE instruction and a TLB SYNC instruction is pipelined the cycle after the MMU table walk accesses the dL1 cache Any system which has an active DST engine while executing a TLB SYNC instruction in a privileged context Insert a DSSALL instruction before a TLBSYNC instruction 6 Queueing six transac tions to secondary bus may hang the system Queueing six transactions from a single MAX processor could use all Data Transaction Queue resources and hang the system if forward progress cannot be made by allowing MAX to complete at least one outstanding transaction Any system which allows 6 outstanding transactions from a sin gle processor and which has a secondary bus with characteristics as detailed in full descrip tion 1 Limit the
13. ypically lt 10 of Vdd power Worst case power consumption for AVdd 15 mw and L2AVdd 15 mW 2 Maximum power is measured at Vdd 2 2V while running an entirely cache resident contrived sequence of instructions which keep the execution units including AltiVec maximally busy 3 Typical power is an average value measured at Vdd AVdd L2AVdd 2 15V OVdd L2OVdd 3 3V in a system while running a codec application that is AltiVec intensive 1 4 2 3 L2 Clock AC Specifications Table 10 provides the L2CLK Output AC Timing Specifications for the MPC7400 part described in this Part Number Specification Table 10 L2CLK Output AC Timing Specifications At recommended operating conditions See Table 3 400 MHz 450 MHz 500 MHz Parameter Notes L2CLK frequency fL2cLK 150 400 150 450 150 500 MHz 1 L2CLK cycle time tL2cLK 2 5 6 67 2 22 6 67 2 0 6 67 ns L2CLK duty cycle teHct tL2cLK 50 50 50 2 Internal DLL relock time 640 640 640 lt L2CLK 4 DLL capture window 200 200 200 ns 5 Notes See General hardware specification MPC7400 Part Number Specifications 5 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 4 2 4 L2 Bus AC Specifications Table 11 provides the L2 Bus Interface AC Timing Specifications for the frequencies described in this Part Number Specification
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