Home

Datasheet - Mouser Electronics

Contents

1. Doc ID 16259 Rev 3 4mA ky SPEAr600 Pin description 2 Table 8 GPIO pins Group Signal name Ball Direction Function Pin type GPIO 0 W18 GPIO 1 V18 GPIO 2 U18 GPIO 3 118 TTL bidirectional GPIO ee ud O aenea ae d GPIO_5 V19 purpose 3 3 V tolerant GPIO_6 919 Pu GPIO_7 T19 GPIO 8 R19 GPIO 9 R18 1 When the pin is not driven the output voltage is 2 5 V On the core side logic 1 state is guaranteed Table 9 ADC pins Group Signal name Ball Direction Function Pin Type AIN 0 W11 AIN_1 V11 AIN_2 V12 W12 ADC analog AIN 4 W13 input channel Analog buffer iui i 2 5 V tolerant AIN_6 V14 AIN 7 W14 ADC_VREFN W15 ADC negative _ voltage ADC_VREP V15 ADC positive _ voltage Doc ID 16259 Rev 3 31 97 Pin description SPEAr600 32 97 Table 10 NAND Flash I F pins Group Signal name Ball Direction Function Pin Type NF IO 0 H19 NF IO 1 H18 NF IO 2 G19 TTL bidirectional NF IO G18 Te Data 3 3 na NF_IO_4 F19 mA 3 3 V tolerant NF_IO_5 F18 NF IO 6 E18 NAND NF IO 7 E19 FLASH _ G20 Chip enable TTL output buffer NF_RE G22 Read enable 3 3 V capable NF_WE H20 Write enable active low H21 Output Address latch enable TTL o
2. 69 Table 41 5 69 Table 42 SOC slave 69 Table 43 timings with 1 71 Table 44 timings with 72 Table 45 Timing characteristics for in high speed 74 Table 46 Timing characteristics for in fast speed mode 74 Table 47 Timing characteristics for 2 in standard speed mode 74 Table 48 Timing characteristics for 8 bit NAND Flash 77 ky Doc ID 16259 Rev 3 5 97 List of tables SPEAr600 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 6 97 Timing characteristics for 16 bit NAND Flash 79 TX timing 20 1 80 TX MMOS iuo 20500000 Ree m demie Pee Lee CR C RE 81 GMII MII RX 05 1 82 MDC MDIO
3. 58 5 8 Power on reset 5 58 5 9 ADC electrical parameters 59 6 Timing characteristics 60 6 1 DDR2 timing characteristics 60 6 1 1 DDR2 read cycle timings 60 6 1 2 DDR2 write cycle 61 6 1 3 DDR2 command timings 63 6 2 EXPI timing characteristics 65 6 2 1 Pad delay 66 6 2 2 Pad delay enabled 68 6 3 CLOD timing characteristics 71 6 3 1 timing characteristics direct clock 71 Doc ID 16259 Rev 3 3 97 Contents SPEAr600 6 3 2 timing characteristics divided clock 72 6 4 l2C timing characteristics 73 6 5 FSMC timing 76 6 5 1 8 bit NAND Flash configuration 76 6 5 2 16 bit Flash configuration 78 6 6 Ether MAC 10 100 1000 Mbps GMAC Univ timing characteristics 80 6 6 1 GMII Transmit timing specifications
4. 83 SMI timings in default configuration 84 SMI Timings of SMI_CS_3 in non default 5 85 Timing requirements for SSP all 86 Timing requirements for SPI mode on MISO 0 87 Timing requirements for SPI mode on MOSI 01 87 Timing requirements for SPI mode on MISO 1 88 Timing requirements for SPI mode on MOSI 11 89 PBGA420 23 x 23 x 2 06 mm mechanical data 91 SPEAr600 PBGA420 thermal resistance 93 Document revision history 94 Doc ID 16259 Rev 3 ky SPEAr600 List of figures List of figures Figure 1 Functional block 8 Figure 2 Typical system architecture using 0 11 Figure 3 Power on reset timing 1 58 Figure 4 DDR2 read cycle waveforms 60 Figure 5 DDR2 read cycle 60 Figure 6 DDR2 write cycle wavef
5. 75 Figure 23 Output pads for 8 bit Flash configuration 76 Figure 24 Input pads for 8 bit NAND Flash configuration 76 Figure 25 Output command signal waveforms for 8 bit NAND Flash configuration 76 Figure 26 Output address signal waveforms for 8 bit NAND Flash configuration 77 Figure 27 In out data address signal waveforms for 8 bit NAND Flash configuration 77 Figure 28 Output pads for 16 bit NAND Flash configuration 78 Figure 29 Input pads for 16 bit NAND Flash 78 Figure 30 Output command signal waveforms 16 bit NAND Flash configuration 78 Figure 31 Output address signal waveforms 16 bit NAND Flash configuration 79 Figure 32 In out data signal waveforms for 16 bit NAND Flash configuration 79 Figure 33 TX waveforms 80 Figure 34 Block diagram of TX 5 80 Figure 35 MII TX 1 0 81 Figure 36 Block diagram of MII 4 81 Figure 37 GMII MIl RX 5 82
6. 23 2 97 Doc ID 16259 Rev 3 SPEAr600 Contents 3 PIN description susurro eR Rh 24 3 1 Required external components 24 3 2 Pin descriptions listed by functional block 24 3 3 Configuration modes 41 3 3 1 Fullfeat res e a a OLA eo DR 41 3 3 2 Disable NAND Flash 41 3 3 3 Disable LOD Cth 25549552 kx ee daa 41 3 3 4 Disable GMAC ctr 42 3 3 5 adeeb ang hoe dee PER oe d 42 3 3 6 Self suisse rot heeded EGA E Rand e ede 42 3 3 7 All processors disabled 42 4 Memory eeaeee aa aa aa RR OR Un c RR 53 5 Electrical characteristics 55 5 1 Absolute maximum 05 55 5 2 Maximum power consumption 55 5 8 DC electrical characteristics 56 5 4 Overshoot and 56 5 5 3 3V I O characteristics 57 5 6 DDR2 pin characteristics 57 5 7 Power up sequence
7. 80 6 6 2 transmit timing specifications 81 6 6 3 GMII MII Receive timing specifications 82 6 6 4 timing specifications 83 6 7 SMI timing characteristics 84 6 7 1 SMI timing specifications 84 6 8 SSP timing characteristics 86 6 8 1 SPI master mode timings 0 87 6 8 2 SPI master mode timings 1 88 7 Package information 90 7 1 Package mechanical data 91 8 Revision history 94 4 97 Doc ID 16259 Rev 3 Ti SPEAr600 List of tables List of tables Table 1 Device SUMMAN us 1 Table 2 System reset master clock RTC and configuration 24 Table 3 Power supply 25 Table 4 Debug PINS RE 27 Table 5 SMI SSP UART FIRDA and 2 pins 27 Table 6 USB PINS T rcc 29 Table 7 Ethernet plns ened nee Me EEE Y ees E YER ore 30 Table 8 GPIO PINS 31 9
8. 57 Table 25 and pull down 5 5 57 Table 26 DC 5 57 Table 27 Driver characteristics 57 Table 28 die termination 58 Table 29 Reference 4 58 Table 30 characteristics 59 Table 31 DDR2 read cycle path timings without pad 60 Table 32 DDR2 read cycle timings without pad 60 Table 33 DDR2 write cycle path timings without pad 62 Table 34 DDR2 write cycle timings without pad 62 Table 35 DDR2 command timings without pad 64 Table 36 EXPI pad signal 65 Table 37 EXPI clock and reset 5 67 Table38 5 67 Table39 SOC slave 67 Table 40 Clock
9. tax Doc ID 16259 Rev 3 SPEAr600 Note To calculate the value for the PHY you have to consider the next rising edge so you have to apply the following formula tsgrup tmax 6 6 2 MII transmit timing specifications Figure 35 TX waveforms TX CLK _ Tclock Tmax gt TXDO TXD3 Tf Tr Figure 36 Block diagram of MII TX pins TX 0 3 TXDJ O 3 TX CLK Table 51 TX timings Value using 100 Mb Value using MII 10 Mb tc Parameter period 40 ns 25 MHz period 400 ns 2 5 MHz tmax t8min 6 8 ns 6 8 ns tmin t2min 2 9 ns 2 9 ns SETUP 33 2 ns 393 2 ns Note To calculate the value for the PHY you have to consider the next rising edge so 81 97 Timing characteristics SPEAr600 6 6 3 Note 82 97 GMII MII Receive timing specifications Figure 37 GMII MII RX waveforms RX CLK AMAA RXDO RXD3 GMIIRX_D4 GMIIRX_D7 RX_ER RX_DV 15 gt gt lt ih Tf Tr Figure 38 Block diagram of GMII MII RX pins E RX_CLK RX 0 3 GMII_RX 4 7 RX_ER RX_DV Sar Table 52 Parameter tsETUPmax ts t2max ti min t HoLDmin tH t2min ti max GMII MII RX timings Value using GMII period 8 ns 125 MHz 2 26 ns 0 11 ns Value using
10. B fff Table 62 Symbol SPEAr600 PBGA420 thermal resistance characteristics Parameter Value Unit Thermal resistance junction to ambient 1 26 7 Thermal resistance junction to board 18 2 C W Thermal resistance junction to case 9 9 Junction to case thermal characterisation parameter 0 38 1 Measured on JESD51 2s2p test board 2 Doc ID 16259 Rev 3 93 97 Revision history SPEAr600 8 94 97 Revision history Table 63 Document revision history Date 22 Sep 2009 Revision 1 Initial release Changes Doc ID 16259 Rev 3 SPEAr600 Revision history Table 63 Document revision history continued Date 8 Feb 2010 Revision Changes Added I2S to Table 18 Memory map Modified pin list of 125 and EXPI Table 14 EXPI I2S pins and Table 15 pins Updated sections Features Main features 125 audio block improving the description of 125 feature Updated Table 19 Absolute maximum ratings Updated section DDR2 timing characteristics Updated Table 27 Driver characteristics Updated Section 5 1 Absolute maximum ratings Updated Table 21 Recommended operating conditions Updated Section 2 15 UARTs Updated introduction of Chapter 7 Package information Updated Table 10 NAND Flash I F pins Updated Table 3 Power supply pins Update
11. det Yaa ee ede es 31 Table 10 NAND Flash I F 5 32 Table 11 25 em ne 33 Table 12 1 2 2 35 13 LVDS I F pins srai ee Perio bes Me RR epu guo uer rua 36 Table 14 25 1 1 37 Table 15 ee cee ade a x 38 Table 16 Multiplexing 43 Table 17 Table 0 2 52 Table 18 Memory 53 Table 19 Absolute maximum 08 0 5 55 Table 20 Maximum current and power 55 Table 21 Recommended operating conditions 56 Table 22 Overshoot and undershoot 5 56 Table 23 Low voltage TTL DC input specification V lt Vpp 3 6 57 Table 24 Low voltage TTL DC output specification V lt Vpp 3 6
12. Doc ID 16259 Rev 91 97 Package information SPEAr600 Figure 46 PBGA420 23 x 23 x 2 06 mm package top view CORNER 6 8 10 12 14 16 18 20 22 7 9 44 15 15 17 19 21 jExAX z camuzzr xcrommoogu 92 97 Doc ID 16259 Rev 3 ky SPEAr600 Package information Figure 47 PBGA420 23 x 23 x 2 06 mm package bottom view SEATING PLANE ddd C M A2 D1 e F NEN 00000000000000000000044 4 90 000 O O tS 5 7 9 TRANS 15 17 19 21 2 4 6 8 10 124 14 16 18 20 22 gt A1 BALL PAD CORNER b 384436 BALLS
13. SPEAr600 Embedded MPU with dual ARM926 core flexible memory support powerful connectivity features and programmable LCD interface Features Dual ARM926EJ S core up to 333 MHz Each with 16 Kbytes instruction cache 16 Kbytes data cache Datasheet production data m High performance 8 channel DMA m Dynamic power saving features m Upto 733 DMIPS m Memory 420 23 x 23 x 2 06 mm External DRAM interface 8 16 bit DDR1 333 DDR2 666 m 3 125 interfaces for audio features 32 Kbytes BootROM 8 Kbytes internal One stereo input and two stereo outputs SRAM audio 3 1 configuration capable Flexible static memory controller FSMC m Customizable logic with 600 Kgate standard supporting parallel NAND Flash memory cell array interface ONFI 1 0 support internal 1 bit ECC or external 4 bit ECC m Software Serial NOR Flash Memory interface System compliant with all operating systems including Linux m Connectivity 2x USB 2 0 Host USB 2 0 Device Applications Giga Ethernet GMII port m The SPEAr embedded MPU family targets and fast IrDA interfaces networked devices used for communication SSP Synchronous serial peripheral display and control This includes diverse SPI Microwire or TI protocol ports consumer business industrial and life science 2x UART interfaces applications such as Peripherals su
14. Table 34 DDR2 write cycle timings without pad delay Period T Frequency 4 ton 3ns 333 MHz 396 ps 492 ps 3 75 ns 266 MHz 585 ps 681 ps 5ns 200 MHz 895 ps 991 ps 6 ns 166 MHz 1 15 ns 1 25 ns 7 5 ns 133 MHz 1 52 ns 1 62 ns Table 34 shows the internal chip timing without the contribution of the pads These values are obtained considering the nominal setting of DLL at T period for DQS path and T 3 4 for DQ path in fact the memory controller launches data DQ and data strobe DQS misaligned Internally the clock is delayed by T to produce the DQS and the same clock is delayed by T 3 4 to clock the data DQ in order to perform a correct write to the memory The table values are measured in a particular pad configuration Drive strength strong zprog_out L Slope prog_a L prog b corresponding to 266 MHz The waveforms in Figure 6 refer to the pad or memory side so the DQS edges are centered on the data valid window In this case we consider the minimum values for t4 and t5 in order to obtain the minimum data valid window For a correct data write on the memory side the last variation of the data must precede the first arrival of the data strobe In other words we can consider as the of the data that can be defined as the time range where the Doc ID 16259 Rev 3 ky SPEAr600 Timing characteristics Note data are stable before the arrival of the DQS
15. Timing characteristics SPEAr600 Note 1 2 3 6 3 2 72 97 Tstable Tclock direct max Tmax Tmin For Tmax the maximum value is taken from the worst case and best case while for Tmin the minimum value is taken from the worst case and best case should be delayed by Tmax Tclock direct max Tmax 2 4 7915 ns CLCD timing characteristics divided clock Figure 17 CLCD waveform with CLCP divided CLCP Tclock 4 Tmax us min CLD 23 0 CLAC CLLE CLLP CLFP CLPOWER Tstable Tf Figure 18 CLCD block diagram with divided ca CLD 23 0 CLAC CLLE CLCDCLK CLLP CLFP CLPOWER t2 CLR Q CLCP D SET Q Table 44 CLCD timings with divided Parameter Value Frequency Tclock divided max 12 ns 83 3 MHz Tclock divided max rise Tr 0 81 ns Tclock divided max Tf 0 87 ns Tmin 0 49 ns Tmax 2 38 ns Tstable 9 13 ns Doc ID 16259 Rev 3 SPEAr600 Timing characteristics Note 1 Tstable Tclock direct max Tmax Tmin 2 For Tmax the maximum value is taken from the worst case for Tmin the minimum value is taken from the best case 3 CLCP should be delayed by Tmax Tclock direct max Tmax
16. 3 AIN 3 W13 AIN 4 AIN 4 4 4 V13 AIN 5 AIN 5 5 AIN 5 V14 AIN_6 AIN_6 AIN_6 AIN_6 W14 AIN_7 AIN_7 AIN_7 AIN_7 W15 ADC_VREFN ADC_VREFN ADC_VREFN ADC_VREFN V15 ADC_VREFP ADC_VREFP ADC_VREFP ADC_VREFP W18 EXPI 0 EXPI 0 EXPI 0 EXPI 0 V18 EXPI 1 EXPI 1 EXPI 1 EXPI 1 U18 EXPI 2 EXPI 2 EXPI 2 EXPI 2 T18 EXPI 3 EXPI 3 EXPI 3 EXPI 3 W19 EXPI 4 EXPI 4 EXPI 4 EXPI 4 V19 EXPI 5 EXPI 5 EXPI 5 EXPI 5 U19 EXPI 6 EXPI 6 EXPI 6 EXPI 6 T19 EXPI 7 EXPI 7 EXPI 7 EXPI 7 R19 EXPI 8 EXPI 8 EXPI 8 EXPI 8 R18 EXPI 9 EXPI 9 EXPI 9 EXPI 9 AB18 FIRDA RXD FIRDA RXD FIRDA RXD FIRDA RXD AA18 FIRDA TXD FIRDA TXD FIRDA TXD FIRDA TXD AB19 UART1 RXD UART1 RXD 1 RXD UART1 RXD AA19 UART1_TXD UART1_TXD UART1_TXD UART1_TXD AB20 UART2_RXD UART2_RXD UART2_RXD UART2_RXD AA20 UART2_TXD UART2_TXD UART2_TXD UART2_TXD Y18 SDA SDA SDA SDA 19 SCL SCL SCL SCL 009445 uonduosep 26 77 6429 12001 Table 16 Multiplexing scheme continued Ball Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Full RAS Mode 7 AB22 SSP_1_SCLK SSP_1_SCLK SSP_1_SCLK SSP_1_SCLK 21 SSP 1 MISO SSP 1 MISO SSP 1 MISO SSP 1 MISO 21 SSP 1 MOSI SSP 1 MOSI SSP 1 MOSI SSP 1 MOSI AA22 SSP 1 SS SSP 1 SS SSP 1 SS SSP 1 SS Y20 CLD 0 GPIO basic 7 CLD 0 CLD 0 CLD 0 Y21 CLD 1 GPIO basic 6 CLD 1 CLD 1 CLD 1 Y22 CLD 2 GPIO basic 5
17. Group DDR Signal name Ball Direction Function Pin type DDR_DATA_5 Y12 Data lines SSTL_2 DDR DATA AB12 6 Lower byte SSTTL_18 DDR_DATA_7 AA12 DDR_DQS_0 AB13 Differential Differential lower Data Strobe SSTL_2 DDR_nDQS_0 AA13 ata SSTTL_1 8 DDR DM 0 AA11 Output mask DDR GATE 0 Y13 Lower gate open DDR_DATA_8 AB15 DDR_DATA_9 AA16 DDR_DATA_10 16 SSTL_2 SSTTL_18 DDR_DATA_1 1 Y16 VO Data lines DDR DATA 12 Y15 Upper byte DDR DATA 13 Y14 DDR DATA 14 AB14 DDR DATA 15 AA14 DDR DOS 1 AB17 Diferential Differential upper SSTL_2 DDR_nDQS_1 AA17 Data strobe SSTTL 18 DDR DM 1 AA15 Output Upper data mask SSTL_2 SSTTL_18 DDR_GATE_1 17 Upper gate open DDR_VREF V10 Input Ref voltage Analog Analog see DDR_COMP_2V5 V9 Ref Ext ref resistor Note 2 on page 24 DDR COMP GN v8 Common return Power D for Ext resistors Analog see DDR_COMP_1V8 V7 Ref Ext ref resistor Note 1 24 input buffer DDR2_EN D11 Input Configuration 3 3 V tolerant PU 34 97 Doc ID 16259 Rev 3 SPEAr600 Pin description Table 12 LCD I F pins Group Signal name Ball Direction Function Pin Type CLD 0 Y20 CLD_1 Y21 CLD_2 Y22 CLD_3 W22 CLD 4 W21 CLD_5 W20 CLD
18. 009445 SPEAr600 Memory map 4 Memory map Table 18 Memory map Start address End address Peripheral Description 0x0000 0000 Ox3FFF FFFF External DRAM DDR1 or DDR2 0x4000 0000 0x4000 07FF R F U Reserved 0x4000 0800 0x4000 0820 125 125 dual port memory 0 4000 0821 OxBFF FFFF R F U Reserved 00 0000 7 2 expansion interface OxCFFF F800 OxCFFF FFFF AHB_EH2H registers 0xD000 0000 0xD007 FFFF UART 1 0xD008 0000 OxDOOF FFFF UART 2 0xD010 0000 0xD017 FFFF SSP 1 0xD018 0000 0xD01F FFFF SSP 2 0xD020 0000 0xD027 FFFF 2 0xD028 0000 OxDO7F FFFF Reserved 0xD080 0000 OxDOFF FFFF JPEG Codec 0xD100 0000 OxD17F FFFF Fast IrDA 0 0180 0000 0xD1FF FFFF FSMC NAND Flash controller 0xD200 0000 OxD27F FFFF FSMC NAND Flash memory 0 0280 0000 OxD2FEFFFF SRAM Static a memory 0xD300 0000 OxD7FFE FFFF Reserved 0xD800 0000 0xD807 FFFF Timer 1 0xD808 0000 OxD80F FFFF Timer 2 0xD810 0000 0xD817 FFFF GPIO 0xD818 0000 OxD81F FFFF SSP3 0xD820 0000 0xD827 FFFF ADC 0xD828 0000 OxDFFF FFFF Reserved 0 000 0000 OxE07F FFFF Reserved 0 080 0000 OxEOFF FFFF Ethernet controller GMAC 100 0000 OxE10F FFFF USB 2 0 device FIFO OxE110 0000 OxE11F FFFF USB 2 0 device Configuration registers 0 120 0000 OxE12F FFFF USB 2 0 device Plug detect 0xE130 0000 OxE17F FFFF Reserved OxE180 0000 USB2 0 1
19. 15 2 6 LCD controller 15 27 PIOS borin naana Daaa RR Rd 15 26 JPEGCOdE o si oana ee eee Rees 16 2 9 8 channel ADC 16 2 10 Ethernet controller 16 2 11 USB2 host controller 17 212 USB2 device 17 2 13 Synchronous Serial Peripheral SSP 18 esei a nd RS E 18 25 18 2 16 Fast IrDA 19 217 audio block ax vea dO ERN ES M ENSE 19 2 18 System controller 19 2 18 1 Power saving system mode control 20 2 19 Clock and reset system 20 2 20 Vectored interrupt controller VIC 21 221 General purpose timers 21 2 22 Watchdog timer 22 228 RITU OSCIIBIOE tee Hee Rete ee deas 22 2 24 Reconfigurable array subsystem connectivity RAS 22 2 25 External Port Controller EXPI I F
20. 16 bpp true color non palletized for color STN and TFT 24 bpp true color non palletized for color TFT Supports single and dual panel mono super twisted nematic STN displays with 4 or 8 bit interfaces Supports single and dual panel color and monochrome STN displays Supports thin film transistor TFT color displays 15 gray level mono 3375 color STN and 32 K color TFT support 1 2 or 4 bits per pixel bpp palletized displays for mono STN 1 2 4 or 8 bpp palletized color displays for color STN and TFT Programmable timing for different display panels 256 entry 16 bit palette RAM arranged as a 128 x 32 bit RAM physically frame line and pixel clock signals AC bias signal for STN and data enable signal for TFT panels patented gray scale algorithm e Supports little endian big endian and WinCE data formats GPIOs The General Purpose Input Outputs GPIOs provide programmable inputs or outputs Each input output can be controlled in two distinct modes e Software mode through an APB interface e Hardware mode through a hardware control interface SPEAr600 provides up to 10 GPIO lines e Individually programmable input output pins default to input at reset e An slave acting as control interface in software mode e Programmable interrupt generation capability on any number of pins e Bit masking in both read and write operations through address lines Doc ID 16259 Rev 15 97 Architecture overview SPEAr60
21. 5 333 2 977 ps 1 33 ns 3 75 ns 266 MHz 1 35 ns 1 71 ns 5 ns 200 MHz 1 98 ns 2 33 ns ns 166 MHz 2 49 ns 2 84 ns 7 5 ns 133 MHz 3 23 ns 3 59 ns Table 35 shows the internal chip timing without the contribution of the pads Doc ID 16259 Rev 3 ky SPEAr600 Timing characteristics 6 2 EXPI timing characteristics The characterization timing is done for an output load of 10 pF on PL_CLKx and 5 pF on PL_GPIO_x The operating conditions are in worst case V 0 90 V TA 125 C and in best case V 1 10 V TA 40 C The timings are measured using TEST 5 0 101xxx Selg_cfg5 EXPI with internal clock Please refer to the user manual for the description of the SoC_cfg bits in the MISC registers Figure 10 AHB EXPI transfer waveforms HCLK HADDR 31 0 Control HWDATA 31 0 HREADY HRDATA 31 0 Address phase Data phase Table 36 EXPI pad signal assignment EXPI signal Direction PL GPIOs signal assignment HAdd 19 00 Bidir PL GPIO 19 00 HAdd 21 20 Bidir PL_GPIO 56 55 HAdd 23 22 Bidir PL GPIO 82 81 HRWData 07 00 Bidir PL GPIO 27 20 HRWData 15 08 Bidir PL GPIO 64 57 HRWData 31 16 Bidir PL GPIO 80 65 HSize 2 0 Bidir PL GPIO 30 28 HWrite Bidir PL GPIO 31 HBurst 2 0 Bidir PL GPIO 34 32 HTrans 1 0 Bidir PL GPIO 36 35 Doc ID 16259 Rev 65 97 Timing characteristics SPEAr600 Not
22. DLL Table 31 DDR2 read cycle path timings without pad delay t3max t1 t1 Rising best 133 ps 212 ps 125 ps 244 ps Falling best 134 ps 205 ps 127 ps 239 ps Rising worst 336 ps 611 ps 311 ps 646 ps Falling worst 348 ps 550 ps 324 ps 590 ps Table 32 DDR2 read cycle timings without pad delay Period T Frequency t5uAx 3ns 333 MHz 814 ps 343 ps 3 75 ns 266 MHz 996 ps 532 ps 60 97 Doc ID 16259 Rev SPEAr600 Timing characteristics Note Table 32 DDR2 read cycle timings without pad delay continued Period T 5 ns Frequency 200 MHz t4max 1 31 ns t5max 842 ps ns 166 MHz 1 56 ns 1 10 ns 7 5 ns 133 MHz 1 93 ns 1 47 ns Table 32 shows the internal chip timing without the contribution of the pads These values are obtained considering the nominal setting of DLL at T 4 period in fact the DDR memory launches data DQ and data strobe DQS aligned Internally the DQS is delayed by T 4 DLL to guarantee correct data capture The waveforms in Figure 4 refers to the pad or memory side so the data move around the edges of DQS signals In this case we consider the maximum values for t4 and t5 to obtain the minimum data valid window For correct data capture at the controller side the last arrival time of the data last variation must precede the first arrival of the data strobe t4MAX DQS delay yin
23. Figure 38 Block diagram of GMII MII RX pins 82 Figure 39 MDC waveforms 83 Figure 40 Paths from MDC MDIO pads 83 Figure 41 SMI 40 84 Figure 42 Block diagram of the SMI pins 84 Figure 43 SSP 0 2 86 Figure 44 SPI master mode external timing 0 88 Figure 45 SPI master mode external timing 1 89 Figure 46 PBGA420 23 x 23 x 2 06 mm package top view 92 Figure 47 PBGA420 23 x 23 x 2 06 mm package bottom view 93 ky Doc ID 16259 Rev 3 7 97 Description SPEAr600 1 Description The SPEAr600 is a member of the SPEAr family of embedded MPUs for networked devices itis based on dual ARM926EJ S processors up to 333 MHz widely used in applications where high computation performance is required Both processors have an MMU supporting virtual memory management and making the system compliant with the Linux operating system They also offer 16 KBytes of data cache 16 KBytes of instruction cache JTAG and ETM embedded trace macro cell for debug operatio
24. PL CLK1 x Tdock gt Input PL m 4 Output tmin Table 37 clock and reset parameters Parameter Value ns Frequency MHz CLK period 15 66 6 Tf CLK fall 0 81 Tr CLK rise 0 81 Output Signals tmin ns tmax Ns Reset 0 84 6 Table 38 5 Output Signals tmin ns tmax Ns HADDR 1 11 5 93 HSIZE HWRITE HBURST HTRANS HMASTLOCK HSEL 0 92 4 71 HReady_in 45 HWDATA 1 00 7 3 Input tsetup ns 5 HReady_out 44 HRESP 7 2 09 HRDATA 6 32 1 94 Table 39 SOC slave Input Signals tserup ns tuotp ns HADDR 7 77 1 94 Doc ID 16259 Rev 3 67 97 Timing characteristics SPEAr600 Table 39 SOC slave continued Input HSIZE HWRITE HBURST 7 02 1 94 HTRANS HLOCK HBUSREQ HWDATA 6 17 1 94 Output tmin ns tmax Ns HGRANT HReady_mst 43 HRESP 0 66 4 21 HRDATA 1 09 7 34 Input path SETUP_FF tin max tck_PAD max FF tHorp tin min tck_PAD min FF Output Path tmax tout tmin tout tck_Fr min pAp max Note For tsetup tuo p tmax are taken the maximum value from worst case and best case while the minimum value is taken for tmin 6 2 2 Pad delay enabled Figure 13 pad delay enabled block diagra
25. To have a positive quantity the delay obtained by the DQ maximum delay or last variation must be less than one obtained by the DQS minimum delay So DQS delay yin DQ delay max t1 MIN T DLL element T T 3 4 one DLL element tl yin 12 one DLL element t3 t5 can be expressed in a similar way and be defined as the of the data DQ delay win DOS delay yax T 2 T 3 4 one DLL element 13 1 t1 ax T one DLL element t2max T 4 t2MAX t1 one DLL element DQS delay is the combination of delays experienced by the DQS data strobe signal DQ delay is the combination of delays experienced by the DQ data signal both until the capture performed by the controller DDR2 command timings Figure 8 DDR2 command waveforms MA ADDRESS STROBEs lt gt lt gt and CONTROL LINES t4 t5 Figure 9 DDR2 command path ADDRESS STROBEs and CONTROL LINES ADDRESS STROBEs and CONTROL LINES p ENG CLR Q 8 CLK For the command and control timings we have to consider that the commands are launched on the negative edge of the clock and are captured on the next positive edge of the clock a The value DLL element stands for the DLL accu
26. VSSBS 02 USB_PLL_VSSP W3 USB_PLL_VSSP2V5 2 GND MCLK_GNDSUB AA3 DITH_VSS2V5 V5 VDDESVS3 J6 H6 c Me e 3 3V cone voo IT INT USB_HOST_VDD3V3 R3 3 3V HOST USB USB HOST2 VDDBC N1 2 5 PHY USB_HOST2_VDDBS N3 1 0V Doc ID 16259 Rev 25 97 Pin description SPEAr600 Table 3 Power supply pins continued Group Signal name Ball Value HOST1 USB USB 5 1 VDDBC P3 2 5V PHY USB_HOST1_VDDBS R2 1 0 V USB DEV VDDBC U1 251 ua USB_DEV_VDDBS U3 1 0V USB DEV VDD3V3 T3 3 3 V m USB PLL VDDP 1 0V USB_PLL_VDDP2V5 w1 2 5 V OSCI MASTER MCLK_VDD AA1 1 0 V CLOCK MCLK_VDD2V5 AA2 25V DITH_VDD2V5 V4 251 PLL1 DITH_VDD U6 1 0V DDR 1 0 SSTL_VDDE1V8 U7 U8 U9 U11 U12 U14 015 1 8 2 5 V ADC ADC_AVDD W16 2 5 V DDR MEM PLL VDD ANA W17 251 DDR_MEM_PLL_VDD_DIG Tiz 1 0V LVDS I O LVDS_VDDE2V5 11 F12 F14 25V OSCI RTC RTC VDDE 1V8 B10 1 8V 1 For DDRI the supply voltage must be 2 5 V instead for DDRII the supply voltage must be 1 8 V 26 97 Doc ID 16259 Rev 3 SPEAr600 Pin description Table 4 Debug pins Group Signal name Ball Direction Function Pin type BOOT SEL K18 Input Boot selection TEST 0 E15 TEST 1 E14 TEST 2 D14 iourati TTL input Input Configuration buff
27. VppE 5 7 Power sequence No particular sequence is required It is only required that the various power supplies reach the correct range in less than 10 msec 5 8 Power on reset MRESET The MRESET must remain active for at least 10 ms after all the power supplies are in the correct range and should become active in no more than 10 us when one of the power supplies goes out of the correct range Figure 3 Power on reset timing diagram All Vdd are stable od 2 MRESET OSCI 30MHz L resets_o E PTS 60 clock TR E cycles sclk i hresetn arm_fetching XX T clock cycles at 30MHz lock i ime note 2 k E toms DOZE MODE NORMAL 2 95 us i MODE 1 58 97 Doc ID 16259 Rev 3 ky SPEAr600 Electrical characteristics Note 1 2 The Pil lock time is given by the following formula The oscillator generates a stable clock 1 5 ms after the power supply becomes stable Lock time 4 ms decimal equivalent of PLL charge pump bit setting 1 The PLL charge pump CP bits are in the PLL1 2_CTR register in the Miscellaneous register block Please refer to the user manual for more details For example if the application software sets CP
28. an error may occur Workaround If a device needs more SDA data hold time than one clock cycle an RC delay circuit is needed on the SDA line as illustrated in Figure 22 Figure 22 RC delay circuit SDA from SPEArpad SDA to Device For example R K and C 200 pF Doc ID 16259 Rev 3 75 97 Timing characteristics SPEAr600 6 5 FSMC timing characteristics The characterization timing is done using primetime considering an output load of 3 pF on the data 15 pF on NF_CE NF_RE and NF_WE and 10 pF on NF_ALE and NF_CLE The operating conditions are V 0 90 V T 125 C in worst case and V 1 10 V T 40 C in best case 6 5 1 8 bit NAND Flash configuration Figure 23 Output pads for 8 bit NAND Flash configuration D a NFCLE NFCE HCLK on NFWE NFRE NFRWPRT D a NFALE NFIO 0 7 Figure 24 Input pads for 8 bit NAND Flash configuration NFRB HCLK D CLR Q NFIO 0 7 CLR Q Figure 25 Output command signal waveforms for 8 bit NAND Flash configuration NE Tag NFCLE E Twe NFWE Command X 76 97 Doc ID 16259 Rev 3 ky SPEAr600 Timing characteristics Figure 26 Output address signal waveforms for 8 bit Flash configuration
29. 4 Doc ID 16259 Rev 3 53 97 SPEAr600 Table 18 Memory map continued Start address End address Peripheral Description 190 0000 OxE19F FFFF USB2 0 OHCI 1 OxE1A0 0000 OxE1FF FFFF Reserved OxE200 0000 OxE20F FFFF USB2 0 EHCI 2 OxE210 0000 OxE21F FFFF USB2 0 OHCI 1 0 220 0000 OxE27F FFFF Reserved OxE280 0000 OxE28F FFFF Layer Configuration register 0xE290 0000 OxE7FF FFFF Reserved 0 800 0000 OxEFFF FFFF Reserved OxF000 0000 OxFOOF FFFF Timer OxF010 0000 GPIO OxF020 0000 OxFOFF FFFF Reserved OxF 100 0000 OxF10F FFFF ITC Secondary OxF 110 0000 OxF11F FFFF ITC Primary OxF 120 0000 OxF7FF FFFF Reserved OxF800 0000 OxFBFF FFFF Serial Flash Memory 0 00 0000 OxFC1F FFFF Serial Flash Controller 0 20 0000 LCD Controller 0 40 0000 OxFC5F FFFF DMA Controller OxFC60 0000 OxFC7F FFFF SDRAM Controller OxFC80 0000 OxFC87 FFFF Timer 1 OxFC88 0000 OxFC8F FFFF Watchdog Timer OxFC90 0000 OxFC97 FFFF Real time Clock OxFC98 0000 OxFC9F FFFF General Purpose OxFCAO0 0000 OxFCA7 FFFF System Controller 8 0000 OxFCAF FFFF Miscellaneous Registers 0000 OxFEFF FFFF Reserved 0 00 0000 OxFFFF FFFF Internal ROM Boot Doc ID 16259 Rev 3 SPEAr600 Electrical
30. DQ delay max ti MIN t2MIN T 4 one DLL element 15 be expressed similar 15 DQ delay min DQS delay max T 2 MAX 2 T 4 one DLL element 2 T 4 t3yin t2max one DLL element DQS delay is the combination of delays experienced by the DQS data strobe signal DQ delay is the combination of delays experienced by the DQ data signal both until the capture is performed by the controller DQS delay depends on t1 and 2 while DQ delay depends on t3 DDR2 write cycle timings Figure 6 DDR2 write cycle waveforms os Y Y t4 t5 t4 t5 t4 t5 DQ a The value DLL element stands for the DLL accuracy so we put DLL element in the formulas One DLL element 15 ps in best case and 85 ps in worst case Doc ID 16259 Rev 61 97 Timing characteristics SPEAr600 62 97 Figure 7 DDR2 write cycle path j tt 2 gt Das CLR Q CLK D n gt DQ CLR Q Table 33 DDR2 write cycle path timings without pad delay t3max t1 t1 Rising best 2 19 ns 2 08 ns 1 91 ns 2 13 ns Falling best 2 21 ns 2 11 ns 1 95 ns 2 15 ns Rising worst 5 55 ns 5 28 ns 5 2 ns 5 88 ns Falling worst 5 54 ns 5 30 ns 5 8 ns 5 85 ns
31. L2 L1 M1 M2 M3 M4 M5 6 5 4 P4 R4 USB_DEV_VBUS USB_DEV_VBUS USB_DEV_VBUS USB_DEV_VBUS P5 USB_HOST1_VBUS USB_HOST1_VBUS USB_HOST1_VBUS USB_HOST1_VBUS R5 USB_HOST2_VBUS USB_HOST2_VBUS USB_HOST2_VBUS USB_HOST2_VBUS P6 USB_HOST1_OVRC USB_HOST1_OVRC USB_HOST1_OVRC USB_HOST1_OVRC R6 USB_HOST2_OVRC USB_HOST2_OVRC USB_HOST2_OVRC USB_HOST2_OVRC P1 USB HOST2 DP USB HOST2 DP USB HOST2 DP USB HOST2 DP P2 USB HOST2 DM USB HOST2 DM USB HOST2 DM USB HOST2 DM T1 USB HOST DP USB HOST1 DP USB HOST1 DP USB HOST1 DP T2 USB HOST1 DM USB HOST1 DM USB HOST1 DM USB HOST1 DM 009445 uonduosep 46 66 eu 6429 12001 Table 16 Multiplexing scheme continued Ball Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Full RAS Mode 7 V1 USB DEV DP USB DEV DP USB DEV DP USB DEV DP v2 USB_DEV_DM USB_DEV_DM USB_DEV_DM USB_DEV_DM U4 USB_USB_RREF USB_USB_RREF USB_USB_RREF USB_USB_RREF 2 MCLK XO MCLK XO MCLK XO MCLK XO Y1 MCLK XI MCLK XI MCLK XI MCLK XI Table 17 Table shading Shading Pin group Shading Pin group GPIO GPIO pins FSMC FSMC pins UART UART pins SMI SMI pins GPT GPT pins TEST Test mode configuration pins uonduosep
32. TTL output Output Serial data out buffer 3 3 V UART2 TXD AA20 capable 4 mA UART UART1 RXD AB19 TTL input Input Serial data in buffer 3 3 V UART2_RXD AB20 tolerant PD TTL output FIRDA_TXD AA18 Output Serial data out buffer 3 3 V capable 4mA FIRDA TTL input FIRDA RXD AB18 Input Serial data in buffer 3 3 V tolerant PU Serial data TTL bidir SDA Yig vo in out buffer 3 3V 12C capable 4 mA SCL Y19 Serial clock 9 3 1 When the pin is not driven the output voltage is 2 5 On the core side logic 1 state is guaranteed Doc ID 16259 Rev 3 3 SPEAr600 Pin description Table 6 Group USB USB pins Signal name Ball Direction Function Pin type USB DEV DP V1 USB Device D Bidirectional yo analog buffer USB DEV DM v2 USB Device D 5 V tolerant TTL input buffer USB_DEV_VBUS R4 Input USB Device 3 3 V tolerant VBUS PD USB_HOST1_DP T1 USB HOST1 Bidirectional D analog buffer 5 V tolerant USB_HOST1_DM T2 USB HOST1 D TTL output USB_HOST1_VBUS 5 Output YSBHOSTT 3 3v VBUS capable 4 mA TTL input buffer USB_HOST1_OVRC P6 Input USB 53V tolerant Over current active low USB HOST2 DP P1 USB HOST Bidirectional 0 analog buffer 5 V tolerant USB_HOST2_DM P2 USB HOST2 D TTL output USB_HOST2_VBUS R5 Output USBHOST2 fer 3 3 V VBUS capable 4 mA TTL input bu
33. a FIQ or an IRQ interrupt is generated through the VIC the system enters DOZE mode Additionally the operating mode setting in the system control register automatically changes from SLEEP to DOZE DOZE mode In this mode the system clocks HCLK and CLK and the System Controller clock SCLK are driven by a low speed oscillator The System Controller moves into SLEEP mode from DOZE mode only when none of the mode control bits set and the processor is Wait for interrupt state If SLOW mode or NORMAL mode is required the system moves into the XTAL control transition state to initialize the crystal oscillator SLOW mode During this mode both the system clocks and the System Controller clock are driven by the crystal oscillator lf NORMAL mode is selected the system goes into the PLL control transition state If neither the SLOW nor the NORMAL mode control bits are set the system goes into the Switch from XTAL transition state NORMAL mode In NORMAL mode both the system clocks and the System Controller clock are driven by the PLL output If the NORMAL mode control bit is not set then the system goes into the Switch from PLL transition state Clock and reset system The clock system is a fully programmable block that generates all the clocks for the SPEAr600 The default operating clock frequencies are Clock 333 MHz for the CPUs Clock 166 MHz for AHB bus and AHB peripherals PLL1 source Clock 83 MHz f
34. bit e Master and slave mode capability e DMA interface I2C Main features Compliance to the 2 bus specification Philips 2 v2 0 compatible Supports three modes Standard 100 kbps Fast 400 kbps High speed 3 4 Mbps e Master and slave mode configuration possible e Slave Bulk data transfer capability DMA interface UARTs The SPEAr600 has two UARTs Main features Hardware flow control Separate 16x8 16 locations deep x 8 bits wide transmit and 16 x 12 receive FIFOs to reduce CPU interrupts Speed up to 3 Mbps Doc ID 16259 Rev 3 SPEAr600 Architecture overview 2 16 2 17 2 18 Fast IrDA controller The SPEAr600 has a Fast IrDA controller Main features Supports the following standards serial infrared physical layer specification IrPHY version 1 3 IrDA link access protocol IrLAP version 1 1 Supports the following infrared modes and baud rates Serial infrared SIR with rates 9 6 kbps 19 2 kbps 38 4 kbps 57 6 kbps and 115 2 kbps Medium Infrared MIR with rates 576 kbps and 1 152 Mbps Fast Infrared FIR with rate 4 Mbps Transceiver interface compliant to all IrDA transceivers with configurable TX and RX signal polarity Half duplex infrared frame transmission and reception 16 bit CRC algorithm for SIR and MIR and 32 bit CRC algorithm for FIR Generates preamble start and stop flags Uses the RZI Return to Zero Inve
35. characteristics 5 Electrical characteristics 5 1 Absolute maximum ratings This product contains devices to protect the inputs against damage due to high low static voltages However it is advisable to take normal precaution to avoid application of any voltage higher lower than the specified maximum minimum rated voltages The Absolute maximum rating is the maximum stress that can be applied to a device without causing permanent damage However extended exposure to minimum maximum ratings may affect long term device reliability Table 19 Absolute maximum ratings Symbol Parameter Minimum value Maximum value Unit Vpp 1 0 Supply voltage at 1 0 0 3 1 2 V Vpp 3 3 Supply voltage at 3 3 0 3 3 9 V Vpp 2 5 Supply voltage at 2 5 0 3 3 V Vpp 1 8 Supply voltage at 1 8 0 3 2 16 V Storage temperature 55 150 C Junction temperature 40 125 C 5 2 Maximum power consumption The following table includes the maximum current and power consumption for each power domain Note These values take into consideration the worst cases of process variation and voltage range and must be used to design the power supply section of the board Table 20 Maximum current and power consumption Symbol Description Max Unit Vpp 1 0 Supply voltage at 1 0 V 1000 mA Vpp 1 8 Supply voltage at 1 8 1 130 mA Vpp 2 5 Supply voltage at 2 5 V 22 mA Vpp 3 3 Supply voltage at 3 3 V 60 mA Vpp RTC Supply voltage at 1 8 V 10 Maximum pow
36. enable other ones The following modes be selected by setting the TEST 0 TEST 5 pins at the appropriate values This setting is used to program the control register SOC present in the Miscellaneous registers block MISC Please refer to the section 11 4 3 of the SPEAr600 reference manual RM0305 e Mode 0 Full features Mode 1 Disable_nand_flash Mode 2 Disable_LCD_ctr Mode 3 Disable_GMAC_ctr Mode 4 self_cfg4 Mode 5 self_cfg5 Full RAS Mode7 All Process disable Table 16 Multiplexing scheme shows all the alternate functions available in each mode Mode 0 is the default mode for SPEAr600 Full features Default configuration standard features Disable NAND Flash The NAND Flash interface is disabled and alternatively the following features are provided e extension for modem flow control e One additional SMI chip select please refer to section 17 8 1 in the SPEAr600 user manual for more details Disable LCD ctr The Color LCD controller interface is disabled and alternatively the following features are provided e UART extension for modem flow control e One additional clock programmable trought GPT registers Please refer to the SPEAr600 user manual 510 for more details e Additional 8 data lines of NAND Flash interface not otherwise available e One additional SMI chip select please refer to section 17 8 1 in the SPEAr600 user manual for more deta
37. speed with integrated PHY transceiver 10 GPIO bidirectional signals with interrupt capability JPEG codec accelerator 1clock pixel ADC 10 bit 1 Msps 8 inputs 1 bit DAC 3 SSP master slave supporting Motorola Texas instruments National Semiconductor protocols up to 40 Mbps 2 master slave interface slow fast high speed up to 1 2 Mb s 10 independent 16 bit timers with programmable prescaler peripherals Two UARTs speed rate up to 460 8 kbps Fast IrDA FIR MIR SIR 9 6 Kbps to 4 Mbps speed rate Audio block with 3 I2Ss interfaces to support Audio Play Up to 3 1 and Audio Record functionality Advanced power saving features Normal Slow Doze and Sleep modes CPU clock with software programmable frequency Enhanced dynamic power domain management Clock gating functionality Low frequency operating mode Automatic power saving controlled from application activity demands Vectored interrupt controller System and peripheral controller Doc ID 16259 Rev 9 97 Description SPEAr600 RTC with separate power supply allowing battery connection Watchdog timer Miscellaneous registers array for embedded MPU configuration External local bus EXPI I f that is an AMBA AHB like interface Programmable PLLs for CPU and system clocks JTAG IEEE 1149 1 boundary scan ETM functionality multiplexed on primary pins Supply voltages 1 0V core 1 8 V 2 5 V DDR 2 5 PLLs 1 8
38. 0 2 8 2 9 2 10 16 97 JPEG codec Main features Compliance with the baseline JPEG standard ISO IEC 10918 1 Single clock per pixel encoding decoding Support for up to four channels of component color 8 bit channel pixel depths Programmable quantization tables up to four Programmable Huffman tables two AC and two DC Programmable minimum coded unit MCU Configurable JPEG headers processing Support for restart marker insertion Use of two DMA channels and of two 8 x 32 bits FIFOs local to the JPEG for efficient transferring and buffering of encoded decoded data from to the codec core 8 channel ADC Main features Successive approximation ADC 10 bit resolution 1 Msps Hardware over sampling and accumulation up to 128 samples Eight analog input AIN channels ranging from 0 to 2 5 V INL 1 LSB DNL 1 LSB Programmable conversion speed min conversion time is 1 us Programmable averaging of results from 1 No averaging up to 128 Ethernet controller Main features Supports the default Gigabit Media Independent Interface GMII Media Independent Interface MII defined in the IEEE 802 3 specifications Supports 10 100 1000 Mbps data transfer rates with any one or a combination of the above PHY interfaces Supports both half duplex and full duplex operation In half duplex operation CSMA CD protocol is provided for as well as packet bursting and frame extension at 1000 Mbps Programmable fra
39. 01110 14 decimal then Lock time 4 ms 15 267 ys 5 9 ADC electrical parameters Table 30 ADC characteristics Parameters Min Typ Max Unit Input range absolute 0 0 3 AVppt0 3 V Conversion Range VREFN VREFP V Analog Input input Capacitance 5 6 4 8 pF Input Mux Resistance Total 1 5K 2K 2 5K equivalent Sampling Resistance Analog Supply AVpp 2 25 2 5 2 8 V Power Supply Digital Supply Vpp 0 9 1 0 1 1 V External VREFP 1 0 2 5 2 8 V Reference voltages VREFN 0 0 0 7 V Clock 3 14 MHz Frequency INL x1 LSB Performance DNL 1 LSB parameters Gain error 2 LSB Offset error LSB Temperature 40 25 125 AV pp External reference mode 0 6 0 8 1 mA Current AV pp Power down mode EN 0 0 4 Consumption Functional mode 0 1 0 15 0 2 mA Vpp Power down mode 1 ky Doc ID 16259 Rev 3 59 97 Timing characteristics SPEAr600 6 Timing characteristics 6 1 DDR timing characteristics The characterization timing is done considering an output load of 10 pF on all the DDR pads The operating conditions in worst case V 0 90 V TA 125 C and in best case V 1 10 V TA 40 C 6 1 1 DDR2 read cycle timings Figure 4 DDR2 read cycle waveforms t4 t5 t4 t5 t4 DQ Figure 5 DDR2 read cycle path DQ D SET Q DQS as
40. 2 6 945 ns 6 4 I2C timing characteristics The characterization timing is given for an output load of 10 pF on SCL and SDA The operating conditions are V 0 90 V T2125 C in worst case and V 1 10 V 40 C in best case Figure 19 output pads D Q SCL ol HCLK i SDA as Q Figure 20 input pads T HCLK TEE an Q The flip flops used to capture the incoming signals are re synchronized with the AHB clock so no input delay calculation is required Doc ID 16259 Rev 3 73 97 Timing characteristics SPEAr600 Figure 21 Output signal waveforms for 2 signals TsclHigh TSCLLow SCL 4 gt lt Tsu sTa Tsu pat A T STA HDDAT SU STQ SDA m The timings of high and low level of SCL TSCLHigh and TSCLLow are programmable Table 45 Timing characteristics for 2 in high speed mode Parameter Min TSU STA 163 31 ns THD STA 487 73 ns TSU DAT 313 38 ns THD DAT 7 04 ns TSU STO 642 98 ns THD STO 4 74 us Table 46 Timing characteristics for in fast speed mode Parameter Min TSU STA 643 27 ns THD STA 601 73 ns TSU DAT 1 19 us THD DAT
41. 259 Rev 3 SPEAr600 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER T
42. 3 SPEAr600 Timing characteristics 6 3 6 3 1 CLCD timing characteristics The characterization timing is done considering an output load of 10 pF on all the outputs The operating conditions in worst case V 0 90 V T 125 and in best case V 1 10 V T 40 C The CLCD has a wide variety of configurations and setting and the parameters change accordingly Two main scenarios will be considered one with direct clock to output 166 MHz setting BCD bit to 1 and the second one with the clock passing through a clock divider 83 MHz setting BCD bit to 0 Please refer to the Table 477 for more information on the significance of bit BCD CLCD timing characteristics direct clock Figure 15 CLCD waveform with CLCP direct EE Tclock 4 Tmax lt _ Tmin Tstable CLD 23 0 CLAC CLLE Te CLLP CLFP CLPOWER Figure 16 CLCD block diagram with CLCP direct Cu CLD 23 0 CLAC CLLE CLCDCLK CLLP CLFP CLPOWER CLCP Table 43 CLCD timings with direct Parameter Value Frequency Tclock direct max Tclock 6ns 166 MHz Tclock direct max rise Tr 0 81 ns Tclock direct max Tf 0 87 ns Tmin 0 04 ns Tmax 3 62 ns Tstable 2 34 ns Doc ID 16259 Rev 3 71 97
43. 6 V20 CLD 7 V21 CLD 8 V22 CLD 9 U22 CLD 10 U21 CLD 11 U20 LCD Data CLD 12 T20 CLD 13 T21 CLD 14 R21 CLD 15 R20 CLD 16 P19 TTL output buffer LCD I F CLD 17 P20 Output 3 3 V capable 8mA CLD_18 P21 CLD_19 N21 CLD_20 N20 CLD_21 N19 CLD_22 M20 CLD_23 M21 STN AC bias CLAC T22 drive TFT Data Enable CLCP R22 LCD Panel Clock STN Frame CLFP P22 Pulse TFT Vertical Sync STN Line CLLP N22 Pulse TFT Horizontal Sync CLLE M22 Line End CLPOWER M19 LCD Power Enable ky Doc ID 16259 Rev 3 35 97 Pin description SPEAr600 36 97 Table 13 LVDS I F pins Group Signal name Ball Direction Function Pin Type PHO A16 PHOn B16 PH1 C16 PHin C15 PH2 A15 PH2n B15 PH3 14 PH8n B14 Output General LVDS Driver LVDS I F PH4 C14 purpose PH4n C13 With LVDS transceiver PH5 13 PH5n B13 PH6 12 PH6n B12 PH7 C12 PH7n C11 PH8 11 Input LVDS Receiver PH8n B11 Doc ID 16259 Rev 3 3 SPEAr600 Pin description Table 14 EXPI I2S pins Group Signal name Ball Direction Function Pin Type PL GPIO 47 C2 ADO REC DIN PL GPIO 48 ADO_REC_WS PL_GPIO_50 A1 ADO WS OUT TTL bidirectional PL GPIO 51 B2 buffer ADO DOUT2 3V 8 V capable PL GPIO 52 45 3 3 V tolerant ADO_DOUT1 Ms EXPI I2S PL GPIO 53 C3 ADO CLK in 529 PL GPIO 54 B3 MCLK out 309 PL GPIO 55 A3 ADO REC
44. 7 04 ns TSU STO 642 98 ns THD STO 4 74 us Table 47 Timing characteristics for in standard speed mode Parameter Min TSU STA 4 73 us THD STA 3 99 us TSU DAT 4 67 us THD DAT 7 04 ns TSU STO 4 03 us THD STO 4 74 us 74 97 Doc ID 16259 Rev 3 ky SPEAr600 Timing characteristics Note Note The timings shown in Figure 21 depend on the programmed values of TSCLHigh and TSCLLow so the values present in Table 45 to Table 47 have been calculated using the minimum programmable values of IC_HS_SCL_HCNT 19 IC_HS_SCL_LCNT 53 registers for High Speed mode IC_FS_SCL_HCNT 99 and IC_FS_SCL_LCNT 215 registers for Fast Speed mode IC_SS_SCL_HCNT 664 and IC_SS_SCL_LCNT 780 registers for Standard Speed mode These minimum values depend on the AHB clock frequency which is 166 MHz A device may internally require a hold time of at least 300 ns for the SDA signal referred to the of the SCL signal to bridge the undefined region of the falling edge of SCL Please refer to the 2 Bus Specification v3 0 Jun 2007 However the SDA data hold time in the I2C controller of SPEAr600 is one clock cycle based 7 ns with the HCLK clock at 166 MHz This time be insufficient for some slave devices A few slave devices not receive the valid address due to the lack of SDA hold time and will not acknowledge even if the adaress is valid If the SDA data hold time is insufficient
45. 8 8 11 8 8 8 8 9 RTC XO RTC XO XO XO A9 RTC XI RTC XI RTC XI RTC XI A7 A6 A5 4 C10 D10 E10 9 D9 C9 A8 B8 C8 uonduosep 009445 69091 12001 26 67 Table 16 Multiplexing scheme continued D8 Ball Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Full RAS Mode 7 E8 B7 C7 D7 E7 F7 F6 E6 D6 C6 B6 B5 C5 D5 E5 D4 C4 B4 A3 B3 C3 A2 B2 Al B1 C1 C2 009445 uonduosep 26 04 69091 12001 Table 16 Multiplexing scheme continued D1 Ball Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Full RAS Mode 7 D2 D3 E1 E2 ES E4 F1 F2 F3 F4 F5 G5 G4 G3 G2 G1 H1 H2 H3 H4 H5 J5 J4 J3 J2 J1 K1 uonduosep 009445 6429 12001 26 16 Table 16 Multiplexing scheme continued K2 Ball Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Full RAS Mode 7 K3 K4 K5 K6 L5 L4 L3
46. ALE nUART1DTR NF_ALE NF_ALE NF_ALE G21 NF_CLE nUART1DSR NF_CLE NF_CLE NF_CLE H22 NF_RB nUART1RI NF_RB NF_RB NF_RB J18 NF_WP SMICS_OUT_3 NF_WP NF_WP NF_WP C17 MRESET MRESET MRESET MRESET D11 DDR2 EN DDR2 EN DDR2 EN DDR2 EN D17 nTRST nTRST nTRST nTRST E16 D15 TMS TMS TMS TMS D16 TDI TDI TDI TDI E17 TDO TDO TDO TDO E15 TEST O 0 0 0 0 0 0 0 0 E14 TEST 1 0 0 0 0 0 0 0 0 D14 TEST 2 0 0 0 0 0 0 0 1 D13 TEST 3 0 1 0 1 0 1 0 0 E1S TEST 4 0 0 1 1 0 0 1 1 D12 TEST 5 0 0 0 0 1 1 1 1 E22 TXCLK125 TXCLK125 TXCLK125 TXCLK125 F22 TXCLK GPIO basic 7 TXCLK TXCLK TXCLK D22 TXCLK GPIO basic 6 TXCLK TXCLK MII TXCLK F21 TXD 0 GPIO basic 5 TXD 0 TXD 0 TXD 0 E21 TXD 1 GPIO basic 4 TXD 1 TXD 1 TXD 1 F20 TXD 2 GPIO basic 3 TXD 2 TXD 2 TXD 2 E20 TXD 3 GPIO basic 2 TXD 3 TXD 3 TXD 3 D21 TXD 4 ARM1 7 TXD 4 TXD 4 GMII_TXD_4 uonduosep 009445 69091 12001 26 27 Table 16 Multiplexing scheme continued Ball Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Full RAS Mode 7 20 TXD 5 GPIO_ARM2 7 TXD 5 TXD 5 5 C22 TXD 6 nUARTIRTS TXD 6 TXD 6 TXD 6 C21 TXD 7 nUART1CTS TXD 7 TXD 7 GMIL TXD 7 D19 TX
47. CLD 2 CLD 2 CLD 2 w22 CLD_3 GPIO basic 4 CLD 3 CLD 3 CLD 3 w21 CLD_4 GPIO basic 3 CLD 4 CLD 4 CLD 4 20 CLD_5 GPIO basic 2 CLD 5 CLD 5 CLD 5 20 CLD_6 GPIO ARM1 7 CLD 6 CLD 6 CLD 6 v21 CLD_7 GPIO_ARM2 7 CLD_7 CLD_7 CLD_7 v22 CLD_8 5 CLD_8 CLD_8 CLD_8 U22 CLD 9 nUART1CTS CLD 9 CLD 9 CLD 9 U21 CLD_10 nUART1DCD CLD_10 CLD_10 CLD_10 U20 CLD_11 nUART1DTR CLD 11 CLD 11 CLD 11 T20 CLD 12 nUART1DSR CLD 12 CLD 12 CLD 12 T21 CLD_13 nUART1RI CLD 13 CLD 13 CLD 13 R21 CLD 14 5 5 OUT 3 CLD 14 CLD 14 CLD 14 R20 CLD 15 ARM1 6 CLD 15 CLD 15 CLD 15 P19 CLD 16 ARM1 5 CLD 16 CLD 16 CLD 16 P20 CLD 17 ARM1 4 CLD 17 CLD 17 CLD 17 P21 CLD 18 ARM 6 CLD 18 CLD 18 CLD 18 N21 CLD_19 GPIO_ARM2 5 CLD_19 CLD_19 CLD_19 N20 CLD_20 GPIO_ARM2 4 CLD_20 CLD_20 CLD_20 N19 CLD 21 HT EL CLD 21 CLD_21 CLD_21 M20 CLD_22 15 o CLD 22 CLD 22 CLD 22 M21 CLD_23 140 23 CLD_23 CLD_23 uonduosep 009445 69091 12001 26 9 Table 16 Multiplexing scheme continued Ball Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Full RAS Mode 7 T22 CLAC NFIO 13 o CLAC CLAC CLAC R22 CLCP NFIO 12 o CLCP CLCP CLCP P22 CLFP NFIO 11 o CLFP CLFP CLFP M22 CLLE NFIO 10 o CLLE CLLE CLLE N22 CLLP NFIO 9 o CLLP CLLP CLLP M19 CLPOWER NFIO 8 o CLPOWER CLPOWER CLPOWER L21 5 DA
48. EN nUART1DCD TX_EN TX_EN TX_EN D18 TX_ER nUART1DTR TX_ER TX_ER TX_ER A22 RX_CLK nUART1DSR RX_CLK RX_CLK RX_CLK C19 DV nUART1RI RX DV RX DV RX DV C20 RX ER SMICS OUT 3 RX ER RX ER RX ER B22 RXD 0 GPIO_ARM1 6 RXD 0 RXD 0 RXD 0 B21 RXD 1 GPIO_ARM1 5 RXD_1 RXD_1 RXD_1 A21 RXD 2 GPIO_ARM1 4 RXD_2 RXD_2 RXD_2 B20 RXD_3 GPIO_ARM2 6 RXD_3 RXD_3 RXD_3 A20 GMII_RXD_4 GPIO_ARM2 5 GMII_RXD_4 GMII_RXD_4 GMII_RXD_4 B19 GMII_RXD_5 GPIO_ARM2 4 GMII_RXD_5 5 RXD 5 18 6 M GMII_RXD_6 GMII_RXD_6 GMII_RXD_6 A19 GMII_RXD_7 GMII_RXD_7 GMII_RXD_7 GMII_RXD_7 A17 COL ee COL COL COL B17 CRS CRS CRS CRS C18 MDC nUART2RTS MDC MDC MDC B18 MDIO nUART2CTS MDIO MDIO MDIO E11 DIGITAL_REXT DIGITAL_REXT DIGITAL_REXT DIGITAL_REXT A16 PHO PHO PHO PHO B16 PHOn PHOn PHOn PHOn C16 PH1 PH1 PH1 PH1 C15 PH1n PH1n PH1n PHin A15 PH2 PH2 PH2 PH2 009445 uonduosep 26 87 6429 12001 Table 16 Multiplexing scheme continued Ball Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Full RAS Mode 7 B15 PH2n PH2n PH2n PH2n 14 14 PH3n PH3n C14 PHA PHA PHA PHA C13 PH4n PH4n PH4n PH4n A13 PH5 PH5 PH5 PH5 B13 PH5n PH5n PH5n PH5n A12 PH6 PH6 PH6 PH6 B12 PH6n PH6n PH6n PH6n C12 PH7 PH7 PH7 PH7 C11 PH7n PH7n PH7n PH7n A11 PH8 8
49. HE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2012 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Swe
50. MII 100Mb period 40 ns 25 MHz 2 26 ns 0 11 ns Value using MII 10 Mb 400 ns 2 5 MHz 2 26 ns 0 11 ns The input stage is the same for all the interfaces GMII and MII10 100 so tsgrup and 5 values are equal in all the cases The receive path is optimized for the GMII interface this also ensures correct capture of data for the MII10 100 interface Doc ID 16259 Rev SPEAr600 Timing characteristics 6 6 4 MDIO timing specifications Figure 39 MDC waveforms MDC Input Tsetup Thold MDIO lt gt lt Output 4 Tmax gt Tmin Figure 40 Paths from MDC MDIO pads INPUT 97D t1 2 4 OUTPUT CLK 2 MDIO ar Q t3 MDC Table 53 MDC MDIO timing Parameter Value Frequency period 614 4 ns 1 68 MHz fall tp 1 18 ns tci rise tj 1 14 ns Output tmax lcik 2 307 ns tmin 2 307 ns Input tseTUPmax 1 max 6 88 ns tnoLDmin 1 54 ns Note When MDIO is used as output the data are launched on the falling edge of the clock as shown in Figure 39 Doc ID 16259 Rev 3 83 97 Timing characteristics SPEAr600 6 7 SMI timing characteristics The characterization timing is gi
51. NFCE NFALE Twe NFWE Tio NFIO Address Figure 27 In out data address signal waveforms for 8 bit NAND Flash configuration NFCE Twe NFWE Tio NFIO out 4 0 Data Out X 3 TREAD NFRE e a TRE gt 10 TNrio gt FFs NFIO in lt gt lt gt X Table 48 Timing characteristics for 8 bit NAND Flash configuration Parameter Min Max TCLE 16 85 ns 19 38 ns TALE 16 84 ns 19 37 ns TWE s 1 11 10 ns 13 04 ns TRE 5 1 0 11 18 ns 13 05 ns TIO 1 3 43 ns 8 86 ns 1 TWE e TRE are the timings between the falling edge of NFCE and the once related to NFWE and NFRE respectively Both are composed by the algebric sum of a fixed part due to the internal delays of Spear and a programmable one in a FSMC register The programmable one is equal to s 1 Thclk where s Tset The values shown in the table are calculated using 5 1 2 TIO is the timing between the falling edge of NFCE and the first or the last change of NFIO depending on the min or the max timing It s composed by the algebric sum of a fixed part due to the internal delays of Spear and a programmable one in a FSMC register The programmable one is equal to h Thclk where h Thiz The values shown in the table are calculated using h 1 3 TREAD is the timing between the falling edge and the rising edge of NFRE This value is fully program
52. ORD CLK TTL bidirectional buffer 3 3 V PL CLK 4 Logic External 4 Output capable 8 mA ADO_CLK_OUT Clock 3 3 V tolerant Pu 1 When the pin is not driven the output voltage is 2 5 V On the core side logic 1 state is guaranteed ky Doc ID 16259 Rev 3 37 97 Pin description SPEAr600 38 97 Table 15 pins Group Signal name Ball Direction Function Pin Type PL GPIO 0 P4 PL GPIO 1 N4 PL_GPIO_2 N5 PL_GPIO_3 6 PL 4 5 PL GPIO 5 M4 PL_GPIO_6 M3 PL_GPIO_7 M2 PL_GPIO_8 M1 PL_GPIO_9 L1 PL GPIO 10 L2 PL GPIO 11 L3 PL GPIO 12 14 PL 13 L5 PL GPIO 14 K6 TTL 2 Logic B 4 PL 17 pu PL_GPIO_18 K2 PL_GPIO_19 K1 PL_GPIO_20 J1 PL_GPIO_21 J2 PL_GPIO_22 J3 PL_GPIO_23 J4 PL_GPIO_24 J5 PL_GPIO_25 H5 PL_GPIO_26 H4 PL_GPIO_27 H3 PL_GPIO_28 H2 PL_GPIO_29 H1 PL_GPIO_30 G1 PL GPIO 31 G2 Doc ID 16259 Rev 3 7974 SPEAr600 Pin description Table 15 pins continued Group Signal name Ball Direction Function Pin Type PL GPIO 32 G3 PL GPIO 33 G4 PL_GPIO_34 G5 PL_GPIO_35 F5 PL_GPIO_36 F4 PL_GPIO_37 F3 PL_GPIO_38 F2 PL_GPIO_39 F1 PL GPIO 40 E4 PL GPIO 41 ES PL GPIO 42 E2 TTL bidirectiona
53. TAIN 5 DATAIN SMI DATAIN DATAIN L20 DATAOUT DATAOUT DATAOUT DATAOUT L22 SMI SMI 119 SMI CS 0 SMI CS 0 SMI CS 0 SMI CS 0 L18 SMI CS 1 SMI CS 1 SMI CS 1 SMI CS 1 K22 SSP 2 SCLK SSP 2 SCLK SSP 2 SCLK SSP 2 SCLK K21 SSP 2 MISO SSP 2 MISO SSP 2 MISO SSP 2 MISO K20 SSP 2 MOSI SSP 2 MOSI SSP 2 MOSI SSP 2 MOSI K18 BOOT SEL K19 SSP 2 SS 0 SSP 2 SS 0 SSP 2 SS 0 SSP 2 55 0 J22 SSP 3 SCLK SSP 3 SCLK SSP 3 SCLK SSP 3 SCLK J21 SSP 3 MISO SSP 3 MISO SSP 3 MISO SSP 3 MISO J20 SSP 3 MOSI SSP 3 MOSI SSP 3 MOSI SSP 3 MOSI J19 SSP 3 SS 55 3 SS 3 SS SSP 3 SS H19 NF IO O GPIO_basic 7 NF 10 0 NF IO 0 NF IO O H18 NF IO 1 basic 6 NF IO 1 NF IO 1 NF IO 1 G19 NF IO 2 GPIO basic 5 NF IO 2 NF IO 2 NF IO 2 G18 NF IO 3 GPIO basic 4 NF IO 3 NF IO 3 NF IO 3 F19 NF IO 4 GPIO_basic 3 4 4 NF IO 4 F18 NF IO 5 GPIO basic 2 NF IO 5 NF IO 5 NF IO 5 E18 NF IO 6 ARM1 7 NF IO 6 NF IO 6 NF IO 6 E19 NF IO 7 GPIO_ARM2 7 NF IO 7 NF IO 7 NF IO 7 009445 uonduosep 26 90 eu 69091 dI 90d Table 16 Multiplexing scheme continued Ball Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Full RAS Mode 7 G20 NF_CE nUART1RTS NF_CE NF_CE NF_CE H20 NF_WE nUART1CTS NF_WE NF_WE NF_WE G22 NF_RE nUART1DCD H21 NF_
54. V RTC and 3 3 V I Os Operating temperature 40 to 85 C ESD rating HBM class 2 CDM class Il PBGA420 23 x 23 x 2 06 mm pitch 1 mm 10 97 Doc ID 16259 Rev 3 ky SPEAr600 Architecture overview 2 Architecture overview Figure 2 shows an example of a typical SPEAr600 based system Figure 2 Typical system architecture using SPEAr600 Internet Access TouchScreen USB2 0 PHY device USB2 0 PHY Host ADC LCD controller Ethernet USB2 0 PHY Host 8 Channel DMA B Debug Trace 2 uas EXPI I f 30 MHz 32 kHz The of the SPEAr600 is the dual 926 5 reduced instruction set computer RISC processor It supports the 32 bit ARM and 16 bit Thumb instruction sets enabling the user to trade off between high performance and high code density and includes features for efficient execution of Java byte codes Each ARM CPU e Is clocked at a frequency up to 333 MHz Embeds 16 Kbytes instruction cache 16 Kbytes data cache e Features a memory management unit MMU which makes it fully compliant with Linux and VxWorks operating systems The SoC includes three major subsystems logic domains which control the following function blocks Configurable Cell Array Subsystem This block contains the Reconfigurable Array Subsystem logic RAS made by an array of 600Kgate equivalent stan
55. and MOSI master output slave input pad are provided Table 56 Timing requirements for SSP all modes No parameters value unit 1 Tc CLk Cycle time SSP_SCLK 24 min ns 2 Tw CLKH Pulse duration SSP_SCLK high AQT 51T ns 3 Tw CLKL Pulse duration SSP_SCLK low 51T 49T ns T Tc CLK 55 CLK period is equal to the SSP module master clock divided by a configurable divider Figure 43 SSP CLK timing 2 y k CPOL 0 SCLK CPOL 1 Doc ID 16259 3 ky SPEAr600 Timing characteristics The Motorola SPI interface is a four wire interface where SSP_SS signal behaves as a slave select The main feature of the Motorola SPI format is that the inactive state and phase of the output clock signal are programmable through the CPOL clock polarity and CPHA clock phase parameters inside an IP control register CPOL clock polarity When CPOL clock polarity control parameter is low it produces a steady state low value on the output clock pin If this parameter is high a steady state high value is placed on the output clock pin when data is not being transferred clock phase The CPHA clock phase control parameter selects the clock edge that captures data and allows it to change state When CPHA is low data is captured on the first clock edge transition after slave selection and is changed on the sec
56. at 1 8 1 62 1 8 1 98 V TA Ambient temperature 40 85 C Ty Junction temperature 40 125 C Overshoot and undershoot This product can support the following values of overshoot and undershoot Table 22 Overshoot and undershoot specifications Parameter 3V3 I Os 2 51 1V8 I Os Amplitude 500 mV 500 mV 500 mV Ratio of overshoot or undershoot duration with respect to pulse width 15 vs If the amplitude of the overshoot undershoot increases decreases the ratio of overshoot undershoot width to the pulse width decreases increases The formula relating the two is Amplitude of OS US 0 75 1 ratio of OS or US duration with respect to pulse width The value of overshoot undershoot should not exceed the value of 0 5 V However the duration of the overshoot undershoot can be increased by decreasing its amplitude Doc ID 16259 Rev 3 SPEAr600 Electrical characteristics 5 5 5 6 3 3V I O characteristics The 3 3 V I Os are compliant with JEDEC standard JESD8b Table 23 Low voltage TTL DC input specification V lt Vpp 3 6 V Symbol Parameter Min Max Unit Vit Low level input voltage 0 8 V High level input voltage 2 V Vhyst Schmitt trigger hysteresis 300 800 mV Table 24 Low voltage TTL DC output specification V lt Vpp 3 6 V Symbol Paramete
57. cess latency The overall memory bandwidth assigned to each master port can be programmed and optimized through an internal efficient weighted round robin arbitration mechanism Embedded memory units The SPEAr600 has two embedded memory units 32 Kbytes of BootROM 8 Kbytes of SRAM DDR DDR2 memory controller SPEAr600 integrates a high performance multi channel memory controller able to support DDR1 and DDR2 double data rate memory devices The multi port architecture ensures that memory is shared efficiently among different high bandwidth client modules Main features Multi channel AHB interfaces Seven independent AHB ports Separate AHB memory controller programming interface Support all AHB burst types Lock transaction are not supported e Internal efficient port arbitration scheme to ensure high memory bandwidth utilization Programmable register interface to control memory device parameters and protocols e DRAM controller supports both DDR1 and DDR2 memory devices DDR1 up to 166 MHz DDR2 up to 333 MHz e Memory frequency with DLL enable configurable from 100 MHz to 333 MHz e Wide range of memory devices supported 128 Mbit 256 Mbit 512 Mbit 1 Gbit 2 Gbit Two chip selects 16 bit data width Serial memory interface SPEAr600 provides a Serial Memory Interface SMI acting as an AHB slave interface 32 16 or 8 bit to SPI compatible off chip memories These serial memori
58. coming from the integrated frequency synthesizers core clock frequency PII2 frequency 48 MHz clock USB PII 30 MHz clock Main Oscillator 32 768 kHz clock RTC Oscillator clock programmable AHB clock programmable User Configurable sync async clock towards Memory Controller port 2 M2 Connection with 84 112 I Os Connection with 9 LVDS lines 12 interrupt lines towards CPU1 and CPU2 64 interrupt input lines from the various platform IP sources 16 peripheral DMA request lines 64 user configurable in the SoC general purpose input lines 64 user configurable in the RAS general purpose output lines SoC dynamic power management control interface 50 specific ATE Test interface signals dedicated to RAS External Port Controller EXPI I F The port controller is a socket communication interface between the SPEAr600 and an external FPGA device it implements a simple AHB bidirectional protocol used to compress a couple of std AHB master slave bus onto 84 PL GPIOs and 4 PL primary signals PL GPIO pins are not configurable by software ST provide a symmetric port controller logic solution to be embedded inside the external FPGA with the purpose of interfacing the EXPI bus directly and decompressing the same pair of AHB master slave ports on the FPGA side in order to interconnect the customer logic as follows more slave and master agents can be connected to the SPEAr600 AHB mas
59. d Table 6 USB pins Updated Figure 1 Functional block diagram and Figure 2 Typical system architecture using SPEAr600 Changed SPI with SSP where necessary Inserted the new Section 6 8 SSP timing characteristics Corrected the frequency of DDR1 Separated the Electrical characteristics and Timing characteristics in two chapters Changed the title of the Section 5 5 3 3V I O characteristics Added Table 62 SPEAr600 PBGA420 thermal resistance characteristics Updated Figure 25 Figure 26 Figure 27 Figure 30 Figure 31 Figure 32 Added a line of explanation in the introduction of Section 3 Pin description Added new Section 3 3 Configuration modes Added new Section 2 25 External Port Controller EXPI I F Doc ID 16259 Rev 3 95 97 Revision history SPEAr600 96 97 Table 63 Document revision history continued Date 09 May 2012 Revision Changes Modified FSMC feature on page 1 Figure 2 Typical system architecture using SPEAr600 Deleted SRAM and ROM blocks which were connected to the FSMC block Substituted SSP with 3xSSP Added the RAS block Section 1 1 Main features on page 9 Deleted the word parallel from bullet seven about FSMC Replaced SPI with SSP in bullet sixteen Modified number of GPIOs to 10 Added information about RAS Reconfigurable Array Subsystem Chapter 2 Architecture overview reviewed the first i
60. dard cells freely customizable by means of a few metal and via mask layer changes during the customization process The programmable logic allows reducing the SoC NRE cost the development cycle time improving the devices time to Doc ID 16259 Rev 3 11 97 Architecture overview SPEAr600 Caution 12 97 market The user custom logic can be configured using the following SoC internal resources e 130Kbyte of static memory arranged in four 32 KB macro group and one 2 KB group Up to 17 selectable source clocks either internal or external DMA support up to 16 configurable dma input output request lines Power management Interrupts line 12 outputs 64 inputs 4 AHB output master ports interconnected with the multi channel memory controller 5 AHB input slave ports 1 interconnection port with the Expansion Interface bus EXPI 9 LVDS 8 outputs 1 input signals 88 112 PL GPIOs primary input output signals PL GPIO pins are not configurable by software Common Subsystem This block consists of four different logic subsystems used to control the SoC basic functions e connectivity Low speed UARTs SSPs I2C and IrDA High speed MII 10 100 1000 USB 2 0 host and devices Hardware accelerator JPEG codec and DMA Video Color LCD interface Common resources Timers GPIOs RTC and Watchdog Power management functionality SoC configurability Miscellaneous control logic CPU Subsystem The SPEAr600
61. den Switzerland United Kingdom United States of America www st com ky Doc ID 16259 Rev 3 97 97 Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information STMicroelectronics EVALSPEAR600FPG SPEAR600 2
62. e 6 2 1 Note 66 97 Table 36 EXPI pad signal assignment continued EXPI signal Direction PL GPIOs signal assignment HLock Inp PL GPIO 37 HMastlock Out PL GPIO 38 HBreq Inp PL GPIO 39 HGrant Out PL GPIO 40 HResp 1 0 Bidir PL GPIO 42 41 HReagy mst Out PL GPIO 43 HReagy out Inp PL GPIO 44 HReady Out PL GPIO 45 HSel Out PL GPIO 46 LREQ 1 0 HAdd 25 24 Inp PL GPIO 48 47 DMA REQ 1 0 HAdd 27 26 Inp PL GPIO 50 49 DMACCLR 1 0 HAdd 29 28 Out PL GPIO 52 51 DMACTC 1 0 HAdd 31 30 Out PL GPIO 54 53 INT IN 2 Inp PL GPIO 83 CLK Bidir PL_CLK_1 Reset Bidir PL_CLK_2 INT_IN_1 Inp PL_CLK_3 INT_OUT Out PL_CLK_4 For more details please refer to the Expansion interface EXPI chapter of the user manual Pad delay disabled Figure 11 Pad delay disabled block diagram gem tn D Qar CLK D QL tout LLL PL GPIO x lt Q io pad PL_CLK1 The pad of the clock is disabled or enabled using the expi_clk_retim bit in the EXPI_CLK_CFG register Refer to the MISC registers chapter of the user manual Doc ID 16259 Rev 3 SPEAr600 Timing characteristics Figure 12 EXPI signal timing waveforms
63. e SPEAr600 internal delay 9 ns Doc ID 16259 Rev 3 79 97 Timing characteristics SPEAr600 Note 6 6 6 6 1 80 97 Values in Table 49 are referred to the common internal source clock which has a period of THCLK 6 ns Ether MAC 10 100 1000 Mbps GMAC Univ timing characteristics The characterization timing is given for an output load of 5 pF on the GMII TX clock and 10 pF on the other pads The operating conditions in worst case V 0 90 V T2125 C and in best case 1 10 V 40 C GMII Transmit timing specifications Figure 33 GMII TX waveforms GMIITX CLK lt Tclock i 7 Tmax TXDO TXD3 GMIITX D4 GMIITX TXEN TXER Tf Tr Figure 34 Block diagram of GMII TX pins TX 0 3 TX 4 7 TXEN TXER 3 GMII TX 4 7 C 2 gt TXEN TXER CLK ar Q t3 GMII_TXCLK Table 50 TX timing Parameter Value using tc period 8 ns 125 MHz trise tr 1 ns tran tr 1 ns tmax 2 8 ns tmin t2min 0 4 ns SETUP 5 19 ns Doc ID 16259 Rev 3 ky Timing characteristics you have to apply the following formula
64. er 3 3 V TEST_3 D13 ports tolerant PD TEST_4 E13 TEST_5 D12 DEBUG TTL Schmitt trigger input nTRST D17 Input Test reset Input buffer 3 3 V tolerant PU TTL output TDO E17 Output Test data outpuT buffer 3 3 V capable 4 mA TCK E16 Input Test clock TTL Schmitt trigger input TDI D16 Input Test data input buffer 3 3 V TMS D15 Input Test mode select tolerant PU Table 5 SMI SSP UART FIRDA and 2 pins Group Signal name Ball Direction Function Pin type SMI DATAIN L21 Input Serial Flash TTL input input data buffer 3 3 V DATAOUT L20 Serial Flash output data SMI TTL output SMI_CLK 22 Serial Flash buffer 3 3 V p clock capable SMI_CS_0 L19 Serial Flash 4mA SMI_CS_1 L18 chip selects ky Doc ID 16259 Rev 3 27 97 Pin description SPEAr600 28 97 Table 5 SMI SSP UART FIRDA and I2C pins continued Group Signal name Ball Direction Function Pin type SSP_1_MOSI 21 Master out slave in SSP_1_MISO 21 Master in slave out SSP_1_SCLK AB22 Serial clock SSP_1_SS AA22 Slave select SSP 2 K20 E a TTL bidir buffer 3 3 aster in slave SSP SSP_2_MISO K21 capable 8 mA SSP_2_SCLK K22 Serial clock 3 3 V 88 2 55 0 19 Slave select 9 SSP 3 MOSI J20 Master out slave in SSP 3 MISO J21 Master in slave out SSP_3_SCLK J22 Serial clock SSP_3_SS J19 Slave select UART1_TXD 19
65. er consumption 1500 mW 1 Average current with Linux memory test 50 write and 50 read plus DMA reading memory 2 With 30 logic channels connected to the device and simultaneously switching at 10 MHz Doc ID 16259 Rev 3 55 97 Electrical characteristics SPEAr600 5 3 5 4 Note 56 97 3 The maximum current and power values listed above obtained with typical supply voltages are not guaranteed to be the highest obtainable These values are dependent on many factors including the type of applications running clock rates use of internal functional capabilities external interface usage case temperature and the power supply voltages Your specific application can produce significantly different results 1 V current and power are primarily dependent on the applications that are running and the use of internal chip functions DMA USB Ethernet and so on 3 3 V current and power are primarily dependent on the capacitive loading frequency and utilization of the external buses DC electrical characteristics The recommended operating conditions are listed in the following table Table 21 Recommended operating conditions Symbol Parameter Min Typ Max Unit Vpp 1 0 Supply voltage at 1 0 0 95 1 1 10 V Vpp 3 3 Supply voltage at 3 3 3 3 3 3 6 V Vpp 2 5 Supply voltage at 2 5 2 25 2 5 2 75 V Vpp 1 8 Supply voltage at 1 8 1 70 1 8 1 9 V VppRTC Supply voltage
66. es can be used either as data storage or for code execution Doc ID 16259 Rev 13 97 Architecture overview SPEAr600 2 4 Note 14 97 Main features d the following SPl compatible Flash and EEPROM devices STMicroelectronics M25Pxxx 45 STMicroelectronics M95xxx except M95040 M95020 and M95010 ATMEL AT25Fxx YMC Y25Fxx SST SST25LFxx Acts always as a SPI master and supports up to SPI slave memory devices with separate chip select signals with up to 16 MB address space each SMI clock SMICLK is generated by SMI and input to all slaves using a clock provided by the AHB bus SMI CLK can be up to 50 MHz in fast read mode 20 MHz in normal mode It can be controlled by 7 programmable bits Flexible static memory controller Root part number 1 provides Flash Nand Static Memory Controller FSMC which is intended to interface an AHB bus to external NAND Flash memories Main purpose of FSMC is then e Translate AHB protocol into the appropriate external storage device protocol e Meetthe timing of the external devices slowing down and counting an appropriate number of HCLK AHB clock cycles to complete the transaction to the external device The external storage device cannot be faster than one AHB cycle Main features of the FSMC are listed below e is an AMBA slave module connected to the AHB e Provides an interface between AHB system bus and Na
67. est status e Software interrupt generation General purpose timers SPEAr600 provides five general purpose timers GPTs acting as APB slaves Each GPT consists of 2 channels each one made up of a programmable 16 bit counter and a dedicated 8 bit timer clock prescaler The programmable 8 bit prescaler performs a clock division by 1 up to 256 and different input frequencies can be chosen through SPEAr600 configuration registers frequencies up to 83 MHz can be synthesized Doc ID 16259 Rev 3 21 97 Architecture overview SPEAr600 2 22 2 23 2 24 22 97 Two different modes of operation are available Auto reload mode an interrupt source is activated the counter is automatically cleared and then it restarts incrementing e Single shot mode an interrupt source is activated the counter is stopped and the GPT is disabled Watchdog timer The ARM watchdog module consists of a 32 bit down counter with a programmable time out interval that has the capability to generate an interrupt and a reset signal on timing out The watchdog module is intended to be used to apply a reset to a system in the event of a software failure RTC oscillator The RTC provides a 1 second resolution clock This keeps time when the system is inactive and can be used to wake the system up when a programmed alarm time is reached It has a clock trimming feature to compensate for the accuracy of the 32 768 kHz crystal and a secured time upda
68. ffer USB HOST2 OVRC R6 Input USB Host2 44 V tolerant Over current active low Analog see USB_USB_RREF U4 Output 3 on resistor page 24 Doc ID 16259 Rev 29 97 Pin description SPEAr600 Table 7 Ethernet pins Group Signal name Ball Direction Function Pin type Transmit clock 22 Output 3 3 V capable GMIl 8 mA TXCLK125 22 Input Ext Clock input buffer TXCLK D22 cock 33v tolerant PD TXD 0 F21 TXD 1 E21 TTL output buffer Output 3 3 V capable TXD_2 F20 8 mA TXD_3 E20 Transmit data GMII_TXD_4 D21 TTL bidirectional GMII_TXD_5 D20 i buffer 3 3 V GMII_TXD_6 C22 capable 8 mA 3 3 V tolerant PD GMII_TXD_7 C21 TX_ER D18 Transmit error TTL output buffer Output 3 3 V capable TX_EN D19 Transmit enable 8 mA RX_ER C20 Receive error Ethernet RX_DV C19 RX_CLK A22 Receive clock TTL input butter RXD 0 B22 P 3 3 V tolerant PD RXD_1 B21 RXD_2 A21 RXD_3 B20 Receive data GMII_RXD_4 A20 TTL bidirectional GMII_RXD_5 B19 buffer 3 3 6 18 capable 8 mA 3 3 V tolerant PD GMII_RXD_7 A19 COL A17 Collision detect TTL input buffer CRS B17 Carrier sense 3 3 V tolerant PD TTL bidirectional Management buffer 3 3 V MDIO BIS O data I O capable 4 mA 3 3 V tolerant PD Management TTL output buffer MDC C18 Output 9 3 3 capable data clock 30 97
69. has a symmetric processor architecture with e 2 equivalent subsystems including the ARM926 and its private subsystem logic GPIOs Interrupt controller and Timer providing the essential hardware resources to support a generic Operating System e subsystem is replicated twice so both processors have the same memory This structure enables a true symmetric multi processor architecture were both processors can simultaneously execute the same OS all interrupt sources are handled by both processors e Allinternal peripherals are shared allowing flexible and efficient software partitions e High aggregate throughput can be sustained by splitting critical tasks either onto additional CPUs and optional hardware accelerator engines e Both processors are equipped with ICE and ETM configurable debug interfaces for real time CPU activity tracing and debugging 4 bit and 8 bit normal trace mode and 4 bit demultiplexed trace mode is supported with normal or half rate clock The internal architecture is also based on several shared subsystem logic blocks interconnected through a multilayer interconnection matrix The switch matrix structure Doc ID 16259 Rev 3 ky SPEAr600 Architecture overview 2 1 2 2 2 3 allows different subsystem data flows to be executed in parallel improving the core platform efficiency High performance master agents are directly interconnected with the memory controller reducing the memory ac
70. ils Doc ID 16259 Rev 3 41 97 Pin description SPEAr600 3 3 4 3 3 5 3 3 6 3 3 7 42 97 Disable GMAC ctr The GMAC interface is disabled and alternatively the following features are provided Two UARTs with extension for modem flow control and one with simplified hardware flow control e One additional SMI chip select please refer to section 17 8 1 in the SPEAr600 user manual for more details e Fouradditional clocks programmable trough the GPT registers Please refer to the SPEAr600 user manual 510 for more details Self cfg 4 In this mode the AHB expansion interface is enabled on the GPIO 83 0 pins In this mode source clock and reset signals are provided from the external application logic Self cfg 5 In this mode the AHB expansion interface is enabled on the PL GPIO 83 0 pins In this mode source clock and reset signals are internally provided All processors disabled This mode configures the SoC as I O slave target device controlled by an external master application the internal processors can be disabled Doc ID 16259 Rev 3 ky eu 69091 12001 Z6 V Table 16 Multiplexing scheme Ball Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Full RAS Mode 7 W11 AIN 0 AIN 0 0 0 V11 1 1 1 1 V12 AIN 2 AIN 2 AIN 2 AIN 2 W12 AIN 3 AIN 3
71. l buffer PL_GPIO_43 E1 4 TT div capable PL GPIO 44 D3 4 mA PL GPIO 45 D2 s ao PL_GPIO_46 D1 PL_GPIO_49 B1 PL_GPIO_56 B4 PL_GPIO_57 C4 PL_GPIO_58 D4 PL_GPIO_59 E5 PL_GPIO_60 D5 PL_GPIO_61 C5 PL_GPIO_62 B5 PL_GPIO_63 B6 ky Doc ID 16259 Rev 3 39 97 Pin description SPEAr600 Table 15 pins continued Group Signal name Ball Direction Function Pin Type PL GPIO 64 C6 PL GPIO 65 D6 PL GPIO 66 E6 PL_GPIO_67 F6 PL GPIO 68 F7 PL GPIO 69 E7 PL GPIO 70 D7 PL GPIO 71 C7 PL GPIO 72 B7 TTL PL GPIO 73 E8 NE D8 EA sie 4 mA EXPI PL GPIO 75 C8 PL GPIO 76 B8 PL GPIO 77 A8 PL GPIO 78 C9 PL GPIO 79 D9 PL GPIO 80 E9 PL GPIO 81 E10 PL GPIO 82 D10 PL GPIO 83 C10 PL CLK 1 A7 TTL bidirectional PL 2 A6 Logic External 2 3 3 V tolerant PL_CLK_3 5 40 97 1 When the pin is not driven the output voltage is 2 5 V On the core side logic 1 state is guaranteed Doc ID 16259 Rev SPEAr600 Pin description 3 3 3 3 1 3 3 2 3 3 3 Configuration modes The previous tables show the connectivity of the pins in the default configuration mode full features On top of this SPEAr600 can be also configured in different modes This section describes the main operating modes created by disabling some IPs to
72. m Q D tin gt Qar D 0 C tout PL_GRO x tac ff nd Q SEK PR PL_CLK1 Note The pad of the clock is disabled or enabled using the expi_clk_retim bit in the EXPI_CLK_CFG register Refer to the MISC registers chapter of the user manual 68 97 Doc ID 16259 Rev 3 SPEAr600 Timing characteristics Figure 14 EXPI signal timing waveforms PL_CLK1 2 im Input X PL GPIO x 4 Ls fal T 4 Output Dg lt Ea Table 40 Clock and Reset Parameter Value Frequency CLK period 15 66 6 MHz Tf CLK fall 0 81 ns Tr CLK rise 0 81 ns Output Signals Tmin ns Tmax ns Reset 0 84 6 Table 41 50 Output Signals Tmin ns Tmax ns HADDR 2 66 12 33 HSIZE HWRITE HBURST HTRANS HMASTLOCK HSEL 2 85 11 11 HReady 45 HWDATA 2 77 13 7 Input Tsetup ns Thold ns HReady out 44 HRESP 0 6 1 68 HRDATA 0 08 1 83 Table 42 SOC slave Input Signals Tsetup ns Thold ns HADDR 1 37 1 83 HSIZE HWRITE HBURST 0 62 1 83 HTRANS HLOCK HBUSREQ HWDATA 0 23 1 83 Doc ID 16259 Rev 69 97 Timing characteristics SPEAr600 70 97 Table 42 SOC slave continued Input Output Tmin ns Tmax ns HGRANT HReady_mst 43 HRESP 3 11 10 61 HRDATA 2 68 13 74 Doc ID 16259 Rev
73. mable and it s equal to w 1 T hclk gt gt T nfio gt FFs where w Twait T re gt io is the output delay of the NAND Flash and T nfio gt FFs is the SPEAr600 internal delay 9 ns Doc ID 16259 Rev 3 77 97 Timing characteristics SPEAr600 Note Values in Table 48 are referred to the common internal source clock which has a period of THCLK 6 ns 6 5 2 16 bit NAND Flash configuration Figure 28 Output pads for 16 bit NAND Flash configuration NFCLE NFCE diio NFWE HCLK NFRWPRT NFALE NFIO 0 7 CLPOWER CLLP CLLE CLFP NFIO_8 15 CLCP CLAC e CLD_23 22 Figure 29 Input pads for 16 bit Flash configuration NFRB 0 7 gt HCLK ar CLPOWER CLLP CLLE CLFP NFIO 8 15 CLCP CLAC D SET Q CLD 23 22 CLR Q Figure 30 Output command signal waveforms 16 bit NAND Flash configuration NFCE N Tere NFCLE X Twe NFWE lt 2 Tio NFIO Command X 78 97 Doc ID 16259 Rev 3 ky SPEAr600 Timing characteristics 2 Figure 31 Output address signal waveforms 16 bit NAND Flash configuration NFCE TALE NFALE b Twe NFWE Tio NFIO Address Figure 32 I
74. me length to support both Standard and Jumbo Ethernet frames with size up to 16 Kbytes 32 bit data transfer interface on system side A variety of flexible address filtering modes are supported A set of control and status registers CSRs to control GMAC Core operation Complete network statistics with RMON Counters MMC MAC Management Counters Doc ID 16259 Rev 3 ky SPEAr600 Architecture overview 2 11 2 12 Native DMA with single channel Transmit and Receive engines providing 32 64 128 bit data transfers DMA implements dual buffer ring or linked list chained descriptor chaining A set of CSRs to control DMA operation An AHB slave acting as programming interface to access all CSRs for both DMA and GMAC core subsystems An AHB master for data transfer to system memory 32 bit AHB master bus width supporting 32 bit wide data transactions Supports both big endian and little endian byte ordering Power Management Module PMT with Remote Wake up and Magic Packet frame processing options USB2 host controller SPEAr600 has two fully independent USB 2 0 hosts Each consists of 5 major blocks EHCI capable of managing high speed transfers HS mode 480 Mbps OHCI that manages the full and the low speed transfers 12 and 1 5 Mbps Local 2 Kbyte FIFO Local DMA e Integrated USB2 transceiver PHY Both hosts can manage an external power switch providing a control line to enable or disable the power and an inp
75. n out data signal waveforms for 16 bit NAND Flash configuration NFCE NFWE NFIO out js Out READ a RE gt TNFIO gt FFs NFIO in 4 4 gt X Table 49 Timing characteristics for 16 bit NAND Flash configuration Parameter Min Max TCLE 16 85 ns 19 38 ns TALE 16 84 ns 19 37 ns TWE s 1 11 10 ns 13 04 ns TRE 5 1 0 11 18 ns 13 05 ns TIO 1 3 27 ns 11 35 ns 1 TWE e TRE are the timings between the falling edge of NFCE and the once related to NFWE and NFRE respectively Both are composed by the algebric sum of a fixed part due to the internal delays of Spear and a programmable in a FSMC register The programmable one is equal to s 1 Thclk where s Tset The values shown in the table are calculated using 5 1 2 TIO is the timing between the falling edge of NFCE and the first or the last change of NFIO depending on the min or the max timing It s composed by the algebric sum of a fixed part due to the internal delays of Spear and a programmable one in a FSMC register The programmable one is equal to h Thclk where h Thiz The values shown in the table are calculated using h 1 3 TREAD is the timing between the falling edge and the rising edge of NFRE This value is fully programmable and it s equal to T read w 1 T hclk gt gt T nfio gt FFs where w Twait T re gt io is the output delay of the NAND Flash and T nfio gt FFs is th
76. nd Flash memory devices with 8 and 16 bits wide data paths FSMC performs only one access at a time and only one external device is accessed Support little endian and big endian memory architectures Handles AHB burst transfers to reduce access time to external devices Supplies an independent configuration for each memory bank Provides programmable timings to support a wide range of devices Programmable wait states up to 31 Programmable bus turn around cycles up to 15 Programmable output enable and write enable delays up to 15 e Provides only one chip select for the first memory bank e Shares the address bus and the data bus with all the external peripherals whereas only chips selects are unique for each peripheral e Offers an external asynchronous wait control e Offers configurable size at reset for boot memory bank using external control pins Doc ID 16259 Rev 3 ky SPEAr600 Architecture overview 2 5 2 6 2 7 Multichannel DMA controller Within its basic subsystem SPEAr600 provides a DMA controller DMAC able to service up to 8 independent DMA channels for serial data transfers between a single source and destination i e memory to memory memory to peripheral peripheral to memory and peripheral to peripheral Each DMA channel can support unidirectional transfers with one internal four word FIFO per channel LCD controller Main features e Resolution programmable up to 1024 x 768
77. ns To expand its range of target applications SPEAr600 can be extended by adding additional peripherals through the external local bus EXPI interface Figure 1 Functional block diagram USB Host 2 0 Phy USB Host 2 0 Phy USB Device 2 0 Phy PC master slave 2x UART MultiChannel DMA controller JPEG Codec accelerator LCD controller 1024 768 Ethernet Controller 10 100 1000 Mbps 10x Timers ADC 10 bit 8ch 3 8 97 Doc ID 16259 Rev 3 SPEAr600 Description 1 1 Main features Dual core ARM926EJ S 32 bit RISC CPU up to 333 MHz each with 16 Kbytes of instruction cache 16 Kbytes of data cache sets 32 bit for high performance 16 bit Thumb for efficient code density byte Java mode Jazelle for direct execution of Java code Tightly Coupled Memory AMBA bus interface 32 KByte on chip BootROM 8 KByte on chip SRAM Dynamic memory controller managing external DDR1 memory up to 166 MHz and external DDR2 memory up to 333 MHz Serial memory interface 8 16 bits NAND Flash controller Possible NAND Flash or serial NOR flash booting Multichannel DMA controller Color LCD Controller for STN TFT display panels Upto 1024 x 768 resolution 24 bpp true color Ethernet GMAC 10 100 1000 Mbps GMII MII PHY interface Two USB 2 0 host high full low speed with integrated PHY transceiver One USB 2 0 device high full
78. ntroduction part Section 2 4 Flexible static memory controller Updated the introduction Main features changed the sentence Provides independent chip select for each memory bank by Provides only one chip select for the first memory bank Table 3 Power supply pins swapped ball R1 from the Digital ground group to the Analog ground group Section 2 15 UARTs corrected the value of the baud rate to 3 Mbps Table 48 Timing characteristics for 8 bit NAND Flash configuration and Table 49 Timing characteristics for 16 bit NAND Flash configuration added three footnotes Table 3 Power supply pins swapped ball R1 from the Digital ground group to the Analog ground group Section 2 15 UARTs corrected the value of the baud rate in 3 Mbps Table 48 Timing characteristics for 8 bit NAND Flash configuration and Table 49 Timing characteristics for 16 bit NAND Flash configuration added three footnotes Created the new Section 2 24 Reconfigurable array subsystem connectivity RAS Section 3 3 Configuration modes and Section Table 16 Multiplexing scheme removed additional PL GPIOs PL signals and renamed GPIOs to EXPI 5 Section 6 6 3 GMII MII Receive timing specifications added Table 52 GMII MII RX timings Changed parameter to and added Ty Table 21 Recommended operating conditions Updated Table 62 SPEAr600 PBGA420 thermal resistance characteristics Doc ID 16
79. ond clock edge transition If the CPHA clock phase control parameter is high data is captured on the second clock edge transition after the slave selection and is changed on the first clock edge transition 6 8 1 SPI master mode timings CPHA 0 Table 57 Timing requirements for SPI mode on MISO pad CPHA 0 No parameters CPOL SPH SPI2 SPI3 unit Setup time MISO input 13 valid before SSP_SCLK 0 9 563 10 759 10 357 ns output rising edge Setup time MISO input 14 valid before SSP_SCLK 1 9 632 10 804 10 427 ns output falling edge Hold time MISO input 15 valid after SSP_SCLK 0 8 849 10 112 9 753 ns output rising edge Hold time MISO input 16 valid after SSP_SCLK 1 8 956 10 149 9 785 ns output falling edge Table 58 Timing requirements for SPI mode on MOSI pad CPHA 0 No parameters CPOL SPH SPI2 SPI3 unit Delay time SSP_SCLK 17 output falling edge to 0 0 675 1 141 1 638 ns MOSI output transition Delay time SSP_SCLK 18 output rising edge to 1 0 607 1 097 1 568 ns MOSI output transition ky Doc ID 16259 Rev 3 87 97 Timing characteristics SPEAr600 6 8 2 88 97 Table 58 Timing requirements for SPI mode on MOSI pad CPHA 0 continued No parameters CPOL SPH SPI2 SPI3 Delay time SSP_SS output falling edge to first unit edge to SSP_SS output rising edge 19 SSP_SCLK outpu
80. or bus and peripherals PLL1 source Clock 100 333 MHz for DDR memory interface PLL1 PLL2 source Clock 12 MHz 30 MHz and 48 MHz for USBs PLL3 source The above frequencies are the maximum allowed values All these clocks are generated by three PLLs PLL1 and PLL2 sources are fully programmable through dedicated registers The clock system consists of 2 main parts a multi clock generator block and two internal PLLs The multi clock generator block takes a reference signal which is usually delivered by the PLL generates all clocks for the IPs of SPEAr600 according to dedicated programmable registers Doc ID 16259 Rev 3 ky SPEAr600 Architecture overview 2 20 2 21 Each PLL uses an oscillator input of 30 MHz to generate a clock signal at a frequency corresponding to the highest of the group This is the reference signal used by the multi clock generator block to obtain all the other required clocks for the group Its main feature is electromagnetic interference reduction capability The user can set up the PLL in order to modulate the VCO with a triangular wave The resulting signal has a spectrum and power spread over a small programmable range of frequencies centered on FO the VCO frequency obtaining minimum electromagnetic emissions This method replaces all the other traditional methods of EMI reduction such as filtering ferrite beads chokes adding power layers and ground planes to PCB
81. orms 61 Figure 7 DDR2 write cycle path 62 Figure 8 DDR2 command 63 Figure 9 DDR2 command 63 Figure 10 AHB EXPI transfer waveforms 65 Figure 11 Pad delay disabled block diagram 66 Figure 12 signal timing waveforms 67 Figure 13 pad delay enabled block diagram 68 Figure 14 signal timing waveforms 69 Figure 15 CLCD waveform with 71 Figure 16 CLCD block diagram with CLCP 71 Figure 17 CLCD waveform with 72 Figure 18 CLCD block diagram with CLCP divided 72 Figure 19 output Dads dE Ud cadets 73 Figure 20 C input 5 Rr pM EN 73 Figure 21 Output signal waveforms for 2 74 Figure 22 delay
82. pported IP phones thin client computers printers TFT STN LCD controller resolution up to programmable logic controllers PC 1024 x 768 and colors up to 24 bpp docking stations Touchscreen support Medical lab diagnostics equipment Miscell f wireless access devices home appliances a eve alleen unctions residential control and security systems Integrated real time clock watchdog and digital picture frames and bar code system controller scanners readers 8 channel 10 bit ADC 1 Msps JPEG codec accelerator Table 1 Device summary 10 GPIO bidirectional signals with interrupt capability Order code Package Packing 10 independent 16 bit timers with programmable prescaler PBGA420 m 32 bit width External local bus EXPI interface SPEARGO0 2 1401085 esed Way 2 06 mm May 2012 Doc ID 16259 Rev 3 1 97 This is information on a product in full production www st com Contents SPEAr600 Contents 1 Description MEE 8 1 1 Main features 9 2 Architecture overview 11 2 1 Embedded memory units 13 2 2 DDR DDR2 memory controller 13 2 3 Serial memory interface 13 2 4 Flexible static memory controller 14 2 5 Multichannel DMA controller
83. r fmin d bus 1 32 ns 2 47 and min delay time of chip select 3 falling edge referred to SMI_CLK 1 56 falling edge Doc ID 16259 Rev 3 85 97 Timing characteristics SPEAr600 6 8 86 97 SSP timing characteristics The device SPEAr600 contains 3 SSP modules The Low Speed Connectivity Subsystem contains SSP1 and SSP2 the Application Subsystem contains SSP3 These 3 identical modules provide a programmable length shift register which allows serial communication with other SSP devices through a 3 or 4 wire interface SSP_SCLK SSP_MISO SSP_MOSI and SSP_SS The SSP module supports the following features e Master Slave mode operations Programmable clock bit rate and prescaler e Programmable choice of interface operation SPI Microwire or synchronous serial Programmable data frame size from 5 to 16 bits Separate transmit and receive FIFO 16 bits wide 8 locations deep The features of the Motorola SPI compatible interface are e Full duplex four wire synchronous transfers SSP SCLK 55 MISO 55 MOSI and SSP SS e Programmable Clock Polarity CPOL and Clock Phase CPHA The following Tables show the Timing Requirements of the SPI four wire synchronous transfer for the 3 SSP modules present in the Spear600 configured in master mode indicated in the tables as SPI1 SPI2 and SPI3 Both the Timings on MISO master input slave output pad
84. r Test Condition Min Max Unit VoL Low level output voltage loi X mA 1 0 3 V Vou High level output voltage X mA 1 Vpp 0 3 V 1 Forthe max current value X mA refer to Section 3 Pin description Table 25 Pull up and pull down characteristics Symbol Parameter Test Condition Min Max Unit Equivalent pull up resistance 29 67 Equivalent pull down _ Rpp Vi 29 103 KQ DDR2 pin characteristics Table 26 DC characteristics Symbol Parameter Test Condition Min Max Unit SSTL2 0 3 0 15 V Vit Low level input voltage 5 gt SSTL18 0 3 Vrer 0 125 V SSTL2 VpRer 0 1 5 Vppe2V5 0 3 V Vin High level input voltage SSTL18 1 25 VppE1V8 0 3 V Vhyst Input voltage hysteresis 200 mV Table 27 Driver characteristics Symbol Parameter Min Typ Max Unit Output impedance strong value 18 9 21 23 1 Q Ro Output impendance weak value 32 9 35 37 1 Q Doc ID 16259 Rev 3 57 97 Electrical characteristics SPEAr600 Table 28 die termination Symbol Parameter Min Typ Max Unit RT4 Termination value of resistance for on die 75 Q termination Termination value of resistance for on die 150 termination Table 29 Reference voltage Symbol Parameter Min Typ Max Unit 0 49 0 500 0 51 VREFIN Voltage applied to core pad V
85. racy so we put DLL element in the formulas One DLL element 15 ps in best case and 85 ps in worst case Doc ID 16259 Rev 63 97 Timing characteristics SPEAr600 Note 64 97 Therefore we have to add the value T to the clock path and the value T 2 to the command path The waveform shown in Figure 8 refers to the pad or memory side so the CLK edges are centered on the command valid window In this case we consider the minimum values for t4 and t5 in order to obtain the minimum command valid window We can consider t4 as the tegrup of the commands that can be defined as the time range where the commands are stable before the arrival of the clock To have a positive quantity the delay obtained by the commands maximum delay or last variation must be less than the one obtained by the clock minimum delay So delay MIN CMD delay MAX T 2 t2max 2 2 t5 can be expressed a similar way and be defined as the of the commands t5MIN CMD delay yin CLK delay max T 7 2 T 2 t2 min CLK delay is the combination of delays experienced by the CLK signal CMD delay is the combination of delays experienced by the command ctri address signal both until the capture performed by the memory Table 35 DDR2 command timings without pad delay Period T Frequency
86. rted modulation demodulation scheme for SIR and MIR and the 4PPM 4 Pulse Position Modulation modulation demodulation scheme for FIR Provides synchronization by means of a DPLL in FIR mode Easily adaptable to different bus systems with 32 bit register interface and FIFO with configurable FIFO size 125 audio block SPEAr600 contains three 125 interfaces providing the following features Main features Conversion of AHB protocol to 125 protocol and vice versa Supports 2 0 2 1 and 3 1 audio outputs 125 master mode 32 16L 16R and 64 bit 32L 32R of raw PCM data length supported MIC Line In 2 0 recording 125 master slave mode Stereo headphone out System controller The System Controller provides an interface for controlling the operation of the overall system Main features Power saving system mode control Crystal oscillator and PLL control Configuration of system response to interrupts Doc ID 16259 Rev 19 97 Architecture overview SPEAr600 2 18 1 2 19 20 97 Reset status capture and soft reset generation Watchdog module clock enable Power saving system mode control Using three mode control bits the system controller switch the SPEAr600 to any one of four different modes DOZE SLEEP SLOW and NORMAL SLEEP mode In this mode the system clocks HCLK and CLK are disabled and the System Controller clock SCLK is driven by a low speed oscillator nominally 32768 Hz When either
87. s metal shielding and so on This gives the customer appreciable cost savings In sleep mode the SPEAr600 runs with the PLL disabled so the available frequency is 30 MHz or a sub multiple 2 4 16 and 32 or 32 KHz PLL3 is used to generate the USB controller clocks and it is not configured through registers Vectored interrupt controller VIC Each ARM Subsystem of SPEAr600 offers Vectored Interrupted Controller VIC blocks providing a software interface to the interrupt system Acting as an interrupt controller the VIC determines the source that is requesting service and where its interrupt service routine ISR is loaded doing that in hardware In particular the VIC supplies the starting address or vector address of the ISR corresponding to the highest priority requesting interrupt source Main features of the VIC are listed below Support for 32 standard interrupt sources a total of 64 lines are available for each CPU from its two daisy chained VICs Generation of both Fast Interrupt request FIQ and Interrupt Request IRQ IRQ is used for general interrupts whereas FIQ is intended for fast low latency interrupt handling e Support for 16 vectored interrupts IRQ only Hardware interrupt priority FlQinterrupt has the highest priority followed by vectored IRQ interrupts from vector 0 to vector 15 then non vectored IRQ interrupts with the lowest priority e Interrupt masking interrupts requ
88. t rising ne or falling edge Delay time 55 SCLK 20 output rising or falling Figure 44 SPI master mode external timing 0 SSP_SS CPOL 0 yg y SSP_SCLK REND 16 le gt Input Output SSP_SCLK f CPOL 1 j SPI master mode timings CPHA 1 Table 59 Timing requirements for SPI mode on MISO pad CPHA 1 No parameters CPOL SPH SPI2 SPI3 Setup time MISO input 4 valid before SSP_SCLK 0 9 632 10 804 10 427 output falling edge unit ns Setup time MISO input 5 valid before SSP_SCLK 1 9 563 10 759 10 357 output rising edge ns Doc ID 16259 Rev 3 SPEAr600 Timing characteristics Table 59 Timing requirements for SPI mode on MISO pad CPHA 1 continued No parameters CPOL SPI1 SPI2 SPI3 unit Hold time MISO input 6 valid after SSP_SCLK 0 8 956 10 149 9 785 ns output falling edge Hold time MISO input 7 valid after SSP_SCLK 1 8 849 10 112 9 753 ns output rising edge Table 60 Timing requirements for SPI mode on MOSI pad CPHA 1 No parameters CPOL SPH SPI2 SPI3 unit Delay time SSP_SCLK 8 output rising edge to 0 0 607 1 097 1 568 ns MOSI output transition Delay time SSP_SCLK 9 output falling edge to 1 0 675 1 141 1 638 ns MOSI o
89. t an external 1 5 k2 pull down resistor to ball U4 4 DIGITAL REXT place an external 121 resistor between ball E11 and ball E126 3 2 Pin descriptions listed by functional block Table 2 System reset master clock RTC and configuration pins Group Signal name Ball Direction Function Pin type TTL Schmitt SYSTEM trigger input RESET MRESET C17 Input Main reset buffer 3 3 V tolerant PU Analog CONFIG DIGITAL_REXT E11 Ref Configuration 3 3 V capable See Note 4 24 97 Doc ID 16259 Rev 3 ky SPEAr600 Pin description 2 Table 2 System reset master clock RTC and configuration pins continued Group Signal name Ball Direction Function Pin type Master MCLK XI Y1 Input 30 MHz crystal Oscillator clock MCLK_XO 2 Output 30 MHz crystal O 2 5 V capable RTC XI A9 Input 32 kHz crystal I Oscillator a RTC_XO 9 Output 32 kHz crystal O 1 8 V capable Table 3 Power supply pins Group Signal name Ball Value 9 J10 11 12 13 14 9 K10 11 12 K13 K14 L9 110 L11 GND L12 L13 L14 M9 M10 M11 M12 M13 M14 N9 N10 N11 N12 N13 N14 P9 P10 P11 P12 P13 P14 DIGITAL M18 N18 P18 T5 V6 GROUND RTC_GNDE A10 DITH_VSS U5 DDR_MEM_PLL_VSS_DIG U17 DIGITAL_GNDBGCOMP E12 ADC_AGND V16 DDR_MEM_PLL_VSS_ANA V17 USB_VSSC2V5 4 USB_HOST1_VSSBS R1 USB HOST2 VSSBS N2 cU USB
90. te Main features e Time of day clock in 24 hour mode e Calendar e Alarm capability e Isolation mode allowing RTC to work even if power is not supplied to the rest of the device Reconfigurable array subsystem connectivity RAS The Reconfigurable Logic Array consists of an embedded macro where it is possible to implement a custom project by mapping up to 600k equivalent standard cells The user can design custom logic and special function using various features offered by the Reconfigurable Logic Array and by the SPEAr600 system listed here below 4 AHB bus master interfaces 5 AHB bus slave interfaces Dedicated interface with CPU1 to customize the Tightly Couple Memory Dedicated interface with CPU1 to customize the Coprocessor Dedicated interface with CPU2 to customize the Tightly Coupled Memory Interfaces towards a dedicated 130 Memory Array Subsystem provided of functional BIST driven by SoC via software and divided in the following ST memory cuts Ssingle port memory cuts 48 words x 128 bits A 4single port memory cuts 2048 words x 32 bits 8single port memory cuts 1024 words x 32 bits 16 single port memory cuts 512 words x 32 bits 8dual port memory cuts 512 words x 32 bits Doc ID 16259 Rev 3 ky SPEAr600 Architecture overview 2 25 Caution 4 dual port memory cuts 1024 words x 32 bits Clock system constituted by 5 clocks coming from the external balls 4 clocks
91. ter gt gt FPGA AHB slave SPEAr600 AHB slave lt lt FPGA AHB master AHB full The EXPI interface is based on two main groups of signals e AHBbidirectional signal bus driven alternatively from the SPEAr600 and FPGA side e Unidirectional signals continuously driven from both the SPEAr600 and FPGA sides Table 36 EXPI pad signal assignment lists the EXPI signal names Further details in these signals are given in the SPEAr600 user manual UM0510 Doc ID 16259 Rev 23 97 Pin description SPEAr600 3 Pin description The following tables describe the pinout of the SPEAr600 listed by functional block This description refers to the default configuration of SPEAr600 full features More details on the configuration of each pin are given in Table 16 Multiplexing scheme Table 2 System reset master clock RTC and configuration pins Table 3 Power supply pins Table 4 Debug pins Table 5 SMI 55 UAHT FIRDA and I2C pins Table 6 USB pins Table 7 Ethernet pins Table 8 GPIO pins Table 9 ADC pins Table 10 NAND Flash pins Table 11 DDR I F pins Table 12 LCD I F pins Table 13 LVDS I F pins Table 14 EXPI I2S pins Table 15 EXPI pins List of abbreviations PU Pull Up PD Pull Down 3 1 Required external components 1 DDR COMP 1 an external 121 k resistor between ball V7 and ball V8 2 DDR COMP 2V5 place an external 121 k resistor between ball V9 and ball V8 3 USB RREF connec
92. ut line to sense any over current condition detected by the external switch Both host controllers can perform high speed transfer simultaneously USB2 device controller Main features Supports 480 Mbps high speed mode HS for USB 2 0 as well as 12 Mbps full speed FS and the low speed LS modes for USB 1 1 Supports 16 physical endpoints which can be assigned to different interfaces and configurations to implement logical endpoints Integrated USB transceiver PHY Local 4 Kbyte FIFO shared by all endpoints DMA mode and slave only mode are supported In DMA mode the UDC supports descriptor based memory structures in application memory In both modes an AHB slave is provided by UDC AHB acting as programming interface to access to memory mapped control and status registers CSRs An AHB master for data transfer to system memory is provided supporting 8 16 and 32 bit wide data transactions on the AHB bus AUSB plug detect UPD which detects the connection of a cable Doc ID 16259 Rev 3 17 97 Architecture overview SPEAr600 2 13 2 14 2 15 18 97 Synchronous Serial Peripheral SSP The SPEAR600 has three Synchronous Serial Peripherals SSPs SPI Microwire or TI protocol Main features e Maximum speed of 40 Mbps e Programmable choice of interface protocol Motorola Microwire National Semiconductor synchronous serial e Programmable data frame size from 4 to 16
93. utput transition Delay time SSP_SS output falling edge to first 19 SSP_SCLK output rising Te e or falling edge Delay time 55 SCLK output rising or falling M edge to SSP SS output ns rising edge Figure 45 SPI master mode external timing CPHA 1 4 11 SSP_SS Output 4 10 CPOL 0 CPOL 1 6 7 444 0 SSP_MISO Input gt 8 9 Doc ID 16259 Rev 89 97 Package information SPEAr600 7 Package information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark SPEAr600 is ROHS 6 compliant 90 97 Doc ID 16259 Rev ky SPEAr600 Package information 7 1 Package mechanical data Table 61 PBGAA20 23 x 23 x 2 06 mm mechanical data mm inches Dim Min Typ Max Min Typ Max A L1 26 o0 A1 0 24 0 0094 A2 0 56 0 0220 A3 0 97 0 0382 4 1 53 0 0602 0 40 0 50 0 60 0 0157 0 0197 0 0236 22 80 23 00 23 20 0 8976 0 9055 0 9134 D1 21 00 0 8268 D2 20 00 0 7874 E 22 80 23 00 23 20 0 8976 0 9055 0 9134 E1 21 00 0 8268 E2 20 00 0 7874 e 1 00 0 0394 F 1 00 0 0394 ddd 0 20 0 0079 eee 0 25 0 0098 fff 0 10 0 0039
94. utput buffer NF CLE G21 Command latch 3 3 V capable enable 4 mA WP J18 Write protect TTL input buffer NF RB H22 Input Read b B 3 3 V tolerant PU 1 When the pin is not driven the output voltage is 2 5 V On the core side logic 1 state is guaranteed Doc ID 16259 Rev 3 SPEAr600 Pin description 3 Table 11 DDR I F pins Group Signal name Ball Direction Function Pin type DDR ADD O DDR_ADD_1 AB4 DDR_ADD_2 AA4 DDR_ADD_3 Y4 DDR_ADD_4 W4 DDR_ADD_5 W5 DDR_ADD_6 Y5 DDR_ADD_7 AAS Output DDR_ADD_8 AB5 DDR_ADD_9 AB6 DDR_ADD_10 AA6 SSTL_2 DDR_ADD_11 Y6 SSTTL_18 DDR_ADD_12 W6 DDR_ADD_13 W7 DDR_ADD_14 Y7 DDR_BA_O Y9 DDR DDR BA 1 Output VF DDR BA 2 W10 DDR RAS AB7 Row strobe DDR CAS Column strobe DDR_WE 8 en Write enable DDR_CLKEN AB8 Clock enable DDR_CLK_P 9 Differential Differential Output DDR_CLK_N Clock DDR CS 0 Y8 Chip select DDR CS 1 W8 nee Chip select DDR ODT 0 2 On die Output Termination DDR_ODT_1 AB1 Enable lines SSTL 2 DDR DATA 0 AB11 SSTTL 18 DDR DATA 1 AA10 DDR DATA 2 AB10 O 2 DDR_DATA_3 Y10 DDR_DATA_4 Y11 Doc ID 16259 Rev 3 33 97 Pin description SPEAr600 Table 11 DDR I F pins continued
95. ven for an output load of 5 pF on the clock and 10 pF on the other pads The operating conditions in worst case V 0 90 V 125 and in best case 1 10 V 40 C 6 7 1 SMI timing specifications Figure 41 SMI waveforms SMI 44 gt i Thold SMI_DATAIN A Tsetup gt lt gt Tf Tr SMI DATAOUT Tmin 9 lt gt Tmax SMI 50 ree lt lt 4 lt gt Figure 42 Block diagram of the SMI pins m DATAIN SMI CLK HCLK E SMI DATAOUT SMI CS n 56 0 1 3 lt A SMI DATAOUT e SMI CS n 0 1 3 Table 54 SMI timings in default configuration Signal Parameter Value Description 50 ns SMI period normal mode t 20 ns SMI period fast read mode SMI_CLK 0 8 5 Transition times 0 84 5 SETUP 4 5 ns Max setup time and min hold time of SMI_DATAIN data in referred to SMI_CLK rising tHoLD 0 08 5 84 97 Doc ID 16259 Rev 3 ky SPEAr600 Timing characteristics 4 Table 54 SMI timings in default configuration continued Signal Parameter Value Description eua tmax 0 65 ns Max and min dela
96. y time of data out E tmin 0 41 ns referred to SMI_CLK falling edge trmax 0 59 ns Max and min delay time of chip select 0 rising edge referred to SMI_CLK trmin 0 52 ns falling edge SMI CS 0 0 46 5 and min delay time of chip select 0 falling edge referred to SMI_CLK timin 052 ns falling edge trmax 0 67 ns Max and min delay time of chip select 0 rising edge referred to SMI_CLK trmin 0 27 ns falling edge SMI_CS_1 0 54 5 and min delay time of chip select 1 falling edge referred to SMI_CLK timin 0 3 ns falling edge Table 55 SMI Timings of SMI_CS_3 in non default configurations Signal Parameter Value Description trmax 2 64 ns Max and min delay time of chip select 3 rising edge referred to SMI_CLK NF_WP SMI_CS_3 in lrmin 1 32 ns falling edge Disable nand flash timax 2 47 ns Max and min delay time of chip select 3 falling edge referred to SMI CLK timin 0 31nS falling edge trmax 0 71ns Max and min delay time of chip select 3 rising edge referred to SMI CLK CLD 14 SMI CS 3 in 0 08 5 falling edge Disable LCD ctr timax 0 52 ns Max and min delay time of chip select falling edge referred to CLK timin 0 36 ns falling edge timax 3 99 ns Max and min delay time of chip select 3 rising edge referred to SMI_CLK trmin 0 6 ns falling edge SSNS Max and min delay time of chip select EM GMI Us chin timi 1 56 ns 3 falling edge referred to SMI_CLK Disable ct

Download Pdf Manuals

Related Search

Related Contents

MXSP-1200  使用說明  Nº 21. 2010. julio-agosto-septiembre  SmartMetals 002.2470-10 project mount  

Copyright © All rights reserved. Failed to retrieve file