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DE2 Development and Education Board User Manual

1. dunare nenen anna 99 6 3 PC PCI EXPRESS SYSTEM 103 6 4 PCIE FUNDAMENTAL COMMUNICATION e eiie eise s 112 6 5 IMAGE PROCESSING 1 101020 117 CHAPTER 7 APPENDIX A HSMC PIN ASSIGNMENT eee eee eene nee tenant tasse 123 ADDITIONAL 1 2 Terasic TR4 User Manual www terasic com Chapter 1 Overview This chapter provides an overview of the TR4 Development Board and details the components and features of the board 1 1 General Description The TR4 Development Board provides the ideal hardware platform for system designs that demand high performance serial connectivity and advanced memory interfacing Developed specifically to address the rapidly evolving reguirements in many end markets for greater bandwidth improved jitter performance and lower power consumption the TR4 is powered by the Stratix IV GX device and supported by industry standard peripherals connectors and interfaces that offer a rich set features that is suitable for wide range of compute intensive applications The advantages of the Stratix GX FPGA platform with integrated transceivers have allowed the TR4 to be fully compliant with version 2 0
2. Figure 6 2 Read Transaction Waveform of the PCle Basic I O Interface 14 12 1 2 14 5 1 oCORE V WW wx V XX wW X Y X 1 1 1 1 1 1 1 1 5 WR WRITE 3f X Figure 6 3 Write Transaction Waveform of the Basic I O Interface B PCI Express Transaction To support greater bandwidth and to improve latency Terasic PCIe IP provides a high speed DMA channel with two modes of interfaces including memory mapping and FIFO link The oFIFO MEM SEL signal determines the DMA channel used memory mapping or FIFO link which is enabled with the assertion of a low and high signal respectively The address bus of DMA indicates the FIFO ID which is defined by users from the PC software API Most interfaces experience read latency during the event data is read and processed to the output To mitigate the overall effects of read latency minimum delay and timing efficiency is required to enhance the performance of the high speed DMA transfer As oDMARD READ signal is asserted the read data valid signal oDMARD RDVALID is inserted high to indicate the data on the iDMARD DATA data bus is valid to be read after two clock cycles 100 1 Terasic TR4 User Manual www terasic com www terasic com Table 6 2 DMA Channel Signals of Terasic PCIe IP Name Type Polar
3. TR4 User Manual www terasic com www terasic com alt dache flush all to make sure all data has been written Finally it reads data from DDR3 for data verification The program will show progress in JTAG Terminal when writing reading data to from the DDR3 When the verification process is completed the result is displayed in the JTAG Terminal B Altera DDR3 SDRAM Controller with UniPHY To use the Altera DDR3 controller users need to perform three major steps 1 Create correct pin assignments for the DDR3 2 Set up correct parameters in DDR3 controller dialog 3 Execute TCL files generated by DDR3 IP under your Quartus II project The following section describes some of the important issues in support of the DDR3 controller configuration On the PHY Setting tab in order to achieve 533 0 MHz clock frequency a reference clock frequency of 50 MHz should be used If a different DDR3 SODIMM is used the memory parameters should be modified according to the datasheet of the DDR3 SODIMM B Design Tools e Quartus II 11 1 Nios IL IDE 11 1 B Demonstration Source Code e Project directory TRA DDR3 UniPHY QSYS e Bit stream used TRA DDR3 UniPHY 10 QSYS sof Nios II Workspace TRA DDR3 UniPHY 16 OSYS Software B Demonstration Batch File Demo Batch File Folder DDR3 UniPHY OSYNdemo batch The demo batch file includes following files e Batch File TRA DDR3 UniPHY QSYS bat TR4 DDR3 U
4. Programmable PLL HSMA REFCLK Pnehange REFCLK Pnehange GXBCLK nchenge HSMC Expansion HSMC D HSMC A Transceiver x 8 None None v HSMC E Transceiver 8 HSMC B None None Prefix Name SSS Prefix Name O HSMC F HSMC C GPIO HSMC None None M Defaut Setting Load Setting Save Setting Generate Figure 4 2 TR4 System Builder Window B Select Board Type and Input Project Name Select the target board type and input project name as show in Figure 4 3 e Board Type Select the appropriate FPGA device according to the TR4 board which includes the EPASGX230 and EP4SGX530 devices e Project Name Specify the project name as it is automatically assigned to the name of the 72 Terasic TR4 User Manual www terasic com www terasic com ATERA top level design entity Terasic IR4 Y1 0 0 ATERA System Configuration university Board Type 230 Project Name Switch x 4 v Button x 4 SSRAM 2MB v Temperature Flash 64MB Fan Control SMA O DDR3 SODIMM 0 PCle 1 Programmable PLL 0 0 EJ FSI FSI FSI S Programmable PLL HSMA REFCLK nchange HSME_REFCLK Unehange PGM_GXBCLK Unehange HSMC Expansion HSMC D HSMC A Transceiver x 8 None None Prefix Name Prefix Name
5. PCIe Fundamental Demo Y1 0 Select FPGA Board vip 1172h DID E001h Refresh Register Read Write Button Register 0x04 LED Register 0x04 Custom Registers BUTTON 0 LEDO Register Address LEDI BUTTON 1 Register Value BUTTON 2 00 BUTTON 3 LEDS Read Read Status Set LED Write Memory Mapped Write and Read FIFO Write and Read ter www terasic com PCIE Board Connected Figure 6 13 PCle Fundamental Demo GUI Make sure Select FPGA Board appears as VID 1172 DID E001 Press BUTTONO BUTTON3 on the TR4 and click Read Status in the application software Check Uncheck the LEDO 3 in this application software and click Set LED The LEDs on the TR4 should light and unlight accordingly Click Memory Mapped Write and Read to test the memory mapped DMA A report dialog will appear when the DMA process is completed Click FIFO Write and Read to test the FIFO DMA A report dialog box will appear when the DMA process is completed The Custom Registers Group is used to test custom design registers on the FPGA side Users can use this function to verify custom register design B Demonstration Setup e Quartus II 11 1 B Demonstration Source Code Location e Quartus Project TRA 0 Fundamental Borland C Project PCIeO Fundamental 114 Terasic TR4 User Manual www terasic com www teras
6. In the design basic I O is used to read or write the buttons and LEDs on the TR4 High speed data transfer is performed by DMA Both Memory Mapped and FIFO memory types are demonstrated in the reference design The demonstration also makes use of the associated PCIe adapter card B Demonstration Files Location The demo file is located in the folder 0 FundamentaNdemo batch The folder includes following files PC Application Software PCIe Fundamental Demo exe FPGA Configuration File tr4 0 fundamental sof e PCIe Library TERASIC PCIE DLL 112 TR4 User Manual www terasic com www terasic com ANU S RYA Demo Batch File 174 0 fundamental bat B Demonstration Setup e Make sure and PC are both powered off e Plug the PCIe adapter card into PCIe slot on the PC motherboard e Use the PCIe cable to connect to the TRA PCIEO connector and PCIe adapter card as shown in Figure 6 12 Figure 6 12 PCle Fundamental Communication Demonstration Setup e Power on your PC e After the Windows OS desktop shows up Download the tr4 pcie0 fundamental sof into the TR4 using the Quartus II Programmer e Restart Windows e Install PCIe driver if necessary The driver is located in the folder PCIe SDK Driver e Launch the demo program PCIe Fundamental Demo exe shown in Figure 6 13 113 Terasic TR4 User Manual www terasic com www terasic com Terasic
7. 25 AE26 108 HSMD 9 LVDS RX 9 or CMOS LVDS or 2 5 V 0 109 HSMD TX n9 LVDS TX bit 9n or CMOS LVDS or 2 5 V AF26 110 HSMD RX n9 LVDS RX bit 9n or CMOS I O LVDS 2 5 113 HSMD TX p10 LVDS bit 10 CMOS LVDS or 2 5 V V29 114 HSMD RX p10 LVDS RX bit 10 CMOS I O LVDS or 2 5 V AP32 115 HSMD TX n10 LVDS TX bit 10n or CMOS I O LVDS or 2 5 V V30 116 HSMD RX n10 LVDS bit 10n or CMOS I OLVDS or 2 5 V 2 119 HSMD TX LVDS TX bit 11 CMOS LVDS or 2 5 V W28 120 HSMD LVDS bit 11 CMOS I O LVDS or 2 5 V V34 121 HSMD TX n11 LVDS TX bit 11n or CMOS I O LVDS or 2 5 V V28 122 HSMD_RX_n11 LVDS RX bit 11n or CMOS OLVDS or 2 5 V 1035 125 HSMD TX p12 LVDS TX bit 12 CMOS LVDS or2 5 V 30 126 HSMD RX p12 LVDS RX bit 12 CMOS I O LVDS or 2 5 V 031 127 HSMD TX n12 LVDS TX bit 12n or CMOS I O LVDS 2 5 V T31 128 HSMD 12 LVDS RX bit 12n or CMOS I OLVDS or 2 5 V V31 131 HSMD TX p13 LVDS TX bit 13 CMOS LVDS or 2 5 V R32 132 HSMD LVDS bit 13 CMOS LVDS or 2 5 V N33 133 HSMD TX n13 LVDS TX bit 13n or CMOS I O LVDS or 2 5 V R33 134 HSMD RX n13 LVDS RX bit 13n CMOS l OLVDS or 2 5 V N34 137 HSMD TX p14 LVDS TX bit 14 CMOS LVDS or2 5 V P31 138 HSMD 14 LVDS RX bit 14 CMOS LVDS or 2 5 V 33 139 HSMD TX n14 LVDS TX bit 14n or CMOS V O LVDS or 2 5 V 2 140
8. PINALI7 FSM Dia Databus PINAKI6 FSM 15 PIN AJ6 FLASH Clock 5 FLASH RESET Rest 30 AVIG FSM OEn Output Enable 30VPCKX 6 FSM WE n WriteEnable 30 VPCKX 0 FLASH RDY BSY n Ready 15V FLASH WP n Write Protect 15 PINA2 51 Terasic TR4 User Manual www terasic com www terasic com 2 11 SSRAM Memory The Synchronous Static Random Access Memory SSRAM device featured on the TR4 development board is part of the shared Flash SSRAM Max II FSM bus which connects to Flash memory SSRAM and the MAX II CPLD EEPM2210 System Controller This device is a 2MB synchronously pipelined and high speed low power synchronous static RAM designed to provide burstable high performance memory for communication and networking applications Table 2 19 lists the SSRAM pin assignments and signal names relative to the Stratix IV GX device in terms of I O setting Table 2 19 SSRAM Memory Pin Assignments Schematic Signal Names and Functions Schematic Signal 22 Stratix IV GX Description VO Standard Name Pin Number FSM A2 Address bus A0 3 0 V PCI X PIN F34 FSM A3 Address bus A1 3 0 V PCI X PIN D35 FSM A4 Address bus A2 3 0 V PCI X PIN D34 FSM A5 Address bus A3 3 0 V PCI X PIN E34 FSM A6 Address bus A4 3 0 V PCI X PIN C35 FSM A7 Address bus A5 3 0 V
9. LVDS 2 5 V LVDS RX bit 13n orLVDS or 2 5 V 139 AT18 AW18 AU18 AN19 AU17 AM19 AV17 AJ22 AM22 AK24 AN22 AE23 AN18 AH22 AP18 AF23 AK23 AE22 AL23 AG21 AH23 AE21 AJ23 www terasic com 10 LVDS TX bit 14 o AA Toar CNN oma ban 2 NE LVDS TX bit 16n o HSMF TX n16 COSI LVDS or 2 5 V LVDS RX bit 16n o merus mese ae LVDS TX or CMOS I O HSMF_OUT_p2 or differential clockLVDS or 2 5 V A input output LVDS RX or CMOS 10 HSMF CLKIN p2 or differential clockLVDS or 2 5 V A input LVDS TX or CMOS I O s differential clockLVDS or 2 5 AJ20 input output LVDS RX or CMOS I O HSMF_CLKIN_n2 or differential clockLVDS or 2 5 V input 140 Terasic TR4 User Manual www terasic com www terasic com Additional Information Getting Help Here is the contact information where you can get help if you encounter problems e Terasic Technologies No 356 Sec 1 Fusing E Rd Jhubei City HsinChu County Taiwan 302 Email support terasic com Web www terasic com Revision History Date Version Changes 2011 12 29 First publication TR4 User Manual www terasic com www terasic com
10. 2 5 V 27 74 HSMD_RX_n4 LVDS bit 4n or CMOS I O LVDS or 2 5 V AP34 77 HSMD_TX_p5 LVDS TX bit 5 or CMOS I O LVDS or 2 5 V AG29 78 HSMD_RX_p5 LVDS bit 5 or CMOS I O LVDS 2 5 34 Terasic TR4 User Manual www terasic com 131 www terasic com 79 HSMD TX n5 LVDS TX bit 5n CMOS LVDS or2 5 V AH29 80 HSMD RX n5 LVDS RX bit 5n or CMOS I O LVDS or2 5 V AR34 83 HSMD TX p6 LVDS TX bit 6 or CMOS I O 1 25 AG28 84 HSMD RX p6 LVDS RX bit CMOS LVDSor2 5 V 5 85 HSMD TX n6 LVDS TX bit 6n or CMOS LVDS or2 5 V AH28 86 HSMD RX n6 LVDS RX bit 6n CMOS I O LVDS or2 5 V AR35 89 HSMD TX p7 LVDS TX bit7or CMOS I O LVDS or2 5 V 27 90 HSMD RX p7 LVDS RX bit7orCMOS O LVDSor2 5 V 2 91 HSMD TX n7 LVDS TX bit or CMOS LVDS or2 5 V AE27 92 HSMD RX n7 LVDS RX bit 7n CMOS I O LVDS or2 5 V AP33 95 HSMD CLKOUT p1 LVDS or CMOS LVDS or 2 5 V 32 96 HSMD CLKIN LVDS RX or CMOS VO orev w34 differential clock input 97 HSMD CLKOUT n1 LVDS RX or CMOS LVDS or 2 5 V 98 HSMD CLKIN n1 LVDS RX CMOS VO o was differential clock input 101 HSMD TX p8 LVDS TX bit 8 CMOS I O LVDS or2 5 V AC26 102 HSMD RX p8 LVDS RX 8 CMOS LVDSor2 5 V 31 103 HSMD TX n8 LVDS TX bit 8n or CMOS LVDS or2 5 V AD26 104 HSMD RX n8 LVDS RX bit 8n or CMOS I O LVDS or2 5 V AN31 107 HSMD TX p9 LVDS TX bit9or CMOS I O 1
11. HSMC E 8 HSMC B None None Prefix Name Prefix Name a HSMC F HSMC C GPIO HSMC None None Default Setting Load Setting Save Setting Generate Figure 4 3 TR4 Board Type and Project Name B System Configuration Under System Configuration users are given the flexibility of enabling their choice of components on the TR4 as shown in Figure 4 4 Each component of the TR4 is listed where users can enable or disable a component according to their design by simply marking a check or removing the check in the field provided If the component is enabled the TR4 System Builder will automatically generate the associated pin assignments including the pin name pin location pin direction and I O standards Note The pin assignments for some components for e g DDR3 require associated controller codes in the Quartus II project otherwise Quartus II will result in compilation errors Therefore do not select them if they are not necessary in your design 73 Terasic TR4 User Manual www terasic com www terasic com 4 1 0 0 MOTERA UNIVERSITY PROGRAM WWW erasic com HSMC Expansion HSMC D None Prefix Name HSMC E Transceiver 8 None Prefix Name HSMC F None Prefix Name System Configuration Board TR4 230 Project Name 4 CLOCK Switch x 4
12. SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I Clock p0 for DDR3 Clock p1 for DDR3 Clock n0 for DDR3 Clock n1 for DDR3 Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I DDR3 Chip Select 0 DDR3 Chip Select 1 DDR3 Data Mask 0 DDR3 Data Mask 1 DDR3 Data Mask 21 DDR3 Data Mask 3 DDR3 Data Mask 4 DDR3 Data Mask 5 DDR3 Data Mask 6 DDR3 Data Mask 7 DDR3 Data 0 DDR3 Data 1 DDR3 Data 2 DDR3 Data 3 DDR3 Data 4 DDR3 Data 5 DDR3 Data 6 DDR3 Data 7 Terasic TR4 User Manual www terasic com SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I 39 PIN N25 PIN C24 PIN N21 PIN M25 PIN K26 PIN F16 PIN R20 PIN B26 PIN A29 PIN R24 PIN L26 PIN P25 PIN M16 PIN K27 PIN L25 J27 PIN K28 PIN D23 PIN G28 PIN G16 PIN N16 PIN P23 PIN B29 PIN H28 PIN E17 PIN C26 PIN E23 PIN G15 PIN F15 PIN C16 PIN B16 PIN G17 PIN A16 PIN D16 PIN E16 www terasic com mem dq 8 mem 4419 mem dq 10 mem dq 11 dq 12 mem dq 13 mem dq 14 mem dq 15 mem dq 16 mem dq 17 mem dq 18 mem dq 1
13. 87 Terasic TR4 User Manual www terasic com www terasic com 2048 1024 1024 2048 3072 4096 5120 6144 ext Ti a ext ctrtu ext 2 set wr 3h ext pr 4h Jati ext pli r amp p E ekpl sera 2 2h gt sera 3 3h x extplcttu ext setrd 8 4h ext ext ready gt 5 ext _ext pl 2 set wr ext ext ctrilclk3 set wr je eec B Desi ext ext ctricik1 set rd ext ext ctrilcik2 set rd AN ext ctrku ext pil ctrilconf rd ET 1 R gt El ext ext ctrijcik3 set rd ex ext PI etrilconf ready lr Figure 5 4 Read Timing Waveform gn Tools Ouartus II 11 1 B Demonstration Source Code The demo Project directory TR4 EXT PLL Bit stream used TRA EXT PLL sof Demonstration Batch File Demo Batch File Folder TRA EXT
14. AJ35 137 HSMC TX 14 LVDS TX bit 14 CMOS LVDS or2 5 V AL25 138 HSMC 14 LVDS RX bit 14 CMOS I O LVDS or2 5 V AH34 139 HSMC TX n14 LVDS TX bit 14n or CMOS VOLVDS 2 5 26 140 HSMC_RX_n14 LVDS RX bit 14n or CMOS l OLVDS or 2 5 V AH35 143 HSMC TX p15 LVDS TX bit 15 CMOS LVDS or2 5 V AU29 144 HSMC 15 LVDS RX bit 15 CMOS I O LVDS or2 5 V AH32 145 HSMC TX n15 LVDS TX bit 15n CMOS VOLVDS 2 5 V AT29 146 HSMC RX n15 LVDS RX bit 15n or CMOS l OLVDS 2 5 V AH33 149 HSMC TX p16 LVDS TX bit 16 CMOS I O LVDS 2 5 AP27 150 HSMC RX p16 LVDS RX bit 16 CMOS I O LVDS or2 5 V AC31 151 HSMC TX n16 LVDS TX bit 16n or CMOS l OLVDS 2 5 AN27 130 TR4 User Manual www terasic com www terasic com 152 HSMC n16 LVDS RX bit 16n or CMOS l OLVDS or 2 5 V 2 LVDS TX or CMOS I O or 25 155 HSMC OUT 2 differential clockLVDS or 2 5 V input output 156 HSMC CLKIN p2 LVDS RX or CMOS VO Ol differential clock input LVDS TX or CMOS 1 or 157 HSMC OUT n2 differential clockLVDS or 2 5 V AD25 input output 158 HSMC CLKIN n2 LVDS RX or CMOS 10 25 differential clock input Table 7 4 HSMC Port D Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description VO Standard J7 Pin Number 39 HSMD OUTO CMOS I O LVDS or 2 5 V P19 40 HSMD CLKINO Dedicat
15. Random Access 10000000 10000 00000000 ETE 0000 rDATA 0000 Rea Sequential Write 20000000 Fie Length y HSMC Temperature Information T Sequential Read Address 100000000 Length n DISCONNECT t 63 Terasic TR4 User Manual www terasic com E ee e a EEEE e Memory Type DDR3 SODIMM 20000000h WORDS 1 GB Random Access TET H asd 00000100 AES rDATA 0000 eS 9 Sequential Write Memory ET 00000000 File Length am Na Temperature Information amp Seguential Read 77 00000000 Length 221 Entire Memory DISCONNECT Figure 3 8 Writing the Hexadecimal Value 7EFF to Location 0x100 3 5 Temperature Monitor Choose the Temperature tab to reach the window shown in Figure 3 9 This function is designed to control temperature sensor through the Control Panel The temperatures of Stratix IV GX and TR4 board are shown on the right hand side of the Control Panel When the temperature of Stratix IV GX exceeds the maximum setting of Over Temperature or Alert a warning message will be shown on the Control Panel Click Read button to get current settings for Over temperature and Alert Users can enter the maximum and mini
16. TDO TDI s TDO TDI TDO TDI HSMA HSMB HOME Bottom Bottom Figure 2 17 JTAG Chain for a Daughter Card is used Connected to HSMC Port D of the TDI TDO Daughter When JP7 Header Connected HSMC Included In JTAG Chain TR4 Board 100 ii HSMD Top Lise d Ibi EMI Pre HSMC Bottom JP7 Header ATERA Bottom E E i E TDO TDI 4 TDO TDI bd OO TDI bm OO TDI fgg TOO TDI 4 TDO TDI HSME HSMA HSMA HSMB HSMB HSMF Figure 2 18 JTAG chain for a Daughter Card JTAG not used Connected to HSMC Port D of the TR4 32 Terasic TR4 User Manual www terasic com www terasic com ANU S RYA B Multi FPGA High Capacity Platforms through HSMC The offers a selection of two Stratix IV GX devices EP4SGX230 EPSGX530 which offer logic elements LEs up to 228 000 and 531 200 respectively to provide the flexibility for users to select a suitable device In situations where users design exceeds the capacity of the FPGA the HSMC interface can be used to connect to other FPGA system boards creating a multi FPGA scalable system Users can stack two TR4s as shown in Figure 2 19 Another option is to use a Samtec high speed cable to connect two TR4 boards See Figure 2 20 to expand your system For more information on how to use multi TR4 systems p
17. DVI TX RX Prefix Name HSMC E Transceiver x 8 XTS Transceiver to SMA Prefix Name System Configuration Board Type TR4 230 Project Name M CLOCK Switch x 4 MLEDx 4 Button x 4 v SSRAM 2MB Temperature Flash 64MB Fan Control OSMA O DDR3 SODIMM O PCle 0 L1 PCIe 1 Programmable PLL Programmable PLL HSMA REFCLK Unchange HSME REFCLK Unc PGM GXBCLK HSMC A Transceiver x 8 IDCC High SpeedADCIDAC Ep Prefix Name HSMC B HDMI RX Prefix Name HSMC F HSMC C GPIO HSMC LTC2 8 LCD Touch Camera NET 10 100 1000 Eth Prefix Name Prefix Name Default Setting Load Setting Save Setting Figure 4 6 HSMC Expansion Group The Prefix Name is an optional feature that denotes the pin name of the daughter card assigned in your design Users may leave this field empty Note If the same HSMC daughter card is selected in both HSMC A and HSMC B expansion a prefix name is required to avoid pin name duplication as shown in Figure 4 7 otherwise System Builder will prompt an error message 76 Terasic TR4 User Manual www terasic com www terasic com Terasic IR4 Y1 0 0 ANA UNIVERSITY PROGRAM ww terasic com System Configuration Board Type 230 Project Name TR4 lv CLOCK MLEDx 4 lvl SSRAM 2MB
18. Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Output Enable Byte Write Enable Address Status Controller Address Status Processor Synchronous Burst Address Advance Synchronous Byte Write Controls Synchronous Byte Write Controls Synchronous Byte Write Controls Synchronous Byte Write Controls Synchronous Chip Enable Synchronous Clock Burst Sequence Selection Synchronous Global Write Enable Synchronous Chip Enable Synchronous Chip Enable Power Sleep Mode 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 3 0 V PCI X 2 12 Temperature Sensor and Fan The TR4 is equipped with a temperature sensor MAX1619 which provides temperature sensing and 53 Terasic TR4 User Manual www terasic com 29 PIN N29 PIN P29 PIN T27 PIN AM17 PIN AL17 PIN AK16 PIN AJ16 PIN AK17 PIN T28 PIN R27 PIN R28 PIN R29 PIN N30 N28 PIN M28 PIN H31 PIN G3
19. FPGA Development Kit User Manual LECET NIERA www terasic com Copyright 2003 2012 Terasic Technologies Inc All Rights Reserved CONTENIS prz CHAPTER 1 012i duque M 3 1 GENERAL DESCRIPTION E 3 1 2 EUR 4 1 3 BOARD OVERVIEW D ea Ne bea Bae memadai 5 1 4 BLOCK DIAGRAM Rn nana 6 CHAPTER 2 USING THE TR4 BOARD 11 2 l CONFIGURATION OPTIONS sekian an Nan ea 11 2 2 SETUP BLEMENTS hmm massa ena ema ikan 18 2 3 STATUS BIEEMENTS sess dese aes ana nan atu benni Ga 19 2 4 GENERAL USER INPUT OUTPUT 20 2 5 HIGH SPEED MEZZANINE CARDS ane aan enam 22 2 6 GPIO EXPANSION HEADERS makna 34 2 FDDR5SOQ DIMNI 38 2 8 CLOCK CIRCUITRY 52525222 DD DE 42 2 9 E E D E E T 45 210 FLASH MEMORY master ester ba banana an nd sean banana 49 2 11 SSRAM 52 2 12 TEMPERATURE SENSOR AND FAN 53 2 13 POWER M M OQ 54 p delude 54 CHAPTER 3 CONTROL PANEL 55 CONTROL PANEL SETUP simak aan EA aah 55 3
20. ctricont wr dt a ext ctrtu ext pl set wr 2h amp p et ext pil set wr qo I 3h 9 ext set wr 111 4h ext plcticont yd a Ta ext pll ext ctrijcik1 set rd lu ru Oh amp p ext set rd Oh amp ext ext pil ctrllcik3 set rd AN Oh ext pil ready gs as tame 3j ext T ext set wr 49 ext ext ctrilcik2 set wr F ext pll ext ctrilcik3 set wr 2 Hit ext ctricont ra Loo 4 amp p E ext ext set rd x pue _ F ext pil ext ctrilcik2 set rd 49 9 ctrbu ext ctrjcik3 set rd e ext ext ctrilconf ready Figure 5 3 Write Timing Waveform Read Timing Waveform As the trigger source defined by Terasic is pressed the conf signal is on the rising edge the user settings are read back immediately once the conf ready signal is on the falling edge as shown in Figure 5 4 As the transfer is complete the conf ready returns back to original state at high level
21. oFIFO MEM SEL Figure 6 7 Write Transaction Waveform of the PCle DMA Channel in FIFO link Mode 6 3 PC PCI Express System Design The TR4 CD contains a PC Windows based SDK to allow users to develop their software application SDK demonstrations tr4_ lt Stratix device PCIe SDK includes e PCI Express Driver e PCI Express Library The kernel mode driver requires users to modify the PCIe vendor ID VID and device ID DID in the driver INF file to match the design in the FPGA where Windows searches for the associated driver Note The kernel mode driver currently only supports Windows XP 32 bit Edition provided by Jungo Inc which can be found at www jungo com The PCI Express Library is implemented as a single DLL called TERASIC PCIE DLL With the DLL exported to the software API users can easily communicate with the FPGA The library provides the following functions Device Scanning on PCIe Bus Basic Data Read and Write Data Read and Write DMA For high performance data transmission DMA is required as the read and write operations are specified under the hardware design on the FPGA 103 TR4 User Manual www terasic com www terasic com ANU S RYA B PCI Express Software Stack Figure 6 8 shows the software stack for the PCI Express application software The PCI Express driver is incorporated in the DLL library called TERASIC PCIE DLL Users can develop their applic
22. 0 first matched board To download the raw image from PC to FPGA memory the function is called m hPCIE DmaWrite DEMO IMAGE DATA ADDR plImage nImagesSize where pImage is a pointer of the image raw data and the nImageSize specifies the image size In this reference design nImageSize 320x240x3 bytes To start the image process the function is called m hPCIE Write32 DEMO PCIE USER BAR DEMO IMAGE REG ADDR 1 The image process is started whenever the register is written with any value To check whether the image process is finished the control register is monitored by calling the function m hPCIE Read32 DEMO PCIE USER BAR DEMO IMAGE REG ADDR amp dwStatus When the image process is finished the value of dwStatus becomes zero 121 TR4 User Manual www terasic com www terasic com ANOTE RYA To update the processed image from FPGA memory to PC the function is called m hPCIE DmaRead DEMO IMAGE DATA ADDR pImage nImageSize 122 Terasic TR4 User Manual www terasic com www terasic com Chapter 7 Appendix A HSMC Pin Assignment Table 7 1 HSMC Port A Pin Assignments Schematic Signal Names and Functions Terasic TR4 User Manual 123 www terasic com Board Reference Schematic Signal Stratix IV GX Description VO Standard J6 Name Pin Number 1 HSMA GXB TX p7 Transceiver TX bit 7 1 4 V PCML B4 2 GX
23. 150 151 152 155 156 157 CLKOUT n1 LVDS TX or CMOS I O HSMB HSMB TX p8 HSMB RX p8 HSMB TX n8 HSMB RX n8 HSMB TX p9 HSMB RX p9 HSMB TX n9 HSMB RX n9 HSMB TX p10 HSMB RX p10 HSMB TX n10 HSMB RX n10 HSMB TX HSMB RX p11 HSMB TX 11 HSMB RX 11 HSMB TX p12 HSMB RX p12 HSMB TX n12 HSMB RX n12 HSMB TX p13 HSMB RX p13 HSMB TX n13 HSMB RX n13 HSMB TX p14 HSMB RX p14 HSMB TX n14 HSMB n14 HSMB TX p15 HSMB RX p15 HSMB TX n15 HSMB n15 HSMB TX p16 HSMB RX p16 HSMB TX n16 HSMB RX n16 HSMB OUT p2 HSMB CLKIN p2 HSMB OUT n2 Terasic TR4 User Manual LVDS RX or CMOS I O or differential clock input LVDS TX bit 8 or CMOS I O LVDS RX bit 8 or CMOS I O LVDS TX bit 8n or CMOS I O LVDS RX bit 8n or CMOS I O LVDS TX bit 9 or CMOS I O LVDS RX bit 9 or CMOS I O LVDS TX bit 9n or CMOS I O LVDS RX bit 9n or CMOS I O LVDS TX bit 10 or CMOS I O LVDS RX bit 10 or CMOS I O LVDS TX bit 10n or CMOS I O LVDS RX bit 10n or CMOS I O LVDS TX bit 11 or CMOS I O LVDS RX bit 11 or CMOS I O LVDS TX bit 11n or CMOS I O LVDS RX bit 11n or CMOS I O LVDS TX bit 12 or CMOS I O LVDS RX bit 12 or CMOS I O LVDS TX bit 12n or CMOS I O LVDS RX bit 12n or CMOS I O LVDS TX bit 13 or CMOS I O LVDS RX bit 13 or CMOS I O LVDS TX bit 13n or CMOS I O LVDS RX bit 13n or CMOS I O LVDS TX bit 14 or CMOS I O LVDS RX bit 14 or CMOS I O LVDS TX bit 14n or CMOS I O LVDS RX bit 14n or CMOS I O LV
24. 38 39 40 GPIO1 D21 GPIO1 D22 GPIO1 D23 GPIO1 D24 GPIO1 D25 GPIO1 D26 GPIO1 D27 GPIO1 D28 GPIO1 D29 GPIO1 D30 GPIO1 D31 GPIO1 D32 GPIO1 D33 GPIO1 D34 GPIO1 D35 GPIO Expansion 1 10 21 GPIO Expansion 1 10 22 GPIO Expansion 1 10 23 GPIO Expansion 1 IO 24 GPIO Expansion 1 10 25 GPIO Expansion 1 10 26 GPIO Expansion 1 27 GPIO Expansion 1 10 28 GPIO Expansion 1 10 29 GPIO Expansion 1 10 30 GPIO Expansion 1 10 31 GPIO Expansion 1 10 32 GPIO Expansion 1 IO 33 GPIO Expansion 1 10 34 GPIO Expansion 1 IO 35 2 7 DDR3 SO DIMM One DDR3 SO DIMM socket is provided as a flexible and efficient form factor volatile memory for user applications The DDR3 SODIMM socket is wired to support a maximum capacity of 4GB with a 64 bit data bus Using differential DQS signaling for the DDR3 SDRAM interfaces it is capable of running at up to 533MHz memory clock for a maximum theoretical bandwidth up to 68Gbps Figure 2 23 shows the connections between the DDR3 SO DIMM socket and Stratix IV GX device The information about mapping of the FPGA pin assignments to the DDR3 SODIMM connectors please refer to Table 2 15 Depends on Standard of HSMC Port C PIN AD30 PIN AE24 PIN AD31 PIN AB30 PIN AE30 PIN AB31 PIN AE31 AG31 PIN AE28 PIN AG32 PIN AE29 PIN AF29 PIN AD28 PIN AG30 PIN AD29 Table 2 15 DDR3 SODIMM Pin Assignments Schematic Signal Names and Functions Schematic Signal Name mem addr 0 me
25. 42 43 44 47 48 49 50 53 54 55 56 59 60 61 62 65 66 67 68 71 72 73 74 77 78 79 80 83 84 85 86 89 90 91 92 HSMA GXB TX n1 HSMA GXB RX n1 HSMA GXB TX pO HSMA GXB RX pO HSMA GXB TX HSMA GXB HSMA OUTO HSMA CLKINO HSMA DO HSMA D1 HSMA D2 HSMA D3 HSMA TX p0 HSMA RX HSMA TX n0 HSMA HSMA TX HSMA RX p1 HSMA TX HSMA HSMA TX p2 HSMA RX p2 HSMA TX n2 HSMA RX n2 HSMA TX p3 HSMA RX p3 HSMA TX n3 HSMA RX n3 HSMA TX p4 HSMA RX p4 HSMA TX n4 HSMA RX n4 HSMA TX p5 HSMA RX p5 HSMA TX n5 HSMA RX n5 HSMA TX p6 HSMA RX p6 HSMA TX n6 HSMA RX n6 HSMA TX p7 HSMA RX p7 HSMA TX n7 HSMA RX n7 Terasic TR4 User Manual www terasic com Transceiver TX bit 1n Transceiver RX bit 1n Transceiver TX bit 0 Transceiver TX bit 0 Transceiver TX bit On Transceiver RX bit On Dedicated clock output Dedicated clock input LVDS TX or CMOS I O LVDS RX or CMOS I O LVDS TX or CMOS I O LVDS RX or CMOS I O LVDS TX bit 0 or CMOS I O LVDS RX bit 0 or CMOS I O LVDS TX bit On or CMOS I O LVDS RX bit On or CMOS I O LVDS TX bit 1 or CMOS I O LVDS RX bit 1 or CMOS I O LVDS TX bit 1n or CMOS I O LVDS RX bit 1n or CMOS I O LVDS TX bit 2 or CMOS I O LVDS RX bit 2 or CMOS I O LVDS TX bit 2n or CMOS I O LVDS RX bit 2n or CMOS I O LVDS TX bit 3 or CMOS I O LVDS RX bit 3 or CMOS I O LVDS TX bit 3n or CMOS I O LVDS RX bit 3n or CMOS I O LVDS TX bit 4 or CMOS I O LVDS RX
26. 64MB Fan Control SMA DDR3 SODIMM PCle 0 PCle 1 Programmable PLL Programmable PLL HSMA_REFCLK 5 REFCLK PGM GXBCLK HSMC A Transceiver x None Prefix Name Prefix Name HSMC E Transceiver x 8 HSMC B None Prefix Name Prefix Name HSMC F HSMC C GPIO HSMC None None Prefix Name Prefix Name Default Setting Load Setting Save Setting Generate Exit Figure 4 5 External Programmable PLL HSMC Expansion Users can connect HSMC interfaced daughter cards onto the HSMC ports located on the board shown in Figure 4 6 Select the daughter card you wish to add to your design under the appropriate HSMC connector where the daughter card is connected to The System Builder will automatically generate the associated pin assignment including pin name pin location pin direction and IO standard If a customized daughter board is used users can select HSMC Default followed by changing the pin name pin direction and IO standard according to the specification of the customized daughter board If transceiver pins are not required on the daughter board please remember to remove it otherwise Quartus II will report errors 75 Terasic TR4 User Manual www terasic com www terasic com Terasic IR4 1 0 0 venio UNIVERSITY 59 PROGRAM WwWw terasic com HSMC Expansion HSMC D
27. Before running the loopback verification HSMC test select the desired HSMC connector to be tested Follow the instruction noted under Loopback Installation section and click on Verify Note the Control Panel HSMC loopback test does not test the transceiver signals on the HSMC interface For HSMC transceiver loopback test please refer to the demonstration section 66 Terasic TR4 User Manual www terasic com www terasic com BUTTON Memory plea se follow the Temperature Figure 3 11 HSMC Loopback Verification Test Performed under Control Panel 3 8 Fan Choose the Fan tab to reach the window shown in Figure 3 12 This function is designed to verify the functionality of the fan components and signals Please make sure the fan is installed on the TR4 before running this function 67 Terasic TR4 User Manual www terasic com www terasic com Fan Control BUTTON Memory Temperature Figure 3 12 Fan Control of the TRA 3 9 Information For more information please click on the Information button in order to reach the window shown in Figure 3 13 Users can click Terasic Web button and TR4 Web button to reach the respective websites in order to learn more about the TR4 and Terasic Technologies 68 Terasic TR4 User Manual www terasic com www terasic com BUTTON HSMC Temperature www terasic com Figure 3 13 Information Tab of TR4 Control Panel 69 Terasic TR4 Us
28. CLKIN n2 CLK8n CLK3n CLK10n CLK4n 12 Interface The I2C bus on the HSMC connectors is separated into two groups HSMC Port A B and C share the same I2C interface HSMC ports D E and F share the other I2C bus Table 2 10 lists the detailed distribution 26 Terasic TR4 User Manual www terasic com www terasic com Table 2 10 HSMC I2C Group HSMC A B C 2C Schematic Signal Description VO Standard Stratix IV GX Name Pin Number HSMC A B C 2C 2 5 1 AE16 HSMB SCL clock signal HSMC A B C I2C 2 5 V 1 AF16 HSMB SDA data signal HSMC D E F I2C Schematic Signal Description VO Standard Stratix IV GX Name Pin Number HSMC D E F I2C 1 5V 1 G21 HSMD SCL clock signal HSMC D E F I2C 1 5V 1 F21 HSMD SDA data signal 4 The I2C I O on the TR4 HSMC connector is defined with 3 3V There is a level translator between FPGA and HSMC connector to translate FPGA 2 5V or 1 5 I O to 3 3V The signals above are also connected to the level translator When these signals are used as general purpose I O the maximum data rate is 60Mbps I O through the Level Translator There is a pin named HSMD OUTO on HSMC Port D which is connected to an FPGA 1 5V standard bank To meet the I O standard of adjustable specification a level translator is used between the FPGA and HSMC Port D on this net Thus the maximum data rate of this pin is 60Mbps due to the limitations of the level translator B HSMC Port C Shared Bus
29. LEDx 4 Button x 4 SSRAM 2MB Temperature Flash 64MB Fan Control SMA O DDR3 SODIMM PCle 0 L1 PCIe 1 Programmable PLL Programmable PLL HSMA REFCLK Unchange HSME REFCLK 7274705 PGM GXBCLK Unehange HSMC A Transceiver x 8 None Prefix Name HSMC B None Prefix Name HSMC C GPIO HSMC None Prefix Name Default Setting Load Setting Save Setting Figure 4 4 System Configuration Group B Programmable PLL There are three external programmable PLLs on board that provide reference clocks for the following signals REFCLK HSME REFLCLK and GXBCLK To use these PLLs users can select the desired frequency on the Programmable PLL group as shown in Figure 4 5 As the Quartus II project is created System Builder automatically generates the associated PLL configuration code according to users desired frequency in Verilog which facilitates users implementation as no additional control code is required to configure the PLLs Note If users need to dynamically change the frequency they will need to modify the generated control code themselves Terasic TR4 User Manual www terasic com www terasic com Terasic IR4 1 0 0 ATERA System Configuration RSITY RAM www terasic com Board Type TR4 230 Project Name CLOCK v Switch x 4 LEDx 4 Button x 4 SSRAM 2MB v Temperature Flash
30. LVDS TX bit 14n or CMOS I O LVDS RX bit 14n or CMOS I O LVDS TX bit 15 or CMOS I O LVDS RX bit 15 or CMOS I O LVDS TX bit 15n or CMOS I O LVDS RX bit 15n or CMOS I O LVDS TX bit 16 or CMOS I O LVDS RX bit 16 or CMOS I O LVDS TX bit 16n or CMOS I O LVDS RX bit 16n or CMOS I O LVDS TX or CMOS I O or differential clock input output or or 125 LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V www terasic com R12 AF6 R11 AE5 R13 F10 P13 E10 N11 G9 N10 F9 N12 D9 M12 C9 M10 G6 L10 F6 M11 G5 L11 ANOTE RYA E HSMA CLKIN 2 differential clock input output LVDS 2 5 V 8 an 157 HSMA OUT 2 differential clock input output LVDS or 2 5 LVDS RX or CMOS 10 o HSMA CLKIN n2 differential clock input output LVDS 2 5 V 5 126 Terasic TR4 User Manual www terasic com www terasic com Bo
31. M Flash 64MB OSMA L1PCle 0 Programmable PLL Programmable PLL HSMA_REFCLK HSME_REFCLK PGM GXBCLK Switch x 4 Button x 4 Temperature Fan Control DDR3 SODIMM PCle 1 Jnchange nchange Jnchange HSMC Expansion HSMC D DVI FulHD TXIRX Prefix Name DVI 1 HSMC E Transceiver x 8 A Transceiver to SMA Prefix Name HSMC F LTC2 8 LCD Touch Camera Prefix Name HSMC A Transceiver x 8 DVI FulHD Prefix Name Dwi 2 HSMC B HDMI Prefix Name HSMC C GPIO HSMC NET 10 100 1000 Ethemet Prefix Name Default Setting Load Setting Save Setting Generate Figure 4 7 Specify Prefix Name for HSMC Expansion Board Additionally users can choose the HSMC C GPIO as either HSMC or GPIO since the GPIO ports share pins with HSMC Port C as shown in Figure 4 8 Terasic TR4 User Manual www terasic com T www terasic com Terasic IR4 Y1 0 0 ND S RYA 2 System Configuration ter UNIVERSI www terasic cCom Board Type TR4_230 Project Name TR4 CLOCK v Switch x 4 LEDx 4 v Button x 4 v SSRAM 2MB M Temperature Flash 64MB v Fan Control SMA O DDR3 SODIMM PCle 0 1 Programmable PLL Programmable PLL HSMA_REFCLK Unchange HSME_REFCLK Unehange PGM GXBCLK 7074726 HSM
32. Or vps or 2 5 V differential clock input LVDS RX or CMOS I O LVDS or 2 5 V PES CMOS Or vps or 2 5 V differential clock input LVDS TX bit 8 or CMOS I O LVDS or 2 5 V LVDS RX bit 8 or CMOS I O LVDS or 2 5 V LVDS TX bit 8n or CMOS 5 V LVDS or 2 5 RX bit or CMOS Vps or 2 5 V LVDS TX bit 9 or CMOS I O LVDS or 2 5 V LVDS RX bit 9 or CMOS I O LVDS or 2 5 V LVDS TX bit 9n or CMOS LVDS or 2 5 V S or 2 5 Tid RX bit 9n or CMOS bc or 2 5 V LVDS TX bit 10 or CMOS I OLVDS or 2 5 V m RX bit 10 or CMOS Vps or 2 5 V TX bit 10n or CMOS vps or 2 5 V a RX bit 10n or CMOS vps or 2 5 V 135 www terasic com N7 M6 M7 L5 L8 K6 L7 K5 K7 J6 J7 J5 W12 W6 W11 W5 N13 P14 M13 N14 M14 L13 K12 K13 D11 L14 B10 K14 119 120 121 122 125 126 127 128 131 132 133 134 137 138 139 140 143 144 145 146 149 150 151 152 155 156 HSME TX p11 HSME RX p11 HSME TX n11 HSME RX n11 HSME TX p12 HSME RX p12 HSME TX n12 HSME RX n12 HSME TX p13 HSME RX p13 HSME TX n13 HSME RX n13 HSME TX p14 HSME RX p14 HSME TX n14 HSME RX n14 HSME TX p15 HSME RX p15 HSME TX n15 HSME RX n15 HSME TX p16 HSME RX p16 HSME TX n16 HSME RX n16 HSME OUT p2 HSME CLKIN p2 Terasic TR4 User Manual LVDS TX bit 11 or CMOS I OLVDS or 2 5 V da RX bit 11 or CMOS Vps or 2 5 V Pai
33. 1 2 APA 1 WE iDMARD RDVALID A 1 1 1 oFIFO SEL Low Level 2 clock cycles Figure 6 4 Read Transaction Waveform of the PCle DMA Channel on Memory Mapping Mode Terasic TR4 User Manual www terasic com 101 www terasic com 14 2 3 4 5 6 7 8 9 ck N V N V NV NV NV Ny NY NYv 1 oDMAWR_ADDR AD XAT KE OX Ri DX gt oDMAWR K Di X 02 X D3 X gt 1 oDMAWR WRITE i oFIFO MEM SEL 1 Figure 6 5 Write Transaction Waveform of the channel memory mapping mode 1 1 1 1 1 12 4 i 6 7 8 9 oCORE 1 oDMARD_ADDR K gt lt FIFO ID 1 iDMARD lt X D 02 K 03 gt 1 1 1 1 14 1 143 iDMARD RDVALID 1 1 1 2 clock cycles oFIFO_MEM_SEL le P 343534 1 1 1 1 1 1 1 1 1 High Level Figure 6 6 Read Transaction Waveform of the PCle DMA Channel in FIFO link Mode 102 Terasic TR4 User Manual www terasic com www terasic com oCORE oDMAWR ADDR gt lt FIFO ID oDMAWR DATA KOK Do KDI X D2 K K D4 gt 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 oDMAWR WRITE X
34. 12 Table 2 7 gives the detailed numbers of true and emulated LVDS interfaces of each HSMC port Also it lists the numbers of LVDS receivers needed to assemble external input termination resistors on each HSMC ports Table 2 8 shows all the external input differential resistors for LVDS receivers on HSMC Port B and C The factory default setting is not installed Finally because HSMC Port C shares FPGA I O pins with GPIO headers so the LVDS performance can only support a data rate of up to 500Mbps 1 Although the specifications of the HSMC connector defines signals D0 D3 as single ended I Os DO and D2 can be used as LVDS transmitters and DI and D3 can be used as LVDS receivers on the TR4 FPGA Resistor Network LVDS Receiver Emulated LVDS Transmitter Figure 2 12 Emulated LVDS Resistor Network between FPGA and HSMC Port 24 Terasic TR4 User Manual www terasic com www terasic com ANOTE RYA Transmitting Device Input Buffer Figure 2 13 External On Board Termination between FPGA and HSMC Port Table 2 7 LVDS Breakdown HSMA HSMB HSMC HSMD HSME HSMF True LVDS Transmitters 18 Emulated LVDS Transmitters 0 Supported with OCT 18 Needed External Input Termination Resistors 0 10 9 18 8 9 0 11 9 18 7 9 0 Table 2 8 Distribution of the Differential Termination Resistors for HSMC Connector HSM
35. 2 CONTROLLING THE LED amen ban ee BE 59 3 3 SWITCHES AND PUSH BUTTONS eo nee banana na BNN Ea nah a tea bue eua 60 3 4 MEMORY CONTROLLER 2 PU Ege UE ENERO UOI RI E NN 61 3 9 TEMPERATURE MONITOR RR 64 JOPE 525 4 5 40155455 14 11 41 0 65 3 Ka com 66 3 8 FAN 67 3 9 INFORMATION 68 1 TR4 User Manual www terasic com www terasic com ANU S RYA 4 TR4 SYSTEM 70 Z INTRODUCTION en eni ia NI 70 4 2 GENERAL DESIGN ben nba 70 4 3 USING TRA SYSTEM BUIEDER 71 CHAPTER 5 EXAMPLES OF ADVANCED DEMONSTRATION co o coco 82 BREATHING LEDS anna ANN NB DERE Pedes 82 5 2 EXTERNAL CLOCK GENERATOR 2 ee SNN NN NN SB BBB na 83 5 3 HIGH SPEED MEZZANINE CARD 89 34 DDR3SD RA Mb aa 91 5 DDR3 SDRAM AGB dengan 94 CHAPTER 6 PCI EXPRESS REFERENCE DESIGN oo 98 6 1 PCI EXPRESS SYSTEM 5 aan 98 6 2 FPGA PCI EXPRESS SYSTEM DESIGN
36. 66 66 06 Program flash please wait a few minutes Using cable USB Blaster USB 1 device 1 instance 6x60 Resetting and pausing target processor OK Checksums took 2 35 Erase not reguired 66186666 124 Programming Figure 2 8 Programming Flash 8 Programming complete 17 Terasic TR4 User Manual www terasic com warnings www terasic com Wios II EDS 11 1 gec3 Program flash please vait a fev minutes Using cable USB Blaster USB 1 device 1 instance 0x00 Resetting and pausing target processor OK Checksums took 2 3s Erase not required Programmed 11596KB 737 15 15 7KB s gt Device contents checksummed OK Leaving target processor paused Using cable USB Blaster USB device 1 instance 6x80 Resetting and pausing target processor OK Checksums took s Erase not required Programmed 1KB in s Device contents checksummed OK Leaving target processor paused Press ENTER key to continuance Figure 2 9 Programming Flash complete 2 2 Setup Elements B JTAG Control DIP Switch The TR4 supports individual JTAG interfaces on each HSMC connector This feature allows users to extend the JTAG chain to daughter cards or additional TR4s Before using this interface JP7 needs to be shorted to enable the JTAG interface on all the HSMC connectors The JTAG signals on each HSMC connector can be removed or included in the active JTAG chain via DIP switches Tabl
37. AU19 AN21 AW20 AP21 AW21 AT17 www terasic com 102 103 104 107 108 109 110 113 114 115 116 119 120 121 122 125 126 127 128 131 132 133 134 HSMF RX p8 HSMF TX n8 HSMF RX n8 HSMF TX p9 HSMF RX p9 HSMF TX n9 HSMF RX n9 HSMF TX p10 HSMF RX p10 HSMF TX n10 HSMF RX n10 HSMF TX p11 HSMF RX HSMF TX 11 HSMF 11 HSMF TX p12 HSMF RX p12 HSMF TX n12 HSMF RX n12 HSMF TX p13 HSMF RX p13 HSMF TX n13 HSMF RX n13 Terasic TR4 User Manual www terasic com LVDS bit 8 or CMOS VDS or 2 5 V LVDS TX bit 8n or LVDS or 2 5 V LVDS RX bit 8n or D 2 5 V CMOS I O 222225 LVDS TX bit 9 or CMOS ps or 2 5 V LVDS bit 9 or CMOS Vps or 2 5 V LVDS TX bit 9n or LVDS 2 5 V LVDS RX bit 9n or CETT LVDS or 2 5 V LVDS TX bit 10 or LVDS 2 5 V LVDS RX bit 10 or D 2 5 V CMOS I O LVDS TX bit 10n or Ced LVDS or 2 5 V LVDS RX bit 10n or LVDS 2 5 V LVDS TX bit 11 or CMOS Vps or 2 5 V LVDS RX bit 11 or LVDS 2 5 V LVDS TX bit 11n or LVDS or 2 5 V LVDS RX bit 11 D 2 5 V CMOS I O LVDS TX bit 12 or LVDS 2 5 V LVDS RX bit 12 or maa LVDS or 2 5 V LVDS TX bit 12n or LVDS 2 5 V LVDS RX bit 12n or LVDS or 2 5 V LVDS TX bit 13 or LVDS 2 5 V LVDS RX bit 13 or LVDS or 2 5 V CMOS I O LVDS TX bit 13n
38. Breathing LEDs sof B Demonstration Batch File Demo Batch File Folder Breathing LEDsY Demo batch 82 Terasic TR4 User Manual www terasic com www terasic com The demo batch file includes following files e Batch File Breathing LEDs bat e FPGA Configuration File Breathing LEDs sof B Demonstration Setup e Make sure Quartus II and Nios are installed on your PC e Connect the USB Blaster cable to the board and host PC Install the USB Blaster driver if necessary e Power on the board Execute the demo batch file Breathing LEDs bat under the batch file folder Breathing LEDsWDemo batch Press BUTTONO of the TR4 board to reset e The LEDs will pulse according to the set frequency 5 2 External Clock Generator The External Clock Generator provides designers with 3 programmable clock generators via Texas Instruments chips CDCM61001RHBT x 2 CDCM61004RHBT with the ability to specify the clock frequency individually as well as addressing the input reference clock for the Stratix IV GX transceivers The programmable clock is controlled by a control bus connected to the MAX II EPM2210 device This can reduce the Stratix IV GX I O usage while enabling greater functionality on the FPGA device The MAX II EPM2210 device is capable of storing the last entered clock settings at which in the event the board restarts the last known clock settings are fully restored In this demonstration we ill
39. HSMC TX n8 LVDS TX bit 8n or CMOS LVDS or2 5 V 26 104 HSMC RX n8 LVDS RX bit 8n or CMOS I O LVDS or2 5 V AK33 107 HSMC TX p9 LVDS TX bit9or CMOS I O LVDSor2 5 V 27 108 HSMC RX p9 LVDS RX bit 9 CMOS LVDSor2 5 v AN34 109 HSMC TX n9 LVDS TX bit 9n or CMOS LVDS 2 5 24 110 HSMC RX n9 LVDS RX bit 9n or CMOS I O LVDS or2 5 V AN35 113 HSMC TX p10 LVDS TX bit 10 CMOS LVDS 2 5 27 114 HSMC RX p10 LVDS RX bit 10 CMOS LVDS or2 5 V AM34 115 HSMC TX n10 LVDS TX bit 10n CMOS l OLVDS or 2 5 V 28 116 HSMC RX n10 LVDS RX bit 10n CMOS I OLVDS or 2 5 V 35 119 HSMC TX LVDS TX bit 11 or CMOS I O LVDSor2 5 V 24 120 HSMC LVDS bit 11 CMOS LVDS or 2 5 134 121 5 11 LVDS TX bit 11n CMOS I O LVDS or2 5 V AG24 122 HSMC 11 LVDS RX bit 11n or CMOS I OLVDS 2 5 135 125 HSMC TX p12 LVDS TX bit 12 CMOS LVDS 2 5 AW31 126 HSMC 2 LVDS bit 12 CMOS I O LVDS or2 5 V AK34 127 HSMC TX n12 LVDS TX bit 12n or CMOS l OLVDS 2 5 V AV31 128 HSMC 12 LVDS RX bit 12n or CMOS l OLVDS 2 5 5 131 HSMC TX p13 LVDS bit 13 CMOS LVDS or 2 5 V AW33 132 HSMC LVDS bit 13 CMOS LVDS 2 5 AJ34 133 HSMC TX n13 LVDS TX bit 13n or CMOS I OLVDS 2 5 V AW34 134 HSMC RX n13 LVDS RX bit 13n or CMOS l OLVDS or 2 5
40. HSMD_RX_n14 LVDS RX bit 14n or CMOS I OLVDS or 2 5 V M34 132 TR4 User Manual www terasic com www terasic com 143 HSMD TX p15 LVDS TX bit 15 or CMOS LVDS or 2 5 V R30 144 HSMD RX p15 LVDS RX bit 15 or CMOS I O LVDS or 2 5 V L34 145 HSMD TX n15 LVDS TX bit 15n or CMOS I O LVDS 2 5 V R31 146 HSMD RX n15 LVDS RX bit 15n or CMOS I O LVDS or 2 5 V 135 149 HSMD TX p16 LVDS TX bit 16 CMOS LVDS 2 5 1 150 HSMD RX p16 LVDS RX bit 16 or CMOS I O LVDS or 2 5 V K34 151 HSMD TX n16 LVDS TX bit 16n CMOS I O LVDS or 2 5 AL31 152 HSMD RX n16 LVDS bit 16n or CMOS l OLVDS or 2 5 V K35 LVDS TX or CMOS I O or 155 HSMD OUT p2 differential clockLVDS or 2 5 V M32 input output 156 HSMD CLKIN p2 lisa differential clock input LVDS TX or CMOS I O or 157 HSMD OUT n2 differential clockLVDS or 2 5 V 132 input output 158 HSMD CLKIN n2 LVDS PA Or CMOS UO jas differential clock input Table 7 5 HSMC Port E Pin Assignments Schematic Signal Names and Functions Board Reference Stratix IV GX Schematic Signal Name Description VO Standard J3 Pin Number 1 HSME GXB TX p7 Transceiver TX bit 7 1 4 V PCML B36 2 HSME GXB RX p7 Transceiver RX bit 7 1 4 V PCML C38 3 HSME GXB TX n7 Transceiver TX bit 7n 1 4 V PCML B37 4 HSME GXB RX n7 Transceiver RX bit 7n 1 4 V PCML C39 5 HSME GXB TX p6 Transceiver TX bit 6 1 4 V PCML D36 6 HSME GXB RX p6 Transceiver TX bit 6 1 4 V PCML E38 7 HSME GXB TX n6
41. LVDS RX bit 5n or CMOS I O LVDS TX bit 6 or CMOS I O LVDS RX bit 6 or CMOS I O LVDS TX bit 6n or CMOS I O LVDS RX bit or CMOS I O LVDS TX bit 7 or CMOS I O LVDS RX bit 7 or CMOS I O LVDS TX bit 7n or CMOS I O LVDS RX bit 7n or CMOS I O LVDS TX or CMOS I O LVDS RX or CMOS 10 or differential clock input 127 Standard LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V Table 7 2 HSMC Port B Pin Assignments Schematic Signal Names and Functions Stratix IV GX Pin Number AN15 AP15 AD15 AV13 AE15 13 13 10 AL15 10 AT14 9 AU14 AU9 AW12 7 AW11 AW7 AL14 AW6 AM14 AW5 AT12 AV5 AU12 AW4 AP13 AV8 AN14 8 AG14 AR5 AG15 5 9 AT6 AP9 AU6 AN10 AT7 www terasic com 97 98 101 102 103 104 107 108 109 110 113 114 115 116 119 120 121 122 125 126 127 128 131 132 133 134 137 138 139 140 143 144 145 146 149
42. TRA DDR3 UniPHY 4G RTL bat FPGA Configure File TRA DDR3 UniPHY 4G RTL sof B Demonstration Setup e Make sure Quartus II is installed on your PC Make sure DDR3 SDRAM SODIMM 4 GB is installed on your board as shown in Figure 5 10 e Connect the USB Blaster cable to the board and host PC Install the USB Blaster driver if necessary Poweron the TR4 board Execute the demo batch file DDR3 UniPHY 4G RTL bat under the batch file folder DDR3 UniPHY 4G RTL Memo batch e Press BUTTONO of the TR4 board to start the verification process When BUTTONO is pressed all the LEDs go out At the instant of releasing BUTTONO LED3 should turn on local init done After approximately 15 seconds if LEDO and LEDI turn on the test has passed e If LED2 turns at any time during the process the test has failed Table 5 3 lists the function for different LEDs e Press BUTTONO to reset the process for a repeat test 96 TR4 User Manual www terasic com www terasic com PE paman HEEL 7 EE 1 0000 50 Figure 5 10 Insert DDR3 SDRAM SODIMM for the DDR3 4G Demonstration NAME LEDO LED1 LED2 LED3 Terasic TR4 User Manual www terasic com Table 5 3 LED Indicators Description test complete test pass test fail local_init_done amp local_cal_success 97 www terasic com Chapter 6 PCI Express Reference Design PCI Expres
43. TX bit Tin or CMOS Vps or 2 5 V o RX bit 11n or CMOS vps or 2 5 V LVDS TX bit 12 or CMOS I OLVDS 2 5 V RX bit 12 or CMOS Vps or 2 5 V e TX bit 12n or CMOS Vps or 2 5 V 5 RX bit 12n or CMOS vps or 2 5 V LVDS TX bit 13 or CMOS I OLVDS or 2 5 V S RX bit 13 or CMOS Vps or 2 5 V i TX bit 13n or CMOS Vps or 2 5 V P RX bit 13n or CMOS vps or 2 5 V LVDS TX bit 14 or CMOS I OLVDS or 2 5 V d RX bit 14 or CMOS v e or 2 5 V ii TX bit 14n or CMOS voe or 2 5 V e RX bit 14n or CMOS vps or 2 5 V LVDS TX bit 15 or CMOS I OLVDS or 2 5 V PM RX bit 15 or CMOS VDS or 2 5 V vd TX bit 15n or CMOS or 2 5 V m RX bit 15n or CMOS vps or 2 5 V LVDS TX bit 16 or CMOS I OLVDS or 2 5 V LVDS RX bit 16 or CMOS 5 V lO LVDS or 2 5 LVDS TX bit 16n or CMOS Ds or 2 5 V LVDS RX bit 16n CMOS vps or 2 5 V LVDS TX or CMOS or differential clockLVDS or 2 5 V input output LVDS or CMOS orLVDS or 2 5 V 136 www terasic com A10 H13 C11 G13 J12 F13 J13 E13 F12 B11 D13 A11 B14 F14 A14 E14 H14 B13 G14 A13 K15 D14 J15 C14 R14 AB6 differential clock input LVDS TX or CMOS I O or 157 HSME OUT n2 differential clockLVDS or 2 5 V N15 input output 158 HSME CLKIN n2 LVDS RX or CMOS VO Wns 2 5 V JAAS differential clock input Table 7 6 HSMC Port F Pin Assignments Schematic Signal Names and Functions Board Reference n Strati
44. Transceiver TX bit 6n 1 4 V PCML D37 8 HSME GXB RX n6 Transceiver RX bit 6n 1 4 V PCML E39 9 HSME GXB TX p5 Transceiver TX bit 5 1 4 V PCML K36 10 HSME GXB RX p5 Transceiver RX bit 5 1 4 V PCML L38 11 HSME GXB TX n5 Transceiver RX bit 5n 1 4 V PCML K37 12 HSME GXB RX n5 Transceiver RX bit 5n 1 4 V PCML L39 13 HSME GXB TX p4 Transceiver TX bit 4 1 4 V PCML M36 14 HSME GXB RX p4 Transceiver RX bit 4 1 4 V PCML N38 15 HSME GXB TX n4 Transceiver TX bit 4n 1 4 V PCML M37 16 HSME GXB RX n4 Transceiver RX bit 4n 1 4 V PCML N39 17 HSME GXB TX p3 Transceiver TX bit 3 1 4 V PCML P36 18 HSME GXB RX p3 Transceiver TX bit 3 1 4 V PCML R38 19 HSME GXB TX n3 Transceiver TX bit 3n 1 4 V PCML P37 20 HSME GXB RX n3 Transceiver RX bit 3n 1 4 V PCML R39 21 HSME GXB TX p2 Transceiver TX bit 2 1 4 V PCML T36 Terasic TR4 User Manual 133 www terasic com 22 23 24 25 26 27 28 29 30 31 32 39 40 41 42 43 44 47 48 49 50 53 54 55 56 59 60 61 62 65 66 67 68 71 72 73 HSME RX 2 HSME GXB TX n2 HSME GXB RX n2 HSME GXB TX p1 HSME GXB RX p1 HSME GXB TX n1 HSME GXB RX n1 HSME GXB TX HSME GXB RX pO HSME GXB TX HSME GXB HSME OUTO HSME CLKINO HSME DO HSME D1 HSME D2 HSME D3 HSME TX pO HSME RX pO HSME TX nO HSME RX nO HSME TX p1 HSME RX p1 HSME TX n1 HSME RX n1 HSME TX p2 HSME RX p2 HSME TX n2 HSME RX n2 HSME TX p3 HSME RX p3 HSME TX n3 HSME R
45. bit 4 or CMOS I O LVDS TX bit 4n or CMOS I O LVDS RX bit 4n or CMOS I O LVDS TX bit 5 or CMOS I O LVDS RX bit 5 or CMOS I O LVDS TX bit 5n or CMOS I O LVDS RX bit 5n or CMOS I O LVDS TX bit 6 or CMOS I O LVDS RX bit 6 or CMOS I O LVDS TX bit 6n or CMOS I O LVDS RX bit 6n or CMOS I O LVDS TX bit 7 or CMOS I O LVDS RX bit 7 or CMOS I O LVDS TX bit 7n or CMOS I O LVDS RX bit 7n or CMOS I O 124 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V www terasic com AB3 AC1 AD4 AE2 AD3 AE1 D10 C10 AK8 AP6 7 5 AG10 AN6 AG9 5 9 AM6 AH8 AM5 AG8 AL6 AG7 AL5 AF11 AK6 AF10 AK5 AD10 AJ6 AD9 AJ5 AB13 AH6 AB12 AH5 AB11 AG6 AB10 AG5 T13 AB9 T12 AC8 95 96 97 98 101 102 103 104 107 108 109 110 113 114 115 116 119 120 121 122 125 126 127 128 131 132 133 134 137 138 139 140 143 144 145 14
46. board and installed into the HSMC connectors B Power Switch The slide switch SW7 is the board power switch for the DC power input When the slide switch is in the ON position the board is powered on Alternatively when the switch is in the OFF position the board is powered off 2 14 Security The TR4 board features design security to protect your designs against unauthorized copying reverse engineering and tampering of your configuration files For more information please refer to Altera s application note AN556 Using the Design Security Features in Altera FPGAs 54 TR4 User Manual www terasic com www terasic com Chapter 3 Control Panel The TR4 board comes with a PC based Control Panel that allows users to access various components onboard The host computer communicates with the board via USB Blaster port The tool can be used to verify the functionality of components This chapter presents some basic functions of the Control Panel illustrates its structure in block diagram form and finally describes its capabilities 3 1 Control Panel Setup The Control Panel software utility is located in the directory Tools TR4 ControlPanel in the TR4 System CD To execute the program simply copy the whole folder to your host computer and launch the control panel by double clicking the TR4 ControlPanel exe CAUTION Please make sure Quartus II and USB Blaster Driver are installed before l
47. device 1 instance nios2 terminal Use the IDE stop button or Ctrl C to terminate TR4 DDR3 Test Program DDR3 Clock 533 MHZ DDR3 Size 1924 MBytes any BUTTON to start test IBUTTONG for continued test DDR3 Testing Iteration 1 50 66 78 80 9807 1004 read uverify LOL 20 30 40 580 60 70 80 9807 1807 DDR3 test pass size 16073741824 bytes 133 070 sec Press any BUTTON to start test BUTTON for continued test Figure 5 8 Display Progress and Result for the DDR3 1G Demonstration 5 5 DDR3 SDRAM 4GB This demonstration presents user a basic utilization of DDR3 SDRAM 4G on TR4 It describes how the Altera s DDR3 SDRAM Controller with UniPHY IP is used to create DDR3 SDRAM controller and modify the IP generated example top to test the entire space of DDR3 SDRAM This demonstration is a pure RTL project The required DDR3 SDRAM SODIMM module should be exactly 4 GB of DDR3 1066 B Function Block Diagram Figure 5 9 shows the function block diagram of this demonstration The DDR3 controller is configured as a 4GB DDR3 1066 controller The DDR3 IP generates one 533 0 MHz clock as memory clock and one half rate system clock 266 5 MHz for the controller 94 TR4 User Manual www terasic com www terasic com Test Result DDR3 SDRAM pr wm ew we www ww ew we we ewe eee eee eee end Figure 5 9 Block Dia
48. flash Program pfl option bit into the flash Readme File AE AHA HAHAHA HAHAHA HAHAHA HAHAHA HAHAHA HAHAHA HH HAHAHA HAHAHA HH HAHAHA HAHAHA HAHAHA HAHAHA Enter number lt D for Done Figure 2 3 Flash Program Tools 3 Select option 2 TR4 User Manual www terasic com www terasic com NB SDN AX ony LAMB TR4 Development Kit Flash Program Tools ver 1 0 0 0 menu HAHA MH MM MM HH gt Program sof and elf to flash include option bit 1 Erase flash 2 Program sof file into the flash 3 Program elf file into the flash 4 Program pfl option bit into the flash 9 Readme File AHA HAHAHA HAHAHA HH HAHAHA HM HH HH 9E 9E 9E 9E 9E 9E 9E 9E 9E 9E 9E H HH MH HM HH HH KH HAHAHA Enter a number D for Done 2 Figure 2 4 Option 2 4 Enterthe sof file name to be programmed onto the flash memory BEE Please input sof file name tr4 default flash loader sof Figure 2 5 Enter sof Name to Program 15 Terasic TR4 User Manual www terasic com www terasic com 5 The following lines will appear during Flash programming Extracting Option bits SREC Extracting FPGA Image SREC and Deleting intermediate files If these lines don t appear on the windows command programming on the flash memory is not successfully set up Please make sure Quartus II 11 1 and Nios II 11 1 IDE or
49. found in the system The m szPcielnfo array contains detailed information for each PCIe card To connect the selected PCIe card the functions are called int nSel ComboBoxBoard gt ItemIndex WORD VID m szPcieInfo nSel VendorID WORD DID m szPcieInfo nSel DeviceID bSuccess m hPCIE Open VID DID O 0 first matched board where nSel is selected index in the Selected FPGA Board poll down menu Based on the return m szPcieInfo we can find the associated PID and DID which can br used to specifiy the target PCIe card To read the BUTTON status the function is called m hPCIE Read32 DEMO PCIE USER BAR DEMO PCIE IO ADDR amp dwData To set LED status the function is called m hPCIE Write32 DEMO PCIE USER BAR DEMO PCIE IO ADDR dwData To write and read memory mapped memory call the functions write bSuccess m hPCIE Dmalrite Local ddr pWrite nTestSize if bSuccess read bSuccess m hPCIE DmaRead Local ddr pRead nTestSize 116 Terasic TR4 User Manual www terasic com www terasic com ANU S RYA write and read FIFO memory call the functions write hSuccess m hPCIE DmaFifoWrite FifoID pWrite nTestSize if bSuccess t read bSuccess m hPCIE DmaFifoRead FifoID pRead nTestSize 6 5 Image Processing Application This example shows how to utilize computing power of the FPGA for image processing The appl
50. indicate the I O standard of each HSMC port as shown in Table 2 12 For example LEDs D11 and D12 will be turned on and off respectively when the I O Standard of HSMC Port A is set to 2 5V 28 TR4 User Manual www terasic com www terasic com Position 1 1 5 Position 2 18 Position 3 25V Position 4 3 0V JP X X21 2 3 4 5 6 Figure 2 14 HSMC I O Configuration Header Table 2 12 HSMC IO Standard Indicators HSMA HSMB HSMC HSMD HSME HSMF 011 012 D9 Dio D7 D8 D5 D6 D3 D4 D1 D2 1 5V OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 1 8V OFF ON OFF ON OFF ON OFF ON OFF ON OFF 25V ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF 3 0V ON ON ON ON ON ON ON ON ON ON 4 Users who connect a daughter card onto the HSMC ports need to pay close attention to the I O standard between TR4 HSMC connector pins and daughter card system For example if the I O standard of HSMC pins on TR4 board is set to 1 8V a daughter card with 3 3V or 2 5V I O standard may not work properly on TR4 board due to I O standard mismatch When using custom or third party HSMC daughter cards make sure that all the pin locations are aligned to prevent shorts B Using THCB HME2 Adapter Card The purpose of the HSMC Height Extension Male to Female card THCB HMF2 included in the TR4 kit package is to increase the height of the HSMC Port C and D connector to avoid any obstruction that might take place as a HSMC daughter ca
51. later is used 6 Nios II EDS 11 1 gec3 Info Processing started Mon Dec 12 14 11 52 2011 Info Command quartus cpf c tr4 hu pof tr4 hu hexout Info Quartus II 32 bit Convert programming file was successful errors war Peak virtual memory 378 megabytes Processing ended Mon Dec 12 14 12 27 2611 Elapsed time 66 68 35 Total CPU time on all processors 66 66 34 Extracting Option bits SREC Extracting FPGA Image SREC Deleting intermediate files Modify tr4_hw map flash file ok Load tr4_default_flash_loader file into FPGA please wait Figure 2 6 Loading sof File Erasing Flash 16 TR4 User Manual www terasic com www terasic com Nios II EDS 11 1 gec3 Info applicable agreement for further details Info Processing started Mon Dec 12 14 23 26 2011 Info Command quartus pgm c USB BlasterlUSB 81 m jtag o p tr4 default flash loader sof Info 2139045 Using programming cable USB Blaster USB Info 213811 Using programming file tr4 default flash loader sof with checksum G x 79EA74D for device 456 230 4001 209868 Started Programmer operation at Mon Dec 12 14 23 35 2011 289016 Configuring device index 1 2090172 Device 1 contains JTAG ID code 9 024090 28098807 Configuration succeeded 1 devices configured 289011 Successfully performed operation ts 289061 Ended Programmer operation at
52. of the PCI Express standard This will accelerate mainstream development of PCI Express based applications and enable customers to deploy designs for a broad range of high speed connectivity applications The TR4 is supported by multiple reference designs and six High Speed Mezzanine Card HSMC connectors that allow scaling and customization with mezzanine daughter cards For large scale ASIC prototype development multiple TR4s can be stacked together to create easily customizable multi FPGA system Terasic TR4 User Manual www terasic com www terasic com 1 2 Key Features Featured Device o Altera Stratix IV GX FPGA EP4SGX230C2 EP4SGX530C2 Configuration and Set up Elements o Built in USB Blaster circuit for programming o Fast passive parallel FPP configuration via MAX II CPLD and FLASH Components and Interfaces o Six HSMC connectors two with transceiver support o Two 40 pin GPIO expansion headers shares pins with HSMC Port C o Two external PCI Express 2 0 x4 lane connectors Memory o DDR3 SO DIMM socket Max o 64MB FLASH o 2MB SSRAM General User Input Output o Four LEDs o Four push buttons o Four slide switches Clock system o On board 50MHz oscillator Three on board programmable PLL timing chips SMA connector pair for differential clock input SMA connector pair for differential clock output SMA connector for external clock input O O O SMA connector for clock output
53. the board e Open JP7 to bypass the JTAG interface of HSMC if it won t be used e Connect the USB cable supplied directly to the USB Blaster port of the TR4 board see Figure 2 1 The FPGA can now be programmed in the Quartus II Programmer by selecting a configuration bit stream file with the sof filename extension e If users need to use the JTAG interface on HSMC please refer to Section 2 2 for detailed HSMC JTAG switch settings TR4 Board JP7 SE ANO S RYAN pe Connector lt V Figure 2 1 JTAG Configuration Scheme B JTAG FPGA Programming with External Blaster The TR4 board supports JTAG programming over external blaster via J2 To use this interface users need to solder a 2x5 pin connector 2 54mm pitch to J2 Make sure JP7 is open to bypass the JTAG interface of HSMC B Flash Programming The TR4 development board contains a common Flash interface CFI memory to meet the demands for larger FPGA configurations The Parallel Flash Loader PFL feature in MAX II devices provides an efficient method to program CFI flash memory devices through the JTAG interface and the logic to control configuration from the flash memory device to the Stratix IV GX FPGA Figure 2 2 depicts the connection setup between the CFI flash memory Max II CPLD and Stratix IV GX Terasic TR4 User Manual www terasic com www terasic com FPGA Nios dim Flash Programmin
54. 0 0006 GPIO Expansion 010 6 AC32 8 77 QPIO0D7 GPlOExpasionOlOQ7 PIN AH33 9 7 GPIO0 D8 GPIO 010 8 10 10 7 GPIO0 09 GPIO Expansion 01019 13 GPIooDi0 GPIO Expansion 0 IO 10 PIN AH35 14 7 6 0 D11 QGPlOExpansionOlO 15 7 GPIO0 012 GPlOExpansionOlO i2 PIN AK34 16 D13 QGPlOExpansionOIO i3 PIN AK35 18 GPIooD15 Expansion 01015 19 7 016 GPIO Expansion 0 IO 16 PIN 4 20 _ 017 GPIOExpansionOlOfi71 PIN 4 21 018 Expansion 010118 PIN AM35 36 Terasic TR4 User Manual www terasic com www terasic com 22 D19 GPIO Expansion 0 IO 19 PIN AN35 23 020 GPIO Expansion 0 10 20 PIN AJ32 24 D21 GPIO Expansion 0 IO 21 PIN AJ26 25 022 GPIO Expansion 0 101221 PIN AK33 26 D23 GPIO Expansion 0 10 23 PIN AK26 27 GPIOO 024 GPIO Expansion 0 IO 24 PIN AF25 28 D25 GPIO Expansion 0 IO 25 PIN AV29 Depends on 10 31 GPIOO 026 GPIO Expansion 0 IO 26 Standard ai AG25 32 027 Expansion 0 IO 27 Port C PIN AWS30 33 D28 GPIO Expansion 0 10 28 PIN AV32 34 GPIOO 029 GPIO Expansion 0 IO 29 PIN AT28 35 030 GPIO Expansion 0 10 30 PIN AW32 36 031 GPIO Expansion 0 10 31 PIN AU28 37 GPIOO 032 GPIO Expansion 0 IO 32 PIN AV28 38 03
55. 01 Terasic TR4 User Manual www terasic com HSMF TX n3 HSMF RX n3 HSMF TX p4 HSMF RX p4 HSMF TX n4 HSMF RX n4 HSMF TX p5 HSMF RX p5 HSMF TX n5 HSMF RX n5 HSMF TX p6 HSMF RX p6 HSMF TX n6 HSMF RX n6 HSMF TX p7 HSMF RX p7 TX n7 HSMF RX n7 HSMF CLKOUT p1 HSMF CLKIN p1 HSMF CLKOUT n1 HSMF CLKIN n1 HSMF TX p8 LVDS TX bit 3n or LVDS 2 5 V LVDS RX bit 3n or Na LVDS or 2 5 V d TX bit 4 or CMOS v ps or 2 5 V um RX bit 4 or CMOS or 2 5 V LVDS TX bit 4n or 527 LVDS 2 5 V LVDS RX bit 4n or COSE LVDS or 2 5 V Pid TX bit 5 or CMOS ps or 2 5 V BA bita er CMOS LVDS TX bit 5n or DS or 2 5 V CMOS 1 0 222 LVDS RX bit 5n or Na LVDS or 2 5 V TX bit 6 or CMOS vps or 2 5 V m RX bit 6 or CMOS vps or 2 5 V LVDS TX bit 6n or LVDS 2 5 V LVDS RX bit 6n LVDS 2 5 V d TX bit 7 or CMOS ps or 2 5 V RX bit 7 or CMOS Wns cro E LVDS TX bit 7n or Ea LVDS or 2 5 V LVDS RX bit 7n or CMOS LVDS or 2 5 V LVDS TX or CMOS LVDS or 2 5 V LVDS RX or CMOS 10 or differential clock LVDS or 2 5 V input LVDS RX or CMOS I O LVDS or 2 5 V LVDS RX or CMOS 10 or differential clock LVDS or 2 5 V input LVDS TX bit 8 or CMOSLVDS or 2 5 V 138 AR23 AU23 AM23 AR20 AN23 20 25 22 25 AU22 AL22 AU20 AL21 AV20 AR19 AT19 AP19
56. 0x100 followed by reading the same location 61 Terasic TR4 User Manual www terasic com www terasic com ANU S RYA The Seguential Write function of the Control Panel is used to write the contents of file to the serial configuration device as described below Specify the starting address in the Address box Specify the number of bytes to be written in the Length box If the entire file is to be loaded a check mark can be placed in the File Length box instead of giving the number of bytes To initiate the writing of data click on the Write a File to Memory button When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Seguential Read function is used to read the contents of the serial configuration device and place them into a file as follows Specify the starting address in the Address box Specify the number of bytes to be copied into a file in the Length box If the entire contents of the serial configuration device are to be copied then place a check mark in the Entire Memory box Press Load Memory Content to a File button When the Control Panel responds with the standard Windows dialog box ask for the destination file users can specify the desired file in the usual manner 62 TR4 User Manual www terasic com www tera SIC COM Memory DDR3 SODIMM 20000000h WORDS
57. 1 D31 PIN E31 PIN F31 PIN E32 PIN C33 PIN D33 AT16 PIN AL16 PIN AP17 PIN AR17 PIN AW16 PIN AN16 PIN AN17 PIN AR16 PIN AU16 PIN AF17 PIN AG17 www terasic com over temperature alerts These functions are accomplished by connecting the temperature sensor to the internal temperature sensing diode of the Stratix IV GX device The temperature status and alarm threshold registers of the temperature sensor can be programmed by a two wire SMBus which is connected to the Stratix IV GX FPGA The 7 bit power on reset POR slave address for this sensor is 0011000b An optional 3 pin 12V header for fan control located on of the board is intended to reduce the temperature of the FPGA When the temperature of the FPGA device is over the threshold value set by the users the fan will turn on automatically The pin assignments for the associated interface are listed in Table 2 20 Table 2 20 Temperature Sensor Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description VO Standard Stratix IV GX Pin Number TEMP SMCLK SMBus clock 2 5 V PIN AR14 TEMP SMDAT SMBus data 2 5 V PIN AP14 TEMP OVERT n SMBus over temperature alarm 2 5 V PIN AK14 TEMP INT n SMBus alert interrupt 2 5 V PIN AH13 FAN CTRL Fan control 1 5 V PIN B17 2 13 Power The TR4 board features a standalone DC input rated at 19V The DC voltage is stepped down to various power rails used by the components on the
58. 23 GPIO1 D22 2526 GPIO1 D23 GPIOO D24 27 28 025 GPIO1 D24 e GPIO1 D25 3 3V 29 30 GND 3 3V 29 30 GND 026 31800 32 027 GPIO1 026 31 32 GPIO1 D27 D28 34 GPIOO 029 GPIO1 D28 33 34 GPIO1 D29 D30 35 36 031 GPIO1 030 35 36 GPIO1 D31 GPIOO 032 3738 GPIOO D33 GPIO1 032 e 38 GPIO1 D33 034 40 D35 34 40 GPIO1 035 s Figure 2 21 Pin Distribution of the GPIO Expansion Headers Finally Figure 2 22 shows the connections between the GPIO expansion headers and Stratix IV GX 35 Terasic TR4 User Manual www terasic com www terasic com lt 36 LdOd INSH 2 S lt X36 Figure 2 22 Connection between the GPIO Expansion Headers and Stratix IV GX The information about mapping of the FPGA pin assignments to the GPIOO and connectors please refer Table 2 13 and Table 2 14 Table 2 13 GPIO Expansion Header JP9 Pin Assignments Schematic Signal Names and Functions Board Reference Schematic dea Stratix IV GX Description Standard 4 JP9 Signal Name Pin Number GPIOO DO GPIO Expansion 0 IO O Clock In GPIOO 1 GPIO Expansion 0 IO 1 PIN AG34 02 GPIO Expansion 0 10 2 Clock In PIN AE35 3822 4 77 03 Expansion 010 3 07 PIN AG35 5 7 GPIO0D4 GPIO ExpansionOlojal AC31 6 GPIo0D5 GPlOExpansonOlO S PIN AH32 7
59. 3 GPIO Expansion 0 10 33 PIN AP28 39 034 GPIO Expansion 0 10 34 PIN AW29 40 035 Expansion 0 10 35 PIN AR28 Table 2 14 GPIO Expansion Header JP10 Pin Assignments Schematic Signal Names and Functions Board Reference Schematic Description Sugar Stratix IV GX JP10 Signal Name Pin Number 1 GPIO1 00 GPIO Expansion 1 IO 0 PIN AB27 2 GPIO1 01 GPIO Expansion 1 IO 1 PIN AE25 3 GPIO1 02 GPIO Expansion 1 IO 2 PIN AB28 4 GPIO1 03 GPIO Expansion 1 IO 3 PIN AD25 5 GPIO1 04 Expansion 1 IO 4 27 6 GPIO1 05 GPIO Expansion 1 10 5 PIN AU29 7 GPIO1 06 GPIO Expansion 1 IO 6 PIN AN27 8 GPIO1 D7 Expansion 1 IO 7 AT29 9 GPIO1 08 GPIO Expansion 1 IO 8 PIN AL25 10 GPIO1 09 GPIO Expansion 1 IO 9 Depends on Aw33 13 GPIO1 010 GPIO Expansion 1 10 10 of HSMC AP26 14 GPIO1 011 Expansion 1 IO 11 PIN AW34 15 GPIO1 012 GPIO Expansion 1 10 12 AW31 16 GPIO1 D13 GPIO Expansion 1 10 13 PIN AH24 17 GPIO1 014 GPIO Expansion 1 10 14 AV31 18 GPIO1 015 GPIO Expansion 1 10 15 PIN AG24 19 GPIO1 D16 Expansion 1 10 16 AL27 20 GPIO1 D17 GPIO Expansion 1 10 17 PIN AW27 21 GPIO1 018 GPIO Expansion 1 10 18 PIN AH26 22 GPIO1 019 GPIO Expansion 1 10 19 PIN AW28 23 GPIO1 020 GPIO Expansion 1 10 20 PIN AK27 37 TR4 User Manual www terasic com www terasic com 24 25 26 27 28 31 32 33 34 35 36 37
60. 6 149 150 151 152 155 HSMA CLKOUT p1 HSMA CLKIN p1 HSMA CLKOUT n1 HSMA CLKIN n1 HSMA TX p8 HSMA RX p8 HSMA TX n8 HSMA RX n8 HSMA TX p9 HSMA RX p9 HSMA TX n9 HSMA RX n9 HSMA TX p10 HSMA RX p10 HSMA TX n10 HSMA n10 HSMA TX p11 HSMA RX p11 HSMA TX 11 HSMA n11 HSMA TX p12 HSMA RX p12 HSMA TX n12 HSMA 12 HSMA TX p13 HSMA RX p13 HSMA TX n13 HSMA n13 HSMA TX p14 HSMA RX p14 HSMA TX n14 HSMA 14 HSMA TX p15 HSMA RX p15 HSMA TX n15 HSMA 15 HSMA TX p16 HSMA RX p16 HSMA TX 16 HSMA n16 HSMA OUT p2 Terasic TR4 User Manual www terasic com LVDS TX or CMOS I O LVDS RX or CMOS differential clock input LVDS RX or CMOS I O LVDS RX or CMOS differential clock input LVDS TX bit 8 or CMOS I O LVDS RX bit 8 or CMOS I O LVDS TX bit 8n or CMOS I O LVDS RX bit 8n or CMOS I O LVDS TX bit 9 or CMOS I O LVDS RX bit 9 or CMOS I O LVDS TX bit 9n or CMOS I O LVDS RX bit 9n or CMOS I O LVDS TX bit 10 or CMOS I O LVDS RX bit 10 or CMOS I O LVDS TX bit 10n or CMOS I O LVDS RX bit 10n or CMOS I O LVDS TX bit 11 or CMOS I O LVDS RX bit 11 or CMOS I O LVDS TX bit 11n or CMOS I O LVDS RX bit 11n or CMOS I O LVDS TX bit 12 or CMOS I O LVDS RX bit 12 or CMOS I O LVDS TX bit 12n or CMOS I O LVDS RX bit 12n or CMOS I O LVDS TX bit 13 or CMOS I O LVDS RX bit 13 or CMOS I O LVDS TX bit 13n or CMOS I O LVDS RX bit 13n or CMOS I O LVDS TX bit 14 or CMOS I O LVDS RX bit 14 or CMOS I O
61. 9 mem dq 20 mem dq 21 mem dq 22 mem dq 23 mem dq 24 mem dq 25 mem dq 26 mem dq 27 mem 441 28 mem dq 29 mem dq 30 mem dq 31 mem dq 32 mem dq 33 mem dq 34 dq 35 mem dq 36 mem dq 37 dmq 38 mem dq 39 mem dq 40 mem dq 41 mem dq 42 mem dq 43 Terasic TR4 User Manual www terasic com DDR3 Data 8 DDR3 Data 9 DDR3 Data 10 DDR3 Data 11 DDR3 Data 12 DDR3 Data 13 DDR3 Data 14 DDR3 Data 15 DDR3 Data 16 DDR3 Data 17 DDR3 Data 18 DDR3 Data 19 DDR3 Data 20 DDR3 Data 21 DDR3 Data 22 DDR3 Data 23 DDR3 Data 24 DDR3 Data 25 DDR3 Data 26 DDR3 Data 27 DDR3 Data 28 DDR3 Data 29 DDR3 Data 30 DDR3 Data 31 DDR3 Data 32 DDR3 Data 33 DDR3 Data 34 DDR3 Data 35 DDR3 Data 36 DDR3 Data 37 DDR3 Data 38 DDR3 Data 39 DDR3 Data 40 DDR3 Data 41 DDR3 Data 42 DDR3 Data 43 SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Clas
62. A GXBCLK Bank OL2 REFCLK 14 PCle1 REFCLK downstream Bank QRO REFCLK RO HSMA REFCLK Bank QR1 REFCLK R2 PGM GXBCLK1 Bank QR2 REFCLK_R4 HSMD_CLKIN1 OSC 50 BANK1 HSMD CLKINO gt 50MHz HSMD CLKOUT1 HSMC CLKIN1 HSMC CLKOUT1 HSMC CLKIN2 LVDS Single End HSMF CLKIN2 HSMF CLKOUT1 P OSC 50 BANK3 HSMF CLKINO HSMF CLKOUT2 ee B El ad dn HSMF CLKIN1 _ OSC 50 BANK4 SMA CLKOUT 8 SMA CLKIN 4 HSMA CLKIN2 Efe 3 HSMA CLKIN1 SMA DIFF HSME CLKIN2 Bank 6C CEKO NES HSME CLKOUT1 HSME_CLKIN1 OSC 50 BANK7 LOOP CLKOUT1 LOOP CLKIN1 LS MAX2 I2C SCL LOOP CLKOUTO LOOP CLKINO LOOP CLKOUTO CLK_15p OSC 50 PLL_T1_ LOOP CLKOUT1 CLKOUTOn PLL_T LS_HSMD_SCL 1_FBp Figure 2 24 Clock Connections of the TR4 Note 1 5 and some HSMC A clock signals are connected to Bank 5C If users use 43 Terasic TR4 User Manual www terasic com www terasic com SMA CLKOUT please set HSMC A I O standard to 2 5V 2 SMA GXBCLK input HSMC E and 0 Transceiver Bank GXBL 3 PGM GXBCLK pl nlinput HSMC A PCIEI s Transceiver Bank GXBR 4 HSMD OUTO interface through a level shift so the maximum speed is 60Mbps The Stratix IV GX FPGA consists of 8 dedicated clock input pins and from tho
63. B RX 7 Transceiver RX bit 7 1 4 V PCML 2 3 HSMA GXB TX n7 Transceiver TX bit 7n 1 4 V PCML B3 4 GXB n7 Transceiver RX bit 7n 1 4 V PCML C1 5 GXB TX Transceiver TX bit 6 1 4 V PCML D4 6 GXB RX Transceiver TX bit 6 1 4 V PCML E2 7 HSMA GXB TX n6 Transceiver TX bit 6n 1 4 V PCML D3 8 GXB n6 Transceiver RX bit 1 4 V PCML E1 9 HSMA GXB TX p5 Transceiver TX bit 5 1 4 V PCML K4 10 GXB RX p5 Transceiver RX bit 5 1 4 V PCML L2 11 HSMA GXB TX n5 Transceiver RX bit 5n 1 4 V PCML K3 12 RX n5 JTransceiver RX bit 5n 1 4 V PCML L1 13 HSMA GXB TX p4 Transceiver TX bit 4 1 4 V PCML M4 14 GXB RX p4 Transceiver RX bit 4 1 4 V PCML N2 15 GXB TX n4 Transceiver TX bit 1 4 V PCML M3 16 n4 Transceiver RX bit 1 4 V PCML N1 17 HSMA GXB TX Transceiver TX bit 1 4 V PCML P4 18 GXB Transceiver TX bit 3 1 4 V PCML R2 19 HSMA GXB TX n3 Transceiver TX bit 3n 1 4 V PCML P3 20 GXB RX n3 RX bit 1 4 V PCML R1 21 HSMA GXB TX p2 Transceiver TX bit 2 1 4 V PCML T4 22 GXB RX p2 Transceiver RX bit 2 1 4 V PCML U2 23 HSMA GXB TX n2 Transceiver RX bit 2n 1 4 V PCML 24 n2 RX bit 2n 1 4 V PCML U1 25 HSMA GXB TX Transceiver TX bit 1 1 4 V PCML ABA 26 GXB Transceiver RX bit 1 1 4 V PCML AC2 27 28 29 30 31 32 39 40 41
64. Bank Diagram Due to the limitation of FPGA bank I O distribution and dedicated clock in out pin numbers there are some differences between individual HSMC connectors listed below LVDS Interface On the TR4 board only HSMC ports B C and D support LVDS Each HSMC port provides 18 1 LVDS channel transceivers For LVDS transmitters HSMC ports A and D support 18 true LVDS channels which can run up to 6Gbps The LVDS transmitter on HSMC Port B and C contain true and emulated LVDS channels The emulated LVDS channels use two single ended output buffers and external resistors as shown in Figure 2 12 The associated I O standard of these differential FPGA I O pins in the Quartus II project should be set to LVDS E 3R Emulated LVDS I O data rates can reach speeds up to 1 1Gbps The factory default setting for the Rs resistor will be 0 ohm and the Rp resistor will not be 23 Terasic TR4 User Manual www terasic com www terasi ANOTE RYA assembled for single ended I O standard applications For emulated LVDS transmitters please solder 120 and 170 ohm resistors onto the Rs and Rp positions respectively For the LVDS receivers HSMC Port A B D support true LVDS receivers which can run at 1 6Gbps Unlike HSMC ports A D not all the LVDS receivers in HSMC ports B C support On Chip termination OCT To use these I Os as LVDS receivers the user needs to solder a 100 ohm resistor for input termination as show in Figure 2
65. C Differential Net Reference name of the differential termination resistor HSMB RX p 11 R333 HSMB RX p 12 R318 HSMB RX p 13 R312 HSMB RX p 14 R311 HSMB RX p 15 R303 HSMB RX p 16 R315 HSMB D 1 R332 HSMC RX p 0 R314 HSMC p 1 R316 HSMC RX 2 R330 HSMC RX R341 HSMC RX 4 R329 HSMC p 5 R328 HSMC RX p 6 R309 Terasic TR4 User Manual www terasi 25 www terasic com HSMC RX p 7 R306 HSMC D 1 R310 High speed Serial I O transceiver Interface There are 8 CDR transceiver channels located on the top side of HSMC ports A and E respectively Each CDR transceiver can run up to 6 5Gbps Clock Interface Due to the limitation of the FPGA clock input pin numbers not all the HSMC ports have same clock interface Table 2 9 shows the FPGA clock input pin placement on each HSMC port In addition since FPGA dedicated clock input pins CLK 1 3 8 10 or corner PLL clocks don t support On Chip differential termination please solder input termination resistors on R299 and R300 respectively when using HSMC CLKIN p2 n2 and HSMA CLKIN p2 n2 as LVDS signals Table 2 9 HSMC clock interface distribution HSMC Clock in out pin FPGA Clock Input Pin Placement name HSMA HSMB HSMC HSMD HSME HSMF CLKINO CLK1n 5 1 I O CLK2p CLKOp CLKiip CLK6p CLKIN n1 CLK9n CLK2n CLKOn CLK11n CLK6n CLKIN p2 CLK8p CLK10p CLK4p
66. C Expansion HSMC D HSMC A Transceiver x 8 DVI TXIRX DVI D9RX Prefix Name Prefix Name a HSMC E Transceiver 8 HSMC B XTS Transceiver to SMA HDMI RX Prefix Name Prefix Name HSMC F HSMC C GPIQ LTC2 8 LCD Touch Camera Prefix Name Prefix Name Default Setting Load Setting Save Setting Generate Figure 4 8 HSMC C GPIO share pins option After users select the GPIO option a GPIO Edit button will appear If this is clicked a GPIO Expansion window will pop up for users to select a compatible Terasic daughter card Once a daughter card selected the JP4 header diagram in the upper left hand corner of the window which configures HSMC Port C and GPIO I O standards will adjust automatically to recommend a suitable I O standard for the selected daughter card as shown in Figure 4 9 78 Terasic TR4 User Manual www terasic com www Terasic IR4 Y1 0 0 N DTE RYAN System Configuration ter PROGRAM Board Type 4_230 Project Name CLOCK Switch x 4 LEDx 4 M Button x 4 SSRAM 2MB Temperature Flash 64MB Fan Control OSMA O DDR3 SODIMM OPCIe 1 10 0 Heade Unchange 5M 5M Pixel Camera Prefix Name GPIO 1 Header HSMC D LTM 4 8 LCD and Touch DVI TX R HSMC Expa
67. DS TX bit 15 or CMOS I O LVDS RX bit 15 or CMOS I O LVDS TX bit 15n or CMOS I O LVDS RX bit 15n or CMOS I O LVDS TX bit 16 or CMOS I O LVDS RX bit 16 or CMOS I O LVDS TX bit 16n or CMOS I O LVDS RX bit 16n or CMOS I O LVDS TX or CMOS or differential clock input LVDS RX or CMOS 10 or differential clock input LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS TX or CMOS I O orLVDS or 2 5 V 128 www terasic com AP10 AU7 AL8 AP8 8 AR8 AK9 AT8 AL9 AUS AL10 AT10 AM10 AU10 AH11 AU11 AJ11 AV 11 AG12 AR13 AH12 AT13 AE13 AJ13 AE12 AK13 AF13 AH14 AG13 AJ14 AD13 AE14 AD12 AF14 AL13 AP7 AM13 AH10 14 AJ10 158 Board Reference J15 39 40 41 42 43 44 47 48 49 50 53 54 55 56 59 60 61 62 65 66 67 68 71 72 73 74 77 78 79 80 83 84 85 86 89 HSMB CLKIN n2 differential clock input LVDS RX or CMOS diff
68. FPGA where the MAX II CPLD EPM2210 can access flash for FPP configuration of the FPGA using the PFL Megafunction Table 2 18 lists the flash pin assignments signal names and functions 49 TR4 User Manual www terasic com www terasic com FLASH CLK FLASH RESET n FLASH FLASH ADV FLASH RDY BSY n FLASH WP n FSM WE n FSM OE n FSM D 15 0 FSM A 25 1 pA SSS SS SS FSM A 22 2 FSM D 31 0 FSM OE n FSM WE n BWE n SSRAM ADSC n SSRAM ADSP n SSRAM ADV n SSRAM BE n0 SSRAM BE n1 SSRAM BE n2 SSRAM BE n3 SSRAM CE1 n SSRAM CLK SSRAM MODE SSRAM_CE2 SSRAM CE3 n SSRAM ZZ Figure 2 29 Connection between Flash SSRAM MAXII EPM2210 and the Stratix IV GX FPGA Table 2 18 Flash Memory Pin Assignments Schematic Signal Names and Functions T 22 Stratix IV GX Schematic Signal Description VO Standard Pin Number FSM 7 Address bus 3 0 V PCI X 131 FSMA2 7 Address bus 3 0 FSM A3 JAddressbus 30VPCKX 035 FSM AA 3 0 VPCI X 034 FSM 7 FSM A6 7 JAddressbus 30VPCKX 35 FSM 8 30 PINF33 50 Terasic TR4 User Manual www terasic com www terasic com FSMA9 7 Addressbus 30VPCKX 035 FS
69. Figure 3 5 indicates where you can directly turn all the LEDs on or off individually by selecting them and clicking Light or Unlight 59 Terasic TR4 User Manual www terasic com www terasic com TN 1 b Memory LED3 LED2 LED1 LEDO Toran 3 3 Switches and Push Buttons Choose the Button tab as shown in Figure 3 6 This function is designed to monitor status of switches and buttons from a graphical user interface in real time It can be used to verify the functionality of switches and buttons 60 Terasic TR4 User Manual www terasic com www terasic com Switch BUTTON SW3 SW2 5 1 5 0 Button3 Button2 Button1 Button0 Temperature Button pre pe MB Monitor Button Switch Figure 3 6 Monitoring Switches and Buttons 3 4 Memory Controller The Control Panel can be used to write read data to from the DDR3 SO DIMM Flash SSRAM memory on the TR4 board We will describe how the DDR3 SO DIMM is accessed Click on the Memory tab to reach the tab window shown in Figure 3 7 A 16 bit value can be written into the DDR3 SO DIMM memory by three steps namely specifying the address of the desired location entering the hexadecimal data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 3 8 depicts the result of writing the hexadecimal value 7EFF to location
70. G szConfigList Parameters w VendorID Specify the desired vendor ID A zero value means to ignore the vendor ID wDeviceID Specify the desired device ID A zero value means to ignore the produce ID pdwDeviceNum A buffer to retrieve the number of PCIe card which is matched by the desired vendor ID and product ID szConfigList A buffer to retrieve the device information of PCIe card found which is matched by the desired vendor ID and device ID Return Value Return TRUE if PCle cards are successfully enumeated otherwise FALSE is return PCIE Open Function Open a specified PCle port with vendor ID device ID and matching card index Prototype PCIE HANDLE PCIE Open WORD wVendorID WORD wDevicelD WORD wCardIndex Parameters 107 TR4 User Manual www terasic com www terasic com w VendorID wDevicelID wCardIndex device ID Specify the desired device ID A zero value means to ignore the device ID Specify the desired vendor ID A zero value means to ignore the vendor ID Specify the matching card index a zero based index based on the matching vendor ID and Return Value Returns a handle to present the specified PCIe card A positive value is returned if the PCIe port is opened successfully A value zero means failed to connect the target PCIe card This handle value is used as a parameter for other functions e g PCIE_Re
71. II EPM2210 Through the I2C bus interface the PLL CTRL controller is able to control the Max II device by specifying the desire clock outputs set by the user By changing the IP parameters of the Terasic EXT PLL CTRL IP the external clock output 84 Terasic TR4 User Manual www terasic com WWW ter8Sic COm 2 ANTENA freguency can be adjusted accordingly EXT PLL CTRL SLAVE CIk1 set wr 1 set rd 2 set wr move clk3_rstn clk2_set_rd max_sclk clk3_set_wr MAX2 I2C SCL MAX2 I2C SCL Sbs set rd max 2 05 MAX2 2 SDA MAX2 I2C SDA 2 ce d 2 rstn conf rd cik2 pr cik2 os conf ready clones User define 05 osc_50 2 rstn gt rstn osc 50 rstn Figure 5 2 EXT PLL CTRL Instruction Hardware Ports Table 5 1 lists the EXT PLL CTRL instruction ports Table 5 1 EXT PLL CTRL Instruction Ports osc 50 input System Clock 50 2 Synchronous Reset 0 Module Reset 1 Normal Setting Output Freguency Value Read Back Output Freguency Value Start to Transfer Serial Data postive edge Start to Read Serial Data postive edge Serial Data Transmission is Complete 0 Transmission in Progress 1 Transmission Complete Output Clock to MAX II max sdat Inout Serial Data to from MAX II B The EXT PLL CTRL IP Parameter Setting Users can refer to the following Table 5 2 to s
72. M A10 7 AAddressbus 0VPCKX PINH35 FSM Ai Addresbus 0VPCKX 432 FSM Addresbus 30 VPCKX PIN 33 FSM A13 VAddressbus 30VPCKX PINK3 FSM A14 JAddressbus 0VPCKX PINK3 FSM Ai5 AAddressbus 0 VPCKX PIN FSM 16 7 JAddressbus 30 VPCKX 6 FSM A18 Address bus 3 0 VPCLX AGIG FSM A19 Addressbus 0 VPCKX H32 FSM A20 Address bus 3 0 VPCLX 0000 FSM A21 JAddressbus 30VPCKX FSM A22 Addressbus 0VPCKX PINF35 FSM A23 Addressbus PIN N31 0 FSM 7 Addresbus 000 FSM A25 Addressbus 30 M30 0 FSM DO Databus 30VPCKX PINB32 FSMDi Databus 3 0VPCKX PINC32 FSM D2 patabbus 3 0 FSM 03 Databus 3 0 FsmD4 Databus 30 FSM 05 Databus 3 0VPCKX PINK29 FSM D6 Databus 00 FSM 08 Databus 0 PINM29 FSM D9 Databus 29 FSM Databus 3 0 VPCI X 9 FSM Dii Databus 7 FSM 012 Databus PINAM7 FSM Di3 Databus 30
73. Mon Dec 12 14 23 56 2011 Info Quartus II 32 bit Programmer was successful errors warnings Info Peak virtual memory 341 megabytes Info Processing ended Mon Dec 12 14 23 56 2611 Info Elapsed time 99 99 38 Info Total CPU time on all processors 00 00 06 Erase flash please wait a few minutes Using cable USB Blaster USB device 1 instance 6x80 Resetting and pausing target processor OK Checksums took 6 4s npalagggg 77 Erasing Figure 2 7 Erasing Flash 7 Programming Flash Nios II EDS 11 1 gcc3 Info Processing started Dec 12 14 29 00 2011 Info Command quartus c USB BlasterlUSB 81 m jtag o p tr4 default flash loader sof Info 213945 Using programming cable USB Blaster USB 6 Info 2138011 Using programming file tr4 default flash loader sof with checksum x 79EA74D for device EP4SGX230KF4U0 91 289060 Started Programmer operation at Mon Dec 12 14 29 06 2011 2899016 Configuring device index 1 20981727 Device 1 contains JTAG ID code 0 024090 289087 Configuration succeeded 1 devices configured 289911 Successfully performed operation s 289061 Ended Programmer operation at Dec 12 14 29 27 2011 Info Quartus II 32 bit Programmer vas successful errors Info Peak virtual memory 341 megabytes Info Processing ended Mon Dec 12 14 29 27 2611 Info Elapsed time 00 00 27 Info Total CPU time on all processors
74. Other o Temperature sensor o FPGA cooling fan Terasic TR4 User Manual www terasic com www terasic com ANU S RYA 1 3 Board Overview Figure 1 1 and Figure 1 2 show the top and bottom view of the TR4 board It depicts the layout of the board and indicates the location of the connectors and key components Users can refer to these figures for relative location when the connectors and key components are introduced in the following chapters USB Besler DDR3SO DIMM HSMC 64MB support up to 4GB Port Flash 19V DC Power 2 SSRAM Supply 1 1 HSMC Port A JTAG Heade STRATIX IV GX EP4SGX230KF40C2 or EP4SGX530KH40C2 PCle 1 Connector Fan Connector HSMC Port B JTAG DIP Switches 4 User LEDs 4 Slide Switches Re config 4 Push Buttons HSMC Port F Clock Push Button Input Output MAX II Reset SMA Connectors Push Button Figure 1 1 TR4 Board View Top Terasic TR4 User Manual www terasic com Groups Voltage Level Indicator LEDs Groups Voltage Level Setting Header MAX II CPLD EPM2210 System Controller Three External PLLs PCIe 0 Connector 50MHz Oscillator Two 40 Pin GPIO Connectors HSMC Port C www terasic com 3 3V HSMC Fuse HSMC Port 0 HSMC Port A HSMC Port C HSMC Port B 12V HSMC Fuse Figure 1 2 TR4 Board View Bottom 1 4 Block Diagram Figure 1 3 shows the
75. PCI X PIN C34 FSM A8 Address bus A6 3 0 V PCI X PIN F33 FSM A9 Address bus A7 3 0 V PCI X PIN G35 FSM A10 Address bus A8 3 0 V PCI X PIN H35 FSM A11 Address bus A9 3 0 V PCI X PIN J32 FSM A12 Address bus A10 3 0 V PCI X PIN J33 FSM A13 Address bus A11 3 0 V PCI X PIN K32 FSM A14 Address bus A12 3 0 V PCI X PIN K31 FSM A15 Address bus A13 3 0 V PCI X PIN AH17 FSM A16 Address bus A14 3 0 V PCI X PIN AH16 FSM A17 Address bus A15 3 0 V PCI X PIN AE17 FSM A18 Address bus A16 3 0 V PCI X PIN AG16 FSM A19 Address bus A17 3 0 V PCI X PIN H32 FSM A20 Address bus A18 3 0 V PCI X PIN H34 FSM A21 Address bus A19 3 0 V PCI X PIN G33 FSM A22 Address bus A20 3 0 V PCI X PIN F35 FSM DO Data bus 3 0 V PCI X PIN B32 FSM D1 Data bus 3 0 V PCI X PIN C32 FSM D2 Data bus 3 0 V PCI X PIN C31 FSM D3 Data bus 3 0 V PCI X PIN F32 FSM D4 Data bus 3 0 V PCI X PIN J30 FSM D5 Data bus 3 0 V PCI X PIN K29 FSM D6 Data bus 3 0 V PCI X PIN K30 FSM D7 Data bus 3 0 V PCI X PIN L29 Terasic TR4 User Manual www terasic com 52 www terasic com FSM D8 FSM D9 FSM D10 FSM D11 FSM D12 FSM D13 FSM D14 FSM D15 FSM D16 FSM D17 FSM D18 FSM D19 FSM D20 FSM D21 FSM D22 FSM D23 FSM D24 FSM D25 FSM D26 FSM D27 FSM D28 FSM D29 FSM D30 FSM D31 FSM OE n OE n FSM WE n BWE n SSRAM ADSC n SSRAM ADSP n SSRAM ADV n SSRAM BE SSRAM BE n1 SSRAM BE n2 SSRAM BE n3 SSRAM n SSRAM CLK SSRAM MODE SSRAM GW n SRAM CE2 SSRAM CE3 n SSRAM ZZ Data bus
76. PLLAdemo batch batch file folders include the following files Batch File TRA EXT PLL bat FPGA Configuration File TR4 EXT PLL sof B Demonstration Setup Terasic TR4 User Manual www terasic com Make sure Quartus II is installed on your PC 88 www terasic com 7168 e Connect the USB Blaster cable to the board host PC Install the USB Blaster driver if necessary e Power on the board Execute the demo batch file TR4 EXT PLL bat under the batch file folder EXT PLINdemo batch Press BUTTONO to configure the external PLL chips via MAX CPLD 5 3 High Speed Mezzanine Card HSMC The HSMC loopback demonstration reference design observes the traffic flow with an HSMC loopback adapter which provides a quick way to implement your own design utilizing the transceiver signals situated on the HSMC interface This design also helps you verify the transceiver signals functionality for ports A and E of the HSMC interface A total of 8 transceiver pairs on the HSMC Port A and port E each are tested HSMC Port A Loopback Test B Demonstration Source Code Quartus Project directory TR4 HSMA LOOPBACK TEST FPGA Bit Stream TRA HSMA LOOPBACK TEST sof B Demonstration Setup e Check that Quartus II and Nios II are installed on your PC e Insert the HSMC loopback adapter onto HSMC Port e Connect the USB Blaster cable to the board and host PC Install the USB Blaster driver if n
77. Port E present D14 HSMC Port D present D15 HSMC Port A present D20 HSMC Port C Present D27 HSMC Port B Present D28 HSMC Port F Present D16 USB Blaster Circuit www terasic Com Table 2 2 LED Indicators Description Default OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF These LEDs are lit when HSMC Port A B C D E F have board or cable plugged in such that pin 160 becomes grounded This LED is lit when the USB blaster circuit transmits or receives data www terasic com D17 MAX LOAD D18 MAX ERROR D19 MAX CONF DONEn D33 19V POWER 01 012 HSMC VCCIO LED This LED is lit when the FPGA is being actively configured This LED is lit when the MAX II CPLD EPM2210 System Controller fails to configure the FPGA This LED is lit when the FPGA is successfully configured This LED is lit after the 19V adapter is plugged in These LEDs indicate the I O standard of the HSMC ports see Table 2 12 2 4 General User Input Output B Push buttons The TR4 includes six push buttons that allow you to interact with the Stratix IV GX FPGA Each of these buttons is debounced using a Schmitt Trigger circuit as indicated in Figure 2 10 Each push button provides a high logic level or a low logic level when it is not pressed or pressed respectively active low Table 2 3 lists the board references signal names and their corresponding Stratix IV GX device pin numbers Before depressed poem releas
78. TL 15 Class DDR3 On die termination 1 SSTL 15 Class DDR3 Row ADDRess Strobe SSTL 15 Class DDR3 Write Enable SSTL 15 Class DDR3 Temperature Event SSTL 15 Class DDR3 Reset SSTL 15 Class I DDR3 I2C Serial Clock 1 5V DDR3 I2C Serial Data Bus 1 5V RYAN Stratix 1 V PIN F26 PIN G26 PIN D24 PIN M27 PIN R18 PIN J18 PIN H19 PIN P18 DDR3 CLK 1 0 DDR3 CLKIn1 0J DDR3 BA 2 0 DDR3 ODT 1 0 DDR3 CS n 1 0 DDR3 RESET n DDR3 EVENT n DDR3 DQ 63 0 DDR3 DOSI7 0J DDR3 DQSn 7 0 DDR3 ADDR 15 0 DDR3 DN 7 0 DDR3 CKE 1 0 DDR3 WE n DDR3 CAS n DDR3 RAS n DDR3 SDA DDR3 SCL Figure 2 23 Connection between DDR3 and Stratix IV GX FPGA Circuitry B Stratix IV GX FPGA Clock Inputs and Outputs The TR4 development board contains three types of clock inputs which include 26 global clock input pins external PLL clock inputs and transceiver reference clock inputs The clock input sources of the Stratix IV GX FPGA originate from on board oscillators a SOMHz driven through the clock buffers as well as other interfaces including HSMC GPIO expansion headers share pins with HSMC Port C and SMA connectors The overall clock distribution of the TR4 is presented in Figure 2 24 42 Terasic TR4 User Manual www terasic com www terasic com Output 100MHz HSME REFCLK Bank OL1 gt REFCLK L2 a 0 gt REFCLK Bank QLO REFCLK LO SM
79. TR4 board and USB Blaster is not established or the TR4 board is not powered on before running the ControlPanel exe the Control Panel will fail to detect the FPGA and a warning message window will pop up as shown in Figure 3 3 57 Terasic TR4 User Manual www terasic com www terasic com to find TR4 Please make sure TR4 and C are connected by an USB cable 5 TR4 is powered on Figure 3 3 The TR4 Control Panel Fails to Download sof File The concept of the TR4 Control Panel is illustrated in Figure 3 4 The Control Codes which performs the control functions is implemented in the FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical user interface is used to issue commands to the control codes It handles all reguests and performs data transfer between the computer and the TR4 board 58 Terasic TR4 User Manual www terasic com www terasic com TR4 Board Flash DDR3 SO DIMM FPGA External an a mo Monitor LEDs Buttons Switches Figure 3 4 TR4 Control Panel Block Diagram The TR4 Control Panel can be used to illuminate the LEDs monitoring buttons switches status read write from various memory types in addition to testing various components of the TR4 board 3 2 Controlling the LEDs One of the functions of the Control Panel is to set up the status of the LEDs The tab window shown in
80. User Manual www terasic com www terasic com The clock freguency for the programmable clock generators can be specified by using the TR4 control panel TR4 system builder or the external clock generator demo provided The associated pin assignments for clock buffer and SMA connectors to pins are shown in Table 2 20 Table 2 20 Clock Inputs Outputs Pin Assignments Schematic Signal Names and Functions Board Schematic Description VO Standard Stratix IV GX Reference Signal Name Pin Number U49 4 OSC 50 Dedicated 50MHz clock 2 5 AB34 input for bank 1C U21 4 OSC 50 BANK3 50MHz clock input for 2 5 V AW22 bank 3C U20 4 OSC 50 BANK4 50MHz clock input for 2 5 V AV19 bank 4C U12 4 OSC 50 BANK7 50MHz clock input for 1 5 V A21 bank 7C U13 4 OSC 50 BANK8 50MHz clock input for 1 5 V B23 bank 8 U11 6 HSMA REFCLK p HSMC A transceiver LVDS AA2 reference clock input U11 5 HSMA REFCLK n HSMC A transceiver LVDS AA1 reference clock input U5 6 HSME REFCLK p HSMC E transceiver LVDS AA38 reference clock input U5 5 HSME REFCLK n HSMC E transceiver LVDS AA39 reference clock input J20 SMA CLKOUT p SMA differential clock 2 5 or LVDS AC11 output J19 SMA CLKOUT n SMA differential clock 2 5V or LVDS AC10 output J16 SMA SMA transceiver LVDS J38 reference clock input J17 SMA_GXBCLK_n SMA transceiver LVDS J39 reference clock input J21 SMA_CLKIN SMA clock input 2 5V AW19 2 9 PCI Ex
81. VDS or 2 5 V LVDS TX bit 4n or CMOS 134 LVDS 2 5 V www terasic com U38 T37 U39 AB36 AC38 AB37 AC39 AD36 AE38 AD37 AE39 C12 C13 V12 W8 V11 W7 V10 V6 V9 U5 T10 R6 R10 R5 U10 R7 T9 P6 R9 N6 R8 N5 N9 N8 P8 74 77 78 79 80 83 84 85 86 89 90 91 92 95 96 97 98 101 102 103 104 107 108 109 110 113 114 115 116 HSME n4 HSME TX 5 HSME RX p5 HSME TX n5 HSME RX n5 HSME TX p6 HSME RX p6 HSME TX n6 HSME RX n6 HSME TX p7 HSME RX p7 HSME TX n7 HSME n7 HSME CLKOUT HSME CLKIN p1 HSME CLKOUT n1 HSME CLKIN n1 HSME TX p8 HSME RX p8 HSME TX n8 HSME RX n8 HSME TX p9 HSME RX p9 HSME TX n9 HSME RX n9 HSME TX p10 HSME RX p10 HSME TX n10 HSME RX n10 Terasic TR4 User Manual Pi RX bit 4n or CMOS vps or 2 5 V LVDS TX bit 5 or CMOS I O LVDS or 2 5 V LVDS RX bit 5 or CMOS I O LVDS or 2 5 V LVDS TX bit 5n or CMOS 5 V LVDS or 2 5 RX bit 5n or CMOS Vps or 2 5 V LVDS TX bit 6 or CMOS I O LVDS or 2 5 V LVDS RX bit 6 or CMOS I O LVDS or 2 5 V LVDS TX bit 6n CMOS 5 V LVDS 2 5 i RX bit or CMOS Vps or 2 5 V LVDS TX bit 7 or CMOS I O LVDS or 2 5 V LVDS RX bit 7 or CMOS I O LVDS or 2 5 V LVDS TX bit 7n or CMOS LVD 2 5 V lO S or 2 5 LVDS RX bit 7n or CMOS vps or 2 5 V LVDS TX or CMOS I O LVDS or 2 5 V Eyes RX or GMOS
82. X n3 HSME TX p4 HSME RX p4 HSME TX n4 Terasic TR4 User Manual www terasic com Transceiver RX bit 2 Transceiver RX bit 2n Transceiver RX bit 2n Transceiver TX bit 1 Transceiver RX bit 1 Transceiver TX bit 1n Transceiver RX bit 1n Transceiver TX bit 0 Transceiver TX bit 0 Transceiver TX bit On Transceiver RX bit On CMOS I O Dedicated clock input LVDS TX or CMOS I O LVDS RX or CMOS I O LVDS TX or CMOS I O LVDS RX or CMOS I O 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS TX bit 0 or CMOS I O LVDS or 2 5 V LVDS RX bit 0 or CMOS I O LVDS or 2 5 V LVDS TX bit On or CMOS LVDS RX bit On 5 LVDS or 2 5 V LVDS or 2 5 V LVDS TX bit 1 or CMOS I O LVDS or 2 5 V LVDS RX bit 1 or CMOS I O LVDS or 2 5 V LVDS TX bit 1n or CMOS LVDS RX bit 1n or 5 LVDS or 2 5 V LVDS or 2 5 V LVDS TX bit 2 or CMOS I O LVDS or 2 5 V LVDS RX bit 2 or CMOS I O LVDS or 2 5 V LVDS TX bit 2n or CMOS LVDS RX bit 2 or CMOS LVDS or 2 5 V LVDS or 2 5 V LVDS TX bit 3 or CMOS I O LVDS or 2 5 V LVDS RX bit 3 or CMOS I O LVDS or 2 5 V LVDS TX bit 3n or CMOS LVDS RX bit 3n or CMOS LVDS or 2 5 V LVDS or 2 5 V LVDS TX bit 4 or CMOS I O LVDS or 2 5 V LVDS RX bit 4 or CMOS I O L
83. ad32 Users need to call PCIE_Close to release handle once the handle is not used anymore PCIE_Close Function Close a handle associated to the card Prototype void PCIE_Close PCIE HANDLE hPCIE Parameters hPCIE A PCIe handle return by PCIE Open function Return Value None PCIE Read32 Function Reads 32 bit data from the FPGA board Prototype bool PCIE Read32 PCIE HANDLE hPCIE PCIE BAR PcieBar PCIE ADDRESS PcieAddress DWORD pdwData Parameters hPCIE 108 Terasic TR4 User Manual www terasic com www terasic com A PCIe handle return by PCIE Open function PcieBar Specify the target BAR PcieAddress Specify the target address in FPGA pdwData A buffer to retrieve the 32 bit data Return Value Return TRUE if read data is successful otherwise FALSE is returned PCIE Write32 Function Write a 32 bit data to the FPGA Board Prototype bool PCIE Write32 PCIE HANDLE hPCIE PCIE BAR PcieBar PCIE ADDRESS PcieAddress DWORD dwDoata Parameters hPCIE A PCIe handle return by PCIE Open function PcieBar Specify the target BAR PcieAddress Specify the target address in FPGA dwData Specify a 32 bit data which will be written to the FPGA board Return Value Return TRUE if write data is successful otherwise FALSE is returned PCIE DmaRead Function Read data from
84. al www terasic com www terasic com ANU S RYA e Shares pins with HSMC Port e Configurable I O standards 1 5V 1 8V 2 5V 3 0V Power e Standalone DC 19V input Other e Temperature Sensor e Cooling Fan 10 Terasic TR4 User Manual www terasic com www terasic col m Chapter 2 Using the Board This chapter gives instructions for using the TR4 board and its components It is strongly recommended that users read the Getting Started Guide pdf before operating the TR4 board The document is located in the Usermanual folder on the TR4 System CD The contents of the document include the following Introduction to the TR4 Development Board TR4 Development Kit Contents Key Features Before You Begin Software Installation Development Board Setup Programming the Stratix IV GX Device Programming through Flash 2 1 Configuration Options B JTAG FPGA Programming with USB Blaster The USB blaster is implemented on the TR4 board to provide a JTAG configuration through the on board USB to JTAG configuration logic through the type B USB connector an FTDI USB 2 0 PHY device and an Altera MAX II CPLD For this programming mode configuration data will be lost when the power is turned off 11 Terasic TR4 User Manual www terasic com www terasic com To download a configuration bit stream into the Stratix IV GX FPGA perform the following steps Make sure that power is provided to
85. ard Reference Schematic Signal J14 39 40 41 42 43 44 47 48 49 50 53 54 55 56 59 60 61 62 65 66 67 68 71 72 73 74 77 78 79 80 83 84 85 86 89 90 91 92 95 96 HSMB OUTO HSMB CLKINO HSMB DO HSMB D1 HSMB D2 HSMB D3 HSMB TX pO HSMB RX pO HSMB TX nO HSMB RX nO HSMB TX p1 HSMB RX p1 HSMB TX n1 HSMB RX n1 HSMB TX p2 HSMB RX p2 HSMB TX n2 HSMB RX n2 HSMB TX p3 HSMB RX p3 HSMB TX n3 HSMB RX n3 HSMB TX p4 HSMB RX p4 HSMB TX n4 HSMB RX n4 HSMB TX p5 HSMB RX p5 HSMB TX n5 HSMB RX n5 HSMB TX p6 HSMB RX p6 HSMB TX n6 HSMB RX n6 HSMB TX p7 HSMB RX p7 HSMB TX n7 HSMB RX n7 HSMB CLKOUT HSMB CLKIN p1 Terasic TR4 User Manual Description CMOS I O Dedicated clock input LVDS TX or CMOS I O LVDS RX or CMOS I O LVDS TX or CMOS I O LVDS RX or CMOS I O LVDS TX bit 0 or CMOS I O LVDS RX bit 0 or CMOS I O LVDS TX bit On or CMOS I O LVDS RX bit On or CMOS I O LVDS TX bit 1 or CMOS I O LVDS RX bit 1 or CMOS I O LVDS TX bit 1n or CMOS I O LVDS RX bit 1n or CMOS I O LVDS TX bit 2 or CMOS I O LVDS bit 2 or CMOS I O LVDS TX bit 2n or CMOS I O LVDS RX bit 2n or CMOS I O LVDS TX bit or CMOS I O LVDS RX bit 3 or CMOS I O LVDS TX bit 3n or CMOS I O LVDS RX bit or CMOS I O LVDS TX bit 4 or CMOS I O LVDS RX bit 4 or CMOS I O LVDS TX bit 4n or CMOS I O LVDS RX bit or CMOS I O LVDS TX bit 5 or CMOS I O LVDS RX bit 5 or CMOS I O LVDS TX bit 5n or CMOS I O
86. ation based on this DLL User Application TERASIC PCIE dll wdapi921 dll User Mode Kernel Mode windrvr6 sys TERASIC PCIE inf TERASIC Jungo Driver Figure 6 8 PCI Express Software Stack B Install PCI Express Driver To install the PCI Express driver execute the steps below 1 From the TR4 system CD locate the PCIe driver folder in the directory CDROMdemonstrations device PCIe SDK Driver 2 Double click the PCIe DriverInstall exe executable file to launch the installation program shown in Figure 6 9 104 Terasic TR4 User Manual www terasic com www terasic com Figure 6 9 PCle Driver Installation Program 3 Click Install to begin installation process It takes several seconds to install the driver When installation is complete the following dialog window will popup shown in Figure 6 10 Click OK and then Exit to close the installation program Iprasic Driver Information Congratulations 1 The PCIe driver has installed successfully Figure 6 10 PCle Driver Installed Successfully 5 Once the driver is successfully installed users can view the device under the device manager window shown in Figure 6 11 105 Terasic TR4 User Manual www terasic com www terasic com Devee Manager File Action View 39 65 9 mIa E 4 Computer Disk drives Display adapters 9 9 Human Interface De
87. aunching TR4 Control Panel In addition before the TR4 control panel is launched it is imperative that the fan is installed on the Stratix IV GX device to prevent excessively high temperatures on the FPGA To activate the Control Panel perform the following steps e sure Quartus II and Nios II are installed successfully on your PC e Connect the supplied USB cable to the USB Blaster port and the supplied power cord to J4 Turn the power switch ON e Verify the connection on the USB blaster is available and not occupied or used between Quartus and TR4 Start the executable ControlPanel exe on the host computer Figure 3 1 will appear and the Control Panel starts to auto detect the FPGA and download the sof files After the configuration file is programmed to the TR4 board the FPGA device information will be displayed on the window 55 Terasic TR4 User Manual www terasic com www terasic com RYA Note The Control Panel will occupy the USB port users will not able to download configuration file into the FPGA before you exit the Control Panel program Vi TM teste Panel Figure 3 1 Download sof Files to the board The Control Panel is now ready as shown in Figure 3 2 56 Terasic TR4 User Manual www terasic com www terasic com n n LED2 LED1 LEDO TIA Figure 3 2 Control Panel is Ready If the connection between
88. block diagram of the TR4 board To provide maximum flexibility for the users all key components are connected with the Stratix IV GX FPGA device allowing the users to implement any system design Terasic 4 User Manual www terasic com www terasic com GPIO fee FPGA FLASH 512Mb HSME amp SSRAM 2MB e I DDR3 SODIMM 4GB 5 26 2 HSMA X8 gt X4 0 X82 HSMD X4 95684 Stratix I V 2 HSMC pos LED X4 Button X4 SMA CLK OUT 9 gi SMA GXBCLK l sma Figure 1 3 TR4 Block Diagram Slide SW X4 Below is more detailed information regarding the blocks in Figure 1 3 Stratix IV GX FPGA EPASGX230C2 o 228 000 logic elements LEs 17 133K total memory Kb 1 288 18x18 bit multipliers blocks 2 PCI Express hard IP blocks 744 user I Os 8 phase locked loops PLLs 1 51 Terasic TR4 User Manual www terasic com www ter e EP4SGX530C2 O O 531 200 logic elements LEs 27 376K total memory Kb 1 024 18x18 bit multipliers blocks 4 PCI Express hard IP blocks 744 user I Os 8 phase locked loops PLLs Configuration Device and USB Blaster Circuit e MAXII CPLD EPM2210 System Controller and Fast Passive Parallel FPP configuration e On board USB Blaster for use with the Quartus II Programmer e Programmable PLL timing chip conf
89. cation Software Image Demo exe e FPGA Configuration File TRA 0 imageprocess sof e PCIe Library TERASIC PCIE DLL e Demo Batch File TRA PCIeO imageprocess bat B Demonstration Setup e Make sure and PC are powered off e Plug the PCIe adapter card into PCIe slot on the PC e Use the PCIe cable to connect the PCIEO connector and PCIe adapter card as shown in Figure 6 12 Power on your PC e After the Windows OS desktop shows up Download the PCIeO Imageprocess sof into the TR4 using the Quartus II Programmer 118 11 51 Terasic TR4 User Manual www terasic com www terasic coi ANOTE RYA e Restart Windows e Installed PCIe driver if necessary The driver is located in the folder PCIe _SDK Driver e Launch demo program PCIe Image Demo exe Terasic TR4 PCIe Image Demo 11 0 1 www terasic com Download Image Process Image Upload Image Figure 6 16 PCle Image Demo GUI Click Select Image to select a bitmap or jpeg file for image processing Terasic TR4 PCIe Image Demo V1 0 T www Lterasic com Dow Figure 6 17 PCle Image Demo Selected Image e Click Download Image to download image raw data into the local memory of FPGA e Click Process Image to trigger the invert image process e Click Upload Image to upload an image to PC from local memory of FPGA to be displayed on the window demo appl
90. clk3 set wr set 140 setting trigger conf wr conf wr SOMHz conf rd 1T 50MHz status conf ready 2 wire interface max sclk MAX2 RC SCL max sdat MAX2 I2C SDA If dynamic PLL configuration is required users need to modify the code according to users desired PLL behavior 81 Terasic TR4 User Manual www terasic com www terasic com Chapter 5 Examples of Advanced Demonstration This chapter introduces several advanced designs that demonstrate Stratix IV GX features using the TR4 board The provided designs include the major features on board such as the HSMC comnectors PCIe and DDR3 For each demonstration the Stratix GX FPGA configuration file is provided as well as full source code in Verilog HDL All of the associated files can be found in the demonstrations tr4_ lt Stratix device folder from the System CD For each of demonstrations described in the following sections we give the name of the project directory for its files which are sub directories of the demonstrationsNr4 Stratix device folder 5 1 Breathing LEDs This demonstration shows how to use the FPGA to control the luminance of the LEDs by means of dividing frequency By dividing the frequency from 50 MHz to 1 Hz you can see LED flash once per second B Design Tools e Quartus II 11 1 B Demonstration Source Code e Project directory Breathing LEDs e Bit stream used
91. ction Under a read operation the Terasic PCIe IP issues a read signal followed by the address of the data Once the address is received a 32 bit data will be sent along with a read valid signal Under a write operation the PCIe IP issues a write signal along with the address to be written A 32 bit data is written to the corresponding address with a data enable signal of write operation All the write commands are issued on the same clock cycle Table 6 1 lists the associated port names along with the description Table 6 1 Single Cycle Transaction Signals of Terasic PCIe IP Name Type Polarity Description oCORE Output Clock reference clock output of PCle local interface F 7 1 oSC RD ADDR 11 0 Output Address bus of read transaction It is a 32 bit data address iSC RD DATA 31 0 Input Read data bus oSC RD READ Output High Read signal iSC RD DVAL Input High Read data valid 0SC WR ADDR 11 0 Output Address bus of write transaction It is 32 bit data address oSC WR DATA 31 0 Output Write data bus oSC WR WRITE Output High Write signal 99 Terasic TR4 User Manual www terasic com www terasic com 1 1 1 i i2 4 j 9 6 N V NY Ny NV NY _ 1 1 Tm oSC RD READ N 1 iSC RD DVAL
92. ctor on the top side of the TR4 If there is no connection established on the HSMC connectors the 4 position DIP switch SW4 or SW6 should be set to Off so the JTAG signals on the HSMC connectors are bypassed illustrated in Figure 2 16 When JP7 Header Connected HSMC Included In JTAG Chain TR4 Board JP7 Header DO Lo Eo i Bl Bi ERA HSMD HSMD HSMC HSMC Top Bottom Bottom TDO TDI z 1DO TDI a TDO TDI z TDO TDI m TDO TDIR TDO TDI HSMA HSMA HSMB HSMB Bottom Top Bottom Top Sw6 SW5 SW4 Figure 2 16 JTAG Chain for Standalone TR4 If the HSMC based daughter card connected to the HSMC connector uses the JTAG interface the 4 position DIP switch SW4 or SW6 should be set to On according to the HSMC port used In this case from Figure 2 17 HSMC Port D is used so position 4 of the SW4 switch is set to On Similarly if the JTAG interface isn t used on the HSMC based daughter card position 4 of SW4 is set to Off thus bypassing the JTAG signals as shown in Figure 2 18 31 Terasic TR4 User Manual www terasic com www terasic com TDI TDO Daughter When JP7 Header Connected HSMC Included In JTAG Chain TR4 Board JP7 Header TDI ui M Pr gt iiri ir iiir gt ATERA HSMD HSMD HSMC NDTERYA Bottom Bottom TDO TDI f TDO TDI a TDO TDI 4
93. e 2 1 lists the position of the DIP switches and their associated interfaces Note that if the JTAG interface on HSMC connector is enabled make sure that the active JTAG chain must be a closed loop or the FPGA may not be detected Section 2 5 will give an example on how to extend the JTAG interface to a daughter card Also a document named Using_Mult TR4_system pdf in TR4 system CD shows how to connect the JTAG interface on two stacked TR4 boards 18 TR4 User Manual www terasic com www terasic com Components Name position 1 HSMCA TOP position 2 HSMCB position HSMCC TOP position 4 TOP position 1 5 BOT SW5 position 2 HSMCB BOT position 3 HSMCC BOT position 4 HSMCD BOT SW6 position 1 HSMCE position 2 HSMCF TOP Table 2 1 JTAG Control Description ON ON ON ON ON ON ON ON ON ON 2 3 Status Elements HSMA TOP in chain HSMB TOP in chain HSMC TOP in chain HSMD TOP in chain HSMA BOT in chain HSMB BOT in chain HSMC BOT in chain HSMD BOT in chain HSME TOP in chain HSMF TOP in chain OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF Bypass HSMA TOP Bypass HSMB TOP Bypass HSMC TOP Bypass HSMD TOP Bypass HSMA BOT Bypass HSMB BOT Bypass HSMC BOT Bypass HSMD BOT Bypass HSME TOP Bypass HSMF TOP The TR4 includes status LEDs Please refer Table 2 2 for the status of the LED indicator Board LED name Reference D13 HSMC
94. ecessary Power on the board e Program the using TRA HSMA LOOPBACK TEST sof through Quartus programmer Press BUTTONO of the TR4 board to initiate the verification process e LED 3 0 will flash indicating the loopback test passed HSMC Port E Loopback Test 89 TR4 User Manual www terasic com www terasic com ANOTE RYA B Demonstration Source Code Quartus Project directory TR4 HSME LOOPBACK TEST FPGA Bit Stream HSME LOOPBACK TEST sof B Demonstration Setup e Check that Quartus II and Nios II are installed on your PC e Insert the HSMC loopback daughter card onto the HSMC Port E as shown in Figure 5 5 e Connect the USB Blaster cable to the TR4 board and host PC Install the USB Blaster driver if necessary e Power on the TR4 board e Program the TR4 using HSME LOOPBACK TEST sof through Quartus II programmer Press BUTTONO on the TR4 board to initiate the verification process e LED 3 0 will flash once to indicate the loopback test passed Figure 5 5 HSMC Loopback Design Setup 90 Terasic TR4 User Manual www terasic com www terasi ANU S RYA 5 4 DDR3 SDRAM 1GB Many applications use a high performance RAM such as a DDR3 SDRAM to provide temporary storage In this demonstration hardware and software designs are provided to illustrate how the DDR3 SDRAM SODIMM on the can be accessed We describe how the Alt
95. ed Debouncing LJ LILI Ly Schmitt Trigger Debounced gt Figure 2 10 Push button Debouncing Table 2 3 Push button Pin Assignments Schematic Signal Names and Functions Name Locate Description VO Standard Stratix IV GX Pin Number PB3 BUTTON3 Lowwhenpushed 15V PIN P20 PB4 BUTTON2 Activelow 15 PIN A19 PB5 BUTTONI 19 Terasic TR4 User Manual www terasic com 20 www terasic com PB6 BUTTONO 1 5V PIN L19 The MAX RSTN push button is used to reset the MAX II EPM2210 CPLD The Config push button can configure default code to FPGA Table 2 4 lists the board references signal names and their corresponding Stratix IV GX device pin numbers Table 2 4 Push button Pin Assignments Schematic Signal Names and Functions Name Locate Description VO EPM2210 Pin Number Standard PB1 MAX RSTn reset 3 3V VTTL PIN M9 PB2 CONFIG FPGAreconfig 3 3V VTTL PIN D12 B Slide Switches There are four slide switches on the TR4 to provide additional FPGA input control Each switch is connected directly to a pin of the Stratix IV GX FPGA When a slide switch is in the DOWN position or the UP position it provides a low logic level or a high logic level VCCIO HSMF or VCCIO HSMA to the FPGA respectively Table 2 5 lists the board references signal names and their corresponding Stratix IV GX device pin numbers Table 2 5 Slide S
96. ed clock input LVDS or 2 5 V AA35 41 HSMD LVDS TX or CMOS I O LVDS or2 5 V AJ29 42 HSMD D1 LVDS RX or CMOS I O LVDS 2 5 AR31 43 HSMD D2 LVDS TX or CMOS I O LVDS or2 5 V 29 44 HSMD D3 LVDS RX or CMOS I O LVDS or2 5 V 0 47 HSMD TX p0 LVDS TX bit 0 or CMOS I O 1 25 129 48 HSMD RX p0 LVDS RX bit 0 or CMOS LVDS 2 5 AT31 49 HSMD TX nO LVDS TX bit On or CMOS I O LVDS or 2 5 29 50 HSMD RX nO LVDS RX bit or CMOS I O LVDS or 2 5 V 1 53 HSMD TX p1 LVDS TX CMOS LVDS 2 5 30 54 HSMD LVDS bit 1 CMOS LVDS 2 5 32 55 HSMD TX LVDS TX bit 1n or CMOS I O LVDS 2 5 AL30 56 HSMD RX n1 LVDS RX bit 1n or CMOS I O LVDS or 2 5 V AU32 59 HSMD TX p2 LVDS TX bit 2 or CMOS LVDS or 2 5 AK32 60 HSMD RX p2 LVDS RX bit 2 or CMOS LVDS 2 5 AT33 61 HSMD TX n2 LVDS TX bit 2n or CMOS I O LVDS or2 5 V AL32 62 HSMD RX n2 LVDS RX bit 2n or CMOS I O LVDS or 2 5 V AUS33 65 HSMD TX p3 LVDS TX bit 3 or CMOS LVDS 2 5 AJ31 66 HSMD RX p3 LVDS bit 3 or CMOS LVDS or 2 5 AU34 67 HSMD TX n3 LVDS TX bit or CMOS I O LVDS or 2 5 0 68 HSMD RX n3 LVDS RX bit or CMOS I O LVDS or 2 5 4 71 HSMD_TX_p4 LVDS TX 4 CMOS I O LVDS or 2 5 V 627 72 HSMD_RX_p4 LVDS RX bit CMOS LVDS or 2 5 33 73 HSMD TX 4 LVDS TX bit or CMOS I O LVDS
97. er Manual www terasic com www terasic com Chapter 4 TR4 System Builder This chapter describes how users can create a custom design project on the TR4 board by using the included TR4 software tool TR4 System Builder 4 1 Introduction The TR4 System Builder 15 Windows based software utility designed to assist users in creating Ouartus II project for the TR4 board within minutes The generated Ouartus II project files include Ouartus II Project File gpf Ouartus II Setting File gsf Top Level Design File v External PLL Controller v Synopsis Design Constraints file sdc Pin Assignment Document htm The TR4 System Builder not only can generate the files above but can also provide error checking rules to handle situations that are prone to errors The common mistakes that users encounter are the following Board damaged due to wrong pin bank voltage assignments Board malfunction caused by wrong device connections or missing pin counts for connections Poor performance drop due to improper pin assignments 4 2 General Design Flow This section will introduce the general design flow to build a project for the TR4 board via the TR4 System Builder The general design flow is illustrated in the Figure 4 1 70 Terasic TR4 User Manual www terasic com www terasic com ANOTE RYA Users should launch TR4 System Builder and create a new project according to their design requi
98. era s DDR3 SDRAM Controller with UniPHY IP is used to create a DDR3 SDRAM controller and how the Nios II processor is used to read and write the SDRAM for hardware verification The DDR3 SDRAM controller handles the complex aspects of using DDR3 SDRAM by initializing the memory devices managing SDRAM banks and keeping the devices refreshed at appropriate intervals The required DDR3 SDRAM SODIMM module should be 1 GB DDR3 1066 B System Block Diagram Figure 5 6 shows the system block diagram of this demonstration The system requires a 50 MHz clock provided from the board The DDR3 controller is configured as a 1GB DDR3 1066 controller The DDR3 IP generates one 533 0 MHz clock as memory clock and one quarter rate system clock 133 125 for controllers e g Nios II processor accessing the SDRAM In Qsys Nios II and On Chip Memory are designed running with the 133 125 MHz clock and the other controllers are designed running with 50 MHz clock which is the external clock The Nios II program itself is running in the on chip memory FPGA UO naa 50 MHz i Memory emp Button Timer DDR3 DDR3 Controller SDRAM 1 System Intercoment Fabric Figure 5 6 Block diagram of the DDR3 1G demonstration The system flow is controlled by a Nios II program First the Nios II program writes test patterns into the DDR3 filling it up to maximum capacity Then it calls Nios II system function 9
99. erential clock input Schematic Signal Name Description HSMC OUTO HSMC CLKINO HSMC DO HSMC D1 HSMC D2 HSMC D3 HSMC TX HSMC HSMC TX HSMC RX n0 HSMC TX p1 HSMC RX p1 HSMC TX n1 HSMC HSMC TX p2 HSMC RX p2 HSMC 2 HSMC 2 HSMC TX p3 HSMC RX p3 HSMC TX n3 HSMC RX n3 HSMC TX p4 HSMC RX p4 HSMC TX n4 HSMC RX n4 HSMC TX p5 HSMC RX p5 HSMC TX n5 HSMC RX n5 HSMC TX p6 HSMC RX p6 HSMC TX n6 HSMC RX n6 HSMC TX p7 Terasic TR4 User Manual CMOS I O Dedicated clock input LVDS TX or CMOS I O LVDS RX or CMOS I O LVDS TX or CMOS I O LVDS RX or CMOS I O LVDS TX bit 0 or CMOS I O LVDS RX bit 0 or CMOS I O LVDS TX bit On or CMOS I O LVDS RX bit On or CMOS I O LVDS TX bit 1 or CMOS I O LVDS RX bit 1 or CMOS I O LVDS TX bit 1n or CMOS I O LVDS RX bit 1n or CMOS I O LVDS TX bit 2 or CMOS I O LVDS RX bit 2 or CMOS I O LVDS TX bit 2n or CMOS I O LVDS RX bit 2n or CMOS I O LVDS TX bit 3 or CMOS I O LVDS RX bit 3 or CMOS I O LVDS TX bit 3n or CMOS I O LVDS RX bit 3n or CMOS I O LVDS TX bit 4 or CMOS I O LVDS RX bit 4 or CMOS I O LVDS TX bit or CMOS I O LVDS RX bit 4n or CMOS I O LVDS TX bit 5 or CMOS I O LVDS RX bit 5 or CMOS I O LVDS TX bit 5n or CMOS I O LVDS bit 5n or CMOS I O LVDS TX bit 6 or CMOS I O LVDS RX bit 6 or CMOS I O LVDS TX bit 6n or CMOS I O LVDS RX bit 6n or CMOS I O or LVDS 2 5 AW14 VO Standard LVDS or 2 5 V LVDS or 2 5 V LVDS o
100. et the external clock generator for the output frequency Table 5 2 EXT PLL CTRL Instruction Ports clk1 set wr set wr Output Frequency MHz 85 Terasic TR4 User Manual www terasic com www terasic com 0 RYA 4 b0101 Clock Generator Disable Setting External Clock Generator 1001 es ooo Others Seting Unchanged B The EXT PLL CTRL IP Timing Diagram In this reference design the output freguency is set to 62 5 75 and 100 MHz with the following timing diagrams illustrated below When the ext ctrl IP receives the conf wr signal the user needs to define clkl set wr 2 set wr and cik3 set wr to set the External Clock Generator When the ext pll IP receives the conf rd signal it will read the value back to ciki set rd clk2 set rd and cik3 set rd Write Timing Waveform As BUTTONO the trigger source defined by Terasic is pressed the conf wr signal is on the rising edge serial data is transferred immediately with the conf ready signal in the transmission period starting at falling edge level as shown in Figure 5 3 As the transfer is completed the conf ready signal returns back to original state at high level 86 TR4 User Manual www terasic com www terasic com ANU S RYA Alias llame 1024 2048 3072 4096 5120 6144 7168 jet ext
101. g Flash Memory Batch Program TR4 Board Figure 2 2 Flash Programming Scheme B Programming Flash Memory using Batch File The TR4 provides a batch file program Flash bat to limit the steps that are taken when users program the flash memory on the TR4 Software Requirements e Quartus II 11 1 or later Nios 11 1 or later e Program Flash folder contents e Program Flash bat e Program Flash pl e Program Flash sh e tr4 default flash loader sof e boot loader cfi srec 13 Terasic TR4 User Manual www terasic com www terasic CO m Before you use the program Flash bat batch file to program the flash memory make sure the TR4 is turned on and USB cable is connected to the USB blaster port J4 In addition place the sof and elf file you wish to program convert in the Program Flash directory Programming Flash Memory with sof using Program Flash bat 1 Launch the program Flash bat batch file from the directory demonstrations TR4_ lt Stratix device gt Default Flash Loaderr Program Flash of the system CD ROM 2 The Flash program tool shows the menu options Nios II EDS 11 1 gec3 5 x TR4 Development Kit Flash Program Tools ver 1 0 0 0 PE EA HAHA HAHA HAHAHA HAHAHA HAHAHA HAHAHA HAHA menu 33333 33 ECCE ECCE ECCE COGO Program sof and elf to flash include pfl option bit Erase flash Program sof file into the flash Program elf file into the
102. gram of the DDR3 4G Demonstration The project is based on the example top code which is generated by the DDR3 IP and can be used to test the whole module after modifying the code In the project example driver will read out the data for a comparison after writing every 1 pseudo random data The read compare module will buffer the write data and then compare it with the data read back If the right result is achieved the address will be accumulated and the test will check the whole memory span of 4GB after finishing 4 1024 1024 loops B Altera DDR3 SDRAM Controller with UniPHY To use Altera DDR3 controller users need to perform three major steps 1 Create correct pin assignment for DDR3 2 Setup correct parameters in DDR3 controller dialog 3 Execute TCL files generated by DDR3 IP under your Quartus project The following section describes some of the important issues in support of the DDR3 controller configuration On the PHY Setting tab in order to achieve 533 0 MHz clock frequency a reference clock frequency of 50 MHz should be used B Design Tools Quartus 11 1 B Demonstration Source Code 95 Terasic TR4 User Manual www terasic com www terasic co m Project directory TRA DDR3 4G RTL e Bit stream used TRA DDR3 UniPHY 4G RTL sof B Demonstration Batch File Demo Batch File Folder DDR3 UniPHY 4G batch The demo batch file includes following files e Batch File
103. ic col m ANU S RYA B FPGA Application Design The Express demonstration uses the basic I O interface and DMA channel on the Terasic IP to control I O Button LED and access two internal memories RAM FIFO through the MUX block FPGA ME Address PCI Express qu Basic y o Interface Terasic PCle IP Decoder Internal DMA Channel Figure 6 14 Hardware Block Diagram of the PCle Reference Design B PC Application Design The application shows how to call the TERASIC PCIE DLL exported to API To enumerate all PCIe cards in system call the software design defines some constants based on FPGA design shown below define PCIE VID 0 1172 define PCIE DID 1 define DEMO PCIE USER BAR PCIE BARI define DEMO PCIE IO ADDR 0x04 define DEMO PCIE FIFO ID 0x00 The vendor ID is defined as 0x1172 and the device ID is defined as 0 001 The BUTTON LED register address is 0x04 based on PCIE BARI 115 Terasic TR4 User Manual www terasic com www terasic com ANOTE RYA A C class PCIE is designed to encapsulate the DLL dynamic loading for TERASIC_PCIE DLL A PCIE instance is created with the name m_hPCIE To enumerate all PCIe cards in system call the function m hPCIE ScanCard wVendorID wDeviceID amp dwDeviceNum m szPcieInfo where wVendorID and wDeviceID are zeros The return value dwDeviceNum represents the number of PCIe cards
104. ication 119 Terasic TR4 User Manual www terasic com www terasic com www terasic com Download Image Process Image Upload Image Figure 6 18 PCle Image Demo Inverted Image B Design Tools Quartus IL 11 1 B Demonstration Source Code Location e Quartus Project 0 imageprocess e Borland C Project TRA 0 imageprocess B FPGA Application Design This demonstration uses the DMA channel of PCIe IP to download upload the image into the internal RAM of FPGA and controls the user register that switches the function which inverts the image data from the internal RAM B PC Application Design The software design defines some constant based on the FPGA design as shown below 120 Terasic TR4 User Manual www terasic com www terasic com define PCIE VID 0x1172 define PCIE DID OxEOO01 define IMAGE WIDTH 320 define IMAGE HEIGH 240 define DEMO PCIE USER BAR PCIE BARI define DEMO IMAGE REG ADDR 0 10 define DEMO IMAGE DATA ADDR The vendor ID is defined as 0x1172 and the device ID is defined as 0 001 The image dimension is defined as 320x240 The register address is 0x10 and memory address is 0x00 A class PCIE is designed to encapsulate the DLL dynamic loading for TERASIC PCIE DLL A PCIE instance is created with the name m hPCIE To open a connection with FPGA the function is called m hPCIE Open PCIE VID PCIE
105. ication demonstrates the invert image processing by utilizing the FPGA The PC and FPGA source code of the application layer are all available in the TR4 system CD allowing users to easily extend the image process function based on this fundamental reference design In the demonstration a memory mapped memory is designed in the FPGA to work as an image frame buffer The memory size is 320x240x3 bytes with a starting address 0x00 The raw image is downloaded to and uploaded from the FPGA via DMA The image process command and status is controlled by a register which can be accessed from the PC using basic I O control The register address is 0x10 under PCIE BARI Writing any value into this register will start the image process The status of the image process is reported by a read from this register The PCIe vendor ID and device ID is 0x1172 and OxE001 respectively The block diagram of FPGA PCIe design is shown in Figure 6 15 117 TR4 User Manual www terasic com www terasic com FPGA 3 Tersic PCle Basic 119 Register Gan Interface sd Invert PCI Express 21 function AR 4 Basic Internal y o RAM Interface Figure 6 15 Block Diagram of Image Processing Reference Design B Demonstration Files Location The demo file is located in the folder 0 imageprocesNdemo batch The folder includes the following files e PC Appli
106. igured via MAX II CPLD e Supports JTAG mode Memory Devices e 64MB Flash 32M x16 with a 16 bit data bus 2MB SSRAM 512K x 32 DDR3 SO DIMM Socket e Upto 4GB capacity e Maximum memory clock rate at 533MHz e Theoretical bandwidth up to 68Gbps LEDs e 4 user controllable LEDs e Active low Push buttons TR4 User Manual www terasic com www terasic com e 4 user defined inputs Active low Slide Switches e 4 slide switches for user defined inputs e Logic low for DOWN position Logic high for UP position On Board Clocking Circuitry e 50MBZz oscillator e SMA connector pair for differential clock inputs e SMA connector pair for differential clock outputs e SMA connector for external clock input e SMA connector for clock output Two PCI Express x4 Edge Connectors e Support connection speed of Genl at 2 5Gbps lane to Gen2 at 5 0Gbps lane e Support downstream mode Six High Speed Mezzanine Card HSMC Connectors e Two HSMC ports include 16 pairs of CDR based transceivers at data rates of up to 6 5Gbps e 52true LVDS transmitter channels and 54 true LVDS receiver channels at data rate up to 6Gbps e 16 emulated LVDS transmitter channels and 14 emulated LVDS receiver channels at data rate up to 1 1Gbps e Configurable I O standards 1 5V 1 8V 2 5V 3 0V Two 40 pin GPIO Expansion Headers e 72 FPGA pins 4 power and ground lines 9 Terasic TR4 User Manu
107. ity Description oCORE CLK Output Clock The reference clock output of PCle local interface When oFIFO MEM SEL is set to low it is address bus of DMA transfer and the value of address bus is cumulative by PCle IP and it is 128 bit data per address When Man BHO SEL is set to high ADDR bus isa FIFO ID that is used to indicate that which FIFO buffer is selected by PC API iDMARD DATA 127 0 Input Read data bus oDMARD READ Output High Read signal iDMARD RDVALID Input High Read data valid When oFIFO MEM SEL is set to low it is address bus of DMA transfer and the value of address bus is cumulative by PCle IP and it is 128 bit data per address When Ba PUUE i MEM SEL is set to high ADDR bus is FIFO ID that is used to indicate that which FIFO buffer is selected by PC API oDMAWR DATA 127 0 Output Write data bus oDMAWR WRITE Output High Write signal Indicates that DMA channel is memory mapping interface oFIFO MEM SEL Output or FIFO link interface When this signal is asserted high 11 1 1 oCORE CS Y NY 1 1 1 1 1 1 1 1 1 1 1 2 3 DMA channel FIFO link interface When the signal is asserted low it is memory mapping interface 4 5 6 7 8 9 oDMARD_ADDR CR IDMARD DATA KAKEK EK 1 oDMARD READ 2 1 1 1
108. lease refer to Using Mult TR4 system pdf which can be found on the TR4 System CD Figure 2 19 Two Stacked TR4 Boards 33 Terasic TR4 User Manual www terasic com www terasic com Figure 2 20 Two TR4 Boards Connected via HSMC Cable 2 6 GPIO Expansion Headers The TR4 consists of two 40 pin expansion headers as shown in Figure 2 21 Each header has 36 I O pins connected to the Stratix IV GX FPGA with the other 4 pins providing 5V VCC5 DC 3 3V VCC33 DC and two GND pins GPIO 0 and GPIO 1 share pins with HSMC Port C The I O standards of the GPIO headers are the same as HSMC Port C which can be configured between 1 5 1 8 2 5 and 3 0V 34 Terasic TR4 User Manual www terasic com www terasic col m JP9 JP10 GPIO 0 GPIO 1 Clock Input GPIOO DO 2 D1 GPIOO DO ME 2 GPIO1 D1 Clock Input GPIOO D2 4 D3 GPIO1 D2 2 GPIO1 D3 GPIOO D4 5 D5 D4 5 GPIO1 D5 D6 D7 D6 GPIO1 D7 D8 GPIOO D9 GPIO1 D8 GPIO1 D9 5 11 12 GND 5V 1 1 12 GND D10 13 011 GPIO1 10 13 14 GPIO1 011 012 15 16 GPIOO 013 GPIO1 0112 15 5 GPIO1 13 014 17 D15 GPIO1 D14 GPIO1 015 GPIOO D16 19 20 D17 GPIO1 D16 19 20 GPIO1 D17 018 A 22 019 GPIO1 018 21 22 GPIO1 D19 GPIOO D20 2324 021 GPIO1 D20 2324 GPIO1 D21 022 2526 GPIOO D
109. m addr 1 mem addr 2 mem addr 3 mem addr 4 mem addr 5 mem addr 6 mem addr 7 mem addr 8 Description DDR3 ADDRess 0 DDR3 ADDRess 1 DDR3 ADDRess 2 DDR3 ADDRess 3 DDR3 ADDRess 4 DDR3 ADDRess 5 DDR3 ADDRess 6 DDR3 ADDRess 7 DDR3 ADDRess 8 Standard SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I 38 Terasic TR4 User Manual www terasic com Stratix IV GX Pin Number PIN N23 PIN 22 PIN M22 PIN D21 PIN P24 PIN A24 PIN M21 PIN D17 PIN A25 www terasic com mem addr 9 mem addr 10 mem addr 11 mem addr 12 mem addr 13 mem addr 14 mem addr 15 mem ba 0 mem ba 1 mem ba 2 mem cas n mem cke 0 mem cke 1 mem ck 0 mem ck 1 mem ck n 0 mem ck n 1 mem cs n 0 mem cs n 1 mem dm 0 mem dm 1 mem dm 2 mem dm 3 mem 4 mem dm 5 mem dm 6 mem dm 7 mem dq 0 mem dq 1 mem dq 2 mem dq 3 mem dq 4 mem dq 5 mem dq 6 mem dq 7 DDR3 ADDRess 9 DDR3 ADDRess 10 DDR3 ADDRess 11 DDR3 ADDRess 12 DDR3 ADDRess 13 DDR3 ADDRess 14 DDR3 ADDRess 15 DDR3 Bank ADDRess 0 DDR3 Bank ADDRess 1 DDR3 Bank ADDRess 2 DDR3 Column ADDRess Strobe Clock Enable pin 0 for DDR3 Clock Enable pin 1 for DDR3 SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class
110. mory FIFO of the FPGA board in DMA function Prototype bool PCIE DmaFifoRead PCIE HANDLE hPCIE PCIE LOCAL FIFO ID LocalFifold void pBuffer DWORD dwBufSize n Parameters hPCIE A PCIe handle return by PCIE Open function LocalFifold Specify the target memory FIFO ID in FPGA pBuffer A pointer to a memory buffer to retrieved the data from FPGA The size of buffer should be equal or larger the dwBufSize dwBufSize Specify the byte number of data retrieved from FPGA Return Value Return TRUE if read data is successful otherwise FALSE is returned PCIE DmaFifoWrite Function Write data to the memory FIFO of the FPGA board in DMA function Prototype 111 TR4 User Manual www terasic com www terasic com bool PCIE DmaFifoWrite PCIE HANDLE hPCIE PCIE LOCAL FIFO ID LocalFifold void pData DWORD dwDataSize Parameters hPCIE A PCIe handle return by PCIE Open function LocalFifold Specify the target memory FIFO ID in FPGA pData A pointer to a memory buffer to store the data which will be written to FPGA dwDataSize Specify the byte number of data which will be written to FPGA Return Value Returns TRUE if write data is successful otherwise FALSE is returned 6 4 PCle Fundamental Communication The application reference design shows how to implement fundamental control and data transfer using port on the
111. mum temperatures for Over temperature or Alert as required Click the Write button to update the values entered 64 Terasic TR4 User Manual www terasic com www terasic com sensor Configuration Unit Celsius Degree hyst Read E T high Read 127 T high Write Alert pz aa T low Read 55 T low Write Temperature Information Pp M Board Temperature FPGA Temperature 29 DISCONNECT Monitor Temperature Figure 3 9 Accessing the Temperature Sensor through Control Panel 3 6 PLL The PLL function is designed to configure the external programmable PLL on the TR4 There are 3 programmable clocks for the TR4 board that generates reference clocks for the following signals HSMA REFCLK HSMB REFCLK p n and PGM GXBCLK The clock freguency can be adjusted to 62 5 75 100 125 150 156 25 187 5 200 250 312 5 and 625MHz Choose the PLL tab to reach the window shown in Figure 3 10 To set the desire clock frequency for the associated clock signal click on Set 65 Terasic TR4 User Manual www terasic com www terasic com Unchanged Unchanged Figure 3 10 Programmable External PLL Configured through Control Panel 3 7 HSMC Choose the HSMC tab to reach the window shown in Figure 3 11 This function is designed to verify the functionality of signals found on the HSMC connectors of ports A B C D E and F using a loopback approach
112. nally section 6 3 and 6 4 demonstrate two examples on how to use the PCIe interface of TR4 board with a PC Table 2 16 and Table 2 17 summarize the PCI Express pin assignments of the signal names relative to the Stratix IV GX FPGA Figure 2 25 PCle Adapter Card for Host Computer 46 Terasic TR4 User Manual www terasic com www terasic col m Figure 2 26 PCle External Cable Figure 2 27 PCle Link Setup between TR4 and PC 47 Terasic TR4 User Manual www terasic com www terasic com PCle0 WAKE PCle0 pRESTn PCle0 REFCLK 0 REFCLK n PCle0 TX p 3 0 0 TX n 3 0 0 RX n 3 0 H PCle0 3 0 PCle1 n 3 0 PCle1 TX p 3 0 PCle1 TX n 3 0 PCle1 REFCLK p PCle1 REFCLK PCle1 PREST n PCle1 WAKE n Figure 2 28 PCI Express Pin Connection Table 2 16 PCIe0 Pin Assignments Schematic Signal Names and Functions Name PCIEO REFCLK p PCIEO PREST n PCIEO WAKE n PCIEO TX 0 PCIEO p 0 PCIEO TX p 1 PCIEO p 1 PCIEO TX p 2 PCIEO RX 2 PCIEO TX PCIEO PCle0 4 Lane Downstream Description VO Standard PCleO reference HCSL clock Depends on HSMC Port A I O standard Depends on HSMC Port A I O standard 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML PCle0 present PCle0 wake PCle0 data lane 48 Terasic TR4 User Manual ww
113. niPHY 1G QSYS bashrc FPGA Configuration File TRA DDR3 UniPHY QSYS sof Nios II Program TRA DDR3 UniPHY QSYS elf 92 TR4 User Manual www terasic com www terasic com ANOTE RYA B Demonstration Setup e Make sure Quartus II and Nios II are installed on your PC e Make sure DDR3 SDRAM SODIMM 1G is inserted into your board as shown in Figure 5 7 e Connect the USB Blaster cable to the TR4 board and host PC Install the USB Blaster driver if necessary e Power on the TR4 board e Execute the demo batch file DDR3 UniPHY OSYS bat under the batch file folder DDR3 UniPHY OSYNdemo batch e After Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal e Press BUTTON3 BUTTONO of the board to start the DDR3 verification process Press to continue the test and Ctrl C to terminate the test e The program will display the progress and result as shown in Figure 5 8 Figure 5 7 Insert the DDR3 SDRAM SODIMM for the DDR3 1G Demonstration 93 Terasic TR4 User Manual www terasic com www terasi Nios II EDS 11 05 1 gcc3 Initializing CPU cache if present OK Downloaded 67KB 1 15 60 9KB s Uerified OK Starting processor at address 9 4192018 4 nios2 terminal connected to hardware target using JTAG UART on cable nios2 terminal USB Blaster 5 1
114. nsion Prefix Name HSMC E XTS Transceiver t Prefix HSMC F GPIO LTC2 8 LCD Touch Camera GPIO 0 GPIO 1 None Prefix Name Default Setting Load Setting Save Setting Generate Exit Figure 4 9 GPIO option and I O standard recommend B Project Setting Management The TR4 System Builder also provides functions to restore a default setting loading a setting and saving users board configuration file shown in Figure 4 10 Users can save the current board configuration information into a cfg file and load it to the TR4 System Builder 79 Terasic TR4 User Manual www terasic com www terasic com Terasic Y1 0 0 AN S RYAN System Configuration UNIVERSITY PROGRAM WWW terasic com Board Type TR4 230 Project Name CLOCK Switch x 4 MLEDx 4 v Button x 4 v SSRAM 2MB Temperature v Flash 64 Fan Control OSMA O DDR3 SODIMM O PCle 0 1 O Programmable PLL Programmable PLL HSMA REFCLK REFCLK GXBCLK HSMC Expansion HSMC D HSMC A Transceiver x 8 DVI TXIRX DVI TXIRX Prefix Name Prefix Name HSMC E Transceiver x 8 HSMC B XTS Transceiver t
115. o SMA RX Name Prefix Name HSMC F HSMC C GPIO HSMC LTC2 8 LCD Touch Camera NET 10 100 1000 Ethernet v Prefix Name Name Figure 4 10 Project Settings B Project Generation When users press the Generate button the TR4 System Builder will generate the corresponding Quartus II files and documents as listed in the Table 4 1 in the directory specified by the user Table 4 1 Files Generated by TR4 System Builder op level Verilog file for Quartus II 2 CTRL v External PLL configuration controller IP 3 Project name gt qpf Quartus II Project File Project name gt qsf Quartus II Setting File Project name gt sdc Synopsis Design Constraints file for Quartus II Terasic TR4 User Manual www terasic com www terasic col ANOTE RYA Project gt Pin Assignment Document Users can use Quartus II software to add custom logic into the project and compile the project to generate the SRAM Object File sof In addition External Programmable PLL Configuration Controller IP will be instantiated in the Quartus II top level file as listed below ext u ext system input osc_50 OSC_50_BANK1 rstn rstn device 1 clk1 set wr clkl set wr cikl set 140 device 2 cIk2 set wr cik2 set wr cIk2 set device 3 clk3 set wr
116. obe n 4 DDR3 Data Strobe n 5 DDR3 Data Strobe n 6 DDR3 Data Strobe n 7 Terasic TR4 User Manual www terasic com SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I SSTL 15 Class I Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class I Differential 1 5 V SSTL Class 41 PIN C17 PIN F17 PIN C18 PIN D18 PIN D25 PIN C25 PIN G24 PIN G25 PIN B25 PIN A26 PIN D26 PIN F24 PIN F23 PIN G23 PIN J22 PIN H22 PIN K22 PIN D22 PIN G22 PIN E22 PIN D15 PIN K16 PIN L23 PIN C28 PIN E29 PIN G18 PIN F25 PIN J23 PIN C15 PIN J16 PIN K23 PIN B28 PIN D29 PIN F18 PIN E25 PIN H23 www terasic com ANU S RYA mem odt 0 mem odt 1 mem ras n mem we n mem event n mem reset n mem scl mem sda 2 8 Clock DDR3 On die Termination 0 SS
117. press The TR4 development board features two PCIe Express downstream interfaces x4 lane which are designed to interface with a PC motherboard x4 slot via PCIe cable and PCIe adapter card Utilizing 45 TR4 User Manual www terasic com www terasic com built in transceivers on Stratix IV GX device it is able to provide fully integrated PCI Express compliant solution for multi lane x4 applications With the PCI Express hard IP block incorporated in the Stratix IV GX device it will allow users to implement simple and fast protocol as well as saving logic resources for logic application The PCI Express interface supports complete PCI Express Genl at 2 5Gbps lane and Gen2 at 5 0Gbps lane protocol stack solution compliant to PCI Express base specification 2 0 that includes Data Link and transaction layer circuitry embedded in PCI Express hard IP blocks To use PCIe interface two external associated devices will be needed to establish link with PC First a PCIe half height add in host card with a PCIe x4 cable connector See Figure 2 25 will be used to plug into the PCIe slot on a mother board Then a PCIe x4 cable See Figure 2 26 will be used to connect TR4 board and PCIe add in card as shown in Figure 2 27 These two associated devices are not included in TR4 kit To purchase the PCIe add in host card as well as the external cable please contact Terasic sales team sales terasic com Fi
118. r 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS TX bit 7 or CMOS I O LVDS or 2 5 V 129 Table 7 3 HSMC Port C Pin Assignments Schematic Signal Names and Functions Stratix IV GX Pin Number 27 AU27 AB27 AJ25 AB28 AK25 AC28 26 26 29 AD28 AP28 AD29 AR28 AE28 AT28 AE29 AU28 AF29 AV28 AG30 29 AE30 AV29 AE31 30 AG31 2 AG32 AW32 AD30 AJ26 AD31 AK26 AB30 www terasic com 90 HSMC LVDS RX bit CMOS LVDSor2 5 V 25 91 HSMC TX n7 LVDS TX bit 7n CMOS LVDS or2 5 V AB31 92 HSMC RX n7 LVDS RX bit 7n or CMOS I O LVDS 2 5 AG25 95 HSMC CLKOUT p1 LVDS TX or CMOS LVDSor2 5 V 34 96 HSMC CLKIN p1 LVDS RX or CMOS VO or differential clock input 97 HSMC CLKOUT ni LVDS RX or CMOS LVDS or 2 5 V AG35 98 HSMC_CLKIN_n1 LVDS RX or CMOS VO Of Wns 5 AE35 differential clock input 101 HSMC TX p8 LVDS TX bit 8 CMOS I O LVDSor2 5 V AL27 102 HSMC RX p8 LVDS RX 8 CMOS LVDSor2 5 V 32 103
119. rd is connected The 2 adapter card can be connected to either ports of the HSMC connector shown in Figure 2 15 There are numerous adapter cards that are supported by the TR4 such as loopback and differential 29 Terasic TR4 User Manual www terasic com www terasic com ANOTE RYA transmission adapters For more detailed information about these adapter cards please refer to HSMC_adapter_card pdf which can be found system CD Figure 2 15 Connection between HMF2 Adapter Card and HSMC B JTAG Chain on HSMC The JTAG chain on the HSMC can be activated through the three 4 position DIP switches SW4 SW5 and SW6 Table 2 1 in section 2 2 gives a detailed description of the positions of the DIP switches and their associated interfaces The HSMC connectors on the top side of TR4 board are controlled by SW4 and SW6 SW5 is used to control the HSMC JTAG chain on the bottom side of the TR4 Only when multiple TR4s are stacked should the boards use this switch A document titled Using Multi TR4 system pdf in the system CD will give an example to demonstrate how to set SW5 to connect JTAG chains together for multiple boards Finally before using the JTAG interface on HSMC connector please short JP7 in order to enable the HSMC JTAG interface 30 Terasic TR4 User Manual www terasic com www terasi ANU S RYA The following will describe how to configure the JTAG interface HSMC conne
120. rements When users complete the settings the TR4 System Builder will generate two major files which include a top level design file v and the Quartus II settings file qsf The top level design file contains a top level Verilog wrapper for users to add their own design logic The Quartus II settings file contains information such as FPGA device type top level pin assignments and I O standards for each user defined I O pin Finally Quartus II programmer must be used to download SOF file to TR4 board using JTAG interface Figure 4 1 General Design Flow 4 3 Using TR4 System Builder This section provides the detail procedures on how the TR4 System Builder is used 71 Terasic TR4 User Manual www terasic com www terasic com ANU S RYA B Install and launch the System Builder The System Builder is located in the directory Tools TRA SystemBuilder the System CD Users can copy the whole folder to a host computer without installing the utility Before using the TR4 System Builder execute the TR4 SystemBuilder exe on the host computer as appears in Figure 4 2 Terasic IR4 V1 0 0 S RYAN System Configuration ter UNIVERSITY PROGRAM Board 230 Project Name CLOCK v Switch x 4 LEDx 4 Button x 4 SSRAM 2MB Temperature Flash 64MB Fan Control OSMA 10083 SODIMM L1PCle 0 PCle 1 Programmable PLL
121. s I SSTL 15 Class I SSTL 15 Class I 40 PIN N17 PIN M17 PIN K17 PIN L16 PIN P16 PIN P17 J17 PIN H17 PIN N22 PIN M23 PIN J25 PIN M24 PIN R22 PIN P22 PIN K24 PIN J24 A27 PIN A28 PIN C29 PIN C30 PIN C27 PIN D27 A31 B31 PIN G27 PIN G29 PIN F28 PIN F27 PIN E28 PIN D28 PIN H26 PIN J26 PIN F19 PIN G19 PIN F20 PIN G20 www terasic com mem dq 44 mem dq 45 mem dmq 46 mem dq 47 dmq 48 mem dq 49 mem dmq 50 mem dq 51 mem dq 52 mem dq 53 mem dq 54 mem dq 55 mem dmq 56 mem dq 57 mem dmq 58 mem dq 59 mem 44160 mem dq 61 44162 dmq 63 dmqs 0 mem dqs 1 44512 dqs 3 445141 dmqs 5 mem dmqs 6 mem dqs 7 mem 445 n 0 mem dqs n 1 mem 445 n 2 mem dqs n 3 mem 445 n 4 mem 445 n 5 mem 445 n 6 mem 445 n 7 DDR3 Data 44 DDR3 Data 45 DDR3 Data 46 DDR3 Data 47 DDR3 Data 48 DDR3 Data 49 DDR3 Data 50 DDR3 Data 51 DDR3 Data 52 DDR3 Data 53 DDR3 Data 54 DDR3 Data 55 DDR3 Data 56 DDR3 Data 57 DDR3 Data 58 DDR3 Data 59 DDR3 Data 60 DDR3 Data 61 DDR3 Data 62 DDR3 Data 63 DDR3 Data Strobe p 0 DDR3 Data Strobe p 1 DDR3 Data Strobe p 2 DDR3 Data Strobe p 3 DDR3 Data Strobe p 4 DDR3 Data Strobe p 5 DDR3 Data Strobe p 6 DDR3 Data Strobe p 7 DDR3 Data Strobe n 0 DDR3 Data Strobe n 1 DDR3 Data Strobe n 2 DDR3 Data Strobe n 3 DDR3 Data Str
122. s is commonly used in consumer server and industrial applications to link motherboard mounted peripherals From this demonstration it will show how the PC and FPGA communicate with each other through the PCI Express interface The PCle drivers used in this example design are from Jungo For more information please check out www jungo com 6 1 PCI Express System Infrastructure The system consists of two primary components the FPGA hardware implementation and the PC based application The FPGA hardware component is developed based on Altera IP and the PC based application is developed under the Jungo driver Figure 6 1 shows the system infrastructure FPGA TERASIC PCle IP TERASIC PCIE DLL Altera PCle User Mode Hard IP Kernel Mode UNE Figure 6 1 PCI Express System Infrastructure 98 Terasic TR4 User Manual www terasic com www terasic coi m 6 2 FPGA PCI Express System Design The TR4 PCI Express connector is able to allow interconnection to the PCIe motherboard slots via PCIe adapter card and cable For more information on the PCIe adapter card and cable please consult Section 2 9 For basic I O control communication is established through the PCI Express bus where it is able to control the LEDs and monitor the status of the TR4 buttons By implementing an internal RAM and FIFO the demonstration is capable of direct memory access DMA transfers B PCI Express Basic I O Transa
123. se pins 3 dedicated differential clock input listed in Table 2 19 In addition there are atotal of 8 PLLs available for the Stratix IV GX device Table 2 19 Dedicated Clock Input Pins Dedicated Clock Input Pins OSC 50 BANK1 HSMD CLKINO HSMC CLKIN p2 HSMC CLKIN n2 HSMA CLKIN p2 HSMA CLKIN n2 HSME CLKIN p2 HSME CLKIN n2 The dedicated clock input pins from the clock input multiplexer allow users to use any of these clocks as a source clock to drive the Stratix IV PLL circuit through the GCLK and RCLK networks Alternatively PLLs through the GCLK and RCLK networks or from dedicated connections on adjacent top bottom and left right PLLs can also drive the PLL circuit The clock outputs of the Stratix IV GX FPGA are derived from various interfaces notably the HSMC and the SMA connectors B Stratix IV GX FPGA Transceiver Clock Inputs The transceiver reference clock inputs for the serial protocols supported by the Stratix IV GX FPGA transceiver channels include the PCI Express PIPE and the SMA connectors The TR4 uses three programmable low jitter clock generators with default clock output of 100MHz and an I O standard of LVDS that is non configurable The clock generators are programmed via Max II CPLD to generate the necessary clocks for the Stratix IV GX transceiver protocols and interfaces such as HSMC The PCI Express PIPE transceiver reference clock is generated from the PCIe connector 44 TR4
124. the memory mapped memory of FPGA board in DMA function Prototype 109 Terasic TR4 User Manual www terasic com www terasic com bool PCIE DmaRead PCIE HANDLE hPCIE PCIE LOCAL ADDRESS LocalAddress void pBuffer DWORD dwBufSize Parameters hPCIE A PCIe handle return by PCIE Open function LocalAddress Specify the target memory mapped address in FPGA pBuffer A pointer to a memory buffer to retrieved the data from FPGA The size of buffer should be equal or larger than the dwBufSize dwBufSize Specify the byte number of data retrieved from FPGA Return Value Return TRUE if read data is successful otherwise FALSE is returned PCIE DmaWrite Function Write data to the memory mapped memory of FPGA board in DMA function Prototype bool PCIE DmaWrite PCIE HANDLE hPCIE PCIE LOCAL ADDRESS LocalAddress void pData DWORD dwDataSize 2 Parameters hPCIE A PCIe handle return by PCIE Open function LocalAddress Specify the target memory mapped address in FPGA pData 110 Terasic TR4 User Manual www terasic com www terasic com A pointer to a memory buffer to store the data which will be written to FPGA dwDataSize Specify the byte number of data which will be written to FPGA Return Value Return TRUE if write data is successful otherwise FALSE is returned PCIE DmaFifoRead Function Read data from the me
125. ustrate how to utilize the clock generators IP to define the clock output using the serial bus The programmable clock outputs generate clock signals HSMA REFCLK p n CDCM61001 01 PGM GXBCLK pl nl CDCM61004 and REFCLK p n CDCM61001 02 with adjustable output clock frequencies of 62 5 75 100 125 150 156 25 187 5 200 250 312 5 and 625MHz The standard for the clock frequencies is set to LVDS which is not configurable An overall block diagram of the external clock generator is shown below in Figure 5 1 83 Terasic TR4 User Manual www terasic com www terasic com ANU S RYA E _50MHz a PR1 CLK PRO _PRO 002 OD1 _ODO HSMA_REFCLK CLK1 OS1 CLK1 50 CLK1 CE CLK1 RSTn CLK2 OD2 CLK2 OD1 CLK2 REFCLK AERA CLK2 OS1 _ CLK2 050 CLK2 CLK2 RSTn CLK3 PR1 CLK3 PRO CLK3 OD2 CLK3 OD1 CLK3 ODO PGM GXBCLK CLK3 OS1 CLK3 OSO CLK3 CE CLK3 RSTn SCL Figure 5 1 External Clock Generator Block Diagram B The EXT PLL CTRL IP Port Description This section describes the operation for the EXT PLL CTRL instruction hardware port Figure 5 2 shows the EXT PLL CTRL instruction block diagram connected to the MAX II EPM2210 device The EXT PLL CTRL controller module is defined by a host device the Stratix IV GX FPGA and a slave device the MAX
126. uts high speed serial I O transceivers and single ended or differential signaling The detailed specifications of the HSMC connectors are described below B 6HSMC Connector Groups There are ten HSMC connectors on the TR4 board are divided into 6 groups HSMC A HSMC B HSMC C HSMC D HSMC E and HSMC F Each group has a male and female HSMC port on the top and bottom side of the TR4 board except HSMC E and HSMC F In addition both the male and female HSMC connector share the same I O pins besides JTAG interface and high speed serial I O transceivers Caution DO NOT connect HSMC daughter cards to the backside HSMC male connectors Doing so will permanently damage the on board FPGA B I O Distribution The HSMC connector on the TR4 includes a total of 172 pins including 121 signal pins 120 signal pins 1 PSNTn pin 39 power pins and 12 ground pins Figure 2 11 shows the signal bank diagram of HSMC connector Bank 1 also has dedicated JTAG I2C bus and clock signals The main CMOS LVDS interface signals including LVDS CMOS clocks are found in banks 2 and 3 Both 12V and 3 3V power pins are also found in banks 2 and 3 22 TR4 User Manual www terasic com www terasic com Bank 3 Power D 79 40 CLKIN2 CLKOUT2 Bank 2 Power 0 39 0 Or D 3 0 LVDS CLKIN1 CLKOUT1 Bank 1 Power 8 TX Channels CDR 8 RX Channels CDR JTAG SMBus CLKINO CLKOUTO Figure 2 11 HSMC Signal
127. vices DE pT a AT ADT Bg Jungo B8 TERASIC PCIe FPGA Board 7 Mice and other pointing devices 18 Monitors B8 Network adapters 7 Ports COM amp LPT Processors 8 0 Sound video and game controllers System devices Universal Serial Bus controllers Figure 6 11 Device Manager B Create a Software Application necessary files to create a PCIe software application are located in the PCIe SDKNLibrary which includes the following files TERASIC PCIE h TERASIC PCIE DLL Below lists the procedures to use the SDK files project e Create C C project Include TERASIC PCIE h in the project Copy TERASIC PCIE DLL to the folder where the project exe is located Dynamically load TERASIC PCIE DLL in project To load the DLL please refer to the two examples below e Call the SDK API to implement desired application B TERASIC PCIE DLL Software API Using the TERASIC PCIE DLL software API users can easily communicate with the FPGA through the PCIe bus The API details are described below 106 Terasic TR4 User Manual www terasic com www terasic com PCIE ScanCard Function Lists the PCIe cards which matches the given vendor ID and device ID Set Both ID to zero to lists the entire PCIe card Prototype BOOL PCIE ScanCard WORD wVendorlD WORD wDeviceID DWORD pdwDeviceNum PCIE CONFI
128. w terasic com Stratix IV GX Pin Number AN38 F8 AE10 AT36 AU38 AP36 AR38 AH36 AJ38 AF36 AG38 www terasic com Table 2 17 1 Express Pin Assignments Schematic Signal Names and Functions PCle1 4 Lane Downstream Name Description OStandard Stratix IV GX Pin Numbei PCIE1 REFCLK p Cle reference Jing AN2 clock Depends on HSMC PCIE1 PREST n PCle1 present Port ATO standard G8 Depends on HSMC PCIE1 WAKE n PCle1 wake ee ey PCIE1 TX 0 1 4 V PCML ATA PCIE1 RX 0 1 4 V PCML AU2 PCIE1 TX p 1 1 4 V PCML AP4 PCIE1 RX pfil 1 4 V PCML AR2 A PCIe1 data PCIE1 TX 2 1 1 datalane PCML AH4 PCIE1 2 1 4 V PCML AJ2 PCIE1 TX p 3 1 4 V PCML AF4 PCIE1 RX input AG2 2 10 Flash Memory The development board features a 64MB Intel CFI compliant NOR type flash memory device which is part of the shared FMS Bus consisting of flash memory SSRAM and the Max II CPLD EPM2210 System Controller The single synchronous flash memory with 16 bit data bus supports 4 word 8 word 16 word and continuous word burst mode provides non volatile storage that can be used for configuration as well as software storage The memory interface can sustain output synchronous burst read operations at 40MHz with zero wait states The device defaults to asynchronous page mode read when power up is initiated or returned from reset This device is also used to store configuration files for the Stratix IV GX
129. witches Pin Assignments Schematic Signal Names and Functions Name Locate Description VO Standard Stratix IV GX Pin Number SWO SLIDE SW Provides high VCCIO HSMF PIN AH18 SW1 SLIDE SW logic level VCCIO HSMF PIN AH19 SW2 SLIDE SW when in the HSMA PIN D6 SW3 SLIDE SW position VCCIO HSMA PIN C6 B LEDs The TR4 consists of 4 user controllable LEDs to allow status and debugging signals to be driven to the LEDs from the designs loaded into the Stratix IV GX device Each LED is driven directly by the Stratix IV GX FPGA The LED is turned on or off when the associated pins are driven to a low or high logic level respectively active low A list of the pin names on the FPGA that are connected to the LEDs is given in Table 2 6 21 TR4 User Manual www terasic com www terasic com Table 2 6 User LEDs Pin Assignments Schematic Signal Names and Functions Name Description Description Standard Stratix IV GX Pin Number D27 LEDO LEDs turn on when 1 5V PIN B19 D28 LED1 output is logic low 1 5V PIN A18 D29 LED2 Active low 1 5V PIN D19 D30 LED3 1 5V PIN C19 2 5 High Speed Mezzanine Cards The High Speed Mezzanine Card HSMC interface provides a mechanism to extend the peripheral set of an FPGA host board by means of add on daughter cards which can address today s high speed signaling reguirements as well as low speed device interface support The HSMC interfaces support JTAG clock outputs and inp
130. with GPIO The HSMC Port C shares the same FPGA I O pins with the GPIO expansion headers JP9 JP10 Hence none of the combinations above are allowed to be used simultaneously B Power Supply 27 TR4 User Manual www terasic com www terasic com ANOTE RYA The TR4 board provides 12V DC and 3 3V DC power through HSMC ports Table 2 11 indicates the maximum power consumption for all HSMC ports Please note that this table shows the total max current limit for all six ports not just for one Also the 12V DC and 3 3V DC power supplies from the HSMC ports have fuses for protection Users who don t need the power from the HSMC can remove these fuses to cut the power on connector CAUTION Before powering on the TR4 board with a daughter card please check to see if there is a short circuit between the power pins and FPGA I O Table 2 11 Power Supply of the HSMC Supplied Voltage Max Current Limit 12V 2A 3 3V 3A B Adjustable I O Standards The FPGA I O standards of the HSMC ports can be adjusted by configuring the header position Each port can be individually adjusted to 1 5V 1 8V 2 5V or 3 0V via jumpers on the top right corner of board Figure 2 14 depicts the position of the jumpers and their associated I O standards Users can use 2 pin jumpers to configure the I O standard by choosing the associated positions on the header Finally there are LEDs on the top right corner of TR4 board to
131. x IV GX Schematic Signal Name Description VO Standard 416 Pin Number 39 OUTO CMOS 1 0 LVDS or 2 5 20 40 HSMF_CLKINO Dedicated clock input LVDS 2 5 V 22 41 HSMF DO LVDS CMOS LVDSor2 5 V AU25 42 HSMF D1 LVDS or CMOS I O LVDSor2 5 V 26 43 HSMF D2 LVDS CMOSI O LVDSor2 5 V 25 44 HSMF D3 LVDS CMOS I O LVDSor2 5 v 26 47 HSMF TX d TX bit 0 or CMOS Vps or 2 5 V AV25 48 HSMF RX pO c RX bit 0 or CMOS ing or 25 AT26 LVDS TX bit On or 49 5 LVDS 2 5 25 LVDS RX bit On or 50 HSMF LVDS 2 5 26 53 HSMF TX TX bit 1 or CMOS Vins 2 5 25 54 HSMF RX bit 1 CMOS vb 25 AT24 LVDS TX bit in or 55 HSMF TX ni 11 LVDS or 2 5 25 LVDS RX bit 1n or 56 HSMF LVDS or2 5 V 24 59 HSMF TX p2 ad TX bit 2 or CMOS ng or 2 5 V AV23 60 HSMF RX p2 ad RX bit 2 or CMOS VDS or 2 5 V Jana LVDS TX bit 2n or 61 HSMF TX n2 LVDS 2 5 23 LVDS RX bit 2n or 62 HSMF n2 ID LVDS or2 5 V 24 65 HSMF TX p3 2 TX bit or CMOS VDS 2 5 23 66 HSMF RX p3 LVDS bit 3 or CMOSLVDS 2 5 23 Terasic TR4 User Manual www terasic com 137 www terasic com 67 68 71 72 73 74 77 78 79 80 83 84 85 86 89 90 91 92 95 96 97 98 1

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