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1. AN1060 Rev 1 0 308 MOTOROLA 1050 1060 1070 1080 1090 1099 1100 1102 1104 1106 1108 1110 1112 1114 1116 1118 1120 1122 1124 1129 1130 1140 1150 1160 1170 1180 1190 1200 1210 1220 1230 1250 1499 1500 1505 1510 1512 1513 1514 ESTS 1520 1530 1540 1550 1560 1564 1565 1570 1590 L525 1597 Application Note BYTECOUNT 16 X ADJUST FOR HIGH NIBBLE GOSUB 6000 GOSUB 7000 BYTECOUNT BYTECOUNT X ADD LOW NIBBLE BYTECOUNT 3 ADJUST FOR ADDRESS CHECKSUM REM NEXT 4 HEX DIGITS BECOME THE STARTING ADDRESS FOR THE DATA GOSUB 6000 FIRST NIBBLE OF ADDRESS GOSUB 7000 CONVERT TO DECIMAL ADDRESS 4096 X GOSUB 6000 NEXT NIBBLE GOSUB 7000 ADDRESS ADDRESS 256 X GOSUB 6000 GOSUB 7000 ADDRESS ADDRESS 16 X GOSUB 6000 GOSUB 7000 ADDRESS ADDRESS X ARRAYCNT ADDRESS ADRSTART INDEX INTO ARRA
2. Memory Map 0000 ET 0000 512 BYTES RAM EXT E 51000 7 1000 64 REGISTER BLOCK EXT EXT 103F 600 512 BYTES EEPROM B600 B7FF 8007 BFCO SPECIAL MODES EXT ROM INTERRUPT s x Ri BEFF grrr VECTORS D000 0000 12 KBYTES ROM EPROM FFCO NORMAL MODES INTERRUPT FFFF FFFF FFFF VECTORS SINGLE EXPANDED BOOTSTRAP SPECIAL CHIP TEST Figure 4 4 Memory Map for MC68HC 7 11E9 0000 0000 768 BYTES RAM EXT EXT 02 Y Y 1000 1000 A A 64 BYTE REGISTER BLOCK EXT EXT 103F Y Y 9000 8 KBYTES ROM EPROM 9000 AFFF B600 512 BYTES EEPROM Y Y 58600 B7FF prog 78007 BFCO SPECIAL MODES EXT LET J ROM INTERRUPT 22 1 VECTORS 50000 2000 12 KBYTES ROM EPROM NORMAL MODES eb INTERRUPT FFFF FFFF FFFF VECTORS SINGLE EXPANDED BOOTSTRAP SPECIAL CHIP TEST 20 Kbytes ROM EPROM are contained in two segments of 8 Kbytes and 12 Kbytes each Figure 4 5 Memory Map for MC68HC 7 11E20 MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 71 Operating Modes and On Chip Memory
3. Operation Description Addressing Instruction Condition Codes Mode Opcode Operand Cycles H 2 V CMPB opr Compare B to B M B IMM C1 ii 2 A A Memory B DIR 01 dd 3 B EXT F1 hh Il 4 B IND X E1 4 B IND Y 18 E1 ff b COM opr Ones 73 hh Il 6 0 Complement IND X 63 ff 6 Memory Byte IND Y 18 63 ff 7 COMA Ones FF A gt A A INH 43 2 0 Complement A COMB Ones FF gt 53 2 0 B CPD opr Compare D to D M M 1 IMM 1A 83 jj kk 5 A A A Memory 16 Bit DIR 1A 93 dd 6 EXT 1A B3 hh Il 7 IND X 1A A3 7 IND Y CD A3 7 CPX opr Compare X to IX M M 1 IMM 8C kk 4 eL Memory 16 Bit DIR 9C dd 5 EXT BC hh Il 6 IND X AC 6 IND Y CD AG 7 CPY opr Compare Y to IY M M 1 IMM 18 8C kk 5 S A A A Memory 16 Bit DIR 18 9C dd 6 EXT 18 BC hh Il 7 IND X 1A AC 7 IND Y 18 AC DAA Decimal Adjust Sum to BCD INH 19 2 A DEC Decremen 1 7A hh ll 6 A A A Memory Byte IND X 6A ff 6 IND Y 18 6A 7 DECA Decremen A 1 A A INH 4A 2 A A A Accumulator A DECB Decremen B 1 B B INH 2 A A A Accumulator B DES Decremen SP 1 gt SP INH 34 3 Stack Pointer DEX Decremen IX 1 gt 1X INH 09 3 Index Register X DEY Decremen IY 1 IY INH 18 09 4 Index Reg
4. Description CONFIG Temperature Frequency MC Order Number 52 pin plastic leaded chip carrier PLCC 2 MHz MC68HC11E9BCFN2 BUFFALO ROM 0F 409 to 85 C 3 MHz MC68HC11E9BCFN3 2 MHz MC68HC11E1CFN2 409 to 85 C 3 MHz MC68HC11E1CFN3 No ROM 0D 40 to 105 C 2 MHz MC68HC11E1VFN2 40 to 125 C 2MHz MC68HC11E1MFN2 2 MHz 6 11 2 409 to 85 C 3 MHz MC68HC11E0CFN3 No ROM no EEPROM 0C 40 to 105 C 2 MHz MC68HC11EO0VFN2 40 to 125 C 2 MHz MC68HC11EOMFN2 2 MHz MC68HC711E9CFN2 40 C to 85 C 3 MHz MC68HC711E9CFN3 OTPROM 0F 40 to 105 C 2 MHz MC68HC711E9VFN2 40 C to 125 C 2 MHz MC68HC711E9MFN2 Venhanged sauni 40 C to 85 C 2 MHz 688711 9 2 feature 0 C to 70 C 3 MHz MC68HC711E20FN3 2 MHz MC68HC711E20CFN2 409 to 85 C 20 Kbytes OTPROM 0F 3 MHz MC68HC711E20CFN3 40 C to 105 C 2 MHz MC68HC711E20VFN2 40 C to 125 C 2 MHz MC68HC711E20MFN2 0 C to 70 C 2 MHz MC68HC811E2FN2 409 to 85 C 2 MHz MC68HC811E2CFN2 No ROM 2 Kbytes EEPROM FF 40 C to 105 C 2 MHz MC68HC811E2VFN2 40 C to 125 C 2MHz MC68HC811E2MFN2 Technical Data MC68HC11E Family Rev 4 262 Ordering Information MOTOROLA Ordering Information Standard Device Ordering Information D
5. 0000 0000 256 5 RAM OOF F y y 51000 1000 A A 64 BYTE REGISTER BLOCK 103F EXT EXT BOOT BFCO SPECIAL MODES 00 ROM INTERRUPT eps BFFF 7 grrr VECTORS Y _ 2048 BYTES EEPROM F800 F800 NORMAL MODES ere INTERRUPT FFFF Y FFFF FFFF VECTORS SINGLE EXPANDED BOOTSTRAP SPECIAL CHIP TEST Figure 4 6 Memory Map for MC68HC811E2 Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read Port A Data Register PA7 PA6 PA5 PA4 PA3 PA2 PA1 PAO 1000 PORTA Write TERETE pause 0 0 0 1001 Reserved R R R R R R R R Read Parallel I O Control Register STAF STAI CWOM HNDS OIN PLS EGA INVB 1002 PIOC Write 141 GE 0 0 0 0 U 1 1 Unimplemented R Reserved U Unaffected 2 Indeterminate after reset Figure 4 7 Register and Control Bit Assignments Sheet 1 of 8 Technical Data MC68HC11E Family Rev 4 72 Operating Modes and On Chip Memory MOTOROLA Operating Modes Memory Memory Map Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read Port C Data Register PC7 PC6 5 4 PC3 PC2 PC1 0 51003 PORTC Write one eee Reset Indeterminate after reset Read Port B Data Register PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO 1004 PORTB Write 136
6. 170 Slave 170 System BINNS Lud phn ad aah oe KOK Ea aaa 171 sdb oi Mp 172 Serial Peripheral Control Register 173 Serial Peripheral Status Register 175 Serial Peripheral Data I O Register 176 Section 9 Timing System 10 be Fede RETA ERE EER 177 lj 178 WINGY DMU Pm 180 eke ae Cee eee eee oe 182 Timer Control Register2 183 Timer Input Capture Registers 184 Timer Input Capture 4 Output Compare 5 Register 186 15d 186 Timer Output Compare Registers 187 Timer Compare Force Register 190 Output Compare Mask Register 191 Output Compare Data Register 192 Timer Counter Register 193 Timer Control Register 1 _ 194 Timer Interrupt Mask 1 195 Timer Interrupt Flag 1 Register 196 MC68HC11E Family Rev 4 12 Table of Contents MOTOROLA Table of Contents 9 5 9 Timer Interrupt Mask 2 Register 196 9 5 10 Timer Interrupt Flag Register2 198 96 Real Time Interrupt RTI 199 9 6 1 Tim
7. 148 Wakeup 148 Idle Line Wakeup 150 Address Mark Wakeup 150 SCI Error Detection 151 SGI REJIS E ebak ARA 152 Serial Communications Data Register 152 Serial Communications Control Register 1 153 Serial Communications Control Register 2 154 Serial Communication Status Register 155 Baud Rate Register 157 Status Flags and Interrupts 160 162 Technical Data MOTOROLA Table of Contents 11 Table of Contents Technical Data 8 1 8 2 8 3 8 4 8 5 8 6 8 6 1 8 6 2 8 6 3 8 6 4 8 7 8 8 8 8 1 8 8 2 8 8 3 9 1 9 2 9 3 9 4 9 4 1 9 4 2 9 4 3 9 5 9 5 1 9 52 9 5 3 9 5 4 9 5 5 9 5 6 9 5 7 9 5 8 Section 8 Serial Peripheral Interface SPI Ton 165 INCE ci E EE A EEE EEO 166 Functional Description 2 2 4 222222 4 166 SPI Transier FOBYNNSIS od de RIO 168 Glock Phase and Polarity Controls 169 SEI casa iras qua s Q ope q ucap Q QB p end 169 Master In Slave Out 170 Master amia a 170 222222444
8. FD 13 characters 3906 4096 5859 6144 7812 8192 AN1060 Rev 1 0 316 MOTOROLA Listing 3 MC68HC711E9 Bootloader ROM 014 Q N P DO DOs EE pak C N Ir gt Q N S O 0008 000 0016 0023 Co WWW CO D 0080 w w O1 0028 002B 002D 002E 002F 003B C9 w N N P OW 0020 0001 am 1060 Rev 1 0 k k k k x CK CK k k lt k k x lt x k k k lt lt k k lt lt k x lt x k k lt x k lt lt lt x k lt lt lt x k x x lt BOOTLOADER FIRMWARE FOR 68HC711E9 21 Aug 89 k K K k k K K K K K K K K K K K K K K K K K K K K ck K K ck K K ck KOK K K KOK K K Features of this bootloader are Auto baud select between 7812 5 and 1200 8 MHz 0 512 byte variable length download Jump to EEPROM at 5 600 if 1st download byte 500 PROGRAM Utility subroutine to program EPROM UPLOAD Utility subroutine to dump memory to host Mask I D at SBFD4 571 9 KEK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KK KK KKK Revision A Fixed bug in PROGRAM routine where the first byte programmed into the EPROM was not transmitted for verify Also added to PROGRAM routine a skip of bytes This new versi
9. 199 Timer Interrupt Mask Register 2 200 Timer Interrupt Flag Register 2 201 Pulse Accumulator Control Register 202 Computer Operating Properly COP Watchdog Function 203 Pulse BAOBHDUIBIDI 64 Eo EC ER pa nA ORE ROO eR eRe 203 Pulse Accumulator Control Register 205 Pulse Accumulator Count Register 206 Pulse Accumulator Status and Interrupt Bits 207 Technical Data MOTOROLA Timing System 177 Timing System 9 2 Introduction Technical Data The M68HC11 timing system is composed of five clock divider chains The main clock divider chain includes a 16 bit free running counter which is driven by a programmable prescaler The main timer s programmable prescaler provides one of the four clocking rates to drive the 16 bit counter Two prescaler control bits select the prescale rate The prescaler output divides the system clock by 1 4 8 or 16 Taps off of this main clocking chain drive circuitry that generates the slower clocks used by the pulse accumulator the real time interrupt RTI and the computer operating properly COP watchdog subsystems also described in this section Refer to Figure 9 1 All main timer system activities are referenced to this free running counter The counter begins incrementing from 0000 as the MCU comes oul of reset and continues to the maximum count F
10. BIT X IN CCR 21 N XIRQ Y PIN LOW N STACK CPU REGISTERS Y SETBITSIAND X Y FETCH VECTO SFFF4 FFF5 R Figure 5 5 Processing Flow Out of Reset Sheet 1 of 2 MC68HC11E Family Rev 4 Technical Data MOTOROLA Resets and Interrupts Resets and Interrupts STACK CPU REGISTERS Y INTERRUPT PENDING STACK CPU REGISTERS Y SET I IN W FETCH VECTOR STACK CPU FFF8 FFF9 INSTRUCTION REGISTERS mmr STACK CPU Y REGISTERS INTERRUPT Y PENDING SET BIT Y Y FETCH VECTOR SET BIT CCR FFF6 FFF7 Y RESOLVE INTERRUPT RESTORE CPU REGISTERS VECTOR FORHIC NEST FROM STACK EXECUTE THIS PENDING SOURCE INSTRUCTION SEE FIGURE 5 2 Ab y Figure 5 5 Processing Flow Out of Reset Sheet 2 of 2 Technical Data MC68HC11E Family Rev 4 126 Resets and Interrupts MOTOROLA Resets Interrupts Interrupts MN SET X BIT IN FETCH VECTOR FFF4 FFF5 HIGHEST VES PRIORITY FETCHVECTOR gt INTERRUPT FETCH VECTOR FFF2 FFF3 gt REAL TIME FETCH VECTOR
11. N 1 Symbol Unit um isti mbo ni Characteristic y Min Max Min Max Frequency of operation fo dc 20 de 20 period 500 500 ns Operating frequency Master fop m 1 32 1 2 1 128 1 2 MHz Slave fop s dc fo dc fo Cycle time 1 Master lcyc m 2 32 2 128 Slave teye s 1 1 Enable lead time 2 2 t 1 1 t Slave lead s cyc Enable lag time 3 t 1 1 t Slave lag s 5 high time 4 Master tw SCKH m lcyc 30 16 lcyc 30 64 ns Slave tw SCKH s 1 2 30 1 2 30 low time 5 Master tw SCKL m lcyc 30 16 tcyc 30 64 ns Slave tw SCKL s 1 2 30 1 2 30 Data setup time inputs 6 Master lsu m 40 40 ns Slave tsu s 40 40 Data hold time inputs 7 Master 40 40 ns Slave this 40 40 Slave access time 8 0 ta 0 50 0 50 ns CPHA 1 0 50 0 50 Disable time hold time 9 to high impedance state ldis 60 60 ns Slave 10 Data after enable edge ty 60 60 ns Data hold time outputs 4 after enable edge hig 0 is otherwise noted 2 Time to data active from high impedance state 3 Assumes 100 pF load on SCK MOSI and MISO pins MC68HC11E Family Rev 4 Vpp 3 0 Vdc to 5 5 Vdc Vss 0 Vac T4 T to Ty all timing is shown with respect to 20 V
12. L Vepe applies only to devices with EPROM OTPROM Figure 2 2 Pin Assignments for 64 Pin QFP Technical Data MOTOROLA Pin Descriptions 29 Pin Descriptions Technical Data PASZS OC5 C4 OC1 PAA OCA OC1 PAG OC2 OC1 L2 L2 PD5YSS N U a 2 1 L3 PD4 SCK 49 46 PB7 ADDR15 P B6 ADDR 14 i P B5 ADDR 13 i PBA ADDR12 i PB3 ADDR11 i PB2 ADDR 10 T PB1 ADDR9 i PBO ADDR8 PEO ANO PE4 AN4 1 PE5 AN5 i M68HC11E SERIES 14 17 PEZ AN2 PEG ANG C1 PEZ AN7 Va Va PD3YMOSI L3 PD2 MISO L3 PD1 T gt D 41 H 7 7 7 H PC6 ADDR6 DATA6 pP C5 ADDR5 DATA5 H PC4 ADDR4 DATA4 EP C3 ADDR3 DATA3 p 31P C2 ADDR2 DATA2 H PC1 ADDR1 DATA1 H PC0 ADDR0 DATA0 H XTAL Vppe applies only to devices with EPROM OTPROM Figure 2 3 Pin Assignments for 52 Pin TQFP MC68HC11E Family Rev 4 30 Pin Descriptions MOTOROLA Pin Descriptions Introduction Vss Hi 1 MODBNstey gt MODAJ LIR Vni STRA AS PE3 AN3 STRB R W PE6 ANG EXTAL 7 PE2 AN2 XTAL Jg PES ANS PCO ADDRO DATAO PET ANI PCI ADDRI DATA1 PE4JAN4 PC2 ADDR2 DATA2 PEO ANO PC3 ADDR3 DATA3 PBO ADDR8B PC4 ADDR4 DATA4 PBI ADDRO PCS5 ADDRS DAT
13. 219 Technical Data MC68HC11E Family Rev 4 22 List of Tables MOTOROLA Technical Data M68HC11E Family 1 1 Contents 1 2 Introduction Section 1 General Description 1 2 nili od Uc OE a cca dde CER eov o do RR 23 1 3 Feats uuu cuu a Sie qox od Res a ROC RC d ge 24 1 4 oe ice aao Oe ee eram Rae dus sa 25 This document contains a detailed description of the M68HC11 E series of 8 bit microcontroller units MCUs These MCUs all combine the M68HC1 1 central processor unit CPU with high performance on chip peripherals The E series is comprised of many devices with various configurations of e Random access memory RAM e Read only memory ROM Erasable programmable read only memory EPROM Electrically erasable programmable read only memory EEPROM Several low voltage devices are also available With the exception of a few minor differences the operation of all E series MCUs is identical A fully static design and high density complementary metal oxide semiconductor HCMOS fabrication process allow the E series devices to operate at frequencies from 3 MHz to with very low power consumption MC68HC11E Family Rev 4 Technical Data MOTOROLA General Description 23 General Description 1 3 Features Technical Data Features of the E series devices include M68HC11 CPU Power saving stop and wait modes Low vol
14. EE ee RE 68 44 Memory 69 4 4 1 RAM and Input Output Mapping 80 4 4 2 Mode BONES d n KARE n C OR papa 82 4 4 3 System 85 4 4 3 1 System Configuration Register 86 4 4 3 2 RAM and I O Mapping Register 89 4 4 3 3 System Configuration Options Register 91 45 2 gt gt 2 2 lt lt gt 4 lt 25 92 4 5 1 Programming an Individual EPROM Address 93 4 5 2 Programming the EPROM with Downloaded Data 94 4 5 3 EPROM and EEPROM Programming Control Register 94 AG EEPROM aaa dad d d dud R16 A dE DR Edda ae ddl dea 98 4 6 1 EEPROM and CONFIG Programming and Erasure 98 4 6 1 1 Block Protect Register 99 4 6 1 2 EPROM and EEPROM Programming Control FOURS 101 4 6 1 3 EEPROM Bulk Erase 103 4 6 1 4 EEPROM How gt 25 555 5824 6 54 103 4 6 1 5 EEPROM Byte 104 4 6 1 6 CONFIG Register Programming 104 4 6 2 EEFBUM SECU wawa 104 MC68HC11E Family Rev 4 Technical Data MOTOROLA Table of Contents 9 Table of Contents Section 5 Resets and Interrupts ec cid Obs Sar a pe M ee de Dd
15. 18 30 4 Pointer to Y TXS Transfer X to IX 1 SP INH 35 3 Stack Pointer TYS Transfer Y to IY 12 SP INH 18 35 4 Stack Pointer WAI Wait for Stack Regs amp WAIT INH 3E Interrupt XGDX Exchange D IX gt D D gt IX INH 8F 3 with X XGDY Exchange D Y gt D D gt IY INH 18 8F 4 with Y Cycle d Infinity or until reset occurs t 12 cycles are used beginning with the opcode fetch A wait state is entered which remains in effect for an integer number of MPU E clock cycles n until an interrupt is recognized Finally two additional cycles are used to fetch the appropriate interrupt vector 14 n total Operands dd 8 bit direct address 0000 00FF high byte assumed to be 00 ff 8 bit positive offset 00 0 to FF 255 is added to index hh High order byte of 16 bit extended address ii One byte of immediate data ji High order byte of 16 bit immediate data kk Low order byte of 16 bit immediate data ll Low order byte of 16 bit extended address mm 8 bit mask set bits to be affected rr Signed relative offset 80 128 to 7F 127 offset relative to address following machine code offset byte Operators Contents of register shown inside parentheses Is transferred to ft Is pulled from stack U Is pushed onto stack Boolean AND Arithmetic addition symbol except where used as inclusive OR symbol in Boolean formula e Exclusive OR Multiply Concatenation _ Arithme
16. 3 3 6 8 STOP Disable S md 1068 5644485 ee eds 3 5 Opcodes Operands 3 6 Addressing Modes 3 6 1 Immediate 3 6 2 ll APPETIT 3 6 3 EXISDOUU sos 43 P WIE ER FUR RR ERR 3 6 4 j AME MP 3 6 5 MEMS on 522 3 6 6 ee ed er Iusiniuon 01 axes doa doce MC68HC11E Family Rev 4 Technical Data MOTOROLA Central Processor Unit CPU 45 Central Processor Unit CPU 3 2 Introduction This section presents information on M68HC11 Central processor unit CPU architecture Data types Addressing modes Instruction set Special operations such as subroutine calls and interrupts The CPU is designed to treat all peripheral input output I O and memory locations identically as addresses in the 64 Kbyte memory map This is referred to as memory mapped I O There no special instructions for I O that are separate from those used for memory This architecture also allows accessing an operand from an external memory location with no execution time penalty 3 3 CPU Registers M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations The seven registers discussed in the following paragraphs are shown in Figure 3 1 Technical Data MC68HC11E Family Rev 4 46 Central Processor Unit CPU MOTOROLA
17. Characteristic 55040 70 Unit Programming time 3 V E lt 2 0 MHz RCO enabled 25 ms 5 V E lt 2 0 MHz RCO enabled 10 Erase time byte row and bulk 3 V E lt 2 0 MHz RCO enabled 25 ms 5 V E lt 2 0 MHz RCO enabled 10 Write erase endurance 10 000 Cycles Data retention 10 Years 1 Vpp 3 0 Vdc to 5 5 Vss 0 to 2 The RC oscillator RCO must be enabled by setting the CSEL bit in the OPTION register for EEPROM programming and erasure Technical Data MC68HC11E Family Rev 4 250 Electrical Characteristics MOTOROLA Electrical Characteristics EPROM Characteristics 11 22 EPROM Characteristics Characteristics Symbol Min Typ Max Unit Programming voltage VppE 11 75 12 25 12 75 V Programming current 2 3 10 mA Programming time 2 2 4 ms 1 Vpp 5 0 Vdc 1096 2 Typically a 1 kQ series resistor is sufficient to limit the programming current for the MC68HC711E9 100 0 series resistor is sufficient to limit the programming current for the MC68HC711E20 MC68HC11E Family Rev 4 Technical Data MOTOROLA Electrical Characteristics 251 Electrical Characteristics Technical Data MC68HC11E Family Rev 4 252 Electrical Characteristics MOTOROLA Technical Data M68HC11E Family 12 1 Contents 12 2 Introduction 12 2 12 3 12 4 12 5 12 6 12 7 12 8 Section 12 Mechanica
18. ADDR11 PB4 PB4 ADDR12 PB5 PB5 ADDR13 PB6 PB6 ADDR14 PB7 PB7 ADDR15 PC0 PC0 ADDRO DATAO PC1 PC1 ADDR1 DATA1 PC2 PC2 ADDR2 DATA2 PC3 PC3 ADDR3 DATA3 PC4 PC4 ADDR4 DATA4 PC5 PC5 ADDRS5 DATA5 PC6 PC6 ADDR6 DATA6 PC7 PC7 ADDR7 DATA7 PDO PDO RxD PD1 PD1 TxD PD2 PD2 MISO PD3 MOSI PD4 PD4 SCK PD5 PD5 SS STRA AS STRB R W PE0 PE0 AN0 PE1 PE1 AN1 PE2 PE3 AN2 PE3 PE3 AN3 PE4 PE4 AN4 PE5 PE5 AN5 PE6 PE6 AN6 PE7 PE7 AN7 MC68HC11E Family Rev 4 40 Pin Descriptions MOTOROLA 2 13 2 Port B Pin Descriptions Port Signals can function as general purpose or as timer output compare for OC1 PA7 is also the input to the pulse accumulator even while functioning as a general purpose or an OC1 output 4 serve as either general purpose outputs timer input captures or timer output compare 2 4 In addition 6 4 can be controlled by OC1 can be a general purpose pin or a timer IC OC pin Timer functions associated with this pin include OC1 and IC4 OC5 IC4 OC5 is software selectable as either a fourth input capture or a fifth output compare can also be configured to allow OC1 edges to trigger IC4 captures 2 serve as general purpose inputs or as IC1 1C3 PORTA can be read at any time Reads of pins configured as inputs return the logic level present on the pin Pins configured as outputs return the logic level present at the
19. MOTOROLA Table of Contents 13 Table of Contents 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 11 11 11 12 11 13 11 14 11 16 11 17 11 18 11 19 11 20 11 21 11 22 Technical Data Section 11 Electrical Characteristics os race SER EROR 221 li iss NDA TM PRINTED s u k ak 222 Maximum Ratings for Standard and Extended Voltage 222 Functional Operating Range 223 Thermal Characteristics 223 DC Electrical Characteristics 224 Supply Currents and Power Dissipation 225 MC68L11E9 E20 DC Electrical Characteristics 226 MC68L11E9 E20 Supply Currents and Power Dissipation 227 eRe REA NO CR d CR ee 229 MC68L11E9 E20 Control Timing 230 Peripheral Port Timing 235 681 11 9 20 Peripheral Port Timing 236 Analog to Digital Converter Characteristics 240 MC68L11E9 E20 Analog to Digital Converter Characteristics _ 241 Expansion Bus Timing 242 MC68L11E9 E20 Expansion Bus Timing Characteristics 244 Serial Peripheral Interface Timing Characteristics 246 MC68L11E9 E20 Serial Peirpheral Interface Characteristics
20. Cycle time 1 Master 2 32 2 128 Slave 1 1 Enable lead time 2 t 1 1 t Slave lead s cyc Enable lag time 3 t 1 1 t Slave lag s 5 high time 4 Master tw SCKH m 25 16 lcyc 725 64 ns Slave tw SCKH s 1 2 25 1 2 25 5 low time 5 Master twisckLym teye 25 16 25 64 ns Slave tw SCKL s 1 2 25 1 2 25 Data setup time inputs 6 Master lsu m 30 30 ns Slave tsu s 30 30 Data hold time inputs 7 Master thm 30 30 ns Slave th s 30 30 Slave access time 8 CPHA 0 ta 0 40 0 40 ns 1 0 40 0 40 Disable time hold time 9 to high impedance state ldis 50 50 ns Slave 10 Data valid 9 after enable edge ty 50 50 ns Data hold time outputs 2 n after enable edge tho 2 b a otherwise noted 2 Time to data active from high impedance state 3 Assumes 200 pF load on SCK MOSI and MISO pins Technical Data Vpp 5 0 10 Vss 0 TA T to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless MC68HC11E Family Rev 4 246 Electrical Characteristics MOTOROLA Electrical Characteristics MC68L11E9 E20 Serial Peirpheral Interface Characteristics 11 19 MC68L11E9 E20 Serial Peirpheral Interface Characteristics
21. E S E PEERS H I 8 Notes 1 Edge sensitive IRQ pin IRQE bit 1 2 Level sensitive IRQ pin IRQE bit 0 Figure 11 6 Interrupt Timing Diagram m O m e m O 0 Electrical Characteristics Peripheral Port Timing 11 12 Peripheral Port Timing Characteristic 2 Frequency of operation E clock frequency E clock period Peripheral data setup time MCU read of ports D and E Peripheral data hold time MCU read of ports D and E Delay time peripheral data write tpwp 1 4 100 ns MCU writes to port A MCU writes to ports B C and D Port C input data setup time Port C input data hold time Delay time E fall to STRB tDEB 1 4 100 ns Delay time STRA asserted to port data 565 100 100 100 output valid Hold time STRA negated to port data time STRA Hold time STRA negated to port data to port C data I saa ae 1 Vpp 5 0 Vdc z 10 Vss 0 Vdc TA T to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 Ports C and D timing is valid for active drive CWOM and DWOM bits are not set in PIOC and SPCR registers respectively 3 If this setup time is met STRB acknowledges in the next cycle If it is not met the response be delayed one more cycle MC68HC11E Family Rev 4 Technical Data MOTOROLA Electrical Characteristics 235
22. P RBS 37 MCUS7 17 muz 5 BABL 35 MU 29 SS ae s PASOC3 PBZ A15 i MOUBL Mcuz7 27 Apo 9 de pr HO E MELO 5 MCU2O 20 VADI 3 wcun PDORXD MCU21 21 12 MCUI2 MCUI9 RO J2 R4 muz gt gt FUVTXD PC3ADB 15 MUL 9 gt MU PEQ MCU23 23 I PC AD4 14 wena 3 MCU2A 24 P 15 mous EN muz 25 5 CO D6 16 mouie MCUS MODY _ _ 55 PC7AD7 ED MUB B 5 MCU2 1 45 45 E PE1 6 MCUA7 47 STRE RAV PE2 16 5 5 MCUAS9 49 u 17 NMCU17 22 gli muag as PE4 iro 212 19 T E inc 1S 15 48 pre 2 1 m MCUSD 50 pg MEOMUR gt 1 1 MODBM sry MCUS2 Va MUS 52 lt NOTE 1 CONNECTOR DB25 MCUSI 51 LS EXTAL 1 8 opf Vss XTAL adin R2 mas o MCeBHCTIESEN 10M 24 9 NA 9 1 GND x ES USER S TERMINAL OR PC 23 MASTER RESET w i 10 x o 1 22 cs 9 1 Voc 1 27pF 27pF 21 9 RNIA NOTE 1 RNIE ca 0 DCD 8 x U2 47K 47K ER 2 10uF NL DIR 20 2 J9 6 20v T 2 INPUT 0 MCUI7 RESET PDVTXD 2 1 1 19 RESE Ld 17 3 18 1 Veo 6 18 SIE 1 14 18 1 55 L maor MUO 41 124 T 3 2 1 gt
23. As soon as the first byte is verified the third byte is sent In the meantime the MCU has already started programming the second byte This process of verifying and queueing a byte continues until the host finishes sending data If the programming is completely successful no error messages will have been displayed at the top of the screen Subroutines follow the end of the program to handle some of the repetitive tasks These routines are short and the commenting in the source code should be sufficient explanation AN1060 Rev 1 0 MOTOROLA 305 Application Note Modifications Operation This example programmed version 3 4 of the BUFFALO monitor into the EPROM of an MC68HC711E9 the changes to the BASIC program to download some other program are minor The necessary changes are 1 Inline 30 the length of the program to be downloaded must be assigned to the variable CODESIZE 2 Also in line 30 the starting address of the program is assigned to the variable ADRSTART 3 Inline 9570 the start address of the program is stored in the third and fourth items in that DATA statement in hexadecimal 4 If any changes are made to the number of bytes in the boot code in the DATA statements in lines 9500 9580 then the new count must be set in the variable BOOTCOUNT in line 25 Configure the EVBU for boot mode operation by putting a jumper at J3 Ensure that the trace command jumper at J7 is not installed because this
24. EEEE S 152 Serial Communications Data Register 152 Serial Communications Control Register 1 158 Serial Communications Control Register 2 154 Serial Communication Status Register 155 Baud Rate Register 157 Status Flags and Interrupts 160 Receiver Fags 6 45 534 Ow 162 The serial communications interface SCI is a universal asynchronous receiver transmitter UART one of two independent serial input output I O subsystems in the M68HC11 E series of microcontrollers It has a standard non return to zero NRZ format one start bit eight or nine data bits and one stop bit Several baud rates are available The SCI MC68HC11E Family Rev 4 Technical Data MOTOROLA Serial Communications Interface SCI 145 Serial Communications Interface SCI 7 3 Data Format transmitter and receiver are independent but use the same data format and bit rate All members of the E series contain the same SCI with one exception The SCI system in the MC68HC11E20 and MC68HC711E20 MCUs have an enhanced SCI baud rate generator A divide by 39 stage has been added that is enabled by an extra bit in the BAUD register This increases the available SCI baud rate selections Refer to Figure 7 8 and 7 8 5 Baud Rate Register The serial data format requires these conditions 1 An idle line in the high stat
25. Output Compare 1 Data Register OC1D Timer Counter Register Timer Control Register 1 1 Timer Interrupt Mask 1 Register TMSK1 Timer Interrupt Flag 1 Register TFLG1 Timer Interrupt Mask 2 Register TMSK2 Timer Interrupt Flag 2 Register TFLG2 Timer Interrupt Mask 2 Register TMSK2 Timer Interrupt Flag 2 Register TFLG2 Pulse Accumulator Control Register PACTL Pulse Accumulator List of Figures Technical Data MOTOROLA List of Figures 19 List of Figures Figure 9 25 9 26 8 27 9 28 10 1 10 2 10 3 10 4 10 5 10 6 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 11 11 11 12 11 13 11 14 11 15 1 Technical Data Title Page Pulse Accumulator Control Register PACTL 205 Pulse Accumulator Count Register PACNT 206 Timer Interrupt Mask 2 Register TMSK2 207 Timer Interrupt Flag 2 Register TFLG2 207 A D Converter Block Diagram 211 Electrical Model of an A D Input Pin Sample 211 A D Conversion Sequence 213 System Configuration Options Register OPTION 214 A D Control Status Register ADCTL 218 Analog to Digital Converter Result Registers 1 4 220 Test 22d case chee bo ORO dob kool
26. 124 5 6 5 Maskable Interrupts 124 5 6 6 Reset and Interrupt Processing 124 br Low Power OperallOfi k sd scd doe C or Kade 129 2 41 Wat MOGE ninmiki A E 130 5 7 2 130 MC68HC11E Family Rev 4 10 Table of Contents MOTOROLA 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 1 7 2 7 3 7 4 ia 7 6 7 6 1 7 6 2 7 7 7 8 7 8 1 7 8 2 7 8 3 7 8 4 7 8 5 im 7 10 MC68HC11E Family Rev 4 Table of Contents Section 6 Parallel Input Output I O Ports ied RUE eae eee e 133 nier bes l uuu te a ah gs a 133 MR ed M NAE uama uc RURAL 134 B eoo sx od ee 136 EUN D es eX ed 136 D aca aod eee cad ud 138 pus sega ces 139 Handshake 139 Parallel Control Register 141 Section 7 Serial Communications Interface SCI 145 2 2 145 Data quwaq yaqa iwa qaa 146 Transmit Operation 146 Receive Operation
27. 214 Conversion Process 215 Channel Assignments 216 Single Channel Operation 216 Multiple Channel Operation 217 Operation in Stop and Wait 217 A D Control Status 218 A D Converter Result Registers 220 The analog to digital A D system a successive approximation converter uses an all capacitive charge redistribution technique to convert analog signals to digital values MC68HC11E Family Rev 4 Technical Data MOTOROLA Analog to Digital A D Converter 209 Analog to Digital A D Converter 10 3 Overview 10 3 1 Multiplexer Technical Data The A D system is an 8 channel 8 bit multiplexed input converter The converter does not require external sample and hold circuits because of the type of charge redistribution technique used A D converter timing can be synchronized to the system E clock or to an internal resistor capacitor RC oscillator A D converter system consists of four functional blocks multiplexer analog converter digital control and result storage Refer to Figure 10 1 The multiplexer selects one of 16 inputs for conversion Input selection is controlled by the value of bits CD CA in the ADCTL register The eight port E pins are fixed direction analog inputs to the multiplexe
28. 247 EEPROM Characteristics 250 MC68L11E9 E20 EEPROM Characteristics 250 EPROM 15 eA REA ORT OSS 251 MC68HC11E Family Rev 4 14 Table of Contents MOTOROLA Table of Contents Section 12 Mechanical Data Contents 253 12 2 u us uuu sa qn de RR b sey 253 12 3 52 Plastic Leaded Chip Carrier Case 778 254 12 4 52 Pin Windowed Ceramic Leaded Chip Carrier Case 778 255 12 5 64 Quad Flat Pack Case 840C 256 12 6 52 Pin Thin Quad Flat Pack Case 848D 257 12 7 56 Dual in Line Package Case 859 258 12 8 48 Plastic DIP Case 767 259 Section 13 Ordering Information COMENS repr 261 132 ukyasaq aa aqu 261 13 3 Standard Device Ordering Information 262 13 4 Custom ROM Device Ordering Information 265 13 5 Extended Voltage Device Ordering Information 30 Vde t0 5 5 VACI wd YA dre DOUCEUR OR RR 267 Appendix A Development Support j t OON Lo pi Edo do e SERIEN eed Jub Roa p a PCR 269 A2 0000 ee ees 269 Motorola M68HC11 E Series Development Tools 270 4 EVS Evaluation 270 A 5 Motorola Modular Development System MMDS11 271
29. 27 15 6 crs O 16 D pa 5 e 4 NOTE 1 ma 115 26 13 8 2 1 XD 3 a 7 15 11 522 Peo lt 15 ra NOTE 1 F 19 gt 1 VacO 9 Vv a 145407 O1HF Notes 94s 1 Default cut traces installed from factory on bottom of the board 2 X1 is shipped as a ceramic resonator with built in capacitors Holes are provided for a crystal and two Figure 1 EVBU Schematic Diagram m lt w 2 gt 1 3 Order this document by AN1060 D Rev 1 0 Motorola Semiconductor Application Note AN1060 M68HC11 Bootstrap Mode By Jim Sibigtroth Mike Rhoades and John Langan Austin Texas Introduction Motorola Inc 1999 The M68HC11 Family of MCUSs microcontroller units has a bootstrap mode that allows a user defined program to be loaded into the internal random access memory RAM by way of the serial communications interface 5 the M68HC11 then executes this loaded program The loaded program can do anything a normal user program can do as well as anything a factory test program can do because protected control bits are accessible in bootstrap mode Although the bootstrap mode is a single chip mode of operation expanded mode resources are accessible because the mode control bits can be changed while operating in the bootstrap mode This application note explains the operation and a
30. 325 Engineering Bulletin Step 8 Step 9 Step 10 NOTE NOTE You are now ready to enable the security feature on the MCHC711E9 At the PCbug11 command prompt type MS 103F 05 After the programming operation is complete verifyng the CONFIG on the MCHC711E9 is not possible because in bootstrap mode the default value is always forced The part is now in secure mode and whatever code you loaded into EEPROM will be erased if you tried to bring the microcontroller up in either expanded mode or bootstrap mode It is important to note that the microcontroller will work properly in secure mode only in single chip mode If the part is placed in bootstrap or expanded the code in EEPROM and RAM will be erased and the microcontroller cannot be reused The security software will constantly read the NOSEC bit and lock the part EB184 326 MOTOROLA Order this document by EB188 Motorola Semiconductor Engineering Bulletin EB188 Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR By Edgar Saenz Austin Texas Introduction NOTE Motorola Inc 1998 The PCbug11 software needed along with the M68HC711E9PGMR to program MC68HC811E2 devices is available from the download section of the Microcontroller Worldwide Web site http www motorola com semiconductors Retrieve the file pcbug342 exe a self extracting archive from the MCU11 directory Some Motorola eval
31. Central Processor Unit CPU CPU Registers A 0 7 B 0 8 BIT ACCUMULATORS A amp B 15 D 0 OR 16 BIT DOUBLE ACCUMULATOR D IX INDEX REGISTER X IY INDEX REGISTER Y SP STACK POINTER PC PROGRAM COUNTER 1 0 S X H I N Z vc CONDITION CODES FROM MSB OVERFLOW ZERO NEGATIVE I INTERRUPT MASK HALF CARRY FROM BIT 3 X INTERRUPT MASK STOP DISABLE Figure 3 1 Programming Model 3 3 1 Accumulators and D Accumulators A and B are general purpose 8 bit registers that hold operands and results of arithmetic calculations or data manipulations For some instructions these two accumulators are treated as a single double byte 16 bit accumulator called accumulator D Although most instructions can use accumulators A or B interchangeably these exceptions apply The and ABY instructions add the contents of 8 bit accumulator B to the contents of 16 bit register X or Y but there are no equivalent instructions that use A instead of B The TAP and TPA instructions transfer data from accumulator A to the condition code register or from the condition code register to accumulator A However there are no equivalent instructions that use B rather than A MC68HC11E Family Rev 4 Technical Data MOTOROLA Central Processor Unit CPU 47 Central Processor Unit CPU The decimal adjust accumulator DAA instruction is used after
32. Configure IRQ for Edge Sensitive Only Operation Bit Refer to Section 5 Resets and Interrupts DL Y Enable Oscillator Startup Delay Bit 0 The oscillator startup delay coming out of stop mode is bypassed and the MCU resumes processing within about four bus cycles 1 A delay of approximately 4000 E clock cycles is imposed as the MCU is started up from the stop power saving mode This delay allows the crystal oscillator to stabilize MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 91 Operating Modes Memory CME Clock Monitor Enable Bit Refer to Section 5 Resets and Interrupts Bit 2 Not implemented Always reads 0 CR 1 0 COP Timer Rate Select Bits The internal E clock is divided by 215 before it enters the COP watchdog system These control bits determine a scaling factor for the watchdog timer Refer to Section 5 Resets and Interrupts 4 5 EPROM OTPROM Certain devices in the M68HC11 E series include on chip EPROM OTPROM For instance The MC68HC711E9 devices contain 12 Kbytes of on chip EPROM OTPROM in non windowed package The MC68HC711E20 has 20 Kbytes of EPROM OTPROM in non windowed package The MC68HC711E32 has 32 Kbytes of EPROM OTPROM in non windowed package Standard MC68HC71E9 and MC68HC71 1E20 devices are shipped with the EPROM OTPROM contents erased all 1s The programming operation programs Os Windowed device
33. OO 7F103D 8604 9728 8680 9704 132 20 86FF 972F CEB675 8D53 8CB67D 26F9 AN1060 Rev 1 0 Ck Ck Ck lt k k lt lt CK CI lt Ck CK lt lt lt k k CK k k k k ko ko KKK 68HC711 F9 Duplicator Program for AN1060 CA CKCK k x CK CK k k lt k k lt lt k KC lt lt k amp lt k k k amp amp k k k k k k k k ko ko X X KKKKK Equates All reg addrs except INIT 2 digit for direct addressing EQU 103D RAM Reg mapping SPCR EQU 528 DWOM bit 5 504 Red LED bit 1 Grn 1 0 Reset of prog socket Dit 7 RESET EQU 10000000 RED EQU 00000010 GREEN EQU 00000001 PORTE EQU 0A Vpp Sense in bit 7 1 SCSR EQU 52 5 status register TDRE IDLE OR NF FE TDRE EQU 10000000 RDRF EQU 00100000 SCDR EQU 2 register PROGRAM EQU BF00 EPROM prog utility in boot ROM EPSTRT EQU 5 000 Starting address of EPROM ORG SB600 Start of EEPROM k Ck Ck Ck k k CK CK lt k k k lt lt k k K lt lt k k lt k k k amp lt k k amp k k k x k k k ko ko k X lt WT4BRK BLLOOP KKKKK CLR INIT Moves Registers to 0000 3F LDAA 504 Pattern for DWOM off no SPI STAA SPCR Turns off DWOM
34. Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 99 Operating Modes Memory PTCON Protect CONFIG Register Bit 0 CONFIG register can be programmed or erased normally 1 CONFIG register cannot be programmed or erased BPRT 3 0 Block Protect Bits for EEPROM When set these bits protect a block of EEPROM from being programmed or electronically erased Ultraviolet light however can erase the entire EEPROM contents regardless of BPRT 3 0 windowed packages only Refer to Table 4 6 and Table 4 7 When cleared BPRT 3 0 allow programming and erasure of the associated block Table 4 6 EEPROM Block Protect Bit Name Block Protected Block Size BPRTO B600 B61F 32 bytes BPRT1 B620 B65F 64 bytes BPRT2 B660 B6DF 128 bytes BPRT3 B6E0 B7FF 288 bytes Table 4 7 EEPROM Block Protect in MC68HC811E2 MCUs Bit Name Block Protected Block Size BPRTO x800 x9FF 512 bytes BPRT1 xA00 xBFF 512 bytes BPRT2 xC00 xDFF 512 bytes BPRT3 xE00 xFFF 512 bytes 1 x is determined by the value of EE 3 0 in CONFIG register Refer to Figure 4 13 Technical Data MC68HC11E Family Rev 4 100 Operating Modes and On Chip Memory MOTOROLA Operating Modes Memory EEPROM 4 6 1 2 EPROM and EEPROM Programming Control Register The EPROM and EEPROM programming control register PPROG selects and co
35. S878 25 4a Eand AS rise time ty 20 20 20 ns 4b E and AS fall time lr 20 20 15 ns Address hold time t 5 E i taH 1 8 toy 29 5 ns AH 95 5 33 26 A Non multiplexed address valid time to E rise t 2 4 4 tay tasp 80 ns 9 281 5 9 5 ns 17 Read data setup time tpsR 30 30 30 ns Read data hold time i 0 1455 o 83 o 51 ns Write data delay time 1 8 teye 65 5 ns 9 toow 1905 128 71 ns Write data hold time i 1 8 29 5 2 tpHw 95 5 33 26 m Ag Multiplexed address valid time to E rise t BS _ tavm PWg 90 5 2 3 a AVM 271 5 84 54 d T Multiplexed address valid time to AS fall i ie n w tas 70 ns ASL 25 Multiplexed address hold time tau 1 8 29 5 2 9 AHL 5 2E Continued Technical Data MC68HC11E Family Rev 4 242 Electrical Characteristics MOTOROLA Electrical Characteristics Expansion Bus Timing Characteristics 1 0 MHz 2 0 MHz 3 0 MHz Num Characteristic Symbol Unit Min Min Min T Delay time E to AS rise d ai tasn 1 8 toyo 9 5 ns a ASD B as Pulse width AS high PW EN 7 PWasH 1 4 toyo 29 ns MPH pi
36. SMOD and MDA Special Mode Select and Mode Select A Bits The initial value of SMOD is the inverse of the logic level present on the MODB pin at the rising edge of reset The initial value of MDA equals the logic level present on the MODA pin at the rising edge of reset These two bits can be read at any time They can be written anytime in special modes MDA can be written only once in normal modes SMOD cannot be set once it has been cleared MC68HC11E Family Rev 4 Input Latched at Reset Mode MODB MODA SMOD MDA 1 0 Single chip 0 0 1 1 Expanded 0 1 0 0 Bootstrap 1 0 0 1 Special test 1 1 Technical Data MOTOROLA Operating Modes and On Chip Memory 83 Operating Modes Memory IRV NE Internal Read Visibility Not E Bit IRVNE can be written once in any mode In expanded modes IRVNE determines whether IRV is on or off In special test mode IRVNE is reset to 1 In all other modes IRVNE is reset to 0 For the MC68HC811E2 this bit is IRV and only controls the internal read visibility function 0 No internal read visibility on external bus 1 Data from internal reads is driven out the external data bus In single chip modes this bit determines whether the E clock drives out from the chip For the MC68HC811E2 this bit has no meaning or effect in single chip and bootstrap modes 0 E is driven out from the chip 1 E pin is driven low R
37. 0 0 0 0 0 0 0 0 Read Port C Latched Register PCL7 PCL6 PCL5 PCL4 PCL2 PCL1 PCLO 51005 PORTCL Write SRE page 185 Reset Indeterminate after reset 1006 Reserved R R R R R R R R ee Read Port C Data Direction R egister DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRCO 1007 DDRC Write 137 SPEI pub 70 0 0 0 0 0 0 0 Read Port D Data Register 0 0 PD5 PD4 PD3 PD2 PD1 PDO 1008 PORTD Write 138 WET U Read Port D Data Direction Register DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRDO 1009 DDRD Write 138 SHIRE 0 0 0 0 0 0 0 Read Port E Data Register PE7 PE6 PE5 PE4 PE3 PE2 PE1 0 100A PORTE Write 139 Reset Indeterminate after reset Read Timer Compare Force FOC2 FOC3 FOC4 FOC5 100B Register CFORC Write 190 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected Indeterminate after reset Figure 4 7 Register and Control Bit Assignments Sheet 2 of 8 MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 73 Operating Modes Memory Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read Output Compare 1 Mask 0 1 7 OC1M6 OC1M5 OC1M4 OCIM3 100C Register OC1M Write 191 IA 0 0 0 0 0 0 0 Read Output Compare 1 Data 0 1 7 OCID6 OCID5 06104 OCID3 100D Register OC1D Write S 192 ee page v Reset 0
38. 11 1 Contents 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 11 11 11 12 11 13 11 14 11 15 11 16 11 17 11 18 11 19 11 20 11 21 11 22 MC68HC11E Family Rev 4 Section 11 Electrical Characteristics Pig l u nte Aree 222 Maximum Ratings for Standard and Extended Voltage Devices 222 Functional Operating Range 223 Thermal Characteristics 223 DC Electrical Characteristics 224 Supply Currents and Power Dissipation 225 MC68L11E9 E20 DC Electrical Characteristics 226 MC68L11E9 E20 Supply Currents and Power Dissipation 227 Control TN C ER EROR ERR 229 MC68L11E9 E20 Control Timing 230 Peripheral Port Timing 235 MC68L11E9 E20 Peripheral Port Timing 236 Analog to Digital Converter Characteristics 240 MC68L1 1E9 E20 Analog to Digital Converter di iti RE 241 Expansion Bus Timing 242 MC68L11E9 E20 Expansion Bus Timing Characteristics 244 Serial Peripheral Interface Timing Characteristics 246 MC68L11E9 E20 Serial Peirpheral Interface Characteristics 247 EEPROM Characteristics 250 MC68L11E9 E20 EEPROM Characteristics
39. 2 500 ns 32 8 192 ms 12 0 2 3 MHz 333 ns 21 33 us 5 461 ms Pulse accumulator control bits are also located within two timer registers TMSK2 and TFLG2 as described in the following paragraphs MC68HC11E Family Rev 4 Timing System MOTOROLA Timing System Pulse Accumulator 9 8 1 Pulse Accumulator Control Register Four of this register s bits control an 8 bit pulse accumulator system Another bit enables either the OC5 function or the IC4 function while two other bits select the rate for the real time interrupt system Address 1026 Bit 7 6 5 4 3 2 1 Bit 0 Read DDRA7 PAEN PAMOD PEDGE DDRA3 14 05 RTR1 RTRO Write Reset 0 0 0 0 0 0 0 0 Figure 9 25 Pulse Accumulator Control Register PACTL DDRA7 Data Direction for Port A Bit 7 Refer to Section 6 Parallel Input Output I O Ports PAEN Pulse Accumulator System Enable Bit 0 Pulse accumulator disabled 1 Pulse accumulator enabled PAMOD Pulse Accumulator Mode Bit 0 Event counter 1 Gated time accumulation PEDGE Pulse Accumulator Edge Control Bit This bit has different meanings depending on the state of the PAMOD bit as shown in Table 9 7 Table 9 7 Pulse Accumulator Edge Control PAMOD PEDGE Action on Clock 0 0 PAI falling edge increments the counter 0 1 PAI rising edge increments the counter 1 0 A PAI inhibits counting 1 1 1 P
40. 33 Common Parallel Resonant Crystal Connections 35 External Oscillator Connections 35 Programming Model 47 rap ODSISIOUS 12v 40 u ER VOCE ERK Od aus ya REX 49 Address Data Demultiplexing 68 Memory for 6 11 0 70 Memory Map for 68 11 1 70 Memory for 68 7 11 9 71 Memory for 68 7 11 20 71 Memory for 68 811 72 Register and Control Bit Assignments 72 RAM Standby Connections 81 Highest Priority I Bit Interrupt and Miscellaneous Register HPRIO uisus deen ka kr CORRER ECCE e 83 System Configuration Register CONFIG 87 MC68HC811E2 System Configuration Register CONFIG Lus esae ck x dodo Roe ee ee E ERR CR RR C 87 RAM and I O Mapping Register 89 Technical Data MOTOROLA List of Figures 17 List of Figures Technical Data Figure 4 13 4 14 4 15 4 16 4 17 5 1 6 2 5 3 5 4 5 6 8 7 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 10 7 1 7 2 ma 7 4 75 De f f Title Page System Configuration Options Register OPTION 91 EPROM and EEPROM Programming Control Register PPROG 95 MC68HC711E20 EPROM Programming Co
41. 54 54 57 BF5A BF5D BF60 BF62 BF64 BF67 8 C FO1FF F1000 1C2820 CCA20C 72 E72D 021 16 1 2 01 1 1 0801 D2D01 1F2F20FC A62F 2 7 8 2 603 600 1FF 708 1C2B33 CCODBO 1 ED16 8 0000 16 2 2007 8F 0 9 8F 2 2 6 7 OOF A62F 1 8 700 A72F 1 1 2 808 88C0200 4 k k k x lt lt x k lt k k lt lt lt k CK lt lt k k k lt lt k X k lt amp lt lt x k lt amp lt ko x x lt Main bootloader starts here CK CK KKK CK Ck C C k x x k Ck KKK k k x CC Ck Ck x x k k x Ck x x k x x x x x x x x x x x lt RESET vec BEGIN Writing 1 to MSB Lor points to here EQU LDS RAMEND LDX 51000 BSET SPCR X 20 LDD SA20C STAA BAUD X STAB SCCR2 X LDD DELAYF STD TOC1 X Send BREAK to BSET SCCR2 X 501 BRSET PORTD X 01 BCLR SCCR2 X 01 BRCLR SCSR X 20 LDAA SCDAT X Data will be 00 if BREAK OR BNE NOTZERO JMP EEPMSTR NOTZERO EQU CMPA SFF BEQ BAUDOK Or else change to 104 13 amp BSET BAUD X 33 LDD DELAYS STD TOC1 X BAUDOK EQU LDY RAMSTR WAIT EQU LDD WTLOOP EQU BRSET XGDX DEX XGDX BNE WTLOOP BRA STAR NEWONE LDAA SCDAT X STAA 500 STAA SCDAT X I
42. 93 B673 08 INX Advance pointer 94 B674 39 RTS Return 95 AN1060 Rev 1 0 300 MOTOROLA 96 97 98 Application Note k x lt k k lt lt CK k lt lt k k lt lt k lt k k amp A amp k k k ko ko X X Program to be bootloaded to target 711 9 k k lt K k lt lt k x lt K k x lt k k x x k x lt Ck x C x k x lt k CK lt lt k x x Ck x Sk x k x lt x x ko x Pattern for DWOM off no SPI Turns off DWOM in target MCU NOTE Can t use direct addressing in target MCU because 00075 00083 00072 00071 Jumps to EPROM prog routine 00081 00083 00092 00091 99 B675 8604 BLPROG LDAA 504 100 677 71028 STAA 1028 101 102 regs are located at 1000 103 B67A T7EBFOO JMP PROGRAM 104 B67D ENDBPR EQU Symbol Table Symbol Name Value Def Line Number Cross Reference BEGIN B600 00029 BLLOOP B616 00038 00040 BLPROG B675 00099 00037 DATALP B648 00068 00079 DLYLP B620 00046 00047 DLYLP2 B637 00059 00063 DUNPRG B666 00083 00076 ENDBPR B67D 00104 00039 EPSTRT 000 00023 00055 00066 GREEN 0001 00015 00075 00081 INIT 103D 00009 00029 PORTB 0004 00011 00033 00058 00061 PORTE 000 00016 00059 PROGRAM BFOO 00022 00103 RDRF 0020 00020 00034 00053 00071 RED 0002 00014 00058 00061 00075 RESET 0080 00013 00032 00083 SCDR 002F 00021 00036 00049 00054 SCSR 002 00017
43. BFAA STAR EQU x BFAA CE1068 LDX PROGDEL Init X with programming delay BFAD 18CED000 LDY EPRMSTR Init Y with EPROM start addr 1 7E0000 JMP RAMSTR EXIT to start of RAM BFB4 Ck k KK KKK KK KKK KKK k KKK x Ck x k x lt Ck lt x x k lt lt k x x x k x x x x Block fill unused bytes with zeros BFB4 000000000000 BSZ SBFD1 000000000000 000000000000 000000000000 0000000000 k lt Ck k k Ck k CK C C k x lt k x lt lt k CI Ck CK Ck x k x lt Ck x lt x k lt lt x x lt x k x x x x lt Boot ROM revision level in ASCII ORG SBFD1 BFD1 41 FCC UAM CK Ck Ck k x C k k Ck k CK C C k x lt CK Ck Ck k Ck Ck CK Ck lt k x lt Ck CK lt x k Sk x x lt x k x x x x lt Mask set I D 50000 FOR EPROM PARTS ORG SBFD2 BFD2 0000 FDB 0000 CK lt Ck k Ck k x C k x lt k CK Ck x k x lt x CK Ck Ck k x lt Ck CK lt x k x lt x x x lt x x x x x lt 711E9 I D Can be used to determine MCU type ORG SBFD4 BFD4 71 9 FDB 571 9 Ck k K k x lt x lt k lt lt lt k x lt k CK lt x k x lt k x lt x k x lt x x lt x k x lt x x x lt k x x x KK VECTORS point to RAM for pseudo vector JUMBs BFD6 00C4 FDB S100 60 SCI BFD8 00 7 FDB 5100 57 SPI BFDA OOCA FDB 5100 54 PULSE ACCUM INPUT EDGE BFDC 00CD FDB 100 51 PULSE ACCUM OVERFLOW 0010 FDB 100 48 TIMER OVERFLOW BFEO 0003 FDB 100 45 TIMER OUTPUT COMPARE 5 BFE2 00D6 FDB 100
44. Electrical Characteristics 11 13 68111 9 20 Peripheral Port Timing 1 0 MHz 2 0 MHz Characteristic 2 Symbol Unit Min Max Min Max Frequency of operation fo 10 d 20 MHz E clock frequency E clock period 1000 500 ns Peripheral data setup time t MCU read of ports A C D and E PESE 100 100 ns Peripheral data hold time t MCU read of ports C D and E 99 90 Delay time data write tpwp 1 4 150 ns t MCU writes to port A END 250 250 S MCU writes to ports B C and D 400 275 Port C input data setup time tis 60 60 5 Port input data hold time tiH 100 100 ns Delay time E fall to STRB 1 4 150 ns DEB 400 275 ns Setup time STRA asserted to E fall 9 tAES 0 0 ns Delay time STRA asserted to port C data output valid tpcp 100 100 ns Hold time STRA negated to port C data tPcH 10 10 ns 3 state hold time tpcz 150 150 ns 1 Vpp 3 0 Vdc to 5 5 Vss 0 Vdc TA T to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 Ports and D timing is valid for active drive CWOM and DWOM bits are not set in PIOC and SPCR registers respectively 3 If this setup time is met STRB acknowledges in the next cycle If it is not met the response may be d
45. K1 0 007 0 18 T L M 0 007 0 18 MOING VIEW S Technical Data lt pig gt F TH ROTI ROTI gt DATUMS L M LASH ER SIDE MENSIONING AND 4 5M 1982 ONTROLLING DIMENSION INCH HE PACKAGE TOP MAY BE SMALLER THAN THE BY UP TO 0 012 0 300 ARE DETERMINED AT THE UTERMOST EXTREMES OF THE PLASTIC BODY D FLASH TIE BAR BURRS GATE EAD FLASH BUT INCLUDING ISMATCH BETWEEN THE TOP AND BOTTOM ACKAGE BOTTOM MENSIONS R AND U XCLUSIVE OF MOLI URRS AND INTERL NYM H DIMENSION PARTING LINE E PLASTIC BODY RUSION S SHALL NOT CAU OLERANCING PER ANS MENSION H DOES NOT INCLUDE DAMBAR RUSION OR INTRUSION THE DAMBAR SE THE H MENSION TO BE GREATER THAN 0 037 0 940 THE DAMBAR INTRUSION S 5 D N DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MENSION G1 TRUE POSITION TO BE MEASURED DATUM T SEATING PLANE MENSIONS R AND U DO NOT INCLUDE MOLD ALLOWABLE MOLD FLASH IS 0 010 0 250 LL NOT CAUSE THE O BE SMALLER THAN 0 025 0 636 INCHES MILLIMETERS MIN MAX MIN MAX 0 785 0 795 19 94 20 19 0 785 0 795 19 94 20 19 0 165 0 180 4 20 4 57 0 090 0 110 2 29 2 79 0 013 0 019 0 33 0 48 0 050 5 1 27 BSC 0 026 0 032 0
46. Reset Indeterminate after reset Read Baud Rate Register TCLR 5 2 5 1 SCPO RCKB SCR2 SCR1 SCRO 102B BAUD Write 157 aac Q 0 0 0 0 U U U I Read Serial Communications R8 T8 M WAKE 102C Control Register 1 SCCR1 Write EBENE s 0 0 0 0 0 0 Read Serial Communications TIE TCIE RIE ILIE TE RE RWU SBK 1020 Control Register 2 SCCR2 Write 154 hie LE 0 0 0 0 0 0 0 0 Read Serial Communications Status TDRE TC RDRF IDLE OR NF FE 102E Register SCSR Write ss 1 0 0 0 0 0 0 1 SCP2 adds 39 to SCI prescaler and is present only in MC68HC 7 11E 20 Unimplemented R Reserved U Unaffected Indeterminate after reset Figure 4 7 Register and Control Bit Assignments Sheet 6 of 8 MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 77 Operating Modes Memory Addr 102F 1030 1031 1032 1033 1034 1035 1036 1037 Register Name Serial Communications Data Register SCDR See page 152 Analog to Digital Control Status Register ADCTL See page 218 Analog to Digital R esults Register 1 ADR1 See page 220 Analog to Digital R esults Register 2 ADR2 See page 220 Analog to Digital R esults Register 3 See page 220 Analog to Digital R esults Register 4 ADR 4 See page 220 Block Protect Register BPROT See page 99 EPROM Programming Control Reg
47. and z conditions can be determined MC68HC11E Family Rev 4 Technical Data MOTOROLA Central Processor Unit CPU 51 Central Processor Unit CPU 3 3 6 4 Negative N The N bit is set if the result of an arithmetic logic or data manipulation operation is negative MSB 1 Otherwise the N bit is cleared A result is said to be negative if its most significant bit MSB is a 1 A quick way to test whether the contents of a memory location has the MSB set is to load it into an accumulator and then check the status of the N bit 3 3 6 5 Interrupt Mask 1 3 3 6 6 Half Carry H The interrupt request IRQ mask I bit is a global mask that disables all maskable interrupt sources While the bit is set interrupts can become pending but the operation of the CPU continues uninterrupted until the bit is cleared After any reset the bit is set by default and can only be cleared by a software instruction When an interrupt is recognized the bit is set after the registers are stacked but before the interrupt vector is fetched After the interrupt has been serviced a return from interrupt instruction is normally executed restoring the registers to the values that were present before the interrupt occurred Normally the bit is 0 after a return from interrupt is executed Although the bit can be cleared within an interrupt service routine nesting interrupts in this way should only be done when there is a clear und
48. 0 NOTE Software can change some aspects of the memory map after reset Figure 1 MC68HC711E9 Composite Memory Map 6 4 FF CHARACTER START BIT1 BIT2 BIT4 STOP Tx DATA LINE IDLES HIGH Q 7812 BAUD Rx DATA SAMPLES 90 2 T Tie 50 1 1 1 1 py 1 1 1 1 1 SEF FF CHARACTER start P BIT 0 BIT 1 Q 1200 BAUD Rx DATA SAMPLES 1 8 1 0 0 0 0 0 0 FOR 7812 BAUD 5 1 0 0 10 ka 12 9 Figure 2 Automatic Detection of Baud Rate AN1060 Rev 1 0 284 MOTOROLA Application Note Samples taken at 7 detect the failing edge of the start bit and verify it is a logic 0 Samples taken at the middle of what the receiver interprets as the first five bit times 8 detect logic 0s The sample taken at the middle of what the receiver interprets as bit 5 9 may detect either a 0 or a 1 because the receive data has a rising transition at about this time The samples for bits 6 and 7 detect 1s causing the receiver to think the received character was CO or E0 10 at 7812 baud instead of the FF which was sent at 1200 baud The stop bit sample detects a 1 as expected 11 but this detection is actually in the middle of bit 0 of the 1200 baud FF character The SCI receiver is not confused by the rest of the 1200 baud FF character because the receive data line is high 12 just as it would be for the idle con
49. 1 count 8 0 us 4 0 us 2 667 us E 8 overflow 524 29 ms 262 14 ms 174 76 ms 219 11 1 count 16 0 us 8 0 us 5 333 us E 16 overflow 1 049 s 524 29 ms 349 52 ms E 220 9 3 Timer Structure Technical Data Figure 9 2 shows the capture compare system block diagram The port pin control block includes logic for timer functions and for general purpose I O For pins PA2 1 and this block contains both the edge detection logic and the control logic that enables the selection of which edge triggers an input capture The digital level on PA 3 0 can be read at any time read PORTA register even if the pin is being used for the input capture function Pins PA 6 3 are used for either general purpose I O or as output compare pins When of these pins is being used for an output compare function it cannot be written directly as if it were a general purpose output Each of the output compare functions OC 5 2 is related to one of the port A output pins Output compare one OC1 has extra control logic allowing it optional control of any combination of the PA 7 3 pins The PA7 pin can be used as a general purpose I O pin as an input to the pulse accumulator or as an OC1 output pin MC68HC11E Family Rev 4 180 Timing System MOTOROLA Timing System Timer Structure PRESCALER DIVIDE BY TCNT HI TCNT LO TOI 9 1 4 8 OR 16 Ww MCU 16 BIT FREE RUNNING TOF E
50. 1015 1016 1017 1018 1019 101A 101B 101C 101D Register Name Timer Input Capture 3 Register Low TIC3L See page 185 Timer Output Compare 1 Register High TOC 1H See page 188 Timer Output Compare 1 Register Low TOC1L See page 188 Timer Output Compare 2 Register High TOC 2H See page 188 Timer Output Compare 2 Register Low TOC2L See page 188 Timer Output Compare 3 Register High TOC 3H See page 189 Timer Output Compare 3 Register Low TOC3L See page 189 Timer Output Compare 4 Register High TOC 4H See page 189 Timer Output Compare 4 Register Low TOC4L See page 189 Figure 4 7 Register and Control Bit Assignments Sheet 4 of 8 MC68HC11E Family Rev 4 Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Operating Modes and On Chip Memory Memory Map Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit2 Bit1 Bit 0 Indeterminate after reset Bit15 Bitl4 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit2 Bit1 Bit O 1 1 1 1 1 1 1 1 Bit15 Bit14 Bit 13 Bit 12 Bit11 Bit 10 Bit 9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit2 Bit1 Bit O 1 1 1 1 1 1 1 1 Bit15 Bitl4 Bit 13 B
51. 250 EPROM Characteristics 4 dod ode CROCO GE C RD 251 Technical Data MOTOROLA Electrical Characteristics 221 Electrical Characteristics 11 2 Introduction This section contains electrical specifications for the M68HC11 E series devices 11 3 Maximum Ratings for Standard and Extended Voltage Devices Technical Data NOTE NOTE Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it This device is not guaranteed to operate properly at the maximum ratings Refer to 11 6 DC Electrical Characteristics 11 7 Supply Currents and Power Dissipation 11 8 MC68L11E9 E20 DC Electrical Characteristics and 11 9 MC68L11E9 E20 Supply Currents and Power Dissipation for guaranteed operating conditions Rating Symbol Value Unit Supply voltage Vpp 0 3 to 7 0 V Input voltage Vin 0 3 to 7 0 V 1 225 Storage temperature 55 to 150 C 1 One pin at a time observing maximum power dissipation limits This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields however it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit For proper operation it is recommended that Vin and Vo be constrained to the range Vss lt Vn or Vpp Reliability of operation is
52. 5103 Bit7 6 5 4 3 2 1 Bit O Read 0DD EVEN ELAT BYTE ROW ERASE EELAT EPGM Write Reset 0 0 0 0 0 0 0 0 1 MC68HC711E9 only Figure 4 14 EPROM and EEPROM Programming Control Register PPROG ODD Program Odd Rows in Half of EEPROM Test Bit Refer to 4 6 EEPROM EVEN Program Even Rows in Half of EEPROM Test Bit Refer to 4 6 EEPROM ELAT EPROM OTPROM Latch Control Bit When ELAT 1 writes to EPROM cause address and data to be latched and the EPROM OTPROM cannot be read ELAT can be read any time ELAT can be written any time except when EPGM 1 then the write to ELAT is disabled 0 EPROM address and data bus configured for normal reads 1 EPROM address and data bus configured for programming For the MC68HC711E9 a EPGM enables the high voltage necessary forboth EEPROM and EPROM OTPROM programming b ELAT and EELAT are mutually exclusive and cannot both equal 1 BYTE Byte Other EEPROM Erase Mode Bit Refer to 4 6 EEPROM ROW Row All EEPROM Erase Mode Bit Refer to 4 6 EEPROM MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 95 Operating Modes Memory ERASE Erase Mode Select Bit Refer to 4 6 EEPROM EELAT EEPROM Latch Control Bit Refer to 4 6 EEPROM EPGM EPROM OTPROM EEPROM Programming Voltage Enable Bit EPGM can be read any time and can be written only when ELAT 1 for EPROM OTPROM programming or when EE
53. 63 B640 26F5 BNE DLYLP2 3 Total loop time 19 cyc 64 Vpp has been stable for 200ms 65 66 B642 18CEDO000 LDY EPSTRT X Tx pointer Y verify pointer 67 B646 8D23 BSR SEND1 Send first data to target 68 648 8 0000 DATALP CPX 0 X points at 0000 after last 69 B64B 2702 VERF Skip send if no more 70 B64D 8D1C BSR SEND1 Send another data char 71 B64F 132E20FC VERE BRCLR SCSR VERF Wait for Rx ready 72 B653 962F LDAA SCDR Get char and clr RDRF 73 B655 18A100 CMPA 0 Y Does char verify 74 B658 2705 VERFOK Skip error if OK 75 B65A 150403 BCLR PORTB RED GREEN Turn off LEDs 76 B65D 2007 BRA DUNPRG Done programming failed 77 B65F 78 B65F 1808 VERFOK INY Advance verify pointer 79 B661 26E5 BNE DATALP Continue till all done 80 B663 81 B663 140401 BSET PORTB GREEN Grn LED ON 82 B666 83 B666 150482 DUNPRG BCLR RESET RED Red OFF apply reset 84 B669 20FE BRA Done just hang 85 B66B 86 k lt lt k k C k x lt k x lt K k x lt k lt x K k x lt k x lt lt k x lt x x x x k x lt x x x x 87 Subroutine to get amp send an SCI char Also 88 advances pointer X 89 k lt lt k k lt lt k lt lt k x lt x k x lt k x x x k x lt k x lt lt k x lt x x lt x k x lt x x lt x 90 B66B A600 SEND1 LDAA 0 X Get a character 91 B66D 132E80FC TRDYLP BRCLR SCSR TDRE TRDYLP Wait for TDRE 92 B671 972F STAA SCDR Send character
54. A 6 SPGMRHR11 Serial Programmer for M68HC11 MCUs 273 Appendix B EVBU Schematic M68HC11EVBU 5 275 MC68HC11E Family Rev 4 Technical Data MOTOROLA Table of Contents 15 Table of Contents AN1060 AN1060 M68HC11 Bootstrap 277 EB184 EB184 Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR 323 EB188 EB188 Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR 327 EB296 EB296 Programming MC68HC711E9 Devices with PCbug11 the 68 11 331 Technical Data MC68HC11E Family Rev 4 16 Table of Contents MOTOROLA Technical Data M68HC11E Family Figure 2 1 E 2 3 2 8 2 6 2 7 2 8 2 9 3 1 3 2 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 10 4 11 4 12 MC68HC11E Family Rev 4 List of Figures Title Page M68HC11 E Series Block Diagram 26 Pin Assignments for 52 PLCC and 28 Pin Assignments for 64 Pin QFP 29 Pin Assignments for 52 Pin TOPP 30 Pin Assignments for 56 31 Pin Assignments for 48 DIP MC68HC811E2 32 External Reset 33 External Reset Circuit with Delay
55. CLOCK DDD1 10 11 BIT Tx SHIFT REGISTER SEE NOTE PIN BUFFER PD1 FORCE PIN DIRECTION OUT wef Pe Js IHE SCCR2 SCI CONTROL 2 SCI Rx SCI INTERRUPT INTERNAL REQUESTS REQUEST DATA BUS Note Refer to Figure B 1 EVBU Schematic Diagram for an example of connecting TxD to a PC Figure 7 1 SCI Transmitter Block Diagram MC68HC11E Family Rev 4 Technical Data MOTOROLA Serial Communications Interface SCI 147 Serial Communications Interface SCI 7 5 Receive Operation During receive operations the transmit sequence is reversed The serial shift register receives data and transfers it to a parallel receive data register SCDR as a complete word This double buffered operation allows a character to be shifted in serially while another character is already in the SCDR An advanced data recovery scheme distinguishes valid data from noise in the serial data stream The data input is selectively sampled to detect receive data and a majority voting circuit determines the value and integrity of each bit See Figure 7 2 7 6 Wakeup Feature The wakeup feature reduces SCI service overhead in multiple receiver systems Software for each receiver evaluates the first character of each message The receiver is placed in wakeup mode by writing a 1 to the RWU bit in the SCCR2 register While RWU is 1 all of the receiver related status flags RDRF IDLE OR NF and FE are inhibited cannot become set A
56. DDRC1 DDRCO Write Reset 0 0 0 0 0 0 0 0 Figure 6 6 Port C Data Direction Register DDRC DDRC 7 0 Port C Data Direction Bits In handshake output mode DDRC bits select the 3 stated output option DDCx 1 0 Input 1 Output MC68HC11E Family Rev 4 Technical Data MOTOROLA Parallel Input Output I O Ports 137 Parallel Input Output I O Ports 6 6 Port D In all modes port D bits 5 0 can be used either for general purpose I O or with the serial communications interface SCI and serial peripheral interface SPI subsystems During reset port D pins PD 5 0 are configured as high impedance inputs DDRD bits cleared Address 1008 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 PD5 PD4 PD3 PD2 PD1 PDO Write Reset EEE PD5 PD4 PD3 PD2 PD1 PDO ERS i 55 SCK MOSI MISO Tx RxD Indeterminate after reset Figure 6 7 Port D Data Register PORTD Address 1009 Bit7 6 5 4 3 2 1 Bit 0 Read DDRD5 00804 DDRD3 DDRD2 00801 DDRDO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 6 8 Port D Data Direction Register DDRD Bits 7 6 Unimplemented Always read 0 DDRD 5 0 Port D Data Direction Bits When DDRD bit 5 is 1 and MSTR 1 in SPCR PD5 SS is a general purpose output and mode fault logic is disabled 0 Input 1 Output Technical Data MC68HC11E Family Rev 4 138 Parallel Input Output I O Ports M
57. In normal modes PR 1 0 can be written only once and the write must be within 64 cycles after reset Refer to Table 9 1 and Table 9 4 for specific timing values Table 9 4 Timer Prescale PR 1 0 Prescaler 00 1 0 1 4 10 8 11 16 NOTE Bits TMSK2 correspond bit for bit with flag bits TFLG2 Bits TMSk2 enable the corresponding interrupt sources MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 197 Timing System 9 5 10 Timer Interrupt Flag Register 2 Bits in this register indicate when certain timer system events have occurred Coupled with the four high order bits of TMSK2 the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven system Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position Address 1025 Bit 7 6 5 4 3 2 1 Bit 0 Read TOF RTIF PAIF Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 20 Timer Interrupt Flag 2 Register TFLG2 Clear flags by writing a 1 to the corresponding bit position s TOF Timer Overflow Interrupt Flag Set when TCNT changes from FFFF to 0000 RTIF Real Time Periodic Interrupt Flag Refer to 9 6 Real Time Interrupt RTI PAOVF Pulse Accumulator Overflow Interrupt Flag Refer to 9 8 Pulse Accumulator PAIF Pulse Accumulator Input Edge Interrupt Flag Refer to 9 8 Pulse Accumulator Bi
58. Indeterminate after reset Figure 8 5 Serial Peripheral Data I O Register SPDR SPI is double buffered in and single buffered out Technical Data MC68HC11E Family Rev 4 176 Serial Peripheral Interface SPI MOTOROLA Technical Data M68HC11E Family 9 1 Contents 9 2 9 3 9 4 9 4 1 9 4 2 9 4 3 9 5 9 5 1 9 5 2 9 5 3 9 5 4 9 5 5 9 5 6 9 5 7 9 5 8 9 5 9 9 5 10 9 6 9 6 1 9 6 2 9 6 3 a7 9 8 9 8 1 9 8 2 9 8 3 MC68HC11E Family Rev 4 Section 9 Timing System iA ecient ae entaeen aed 178 Timer SRW ECT 180 Input UN on ceo ITE 182 Tuner Control Register2 183 Timer Input Capture Registers 184 Timer Input Capture 4 Output Compare 5 Register 186 Qutp t Ail eH dira tr RR Pda Re RR e 186 Timer Output Compare Registers 187 Timer Compare Force Register 190 Output Compare Mask 191 Output Compare Data Register 192 Timer Counter Register 193 Timer Control Register 1 _ 194 Timer Interrupt Mask 1 195 Timer Interrupt Flag 1 Register 196 Timer Interrupt Mask 2 196 Timer Interrupt Flag Register 2 198 Real Time Interrupt
59. PACTL DDRA7 Data Direction for Port A Bit 7 Refer to Section 6 Parallel Input Output Ports PAEN Pulse Accumulator System Enable Bit Refer to 9 8 Pulse Accumulator PAMOD Pulse Accumulator Mode Bit Refer to 9 8 Pulse Accumulator PEDGE Pulse Accumulator Edge Control Bit Refer to 9 8 Pulse Accumulator DDRA3 Data Direction for Port A Bit Refer to Section 6 Parallel Input Output I O Ports 14 05 Input Capture 4 Output Compare Bit Refer to 9 8 Pulse Accumulator RTR 1 0 RTI Interrupt Rate Select Bits These two bits determine the rate at which the RTI system requests interrupts The RTI system is driven by an E divided by 21 rate clock that is compensated so it is independent of the timer prescaler These two control bits select an additional division factor Refer to Table 9 5 Technical Data MC68HC11E Family Rev 4 202 Timing System MOTOROLA Timing System Computer Operating Properly COP Watchdog Function 9 7 Computer Operating Properly COP Watchdog Function The clocking chain for the COP function tapped off of the main timer divider chain is only superficially related to the main timer system The CR 1 0 bits in the OPTION register and the NOCOP bit in the CONFIG register determine the status of the COP function One additional register COPRST is used to arm and clear the COP watchdog reset system Refer to Section 5 Resets and Interrupts for a more detailed
60. Port Data Register 6 5 Port C In single chip and bootstrap modes port C pins resetto high impedance inputs DDRC bits are set to 0 In expanded and special test modes port C pins are multiplexed address data bus and the port C register address is treated as an external memory location Address 1003 Bit 7 6 5 4 3 2 1 Bit 0 Single chip or bootstrap modes Read PC7 PC6 5 4 PC3 PC2 PC1 PCO Write Reset Indeterminate after reset Expanded or special test modes Read ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDRO Write DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 1 DATAO Reset Indeterminate after reset Figure 6 4 Port C Data Register PORTC Technical Data MC68HC11E Family Rev 4 136 Parallel Input Output I O Ports MOTOROLA Parallel Input Output I O Ports Port C Address 1005 Bit 7 6 5 4 3 2 1 Bit 0 Read PCL7 PCL6 PCL5 PCL4 PCL3 PCL2 PCL1 PCLO Write Reset Indeterminate after reset Figure 6 5 Port C Latched Register PORTCL PORTCL is used in the handshake clearing mechanism When an active edge occurs on the STRA pin port C data is latched into the PORTCL register Reads of this register return the last value latched into PORTCL and clear STAF flag following a read of PIOC with STAF set Address 1007 Bit 7 6 5 4 3 2 1 Bit 0 Read DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2
61. Read Bit 6 Bit 5 Bit4 Bit 3 Bit2 Bit 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 15 Timer Counter Register TCNT MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 193 Timing System 9 5 6 Timer Control Register 1 The bits of this register specify the action taken as a result of a successful OCx compare Address 1020 Bit 7 6 5 4 3 2 1 Bit 0 Read OM2 OL2 0 3 013 0 4 014 0 5 015 Write Reset 0 0 0 0 0 0 0 0 Figure 9 16 Timer Control Register 1 TCTL1 OM 2 5 Output Mode Bits OL 2 5 Output Level Bits These control bit pairs are encoded to specify the action taken after a successful OCx compare OC5 functions only if the 14 O5 bit in the PACTL register is clear Refer to Table 9 3 for the coding Table 9 3 Timer Output Compare Actions OMx OLx Action Taken on Successful Compare 0 0 Timer disconnected from output pin logic 0 1 Toggle OCx output line 1 0 Clear OCx output line to 0 1 1 Set OCx output line to 1 Technical Data MC68HC11E Family Rev 4 194 Timing System MOTOROLA Timing System Output Compare 9 5 7 Timer Interrupt Mask 1 Register Use this 8 bit register to enable or inhibit the timer input capture and output compare interrupts Address 1022 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 21
62. SPI device and the communicating slave device In some cases the phase and polarity are changed between transfers to allow a master device to communicate with peripheral slaves having different requirements When CPHA equals 0 the SS line must be negated and reasserted between each successive serial byte Also if the slave writes data to the SPI data register SPDR while SS is low a write collision error results When CPHA equals 1 the SS line can remain low between successive transfers 8 6 SPI Signals This subsection contains descriptions of the four SPI signals Master in slave out MISO Master out slave in MOSI Serial clock SCK Slave select SS Any SPI output line must have its corresponding data direction bit in DDRD register set If the DDR bit is clear that line is disconnected from the SPI logic and becomes a general purpose input SPI input lines are forced to act as inputs regardless of the state of the corresponding DDR bits in DDRD register MC68HC11E Family Rev 4 Technical Data MOTOROLA Serial Peripheral Interface SPI 169 Serial Peripheral Interface SPI 8 6 1 Master In Slave Out MISO is one of two unidirectional serial data signals It is an input to a master device and an output from a slave device The MISO line of a slave device is placed in the high impedance state if the slave device is not selected 8 6 2 Master Out Slave In 8 6 3 Serial Clock 8 6 4 Slave Select Techn
63. SUBB opr Subtract B M B A IMM CO jii 2 A A A A Memory from A DIR DO dd 3 B A EXT FO hh Il 4 A IND X EO 4 A IND Y 18 EO 5 SUBD Subtract D M M 12D IMM 83 kk 4 A A A A Memory from DIR 93 dd 5 D EXT B3 hh Il 6 IND X A3 6 IND Y 18 A3 7 SWI Software See Figure 3 2 INH 3F 14 1 Interrupt TAB Transfer A to B 16 2 A A 0 TAP Transfer A to CCR INH 06 2 A Register Transfer B to A B gt A INH 17 2 A A 0 Technical Data MC68HC11E Family Rev 4 62 Central Processor Unit CPU MOTOROLA Central Processor Unit CPU Instruction Set Table 3 2 Instruction Set Sheet 7 of 7 Mnemonic Operation Description Addressing Instruction Condition Codes Mode Opcode Operand Cycles S X H 2 5 TEST Address Bus Counts INH 00 5 Test Modes TPA Transfer CC gt 07 2 Register to TST opr Test for Zero or M 0 EXT 7D 6 E SEL VA 0 0 Minus IND X 6D 6 IND Y 18 6D 7 TSTA Test A for Zero 0 4D 2 0 0 or Minus TSTB Test B for Zero B 0 B INH 5D 2 0 0 Minus TSX Transfer Stack 1 X INH 30 3 Pointer to X TSY Transfer Stack 1
64. The EEPROM programming voltage power supply voltage to the EEPROM array is not enabled until there has been a write to PPROG with EELAT set and PGM cleared This must be followed by a write to valid EEPROM location or to the CONFIG address and then a write to PPROG with both the EELAT EPGM bits set Any attempt to set both EELAT and EPGM during the same write operation results in neither bit being set 4 6 1 1 Block Protect Register This register prevents inadvertent writes to both the CONFIG register and EEPROM The active bits in this register are initialized to 1 out of reset and can be cleared only during the first 64 E clock cycles after reset in the normal modes When these bits are cleared the associated EEPROM section and the CONFIG register can be programmed or erased EEPROM is only visible if the EEON bit in the CONFIG register is set The bits in the BPROT register can be written to 1 at any time to protect EEPROM and the CONFIG register In test or bootstrap modes write protection is inhibited and BPROT can be written repeatedly Address ranges for protected areas of EEPROM differ significantly for the MC68HC81 1E2 Refer to Figure 4 16 Address 1035 Bit 7 6 5 4 3 2 1 Read PTCON BPRT3 BPRT2 BPRT1 BPRTO Write Reset 0 0 0 1 1 1 1 1 Unimplemented Figure 4 16 Block Protect Register BPROT Bits 7 5 Unimplemented Always read 0 MC68HC11E Family
65. User array is disabled and extra columns are accessed at bits 7 0 Addresses use bits 13 5 and bits 4 0 are don t care EXCOL can be read and written only in special modes and always returns 0 in normal modes EXROW Select Extra Rows Bit 0 User array selected 1 User array is disabled and two extra rows are available Addresses use bits 7 0 and bits 13 8 are don t care EXROW can be read and written only in special modes and always returns 0 in normal modes T 1 0 EPROM Test Mode Select Bits These bits allow selection of either gate stress or drain stress test modes They can be read and written only in special modes and always read 0 in normal modes T1 TO Function Selected 0 0 Normal mode 0 1 Reserved 1 0 Gate stress 1 1 Drain stress MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 97 Operating Modes Memory 4 6 EEPROM PGM EPROM Programming Voltage Enable Bit PGM can be read any time and can be written only when ELAT 1 0 Programming voltage to EPROM array disconnected 1 Programming voltage to EPROM array connected Some E series devices contain 512 bytes of on chip EEPROM MC68HC811E2 contains 2048 bytes of EEPROM with selectable base address All E series devices contain the EEPROM based CONFIG register 4 6 1 EEPROM and CONFIG Programming and Erasure Technical Data The erased sta
66. clocks and reduces power consumption to an absolute minimum while retaining the contents of the entire RAM array MC68HC11E Family Rev 4 Technical Data MOTOROLA Resets and Interrupts 129 Resets and Interrupts 5 7 1 Wait Mode 5 7 2 Stop Mode Technical Data The WAI opcode places the MCU in wait mode during which the CPU registers are stacked and CPU processing is suspended until a qualified interrupt is detected The interrupt can be an external IRQ an or any of the internally generated interrupts such as the timer or serial interrupts The on chip crystal oscillator remains active throughout the wait standby period The reduction of power in the wait condition depends on how many internal clock signals driving on chip peripheral functions can be shut down The CPU is always shut down during wait While in the wait state the address data bus repeatedly runs read cycles to the address where the CCR contents were stacked The MCU leaves the wait state when it senses any interrupt that has not been masked The free running timer system is shut down only if the l bit is setto 1 and the COP system is disabled by NOCOP being set to 1 Several other systems also can be in a reduced power consumption state depending on the state of software controlled configuration control bits Power consumption by the analog to digital A D converter is not affected significantly by the wait condition However the A D converter c
67. dc 111 System Configuration Options Register 112 Configuration Control Register 113 Effects of oll success sss aa aa was 114 Central Processor Unit CPU 115 Memory c E 115 lu PPP 115 Real Time Interrupt PIED 116 Pulse 116 Computer Operating Properly COP 116 Serial Communications Interface 5 116 Serial Peripheral Interface 117 Analog to Digital A D TIT ee Rc RR CIERRE d RR PX Vd RR ET 117 Reset and Interrupt Priorily 117 Highest Priority Interrupt and Miscellaneous Register 119 EI a Qr ACER REI CE DPI Rene dod th e SUM aa 121 Interrupt Recognition and Register Stacking 122 Non Maskable Interrupt Request 123 Illegal Opcode Trap 123 Software Interrupt SWI 124 Maskable Interrupts 124 Reset and Interrupt Processing 124 Technical Data MOTOROLA Resets and Interrupts 107 Resets and Interrupts 5 2 Introduction 5 3 Resets Technical Data 5 7 Low Power 129 5 7 1 ilc doo Pr TD pU 130 5 7 2 SID 4 64 5
68. discussion of the COP function 9 8 Pulse Accumulator The M68HC11 Family of MCUs has an 8 bit counter that can be configured to operate either as a simple event counter or for gated time accumulation depending on the state of the PAMOD bit in the PACTL register Refer to the pulse accumulator block diagram Figure 9 24 In the event counting mode the 8 bit counter is clocked to increasing values by an external pin The maximum clocking rate for the external event counting mode is the E clock divided by two In gated time accumulation mode a free running E clock divide by 64 signal drives the 8 bit counter but only while the external PAI pin is activated Refer to Table 9 6 The pulse accumulator counter can be read or written at any time MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 203 Timing System PAOVI INTERRUPT REQUESTS 64 CLOCK FROM MAIN TIMER 5 amp TFLG2 INTERRUPT STATUS PAI EDGE x DISABLE EREN FLAG SETTING NL PACNT 8 COUNTER MCU PIN PAT INPUT BUFFER E 2 PAI AND MUX 0 1 EDGE DETECTOR DATA ENABLE BUS OUTPUT BUFFER EE FROM MAIN TIMER 2 oci n ajaja FROM DDRA7 1 CONTROL INTERNAL DATA BUS Figure 9 24 Pulse Accumulator Table 9 6 Pulse Accumulator Timing Technical Data Cycle Time 64 4 0 MHz 1 MHz 1000 ns 64 us 16 384 ms 8 0 MHz 2
69. 0C3l 0 41 141051 IC2I Write Reset 0 0 0 0 0 0 0 0 Figure 9 17 Timer Interrupt Mask 1 Register TMSK1 OC1I OC4I Output Compare x Interrupt Enable Bits If the OCxl enable bit is set when the OCxF flag bit is set a hardware interrupt sequence is requested 14 051 Input Capture 4 Output Compare 5 Interrupt Enable Bit When 14 05 PACTL is 1 14 051 is the input capture 4 interrupt enable bit When 14 05 is 0 14 051 is the output compare 5 interrupt enable bit Input Capture x Interrupt Enable Bits If the enable bit is set when the ICxF flag bit is set a hardware interrupt sequence is requested NOTE Bits in TMSK1 correspond bit for bit with flag bits in TFLG1 Bits in TMSK1 enable the corresponding interrupt sources MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 195 Timing System 9 5 8 Timer Interrupt Flag 1 Register Bits in this register indicate when timer system events have occurred Coupled with the bits of TMSK1 the bits of TFLG1 allow the timer subsystem to operate in either a polled or interrupt driven system Each bit of TFLG1 corresponds to a bit in TMSK1 in the same position Address 1023 Bit 7 6 5 4 3 2 1 Bit 0 Read OCIF OC2F OC3F OC4F 14 05F IC1F IC2F IC3F Write Reset 0 0 0 0 0 0 0 0 Figure 9 18 Timer Interrupt Flag 1 Register TFLG1 Clear flags by writing a 1 to the corre
70. 2 0 A A A Right A 0 COM b7 bo C Technical Data MC68HC11E Family Rev 4 60 Central Processor Unit CPU MOTOROLA Central Processor Unit CPU Instruction Set Table 3 2 Instruction Set Sheet 5 of 7 Operation Description Addressing Instruction Condition Codes Mode Opcode Operand Cycles S x H 2 LSRB Logical Shift B INH 54 2 0 A A A Right B zo 0 b7 b0 C LSRD Logical Shift INH 04 3 Right Double eas b A 00 7 B 00 C MUL Multiply 8 by 8 A B gt D INH 3D 10 NEG opr Two s 0 70 6 Complement IND X 60 f 6 Memory Byte IND Y 18 60 ff 7 NEGA Two s 0 40 2 Complement A NEGB Two s 0 B gt B B INH 50 2 B NOP No operation No Operation INH 01 2 OR A M A A IMM 8A lii 2 A 0 Accumulator A DIR 9A dd 3 A Inclusive A EXT BA hh Il 4 A IND X AA 4 IND Y 18 AA 5 ORAB opr OR B M gt B B IMM ii 2 0 Accumulator B DIR DA 4 3 B Inclusive B EXT FA hh Il 4 B IND X EA 4 B IND Y 18 EA 5 PSHA Push A onto gt SIKSP 1 A INH 36 3 Stack PSHB Push B onto Stk SP 1 B INH 37 3 Stack PSHX Push X o
71. 4 0 MHz MC68HC11E Family Rev 4 110 Resets and Interrupts MOTOROLA Resets Interrupts Resets Address 103 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Figure 5 1 Arm Reset COP Timer Circuitry Register COPRST Complete this 2 step reset sequence to service the COP timer 1 Write 55 to COPRST to arm the COP timer clearing mechanism 2 Write AA to COPRST to clear the COP timer Performing instructions between these two steps is possible as long as both steps are completed in the correct sequence before the timer times out 5 3 4 Clock Monitor Reset The clock monitor circuit is based on an internal resistor capacitor RC time delay If no MCU clock edges are detected within this RC time delay the clock monitor can optionally generate a system reset The clock monitor function is enabled or disabled by the CME control bit in the OPTION register The presence of a timeout is determined by the RC delay which allows the clock monitor to operate without any MCU clocks Clock monitor is used as a backup for the COP system Because the COP needs a clock to function it is disabled when the clock stops Therefore the clock monitor system can detect clock failures not detected by the COP system Semiconductor wafer processing causes variations of the RC timeout values between individual devices An E cl
72. 4 1 Central Processor Unit CPU 5 4 2 Memory Map 5 4 3 Timer After reset the central processor unit CPU fetches the restart vector from the appropriate address during the first three cycles and begins executing instructions The stack pointer and other CPU registers are indeterminate immediately after reset however the X and l interrupt mask bits in the condition code register CCR are set to mask any interrupt requests Also the S bit in the CCR is set to inhibit stop mode After reset the INIT register is initialized to 01 mapping the RAM at 00 and the control registers at 1000 For the MC68HC811E2 the CONFIG register resets to FF EEPROM mapping bits EE 3 0 place the EEPROM at F800 Refer to the memory map diagram for MC68HC811E2 in Section 4 Operating Modes and On Chip Memory During reset the timer system is initialized to a count of 0000 The prescaler bits are cleared and all output compare registers are initialized to FFFF All inout capture registers are indeterminate after reset The output compare 1 mask OC 1M register is cleared so that successful OC1 compares do not affect any pins The other four output compares are configured so that they do not affect any pins on successful compares All input capture edge detector circuits are configured for capture disabled operation The timer overflow interrupt flag and all eight timer function interrupt flags are cleared All nine timer interrupts
73. 48 3 3 5 Program Counter PG uu ac de aaa wisa saa qa k 50 3 3 6 Condition Code Register CCR 51 3 3 6 1 Cay SOM G 4553 ad 6d lobe ead ee 51 3 3 6 2 WOOW V P ere 51 3 3 6 3 ZO DE Loss ada e e 51 3 3 6 4 Negative Niri ba EROGO OE OR EGER 52 3 3 6 5 Intemupt Mask DIE ara cde dei 4o qo Ee oo apr eR oa 52 3 3 6 6 52 3 3 6 7 X nterr pt Mask X oie s s aa aa aces dora wawa 52 3 3 6 8 STOP Disable S Lusso addc dedos ob e Sarl e eR 53 24 Data PES Chaaeaa od ac DIE eR odd ea CREE OR CAR 53 35 Opcodes and Operands 53 3 6 Addressing Modes 54 3 6 1 54 3 6 2 55 3 6 3 MDC 3 6 4 rr Per eee 55 3 6 5 a 30 bh ee wamak ed 55 3 6 6 lh 1 e 56 er Jus od a dh dd 56 MC68HC11E Family Rev 4 8 Table of Contents MOTOROLA Table of Contents Section 4 Operating Modes and On Chip Memory d a a eee eee 65 n ka 66 43 Operating 66 4 3 1 SAS ModE ok ok was ea std a ee 66 4 3 2 ExpandedMode 67 4 3 3 TES MD Q s a suska us 67 4 3 4 Boden ModE
74. 66 0 81 0 020 0 51 0 025 0 64 0 750 0 756 19 05 19 20 0 750 0 756 19 05 19 20 0 042 0 048 1 07 1 21 0 042 0 048 1 07 1 21 0 042 0 056 1 07 1 42 0 020 0 50 29 109 0 9 109 0 710 0 730 18 04 18 54 lt gt lt gt 0 040 1 02 MC68HC11E Family Rev 4 254 Mechanical Data MOTOROLA Mechanical Data 52 Pin Windowed Ceramic Leaded Chip Carrier Case 778B 12 4 52 Pin Windowed Ceramic Leaded Chip Carrier Case 778B A 0 51 0 020 T AO B B Y 051 0020 9 T A O BO i i y A 10000000000 fa 0 15 0 006 SEATING J PLANE H D 52 PL s 0180007 MC68HC11E Family Rev 4 NOTES 1 2 3 4 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 CONTROLLING DIMENSION INCH DIMENSION R AND N DO NOT INCLUDE GLASS PROTRUSION GLASS PROTRUSION TO BE 0 25 0 010 MAXIMUM ALL DIMENSIONS AND TOLERANCES INCLUDE
75. 7 1 Baud Rate Values Crystal Frequency MHz Pr scale pu 4 00 4 9152 8 00 10 00 12 00 16 00 Prescaler Selects Divide Divide Bus Frequency MHz SCP2 SCP1 SCPO SCR2 SCR1 SCRO 1 00 1 23 2 00 2 50 3 00 4 00 0 0 0 0 0 0 1 1 62500 76800 125000 156250 187500 250000 0 0 0 0 0 1 1 2 31250 38400 62500 78125 93750 125000 0 0 0 0 1 0 1 4 15625 19200 31250 39063 46875 62500 0 0 0 0 1 1 1 8 7813 9600 15625 19531 23438 31250 0 0 0 1 0 0 1 16 3906 4800 7813 9766 11719 15625 0 0 0 1 0 1 1 32 1953 2400 3906 4883 5859 7813 0 0 0 1 1 0 1 64 977 1200 1953 2441 2930 3906 0 0 0 1 1 1 1 128 488 600 977 1221 1465 1953 0 0 1 0 0 0 3 1 20833 25600 41667 52083 62500 83333 0 0 1 0 0 1 3 2 10417 12800 20833 26042 31250 41667 0 0 1 0 1 0 3 4 5208 6400 10417 13021 15625 20833 0 0 1 0 1 1 3 8 2604 3200 5208 6510 7813 10417 0 0 1 1 0 0 3 16 1302 1600 2604 3255 3906 5208 0 0 1 1 0 1 3 32 651 800 1302 1628 1953 2604 0 0 1 1 1 0 3 64 326 400 651 814 977 1302 0 0 1 1 1 1 3 128 163 200 326 407 488 651 0 1 0 0 0 0 4 1 15625 19200 31250 39063 46875 62500 0 1 0 0 0 1 4 2 7813 9600 15625 19531 23438 31250 0 1 0 0 1 0 4 4 3906 4800 7813 9766 11719 15625 0 1 0 0 1 1 4 8 1953 2400 3906 4883 5859 7813 0 1 0 1 0 0 4 16 977 1200 1953 2441 2930 3906 0 1 0 1 0 1 4 32
76. EEPROM security functions AN1060 Rev 1 0 282 MOTOROLA Application Note Automatic Selection of Baud Rate NOTE AN1060 Rev 1 0 The bootloader program in the MC68HC711E9 accommodates either of two baud rates The higher of these baud rates 7812 baud at a 2 MHz E clock rate is used in systems that operate from a binary frequency crystal such as 2 Hz 8 389 MHz At this crystal frequency the baud rate is 8192 baud which was used extensively in automotive applications The second baud rate available to the M68HC11 bootloader is 1200 baud at a 2 MHz E clock rate Some of the newest versions of the M68HC1 1 including the MC68HC11F1 and MC68HC117K4 accommodate other baud rates using the same differentiation technique explained here Refer to the reference numbers in square brackets in Figure 2 during the following explanation Software can change some aspects of the memory map after reset Figure 2 shows how the bootloader program differentiates between the default baud rate 7812 baud at a 2 MHz E clock rate and the alternate baud rate 1200 baud at a 2 MHz E clock rate The host computer sends an initial FF character which is used by the bootloader to determine the baud rate that will be used for the downloading operation The top half of Figure 2 shows normal reception of FF Receive data samples at 1 detect the falling edge of the start bit and then verify the start bit by taking a sample at
77. Figure 5 7 Any one of these interrupts can be assigned the highest maskable interrupt priority by writing the appropriate value to the PSEL bits in the HPRIO register Otherwise the priority arrangement remains the same An interrupt that is assigned highest priority is still subject to global MC68HC11E Family Rev 4 118 Resets and Interrupts MOTOROLA Resets and Interrupts Reset and Interrupt Priority masking by the l bit in the CCR or by any associated local bits Interrupt vectors are not affected by priority assignment To avoid race conditions HPRIO can be written only while l bit interrupts are inhibited 5 5 1 Highest Priority Interrupt and Miscellaneous Register Address 5103 Bit7 6 5 4 3 2 1 Bit 0 Read RBOOT 00 IRVNE PSEL2 PSEL2 PSEL1 PSELO Write Reset Single chip 0 0 0 0 0 1 1 0 Expanded 0 0 1 0 0 1 1 0 Bootstrap 1 1 0 0 0 1 1 0 Special test 0 1 1 1 0 1 1 0 1 values of the SMOD MDA reset bits depend the mode selected at the RESET pin rising edge Refer to Table 4 1 Hardware Mode Select Summary Figure 5 4 Highest Priority I Bit Interrupt and Miscellaneous Register HPRIO RBOOT Read Bootstrap ROM Bit Has meaning only when the SMOD bit is a 1 bootstrap mode or special test mode At all other times this bit is clear and cannot be written Referto Section 4 Operating Modes and On Chip Memory
78. Hardware Mode Select Summary Input Levels Control Bits in HPRIO at Reset Mode Latched at Reset MODB MODA RBOOT SMOD MDA 1 0 Single chip 0 0 0 1 1 Expanded 0 0 1 0 0 Bootstrap 1 1 0 0 1 Special test 0 1 1 A normal mode is selected when MODB is logic 1 during reset One of three reset vectors is fetched from address FFFA FFFF and program execution begins from the address indicated by this vector If MODB is logic O during reset the special mode reset vector is fetched from addresses BFFA BFFF and software has access to special test features Refer to Section 5 Resets and Interrupts MC68HC11E Family Rev 4 82 Operating Modes and On Chip Memory MOTOROLA Address Read Write Resets Single chip Expanded Bootstrap Test Operating Modes and On Chip Memory Memory Map 103C Bit 7 6 5 4 3 2 1 Bit 0 RBOOT 5 IRV INE PSEL3 PSEL2 PSEL1 PSELO 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 1 0 0 0 1 1 0 0 1 1 1 0 1 1 0 1 The reset values depend on the mode selected at the RESET pin rising edge Figure 4 9 Highest Priority I Bit Interrupt and Miscellaneous Register HPRIO RBOOT Read Bootstrap ROM Bit Valid only when SMOD is set bootstrap or special test mode can be written only in special modes 0 Bootloader ROM disabled and not in map 1 Bootloader ROM enabled and map at BEOO BFFF
79. INTERRUPT FFF0 FFF1 YES FETCH VECTOR FFEE FFEF gt YES FETCH VECTOR FFEC FFED gt YES FETCH VECTOR FFEA FFEB 5 FETCH VECTOR FFE8 FFE9 gt Figure 5 6 Interrupt Priority Resolution Sheet 1 of 2 MC68HC11E Family Rev 4 Technical Data MOTOROLA Resets and Interrupts 127 Resets and Interrupts VECTOR SFFE6 FFE7 VECTOR FFE4 FFE5 FETCH VECTOR FFE2 FFE3 gt FETCH VECTOR SFFEO FFE1 7 FETCH VECTOR FFDE FFDF di FETCH VECTOR FFDC FFDD FETCH VECTOR FFDA FFDB FETCH VECTOR SPIF 1 OR 21 FFD8 FFD9 FETCH VECTOR INTERRUPT SEE FIGURE di FFD6 FFD7 7 FETCH VECTOR S FFF2SFFF END Figure 5 6 Interrupt Priority Resolution Sheet 2 of 2 Technical Data MC68HC11E Family Rev 4 128 Resets and Interrupts MOTOROLA Resets and Interrupts Low Power Operation FLAG Y RDRF 1 NO VALID SCI REQUEST VALID 5 REQUEST Figure 5 7 Interrupt Source Resolution Within SCI 5 7 Low Power Operation Both stop mode and wait mode suspend CPU operation until a reset or interrupt occurs Wait mode suspends processing and reduces power consumption to an intermediate level Stop mode turns off all on chip
80. M DIR 15 dd mm 6 0 msk IND X 1D ff mm 7 IND Y 18 1D mm 8 MC68HC11E Family Rev 4 Technical Data MOTOROLA Central Processor Unit CPU 57 Central Processor Unit CPU Table 3 2 Instruction Set Sheet 2 of 7 Mnemonic Operation Description Addressing Instruction Condition Codes Mode Opcode Operand Cycles x H 2 BCS rel Branch if Carry 1 REL 25 3 Set BEQ rel Branch if Zero Z 1 REL 27 3 BGE rel Branch if A Zero 2 0 REL 2C 3 BGT rel Branch if gt Zero 7 0 REL 2E 3 BHI rel Branch if C Z 0 REL 22 3 Higher BHS rel Branch if C 0 REL 24 3 Higher or Same BITA opr Bit s Test A A M A IMM 85 2 with Memory A DIR 95 dd 3 A EXT B5 hh Il 4 A IND X A5 ff 4 A IND Y 18 A5 ff 5 BITB opr Bit s Test B B M B IMM C5 ji 2 0 with Memory B DIR D5 dd 3 B EXT F5 jhh Il 4 B IND X E5 ff 4 B IND Y 18 ff 5 BLE rel BranchifAZero 2 1 REL 2F 3 BLO rel Branch if Lower 1 REL 25 3 BLS rel Branch if Lower 2 C Z 1 REL 23 3 or Same BLT rel Branch if lt Zero IN V 1 REL 2D 3 BMI rel Branch if Minus 2 1 REL 2B 3 BNE re
81. MHz Characteristic 2 Symbol Unit Min Max Min Max Frequency of operation 1 0 2 0 MHz E clock period 1000 500 ns Crystal frequency fy TAL 4 0 8 0 MHz External oscillator frequency 4 4 0 8 0 MHz Processor control setup time tpogu 1 4 tuyo 75 ns I dis Reset input pulse width To guarantee external reset vector PWRnsTL 8 8 Minimum input time be pre empted by internal reset 1 1 Mode programming setup time 2 2 Mode programming hold time 10 10 ns Interrupt pulse width IRQ edge sensitive mode PWira teye 20 ns 1020 520 ns Wait recovery startup time twrs 4 4 pulse width input capture pulse accumulator input PWrm 1020 520 i PWrim 20 ns 1 Vpp 3 0 Vdc to 5 5 Vss 0 TA T to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 RESET is recognized during the first clock cycle it is held low Internal circuitry then drives the pin low for four clock cycles releases the pin and samples the pin level two cycles later to determine the source of the interrupt Refer to Section 5 Resets and Interrupts for further detail pA 2011 N 2 0 2 paz 3 N Notes 1 Rising edge sensitive input
82. PD 4 1 100 1 Vpp 5 0 10 Vss 0 Vdc TA T to Ty unless otherwise noted 2 specification for RESET and MODA is not applicable because they open drain pins specification not applicable to ports C and D in wired OR mode 3 Refer to 11 14 Analog to Digital Converter Characteristics and 11 15 MC68L11E9 E20 Analog to Digital Converter Characteristics for leakage current for port E Technical Data MC68HC11E Family Rev 4 224 Electrical Characteristics MOTOROLA 11 7 Supply Currents and Power Dissipation Electrical Characteristics Supply Currents and Power Dissipation Characteristics Symbol Min Max Unit Run maximum total supply current Single chip mode 2MHz 15 3 MHz 27 Expanded multiplexed mode 2 MHz 27 3 MHz 35 Wait maximum total supply current 2 all peripheral functions shut down 6 Single chip mode 2 2 Wipp 15 mA 3 MHz __ 10 Expanded multiplexed mode 2 MHz 20 3 MHz Stop maximum total supply current Single chip mode no clocks 40 to 85 C Sipp 25 uA gt 85 C to 105 C 50 gt 105 to 125 E 100 Maximum power dissipation Single chip mode 2 MHz 85 3 MHz Pp 150 mW Expanded multiplexed mode 2MHz 150 3 MHz 195 1 Vpp 5 0 10 Vas 0 Vdc TA T to Ty unless otherwise noted 2 EXTAL is driven with a square wave and 500 ns
83. Serial Communications Interface SCI SCI Registers FE Framing Error Flag FE is set when a 0 is detected where a stop bit was expected Clear the FE flag by reading SCSR with FE set and then reading SCDR 0 Stop bit detected 1 Zero detected Bit 0 Unimplemented Always reads 0 7 8 5 Baud Rate Register Use this register to select different baud rates for the SCI system The SCP 1 0 SCP 2 0 in MC68HC 7 11E20 bits function as a prescaler for the SCR 2 0 bits Together these five bits provide multiple baud rate combinations for a given crystal frequency Normally this register is written once during initialization The prescaler is set to its fastest rate by default out of reset and can be changed at any time Refer to Table 7 1 for normal baud rate selections Address 1028 Bit 7 6 5 4 3 2 1 Bit 0 Read TCLR SCP2 SCP1 5 0 RCKB SCR2 SCR1 SCRO Write Reset 0 0 0 0 0 U U U U Unaffected Figure 7 7 Baud Rate Register BAUD TCLR Clear Baud Rate Counter Bit Test SCP 2 0 SCI Baud Rate Prescaler Select Bits NOTE SCP2 applies to MC68HC 7 11E20 only When SCP2 1 SCP 1 0 must equal 05 Any other values for SCP 1 0 are not decoded in the prescaler and the results are unpredictable Refer to Figure 7 8 and Figure 7 9 MC68HC11E Family Rev 4 Technical Data MOTOROLA Serial Communications Interface SCI 157 Serial Communications Interface 1 Table
84. UU UU UU CO CO CO CJ UJ CO CG CPNWRUO ADDR10 ADDR9 ADDR8 HC373 PCT DI 01 ADDR7 PC6 D2 02 ADDR6 5 03 ADDR5 PC4 D4 04 ADDR4 PC3 05 05 ADDR3 PC2 06 06 ADDR2 PC1 D 07 ADDR1 0 08 98 ADDRO AS LE Y MCU DATAL Figure 4 1 Address Data Demultiplexing When the MCU is reset in special bootstrap mode a small on chip read only memory ROM is enabled at address BFOO BFFF The ROM contains a bootloader program and a special set of interrupt and reset vectors The MCU fetches the reset vector then executes the bootloader Bootstrap mode is a special variation of the single chip mode Bootstrap mode allows special purpose programs to be entered into internal random access memory RAM When bootstrap mode is selected at reset a small bootstrap ROM becomes present in the memory map Reset and interrupt vectors are located in this ROM at BFCO BFFF The bootstrap ROM contains a small program which initializes the serial communications interface SCI and allows the user to download a program into on chip RAM The size of the downloaded program can be as large as the size of the on chip RAM After a 4 character delay or after receiving the character for the highest address in RAM control MC68HC11E Family Rev 4 68 Operating Modes and On Chip Memo
85. and zero one two or three operands The operands contain information the CPU needs for executing the instruction Complete instructions can be from one to five bytes long 3 6 Addressing Modes 3 6 1 Immediate Technical Data Six addressing modes can be used to access memory Immediate Direct Extended Indexed Inherent Relative These modes are detailed in the following paragraphs All modes except inherent mode use an effective address The effective address is the memory address from which the argument is fetched or stored or the address from which execution is to proceed The effective address can be specified within an instruction or it can be calculated In the immediate addressing mode an argument is contained in the byte s immediately following the opcode The number of bytes following the opcode matches the size of the register or memory location being operated on There are 2 3 and 4 if prebyte is required byte immediate instructions The effective address is the address of the byte following the instruction MC68HC11E Family Rev 4 54 Central Processor Unit CPU MOTOROLA 3 6 2 Direct 3 6 3 Extended 3 6 4 Indexed 3 6 5 Inherent Central Processor Unit CPU Addressing Modes In the direct addressing mode the low order byte of the operand address is contained in a single byte following the opcode and the high order byte of the address is assumed to be 00 Addresse
86. be extended to include additional external interrupt sources through the IRQ pin The default configuration of this pin is a low level sensitive wired OR network When an event triggers an interrupt a software accessible interrupt flag is set When enabled this flag causes a constant request for interrupt service After the flag is cleared the service request is released 5 6 6 Reset and Interrupt Processing Figure 5 5 and Figure 5 6 illustrate the reset and interrupt process Figure 5 5 illustrates how the CPU begins from a reset and how interrupt detection relates to normal opcode fetches Figure 5 6 is an expansion of a block in Figure 5 5 and illustrates interrupt priorities Figure 5 7 shows the resolution of interrupt sources within the SCI subsystem Technical Data MC68HC11E Family Rev 4 124 Resets and Interrupts MOTOROLA POWER ON RESET POR HIGHEST PRIORITY Y DELAY 4064E CYCLES EXTERNAL RESET Y LOAD PROGRAM COUNTER WITH CONTENTS 0F FFFE FFFF VECTOR FETCH CLOCK MONITOR FAIL WITH CME 1 Resets and Interrupts Interrupts LOWEST PRIORITY COP WATCHDOG TIMEOUT WITH NOCOP 0 LOAD PROGRAM COUNTER WITH CONTENTS OF FFFC FFFD VECTOR FETCH LOAD PROGRAM COUNTER WITH CONTENTS OF SFFFA FFFB VECTOR FETCH SET BITS S I AND X Y RESET MCU HARDWARE BEGIN INSTRUCTION SEQUENCE
87. begins when the MCU sends the first character to the host computer indicating that it is ready for the first data character The host computer sends the first data byte 3 and enters its main loop The second data character is sent 4 and the host then waits 5 for the first verify byte to come back from the MCU After the MCU sends FF 8 it enters the WAIT1 loop 9 and waits for the first data character from the host When this character is received 10 the MCU programs it into the address pointed to by the Y index register When the programming time delay is over the MCU reads the programmed data transmits it to the host for verification 11 and returns to the top of the WAIT1 loop to wait for the next data character 12 Because the host previously sent the second data character it is already waiting in the SCI receiver of the MCU Steps 13 14 and 15 correspond to the second pass through the WAIT1 loop Back in the host the first verify character is received and the third data character is sent 6 The host then waits for the second verify character 7 to come back from the MCU The sequence continues as long as the host continues to send data to the MCU Since the WAIT1 loop in the PROGRAM utility is an indefinite loop reset is used to end the process in the MCU after the host has finished sending data to be programmed AN1060 Rev 1 0 290 MOTOROLA INITIALIZE X PROGRAM TIME Y FI
88. chip carrier PLCC Custom ROM 2 MHz E ind 2 MHz MC68L11E1FN2 No ROM no EEPROM 2 MHz MC68L11E0FN2 64 pin quad flat pack QFP Custom ROM 2 MHz 2 ROM 2 MHz MC68L11E1FU2 No ROM no EEPROM 2 MHz MC68L11E0FU2 52 pin thin quad flat pack 10 mm x 10 mm Custom ROM 2 MHz MC68L11E9PB2 No ROM 20 C to 70 C 2 MHz MC68L11E1PB2 No ROM no EEPROM 2 MHz MC68L11E0PB2 56 pin dual in line package with 0 70 inch lead spacing SDIP Custom ROM 2 MHz MC68L11E9B2 No ROM 20 C to 70 C 2 MHz MC68L11E1B2 No ROM no EEPROM 2 MHz MC68L11E0B2 MC68HC11E Family Rev 4 Technical Data MOTOROLA Ordering Information 267 Ordering Information Technical Data MC68HC11E Family Rev 4 268 Ordering Information MOTOROLA Technical Data M68HC11E Family A 1 Contents A 2 A 3 A 4 A 5 A 6 A 2 Introduction Appendix A Development Support In DROP drain QA ESSERE DO E eee eae en eed 269 Motorola M68HC11 E Series Development Tools 270 EVS Evaluation System 270 Motorola Modular Development System MMDS11 271 SPGMR11 Serial Programmer for M68HC11 MCUs 273 This section provides information the development support offered for the E series devices MC68HC11E Family Rev 4 Technical Data MOTOROLA Development Support 269 Development Support A 3 Motorola M68HC11 E Series Development Tools De
89. ee e b bo ee 130 Resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched A reset immediately stops execution of the current instruction and forces the program counter to a known starting address Internal registers and control bits are initialized so the MCU can resume executing instructions An interrupt temporarily suspends normal program execution while an interrupt service routine is being executed After an interrupt has been serviced the main program resumes as if there had been no interruption The four possible sources of reset are e Power on reset POR External reset RESET Computer operating properly COP reset Clock monitor reset POR and RESET share the normal reset vector COP reset and the clock monitor reset each has its own vector MC68HC11E Family Rev 4 108 Resets and Interrupts MOTOROLA Resets and Interrupts Resets 5 3 1 Power On Reset POR A positive transition on Vpp generates a power on reset POR which is used only for power up conditions POR cannot be used to detect drops in power supply voltages 4064 internal clock cycle delay after the oscillator becomes active allows the clock generator to stabilize If RESET is at logical 0 at the end of 4064 teyc the CPU remains in the reset condition until RESET goes to logical 1 The POR circuit only initializes internal circuitry dur
90. expanded mode to gain access to external memories and peripherals To force an immediate jump to the start of EEPROM the bootstrap firmware looks for the first received character to be 00 or break The data reception logic in the SCI looks for a 1 to 0 transition on the RxD pin to synchronize to the beginning of a receive character If the RxD pin is tied to ground no 1 to 0 transition occurs The SCI transmitter sends a break character when the bootloader firmware starts and this break character can be fed back to the RxD pin to cause the jump to EEPROM Since TxD is configured as an open drain output a pullup resistor is required The initial character usually FF that sets the download baud rate is often forgotten AN1060 Rev 1 0 312 MOTOROLA VIOYOLOW ELE o 090 LNY Table 2 Summary of Boot ROM Related Features BOOT 3 MCU Part ROM i xe LD Security Downoad MP on rae 1 2 BFD2 3 BFD4 5 Pen JBHICOESO0 t Utility MC68HC11A0 Mask set 256 0000 FF MC68HC11A1 Mask set 256 0000 FF MC68HC11A8 Mask set 256 0000 FF MC68SEC11A8 Mask set 256 0000 FF MC68HC811E2 MC68SEC811E2 256 B600 0000 0000 FF 256 B600 0000 0000 FF MC68HC11E0 0000 1FF MC68HC11E1 0000 1FF MC68HC11E9 0000 1FF MC68SEC11E9 Yes 0000 1FF B MC68HC711E9 41 A B600 0000 1FF Y MC68HC11F1 42 B 0000 F1
91. for 2 MHz rating 333 ns for 3 MHz rating ViL lt 0 2V no dc loads MC68HC11E Family Rev 4 Technical Data MOTOROLA Electrical Characteristics Electrical Characteristics 11 8 MC68L11E9 E20 DC Electrical Characteristics Characteristics Symbol Min Max Unit Output voltage lLoad 10 0 All outputs except XTAL All outputs except XTAL RESET and MODA V oL Vpp 0 1 Output high voltage lLoad 0 5 mA Vpp 3 0 V lLoad 0 8 mA Vpp 4 5 V All outputs except XTAL RESET and MODA Vpp 0 8 Output low voltage lLoad 1 6 mA Vpp 5 0 V lLoad 1 0 mA Vpp 3 0V All outputs except XTAL VoL 0 4 Input high voltage All inputs except RESET RESET 0 7 x Vpp 0 8 x Vpp Vpp 0 3 Vpp 0 3 Input low voltage all inputs Vss 0 3 0 2 x Vpp I O ports 3 state leakage Vin Vin or Vip PA7 PC 7 0 PD 5 0 AS STRA MODA LIR RESET loz Input leakage current 9 Vin or Vss PA 2 0 IRQ XIRQ XIRQ on EPROM based devices RAM standby voltage power down RAM standby current power down uA Input capacitance PA 2 0 PE 7 0 IRQ XIRQ EXTAL PA7 PC 7 0 PD 5 0 AS STRA MODA LIR RESET 12 pF Output load capacitance All outputs except PD 4 1 PD 4 1 CL 90 100 pF 1 Vp
92. half of each bus cycle the pins become the bidirectional data bus AS is an active high latch enable signal for an external address latch Address information is allowed through the transparent latch while AS is high and is latched when AS drives low The address R W and AS signals are active and valid for all bus cycles including accesses to internal memory locations The E clock is used to enable external devices to drive data onto the internal data bus during the second half of a read bus cycle E clock high R W controls the direction of data transfers R W drives low when data is being written to the internal data bus R W will remain low during consecutive data bus write cycles such as when a double byte store occurs Refer to Figure 4 1 The write enable signal for an external memory is the NAND of the E clock and the inverted R W signal Test mode a variation of the expanded mode is primarily used during Motorola s internal production testing however it is accessible for programming the configuration CONFIG register programming calibration data into electrically erasable programmable read only memory EEPROM and supporting emulation and debugging during development MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 67 Operating Modes Memory 4 3 4 Bootstrap Mode Technical Data ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 CO U
93. in SCDR is not disturbed The OR is cleared when the SCSR is read with OR set followed by a read of the SCDR The noise flag NF bit is set if there is noise on any of the received bits including the start and stop bits The NF bit is not set until the RDRF flag is set The NF bit is cleared when the SCSR is read with FE equal to 1 followed by a read of the SCDR When no stop bit is detected in the received data character the framing error FE bit is set FE is set at the same time as the RDRF If the byte received causes both framing and overrun errors the processor only recognizes the overrun error The framing error flag inhibits further transfer of data into the SCDR until it is cleared The FE bit is cleared when the SCSR is read with FE equal to 1 followed by a read of the SCDR MC68HC11E Family Rev 4 Technical Data MOTOROLA Serial Communications Interface SCI 151 Serial Communications Interface 5 7 8 SCI Registers Five addressable registers are associated with the SCI e Four control and status registers Serial communications control register 1 SCCR1 Serial communications control register 2 SCCR2 Baudrate register BAUD Serial communications status register SCSR One data register Serial communications data register SCDR The SCI registers the same for all M68HC11 E series devices with one exception The SCI system for MC68HC 7 11E20 contains an extra bit in
94. include the MC68L11E20 11 9 MC68L11E9 E20 Supply Currents and Power Dissipation 227 Title changed to include the MC68L11E20 11 11 MC68L11E9 E20 Control Timing Title changed to include 230 the MC68L11E20 11 13 MC68L11E9 E20 Peripheral Port Timing Title changed to 236 include the MC68L11E20 11 15 MC68L11E9 E20 Analog to Digital Converter July 00 Characteristics Title changed to include the MC68L11E20 ari 11 17 MC68L11E9 E20 Expansion Bus Timing Characteristics 244 Title changed to include the MC68L11E20 11 19 MC68L11E9 E20 Serial Peirpheral Interface Characteristics 247 Title changed to include the MC68L11E20 11 21 MC68L11E9 E20 EEPROM Characteristics Title changed 250 to include the MC68L11E20 13 5 Extended Voltage Device Ordering Information 3 0 Vdc to 267 5 5 Vdc Updated table to include MC68L1120 Technical Data MC68HC11E Family Rev 4 4 MOTOROLA Technical Data M68HC11E Family List of Sections Section 1 General Description 23 Section 2 Pin Descriptions 27 Section 3 Central Processor Unit CPU 45 Section 4 Operating Modes and On Chip Memory 65 Section 5 Resets and Interrupts 107 Section 6 Parallel Input Output I O Ports 133 Section 7 Serial Communications Interface SCI 145 Section 8 Serial Peripheral Interface SPI 165 Section 9 Tim
95. initialize any parameters for the EPROM programming process The bootstrap software that ran prior to the loaded program left the SCI turned on and configured in a way that was compatible with the SCI in the master MCU the duplicator program in the master MCU also did not have to set up the SCI for the same reason The programming time and starting address for EPROM programming in the target MCU were also set to default values by the bootloader software before jumping to the start of the downloaded program Before the EPROM in the target MCU can be programmed the Vpp power supply must be available at the XIRQ Vppg pin of the target MCU The duplicator program running in the master MCU monitors this voltage for presence or absence not level at PE7 through resistor divider MOTOROLA 297 Application Note FROM OC5 PIN OF MCU TO MC68HC68T1 RE MO JUM PER 14 BE SURE NO JUMPER IS 55 0NJ14 VEJ7 R14 RI5 input was chosen because the internal circuitry for port E pins can tolerate voltages slightly higher than Vpp therefore resistors R14 and R15 are less critical No data to be programmed is passed to the target MCU until the master MCU senses that Vpp has been stable for about 200 ms When Vpp is ready the master MCU turns on the red LED light emitting diode and begins passing data to the target MCU EPROM Programming Utility explains the activity as data is sent from the maste
96. interrupt CPU operations The most common use for such an interrupt is for serious system problems such as program runaway or power failure The XIRQ input is an updated version of the NMI non maskable interrupt input of earlier MCUs Upon reset both the X bit and bit of the CCR are set to inhibit all maskable interrupts and XIRQ After minimum system initialization software can clear the X bit by a TAP instruction enabling XIRQ interrupts Thereafter software cannot set the X bit Thus an XIRQ interrupt is a non maskable interrupt Because the operation of the bit related interrupt structure has no effect on the X bit the internal XIRQ pin remains unmasked In the interrupt priority logic the XIRQ interrupt has a higher priority than any source that is maskable by the I bit All I bit related interrupts operate normally with their own priority relationship When an l bit related interrupt occurs the bit is automatically set by hardware after stacking the CCR byte The X bit is not affected When an X bit related interrupt occurs both the X and l bits are automatically set by hardware after stacking the CCR A return from interrupt instruction restores the X and l bits to their pre interrupt request state 5 6 3 Illegal Opcode Trap Because not all possible opcodes or opcode sequences are defined the MCU includes an illegal opcode detection circuit which generates an interrupt request When an illegal opcode is de
97. load information into the EPROM or EEPROM of an M68HC11 after final assembly of a module Bootstrap mode is also useful for performing system checks and calibration routines The following paragraphs explain system requirements for use of bootstrap mode in a product It must be possible to force the MODA and MODB pins to logic 0 which implies that these two pins should be pulled up to Vpp through resistors rather than being tied directly to Vpp If mode pins are connected directly to Vpp it is not possible to force a mode other than the one the MCU is hard wired for It is also good practice to use pulldown resistors to Vss rather than connecting mode pins directly to Vss because it is sometimes a useful debug aid to attempt reset in modes other than the one the system was primarily designed for Physically this requirement sometimes calls for the addition of a test point or a wire connected to one or both mode pins Mode selection only uses the mode pins while RESET is active It must be possible to initiate a reset while the mode select pins are held low In systems where there is no provision for manual reset it is usually possible to generate a reset by turning power off and back on It must be possible to drive the PDO RxD pin with serial data from a host computer or another MCU In many systems this pin is already used for SCI communications thus no changes are required In systems where the PDO RxD pin is normally used as a gen
98. made the proper connections and have a high quality cable you should quickly get a PCbug11 command prompt If you do receive a Comms fault error check your cable and board connections Most PCbug11 communications problems can be traced to poorly made cables or bad board connections EB296 332 MOTOROLA Step 3 Step 4 Step 5 Step 8 EB296 Engineering Bulletin PCbug11 defaults to base 10 for its input parameters change this to hexadecimal by typing CONTROL BASE HEX You must declare the addresses of the EPROM array to PCbug11 To do this type EPROM D000 FFFF You are now ready to download your program into the EPROM Connect 12 volts at most 12 5 volts through a 100 O current limiting resistor to P4 connector pin 18 the XIRQ pin At the PCbug11 command prompt type LOADS C MYPROG ISHERE S19 Substitute the name of your program into the command above Use a full path name if your program is not located in the same directory as PCbugl 1 After the programming operation is complete PCbug1 1 will display this message Total bytes loaded xxxx Total bytes programmed yyyy You should now remove the programming voltage from P4 connector pin 18 the XIRQ pin Each ORG directive in your assembly language source will cause a pair of these lines to be generated For this operation yyyy will be incremented by the size of each block of code programmed into the EPROM of the MC68HC711E9 MOTOROL
99. modes signal is always enabled on the MC68HC811E2 2 7 Interrupt Request IRQ The IRQ input provides a means of applying asynchronous interrupt requests to the MCU Either negative edge sensitive triggering or level sensitive triggering is program selectable OPTION register IRQ is always configured to level sensitive triggering at reset When using IRQ in a level sensitive wired OR configuration connect an external pullup resistor typically 4 7 kQ to Vpp 2 8 Non Maskable Interrupt XIRQ Vppg Technical Data NOTE The XIRQ input provides a means of requesting a non maskable interrupt after reset initialization During reset the X bit in the condition code register CCR is set and any interrupt is masked until MCU software enables it Because the XIRQ input is level sensitive it can be connected to a multiple source wired OR network with an external pullup resistor to XIRQ is often used as a power loss detect interrupt Whenever or IRQ is used with multiple interrupt sources each source must drive the interrupt input with an open drain type of driver to avoid contention between outputs IRQ must be configured for level sensitive operation if there is more than one source of IRQ interrupt MC68HC11E Family Rev 4 36 Pin Descriptions MOTOROLA Pin Descriptions MODA and MODB MODA LIR and MODB VSTBY There should be a single pullup resistor near the MCU interrupt
100. on high voltage JSR DLY10 Delay 10 ms CLR 103B Turn off high voltage and set to READ mode 4 6 1 6 CONFIG Register Programming Because the CONFIG register is implemented with EEPROM cells use EEPROM procedures to erase and program this register The procedure for programming is the same as for programming a byte in the EEPROM array except that the CONFIG register address is used CONFIG can be programmed or erased including byte erase while the MCU is operating in any mode provided that PTCON in BPROT is clear To change the value in the CONFIG register complete this procedure 1 Erase the CONFIG register 2 Program the new value to the CONFIG address 3 Initiate reset Do not initiate a reset until the procedure is complete 4 6 2 EEPROM Security Technical Data The optional security feature available only on ROM based MCUs protects the EEPROM and RAM contents from unauthorized access A program or a key portion of a program can be protected against unauthorized duplication To accomplish this the protection mechanism restricts operation of protected devices to the single chip modes This MC68HC11E Family Rev 4 104 Operating Modes and On Chip Memory MOTOROLA Operating Modes Memory EEPROM prevents the memory locations from being monitored externally because single chip modes do not allow visibility of the internal address and data buses Resident programs however hav
101. pin driver input If written PORTA stores the data in an internal latch bits 7 and 3 It drives the pins only if they are configured as outputs Writes to PORTA do not change the pin state when pins are configured for timer input captures or output compares Refer to Section 6 Parallel Input Output Ports During single chip operating modes all port B pins are general purpose output pins During MCU reads of this port the level sensed at the input side of the port B output drivers is read Port B can also be used in simple strobed output mode In this mode an output pulse appears at the STRB signal each time data is written to port B In expanded multiplexed operating modes all of the port B pins act as high order address output signals During each MCU cycle bits 15 8 of the address bus are output on the PB7 PBO pins The PORTB register is treated as an external address in expanded modes MC68HC11E Family Rev 4 Technical Data MOTOROLA Pin Descriptions 41 Pin Descriptions 2 13 3 Port C Technical Data While in single chip operating modes all port C pins are general purpose pins Port C inputs can be latched into alternate PORTCL register by providing an input transition to the STRA signal Port C can also be used in full handshake modes of parallel where the STRA input and STRB output act as handshake control lines When in expanded multiplexed modes all port C pins are configured as mult
102. responsible for keeping a free running watchdog timer from timing out When the software is no longer being executed in the intended sequence a system reset is initiated The state of the NOCOP bit inthe CONFIG register determines whether the COP system is enabled or disabled To change the enable status of the COP system change the contents of the CONFIG register and then perform a system reset In the special test and bootstrap operating modes the COP system is initially inhibited by the disable resets DISR control bit in the TEST1 register The DISR bit can subsequently be written to 0 to enable COP resets The COP timer rate control bits CR 1 0 in the OPTION register determine the COP timeout period The system E clock is divided by 215 and then further scaled by a factor shown in Table 5 1 After reset these bits are 0 which selects the fastest timeout period In normal operating modes these bits can be written only once within 64 bus cycles after reset Table 5 1 COP Timer Rate Select Technical Data Divide XTAL 4 0 MHz XTAL 8 0 MHz XTAL 12 0 MHz XTAL 16 0 MHz CR 1 0 E 215 B Timeout Timeout Timeout Timeout 0 ms 32 8 ms 0 ms 16 4 ms 0 ms 10 9 ms 0 ms 8 2 ms 00 1 32 768 ms 16 384 ms 10 923 ms 8 19 ms 01 4 131 072 ms 65 536 ms 43 691 ms 32 8 ms 10 16 524 28 ms 262 14 ms 174 76 ms 131 ms 11 64 2 098 s 1 049 s 699 05 ms 524 ms 1 0 MHz 2 0 MHz 3 0 MHz
103. semiconductors The file is also on the software download system is called pcbugl1 1 pdf Mj MOTOROLA EB184 Engineering Bulletin To Execute the Program Step 1 Step 2 Use this step by step procedure to program the MC68HC711E9 device Before applying power to the programming board connect the M68HC711E9PGMR serial port P2 to one of your PC COM ports with a standard 25 pin RS 232 cable Do not use a null modem cable or adapter which swaps the transmit and receive signals between the connectors at each end of the cable Place the MC68HC711E9 part in the PLCC socket on your board Insert the part upside down with the notched corner pointing toward the red power LED Make sure both S1 and S2 switches are turned off Apply 5 volts to 5 V 12 volts at most 12 5 volts to Vpp and ground to GND on your programmer board s power connector P1 The remaining TXD PD1 and RXD PDO connections are not used in this procedure They are for gang programming MC68HC711E9 devices which is discussed in the M68HC711E9PGMR Manual You cannot gang program with PCbugl 1 Ensure that the remove for multi programming jumper J1 below the 5 V power switch has a fabricated jumper installed Apply power to the programmer board by moving the 5 V switch to the ON position From a DOS command line prompt start PCbug1 1this way C PCBUG11 gt PCBUG11 E PORT 1 with the connected to COM1 Or CAPCBUG11V gt P
104. special test mode When either special mode is in effect SMOD 1 certain privileges are in effect for instance the ability to write to the mode control bits and fetching the reset and interrupt vectors from BFxx rather than FFxx Table 1 Mode Selection Summary Input Pins Control Bits in HPRIO Mode Selected MODB MODA RBOOT SMOD MDA 1 0 Normal single chip 0 0 0 0 0 Normal expanded 0 0 1 0 0 Special bootstrap 1 1 0 0 1 Special test 0 1 1 The alternate vector locations are achieved by simply driving address bit A14 low during all vector fetches if SMOD 1 For special test mode the alternate vector locations assure that the reset vector can be fetched from external memory space so the test system can control MCU operation In special bootstrap mode the small boot ROM is enabled in the memory map by RBOOT 1 so the reset vector will be fetched from this ROM and the bootloader firmware will control MCU operation MOTOROLA 281 Application Note RBOOT is reset to 1 in bootstrap mode to enable the small boot ROM In the other three modes RBOOT is reset to 0 to keep the boot ROM out of the memory map While in special test mode SMOD 1 which allows the RBOOT control bit to be written to 1 by software to enable the boot ROM for testing purposes Boot ROM Firmware The main program in the boot ROM is the bootloader which is automatically executed as a result of resetting the MC
105. system 0101 Reserved default to IRQ 0110 IRQ external pin or parallel I O 0111 Real time interrupt 1000 Timer input capture 1 1001 Timer input capture 2 1010 Timer input capture 3 1011 Timer output compare 1 1100 Timer output compare 2 1101 Timer output compare 3 1110 Timer output compare 4 1111 Timer input capture 4 output compare 5 Technical Data MC68HC11E Family Rev 4 120 Resets and Interrupts MOTOROLA Resets and Interrupts Interrupts 5 6 Interrupts The MCU has 18 interrupt vectors that support 22 interrupt sources 15 maskable interrupts are generated by on chip peripheral systems These interrupts are recognized when the global interrupt mask bit 1 in the condition code register CCR is clear The three non maskable interrupt sources are illegal opcode trap software interrupt and XIRQ pin Refer to Table 5 4 which shows the interrupt sources and vector assignments for each source Table 5 4 Interrupt and Reset Vector Assignments R Local Vector Address Interrupt Source Bit Mask FFCO C1 FFD4 D5 Reserved FFD6 D7 SCI serial system e SCI receive data register full RIE SCI receiver overrun f RIE SCI transmit data register empty TIE SCI transmit complete TCIE SCI idle line detect ILIE FFD8 D9 SPI serial transfer complete SPIE FFDA DB Pulse accumulator input edge FF
106. the BAUD register that provides a greater selection of baud prescaler rates Refer to 7 8 5 Baud Rate Register Figure 7 8 and Figure 7 9 7 8 1 Serial Communications Data Register SCDR is a parallel register that performs two functions e The receive data register when it is read The transmit data register when it is written Reads access the receive data buffer and writes access the transmit data buffer Receive and transmit are double buffered Address 102 Bit 7 6 5 4 3 2 1 Bit 0 Read R7 T7 R6 T6 R5 T5 R4 T4 R3 T3 R2 T2 Write Reset Indeterminate after reset Figure 7 3 Serial Communications Data Register SCDR Technical Data MC68HC11E Family Rev 4 152 Serial Communications Interface SCI MOTOROLA Serial Communications Interface SCI SCI Registers 7 8 2 Serial Communications Control Register 1 The SCCR1 register provides the control bits that determine word length and select the method used for the wakeup feature Address 102 Bit 7 6 5 4 3 2 1 Bit 0 Read R8 T8 M WAKE Write Reset 0 0 0 0 0 0 Indeterminate after reset Unimplemented Figure 7 4 Serial Communications Control Register 1 SCCR1 R8 Receive Data Bit 8 If M bit is set R8 stores the ninth bit in the receive data character 8 Transmit Data Bit 8 If M bit is set T8 stores the ninth bit in the transm
107. the PCbug11 command prompt type MS 103F 05 The value 05 assumes the EEPROM is to be mapped from 0800 to After the programming operation is complete verifying the the MCHC811E2 is not possible because bootstrap mode the default value is always forced The part is now in secure mode and whatever code you loaded into EEPROM will be erased if you tried to bring the microcontroller up in either expanded mode or bootstrap mode The microcontroller will work properly in the secure mode only in single chip mode If the part is placed in bootstrap mode or expanded mode the code EEPROM and RAM will be erased the microcontroller can be reused EB188 330 MOTOROLA Order this document by EB296 D Motorola Semiconductor Engineering Bulletin EB296 Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU By John Bodnar Austin Texas Introduction Motorola Inc 1998 The PCbug1software needed along with the M68HC11EVBU to program MC68HC711E9 devices is available from the download section ofthe Microcontroller Worldwide Web site http Awww motorola com semiconductors Retrieve the file pcbug342 exe a self extracting archive from the MCU11 directory Some Motorola evaluation board products also are shipped with PCbug11 For specific information about any of the PCbug11 commands see the appropriate sections in the PCbug11 User s Manual part number M68PCBUG11 D
108. the center of the start bit time Samples are then taken at the middle of each bit time 2 to reconstruct the value of the received character all 1s in this case A sample is then taken at the middle of the stop bit time as a framing check a 1 is expected 3 Unless another character immediately follows this FF character the receive data line will idle in the high state as shown at 4 The bottom half of Figure 2 shows how the receiver will incorrectly receive the FF character that is sent from the host at 1200 baud Because the receiver is set to 7812 baud the receive data samples are taken at the same times as in the upper half of Figure 2 The start bit at 1200 baud 5 is 6 5 times as long as the start bit at 7812 baud 6 MOTOROLA 283 Application Note 50000 2 MAY BE REMAPPED 512 TO ANY 4K BOUNDARY k RAM EXTERNAL EXTERNAL 1000 E 103F REGISTER TO ANY 4K BOUNDARY BLOCK EXTERNAL EXTERNAL 512 BYTE MAY BE DISABLED 2 BY AN EEPROM BIT B7FF c SPECIAL Gigs EXTERNAL _ EXTERNAL PECIA VECTORS BFCO m BFFF MAY DISABLED D000 12K USER BY AN EEPROM BIT EPROM or OTP SFFCO NORMAL MODE FFCO VECTORS SFFFF SINGLE EXPANDED SPECIAL SPECIAL FFFF CHIP MULTIPLEXED BOOTSTRAP TEST MODA 0 MODA 1 MODA 0 MODA 1 MODB 1 MODB 1 MODB 0 MODB
109. then read l CERA 9 to PORTB PORTCL Full input TC with 0 STRB Inputs latched jede puipui hand active level 1 into PORTCL on port STAF 1 1 0 N unaffected in shake 12 STRB any active edge handshake mode PORTCL active pulse 0 on STRA Medes Full Read ds Outputs Normal output output PIOC with 0 STRB 0 Y if STRA at active port hand 6 4 4 1 i bwa f 101005 unaffected in shake then write n STRA handshake mode PORTCL active pulse Folow Edge Folow if STRA not at modas DDRC DDRC active level MC68HC11E Family Rev 4 Technical Data MOTOROLA Parallel Input Output I O Ports 143 Parallel Input Output I O Ports Technical Data MC68HC11E Family Rev 4 144 Parallel Input Output I O Ports MOTOROLA Technical Data M68HC11E Family Section 7 Serial Communications Interface SCI 7 1 Contents 7 2 Introduction fam 7 8 7 4 ia 7 6 7 6 1 7 6 2 7 3 7 8 7 8 1 7 8 2 7 8 3 7 8 4 7 8 5 ia 7 10 che 145 acu nes cd 146 Jun CGE PPP uama ama ga 146 Receive Operation 148 Wakeup 148 Idle Line 150 Address Mark Wakeup 150 SCI Error Detection 151 ULT OS
110. verify data is ignored MOTOROLA 315 Application Note Boot ROM Variations Different versions of the M68HC11 have different versions of the bootstrap ROM program Table 3 summarizes the features of the boot ROMs in 16 members of the M68HC11 Family The boot ROMs for the MC68HC11F1 the MC68HC711K4 and the MC68HC11K4 allow additional choices of baud rates for bootloader communications For the three new baud rates the first character used to determine the baud rate is not FF as it was in earlier M68HC11s The intercharacter delay that terminates the variable length download is also different for these new baud rates Table 3 shows the synchronization characters delay times and baud rates as they relate to E clock frequency Commented Boot ROM Listing Listing 3 MC68HC711E9 Bootloader ROM contains a complete commented listing of the boot ROM program in the MC68HC711E9 version of the M68HC11 Other versions can be found in Appendix B of the M68HC11 Reference Manual and in the freeware area of the Motorola Web site Table 3 Bootloader Baud Rates Baud Rates at E Clock Sync Timeout Character Delay 2 MHz 2 1 MHz 3 MHz 3 15 MHz 4 MHz 4 2 MHz FF 4 characters 7812 8192 11 718 12 288 15 624 16 838 4characters 1200 1260 1800 1890 2400 2520 F0 4 9 characters 9600 10 080 14 400 15 120 19 200 20 160 FD 17 3 characters 5208 5461 7812 8192 10 416 10 922
111. would connect the 12 V programming voltage to the OC5 output of the MCU Connect the EVBU to its dc power supply When it is time to program the MCU EPROM turn on the 12 volt programming power supply to the new circuitry in the wire wrap area Connect the EVBU serial port to the appropriate serial port on the host system For the Macintosh this is the modem port with a modem cable For the MS DOS computer it is connected to COM1 with a straight through or modem cable Power up the host system and start the BASIC program If the program has not been compiled this is accomplished from within the appropriate BASIC compiler or interpreter Power up the EVBU Answer the prompt for filename with either a RETURN to accept the default shown or by typing in a new filename and pressing RETURN MS DOS is a registered trademark of Microsoft Corporation in the United States and other countries AN1060 Rev 1 0 306 MOTOROLA AN1060 Rev 1 0 Application Note The program will inform the user that it is working on converting the file from S records to binary This process will take from 30 seconds to a few minutes depending on the computer A prompt reading Comm port open will appear at the end of the file conversion This is the last chance to ensure that everything is properly configured on the EVBU Pressing RETURN will send the bootcode to the target MC68HC711E9 The program then informs the user that the
112. x lt Ck x lt x k x lt x x x x k x x x x lt 67 BF00 ORG SBF00 68 k lt lt k k lt lt k x C Ck k C k x lt x k x lt x x lt x k x lt Ck x lt x k x lt x x x x k x x x x lt 69 70 Next two instructions provide a predictable place 71 to call PROGRAM UPLOAD even if the routines 72 change size future versions 73 74 BF00 7EBF13 PROGRAM JMP PRGROUT EPROM programming utility 75 BFO3 UPLOAD EQU Upload utility 76 Ck k k k lt Ck k x Ck Ck k Ck k x x K k x lt k x lt x k x lt x x lt x k x lt Ck x lt x k x lt x x x x k x x lt x x lt 78 UPLOAD Utility subroutine to send data from 79 inside the MCU to the host via the SCI interface 80 Prior to calling UPLOAD set baud rate turn on SCI 81 and set Y first address to upload 82 Bootloader leaves baud set SCI enabled and 83 Y pointing at EPROM start 50000 so these default 84 values do not have to be changed typically 85 Consecutive locations are sent via SCI in an 86 infinite loop Reset stops the upload process 87 Ck k K k x lt k x Ck k k lt lt k CK C Ck KKK KK KKK KKK x lt x k x lt Ck x lt x k x lt x x x x k x x lt x x lt 88 BF03 CF1000 LDX S1000 Point to internal registers 89 BF06 18A600 UP LOOP LDAA 0 Read 90 09 1F2E80FC BRCLR SCSR X 80 Wait for TDRE 91 BFOD A72F STAA SCDAT X Send it 92 BFOF 1808 INY 93 BF11 20F3 BRA UPLOOP Next 94 AN
113. 0 EEPROM Mapping Bits EE 3 0 apply only to MC68HC811E2 Refer to Section 4 Operating Modes and On Chip Memory NOSEC Security Mode Disable Bit Refer to Section 4 Operating Modes and On Chip Memory MC68HC11E Family Rev 4 Technical Data MOTOROLA Resets and Interrupts 113 Resets and Interrupts NOCOP COP System Disable Bit 0 COP enabled forces reset on timeout 1 COP disabled does not force reset on timeout ROMON ROM EPROM Enable Bit Refer to Section 4 Operating Modes and On Chip Memory EEON EEPROM Enable Bit Refer to Section 4 Operating Modes and On Chip Memory 5 4 Effects of Reset When a reset condition is recognized the internal registers and control bits are forced to an initial state Depending on the cause ofthe reset and the operating mode the reset vector can be fetched from any of six possible locations Refer to Table 5 2 Table 5 2 Reset Cause Reset Vector and Operating Mode Normal Mode Special Test Cause of Reset Vector or Bootstrap POR or RESET pin FFFE FFFF BFFE BFFF Clock monitor failure FFFC FFFD BFFC BFFD COP Watchdog Timeout FFFA FFFB BFFA BFFB These initial states then control on chip peripheral systems to force them to known startup states as described in the following subsections Technical Data MC68HC11E Family Rev 4 114 Resets and Interrupts MOTOROLA Resets and Interrupts Effects of Reset 5
114. 0 0 0 0 0 0 0 _ Read Bitl5 Bitl4 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Timer Counter Register High 100E TCNTH Write see page 193 eset 0 0 0 0 0 0 0 0 Read Bit Bit Bit 4 Bit Bit 2 Bit 1 Bit Timer Counter Register Low eag ES ra ES i 100F TCNTL Write See page 193 Reset 0 0 0 0 0 0 0 0 Read Timer Input Capture 1 Register Bitl5 Bitl4 Bit13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1010 High Write are page I Reset Indeterminate after reset Read Timer Input Capture 1 Register Bit 7 Bit6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 1011 Low TIC1L Write Reset Indeterminate after reset Read Timer Input Capture 2 Register Bitl5 Bitl4 Bitl3 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1012 High TIC2H Write Reset Indeterminate after reset Read TImer Input Capture 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1013 Register Low TIC2L Write SEE PORE Reset Indeterminate after reset Read Timer Input Capture 3 Register Bitl5 Bitl4 Bit13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1014 High TIC3H Write ME EAE Jan Reset Indeterminate after reset Unimplemented R Reserved U Unaffected 2 Indeterminate after reset Figure 4 7 Register and Control Bit Assignments Sheet 3 of 8 Technical Data MC68HC11E Family Rev 4 74 Operating Modes and On Chip Memory MOTOROLA Addr
115. 00034 00048 00053 SEND1 B66B 00090 00038 00067 00070 SPCR 0028 00010 00031 TDRE 0080 00019 00091 TRDYLP B66D 00091 00091 VERF B64F 00071 00069 00071 VERFOK B65F 00078 00074 WT4BRK B60B 00034 00034 WTAFF B627 00053 00053 WTAVPP B630 00057 00060 Errors None Labels 28 Last Program Address 5 67 Last Storage Address 0000 Program Bytes 007D 125 Storage Bytes 0000 0 AN1060 Rev 1 0 MOTOROLA 301 Application Note Driving Boot Mode from a Personal Computer Hardware Software In this example a personal computer is used as the host to drive the bootloader of an MC68HC711E9 An M68HC11 EVBU is used for the target MC68HC711E9 A large program is transferred from the personal computer into the EPROM of the target MC68HC711E9 Figure 7 shows a small modification to the EVBU to accommodate the 12 volt nominal EPROM programming voltage The XIRQ pin is connected to a pullup resistor two jumpers and the 60 pin connectors P4 and P5 The object of the modification is to isolate the XIRQ pin and then connect it to the programming power supply Carefully cut the trace on the solder side of the EVBU as indicated in Figure 7 This disconnects the pullup resistor RN1 D from XIRQ but leaves 4 18 P5 18 and jumpers J7 and J14 connected so the EVBU can still be used for other purposes after programming is done Remove any fabricated jumpers from J7 and J14 The EVBU normally has a jumper at J7 to support the tra
116. 1060 Rev 1 0 318 MOTOROLA Application Note 95 k k x lt k x k Ck k x lt k x lt k k x lt k x lt x k x lt k x x x k x lt Ck x lt x k lt lt x x lt lt k x lt x x lt 96 PROGRAM Utility subroutine to program EPROM 97 Prior to calling PROGRAM set baud rate turn on SCI 98 set X 2ms prog delay constant and set Y first 99 address to program SP must point to RAM 100 Bootloader leaves baud set SCI enabled X 4200 101 and Y pointing at EPROM start D000 so these 102 default values don t have to be changed typically 103 Delay constant in X should be equivalent to 2 ms 104 at 2 1 MHz X 4200 at 1 MHz X 2000 105 An external voltage source is required for EPROM 106 programming 107 This routine uses 2 bytes of stack space 108 Routine does not return Reset to exit 109 CK k k CK C Ck k CC 00K C C CK C k CK lt Ck k Ck Ck CK lt lt k x lt Ck Ck lt x k kk Sk x x x k x x x x lt 110 BF13 PRGROUT EQU a Tat BEL 36 PSHX Save program delay constant 112 BF14 CE1000 LDX 51000 Point to internal registers 113 17 114 Send SFF to indicate ready for program data 115 116 17 1F2E80FC BRCLR SCSR X 80 Wait for TDRE 117 86FF LDAA SFF 118 1 A72F STAA SCDAT X 119 120 BF1F WAITI1 EQU Ws 121 1 2 20 BRCLR SCSR X 20 Wait fo
117. 18 E9 5 ADDA Add Memory to A M gt A A IMM 8B 2 A A A A A A DIR 9B dd 3 A EXT BB hh Il 4 A IND X AB 4 A IND Y 18 AB 5 ADDB opr Add Memory to B M B B IMM CB jii 2 A B B DIR 3 B EXT FB hh Il 4 B IND X EB 4 B IND Y 18 5 ADDD Add 16 BittoD D M M 1 gt D IMM C3 jj kk 4 A A A DIR D3 dd 5 EXT hh Il 6 IND X ff 6 IND Y 18 ff 7 ANDA opr AND A with A M A A IMM 84 2 0 Memory A DIR 94 3 A EXT B4 hh Il 4 A IND X A4 4 A IND Y 18 A4 5 ANDB opr AND B with BeM gt B B IMM C4 jii 2 A 0 Memory B DIR D4 dd 3 B EXT F4 hh Il 4 B IND X E4 4 B IND Y 18 E4 5 ASL opr Arithmetic Shif EXT 78 hh Il 6 IND X 68 6 ao INDY 18 68 7 ASLA Arithmetic Shif A INH 48 2 Left A 0 C b7 b0 ASLB Arithmetic Shif B INH 58 2 Left B Deco C b7 b0 ASLD Arithmetic Shif INH 05 3 Left D D lt EDT TD lt 0 C b0b7 B 00 ASR Arithmetic Shif EXT 77 hh il 6 Right IND X 67 6 b7 b0 C IND Y 18 67 7 ASRA Arithmetic Shif A INH 47 2 Right A c b7 b0 C ASRB Arithmetic Shif B INH 57 2 Right b7 b C BCC rel Branch if Carry C 0 REL 24 3 Clear BCLR opr Clear Bit s
118. 2 which is available from the Motorola Literature Distribution Center as well as the Worldwide Web at http www motorola com semiconductors The is also on the software download system and is called pcbug11 pdf Mj MOTOROLA EB296 Engineering Bulletin Programming Procedure Step 1 Step 2 Once you have obtained PCbug11 use this step by step procedure to program your MC68HC711E9 part Before applying power to the EVBU remove the jumper from J7 and place it across J3 to ground the MODB pin e Place a jumper across J4 to ground the MODA pin This will force the EVBU into special bootstrap mode on power up Remove the resident MC68HC11E9 MCU from the EVBU Place your MC68HC711E9 in the open socket with the notched corner of the part aligned with the notch on the PLCC socket Connect the EVBU to one of your PC COM ports Apply 5 volts to Vpp and ground to GND on the power connector of your EVBU Also take note of P4 connector 18 In step 5 you will connect a 12 volt at most 12 5 volts programming voltage through a 100 0 current limiting resistor to the XIRQ pin Do not connect this programming voltage until you are instructed to do so in step 5 From a DOS command line prompt start PCbug11 with C PCBUG11 gt PCBUG11 E PORT 1 with the EVBU connected to COM1 C PCBUG11 gt PCBUG11 E PORT 2 with the EVBU connected to COM2 PCbug11 only supports COM ports 1 and 2 If you have
119. 2 Falling edge sensitive input 3 Maximum pulse accumulator clocking rate is E clock frequency divided by 2 Figure 11 2 Timer Inputs Technical Data MC68HC11E Family Rev 4 230 Electrical Characteristics MOTOROLA VIOYOLOW sonsuejoeJeu2 91192 3 3LLOH89ON ejeq jeoiuuoe Figure 11 3 POR External Reset Timing Diagram Dui 04302 023 631 H890 91192 3 sonsuejoeJeu 9119213 VIOYOLOW ejeq jeoiuuoe 31L0H890IN Notes 1 Edge Sensiti ve IRQ pin IRQE bit 1 2 Level sensitive IRQ pin IRQE bit 0 3 OR 4064 tcvc i if DLY bit 1 or 4 tcvc if DLY 0 RQ with X bit in CCR 5 IRQ or r XIRQ with X bit i in 0 Figure 11 4 STOP Recovery Timing Diagram m O m fo e m O 0 VIOYOLOW sonsuejoeJeu 9119213 Eez t 3LLOH89ON ejeq jeoiuuoe XIRO OR INTERNAL INTERRUPTS ADDRESS PCH XL XH A B CCR STACK REGISTERS DN Note RESET also causes recovery from WAIT Figure 11 5 WAIT Recovery from Interrupt Timing Diagram OU0D 023 634 H890 e211199 3 vee sonsuejoeJeu 9119213 VIOYOLOW ejeq jeoiuuoe V 3L1L0H890IN OP OP ow EC Hee
120. 3 ns Crystal frequency fyTAL 4 0 8 0 12 0 MHz External oscillator frequency 4 40 8 0 dc 12 0 MHz Processor control setup time t 300 175 133 tpcsu 1 4 50 ns PCSU 2n Hs Reset input pulse width To guarantee external reset vector PW t Minimum input time can be pre empted RET 8 8 by internal reset 1 1 1 Mode programming setup time 2 2 2 Mode programming hold time 10 10 10 ns Interrupt pulse width IRQ edge sensitive mode PWIno 20 ns 1020 520 353 ns Wait recovery startup time twrs 4 4 4 pulse width input capture pulse accumulator input 1020 520 353 PWrim 20 ns 1 Vpp 5 0 Vdc 10 Vss 0 Vdc TA T to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 RESET is recognized during the first clock cycle it is held low Internal circuitry then drives the pin low for four clock cycles releases the pin and samples the pin level two cycles later to determine the source of the interrupt Refer to Section 5 Resets and Interrupts for further detail MC68HC11E Family Rev 4 Technical Data MOTOROLA Electrical Characteristics 229 Electrical Characteristics 11 11 MC68L11E9 E20 Control Timing 1 0 MHz 2 0
121. 3 which accounts for the address and checksum bytes and leaves just the number of object code bytes in the record Starting at line 1100 the 2 byte 4 character starting address is converted to decimal This address is the starting address for the object code bytes to follow An index into the CODE array is formed by subtracting the base address initialized at the start of the program from the starting address for this S record A FOR NEXT loop starting at line 1130 converts the object code bytes to decimal and saves them in the CODE array When all the object code bytes have been converted from the current S record the program loops back to find the next S1 record A problem arose with the BASIC programming technique used The draft versions of this program tried saving the object code bytes directly as binary in a string array This caused Out of Memory or Out of String Space errors on both a 2 Mbyte Macintosh and a 640 Kbyte PC The solution was to make the array an integer array and perform the integer to binary conversion on each byte as it is sent to the target part The one compromise made to accommodate both Macintosh and PC versions of BASIC is in lines 1500 and 1505 Use line 1500 and comment out line 1505 if the program is to be run on a Macintosh and conversely use line 1505 and comment out line 1500 if a PC is used After the COM port is opened the code to be bootloaded is modified by adding the FF to the start of t
122. 3 0 Vdc to 5 5 Vss 0 TA T to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 Input clocks with duty cycles other than 5096 affect bus performance Timing parameters affected by input clock duty cycle are identified by a and b To recalculate the approximate bus timing values substitute the following expressions in place of 1 8 in the above formulas where applicable 1 x 1 4 toyo b dc x 1 4 tcyc Where dc is the decimal value of duty cycle percentage high time Technical Data MC68HC11E Family Rev 4 244 Electrical Characteristics MOTOROLA Electrical Characteristics MC68L11E9 E20 Expansion Bus Timing Characteristics R W ADDRESS 2 e UR CT pe MULTIPLEXED D k 1 8 Q5 Q4 AS 1 gt Note Measurement points shown 20 70 Figure 11 14 Multiplexed Expansion Bus Timing Diagram MC68HC11E Family Rev 4 Technical Data MOTOROLA Electrical Characteristics 245 Electrical Characteristics 11 18 Serial Peripheral Interface Timing Characteristics N 1 Symbol ES Unit um isti mbo ni Characteristic y Min Max Min Max Frequency of operation fy de 3 0 die 3 0 MHz E clock E clock period 333 333 ns Operating frequency Master fop m 1 32 1 2 1 128 2
123. 31 Resets and Interrupts Technical Data MC68HC11E Family Rev 4 132 Resets and Interrupts MOTOROLA Technical Data M68HC11E Family 6 1 Contents 6 2 Introduction Section 6 Parallel Input Output I O Ports 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 liebe are ees AEAEE 133 134 RC TIPP n 136 MU Ionio Sup dic aA wa 136 gtk PPP 138 e a GEO 139 Handshake PRICE a a u wer gor asas scena doe 139 Parallel Control 141 All M68HC1 1 E series MCUs have five input output I O ports and up to 38 I O lines depending on the operating mode Refer to Table 6 1 for a summary of the ports and their shared functions Table 6 1 Input Output Ports Port Input Bidirectional Shared Functions Pins Pins Pins Port A 3 3 2 Timer Port B 8 High order address Port C 8 Low order address and data bus Serial communications interface Port D 6 SCI and serial peripheral interface SPI Port E 8 Analog to digital A D converter MC68HC11E Family Rev 4 Technical Data MOTOROLA Parallel Input Output I O Ports 133 Parallel Input Output I O Ports Port pin function is mode dependent Do not confuse pin function with the electrical state of the pin at reset Port pins are either driven to a specified logic l
124. 4 DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH MAXIMUM MOLD FLASH 0 25 0 010 INCHES MILLIMETERS DIM MIN MAX MIN MAX A 2035 2065 5169 5245 B 0540 0560 13 72 1422 C 0155 0200 3 94 5 08 lt H D 0014 0022 036 0 56 0035BSC 0 89 BSC 0032 0046 081 117 G 0070BSC 1 778 BSC H 0 300BSC 7 62 85 J 0008 0 015 020 038 SEATING K 0115 0135 2 92 343 F Mal L 0600BSC 1524 BSC x M oe o 159 Diti lt J sopi 0 020 0 040 051 1 02 0 2510 10 9 0 25 0 010 T B Technical Data MC68HC11E Family Rev 4 258 Mechanical Data MOTOROLA Mechanical Data 48 Pin Plastic DIP Case 767 12 8 48 Plastic DIP Case 767 NOTE MC68HC81 1E2 is the only member of the E series that is offered in a 48 pin plastic dual in line package NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION INCH 3 DIMENSION LTO CENTER OF LEAD WHEN FORMED LEL 4 DIMENSIONS AANDBDO NOT INCLUDE MOLD FLASH MAXIMUM MOLD FLASH 0 25 0 010 TIR TAPER INCHES MILLIMETERS DIM MIN MAX MI
125. 42 TIMER OUTPUT COMPARE 4 BFE4 00109 FDB 100 39 TIMER OUTPUT COMPARE 3 BFE6 00DC FDB 100 36 TIMER OUTPUT COMPARE 2 BFE8 OODF FDB 100 33 TIMER OUTPUT COMPARE 1 BFEA 00 2 FDB 100 30 TIMER INPUT CAPTURE 3 BFEC 00 5 FDB 100 27 TIMER INPUT CAPTURE 2 BFEE 00 8 FDB 100 24 TIMER INPUT CAPTURE 1 BFFO 00 FDB 100 21 REAL TIME INT BFF2 00 FDB 100 18 BFF4 00 1 FDB 5100 15 BFF6 00F4 FDB 5100 12 SWI BFF8 00F7 FDB 100 9 ILLEGAL OP CODE BFFA 00FA FDB 100 6 COP FAIL BFFC 00FD FDB 100 3 CLOCK MONITOR BFFE BF54 FDB BEGIN RESET C000 END AN1060 Rev 1 0 MOTOROLA 321 Application Note Symbol Table Line Number Cross Reference Symbol Name Value Def BAUD 002B 00037 00160 00180 BAUDOK BF8A 00183 00178 BEGIN 54 00155 00250 DELAYF 021B 00061 00163 DELAYS ODBO 00060 00181 DONEIT 47 00142 00124 EE PMEND BUFF 00050 EEPMSTR B600 00049 00175 ELAT 0020 00043 00125 00128 EPGM 0001 00044 00128 EPRMEND FFFF 00053 EPRMSTR 000 00052 00206 NEWONE BF9B 00196 00189 NOTZERO BF7E 00176 00174 OC1F 0080 00034 00136 00139 PORTD 0008 00029 00168 PPROG 003B 00041 00126 00129 PRGROUT BF13 00110 00074 PROGDEL 1068 00063 00205 PROGRAM BFOO 00074 RAMEND OlFF 00056 00156 00201 RAMSTR 0000 00055 00184 00207 SCCR2 002D 00038 00162 00167 SCDAT 002F 00040 00091 00118 SCSR 002E 00039 000
126. 488 600 977 1221 1465 1953 0 1 0 1 1 0 4 64 244 300 488 610 732 977 0 1 0 1 1 1 4 128 122 150 244 305 366 488 0 1 1 0 0 0 13 1 4808 5908 9615 12019 14423 19231 0 1 1 0 0 1 13 2 2404 2954 4808 6010 7212 9615 0 1 1 0 1 0 13 4 1202 1477 2404 3005 3606 4808 0 1 1 0 1 1 13 8 601 738 1202 1502 1803 2404 0 1 1 1 0 0 13 16 300 369 601 751 901 1202 0 1 1 1 0 1 13 32 150 185 300 376 451 601 0 1 1 1 1 0 13 64 75 92 150 188 225 300 0 1 1 1 1 1 13 128 38 46 75 94 113 150 1 0 0 0 0 0 39 1 1603 1969 3205 4006 4808 6410 1 0 0 0 0 1 39 2 801 985 1603 2003 2404 3205 1 0 0 0 1 0 39 4 401 492 801 1002 1202 1603 1 0 0 0 1 1 39 8 200 246 401 501 601 801 1 0 0 1 0 0 39 16 100 123 200 250 300 401 1 0 0 1 0 1 39 32 50 62 100 125 150 200 1 0 0 1 1 0 39 64 25 31 50 63 75 100 1 0 0 1 1 1 39 128 13 15 25 31 38 50 Shaded areas reflect standard baud rates MC68HC 7 11E20 do not set SCP1 or SCPO when SCP2 is 1 Technical Data MC68HC11E Family Rev 4 158 Serial Communications Interface SCI MOTOROLA Serial Communications Interface SCI SCI Registers RCKB SCI Baud Rate Clock Check Bit Test SCR 2 0 SCI Baud Rate Select Bits MC68HC11E Family Rev 4 Selects receiver and transmitter bit rate based on output from baud rate prescaler stage Refer to Figure 7 8 and Figure 7 9 The prescaler bits SCP 2 0 determine the highest baud rate and the SCR 2 0 bit
127. 7 6 5 4 3 2 1 Bit 0 Bit15 Bitl4 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit2 Bit1 Bit 0 1 1 1 1 1 1 1 1 0 2 012 0 3 013 0 4 014 0 5 015 0 0 0 0 0 0 0 0 EDG4B EDG4A EDG1B EDGIA EDG2B EDG2A EDG3B EDG3A 0 0 0 0 0 0 0 0 0 21 0C3l 0C4l 141051 2 0 0 0 0 0 0 0 0 OCIF OC2F OC3F OC4F 14 05F IC1F IC2F IC3F 0 0 0 0 0 0 0 0 TOI RTII PAOVI PRO 0 0 0 0 0 0 0 0 TOF RTIF PAOVF PAIF 0 0 0 0 0 0 0 0 DDRA7 PAEN PAMOD PEDGE DDRA3 14 05 RTR1 RTRO 0 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected 2 Indeterminate after reset MC68HC11E Family Rev 4 76 Operating Modes and On Chip Memory MOTOROLA Operating Modes Memory Memory Map Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read Pulse Accumulator Count Bit7 Bit6 Bit 5 Bit4 Bit 3 Bit2 Bit1 Bit 0 1027 Register PACNT Write Sen poge 20i Reset Indeterminate after reset Read Serial P eripheral Control SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPRO 1028 Register SPCR Write See page 173 pag Reset 0 0 0 0 0 1 U U Read Serial Peripheral Status is SPIF WCOL MODF 1029 Register SPSR Write 119 aat 0 0 0 0 0 0 0 0 I Read Serial Peripheral Data 1 0 Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 102A Register SPDR Write
128. 8 T LM N 3x VIEW Y e UUUUUUYUUUUUU E N lt 5 1 jen E zi EX lt 1 A TT lt A1 51 gt F lt A gt l 5 DT SEATING 4 03 0 05 0 002 Y A 0 10 0 004 oH 2xRR1 0 25 0 010 M GAGE PLANE VIEW AA MC68HC11E Family Rev 4 MU Mechanical Data 52 Pin Thin Quad Flat Pack Case 848D lt Je M N VIEW Y F BASE METAL PLATING J U a 0 13 0 005 1 OINO SECTION ROTATED 90 CLOCKWISE NOTES m wn a DIMENSIONING AND TOLERANCING PER ANSI 982 Y14 5M 1 CONTROLLING DIMENSION MILLIMETER DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE DATUMS L M AND N TO BE DETERMINED AT DATUM PLANE DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE T DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTR
129. 8HC11E9CFU3 40 C to 105 C 2 MHz MC68HC11E9VFU2 40 C to 125 C 2 MHz MC68HC11E9MFU2 64 pin quad flat pack continued 0 C to 70 3 MHz MC68HC11E20FU3 2 MHz MC68HC11E20CFU2 409 to 85 C 20 Kbytes Custom ROM 3 MHz MC68HC11E20CFU3 40 to 105 C 2 MHz MC68HC11E20VFU2 40 C to 125 C 2 MHz MC68HC11E20MFU2 MC68HC11E Family Rev 4 Technical Data MOTOROLA Ordering Information 265 Ordering Information Description Temperature Frequency MC Order Number 52 pin thin quad flat pack 10 mm x 10 mm 0 C to 70 3 MHz MC68HC11E9PB3 2 MHz MC68HC11E9CPB2 40 C to 85 C Custom ROM 3 MHz MC68HC11E9CPB3 409 to 105 C 2 MHz MC68HC11E9VPB2 40 C to 125 C 2 MHz MC68HC11E9MPB2 56 pin dual in line package with 0 70 inch lead spacing SDIP 0 C to 70 C 3 MHz MC68HC11E9B3 2 MHz MC68HC11E9CB2 40 C to 85 C Custom ROM 3MHz MC68HC11E9CB3 409 to 105 C 2 MHz MC68HC11E9VB2 40 to 125 C 2 MHz MC68HC11E9MB2 Technical Data MC68HC11E Family Rev 4 266 Ordering Information MOTOROLA Ordering Information Extended Voltage Device Ordering Information 3 0 Vdc to 5 5 Vdc 13 5 Extended Voltage Device Ordering Information 3 0 Vdc to 5 5 Description Temperature Frequency MC Order Number 52 pin plastic leaded
130. 90 00116 SPCR 0028 00036 00158 STAR BFAA 00204 00194 000 00030 00134 TFLG1 0023 00032 00137 00139 0016 00031 00135 00164 UPLOAD BF03 00075 UPLOOP BF06 00089 00093 WAIT 00186 00202 1 BF1F 00120 00147 WTLOOP 90 00188 00193 Errors None Labels 35 Last Program Address SBFFF Last Storage Address 0000 Program Bytes 0100 256 Storage Bytes 0000 0 00140 00169 00122 00121 00182 00145 00172 00197 00199 00143 00171 00189 00187 AN1060 Rev 1 0 322 MOTOROLA Order this document by EB184 D Motorola Semiconductor Engineering Bulletin EB184 Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR By Edgar Saenz Austin Texas Introduction NOTE Motorola Inc 1998 The PCbug11 software needed along with the M68HC711E9PGMR to program 68 711 9 devices is available from the download section ofthe Microcontroller Worldwide Web site http www motorola com semiconductors Retrieve the file pcbug342 exe a self extracting archive from the MCU11 directory Some Motorola evaluation board products also are shipped with PCbug11 For specific information about any of the PCbug11 commands see the appropriate sections in the PCbug11 User s Manual part number M68PCBUG11 D2 which is available from the Motorola Literature Distribution Center as well as the Worldwide Web at http www motorola com
131. A 333 Engineering Bulletin PCbug11 will display the above message whether or not the programming operation was successful As a precaution you should have PCbug11 verify your code At the PCbug11 command prompt type VERF CAMYPROQGWSHERE S19 Substitute the name of your program into the command above Use a full path name if your program is not located in the same directory as PCbug11 If the verify operation fails a list of addresses which did not program correctly is displayed Should this occur you probably need to erase your part more completely To do so allow the MC68HC711E9 to sit for at least 45 minutes under an ultraviolet light source Attempt the programming operation again If you have purchased devices in plastic packages one time programmable parts you will need to try again with a new unprogrammed device EB296 334 MOTOROLA HOW REACH US USA EUROPE LOCATIONS LISTED Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 TECHNICAL INFORMATION CENTER 1 800 521 6274 HOME PAGE http www motorola com semiconductors Information in this d
132. AI inhibits counting MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 205 Timing System DDRA3 Data Direction for Port A Bit 3 Refer to Section 6 Parallel Input Output Ports 14 05 Input Capture 4 Output Compare 5 Bit 0 Output compare 5 function enable 4 1 Input capture 4 function enable OC5 RTR 1 0 RTI Interrupt Rate Select Bits Refer to 9 6 Real Time Interrupt RTI 9 8 2 Pulse Accumulator Count Register This 8 bit read write register contains the count of external input events at the PAI input or the accumulated count The PACNT is readable even if PAI is not active in gated time accumulation mode The counter is not affected by reset and can be read or written at any time Counting is synchronized to the internal PH2 clock so that incrementing and reading occur during opposite half cycles Address 1027 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit2 Bit 1 Bit 0 Write Reset Indeterminate after reset Figure 9 26 Pulse Accumulator Count Register PACNT Technical Data MC68HC11E Family Rev 4 206 Timing System MOTOROLA Timing System Pulse Accumulator 9 8 3 Pulse Accumulator Status and Interrupt Bits The pulse accumulator control bits PAOVI and PAII PAOVF and PAIF are located within timer registers TMSK2 and TFLG2 Address 1024 Bit 7 6 5 4 3 2 1 Bit 0 Read TO
133. AS PB2 ADDR10 PC6 ADDR6 DATA6 4 M68HC11E SERIES PB3 ADDR11 PC7 ADDR7 DATAT PB4 ADDR12 RESET PB5 ADDR13 XIRQMppe PB6 ADDR14 IRQ PB7 ADDR15 PDO RxD PA0 IC3 EVss PA1 IC2 PA2 IC1 0 5 4 0 1 4 0 4 0 1 04 5 5 0 3 0 1 5 55 6 0 2 0 1 Voo 27 0 1 Vss 28 EVpp PD1 TxD PD2 MISO PD3 MOSI applies only to devices with EPROM OTPROM Figure 2 4 Pin Assignments for 56 Pin SDIP MC68HC11E Family Rev 4 Technical Data MOTOROLA Pin Descriptions 31 Pin Descriptions 2 3 Vpp and Vss Technical Data 0 1 48 Vpp 6 0 2 0 1 47 PD5 SS 5 0 3 0 1 46 PD4 SCK 4 0 4 0 1 45 PD3 MOSI 0 5 4 0 1 44 PD2 MISO PA2 IC1 43 PD1 TxD 1 2 42 PDO RXD 4110 IRQ PB7 ADDR15 40 XIRQ PB6 ADDR14 1 39 RESET PB5 ADDR13 PCTIADDR7 DATAT PBA ADDR12 1 MC68HC811bE2 37 I PC6 ADDRE DATAG PB3 ADDR11 PC5 ADDR5 DATA5 PB2 ADDR10 PC4 ADDR4 DATA4 PB1 ADDR9 PC3 ADDR3 DATA3 PBO ADDR8 PC2 ADDR2 DATA2 PEO ANO PCI ADDRI DATAl PEI ANI PCO ADDRO DATAO PE2 AN2 XTAL PE3 AN3 20 EXTAL Vat 0 21 STRB R W 22 Vss 23 STRA AS MODBNMsrpy 24 MODAILIR Figure 2 5 Pin Assignments for 48 Pin DIP MC68HC811E2 Power is supplied to the MCU through Vpp and Vss Vpp is the power supply Vss is ground The MCU operates from a single 5 volt nominal power supply Low voltage
134. Bit 1 Bit 0 Write Reset Indeterminate after reset Figure 9 4 Timer Input Capture 1 Register Pair TIC1 Technical Data MC68HC11E Family Rev 4 184 Timing System MOTOROLA Timing System Input Capture Register name Timer Input Capture 2 Register High Address 1012 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit 8 Write Reset Indeterminate after reset Register name Timer Input Capture 2 Register Low Address 1013 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit2 Bit 1 Bit 0 Write Reset Indeterminate after reset Figure 9 5 Timer Input Capture 2 Register Pair TIC2 Register name Timer Input Capture 3 Register High Address 1014 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit 8 Write Reset Indeterminate after reset Register name Timer Input Capture 3 Register Low Address 1015 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset Indeterminate after reset Figure 9 6 Timer Input Capture 3 Register Pair TIC3 MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 185 Timing System 9 4 3 Timer Input Capture 4 Output Compare 5 Register Use TI4 O5 as either an input capture register or an output compare register depe
135. C11s in Motorola EVMs The following hardware and software example will demonstrate this and other bootstrap mode features The schematic in Figure 6 shows the circuitry for a simple EPROM duplicator for the MC68HC711E9 The circuitry is built in the wire wrap area of an M68HC11EVBU evaluation board to simplify construction The schematic shows only the important portions of the EVBU circuitry to avoid confusion To see the complete EVBU schematic refer to the M68HC11EVBU Universal Evaluation Board User s Manual Motorola document order number M68HC11EVBU D The default configuration of the EVBU must be changed to make the appropriate connections to the circuitry in the wire wrap area and to configure the master MCU for bootstrap mode A fabricated jumper must be installed at J6 to connect the XTAL output of the master MCU to the wire wrap connector P5 which has been wired to the EXTAL input of the target MCU Cut traces that short across J8 and J9 must be cut on the solder side of the printed circuit board to disconnect the normal SCI connections to the RS232 level translator U4 of the EVBU The J8 and J9 connections can be restored easily at a later time by installing fabricated jumpers on the component side of the board A fabricated AN1060 Rev 1 0 294 MOTOROLA 1060 1 0 Application Note jumper must be installed across J3 to configure the master MCU for bootstrap mode One 68 711 9 is first pro
136. CBUG11 E PORT 2 with the E9PGMR connected to COM2 PCbug11 only supports COM ports 1 and 2 If the proper connections are made and you have a high quality cable you should quickly get a EB184 324 MOTOROLA Step 3 Step 4 Step 5 Step 6 Step 7 184 Engineering Bulletin PCbug11 command prompt If you do receive Comms fault error check the cable and board connections Most PCbug11 communications problems can be traced to poorly made cables or bad board connections PCbug11 defaults to base 10 for its input parameters Change this to hexadecimal by typing CONTROL BASE HEX Clear the block protect register BPROT to allow programming of the MC68HC711E9 EEPROM At the PCbug11 command prompt type MS 1035 00 The CONFIG register defaults to hexadecimal 103F on the MC68HC711E9 PCBUG11 needs adressing parameters to allow programming of a specific block of memory so the following parameter must be given At the PCbug11 command prompt type EEPROM 0 Then type EEPROM 103F 103F Erase the CONFIG to allow byte programming At the PCbug11 command prompt type EEPROM ERASE BULK 103F You are now ready to download the program into the EEPROM and EPROM At the PCbug11command prompt type LOADSC MYPROG MYPROG S19 For more details on programming the EPROM read the engineering bulletin Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVB Motorola document number EB187 MOTOROLA
137. CF Conversion Complete Flag A read only status indicator this bit is set when all four A D result registers contain valid conversion results Each time the ADCTL register is overwritten this bit is automatically cleared to 0 anda conversion sequence is started In the continuous mode CCF is set at the end of the first conversion sequence Bit 6 Unimplemented Always reads 0 SCAN Continuous Scan Control Bit When this control bit is clear the four requested conversions are performed once to fill the four result registers When this control bit is set conversions are performed continuously with the result registers updated as data becomes available MULT Multiple Channel Single Channel Control Bit When this bit is clear the A D converter system is configured to perform four consecutive conversions on the single channel specified by the four channel select bits CD CA bits 3 0 of the ADCTL register When this bit is set the A D system is configured to perform MC68HC11E Family Rev 4 218 Analog to Digital A D Converter MOTOROLA Analog to Digital A D Converter A D Control Status Register a conversion on each of four channels where each result register corresponds to one channel NOTE When the multiple channel continuous scan mode is used extra care is needed in the design of circuitry driving the A D inputs The charge on the capacitive DAC array before the sample time is related to the vo
138. CLK PRI PRO COUNTER TAPS FOR INTERRUPT REQUESTS COP WATCHDOG AND FURTHER QUALIFIED BY PULSE ACCUMULATOR BIT IN CCR 16 BIT TIMER BUS TO PULSE ACCUMULATOR 0 1 FUNCTIONS PATIOCL TER I PA6 OC2 0 1 PA5 0C3 0 1 4 0 4 0 1 0 5 BIT 3 gt IC4 0C1 PA2 IC1 PA1 IC2 PAO IC3 16 BIT COMPARATOR 0 TOC1 TOC1 LO 16 BIT COMPARATOR TOC2 TOC2 LO 16 BIT COMPARATOR TOC3 TOC3 LO TOC4 4 LO 16 COMPARATOR N TM O5 TM OS LO 16 BIT LATCH CLK 16 BIT LATCH CLK 16 BIT LATCH CLK 16 BIT LATCH CLK TIC3 HI TIC3 LO F F 16 BIT COMPARATOR Au p zd 5 co oo TMSK 1 PORTA INTERRUPT PIN CONTROL FLAGS ENABLES Figure 9 2 Capture Compare Block Diagram MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 181 Timing System 9 4 Input Capture Technical Data The input capture function records the time an external event occurs by latching the value of the free running counter when a selected edge is detected at the associated timer input pin Software can store latched values and use them to compute the periodicity and duration of events For example by storing the times of successive edges of an incoming signal software can determine the period and pulse width of a signal To measure period two successive edges of the sam
139. CU to change operating modes Refer to the description of HPRIO register in Section 4 Operating Modes and On Chip Memory for a detailed description of SMOD and MDA The DLY control bit is set to specify that an oscillator startup delay is imposed upon recovery from stop mode The clock monitor system is disabled because CME is cleared 5 5 Reset and Interrupt Priority Resets and interrupts have a hardware priority that determines which reset or interrupt is serviced first when simultaneous requests occur Any maskable interrupt can be given priority over other maskable interrupts MC68HC11E Family Rev 4 Technical Data MOTOROLA Resets and Interrupts 117 Resets and Interrupts The first six interrupt sources are not maskable The priority arrangement for these sources is Technical Data 1 D Er oue e JM POR or RESET pin Clock monitor reset COP watchdog reset XIRQ interrupt Illegal opcode interrupt Software interrupt SWI The maskable interrupt sources have this priority arrangement 12 13 14 15 eos ume IS IRQ Real time interrupt Timer input capture 1 Timer input capture 2 Timer input capture 3 Timer output compare 1 Timer output compare 2 Timer output compare 3 Timer output compare 4 Timer input capture 4 output compare 5 Timer overflow Pulse accumulator overflow Pulse accumulator input edge SPI transfer complete SCI system refer to
140. DAB STAB STAA LDAB STAB JSR CLR 520 5103 50 521 5103 DLYI EP 103B Set EPROM latches Store data to Set ELAT bit in EPGM 0 EPRO EPGM bit with to enable M address ELAT 1 to enable Delay 2 4 ms Turn to READ mode This example applies only to MC68HC711E20 EPROG LDAB STAB STAA LDAB STAB JSR CLR MC68HC11E Family Rev 4 520 51036 50 521 51036 DLYI EP 1036 EPGM Set ELAT bit EPROM latches Store data to Set EPRO EPGM bit with ELAT EPROM programming voltage off programming voltage and set 0 to enable M address 1 to enable Delay 2 4 ms Turn to READ mode EPROM programming voltage off programming voltage and set Technical Data MOTOROLA Operating Modes and On Chip Memory 93 Operating Modes Memory 4 5 2 Programming the EPROM with Downloaded Data When using this method the EPROM is programmed by software while in the special test or bootstrap modes User developed software can be uploaded through the SCI or a ROM resident EPROM programming utility can be used The 12 volt nominal programming voltage must be present on the XIRQ Vppg pin To use the resident utility bootload a 3 byte program consisting of a single jump instruction to BF00 BF00 is the starting address of a resident EPROM programming u
141. DC DD Pulse accumulator overflow FFDE DF Timer overflow TOI FFEO E1 Timer input capture 4 output compare 5 14 051 FFE2 E3 Timer output compare 4 OCAI FFE4 E5 Timer output compare 3 FFE6 7 output compare 2 OC2l FFE8 E9 Timer output compare 1 input capture 3 IC3I FFEC ED Timer input capture 2 2 FFEE EF Timer input capture 1 IC1I FFF0 F1 Real time interrupt RTII FFF2 F3 external pin FFF4 F5 XIRQ pin X None FFF6 F7 Software interrupt None None FFF8 F9 Illegal opcode trap None None FFFA FB COP failure None NOCOP FFFC FD Clock monitor fail None CME FFFE FF RESET None None MC68HC11E Family Rev 4 Technical Data MOTOROLA Resets and Interrupts 121 Resets and Interrupts For some interrupt sources such as the SCI interrupts the flags are automatically cleared during the normal course of responding to the interrupt requests For example the RDRF flag in the SCI system is cleared by the automatic clearing mechanism consisting of a read of the SCI status register while RDRF is set followed by a read of the SCI data register The normal response to an RDRF interrupt request would be to read the SCI status register to check for receive errors then to read the received data from the SCI data register These steps satisfy the automatic clearing mechanism without requiring special instructions 5 6 1 Interrupt Re
142. E 215 is tapped off of the free running counter chain The COP automatically times out unless it is serviced within a specific time by a program reset sequence If the COP is allowed to time out a reset is generated which drives the RESET pin low to reset the MCU and the external system Refer to Table 9 1 for crystal related frequencies and periods OSCILLATOR AND AS CLOCK GENERATOR DIVIDE BY FOUR E CLOCK INTERNAL BUS CLOCK PH2 PRESCALER 7 2 4 16 32 SPI SPR L 0 PRESCALER PRESCALER 134 13 1 2 4 128 SCI RECEIVER CLOCK SCP 1 0 SCR 2 0 SCI TRANSMIT CLOCK PULSE ACCUMULATOR PRESCALER 213 1 2 4 8 REAL TIME INTERRUPT RTR 1 0 PRESCALER 1 4 8 16 PR 1 0 TOF TCNT PRESCALER 1 4 16 64 CR 1 0 FORCE gp COP RESET IC OC CONI NIE EPOD E CLEAR COP SYSTEM SCP2 present on MC68HC 7 11E20 only TIMER RESET Figure 9 1 Timer Clock Divider Chains MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 179 Timing System Table 9 1 Timer Summary XTAL Frequencies 4 0 MHz 8 0 MHz 12 0 MHz Other Rates Control Bits 1 0 MHz 2 0 MHz 3 0 MHz E PR1 PRO 1000 ns 500 ns 333 ns 1 E Main Timer Count Rates 00 1 count 1000 ns 500 ns 333 ns E 1 overflow 65 536 ms 32 768 ms 21 845 ms 216 01 1 count 4 0 us 2 0 us 1 333 us E 4 overflow 262 14 ms 131 07 ms 87 381 ms 218 10
143. E NOTE MOSI INPUT MSBIN Gel BIT6 1 LSB IN Note Not defined but normally MSB of character just received A SPI Slave Timing CPHA 0 gt 1 4 10 lt 4 gt Q gt MISO md X stave msBout X BiT6 1 SLAVE LSB OUT o MOSI MSBIN BT6 1 LSB IN Note Not defined but normally LSB of character previously transmitted B SPI Slave Timing CPHA 1 Figure 11 15 SPI Timing Diagram Sheet 2 of 2 MC68HC11E Family Rev 4 Technical Data MOTOROLA Electrical Characteristics 249 Electrical Characteristics 11 20 EEPROM Characteristics 1 Temperature Range TM Characteristic ni 40 to 85 C 40 to 105 C 40 to 125 C Programming time 1 0 MHz RCO enabled 10 15 20 iE 1 0 to 2 0 MHz RCO disabled 20 Must use RCO Must use RCO 2 2 0 MHz or anytime RCO enabled 10 15 20 ima 2 Erase time 2 10 10 10 na Byte row and bulk Write erase endurance 10 000 10 000 10 000 Cycles Data retention 10 10 10 Years 1 Vpp 5 0 410 Vss 0 Vdc TA T to Tu 2 The RC oscillator RCO must be enabled by setting the CSEL bit in the OPTION register for EEPROM programming and erasure when the E clock frequency is below 1 0 MHz 11 21 MC68L11E9 E20 EEPROM Characteristics Temperature Range
144. EEON Resets Single chip 1 1 1 1 0 0 1 1 Bootstrap 1 1 1 1 U U L 1 1 Expanded U U U U 1 U 1 U Test U U U U 1 U L 1 0 Unimplemented U indicates a previously programmed bit U L indicates that the bit resets to the logic level held in the latch prior to reset but the function of COP is controlled by the DISR bitin TEST1 register Figure 4 11 MC68HC811E2 System Configuration Register CONFIG MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 87 Operating Modes Memory EE 3 0 EEPROM Mapping Bits EE 3 0 apply only to MC68HC811E2 and allow the 2048 bytes of EEPROM to be remapped to any 4 Kbyte boundary See Table 4 3 Table 4 3 EEPROM Mapping EE 3 0 EEPROM Location 0000 0800 0FFF 0001 1800 1FFF 0010 2800 2FFF 0011 3800 3FFF 0100 4800 4FFF 0101 5800 5FFF 0110 6800 6FFF 0111 7800 7FFF 1000 8800 8FFF 1001 9800 9FFF 1010 A800 AFFF 1011 B800 BFFF 1100 C800 CFFF 1101 D800 DFFF 1110 E800 EFFF 1111 F800 FFFF NOSEC Security Disable Bit NOSEC is invalid unless the security mask option is specified before the MCU is manufactured If the security mask option is omitted NOSEC always reads 1 The enhanced security feature is available in the MC68S711E9 MCU The enhancement to the standard security feature protects the EPROM as well as RAM and EEP
145. EY PRESSED THEN ABORT 8010 WEND 8020 BS INPUTS 1 2 8030 RETURN 8490 Xo xk ok kk ok kk K AE A Ck ke k ko kk 8491 DECIMAL TO HEX CONVERSION 8492 INPUT INTEGER TO BE CONVERTED 8493 OUTPUT 5 TWO CHARACTER STRING WITH HEX CONVERSION 8494 f ck ck ck kk Ck kk Ck KC CI CK CK CI CC KC Ck KC Sk CC CC SCC SCC SCC Ck Sk kk Sk Sk S Kk ko ko 8500 IF K gt 255 THEN 5 big GOTO 8530 8510 HXS MIDS HS 16 1 1 UPPER NIBBLE 8520 HXS HXS MIDS HS MOD 16 1 1 LOWER NIBBLE 8530 RETURN 9499 CODE CK CK Ck Ck Ck Ck KKK k k Ck KKK k k lt k k k x k lt KKK k k x x lt x 9500 DATA 86 23 LDAA 523 9510 7 10 02 STAA OPT2 make port C wire or 9520 DATA 86 FE LDAA SFE 9530 DATA B7 10 03 STAA PORTC light 1 LED on port C bit O0 9540 DATA C6 FF LDAB SFF 9550 DATA F7 10 07 STAB DDRC make port C outputs 9560 DATA CE OF AO LDX 4000 2msec at 2MHz 9570 DATA 18 CE EO 00 58000 Start of BUFFALO 3 4 9580 DATA 7E BF 00 JMP SBFOO EPROM routine start address 9590 DKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK KKK KKK Bootstrap Mode Problems It is not unusual for a user to encounter problems with bootstrap mo
146. Erase Mode Select Bit 0 Normal read or program mode 1 Erase mode EELAT EEPROM Latch Control Bit 0 EEPROM address and data bus configured for normal reads and cannot be programmed 1 address and data bus configured for programming or erasing and cannot be read EPGM EPROM OTPROM EEPROM Programming Voltage Enable Bit 0 Programming voltage to EEPROM array switched off 1 Programming voltage to EEPROM array switched on During EEPROM programming the ROW and BYTE bits of PPROG are not used If the frequency of the E clock is 1 MHz or less setthe CSEL bit in the OPTION register Recall that 0s must be erased by a separate erase operation before programmino The following examples of how to program an EEPROM byte assume that the appropriate bits in BPROT are cleared PROG LDAB 502 EELAT 1 STAB 103B Set EELAT bit STAA SXXXX Store data to EEPROM address for valid EEPROM address see memory map for each device LDAB 503 EELAT 1 EPGM 1 5 103B Turn on programming voltage JSR DLY10 Delay 10 ms CLR 103B Turn off high voltage and set to READ mode Technical Data MC68HC11E Family Rev 4 102 Operating Modes and On Chip Memory MOTOROLA 4 6 1 3 EEPROM Bulk Erase Operating Modes and On Chip Memory EEPROM This is an example of how to bulk erase the entire EEPROM The CONFIG register is not affected in this example BU
147. F1 9 00 0000 3FF 6 7 0 es MC68HC11K4 30 0 ROM 1 0 044B 0D80 0080 37F MC68HC711K4 42 B 0000 744B 0D80 0080 37F Yes 1 By sending 00 or a break as the first SCI character after reset in bootstrap mode a jump JMP is executed to the address in this table rather than doing a download Unless otherwise noted this address is the start of EEPROM Tying RxD to TxD and using a pullup resistor from TxD to Vpp will cause the SCI to see a break as the first received character 2 If 55 is received as the first character after reset in bootstrap mode a jump JMP is executed to the start of on chip RAM rather than doing a download This 55 character must be sent at the default baud rate 7812 baud E 2 MHz For devices with variable length download the same effect can be achieved by sending FF and no other SCI characters After four SCI character times the download terminates and a jump JMP to the start of RAM is executed The jump to RAM feature is only useful if the RAM was previously loaded with a meaningful program Acallable utility subroutine is included in the bootstrap ROM of the indicated versions to program bytes of on chip EPROM with data received via the SCI A callable utility subroutine is included in the bootstrap ROM of the indicated versions to upload contents of on chip memory to a host computer via the SCI The complete listing for this bootstrap ROM may be found in the M68HC11
148. FF 1100 C000 CO3F 1101 D000 DxFF 1101 D000 DO3F 1110 E000 ExFF 1110 E000 EO3F 1111 F000 FxFF 1111 F000 FO3F Technical Data MC68HC11E Family Rev 4 90 Operating Modes and On Chip Memory MOTOROLA Operating Modes Memory Memory Map 4 4 3 3 System Configuration Options Register The 8 bit special purpose system configuration options register OPTION sets internal system configuration options during initialization The time protected control bits IRQE DLY CR 1 0 can be written only once after a reset and then they become read only This minimizes the possibility of any accidental changes to the system configuration Address 1039 Bit 7 6 5 4 3 2 1 Bit 0 Read 1 1 1 1 ADPU CSEL IRQEU py CME CR1 CRO Write Reset 0 0 0 1 0 0 0 0 1 Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes Unimplemented Figure 4 13 System Configuration Options Register OPTION ADPU Analog to Digital Converter Power Up Bit Refer to Section 10 Analog to Digital A D Converter CSEL Clock Select Bit Selects alternate clock source for on chip EEPROM charge pump Refer to 4 6 1 EEPROM and CONFIG Programming and Erasure for more information on EEPROM use CSEL also selects the clock source for the A D converter a function discussed in Section 10 Analog to Digital A D Converter IRQE
149. FFF At the maximum count the counter rolls over to 90000 sets an overflow flag and continues to increment As long as the MCU is running in a normal operating mode there is no way to reset change or interrupt the counting The capture compare subsystem features three input capture channels four output compare channels and one channel that can be selected to perform either input capture or output compare Each of the three input capture functions has its own 16 bit input capture register time capture latch and each of the output compare functions has its own 16 bit compare register All timer functions including the timer overflow and RTI have their own interrupt controls and separate interrupt vectors The pulse accumulator contains an 8 bit counter and edge select logic The pulse accumulator can operate in either event counting mode or gated time accumulation mode During event counting mode the pulse accumulator s 8 bit counter increments when a specified edge is detected on an input signal During gated time accumulation mode an internal clock source increments the 8 bit counter while an input signal has a predetermined logic level The real time interrupt RTI is a programmable periodic interrupt circuit that permits pacing the execution of software routines by selecting one of four interrupt rates MC68HC11E Family Rev 4 178 Timing System MOTOROLA Timing System Introduction The COP watchdog clock input
150. I transmitter has two status flags These status flags be read by software polled to tell when the corresponding condition exists Alternatively a local interrupt enable bit can be set to enable each of these status conditions to generate interrupt requests when the corresponding condition is present Status flags are automatically set by hardware logic conditions but must be cleared by software which provides an interlock mechanism that enables logic to know when Technical Data MC68HC11E Family Rev 4 160 Serial Communications Interface SCI MOTOROLA Serial Communications Interface SCI Status Flags and Interrupts EXTAL El OSCILLATOR INTERNAL BUS CLOCK PH2 CLOCK GENERATOR gt gt lt 4 XTAL 23 4 218 239 E SCP 2 0 z AS 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 9 e SCR 2 0 0 0 0 XXE XX N H gt 16 1 0 0 SCI E3 TRANSMIT 2 1 0 1 BAUD RATE 1X ES D 1 1 0 ES 1 1 1 SCI RECEIVE ES gt BAUD RATE 16X SCP2 is present only on MC68HC 7 11E20 Figure 7 9 MC68HC 7 11E20 SCI Baud Rate Generator Block Diagram software has noticed the status indicati
151. KK T S SO SS Ax Su X X 6492 SUBROUTINE TO SEND THE STRING 6 OUT TO THE DEVICE 6494 OPENED AS FILE 2 6496 KK KK KK KKK Ck Ck C KKK CC KKK KKK CC KKK KKK KKK KKK KKK KK KKK S S x S Sk Sk Sk kA Ax Su X X 6500 PRINT 2 AS 6510 RETURN 6590 DKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK KKK 6594 SUBROUTINE THAT CONVERTS THE DIGIT AS INTEGER 6596 ee ee ee eee ee ee ee ee K K k ee ee 7000 X INSTR HS AS 7010 IF X 0 THEN FLAG 1 7020 X X 1 7030 RETURN X Gl AN1060 Rev 1 0 310 MOTOROLA Application Note 7990 JOCkck ck ck kk ck kk Ck xxx xxx xxx xxx xx xxx xx xxx xxx xxx xxx xxx I xx xxx xxx ko ko ko UE SUBROUTINE TO READ IN ONE BYTE THROUGH THE COMM PORT OPENED 7994 AS FILE 2 WAITS INDEFINITELY FOR THE BYTE TO BE 49 96 7x RECEIVED SUBROUTINE WILL BE ABORTED BY ANY 7998 KEYBOARD INPUT RETURNS BYTE IN BS USES QS 7999 XX kk kk ok IR I IR IR IR IR IR IR IR I ck K K k 8000 WHILE LOC 2 0 WAIT FOR COMM PORT INPUT 8005 QS INKEYS IF QS lt gt THEN 4900 IF ANY K
152. KKK KKK KKK KKK KKK KKK CK CC Ck Ck C CK Ck Ck Ck Ck Sk Sk S S Kk Pk ko Sk A kx kx X X 25 H 0123456789ABCDEF STRING TO USE FOR HEX CONVERSIONS 30 DEFINT B I CODESIZE S 8192 ADRSTART 57344 35 BOOTCOUNT 25 NUMBER OF BYTES IN BOOT CODE 40 DIM CODE CODESIZES BUFFALO 3 4 IS 8K BYTES LONG 45 BOOTCODES INITIALIZE BOOTCODES TO NUL 49 REM READ IN AND SAVE THE CODE TO BE BOOT LOADED 50 FOR I 1 TO BOOTCOUNT OF BYTES IN BOOT CODE 55 READ 0 60 AS 5 05 1 1 65 GOSUB 7000 CONVERTS HEX DIGIT TO DECIMAL 70 TEMP 16 X HANG ON TO UPPER DIGIT 75 AS 5 05 2 1 80 GOSUB 7000 85 TEMP TEMP X 90 BOOTCODES BOOTCODES CHRS TEMP BUILD BOOT CODE 95 NEXT I 96 REM S RECORD CONVERSION STARTS HERE 97 FILNAMS BUF34 S19 DEFAULT FILE NAME FOR S RECORDS 100 CLS 105 PRINT Filename ext of S record file to be downloaded FILNAMS 107 INPUT Q 110 IF Q THEN FILNAMS Q 120 OPEN FILNAMS FOR INPUT AS 1 130 PRINT PRINT Converting FILNAMS to binary 999 REM SCANS FOR 51 RECORDS 1000 GOSUB 6000 GET 1 CHARACTER FROM INPUT FILE 1010 IF FLAG THEN 1250 FLAG IS EOF FLAG FROM SUBROUTINE 1020 IF AS lt gt S THEN 1000 1022 GOSUB 6000 1024 IF AS lt gt 1 THEN 1000 1029 REM Sl RECORD FOUND NEXT 2 HEX DIGITS ARE THE BYTE COUNT 1030 GOSUB 6000 1040 GOSUB 7000 RETURNS DECIMAL IN X
153. LAT 1 for EEPROM programming 0 Programming voltage to EPROM OTPROM EEPROM array disconnected 1 Programming voltage to EPROM OTPROM EEPROM array connected Address 1036 Bit7 6 5 4 3 2 1 Bit 0 Read MBE ELAT EXCOL EXROW T1 TO PGM Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 4 15 MC68HC711E20 EPROM Programming Control Register EPROG MBE Multiple Byte Programming Enable Bit When multiple byte programming is enabled address bit 5 is considered a don t care so that bytes with address bit 5 0 and address bit 5 2 1 both get programmed MBE can be read in any mode and always reads 0 in normal modes MBE can be written only in special modes 0 EPROM array configured for normal programming 1 Program two bytes with the same data Bit 6 Unimplemented Always reads 0 Technical Data MC68HC11E Family Rev 4 96 Operating Modes and On Chip Memory MOTOROLA Operating Modes Memory EPROM OTPROM ELAT EPROM OTPROM Latch Control Bit When ELAT 1 writes to EPROM cause address and data to be latched and the EPROM OTPROM cannot be read ELAT can be read any time ELAT can be written any time except when PGM 1 then the write to ELAT is disabled 0 EPROM OTPROM address and data bus configured for normal reads 1 EPROM OTPROM address and data bus configured for programming EXCOL Select Extra Columns Bit 0 User array selected 1
154. LEAD TRIM OFFSET AND LEAD FINISH INCHES MILLIMETERS DIM MIN MAX MIN A 0 785 0 795 19 94 20 19 B 0785 0795 1994 2019 C 0 165 0 200 420 5 08 D 0017 0021 0 44 0 53 0 026 0 032 0 67 0 81 G 0 050 BSC 1 27 BSC 0 090 0 130 2 29 3 30 J 0 006 0 010 0 16 0 25 0 035 0 045 0 89 114 N 0735 0 756 1867 1920 R 0735 0756 18 67 19 20 S 0 690 0730 1753 1854 Technical Data MOTOROLA Mechanical Data 255 Mechanical Data 12 5 64 Pin Quad Flat Pack Case 840C DO DO 02010 0080 H aB D o20 009 9 c i 020 0 008 p SECTION 102010 008 090 DO NOTES DIMENSIONING AND TOLERANCING PER ANSI _ 10 05 0 002 Y14 5M 1982 2 CONTROLLING DIMENSION MILLIMETER 3 DATUM PLANE H IS LOCATED AT BOTTOM OF lt s gt LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT 6 20 0 008 c as p HE BOTTOM OF THE PARTING LINE ATUMS A 8 AND D TO BE DETERMINED AT ATUM PLANE H MENSIONS S AND V TO BE DETERMINED AT EATING PLANE C MENSIONS A AND B DO NOT INCLUDE MOLD ROTRUSION ALLOWABLE PROTRUSION IS 0 25 0 010 PER SIDE DIMENSIONS A AND B DO NCLUDE MOLD MISMATCH AND ARE ETERMINED AT DA
155. LKE P LDAB STAB STAA LDAB STAB JSR CLR 506 5103 SXXXX 507 5103 DLY10 5103 EELAT 1 ERASE 1 Set to BULK erase mode valid for eac EELAT Turn on hig Store data to any EEPROM address see memory map EEPROM address for h device 1 EPGM Delay 10 ms ERASE 1 1 h voltage Turn off high voltage and set Lo READ mode 4 6 1 4 EEPROM Row Erase This example shows how to perform a fast erase of large sections of EEPROM ROWE LDAB SOE ROW 1 ERASE 1 EELAT 1 STAB 103B Set to ROW erase mode STAB 0 Write any to any address ROW LDAB OF ROW 1 ERASE 1 EELAT 1 FPGM 1 STAB 103B Turn on high voltage JSR DLY10 Delay 10 ms CLR 103B Turn off high voltage and set to READ mode MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 103 Operating Modes Memory 4 6 1 5 EEPROM Byte Erase This is an example of how to erase a single byte of EEPROM BYTEF LDAB S16 BYTE 1 ERASE 1 EELAT 1 STAB S103B Set to BYTE erase mode STAB 0 Write to address to erased LDAB 17 BYTE 1 ERASE 1 EELAT 1 EPGM 1 STAB 103B Turn
156. MOTOROLA MC68HC11E Family Rev 4 Electrical Characteristics MC68L11E9 E20 Peripheral Port Timing Pd ie YY YN PORT C OUT XA READY STRB OUT thes STRA IN Comm a STRA ACTIVE BEFORE PORTCL WRITE PORT C OUT DD STRA IN N NEW DATA VALID PORT C OUT DD b STRA ACTIVE AFTER PORTCL WRITE Notes 1 After reading PIOC with STAF set 2 Figure shows rising edge STRA EGA 1 and high true STRB INVB 1 Figure 11 13 3 State Variation of Output Handshake Timing Diagram STRA Enables Output Buffer Technical Data MOTOROLA Electrical Characteristics 239 Electrical Characteristics 11 14 Analog to Digital Converter Characteristics 2 0 MHz 3 0 MHz Characteristic Parameter Min Absolute Unit Max Max Resolution Number of bits resolved by A D converter 8 Bits Non linearity Maximum deviation from the ideal A D E 1 2 1 LSB transfer characteristics Faro erior Difference between the output of an ideal and E 1 2 1 LSB an actual for 0 input voltage Eli sese ener Difference between the output of an ideal and E ET 44 2 1 LSB an actual A D for full scale input voltage Total unadjusted Maximum sum of non linearity zero error and 44 2 1 2 LSB error full scale error 2 Uncertainty because of converter resolut
157. N MAX DETAIL X 2415 2445 6134 62 10 B 0540 0560 1372 1422 C 0155 0200 394 5 08 D 0014 0 022 036 055 F 0040 0 060 10 152 G 010085 2 54 BSC H 0 070BSC 1 79 BSC see oe eee J 0008 0 015 020 038 lY 0115 0 150 292 381 T L 0 60085 15 24 BSC 1 Ox 15x 0 15 SEAUNG z PL N 0020 0 040 051 101 DETAIL X N F G J 4 D 32 PL 0 25 0 010 T B 0 51 0 020 T MC68HC11E Family Rev 4 Technical Data MOTOROLA Mechanical Data 259 Mechanical Data Technical Data MC68HC11E Family Rev 4 260 Mechanical Data MOTOROLA Technical Data M68HC11E Family Section 13 Ordering Information 13 1 Contents Te IMNOOUDOEDNLLA 222232255 261 13 3 Standard Device Ordering Information 262 13 4 Custom ROM Device Ordering Information 265 13 5 Extended Voltage Device Ordering Information 9 0 Vde to 5 5 Vde L wawa 267 13 2 Introduction This section provides ordering information for the E series devices Information is grouped by e Standard devices e Custom ROM devices Extended voltage devices MC68HC11E Family Rev 4 Technical Data MOTOROLA Ordering Information 261 Ordering Information 13 3 Standard Device Ordering Information
158. NY CPY RAMEND 1 BNE WAIT signal ready for download of BAUD resets count chain Initialize stack pntr Point at internal regs Select port D wire OR mode BAUD in A SCCR2 in B SCPx 4 SCRx 4 Rx and Tx Enabled Delay for fast baud rate Set as default delay Set send break bit Wait for RxD pin to go low Clear send break bit Wait for RDRF Read data 00 received Bypass JMP if not 0 Jump to EEPROM if it was 0 SFF will be seen as SFF If baud was correct 8 1200 8 2MHZ Works because 22 gt 33 And switch to slower delay constant Point at start of RAM Move delay constant to D SCSR X 20 NEWONE Exit loop if RDRF set Swap delay count to X Decrement count Swap back to D Loop if not timed out Quit download on timeout Get received data Store to next RAM location Transmit it for handshake Point at next RAM location See if past end If not Get another AN1060 Rev 1 0 320 MOTOROLA 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 Application Note
159. O Ports 139 Parallel Input Output I O Ports Full handshake modes use port C pins and the STRA and STRB lines Input and output handshake modes are supported and output handshake mode has a 3 stated variation STRA is an edge detecting input and STRB is a handshake output Control and enable bits are located in the PIOC register In full input handshake mode the MCU asserts STRB to signal an external system that it is ready to latch data Port C logic levels are latched into PORTCL when the STRA line is asserted by the external system The MCU then negates STRB The MCU reasserts STRB after the PORTCL register is read In this mode a mix of latched inputs static inputs and static outputs is allowed on port C differentiated by the data direction bits and use of the PORTC and PORTCL registers In full output handshake mode the MCU writes data to PORTCL which in turn asserts the STRB output to indicate that data is ready The external system reads port C data and asserts the STRA input to acknowledge that data has been received In the 3 state variation of output handshake mode lines intended as 3 state handshake outputs are configured as inputs by clearing the corresponding DDRC bits The MCU writes data to PORTCL and asserts STRB The external system responds by activating the STRA input which forces the MCU to drive the data in PORTC out on all of the port C lines After the trailing edge of the active signal on STRA the MCU neg
160. O ADDR8 41 PBI ADDR9 M68HC11 E SERIES 40 PB2 ADDR10 39 PB3 ADDR 11 38 PB4 ADDR 12 37 PB5 ADDR 13 36 PB6 ADDR 14 35 PB7 ADDR 15 34 PCO ADDRO DATAO 9 PC1 ADDR1 DATA1 1 PC2 ADDR2 DATA2 PC3 ADDR3 DATA3 PC4 ADDR4 DATA4 PC5 ADDR5 DATAS PC6 ADDR6 DATA6 PC7 ADDR7 DATAT PPP A m PDO RxD 20 27 31 PD1 T gt D PD2 MISO PD3MOSI PA7 PAI OC1 PA6G OC2 OC1 PAS OC3 OC1 PAA OCA OC1 PA3OCBSACA OC1 2 1 PAINC2 Vppe applies only to devices with EPROM OTPROM Figure 2 1 Pin Assignments for 52 Pin PLCC and CLCC MC68HC11E Family Rev 4 28 Pin Descriptions MOTOROLA MC68HC11E Family Rev 4 PB7 ADDR15 PB6 ADDR14 PB5 ADDR13 PB4 ADDR12 cx PB3 ADDR11 PB2 ADDR10 c Pin Descriptions Introduction PAYOCSACA OC1 NC NC PA4 OC4 OC1 PAS OC3 OC1 I1 PAG OC2 OC1 MO PA14AC2 1 2 1 HO PA7 PAI OC1 PDA SCK I PDS MOSI HO PD2 MISO 1 PD1 TxD 64 62 59 56 53 52 51 n PC7 ADDR7 DATA7 PC6 ADDR6 DATA6 H PC5 ADDR5 DATAS H PC4 ADDR4 DATA4 I Oa n gt M68HC11E SERIES PBI ADDR9 cd P C3 ADDR3 DATA3 PBO ADDR8 cad H P C2 ADDR2 DATA2 PEO ANO p PCI ADDRI DATAT PE4 AN4 c HNC PE1 AN1 cu PCO ADDRO DATAO PE5 AN5 cad XTAL 17 19 20 19652240 53 Q ul 29
161. ODE 1 SEND SECOND BYTE TO GET ONE IN QUEUE 1635 GOSUB 6500 SEND 1640 GOSUB 8000 BYTE FOR VERIFICATION 1650 RCV I 1 1660 LOCATE 10 1 PRINT Verifying byte I 1664 IF CHRS CODES RCV B THEN 1670 1665 K CODE RCV GOSUB 8500 1666 LOCATE 1 1 PRINT Byte 4 I Sent HX 1668 K ASC B GOSUB 8500 1669 PRINT Received HX 1670 NEXT I 1680 GOSUB 8000 GET BYTE FOR VERIFICATION 1690 RCV CODESIZES 1 1700 LOCATE 10 1 PRINT Verifying byte CODESIZE 1710 IF CHR CODE RCV BS THEN 1720 1713 K CODE RCV GOSUB 8500 1714 LOCATE 1 1 PRINT Byte CODESIZE Sent HX 1715 K ASC B GOSUB 8500 1716 PRINT Received 5 1720 LOCATE 8 1 PRINT PRINT Done I 4900 CLOSE 4910 INPUT Press RETURN to quit QS 5000 END 5900 DKK ck ck ck ck ck Ck Ck Ck CI C KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK SU ko Sk ko Ax kx X X JILL 5e SUBROUTINE TO READ IN ONE BYTE FROM A DISK FILE 5930 7 RETURNS BYTE 5 5940 KKK ck Ck Ck Ck CI CI KK KEK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK SASA Ck Pk Sk Sk kA Su X X 6000 FLAG 0 6010 IF 1 THEN FLAG 1 RETURN 6020 AS INPUTS 1 1 6030 RETURN 6490 KKK KKK C Ck Ck KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK Ck Ck KKK K
162. OM is sent starting with the character for location 90000 After the last byte to be programmed is sent to the MC68HC711E9 and the corresponding verification data is returned to the host the programming operation is terminated by resetting the MCU The number of bytes to be programmed the first address to be programmed and the programming time can be controlled by the user if values other than the default values are desired MOTOROLA 289 Application Note To understand the detailed operation ofthe EPROM programming utility refer to Figure 4 during the following discussion Figure 4 is composed of three interrelated parts The upper left portion shows the flowchart of the PROGRAM utility running in the boot ROM of the MCU The upper right portion shows the flowchart for the user supplied driver program running in the host computer The lower portion of Figure 4 is a timing sequence showing the relationship of operations between the MCU and the host computer Reference numbers in the flowcharts in the upper half of Figure 4 have matching numbers in the lower half to help the reader relate the three parts of the figure The shaded area 1 refers to the software and hardware latency in the MCU leading to the transmission of a character in this case the FF The shaded area 2 refers to a similar latency in the host computer in this case leading to the transmission of the first data character to the MCU The overall operation
163. OTOROLA 6 7 Port E Parallel Input Output I O Ports Port E Port E is used for general purpose static inputs or pins that share functions with the analog to digital A D converter system When some port E pins are being used for general purpose input and others are being used as A D inputs PORTE should not be read during the sample portion of an A D conversion Address 100 Bit 7 6 5 4 3 2 1 Bit 0 Read PE7 PE6 PE5 PE4 PE3 PE2 PE1 0 Write Reset Indeterminate after reset Alternate Function AN7 AN6 AN5 AN4 AN3 AN2 AN1 ANO Figure 6 9 Port E Data Register PORTE 6 8 Handshake Protocol Simple and full handshake input and output functions are available on ports B and C pins in single chip mode In simple strobed mode port B is a strobed output port and port C is a latching input port The two activities are available simultaneously The STRB output is pulsed for two E clock periods each time there is a write to the PORTB register The INVB bit in the PIOC register controls the polarity of STRB pulses Port C levels are latched into the alternate port C latch PORTCL register on each assertion of the STRA input STRA edge select flag and interrupt enable bits are located in the register Any or all of the port C lines can still be used as general purpose while in strobed input mode MC68HC11E Family Rev 4 Technical Data MOTOROLA Parallel Input Output I
164. REQUEST Figure 7 10 Interrupt Source Resolution Within SCI MC68HC11E Family Rev 4 Technical Data MOTOROLA Serial Communications Interface SCI 163 Serial Communications Interface SCI Technical Data MC68HC11E Family Rev 4 164 Serial Communications Interface SCI MOTOROLA Technical Data M68HC11E Family Section 8 Serial Peripheral Interface 8 1 Contents 8 2 8 3 8 4 8 5 8 6 8 6 1 8 6 2 8 6 3 8 6 4 8 7 8 8 8 8 1 8 8 2 8 8 3 MC68HC11E Family Rev 4 are es er ee 166 Functional Description 166 sc cceneuweceneedetisrcaeaunsicnd 168 Clock Phase and Polarity Controls 169 SPI NS PPS Sa a 169 Master WU ia uu ua a pasa 170 Master Out Slavel n 170 sio ceo PP 170 annua SB 55555 UR OR DER E a ede ed OR ees 170 SPI SUNG EINE tc oped dah edhe hd ay ee bol asua qaw 171 OF TIO uasa xdi d asc ede he aoo OE old a ee 172 Serial Peripheral Control Register 173 Serial Peripheral Status Register 175 Serial Peripheral Data I O Register 176 Technical Data MOTOROLA Serial Peripheral Interface SPI 165 Serial Peripheral Interface SPI 8 2 Introduction The serial peripheral interface SPI an independent serial communications subsyst
165. ROM 0 Security enabled 1 Security disabled NOCOP COP System Disable Bit Refer to Section 5 Resets and Interrupts 1 COP disabled 0 COP enabled Technical Data MC68HC11E Family Rev 4 88 Operating Modes and On Chip Memory MOTOROLA Operating Modes Memory Memory Map ROMON ROM EPROM OTPROM Enable Bit When this bit is 0 the ROM or EPROM is disabled and that memory space becomes externally addressed In single chip mode ROMON is forced to 1 to enable ROM EPROM regardless of the state of the ROMON bit 0 ROM disabled from the memory map 1 ROM present in the memory map EEON EEPROM Enable Bit When this bit is 0 the EEPROM is disabled and that memory space becomes externally addressed 0 EEPROM removed from the memory map 1 EEPROM present in the memory map 4 4 3 2 RAM and I O Mapping Register The internal registers used to control the operation of the MCU can be relocated on 4 Kbyte boundaries within the memory space with the use of the RAM and I O mapping register INIT This 8 bit special purpose register can change the default locations of the RAM and control registers within the MCU memory map It can be written only once within the first 64 E clock cycles after a reset in normal modes and then it becomes a read only register Address 1030 Bit 7 6 5 4 3 2 1 Bit O Read RAM3 RAM2 RAM1 RAMO REG3 REG2 REG1 REGO Write Res
166. RST ADDRESS 9 WAIT1 ANY DATA RECEIVED YES PROGRAM BYTE BF00 PROGRAM 8 INDICATES READY TO HOST 10 13 READ PROGRAMMED DATA AND SEND TO VERIFY POINT TO NEXT LOCATION TO BE PROGRAMMED 11 14 PROGRAM CONTINUES AS LONG AS DATA IS RECEIVED L PROGRAM Utility in MCU VERIFY DATA TO HOST SAME AS MCU Tx DATA E stt MCU RECEIVE DATA FROM HOST EPROM PROGRAMMING 8 MCU TRANSMIT DATA VERIFY Application Driver Program in HOST 4 HOST NORMALLY WAITS FOR FF FROM MCU BEFORE SENDING DATA FOR EPROM PROGRAMMING 3 SEND FIRST DATA BYTE DATA_LOOP MORE DATA TO SEND INDICATE ERROR MORE TO VERIFY Note B 8 LR NO oi DATA FOR MCU EPROM MC68HC711E9 EXECUTING Figure 4 Host and MCU Activity during EPROM PROGRAM Utility AN1060 Rev 1 0 HOST SENDING PROGRAM LOOP MOTOROLA 291 Application Note Allowing for Bootstrap Mode Mode Select Pins RESET RxD Pin Since bootstrap mode requires few connections to the MCU it is easy to design systems that accommodate bootstrap mode Bootstrap mode is useful for diagnosing or repairing systems that have failed due to changes in the CONFIG register or failures of the expansion address data buses rendering programs in external memory useless Bootstrap mode can also be used to
167. Reference Manual Motorola document order number M68HC1 1RM AD The complete listing for this bootstrap ROM is available in the freeware area of the Motorola Web site Due to the extra program space needed for EEPROM security on this device there are no pseudo vectors for SCI SPI PAIF PAOVF TOF OC5F or interrupts 8 This bootloader extends the automatic software detection of baud rates to include 9600 baud at 2 MHz E clock rate MC68HC11D3 00 ROM I D 11D3 0 192 F000 ROM MC68HC711D3 42 0000 71D3 0 192 F000 EPROM O 91oN Application Note Original M68HC11 Versions Required Exactly 256 Bytes to be Downloaded to RAM Variable Length Download EPROM OTP Versions of M68HC11 Have an EPROM Emulation Mode Even users that know about the 256 bytes of download data sometimes forget the initial FF that makes the total number of bytes required for the entire download operation equal to 256 1 or 257 bytes When on chip RAM surpassed 256 bytes the time required to serially load this many characters became more significant The variable length download feature allows shorter programs to be loaded without sacrificing compatibility with earlier fixed length download versions of the bootloader The end of a download is indicated by an idle RxD line for at least four character times If a personal computer is being used to send the download data to the MCU there can be proble
168. SP EXECUTED UPON RETURN FROM SUBROUTINE RTNy MOST SIGNIFICANT BYTE OF RETURN ADDRESS LEAST SIGNIFICANT BYTE OF RETURN ADDRESS RTS RETURN FROM C STACK POINTER POSITION AFTER OPERATION IS COMPLETE SUBROUTINE dd 8 BIT DIRECT ADDRESS 0000 00FF HIGH BYTE ASSUMED TACK TO BE 00 MAIN PROGRAM ff 8 BIT POSITIVE OFFSET 00 0 TO FF 255 IS ADDED TO INDEX PC 39 RTS SP hh HIGH ORDER BYTE OF 16 BIT EXTENDED ADDRESS SP41 RTNy LOW ORDER BYTE OF 16 BIT EXTENDED ADDRESS c Sp42 RTN rr SIGNED RELATIVE OFFSET 80 128 TO 7F 4127 OFFSET L RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE OFFSET BYTE MC68HC11E Family Rev 4 Figure 3 2 Stacking Operations When a subroutine is called by a jump to subroutine JSR or branch to subroutine BSR instruction the address of the instruction after the JSR or BSR is automatically pushed onto the stack least significant byte first When the subroutine is finished a return from subroutine RTS instruction is executed The RTS pulls the previously stacked return address from the stack and loads it into the program counter Execution then continues at this recovered return address Technical Data MOTOROLA Central Processor Unit CPU 49 Central Processor Unit CPU When an interrupt is recognized the current instruction finishes normally the return address the current value in the program counter is pushed onto the stack all of t
169. SR is read with SPIF set first attempts to write SPDR are inhibited WCOL Write Collision Bit Clearing the WCOL bit is accomplished by reading the SPSR with WCOL set followed by an access of SPDR Refer to 8 6 4 Slave Select and 8 7 SPI System Errors 0 No write collision 1 Write collision Bit 5 Unimplemented Always reads 0 MODF Mode Fault Bit To clear the MODF bit read the SPSR with MODF set then write to the SPCR Refer to 8 6 4 Slave Select and 8 7 SPI System Errors 0 No mode fault 1 Mode fault Bits 3 0 Unimplemented Always read 0 MC68HC11E Family Rev 4 Technical Data MOTOROLA Serial Peripheral Interface SPI 175 Serial Peripheral Interface SPI 8 8 3 Serial Peripheral Data I O Register The SPDR is used when transmitting or receiving data on the serial bus Only a write to this register initiates transmission or reception of a byte and this only occurs in the master device At the completion of transferring a byte of data the SPIF status bit is set in both the master and slave devices A read of the SPDR is actually a read of a buffer To prevent an overrun and the loss of the byte that caused the overrun the first SPIF must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated Address 102 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset
170. TUM PLANE H 7 DIMENSION D DOES NOT INCLUDE DAMBAR C010 0 004 ROTRUSION DAMBAR PROTRUSION SHALL SEATING PLANE NOT CAUSE THE D DIMENSION TO EXCEED 0 53 0 021 DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT 8 DIMENSION K IS TO BE MEASURED FROM THE HEORETICAL INTERSECTION OF LEAD FOOT AND LEG CENTERLINES y Cg tn C C C H DATUM PLANE D D MILLIMETERS INCHES MIN MAX MIN MAX 13 90 1410 0 547 0 555 13 90 1410 0 547 0 555 2 07 2 46 0 081 0 097 0 30 0 45 0 012 0 018 2 00 2 40 0 079 0 094 0 30 0 012 0 80 BSC 0 031 BSC 0 067 0 250 0 003 0 010 0 130 0 230 0 005 0 090 0 50 0 66 0 020 0 026 12 00 REF 0 472 REF gt lt lt 0 o o lt oo n m om gt SEATING PLANE 5 ie 5 10 0130 0 170 0 005 0 007 0 40 BSC 0 016 BSC 2 Bef 2 82 X 013 030 0 005 0 012 1620 16 60 0 638 0 654 M 0 20 REF 0 008 REF oo 0 DETAIL C 16 20 16 60 0 638 0 654 110 130 0 043 0 051 Technical Data MC68HC11E Family Rev 4 256 Mechanical Data MOTOROLA 12 6 52 Pin Thin Quad Flat Pack Case 8480 p C 0 20 0 008 H LM N 2100000 4X TIPS A 0 20 0 00
171. U in bootstrap mode Some newer versions of the M68HC11 Family have additional utility programs that can be called from a downloaded program One utility is available to program EPROM or OTP versions of the M68HC11 second utility allows the contents of memory locations to be uploaded to a host computer In the MC68HC711K4 boot ROM a section of code is used by Motorola for stress testing the on chip EEPROM These test and utility programs are similar to self test ROM programs in other MCUs except that the boot ROM does not use valuable space in the normal memory map Bootstrap firmware is also involved in an optional EEPROM security function on some versions of the M68HC11 This EEPROM security feature prevents a software pirate from seeing what is in the on chip EEPROM The secured state is invoked by programming the no security NOSEC EEPROM bit in the CONFIG register Once this NOSEC bit is programmed to 0 the MCU will ignore the mode A pin and always come out of reset in normal single chip mode or special bootstrap mode depending on the state of the mode B pin Normal single chip mode is the usual way a secured part would be used Special bootstrap mode is used to disengage the security function only after the contents of EEPROM and RAM have been erased Refer to the M68HC11 Reference Manual Motorola document order number M68HC11RM AD for additional information on the security mode and complete listings of the boot ROMs that support the
172. USION IS 0 25 0 010 PER SIDE DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0 46 0 018 MINIMUM SPACE BETWEEN PROTRUSION AND ADJ ACENT LEAD OR PROTRUSION 0 07 0 003 MILLIMETERS INCHES DiM MN MAX A 10 00BSC 0394 BSC at 5 0085 0 197 BSC B 10 00BSC 0 394 BSC Bi 500BSC 0 197 BSC c im Ci 005 020 0 002 0 008 C2 130 150 0051 0 059 D 020 040 0 008 0 016 E 045 075 0 018 0 030 F 022 035 0 009 0 014 G 04585 0 026 BSC J 0 07 020 0 003 0 008 0 50REF 0 020 REF Ri 008 020 0 003 0 008 S 1200BSC 0472 BSC 51 600BSC 0 236 BSC u 0 09 016 0 004 0 006 12 0085 0472 BSC Vi 6 008SC 0 236 BSC 020REF 0 008 REF Z 100 0 039 REF ef 0 7 of re et oe 0 02 129 REF 12 REF o 5 13 5 13 Technical Data MOTOROLA Mechanical Data 257 Mechanical Data 12 7 56 Pin Dual in Line Package Case 859 NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI NAAAAAAAAAAAAAAAAAAAANANNANNNN Y14 5M 1982 2 CONTROLLING DIMENSION INCH 3 DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL
173. Utility NOTE Application Note The UPLOAD utility subroutine transfers data from the MCU to a host computer system over the SCI serial data link Only EPROM versions of the M68HC11 include this utility Verification of EPROM contents is one example of how the UPLOAD utility could be used Before calling this program the Y index register is loaded by user firmware with the address of the first data byte to be uploaded If a baud rate other than the current SCI baud rate is to used for the upload process the user s firmware must also write to the baud register The UPLOAD program sends successive bytes of data out the SCI transmitter until a reset is issued the upload loop is infinite For a complete commented listing example of the UPLOAD utility refer to Listing 3 MC68HC711E9 Bootloader ROM EPROM Programming Utility AN1060 Rev 1 0 The EPROM programming utility is one way of programming data into the internal EPROM of the MC68HC711E9 MCU An external 12 V programming power supply is required to program on chip EPROM The simplest way to use this utility program is to bootload a 3 byte program consisting of a single jump instruction to the start of the PROGRAM utility program BF00 The bootloader program sets the X and Y index registers to default values before jumping to the downloaded program see 16 at the bottom of Figure 3 When the host computer sees the FF character data to be programmed into the EPR
174. Y REM CONVERT THE DATA DIGITS TO BINARY AND SAVE IN THE ARRAY FOR 1 TO BYTECOUNT GOSUB 6000 GOSUB 7000 16 X SAVE UPPER NIBBLE OF BYTE GOSUB 6000 GOSUB 7000 Y Y X ADD LOWER NIBBLE CODES ARRAYCNT Y SAVE BYTE IN ARRAY ARRAYCNT ARRAYCNT 1 INCREMENT ARRAY INDEX NEXT GOTO 1000 CLOSE 1 REM DUMP BOOTLOAD CODE TO PART x R 2 COM1 1200 N 8 1 Macintosh COM statement OPEN COM1 1200 N 8 1 CD0 CSO0 DSO RS FOR RANDOM AS 2 DOS COM statement INPUT Comm port open 05 WHILE LOC 2 gt 0 FLUSH INPUT BUFFER GOSUB 8020 WEND PRINT PRINT Sending bootload code to target part AS 255 BOOTCODES ADD HEX FF TO SET BAUD RATE ON TARGET 11 GOSUB 6500 PRINT FOR 1 TO BOOTCOUNT 4 OF BYTES IN BOOT CODE BEING ECHOED GOSUB 8000 K ASC B GOSUB 8500 PRINT Character I received HX NEXT I PRINT Programming is ready to begin INPUT Are you ready 05 CLS WHILE LOC 2 gt O FLUSH INPUT BUFFER AN1060 Rev 1 0 MOTOROLA 309 Application Note 1598 GOSUB 8020 1599 WEND 1600 XMT 0 RCV 0 POINTERS TO XMIT AND RECEIVE BYTES 1610 AS CHRS CODES XMT 1620 GOSUB 6500 SEND FIRST BYTE 1625 FOR I 1 CODESIZE 1 ZERO BASED ARRAY 0 gt CODESIZE 1 1630 AS CHRS C
175. active high levels a pullup resistor to Vpp is needed if the TxD signal is used In systems where the PD1 TxD pin is normally used as a general purpose output there are no output driver conflicts It may be important to consider what the existing logic will do with the SCI serial data instead of the signals that would have been produced by the PD1 pin In systems where the PD1 pin is normally used as a general purpose input the driver circuit that drives the PD1 pin must be designed so that the PD1 TxD pin driver in the MCU can override this driver A simple series resistor between the driver and the PD1 pin can solve this problem The TxD pin can then be configured as an output and the MOTOROLA 293 Application Note Other series resistor will prevent direct conflict between the internal TxD driver and the external driver connected to PD1 through the series resistor The bootloader firmware sets the DWOM control bit which configures all port D pins for wire OR operation During the bootloading process all port D pins except the PD1 TxD pin are configured as high impedance inputs Any port D pin that normally is used as an output should have a pullup resistor so it does not float during the bootloading process Driving Boot Mode from Another M68HC11 second M68HC11 system can easily act as the host to drive bootstrap loading of an M68HC11 MCU This method is used to examine and program non volatile memories in target M68H
176. an also be used as general purpose or as an output compare NOTE Even when port A bit 7 is configured as an output the pin still drives the input to the pulse accumulator PAEN Pulse Accumulator System Enable Bit Refer to Section 9 Timing System PAMOD Pulse Accumulator Mode Bit Refer to Section 9 Timing System PEDGE Pulse Accumulator Edge Control Bit Refer to Section 9 Timing System DDRA3 Data Direction for Port A Bit 3 This bit is overridden if an output compare function is configured to control the pin 0 Input 1 Output 14 O5 Input Capture 4 Output Compare 5 Bit Refer to Section 9 Timing System RTR 1 0 RTI Interrupt Rate Select Bits Refer to Section 9 Timing System MC68HC11E Family Rev 4 Technical Data MOTOROLA Parallel Input Output I O Ports 135 Parallel Input Output I O Ports 6 4 Port B In single chip or bootstrap modes port B pins are general purpose outputs In expanded or special test modes port B pins are high order address outputs Address 1004 Bit 7 6 5 4 3 2 1 Bit 0 Single chip or bootstrap modes Read PB7 PB6 PB5 4 PB3 PB2 PB1 PBO Write Reset 0 0 0 0 0 0 0 0 Expanded or special test modes Read a ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 rite Reset 0 0 0 0 0 0 0 0 Figure 6 3
177. ansmitting devices to direct a message to individual receivers or to groups of receivers This addressing scheme can take any form as long as all transmitting and receiving devices are programmed to understand the same scheme Because the addressing information is usually the first frame s in a message receivers that are not part of the current task do not become burdened with the entire set of addressing frames All receivers are awake RWU 0 when each message begins As soon as a receiver determines that the message is not intended for it software sets the RWU bit RWU 1 which inhibits further flag setting until the RxD line goes idle at the end of the message As soon as an idle line is detected by receiver logic hardware automatically clears the RWU bit so that the first frame of the next message can be received This type of receiver wakeup requires a minimum of one idle line frame time between messages and no idle time between frames in a message 7 6 2 Address Mark Wakeup Technical Data The serial characters in this type of wakeup consist of seven eight if M 1 information bits and an MSB which indicates an address character when set to 1 or mark The first character of each message is an addressing character MSB 1 All receivers in the system evaluate this character to determine if the remainder of the message is directed toward this particular receiver AS soon as a receiver determines that a message is not intended
178. are disabled because their mask bits have been cleared The 14 05 bit in the register is cleared to configure the 14 05 function as OC5 however the OM5 OL5 control bits in the TCTL1 register are clear so OC5 does not control the pin MC68HC11E Family Rev 4 Technical Data MOTOROLA Resets and Interrupts 115 Resets and Interrupts 5 4 4 Real Time Interrupt RTI The real time interrupt flag RTIF is cleared and automatic hardware interrupts are masked The rate control bits are cleared after reset and can be initialized by software before the real time interrupt RTI system is used 5 4 5 Pulse Accumulator The pulse accumulator system is disabled at reset so that the pulse accumulator input PAI pin defaults to being a general purpose input pin 5 4 6 Computer Operating Properly COP The COP watchdog system is enabled if the NOCOP control bit in the CONFIG register is cleared and disabled if NOCOP is set The COP rate is set for the shortest duration timeout 5 4 7 Serial Communications Interface SCI The reset condition of the SCI system is independent of the operating mode At reset the SCI baud rate control register BAUD is initialized to 04 All transmit and receive interrupts are masked and both the transmitter and receiver are disabled so the port pins default to being general purpose lines The SCI frame format is initialized to an 8 bit character size The send break and receive
179. ates the STRB signal The 3 state mode variation does not allow part of port C to be used for static inputs while other port C pins are being used for handshake outputs Refer to the 6 9 Parallel I O Control Register for further information Technical Data MC68HC11E Family Rev 4 140 Parallel Input Output I O Ports MOTOROLA Parallel Input Output I O Ports Parallel Control Register 6 9 Parallel I O Control Register The parallel handshake functions are available only in the single chip operating mode PIOC is a read write register except for bit 7 which is read only Table 6 2 shows a summary of handshake operations Address 1002 Bit 7 6 5 4 3 2 1 Bit 0 Read STAF STAI CWOM HNDS OIN PLS EGA INVB Write Reset 0 0 0 0 0 U 1 1 U Unaffected Figure 6 10 Parallel I O Control Register PIOC STAF Strobe A Interrupt Status Flag STAF is set when the selected edge occurs on strobe A This bit can be cleared by a read of PIOC with STAF set followed by a read of PORTCL simple strobed or full input handshake mode or a write to PORTCL output handshake mode 0 No edge on strobe A 1 Selected edge on strobe A STAI Strobe A Interrupt Enable Mask Bit 0 STAF does not request interrupt 1 STAF requests interrupt CWOM Port C Wired OR Mode Bit affects all eight port C pins It is customary to have an external pullup resistor on lines that are driven by open drain d
180. ates the need for an external 12 volt supply Includes programming software and a user s manual Includes a 5 volt power cable and DB9 to DB25 connector adapter Technical Data MOTOROLA Development Support 273 Development Support Technical Data MC68HC11E Family Rev 4 274 Development Support MOTOROLA Technical Data M68HC11E Family Appendix B EVBU Schematic Refer to Figure B 1 for a schematic diagram of the M68HC11EVBU Universal Evaluation Board This diagram is included for reference only MC68HC11E Family Rev 4 Technical Data MOTOROLA EVBU Schematic 275 9 6 VIOYOLOW ejeq jeoiuuoe V 31L0H890IN 9 Voc 9 9 9 Voc uu E 1 RNID 5 gt RNIC lt RNIB R1 22 M 2 47K 47K gt 47K 25 PBO AB 5 4 PBy g MOUIS ARQ MCU3A 34 40 1 Lo PBA AID 55 1 MCU 32 Spates PBAALL sS wc muza
181. binary coded decimal BCD arithmetic operations but there is no equivalent BCD instruction to adjust accumulator B The add subtract and compare instructions associated with both A and B ABA SBA and only operate one direction making it important to plan ahead to ensure that the correct operand is in the correct accumulator 3 3 2 Index Register X IX The register provides 16 bit indexing value that can be added to the 8 bit offset provided in an instruction to create an effective address The IX register can also be used as a counter or as a temporary storage register 3 3 3 Index Register Y IY The 16 bit IY register performs an indexed mode function similar to that of the register However most instructions using the register require an extra byte of machine code and an extra cycle of execution time because of the way the opcode map is implemented Refer to 3 5 Opcodes and Operands for further information 3 3 4 Stack Pointer SP Technical Data The M68HC11 CPU has an automatic program stack This stack can be located anywhere in the address space and can be any size up to the amount of memory available in the system Normally the SP is initialized by one of the first instructions in an application program The stack is configured as a data structure that grows downward from high memory to low memory Each time a new byte is pushed onto the stack the SP is decremented Each time a byte i
182. bootload code is being sent to the target and the results of the echoing of this code are displayed on the screen Another prompt reading Programming is ready to begin Are you will appear Turn on the 12 volt programming power supply and press RETURN to start the actual programming of the target EPROM A count of the byte being verified will be updated continually on the screen as the programming progresses Any failures will be flagged as they occur When programming is complete a message will be displayed as well as a prompt requesting the user to press RETURN to quit Turn off the 12 volt programming power supply before turning off 5 volts to the EVBU MOTOROLA 307 Application Note Listing 2 BASIC Program for Personal Computer 1 k k Ck k k KKK KKK k K K k k x K x x k C Ck Ck KKK x k x x k Ck Ck x x k lt x x x x k x K x x k lt lt x X x lt x x x lt 2 Mo E E9BUF BAS A PROGRAM TO DEMONSTRATE THE USE OF THE BOOT MODE ok ON THE 11 BY PROGRAMMING 711 9 WITH Dus BUFFALO 3 4 6 REQUIRES THAT THE S RECORDS FOR BUFFALO BUF34 S19 gu 1 BE AVAILABLE IN THE SAME DIRECTORY OR FOLDER 9 T9 472 THIS PROGRAM HAS BEEN RUN BOTH A MS DOS COMPUTER qT USING QUICKBASIC 4 5 AND MACINTOSH USING T QUICKBASIC 1 0 L4 15 KKK KKK Ck Ck CI
183. bout 0 7 volts above the Vpp voltage the internal RAM and part of the reset logic are powered from this signal rather than the Vpp input This allows RAM contents to be retained without Vpp power applied to the MCU Reset must be driven low before Vpp is removed and must remain low until Vpp has been restored to a valid level MC68HC11E Family Rev 4 Technical Data MOTOROLA Pin Descriptions 37 Pin Descriptions 2 10 VRH 2 11 STRA AS 2 12 STRB R W Technical Data These two inputs provide the reference voltages for the analog to digital A D converter circuitry e Vp is the low reference typically 0 Vdc e VnHis the high reference For proper A D converter operation should be at least Vdc greater than VpL Vp and Vay should be between Vss The strobe A STRA and address strobe AS pin performs either of two separate functions depending on the operating mode single chip mode STRA performs an input handshake strobe input function e Inthe expanded multiplexed mode AS provides an address strobe function AS be used to demultiplex the address and data signals at port C Refer to Section 4 Operating Modes and On Chip Memory The strobe B STRB and read write RAN pin act as either an output strobe or as a data bus direction indicator depending on the operating mode In single chip operating mode STRB acts as a programmable strobe for ha
184. bueno 107 SE iu oda sa A S crat has a das Hr dd d ee 108 R cem 108 5 3 1 Power On Reset POR 109 5 3 2 External Reset RESET 109 5 3 3 Computer Operating Properly COP Reset 110 5 3 4 uuu dadurdqdoodo d 111 5 3 5 System Configuration Options Register 112 5 3 6 Configuration Control Register 113 54 cuui der ia eO RR 114 5 4 1 Central Processor Unit 115 5 4 2 115 5 4 3 UC abisaq ee 1 72711271117 7517 017 7 115 5 4 4 Real Time Interrupt 116 5 4 5 Pulse Accumulator 116 5 4 6 Computer Operating Properly 116 5 4 7 Serial Communications Interface 5 116 5 4 8 Serial Peripheral Interface 117 5 4 9 Analog to Digital A D 117 54 10 System 117 5 5 Reset and Interrupt 117 5 5 1 Highest Priority Interrupt and Miscellaneous Register 119 50 MENPE PET 121 5 6 1 Interrupt Recognition and Register Stacking 122 5 6 2 Non Maskable Interrupt Request 123 5 6 3 Illegal Opcode Trap 123 5 6 4 Software Interrupt SWI
185. ce function Figure 8 shows a small circuit that is added to the wire wrap area of the EVBU The 3 terminal jumper allows the XIRQ line to be connected to either the programming power supply or to a substitute pullup resistor for XIRQ The 100 ohm resistor is a current limiter to protect the 12 volt input of the MCU The resistor and LED connected to P5 pin 9 port C bit 0 is an optional indicator that lights when programming is complete BASIC was chosen as the programming language due to its readability and availability in parallel versions on both the IBM PC and the Macintosh The program demonstrates several programming techniques for use with an M68HC1 1 and is not necessarily intended to be a finished commercial program For example there is little error checking and the user interface is elementary A complete listing of the BASIC program is included in Listing 2 BASIC Program for Personal Computer with moderate comments The following paragraphs include 9 BM is a registered trademark of International Business Machines Macintosh is a registered trademark of Apple Computers Inc AN1060 Rev 1 0 302 MOTOROLA AN1060 Rev 1 0 Application Note a more detailed discussion of the program as it pertains to communicating with and programming the target MC68HC711E9 Lines 25 45 initialize and define the variables and array used in the program Changes to this section would allow for other progra
186. clock 32 Internal RC oscillator 32 us Conversion result never decreases with an Monotonicity increase in input voltage and has no missing Guaranteed codes Zero input reading Conversion result when Vi Var 00 Full scale reading Conversion result when Vi Vay Sample acquisition Analog input acquisition sampling time time E clock 12 Internal RC oscillator 12 us Sample hold Input capacitance during sample __ capacitance PE 7 0 20 typical pF Input leakage on A D pins Input leakage PE 7 0 400 nA VRL VRH 1 0 1 3 0 to 5 5 Vss 0 Vdc Ta T to Ty 750 kHz lt E lt 2 0 MHz unless otherwise noted 2 Source impedances greater than 10 affect accuracy adversely because of input leakage MC68HC11E Family Rev 4 Technical Data MOTOROLA Electrical Characteristics 241 Electrical Characteristics 11 16 Expansion Bus Timing Characteristics 1 0 MHz 2 0 MHz 3 0 MHz Num Characteristic Symbol Unit Min Max Min Max Min Max Frequency of operation f E clock frequency 5 dc 1 0 dc 2 0 dc 3 0 MHz 1 Cycle time 1000 500 333 ns Pulse width E low PW 227 14 1 2 teye 23 ns EL 477 a 12 Pulse width E high PW 222 141 3 1 2 toyo 28 ns
187. cognition and Register Stacking Technical Data An interrupt can be recognized at any time after it is enabled by its local mask if any and by the global mask bit in the CCR Once an interrupt source is recognized the CPU responds at the completion of the instruction being executed Interrupt latency varies according to the number of cycles required to complete the current instruction When the CPU begins to service an interrupt the contents of the CPU registers are pushed onto the stack in the order shown in Table 5 5 After the CCR value is stacked the bit and the X bit if XIRQ is pending are set to inhibit further interrupts The interrupt vector for the highest priority pending source is fetched and execution continues at the address specified by the vector At the end of the interrupt service routine the return from interrupt instruction is executed and the saved registers are pulled from the stack in reverse order so that normal program execution can resume Refer to Section 3 Central Processor Unit CPU Table 5 5 Stacking Order on Entry to Interrupts Memory Location CPU Registers SP PCL SP 1 PCH SP 2 IYL SP 3 IYH SP 4 IXL SP 5 IXH SP 6 ACCA SP 7 ACCB SP 8 CCR MC68HC11E Family Rev 4 122 Resets and Interrupts MOTOROLA Resets Interrupts Interrupts 5 6 2 Non Maskable Interrupt Request XIRQ Non maskable interrupts are useful because they can always
188. contention between two pin drivers For push pull CMOS drivers this contention can cause permanent damage The mode fault mechanism attempts to protect the device by disabling the drivers The MSTR control bit in the SPCR and all four DDRD control bits associated with the SPI are cleared and an interrupt is generated subject to masking by the SPIE control bit and the bit in the CCR Other precautions may need to be taken to prevent driver damage If two devices are made masters at the same time mode fault does not help protect either one unless one of them selects the other as slave The amount of damage possible depends on the length of time both devices attempt to act as master MC68HC11E Family Rev 4 Technical Data MOTOROLA Serial Peripheral Interface SPI 171 Serial Peripheral Interface SPI 8 8 SPI Registers Technical Data A write collision error occurs if the SPDR is written while a transfer is in progress Because the SPDR is not double buffered in the transmit direction writes to SPDR cause data to be written directly into the SPI shift register Because this write corrupts any transfer in progress a write collision error is generated The transfer continues undisturbed and the write data that caused the error is not written to the shifter write collision is normally a slave error because a slave has no control over when a master initiates a transfer A master knows when a transfer is in progress so ther
189. conversion sequence is in progress when either the stop or wait mode is entered the conversion of the current channel is suspended When the MCU resumes normal operation that channel is resampled and the conversion sequence is resumed As the MCU exits wait mode the A D circuits are stable and valid results can be obtained on the first conversion However in stop mode all analog bias currents are disabled and it is necessary to allow a stabilization period when leaving stop mode If stop mode is exited with a delay DLY 1 there is enough time for these circuits to stabilize before the first conversion If stop mode is exited with no delay DLY bit in OPTION register 0 allow 10 ms for the A D circuitry to stabilize to avoid invalid results MC68HC11E Family Rev 4 Technical Data MOTOROLA Analog to Digital A D Converter 217 Analog to Digital A D Converter 10 10 A D Control Status Register All bits in this register can be read or written except bit 7 which is a read only status indicator and bit 6 which always reads as 0 Write to ADCTL to initiate a conversion To quit a conversion in progress write to this register and a new conversion sequence begins immediately Address 1030 Technical Data Bit 7 6 5 4 3 2 1 Bit 0 Read CCF SCAN MULT CD Write Reset 0 0 Indeterminate after reset Unimplemented Figure 10 5 A D Control Status Register ADCTL C
190. de because it is new to many users By knowing some of the common difficulties the user can avoid them or at least recognize and quickly correct them Reset Conditions It is common to confuse the reset state of systems and control bits with vs Conditions the state of these systems and control bits when a bootloaded program as Bootloaded in RAM starts Program Starts AN1060 Rev 1 0 MOTOROLA 311 Application Note Connecting RxD to Vss Does Not Cause the 5 to Receive a Break FF Character Is Required before Loading into RAM Between these times the bootloader program is executed which changes the states of some systems and control bits The system is initialized and turned on Rx and Tx e The system has control of the PDO and PD1 pins e Port D outputs are configured for wire OR operation The stack pointer is initialized to the top of RAM Time has passed two or more SCI character times Timer has advanced from its reset count value Users also forget that bootstrap mode is a special mode Thus privileged control bits are accessible and write protection for some registers is not in effect The bootstrap ROM is in the memory map The DISR bit in the TEST1 control register is set which disables resets from the COP and clock monitor systems Since bootstrap is a special mode these conditions can be changed by software The bus can even be switched from single chip mode to
191. devices in the E series operate at 3 0 5 5 volts Very fast signal transitions occur on the MCU pins The short rise and fall times place high short duration current demands on the power supply To prevent noise problems provide good power supply bypassing at the MCU Also use bypass capacitors that have good MC68HC11E Family Rev 4 32 Pin Descriptions MOTOROLA Pin Descriptions VDD and VSS high frequency characteristics and situate them as close to the MCU as possible Bypass requirements vary depending on how heavily the MCU pins are loaded TO RESET 64 OF M68HC11 TO RESET OF M68HC11 Vpp MANUAL 5 47kQ RESET SWITCH 47kQ Vo AAA 10pF OPTIONAL POWER ON DELAY AND MANUAL RESET SWITCH Figure 2 7 External Reset Circuit with Delay MC68HC11E Family Rev 4 Technical Data MOTOROLA Pin Descriptions 33 Pin Descriptions 2 4 RESET CAUTION Technical Data A bidirectional control signal RESET acts as an input to initialize the MCU to a known startup state It also acts as an open drain output to indicate that an internal failure has been detected in either the clock monitor or computer operating properly COP watchdog circuit The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than two E clock cycles after a reset has occurred See Figure 2 6 and Figure 2 7 Do not c
192. dition If a character other than FF is sent as the first character an SCI receive error could result Main Bootloader Program AN1060 Rev 1 0 Figure 3 is a flowchart of the main bootloader program in the MC68HC711E9 This bootloader demonstrates the most important features of the bootloaders used on all M68HC11 Family members For complete listings of other M68HC11 versions refer to Listing 3 MC68HC711E9 Bootloader ROM at the end of this application note and to Appendix B of the M68HC11 Reference Manual Motorola document order number M68HC11RM AD The reset vector in the boot ROM points to the start 1 of this program The initialization block 2 establishes starting conditions and sets up the SCI and port D The stack pointer is set because there are push and pull instructions in the bootloader program The X index register is pointed at the start of the register block 1000 so indexed addressing can be used Indexed addressing takes one less byte of ROM space than extended instructions and bit manipulation instructions are not available in extended addressing forms The port D wire OR mode DWOM bit in the serial peripheral interface control register SPCR is set to configure port D for wired OR operation to minimize potential conflicts with external systems that use the PD1 TxD pin as an input The baud rate for the SCI is initially set to 7812 baud at a 2 MHz E clock rate but can automatically switch to 1200 baud based on t
193. dle character time logic 1 is queued as a preamble 0 Transmitter disabled 1 Transmitter enabled RE Receiver Enable Bit 0 Receiver disabled 1 Receiver enabled Technical Data MC68HC11E Family Rev 4 154 Serial Communications Interface SCI MOTOROLA Serial Communications Interface SCI SCI Registers RWU Receiver Wakeup Control Bit 0 Normal SCI receiver 1 Wakeup enabled and receiver interrupts inhibited SBK Send Break At least one character time of break is queued and sent each time SBK is written to 1 As long as the SBK bit is set break characters are queued and sent More than one break may be sent if the transmitter is idle at the time the SBK bit is toggled on and off as the baud rate clock edge could occur between writing the 1 and writing the 0 to SBK 0 Break generator off 1 Break codes generated 7 8 4 Serial Communication Status Register The SCSR provides inputs to the interrupt logic circuits for generation of the SCI system interrupt Address 102 Bit 7 6 5 4 3 2 1 Bit 0 Read TDRE TC RDRF IDLE OR NF FE Write Reset 1 1 0 0 0 0 0 0 Unimplemented Figure 7 6 Serial Communications Status Register SCSR TDRE Transmit Data Register Empty Flag This flag is set when SCDR is empty Clear the TDRE flag by reading SCSR with TDRE set and then writing to SCDR 0 SCDR busy 0 SCDR empty MC68HC11E Family Rev 4 Tech
194. e that executes a bootloader program in an internal bootstrap ROM Testis a special mode that allows privileged access to internal resources 4 3 1 Single Chip Mode NOTE Technical Data In single chip mode ports B and C and strobe pins A STRA and B STRB are available for general purpose parallel input output I O In this mode all software needed to control the MCU is contained in internal resources If present read only memory ROM and or erasable programmable read only memory EPROM will always be enabled out of reset ensuring that the reset and interrupt vectors will be available at locations FFCO FFFF For the MC68HC811E2 the vector locations are the same however they are contained in the 2048 byte EEPROM array MC68HC11E Family Rev 4 66 Operating Modes and On Chip Memory MOTOROLA 4 3 2 Expanded Mode NOTE 4 3 3 Test Mode Operating Modes and On Chip Memory Operating Modes In expanded operating mode the MCU can access the 64 Kbyte address space The space includes The same on chip memory addresses used for single chip mode Addresses for external peripherals and memory devices The expansion bus is made up of ports B and C and control signals AS address strobe and R W read write R W and AS allow the low order address and the 8 bit data bus to be multiplexed on the same pins During the first half of each bus cycle address information is present During the second
195. e IRQ pin as a means of recovering from stop the I bit in the CCR must be clear IRQ not masked The XIRQ pin can be used to wake up the MCU from stop regardless of the state of the X bit in the CCR although the recovery sequence depends on the state of the X bit If X is set to 0 XIRQ not masked the MCU starts up beginning with the stacking sequence leading to normal service of the XIRQ request If X is set to 1 XIRQ masked or inhibited then processing continues with the instruction that immediately follows the STOP instruction and no XIRQ interrupt service is requested or pending Because the oscillator is stopped in stop mode a restart delay may be imposed to allow oscillator stabilization upon leaving stop If the internal oscillator is being used this delay is required however if a stable external oscillator is being used the DLY control bit can be used to bypass this startup delay The DLY control bit is set by reset and can be optionally cleared during initialization If the DLY equal to 0 option is used to avoid startup delay on recovery from stop then reset should not be used as the means of recovering from stop as this causes DLY to be set again by reset imposing the restart delay This same delay also applies to power on reset regardless of the state of the DLY control bit but does not apply to a reset while the clocks are running MC68HC11E Family Rev 4 Technical Data MOTOROLA Resets and Interrupts 1
196. e before transmission or reception of a message 2 Astart bit logic 0 transmitted or received that indicates the start of each character 3 Datathatis transmitted and received least significant bit LSB first 4 stop bit logic 1 used to indicate the end of a frame A frame consists of a start bit a character of eight or nine data bits anda stop bit 5 A break defined as the transmission or reception of a logic 0 for some multiple number of frames Selection of the word length is controlled by the M bit of SCI control register SCCHR1 7 4 Transmit Operation Technical Data The SCI transmitter includes a parallel transmit data register SCDR and a serial shift register The contents of the serial shift register can be written only through the SCDR This double buffered operation allows a character to be shifted out serially while another character is waiting in the SCDR to be transferred into the serial shift register The output of the serial shift register is applied to TxD as long as transmission is in MC68HC11E Family Rev 4 146 Serial Communications Interface SCI MOTOROLA Serial Communications Interface SCI Transmit Operation progress or the transmit enable TE bit of serial communication control register 2 SCCR2 is set The block diagram Figure 7 1 shows the transmit serial shift register and the buffer logic at the top of the figure TRANSMITTER WRITE ONLY BAUD RATE SCDR Tx BUFFER
197. e ir TTC Pp 28 Vpp and Vss TE b in 32 55 pa qu a 34 Crystal Driver External Clock Input EX TAL d en REEF 35 E LL wi d od o o o Dod di RT Ed 36 interrupt Request IRQ a 36 Non Maskable Interrupt 36 MODA and MODB MODA LIR and 37 ka qaq sot OA POR PU X X ROW 38 SIB 5 eee ee asss dca ede ded dd 38 ae 38 Pon SDI 39 ao f 39 ius 1 Pre E 41 E ouod Hae dd dpa dor a ird sod dou 42 Ir eT 43 SORA Et RIA RR CN RO AR 43 Technical Data MOTOROLA Table of Contents 7 Table of Contents Technical Data Section 3 Central Processor Unit CPU AT ee ee eod AUR 2 de eee Tere 45 De WOON cock ea ua edd 46 33 i ard di iade 46 3 3 1 Accumulators A B D 47 3 3 2 Index Register X IX 48 3 3 3 Index Register Y YY 48 3 3 4 Slack Poimer DSP aede
198. e is no reason for a master to generate a write collision error although the SPI logic can detect write collisions in both master and slave devices The SPI configuration determines the characteristics of a transfer in progress For a master a transfer begins when data is written to SPDR and ends when SPIF is set For a slave with equal to 0 a transfer starts when SS goes low and ends when SS returns high In this case SPIF is set at the middle of the eighth SCK cycle when data is transferred from the shifter to the parallel data register but the transfer is still in progress until SS goes high For a slave with CPHA equal to 1 transfer begins when the SCK line goes to its active level which is the edge at the beginning of the first SCK cycle The transfer ends in a slave in which CPHA equals 1 when SPIF is set The three registers are Serial peripheral control register SPCR Serial peripheral status register SPSR Serial peripheral data register SPDR These registers provide control status and data storage functions MC68HC11E Family Rev 4 172 Serial Peripheral Interface SPI MOTOROLA Serial Peripheral Interface SPI SPI Registers 8 8 1 Serial Peripheral Control Register Address 1028 Bit 7 6 5 4 3 2 1 Bit 0 Read SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPRO Write Reset 0 0 0 0 0 1 U U U Unaffected Figure 8 3 Serial Peripheral Control Regist
199. e polarity are captured To measure pulse width two alternate polarity edges are captured In most cases input capture edges are asynchronous to the internal timer counter which is clocked relative to an internal clock PH2 These asynchronous capture requests are synchronized to PH2 so that the latching occurs on the opposite half cycle of PH2 from when the timer counter is being incremented This synchronization process introduces a delay from when the edge occurs to when the counter value is detected Because these delays offset each other when the time between two edges is being measured the delay can be ignored When an input capture is being used with an output compare there is a similar delay between the actual compare point and when the output pin changes state The control and status bits that implement the input capture functions are contained in e Pulse accumulator control register PACTL Timer control 2 register TCTL2 Timer interrupt mask 1 register TMSK1 Timer interrupt flag 2 register TFLG1 To configure port A bit 3 as an input capture clear the DDRAG bit of the PACTL register Note that this bit is cleared out of reset To enable PA3 as the fourth input capture set the 14 O5 bit in the PACTL register Otherwise is configured as a fifth output compare out of reset with bit 14 05 being cleared If the DDRAG3 bit is set configuring as an output and IC4 is enabled then writes to ca
200. e present whether or not there was a bootstrap mode Figure 1 shows the composite memory map of the MC68HC711E 9 in its four basic modes of operation including bootstrap mode The active mode is determined by the mode A MDA and special mode SMOD control bits in the HPRIO control register These control bits are in turn controlled by the state of the mode A MODA and mode B MODB pins during reset Table 1 shows the relationship between the state of these AN1060 Rev 1 0 280 MOTOROLA 1060 1 0 Application Note pins during reset the selected mode and the state of the MDA SMOD and control bits Refer to the composite memory map information in Table 1 for the following discussion The MDA control bit is determined by the state of the MODA pin as the MCU leaves reset MDA selects between single chip and expanded operating modes When MDA is 0 a single chip mode is selected either normal single chip mode or special bootstrap mode When MDA is 1 expanded mode is selected either normal expanded mode or special test mode The SMOD control bit is determined by the inverted state of the MODB pin as the MCU leaves reset SMOD controls whether a normal mode or a special mode is selected When SMOD is 0 one of the two normal modes is selected either normal single chip mode or normal expanded mode When SMOD is 1 one of the two special modes is selected either special bootstrap mode or
201. e to output compare registers TOC1 TOC4 and TI4 O5 When TCNT value matches the comparison value specified pin actions occur Register name Timer Output Compare 1 Register High Address 1016 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 Register name Timer Output Compare 1 Register Low Address 1017 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 Figure 9 8 Timer Output Compare 1 Register Pair TOC1 Register name Timer Output Compare 2 Register High Address 1018 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 Register name Timer Output Compare 2 Register Low Address 1019 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 Figure 9 9 Timer Output Compare 2 Register Pair TOC2 Technical Data MC68HC11E Family Rev 4 188 Timing System MOTOROLA Timing System Output Compare Register name Timer Output Compare 3 Register High Address 101A Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 Register name Ti
202. e unlimited access to the internal EEPROM and RAM and can read write or transfer the contents of these memories An enhanced security feature which protects EPROM contents RAM and EEPROM from unauthorized accesses is available in MC68S711E9 Refer to Section 12 Mechanical Data and Section 13 Ordering Information for the exact part number For further information these engineering bulletins have been included at the back of this data book EB183 Enabling the Security Feature the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR EB188 Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 105 Operating Modes and On Chip Memory Technical Data MC68HC11E Family Rev 4 106 Operating Modes and On Chip Memory MOTOROLA Technical Data M68HC11E Family 5 1 Contents DE 5 3 5 3 1 5 3 2 5 3 3 5 3 4 5 3 5 5 3 6 5 4 5 4 1 5 4 2 5 4 3 5 4 4 5 4 5 5 4 6 5 4 7 5 4 8 5 4 9 5 4 10 5 5 5 5 1 5 6 5 6 1 5 6 2 5 6 3 5 6 4 5 6 5 5 6 6 MC68HC11E Family Rev 4 Section 5 Resets and Interrupts MU AEA 108 FA rrr 108 Power On Reset POR 109 External Reset RESET 109 Computer Operating Properly Reset 110 Clock Monitor Resel de he RR oe ee
203. ected at the PA7 PAI OC1 pin To clear this status bit write to the TFLG2 register with a 1 in the corresponding data bit position bit 4 The control bit allows configuring the pulse accumulator input edge detect for polled or interrupt driven operation but does not affect setting or clearing the PAIF bit When is 0 pulse accumulator input interrupts are inhibited and the system operates in a polled mode In this mode the PAIF bit must be polled by user software to determine when an edge has occurred When the PAII control bit is set a hardware interrupt request is generated each time PAIF is set Before leaving the interrupt service routine software must clear PAIF by writing to the TFLG2 register MC68HC11E Family Rev 4 208 Timing System MOTOROLA Technical Data M68HC11E Family Section 10 Analog to Digital A D Converter 10 1 Contents 10 2 10 3 10 3 1 10 3 2 10 3 3 10 3 4 10 3 5 10 3 6 10 4 10 5 10 6 10 7 10 8 10 9 10 10 10 11 10 2 Introduction lin d 6 f 62 0 cece aeende dete asss TT 209 sorria Ux Oa cn waqasa kaisa macam ms ea a 210 210 Analog Converter 212 Digital 212 34455584 dd oe dene 212 A D Converter Clocks 213 Conversion Sequence 213 A D Converter Power Up and Clock Select
204. efe 1 oye digital dna intelligence everywhere M68HC11 Microcontrollers WWW MOTOROLA COM SEMICONDUCTORS M68HC11E Family Technical Data M68HC11E D Rev 4 7 2002 MC68HC11E Family Technical Data To provide the most up to date information the revision of our documents on the World Wide Web will be the most current Your printed copy be an earlier revision To verify you have the latest information available refer to http Awww motorola com semiconductors The following revision history table summarizes changes contained in this document For your convenience the page number designators have been linked to the appropriate location Motorola and the Stylized M Logo are registered trademarks of Motorola Inc DigitalDNA is a trademark of Motorola Inc Motorola Inc 2002 MC68HC11E Family Rev 4 Technical Data MOTOROLA 3 Revision History Revision History Revision ee Page Date Level Description Number s 4 4 3 1 System Configuration Register Addition to NOCOP bit 88 May 2001 3 1 description Added 11 22 EPROM Characteristics 251 June 2001 3 2 11 22 EPROM Characteristics For clarity addition to note 2 251 following the table December 33 7 8 2 Serial Communications Control Register 1 SCCR1 bit 4 153 2001 i M description corrected 11 8 MC68L11E9 E20 DC Electrical Characteristics Title 226 changed to
205. efer to the following table Mode IRVNE Out E Clock Out IRV Out IRVNE IRVNE Can of Reset of Reset of Reset Affects Only Be Written Single chip 0 On Off E Once Expanded 0 On Off IRV Once Bootstrap 0 On Off E Once Special test 1 On On IRV Once PSEL 3 0 Priority Select Bits Refer to Section 5 Resets and Interrupts Technical Data MC68HC11E Family Rev 4 84 Operating Modes and On Chip Memory MOTOROLA 4 4 3 System Initialization Operating Modes and On Chip Memory Memory Map Registers and bits that control initialization and the basic operation of the MCU are protected against writes except under special circumstances Table 4 2 lists registers that can be written only once after reset or that must be written within the first 64 cycles after reset Table 4 2 Write Access Limited Registers Operating Register Register Name Must be Written Write Mode Address in First 64 Cycles Anytime SMOD 0 x024 Timer interrupt mask 2 TMSK2 Bits 1 0 once only Bits 7 2 x035 Block protect register BPROT Clear bits once only Set bits only TJ POM x03C Highest priority l bit interrupt See HPRIO See HPRIO and miscellaneous HPRIO description description x03D RAM and map register INIT Yes once only SMOD 1 x024 Timer interrupt mask 2 TMSK2 All set or clear x035 Block protect register BPROT All set or clear
206. egisters have no effect Data in the A D converter result registers is valid when the CCF flag in the ADCTL register is set indicating a conversion sequence is complete If conversion results are needed sooner refer to Figure 10 3 which shows the A D conversion sequence diagram Register name Analog to Digital Converter Result Register 1 Read Write Reset Read Write Reset Read Write Reset Address 1031 Bit7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit5 Bit4 Bit 3 Bit2 Bit1 Bit 0 Indeterminate after reset Register name Analog to Digital Converter Result Register 2 Address 1032 Bit7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 Indeterminate after reset Register name Analog to Digital Converter Result Register 3 Address 1033 Bit7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit5 Bit4 Bit 3 Bit 2 Bit1 Bit 0 Indeterminate after reset Register name Analog to Digital Converter Result Register4 Address 1034 Bit7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 Read Write Reset Technical Data Unimplemented Indeterminate after reset Figure 10 6 Analog to Digital Converter Result Registers ADR1 ADR4 MC68HC11E Family Rev 4 220 Analog to Digital A D Converter MOTOROLA Technical Data M68HC11E Family
207. elationship between master and slave The CPHA bit selects one of two different clocking protocols Refer to Figure 8 2 and 8 5 Clock Phase and Polarity Controls SPR 1 0 SPI Clock Rate Select Bits These two bits select the SPI clock SCK rate when the device is configured as master When the device is configured as slave these bits have no effect Refer to Table 8 1 Table 8 1 SPI Clock Rates SPR 1 0 Divide Frequency at Frequency at Frequency at Frequency at E 1 MHz Baud E 2 MHz Baud E 3 MHz Baud E 4 MHz Baud 00 2 500 kHz 1 0 MHz 1 5 MHz 2 MHz 01 4 250 kHz 500 kHz 750 kHz 1 MHz 10 16 62 5 kHz 125 kHz 187 5 kHz 250 kHz 11 32 31 3 kHz 62 5 kHz 93 8 kHz 125 kHz Technical Data MC68HC11E Family Rev 4 174 Serial Peripheral Interface MOTOROLA Serial Peripheral Interface SPI Registers 8 8 2 Serial Peripheral Status Register Address 1029 Bit7 6 5 4 3 2 1 Bit 0 Read SPIF WCOL MODF Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 8 4 Serial Peripheral Status Register SPSR SPIF SPI Interrupt Complete Flag SPIF is set upon completion of data transfer between the processor and the external device If SPIF goes high and if SPIE is set a serial peripheral interrupt is generated To clear the SPIF bit read the SPSR with SPIF set then access the SPDR Unless SP
208. elayed one more cycle Technical Data MC68HC11E Family Rev 4 236 Electrical Characteristics MOTOROLA Electrical Characteristics MC68L11E9 E20 Peripheral Port Timing MCU READ OF PORT PORTS 0 PORTE For nomiatched operation of port C Figure 11 7 Port Read Timing Diagram MCU WRITE TO PORT PREVIOUS PORT DATA NEW DATA VALID PORTA PREVIOUS PORT DATA NEW DATA VALID Figure 11 8 Port Write Timing Diagram STRA IN PORT C IN Figure 11 9 Simple Input Strobe Timing Diagram MC68HC11E Family Rev 4 Technical Data MOTOROLA Electrical Characteristics 237 Electrical Characteristics m MCU WRITE TO PORTB EI 22 PORT B PREVIOUS PORT DATA NEW DATA VALID STRB OUT Figure 11 10 Simple Output Strobe Timing Diagram lt READ STRB 007 thes STRA IN ts ty PORT C IN Notes 1 After reading PIOC with STAF set 2 Figure shows rising edge STRA EGA 1 and high true STRB INVB 1 Figure 11 11 Port C Input Handshake Timing Diagram WRITE PORTCLU PORTC OUT PREVIOUS PORT DATA XXXX 3 NEW DATA VALID toes READY STRB IN thes STRA IN Notes 1 After reading PIOC with STAF set 2 Figure shows rising edge STRA EGA 1 and high true STRB INVB 1 Figure 11 12 Port C Output Handshake Timing Diagram Technical Data MC68HC11E Family Rev 4 238 Electrical Characteristics
209. em allows the MCU to communicate synchronously with peripheral devices such as Frequency synthesizers Liquid crystal display LCD drivers e Analog to digital A D converter subsystems Other microprocessors The SPI is also capable of inter processor communication in a multiple master system The SPI system can be configured as either a master or a Slave device When configured as a master data transfer rates can be as high as one half the E clock rate 1 5 Mbits per second for a 3 MHz bus frequency When configured as a slave data transfers can be as fast as the E clock rate 3 Mbits per second for a 3 MHz bus frequency 8 3 Functional Description Technical Data The central element in the SPI system is the block containing the shift register and the read data buffer The system is single buffered in the transmit direction and double buffered in the receive direction This means that new data for transmission cannot be written to the shifter until the previous transfer is complete however received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial character As long as the first character is read out of the read data buffer before the next serial character is ready to be transferred no overrun condition occurs A single MCU register address is used for reading data from the read data buffer and for writing data to the shifter The SPI status block represents the SPI sta
210. emented Always reads 0 CR 1 0 COP Timer Rate Select Bits Refer to Section 5 Resets and Interrupts and Section 9 Timing System 10 5 Conversion Process The A D conversion sequence begins one E clock cycle after a write to the A D control status register ADCTL The bits in ADCTL select the channel and the mode of conversion An input voltage equal to Va converts to 00 and an input voltage equal to Vay converts to FF full scale with no overflow indication For ratiometric conversions of this type the source of each analog input should use Vnr as the supply voltage and be referenced to Vg MC68HC11E Family Rev 4 Technical Data MOTOROLA Analog to Digital A D Converter 215 Analog to Digital A D Converter 10 6 Channel Assignments The multiplexer allows the A D converter to select one of 16 analog signals Eight of these channels correspond to port E input lines to the MCU four of the channels are internal reference points or test functions and four channels are reserved Refer to Table 10 1 Table 10 1 Converter Channel Assignments Channel Channel Result in ADRx Number Signal if MULT 1 1 ANO ADR1 2 AN1 ADR2 3 AN2 ADR3 4 AN3 ADR4 5 AN4 ADR1 6 AN5 ADR2 7 AN6 ADR3 8 AN7 ADR4 9 12 Reserved 13 Vay ADR1 14 Va ADR2 15 20 ADR3 16 Reserved ADR4 1 Used for factory testing 10 7 Single Channel Operation The two types of
211. enhanced if unused inputs are connected to an appropriate logic voltage level for example either Vss or Vpp MC68HC11E Family Rev 4 222 Electrical Characteristics MOTOROLA 11 4 Functional Operating Range Electrical Characteristics Functional Operating Range Rating Symbol Value Unit Operating temperature range T to Ty MC68HC 7 11Ex 0 to 70 MC68HC 7 11ExC 40 to 85 MC68HC 7 11ExV 40 to 105 MC68HC 7 11ExM T 40 to 125 MC68HC811E2 A 0 to 70 MC68HC811E2G 40 to 85 MC68HC811E2V 40 to 105 MC68HC811E2M 40 to 125 MC68L11Ex 20 to 70 Operating voltage range Vpp 5 0 10 V 11 5 Thermal Characteristics Characteristic Symbol Value Unit Average junction temperature Ty Ta Pp x Oya C Ambient temperature Ta User determined Package thermal resistance junction to ambient 48 pin plastic DIP MC68HC811E2 only 50 56 pin plastic SDIP 50 52 plastic chip carrier 50 MM 52 pin plastic thin quad flat pack TQFP 85 64 pin quad flat pack 85 Pint Pro Total power dissipation Pp 273 W Device internal power dissipation PINT pin power dissipation Pio User determined Pp x TA 273 C A constant K W C OjAX Pp 1 This is an approximate value neglecting P yo 2 For most applications lt and can be neglected 3 K is a constant pertain
212. er SPCR SPIE Serial Peripheral Interrupt Enable Bit Set the SPE bit to 1 to request a hardware interrupt sequence each time the SPIF or MODF status flag is set SPI interrupts are inhibited if this bit is clear or if the bit in the condition code register is 1 0 SPI system interrupts disabled 1 SPI system interrupts enabled SPE Serial Peripheral System Enable Bit When the SPE bit is set the port D bit 2 3 4 and 5 pins are dedicated to the SPI function If the SPI is in the master mode and DDRD bit 5 is set then the port D bit 5 pin becomes a general purpose output instead of the SS input 0 SPI system disabled 1 SPI system enabled DWOM Port D Wired OR Mode Bit DWOM affects all port D pins 0 Normal CMOS outputs 1 Open drain outputs MSTR Master Mode Select Bit It is customary to have an external pullup resistor on lines that are driven by open drain devices 0 Slave mode 1 Master mode MC68HC11E Family Rev 4 Technical Data MOTOROLA Serial Peripheral Interface SPI 173 Serial Peripheral Interface SPI CPOL Clock Polarity Bit When the clock polarity bit is cleared and data is not being transferred the SCK pin of the master device has a steady state low value When CPOL is set SCK idles high Refer to Figure 8 2 and 8 5 Clock Phase and Polarity Controls CPHA Clock Phase Bit The clock phase bit in conjunction with the CPOL bit controls the clock data r
213. er Interrupt Mask Register 2 200 9 6 2 Timer Interrupt Flag Register 2 201 9 6 3 Pulse Accumulator Control Register 202 97 Computer Operating Properly COP Watchdog Function 203 98 Pubs Acoumulator 2 cients eee 203 9 8 1 Pulse Accumulator Control Register 205 9 8 2 Pulse Accumulator Count Register 206 9 8 3 Pulse Accumulator Status and Interrupt Bits 207 Section 10 Analog to Digital A D Converter TO TOMS rcm 209 102 JC Z oe REA 209 103 SIE aided dde de ab eee E 210 10 3 1 beeen ee 210 10 3 2 Analog Converter 212 212 10 24 Result Registers 212 10 3 5 Converter Clocks 213 10 3 6 Conversion Sequence 213 10 4 A D Converter Power Up and Clock Select 214 10 5 Conversion 215 10 6 Channel Assignments 216 10 7 Single Channel Operation 216 10 8 Multiple Channel Operation 217 10 9 Operation in Stop and Wait Modes 217 10 10 A D Control Status Register 218 10 11 A D Converter Result Registers 220 MC68HC11E Family Rev 4 Technical Data
214. eral purpose output a serial signal from the host can be connected to the pin AN1060 Rev 1 0 292 MOTOROLA TxD Pin AN1060 Rev 1 0 Application Note without resulting in output driver conflicts It may be important to consider what the existing logic will do with the SCI serial data instead of the signals that would have been produced by the PDO pin In systems where the PDO pin is used normally as a general purpose input the driver circuit that drives the PDO pin must be designed so that the serial data can override this driver or the driver must be disconnected during the bootstrap download A simple series resistor between the driver and the PDO pin solves this problem as shown in Figure 5 The serial data from the host computer can then be connected to the PDO RxD pin and the series resistor will prevent direct conflict between the host driver and the normal PDO driver CONNECTED ONLY DURING FROM BOOTLOADIN SYSTEM RS232 LEVEL SHIFTER MC68HC11 EXISTING CONTROL SIGNAL RxD PDO BEING USED aa AS INPUT EXISTING RESISTOR DRIVER Figure 5 Preventing Driver Conflict The bootloader program uses the PD1 TxD pin to send verification data back to the host computer To minimize the possibility of conflicts with circuitry connected to this pin port D is configured for wire OR mode by the bootloader program during initialization Since the wire OR configuration prevents the pin from driving
215. erial Peripheral Interface SPI System Errors direction register This sets the SS pin to act as a general purpose output rather than the dedicated input to the slave select circuit thus inhibiting the mode fault flag The other three lines are dedicated to the SPI whenever the serial peripheral interface is on The state of the master and slave CPHA bits affects the operation of SS CPHA settings should be identical for master and slave When CPHA 0 the shift clock is the OR of SS with SCK In this clock phase mode SS must go high between successive characters in an SPI message When CPHA 1 SS can be left low between successive SPI characters In cases where there is only one SPI slave MCU its SS line can be tied to Vss as long as only CPHA 1 clock mode is used 8 7 SPI System Errors Two system errors can be detected by the SPI system The first type of error arises in a multiple master system when more than one SPI device simultaneously tries to be a master This error is called a mode fault The second type of error write collision indicates that an attempt was made to write data to the SPDR while a transfer was in progress When the SPI system is configured as a master and the SS input line goes to active low a mode fault error has occurred usually because two devices have attempted to act as master at the same time In cases where more than one device is concurrently configured as a master there is a chance of
216. erstanding of latency and of the arbitration mechanism Refer to Section 5 Resets and Interrupts The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit during an ADD ABA or ADC instruction Otherwise the H bit is cleared Half carry is used during BCD operations 3 3 6 7 X Interrupt Mask X Technical Data The XIRQ mask X bit disables interrupts from the XIRQ pin After any reset X is set by default and must be cleared by a software instruction When an XIRQ interrupt is recognized the X and bits are set after the registers are stacked but before the interrupt vector is fetched After the interrupt has been serviced an RTI instruction is normally executed causing the registers to be restored to the values that were present before the interrupt occurred The X interrupt mask bit is set only by MC68HC11E Family Rev 4 52 Central Processor Unit CPU MOTOROLA Central Processor Unit CPU Data Types hardware RESET or XIRQ acknowledge X is cleared only by program instruction where the associated bit is 0 or RTI where bit 6 of the value loaded into the CCR from the stack has been cleared There is no hardware action for clearing X 3 3 6 8 STOP Disable S 3 4 Data Types Setting the STOP disable S bit prevents the STOP instruction from putting the M68HC11 into a low power stop condition If the STOP instruction is encountered by the CPU while the S bit
217. escription CONFIG Temperature Frequency MC Order Number 64 pin quad flat pack QFP 2 MHz MC68HC11E9BCFU2 BUFFALO ROM 0F 409 to 85 C 3 MHz MC68HC11E9BCFU3 2 MHz MC68HC11E1CFU2 409 to 85 C No ROM 0D 3 MHz MC68HC11E1CFU3 40 to 105 C 2 MHz MC68HC11E1VFU2 409 to 85 C 2 MHz MC68HC11E0CFU2 No ROM no EEPROM 0C 40 to 105 C 2 MHz MC68HC11E0VFU2 0 C to 70 C 3 MHz MC68HC711E20FU3 2 MHz MC68HC711E20CFU2 409 to 85 C 20 Kbytes OTPROM 0F 3 MHz MC68HC711E20CFU3 40 to 105 C 2 MHz MC68HC711E20VFU2 40 to 125 C 2 MHz MC68HC711E20MFU2 52 pin thin quad flat pack TQFP 2 MHz MC68HC11E9BCPB2 BUFFALO ROM 0F 409 to 85 C 3 MHz MC68HC11E9BCPB3 52 pin windowed ceramic leaded chip carrier CLCC 2 MHz MC68HC711E9CFS2 409 to 85 C 3 MHz MC68HC711E9CFS3 EPROM 0F 40 C to 105 C 2 MHz MC68HC711E9VFS2 40 to 125 C 2 MHz MC68HC711E9VFS2 0 C 70 3 MHz MC68HC711E20FS3 2 MHz MC68HC711E20CFS2 409 to 85 C 20 Kbytes EPROM 0F 3 MHz MC68HC711E20CFS3 40 C to 105 C 2 MHz MC68HC711E20VFS2 40 C to 125 C 2 MHz MC68HC711E20MFS2 MC68HC11E Family Rev 4 Technical Data MOTOROLA Ordering Information 263 Ordering Information Description CONFIG Temperature Frequency MC Order Number 48 pin dual in line package DIP MC68HC811E2 only 0 C to 70 C 2 MHz MC68HC811E2P2 40 C to 85 C 2 MHz MC68HC811E2CP2 No ROM 2 Kbytes EEPROM FF 40 C
218. et 0 0 0 0 0 0 0 1 Figure 4 12 RAM and Mapping Register INIT RAM 3 0 RAM Map Position Bits These four bits which specify the upper hexadecimal digit of the RAM address control position of RAM in the memory map RAM can be positioned at the beginning of any 4 Kbyte page in the memory map It is initialized to address 0000 out of reset Refer to Table 4 4 MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 89 Operating Modes Memory REG 3 0 64 Byte Register Block Position These four bits specify the upper hexadecimal digit of the address for the 64 byte block of internal registers The register block positioned atthe beginning of any 4 Kbyte page in the memory map is initialized to address 1000 out of reset Refer to Table 4 5 Table 4 4 RAM Mapping Table 4 5 Register Mapping RAM 3 0 Address REG 3 0 Address 0000 0000 0xFF 0000 0000 003F 0001 1000 1xFF 0001 1000 103F 0010 2000 2xFF 0010 2000 203F 0011 3000 3xFF 0011 3000 303F 0100 4000 4xFF 0100 4000 403F 0101 5000 5xFF 0101 5000 503F 0110 6000 6xFF 0110 6000 603F 0111 7000 7xFF 0111 7000 703F 1000 8000 8xFF 1000 8000 803F 1001 9000 9xFF 1001 9000 903F 1010 A000 AxFF 1010 A000 A03F 1011 B000 BxFF 1011 B000 BO3F 1100 C000 Cx
219. evel or are configured as high impedance inputs I O pins configured as high impedance inputs have port data that is indeterminate In port descriptions an l indicates this condition Port pins that are driven to a known logic level during reset are shown with a value of either 1 or 0 Some control bits are unaffected by reset Reset states for these bits are indicated with a U 6 3 Port A Port A shares functions with the timer system and has Address Read Write Reset Alternate function And or Technical Data Three input only pins Three output only pins Two bidirectional I O pins 1000 Bit 7 6 5 4 3 2 1 Bit 0 PAT PA6 PA5 4 PA2 1 PAQ 0 0 0 PAI 0C2 0C3 0 4 IC4 0C5 2 IC3 0 1 0 1 0 1 0 1 0 1 Indeterminate after reset Figure 6 1 Port A Data Register PORTA MC68HC11E Family Rev 4 134 Parallel Input Output I O Ports MOTOROLA Parallel Input Output I O Ports Port A Address 1026 Bit 7 6 5 4 3 2 1 Bit 0 Read Wii DDRA7 PAEWN PAMOD PEDGE DDRA3 14 05 RTR1 RTRO rite Reset 0 0 0 0 0 0 0 0 Figure 6 2 Pulse Accumulator Control Register PACTL DDRA7 Data Direction for Port A Bit 7 Overridden if an output compare function is configured to control the PA7 pin 0 Input 1 Output The pulse accumulator uses port A bit 7 as the PAI input but the pin c
220. evices 0 Port C outputs are normal CMOS outputs 1 Port C outputs are open drain outputs HNDS Handshake Mode Bit 0 Simple strobe mode 1 Full input or output handshake mode MC68HC11E Family Rev 4 Technical Data MOTOROLA Parallel Input Output I O Ports 141 Parallel Input Output I O Ports OIN Output or Input Handshake Select Bit HNDS must be set to 1 for this bit to have meaning 0 Input handshake 1 Output handshake PLS Pulsed Interlocked Handshake Operation Bit HNDS must be set to 1 for this bit to have meaning When interlocked handshake is selected strobe B is active until the selected edge of strobe A is detected 0 Interlocked handshake 1 Pulsed handshake Strobe B pulses high for two E clock cycles EGA Active Edge for Strobe A Bit 0 STRA falling edge selected high level activates port C outputs output handshake 1 STRA rising edge selected low level activates port C outputs output handshake INVB Invert Strobe B Bit 0 Active level is logic 0 1 Active level is logic 1 Technical Data MC68HC11E Family Rev 4 142 Parallel Input Output I O Ports MOTOROLA Parallel Input Output I O Ports Parallel Control Register Table 6 2 Parallel I O Control STAF Clearing HNDS OIN PLS EGA Port B Port C Sequence Read Simple PIOC with p sist on 5 pulses strobed STAF 1 0 X X b ahwaciveedaa on writes mode
221. exed operating mode port C pins are a multiplexed address data bus Refer to Table 2 1 for a functional description of the 40 port signals within different operating modes Terminate unused inputs and input output I O pins configured as inputs high or low In all operating modes port A can be configured for three timer input capture IC functions and four timer output compare OC functions An additional pin can be configured as either the fourth IC or the fifth OC Any port A pin that is not currently being used for a timer function can be used as either a general purpose input or output line Only port A pins have an associated data direction control bit that allows the pin to be selectively configured as input or output Bits DDRA7 and DDRAS located register control data direction for and PAG respectively All other port A pins are fixed as either input or output MC68HC11E Family Rev 4 Technical Data MOTOROLA Pin Descriptions 39 Pin Descriptions Technical Data Table 2 1 Port Signal Functions Single Chip and Expanded and Port Bit Bootstrap Modes Test Modes PA0 PA0 IC3 PA1 PA1 IC2 PA2 PA2 IC1 PA3 PA3 OC5 IC4 OC1 PA4 PA4 OC4 OC1 PA5 PA5 OC3 OC1 PA6 PA6 OC2 OC1 PA7 PA7 PAI OC1 PBO PBO ADDR8 PB1 PB1 ADDR9 PB2 PB2 ADDR10 PB3
222. for it the receiver activates the RWU function by using a software write to set the RWU bit Because setting RWU inhibits receiver related flags there is no further software overhead for the rest of this message When the next message begins its first character has its MSB set which automatically clears the RWU bit and enables normal character reception The first character whose MSB is set is also the first character to be received after wakeup because RWU gets cleared before the stop bit for that frame is serially received This type of wakeup allows messages to include gaps of idle time unlike the idle line method but MC68HC11E Family Rev 4 150 Serial Communications Interface SCI MOTOROLA Serial Communications Interface SCI SCI Error Detection there is a loss of efficiency because of the extra bit time for each character address bit required for all characters 7 7 5 Error Detection Three error conditions SCDR overrun received bit noise and framing can occur during generation of system interrupts Three bits OR NF and FE in the serial communications status register SCSR indicate if one of these error conditions exists The overrun error OR bit is set when the next byte is ready to be transferred from the receive shift register to the SCDR and the SCDR is already full RDRF bit is set When an overrun error occurs the data that caused the overrun is lost and the data that was already
223. for more information SMOD Special Mode Select Bit This bit reflects the inverse of the MODB input pin at the rising edge of reset Refer to Section 4 Operating Modes and On Chip Memory for more information MC68HC11E Family Rev 4 Technical Data MOTOROLA Resets and Interrupts 119 Resets and Interrupts MDA Mode Select A Bit The mode select bit reflects the status of the MODA input pin at the rising edge of reset Refer to Section 4 Operating Modes and On Chip Memory for more information IRVNE Internal Read Visibility Not E Bit The IRVNE control bit allows internal read accesses to be available on the external data bus during operation in expanded modes In single chip and bootstrap modes IRVNE determines whether the E clock is driven out an external pin For the MC68HC811E2 this bit is IRV and only controls internal read visibility Refer to Section 4 Operating Modes and On Chip Memory for more information PSEL 3 0 Priority Select Bits These bits select one interrupt source to be elevated above all other I bit related sources and can be written only while the bit in the CCR is set interrupts disabled Table 5 3 Highest Priority Interrupt Selection PSEL 3 0 Interrupt Source Promoted 0000 Timer overflow 0001 Pulse accumulator overflow 0010 Pulse accumulator input edge 001 1 SPI serial transfer complete 0100 SCI serial
224. gister CCR This 8 bit register contains Five condition code indicators C V Z N and H Two interrupt masking bits IRQ and XIRQ Astop disable bit S In the M68HC11 CPU condition codes are updated automatically by most instructions For example load accumulator A LDAA and store accumulator A STAA instructions automatically set or clear the N Z and V condition code flags Pushes pulls add B to X ABX add B to Y ABY and transfer exchange instructions do not affect the condition codes Refer to Table 3 2 which shows what condition codes are affected by a particular instruction 3 3 6 1 Carry Borrow C 3 3 6 2 Overflow V 3 3 6 3 Zero Z The C bit is set if the arithmetic logic unit ALU performs a carry or borrow during an arithmetic operation The C bit also acts as an error flag for multiply and divide operations Shift and rotate instructions operate with and through the carry bit to facilitate multiple word shift operations The overflow bit is set if an operation causes an arithmetic overflow Otherwise the V bit is cleared The Z bit is set if the result of an arithmetic logic or data manipulation operation is 0 Otherwise the Z bit is cleared Compare instructions do an internal implied subtraction and the condition codes including Z reflect the results of that subtraction A few operations INX DEX INY and DEY affect the Z bit and no other condition flags For these operations only
225. grammed by other means with a desired 12 Kbyte program in its EPROM and a small duplicator program in its EEPROM Alternately the ROM program in an MC68HC1 1E9 be copied into the EPROM of a target MC68HC711E9 by programming only the duplicator program into the EEPROM of the master MC68HC11E9 The master MCU is installed in the EVBU at socket U3 A blank MC68HC711E9 to be programmed is placed in the socket in the wire wrap area of the EVBU U6 With the Vpp power switch off power is applied to the EVBU system As power is applied to the EVBU the master MCU U3 comes out of reset in bootstrap mode Target MCU U6 is held in reset by the PB7 output of master MCU U3 The PB7 output of U3 is forced to 0 when U3 is reset The master MCU will later release the reset signal to the target MCU under software control The RxD and TxD pins of the target MCU U6 are high impedance inputs while U6 is in reset so they will not affect the TxD and RxD signals of the master MCU U3 while U3 is coming out of reset Since the target MCU is being held in reset with MODA and MODB at 0 it is configured for the PROG EPROM emulation mode and PB7 is the output enable signal for the EPROM data I O input output pins Pullup resistor R7 causes the port D pins including RxD and TxD to remain in the high impedance state so they do not interfere with the RxD and TxD pins of the master MCU as it comes out of reset As 03 leaves reset its mode pins select boo
226. he ADCTL bits determine whether conversions are performed on single or multiple channels 10 3 4 Result Registers Technical Data Four 8 bit registers ADR 4 1 store conversion results Each of these registers can be accessed by the processor in the CPU The conversion complete flag CCF indicates when valid data is present in the result registers The result registers are written during a portion of the system clock cycle when reads do not occur so there is no conflict MC68HC11E Family Rev 4 212 Analog to Digital A D Converter MOTOROLA Analog to Digital A D Converter Overview 10 3 5 A D Converter Clocks The CSEL bit in the OPTION register selects whether the A D converter uses the system E clock or an internal RC oscillator for synchronization When E clock frequency is below 750 kHz charge leakage in the capacitor array can cause errors and the internal oscillator should be used When the RC clock is used additional errors can occur because the comparator is sensitive to the additional system clock noise 10 3 6 Conversion Sequence A D converter operations are performed in sequences of four conversions each A conversion sequence can repeat continuously or stop after one iteration The conversion complete flag CCF is set after the fourth conversion in a sequence to show the availability of data in the result registers Figure 10 3 shows the timing of a typical sequence Synchronization is referenced to the
227. he CPU registers are pushed onto the stack and execution continues at the address specified by the vector for the interrupt At the end of the interrupt service routine an return from interrupt RTI instruction is executed The RTI instruction causes the saved registers to be pulled off the stack in reverse order Program execution resumes at the return address Certain instructions push and pull the A and B accumulators and the X and Y index registers and are often used to preserve program context For example pushing accumulator A onto the stack when entering a subroutine that uses accumulator and then pulling accumulator off the stack just before leaving the subroutine ensures that the contents of a register will be the same after returning from the subroutine as it was before starting the subroutine 3 3 5 Program Counter PC Technical Data The program counter a 16 bit register contains the address of the next instruction to be executed After reset the program counter is initialized from one of six possible vectors depending on operating mode and the cause of reset See Table 3 1 Table 3 1 Reset Vector Comparison Mode POR or RESET Pin Clock Monitor COP Watchdog Normal FFFE FFFC D FFFA B Test or Boot BFFE F BFFC D B MC68HC11E Family Rev 4 50 Central Processor Unit CPU MOTOROLA Central Processor Unit CPU CPU Registers 3 3 6 Condition Code Re
228. he first character received MOTOROLA 285 Application Note The SCI receiver and transmitter are enabled The receiver is required by the bootloading process and the transmitter is used to transmit data back to the host computer for optional verification The last item in the initialization is to set an intercharacter delay constant used to terminate the download when the host computer stops sending data to the MC68HC711E9 This delay constant is stored in the timer output compare 1 TOC1 register but the on chip timer is not used in the bootloader program This example illustrates the extreme measures used in the bootloader firmware to minimize memory usage However such measures are not usually considered good programming technique because they are misleading to someone trying to understand the program or use it as an example After initialization a break character is transmitted 3 by the SCI By connecting the TxD pin to the RxD pin with a pullup because of port D wired OR mode this break will be received as a 00 character and cause an immediate jump 4 to the start of the on chip EEPROM B600 in the MC68HC711E9 This feature is useful to pass control to a program in EEPROM essentially from reset Refer to Common Bootstrap Mode Problems before using this feature If the first character is received as FF the baud rate is assumed to be the default rate 7812 baud at a 2 MHz E clock rate If FF was sent at 1200 baud by
229. he string FF synchronizes the bootloader in the MC68HC711E9 to 1200 baud The entire string is simply sent to the COM port by PRINTing the string This is possible since the string is actually queued in BASIC s COM buffer and the operating system takes care of sending the bytes out one at a time The M68HC11 echoes the AN1060 Rev 1 0 304 MOTOROLA Application Note data received for verification No automatic verification is provided though the data is printed to the screen for manual verification Once the MCU has received this bootloaded code the bootloader automatically jumps to it The small bootloaded program in turn includes a jump to the EPROM programming routine in the boot ROM Refer to the previous explanation of the EPROM Programming Utility for the following discussion The host system sends the first byte to be programmed through the COM port to the SCI of the MCU The SCI port onthe MCU buffers one byte while receiving another byte increasing the throughput of the EPROM programming operation by sending the second byte while the first is being programmed When the first byte has been programmed the MCU reads the EPROM location and sends the result back to the host system The host then compares what was actually programmed to what was originally sent A message indicating which byte is being verified is displayed in the lower half of the screen If there is an error it is displayed at the top of the screen
230. ical Data The MOSI line is the second of the two unidirectional serial data signals It is an output from a master device and an input to a slave device The master device places data on the MOSI line half cycle before the clock edge that the slave device uses to latch the data SCK an input to a slave device is generated by the master device and synchronizes data movement in and out of the device through the MOSI and MISO lines Master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles Four possible timing relationships can be chosen by using control bits CPOL and CPHA in the serial peripheral control register SPCR Both master and slave devices must operate with the same timing The SPI clock rate select bits SPR 1 0 in the SPCR of the master device select the clock rate In a slave device SPR 1 0 have no effect on the operation of the SPI The slave select SS input of a slave device must be externally asserted before a master device can exchange data with the slave device SS must be low before data transactions and must stay low for the duration of the transaction The SS line of the master must be held high If it goes low a mode fault error flag MODF is set in the serial peripheral status register SPSR To disable the mode fault circuit write a 1 in bit 5 of the port D data MC68HC11E Family Rev 4 170 Serial Peripheral Interface SPI MOTOROLA S
231. ily Rev 4 Technical Data MOTOROLA Analog to Digital A D Converter 211 Analog to Digital A D Converter 10 3 2 Analog Converter 10 3 3 Digital Control Conversion of an analog input selected by the multiplexer occurs in this block It contains a digital to analog capacitor DAC array comparator and a successive approximation register SAR Each conversion is a sequence of eight comparison operations beginning with the most significant bit MSB Each comparison determines the value of a bit in the successive approximation register The DAC array performs two functions It acts as a sample and hold circuit during the entire conversion sequence and provides comparison voltage to the comparator during each successive comparison The result of each successive comparison is stored inthe SAR When a conversion sequence is complete the contents of the SAR are transferred to the appropriate result register A charge pump provides switching voltage to the gates of analog switches in the multiplexer Charge pump output must stabilize between 7 and 8 volts within up to 100 us before the converter can be used The charge pump is enabled by the ADPU bit in the register All A D converter operations are controlled by bits in register ADC TL In addition to selecting the analog input to be converted ADC TL bits indicate conversion status and control whether single or continuous conversions are performed Finally t
232. in EVBU MCU LDAA RESET STAA PORTB Release reset to target MCU BRCLR SCSR RDRF WT4BRK Loop till char received LDAA Leading char for bootload STAA SCDR to target MCU LDX BLPROG Point at program for target BSR SEND1 Bootload to target CPX ENDBPR Past end BNE BLLOOP Continue till all sent Delay for about 4 char times to allow boot related SCI communications to finish before clearing Rx related flags DLYLP LDX 1703 of 6 cyc loops DEX 3 BNE DLYLP 3 Total loop time 6 cyc LDAA SCSR Read status RDRF will be set LDAA SCDR Read SCI data reg to clear RDRF MOTOROLA 299 Application Note 50 51 Now wait for character from target to indicate it s ready for 52 data to be programmed into EPROM 53 B627 132E20FC WT4FF BRCLR SCSR RDRF WT4FF Wait for RDRF 54 B62B 962F LDAA SCDR Clear RDRF don t need data 55 B62D 000 LDX EPSTRT Point at start of EPROM 56 Handle turn on of 57 B630 18CE523D WT4VPP LDY 21053 Delay counter about 200ms 58 B634 150402 BCLR PORTB RED Turn off RED LED 59 637 960A DLYLP2 LDAA PORTE 3 Wait for to be 60 B639 2AF5 BPL WI4VPP 3 Vpp sense is on port E MSB 61 6 140402 BSET PORTB RED 6 Turn on RED LED 62 B63E 1809 DEY 4
233. ine SBA Subtract B from A B A INH 10 2 SBCA Subtract with 82 2 Carry from A A DIR 92 dd 3 A EXT B2 hh Il 4 A IND X A2 ff 4 A IND Y 18 A2 5 SBCB Subtract with C2 ii 2 A A A A Carry from B B DIR D2 dd 3 B EXT F2 ihh Il 4 B IND X E2 ff 4 B IND Y 18 E2 ff 5 SEC Set Carry 1 gt C INH 00 2 1 SEI Set Interrupt Texl INH OF 2 1 Mask SEV Set Overflow 1 0B 2 1 Flag STAA opr Store A M A DIR 97 dd 3 A A 0 Accumulator A EXT B7 hh Il 4 A A IND X 4 IND Y 18 A7 5 STAB opr Store DIR D7 3 A A 0 Accumulator B EXT F7 hh Il 4 B B IND X E7 4 B IND Y 18 E7 5 STD opr Store A gt M B gt M 1 DIR DD dd 4 A A 0 Accumulator EXT FD hh Il 5 D IND X ED 5 IND Y 18 ED 6 STOP Stop Internal 2 Clocks STS opr Store Stack SP gt M M 1 DIR 9F dd 4 A A 0 Pointer EXT BF hh Il 5 IND X AF 5 IND Y 18 AF 6 STX opr Store Index IX gt M M 1 DIR DF 4 A A 0 Register X EXT FF hh Il 5 IND X EF 5 IND Y CD EF 6 STY opr Store Index Y gt M M 1 DIR 18 DF 5 0 Register Y EXT 18 FF hh Il 6 IND X 1A EF 6 IND Y 18 EF 6 SUBA opr Subtract gt IMM 80 jii 2 A A A A Memory from A DIR 90 dd 3 A A EXT BO hh Il 4 A IND X 0 4 IND Y 18 AO 5
234. ing System 177 Section 10 Analog to Digital A D Converter 209 Section 11 Electrical Characteristics 221 Section 12 Mechanical Data 253 Section 13 Ordering Information 261 Appendix A Development Support 269 Appendix B EVBU Schematic 275 MC68HC11E Family Rev 4 Technical Data MOTOROLA List of Sections 5 List of Sections AN1060 M68HC11 Bootstrap Mode 277 EB184 Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR 323 EB188 Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR 327 EB296 Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU 331 Technical Data MC68HC11E Family Rev 4 6 List of Sections MOTOROLA Technical Data M68HC11E Family 1 1 1 2 1 3 1 4 2 1 Ze 2 3 2 4 2 5 2 6 27 2 8 2 9 2 10 2 11 2 12 2 13 2 13 1 2 13 2 2 13 3 2 13 4 2 13 5 MC68HC11E Family Rev 4 Table of Contents Section 1 General Description UI OTRO kaba 23 Introduction 23 FeatureSs 24 T 25 sensed aes 27 p jess
235. ing cold starts Refer to Figure 2 6 External Reset Circuit NOTE Itis important to protect the MCU during power transitions Most M68HC11 systems need an external circuit that holds the RESET pin low whenever Vpp is below the minimum operating level This external voltage level detector or other external reset circuits are the usual source of reset in a system 5 3 2 External Reset RESET The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than two E clock cycles after an internal device releases reset When a reset condition is sensed the RESET pin is driven low by an internal device for four E clock cycles then released Two E clock cycles later it is sampled If the pin is still held low the CPU assumes that an external reset has occurred If the pin is high it indicates that the reset was initiated internally by either the COP system or the clock monitor CAUTION Do not connect an external resistor capacitor RC power up delay circuit to the reset pin of M68HC11 devices because the circuit charge time constant can cause the device to misinterpret the type of reset that occurred MC68HC11E Family Rev 4 Technical Data MOTOROLA Resets and Interrupts 109 Resets and Interrupts 5 3 3 Computer Operating Properly COP Reset The MCU includes a COP system to help protect against software failures When the COP is enabled the software is
236. ing to the device Solve for K with a known T4 and a measured Pp at equilibrium Use this value of K to solve for Pp and iteratively for any value of TA MC68HC11E Family Rev 4 Technical Data MOTOROLA Electrical Characteristics 223 11 6 DC Electrical Characteristics Electrical Characteristics Characteristics Symbol Min Max Unit Output voltage 2 L V All outputs except XTAL OM m 0 1 All outputs except XTAL RESET and MODA 0 1 Output high voltage 0 8 mA Vpp 45V Vou Vpp 0 8 V All outputs except XTAL RESET and MODA Output low voltage lLoad 1 6mA VoL 0 4 V All outputs except XTAL Input high voltage 0 7 x Vpop Vpp 0 3 All inputs except RESET V V V RESET 0 8 x DD DD 0 3 Input low voltage all inputs Vsg 0 3 0 2 x Vpp V I O ports 3 state leakage Vin Vin or Vip l A PA7 PC 7 0 PD 5 0 AS STRA MODA LIR RESET Input leakage current Vin oF Vss lin B i 2 0 IRQ 10 XIRQ EPROM based devices RAM standby voltage power down Vsp 4 0 Vpp V RAM standby current power down Isp 10 Input capacitance PA 2 0 PE 7 0 IRQ XIRQ EXTAL ze Cin 8 pF 7 PC 7 0 PD 5 0 AS STRA MODA LIR RESET 12 Output load capacitance All outputs except PD 4 1 CL 90 pF
237. input pin typically 4 7 There must also be an interlock mechanism at each interrupt source so that the source holds the interrupt line low until the MCU recognizes and acknowledges the interrupt request If one or more interrupt sources are still pending after the MCU services a request the interrupt line will still be held low and the MCU will be interrupted again as soon as the interrupt mask bit in the MCU is cleared normally upon return from an interrupt Refer to Section 5 Resets and Interrupts Vppr is the input for the 12 volt nominal programming voltage required for EPROM OTPROM programming On devices without EPROM OTPROM this pin is only an XIRQ input 2 9 MODA and MODB MODA LIR and During reset MODA and MODB select one of the four operating modes Single chip mode e Expanded mode Test mode Bootstrap mode Refer to Section 4 Operating Modes and On Chip Memory Afterthe operating mode has been selected the load instruction register LIR pin provides an open drain output to indicate that execution of an instruction has begun A series of E clock cycles occurs during execution of each instruction The LIR signal goes low during the first E clock cycle of each instruction opcode fetch This output is provided for assistance in program debugging Vsrpy pin is used to input random access memory RAM standby power When the voltage on this pin is more than one MOS threshold a
238. ion 1 2 1 2 LSB Difference between the actual input voltage Absolute and the full scale weighted equivalent of the 1 2 LSB accuracy binary output code all error sources included Conversion Analog input voltage range VRL VRH VRH V range VRH Maximum analog reference voltage VRL 0 1 Vpp 40 1 V VRL Minimum analog reference voltage Vss 0 1 AVR Minimum difference between Vay and Vg 2 3 V Total time to perform a single A D conversion Conversion ila E clock 32 Internal RC oscillator 32 32 us Conversion result never decreases with Monotonicity increase in input voltage has no missing Guaranteed codes 296 Conversion result when Vi VRL 00 Hex reading Conversion result when Vi Vay FF FF reading Sample Analog input acquisition sampling time acquisition E clock 12 time Internal RC oscillator 12 12 us Sample hold Input capacitance during sample u __ capacitance PE 7 0 cU pleat pn Input leakage on A D pins Input leakage PE 7 0 400 400 nA VRH 1 0 1 0 1 Vpp 5 0 10 Vss 0 Ta to T4 750 kHz lt E 3 0 MHz unless otherwise noted 2 Source impedances greater than 10 affect accuracy adversely because of input leakage 3 Performance verified down
239. iplexed address data signals During the address portion of each MCU cycle bits 7 0 of the address are output on the PC7 PCO pins During the data portion of each MCU cycle E high PC7 PCO bidirectional data signals DATA7 DATAO The direction of data at the port C pins is indicated by the R W signal The CWOM control bit in the PIOC register disables the port C P channel output driver CWOM simultaneously affects all eight bits of port C Because the N channel driver is not affected by CWOM setting CWOM causes port C to become an open drain type output port suitable for wired OR operation In wired OR mode When a port C bit is at logic level 0 it is driven low by the N channel driver When a port C bit is at logic level 1 the associated pin has high impedance as neither the N channel nor the P channel devices are active Itis customary to have an external pullup resistor on lines that are driven by open drain devices Port C can only be configured for wired OR operation when the MCU is in single chip mode Refer to Section 6 Parallel Input Output I O Ports for additional information about port C functions MC68HC11E Family Rev 4 42 Pin Descriptions MOTOROLA Pin Descriptions Port Signals 2 13 4 Port D Pins PD5 PDO be used for general purpose I O signals These pins alternately serve as the serial communication interface SCI and serial peripheral interface SPI signals when those subsy
240. is set it is treated as a no operation NOP instruction and processing continues to the next instruction S is set by reset STOP is disabled by default The M68HC11 CPU supports four data types 1 Bit data 2 8 bit and 16 bit signed and unsigned integers 3 16 bit unsigned fractions 4 16 bit addresses A byte is eight bits wide and can be accessed at any byte location A word is composed of two consecutive bytes with the most significant byte at the lower value address Because the M68HC11 is an 8 bit CPU there are no special requirements for alignment of instructions or operands 3 5 Opcodes and Operands The M68HC11 Family of microcontrollers uses 8 bit opcodes Each opcode identifies a particular instruction and associated addressing mode to the CPU Several opcodes are required to provide each instruction with a range of addressing capabilities Only 256 opcodes would be available if the range of values were restricted to the number able to be expressed in 8 bit binary numbers MC68HC11E Family Rev 4 Technical Data MOTOROLA Central Processor Unit CPU 53 Central Processor Unit CPU A 4 page opcode map has been implemented to expand the number of instructions An additional byte called a prebyte directs the processor from page 0 of the opcode map to one of the other three pages As its name implies the additional byte precedes the opcode A complete instruction consists of a prebyte if any an opcode
241. ister EPROG See page 101 Reserved 1 MC68HC711E20 only Figure 4 7 Register and Control Bit Assignments Sheet 7 of 8 Technical Data Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Bit 7 6 5 4 3 2 1 Bit 0 R7 T7 R6 TT6 R5 T5 R4 T4 R3 T3 R2 T2 Indeterminate after reset CCF SCAN MULT CD CC CB CA 0 0 Indeterminate after reset Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset PTCON BPRT3 BPRT2 BPRT1 BPRTO 0 0 0 1 1 1 1 1 MBE ELAT EXCOL EXROW 1 TO PGM 0 0 0 0 0 0 0 0 R R R R R R R R Unimplemented R Reserved U Unaffected Indeterminate after reset MC68HC11E Family Rev 4 78 Operating Modes and On Chip Memory MOTOROLA Addr Register Name 1038 Reserved System Configuration Options 1039 Register OPTION See page 91 Arm Reset COP Timer 103A Circuitry Register COPRST See page 111 EPROM and EEPROM 103B Programming Control Register PPROG See page 95 Highe
242. ister Y EORA opr Exclusive ORA 88 2 0 with Memory A DIR 98 3 A EXT B8 hh Il 4 A IND X A8 4 A IND Y 18 A8 5 EORB opr Exclusive OR B B M gt B B IMM C8 jii 2 0 with Memory B DIR D8 dd 3 B EXT F8 ihh Il 4 B IND X 8 4 IND Y 18 E8 5 FDIV Fractional IX r D INH 03 41 A A Divide 16 by 16 IDIV Integer Divide D IX gt IX r gt D INH 02 41 A 0 16 by 16 INC opr Increment M 1 M EXT 7C hh Il 6 lt A A A Memory Byte IND X 6C ff 6 IND Y 18 6C A 1 A A INH 4 2 MC68HC11E Family Rev 4 Technical Data MOTOROLA Central Processor Unit CPU Central Processor Unit CPU Table 3 2 Instruction Set Sheet 4 of 7 Mnemoni Operation Descripti n Addressing Instruction Condition Codes emonte perauo eser puo Mode Opcode Operand Cycles X H z Incremen B 1 gt B B INH 5C 2 A A A Accumulator B INS Incremen SP 1 SP INH 31 3 Stack Pointer INX Incremen IX 1 gt IX INH 08 3 Index Register X INY Incremen IY 212 INH 18 08 4 Index Register Y JMP opr Jump See Figure 3 2 EXT 7E hh II 3 IND X 6E 3 IND Y 18 6E 4 JSR
243. it 12 Bit 11 Bit 10 Bit9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit2 Bit1 Bit O 1 1 1 1 1 1 1 1 Bit15 Bit14 Bit 13 Bit 12 Bit11 Bit 10 Bit 9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit2 Bit1 Bit 0 1 1 1 1 1 1 1 1 Unimplemented R Reserved U Unaffected Indeterminate after reset Technical Data MOTOROLA Operating Modes and On Chip Memory 75 Operating Modes Memory Addr 101E 101F 1020 1021 1022 1023 1024 1025 1026 Register Name Timer Input Capture 4 O utput Compare 5 Register High TI4 05 See page 186 Timer Input Capture 4 O utput Compare 5 Register Low TI4 05 See page 186 Timer Control Register 1 TCTL1 See page 194 Timer Control Register 2 TCTL2 See page 183 Timer Interrupt Mask 1 Register TMSK1 See page 195 Timer Interrupt Flag 1 TFLG1 See page 196 Timer Interrupt Mask 2 Register TMSK2 See page 196 Timer Interrupt Flag 2 TFLG2 See page 201 Pulse Accumulator Control Register PACTL See page 202 Figure 4 7 Register and Control Bit Assignments Sheet 5 of 8 Technical Data Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Bit
244. it data character Bit 5 Unimplemented Always reads 0 M Mode Bit select character format 0 Start bit 8 data bits 1 stop bit 1 Start bit 9 data bits 1 stop bit WAKE Wakeup by Address Mark ldle Bit 0 Wakeup by IDLE line recognition 1 Wakeup by address mark most significant data bit set Bits 2 0 Unimplemented Always read 0 MC68HC11E Family Rev 4 Technical Data MOTOROLA Serial Communications Interface SCI 153 Serial Communications Interface SCI 7 8 3 Serial Communications Control Register 2 The SCCR2 register provides the control bits that enable or disable individual SCI functions Address 1020 Bit 7 6 5 4 3 2 1 Bit 0 Read TIE TCIE RIE ILIE TE RE RWU SBK Write Reset 0 0 0 0 0 0 0 0 Figure 7 5 Serial Communications Control Register 2 SCCR2 TIE Transmit Interrupt Enable Bit 0 TDRE interrupts disabled 1 SCI interrupt requested when TDRE status flag is set TCIE Transmit Complete Interrupt Enable Bit 0 TC interrupts disabled 1 SCI interrupt requested when TC status flag is set RIE Receiver Interrupt Enable Bit 0 RDRF and OR interrupts disabled 1 SCI interrupt requested when RDRF flag or the OR status flag is set ILIE Idle Line Interrupt Enable Bit 0 IDLE interrupts disabled 1 SCI interrupt requested when IDLE status flag is set TE Transmitter Enable Bit When TE goes from 0 to 1 one unit of i
245. l Branch if not Z 0 REL 26 3 Zero BPL rel Branch if Plus 2 0 REL 2 3 BRA rel Branch Always 1 1 REL 20 3 BRCLR opr Branch if Memm 0 DIR 13 dd mm rr 6 msk Bit s Clear IND X 1F mm rr 7 rel IND Y 18 1F mm rr 8 BRN rel Branch Never 1 0 REL 21 rr 3 BRSET opr Branch if Bit s 0 DIR 12 dd mm rr 6 msk Set IND X 1E mm rr 7 rel IND Y 18 1E mm rr 8 BSET opr Set Bit s DIR 14 dd mm 6 A A 0 msk IND X 1 7 IND Y 18 1 mm 8 BSR rel Branch to See Figure 3 2 REL 8D 6 Subroutine BVC rel Branch if V 0 REL 28 3 Overflow Clear BVS rel Branch if V 1 REL 29 3 Overflow Set CBA Compare A to B A B INH 11 2 A A A A CLC Clear Carry Bit 02C INH 0C 2 0 CLI Clear Interrupt 0 INH 0 2 0 Mask CLR opr Clear Memory 02M EXT hh Il 6 La 0 1 0 0 Byte IND X 6F 6 IND Y 18 6F 7 CLRA Clear 02A A INH 4F 2 0 1 0 0 Accumulator CLRB Clear 0 B B INH 5F 2 1 0 0 Accumulator CLV Clear Overflow 02V INH 0A 2 0 Flag CMPA opr Compare A to A M A IMM 81 ji 2 DIR 91 3 A EXT B1 hh Il 4 A IND X A1 4 A IND Y 18 A1 ff 5 Technical Data MC68HC11E Family Rev 4 58 Central Processor Unit CPU MOTOROLA Central Processor Unit CPU Instruction Set Table 3 2 Instruction Set Sheet 3 of 7
246. l Clock Input ATALand EXTAL 35 CE IB 14 Uo CREE EO ea 36 Interrupt Request IRQ 36 Non Maskable Interrupt 36 MODA and MODB MODA LIR and 37 VnL and TI 38 SIP A TIT 38 38 OIL SIN P 39 i o f ee re ee kaa 39 gi lk TENE TT 41 I ou dried dd d ee oed ied ird de ded o CR dd 42 E o og Kae Reo ee ees 43 F Io as pawaspa qu aes RUE E Ado acd atat 43 Technical Data MOTOROLA Pin Descriptions 27 Pin Descriptions 2 2 Introduction Technical Data M68HC11 E series MCUSs are available packaged in 52 pin plastic leaded chip carrier PLCC 52 pin windowed ceramic leaded chip carrier CLCC 52 pin plastic thin quad flat pack 10 mm x 10 mm TQFP 64 pin quad flat pack QFP 48 pin plastic dual in line package DIP MC68HC811E2 only 56 pin plastic shrink dual in line package 070 inch lead spacing SDIP Most pins on these MCUS serve two or more functions as described in the following paragraphs Refer to Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 and Figure 2 5 which show the M68HC11 E series pin assignments for the PLCC CLCC QFP TQFP SDIP and DIP packages 46 PE5 AN5 45 1 44 PE4 AN4 43 PEO ANO 42 PB
247. l Data ie lla ea 253 52 Pin Plastic Leaded Chip Carrier Case 778 254 52 Pin Windowed Ceramic Leaded Chip Carrier Case 778 255 64 Pin Quad Flat Pack Case 840C 256 52 Pin Thin Quad Flat Pack Case 848D 257 56 Pin Dual in Line Package Case 859 258 48 Pin Plastic DIP Case 767 259 M68HC11E series microcontrollers are available MC68HC11E Family Rev 4 52 pin plastic leaded chip carrier PLCC 52 pin windowed ceramic leaded chip carrier CLCC 64 pin quad flat pack QFP 52 pin thin quad flat pack TQFP 56 pin shrink dual in line package with 070 inch lead spacing SDIP 48 pin plastic DIP 100 inch lead spacing MC68HC811E2 only Technical Data MOTOROLA Mechanical Data 253 Mechanical Data 12 3 52 Pin Plastic Leaded Chip Carrier Case 778 0 007 0 18 T L MO NO U 0 007 0 1885 L MO tO _ G1 0010 025 9 T LM VIEW D D L MO NO 0 007 0 18 T MOLD 0 007 0 18 QQ N 2 0 004 0 100 SEATING PLANE 0 010025 T
248. l RTII PAOVI PAII PRI PRO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 27 Timer Interrupt Mask 2 Register TMSK2 Address 1025 Bit 7 6 5 4 3 2 1 Bit 0 Read TOF RTIF PAOVF PAIF Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 28 Timer Interrupt Flag 2 Register TFLG2 PAOVI and PAOVF Pulse Accumulator Interrupt Enable and Overflow Flag The PAOVF status bit is set each time the pulse accumulator count rolls over from FF to 00 To clear this status bit write a 1 in the corresponding data bit position bit 5 of the TFLG2 register The control bit allows configuring the pulse accumulator overflow for polled or interrupt driven operation and does not affect the state of PAOVF When PAOVI is 0 pulse accumulator overflow interrupts are inhibited and the system operates in a polled mode which requires that PAOVF be polled by user software to determine when an overflow has occurred When the PAOVI control bit is set a hardware MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 207 Timing System Technical Data interrupt request is generated each time PAOVF is set Before leaving the interrupt service routine software must clear PAOVF by writing to the TFLG2 register and PAIF Pulse Accumulator Input Edge Interrupt Enable Bit and Flag The PAIF status bit is automatically set each time a selected edge is det
249. l Register 2 SCCR2 154 Serial Communications Status Register SCSR 155 Baud Rate Register 157 MC68HC11E Family Rev 4 18 List of Figures MOTOROLA Figure 7 8 p 7 10 8 2 8 3 8 4 8 5 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 9 10 9 11 8 12 9 13 9 14 8 15 9 16 9 18 9 19 9 20 9 21 9 22 9 23 9 24 MC68HC11E Family Rev 4 Title SCI Baud Rate Generator Block Diagram MC68HC 7 11E20 SCI Baud Rate Generator Block Diagram Interrupt Source Resolution Within SCI SPI Block Diagram Transiter FORNAL uud peeked eoe Serial Peripheral Control Register SPCR Serial Peripheral Status Register SPSR Serial Peripheral Data I O Register SPDR Timer Clock Divider Chains Capture Compare Block Diagram Timer Control Register 2 2 Timer Input Capture 1 Register Pair TIC1 Timer Input Capture 2 Register Pair 2 Timer Input Capture Register Pair Timer Input Capture 4 Output Compare 5 Register Pair TIMO5 Timer Output Compare 1 Register Pair TOC1 Timer Output Compare 2 Register Pair TOC2 Timer Output Compare 3 Register Pair TOC3 Timer Output Compare 4 Register Pair TOC4 Timer Compare Force Register CFORC Output Compare 1 Mask Register OC1M
250. ltage on the previously converted channel A charge share situation exists between the internal DAC capacitance and the external circuit capacitance Although the amount of charge involved is small the rate at which it is repeated is every 64 us for an E clock of 2 MHz The RC charging rate of the external circuit must be balanced against this charge sharing effect to avoid errors in accuracy Refer M68HC1 1 Reference Manual Motorola document order number M68HC 1 1 RM AD for further information CD CA Channel Selects D A Bits Refer to Table 10 2 When a multiple channel mode is selected MULT 1 the two least significant channel select bits CB and CA have no meaning and the CD and CC bits specify which group of four channels is to be converted Table 10 2 A D Converter Channel Selection Channel Select Result ADRx IB Control Bits Channel Signal if MULT 1 CD CC CB CA 0000 ANO ADR1 0001 AN1 ADR2 0010 AN2 ADR3 0011 AN3 ADR4 0100 AN4 ADR1 0101 AN5 ADR2 0110 AN6 ADR3 0111 AN7 ADR4 10XX Reserved 1100 Vg ADR1 1101 ADR2 1110 20 ADR3 1111 Reserved ADR4 1 Used for factory testing MC68HC11E Family Rev 4 Technical Data MOTOROLA Analog to Digital A D Converter 219 Analog to Digital A D Converter 10 11 A D Converter Result Registers These read only registers hold an 8 bit conversion result Writes to these r
251. lthough RWU be cleared by a software write to SCCR2 to do so would be unusual Normally RWU is set by software and is cleared automatically with hardware Whenever a new message begins logic alerts the sleeping receivers to wake up and evaluate the initial character of the new message Two methods of wakeup are available ldle line wakeup Address mark wakeup During idle line wakeup a sleeping receiver awakens as soon as the RxD line becomes idle In the address mark wakeup logic 1 in the most significant bit MSB of a character wakes up all sleeping receivers Technical Data MC68HC11E Family Rev 4 148 Serial Communications Interface SCI MOTOROLA Serial Communications Interface SCI Wakeup Feature RECEIVER BAUD RATE CLOCK DDDO 216 10 11 BIT SEE NOTE Rx SHIFT REGISTER PDO PIN BUFFER DATA RxD AND CONTROL RECOVERY DISABLE DRIVER RE WAKEUP LOGIC READ ONLY SCCR1 SCICONTROL 1 SCSR SCISTATUS 1 pe SCDR RxBUFFER SCCR2 SCICONTROL2 SCI Tx SCIINTERRUPT REQUESTS REQUEST INTERNAL DATA BUS Note Refer to Figure B 1 EVBU Schematic Diagram for an example of connecting RxD to a PC Figure 7 2 SCI Receiver Block Diagram MC68HC11E Family Rev 4 Technical Data MOTOROLA Serial Communications Interface SCI 149 Serial Communications Interface 5 7 6 1 Idle Line Wakeup To use the receiver wakeup method establish a software addressing scheme to allow the tr
252. me trace data as raw data disassembled instructions raw data and disassembled instructions or assembly language source code Four hardware triggers for commencing trace and to provide breakpoints Nine triggering modes Asmany as 8190 pre or post trigger points for trace data 16 general purpose logic clips four of which be used to trigger the bus state analyzer sequencer 16 bit time tag or an optional 24 bit time tag that reduces the logic clips traced from 16 to eight Four data breakpoints hardware breakpoints MC68HC11E Family Rev 4 Technical Data MOTOROLA Development Support 271 Development Support Hardware instruction breakpoints over either the 64 Kbyte M68HC11 memory map or over a 1 Mbyte bank switched memory map 32 real time variables nine of which can be displayed in the variables window These variables may be read or written while the MCU is running 32 bytes of real time memory can be displayed in the memory window This memory may be read or written while the MCU is running 64 Kbytes of fast emulation memory SRAM Current limited target input output connections Six software selectable oscillator clock sources five internally generated frequencies and an external frequency via a bus analyzer logic clip Command and response logging to MS DOS disk files to save session history SCRIPT command for automatic execution of a sequence of MMDS11 c
253. mer Output Compare 3 Register Low Address 101B Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 Figure 9 10 Timer Output Compare 3 Register Pair TOC3 Register name Timer Output Compare 4 Register High Address 101C Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 Register name Timer Output Compare 4 Register Low Address 101D Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 Figure 9 11 Timer Output Compare 4 Register Pair TOC4 MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 189 Timing System 9 5 2 Timer Compare Force Register The CFORC register allows forced early compares FOC 1 5 correspond to the five output compares These bits are set for each output compare that is to be forced The action taken as a result of a forced compare is the same as if there were a match between the OCx register and the free running counter except that the corresponding interrupt status flag bits are not set The forced channels trigger their programmed pin actions to occur at the next timer count transition after the write to CFORC The CFORC bits should not be used on an output compare function that is programmed to
254. mpare register that represents the time the leading edge of the pulse is to occur The output compare circuit is configured to set the MC68HC11E Family Rev 4 186 Timing System MOTOROLA Timing System Output Compare appropriate output either high or low depending on the polarity of the pulse being produced After a match occurs the output compare register is reprogrammed to change the output pin back to its inactive level at the next match A value representing the width of the pulse is added to the original value and then written to the output compare register Because the pin state changes occur at specific values of the free running counter the pulse width can be controlled accurately at the resolution of the free running counter independent of software latencies To generate an output signal of a specific frequency and duty cycle repeat this pulse generating procedure The five 16 bit read write output compare registers are TOC1 TOC2 TOC3 TOC4 and the TI4 O5 TI4 O5 functions under software control as either 4 or OC5 Each of the registers is set to FFFF on reset A value written to an OC register is compared to the free running counter value during each E clock cycle If a match is found the particular output compare flag is set in timer interrupt flag register 1 TFLG1 If that particular interrupt is enabled in the timer interrupt mask register 1 TMSK1 an interrupt is generated In additio
255. ms keeping characters close enough together to avoid tripping the end of download detect mechanism Using 1200 as the baud rate rather than the faster default rate may help this problem Assemblers often produce S record encoded programs which must be converted to binary before bootloading them to the MCU The process of reading S record data from a file and translating it to binary can be slow depending on the personal computer and the programming language used for the translation One strategy that can be used to overcome this problem is to translate the file into binary and store it into a RAM array before starting the download process Data can then be read and downloaded without the translation or file read delays The end of download mechanism goes into effect when the initial FF is received to set the baud rate Any amount of time may pass between reset and when the FF is sent to start the download process The conditions that configure the MCU for EPROM emulation mode are essentially the same as those for resetting the MCU in bootstrap mode While RESET is low and mode select pins are configured for bootstrap mode low the MCU is configured for EPROM emulation mode AN1060 Rev 1 0 314 MOTOROLA Bootloading a Program to Perform a ROM Checksum Inherent Delays Caused by Double Buffering of SCI Data AN1060 Rev 1 0 Application Note The port pins that are used for EPROM data I O lines may be inp
256. ms to be downloaded 47K NORMAL EVBU OPERATION PROGRAM EPROM 12 25 V lt PROGRAMMING 20 POWER COMMON Figure 8 PC to MCU Programming Circuit Lines 50 95 read in the small bootloader from DATA statements at the end of the listing The source code for this bootloader is presented in the DATA statements The bootloaded code makes port C bit 0 low initializes the X and Y registers for use by the EPROM programming utility routine contained in the boot ROM and then jumps to that routine The hexadecimal values read in from the DATA statements are converted to binary values by a subroutine The binary values are then saved as one string BOOTCODES The next long section of code lines 97 1250 reads in the S records from an external disk file in this case BUF34 S19 converts them to integer and saves them in an array The techniques used in this section show how to convert ASCII S records to binary form that can be sent bootloaded to an M68HC11 MOTOROLA 303 Application Note This S record translator only looks for the S1 records that contain the actual object code All other S record types are ignored When 51 record is found lines 1000 1024 the next two characters form the hex byte giving the number of hex bytes to follow This byte is converted to integer by the same subroutine that converted the bootloaded code from the DATA statements This BYTECOUNT is adjusted by subtracting
257. n to an interrupt a specified action can be initiated at one or more timer output pins For OC 5 2 the pin action is controlled by pairs of bits and OLx in the TCTL1 register The output action is taken on each successful compare regardless of whether or not the OCxF flag in the TFLG1 register was previously cleared OC1 is different from the other output compares in that a successful OC1 compare can affect any or all five of the OC pins The 1 output action taken when a match is found is controlled by two 8 bit registers with three bits unimplemented the output compare 1 mask register OC1M and the output compare 1 data register OC1D OC1M specifies which port A outputs are to be used and OC1D specifies what data is placed on these port pins 9 5 1 Timer Output Compare Registers All output compare registers are 16 bit read write Each is initialized to FFFF at reset If an output compare register is not used for an output compare function it can be used as a storage location A write to the MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 187 Timing System high order byte of an output compare register pair inhibits the output compare function for one bus cycle This inhibition prevents inappropriate subsequent comparisons Coherency requires a complete 16 bit read or write However if coherency is not needed byte accesses can be used For output compare functions write a comparison valu
258. ncludes 64 Kbytes of emulation RAM MCU extension input output I O port for single chip expanded and special test operation modes RS 232C terminal and host I O ports Logic analyzer connector MC68HC11E Family Rev 4 270 Development Support MOTOROLA Development Support Motorola Modular Development System MMDS11 A 5 Motorola Modular Development System MMDS11 The M68MMDS11 Motorola modular development system MMDS11 is an emulator system for developing embedded systems based on an M68HC11 microcontroller unit MCU The MMDS11 provides a bus state analyzer BSA and real time memory windows The unit s integrated development environment includes an editor an assembler user interface and source level debug These features significantly reduce the time necessary to develop and debug an embedded MCU system The unit s compact size requires a minimum of desk space The 11 is one component of Motorola s modular approach to MCU based product development This modular approach allows easy configuration of the MMDS1 1 to fit a wide range of requirements It also reduces development system cost by allowing the user to purchase only the modular components necessary to support the particular MCU derivative MMDS11 features include Real time non intrusive in circuit emulation at the MCU s operating frequency Real time bus state analyzer 8Kx64real time trace buffer Display of real ti
259. nding on the function chosen for the PA3 pin To enable it as an input capture pin set the 14 O5 bit in the pulse accumulator control register PACTL to logic level 1 To use it as an output compare register set the 14 05 bit to a logic level 0 Refer to 9 8 Pulse Accumulator Register name Timer Input Capture 4 Output Compare 5 High Address 101E Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 Register name Timer Input Capture 4 Output Compare 5 Low Address 101F Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 Figure 9 7 Timer Input Capture 4 Output Compare 5 Register Pair 4 5 9 5 Output Compare Technical Data Use the output compare OC function to program an action to occur at a specific time when the 16 bit counter reaches a specified value For each of the five output compare functions there is a separate 16 bit compare register and a dedicated 16 bit comparator The value in the compare register is compared to the value of the free running counter on every bus cycle When the compare register matches the counter value an output compare status flag is set The flag can be used to initiate the automatic actions for that output compare function To produce a pulse of a specific duration write a value to the output co
260. ndshake with other parallel devices Refer to Section 6 Parallel Input Output I O Ports for further information In expanded multiplexed operating mode R W is used to indicate the direction of transfers on the external data bus A low on the R W pin indicates data is being written to the external data bus A high on this pin MC68HC11E Family Rev 4 38 Pin Descriptions MOTOROLA 2 13 Port Signals 2 13 1 Port A Pin Descriptions Port Signals indicates that a read cycle is in progress RAN stays low during consecutive data bus write cycles such as a double byte store It is possible for data to be driven out of port G if internal read visibility IRV is enabled and an internal address is read even though R W is in high impedance state Refer to Section 4 Operating Modes and On Chip Memory for more information about IRVNE internal read visibility not E Port pins have different functions in different operating modes Pin functions for port A port D and port E are independent of operating modes Port B and port C however are affected by operating mode Port B provides eight general purpose output signals in single chip operating modes When the microcontroller is in expanded multiplexed operating mode port B pins are the eight high order address lines Port C provides eight general purpose input output signals when the MCU is in the single chip operating mode When the microcontroller is in the expanded multipl
261. ner First the on chip SCI serial communications interface is initialized The first character received FF determines which of two possible baud rates should be used for the remaining characters in the download operation Next a binary program is received by the SCI system andis stored in RAM Finally a jump instruction is executed to pass control from the bootloader firmware to the user s loaded program AN1060 Rev 1 0 278 MOTOROLA AN1060 Rev 1 0 Application Note Bootstrap mode is useful both at the component level and after the MCU has been embedded into a finished user system At the component level Motorola uses bootstrap mode to control a monitored burn in program for the on chip electrically erasable programmable read only memory EEPROM Units to be tested are loaded into special circuit boards that each hold many MCUS These boards are then placed in burn in ovens Driver boards outside the ovens download an EEPROM exercise and diagnostic program to all MCUs in parallel The MCUs under test independently exercise their internal EEPROM and monitor programming and erase operations This technique could be utilized by an end user to load program information into the EPROM or EEPROM of an M68HC11 before it is installed into an end product As in the burn in setup many M68HC11s can be gang programmed in parallel This technique can also be used to program the EPROM of finished products after final as
262. ng Utility The final step of the bootloader program is to jump to the start of RAM 17 which starts the user s downloaded program MOTOROLA 287 Application Note FROM RESET IN BOOT MODE INITIALIZATION SP OF RAM 01FF X START OF REGS 1000 SPCR 20 SET DWOM BIT BAUD A2 4 4 7812 5 BAUD 2 MHz SCCR2 C0 Tx amp Rx ON TOC1 DELAY CONSTANT 539 4 SCI CHARACTER TIMES SEND BREAK 3 gt NO Y NO RECEIVED FIRST CHAR YET gt 4 YES x YES JUMP TO START FIRST CHAR 00 OF EEPROM B600 NO y NOTZERO NOTE THAT A BREAK CHARACTER IS ALSO RECEIVED AS 00 FIRST CHA SWITCH TO SLOWER SCI RATE BAUD 33 13 8 1200 BAUD 9 2 MHz CHANGE DELAY CONSTANT 1 3504 4 SCI CHARACTER TIMES BAUDOK POINT TO START OF RAM Y 0000 6 7 WAIT INITIALIZE TIMEOUT COUNT 8 r yes DI Y RECEIVE DATA READY y No DECREMENT TIMEOUT COUNT TIMED al YET gt 10 YES STORE RECEIVED DATA TO RAM Y 11 TRANSMIT ECHO FOR VERIFY 12 POINT AT NEXT RAM LOCATION 13 141 PAST END 15 STAR OFRAM SET UP FOR PROGRAM UTILITY X PROGRAMMING TIME CONSTANT 16 Y START OF EPROM JUMP TO START OF RAM 0000 17 Figure 3 MC68HC711E9 Bootloader Flowchart AN1060 Rev 1 0 288 MOTOROLA UPLOAD
263. nical Data MOTOROLA Serial Communications Interface SCI 155 Serial Communications Interface 5 TC Transmit Complete Flag This flag is set when the transmitter is idle no data preamble or break transmission in progress Clear the TC flag by reading SCSR with TC set and then writing to SCDR 0 Transmitter busy 1 Transmitter idle RDRF Receive Data Register Full Flag This flag is set if a received character is ready to be read from SCDR Clear the RDRF flag by reading SCSR with set and then reading SCDR 0 SCDR empty 1 SCDR full IDLE Idle Line Detected Flag This flag is set if the RxD line is idle Once cleared IDLE is not set again until the RxD line has been active and becomes idle again The IDLE flag is inhibited when RWU 1 Clear IDLE by reading SCSR with IDLE set and then reading SCDR 0 RxD line active 1 RxD line idle OR Overrun Error Flag OR is set if a new character is received before a previously received character is read from SCDR Clear the OR flag by reading SCSR with OR set and then reading SCDR 0 No overrun 1 Overrun detected NF Noise Error Flag NF is set if majority sample logic detects anything other than a unanimous decision Clear NF by reading SCSR with NF set and then reading SCDR 0 Unanimous decision 1 Noise detected Technical Data MC68HC11E Family Rev 4 156 Serial Communications Interface SCI MOTOROLA
264. nto IX 2 Stk SP SP 2 INH 3C 4 Stack Lo First PSHY Push Y onto IY 2 Stk SP SP 2 INH 18 5 Stack Lo First PULA Pull A from 5 5 1 Stk A INH 32 4 Stack PULB Pull B from SP 1 B Stk INH 33 4 Stack PULX Pull X From SP SP 2 IX Stk INH 38 5 Stack Hi First PULY Pull Y from SP SP 2 IY Stk INH 18 38 6 Stack Hi First ROL opr Rotate Left EXT 79 ihh Il 6 aoe IND X 69 6 C b7 50 IND Y 18 69 7 ROLA Rotate Left A A INH 49 2 A C b7 b0 ROLB Rotate Left B B INH 59 2 A A Dum C b7 b0 ROR opr Rotate Right EXT 76 hh Il 6 IND X 66 ff 6 b7 b0 C IND Y 18 66 7 RORA Rotate Right A INH 46 2 Lococo b7 b0 C RORB Rotate Right B B INH 56 2 A A b7 b0 C RTI Return from See Figure 3 2 INH 3B 12 Interrupt MC68HC11E Family Rev 4 Technical Data MOTOROLA Central Processor Unit CPU Central Processor Unit CPU Table 3 2 Instruction Set Sheet 6 of 7 M mo nie Operation Description Addressing Instruction Condition Codes Mode Opcode Operand Cycles S x H 2 RTS Return from See Figure 3 2 INH 39 5 Subrout
265. ntrol Register EPROG 96 Block Protect Register 99 EPROM and EEPROM Programming Control Register PPROG 101 Arm Reset COP Timer Circuitry Register COPRST 111 System Configuration Options Register OPTION 112 Configuration Control Register CONFIG 113 Highest Priority I Bit Interrupt and Miscellaneous Register HPRIO 119 Processing Flow Out 125 Interrupt Priority Resolution 127 Interrupt Source Resolution Within 129 Port A Data Register 134 Pulse Accumulator Control Register PACTL 135 Port B Data Register PORTB 136 Port C Data Register PORTO 136 Port C Latched Register PORTCL 137 Port Data Direction Register DDRC 137 Port D Data Register PORT 138 Port D Data Direction Register DDRD 138 Port E Data Register PORTE 139 Parallel Control Register PIOC 141 SCI Transmitter Block Diagram 147 SCI Receiver Block Diagram 149 Serial Communications Data Register SCDR 152 Serial Communications Control Register 1 SCCR1 153 Serial Communications Contro
266. ntrols the EEPROM programming function Bits in enable the programming voltage control the latching of data to be programmed and select the method of erasure for example byte row etc Address 1038 Bit 7 6 5 4 3 2 1 Bit 0 Read ODD EVEN ELAT 2 BYTE ROW ERASE EELAT EPGM Write Reset 0 0 0 0 0 0 0 0 1 MC68HC711E9 only Figure 4 17 EPROM and EEPROM Programming Control Register PPROG ODD Program Odd Rows in Half of EEPROM Test Bit EVEN Program Even Rows in Half of EEPROM Test Bit ELAT EPROM OTPROM Latch Control Bit For the MC68HC711E9 EPGM enables the high voltage necessary for both and EEPROM programming For MC68HC711E9 ELAT and EELAT are mutually exclusive and cannot both equal 1 0 EPROM address and data bus configured for normal reads 1 EPROM address and data bus configured for programming BYTE Byte Other EEPROM Erase Mode Bit This bit overrides the ROW bit 0 Row or bulk erase 1 Erase only one byte ROW Row All EEPROM Erase Mode Bit If BYTE is 1 ROW has no meaning 0 Bulk erase 1 Row erase MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 101 Operating Modes and On Chip Memory Table 4 8 EEPROM Erase BYTE ROW Action 0 0 Bulk erase entire array 0 1 Row erase 16 bytes 1 0 Byte erase 1 1 Byte erase ERASE
267. oaded Data 94 4 5 3 EPROM and EEPROM Programming Control Register 94 HE EEPROM WEE EX 98 4 6 1 EEPROM and CONFIG Programming Erasure 98 4 6 1 1 Block Protect Register 99 4 6 1 2 EPROM and EEPROM Programming Control Register 101 4 6 1 3 EEPROM J su ssu ya hua sasa 103 4 6 1 4 EEPROM ROW ERES 558 IDE OC RR ER 103 4 6 1 5 EEPROM Byte Erase 104 4 6 1 6 CONFIG Register Programming 104 4 6 2 EEPROM SECU CREDE EE RRR 104 MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 65 Operating Modes Memory 4 2 Introduction This section contains information about the operating modes and the on chip memory for M68HC11 E series MCUs Except for a few minor differences operation is identical for all devices in the E series Differences are noted where necessary 4 3 Operating Modes The values of the mode select inputs MODB and MODA during reset determine the operating mode Single chip and expanded multiplexed are the normal modes In single chip mode only on chip memory is available e Expanded mode however allows access to external memory Each of the two normal modes is paired with a special mode Bootstrap a variation of the single chip mode is a special mod
268. ock cycles Since the internal RC oscillator is asynchronous to the MCU clock there is more error attributable to internal system clock noise A D converter accuracy is reduced slightly while the internal RC oscillator is being used CSEL 1 Address 1039 Bit7 6 5 4 3 2 1 Bit 0 Read ADPU CSEL IRQE py CME cR1U cmo Write Reset 0 0 0 1 0 0 0 0 1 Can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes Unimplemented Figure 10 4 System Configuration Options Register OPTION ADPU A D Power Up Bit 0 A D powered down 1 A D powered up CSEL Clock Select Bit 0 A D and EEPROM use system E clock 1 A D and EEPROM use internal RC clock IRQE Configure IRQ for Edge Sensitive Only Operation Refer to Section 5 Resets and Interrupts MC68HC11E Family Rev 4 214 Analog to Digital A D Converter MOTOROLA Analog to Digital A D Converter Conversion Process DLY Enable Oscillator Startup Delay Bit 0 The oscillator startup delay coming out of stop is bypassed and the MCU resumes processing within about four bus cycles 1 A delay of approximately 4000 E clock cycles is imposed as the MCU is started up from the stop power saving mode This delay allows the crystal oscillator to stabilize CME Clock Monitor Enable Bit Refer to Section 5 Resets and Interrupts Bit 2 Not impl
269. ock frequency below 10 kHz is detected as a clock monitor error An E clock frequency of 200 kHz or more prevents clock monitor errors Using the clock monitor function when the E clock is below 200 kHz is not recommended MC68HC11E Family Rev 4 Technical Data MOTOROLA Resets and Interrupts 111 Resets and Interrupts Special considerations are needed when a STOP instruction is executed and the clock monitor is enabled Because the STOP function causes the clocks to be halted the clock monitor function generates a reset sequence if it is enabled at the time the stop mode was initiated Before executing a STOP instruction clear the CME bit in the OPTION register to 0 to disable the clock monitor After recovery from STOP set the CME bit to logic 1 to enable the clock monitor Alternatively executing a STOP instruction with the CME bit set to logic 1 can be used as a software initiated reset 5 3 5 System Configuration Options Register Address 1039 Bit 7 6 5 4 3 2 1 Bit 0 Read ADPU CSEL IRQEU pty CME CR1U cmo Write Reset 0 0 0 1 0 0 0 0 1 Can be written only once first 64 cycles out of reset in normal mode or at any time in special modes Unimplemented Figure 5 2 System Configuration Options Register OPTION ADPU Analog to Digital Converter Power Up Bit Refer to Section 10 Analog to Digital A D Converter CSEL Clock Select Bit Refer to Secti
270. ocument is provided solely to enable system and software implementers to use Motorola products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use M
271. ol bit to change port D thus TxD of U3 to normal driven outputs This configuration will prevent interference due to R9 when TxD from the target MCU U6 becomes active Series resistor R9 demonstrates how TxD of U3 can drive RxD of U3 1 and later TxD of U6 can drive RxD of U3 without a destructive conflict between the TxD output buffers As the target MCU U6 leaves reset its mode pins select bootstrap mode so the bootloader firmware begins executing A break is sent out the TxD pin of U6 At this time the TxD pin of U3 is at a driven high so 9 acts as a pullup resistor for TxD of the target MCU U6 The break character sent from U6 is received by U3 so the duplicator program that is running in the EEPROM of the master MCU knows that the target MCU is ready to accept a bootloaded program The master MCU sends a leading FF character to set the baud rate in the target MCU Next the master MCU passes a 3 instruction program to the target MCU and pauses so the bootstrap program in the target MCU will stop the loading process and jump to the start of the downloaded program This sequence demonstrates the variable length download feature of the MC68HC711E9 bootloader The short program downloaded to the target MCU clears the DWOM bit to change its TxD pin to a normal driven CMOS output and jumps to the EPROM programming utility in the bootstrap ROM of the target MCU Note that the small downloaded program did not have to set up the SCI or
272. ommands Assembly or C language source level debugging with global variable viewing Host emulator communications speeds as high as 57 600 baud for quick program loading Extensive on line MCU information via the CHIPINFO command View memory map vectors register and pinout information pertaining to the device being emulated Host software supports An editor An assembler and user interface Source level debug Bus state analysis mouse 9 BM is a registered trademark of International Business Machines Corporation 9 MS DOS is a registered trademark of Microsoft Corporation Technical Data MC68HC11E Family Rev 4 272 Development Support MOTOROLA Development Support SPGMR11 Serial Programmer for M68HC11 MCUs A 6 SPGMR11 Serial Programmer for M68HC11 MCUs The SPGMR11 isa modular EPROM EEPROM programming tool for all M68HC11 devices The programmer features interchangeable adapters that allow programming of various M68HC11 package types Programmer features include MC68HC11E Family Rev 4 Programs M68HC11 Family devices that contain an EPROM or EEPROM array Can be operated as a stand alone programmer connected to a host computer or connected between a host computer and the M68HC11 modular development system MMDS 1 station module Uses plug in programming adapters to accommodate a variety of MCU devices and packages On board programming voltage circuit elimin
273. ompare Data Register Use this register with OC1 to specify the data that is to be stored on the affected pin of port A after a successful OC1 compare When a successful OC1 compare occurs a data bit in OC1D is stored in the corresponding bit of port A for each bit that is set in OC1M Address 1000 Bit 7 6 5 4 3 2 1 Bit 0 Read OCID7 OCID6 OCID5 0 104 OCID3 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 14 Output Compare 1 Data Register OC1D If OC1Mx is set data in OC1Dx is output to port A bit x on successful OC1 compares Bits 2 0 Unimplemented Always read 0 Technical Data MC68HC11E Family Rev 4 192 Timing System MOTOROLA Timing System Output Compare 9 5 5 Timer Counter Register The 16 bit read only TCNT register contains the prescaled value of the 16 bit timer A full counter read addresses the most significant byte MSB first A read of this address causes the least significant byte LSB to be latched into a buffer for the next CPU cycle so that a double byte read returns the full 16 bit state of the counter at the time of the MSB read cycle Register name Timer Counter Register High Address 100E Bit 7 6 5 4 3 2 1 Bit 0 Read Bit15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 Register name Timer Counter Register Low Address 100F Bit 7 6 5 4 3 2 1 Bit 0
274. on The software clearing sequence for these flags is automatic Functions that are normally performed in response to the status flags also satisfy the conditions of the clearing sequence TDRE and TC flags are normally set when the transmitter is first enabled TE set to 1 The TDRE flag indicates there is room in the transmit queue to store another data character in the TDR The TIE bit is the local MC68HC11E Family Rev 4 Technical Data MOTOROLA Serial Communications Interface SCI 161 Serial Communications Interface 5 interrupt mask for TDRE When TIE is 0 TDRE must be polled When TIE and TDRE are 1 an interrupt is requested The TC flag indicates the transmitter has completed the queue The TCIE bit is the local interrupt mask for TC When TCIE is 0 TC must be polled When TCIE is 1 and TC is 1 an interrupt is requested Writing a 0 to TE requests that the transmitter stop when it can The transmitter completes any transmission in progress before actually shutting down Only an MCU reset can cause the transmitter to stop and shut down immediately If TE is written to 0 when the transmitter is already idle the pin reverts to its general purpose I O function synchronized to the bit rate clock If anything is being transmitted when TE is written to 0 that character is completed before the pin reverts to general purpose I O but any other characters waiting in the transmit queue are lost The TC and TDRE flags are
275. on 10 Analog to Digital A D Converter IRQE Configure IRQ for Edge Sensitive Only Operation Bit 0 IRQ is configured for level sensitive operation 1 IRQ is configured for edge sensitive only operation DLY Enable Oscillator Startup Delay Bit Refer to Section 4 Operating Modes and On Chip Memory and Section 10 Analog to Digital A D Converter Technical Data MC68HC11E Family Rev 4 112 Resets and Interrupts MOTOROLA Resets and Interrupts Resets CME Clock Monitor Enable Bit This control bit can be read or written at any time and controls whether or notthe internal clock monitor circuittriggers a reset sequence when the system clock is slow or absent When it is clear the clock monitor circuit is disabled and when it is set the clock monitor circuit is enabled Reset clears the CME bit 0 Clock monitor circuit disabled 1 Slow or stopped clocks cause reset Bit 2 Unimplemented Always reads 0 CR 1 0 COP Timer Rate Select Bit The internal E clock is first divided by 215 before it enters the COP watchdog system These control bits determine a scaling factor for the watchdog timer See Table 5 1 for specific timeout settings 5 3 6 Configuration Control Register Address 103F Bit 7 6 5 4 3 2 1 Bit 0 Read EE3 EE2 1 0 NOSEC NOCOP ROMON EEON Write Reset 0 0 0 0 1 1 1 1 Figure 5 3 Configuration Control Register CONFIG EE 3
276. on allows variable length download by quitting reception of characters when an idle of at least four character times occurs x k k lt k k k lt lt CK CC CK Ck lt CK lt lt k CCS CK x k lt lt lt k KG lt ko x ko x x lt EQUATES FOR USE WITH INDEX OFFSET 51000 PORTD EQU 508 TCNT EQU SOE TOC1 EQU 16 TFLG1 EQU 23 BIT EQUATES FOR OC1F EQU 80 SPCR EQU 528 FOR DWOM BIT BAUD EQU 52 SCCR2 EQU 52 SCSR EQU S2E SCDAT EQU S2F PPROG EQU 53 BIT EQUATES FOR PPROG ELAT EQU 20 EPGM EQU 501 which already programmed to the value desired Application Note MOTOROLA 317 Application Note 47 MEMORY CONFIGURATION EQUATES 48 49 600 EEPMSTR EQU 5 600 Start of 50 BUFF EEPMEND EQU SB7FF End of EEPROM 51 52 000 EPRMSTR EQU 5 000 Start of 53 FFFF EPRMEND EQU SFFFF End of EPROM 54 55 0000 RAMSTR EQU 0000 56 01FF RAMEND EQU SO1FF 57 58 DELAY CONSTANTS 59 60 ODBO DELAYS EQU 3504 Delay at slow baud 61 021B DELAYE EQU 539 Delay at fast baud 62 63 1068 PROGDEL EQU 4200 2 ms programming delay 64 X At 2 1 MHz 65 66 Ck k x k lt lt k x lt k k KKK KKK KKK KK KKK KKK x lt lt k
277. onnect an external resistor capacitor RC power up delay circuit to the reset pin of M68HC11 devices because the circuit charge time constant can cause the device to misinterpret the type of reset that occurred Because the CPU is not able to fetch and execute instructions properly when Vpp falls below the minimum operating voltage level reset must be controlled A low voltage inhibit LVI circuit is required primarily for protection of EEPROM contents However since the configuration register CONFIG value is read from the EEPROM protection is required even if the EEPROM array is not being used Presently there are several economical ways to solve this problem For example two good external components for LVI reset are 1 The Seiko S0854HN or other S805 series devices Extremely low power 2 uA TO 92 package Limited temperature range 20 C to 70 C Available in various trip point voltage ranges 2 The Motorola MC34064 TO 92 or SO 8 package Draws about 300 uA Temperature range 40 C to 85 C Well controlled trip point Inexpensive Refer to Section 5 Resets and Interrupts for further information MC68HC11E Family Rev 4 34 Pin Descriptions MOTOROLA Pin Descriptions Crystal Driver and External Clock Input XTAL and EXTAL 2 5 Crystal Driver and External Clock Input XTAL and EXTAL These two pins provide the interface for either a crystal or a CMOS compatible clock
278. opr Jump to See Figure 3 2 DIR 9D 5 Subroutine EXT BD hh ll 6 IND X AD 6 IND Y 18 AD 7 LDAA opr Load M A A IMM 86 2 A A 0 Accumulator A DIR 96 dd 3 A A EXT B6 hh Il 4 A IND X A6 4 A IND Y 18 A6 5 opr Load M B B IMM C6 ii 2 A A 0 Accumulator B DIR D6 dd 3 B B EXT F6 ihh Il 4 B IND X E6 4 B IND Y 18 E6 5 LDD opr Load Double 1 CC jj kk 3 A A 0 Accumulator DIR DC dd 4 D EXT FC hh ll 5 IND X 5 IND Y 18 EC 6 LDS opr Load Stack M M 1 SP IMM 8E kk 3 A A 0 Pointer DIR 9E dd 4 EXT BE hh Il 5 IND X AE ff 5 IND Y 18 AE ff 6 LDX opr Load Index M M 1 gt 1X IMM CE j kk 3 A A 0 Register DIR DE dd 4 x EXT FE hh Il 5 IND X EE 5 IND Y CD EE 6 LDY opr Load Index M M 1 IY IMM 18 CE jj kk 4 A A 0 Register DIR 18 DE dd 5 Y EXT 18 FE hh Il 6 IND X 1A EE 6 IND Y 18 EE 6 LSL opr Logical Shi EXT 78 hh Il 6 A A A A Left IND X 68 6 cb Bb INDY 68 7 LSLA Logical Shi A INH 48 2 A A A A Left A lt lt 0 C b7 b0 LSLB Logical Shi B INH 58 2 A A A A Left B lt lt C b7 b0 LSLD Logical Shi INH 05 3 A A A A Left Double patri mar rna 0 C b7A b0 b7 B 00 LSR opr Logical Shi EXT 74 hh Il 6 0 A A A Right 0 IND X 64 6 b7 bo IND Y 18 64 ff 7 LSRA Logical Shi A INH 44
279. or 2 MHz rating 333 ns for MHz rating ViL lt 0 2 V ViH gt Vpp 0 2 V no dc loads MC68HC11E Family Rev 4 Technical Data MOTOROLA Electrical Characteristics 227 Electrical Characteristics Vpp CLOCKS Vpp 0 8 VOLTS STROBES 0 4 VOLTS 0 4 VOLTS 7Vss E NOM gt NOM 10 of Vpp INPUTS 20 of Vpp NOMINAL TIMING Vpp Vpp 0 8 Volts OUTPUTS oa 4 Volts DC TESTING CLOCKS 7000 70 of VoD STROBES 20 y 20 of V pp SPEC SPEC NOTE 2 Vpp 0 8 VOLTS 70 of Vpp DRE INPUTS 20 of V TO KD 04 VOLTS SPEC TIMING V 70 of VoD OUTPUTS 20 of Vpp AC TESTING Notes 1 Full test loads are applied during all dc electrical tests and ac timing measurements 2 During ac timing measurements inputs are driven to 0 4 volts and Vpp 0 8 volts while timing measurements are taken at 20 and 7096 of Vpp points Figure 11 1 Test Methods Technical Data MC68HC11E Family Rev 4 228 Electrical Characteristics MOTOROLA Electrical Characteristics Control Timing 11 10 Control Timing 1 0 MHz 2 0 MHz 3 0 MHz Characteristic 2 Symbol Unit Min Max Min Max Min Max Frequency of operation fo 1 0 dc 2 0 dc 3 0 MHz E clock period tcyc 1000 500 33
280. otorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA Motorola and the Stylized M Logo are registered in the U S Patent and Trademark Office digital dna is a trademark of Motorola Inc All other product or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 2002 M68HC11E D
281. p 3 0 Vdc to 5 5 Vss 0 Vdc TA T to Ty unless otherwise noted 2 specification for RESET and MODA is not applicable because they are open drain pins Vor specification not applicable to ports C and D in wired OR mode 3 Refer to 11 14 Analog to Digital Converter Characteristics and 11 15 MC68L11E9 E20 Analog to Digital Converter Characteristics for leakage current for port E Technical Data MC68HC11E Family Rev 4 226 Electrical Characteristics MOTOROLA Electrical Characteristics MC68L11E9 E20 Supply Currents and Power Dissipation 11 9 MC68L11E9 E20 Supply Currents and Power Dissipation Characteristic Symbol 1 MHz 2 MHz Unit Run maximum total supply current Single chip mode Vpp 5 5 V 8 15 Vpp 3 0 V Ipp 4 8 mA Expanded multiplexed mode Vpp 5 5 V 14 27 Vpp 5 5 V 7 14 Wait maximum total supply current all peripheral functions shut down Single chip mode Vpp 5 5 V 3 6 Vpp 3 0 V IDD 1 5 3 ms Expanded multiplexed mode Vpp 5 5 V 5 10 Vpp 3 0 V 2 5 5 Stop maximum total supply current 2 Single chip mode no clocks Vpp 5 5 V Sipp 50 50 Vpp 3 0 V 25 25 Maximum power dissipation Single chip mode 2 MHz 44 85 3 MHz Pp 12 24 mW Expanded multiplexed mode 2 MHz 77 150 3 MHz 21 42 1 Vpp 3 0 Vdc to 5 5 Vss 0 TA T to Ty unless otherwise noted 2 EXTAL is driven with a square wave and 500 ns f
282. p Four character times at 7812 baud is 10 240 E cycles baud prescale of 4 x baud divider of 4 x 16 internal SCI clocks bit time x 10 bit times character x 4 character times The delay from reset to the initial FF character is not critical since the delay counter is not started until after the first character is received To terminate the bootloading sequence and jump to the start of RAM without downloading any data to the on chip RAM simply send FF and nothing else This feature is similar to the jump to EEPROM at 4 except the FF causes a jump to the start of RAM This procedure requires that the RAM has been loaded with a valid program since it would make no sense to jump to a location in uninitialized memory After receiving a character the downloaded byte is stored in RAM 11 The data is transmitted back to the host 12 as an indication that the download is progressing normally At 13 the RAM pointer is incremented to the next RAM address If the RAM pointer has not passed the end of RAM the main download loop from 7 to 14 is repeated When all data has been downloaded the bootloader goes to 16 because of an intercharacter delay timeout 10 or because the entire 512 byte RAM has been filled 15 At 16 the X and Y index registers are set up for calling the PROGRAM utility routine which saves the user from having to do this in a downloaded program The PROGRAM utility is fully explained in EPROM Programmi
283. p E d Delay time AS to E rise EM A tasen 1 8 ty 9 5 ns 2 95 ASED ot S 28 3 a 29 MPU address access time tacca 7445 307 196 Ae tacca teye tosr t 35 MPU access time 442 192 111 ns tacce PWen Multiplexed address delay 36 Previous cycle MPU read tuap 145 5 83 51 ns tMAD tasp 30 ns 3 a 1 Vpp 5 0 10 Vss 0 TA T to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 Formula only for dc to 2 MHz 3 Input clocks with duty cycles other than 50 affect bus performance Timing parameters affected by input clock duty cycle are identified by a and b To recalculate the approximate bus timing values substitute the following expressions in place of 1 8 the above formulas where applicable 1 x 1 4 b x 1 4 Where dc is the decimal value of duty cycle percentage high time MC68HC11E Family Rev 4 Technical Data MOTOROLA Electrical Characteristics 243 Electrical Characteristics 11 17 MC68L11E9 E20 Expansion Bus Timing Characteristics Num Characteristic Symbol is E 29 me Unit Min Max Min Max Frequency of operation E clock frequency fo dc 1 0 dc 2 0 MHz 1 time 1000 500 ns Pulse width E lo
284. pp and 70 Vpp unless Technical Data MOTOROLA Electrical Characteristics 247 Electrical Characteristics 55 515 HELD HIGH ON MASTER INPUT lt 1 gt SCK G A CPOL 0 NOTE N INPUT 4 gt SCK O gt CPOL 1 NOTE ws N OUTPUT v N aO 107 50 a w mm Mon MASTER MSB OUT BT6 1 MASTER LSB OUT OUTPUT Note This first clock edge is generated internally but is not seen at the SCK pin SPI Master Timing CPHA 0 55 N INPUT S IS HELD HIGH 0N MASTER SCK CPOL 0 SEE NOTE INPUT SCK CPOL 1 N SEE NOTE OUTPUT lt Gop gt e m 6 Moal N MASTER MSB OUT MASTER LSB OUT V OUTPUT Note This first clock edge is generated internally but is not seen at the SCK pin B SPI Master Timing CPHA 1 Figure 11 15 SPI Timing Diagram Sheet 1 of 2 Technical Data MC68HC11E Family Rev 4 248 Electrical Characteristics MOTOROLA Electrical Characteristics MC68L11E9 E20 Serial Peirpheral Interface Characteristics SCK 5 CPOL 0 INPUT SCK CPOL 1 N J N INPUT M a 1 5 lt gt Ona lt 4 MISO OUTPUT SLAVE MSB OUT BT6 1 SLAVE LSB 0UT SE
285. pplication of the M68HC11 bootstrap mode Although basic concepts associated with this mode are quite simple the more subtle implications of these functions require careful consideration Useful applications of this mode are overlooked due to an incomplete understanding of bootstrap mode Also common problems associated with bootstrap mode could be avoided by a more complete understanding of its operation and implications Mj MOTOROLA AN1060 Rev 1 0 Application Note Topics discussed in this application note include Basic Bootstrap Mode Basic operation of the M68HC11 bootstrap mode General discussion of bootstrap mode uses Detailed explanation of on chip bootstrap logic Detailed explanation of bootstrap firmware Bootstrap firmware vs EEPROM security Incorporating the bootstrap mode into a system Driving bootstrap mode from another M68HC11 Driving bootstrap mode from a personal computer Common bootstrap mode problems Variations for specific versions of M68HC11 Commented listings for selected M68HC11 bootstrap ROMs This section describes only basic functions of the bootstrap mode Other functions of the bootstrap mode are described in detail in the remainder of this application note When an M68HC11 is reset in bootstrap mode the reset vector is fetched from a small internal read only memory ROM called the bootstrap ROM or boot ROM The firmware program in this boot ROM then controls the bootloading process in this man
286. r and additional internal analog signal lines are routed to it Port E pins also can be used as digital inputs Digital reads of port E pins are not recommended during the sample portion of an A D conversion cycle when the gate signal to the N channel input gate is on Because no P channel devices are directly connected to either input pins or reference voltage pins voltages above Vpp do not cause a latchup problem although current should be limited according to maximum ratings Refer to Figure 10 2 which is a functional diagram of an input pin MC68HC11E Family Rev 4 210 Analog to Digital A D Converter MOTOROLA Analog to Digital A D Converter Overview VRH 8 BIT CAPACITIVE DAC WITH SAMPLE AND HOLD VRL SUCCESSIVE APPROXIMATION REGISTER AND CONTROL RESULT ANALOG INTERNAL DATA BUS 9981 5 ADCTL A D CONTROL RESULT REGISTER INTERFACE ADR1 A D RESULT 1 ADR2 A D RESULT 2 ADR3 A D RESULT 3 ADR4 A D RESULT 4 Figure 10 1 A D Converter Block Diagram DIFFUSION POLY COUPLER ANPUT AAA 2 5 d 4 20 V 4 lt 2 pF 0 7V 0 7V 20 pF PL X 400 nA pac DUMMY N CHANNEL V_ JUNCTION CAPACITANCE OUTPUT DEVICE LEAKAGE INPUT 2 PROTECTION E DEVICE ig THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12 CYCLE SAMPLE TIME Figure 10 2 Electrical Model of an A D Input Pin Sample Mode MC68HC11E Fam
287. r MCU to the target MCU and programmed into the EPROM of the target The master MCU in the EVBU corresponds to the HOST in the programming utility description and the PROGRAM utility in MCU is running in the bootstrap ROM of the target MCU Each byte of data sent to the target is programmed and then the programmed location is read and sent back to the master for verification If any byte fails the red and green LEDs are turned off and the programming operation is aborted If the entire 12 Kbytes are programmed and verified successfully the red LED is turned off and the green LED is turned on to indicate success The programming of all 12 Kbytes takes about 30 seconds After a programming operation the Vpp switch 52 should be turned off before the EVBU power is turned off Yop CUT TRACE R AS SHOWN N1D 47K P4 18 P5 18 42 Figure 7 Isolating EVBU XIRQ Pin AN1060 Rev 1 0 298 MOTOROLA Application Note Listing 1 MCU to MCU Duplicator Program Q1 C0 N P lt 103 0028 0004 errr WNE o 0080 0002 0001 000A 002E errre 0 d PR 0080 0020 002F BFOO 000 gt 600 No PO 600 603 605 607 609 B60B B60F B611 B613 B616 B618 B61B Pe BS SP 0 9 CO CO CO CO CO CO CO CO C CO B61D B620 B621 B623 B625 gt P gt PD
288. r RDRF 122 BF23 E62F LDAB SCDAT X Get received byt 123 BF25 18E100 CMPB 50 See if already programmed 124 BF28 271D BEQ DONEIT If so skip prog cycle 125 2 8620 LDAA ELAT Put EPROM in prog mode 126 BF2C A73B STAA PPROG X 127 BF2E 18E700 STAB 0 2 Write the data 128 BF31 8621 LDAA ELAT EPGM 129 BF33 A73B STAA PPROG X Turn on prog voltage 130 BF35 32 PULA Pull delay constant 131 BF36 33 PULB into D reg 132 BF37 37 PSHB But also keep delay 133 BF38 36 PSHA keep delay on stack 134 BF39 E30E ADDD Delay const present TCNT 135 BF3B ED16 STD Schedule 2ms delay 136 BF3D 8680 LDAA 137 A723 STAA TFLG1 X Clear any previous flag 138 139 41 1F2380FC BRCLR TFLG1 X Wait for delay to expire 140 BF45 6F3B CLR PPROG X Turn off prog voltage 141 142 BF47 DONEIT EQU i 143 47 1F2E80FC BRCLR SCSR X 80 Wait for TDRE 144 BF4B 18A600 LDAA 0 Y Read from EPROM and 145 A72F STAA SCDAT X Xmit for verify 146 BF50 1808 INY Point at next location 147 BF52 20CB BRA WAIT1 Back to top for next 148 Loops indefinitely as long as more data sent 149 AN1060 Rev 1 0 MOTOROLA 319 Application Note 150 151 152 153 154 159 156 158 159 160 161 162 169 164 165 166 167 168 169 170 171 172 172 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 1 92 193 194 195 196 197 198 199 200 201 202
289. r Unit CPU 3 6 6 Relative The relative addressing mode is used only for branch instructions If the branch condition is true an 8 bit signed offset included in the instruction is added to the contents of the program counter to form the effective branch address Otherwise control proceeds to the next instruction These are usually 2 byte instructions 3 7 Instruction Set Refer to Table 3 2 which shows all the M68HC11 instructions in all possible addressing modes For each instruction the table shows the operand construction the number of machine code bytes and execution time in CPU E clock cycles Technical Data MC68HC11E Family Rev 4 56 Central Processor Unit CPU MOTOROLA Table 3 2 Instruction Set Sheet 1 of 7 Central Processor Unit CPU Instruction Set Miemoni Operation Description Addressing Instruction Condition Codes Mode Opcode Operand Cycles X H z V C ABA Add A B A INH 1B 2 A Accumulators ABX Add B to X IX 00 B IX INH 3A 3 ABY Add B to Y IY 00 B IY INH 18 3A 4 ADCA opr Add with Carry A M C gt A A IMM 89 2 A to A A DIR 99 3 A EXT B9 hh Il 4 A IND X A9 4 A IND Y 18 A9 5 ADCB opr Add with Carry B M C B B IMM C9 jii 2 A to B B DIR D9 3 B EXT F9 hh Il 4 B IND X E9 4 B IND Y
290. r wakeup functions are disabled The TDRE and TC status bits in the SCI status register SCSR are both 1s indicating that there is no transmit data in either the transmit data register or the transmit serial shift register The RDRF IDLE OR NF FE PF and RAF receive related status bits in the SCI control register 2 SCCR2 are cleared Technical Data MC68HC11E Family Rev 4 116 Resets and Interrupts MOTOROLA Resets and Interrupts Reset and Interrupt Priority 5 4 8 Serial Peripheral Interface The SPI system is disabled by reset The port pins associated with this function default to being general purpose I O lines 5 4 9 Analog to Digital A D Converter 5 4 10 System The analog to digital A D converter configuration is indeterminate after reset The ADPU bit is cleared by reset which disables the A D system The conversion complete flag is indeterminate The EEPROM programming controls are disabled so the memory system is configured for normal read operation PSEL 3 0 are initialized with the value 0110 causing the external IRQ pin to have the highest I bit interrupt priority The IRQ pin is configured for level sensitive operation for wired OR systems The RBOOT SMOD and MDA bits in the HPRIO register reflect the status of the MODB and MODA inputs at the rising edge of reset MODA and MODB inputs select one of the four operating modes After reset writing SMOD and MDA in special modes causes the M
291. reset one entire RTI period elapses before the RTIF is set for the first time Refer to the 9 5 9 Timer Interrupt Mask 2 Register 9 6 2 Timer Interrupt Flag Register 2 and 9 6 3 Pulse Accumulator Control Register Technical Data MOTOROLA Timing System 199 Timing System 9 6 1 Timer Interrupt Mask Register 2 This register contains the real time interrupt enable bits Address 51024 Bit 7 6 5 4 3 2 1 Bit 0 Read TOl RTI PAOVI PAII PRI PRO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 21 Timer Interrupt Mask 2 Register TMSK2 TOI Timer Overflow Interrupt Enable Bit 0 TOF interrupts disabled 1 Interrupt requested when TOF is set to 1 RTII Real Time Interrupt Enable Bit 0 RTIF interrupts disabled 1 Interrupt requested when RTIF set to 1 PAOVI Pulse Accumulator Overflow Interrupt Enable Bit Refer to 9 8 Pulse Accumulator PAII Pulse Accumulator Input Edge Bit Refer to 9 8 Pulse Accumulator Bits 3 2 Unimplemented Always read 0 PR 1 0 Timer Prescaler Select Bits Refer to Table 9 4 NOTE in TMSK2 correspond bit for bit with flag bits TFLG2 Bits TMSK enable the corresponding interrupt sources Technical Data MC68HC11E Family Rev 4 200 Timing System MOTOROLA Timing System Real Time Interrupt RTI 9 6 2 Timer Interrupt Flag Register 2 Bits of this register indicate the occurrence of timer system e
292. ry MOTOROLA 4 4 Memory Operating Modes Memory Memory Map passes to the loaded program at 0000 Refer to Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 and Figure 4 6 Use of an external pullup resistor is required when using the SCI transmitter pin because port D pins are configured for wired OR operation by the bootloader In bootstrap mode the interrupt vectors are directed to RAM This allows the use of interrupts through a jump table Refer to the application note AN1060 entitled M68HC11 Bootstrap Mode that is included in this data book The operating mode determines memory mapping and whether external addresses can be accessed Refer to Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 and Figure 4 6 which illustrate the memory maps for each of the three families comprising the M68HC11 E series of MCUs Memory locations for on chip resources are the same for both expanded and single chip modes Control bits in the configuration CONFIG register allow EPROM and EEPROM if present to be disabled from the memory map The RAM is mapped to 0000 after reset It can be placed at any 4 Kbyte boundary x000 by writing an appropriate value to the RAM and map register INIT 64 byte register block is mapped to 1000 after reset and also can be placed at any 4 Kbyte boundary x000 by writing an appropriate value to the INIT register If RAM and registers are mapped to the same boundary the fir
293. s 00 FF are thus accessed directly using 2 byte instructions Execution time is reduced by eliminating the additional memory access required for the high order address byte In most applications this 256 byte area is reserved for frequently referenced data In M68HC 1 1 MCUS the memory map can be configured for combinations of internal registers RAM or external memory to occupy these addresses In the extended addressing mode the effective address of the argument is contained in two bytes following the opcode byte These are 3 byte instructions or 4 byte instructions if a prebyte is required One or two bytes are needed for the opcode and two for the effective address In the indexed addressing mode an 8 bit unsigned offset contained in the instruction is added to the value contained in an index register IX or IY The sum is the effective address This addressing mode allows referencing any memory location in the 64 Kbyte address space These are 2 to 5 byte instructions depending on whether or not a prebyte is required In the inherent addressing mode all the information necessary to execute the instruction is contained in the opcode Operations that use only the index registers or accumulators as well as control instructions with no arguments are included in this addressing mode These are 1 or 2 byte instructions MC68HC11E Family Rev 4 Technical Data MOTOROLA Central Processor Unit CPU 55 Central Processo
294. s must be erased using a suitable ultraviolet light source before reprogramming Depending on the light source erasing can take from 15 to 45 minutes Using the on chip EPROM OTPROM programming feature requires an external 12 volt nominal power supply Vppg Normal programming is accomplished using the EPROM OTPROM programming register PPROG PPROG is the combined EPROM OTPROM and EEPROM programming register on all devices with EPROM OTPROM except the MC68HC711E20 For the MC68HC71 1E20 there is a separate register for EPROM OTPROM programming called the EPROG register Technical Data MC68HC11E Family Rev 4 92 Operating Modes and On Chip Memory MOTOROLA Operating Modes Memory EPROM OTPROM As described in the following subsections these two methods of programming and verifying EPROM are possible Programming an individual EPROM address Programming the EPROM with downloaded data 4 5 1 Programming an Individual EPROM Address NOTE In this method the MCU programs its own EPROM by controlling the PPROG register EPROG in MC68HC711E20 Use these procedures to program the EPROM through the MCU with The ROMON bit set in the CONFIG register The 12 volt nominal programming voltage present on the XIRQ Vppg pin The IRQ pin must be pulled high Any operating mode can be used This example applies to all devices with EPROM OTPROM except for the MC68HC711E20 EPROG L
295. s only 1 0 Capture on falling edges only 1 1 Capture on any edge MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 183 Timing System 9 4 2 Timer Input Capture Registers When an edge has been detected and synchronized the 16 bit free running counter value is transferred into the input capture register pair as a single 16 bit parallel transfer Timer counter value captures and timer counter incrementing occur on opposite half cycles of the phase 2 clock so that the count value is stable whenever a capture occurs The timer input capture registers are not affected by reset Input capture values be read from a pair of 8 bit read only registers A read of the high order byte of an input capture register pair inhibits a new capture transfer for one bus cycle If a double byte read instruction such as load double accumulator D LDD is used to read the captured value coherency is assured When a new input capture occurs immediately after a high order byte read transfer is delayed for an additional cycle but the value is not lost Register name Timer Input Capture 1 Register High Address 1010 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit 8 Write Reset Indeterminate after reset Register name Timer Input Capture 1 Register Low Address 1011 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit7 Bit 6 Bit 5 Bit4 Bit 3 Bit2
296. s pulled from the stack the SP is incremented At any given time the SP holds the 16 bit address of the next free location in the stack Figure 3 2 is a summary of SP operations MC68HC11E Family Rev 4 48 Central Processor Unit CPU MOTOROLA JSR JUNP SUBROUTINE Central Processor Unit CPU RTI RETURN FROM INTERRUPT CPU Registers MAIN PROGRAM INTERRUPT ROUTINE STACK 0 2p JsR 3B RTI SP DIRECT lt dd CCR RTN NEXT MAIN INSTR SP42 ACCB SP43 ACCA MAIN PROGRAM p X PC SR SP45 IX INDEXED X 4 f STACK SP46 RTN NEXT MAIN INSTR A MAIN PROGRAM SP 1 SP48 c 18 SP RTN gt SP49 RTN INDEXED Y 4 SAD JSR SWI SOFTWARE INTERRUPT ff MAIN PROGRAM _ STACK 0 NEXT MAIN INSTR T Soins MAIN PROGRAM SP 8 CCR BD 5 7 hh SP 6 ACCA INDEXED Y lt Sp 5 IX BL e cr WAI WAIT FOR INTERRUPT H NEXT MAIN INSTR 5 4 IX 2 MAINPROGRAM SP 3 3E SP 2 M BSR BRANCH TO SUBROUTINE J L MAIN PROGRAM 7 PC 8D BSR c SP 2 LEGEND SP 1 RTNH RTN ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO
297. s select an additional binary submultiple 1 2 4 through 128 of this highest baud rate The result of these two dividers in series is the 16X receiver baud rate clock The SCR 2 0 bits are not affected by reset and can be changed at any time although they should not be changed when any SCI transfer is in progress Figure 7 8 and Figure 7 9 illustrate the SCI baud rate timing chain The prescaler select bits determine the highest baud rate The rate select bits determine additional divide by two stages to arrive at the receiver timing RT clock rate The baud rate clock is the result of dividing the RT clock by 16 Technical Data MOTOROLA Serial Communications Interface SCI 159 Serial Communications Interface 1 EXTAL ursi INTERNAL BUS CLOCK PH2 m CLOCK GENERATOR gt lt 4 XTAL 3 24 13 1 0 PRI AS 0 0 0 1 1 0 1 1 e SCR 2 0 0 0 0 2 0 0 1 Rje 2 0 1 0 E 9 2 0 1 1 e RS gt 16 2 1 0 0 e ES SCI TRANSMIT 2 101 BAUD RATE 1X RS 2 1 1 0 E ze ana sci RECEIVE BY BAUD RATE 16X Figure 7 8 SCI Baud Rate Generator Block Diagram 7 9 Status Flags and Interrupts The SC
298. selection of aslave SPI device slave devices that are not selected do not interfere with SPI bus activities On a master SPI device the select line can optionally be used to indicate a multiple master bus contention Refer to Figure 8 2 SCK CYCLE L U n T sxc sc WU VA LA LY SAMPLE INPUT CPHA 0 DATA OUT SAMPLE INPUT CPHA 1 DATA OUT SS TO SLAVE 1 1 1 1 1 1 1 lt lt SLAVE 1 TRANSFER IN PROGRES lt MASTER TRANSFER IN PROGRESS gt SLAVE 0 TRANSFER IN PROGRESS 1 55 ASSERTED 2 MASTER WRITES TO SPDR 3 FIRST SCK EDGE 4 SPIF SET 5 55 NEGATED Figure 8 2 SPI Transfer Format Technical Data MC68HC11E Family Rev 4 168 Serial Peripheral Interface MOTOROLA Serial Interface Phase Polarity Controls 8 5 Clock Phase and Polarity Controls Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI control register SPCR The clock polarity is specified by the CPOL control bit which selects an active high or active low clock and has no significant effect on the transfer format The clock phase CPHA control bit selects one of two different transfer formats The clock phase and polarity should be identical for the master
299. sembly Motorola also uses bootstrap mode for programming target devices on the M68HC11 evaluation modules EVM Because bootstrap mode is a privileged mode like special test the EEPROM based configuration register CONFIG can be programmed using bootstrap mode on the EVM The greatest benefits from bootstrap mode are realized by designing the finished system so that bootstrap mode can be used after final assembly The finished system need not be a single chip mode application for the bootstrap mode to be useful because the expansion bus can be enabled after resetting the MCU in bootstrap mode Allowing this capability requires almost no hardware or design cost and the addition of this capability is invisible in the end product until it is needed The ability to control the embedded processor through downloaded programs is achieved without the disassembly and chip swapping usually associated with such control This mode provides an easy way to load non volatile memories such as EEPROM with calibration tables or to program the application firmware into a one time programmable OTP MCU after final assembly Another powerful use of bootstrap mode in a finished assembly is for final test Short programs can be downloaded to check parts of the MOTOROLA 279 Application Note system including components and circuitry external to the embedded MCU If any problems appear during product development diagnostic programs can be downloaded
300. series MCUs Differences among devices are noted in the table accompanying Figure 1 1 MC68HC11E Family Rev 4 Technical Data MOTOROLA General Description 25 General Description MODA MODB LIR XTAL EXTAL E RO RESET MODE CONTROL INTERRUPT CLOCK LOGIC LOGIC ROM OR EPROM SEE TABLE TIMER SYSTEM PERIODIC INTERRUPT BUS EXPANSION ADDRESS ADDRESSIDATA jg q SPI O U TPT PISI I E 58050006 SERIAL SERIAL PERIPHERAL COMMUNICATION INTERFACE INTERFACE 5 EEPROM M68HC11 CPU SEE TABLE RAM SEE TABLE E DEVICE RAM EPROM EEPROM MC68HC11E0 512 MC68HC11E1 512 512 MC68HC11E9 512 12K 512 MC68HC711E9 512 12K 512 MC68HC11E20 768 20 50 MC68HC711E20 768 20 50 68 811 2 256 2048 Vppc applies only to devices with EPROM OTPROM Figure 1 1 M68HC11 E Series Block Diagram Technical Data MC68HC11E Family Rev 4 26 General Description MOTOROLA Technical Data M68HC11E Family 2 1 Contents 2 2 2 3 2 4 2 5 2 6 2 4 2 8 2 9 2 10 2 11 2 12 2 13 2 13 1 2 13 2 2 13 3 2 13 4 2 13 5 MC68HC11E Family Rev 4 Section 2 Pin Descriptions ee he sn ae ee er er aa ee eee er eee 28 Vpp and Vss G urai bd 32 mc 34 Crystal Driver Externa
301. set at the completion of this last character even though TE has been disabled 7 10 Receiver Flags Technical Data The SCI receiver has five status flags three of which can generate interrupt requests The status flags are set by the SCI logic in response to specific conditions in the receiver These flags can be read polled at any time by software Refer to Figure 7 10 which shows interrupt arbitration When an overrun takes place the new character is lost and the character that was in its way in the parallel RDR is undisturbed RDRF is set when a character has been received and transferred into the parallel RDR The OR flag is set instead of RDRF if overrun occurs A new character is ready to be transferred into RDR before a previous character is read from RDR The NF and FE flags provide additional information about the character in the RDR but do not generate interrupt requests The last receiver status flag and interrupt source come from the IDLE flag The RxD line is idle if it has constantly been at logic 1 for a full character time The IDLE flag is set only after the RxD line has been MC68HC11E Family Rev 4 162 Serial Communications Interface SCI MOTOROLA Serial Communications Interface SCI Receiver Flags busy and becomes idle which prevents repeated interrupts for the whole time RxD remains idle BEGIN LAG Y RDRF 1 N lt Y NO VALID SCI REQUEST VALID SCI
302. single channel operation are 1 When SCAN 0 the single selected channel is converted four consecutive times The first result is stored in A D result register 1 ADR1 and the fourth result is stored in ADR4 After the fourth conversion is complete all conversion activity is halted until a new conversion command is written to the ADCTL register 2 When SCAN 1 conversions continue to be performed on the selected channel with the fifth conversion being stored in register ADR1 overwriting the first conversion result the sixth conversion overwriting ADR2 and so on Technical Data MC68HC11E Family Rev 4 216 Analog to Digital A D Converter MOTOROLA Analog to Digital A D Converter Multiple Channel Operation 10 8 Multiple Channel Operation The two types of multiple channel operation are 1 When SCAN 0 a selected group of four channels is converted one time each The first result is stored in A D result register 1 ADR1 and the fourth result is stored in ADR4 After the fourth conversion is complete all conversion activity is halted until anew conversion command is written to the ADCTL register 2 When SCAN 1 conversions continue to be performed on the selected group of channels with the fifth conversion being stored in register ADR1 replacing the earlier conversion result for the first channel in the group the sixth conversion overwriting ADR2 and so on 10 9 Operation in Stop and Wait Modes If a
303. sponding bit position s OC1F OCAF Output Compare x Flag Set each time the counter matches output compare x value 14 O5F Input Capture 4 Output Compare 5 Flag Set by IC4 or OC5 depending on the function enabled by 14 O5 bit in PACTL IC1F ICS3F Input Capture x Flag Set each time a selected active edge is detected on the ICx input line 9 5 9 Timer Interrupt Mask 2 Register Use this 8 bit register to enable or inhibit timer overflow and real time interrupts The timer prescaler control bits are included in this register Address 1024 Bit 7 6 5 4 3 2 1 Bit 0 Read TOl RTII PAOVI PAII PRI PRO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 19 Timer Interrupt Mask 2 Register TMSK2 Technical Data MC68HC11E Family Rev 4 196 Timing System MOTOROLA Timing System Output Compare TOI Timer Overflow Interrupt Enable Bit 0 TOF interrupts disabled 1 Interrupt requested when TOF is set to 1 RTII Real Time Interrupt Enable Bit Refer to 9 6 Real Time Interrupt RTI PAOVI Pulse Accumulator Overflow Interrupt Enable Bit Refer to 9 8 3 Pulse Accumulator Status and Interrupt Bits PAII Pulse Accumulator Input Edge Interrupt Enable Bit Refer to 9 8 3 Pulse Accumulator Status and Interrupt Bits Bits 3 2 Unimplemented Always read 0 PR 1 0 Timer Prescaler Select Bits These bits are used to select the prescaler divide by ratio
304. st 64 bytes of RAM will be inaccessible Refer to Figure 4 7 which details the MCU register and control bit assignments Reset states shown are for single chip mode only MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 69 Operating Modes Memory 0000 1000 B600 D000 FFFF 0000 1000 B600 D000 FFFF Technical Data 0000 512 BYTES RAM EXT EXT OFF y Y n 1000 64 REGISTER BLOCK 103F EXT EXT 800 BFCO SPECIAL MODES ROM INTERRUPT eles BEFF VECTORS FFCO NORMAL MODES lt ees m INTERRUPT Y Y FFFF VECTORS EXPANDED BOOTSTRAP SPECIAL TEST Figure 4 2 Memory Map for MC68HC11E0 0000 A A 512 BYTES RAM EXT EXT O1FF Y y 1000 64 BYTE REGISTER BLOCK EXT EXT 103F B600 512 BYTES EEPROM Y B7FF Bro 800 BFCO SPECIAL MODES BAT s ROM INTERRUPT BEFF grrr VECTORS FFCO NORMAL MODES uu INTERRUPT Y Y FFFF VECTORS EXPANDED BOOTSTRAP SPECIAL TEST Figure 4 3 Memory Map for MC68HC11E1 MC68HC11E Family Rev 4 70 Operating Modes and On Chip Memory MOTOROLA Operating Modes Memory
305. st Priority Bit Interrupt 103C Miscellaneous Register HPRIO See page 83 RAM and 1 0 Mapping 103D Register INIT See page 89 103E Reserved System Configuration Register 103F CONFIG See page 87 System Configuration Register 103F CONFIG See page 87 Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Operating Modes and On Chip Memory Memory Map Bit 7 6 5 4 3 2 1 Bit 0 R R R R R R R R ADPU CSEL IRQE pty CME CR1U cao 0 0 0 1 0 0 0 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit 2 Bil Bito 0 0 0 0 0 0 0 0 ODD EVEN ELAT BYTE ROW ERASE EELAT EPGM 0 0 0 0 0 0 0 0 RBOOT SMOD MDA IRV NE PSEL3 PSEL2 PSEL1 PSELO 0 0 0 0 0 1 1 0 RAM3 RAM2 RAM1 RAMO REG3 REG2 REGI REGO 0 0 0 0 0 0 0 1 R R R R R R R R NOSEC NOCOP ROMON EEON 0 0 0 0 U U 1 U EE3 EE2 1 EEO NOSEC 1 1 1 1 U U 1 1 1 Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes 2 MC68HC711E9 only 3 MC68HC811E2 only Unimplemented 2 Indeterminate after reset Reserved U Unaffected Figure 4 7 Register and Control Bit Assignments Sheet 8 of 8 MC68HC11E Family Rev 4 Technical Da
306. stems are enabled PDO is the receive data input RxD signal for the SCI PD1 is the transmit data output TxD signal for the SCI e PD5 PD2 are dedicated to the SPI PD2 is the master in slave out MISO signal is the master out slave in MOSI signal PD4 is the serial clock signal PD5is the slave select SS input 2 13 5 PortE Use port E for general purpose or analog to digital A D inputs CAUTION If high accuracy is required for A D conversions avoid reading port E during sampling as small disturbances can reduce the accuracy of that result MC68HC11E Family Rev 4 Technical Data MOTOROLA Pin Descriptions 43 Pin Descriptions Technical Data MC68HC11E Family Rev 4 44 Pin Descriptions MOTOROLA Technical Data M68HC11E Family Section 3 Central Processor Unit CPU 3 1 Contents 3 2 Introduction ciscus RR RR 33 CPU Registers 3 3 1 Accumulators A B and D 3 3 2 Index Register X IX 3 3 3 Index Register Y IY 3 3 4 Stack Pointer SP 3 3 5 Program Counter PC 3 3 6 Condition Code Register CCR 3 3 6 1 Carry Borrow C 3 3 6 2 Overflow TV La qoas pe eR Co 3 3 6 3 ERI Lo dU ER OP 3 3 6 4 Negative 3 3 6 5 Interrupt 1 3 3 6 6 Half HJ u u u a au ses 3 9 6 7 X Interrupt Mask
307. sters 85 EEPROM pu puasa 88 RAM Mapping 90 Register Mapping 90 EEPROM Block Protel Leda dhr 100 EEPROM Block Protect MC68HC811E2 MCUs 100 dee ee 102 COP Timer Rate 110 Reset Cause Reset Vector and Operating Mode 114 Highest Priority Interrupt 120 Interrupt and Reset Vector Assignments 121 Stacking Order on Entry to 122 Input Output 133 Parallel O Control s os eee PR 143 Baud Rate 158 SP IGISSEK ee CL LU I eRe OR ee ERR 174 Timer ere 180 Timer Control Configuration 183 Technical Data MOTOROLA List of Tables 21 List of Tables Table Title Page 9 3 Timer Output Compare Actions 194 9 4 Timer Prescale 197 95 RIRIS Lai cuori ACC aede aro e e eR 199 9 6 Pulse Accumulator Timing 204 9 7 Pulse Accumulator Edge Control 205 10 1 Converter Channel Assignments 216 10 2 A D Converter Channel Selection
308. system E clock E CLOCK MSB BIT6 BIT5 BIT2 BIT1 LSB 2 12E CYCLES 4 2 2 2 2 2 2 2 CYC CYCLES CYC CYC CYC CYC CYC CYC CVC END SAMPLE ANALOG INPUT 93 SUCCESSIVE APPROXIMATION SEQUENCE 5 B i u 9 j E 3 CONVERTFIRST CONVERT SECOND CONVERT THIRD CONVERT FOURTH CHANNEL UPDATE CHANNEL UPDATE CHANNEL UPDATE CHANNEL UPDATE ADR1 ADR2 64 ADR3 96 ADR4 128 E CYCLES Figure 10 3 A D Conversion Sequence MC68HC11E Family Rev 4 Technical Data MOTOROLA Analog to Digital A D Converter 213 Analog to Digital A D Converter 10 4 A D Converter Power Up and Clock Select Technical Data Bit 7 of the OPTION register controls A D converter power up Clearing ADPU removes power from and disables the A D converter system Setting ADPU enables the A D converter system Stabilization of the analog bias voltages requires a delay of as much as 100 us after turning on the A D converter When the A D converter system is operating with the MCU E clock all switching and comparator operations are inherently synchronized to the main MCU clocks This allows the comparator output to be sampled at relatively quiet times during MCU cl
309. t PCBUG11 A PORT 2 when the E9PGMR connected to COM2 PCbug11only supports COM ports 1 and 2 PCbug11 defaults to base ten for its input parameters Change this to hexadecimal by typing CONTROL BASE HEX EB188 328 MOTOROLA Step 4 Step 5 Step 6 188 Engineering Bulletin Clear the block protect register BPROT to allow programming of the MC68HC811E2 EEPROM At the PCbug11 command prompt type MS 1035 00 PCbug11 defaults to a 512 byte EEPROM array located at B600 This must be changed since the EEPROM is by default located at F800 on the MC68HC811E2 At the PCbug11 command prompt type EEPROM 0 Then type EEPROM F800 FFFF EEPROM 103F 103F This assumes you have not relocated the EEPROM by previously reprogramming the upper 4 bits of the CONFIG register But if you have done this and your S records reside in an address range other than F800 to FFFF you will need to first relocate the EEPROM Erase the CONFIG to allow programming of NOSEC bit bit 3 It is also recommended to program the EEPROM at this point before programming the CONFIG register Refer to the engineering bulletin Programming MC68HC811E2 Devices with PCbug11 and the M68HC711E9PGMR Motorola document number EB184 At the PCbug11command prompt type EEPROM ERASE BULK 103F MOTOROLA 329 Engineering Bulletin Step 7 Step 8 Step 9 NOTE You are now ready to enable the security feature on the MCHC811E2 At
310. ta MOTOROLA Operating Modes and On Chip Memory 79 Operating Modes Memory 4 4 1 RAM and Input Output Mapping Hardware priority is built into RAM and I O mapping Registers have priority over RAM and RAM has priority over ROM When a lower priority resource is mapped at the same location as a higher priority resource a read write of a location results in a read write of the higher priority resource only For example if both the register block and the RAM are mapped to the same location only the register block will be accessed If RAM and ROM are located at the same position RAM has priority The fully static RAM can be used to store instructions variables and temporary data The direct addressing mode can access RAM locations using a 1 byte address operand saving program memory space and execution time depending on the application RAM contents can be preserved during periods of processor inactivity by two methods both of which reduce power consumption They are 1 Inthe software based stop mode the clocks are stopped while Vpp powers the MCU Because power supply current is directly related to operating frequency in CMOS integrated circuits only a very small amount of leakage exists when the clocks are stopped 2 Inthe second method the MODB Vsrpy can supply RAM power from a battery backup or from a second power supply Figure 4 8 shows a typical standby voltage circuit for a standard 5
311. tage devices available 3 0 5 5 Vdc 0 256 512 or 768 bytes of on chip RAM data retained during standby 0 12 or 20 Kbytes of on chip ROM or EPROM 0 512 or 2048 bytes of on chip EEPROM with block protect for security 2048 bytes of EEPROM with selectable base address in the MC68HC811E2 Asynchronous non return to zero NRZ serial communications interface SCI Additional baud rates available on MC68HC 7 11E20 Synchronous serial peripheral interface 8 channel 8 bit analog to digital A D converter 16 bit timer system Three input capture IC channels Four output compare OC channels One additional channel selectable as fourth IC or fifth OC 8 bit pulse accumulator Real time interrupt circuit Computer operating properly COP watchdog system 38 general purpose input output I O pins 16 bidirectional I O pins 11 input only pins 11 output only pins MC68HC11E Family Rev 4 24 General Description MOTOROLA General Description Structure Several packaging options 52 pin plastic leaded chip carrier PLCC 52 pin windowed ceramic leaded chip carrier CLCC 52 pin plastic thin quad flat pack 10 mm x 10 mm TQFP 64 pin quad flat pack QFP 48 pin plastic dual in line package DIP MC68HC811E2 only 56 pin plastic shrink dual in line package 070 inch lead spacing SDIP 1 4 Structure See Figure 1 1 for a functional diagram of the E
312. tasas de ed 228 Timer T M 230 POR External Reset Timing Diagram 231 STOP Recovery Timing 232 WAIT Recovery from Interrupt Timing Diagram 233 Interrupt Timing Diagram 234 Port Read Timing Diagram 237 Port Write Timing Diagram 237 Simple Input Strobe Timing Diagram 237 Simple Output Strobe Timing Diagram 238 Port C Input Handshake Timing Diagram 238 Port C Output Handshake Timing Diagram 238 3 State Variation of Output Handshake Timing Diagram STRA Enables Output Buffer 239 Multiplexed Expansion Bus Timing Diagram 245 SPI Timing Diagram ui deo eee RC 248 EVBU Schematic Diagram uad ied C ERROR 276 MC68HC11E Family Rev 4 20 List of Figures MOTOROLA Technical Data M68HC11E Family Table 2 1 3 1 3 2 4 2 4 3 4 4 4 5 4 6 4 7 4 8 5 2 5 3 5 4 5 5 6 1 6 2 7 1 8 1 9 1 9 2 MC68HC11E Family Rev 4 List of Tables Title Page Fort Signal FUNCIONS ios ck ee cee trinis r hekea ee 40 Reset Vector Comparison 50 57 Hardware Mode Select 82 Write Access Limited Regi
313. te of an EEPROM bit is 1 During a read operation bit lines are precharged to 1 The floating gate devices of programmed bits conduct and pull the bit lines to 0 Unprogrammed bits remain at the precharged level are read as 1s Programming bit to 1 causes no change Programming a bit to 0 changes the bit so that subsequent reads return 0 When appropriate bits in the BPROT register are cleared the PPROG register controls programming and erasing the EEPROM The PPROG register can be read or written at any time but logic enforces defined programming and erasing sequences to prevent unintentional changes to EEPROM data When the EELAT bit in the PPROG register is cleared the EEPROM can be read as if it were a ROM The on chip charge pump that generates the EEPROM programming voltage from Vpp uses MOS capacitors which are relatively small in value The efficiency of this charge pump and its drive capability are affected by the level of Vpp and the frequency of the driving clock The load depends on the number of bits being programmed or erased and capacitances in the EEPROM array The clock source driving the charge pump is software selectable When the clock select CSEL bit in the OPTION register is 0 the E clock is MC68HC11E Family Rev 4 98 Operating Modes and On Chip Memory MOTOROLA Operating Modes Memory EEPROM used when CSEL is 1 an on chip resistor capacitor RC oscillator is used
314. tected and the interrupt is recognized the current value of the program counter is stacked After interrupt service is complete reinitialize the stack pointer so repeated execution of illegal opcodes does not cause stack underflow Left uninitialized the illegal opcode vector can point to a memory location that contains an illegal opcode This condition causes an infinite loop that causes stack underflow The stack grows until the system crashes The illegal opcode trap mechanism works for all unimplemented opcodes on all four opcode map pages The address stacked as the MC68HC11E Family Rev 4 Technical Data MOTOROLA Resets and Interrupts 123 Resets and Interrupts return address for the illegal opcode interrupt is the address of the first byte of the illegal opcode Otherwise it would be almost impossible to determine whether the illegal opcode had been one or two bytes The stacked return address can be used as a pointer to the illegal opcode so the illegal opcode service routine can evaluate the offending opcode 5 6 4 Software Interrupt SWI SWlis an instruction and thus cannot be interrupted until complete SWI is not inhibited by the global mask bits in the CCR Because execution of SWI sets the mask bit once an SWI interrupt begins other interrupts are inhibited until SWI is complete or until user software clears the bit in the CCR 5 6 5 Maskable Interrupts The maskable interrupt structure of the MCU can
315. the host the SCI will receive the character as E0 or CO because of the baud rate mismatch and the bootloader will switch to 1200 baud 5 for the rest of the download operation When the baud rate is switched to 1200 baud the delay constant used to monitor the intercharacter delay also must be changed to reflect the new character time At 6 the Y index register is initialized to 0000 to point to the start of on chip RAM The index register Y is used to keep track of where the next received data byte will be stored in RAM The main loop for loading begins at 7 The number of data bytes in the downloaded program can be any number between 0 and 512 bytes the size of on chip RAM This procedure is called variable length download and is accomplished by ending the download sequence when an idle time of at least four character times occurs after the last character to be downloaded In AN1060 Rev 1 0 286 MOTOROLA AN1060 Rev 1 0 Application Note M68HC1 1 Family members which 256 bytes of RAM the download length is fixed at exactly 256 bytes plus the leading FF character The intercharacter delay counter is started 8 by loading the delay constant from TOC1 into the X index register The 19 E cycle wait loop is executed repeatedly until either a character is received 9 or the allowed intercharacter delay time expires 10 For 7812 baud the delay constant is 10 241 E cycles 539 x 19 E cycles per loo
316. the location of the 2048 bytes of EEPROM and are present only on the MC68HC81 1E2 Refer to 4 4 3 1 System Configuration Register for a description of the MC68HC811E2 CONFIG register EEPROM can be programmed or erased by software and an on chip charge pump allowing EEPROM changes using the single Vpp supply MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 81 Operating Modes Memory 4 4 2 Mode Selection Technical Data The four mode variations are selected by the logic states of the MODA and MODB pins during reset The MODA and MODB logic levels determine the logic state of SMOD and the MDA control bits in the highest priority I bit interrupt and miscellaneous HPRIO register After reset is released the mode select pins no longer influence the MCU operating mode In single chip operating mode the MODA pin is connected to a logic level 0 In expanded mode MODA is normally connected to Vpp through a pullup resistor of 4 7 The MODA also functions as the load instruction register LIR pin when the MCU is not in reset The open drain active low LIR output pin drives low during the first E cycle of each instruction The MODB pin also functions as standby power input Vstpy which allows RAM contents to be maintained in absence of Vpp Refer to Table 4 1 which is a summary of mode pin operation the mode control bits and the four operating modes Table 4 1
317. tic subtraction symbol or negation symbol two s complement MC68HC11E Family Rev 4 Condition Codes Bit not changed Bit always cleared Bit always set Bit cleared or set depending on operation Bit can be cleared cannot become set Eb O Technical Data MOTOROLA Central Processor Unit CPU 63 Central Processor Unit CPU Technical Data MC68HC11E Family Rev 4 64 Central Processor Unit CPU MOTOROLA Technical Data M68HC11E Family Section 4 Operating Modes and On Chip Memory 4 1 Contents ae 5 525855 66 43 Operating 66 4 3 1 Moder TIT 66 4 3 2 ExpandedMode 67 4 3 3 0 ceded shaq ms 67 4 3 4 ModE ee awe 68 44 Memory 544 RO Eee Sq ha 69 4 4 1 RAM and Input Output Mapping 80 4 4 2 M de Select a 82 4 4 3 System Initialization 85 4 4 3 1 System Configuration Register 86 4 4 3 2 RAM and I O Mapping Register 89 4 4 3 3 System Configuration Options Register 91 45 92 4 5 1 Programming an Individual EPROM Address 93 4 5 2 Programming the EPROM with Downl
318. tility The utility program sets the X and Y index registers to default values then receives programming data from an external host and puts itin EPROM The value in determines programming delay time The value in IY is a pointer to the first address in EPROM to be programmed default 0000 When the utility program is ready to receive programming data it sends the host the FF character Then it waits When the host sees the FF character the EPROM programming data is sent starting with the first location in the EPROM array After the last byte to be programmed is sent and the corresponding verification data is returned the programming operation is terminated by resetting the MCU For more information Motorola application note AN1060 entitled M68HC11 Bootstrap Mode has been included at the back of this document 4 5 3 EPROM and EEPROM Programming Control Register Technical Data The EPROM and EEPROM programming control register PPROG enables the EPROM programming voltage and controls the latching of data to be programmed e For MC68HC711E9 PPROG is also the EEPROM programming control register For the MC68HC711E20 EPROM programming is controlled by the EPROG register and EEPROM programming is controlled by the PPROG register MC68HC11E Family Rev 4 94 Operating Modes and On Chip Memory MOTOROLA Operating Modes Memory EPROM OTPROM Address
319. to 105 C 2 MHz MC68HC811E2VP2 40 to 125 C 2 MHz MC68HC811E2MP2 56 pin dual in line package with 0 70 inch lead spacing SDIP 2 MHz MC68HC11E9BCB2 BUFFALO ROM 0F 409 to 85 C 3 MHz MC68HC11E9BCB3 2 MHz MC68HC11E1CB2 40 C to 85 C 3 MHz MC68HC11E1CB3 No ROM 0D 40 to 105 C 2 MHz MC68HC11E1VB2 40 to 125 C 2 MHz MC68HC11E1MB2 2 MHz MC68HC11E0CB2 40 to 85 C 3 MHz MC68HC11E0CB3 No ROM no EEPROM 0C 40 to 105 C 2 MHz MC68HC11E0VB2 40 to 125 C 2 MHz MC68HC11E0MB2 Technical Data MC68HC11E Family Rev 4 264 Ordering Information MOTOROLA 13 4 Custom ROM Device Ordering Information Ordering Information Custom ROM Device Ordering Information Description Temperature Frequency MC Order Number 52 pin plastic leaded chip carrier PLCC 0 C to 70 3 MHz MC68HC11E9FN3 2 MHz MC68HC11E9CFN2 40 C to 85 C Custom ROM 3 MHz MC68HC11E9CFN3 40 C to 105 2 MHz MC68HC11E9VFN2 40 to 125 C 2 MHz MC68HC11E9MFN2 0 C to 70 3 MHz MC68HC11E20FN3 2 MHz MC68HC11E20CFN2 40 C to 85 G 20 Kbytes custom ROM 3MHz MC68HC11E20CFN3 40 to 105 C 2 MHz MC68HC11E20VFN2 40 C to 125 C 2 MHz MC68HC11E20MFN2 64 pin quad flat pack QFP 0 C to 70 C 3 MHz MC68HC11E9FU3 2 MHz MC68HC11E9CFU2 40 C to 85 C Custom ROM 3 MHz MC6
320. to 2 5 V AVg but accuracy is tested and guaranteed at 5 V 10 Technical Data MC68HC11E Family Rev 4 240 Electrical Characteristics MOTOROLA Electrical Characteristics MC68L11E9 E20 Analog to Digital Converter Characteristics 11 15 MC68L11E9 E20 Analog to Digital Converter Characteristics Characteristic Parameter Min Absolute Max Unit Resolution Number of bits resolved by A D converter 8 Bits Non linearity Maximum deviation from the ideal A D transfer __ __ 1 LSB characteristics Difference between the output of an ideal and 1 LSB an actual for 0 input voltage Fillscala ior Difference between the output of an ideal and id __ 1 LSB an actual A D for full scale input voltage Total unadjusted sum of non linearity zero error and __ 1 2 LSB error full scale error Quantization error Uncertainty because of converter resolution 1 2 LSB Difference between the actual input voltage Absolute accuracy and the full scale weighted equivalent of the x E 2 LSB binary output code all error sources included Conversion range Analog input voltage range Vni VRH V Maximum analog reference voltage Vpp 0 1 V VRL Minimum analog reference voltage Vss 0 1 VRH V AVR Minimum difference between Vay 3 0 m V Total time to perform a single d analog to digital conversion Conversion time E
321. to control the internal clock generator circuitry frequency applied to these pins is four times higher than the desired E clock rate The XTAL pin must be left unterminated when an external CMOS compatible clock input is connected to the EXTAL pin The XTAL output is normally intended to drive only a crystal CAUTION cases use caution around the oscillator pins Load capacitances shown in the oscillator circuit are specified by the crystal manufacturer and should include all stray layout capacitances Refer to Figure 2 8 and Figure 2 9 MCU EXTAL T 10 MQ 4xE CRYSTAL XTAL 4 Figure 2 8 Common Parallel Resonant Crystal Connections 4xE EXTAL CMOS COMPATIBLE EXTERNAL OSCILLATOR MCU XTAL NC Figure 2 9 External Oscillator Connections MC68HC11E Family Rev 4 Technical Data MOTOROLA Pin Descriptions 35 Pin Descriptions 2 6 E Clock Output E E isthe output connection for the internally generated E clock The signal from E is used as a timing reference The frequency of the E clock output is one fourth that of the input frequency at the XTAL and EXTAL pins When E clock output is low an internal process is taking place When it is high data is being accessed All clocks including the E clock are halted when the MCU is in stop mode To reduce RFI emissions the E clock output of most E series devices can be disabled while operating in single chip
322. to find the problems and corrected routines can be downloaded and checked before incorporating them into the main application program Bootstrap mode can also be used to interactively calibrate critical analog sensors Since this calibration is done in the final assembled system it can compensate for any errors in discrete interface circuitry and cabling between the sensor and the analog inputs to the MCU Note that this calibration routine is a downloaded program that does not take up space in the normal application program Bootstrap Mode Logic In the M68HC11 MCUs very little logic is dedicated to the bootstrap mode Consequently this mode adds almost no extra cost to the MCU system The biggest piece of circuitry for bootstrap mode is the small boot ROM This ROM is 192 bytes in the original MC68HC11A8 but some of the newest members of the M68HC11 Family such as the MC68HC711K4 have as much as 448 bytes to accommodate added features Normally this boot ROM is present in the memory map only when the MCU is reset in bootstrap mode to prevent interference with the user s normal memory space The enable for this ROM is controlled by the read boot ROM RBOOT control bit in the highest priority interrupt HPRIO register The RBOOT bit can be written by software whenever the MCU is in special test or special bootstrap modes when the MCU is in normal modes RBOOT reverts to 0 and becomes a read only bit All other logic in the MCU would b
323. toggle its output on a successful compare because a normal compare that occurs immediately before or after the force can result in an undesirable operation Address 1008 Bit7 6 5 4 3 2 1 Bit 0 Read FOCI FOC2 FOC3 FOC4 FOCS Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 12 Timer Compare Force Register CFORC FOC 1 5 Force Output Comparison Bit When the FOC bit associated with an output compare circuit is set the output compare circuit immediately performs the action it is programmed to do when an output match occurs 0 Not affected 1 Output x action occurs Bits 2 0 Unimplemented Always read 0 MC68HC11E Family Rev 4 Timing System MOTOROLA Timing System Output Compare 9 5 3 Output Compare Mask Register Use OC1M with OC 1 to specify the bits of port A that are affected by a successful OC1 compare The bits of the OC1M register correspond to PA 7 3 Address 5100 Bit 7 6 5 4 3 2 1 Bit 0 Read OC1M7 OC1M6 0 5 0 4 OC1M3 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 13 Output Compare 1 Mask Register OC1M 1 7 3 Output Compare Masks 0 OC1 disabled 1 OC1 enabled to control the corresponding pin of port A Bits 2 0 Unimplemented Always read 0 MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 191 Timing System 9 5 4 Output C
324. ts 3 0 Unimplemented Always read 0 Technical Data MC68HC11E Family Rev 4 198 Timing System MOTOROLA Timing System Real Time Interrupt RTI 9 6 Real Time Interrupt RTI MC68HC11E Family Rev 4 The real time interrupt RTI feature used to generate hardware interrupts at a fixed periodic rate is controlled and configured by two bits RTR1 and RTRO in the pulse accumulator control PACTL register The RTII bit in the TMSK2 register enables the interrupt capability The four different rates available are a product of the MCU oscillator frequency and the value of bits RTR 1 0 Refer to Table 9 5 which shows the periodic real time interrupt rates Table 9 5 RTI Rates RTR 1 0 E 3 MHz E 2 NHz 1 MHz E X MHz 00 2 731 ms 4 096 ms 8 192 ms 213 01 5 461 ms 8 192 ms 16 384 ms 214 10 10 923 16 384 32 768 215 11 21 845 ms 32 768 65 536 216 clock source for the RTI function is free running clock that cannot be stopped or interrupted except by reset This clock causes the time between successive RTI timeouts to be a constant that is independent of the software latencies associated with flag clearing and service For this reason an RTI period starts from the previous timeout not from when RTIF is cleared Every timeout causes the RTIF bit in TFLG2 to be set and if RTII is set an interrupt request is generated After
325. tstrap mode so the bootloader firmware begins executing A break is sent out the TxD pin of U3 Pullup resistor R10 and resistor R9 cause the break character to be seen at the RxD pin of U3 The bootloader performs a jump to the start of EEPROM in the master MCU U3 and starts executing the duplicator program This sequence demonstrates how to use bootstrap mode to pass control to the start of EEPROM after reset The complete listing for the duplicator program in the EEPROM of the master MCU is provided in Listing 1 MCU to MCU Duplicator Program MOTOROLA 295 Application Note COM 12 25V M68HC11EVBU KOS S S SSS ss w ww Se PREWIRED AREA WIRE WRAP AREA R11 ON ERE 5 V PP 100 l R14 C18 me 0 15 20 UF MASTER R15 MCU 10K U3 MC68HC711E9 ppg RESET PB7 VES S PBO 1 TARGET 5 MCU U6 Oc XTAL El Vpp Vpp MODB 5 R10 R7 10K 15K ah 21 20 El i z R9 10K 20 21 Cm 2 TO FROM RS232 LEVEL TRANSLATOR U4 SR Figure 6 MCU to MCU EPROM Duplicator Schematic AN1060 Rev 1 0 296 MOTOROLA AN1060 Rev 1 0 Application Note The duplicator program in EEPROM clears the DWOM contr
326. tus functions transfer complete write collision and mode fault performed by the serial peripheral status register SPSR The SPI control block represents those functions that control the SPI system through the serial peripheral control register SPCR MC68HC11E Family Rev 4 166 Serial Peripheral Interface SPI MOTOROLA Serial Peripheral Interface Functional Description Refer to Figure 8 1 which shows the SPI block diagram gt 5 INTERNAL MCU CLOCK MSB LSB gt M 8 BITSHIFTREGISTER s E d DIVIDER READ DATA BUFFER d 2 34 16 32 2 crock SELECT gt lt 1066 im a g 2 U Y Y lt SPICONTROL lt D 2 O SPISTATUS REGISTER SPI CONTROL REGISTER INTERNAL DATA BUS SPIINTERRUPT Y REQUEST Figure 8 1 SPI Block Diagram MC68HC11E Family Rev 4 Technical Data MOTOROLA Serial Peripheral Interface SPI 167 Serial Peripheral Interface SPI 8 4 SPI Transfer Formats During an SPI transfer data is simultaneously transmitted and received A serial clock line synchronizes shifting and sampling of the information on the two serial data lines A slave select line allows individual
327. uation board products also are shipped with PCbug11 For specific information about any of the PCbug11 commands see the appropriate sections in the PCbug11 User s Manual part number M68PCBUG11 D2 which is available from the Motorola Literature Distribution Center as well as the Worldwide Web at http www motorola com semiconductors The file is also on the software download system is called pcbug 1 1 pdf Mj MOTOROLA EB188 Engineering Bulletin To Execute the Program Step 1 Step 2 Step 3 Once you have obtained PCbug11 use this step by step procedure Before applying power to the programming board connect the M68HC711E9PGMR serial port P2 to one of your PC COM ports with a standard 25 pin RS 232 cable Do not use a null modem cable or adapter which swaps the transmit and receive signals between the connectors at each end of the cable Place your MC68HC81 1E2 part in the PLCC socket on your board Insert the part upside down with the notched corner pointing toward the red power LED Make sure both S1 and S2 switches are turned off Apply 5 volts to 5 volts and ground to GND on the programmer board s power connector P1 Applying voltage to the Vpp pin is not necessary Apply power to the programmer board by moving the 5 volt switch to the ON position From a DOS command line prompt start PCbug11 this way C PCBUG11 gt PCBUG11 A PORT 1 when the E9PGMR connected to COM1 or C PCBUG11 g
328. urrent can be eliminated by writing the ADPU bit to 0 The SPI system is enabled or disabled by the SPE control bit The SCI transmitter is enabled or disabled by the TE bit and the SCI receiver is enabled or disabled by the RE bit Therefore the power consumption in wait is dependent on the particular application Executing the STOP instruction while the S bit in the CCR is equal to 0 places the MCU in stop mode If the S bit is not 0 the stop opcode is treated as a no op NOP Stop mode offers minimum power consumption because all clocks including the crystal oscillator are stopped while in this mode To exit stop and resume normal processing a logic low level must be applied to one of the external interrupts IRQ or XIRQ or to the RESET pin A pending edge triggered IRQ can also bring the CPU out of stop MC68HC11E Family Rev 4 130 Resets and Interrupts MOTOROLA Resets and Interrupts Low Power Operation Because all clocks are stopped in this mode all internal peripheral functions also stop The data in the internal RAM is retained as long as Vpp power is maintained The CPU state and I O pin levels are static and are unchanged by stop Therefore when an interrupt comes to restart the system the MCU resumes processing as if there were no interruption If reset is used to restart the system a normal reset sequence results in which all I O pins and functions are also restored to their initial states To use th
329. use edges on the MC68HC11E Family Rev 4 182 Timing System MOTOROLA Timing System Input Capture to result in input captures Writing to 4 5 has no effect when the TI4 O5 register is acting as IC4 9 4 1 Timer Control Register 2 Use the control bits of this register to program input capture functions to detect a particular edge polarity on the corresponding timer input pin Each of the input capture functions can be independently configured to detect rising edges only falling edges only any edge rising or falling or to disable the input capture function The input capture functions operate independently of each other and can capture the same TCNT value if the input edges are detected within the same timer count cycle Address 1021 Bit 7 6 5 4 3 2 1 Bit 0 Read EDG4B EDG4A EDGIB EDGIA EDG2B EDG2A EDG3B EDG3A Write Reset 0 0 0 0 0 0 0 0 Figure 9 3 Timer Control Register 2 TCTL2 EDGxB and EDGxA Input Capture Edge Control Bits There are four pairs of these bits Each pair is cleared to 0 by reset and must be encoded to configure the corresponding input capture edge detector circuit IC4 functions only if the 14 05 bit in the PACTL register is set Refer to Table 9 2 for timer control configuration Table 9 2 Timer Control Configuration EDGxB EDGxA Configuration 0 0 Capture disabled 0 1 Capture on rising edge
330. uts or outputs depending on the pin that is emulating the EPROM output enable pin OE To make these data pins appear as high impedance inputs as they would non EPROM part in reset connect the PB7 OE pin to a pullup resistor The bootloader ROM must be turned off before performing the checksum program To remove the boot ROM from the memory map clear the bit in the register This is normally a write protected bit that is 0 but in bootstrap mode it is reset to 1 and can be written If the boot ROM is not disabled the checksum routine will read the contents of the boot ROM rather than the user s mask ROM or EPROM at the same addresses This problem is troublesome in cases where one MCU is bootloading to another MCU Because of transmitter double buffering there may be one character in the serial shifter as a new character is written into the transmit data register In cases such as downloading in which this 2 character pipeline is kept full a 2 character time delay occurs between when a character is written to the transmit data register and when that character finishes transmitting A little more than one more character time delay occurs between the target MCU receiving the character and echoing it back If the master MCU waits for the echo of each downloaded character before sending the next one the download process takes about twice as long as it would if transmission is treated as a separate process or if
331. vents Coupled with the four high order bits of TMSK2 the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven system Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position Address 1025 Bit 7 6 5 4 3 2 1 Bit 0 Read TOF RTIF PAOVF PAIF Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 22 Timer Interrupt Flag 2 Register TFLG2 Clear flags by writing a 1 to the corresponding bit position s TOF Timer Overflow Interrupt Flag Set when TCNT changes from FFFF to 0000 RTIF Real Time Interrupt Flag RTIF status bit is automatically set to 1 at the end of every RTI period To clear RTIF write a byte to TFLG2 with bit 6 set PAOVF Pulse Accumulator Overflow Interrupt Flag Refer to 9 8 Pulse Accumulator PAIF Pulse Accumulator Input Edge Interrupt Flag Refer to 9 8 Pulse Accumulator Bits 3 0 Unimplemented Always read 0 MC68HC11E Family Rev 4 Technical Data MOTOROLA Timing System 201 Timing System 9 6 3 Pulse Accumulator Control Register Bits RTR 1 0 of this register select the rate for the RTI system The remaining bits control the pulse accumulator and IC4 OC5 functions Address 1026 Bit 7 6 5 4 3 2 1 Bit 0 Read DDRA7 PAEN PAMOD PEDGE DDRA3 14 05 RTR1 RTRO Write Reset 0 0 0 0 0 0 0 0 Figure 9 23 Pulse Accumulator Control Register
332. vice Package LE s Q pains ue 2 Module Cable Target Head A dapter 52FN M68EM11E20 M68CBL11C M68TC11E20FN52 M68PA11E20FN52 MC68HC11E9 52PB M68EM11E20 M68CBL11C 68 11 20 52 68 11 20 52 MC68HC711E9 56B M68EM11E20 M68CBL11B M68TC11E20B56 M68PA11E20B56 64FU M68EM11E20 M68CBL11C M68TC11E20FU64 M68PA11E20FU64 MC68HC11E20 52FN M68EM11E20 M68CBL11C M68TC11E20FN52 M68PA11E20FN52 MC68HC711E20 64FU M68EM11E20 M68CBL11C M68TC11E20FU64 M68PA11E20FU64 TOR 48 P M68EM11E20 M68CBL11B 68 11 20 48 M68PA11A8P48 52FN M68EM11E20 M68CBL11C M68TC11E20FN52 M68PA11E20FN52 1 Each MMDS11 system consists of a system console Me8MMDS 1 1 an emulation module a flex cable and a target head 2 A complete EVS consists of a platform board M68HC11PFB an emulation module a flex cable and a target head 3 Each SPGMR system consists of a universal serial programmer M68SPGMR11 and a programming adapter It can be used alone or in conjunction with the MMDS 1 1 A 4 EVS Evaluation System Technical Data The EVS is an economical tool for designing debugging and evaluating target systems based on the M68HC1 1 EVS features include Monitor debugger firmware One line assembler disassembler Host computer download capability Dual memory maps 64 Kbyte monitor map that includes 16 Kbytes of monitor EPROM M68HC11 E series user map that i
333. volt device Adjustments to the circuit must be made for devices that operate at lower voltages Using the MODB Vsrpy require external hardware but can be justified when a significant amount of external circuitry is operating from Vpp If Vergy is used to maintain RAM contents reset must be held low whenever Vpp is below normal operating level Refer to Section 5 Resets and Interrupts Technical Data MC68HC11E Family Rev 4 80 Operating Modes and On Chip Memory MOTOROLA Operating Modes Memory Memory Map TO MODBWcrpy OF M68HC11 Figure 4 8 RAM Standby MODB Vstpy Connections The bootloader program is contained in the internal bootstrap ROM This ROM which appears as internal memory space at locations BFOO BFFF is enabled only if the MCU is reset in special bootstrap mode In expanded modes the ROM EPROM OTPROM if present is enabled out of reset and located at the top of the memory map if the ROMON bit in the CONFIG register is set ROM or EPROM is enabled out of reset in single chip and bootstrap modes regardless of the state of ROMON For devices with 512 bytes of EEPROM the EEPROM is located at B600 B7FF and has the same read cycle time as the internal ROM The 512 bytes of EEPROM cannot be remapped to other locations For the MC68HC811E2 EEPROM is located at F800 FFFF and can be remapped to any 4 Kbyte boundary EEPROM mapping control bits EE 3 0 in CONFIG determine
334. w PWg 1 2 to 25 ns PWe_ 475 225 ns Pulse width E high PWey 1 2 30 ns PWey 470 220 ns 4a Eand AS rise time tr 25 25 ns 4b E and AS fall time lt 25 25 ns 9 Address hold time 22 tay 1 8 toy 30 ns 95 33 ns a Non multiplexed address valid time to E rise 375 is E n tay PW tasp 80 2 AV 17 Read data setup time tpsn 30 30 ns 18 Read data hold time max tyap tpun 0 150 0 88 ns 19 Write data delay time tppw 1 8 70 ns tow 195 133 ns 21 Write data hold time tpyw 1 8 teye 30 ns 95 33 ns 55 Multiplexed address valid time to E rise i 568 JB PWeL tasp 90 23 oe 24 en 5 time to AS fall 150 _ 25 _ 25 Multiplexed address hold time tay 1 8 30 ns 95 33 ns 26 Delay time E to AS rise tagp 1 8 5 ns 2 a 120 58 ns 27 Pulse width AS high PWagy 1 4 30 ns PWasy 220 95 ns 28 Delay time AS to E rise tasen 1 8 teye 5 ns tasgp 120 58 ns 3 a fon ipsn it PS koq eese ca ee 35 MPU access time tacce PWen tACCE 440 190 ns 38 Multiplexed address delay Previous cycle MPU read 58 88 ns tman tasp 30 ns 22 MAD 1 Vpp
335. will consist of e Bulk erase Byte programming Communication server All of this functionality is provided by PCbug11 which can be found on the Motorola Web site at http www motorola com semiconductors For more information on using PCbug11 to program an E series device Motorola engineering bulletin EB296 entitled Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU has been included at the back of this document The CONFIG register on the 68HC11 is an EEPROM cell and must be programmed accordingly Operation of the CONFIG register in the MC68HC81 1E2 differs from other devices the M68HC11 E series See Figure 4 10 Figure 4 11 MC68HC11E Family Rev 4 86 Operating Modes and On Chip Memory MOTOROLA Operating Modes Memory Memory Map Address 103F Bit 7 6 5 4 3 2 1 Bit 0 Read Wants NOSEC NOCOP ROMON EEON Resets Single chip 0 0 0 0 U U 1 0 Bootstrap 0 0 0 0 U U L U U Expanded 0 0 0 0 1 U U U Test 0 0 0 0 1 U L U U Unimplemented U indicates a previously programmed bit U L indicates that the bit resets to the logic level held in the latch prior to reset but the function of COP is controlled by the DISR bitin TEST1 register Figure 4 10 System Configuration Register CONFIG Address 103F Bit 7 6 5 4 3 2 1 Bit 0 Read Vit EE3 EE2 EE1 EEO NOSEC NOCOP
336. x039 Toon opion All set or clear x03C Highest priority l bit interrupt and See HPRIO See HPRIO miscellaneous HPRIO description description x03D RAM and map register All set or clear MC68HC11E Family Rev 4 Technical Data MOTOROLA Operating Modes and On Chip Memory 85 Operating Modes Memory 4 4 3 1 System Configuration Register Technical Data NOTE The system configuration register CONFIG consists of an EEPROM byte and static latches that control the startup configuration of the MCU The contents of the EEPROM byte are transferred into static working latches during reset sequences The operation of the MCU is controlled directly by these latches and not by CONFIG itself In normal modes changes to CONFIG do not affect operation of the MCU until after the next reset sequence When programming the CONFIG register itself is accessed When the CONFIG register is read the static latches are accessed See 4 6 1 EEPROM and CONFIG Programming and Erasure for information on modifying CONFIG To take full advantage of the MCU s functionality customers can program the CONFIG register in bootstrap mode This can be accomplished by setting the mode pins to logic 0 and downloading a small program to internal RAM For more information Motorola application note AN1060 entitled M68HC11 Bootstrap Mode has been included at the back of this document The downloadable talker

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