Home

M68HC11E Family Data Sheet

1. PRINT 2 RETURN 1 k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k EX SUBROUTINE THAT CONVERTS THE HEX DIGIT IN A TO AN INTEGER 1 k k k K k k k k K k k k K K k k k k k k k k k k k k k k k k k K K k k K K k k k K k k k K k k K K k k k K K k k K K K k lt X INSTR HS AS IF X 0 THEN FLAG 1 X X 1 RETURN k k k k k k k k k k k k k k k k KKK KKK kx lt ke ke lt lt ko lt ko ko SUBROUTINE TO READ IN ONE BYTE THROUGH THE COMM PORT OPENED AS FILE 2 WAITS INDEFINITELY FOR THE BYTE TO BE RECEIVED SUBROUTINE WILL BE ABORTED BY ANY KEYBOARD INPUT RETURNS BYTE IN BS USES QS k lt k k ce k k k k lt lt k k k k KKK KKK k k lt KK k K k k k KKK ko ko ko ko WHILE LOC 2 0 FOR COMM PORT INPUT QS INKEYS 0 lt gt THEN 4900 IF ANY KEY PRESSED THEN ABORT WEND BS INPUTS 1 2 RETURN k k k k k k k K k k k K K k k k k k k K k k k k k K k k k K k k k K K k k k K k k k K k k k k k k K k k kc kk kk M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 217 Common Bootstrap Mode Problems 8491 8492 8493 8494 8500 8510 8520 8530 9499 9500 9510 9520 9530 9540 9550 9560
2. MAIN PROGRAM INTERRUPT ROUTINE 7 STACK 9D JSR PC 3B RTI SP DIRECT lt dd SP 1 CCR NEXT MAIN INSTR SP42 ACCB SP 3 ACCA I MAIN PROGRAM 554 iX AD JSR SP45 IX INDEXED X lt ff 7 STACK IV NEXT MAIN INSTR 5 7 IYL MAIN PROGRAM gt SPH 1 SP 8 RTNy Pc 18 PRE SP SP49 INDEXED Y lt JSR SWI SOFTWARE INTERRUPT CEN MAIN PROGRAM p SSIACK ug NEXT MAIN INSTR sP MAIN PROGRAM SP 8 CCR PC BD PRE SP 7 ACCB r CP SP 6 ACCA INDEXED Y y SP 5 X WAI WAIT FOR INTERRUPT H NEXT MAIN INSTR SP 4 IX L 61 MAIN PROGRAM SP 3 IY PC 3E WAI SP 2 IY BSR BRANCH TO SUBROUTINE je EE RTNH SP RTN MAIN PROGRAM STACK PC 8D BSR E SP 2 LEGEND SP 1 RTNy RTN ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO SP EXECUTED UPON RETURN FROM SUBROUTINE RTNy MOST SIGNIFICANT BYTE OF RETURN ADDRESS RTN LEAST SIGNIFICANT BYTE OF RETURN ADDRESS RTS RETURN FROM STACK POINTER POSITION AFTER OPERATION IS COMPLETE SUBROUTINE STACK dd 8 BIT DIRECT ADDRESS 0000 00FF HIGH BYTE ASSUMED TO BE 00 MAIN PROGRAM D ff 8 BIT POSITIVE OFFSET 00 0 TO FF 255 IS ADDED TO INDEX PC 39 RTS SP hh HIGH ORDER BYTE OF 16 BIT EXTENDED ADDRESS SP 1 RTNy LOW ORDER BYTE OF 16 BIT EXTENDED ADDRESS
3. 68 4 2 6 1 Rr IE irte Cees ee 68 4 2 6 2 68 4 2 6 3 ZEO Z eee ee ee ee ee ee eee ee ee eee ee gasas 68 4 2 6 4 Negare cw ie joe d dole Kae eh A cae EROR ed d le 68 4 2 6 5 miemupt Mask I ee RC enl RR CREER RR o 69 4 2 6 6 rout a T 10272 12011 1270177 69 4 2 6 7 A Intertupt Mask OO re RO CC REOR CR e oe 69 4 2 6 8 cae dudipicdaa oh p RC e CERA RUE 69 M68HC11E Family Data Sheet Rev 5 1 8 Freescale Semiconductor 4 3 4 4 4 5 4 5 1 4 5 2 4 5 3 4 5 4 4 5 5 4 5 6 4 6 5 1 5 2 5 2 1 5 2 2 5 8 9 5 2 4 9 2 9 5 2 6 5 3 5 3 1 5 3 2 5 3 3 5 3 4 5 3 5 5 3 6 5 3 7 5 3 8 5 3 9 5 3 10 5 4 5 4 1 5 5 5 5 1 5 5 2 5 5 3 5 5 4 5 5 5 5 5 6 5 6 5 6 1 5 6 2 E uqata 69 Opcodes and re 70 rcp c ooo o P sence taedbedente 70 jjj Mee Po RSS 70 Bo 70 ocior ae SOR ROR EU k as 71 eC Tm 71 ijo MCT 71 71 GN dece MM Cr 71 Chapter 5 Resets and Interrupts oa qe asrshox ba d AR Rd p
4. Vector Address Interrupt Source FFCO C1 FFD4 05 Reserved m SCI serial system SCI receive data register full RIE FEDBUDE j 1 empty WE SCI transmit complete TCIE e SCI idle line detect ILIE FFD8 D9 SPI serial transfer complete SPIE FFDA DB Pulse accumulator input edge FFDC DD Pulse accumulator overflow PAOVI FFDE DF Timer overflow TOI FFEO E1 Timer input capture 4 output compare 5 l 14 051 FFE2 E3 Timer output compare 4 OCAI FFE4 E5 Timer output compare 3 OC3I FFE6 E7 Timer output compare 2 21 FFE8 E9 Timer output compare 1 Timer input capture 3 FFEC ED Timer input capture 2 2 FFEE EF Timer input capture 1 FFFO F1 Real time interrupt l RTII FFF2 F3 IRQ external pin l None FFF4 F5 XIRQ pin x None FFF6 F7 Software interrupt None None FFF8 F9 Illegal opcode trap None None FFFA FB COP failure None NOCOP FFFC FD Clock monitor fail None CME FFFE FF RESET None None 5 5 1 Interrupt Recognition and Register Stacking An interrupt can be recognized at any time after it is enabled by its local mask if any and by the global mask bit in the CCR Once an interrupt source is recognized the CPU responds at the completion of the instruction being executed Interrupt latency varies according to the number of cycles required to complete the current instruction When the C
5. Bit 7 6 5 4 3 2 1 Bit 0 Read um R7 T7 R6 T6 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 RO TO rite Reset Indeterminate after reset Figure 7 3 Serial Communications Data Register SCDR 7 7 2 Serial Communications Control Register 1 The SCCR1 register provides the control bits that determine word length and select the method used for the wakeup feature Address 102 Bit 7 6 5 4 3 2 1 Bit 0 Read R8 T8 M WAKE Write Reset 0 0 0 0 0 0 Indeterminate after reset Unimplemented Figure 7 4 Serial Communications Control Register 1 SCCR1 R8 Receive Data Bit 8 If M bit is set R8 stores the ninth bit in the receive data character T8 Transmit Data Bit 8 If M bit is set T8 stores the ninth bit in the transmit data character Bit 5 Unimplemented Always reads 0 M Mode Bit select character format 0 Start bit 8 data bits 1 stop bit 1 Start bit 9 data bits 1 stop bit WAKE Wakeup by Address Mark ldle Bit 0 Wakeup by IDLE line recognition 1 Wakeup by address mark most significant data bit set Bits 2 0 Unimplemented Always read 0 M68HC11E Family Data Sheet Rev 5 1 110 Freescale Semiconductor SCI Registers 7 7 3 Serial Communications Control Register 2 The SCCR2 register provides the control bits that enable or disable individual SCI functions Address 1020
6. 88 Non Maskable Interrupt Request 89 89 Intemipt SWI 525355285556 5 SERS OX 90 Maskabl 90 Reset Interrupt Processing 90 Low Power OPONON 90 Wai o 9 04 04544080504 6445S E ee EEr EEk 90 SIDES ka bd E E Doi Ede ARS A E T E E E E RO ET 95 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 9 Table of Contents 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 7 1 7 2 7 3 7 4 7 5 7 5 1 7 5 2 7 6 7 7 7 7 1 7 7 2 7 7 3 7 7 4 7 7 5 7 8 7 9 8 1 8 2 8 3 8 4 8 5 8 5 1 8 5 2 8 5 3 8 5 4 8 6 8 7 8 7 1 8 7 2 8 7 3 Chapter 6 Parallel Input Output I O Ports FOCI P C OT 97 af rrr 98 es dd oic Kcd acp 99 P oL E 99 i Q0 errem 100 ga b c r rrr 101 Handshake 2 acces qne 101 Parallel VO Control Register 50505565 102 Chapter 7 Serial Communications Interface SCI dupli LC Cr 105 PADI eene hoe dead dim Petes ts das ideas 105 Transmit Operation
7. Bit 7 6 5 4 3 2 1 Bit 0 Read 2 012 013 OMA OL4 5 015 Write Reset 0 0 0 0 0 0 0 0 Figure 9 16 Timer Control Register 1 TCTL1 ON 2 5 Output Mode Bits OL 2 5 Output Level Bits These control bit pairs are encoded to specify the action taken after a successful OCx compare OC5 functions only if the 14 05 bit in the PACTL register is clear Refer to Table 9 3 for the coding Table 9 3 Timer Output Compare Actions OMx OLx Action Taken on Successful Compare 0 0 Timer disconnected from output pin logic 0 1 Toggle OCx output line 1 0 Clear OCx output line to 0 1 1 Set OCx output line to 1 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 137 Timing Systems 9 4 7 Timer Interrupt Mask 1 Register Use this 8 bit register to enable or inhibit the timer input capture and output compare interrupts Address 1022 Bit 7 6 5 4 3 2 1 Bit 0 Read 1 OC2I OC3l 14 05 2 IC3l Write Reset 0 0 0 0 0 0 0 0 Figure 9 17 Timer Interrupt Mask 1 Register TMSK1 OC11 OC4I Output Compare x Interrupt Enable Bits If the enable bit is set when the OCxF flag bit is set a hardware interrupt sequence is requested 14 051 Input Capture 4 Output Compare 5 Interrupt Enable Bit When 14 05 PACTL is 1 14 051 is the input capture 4 interrupt enable bit When 14 O5 P
8. lt SLAVE CPHA 0 TRANSFER IN PROGRESS 1 S8 ASSERTED 2 MASTER WRITES TO SPDR 3 FIRST SCK EDGE 4 SPIF SET 5 SS NEGATED Figure 8 2 SPI Transfer Format 8 5 SPI Signals This subsection contains descriptions of the four SPI signals Master in slave out MISO Master out slave in MOSI Serial clock SCK Slave select SS Any SPI output line must have its corresponding data direction bit in DDRD register set If the DDR bit is clear that line is disconnected from the SPI logic and becomes general purpose input All SPI input lines are forced to act as inputs regardless of the state of the corresponding DDR bits in DDRD register 8 5 1 Master In Slave Out MISO is one of two unidirectional serial data signals It is an input to a master device and an output from a slave device The MISO line of a slave device is placed in the high impedance state if the slave device is not selected 8 5 2 Master Out Slave In The MOSI line is the second of the two unidirectional serial data signals It is an output from a master device and an input to a slave device The master device places data on the MOSI line a half cycle before the clock edge that the slave device uses to latch the data M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 121 Serial Peripheral Interface SPI 8 5 3 Serial Clock SCK an input to a slave device is generated by the master device and synchronizes
9. 1 2 1 0 MHz 2 0 MHz mbo ni Characteristic y Min Max Min Max Frequency of operation fo m 10 WE 20 MHz E clock frequency E clock period tcvc 1000 500 ns Peripheral data setup time t m EN MCU read of ports A C D and E 109 109 nS Peripheral data hold time t read of ports A C D and PDH 50 Delay time peripheral data write tpwo 1 4 lcyc 150 ns t ns MCU writes to port A PWD 250 250 MCU writes to ports B C and D mE 400 275 Port C input data setup time tis 60 60 ns Port C input data hold time 100 100 ns Delay time E fall to STRB toes 1 4 tcyc 150 ns 400 275 ns Setup time STRA asserted to E fall taes 0 0 ns Delay time STRA asserted to port C data output valid tPcp 100 100 ns Hold time STRA negated to port C data 10 10 ns 3 state hold time tpcz 150 150 ns 1 Vpp 3 0 Vdc to 5 5 Vdc Vss 0 Vdc TA T to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 Ports C and D timing is valid for active drive CWOM and DWOM bits are not set in PIOC and SPCR registers respec tively 3 If this setup time is met STRB acknowledges in the next cycle If it is not met the response may be delayed one more cycle MOU READ OF PORT For nondatched operation of port C Figure 10 7 Port Read Timing Diagram M68HC11E Fam
10. 135 Rest 1 1 1 1 1 1 1 1 Read Timer Input Capture 4 Output 2771 Bit15 Bit14 Bit13 Bit12 Bit 11 Bit10 Bit9 Bits 101E Compare 5 Register High Write 714 05 See page 133 Reset 4 1 1 1 1 1 1 1 Timer Input Capture 4 Outout Read p n er input vap p Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 101F Compare 5 Register Low Write 114 05 See page 133 Reset 1 1 1 1 1 1 1 1 Timer Control Register 1 Read 9 OM2 OL2 OL3 014 OM5 OL5 1020 TCTL1 Write page 137 Reset Q 0 0 0 0 0 0 0 Read Timer Control Register 2 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A 1021 TCTL2 Write 131 Reset O 0 0 0 0 0 0 0 Read Timer Interrupt Mask 1 Register oot Ocal 003 14 051 2 IC3l 1022 TMSK1 Write page 138 Reset O 0 0 0 0 0 0 0 Timer Interrupt Flag 1 Read pt F ag OC1F OC2F OC3F OC4F I4 O5F IC2F IC3F 1023 TFLG1 Write page 138 Reset O 0 0 0 0 0 0 0 Read Timer Interrupt Mask 2 Register TOI RTII PAOVI PRI PRO 1024 TMSK2 Write page 139 Reset O 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected Indeterminate after reset Figure 2 7 Register and Control Bit Assignments Sheet 3 of 6 M68HC11E Family Data Sheet Rev 5 1 36 Freescale Semiconductor Addr Register Name Timer Interrupt Flag 2 1025 TFLG2 See
11. These initial states then control on chip peripheral systems to force them to known startup states as described in the following subsections 5 3 1 Central Processor Unit CPU After reset the central processor unit CPU fetches the restart vector from the appropriate address during the first three cycles and begins executing instructions The stack pointer and other CPU registers are indeterminate immediately after reset however the X and interrupt mask bits in the condition code register CCR are set to mask any interrupt requests Also the S bit in the CCR is set to inhibit stop mode M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 83 Resets and Interrupts 5 3 2 Memory Map After reset the INIT register is initialized to 01 mapping the RAM at 00 and the control registers at 1000 For the MC68HC811E2 the CONFIG register resets to FF EEPROM mapping bits EE 3 0 place the EEPROM at F800 Refer to the memory map diagram for MC68HC81 1E2 in Chapter 2 Operating Modes and On Chip Memory 5 3 3 Timer During reset the timer system is initialized to a count of 0000 The prescaler bits are cleared and all output compare registers are initialized to FFFF All input capture registers are indeterminate after reset The output compare 1 mask OC1M register is cleared so that successful OC1 compares do not affect any I O pins The other four output compares are configured so that they do not affect a
12. coke 2 2 3 To J rm 2 2 4 ESAE TER pe E 2 3 Memor SB udo ace M cade LOG RC p ORS IE ORs oes Kes 2 3 1 RAM and Input Output Mapping scs s s xk d ca ER Rer RR CER RR Rr ROI din 2 3 2 cm 2 3 3 2 2 3 3 1 System Configuration Register 2 3 3 2 and I O Mapping 5 2 3 3 3 System Configuration Options Register 2 4 FP lI 2 4 1 Programming an Individual EPROM Address 2 4 2 Programming the EPROM with Downloaded Data M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor Table of Contents 2 4 3 EPROM and EEPROM Programming Control Register 49 25 Behe bee eee eres D t T tT Tr 51 2 5 1 EEPROM and CONFIG Programming and Erasure 51 25 1 1 Register udssemouensebeiredchLB iAce Aid cQ dede qUbu des did 51 2 5 1 2 EPROM and EEPROM Programming Control Register 53 2 5 1 3 a 54 2 5 1 4 EEPROM Bi aida RR OR 54 2 5 1 5 ERFRON Dye AG oko ORC Meee PS RG GER eR ee med 55 2 5 1 6 CONFIG 55 2 5 2 EEPROM SECU 55 Chapter 3 Analog to Digital
13. 2 3 3 3 System Configuration Options Register The 8 bit special purpose system configuration options register OPTION sets internal system configuration options during initialization The time protected control bits IRQE DLY and CR 1 0 can be written only once after a reset and then they become read only This minimizes the possibility of any accidental changes to the system configuration Address 1039 Bit 7 6 5 4 3 2 1 Bit 0 Read ADPU CSEL iRQE pLy CME cri Write Reset 0 0 0 1 0 0 0 0 1 Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes Unimplemented Figure 2 13 System Configuration Options Register OPTION ADPU Analog to Digital Converter Power Up Bit Refer to Chapter 3 Analog to Digital A D Converter CSEL Clock Select Bit Selects alternate clock source for on chip EEPROM charge pump Refer to 2 5 1 EEPROM and CONFIG Programming and Erasure for more information on EEPROM use CSEL also selects the clock source for the A D converter a function discussed in Chapter 3 Analog to Digital A D Converter M68HC11E Family Data Sheet Rev 5 1 46 Freescale Semiconductor EPROM OTPROM IRQE Configure IRQ for Edge Sensitive Only Operation Bit Refer to Chapter 5 Resets and Interrupts DLY Enable Oscillator Startup Delay Bit 0 The oscillator startup delay coming ou
14. lt gt S THEN 1000 2 GOSUB 6000 4 AS lt gt 1 THEN 1000 9 REM Sl RECORD FOUND NEXT 2 DIGITS ARE THE BYTE COUNT 0 GOSUB 6000 0 GOSUB 7000 RETURNS DECIMAL IN X 16 X ADJUST FOR HIGH NIBBLE 0 GOSUB 6000 GOSUB 7000 0 BYTECOUNT BYTECOUNT X ADD LOW NIBBLE M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 215 Listing 2 BASIC Program for Personal Computer 1090 1099 1100 1102 1104 1106 1108 1110 1112 1114 1116 1118 1120 1122 1124 1129 1130 1140 1150 1160 1170 1180 1190 1200 1210 1220 1230 1250 1499 1500 1505 1510 1512 T5423 1514 1515 1520 1530 1540 1550 1560 1564 1565 1570 1590 1595 1597 1598 1599 1600 1610 1620 1625 1630 1635 BYTECOUNT REM NEXT 4 HEX DIGITS GOSUB 6000 GOSUB 7000 DDRESS 40 SUB 6000 SUB 7000 SUB 6000 SUB 7000 o o SUB 6000 OSUB 7000 Q Q gt Q Q Q Q ARRAYCNT DRESS ADDRESS DDRESS ADDRESS BYTECOUNT 3 ADJUST FOR ADDRESS CHECKSUM BECOME THE STARTING ADDRESS FOR THE DATA GET FIRST NIBBLE OF ADDRESS CONVERT TO DECIMAL 96 X GET NEXT NIBBLE 256 X 16 X DDRESS ADDRESS X ADDRESS ADRSTART INDEX INTO ARRAY REM CONVERT THE DATA DIGITS TO BINARY AND SAVE IN THE ARRAY FOR I GOSUB 6000 GOSUB 7000 Y 16 X GOSUB 6000 GOSUB 7000 X CODE
15. 8600 B7FF A BFoo 00 BFCO SPECIAL MODES ag EXT ROM INTERRUPT BFFF e D000 NORMAL MODES um INTERRUPT FFFF Y FFFF VECTORS EXPANDED BOOTSTRAP SPECIAL TEST Figure 2 3 Memory Map for MC68HC11E1 0000 A A 512 BYTES RAM EXT EXT 1000 G BYTE REGISTER BLOCK EXT EXT 103F B600 512 BYTES EEPROM B7FF BFoo BOOT SPECIAL MODES EXT LET ROM INTERRUPT pened BFFF grrr VECTORS 0000 12 KBYTES ROM EPROM NORMAL MODES PEN INTERRUPT FFFF FFFF VECTORS SINGLE EXPANDED BOOTSTRAP SPECIAL CHIP TEST Figure 2 4 Memory Map for MC68HC 7 11E9 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 0000 0000 768 BYTES RAM EXT EXT O2FF 1000 1000 A 64 BYTE REGISTER BLOCK EXT EXT 103F 9000 8 KBYTES ROM EPROM A EXT EXT B600 512 BYTES EEPROM Y Y B600 B7FF A A BOOT BFCO BF00 SPECIAL MODES EXT LET _ ROM INTERRUPT LL BEF ee D000 0000 12 KBYTES ROM EPROM NORMAL MODES INTERRUPT FFFF FFFF FFFF VECTORS SINGLE EXPANDED BOOTSTRAP SPECIAL CHIP TEST 20 Kbytes ROM EPROM are contained in two segments of 8 Kbytes and 12 Kbyt
16. BU asqa s 105 i7 15 o 75 Mec Ea 107 244 a9 D EGO ROM EONS CL Ud RHET CU ROLE RC e 107 107 AddressMark Wake rr aiian 109 SUl Enor ORICON 4 46455 45095 6404 06 46804 0 649000 R3 109 HH 109 Serial Communications Data 5 110 Serial Communications Control Register 1 110 Serial Communications Control Register 2 111 Serial Communication Status Register 112 Bug P ate asa 113 Status Flags and Infemppis 116 CL y dad a KK o Sol dod e d ado 117 Chapter 8 Serial Peripheral Interface SPI dpi PT 119 Boece DOSOUIBDODIOa cq qe ee Eod Roe EROR eee ee re er eee dde re ee 119 Se Fomai 25 pci 1d 6806 119 Wick Phase ant POENI LOBOS are dua Eria ai EoD EREE 120 SP NETTO T T T LS 121 Master 121 Master OW 42 pice qe 6685 4 84 1p RD EM 121 al DIU a ee b d dp CI d E AA dre o RO ERR LEER 122 AC dC ae dod UR habea PRG 122 I abd sided seceded REA EORR Op RA dd daba 122 igi 0 TO TIT T LIU 123
17. Memory Byte IND X 6 IND Y 18 7 DECA Decrement A 1 gt A A INH 4A 2 A Accumulator A DECB Decrement B 1 gt B B INH 5A 2 on o eme A A Accumulator B DES Decrement SP 1 SP INH 34 3 Stack Pointer DEX Decrement IX 12 IX INH 09 3 A Index Register x DEY Decrement IY 1 IY INH 18 09 4 A Index Register Y EORA opr Exclusive ORA A M gt A A IMM 88 jii 2 A A 0 with Memory A DIR 98 3 A EXT B8 hh 11 4 A IND X A8 4 A IND Y 18 A8 5 EORB opr Exclusive ORB IMM C8 11 2 0 with Memory B DIR 08 3 B EXT F8 hh 11 4 B IND X E8 4 18 E8 Iff 5 FDIV Fractional D IX gt I X r gt D INH 03 41 A A A Divide 16 by 16 IDIV Integer Divide 0 INH 02 41 0 16 by 16 INC opr Increment M 1 gt M EXT 7 hh 11 6 UL A A A Memory Byte IND X 6C 6 IND Y 18 6C 7 INCA Increment A 1 gt A A INH 4C 2 E E A A A Accumulator A M68HC11E Family Data Sheet Rev 5 1 74 Freescale Semiconductor Table 4 2 Instruction Set Sheet 4 of 7 Instruction Set
18. Bit 7 6 5 4 3 2 1 Bit 0 Read TCIE RIE ILIE TE RE RWU SBK Write Reset 0 0 0 0 0 0 0 0 Figure 7 5 Serial Communications Control Register 2 SCCR2 TIE Transmit Interrupt Enable Bit 0 TDRE interrupts disabled 1 SCI interrupt requested when TDRE status flag is set TCIE Transmit Complete Interrupt Enable Bit 0 TC interrupts disabled 1 SCI interrupt requested when TC status flag is set RIE Receiver Interrupt Enable Bit 0 RDRF and OR interrupts disabled 1 SCI interrupt requested when RDRF flag or the OR status flag is set ILIE Idle Line Interrupt Enable Bit 0 IDLE interrupts disabled 1 SCI interrupt requested when IDLE status flag is set TE Transmitter Enable Bit When TE goes from 0 to 1 one unit of idle character time logic 1 is queued as a preamble 0 Transmitter disabled 1 Transmitter enabled RE Receiver Enable Bit 0 Receiver disabled 1 Receiver enabled RWU Receiver Wakeup Control Bit 0 Normal SCI receiver 1 Wakeup enabled and receiver interrupts inhibited SBK Send Break At least one character time of break is queued and sent each time SBK is written to 1 As long as the SBK bit is set break characters are queued and sent More than one break may be sent if the transmitter is idle at the time the SBK bit is toggled on and off as the baud rate clock edge could occur between writing the 1 and writing the O to SBK 0 Break generator off 1 Brea
19. 02 12 REF 12 REF 59 199 59 13 185 Ordering Information and Mechanical Specifications 11 9 56 Pin Dual in Line Package Case 859 NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI AAAAAAAAAARAAAAAAAAAAAAAAAA Y14 5M 1982 2 CONTROLLING DIMENSION INCH 3 DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL 4 DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH MAXIMUM MOLD FLASH 0 25 0 010 INCHES MILLIMETERS DIM MIN MAX MIN MAX A 2 035 2 065 51 69 52 45 B 0 540 0 560 13 72 14 22 0 155 0 200 3 94 5 08 lt D 0 014 0 022 0 36 0 56 0 035 BSC 0 89 BSC F 0 032 0 046 0 81 1 47 G 0 070 BSC 1 778 BSC H 0 300 BSC 7 62 BSC J 0 008 0 015 0 20 0 38 SEATING K 0 15 0 135 292 L 0 600 BSC 15 24 BSC M 0 15 0 159 Jaep sla N 0 020 0 040 0 51 1 02 0 25 0 010 T A 0 25 0 010 T 11 10 48 Pin Plastic DIP Case 767 NOTE The MC68HC81 1E2 is the only member of the E series that is offered a 48 pin plastic dual in line package NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION INCH 3 DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL 4 DIMENSIONS A AND INCLUDE
20. to Vpp 1 4 6 Non Maskable Interrupt XIRQ Vppg The XIRQ input provides a means of requesting a non maskable interrupt after reset initialization During reset the X bit in the condition code register CCR is set and any interrupt is masked until MCU software enables it Because the XIRQ input is level sensitive it can be connected to a multiple source wired OR network with an external pullup resistor to Vpp XIRQ is often used as a power loss detect interrupt Whenever XIRQ or IRQ is used with multiple interrupt sources each source must drive the interrupt input with an open drain type of driver to avoid contention between outputs M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 23 General Description NOTE IRQ must be configured for level sensitive operation if there is more than one source of IRQ interrupt There should be a single pullup resistor near the MCU interrupt input pin typically 4 7 There must also be an interlock mechanism at each interrupt source so that the source holds the interrupt line low until the MCU recognizes and acknowledges the interrupt request If one or more interrupt sources are still pending after the MCU services a request the interrupt line will still be held low and the MCU will be interrupted again as soon as the interrupt mask bit in the MCU is cleared normally upon return from an interrupt Refer to Chapter 5 Resets and Interrupts Vppe is the input for the 12 v
21. EDGxB EDGxA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge 9 3 2 Timer Input Capture Registers When an edge has been detected and synchronized the 16 bit free running counter value is transferred into the input capture register pair as a single 16 bit parallel transfer Timer counter value captures and timer counter incrementing occur on opposite half cycles of the phase 2 clock so that the count value is stable whenever a capture occurs The timer input capture registers are not affected by reset Input capture values can be read from a pair of 8 bit read only registers A read of the high order byte of an M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 131 Timing Systems input capture register pair inhibits a new capture transfer for one bus cycle If a double byte read instruction such as load double accumulator D LDD is used to read the captured value coherency is assured When a new input capture occurs immediately after a high order byte read transfer is delayed for an additional cycle but the value is not lost Register name Timer Input Capture 1 Register High Address 1010 Bit 7 6 5 4 3 2 1 Bit 0 Read i Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset Indeterminate after reset Register name Timer Input Capture 1 Register Low Address
22. FFE9 Figure 5 6 Interrupt Priority Resolution Sheet 1 of 2 Freescale Semiconductor M68HC11E Family Data Sheet Rev 5 1 Low Power Operation 93 Resets and Interrupts 94 9 lt FLAG OC4F 1 N FLAG I4 OBIF 1 N gt FLAG Y PAOVF 1 N FLAG Y 1 N FLAGS SPIF 1 OR MODF 1 ORO SCI INTERRUPT SEE FIGURE Figure 5 6 Interrupt Priority Resolution Sheet 2 of 2 2B E ET E SESS p s SERERE END M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor Low Power Operation BEGIN lt FLA RDRF 1 N Y lt 9 4 994 Y NO VALID SCI REQUEST VALID SCI REQUEST Figure 5 7 Interrupt Source Resolution Within SCI 5 6 2 Stop Mode Executing the STOP instruction while the S bit in the CCR is equal to 0 places the MCU in stop mode If the S bit is not 0 the stop opcode is treated as a no op Stop mode offers minimum power consumption because all clocks including the crystal oscillator are stopped while in this mode To exit stop and resume normal processing a logic low level must be applied to one of the external interrupts IRQ or XIRQ or to the RESET pin
23. Hardware instruction breakpoints over either the 64 Kbyte M68HC11 memory map or over a 1 Mbyte bank switched memory map 32 real time variables nine of which can be displayed in the variables window These variables may be read or written while the MCU is running 32 bytes of real time memory can be displayed in the memory window This memory may be read or written while the MCU is running 64 Kbytes of fast emulation memory SRAM Current limited target input output connections Six software selectable oscillator clock sources five internally generated frequencies and an external frequency via a bus analyzer logic clip Command and response logging to MS DOS disk files to save session history e SCRIPT command for automatic execution of a sequence of MMDS11 commands e Assembly or C language source level debugging with global variable viewing e Host emulator communications speeds as high as 57 600 baud for quick program loading 9 MS DOS is a registered trademark of Microsoft Corporation M68HC11E Family Data Sheet Rev 5 1 188 Freescale Semiconductor 5 SPGMR11 Serial Programmer for M68HC11 MCUs Extensive on line MCU information via the CHIPINFO command View memory map vectors register and pinout information pertaining to the device being emulated Host software supports An editor assembler and user interface Source level debug analysis m
24. PROGRAM JMP PRGROUT EPROM programming utility UPLOAD EQU Upload utility k k K k k k k k k k k k k k k k K k k k k k k k k k k k k K K k k k K k k k lt K K k k ck K k ck kk UPLOAD Utility subroutine to send data from inside the MCU to the host via the SCI interface Prior to calling UPLOAD set baud rate turn SCI and set Y first address to upload Bootloader leaves baud set SCI enabled and Y pointing at EPROM start D000 so these default values do not have to be changed typically Consecutive locations are sent via SCI in an infinite loop Reset stops the upload process kkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk LDX 1000 Point to internal registers UPLOOP LDAA 0 Y Read byte BRCLR SCSR X 80 Wait for TDRE STAA SCDAT X Send it INY BRA UPLOOP Next K k k k k k k k k k k k k K k k k k k k k k K k k k k K k k k K k k k k k k k k k K k k kk PROGRAM Utility subroutine to program EPROM Prior to calling PROGRAM set baud rate turn SCI Set X 2ms prog delay constant and set Y first address to program SP must point to RAM Bootloader leaves baud set SCI enabled X 4200 and Y pointing at EPROM start D000 so these default values don t have to be changed typically Delay constant in X should be equivalent to 2 ms at 2 1 MHz X 4200 at 1 MHz X 2000 An external voltage source is required for EPROM programming F HF X M68
25. 4 A IND Y 18 A1 5 Freescale Semiconductor M68HC11E Family Data Sheet Rev 5 1 73 Central Processor Unit CPU Table 4 2 Instruction Set Sheet 3 of 7 M 4 ti D ipti Addressing Instruction Condition Codes Mode Opcode Opeand Cydes S X H I NI Z v C Compare B to B M B IMM C1 jii 2 ME IN A A A Memory B DIR D1 3 B EXT Fl hh 11 4 B IND X E1 4 B IND Y 18 E1 5 COM opr Ones FF M gt M EXT 73 11 6 La a A A 0 1 Complement IND X 63 ff 6 Memory Byte IND Y 18 63 7 COMA Ones FF A gt A A INH 43 2 0 1 Complement A COMB Ones FF B B B INH 53 2 0 1 Complement B CPD opr Compare D to D M M 1 IMM 1A 83 11 kk 5 Memory 16 Bit DIR 1A 93 6 1A B3 hh 11 7 IND X 1A 7 IND Y CD 7 Compare X to IX M M 1 IMM 8C jj kk 4 G A A A A Memory 16 Bit DIR 9C 5 EXT BC hh 11 6 IND X 6 IND Y CD Y CPY opr Compare Y to IY M M 1 IMM 18 8C jj kk 5 XA dms A A A Memory 16 Bit DIR 18 9C 6 18 BC hh 11 7 IND X 1A ff T IND Y 18 ff 7 DAA Decimal Adjust Adjust Sum to BCD INH 19 2 SSS E A A A A DEC opr Decrement 1 hh 11 6 e
26. Quy oC o RC CR 137 Timer Interrupt Mask 1 138 Timer Interrupt Flag 1 138 Timer I terrapi Mask 2 ACG cc cheeses llu sl uusha oas ki cet pus 139 Timer Interrupt Flag Register 2 140 RealTime Intertapi AR AE ea 140 Timer Interrupt Mask Register 2 xa kk a 9 EROR ACRIOR 141 Timer Flag Register 2 is sea dee Y pO EXEC LERI ERR CAR RR 142 Pulse Accumulator Control Register 142 Computer Operating Properly COP Watchdog Function 143 Pulse POCA 143 Pulse Accumulator Control Register 145 Pulse Accumulator Count Register 146 Pulse Accumulator Status and Interrupt 146 Chapter 10 Electrical Characteristics 149 Maximum Ratings for Standard and Extended Voltage 149 Functional Operating Range oe ce Fere UE 150 Thermal erates a as 695240056 440540 FPS C ERR 150 DC Electrical iiia a E ER ERE KE 151 Supply Currents and Power Dissipati
27. STORE RECEIVED DATA TO RAM LLY 11 TRANSMIT ECHO FOR VERIFY 12 POINT AT NEXT LOCATION 13 o 4l PASTENDOFRAM 9 YES 15 STAR SET UP FOR PROGRAM UTILITY X PROGRAMMING TIME CONSTANT 16 START OF EPROM JUMP TO START OF RAM 0000 17 Figure 3 MC68HC711E9 Bootloader Flowchart M68HC11 Bootstrap Mode Rev 1 1 200 Freescale Semiconductor UPLOAD Utility UPLOAD Utility The UPLOAD utility subroutine transfers data from the MCU to a host computer system over the SCI serial data link NOTE Only EPROM versions of the M68HC 11 include this utility Verification of EPROM contents is one example of how the UPLOAD utility could be used Before calling this program the Y index register is loaded by user firmware with the address of the first data byte to be uploaded If a baud rate other than the current SCI baud rate is to be used for the upload process the user s firmware must also write to the baud register The UPLOAD program sends successive bytes of data out the SCI transmitter until a reset is issued the upload loop is infinite For a complete commented listing example of the UPLOAD utility refer to Listing 3 MC68HC711E9 Bootloader ROM EPROM Programming Utility The EPROM programming utility is one way of programming data into the internal EPROM of the MC68HC711E9 MCU An external 12 V programming powe
28. 29 Chapter Analog to Digital A D Converter 57 Chapter 4 Central Processor Unit 65 Chapter 5 Resets and Interrupts 79 Chapter 6 Parallel Input Output I O Ports 97 Chapter 7 Serial Communications Interface 5 105 Chapter 8 Serial Peripheral Interface 119 Chapter 9 Timing 127 Chapter 10 Electrical 149 Chapter 11 Ordering Information and Mechanical Specifications 177 Appendix A Development 187 Appendix B EVBU Schemalie eee nen eae 191 AN1060 M68HC11 Bootstrap Mode 193 EB184 Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711bE9PGMR 229 EB188 Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR 233 EB296 Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU eR e ORA RC RR RR CR C RC d 237 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 5 p List of Chapters M68HC11E Famil
29. B600 B603 B605 B607 B609 B60B B60F B611 B613 B616 B618 B61B B61D B620 B621 B623 B625 B627 B62B B62D B630 B634 B637 B639 B63B B63E B640 B642 B646 B648 B64B B64D B64F B653 B655 B658 B65A B65D B65F B65F B661 B663 B663 7F103D 8604 9728 8680 9704 132E20FC 86FF 972F CEB675 8D53 8CB67D 26F9 CE06A7 09 26FD 962E 962F 132E20FC 962F CED000 18CE523D 150402 960A 2AF5 140402 1809 26F5 18CED000 8D23 8C0000 2702 8D1C 132E20FC 962F 18A100 2705 150403 2007 1808 26E5 140401 k K k k k k k k k k k k k k k k k k k k k k k k kk BEGIN CLR INIT LDAA 804 STAA SPCR LDAA RESET STAA PORTB WT4BRK BRCLR SCSR RDRF WT4 LDAA STAA SCDR LDX BLPROG BLLOOP BSR SEND1 CPX ENDBPR BNE BLLOOP kkkkxk Delay for about 4 char times SCI communications to finish Rx related flags LDX 1703 DLYLP DEX BNE DLYLP LDAA SCSR LDAA SCDR Now wait for character from t data to be programmed into EP WTAFF BRCLR SCSR RDRF LDAA SCDR LDX EPSTRT Handle turn on of Vpp WT4VPP LDY 21053 BCLR PORTB RED DLYLP2 LDAA PORTE BPL WTAVPP BSET PORTB RED DEY BNE DLYLP2 Vpp has been stable for 200ms Listing 1 MCU to MCU Duplicator Program k k k k k k k k ck ck k k kk kk Moves Registers to 0000 3F Pattern for DWOM off no SPI Turns off DWOM in EVBU MCU Release reset to target MCU Loop
30. Bit 7 6 5 4 3 2 1 Bit 0 Read ADPU CSEL iRQE Div CME cri Write Reset 0 0 0 1 0 0 0 0 1 Can be written only once in first 64 cycles out of reset in normal mode or at any time in special modes Unimplemented Figure 5 2 System Configuration Options Register OPTION ADPU Analog to Digital Converter Power Up Bit Refer to Chapter 3 Analog to Digital A D Converter CSEL Clock Select Bit Refer to Chapter 3 Analog to Digital A D Converter IRQE Configure IRQ for Edge Sensitive Only Operation Bit 0 IRQ is configured for level sensitive operation 1 IRQ is configured for edge sensitive only operation DLY Enable Oscillator Startup Delay Bit Refer to Chapter 2 Operating Modes and On Chip Memory and Chapter 3 Analog to Digital A D Converter CME Clock Monitor Enable Bit This control bit can be read or written at any time and controls whether or not the internal clock monitor circuit triggers a reset sequence when the system clock is slow or absent When it is clear the clock monitor circuit is disabled and when it is set the clock monitor circuit is enabled Reset clears the CME bit 0 Clock monitor circuit disabled 1 Slow or stopped clocks cause reset Bit 2 Unimplemented Always reads 0 CR 1 0 COP Timer Rate Select Bit The internal E clock is first divided by 215 before it enters the COP watchdog system These control bits determine a scaling factor for the w
31. M68HC11E Family Data Sheet Rev 5 1 177 Ordering Information and Mechanical Specifications Description CONFIG Temperature Frequency MC Order Number 52 pin plastic leaded chip carrier PLCC Continued 2 MHz MC68HC711E9CFN2 40 to 85 3 MHz MC68HC711E9CFN3 OTPROM 40 to 105 2 MHz MC68HC711E9VFN2 409 to 125 C 2 MHz MC68HC711E9MFN2 ehh 40 to 85 C 2 MHz MC68S711E9CFN2 eature 0 C to 70 C 3 MHz MC68HC711E20FN3 2 MHz MC68HC711E20CFN2 40 to 85 20 Kbytes OTPROM 0F 3 MHz MC68HC711E20CFN3 40 to 105 C 2 MHz MC68HC711E20VFN2 40 C to 125 C 2 MHz MC68HC711E20MFN2 0 C to 70 C 2 MHz MC68HC811E2FN2 40 C to 85 C 2 MHz MC68HC811E2CFN2 No ROM 2 Kbytes EEPROM FF 40 C to 105 C 2 MHz MC68HC811E2VFN2 40 C to 125 C 2 MHz MC68HC811E2MFN2 64 pin quad flat pack QFP 2 MHz MC68HC11E9BCFU2 BUFFALO ROM 0F 40 to 85 C 3 MHz MC68HC11E9BCFU3 2 MHz MC68HC11E1CFU2 40 to 85 C No ROM 0D 3 MHz MC68HC11E1CFU3 40 C to 105 C 2 MHz MC68HC11E1VFU2 40 C to 85 C 2 MHz MC68HC11E0CFU2 No ROM no EEPROM 0C 40 C to 105 C 2 MHz MC68HC11EO0VFU2 0 C to 70 C 3MHz MC68HC711E20FU3 2 MHz MC68HC711E20CFU2 40 to 85 C 20 Kbytes OTPROM 0F 3 MHz MC68HC711E20CFU3 40 to 105 C 2 MHz MC68HC711E20VFU2 40 to 125 C 2 MHz
32. Register X EXT FF hh 11 5 IND X EF ff 5 IND Y CD EF ff 6 STY opr Store Index IY 2M M 1 DIR 18 DF 5 MEL A 0 m Register Y EXT 18 FF hh 11 6 IND X 1A EF 6 IND Y 18 EF 6 SUBA Subtract A M gt A A IMM 80 jii 2 CAUCA A A A Memory from A DIR 90 3 A A EXT BO hh 11 4 A IND X AO 4 IND Y 18 AO 5 SUBB opr Subtract CO jii 2 Memory from A DIR 3 B A EXT FO hh 11 4 A IND X EO 4 A IND Y 18 EO 5 SUBD Subtract D M M 1 gt D IMM 83 51 kk 4 Say dae A A A A Memory from DIR 93 5 D EXT B3 hh 11 6 IND X 6 IND Y 18 7 SWI Software See Figure 3 2 INH 3F 14 1 Interrupt TAB Transfer A to B 16 2 SS A A 0 TAP Transfer to CCR INH 06 2 A A A CC Register TBA Transfer to A B gt A INH 17 2 eS mM A 0 TEST TEST Only in Address Bus Counts INH 00 Test Modes TPA Transfer CC gt A INH 07 2 Register to A TST opr Test for Zero or M 0 EXT 7D hh 11 6 UG A 0 0 Minus IND X 60 6 18 60 7 Freescale Semiconductor M68HC11E Family Data Sheet Rev 5 1 77 Central Processor Unit CPU Table 4 2 Instruction Set Sheet 7 of 7 78 Mnemonic Operation Description Addressing Instruction Con
33. SPI INTERRUPT Y REQUEST DATA BUS Figure 8 1 SPI Block Diagram 8 4 Clock Phase and Polarity Controls Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI control register SPCR The clock polarity is specified by the CPOL control bit which selects an active high or active low clock and has no significant effect on the transfer format The clock phase CPHA control bit selects one of two different transfer formats The clock phase and polarity should be identical for the master SPI device and the communicating slave device In some cases the phase and polarity are changed between transfers to allow a master device to communicate with peripheral slaves having different requirements When CPHA equals 0 the SS line must be negated and reasserted between each successive serial byte Also if the slave writes data to the SPI data register SPDR while SS is low a write collision error results When CPHA equals 1 the SS line can remain low between successive transfers M68HC11E Family Data Sheet Rev 5 1 120 Freescale Semiconductor SPI Signals CYCLE CPOL 0 zm SCK CPOL 1 V Vs NV VA VF NV N VJ SAMPLE INPUT 0 DATA OUT SAMPLE INPUT CPHA 1 DATA OUT 55 TOSLAVE Y l l 1 1 1 1 1 1 SLAVE 1 TRANSFER IN PROGRES 3 lt MASTER TRANSFER IN PROGRESS
34. Highest Priority Bit Interrupt and Miscellaneous Register HPRIO See page 41 RAM and Mapping Register INIT See page 45 Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset PTCON BPRT3 BPRT2 BPRT1 BPRTO 0 0 0 1 1 1 1 1 MBE ELAT EXCOL EXROW Ti TO PGM 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R ADPU CSEL IRQE CME cri 0 0 0 1 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 ODD EVEN ELAT BYTE ROW ERASE EELAT EPGM 0 0 0 0 0 0 0 0 RBOOT SMOD MDA IRV NE PSEL3 PSEL2 PSEL1 PSELO 0 0 0 0 0 1 1 0 RAM2 RAM1 RAMO REG3 REG2 REG1 REGO 0 0 0 0 0 0 0 1 Unimplemented R Reserved U Unaffected Indeterminate after reset Figure 2 7 Register and Control Bit Assignments Sheet 5 o
35. PPROG PPROG is the combined EPROM OTPROM and EEPROM programming register on all devices with EPROM OTPROM except the MC68HC711E20 For the MC68HC711E20 there is a separate register for EPROM OTPROM programming called the EPROG register As described in the following subsections these two methods of programming and verifying EPROM are possible 1 Programming an individual EPROM address 2 Programming the EPROM with downloaded data M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 47 Operating Modes and On Chip Memory 2 4 4 Programming an Individual EPROM Address In this method the MCU programs its own EPROM by controlling the PPROG register EPROG MC68HC711E20 Use these procedures to program the EPROM through the MCU with The ROMON bit set in the CONFIG register The 12 volt nominal programming voltage present on the XIRQ Vppg pin The IRQ pin must be pulled high NOTE Any operating mode can be used This example applies to all devices with EPROM OTPROM except for the MC68HC711E20 EPROG LDAB 520 STAB 103B Set ELAT bit in EPGM 0 to enable EPROM latches STAA 50 Store data to EPROM address LDAB 521 STAB 103B Set EPGM bit with ELAT 1 to enable EPROM programming voltage JSR DLYEP Delay 2 4 ms CLR 103B Turn off programming voltage and set to READ mode This example applies only to MC68HC71 1E20 EPROG LDAB 520 STAB 1036 Set ELAT bit EPGM 0 to enable E
36. RTN tt SIGNED RELATIVE OFFSET 80 128 TO 7F 127 OFFSET L RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE Freescale Semiconductor OFFSET BYTE Figure 4 2 Stacking Operations M68HC11E Family Data Sheet Rev 5 1 67 Central Processor Unit CPU 4 2 5 Program Counter PC The program counter a 16 bit register contains the address of the next instruction to be executed After reset the program counter is initialized from one of six possible vectors depending on operating mode and the cause of reset See Table 4 1 Table 4 1 Reset Vector Comparison Mode POR or RESET Pin Clock Monitor COP Watchdog Normal FFFE FFFC D FFFA B Test or Boot BFFE BFFC D B 4 2 6 Condition Code Register CCR This 8 bit register contains Five condition code indicators C V Z and H Two interrupt masking bits IRQ and XIRQ Astop disable bit S In the M68HC11 CPU condition codes are updated automatically by most instructions For example load accumulator A LDAA and store accumulator A STAA instructions automatically set or clear the N Z and V condition code flags Pushes pulls add B to X ABX add B to Y ABY and transfer exchange instructions do not affect the condition codes Refer to Table 4 2 which shows what condition codes are affected by a particular instruction 4 2 6 1 Carry Borrow C The C bit is set if the arithmetic logic
37. SCR 2 0 SCI Baud Rate Select Bits Selects receiver and transmitter bit rate based on output from baud rate prescaler stage Refer to Figure 7 8 and Figure 7 9 The prescaler bits SCP 2 0 determine the highest baud rate and the SCR 2 0 bits select an additional binary submultiple 1 2 4 through 128 of this highest baud rate The result of these two dividers in series is the 16X receiver baud rate clock The SCR 2 0 bits are not affected by reset and can be changed at any time although they should not be changed when any SCI transfer is in progress Figure 7 8 and Figure 7 9 illustrate the SCI baud rate timing chain The prescaler select bits determine the highest baud rate The rate select bits determine additional divide by two stages to arrive at the receiver timing RT clock rate The baud rate clock is the result of dividing the RT clock by 16 EXTAL p sae a INTERNAL BUS CLOCK PH2 CLOCK GENERATOR gt e lt 4 XTAL FE EET EET m E 0 mas 10 13 e SCR 2 0 0 0 0 2 0 0 1 e 2 0 1 0 2 0 1 1 25 gt 16 2 1 0 0 SCI TRANSMIT 29 1 0 1 BAUD RATE 1X e 35 1 1 0 ES 1 1 1 2 SCI RECEIVE BAUD RATE 16X Figure 7 8 SCI Baud Rate Generator Block D
38. STACK CPU REGISTERS SS SET BITS I AND X y FETCH VECTOR SFFF4 FFF5 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 91 Resets and Interrupts STACK CPU REGISTERS GNE Y FETCH VECTOR SFFF8 FFF9 STACK CPU REGISTERS Y SET BIT IIN CCR FETCH VECTOR FFF6 FFF7 RESTORE CPU REGISTERS FROM STACK BIT IN FETCH OPCODE ILLEGAL OPCODE WAI INSTRUCTION EXECUTE THIS INSTRUCTION ANY I BITX INTERRUPT S AOI EEU PENDING STACK CPU REGISTERS ANY INTERRUPT PENDING SET BIT CCR RESOLVE INTERRUPT PRIORITY AND FETCH VECTOR FOR HIGHEST PENDING SOURCE SEE FIGURE 5 2 Figure 5 5 Processing Flow Out of Reset Sheet 2 of 2 M68HC11E Family Data Sheet Rev 5 1 92 Freescale Semiconductor BEGIN XIRQ PIN SET X BIT IN CCR LOW FFF4 HIGHEST PRIORITY FETCH VECTOR FFF5 YES FETCH VECTOR FETCH VECTOR SFFF2 FFF3 REAL TIME INTERRUPT SFFFO FETCH VECTOR FFF1 FFEE FETCH VECTOR FFEF FFEC FETCH VECTOR FFED FETCH VECTOR FFEA FFEB FFE8 FETCH VECTOR
39. Symbol Table Symbol Name V BEGI BLLO BLPR N OP OG DATALP DLYL DLYL DUNP ENDB EPST GREE INIT PORT PORT PROG RDRF RED RESE SCDR SCSR SEND SPCR TDRE TRDY VERF VERF WT4B WTAF P P2 RG PR RT N B E RAM T 1 OK RK F WT4VPP DUNPRG BCLR PORTB RESET RED Red OFF apply reset BRA Done so just hang kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Subroutine to get amp send an SCI char Also advances pointer X kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk SEND1 LDAA 0 X Get a character TRDYLP BRCLR SCSR TDRE TRDYLP Wait for TDRE STAA SCDR Send character INX Advance pointer RTS Return k k k k k k k k k k k k k k k k k k k k k k k k K k k k K k k k K K k k ck ck k k k kk kk Program to be bootloaded to target 711E9 ck k k k k k k k k k k k k k k k k k k k k k k k k kx k k kx k k k k k lt ko BLPROG LDAA 504 Pattern for DWOM off SPI STAA 1028 Turns off DWOM in target MCU NOTE Can t use direct addressing in target MCU because regs are located at 1000 JMP PROGRAM Jumps to EPROM prog routine ENDBPR EQU alue Def Line Number Cross Reference B600 00029 B616 00038 00040 B675 00099 00037 B648 00068 00079 B620 00046 00047 B637 00059 00063 B666 00083 00076 B67D 00104 00039 2000 00023 00055 00066 0001 00015 00075 00081 103D 00009 00029 0004 00011 00033 00058 0006
40. The input capture function records the time an external event occurs by latching the value of the free running counter when a selected edge is detected at the associated timer input pin Software can store latched values and use them to compute the periodicity and duration of events For example by storing the times of successive edges of an incoming signal software can determine the period and pulse width of a signal To measure period two successive edges of the same polarity are captured To measure pulse width two alternate polarity edges are captured In most cases input capture edges are asynchronous to the internal timer counter which is clocked relative to an internal clock PH2 These asynchronous capture requests are synchronized to PH2 so that the latching occurs on the opposite half cycle of PH2 from when the timer counter is being incremented This synchronization process introduces a delay from when the edge occurs to when the counter value is detected Because these delays offset each other when the time between two edges is being measured the delay can be ignored When an input capture is being used with an output compare there is a similar delay between the actual compare point and when the output pin changes state M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 129 Timing Systems PRESCALER DIVIDE BY TCNT H TCNT LO TOI C MCU 1 4 8 0116 16 BIT FREE RUNNING TOF ECLK PRI PRO COUNTER T
41. 0 Programming voltage to EPROM array disconnected 1 Programming voltage to EPROM array connected 2 5 EEPROM Some E series devices contain 512 bytes of on chip EEPROM The MC68HC811E2 contains 2048 bytes of EEPROM with selectable base address All E series devices contain the EEPROM based CONFIG register 2 5 1 EEPROM and CONFIG Programming and Erasure The erased state of an EEPROM bit is 1 During a read operation bit lines are precharged to 1 The floating gate devices of programmed bits conduct and pull the bit lines to 0 Unprogrammed bits remain at the precharged level and are read as ones Programming a bit to 1 causes no change Programming a bit to O changes the bit so that subsequent reads return O When appropriate bits the BPROT register are cleared the PPROG register controls programming and erasing the EEPROM The PPROG register can be read or written at any time but logic enforces defined programming and erasing sequences to prevent unintentional changes to EEPROM data When the EELAT bit in the PPROG register is cleared the EEPROM can be read as if it were a ROM The on chip charge pump that generates the EEPROM programming voltage from Vpp uses MOS capacitors which are relatively small in value The efficiency of this charge pump and its drive capability are affected by the level of Vpp and the frequency of the driving clock The load depends on the number of bits being programmed or erased and capacitances in the E
42. 0 83 0 51 ns 19 Write data delay time tppw 1 8 65 5 ns tppw 190 5 128 71 ns 21 Write data hold time tpyw 1 8 29 5 ns tonw 95 5 33 26 ns 55 Multiplexed address valid time to E rise i 27158 B 7 AVM ns PW tasp 90 ns 54 Multiplexed address valid time to AS fall be tASL PWAsH 70 ns ASL m m ns Multiplexed address hold time BE 33 31 1 8 29 5 ns 3 b AHE Lr 26 Delay time E to AS rise tasp 1 8 9 5 ns Sa taso 115 5 53 31 ns 27 Pulse width AS high PWagy 1 4 29 ns PWasQ 221 96 63 ns 28 Delay time AS to E rise tagen 1 8 9 5 ns 90 tasep 1155 53 31 ns MPU address access time 9 29 tacca 744 5 307 196 ns tacca tcvc PWgi tpsn tr 35 MPU access time tacce PWzgu tpsr tacce 442 LI 192 111 ns 3B Multiplexed address delay Previous cycle MPU read i 54 Bi tasp 30 nsl 3a 72 ns 1 Vpp 5 0 10 Vss 0 Ta T to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless oth erwise noted 2 Formula only for dc to 2 MHz 3 Input clocks with duty cycles other than 50 affect bus performance Timing parameters affected by input clock duty cycle are identified by a and b T
43. 1100 Timer output compare 2 1101 Timer output compare 3 1110 Timer output compare 4 1111 Timer input capture 4 output compare 5 5 5 Interrupts Interrupts The MCU has 18 interrupt vectors that support 22 interrupt sources The 15 maskable interrupts are generated by on chip peripheral systems These interrupts are recognized when the global interrupt mask bit 1 in the condition code register CCR is clear The three non maskable interrupt sources are illegal opcode trap software interrupt and XIRQ pin Refer to Table 5 4 which shows the interrupt sources and vector assignments for each source For some interrupt sources such as the SCI interrupts the flags are automatically cleared during the normal course of responding to the interrupt requests For example the flag in the SCI system is cleared by the automatic clearing mechanism consisting of a read of the SCI status register while RDRF is set followed by a read of the SCI data register The normal response to interrupt request would be to read the SCI status register to check for receive errors then to read the received data from the SCI data register These steps satisfy the automatic clearing mechanism without requiring special instructions M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 87 Resets and Interrupts Table 5 4 Interrupt and Reset Vector Assignments
44. 2 5 1 2 EPROM and EEPROM Programming Control Register The EPROM and EEPROM programming control register PPROG selects and controls the EEPROM programming function Bits in PPROG enable the programming voltage control the latching of data to be programmed and select the method of erasure for example byte row etc Address 103B Bit 7 6 5 4 3 2 1 Bit 0 Read 1 Wis ODD EVEN ELAT BYTE ROW ERASE EELAT EPGM rite Reset 0 0 0 0 0 0 0 0 1 MC68HC711E9 only Figure 2 17 EPROM and EEPROM Programming Control Register PPROG ODD Program Odd Rows in Half of EEPROM Test Bit EVEN Program Even Rows in Half of EEPROM Test Bit ELAT EPROM OTPROM Latch Control Bit For the MC68HC711E9 EPGM enables the high voltage necessary for both EPROM OTPROM and EEPROM programming For MC68HC711E9 ELAT and EELAT are mutually exclusive and cannot both equal 1 0 EPROM address and data bus configured for normal reads 1 EPROM address and data bus configured for programming BYTE Byte Other EEPROM Erase Mode Bit This bit overrides the ROW bit 0 Row or bulk erase 1 Erase only one byte ROW Row All EEPROM Erase Mode Bit If BYTE is 1 ROW has no meaning 0 Bulk erase 1 Row erase Table 2 8 EEPROM Erase BYTE ROW Action 0 0 Bulk erase entire array 0 1 Row erase 16 bytes 1 0 Byte erase 1 1 Byte erase ERASE Erase Mode Select Bit 0 Norm
45. 68 11 Data Sheet HC11 Microcontrollers M68HC11E Rev 5 1 07 2005 freescale com freescale semiconductor MC68HC11E Family Data Sheet To provide the most up to date information the revision of our documents on the World Wide Web will be the most current Your printed copy may be an earlier revision To verify you have the latest information available refer to http freescale com The following revision history table summarizes changes contained in this document For your convenience the page number designators have been linked to the appropriate location Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Freescale Semiconductor Inc 2005 All rights reserved M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor Revision History Revision History Revision 2 1 Date Level Description Number s Mes oodi 3 2 3 3 1 System Configuration Register Addition to NOCOP bit description 44 4 Added 10 21 EPROM Characteristics 175 June 2001 32 10 21 EPROM Characteristics For clarity addition to note 2 following the 175 table December 7 7 2 Serial Communications Control Register 1 1 bit 4 M 3 3 P 110 2001 description corrected 10 7 MC68L11E9 E20 DC Electrical Characteristics Title changed to 153 include the MC68L11E20 10 8 MC68L11E9 E20 Suppl
46. A pending edge triggered IRQ can also bring the CPU out of stop Because all clocks are stopped in this mode all internal peripheral functions also stop The data in the internal RAM is retained as long as Vpp power is maintained The CPU state and I O pin levels are static and are unchanged by stop Therefore when an interrupt comes to restart the system the MCU resumes processing as if there were no interruption If reset is used to restart the system a normal reset sequence results in which all I O pins and functions are also restored to their initial states To use the IRQ pin as a means of recovering from stop the bit in the CCR must be clear IRQ not masked The XIRQ pin can be used to wake up the MCU from stop regardless of the state of the X bit in the CCR although the recovery sequence depends on the state of the X bit If X is set to 0 XIRQ not M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 95 Resets and Interrupts masked the MCU starts up beginning with the stacking sequence leading to normal service of the XIRQ request If X is set to 1 XIRQ masked or inhibited then processing continues with the instruction that immediately follows the STOP instruction and no XIRQ interrupt service is requested or pending Because the oscillator is stopped in stop mode a restart delay may be imposed to allow oscillator stabilization upon leaving stop If the internal oscillator is being used this de
47. ARRAYCNT ARRAYCNT NEXT I GOTO 1000 CLOSE 1 1 TO BYTECOUNT SAVE UPPER NIBBLE OF BYTE ADD LOWER NIBBLE SAVE BYTE IN ARRAY INCREMENT ARRAY INDEX Y ARRAYCNT 1 REM DUMP BOOTLOAD CODE TO PART R 2 COM1 1200 N 8 1 Macintosh COM statement OPEN COM1 1200 N 8 1 CDO CSO DSO RS FOR RANDOM AS 2 DOS COM statement INPUT Comm port open 0 WHILE LOC 2 gt 0 FLUSH INPUT BUFFER GOSUB 8020 WEND PRINT PRINT Sending bootload code to target part AS CHRS 255 BOOTCODES ADD HEX FF TO SET BAUD RATE ON TARGET 11 GOSUB 6500 PRINT FOR I 1 TO BOOTCOUNT OF BYTES IN BOOT CODE BEING ECHOED GOSUB 8000 K ASC BS GOSUB 8500 PRINT Character d I received HX NEXT I PRINT Programming is ready to begin INPUT Are you ready Q CLS WHILE LOC 2 gt 0 FLUSH INPUT BUFFER GOSUB 8020 WEND XMT 0 0 POINTERS XMIT AND RECEIVE BYTES AS CHR CODES XMT GOSUB 6500 SEND FIRST BYTE FOR I 1 CODESIZE 1 ZERO BASED ARRAY 0 gt CODESIZE 1 AS CHR CODES T SEND SECOND BYTE TO GET ONE IN QUEUE GOSUB 6500 SEND IT M68HC11 Bootstrap Mode Rev 1 1 216 Freescale Semiconductor 1640 1650 1660 1664 1665 1666 1668 1669 1670 1680 1690 1700 1710 1713 1714 1715 1716 1720 4900 4910 5000 5900 5910 5930 5940 6000 6010 6020 6030 6490 6492 6494 6496 6500 6510 6590 6594 6596 7000 7010 7020 70
48. CEED Jojonpuoolujeg 4 Vee Voc 1 1 1 RNID m Sy 25 42 MCU42 Sark uK Vpp 41 MCU41 XIRG 5 4 3 C7 C8 MCU34 34 oa niag 40 ee MCU 31 31 1 PB4 A12 57 MCU37 J7 MCU30 30 _ PAS OCS PBS A13 36 MCU36 MCU29 29 4 004 14 35 MCU35 MCU 23 28 PA5 0C3 PB7 A15 2 MCU27 27 PA6 OC2 9 MCU31 PA3 OC5 y PA7 OC1 PCO ADO 10 MCUTG se MCU 20 20 20 51 PDO RXD PC2 AD2 H PESE J2 R4 MCU 52 52 D TXD PC3 AD3 H MCUT9 1 gt 3 2 47K wWCU43 PE MCU23 23 2 50 CA ADA 13 MCU14 3 AAA MCU24 24 Die PCS AD5 l1 Pi AD enam al MCU25 25 ane 16 _MCU16 MCUS MODALIR 4 MCU 43 43 PEO 5 MCUS MCU2 MODBVsrgy MCU47 47 sTRBIRIW CU PE2 4 MCU4 J6 2 MCU49 49 pE3 STRA AS 77 CUTZ MCUB 2 1 MCU44 44 Ea RESET Tig O O MCU46 46 18 MCUIB Mo s R3 MCU48 48 MODA e 3 S Gg 1 50 50 PE7 MODBIVs 2 1 TBY 052 MCU52 52 NOTE 1 P2 MOU 52 553 Vai CON
49. H IS LOCATED AT BOTTOM OF 5 LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY 020 0 008 A B DO HE BOTTOM OF THE PARTING LINE 4 DATUMS AND D TO BE DETERMINED DATUM PLANE H 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE 73 N 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD H DATUM PLANE 0 010 PER SIDE DIMENSIONS A AND B DO 1 NCLUDE MOLD MISMATCH AND EHHH y DETERMINED AT DATUM PLANE H J 0 10 0 004 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION DAMBAR PROTRUSION SHALL H G SEATING PLANE NOT CAUSE THE D DIMENSION TO EXCEED 0 53 0 021 DAMBAR CANNOT BE LOCATED ON THE DETAIL C LOWER RADIUS OR THE FOOT 8 DIMENSION K IS TO BE MEASURED FROM THE a HEORETICAL INTERSECTION OF LEAD FOOT AND LEG CENTERLINES MILLIMETERS INCHES DIM MIN MAX MIN MAX 13 90 14 10 0 547 0 555 13 90 14 10 0 547 0 555 2 07 2 46 0 081 0 097 0 30 0 45 0 012 0 018 R 2 00 240 0 079 0 094 0 30 0 012 0 80 BSC 0 031 BSC 0 067 0 250 0 003 0 010 0 130 0 230 0 005 0 090 0 50 0 66 0 020 0 026 12 00 0 472 52 10 59 10 0 130 0 170 0 005 0 007 0 40 BSC 0 016 BSC oe 8 29 8 x 0 13 0 30 0 005 0 012 16 20 16 60 0 638 0 6
50. It must be possible to initiate a reset while the mode select pins are held low In systems where there is no provision for manual reset it is usually possible to generate a reset by turning power off and back on RxD Pin It must be possible to drive the PDO RxD pin with serial data from a host computer or another MCU In many systems this pin is already used for communications thus no changes are required M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 203 Allowing for Bootstrap Mode In systems where the PDO RxD pin is normally used as a general purpose output a serial signal from the host can be connected to the pin without resulting in output driver conflicts It may be important to consider what the existing logic will do with the SCI serial data instead of the signals that would have been produced by the PDO pin In systems where the PDO pin is used normally as a general purpose input the driver circuit that drives the PDO pin must be designed so that the serial data can override this driver or the driver must be disconnected during the bootstrap download A simple series resistor between the driver and the PDO pin solves this problem as shown in Figure 5 The serial data from the host computer can then be connected to the PDO RxD pin and the series resistor will prevent direct conflict between the host driver and the normal PDO driver CONNECTED ONLY DURING FROM SYSTEM RS232 LEVEL MC68HC11
51. OPTION Bits 5 4 bits 2 0 once only Bits 7 6 bit x03C a See HPRIO description See HPRIO description x03D RAM and map register INIT Yes once only SMOD 1 x024 Timer interrupt mask 2 TMSK2 All set or clear x035 Block protect register BPROT All set or clear x039 System configuration options OPTION All set or clear x03C 2 ang See HPRIO description See HPRIO description x03D RAM and I O map register INIT All set or clear 42 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 2 3 3 1 System Configuration Register The system configuration register CONFIG consists of an EEPROM byte and static latches that control the startup configuration of the MCU The contents of the EEPROM byte are transferred into static working latches during reset sequences The operation of the MCU is controlled directly by these latches and not by CONFIG itself In normal modes changes to CONFIG do not affect operation of the MCU until after the next reset sequence When programming the CONFIG register itself is accessed When the CONFIG register is read the static latches are accessed See 2 5 1 EEPROM and CONFIG Programming and Erasure for information on modifying CONFIG To take full advantage of the MCU s functionality customers can program the CONFIG register in bootstrap mode This can be accomplished by setting the mode pins to logic O and dow
52. Y 0 51 0 020 AO BO F lt z J i c A 0 15 0 006 Go T SEATING PLANE H D 52 PL S gt 0 18 0 007 T AO B M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor ALL DIMENSIONS AND TOLERANCES INCLUDE LEAD TRIM OFFSET AND LEAD INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0 785 0 795 19 94 20 19 B 0785 0 795 19 94 20 19 C 0 165 0 200 4 20 5 08 D 0 017 0 021 044 0 53 F 0 026 0 032 0 67 0 81 G 0 050 BSC 1 27 BSC H 0 090 0 130 2 29 3 30 J 0 006 0 010 0 16 0 25 0 035 0 045 0 89 1 14 0 735 0 756 18 67 19 20 0 735 0 756 18 67 19 20 0 690 0 730 17 53 18 54 183 Ordering Information and Mechanical Specifications 11 7 64 Pin Quad Flat Pack Case 840C a a 3 lt lt e a V DETAIL 2 3 e S S S METAL 9 8 en i k p Y 0 20 0 008 9 c a 8 p SECTION B B z NOTES 020 0 008 H A B DO 1 DIMENSIONING AND TOLERANCING PER ANSI 110 05 0 002 Y14 5M 1982 2 CONTROLLING DIMENSION MILLIMETER 3 DATUM PLANE
53. addressing forms The port D wire OR mode DWOM bit in the serial peripheral interface control register SPCR is set to configure port D for wired OR operation to minimize potential conflicts with external systems that use the PD1 TxD pin as an input The baud rate for the SCI is initially set to 7812 baud at a 2 MHz E clock rate but can automatically switch to 1200 baud based on the first character received The SCI receiver and transmitter are enabled The receiver is required by the bootloading process and the transmitter is used to transmit data back to the host computer for optional verification The last item in the initialization is to set an intercharacter delay constant used to terminate the download when the host computer stops sending data to the MC68HC711E9 This delay constant is stored in the timer output compare 1 TOC1 register but the on chip timer is not used in the bootloader program This example M68HC11 Bootstrap Mode Rev 1 1 198 Freescale Semiconductor Main Bootloader Program illustrates the extreme measures used in the bootloader firmware to minimize memory usage However such measures are not usually considered good programming technique because they are misleading to someone trying to understand the program or use it as an example After initialization a break character is transmitted 3 by the SCI By connecting the TxD pin to the RxD pin with a pullup because of port D wired OR mode this break will be rece
54. start PCbug11this way 11 gt PCBUG11 E PORT 1 with the E9PGMR connected to COM1 or C PCBUG11 gt PCBUG11 E PORT 2 with the E9PGMR connected to PCbug11 only supports COM ports 1 and 2 If the proper connections are made and you have a high quality cable you should quickly get a PCbug11 command prompt If you do receive a Comms fault error check the cable and board connections Most PCbug11 communications problems can be traced to poorly made cables or bad board connections Step 3 PCbug11 defaults to base 10 for its input parameters Change this to hexadecimal by typing CONTROL BASE HEX Step 4 Clear the block protect register BPROT to allow programming of the MC68HC711E9 EEPROM At the PCbug11 command prompt type MS 1035 00 Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR Rev 0 1 230 Freescale Semiconductor To Execute the Program Step 5 The CONFIG register defaults to hexadecimal 103F on the MC68HC711E9 11 needs adressing parameters to allow programming of a specific block of memory so the following parameter must be given At the PCbug11 command prompt type EEPROM O Then type EEPROM 103F 103F Step 6 Erase the CONFIG to allow byte programming At the PCbug11 command prompt type EEPROM ERASE BULK 103F Step 7 You are now ready to download the program into the EEPROM and EPROM At the PCbug11command prompt type LO
55. which automatically clears the RWU bit and enables normal character reception The first character whose MSB is set is also the first character to be received after wakeup because RWU gets cleared before the stop bit for that frame is serially received This type of wakeup allows messages to include gaps of idle time unlike the idle line method but there is a loss of efficiency because of the extra bit time for each character address bit required for all characters 7 6 SCI Error Detection Three error conditions SCDR overrun received bit noise and framing can occur during generation of SCI system interrupts Three bits OR NF and FE in the serial communications status register SCSR indicate if one of these error conditions exists The overrun error OR bit is set when the next byte is ready to be transferred from the receive shift register to the SCDR and the SCDR is already full RDRF bit is set When an overrun error occurs the data that caused the overrun is lost and the data that was already in SCDR is not disturbed The OR is cleared when the SCSR is read with OR set followed by a read of the SCDR The noise flag NF bit is set if there is noise on any of the received bits including the start and stop bits The NF bit is not set until the RDRF flag is set The NF bit is cleared when the SCSR is read with FE equal to 1 followed by a read of the SCDR When no stop bit is detected in the received data character the
56. 0 Bootstrap 1 1 0 0 0 1 1 0 Test 0 1 1 1 0 1 1 0 1 The reset values depend on the mode selected at the RESET pin rising edge Figure 2 9 Highest Priority I Bit Interrupt and Miscellaneous Register HPRIO RBOOT Read Bootstrap ROM Bit Valid only when SMOD is set bootstrap or special test mode can be written only in special modes 0 Bootloader ROM disabled and not in map 1 Bootloader ROM enabled and map at BEO0 BFFF SMOD and MDA Special Mode Select and Mode Select A Bits The initial value of SMOD is the inverse of the logic level present on the MODB pin at the rising edge of reset The initial value of MDA equals the logic level present on the MODA pin at the rising edge of reset These two bits can be read at any time They can be written anytime in special modes MDA can be written only once in normal modes SMOD cannot be set once it has been cleared Input Latched at Reset Mode MODB MODA SMOD MDA 1 0 Single chip 0 0 1 1 Expanded 0 1 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 41 Operating Modes and On Chip Memory 0 0 0 1 Bootstrap 1 0 Special test 1 1 IRV NE Internal Read Visibility Not E Bit IRVNE can be written once in any mode In expanded modes IRVNE determines whether IRV is on or off In special test mode IRVNE is reset to 1 In all other modes IRVNE is reset to 0 For the MC68HC81 1E2 this bit is
57. 00134 TFLG1 0023 00032 00137 00139 1 0016 00031 00135 00164 UPLOAD BFO3 00075 UPLOOP 00089 00093 WAIT BF8E 00186 00202 WAIT1 00120 00147 WTLOOP BF90 00188 00193 Errors None Labels 35 Last Program Address S BFFF Last Storage Address 0000 Program Bytes 0100 256 Storage Bytes 0000 0 00140 00169 00122 00121 00182 Listing 3 MC68HC711E9 Bootloader ROM 00145 00172 00197 00199 00143 00171 00189 00187 M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 227 eee eee Listing 3 MC68HC711E9 Bootloader ROM M68HC11 Bootstrap Mode Rev 1 1 228 Freescale Semiconductor Freescale Semiconductor Engineering Bulletin Rev 0 1 07 2005 Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR By Edgar Saenz Austin Texas Introduction The PCbug11 software needed along with the M68HC711E9PGMR to program MC68HC71 1E9 devices is available from the download section of the Microcontroller Worldwide Web site http www freescale com Retrieve the file pcbug342 exe a self extracting archive from the MCU11 directory Some Freescale evaluation board products also are shipped with PCbug11 NOTE For specific information about any of the PCbug11 commands see the appropriate sections the PCbug11 User s Manual part number M68PCBUG 1 1 D2 which is available from the Freescale Literature Distribution Center as well as the
58. 1000 ns 500 ns 333 ns E 1 overflow 65 536 ms 32 768 ms 21 845 ms 216 01 1 count 4 0 us 2 0 us 1 333 us E 4 overflow 262 14 ms 131 07 ms 87 381 ms 218 10 1 count 8 0 us 4 0 us 2 667 us E 8 overflow 524 29 ms 262 14 ms 174 76 ms 219 11 1 count 16 0 us 8 0 us 5 333 us E 16 overflow 1 049 s 524 29 ms 349 52 ms 220 Timer Structure 9 2 Timer Structure Figure 9 2 shows the capture compare system block diagram The port A pin control block includes logic for timer functions and for general purpose For pins PA2 1 and this block contains both the edge detection logic and the control logic that enables the selection of which edge triggers an input capture The digital level on PA 3 0 can be read at any time read PORTA register even if the pin is being used for the input capture function Pins PA 6 3 are used for either general purpose I O or as output compare pins When one of these pins is being used for an output compare function it cannot be written directly as if it were a general purpose output Each of the output compare functions OC 5 2 is related to one of the port A output pins Output compare one OC1 has extra control logic allowing it optional control of any combination of the PA 7 3 pins The PA7 pin can be used as a general purpose I O pin as an input to the pulse accumulator or as OC1 output 9 3 Input Capture
59. 125 kHz 8 7 2 Serial Peripheral Status Register Address 51029 Bit 7 6 5 4 3 2 1 Bit 0 Read SPIF WCOL MODF Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 8 4 Serial Peripheral Status Register SPSR SPIF SPI Interrupt Complete Flag SPIF is set upon completion of data transfer between the processor and the external device If SPIF goes high and if SPIE is set a serial peripheral interrupt is generated To clear the SPIF bit read the SPSR with SPIF set then access the SPDR Unless SPSR is read with SPIF set first attempts to write SPDR are inhibited WCOL Write Collision Bit Clearing the WCOL bit is accomplished by reading the SPSR with WCOL set followed by an access of SPDR Refer to 8 5 4 Slave Select and 8 6 SPI System Errors 0 No write collision 1 Write collision M68HC11E Family Data Sheet Rev 5 1 124 Freescale Semiconductor SPI Registers Bit 5 Unimplemented Always reads 0 MODF Mode Fault Bit To clear the MODF bit read the SPSR with MODF set then write to the SPCR Refer to 8 5 4 Slave Select and 8 6 SPI System Errors 0 No mode fault 1 Mode fault Bits 3 0 Unimplemented Always read 0 8 7 3 Serial Peripheral Data I O Register The SPDR is used when transmitting or receiving data on the serial bus Only a write to this register initiates transmission or reception of a byte and this only occurs in the master device At the completion of transferring a byte
60. 142 BF47 DONEIT EQU 143 BF47 1F2E80FC BRCLR SCSR X 80 Wait for TDRE 144 18A600 LDAA 50 Read from EPROM and 145 BFAE A72F STAA SCDAT X Xmit for verify 146 BF50 1808 INY Point at next location 147 BF52 20CB BRA WAIT1 Back to top for next 148 Loops indefinitely as long as more data sent 149 150 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk 151 Main bootloader starts here 152 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk 153 RESET vector points to here 154 155 BF54 BEGIN EQU 156 BF54 8E01FF LDS RAMEND Initialize stack pntr 157 BF57 CE1000 LDX 1000 Point at internal regs 158 BF5A 1C2820 BSET SPCR X 20 Select port D wire OR mode 159 BF5D CCA20C LDD SA20C BAUD in A SCCR2 in B 160 BF60 A72B STAA BAUD X SCPx 4 SCRx 4 161 Writing 1 to MSB of BAUD resets count chain M68HC11 Bootstrap Mode Rev 1 1 224 Freescale Semiconductor 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 91 192 193 194 195 196 197 198 1 99 200 201 202 203 204 205 206 207 208 209 210 211 212 BF62 BF64 BF67 BF69 BF6C BF70 BF73 BF73 77 79 BF7B BF7E BF7E BF80 BF82 BF85 BF88 BF8A BF8A BF8E BF8E BF90 BF90 BF94 BF95 BF96 BF97 BF99 BF9B BF9B BF9D BFAO BFA2 4 BFA8 BFAA BFAA BFAD 1 BFB4 BFB4 Listing 3 MC68HC711E9 Bootloader ROM Rx and Tx
61. 15K 20 UF MASTER R15 MCU 10K U3 MC68HC711E9 zum g XIRQ V Re PPE PB7 RESET x 3 3K Vpp ti PB1 PBO TARGET E ES MCU U6 CX SX XTAL ti Vpp Vpp MODB R10 R7 10K 4 15 TxD 1 R9 10K 0 lt lt 2 RS232 LEVEL TRANSLATOR U4 Figure 6 MCU to MCU EPROM Duplicator Schematic M68HC11 Bootstrap Mode Rev 1 1 206 Freescale Semiconductor Driving Boot Mode from Another M68HC11 The duplicator program in EEPROM clears the DWOM control bit to change port D thus TxD of U3 to normal driven outputs This configuration will prevent interference due to R9 when TxD from the target MCU U6 becomes active Series resistor R9 demonstrates how TxD of U3 can drive RxD of U3 1 and later TxD of U6 can drive RxD of U3 without a destructive conflict between the TxD output buffers As the target MCU U6 leaves reset its mode pins select bootstrap mode so the bootloader firmware begins executing A break is sent out the TxD pin of U6 At this time the TxD pin of U3 is at a driven high so R9 acts as a pullup resistor for TxD of the target MCU U6 The break character sent from U6 is received by so the duplicator program that is running in the EEPROM of the master knows that the target MCU is ready to accept a bootloaded program The master MCU sends a leading FF character to set the baud rate in the
62. 4 if prebyte is required byte immediate instructions The effective address is the address of the byte following the instruction 4 5 2 Direct In the direct addressing mode the low order byte of the operand address is contained in a single byte following the opcode and the high order byte of the address is assumed to be 00 Addresses 00 FF are thus accessed directly using 2 byte instructions Execution time is reduced by eliminating the additional memory access required for the high order address byte In most applications this 256 byte area is reserved for frequently referenced data In M68HC11 MCUs the memory map can be configured for combinations of internal registers RAM or external memory to occupy these addresses M68HC11E Family Data Sheet Rev 5 1 70 Freescale Semiconductor Instruction Set 4 5 3 Extended In the extended addressing mode the effective address of the argument is contained in two bytes following the opcode byte These are 3 byte instructions or 4 byte instructions if a prebyte is required One or two bytes are needed for the opcode and two for the effective address 4 5 4 Indexed In the indexed addressing mode an 8 bit unsigned offset contained in the instruction is added to the value contained in an index register IX or IY The sum is the effective address This addressing mode allows referencing any memory location in the 64 Kbyte address space These are 2 to 5 byte instructions depending on
63. 40 C to 105 C 2 MHz MC68HC11E0VB2 40 to 125 C 2 MHz MC68HC11E0MB2 11 3 Custom ROM Device Ordering Information Description Temperature Frequency MC Order Number 52 pin plastic leaded chip carrier PLCC 0 C to 70 C 3 MHz MC68HC11E9FN3 2 MHz MC68HC11E9CFN2 40 C to 85 C Custom ROM 3 MHz MC68HC11E9CFN3 40 to 105 C 2 MHz MC68HC11E9VFN2 40 to 125 C 2 MHz MC68HC11E9MFN2 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 179 Ordering Information and Mechanical Specifications Description Temperature Frequency MC Order Number 0 to 70 3 MHz MC68HC11E20FN3 2 MHz MC68HC11E20CFN2 40 C to 85 C 20 Kbytes custom ROM 3 MHz MC68HC11E20CFN3 40 to 105 C 2 MHz MC68HC11E20VFN2 40 to 125 C 2 MHz MC68HC11E20MFN2 64 pin quad flat pack QFP 0 to 70 3 MHz MC68HC11E9FU3 2 MHz MC68HC11E9CFU2 40 to 85 C Custom ROM 3 MHz MC68HC11E9CFU3 40 to 105 C 2 MHz MC68HC11E9VFU2 40 to 125 C 2 MHz MC68HC11E9MFU2 64 pin quad flat pack continued 0 to 70 3 MHz MC68HC11E20FU3 2 MHz MC68HC11E20CFU2 40 to 85 C 20 Kbytes Custom ROM 3 MHz MC68HC11E20CFU3 40 to 105 C 2 MHz MC68HC11E20VFU2 40 to 125 C 2 MHz MC68HC11E20MFU2 52 pin thin quad flat pack 10 mm x 10 mm 0
64. 9570 9580 9590 E DECIMAL TO HEX CONVERSION DX INPUT INTEGER TO BE CONVERTED ix OUTPUT HX TWO CHARACTER STRING WITH HEX CONVERSION l k k k k K k k k K k k k k K k k k k k k K K k k k K k k k k k k k K K k k k k k k k k k K k k K ck k k k kk kk K gt 255 THEN 5 big GOTO 8530 HX MID 16 1 1 UPPER NIBBLE HXS HXS MIDS HS MOD 16 1 1 LOWER NIBBLE RETURN Yo k lt lt k k lt lt k k ck lt lt BOOT CODE kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk DATA 86 23 LDAA 23 DATA B7 10 02 STAA OPT2 make port C wire or DATA 86 FE LDAA SFE DATA B7 10 03 STAA PORTC light 1 LED on port C bit 0 DATA C6 FF LDAB DATA F7 10 07 STAB DDRC make port C outputs DATA CE OF AO LDX 4000 2msec at 2MHz DATA 18 CE EO 00 LDY 5 000 Start of BUFFALO 3 4 DATA 7E BF 00 SBFOO EPROM routine start address 1 k k k k k K k k k k K k k K K k k k k k k K k k k k K k k k K K kk kk k Common Bootstrap Mode Problems It is not unusual for a user to encounter problems with bootstrap mode because it is new to many users By knowing some of the common difficulties the user can avoid them or at least recognize and quickly correct them Reset Conditions vs Conditions as Bootloaded Program Starts It is common to confuse the reset
65. A D Converter 3 1 POC C CM 57 3 2 T TI TI T D ti oO T T T TT 57 3 2 1 liis 1 57 3 2 2 Anean qct bp CO ROI OR P EERE 57 3 2 3 ihi cbe gg POTUIT 59 3 2 4 Re ACRIOR RC eC ee e CR eA Te 59 3 2 5 AD Converter COCKS 59 3 2 6 bin c eg foo er 59 3 3 Converter Power Up and Clock 60 3 4 Mn MR mI eae bee cael eee GE er okt ene Oi ek eee eee eee 61 3 5 JEn li qi oboe a ee ees ous TT 61 3 6 Single Channel CORON eke edid ad 61 3 7 Multiple Channel Operation RO RC A Cn CIC ROTORS eod cape SMO 62 3 8 Operation in Stop and Wait Modes 62 39 Control Status 1 5 62 310 Converter Result 5 lt 64 Chapter 4 Central Processor Unit CPU 4 1 ccr 65 4 2 ballo ee ee 65 4 2 1 E amd ORCI Pe RC RC Ce 66 4 2 2 ieee Register UM a ee ee RE FUR RR 66 4 2 3 HII Z css feces Pea iur idenS 66 4 2 4 66 4 2 5 1 u ur DEM T Le ade eet 68 4 2 6 Condition Code Register
66. BOOT SPECIAL BF00 m ROM MODE set VECTORS BFCO p BFFF P MAY BE DISABLED D000 ox USER BY AN EEPROM BIT EPROM or OTP SFFC0 NORMAL _ _ MODE SFFCO VECTORS SINGLE EXPANDED SPECIAL SPECIAL FFFF CHIP MULTIPLEXED BOOTSTRAP TEST MODA 0 MODA 1 MODA 0 MODA 1 MODB 1 MODB 1 MODB 0 MODB 0 NOTE Software can change some aspects of the memory map after reset Figure 1 MC68HC711E9 Composite Memory Map M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 197 Main Bootloader Program 6 4 FF CHARACTER START BITO BIT1 BIT2 BIT4 BIT5 BIT6 STOP Tx DATA LINE IDLES HIGH Q 7812 BAUD Rx DATA SAMPLES 3 1 1 1 1 1 1 1 1 FF voeem sn ___ Pri 1200 BAUD Rx DATA SAMPLES a ji i 0 0 0 0 0 0 1 1 1 7812 5 7 9 0 or EO 10 Figure 2 Automatic Detection of Baud Rate Samples taken at 7 detect the failing edge of the start bit and verify it is a logic 0 Samples taken at the middle of what the receiver interprets as the first five bit times 8 detect logic Os The sample taken at the middle of what the receiver interprets as bit 5 9 may detect either a O or a 1 because the receive data has a rising transition at about this time The samples for bits 6 and 7 detect 1s causing the r
67. By Edgar Saenz Austin Texas Introduction The PCbug11 software needed along with the M68HC711E9PGMR to program MC68HC81 1E2 devices is available from the download section of the Microcontroller Worldwide Web site http www freescale com Retrieve the file pcbug342 exe a self extracting archive from the MCU11 directory Some Freescale evaluation board products also are shipped with PCbug11 NOTE For specific information about any of the PCbug11 commands see the appropriate sections the PCbug11 User s Manual part number M68PCBUG11 D2 which is available from the Freescale Literature http www freescale com The file is also on the software download system and is called pcbug1 1 paf Freescale Semiconductor Inc 2005 All rights reserved 2 25d 2 freescale semiconductor To Execute the Program To Execute the Program Once you have obtained PCbugl 1 use this step by step procedure Step 1 Before applying power to the programming board connect the M68HC711E9PGMR serial port P2 to one of your PC COM ports with a standard 25 pin RS 232 cable Do not use a null modem cable or adapter which swaps the transmit and receive signals between the connectors at each end of the cable Place your MC68HC81 1E2 part in the PLCC socket on your board Insert the part upside down with the notched corner pointing toward the red power LED Make sure both S1 and S2 switches are turned off Apply 5 v
68. EVBU Pressing RETURN will send the bootcode to the target MC68HC711E9 The program then informs the user that the bootload code is being sent to the target and the results of the echoing of this code are displayed on the screen Another prompt reading Programming is ready to begin Are you will appear Turn on the 12 volt programming power supply and press RETURN to start the actual programming of the target EPROM A count of the byte being verified will be updated continually on the screen as the programming progresses Any failures will be flagged as they occur When programming is complete a message will be displayed as well as a prompt requesting the user to press RETURN to quit Turn off the 12 volt programming power supply before turning off 5 volts to the EVBU MS DOS is a registered trademark of Microsoft Corporation in the United States and oth175190er countries M68HC11 Bootstrap Mode Rev 1 1 214 Freescale Semiconductor Listing 2 BASIC Program for Personal Computer Listing 2 BASIC Program for Personal Computer Q N HG i UU ANP O 100 105 107 110 120 130 999 100 101 102 102 102 102 103 104 105 106 107 108 k k k k k k K k k k K K k k k K K k k k k k k k K k k K K k k K k k k K k k k K k k k K k k k K k k k K K k k ck k kk k E9BUF BAS A PROGRAM TO DEMONSTRATE THE USE OF THE BOOT MODE ON THE HC11 BY PROGRAMMING A
69. IRV and only controls the internal read visibility function 0 No internal read visibility on external bus 1 Data from internal reads is driven out the external data bus In single chip modes this bit determines whether the E clock drives out from the chip For the MC68HC811E2 this bit has no meaning or effect in single chip and bootstrap modes 0 E is driven out from the chip 1 is driven low Refer to the following table Mode IRVNE Out E Clock Out IRV Out IRVNE IRVNE Can of Reset of Reset of Reset Affects Only Be Written Single chip 0 On Off E Once Expanded 0 On Off IRV Once Bootstrap 0 On Off E Once Special test 1 On On IRV Once PSEL 3 0 Priority Select Bits Refer to Chapter 5 Resets and Interrupts 2 3 3 System Initialization Registers and bits that control initialization and the basic operation of the MCU are protected against writes except under special circumstances Table 2 2 lists registers that can be written only once after reset or that must be written within the first 64 cycles after reset Table 2 2 Write Access Limited Registers Operating Register Register Name Must be Written Write Mode Address in First 64 Cycles Anytime SMOD 0 x024 Timer interrupt mask 2 TMSK2 Bits 1 0 once only Bits 7 2 x035 Block protect register BPROT Clear bits once only Set bits only x039 System configuration options
70. M ti D ipti Addressing Instruction Condition Codes nemone 6 Opcode Operand Cycles H 1 2 V C INCB Increment B 1 B B INH 5C 2 R a A A m Accumulator B INS Increment 1 SP INH 31 3 Stack Pointer INX Increment IX 19 IX INH 08 3 A Index Register x INY Increment IY 1 IY INH 18 08 4 A Index Register Y JMP opr Jump See Figure 3 2 EXT TE hh 11 3 IND X 6E 3 IND Y 18 6E 4 JSR Jump to See Figure 3 2 DIR 9D 5 Subroutine EXT BD hh 11 6 IND X AD ff 6 IND Y 18 AD ff 7 LDAA opr Load MA A IMM 86 jii 2 0 Accumulator A DIR 96 4 3 A A EXT B6 hh 11 4 A IND X 4 IND Y 18 5 LDAB Load MB B IMM C6 jii 2 A 0 Accumulator B DIR 06 3 B B EXT F6 hh 11 4 B IND X EG 4 B IND Y 18 E6 ff 5 LDD opr Load Double M gt AM 1 gt B IMM CC jj kk 3 A A 0 Accumulator DIR DC dd 4 D EXT FC hh 11 5 IND X 5 IND Y 18 EC 6 LDS opr Load Stack M M 1 gt SP IMM 8E jj kk 3 A A 0 Pointer DIR 9E da 4 EXT BE hh 11 5 IND X AE 5 IND Y 18 AE 6 LDX opr Load Index M M 1 gt 1X IMM CE jj kk 3 0 Register DIR DE 4 X EXT FE hh 11 5 IND X 5 IND Y CD EE f 6 LDY opr Load Index 15 IMM 18 jj kk 4 A 0 Register DIR 18 5 Y EXT 18 FE hh 11 6 IND X 1A EE 6 IND Y 18 EE 6 LSL opr Log
71. M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 107 Serial Communications Interface SCI RECEIVER BAUD RATE CLOCK ui 10 11 BIT SEE NOTE Rx SHIFT REGISTER PDO PIN BUFFER DATA AND CONTROL RECOVERY pg 765432 5 DISABLE Put DRIVER RE SCCR1 SCI CONTROL 1 SCSR SCI STATUS 1 SCDR Rx BUFFER i READ ONLY a i a 2 SCICONTROL2 SCI CONTROL 2 SCI Tx SCI INTERRUPT REQUESTS REQUEST INTERNAL DATA BUS Note Refer to Figure B 1 EVBU Schematic Diagram for an example of connecting RxD to a PC Figure 7 2 SCI Receiver Block Diagram M68HC11E Family Data Sheet Rev 5 1 108 Freescale Semiconductor SCI Error Detection 7 5 2 Address Mark Wakeup The serial characters in this type of wakeup consist of seven eight if M 1 information bits and an MSB which indicates an address character when set to 1 or mark The first character of each message is an addressing character MSB 1 receivers in the system evaluate this character to determine if the remainder of the message is directed toward this particular receiver As soon as a receiver determines that a message is not intended for it the receiver activates the RWU function by using a software write to set the RWU bit Because setting RWU inhibits receiver related flags there is no further software overhead for the rest of this message When the next message begins its first character has its MSB set
72. OPTION ADPU A D Power Up Bit 0 A D powered down 1 A D powered up CSEL Clock Select Bit 0 A D and EEPROM use system E clock 1 A D and EEPROM use internal RC clock IRQE Configure IRQ for Edge Sensitive Only Operation Refer to Chapter 5 Resets and Interrupts DLY Enable Oscillator Startup Delay Bit 0 The oscillator startup delay coming out of stop is bypassed and the MCU resumes processing within about four bus cycles 1 delay of approximately 4000 E clock cycles is imposed as the MCU is started up from the stop power saving mode This delay allows the crystal oscillator to stabilize CME Clock Monitor Enable Bit Refer to Chapter 5 Resets and Interrupts Bit 2 Not implemented Always reads 0 CR 1 0 COP Timer Rate Select Bits Refer to Chapter 5 Resets and Interrupts and Chapter 9 Timing Systems M68HC11E Family Data Sheet Rev 5 1 60 Freescale Semiconductor Conversion Process 3 4 Conversion Process The A D conversion sequence begins one E clock cycle after a write to the A D control status register ADCTL The bits in ADCTL select the channel and the mode of conversion An input voltage equal to Vg converts to 00 and an input voltage equal to Vay converts to FF full scale with no overflow indication For ratiometric conversions of this type the source of each analog input should use Vg as the supply voltage and be referenced to Vp 3 5 Channel Assignments The multiplexer allo
73. Port C Data Direction Register DDRC7 ppRoe DDRC5 DDRC4 DDRC3 DDRC2 DDRC DDRCO 1007 DDRC Write 100 Reset O 0 0 0 0 0 0 0 Read Port D Data Register 0 0 PD4 PD3 PD1 PD0 1008 PORTD Write 100 Reset U U Read Port D Data Direction Register DDRD5 DDRD4 DDRD3 00802 DDRDO 1009 DDRD Write 100 Reset O 0 0 0 0 0 0 0 Port E Data Register Read g PE7 PEG PE1 PEO 100A PORTE Write See page 101 Reset Indeterminate after reset Timer Compare Force Register Read FOCI FOC2 FOC3 FOC4 FOC5 100B CFORC Write page 135 Reset O 0 0 0 0 0 0 0 Output Compare 1 Mask Register Head ocims ocima 100C OC1M Write page 136 Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved U Unaffected Indeterminate after reset Figure 2 7 Register and Control Bit Assignments Sheet 1 of 6 M68HC11E Family Data Sheet Rev 5 1 34 Freescale Semiconductor Addr 100D 100E 100F 1010 1011 1012 1013 1014 1015 1016 1017 1018 Register Name Output Compare 1 Data Register OC1D See page 136 Timer Counter Register High TCNTH See page 137 Timer Counter Register Low TCNTL See page 137 Timer Input Capture 1 Register High TIC1H See page 132 Timer Input Capture 1 Registe
74. RAM feature is only useful if the RAM was previously loaded with a meaningful program Acallable utility subroutine is included in the bootstrap ROM of the indicated versions to program bytes of on chip EPROM with data received via the SCI A callable utility subroutine is included in the bootstrap ROM of the indicated versions to upload contents of on chip memory to a host computer via the SCI The complete listing for this bootstrap ROM may be found in the M68HC11 Reference Manual Freescale document order number M68HC11RM AD The complete listing for this bootstrap ROM is available in the freeware area of the Freescale Web site Due to the extra program space needed for EEPROM security on this device there are no pseudo vectors for SCI SPI PAIF PAOVF TOF OC5F or OC4F interrupts This bootloader extends the automatic software detection of baud rates to include 9600 baud at 2 MHz E clock rate desjsjoog uowwog 910N uoneoijddy Common Bootstrap Mode Problems Connecting RxD to Vss Does Not Cause the SCI to Receive a Break To force an immediate jump to the start of EEPROM the bootstrap firmware looks for the first received character to be 00 or break The data reception logic in the SCI looks for a 1 to 0 transition on the RxD pin to synchronize to the beginning of a receive character If the RxD pin is tied to ground no 1 0 transition occurs The SCI transmitter sends a break character
75. Register INIT RAM 3 0 RAM Map Position Bits These four bits which specify the upper hexadecimal digit of the RAM address control position of RAM in the memory map RAM can be positioned at the beginning of any 4 Kbyte page in the memory map It is initialized to address 0000 out of reset Refer to Table 2 4 REG 3 0 64 Byte Register Block Position These four bits specify the upper hexadecimal digit of the address for the 64 byte block of internal registers The register block positioned at the beginning of any 4 Kbyte page in the memory map is initialized to address 1000 out of reset Refer to Table 2 5 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 45 Operating Modes and On Chip Memory Table 2 4 RAM Mapping Table 2 5 Register Mapping RAN 3 0 Address REG 3 0 Address 0000 0000 0xFF 0000 0000 003F 0001 1000 1xFF 0001 1000 103F 0010 2000 2xFF 0010 2000 203F 0011 3000 3xFF 0011 3000 303F 0100 4000 4xFF 0100 4000 403F 0101 5000 5xFF 0101 5000 503F 0110 6000 6xFF 0110 6000 603F 0111 7000 7xFF 0111 7000 703F 1000 8000 8xFF 1000 8000 803F 1001 9000 9xFF 1001 9000 903F 1010 A000 AxFF 1010 A000 A03F 1011 B000 BxFF 1011 B000 B03F 1100 C000 CxFF 1100 C000 C03F 1101 D000 DxFF 1101 D000 D03F 1110 E000 ExFF 1110 E000 E03F 1111 F000 FxFF 1111 F000 F03F
76. SS goes high For a slave with CPHA equal to 1 transfer begins when the SCK line goes to its active level which is the edge at the beginning of the first SCK cycle The transfer ends in a slave in which CPHA equals 1 when SPIF is set 8 7 SPI Registers The three SPI registers are Serial peripheral control register GPCR e Serial peripheral status register SPSR Serial peripheral data register SPDR These registers provide control status and data storage functions 8 7 1 Serial Peripheral Control Register Address 1028 Bit 7 6 5 4 3 2 1 Bit 0 Read WE SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPRO rite Reset 0 0 0 0 0 1 U U U Unaffected Figure 8 3 Serial Peripheral Control Register SPCR SPIE Serial Peripheral Interrupt Enable Bit Set the SPE bit to 1 to request a hardware interrupt sequence each time the SPIF or MODF status flag is set SPl interrupts are inhibited if this bit is clear or if the I bit in the condition code register is 1 0 SPI system interrupts disabled 1 SPI system interrupts enabled SPE Serial Peripheral System Enable Bit When the SPE bit is set the port D bit 2 3 4 and 5 pins are dedicated to the SPI function If the SPI is in the master mode and DDRD bit 5 is set then the port D bit 5 pin becomes a general purpose output instead of the SS input 0 SPI system disabled 1 SPI system enabled DWOM Port D Wired OR Mode Bit DWOM affects all po
77. Serial Peripheral Control Register 123 Serial Peripheral Status 124 Serial Peripheral Data I O 125 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 9 1 9 2 9 3 9 3 1 9 3 2 9 3 3 9 4 9 4 1 9 4 2 9 4 3 9 4 4 9 4 5 9 4 6 9 4 7 9 4 8 9 4 9 9 4 10 9 5 9 5 1 9 5 2 9 5 3 9 6 9 7 9 7 1 9 7 2 9 7 3 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 10 10 11 10 12 10 13 10 14 Chapter 9 Timing Systems oi ys Read ea es 127 EE 4008 3 HELTER Beto E 129 nne gp e ee a ee re eee ee ee 129 Timer Control 131 Timer Input Capture 5 131 Timer Input Capture 4 Output Compare 5 133 EE p 133 Timer Output Compare Registers 134 Timer Compare Force 55 5 53425 5 95 55 CR ORC 135 Output Compare Mask Regist er cee ees RC RR s hasa 136 Outp t Compare Data Register isa pe oap ea ROCA Hob ORO EO 136 Timer Counter ii usi d d 9 137
78. THAN 0 037 0 940 E THE DAMBAR INTRUSION S SHALL NOT CAUSE THE H 0 007 0 18 6 T N H DIMENSION TO BE SMALLER THAN 0 025 0 635 INCHES MILLIMETERS K1 DIM MIN MAX MIN MAX Y 0785 0 795 19 94 20 19 0 785 0795 19 94 20 19 C 0465 0 180 420 457 K 0 007 0 18 T L MO NG 0090 229 279 0013 0019 033 048 G 0 050BSC 1 27 BSC VIEW S H 0 006 0 032 0 66 0 81 J ooo 05 0025 064 R 0750 0756 19 05 1920 U 0750 0756 19 05 19 20 v 0 042 0048 107 121 w 0 042 0 048 107 121 X 0 042 0 056 107 142 Y 0020 050 7 29 10 2 109 61 0710 0730 1804 1854 10 040 102 M68HC11E Family Data Sheet Rev 5 1 182 Freescale Semiconductor 52 Windowed Ceramic Leaded Chip Carrier Case 778B 11 6 52 Pin Windowed Ceramic Leaded Chip Carrier Case 778B DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 CONTROLLING DIMENSION INCH DIMENSION R AND N DO NOT INCLUDE GLASS PROTRUSION GLASS PROTRUSION TO BE 0 25 0 010 MAXIMUM A gt NOTES 1 b 0 51 0 020 T AO BO 2 3 4
79. VALID gt lpcz b STRA ACTIVE AFTER PORTCL WRITE Notes 1 After reading PIOC with STAF set 2 Figure shows rising edge STRA 1 and high true STRB INVB 1 Figure 10 13 3 State Variation of Output Handshake Timing Diagram STRA Enables Output Buffer M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 165 Electrical Characteristics 10 13 Analog to Digital Converter Characteristics 2 0 MHz 3 0 MHz Uni Characteristic Parameter Min Absolute Max Max t Resolution Number of bits resolved by A D converter 8 Bits Maximum deviation from the ideal A D transfer LS Non linearity to 1 2 1 characteristics B Difference between the output of an ideal and an LS Zero error 1 2 1 actual for 0 input voltage B Difference between the output of an ideal and an LS Full scale error 1 2 1 actual A D for full scale input voltage B Total unadjusted Maximum sum of non linearity zero error and a u 1 2 1 2 LS error full scale error x Uncertainty because of converter resolution 1 2 1 2 e Absolute Difference between the actual input voltage and LS the full scale weighted equivalent of the binary 1 2 output code all error sources included Analog input voltage range VRL VRH V VRH Maximum analog reference voltage VRL Vpp 0 1 Vpp 0 1 V Minimum analog refe
80. Worldwide Web at http www freescale com The file is also on the software download system is called pcbug1 1 paf Freescale Semiconductor Inc 2005 All rights reserved 2 25d 2 freescale semiconductor To Execute the Program To Execute the Program Use this step by step procedure to program the MC68HC711E9 device Step 1 Before applying power to the programming board connect the M68HC711E9PGMR serial port P2 to one of your PC COM ports with a standard 25 pin RS 232 cable Do not use a null modem cable or adapter which swaps the transmit and receive signals between the connectors at each end of the cable Place the MC68HC711E9 part in the PLCC socket on your board Insert the part upside down with the notched corner pointing toward the red power LED sure both S1 and S2 switches are turned off Apply 5 volts to 5 V 12 volts at most 12 5 volts to Vpp and ground to GND on your programmer board s power connector P1 The remaining TXD PD1 and RXD PDO connections are not used in this procedure They are for gang programming MC68HC711E9 devices which is discussed in the M68HC711E9PGMR Manual You cannot gang program with PCbug11 Ensure that the remove for multi programming jumper J1 below the 5 V power switch has a fabricated jumper installed Step 2 Apply power to the programmer board by moving the 5 V switch to the ON position From a DOS command line prompt
81. also described in this section Refer to Figure 9 1 All main timer system activities are referenced to this free running counter The counter begins incrementing from 0000 as the MCU comes out of reset and continues to the maximum count FFFF At the maximum count the counter rolls over to 0000 sets an overflow flag and continues to increment As long as the MCU is running in a normal operating mode there is no way to reset change or interrupt the counting The capture compare subsystem features three input capture channels four output compare channels and one channel that can be selected to perform either input capture or output compare Each of the three input capture functions has its own 16 bit input capture register time capture latch and each of the output compare functions has its own 16 bit compare register timer functions including the timer overflow and RTI have their own interrupt controls and separate interrupt vectors The pulse accumulator contains an 8 bit counter and edge select logic The pulse accumulator can operate in either event counting mode or gated time accumulation mode During event counting mode the pulse accumulator s 8 bit counter increments when a specified edge is detected on an input signal During gated time accumulation mode an internal clock source increments the 8 bit counter while an input signal has a predetermined logic level The real time interrupt RTI is a programmable periodic interrup
82. are required to provide each instruction with a range of addressing capabilities Only 256 opcodes would be available if the range of values were restricted to the number able to be expressed in 8 bit binary numbers A 4 page opcode map has been implemented to expand the number of instructions An additional byte called a prebyte directs the processor from page 0 of the opcode map to one of the other three pages As its name implies the additional byte precedes the opcode A complete instruction consists of a prebyte if any an opcode and zero one two or three operands The operands contain information the CPU needs for executing the instruction Complete instructions can be from one to five bytes long 4 5 Addressing Modes Six addressing modes can be used to access memory Immediate Direct Extended Indexed Inherent Relative These modes are detailed in the following paragraphs All modes except inherent mode use an effective address The effective address is the memory address from which the argument is fetched or stored or the address from which execution is to proceed The effective address can be specified within an instruction or it can be calculated 4 5 1 Immediate In the immediate addressing mode an argument is contained in the byte s immediately following the opcode The number of bytes following the opcode matches the size of the register or memory location being operated on There are 2 3 and
83. host has finished sending data to be programmed Allowing for Bootstrap Mode Since bootstrap mode requires few connections to the MCU it is easy to design systems that accommodate bootstrap mode Bootstrap mode is useful for diagnosing or repairing systems that have failed due to changes in the CONFIG register or failures of the expansion address data buses rendering programs in external memory useless Bootstrap mode can also be used to load information into the EPROM or EEPROM of an M68HC11 after final assembly of a module Bootstrap mode is also useful for performing system checks and calibration routines The following paragraphs explain system requirements for use of bootstrap mode in a product Mode Select Pins It must be possible to force the MODA and MODB pins to logic 0 which implies that these two pins should be pulled up to Vpp through resistors rather than being tied directly to Vpp If mode pins are connected directly to Vpp it is not possible to force a mode other than the one the MCU is hard wired for It is also good practice to use pulldown resistors to Vss rather than connecting mode pins directly to Vas because itis sometimes a useful debug aid to attempt reset in modes other than the one the system was primarily designed for Physically this requirement sometimes calls for the addition of a test point or a wire connected to one or both mode pins Mode selection only uses the mode pins while RESET is active RESET
84. including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2005 All rights reserved 2 freescale semiconductor
85. intercharacter delay counter is started 8 by loading the delay constant from TOC1 into the X index register The 19 E cycle wait loop is executed repeatedly until either a character is received 9 or the allowed intercharacter delay time expires 10 For 7812 baud the delay constant is 10 241 E cycles 539 x 19 E cycles per loop Four character times at 7812 baud is 10 240 E cycles baud prescale of 4 x baud divider of 4 x 16 internal SCI clocks bit time x 10 bit times character x 4 character times The delay from reset to the initial FF character is not critical since the delay counter is not started until after the first character FF is received To terminate the bootloading sequence and jump to the start of RAM without downloading any data to the on chip RAM simply send FF and nothing else This feature is similar to the jump to EEPROM at 4 except the FF causes a jump to the start of RAM This procedure requires that the RAM has been loaded with a valid program since it would make no sense to jump to a location in uninitialized memory After receiving a character the downloaded byte is stored in RAM 11 The data is transmitted back to the host 12 as an indication that the download is progressing normally At 13 the RAM pointer is incremented to the next RAM address If the RAM pointer has not passed the end of RAM the main download loop from 7 to 14 is repeated When all data has been downloaded the bootloader goes to
86. made to accommodate both Macintosh and PC versions of BASIC is in lines 1500 and 1505 Use line 1500 and comment out line 1505 if the program is to be run on a Macintosh and conversely use line 1505 and comment out line 1500 if a PC is used After the COM port is opened the code to be bootloaded is modified by adding the FF to the start of the string FF synchronizes the bootloader in the MC68HC711E9 to 1200 baud The entire string is simply sent to the COM port by PRINTing the string This is possible since the string is actually queued in BASIC s COM buffer and the operating system takes care of sending the bytes out one at a time The M68HC11 echoes the data received for verification No automatic verification is provided though the data is printed to the screen for manual verification Once the MCU has received this bootloaded code the bootloader automatically jumps to it The small bootloaded program in turn includes a jump to the EPROM programming routine in the boot ROM Refer to the previous explanation of the EPROM Programming Utility for the following discussion The host system sends the first byte to be programmed through the COM port to the SCI of the MCU The SCI port on the MCU buffers one byte while receiving another byte increasing the throughput of the EPROM programming operation by sending the second byte while the first is being programmed When the first byte has been programmed the MCU reads the EPROM location and sends
87. next two characters form the hex byte giving the number of hex bytes to follow This byte is converted to integer by the same subroutine that converted the bootloaded code from the DATA statements This BYTECOUNT is adjusted by subtracting 3 which accounts for the address and checksum bytes and leaves just the number of object code bytes in the record Starting at line 1100 the 2 byte 4 character starting address is converted to decimal This address is the starting address for the object code bytes to follow An index into the CODE array is formed by subtracting the base address initialized at the start of the program from the starting address for this S record A FOR NEXT loop starting at line 1130 converts the object code bytes to decimal and saves them in the CODE array When all the object code bytes have been converted from the current S record the program loops back to find the next S1 record M68HC11 Bootstrap Mode Rev 1 1 212 Freescale Semiconductor Driving Boot Mode from a Personal Computer A problem arose with the BASIC programming technique used The draft versions of this program tried saving the object code bytes directly as binary in a string array This caused Out of Memory or Out of String Space errors on both a 2 Mbyte Macintosh and a 640 Kbyte PC The solution was to make the array an integer array and perform the integer to binary conversion on each byte as it is sent to the target part The one compromise
88. of data the SPIF status bit is set in both the master and slave devices A read of the SPDR is actually a read of a buffer To prevent an overrun and the loss of the byte that caused the overrun the first SPIF must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated Address 102 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset Indeterminate after reset Figure 8 5 Serial Peripheral Data I O Register SPDR SPI is double buffered in and single buffered out M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 125 AA Serial Peripheral Interface SPI M68HC11E Family Data Sheet Rev 5 1 126 Freescale Semiconductor Chapter 9 Timing Systems 9 1 Introduction The M68HC1 1 timing system is composed of five clock divider chains The main clock divider chain includes a 16 bit free running counter which is driven by a programmable prescaler The main timer s programmable prescaler provides one of the four clocking rates to drive the 16 bit counter Two prescaler control bits select the prescale rate The prescaler output divides the system clock by 1 4 8 or 16 Taps off of this main clocking chain drive circuitry that generates the slower clocks used by the pulse accumulator the real time interrupt RTI and the computer operating properly COP watchdog subsystems
89. on the MC68HC711E9 Devices with PCbug11 on the see g dod 55957 oC qo de FOR eG eR 229 EB188 Enabling the Security Feature on M68HC81 1E2 Devices with PCbug11 on the M68HC711E9PGMR dee eer bese 233 EB296 Programming MC68HC711E9 Devices with PCbug1 1 and he M68SFIGOT4fEVBU C a dico tet Race br iste DINER dente del EPI RIAL EQ 237 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor Chapter 1 General Description 1 1 Introduction This document contains a detailed description of the M68HC1 1 E series of 8 bit microcontroller units MCUs These MCUs all combine the M68HC1 1 central processor unit CPU with high performance on chip peripherals The E series is comprised of many devices with various configurations of Random access memory RAM Read only memory ROM Erasable programmable read only memory EPROM Electrically erasable programmable read only memory EEPROM Several low voltage devices are also available With the exception of a few minor differences the operation of all E series MCUs is identical A fully static design and high density complementary metal oxide semiconductor HCMOS fabrication process allow the E series devices to operate at frequencies from 3 MHz to dc with very low power consumption 1 2 Features Features of the E series devices include M68HC11 CPU Power saving stop and wait modes Low volt
90. page 142 Pulse Accumulator Control Regis 1026 ter PACTL See page 142 Pulse Accumulator Count Regis 1027 ter PACNT See page 146 Serial Peripheral Control Register 1028 SPCR See page 123 Serial Peripheral Status Register 1029 SPSR See page 124 Serial Peripheral Data Regis 102A ter SPDR See page 125 Baud Rate Register 102B BAUD See page 113 Serial Communications Control 102C Register 1 SCCR1 See page 110 Serial Communications Control 102D Register 2 SCCR2 See page 111 Serial Communications Status 102 Register SCSR See page 112 1 SCP2 adds 39 to SCI prescaler and is present on Serial Communications Data Reg 102F ister SCDR See page 110 Analog to Digital Control Status 1030 Register ADCTL See page 62 Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Memory Map Bit 7 6 5 4 3 2 1 Bit 0 TOF RTIF PAOVF PAIF 0 0 0 0 0 0 0 0 DDRA7 PAEN PAMOD PEDGE DDRA3 14 05 RTR1 RTRO 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset SPIE SPE DWOM MSTR CPOL CPHA SP
91. pin is high it indicates that the reset was initiated internally by either the COP system or the clock monitor CAUTION Do not connect an external resistor capacitor RC power up delay circuit to the reset pin of M68HC1 1 devices because the circuit charge time constant can cause the device to misinterpret the type of reset that occurred 5 2 3 Computer Operating Properly COP Reset The MCU includes a COP system to help protect against software failures When the COP is enabled the software is responsible for keeping a free running watchdog timer from timing out When the software is no longer being executed in the intended sequence a system reset is initiated The state of the NOCOP bit in the CONFIG register determines whether the COP system is enabled or disabled To change the enable status of the COP system change the contents of the CONFIG register and then perform a system reset In the special test and bootstrap operating modes the COP system is initially inhibited by the disable resets DISR control bit in the TEST1 register The DISR bit can subsequently be written to O to enable COP resets The COP timer rate control bits CR 1 0 in the OPTION register determine the COP timeout period The system E clock is divided by 215 and then further scaled by a factor shown in Table 5 1 After reset these bits are 0 which selects the fastest timeout period In normal operating modes these bits can be written only once within 64 bus c
92. rates for bootloader communications For the three new baud rates the first character used to determine the baud rate is not FF as it was in earlier M68HC11s The intercharacter delay that terminates the variable length download is also different for these new baud rates Table 3 shows the synchronization characters delay times and baud rates as they relate to E clock frequency Commented Boot ROM Listing Listing 3 MC68HC711E9 Bootloader ROM contains a complete commented listing of the boot ROM program in the MC68HC711E9 version of the M68HC1 1 Other versions can be found in Appendix B of the M68HC11 Reference Manual Table 3 Bootloader Baud Rates Sync Timeout Baud Rates at E Clock Character Delay 2 MHz 2 1 MHz 3 MHz 3 15 MHz 4 MHz 4 2 MHz FF 4 characters 7812 8192 11 718 12 288 15 624 16 838 FF 4 characters 1200 1260 1800 1890 2400 2520 FO 4 9 characters 9600 10 080 14 400 15 120 19 200 20 160 FD 17 3 characters 5208 5461 7812 8192 10 416 10 922 FD 13 characters 3906 4096 5859 6144 7812 8192 M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 221 Listing 3 MC68HC711E9 Bootloader ROM Listing 3 MC68HC711E9 Bootloader ROM HS S dS ud gt gt UU QQ C QQ QO CULO N N N PO N N N PO N N l p E B B R FF FR FR ES O amp N F
93. register Otherwise is configured as fifth output compare out of reset with bit 14 05 being cleared If the DDRAS bit is set configuring as an output and IC4 is enabled then writes to cause edges the pin to result in input captures Writing to TI4 O5 has no effect when the TI4 O5 register is acting as IC4 9 3 1 Timer Control Register 2 Use the control bits of this register to program input capture functions to detect a particular edge polarity on the corresponding timer input pin Each of the input capture functions can be independently configured to detect rising edges only falling edges only any edge rising or falling or to disable the input capture function The input capture functions operate independently of each other and can capture the same value if the input edges are detected within the same timer count cycle Address 1021 Bit 7 6 5 4 3 2 1 Bit 0 Read ri EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A rite Reset 0 0 0 0 0 0 0 0 Figure 9 3 Timer Control Register 2 TCTL2 EDGxB and EDGxA Input Capture Edge Control Bits There are four pairs of these bits Each pair is cleared to 0 by reset and must be encoded to configure the corresponding input capture edge detector circuit IC4 functions only if the 14 05 bit in the PACTL register is set Refer to Table 9 2 for timer control configuration Table 9 2 Timer Control Configuration
94. target MCU Next the master MCU passes a 3 instruction program to the target MCU and pauses so the bootstrap program in the target MCU will stop the loading process and jump to the start of the downloaded program This sequence demonstrates the variable length download feature of the MC68HC711E9 bootloader The short program downloaded to the target MCU clears the DWOM bit to change its TxD pin to a normal driven CMOS output and jumps to the EPROM programming utility in the bootstrap ROM of the target MCU Note that the small downloaded program did not have to set up the SCI or initialize any parameters for the EPROM programming process The bootstrap software that ran prior to the loaded program left the SCI turned on and configured in a way that was compatible with the SCI in the master MCU the duplicator program in the master MCU also did not have to set up the SCI for the same reason The programming time and starting address for EPROM programming in the target MCU were also set to default values by the bootloader software before jumping to the start of the downloaded program Before the EPROM in the target MCU can be programmed the Vpp power supply must be available at the XIRQ Vppg pin of the target MCU The duplicator program running in the master MCU monitors this voltage for presence or absence not level at PE7 through resistor divider R14 RI5 The PE7 input was chosen because the internal circuitry for port E pins can tolerate voltage
95. the result back to the host system The host then compares what was actually programmed to what was originally sent A message indicating which byte is being verified is displayed in the lower half of the screen If there is an error it is displayed at the top of the screen As soon as the first byte is verified the third byte is sent In the meantime the MCU has already started programming the second byte This process of verifying and queueing a byte continues until the host finishes sending data If the programming is completely successful no error messages will have been displayed at the top of the screen Subroutines follow the end of the program to handle some of the repetitive tasks These routines are short and the commenting in the source code should be sufficient explanation Modifications This example programmed version 3 4 of the BUFFALO monitor into the EPROM of an MC68HC71 1E9 the changes to the BASIC program to download some other program are minor The necessary changes are 1 Inline 30 the length of the program to be downloaded must be assigned to the variable CODESIZE 2 Also in line 30 the starting address of the program is assigned to the variable ADRSTART 3 Inline 9570 the start address of the program is stored in the third and fourth items in that DATA statement in hexadecimal 4 If any changes are made to the number of bytes in the boot code in the DATA statements in lines 9500 9580 then the new count mus
96. well as anything a factory test program can do because protected control bits are accessible in bootstrap mode Although the bootstrap mode is a single chip mode of operation expanded mode resources are accessible because the mode control bits can be changed while operating in the bootstrap mode This application note explains the operation and application of the M68HC11 bootstrap mode Although basic concepts associated with this mode are quite simple the more subtle implications of these functions require careful consideration Useful applications of this mode are overlooked due to an incomplete understanding of bootstrap mode Also common problems associated with bootstrap mode could be avoided by a more complete understanding of its operation and implications Topics discussed in this application note include Basic operation of the M68HC11 bootstrap mode e General discussion of bootstrap mode uses Detailed explanation of on chip bootstrap logic Detailed explanation of bootstrap firmware Bootstrap firmware vs EEPROM security Incorporating the bootstrap mode into a system Driving bootstrap mode from another M68HC1 1 Driving bootstrap mode from a personal computer Common bootstrap mode problems e Variations for specific versions of M68HC11 Commented listings for selected M68HC11 bootstrap ROMs Freescale Semiconductor Inc 2005 All rights reserved e O SP Z freescale semiconductor
97. whether or not a prebyte is required 4 5 5 Inherent In the inherent addressing mode all the information necessary to execute the instruction is contained in the opcode Operations that use only the index registers or accumulators as well as control instructions with no arguments are included in this addressing mode These are 1 or 2 byte instructions 4 5 6 Relative The relative addressing mode is used only for branch instructions If the branch condition is true an 8 bit signed offset included in the instruction is added to the contents of the program counter to form the effective branch address Otherwise control proceeds to the next instruction These are usually 2 byte instructions 4 6 Instruction Set Refer to Table 4 2 which shows all the M68HC11 instructions in all possible addressing modes For each instruction the table shows the operand construction the number of machine code bytes and execution time in CPU E clock cycles M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 71 Central Processor Unit CPU Table 4 2 Instruction Set Sheet 1 of 7 M P ti D ipti Addressing Instruction Condition Codes E Opcode Operand Cycles H 1 2 C ABA Add A B gt A INH 1B 2 Accumulators ABX Add B to X 00 B 2 I
98. 0 STAA 00 Y A72F STAA SCDAT X 1808 INY 188C0200 CPY RAMEND 1 26 4 STAR EQU CE1068 LDX PROGDEL 18 000 LDY EPRMSTR 7 0000 JMP RAMSTR ck k k k k k ck k k ce k k k kx k k K k K k ko ok Block fill unused bytes with 000000000000 BSZ SBFD1 000000000000 000000000000 000000000000 0000000000 M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 225 Listing 3 MC68HC711E9 Bootloader ROM 213 214 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk 215 Boot ROM revision level in ASCII 216 SBFD1 217 BFD1 41 FCC WAT 218 219 Mask set I D 0000 FOR EPROM PARTS 220 ORG SBFD2 221 BFD2 0000 FDB 0000 222 ck k k k k k k k k k K k k k K k k k 223 1711 9 Can be used to determine MCU type 224 ORG SBFDA 225 71E9 FDB 71E9 226 227 kkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk 228 VECTORS point to RAM for pseudo vector JUMPs 229 230 BFD6 00 4 FDB 100 60 SCI 231 BFD8 00C7 FDB 100 57 SPI 232 00 FDB 100 54 PULSE ACCUM INPUT EDGE 233 BFDC 00CD FDB 100 51 PULSE ACCUM OVERFLOW 234 BFDE 00DO FDB 100 48 TIMER OVERFLOW 235 BFEO 00D3 FDB 100 45 TIMER OUTPUT COMPARE 5 236 BFE2 00D6 FDB 100 42 TIMER OUTPUT COMPARE 4 237 BFE4 0009 FDB 100 39 TIME
99. 00 Bit 7 6 5 4 3 2 1 Bit 0 Read OC1D7 OC1D6 OC1D5 OC1D4 OC1D3 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 14 Output Compare 1 Data Register OC1D If OC1Mx is set data OC1Dx is output to port A bit x on successful OC1 compares Bits 2 0 Unimplemented Always read 0 M68HC11E Family Data Sheet Rev 5 1 136 Freescale Semiconductor Output Compare 9 4 5 Timer Counter Register The 16 bit read only TCNT register contains the prescaled value of the 16 bit timer A full counter read addresses the most significant byte MSB first A read of this address causes the least significant byte LSB to be latched into a buffer for the next CPU cycle so that a double byte read returns the full 16 bit state of the counter at the time of the MSB read cycle Register name Timer Counter Register High Address 100E Bit 7 6 5 4 3 2 1 Bit 0 Read Bit15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 Register name Timer Counter Register Low Address 100F Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 15 Timer Counter Register TCNT 9 4 6 Timer Control Register 1 The bits of this register specify the action taken as a result of a successful OCx compare Address 1020
100. 00 2604 3255 3906 5208 0 0 1 1 0 1 3 32 651 800 1302 1628 1953 2604 0 0 1 1 1 0 3 64 326 400 651 814 977 1302 0 0 1 1 1 1 3 128 163 200 326 407 488 651 0 1 0 0 0 0 4 1 15625 19200 31250 39063 46875 62500 0 1 0 0 0 1 4 2 7813 9600 15625 19531 23438 31250 0 1 0 0 1 0 4 4 3906 4800 7813 9766 11719 15625 0 1 0 0 1 1 4 8 1953 2400 3906 4883 5859 7813 0 1 0 1 0 0 4 16 977 1200 1953 2441 2930 3906 0 1 0 1 0 1 4 32 488 600 977 1221 1465 1953 0 1 0 1 1 0 4 64 244 300 488 610 732 977 0 1 0 1 1 1 4 128 122 150 244 305 366 488 0 1 1 0 0 0 13 1 4808 5908 9615 12019 14423 19231 0 1 1 0 0 1 13 2 2404 2954 4808 6010 7212 9615 0 1 1 0 1 0 13 4 1202 1477 2404 3005 3606 4808 0 1 1 0 1 1 13 8 601 738 1202 1502 1803 2404 0 1 1 1 0 0 13 16 300 369 601 751 901 1202 0 1 1 1 0 1 13 32 150 185 300 376 451 601 0 1 1 1 1 0 13 64 75 92 150 188 225 300 0 1 1 1 1 1 13 128 38 46 75 94 113 150 1 0 0 0 0 0 39 1 1603 1969 3205 4006 4808 6410 1 0 0 0 0 1 39 2 801 985 1603 2003 2404 3205 1 0 0 0 1 0 39 4 401 492 801 1002 1202 1603 1 0 0 0 1 1 39 8 200 246 401 501 601 801 1 0 0 1 0 0 39 16 100 123 200 250 300 401 1 0 0 1 0 1 39 32 50 62 100 125 150 200 1 0 0 1 1 0 39 64 25 31 50 63 75 100 1 0 0 1 1 1 39 128 13 15 25 31 38 50 Shaded areas reflect standard baud rates On MC68HC 7 11E20 do not set SCP1 or SCPO when SCP2 is 1 M68HC11E Family Data Sheet Rev 5 1 114 Freescale Semiconductor SCI Registers
101. 02 PWIno 20 ns PWira 0 520 353 ns Wait recovery startup time twrs 4 4 4 Timer pulse width input capture pulse accumulator input 102 PWrim tcvc 20 ns PWrim 0 520 353 ns 1 5 0 10 Vss 0 TA T to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless oth erwise noted 2 RESET is recognized during the first clock cycle it is held low Internal circuitry then drives the pin low for four clock cycles releases the pin and samples the pin level two cycles later to determine the source of the interrupt Refer to Chapter 5 Resets and Interrupts for further detail M68HC11E Family Data Sheet Rev 5 1 156 Freescale Semiconductor MC68L11E9 E20 Control Timing 10 10 MC68L11E9 E20 Control Timing Characteristic 2 Symbol ANN Unit Min Max Min Max Frequency of operation fo dc 1 0 dc 2 0 MHz E clock period 1000 500 ns Crystal frequency xTAL 4 0 8 0 MHz External oscillator frequency 4 dc 4 0 dc 8 0 MHz 5 ws 005 200 m Reset input pulse width To guarantee external reset vector PWerstL 8 8 Minimum input time can be pre empted by internal reset 1 1 Mode programming setup time tps 2 2 tcyc Mode programming hold time 10 10 ns 2 Hi edge sensitive mode PWInQ 1020 520 _ r
102. 0FN52 M68PA11E20FN52 MC68HC711E20 64 FU M68EM11E20 M68CBL11C M68TC11E20FU64 M68PA11E20FU64 48 P M68EM11E20 M68CBL11B M68TB11E20P48 M68PA11A8P48 MC68HC811E2 52 FN M68EM11E20 M68CBL11C M68TC11E20FN52 M68PA11E20FN52 1 Each MMDS11 system consists of a system console M68MMDS11 an emulation module a flex cable and a target head 2 Acomplete EVS consists of a platform board M68HC11PFB an emulation module a flex cable and a target head 3 Each SPGMR system consists of a universal serial programmer M68SPGMR11 and a programming adapter It can be used alone or in conjunction with the MMDS11 EVS Evaluation System The EVS is an economical tool for designing debugging and evaluating target systems based on the M68HC11 EVS features include e Monitor debugger firmware One line assembler disassembler e Host computer download capability Dual memory maps 64 Kbyte monitor map that includes 16 Kbytes of monitor EPROM M68HC11 E series user map that includes 64 Kbytes of emulation RAM MCU extension input output I O port for single chip expanded and special test operation modes RS 232C terminal and host I O ports Logic analyzer connector M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 187 Development Support A 4 Modular Development System MMDS11 The M68MMDS11 modular development system MMDS 1 1 is an emulator system for developing embedded systems based on an M68HC11 microcontrol
103. 1 Programming Model M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 65 Central Processor Unit CPU 4 2 1 Accumulators A B and D Accumulators A and B are general purpose 8 bit registers that hold operands and results of arithmetic calculations or data manipulations For some instructions these two accumulators are treated as a single double byte 16 bit accumulator called accumulator D Although most instructions can use accumulators A or B interchangeably these exceptions apply ABX and ABY instructions add the contents of 8 bit accumulator B to the contents of 16 bit register X or Y but there are no equivalent instructions that use A instead of B TAP and TPA instructions transfer data from accumulator A to the condition code register or from the condition code register to accumulator A However there are no equivalent instructions that use B rather than A The decimal adjust accumulator A DAA instruction is used after binary coded decimal BCD arithmetic operations but there is no equivalent BCD instruction to adjust accumulator B The add subtract and compare instructions associated with both A and B ABA SBA and CBA only operate in one direction making it important to plan ahead to ensure that the correct operand is in the correct accumulator 4 2 2 Index Register X IX The IX register provides a 16 bit indexing value that can be a
104. 1 00075 00081 00083 000A 00016 00059 BFOO 00022 00103 0020 00020 00034 00053 00071 0002 00014 00058 00061 00075 00083 0080 00013 00032 00083 002F 00021 00036 00049 00054 00072 00092 002 00017 00034 00048 00053 00071 00091 B66B 00090 00038 00067 00070 0028 00010 00031 0080 00019 00091 B66D 00091 00091 B64F 00071 00069 00071 B65F 00078 00074 B60B 00034 00034 B627 00053 00053 B630 00057 00060 M68HC11 Bootstrap Mode Rev 1 1 210 Freescale Semiconductor Driving Boot Mode from a Personal Computer Errors None Labels 28 Last Program Address 5 67 Last Storage Address 0000 Program Bytes 007D 125 Storage Bytes 0000 0 Driving Boot Mode from a Personal Computer In this example a personal computer is used as the host to drive the bootloader of an MC68HC711E9 An M68HC11 EVBU is used for the target MC68HC711E9 A large program is transferred from the personal computer into the EPROM of the target MC68HC711E9 Hardware Figure 7 shows a small modification to the EVBU to accommodate the 12 volt nominal EPROM programming voltage The XIRQ pin is connected to a pullup resistor two jumpers and the 60 pin connectors P4 and P5 The object of the modification is to isolate the XIRQ pin and then connect it to the programming power supply Carefully cut the trace on the solder side of the EVBU as indicated in Figure 7 This disconnects the pullup resistor RN1 D from XIRQ but leaves P4 1
105. 1 EQU 16 TFLG1 EQU 23 BIT EQUATES FOR TFLG1 EQU 80 SPCR EQU 28 FOR DWOM BIT BAUD EQU 2B SCCR2 EQU 2D SCSR EQU 2 SCDAT EQU 2F PPROG EQU 3B BIT EQUATES FOR PPROG ELAT EQU 20 EPGM EQU 01 MEMORY CONFIGURATION EQUATES EEPMSTR EQU B600 Start of EEPROM EEPMEND EQU B7FF End of EEPROM M68HC11 Bootstrap Mode Rev 1 1 222 Freescale Semiconductor 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 AD 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 D000 FFFF 0000 01 ODBO 021B 1068 00 00 BFO3 BFO3 BFO6 BF09 BFOD BFOF BF11 7EBF13 CE1000 18A600 1F2E80FC A72F 1808 20F3 Listing 3 MC68HC711E9 Bootloader ROM EPRMSTR EQU D000 Start of EPROM EPRMEND EQU SFFFF End of EPROM RAMSTR EQU 0000 RAMEND EQU 01FF DELAY CONSTANTS DELAYS EQU 3504 Delay at slow baud DELAYF EQU 539 Delay at fast baud PROGDEL EQU 4200 2 ms programming delay At 2 1 MHz k k K k k k k k k k k k k k k k K k k k k k k k k k k k k K K kk kk ORG SBFOO k k k K k k k k k k k k k k k k k k k k k k k k k k k k k k K k k k K k k k lt k K k k k K lt k lt lt Next two instructions provide predictable place to call PROGRAM and UPLOAD even if the routines change size in future versions
106. 1011 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset Indeterminate after reset Figure 9 4 Timer Input Capture 1 Register Pair TIC1 Register name Timer Input Capture 2 Register High Address 1012 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset Indeterminate after reset Register name Timer Input Capture 2 Register Low Address 1013 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset Indeterminate after reset Figure 9 5 Timer Input Capture 2 Register Pair TIC2 Register name Timer Input Capture 3 Register High Address 1014 Bit 7 6 5 4 3 2 1 Bit 0 Read 4 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset Indeterminate after reset Register name Timer Input Capture 3 Register Low Address 1015 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset Indeterminate after reset Figure 9 6 Timer Input Capture 3 Register Pair TIC3 M68HC11E Family Data Sheet Rev 5 1 132 Freescale Semiconductor Output Compare 9 3 3 Timer Input Capture 4 Output Compare 5 Register Use TI4 O5 as either an input capture register or an output compare reg
107. 150 LDCForFreescaleSemiconductor hibbertgroup com M68HC11E Rev 5 1 07 2005 RoHS compliant and or Pb free versions of Freescale products have the functionality and electrical characteristics of their non RoHS compliant and or non Pb free counterparts For further information see http www freescale com or contact your Freescale sales representative For information on Freescale s Environmental Products program go to http www freescale com epp Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters
108. 16 because of an intercharacter delay timeout 10 or because the entire 512 byte RAM has been filled 15 At 16 the X and Y index registers are set up for calling the PROGRAM utility routine which saves the user from having to do this in a downloaded program The PROGRAM utility is fully explained in EPROM Programming Utility The final step of the bootloader program is to jump to the start of RAM 17 which starts the user s downloaded program M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 199 Main Bootloader Program 1 C start FROM RESET IN BOOT MODE INITIALIZATION 2 SP OF RAM 01FF X START OF REGS 1000 SPCR 20 SET DWOM BIT BAUD A2 4 4 7812 5 BAUD 2 MHz SCCR2 0 Tx amp Rx ON TOC1 DELAY CONSTANT 539 4 SCI CHARACTER TIMES SEND BREAK RECEIVED FIRST CHAR YET YES FIRST CHAR 00 NOTZERO FIRST CHAR FF JUMP TO START OF EEPROM B600 NOTE THAT A BREAK CHARACTER IS ALSO RECEIVED AS 00 YES YES SWITCH TO SLOWER SCI RATE BAUD 33 13 8 1200 BAUD 2 MHz CHANGE DELAY CONSTANT TOC1 3504 4 SCI CHARACTER TIMES BAUDOK POINT TO START 0000 6 7 WAIT INITIALIZE TIMEOUT COUNT WTLOOP RECEIVE DATA READY 8 yes 9 NO LOOP 19 DECREMENT TIMEOUT COUNT CYCLES NO TIMED OUT YET
109. 30 7990 7992 7994 7996 7998 7999 8000 8005 8010 8020 8030 8490 Listing 2 BASIC Program for Personal Computer GOSUB 8000 GET BYTE FOR VERIFICATION RCV I 1 LOCATE 10 1 PRINT Verifying byte d I IF CHR CODES RCV BS THEN 1670 K CODE RCV GOSUB 8500 LOCATE 1 1 PRINT Byte I Sent HX K ASC B GOSUB 8500 PRINT Received HX NEXT I GOSUB 8000 GET BYTE FOR VERIFICATION RCV CODESIZES 1 LOCATE 10 1 PRINT Verifying byte 4 CODESIZE IF CHRS CODES RCV BS THEN 1720 K CODE RCV GOSUB 8500 LOCATE 1 1 PRINT Byte CODESIZE Sent HX K ASC B GOSUB 8500 PRINT Received HX LOCATE 8 1 PRINT PRINT Done CLOSE INPUT Press RETURN to quit 0 END Ikkxkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk SUBROUTINE TO READ IN ONE BYTE FROM DISK FILE RETURNS BYTE IN A KKK k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k FLAG 0 1 FLAG 1 RETURN AS 1 1 RETURN lt lt k k k k k k k k k k k k k K Kk K K K K K K K KOK K K KOK K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ke ke k k ke k R is SUBROUTINE TO SEND THE STRING IN A OUT TO THE DEVICE EX OPENED AS FILE 2
110. 33 ns 21 33 us 5 461 ms Pulse accumulator control bits are also located within two timer registers TMSK2 and TFLG2 as described in the following paragraphs M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 143 Timing Systems PAOVI INTERRUPT REQUESTS E 64 CLOCK FROM MAIN TIMER PAOVI TFLG2 INTERRUPT STATUS TMSK2 INT ENABLES PAI EDGE d DISABLE ES PAEN FLAG SETTING OVERFLOW MCU PIN VT PACNT 8 BIT COUNTER PAl AND MUX 1 EDGE DETECTOR gH S 2E DATA ENABLE BUS a OUTPUT BUFFER PAEN FROM MAIN TIMER OC1 PAEN PAMOD a FROM DDRA7 PACTL CONTROL INTERNAL DATA BUS Figure 9 24 Pulse Accumulator M68HC11E Family Data Sheet Rev 5 1 144 Freescale Semiconductor Pulse Accumulator 9 7 1 Pulse Accumulator Control Register Four of this register s bits control an 8 bit pulse accumulator system Another bit enables either the OC5 function or the IC4 function while two other bits select the rate for the real time interrupt system Address 1026 Bit 7 6 5 4 3 2 1 Bit 0 Read Ws DDRA7 PAEN PAMOD PEDGE DDRA3 14 05 RTR1 RTRO rite Reset 0 0 0 0 0 0 0 0 Figure 9 25 Pulse Accumulator Control Register PACTL DDRA7 Data Direction for Port A Bit 7 Refer to Chapter 6 Parallel Input Output Ports PAEN Pulse Accumulator System Enable Bit 0 Pulse accumulator disabled 1 Pulse accumulato
111. 54 M 0 20 REF 0 008 REF oc 0 DETAIL C 16 20 16 60 0 638 0 654 o gt a z r gt z c A43 o z o v z z r c x 0o m m o o m 1 10 1 30 0 043 0 051 M68HC11E Family Data Sheet Rev 5 1 184 Freescale Semiconductor 11 8 52 Pin Thin Quad Flat Pack Case 8480 4X 4X TIPS C 0 20 0 008 H L M N 0 20 0 008 T L M N 5110000010000 22 1 39 do 3x VIEW L EN M KS S 8 E t Lx E E lt E Y Y A1 N lt 151 gt lt A 6 T 1 SEATING PLANE Freescale Semiconductor 0 10 0 004 T VIEW AA 0 05 0 002 2XRR1 0 25 0 010 GAGE PLANE VIEW AA 52 Pin Thin Quad Flat Pack Case 848D PLATING _ E M N AB f G AB METAL ae Y U 0 13 0 005 T L u N ROTATED 90 CLOCKWISE NOTES on mm o p M68HC11E Family Data Sheet Rev 5 1 DIMENSIO
112. 8 5 18 and jumpers J7 and J14 connected so the EVBU can still be used for other purposes after programming is done Remove any fabricated jumpers from J7 and J14 The EVBU normally has a jumper at J7 to support the trace function Figure 8 shows a small circuit that is added to the wire wrap area of the EVBU The 3 terminal jumper allows the XIRQ line to be connected to either the programming power supply or to a substitute pullup resistor for XIRQ The 100 ohm resistor is a current limiter to protect the 12 volt input of the MCU The resistor and LED connected to P5 pin 9 port C bit O is an optional indicator that lights when programming is complete Software BASIC was chosen as the programming language due to its readability and availability in parallel versions on both the IBM PC and the Macintosh The program demonstrates several programming techniques for use with M68HC11 and is not necessarily intended to be a finished commercial program For example there is little error checking and the user interface is elementary A complete listing of the BASIC program is included in Listing 2 BASIC Program for Personal Computer with moderate comments The following paragraphs include a more detailed discussion of the program as it pertains to communicating with and programming the target MC68HC71 1E9 Lines 25 45 initialize and define the variables and array used in the program Changes to this section would allow for other progr
113. ACTL is 0 14 051 is the output compare 5 interrupt enable bit Input Capture x Interrupt Enable Bits If the enable bit is set when the ICxF flag bit is set a hardware interrupt sequence is requested NOTE Bits in TMSK1 correspond bit for bit with flag bits in TFLG1 Bits in TMSK1 enable the corresponding interrupt sources 9 4 8 Timer Interrupt Flag 1 Register Bits in this register indicate when timer system events have occurred Coupled with the bits of TMSK1 the bits of TFLG1 allow the timer subsystem to operate in either a polled or interrupt driven system Each bit of TFLG1 corresponds to a bit in TMSK1 in the same position Address 1023 Bit 7 6 5 4 3 2 1 Bit 0 Read Wii OC2F OC3F OC4F 14 O5F IC1F IC2F IC3F rite Reset 0 0 0 0 0 0 0 0 Figure 9 18 Timer Interrupt Flag 1 Register TFLG1 Clear flags by writing a 1 to the corresponding bit position s OC1F OCAF Output Compare x Flag Set each time the counter matches output compare x value 14 O5F Input Capture 4 Output Compare 5 Flag Set by 4 or OC5 depending on the function enabled by 14 05 bit in IC1F IC3F Input Capture x Flag Set each time a selected active edge is detected on the ICx input line M68HC11E Family Data Sheet Rev 5 1 138 Freescale Semiconductor Output Compare 9 4 9 Timer Interrupt Mask 2 Register Use this 8 bit register to enable or inhibit timer overflow and real time interrup
114. ADSC MYPROG MYPROG S19 For more details on programming the EPROM read the engineering bulletin Programming MC68HC711E9 Devices with PCbug11 and the M68HC 1 1EVB Freescale document number EB187 Step 8 You are now ready to enable the security feature on the MCHC711E9 At the PCbug11 command prompt type MS 103F 05 Step 9 After the programming operation is complete verifyng the CONFIG on the MCHC711E9 is not possible because in bootstrap mode the default value is always forced Step 10 The part is now in secure mode and whatever code you loaded into EEPROM will be erased if you tried to bring the microcontroller up in either expanded mode or bootstrap mode NOTE It is important to note that the microcontroller will work properly in secure mode only in single chip mode NOTE If the part is placed in bootstrap or expanded the code in EEPROM and RAM will be erased and the microcontroller cannot be reused The security software will constantly read the NOSEC bit and lock the part Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR Rev 0 1 Freescale Semiconductor 231 To Execute the Program Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR Rev 0 1 232 Freescale Semiconductor Freescale Semiconductor E Engineering Bulletin Rev 0 1 07 2005 Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR
115. APS FOR INTERRUPT REQUESTS COP WATCHDOG AND FURTHER QUALIFIED BY PULSE ACCUMULATOR I BIT IN CCR 16 BIT TIMER BUS TO PULSE ACCUMULATOR E PN 8 FUNCTIONS PATIOCII I 2 PA6 OC2 OC1 PAS OC3 OC1 16 BIT COMPARATOR H LO 16 BIT COMPARATOR TOC2 H TOC2 LO 16 BIT COMPARATOR p TOC3 H TOC3 Lo B 16 BIT COMPARATOR OC4F x a E 4 0 4 OC1 TOC4 H TOC4 LO 16 BIT COMPARATOR TI4 05 H TM OS LO 16 BIT LATCH 5 3 gt IC4 OC1 16 BIT LATCH CLK TIC1 H TIC1 LO TIC2 H TIC2 LO 16 BIT LATCH CLK TIC3 H TIC3 LO PA2 IC1 s PA1 IC2 PA0 IC3 na 4 E gt e o o AQ N c o7 TMSK 1 PORTA INTERRUPT PIN CONTROL FLAGS ENABLES Figure 9 2 Capture Compare Block Diagram M68HC11E Family Data Sheet Rev 5 1 130 Freescale Semiconductor Input Capture The control and status bits that implement the input capture functions are contained in e Pulse accumulator control register PACTL Timer control 2 register TCTL2 Timer interrupt mask 1 register TMSK1 Timer interrupt flag 2 register TFLG1 To configure port A bit 3 as an input capture clear the DDRAS3 bit of the register Note that this bit is cleared out of reset To enable as the fourth input capture set the 14 O5 bit in the PACTL
116. ASR Arithmetic Shift EXT 77 hh 11 6 Right prenem IND X 67 6 b7 0 C IND Y 18 67 ff 7 ASRA Arithmetic Shift A INH 47 2 Right A b7 b0 C ASRB Arithmetic Shift B INH 57 2 Right B Ld tL b7 b0 C BCC rel Branch if Carry 2 0 REL 24 rr 3 Clear BCLR opr Clear Bit s M mm gt M DIR 15 dd mm 6 UL A msk IND X 1D mm 7 IND Y 18 1D mm 8 BCS rel Branch if Carry Cz1 REL 25 rr 3 Set BEQ rel Branch if Zero 27 1 REL 27 3 BGE rel Branch if A Zero N V 0 REL 2C jrr 3 M68HC11E Family Data Sheet Rev 5 1 72 Freescale Semiconductor Table 4 2 Instruction Set Sheet 2 of 7 Instruction Set Mhemonle Operation Description Addressing Instruction Condition Codes Mode Opcode Operand Cycles H 1 2 V C BGT rel Branch if Zero Z N V 0 REL 2E rr 3 BHI rel Branch if C Z 0 REL 22 rr 3 Higher BHS rel Branch if C 0 REL 24 rr 3 Higher or Same BITA opr Bit s Test A AeM A IMM 85 jii 2 0 with Memory A DIR 95 3 A EXT B5 hh 11 4 A IND X 5 4 A IND Y 18 A5 ff 5 BITB opr Bit s Test B IMM C5 jii 2 A 0 with Memory B DIR 05 dd 3 B EXT F5 hh 11 4 B IND X E5 Jff 4 B IND Y 18 ES Tf 5 BLE rel Branchi
117. BOOT is reset to 0 to keep the boot ROM out of the memory map While in special test mode SMOD 1 which allows the RBOOT control bit to be written to 1 by software to enable the boot ROM for testing purposes Boot ROM Firmware The main program in the boot ROM is the bootloader which is automatically executed as a result of resetting the MCU in bootstrap mode Some newer versions of the M68HC11 Family have additional utility programs that can be called from a downloaded program One utility is available to program EPROM or OTP versions of the M68HC11 A second utility allows the contents of memory locations to be uploaded to a host computer In the MC68HC711K4 boot ROM a section of code is used by Freescale for stress testing the on chip EEPROM These test and utility programs are similar to self test ROM programs in other MCUs except that the boot ROM does not use valuable space in the normal memory map Bootstrap firmware is also involved in an optional EEPROM security function on some versions of the M68HC 11 This EEPROM security feature prevents a software pirate from seeing what is in the on chip EEPROM The secured state is invoked by programming the no security NOSEC EEPROM bit in the CONFIG register Once this NOSEC bit is programmed to 0 the MCU will ignore the mode A pin and always come out of reset in normal single chip mode or special bootstrap mode depending on the state of the mode B pin Normal single chip mode is the usual way a
118. Basic Bootstrap Mode Basic Bootstrap Mode This section describes only basic functions of the bootstrap mode Other functions of the bootstrap mode are described in detail in the remainder of this application note When an M68HC 1 1 is reset in bootstrap mode the reset vector is fetched from a small internal read only memory ROM called the bootstrap ROM or boot ROM The firmware program in this boot ROM then controls the bootloading process in this manner First the on chip SCI serial communications interface is initialized The first character received FF determines which of two possible baud rates should be used for the remaining characters in the download operation Next a binary program is received by the SCI system and is stored in RAM Finally a jump instruction is executed to pass control from the bootloader firmware to the user s loaded program Bootstrap mode is useful both at the component level and after the MCU has been embedded into a finished user system At the component level Freescale uses bootstrap mode to control a monitored burn in program for the on chip electrically erasable programmable read only memory EEPROM Units to be tested are loaded into special circuit boards that each hold many MCUS These boards are then placed in burn in ovens Driver boards outside the ovens download an EEPROM exercise and diagnostic program to all MCUs in parallel The MCUs under test independently exercise their inte
119. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset Indeterminate after reset Unimplemented Figure 3 6 Analog to Digital Converter Result Registers ADR1 ADR4 M68HC11E Family Data Sheet Rev 5 1 64 Freescale Semiconductor Chapter 4 Central Processor Unit CPU 4 1 Introduction Features of the M68HC11 Family include Central processor unit CPU architecture Data types e Addressing modes Instruction set e Special operations such as subroutine calls and interrupts The CPU is designed to treat all peripheral input output I O and memory locations identically as addresses in the 64 Kbyte memory map This is referred to as memory mapped I O There are no special instructions for I O that are separate from those used for memory This architecture also allows accessing an operand from an external memory location with no execution time penalty 4 2 CPU Registers M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations The seven registers discussed in the following paragraphs are shown in Figure 4 1 7 A 0 7 0 8 BIT ACCUMULATORS A amp B 15 D 0 OR 16 BIT DOUBLE ACCUMULATOR D IX INDEX REGISTER X INDEX REGISTER Y SP STACK POINTER PC PROGRAM COUNTER 7 0 S X H I N Z V CONDITION CODES CARRY BORROW FROM MSB OVERFLOW ZERO NEGATIVE I NTERRUPT MASK HALF CARRY FROM BIT 3 X INTERRUPT MASK STOP DISABLE Figure 4
120. C bit bit 3 It is also recommended to program the EEPROM at this point before programming the CONFIG register Refer to the engineering bulletin Programming MC68HC811E2 Devices with PCbug11 and the M68HC711E9PGMR Freescale document number EB184 At the PCbug11command prompt type EEPROM ERASE BULK 103F Step 7 You are now ready to enable the security feature on the MCHC811E2 At the PCbug11 command prompt type MS 103F 05 The value 05 assumes the EEPROM is to be mapped from 0800 to 0FFF Step 8 After the programming operation is complete verifying the CONFIG on the MCHC811E2 is not possible because in bootstrap mode the default value is always forced Step 9 The part is now in secure mode and whatever code you loaded into EEPROM will be erased if you tried to bring the microcontroller up in either expanded mode or bootstrap mode The microcontroller will work properly in the secure mode only in single chip mode NOTE If the part is placed in bootstrap mode or expanded mode the code in EEPROM and RAM will be erased the microcontroller can be reused Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR Rev 0 1 Freescale Semiconductor 235 To Execute the Program Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR Rev 0 1 236 Freescale Semiconductor Freescale Semiconductor PE Engineering Bulletin ev 0 1 07 2005 Programming MC68HC711E9
121. CONTINUES AS LONG AS DATA IS RECEIVED VERIFY DATA TO HOST 5 SAME AS MCU Tx DATA OR z HOST SENDING DATA FOR 3 1 N eer e MCU EPROM MCU RECEIVE DATA FROM HOST Y MC68HC711E9 iB ia 4 EU PROGRAM LOOP EPROM PROGRAMMING 9 MCU TRANSMIT DATA VERIFY srr ES v va w Figure 4 Host and MCU Activity during EPROM PROGRAM Utility M68HC11 Bootstrap Mode Rev 1 1 202 Freescale Semiconductor Allowing for Bootstrap Mode After the MCU sends FF 8 it enters the WAIT1 loop 9 and waits for the first data character from the host When this character is received 10 the MCU programs it into the address pointed to by the Y index register When the programming time delay is over the MCU reads the programmed data transmits it to the host for verification 11 and returns to the top of the loop to wait for the next data character 12 Because the host previously sent the second data character it is already waiting in the SCI receiver of the MCU Steps 13 14 and 15 correspond to the second pass through the WAIT1 loop Back in the host the first verify character is received and the third data character is sent 6 The host then waits for the second verify character 7 to come back from the MCU The sequence continues as long as the host continues to send data to the MCU Since the WAIT1 loop in the PROGRAM utility is an indefinite loop reset is used to end the process in the MCU after the
122. CPU The conversion complete flag CCF indicates when valid data is present in the result registers The result registers are written during a portion of the system clock cycle when reads do not occur so there is no conflict 3 2 5 A D Converter Clocks The CSEL bit in the OPTION register selects whether the A D converter uses the system E clock or an internal RC oscillator for synchronization When E clock frequency is below 750 kHz charge leakage in the capacitor array can cause errors and the internal oscillator should be used When the RC clock is used additional errors can occur because the comparator is sensitive to the additional system clock noise 3 2 6 Conversion Sequence A D converter operations are performed in sequences of four conversions each A conversion sequence can repeat continuously or stop after one iteration The conversion complete flag CCF is set after the fourth conversion in a sequence to show the availability of data in the result registers Figure 3 3 shows the timing of a typical sequence Synchronization is referenced to the system E clock CLOCK MUU U UU UU UU UU UU UU UU EU UU L Y 1 MSB BIT 6 5 BIT4 BIT2 BIT1 LSB 12 E CYCLES 4 2 2 2 2 2 2 2 CYC E CYCLES CYC CYC CYC CYC CYC CYC CYC END 2 SAMPLE ANALOG INPUT SUCCESSIVE APPROXIMATION SEQUENCE g 5 mE ui f E zu 8 s CONVERT FIRST 77 CONVERT SECOND CONVERT THIRD C
123. DDR10 PB3 ADDR11 PB4 ADDR12 PB5 ADDR13 PB6 ADDR14 PB7 ADDR15 PAO IC3 PA1 IC2 PA2 IC1 PA3 OC5 ICA4 OC1 PA4 OCA OC1 PAB OC3 OC1 PA6 OC2 OC1 PATIPAI OC1 EVpp Vppe applies only to devices with EPROM OTPROM Figure 1 5 Pin Assignments for 56 Pin SDIP M68HC11E Family Data Sheet Rev 5 1 19 General Description PA7 PAI OC1 Vpp PA6 OC2 OC1 PD5 SS 1 PD4 SCK PA4 OCA OC1 PD3 MOSI PA3 OCB ICA OC1 PD2 MISO PA2 IC1 PD1 TxD PA1 IC2 PDO RxD PAO IC3 iRQ PB7 ADDR15 XIRQ PB6 ADDR14 RESET PB5 ADDR13 PC7 ADDR7 DATA7 PB4 ADDR12 MC68HC811E2 PC6 ADDR6 DATA6 PB3 ADDR11 PC5 ADDR5 DATAS PB2 ADDR10 PC4 ADDR4 DATA4 PB1 ADDR9 PC3 ADDR3 DATA3 PBO ADDR8 PC2 ADDR2 DATA2 PEO ANO PC1 ADDR1 DATA1 PE1 AN1 PCO ADDRO DATAO PE2 AN2 XTAL EXTAL VRL STRB R W STRA AS 24 MODA LIR Figure 1 6 Pin Assignments for 48 Pin DIP MC68HC811E2 M68HC11E Family Data Sheet Rev 5 1 20 Freescale Semiconductor Pin Descriptions 1 4 1 Vpp and Vss Power is supplied to the MCU through Vpp and Vss Vpp is the power supply Vss is ground The MCU operates from a single 5 volt nominal power supply Low voltage devices in the E series operate at 3 0 5 5 volts Very fast signal transitions occur on the MCU pins The short rise and fall times place high short duration current demands on the power supply To prevent noise problems provide good power supply bypassing at the MCU Als
124. Devices with PCbug11 and the M68HC11EVBU By John Bodnar Austin Texas Introduction The PCbug1software needed along with the M68HC11EVBU to program MC68HC711E9 devices is available from the download section of the Microcontroller Worldwide Web site http www freescale com Retrieve the file pcbug342 exe a self extracting archive from the MCU11 directory Some Freescale evaluation board products also are shipped with PCbug11 NOTE For specific information about any of the PCbug11 commands see the appropriate sections in the PCbug11 User s Manual part number M68PCBUG 11 22 which is available from the Freescale Literature Distribution Center as well as the Worldwide Web at http www freescale com The file is also on the software download system is called pcbug1 1 paf Freescale Semiconductor Inc 2005 All rights reserved 2 e 9 T z freescale semiconductor Programming Procedure Programming Procedure Once you have obtained PCbugl 1 use this step by step procedure to program your MC68HC71 1E9 part Step 1 Before applying power to the EVBU remove the jumper from J7 and place it across J3 to ground the MODB pin Place a jumper across J4 to ground the MODA pin This will force the EVBU into special bootstrap mode on power up e Remove the resident MC68HC11E9 MCU from the EVBU your MC68HC711E9 in the open socket with the notched corner of the part aligned with the notch o
125. E M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 90 100 pF Electrical Characteristics 10 6 Supply Currents and Power Dissipation 1 5 0 10 Vss 0 TA T to Ty unless otherwise noted 2 EXTAL is driven with a square wave and tcyc 500 ns for 2 MHz rating 333 ns for 3 MHz rating Vi lt 0 2 V no dc loads M68HC11E Family Data Sheet Rev 5 1 152 Freescale Semiconductor Characteristics Symbol Min Max Unit Run maximum total supply current Single chip mode2 MHz E 15 3 MHz 27 mA Expanded multiplexed mode2 MHz 27 3 MHz 35 Wait maximum total supply current all peripheral functions shut down 6 Single chip mode2 MHz Wisp 15 mA 3 MHz M 10 Expanded multiplexed mode2 MHz 124 20 3 MHz Stop maximum total supply current Single chip mode no clocks 40 C to 85 Sob 25 gt 85 to 105 50 gt 105 C to 125 100 Maximum power dissipation Single chip mode2 MHz 85 3 MHz Pp 150 mW Expanded multiplexed mode2 MHz 150 3 MHz 195 MC68L11E9 E20 DC Electrical Characteristics 10 7 MC68L11E9 E20 DC Electrical Characteristics Characteristics Symbol Min Max Unit Output voltage 10 0 0 1 V All outputs except XTAL Vpp 0 1 All outputs except XTAL RESET MODA Out
126. E 1 after enable edge he E E 1 Vpp 3 0 to 5 5 Vss 0 TA T to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 Time to data active from high impedance state 3 Assumes 100 pF load on SCK MOSI and MISO pins 172 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor MC68L11E9 E20 Serial Peirpheral Interface Characteristics ss INPUT SS IS HELD HIGH ON MASTER lt 1 gt SCK H5 N CPOL 0 sEENOTE N N INPUT gt 4 gt SCK ROO CPOL 1 sEENOrE N 75 470 7 OUTPUT 2 lt gt MISO gt gt DE 11 REF MOSI OUTPUT MASTER MSB OUT BT6 1 MASTER LSB OUT Note This first clock edge is generated internally but is not seen at the SCK pin ss INPUT SCK CPOL 0 INPUT SCK CPOL 1 OUTPUT MISO INPUT MOSI OUTPUT A SPI Master Timing CPHA 0 SS IS HELD HIGH ON MASTER SEE NOTE SEE NOTE IN E gt 017 gt e 11 REF MASTER MSB OUT BIT6 1 MASTER LSB OUT Note This first clock edge is generated internally but is not seen at the SCK pin B SPI Master Timing CPHA 1 Figure 10 15 SPI Timing Diagram Sheet 1 of 2 M68HC11E Family Data Sheet Rev 5 1 173 Freescale Semiconductor Electrical Characteristics SS INPUT o SCK 5 N CP
127. E Family Data Sheet Rev 5 1 30 Freescale Semiconductor located this ROM at BFCO BFFF The bootstrap ROM contains small program which initializes the serial communications interface and allows the user to download a program into on chip RAM size of the downloaded program can be as large as the size of the on chip RAM After a 4 character delay or after receiving the character for the highest address in RAM control passes to the loaded program at 0000 Refer to Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 and Figure 2 6 Use of an external pullup resistor is required when using the SCI transmitter pin because port D pins are configured for wired OR operation by the bootloader In bootstrap mode the interrupt vectors are directed to RAM This allows the use of interrupts through a jump table Refer to the application note AN1060 entitled M68HC11 Bootstrap Mode that is included in this data book 2 3 Memory Map The operating mode determines memory mapping and whether external addresses can be accessed Refer to Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 and Figure 2 6 which illustrate the memory maps for each of the three families comprising the M68HC11 E series of MCUs Memory locations for on chip resources are the same for both expanded and single chip modes Control bits in the configuration CONFIG register allow EPROM and EEPROM if present to be disabled from the memory map The
128. E clock rate The host computer sends an initial FF character which is used by the bootloader to determine the baud rate that will be used for the downloading operation The top half of Figure 2 shows normal reception of FF Receive data samples at 1 detect the falling edge of the start bit and then verify the start bit by taking a sample at the center of the start bit time Samples are then taken at the middle of each bit time 2 to reconstruct the value of the received character all 1s in this case A sample is then taken at the middle of the stop bit time as a framing check a 1 is expected 3 Unless another character immediately follows this FF character the receive data line will idle in the high state as shown at 4 The bottom half of Figure 2 shows how the receiver will incorrectly receive the FF character that is sent from the host at 1200 baud Because the receiver is setto 7812 baud the receive data samples are taken at the same times as in the upper half of Figure 2 The start bit at 1200 baud 5 is 6 5 times as long as the start bit at 7812 baud 6 0000 MAY BE REMAPPED EN 512 BYTE ANY 4K BOUNDARY Bc RAM 01FF EN EN EXTERNAL EXTERNAL 1000 2 PEERS 103F REGISTER TO ANY 4K BOUNDARY BLOCK EXTERNAL EXTERNAL MAYBE DISABLED 8600 BY AN EEPROM BIT B7FF BFCO EXTERNAL EXTERNAL me
129. EMOVE J7 oo JUMPER J14 bo TO MC68HC68T1 BE SURE NO 22 JUMPER IS oo ON J14 oo Figure 7 Isolating EVBU XIRQ Pin Listing 1 MCU to MCU Duplicator Program 1 k k k k k k k k k k k k k k k k k k k lt k k K k 2 68HC711E9 Duplicator Program for AN1060 3 ck k k k k k k k k k ck k k k k k k k k k k k K k K k k k k ko lt 4 5 KKKKK 6 Equates All reg addrs except INIT are 2 digit 7 for direct addressing 8 KKKKK 9 103D INIT EQU 103D RAM Reg mapping 10 0028 SPCR EQU 28 DWOM in bit 5 11 0004 PORTB EQU 04 Red LED bit 1 Grn bit 0 12 Reset of prog socket bit 7 13 0080 RESET EQU 10000000 14 0002 RED EQU 500000010 15 0001 GREEN EQU 00000001 16 000 PORTE EQU 0A Vpp Sense in bit 7 1 17 002E SCSR EQU 2E SCI status register 18 TDRE TC RDRF IDLE OR NF FE 19 0080 TDRE EQU 10000000 20 0020 RDRF EQU 00100000 21 002F SCDR EQU 2 SCI data register 22 BFOO PROGRAM EQU SBFOO EPROM prog utility in boot ROM 23 D000 EPSTRT EQU 50000 Starting address of EPROM 24 25 B600 ORG B600 Start of EEPROM 26 M68HC11 Bootstrap Mode Rev 1 1 208 Freescale Semiconductor 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
130. EPROM array The clock source driving the charge pump is software selectable When the clock select CSEL bit in the OPTION register is O the E clock is used when CSEL is 1 an on chip resistor capacitor RC oscillator is used The EEPROM programming voltage power supply voltage to the EEPROM array is not enabled until there has been a write to PPROG with EELAT set and PGM cleared This must be followed by a write to a valid EEPROM location or to the CONFIG address and then a write to PPROG with both the EELAT and EPGM bits set Any attempt to set both EELAT and EPGM during the same write operation results in neither bit being set 2 5 1 1 Block Protect Register This register prevents inadvertent writes to both the CONFIG register and EEPROM The active bits in this register are initialized to 1 out of reset and can be cleared only during the first 64 E clock cycles after reset in the normal modes When these bits are cleared the associated EEPROM section and the CONFIG register can be programmed or erased EEPROM is only visible if the EEON bit the CONFIG register is set The bits in the BPROT register can be written to 1 at any time to protect EEPROM and the CONFIG register In test or bootstrap modes write protection is inhibited and BPROT can be written repeatedly Address ranges for protected areas of EEPROM differ significantly for the MC68HC81 1E2 Refer to Figure 2 16 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconduc
131. Enabled Delay for fast baud rate Set as default delay Set send break bit Wait for RxD pin to go low Clear send break bit Wait for RDRF Read data 00 received Bypass JMP if not 0 Jump to EEPROM if it was 0 SFF will be seen as SFF If baud was correct 8 1200 2MHZ Works because 22 gt 33 And switch to slower delay constant Point at start of RAM Move delay constant to D Exit loop if RDRF set Swap delay count to X Decrement count Swap back to D Loop if not timed out Quit download on timeout Get received data Store to next RAM location Transmit it for handshake Point at next RAM location See if past end not Get another Init X with programming delay Init Y with EPROM start addr EXIT to start of RAM Zeros E72D STAB SCCR2 X 021 LDD DELAYF ED16 STD 1 Send BREAK to signal ready for download 1C2D01 BSET SCCR2 X 01 1 0801 BRSET PORTD X 01 102101 BCLR SCCR2 X 01 1 2 20 BRCLR SCSR X 20 A62F LDAA SCDAT X Data will be 00 if BREAK OR 2603 BNE NOTZERO 7EB600 JMP EEPMSTR NOTZERO EQU 81FF CMPA SFF 2708 BEQ BAUDOK Or else change to 104 13 amp 1C2B33 BSET BAUD X 33 CCODBO LDD DELAYS ED16 STD 1 BAUDOK EQU 18CE0000 LDY RAMSTR WAIT EQU EC16 LDD 1 WTLOOP EQU 1 2 2007 SCSR X 20 NEWONE 8 XGDX 09 DEX 8F XGDX 26F7 BNE WTLOOP 200F BRA STAR NEWONE EQU A62F LDAA SCDAT X 18A70
132. HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 223 Listing 3 MC68HC711E9 Bootloader ROM 107 This routine uses 2 bytes of stack space 108 Routine does not return Reset to exit 109 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk 110 BF13 PRGROUT EQU 111 BF13 3C PSHX Save program delay constant 112 BF14 CE1000 LDX 51000 Point to internal registers 113 BF17 114 Send SFF to indicate ready for program data 115 116 BF17 1F2E80FC BRCLR SCSR X 80 Wait for TDRE 117 BF1B 86FF LDAA SFF 118 BF1D A72F STAA SCDAT X 119 120 1 1 EQU 121 BFIF 1 2 20 BRCLR SCSR X 20 Wait for RDRF 122 23 E62F LDAB SCDAT X Get received byte 123 BF25 18E100 CMPB 0 Y See if already programmed 124 BF28 271D BEQ DONEIT If so skip prog cycle 125 BF2A 8620 LDAA ELAT Put EPROM in prog mode 126 BF2C A73B STAA PPROG X 127 BF2E 18E700 STAB 0 Write the data 128 BF31 8621 LDAA ELAT EPGM 129 BF33 A73B STAA PPROG X Turn on prog voltage 130 BF35 32 PULA Pull delay constant 131 BF36 33 PULB into D reg 132 BF37 37 PSHB But also keep delay 133 BF38 36 PSHA keep delay on stack 134 BF39 E30E ADDD TCNT X Delay const present TCNT 135 ED16 STD TOC1 X Schedule 1 2ms delay 136 BF3D 8680 LDAA OC1F 137 BF3F A723 STAA TFLG1 X Clear any previous flag 138 139 BF41 1F2380FC BRCLR TFLG1 X OC1F Wait for delay to expire 140 45 6F3B CLR PPROG X Turn off prog voltage 141
133. HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 55 ae eee Operating Modes and On Chip Memory M68HC11E Family Data Sheet Rev 5 1 56 Freescale Semiconductor Chapter 3 Analog to Digital A D Converter 3 1 Introduction The analog to digital A D system a successive approximation converter uses an all capacitive charge redistribution technique to convert analog signals to digital values 3 2 Overview The A D system is an 8 channel 8 bit multiplexed input converter The converter does not require external sample and hold circuits because of the type of charge redistribution technique used A D converter timing can be synchronized to the system E clock or to an internal resistor capacitor RC oscillator The A D converter system consists of four functional blocks multiplexer analog converter digital control and result storage Refer to Figure 3 1 3 2 1 Multiplexer The multiplexer selects one of 16 inputs for conversion Input selection is controlled by the value of bits CD CA in the ADCTL register The eight port E pins are fixed direction analog inputs to the multiplexer and additional internal analog signal lines are routed to it Port E pins also can be used as digital inputs Digital reads of port E pins are not recommended during the sample portion of an A D conversion cycle when the gate signal to the N channel input gate is on Because no P channel devices are directly connected to either input pins
134. Hz 00 2 731 ms 4 096 ms 8 192 ms 213 01 5 461 ms 8 192 ms 16 384 ms E 21 10 10 923 ms 16 384 ms 32 768 ms 215 11 21 845 32 768 65 536 216 The clock source for the RTI function is free running clock that cannot be stopped or interrupted except by reset This clock causes the time between successive RTI timeouts to be a constant that is M68HC11E Family Data Sheet Rev 5 1 140 Freescale Semiconductor Real Time Interrupt RTI independent of the software latencies associated with flag clearing and service For this reason an RTI period starts from the previous timeout not from when RTIF is cleared Every timeout causes the RTIF bit in TFLG2 to be set and if RTII is set an interrupt request is generated After reset one entire RTI period elapses before the RTIF is set for the first time Refer to the 9 4 9 Timer Interrupt Mask 2 Register 9 5 2 Timer Interrupt Flag Register 2 and 9 5 3 Pulse Accumulator Control Register 9 5 1 Timer Interrupt Mask Register 2 This register contains the real time interrupt enable bits Address 1024 Bit 7 6 5 4 3 2 1 Bit 0 Read l TOI RTI PAOVI PAII PR1 PRO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 21 Timer Interrupt Mask 2 Register TMSK2 TOI Timer Overflow Interrupt Enable Bit 0 TOF interrupts disabled 1 Interrupt requested when TOF is set to 1 RTII Real Time Inter
135. ION register The presence of a timeout is determined by the RC delay which allows the clock monitor to operate without any MCU clocks Clock monitor is used as a backup for the COP system Because the COP needs a clock to function it is disabled when the clock stops Therefore the clock monitor system can detect clock failures not detected by the COP system Semiconductor wafer processing causes variations of the RC timeout values between individual devices An E clock frequency below 10 kHz is detected as a clock monitor error An E clock frequency of 200 kHz or more prevents clock monitor errors Using the clock monitor function when the E clock is below 200 kHz is not recommended Special considerations are needed when a STOP instruction is executed and the clock monitor is enabled Because the STOP function causes the clocks to be halted the clock monitor function generates a reset sequence if it is enabled at the time the stop mode was initiated Before executing a STOP instruction clear the CME bit the OPTION register to 0 to disable the clock monitor After recovery from STOP set the CME bit to logic 1 to enable the clock monitor Alternatively executing a STOP instruction with the CME bit set to logic 1 can be used as a software initiated reset M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 81 Resets and Interrupts 5 2 5 System Configuration Options Register Address 1039
136. K PDS PD5 SS s STRA AS STRB R W PEO PEO ANO PE1 PETANI PE3 AN2 PE4 AN4 PES PES5 AN5 7 PE7 AN7 26 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor Pin Descriptions PA6 PAA serve as either general purpose outputs timer input captures or timer output compare 2 4 In addition 6 4 can be controlled by OC1 can be a general purpose pin or a timer IC OC pin Timer functions associated with this pin include OC1 and IC4 OC5 ICA OC5 is software selectable as either a fourth input capture or a fifth output compare can also be configured to allow OC1 edges to trigger 4 captures 2 serve as general purpose inputs or as IC1 1C3 PORTA can be read at any time Reads of pins configured as inputs return the logic level present on the pin Pins configured as outputs return the logic level present at the pin driver input If written PORTA stores the data in an internal latch bits 7 and 3 It drives the pins only if they are configured as outputs Writes to PORTA do not change the pin state when pins are configured for timer input captures or output compares Refer to Chapter 6 Parallel Input Output I O Ports 1 4 13 Port B During single chip operating modes all port B pins are general purpose output pins During MCU reads of this port the level sensed at the input side of the port B output drivers is read
137. M Download JMP on JMP GSBFD1 SBFD2 3 GSBFD4 5 Mask set 256 0000 FF Mask set 256 0000 FF Mask set 256 0000 FF MC68SEC11A8 Mask set 256 0000 FF MC68HC11D3 00 ROM 1 0 1103 0 192 F000 ROM 0040 FF MC68HC711D3 42 B 0000 71D3 0 192 F000 EPROM 0040 FF 0 Default and UPLOAD 1 2 Length BRK or 00 to RAM Location Utility 256 B600 0000 0000 FF 256 B600 0000 0000 FF 0000 71E9 0 512 B600 0000 1 FF MC68HC11K4 30 0 ROM I D 044B 0 768 0D80 0080 37F MC68HC711K4 42 B 0000 744B 0 768 0D80 0080 37F NOTES 1 No oc By sending 00 or a break as the first SCI character after reset in bootstrap mode a jump JMP is executed to the address in this table rather than doing a download Unless otherwise noted this address is the start of EEPROM Tying RxD to TxD and using a pullup resistor from TxD to Vpp will cause the SCI to see a break as the first received character If 55 is received as the first character after reset in bootstrap mode a jump JMP is executed to the start of on chip RAM rather than doing a download This 55 character must be sent at the default baud rate 7812 baud E 2 MHz For devices with variable length download the same effect can be achieved by sending FF and no other SCI characters After four SCI character times the download terminates and a jump JMP to the start of RAM is executed The jump to
138. MC68HC711E20MFU2 52 pin thin quad flat pack TQFP 2 MHz MC68HC11E9BCPB2 BUFFALO ROM 0F 40 to 85 C 3 MHz MC68HC11E9BCPB3 178 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor Custom ROM Device Ordering Information Description CONFIG Temperature Frequency MC Order Number 52 pin windowed ceramic leaded chip carrier CLCC 2 MHz MC68HC711E9CFS2 40 to 85 3 MHz MC68HC711E9CFS3 EPROM OF 40 to 105 C 2 MHz MC68HC711E9VFS2 40 to 125 C 2 MHz MC68HC711E9VFS2 0 70 3MHz MC68HC711E20FS3 2 MHz MC68HC711E20CFS2 40 to 85 20 Kbytes EPROM 3 MHz MC68HC711E20CFS3 40 to 105 C 2 MHz MC68HC711E20VFS2 40 to 125 2 MHz MC68HC711E20MFS2 48 pin dual in line package DIP MC68HC811E2 only 0 C to 70 C 2 MHz MC68HC811E2P2 40 to 85 C 2 MHz MC68HC811E2CP2 No ROM 2 Kbytes EEPROM FF 40 C to 105 C 2 MHz MC68HC811E2VP2 40 to 125 C 2 MHz MC68HC811E2MP2 56 pin dual in line package with 0 70 inch lead spacing SDIP 2 MHz MC68HC11E9BCB2 BUFFALO ROM OF 40 C to 85 C 3 MHz MC68HC11E9BCB3 2 MHz MC68HC11E1CB2 40 to 85 C 3 MHz MC68HC11E1CB3 No ROM 0D 40 C to 105 C 2 MHz MC68HC11E1VB2 40 to 125 C 2 MHz MC68HC11E1MB2 2 MHz MC68HC11E0CB2 40 to 85 3 MHz MC68HC11E0CB3 No ROM no EEPROM 0C
139. MOLD FLASH MAXIMUM MOLD FLASH 0 25 0 010 TARER INCHES MILLIMETERS DIM MIN MAX MIN MAX DETAIL X A 2415 2 445 61 34 62 10 B 0540 0560 1372 1422 C 0155 0200 394 5 08 D 0 014 0 022 036 0 55 0 040 0 060 102 1 52 C4 e LE G 0 100BSC 2 54 BSC H 0 070BSC 1 79 BSC pa J 000 0 015 020 0 38 UL K 0 115 0 150 292 3 81 m L 0 600BSC 15 24 BSC SEATING mE M 48 PL N T T as ae 5 PEANE M L DETAILX N F G J 48 PL lt D 32 PL 0 25 0 010 T B 0 51 0 020 T A e oe 2 M68HC11E Family Data Sheet Rev 5 1 186 Freescale Semiconductor Development Support A 1 Introduction This section provides information on the development support offered for the E series devices A 2 M68HC11 E Series Development Tools Device Package Emulation Flex MMDS11 9 Module 2 Cable 2 Target Head 2 3 Adapter 52 FN M68EM11E20 M68CBL11C M68TC11E20FN52 M68PA11E20FN52 MC68HC11E9 52 PB M68EM11E20 M68CBL11C M68TC11E20PB52 M68PA11E20PB52 MC68HC711E9 56B M68EM11E20 M68CBL11B M68TC11E20B56 M68PA11E20B56 64 FU M68EM11E20 M68CBL11C M68TC11E20FU64 M68PA11E20FU64 MC68HC11E20 52 FN M68EM11E20 M68CBL11C M68TC11E2
140. Max Unit Output voltage 10 0 All outputs except XTAL All outputs except XTAL RESET and MODA Vor Vpp 0 1 Output high voltage 0 8 mA Vpp 4 5 V All outputs except XTAL RESET and MODA Vpp 0 8 Output low voltage 1 6 mA All outputs except XTAL 0 4 Input high voltage All inputs except RESET RESET 0 7 x Vpp 0 8 x VDD Vpp 0 3 Vpp 0 3 Input low voltage all inputs Vss 0 3 0 2 x Vpp ports 3 state leakage Vin Vin OF Vi PA7 PA3 PC 7 0 PD 5 0 AS STRA MODA LIR RESET Input leakage current 9 Vin Vpp Or Vss PA 2 0 IRQ XIRQ MODB Vstpy XIRQ on EPROM based devices uA uA RAM standby voltage power down Vpp RAM standby current power down uA Input capacitance PA 2 0 PE 7 0 IRQ XIRQ EXTAL uu PA7 7 0 PD 5 0 AS STRA MODA LIR RESET 12 pF Output load capacitance All outputs except PD 4 1 PD 4 1 CL 1 5 0 10 Vss 0 TA T to Ty unless otherwise noted 2 Specification for RESET and MODA is not applicable because they are open drain pins specification not appli cable to ports C and D in wired OR mode 3 Refer to 10 13 Analog to Digital Converter Characteristics and 10 14 MC68L11E9 E20 Analog to Digital Converter Char acteristics for leakage current for port
141. N HC711E9 WITH BUFFALO 3 4 REQUIRES THAT THE S RECORDS FOR BUFFALO BUF34 919 BE AVAILABLE IN THE SAME DIRECTORY OR FOLDER E THIS PROGRAM HAS BEEN RUN BOTH ON A MS DOS COMPUTER E USING QUICKBASIC 4 5 AND ON A MACINTOSH USING x QUICKBASIC 1 0 k k K k k k k K k k k k K k k k K k k K k k k k k k k k k k K k k k k k k k k k K k k k K k k K K k k x lt HS 0123456789ABCDEF STRING TO USE FOR CONVERSIONS DEFINT B I CODESIZE 8192 ADRSTART 57344 BOOTCOUNT 25 NUMBER OF BYTES IN BOOT CODE DIM CODE CODESIZE BUFFALO 3 4 IS 8K BYTES LONG BOOTCODES INITIALIZE BOOTCODES TO NULL REM READ IN AND SAVE THE CODE BE BOOT LOADED FOR 1 TO BOOTCOUNT OF BYTES IN BOOT CODE READ Q AS MID Q 1 1 GOSUB 7000 CONVERTS HEX DIGIT TO DECIMAL TEMP 16 X HANG ON TO UPPER DIGIT AS MIDS QS 2 1 GOSUB 7000 TEMP TEMP X BOOTCODES BOOTCODES CHRS TEMP BUILD BOOT CODE NEXT I REM S RECORD CONVERSION STARTS HERE FILNAMS BUF34 S19 DEFAULT FILE NAME FOR S RECORDS CLS PRINT Filename ext of S record file to be downloaded FILNAMS INPUT 0 Q lt gt THEN 0 OPEN FILNAM FOR INPUT AS 1 PRINT PRINT Converting FILNAMS to binary REM SCANS FOR S1 RECORDS 0 GOSUB 6000 GET 1 CHARACTER FROM INPUT FILE O IF FLAG THEN 1250 FLAG IS EOF FLAG FROM SUBROUTINE 0
142. NECTOR Es CERO Vss XTAL em 2519 1 0 9 MC68HC11E9FN 2410 GND USER S TERMINAL OR PC 2719 MASTER Vc Voc 0 221 4 Vcc 2110 NOTE 1 c14 0 DCD 282 O U2 47K 5 12 10 pF 14 DTR 20 o INPUT 2 20 1 UT MCU17 RESET MCU21 PD1 TXD 4 2 9 RESET RESET ik 201 o MCU20 PDURXD 1 En 12 L 064 eu e z C FO E 57 C2 o LI 15 6 CTS 741 O 16 DI TX1 5 5 _ 1 13 001 RX1 8 1 TXD gt 731 9 D 14 7 15 002 Veo The palo 0 20 12 9 14 491003 11 9 Voc Voo GND 2 4 64 MC145407 5 5 Notes _ yF 1 Default cut traces installed from factory on bottom of the board 2 X1 is shipped as a ceramic resonator with built in capacitors Holes are provided for a crystal and two capacitors Figure B 1 EVBU Schematic Diagram Freescale Semiconductor AN1060 Application Note Rev 1 1 07 2005 M68HC11 Bootstrap Mode By Jim Sibigtroth Mike Rhoades John Langan Austin Texas Introduction The M68HC11 Family of MCUs microcontroller units has a bootstrap mode that allows a user defined program to be loaded into the internal random access memory RAM by way of the serial communications interface SCI the M68HC11 then executes this loaded program The loaded program can do anything a normal user program can do as
143. NING AND TOLERANCING PER ANSI 14 5 1982 CONTROLLING DIMENSION MILLIMETER DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE DATUMS L M AND N TO BE DETERMINED AT DATUM PLANE H DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE T DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 25 0 010 PER SIDE DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0 46 0 018 MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0 07 0 003 MILLIMETERS INCHES DIM MIN MAX MIN MAX A 10 00 BSC 0 394 BSC Al 5 00 BSC 0 197 BSC B 10 00 BSC 0 394 BSC Bi 5 00 BSC 0 197 BSC 170 0 067 0 05 0 20 0 002 0 008 c2 1 30 1 50 0 051 0 059 D 0 20 0 40 0 008 0 016 E 0 45 0 75 0 018 0 030 F 0 22 0 35 0 009 0 014 G 0 65 BSC 0 026 BSC J 0 07 0 20 0 003 0 008 K 0 50 REF 0 020 REF R1 0 08 0 20 0 003 0 008 12 00 BSC 0 472 BSC 51 6 00 5 0 236 5 0 09 0 16 0 004 0 006 V 12 00 BSC 0 472 BSC vi 6 00 BSC 0 236 BSC 0 20 0 008 2 1 00 0 039 e 0 7 09 T 01 0 0
144. NTROL 1 TIE TCIE SCI Rx SCI INTERRUPT INTERNAL REQUESTS REQUEST DATA BUS Note Refer to Figure B 1 EVBU Schematic Diagram for an example of connecting TxD to a PC Figure 7 1 SCI Transmitter Block Diagram M68HC11E Family Data Sheet Rev 5 1 106 Freescale Semiconductor Receive Operation 7 4 Receive Operation During receive operations the transmit sequence is reversed The serial shift register receives data and transfers it to a parallel receive data register SCDR as a complete word This double buffered operation allows a character to be shifted in serially while another character is already in the SCDR An advanced data recovery scheme distinguishes valid data from noise in the serial data stream The data input is selectively sampled to detect receive data and a majority voting circuit determines the value and integrity of each bit See Figure 7 2 7 5 Wakeup Feature The wakeup feature reduces SCI service overhead in multiple receiver systems Software for each receiver evaluates the first character of each message The receiver is placed in wakeup mode by writing a 1 to the RWU bit in the SCCR2 register While RWU is 1 all of the receiver related status flags RDRF IDLE OR NF and FE are inhibited cannot become set Although RWU can be cleared by a software write to SCCR2 to do so would be unusual Normally RWU is set by software and is cleared automatically with hardware Whenever a new message begins logic ale
145. O d QQ N O O N F O i000 N F O o 0008 000E 0016 0023 0080 0028 002B 002D 002E 002F 003B 0020 0001 B600 B7FF k k k K k k k k k k k k k k k K k k k k K k k k K k k k k K k k K k k k lt K K k k ck k k k kk BOOTLOADER FIRMWARE FOR 68HC711E9 21 Aug 89 K K k k k k k k k k k k k k k k k k K k k k k k k k K k k k K K k k K K k k ck K kk kk Features of this bootloader are Auto baud select between 7812 5 and 1200 8 MHz 0 512 byte variable length download Jump to EEPROM at B600 if 1st download byte 00 PROGRAM Utility subroutine to program EPROM UPLOAD Utility subroutine to dump memory to host Mask I D at 4 71E9 k K k k k k k k k k k k k k k k k k k k k k k k k k K k k k k K k k k K ck k k kk kk k Revision programmed into the EPROM was not transmitted for verify Also added to PROGRAM routine a skip Of bytes which were already programmed to the value desired This new version allows variable length download by quitting reception of characters when an idle Fixed bug in PROGRAM routine where the first byte of at least four character times occurs k k K k k k k k k k k k k k k k K k k k k k k K k k k K k k k k K k k k K ck k k k K kk k EQUATES FOR USE WITH INDEX OFFSET 1000 PORTD EQU 08 TCNT EQU SOE
146. OCKS 70 of Vpp STROBES 20 of Vp Tm 20 of Vpp SPEC SPEC NOTE 2 Vpp 0 8 VOLT 70 of Vpop INPUT d eon 04 VOLTS lt SPEC TIMING VI Do 70 of VoD OUTPUTS Vss 20 of TESTING 1 Full test loads are applied during all dc electrical tests and ac timing measurements 2 During ac timing measurements inputs are driven to 0 4 volts and Vpp 0 8 volts while timing measurements are taken at 20 and 70 of Vpp points Freescale Semiconductor Figure 10 1 Test Methods M68HC11E Family Data Sheet Rev 5 1 155 Electrical Characteristics 10 9 Control Timing 1 0 MHz 2 0 MHz 3 0 MHz h teristic 2 Symbol Unit Characteristic n Min Max Min Max Min Max Frequency of operation fo dc 1 0 dc 2 0 dc 3 0 MHz 100 E clock period tcvc 0 500 333 ns Crystal frequency fxTAL 40 8 0 120 MHz External oscillator frequency 4 fo dc 40 dc 8 0 12 0 MHz Processor control setup time 1 4 tcyc 50 ns tpcsu 300 175 133 ns Reset input pulse width To guarantee external reset vector PWrstL 8 8 8 Minimum input time be pre empted by internal reset 1 1 1 Mode programming setup time 2 2 2 Mode programming hold time 10 10 10 ns Interrupt pulse width IRQ edge sensitive mode 1
147. OL 0 INPUT SCK CPOL 1 y INPUT gt 2 SLAVE MSBOUT BIT6 O kO NIE MOSI 7 ws Note Not defined but normally MSB of character just received A SPI Slave Timing CPHA 0 SS INPUT AN SCK v 5 di lt 5 CPOL 0 xM m INPUT 4 m SCK 9 5 _ 1 Ke INPUT ca SEE SLAVE LSB OUT NOTE P du mm uem gt lt 0 0 N mud NIE X SLAVE MSBOUT BIT6 1 SLAVE LSB OUT eser 10 D MOSI N INPUT MSB IN BIT6 N LSB IN Note Not defined but normally LSB of character previously transmitted B SPI Slave Timing CPHA 1 Figure 11 15 SPI Timing Diagram Sheet 2 of 2 M68HC11E Family Data Sheet Rev 5 1 174 Freescale Semiconductor 10 19 EEPROM Characteristics EEPROM Characteristics 1 Temperature Range Unit isti ni Characteristic 40 to 85 C 40to 105 C 40 to 125 C Programming time lt 1 0 MHz RCO enabled 10 15 20 ms 1 0 to 2 0 MHz RCO disabled 20 Must use RCO Must use RCO 22 0 MHz or anytime RCO enabled 10 15 20 ima 2 Erase time 10 10 10 ris Byte row and bulk Write erase endurance 10 000 10 000 10 000 Cycles Data retention 10 10 10 Years 1 Vpp 5 0 1 0 Vss 0 Vdc TL to Ty 2 The RC oscillator RCO mus
148. ONVERT FOURTH CHANNEL UPDATE CHANNEL UPDATE CHANNEL UPDATE CHANNEL UPDATE 0 ADR1 32 ADR2 64 ADRS3 96 ADR4 128 CYCLES Figure 3 3 A D Conversion Sequence M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 59 Analog to Digital A D Converter 3 3 A D Converter Power Up and Clock Select Bit 7 of the OPTION register controls A D converter power up Clearing ADPU removes power from and disables the A D converter system Setting ADPU enables the A D converter system Stabilization of the analog bias voltages requires a delay of as much as 100 us after turning on the A D converter When the A D converter system is operating with the MCU E clock all switching and comparator operations are inherently synchronized to the main MCU clocks This allows the comparator output to be sampled at relatively quiet times during MCU clock cycles Since the internal RC oscillator is asynchronous to the MCU clock there is more error attributable to internal system clock noise A D converter accuracy is reduced slightly while the internal RC oscillator is being used CSEL 1 Address 1039 Bit 7 6 5 4 3 2 1 Bit 0 Read 1 1 1 1 ADPU CSEL IRQE piv CME cri Write Reset 0 0 0 1 0 0 0 0 1 Can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes Unimplemented Figure 3 4 System Configuration Options Register
149. OR Overrun Error Flag OR is set if a new character is received before a previously received character is read from SCDR Clear the OR flag by reading SCSR with OR set and then reading SCDR 0 No overrun 1 Overrun detected NF Noise Error Flag NF is set if majority sample logic detects anything other than a unanimous decision Clear NF by reading SCSR with NF set and then reading SCDR 0 Unanimous decision 1 Noise detected M68HC11E Family Data Sheet Rev 5 1 112 Freescale Semiconductor SCI Registers FE Framing Error Flag FE is set when a 0 is detected where a stop bit was expected Clear the FE flag by reading SCSR with FE set and then reading SCDR 0 Stop bit detected 1 Zero detected Bit 0 Unimplemented Always reads 0 7 7 5 Baud Rate Register Use this register to select different baud rates for the SCI system The SCP 1 0 SCP 2 0 in MC68HC 7 11E20 bits function as prescaler for the SCR 2 0 bits Together these five bits provide multiple baud rate combinations for a given crystal frequency Normally this register is written once during initialization The prescaler is set to its fastest rate by default out of reset and can be changed at any time Refer to Table 7 1 for normal baud rate selections Address 1028 Bit 7 6 5 4 3 2 1 Bit 0 Read Wm TCLR SCP2 SCP1 5 0 SCR2 SCR1 SCRO rite Reset 0 0 0 0 0 U U U U Unaffected Figure 7 7 Baud Rat
150. PROM address see memory map for each device LDAB 507 EELAT 1 EPGM 1 ERASE 1 STAB 103B Turn on high voltage JSR DLY10 Delay 10 ms CLR 103B Turn off high voltage and set to READ mode 2 5 1 4 EEPROM Row Erase This example shows how to perform a fast erase of large sections of EEPROM ROWE LDAB S0E ROW 1 ERASE 1 EELAT 1 STAB 103B Set to ROW erase mode STAB 0 X Write any data to any address in ROW LDAB 50 ROW 1 ERASE 1 EELAT 1 EPGM 1 STAB 103B Turn on high voltage JSR DLY10 Delay 10 ms CLR 103B Turn off high voltage and set to READ mode M68HC11E Family Data Sheet Rev 5 1 54 Freescale Semiconductor EEPROM 2 5 1 5 EEPROM Byte Erase This is an example of how to erase a single byte of EEPROM BYTEE LDAB 516 BYTE 1 ERASE 1 EELAT 1 STAB 103B Set to BYTE erase mode STAB 0 Write any to address to be erased LDAB 517 BYTE 1 ERASE 1 EELAT 1 EPGM 1 STAB 103B Turn on high voltage JSR DLY10 Delay 10 ms CLR 103B Turn off high voltage and set to READ mode 2 5 1 6 CONFIG Register Programming Because the CONFIG register is implemented with EEPROM cells use EEPROM procedures to erase and program this register The procedure for programming is the same as for programming a byte in the EEPROM array except that the CONFIG register address is used CONFIG can be programmed or erased including byte erase while the MCU is operating in any mode prov
151. PROM latches STAA 50 Store data to EPROM address LDAB 521 STAB 1036 Set EPGM bit with ELAT 1 to enable EPROM programming voltage JSR DLYEP Delay 2 4 ms CLR 1036 Turn off programming voltage and set to READ mode 2 4 2 Programming the EPROM with Downloaded Data When using this method the EPROM is programmed by software while in the special test or bootstrap modes User developed software can be uploaded through the SCI or a ROM resident EPROM programming utility can be used The 12 volt nominal programming voltage must be present on the XIRQ Vppzg pin To use the resident utility bootload a 3 byte program consisting of a single jump instruction to BFOO is the starting address of a resident EPROM programming utility The utility program sets the X and Y index registers to default values then receives programming data from an external host and puts it in EPROM The value in IX determines programming delay time The value in IY is a pointer to the first address in EPROM to be programmed default 0000 When the utility program is ready to receive programming data it sends the host the FF character Then it waits When the host sees the FF character the EPROM programming data is sent starting with the first location in the EPROM array After the last byte to be programmed is sent and the corresponding verification data is returned the programming operation is terminated by resetting the MCU For more informat
152. PU begins to service an interrupt the contents of the CPU registers are pushed onto the stack in the order shown in Table 5 5 After the CCR value is stacked the bit and the X bit if XIRQ is pending are set to inhibit further interrupts The interrupt vector for the highest priority pending source is fetched and execution continues at the address specified by the vector At the M68HC11E Family Data Sheet Rev 5 1 88 Freescale Semiconductor Interrupts end of the interrupt service routine the return from interrupt instruction is executed and the saved registers are pulled from the stack in reverse order so that normal program execution can resume Refer to Chapter 4 Central Processor Unit CPU Table 5 5 Stacking Order on Entry to Interrupts Memory Location CPU Registers SP PCL SP 1 PCH SP 2 IYL SP 3 IYH SP 4 IXL SP 5 IXH SP 6 ACCA SP 7 ACCB SP 8 CCR 5 5 2 Non Maskable Interrupt Request XIRQ Non maskable interrupts are useful because they can always interrupt CPU operations The most common use for such an interrupt is for serious system problems such as program runaway or power failure The XIRQ input is an updated version of the non maskable interrupt input of earlier MCUs Upon reset both the X bit and bit of the CCR are set to inhibit all maskable interrupts and XIRQ After minimum system initialization software can clear the X bit by a TAP instruction enablin
153. Port B can also be used in simple strobed output mode In this mode an output pulse appears at the STRB signal each time data is written to port B In expanded multiplexed operating modes all of the port B pins act as high order address output signals During each MCU cycle bits 15 8 of the address bus are output on the PB7 PBO pins The PORTB register is treated as an external address in expanded modes 1 4 14 Port C While in single chip operating modes all port C pins are general purpose pins Port C inputs be latched into an alternate PORTCL register by providing an input transition to the STRA signal Port C can also be used in handshake modes of parallel I O where the STRA input and STRB output act as handshake control lines When in expanded multiplexed modes all port C pins are configured as multiplexed address data signals During the address portion of each MCU cycle bits 7 0 of the address are output on the 7 pins During the data portion of each MCU cycle E high 7 are bidirectional data signals DATA7 DATAQ The direction of data at the port C pins is indicated by the RAN signal The CWOM control bit in the PIOC register disables the port C P channel output driver CWOM simultaneously affects all eight bits of port C Because the N channel driver is not affected by CWOM setting CWOM causes port C to become an open drain type output port suitable for wired OR operation In wired OR mo
154. R OUTPUT COMPARE 3 238 BFE6 000 FDB 100 36 TIMER OUTPUT COMPARE 2 239 BFE8 OODF FDB 100 33 TIMER OUTPUT COMPARE 1 240 BFEA OOE2 FDB 100 30 TIMER INPUT CAPTURE 3 241 BFEC 00 5 FDB 100 27 TIMER INPUT CAPTURE 2 242 BFEE 00 8 FDB 100 24 TIMER INPUT CAPTURE 1 243 BFFO OOEB FDB 100 21 REAL TIME INT 244 BFF2 OOEE FDB 100 18 IRQ 245 BFF4 00 1 FDB 100 15 XIRQ 246 BFF6 OOF4 FDB 100 12 SWI 247 BFF8 00F7 FDB 100 9 ILLEGAL OP CODE 248 BFFA OOFA FDB 100 6 COP FAIL 249 BFFC OOFD FDB 100 3 CLOCK MONITOR 250 BFFE BF54 FDB BEGIN RESET 251 C000 END Symbol Table Symbol Name Value Def Line Number Cross Reference BAUD 002B 00037 00160 00180 BAUDOK BF8A 00183 00178 BEGIN BF54 00155 00250 DELAYF 021B 00061 00163 DELAYS ODBO 00060 00181 DONEIT 47 00142 00124 B7FF 00050 EEPMSTR B600 00049 00175 ELAT 0020 00043 00125 00128 EPGM 0001 00044 00128 EPRMEND FFFF 00053 EPRMSTR 2000 00052 00206 M68HC11 Bootstrap Mode Rev 1 1 226 Freescale Semiconductor BF9B 00196 00189 NOTZERO BF7E 00176 00174 0080 00034 00136 00139 PORTD 0008 00029 00168 PPROG 003B 00041 00126 00129 PRGROUT BF13 00110 00074 PROGDEL 1068 00063 00205 PROGRAM BFOO 00074 RAMEND 01 00056 00156 00201 RAMSTR 0000 00055 00184 00207 SCCR2 002D 00038 00162 00167 SCDAT 002F 00040 00091 00118 SCSR 002E 00039 00090 00116 SPCR 0028 00036 00158 STAR BFAA 00204 00194 TCNT 000E 00030
155. R1 SPRO 0 0 0 0 0 1 U U SPIF WCOL MODF 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset TCLR SCP2 1 SCPO RCKB SCR2 SCR SCRO 0 0 0 0 0 U U U R8 T8 M WAKE 0 0 0 0 0 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 TDRE TC RDRF IDLE OR NF FE 1 1 0 0 0 0 0 0 ly in MC68HC 7 11E20 R7 T7 R6 T6 R5 T5 R4 T4 R3 T3 R2 T2 1 1 RO TO Indeterminate after reset SCAN MULT CD CC CB CA 0 0 Indeterminate after reset Unimplemented R Reserved U Unaffected Indeterminate after reset Figure 2 7 Register and Control Bit Assignments Sheet 4 of 6 M68HC11E Family Data Sheet Rev 5 1 37 Freescale Semiconductor Operating Modes and On Chip Memory Addr 1031 1032 1033 1034 1035 1036 1037 Register Name Analog to Digital Results Register 1 ADR1 See page 64 Analog to Digital Results Register 2 ADR2 See page 64 Analog to Digital Results Register 3 ADR3 See page 64 Analog to Digital Results Register 4 ADR4 See page 64 Block Protect Register BPROT See page 52 EPROM Programming Control Register EPROG See page 53 Reserved 1 MC68HC711E20 only 1038 1039 103A 103B 103C 103D 38 Reserved System Configuration Options Register OPTION See page 46 Arm Reset COP Timer Circuitry Register COPRST See page 81 EPROM and EEPROM Program ming Control Register PPROG See page 49
156. RAM is mapped to 0000 after reset It can be placed at any 4 Kbyte boundary x000 by writing an appropriate value to the RAM and I O map register INIT The 64 byte register block is mapped to 1000 after reset and also can be placed at any 4 Kbyte boundary x000 by writing an appropriate value to the INIT register If RAM and registers are mapped to the same boundary the first 64 bytes of RAM will be inaccessible Refer to Figure 2 7 which details the MCU register and control bit assignments Reset states shown are for single chip mode only 0000 x 512 BYTES RAM Y O1FF 1000 A A 1000 64 BYTE REGISTER BLOCK 103F 8600 Ex BFOO 8007 SPECIAL MODES INTERRUPT BFF _ BFFF VECTORS D000 NORMAL MODES 7 INTERRUPT e Y FFFF VECTORS EXPANDED BOOTSTRAP SPECIAL TEST Figure 2 2 Memory Map for MC68HC11E0 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 31 Operating Modes and On Chip Memory 32 0000 1000 B600 0000 FFFF 0000 0000 512 BYTES RAM EXT El Dee 1000 WZ 1000 n 64 BYTE REGISTER BLOCK 103F EXT EXT Y 8600 512 BYTES
157. SHIFTER EXISTING CONTROL RxD PDO SIGNAL SERIES BEING USED EXISTING RESISTOR AS INPUT DRIVER Figure 5 Preventing Driver Conflict TxD Pin The bootloader program uses the PD1 TxD pin to send verification data back to the host computer To minimize the possibility of conflicts with circuitry connected to this pin port D is configured for wire OR mode by the bootloader program during initialization Since the wire OR configuration prevents the pin from driving active high levels a pullup resistor to Vpp is needed if the TxD signal is used In systems where the PD1 TxD pin is normally used as a general purpose output there are no output driver conflicts It may be important to consider what the existing logic will do with the SCI serial data instead of the signals that would have been produced by the PD1 pin In systems where the PD1 pin is normally used as a general purpose input the driver circuit that drives the PD1 pin must be designed so that the PD1 TxD pin driver in the MCU can override this driver A simple series resistor between the driver and the PD1 pin can solve this problem The TxD pin can then be configured as an output and the series resistor will prevent direct conflict between the internal TxD driver and the external driver connected to PD1 through the series resistor Other The bootloader firmware sets the DWOM control bit which configures all port D pins for wire OR operation During the bootloading process all po
158. SS with SCK In this clock phase mode SS must go high between successive characters in an SPI message When CPHA 1 SS can be left low between successive SPI characters In cases where there is only one SPI slave MCU its SS line can be tied to Vas as long as only 1 clock mode is used 8 6 SPI System Errors Two system errors can be detected by the SPI system The first type of error arises in a multiple master system when more than one SPI device simultaneously tries to be a master This error is called a mode fault The second type of error write collision indicates that an attempt was made to write data to the SPDR while a transfer was in progress When the SPI system is configured as a master and the SS input line goes to active low a mode fault error has occurred usually because two devices have attempted to act as master at the same time In cases where more than one device is concurrently configured as a master there is a chance of contention between two pin drivers For push pull CMOS drivers this contention can cause permanent damage The mode fault mechanism attempts to protect the device by disabling the drivers The MSTR control bit in the SPCR and all four DDRD control bits associated with the SPI are cleared and an interrupt is generated subject to masking by the SPIE control bit and the I bit in the CCR Other precautions may need to be taken to prevent driver damage If two devices are made masters at the same tim
159. T 17 37 PB5 ADDR13 36 PB6 ADDR14 IRQ 0 19 35 PB7 ADDR15 PDO RxD 20 34 PAO IC3 PD1 TxD 21 PD2 MISO 22 23 PD4 SCK 24 PD5 SS 25 Vpp 26 PA7 PAI OC1 27 2 1 28 1 29 PA4 0C4 0C1 30 PA3 OC5 ICA4 OC1 31 PA2 IC1 PA1 IC2 Vppre applies only to devices with EPROM OTPROM Figure 1 2 Pin Assignments for 52 Pin PLCC and CLCC M68HC11E Family Data Sheet Rev 5 1 16 Freescale Semiconductor Pin Descriptions H PA1 IC2 2 1 1 PA3 OC5 IC4 0C1 PA4 0C4 0C1 5 1 6 2 1 m PA7 PAI OC1 m Vpp n PD5 SS r3 PD4 SCK n PD3 MOSI r 3PD2 MISO r3 PD1 TxD 59 58 57 56 54 53 64 63 62 52 51 50 H 79 c H PC7 ADDR7 DATA7 1 3 PC6 ADDR6 DATA6 1 3 PC5 ADDR5 DATA5 H PC4 ADDR4 DATA4 H PC3 ADDR3 DATA3 H PC2 ADDR2 DATA2 H PC1 ADDR1 DATA1 1 31 NC H PCO ADDRO DATAO H XTAL O0 woh M68HC11 E SERIES 17 18 19 20 25 27 28 30 31 uuguuuuasBuHdBdliuddlHultul Z 9 9 ZO QO ui 22 22 5 lt 2222055552582 TEZ lt gt lt 5825 a gt 1 applies only to devices with EPROM OTPROM Figure 1 3 Pin Assignments for 64 Pin QFP M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 17 General Des
160. TL register When this bit is set the A D system is configured to perform a conversion on each of four channels where each result register corresponds to one channel NOTE When the multiple channel continuous scan mode is used extra care is needed in the design of circuitry driving the A D inputs The charge on the capacitive DAC array before the sample time is related to the voltage on the previously converted channel A charge share situation exists between the internal DAC capacitance and the external circuit capacitance Although the amount of charge involved is small the rate at which it is repeated is every 64 us for an E clock of 2 MHz The RC charging rate of the external circuit must be balanced against this charge sharing effect to avoid errors in accuracy Refer to M68HC11 Reference Manual Freescale document order number M68HC11RM AD for further information CD CA Channel Selects D A Bits Refer to Table 3 2 When a multiple channel mode is selected MULT 1 the two least significant channel select bits CB and CA have no meaning and the CD and CC bits specify which group of four channels is to be converted Table 3 2 A D Converter Channel Selection Channel Select Control Bits esult in x Channel Signal if MULT 1 CD CC CB CA 0000 ANO ADR1 0001 AN1 ADR2 0010 AN2 0011 AN3 ADR4 0100 AN4 ADR1 0101 AN5 ADR2 0110 AN6 ADR3 0111 AN7 ADR4 10XX R
161. U is being held in reset with MODA and MODB at 0 it is configured for the PROG EPROM emulation mode and PB7 is the output enable signal for the EPROM data input output pins Pullup resistor R7 causes the port D pins including RxD and TxD to remain in the high impedance state so they do not interfere with the RxD and TxD pins of the master MCU as it comes out of reset As U3 leaves reset its mode pins select bootstrap mode so the bootloader firmware begins executing A break is sent out the TxD pin of U3 Pullup resistor R10 and resistor R9 cause the break character to be seen at the RxD pin of U3 The bootloader performs a jump to the start of EEPROM in the master MCU U3 and starts executing the duplicator program This sequence demonstrates how to use bootstrap mode to pass control to the start of EEPROM after reset The complete listing for the duplicator program in the EEPROM of the master MCU is provided in Listing 1 MCU to MCU Duplicator Program M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 205 Driving Boot Mode from Another M68HC11 COM 12 25V M68HC11EVBU E MC E E JE E E E C E EC QE E E C EO C QE E E QC EE C EE C C EC EC QE E E QC EC KC QE E E QC E EC QE E C EC Eo C EE E C Eo KC QE e E EC ee E Qe Ke QE e Kn e Kn e Kn en nu nn nn rrr Drs PREWIRED AREA PES WIRE WRAP AREA z z P4 1 4 O 100 z z R14 C18 OFF 0
162. WITH SAMPLE AND HOLD SUCCESSIVE APPROXIMATION REGISTER AND CONTROL RESULT lt VRH lt Vni AA MULT 72 O O O ADCTL A D CONTROL YYYYYY INTERNAL DATA BUS RESULT REGISTER INTERFACE ADR1 A D RESULT 1 ADR2 A D RESULT 2 ADR3 A D RESULT 3 ADR4 A D RESULT 4 Figure 3 1 A D Converter Block Diagram DIFFUSION POLY COUPLER 20 12V 84 2pF 07 07 20 pF 400 nA DAC DUMMY N CHANNEL JUNCTION CAPACITANCE OUTPUT DEVICE LEAKAGE INPUT 4 PROTECTION DEVICE v VAL THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12 CYCLE SAMPLE TIME M68HC11E Family Data Sheet Rev 5 1 Figure 3 2 Electrical Model of an A D Input Pin Sample Mode Freescale Semiconductor Overview 3 2 3 Digital Control All A D converter operations are controlled by bits in register ADCTL In addition to selecting the analog input to be converted ADCTL bits indicate conversion status and control whether single or continuous conversions are performed Finally the ADCTL bits determine whether conversions are performed on single or multiple channels 3 2 4 Result Registers Four 8 bit registers ADR 4 1 store conversion results Each of these registers can be accessed by the processor in the
163. Wait recovery startup time twrs 4 4 lcvc 4 27 pulse accumulator input 1020 520 E T 1 3 0 to 5 5 Vss 0 Vdc TA T to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 RESET is recognized during the first clock cycle it is held low Internal circuitry then drives the pin low for four clock cycles releases the pin and samples the pin level two cycles later to determine the source of the interrupt Refer to Chapter 5 Resets and Interrupts for further detail PA 0 R4 N PA 2 0 N 9 Notes 1 Rising edge sensitive input 2 Falling edge sensitive input 3 Maximum pulse accumulator clocking rate is E clock frequency divided by 2 Figure 10 2 Timer Inputs M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 157 891 Jojonpuooluleg 4 6 3LL9H89IN 4064 MODA MODB ADDRESS lt Gm FFFE X FFFE X rere X rere rere X rere X FFFE X FFFE X rene X NEW Figure 10 3 POR External Reset Timing Diagram Ssonsuo 2eJeu e9293 40jonpuooluJeg ejeoseaJ4 est 4S 4 3LL9H99IN INTERNAL CLOCKS RQ _ lt PWina IRQ or XIRQ lt tstoppetay E E por EE STOP STOP ADDRESS ADDR 1 5 STOP STOP ADDRESS rg Notes STOP L Re
164. X INH 3A 3 ABY Add B to Y IY 00 B 2 IY INH 18 3A 4 Add with Carry A M C gt A A IMM 89 11 2 to A A DIR 99 3 A EXT B9 hh 11 4 A IND X AQ ff 4 A IND Y 18 9 5 Add with Carry B M C gt B B IMM C9 11 2 to B B DIR 09 3 B EXT F9 hh 11 4 B IND X E9 4 B IND Y 18 E9 5 ADDA Add Memory to A M gt A A IMM 8B jii 2 A A A A A DIR 9B 3 A EXT hh 11 4 A IND X AB 4 A IND Y 18 AB 5 ADDB opr Add Memory to B M gt B B IMM CB 2 A A A B B DIR DB 3 B EXT FB hh 11 4 B IND X EB 4 B IND Y 18 EB 5 ADDD Add 16 Bitto D D M M 1 gt D IMM C3 jj kk 4 A A DIR 5 EXT F3 hh 11 6 IND X 6 IND Y 18 ES ff 7 ANDA opr AND A with A M A A IMM 84 14 2 Memory A DIR 94 3 A EXT B4 hh 11 4 A IND X 4 ff 4 A IND Y 18 4 5 ANDB AND B with BeM gt B B IMM C4 11 2 A Memory B DIR 04 3 B EXT F4 hh 11 4 B IND X E4 4 B IND Y 18 E4 5 ASL Arithmetic Shift EXT 78 hh 11 6 4 A A Left os IND X 68 6 bO IND Y 18 68 ff 7 ASLA Arithmetic Shift A INH 48 2 Left A CIE 1 0 C b7 b0 ASLB Arithmetic Shift B INH 58 2 Left B De 0 C b7 50 ASLD Arithmetic Shift INH 05 3 A Left D DRCILIDAULIDAO C b0b7 B b0
165. a Sheet Rev 5 1 Freescale Semiconductor 103 rr Parallel Input Output Ports M68HC11E Family Data Sheet Rev 5 1 104 Freescale Semiconductor Chapter 7 Serial Communications Interface SCI 7 1 Introduction The serial communications interface SCI is a universal asynchronous receiver transmitter UART one of two independent serial input output subsystems in the M68HC11 E series of microcontrollers It has a standard non return to zero NRZ format one start bit eight or nine data bits and one stop bit Several baud rates are available The SCI transmitter and receiver are independent but use the same data format and bit rate All members of the E series contain the same SCI with one exception The SCI system in the MC68HC11E20 and MC68HC711E20 MCUs have an enhanced SCI baud rate generator A divide by 39 stage has been added that is enabled by an extra bit in the BAUD register This increases the available SCI baud rate selections Refer to Figure 7 8 and 7 7 5 Baud Rate Register 7 2 Data Format The serial data format requires these conditions 1 An idle line in the high state before transmission or reception of a message 2 A start bit logic transmitted or received that indicates the start of each character 3 Data that is transmitted and received least significant bit LSB first 4 A stop bit logic 1 used to indicate the end of a frame A frame consists of a start bit a
166. a file and translating it to binary can be slow depending on the personal computer and the programming language used for the translation One strategy that can be used to overcome this problem is to translate the file into binary and store it into a RAM array before starting the download process Data can then be read and downloaded without the translation or file read delays The end of download mechanism goes into effect when the initial FF is received to set the baud rate Any amount of time may pass between reset and when the FF is sent to start the download process EPROM OTP Versions of M68HC11 Have an EPROM Emulation Mode The conditions that configure the MCU for EPROM emulation mode are essentially the same as those for resetting the MCU in bootstrap mode While RESET is low and mode select pins are configured for bootstrap mode low the MCU is configured for EPROM emulation mode The port pins that are used for EPROM data lines may be inputs or outputs depending on the pin that is emulating the EPROM output enable pin OE To make these data pins appear as high impedance inputs as they would on a non EPROM part in reset connect the PB7 OE pin to a pullup resistor M68HC11 Bootstrap Mode Rev 1 1 220 Freescale Semiconductor Boot ROM Variations Bootloading a Program to Performa ROM Checksum The bootloader ROM must be turned off before performing the checksum program To remove the boot ROM from the memory map cle
167. age devices available 3 0 5 5 Vdc 0 256 512 or 768 bytes of on chip RAM data retained during standby 0 12 or 20 Kbytes of on chip ROM or EPROM 0 512 or 2048 bytes of on chip EEPROM with block protect for security 2048 bytes of EEPROM with selectable base address the MC68HC81 1E2 Asynchronous non return to zero NRZ serial communications interface SCI Additional baud rates available on MC68HC 7 11E20 Synchronous serial peripheral interface SPI 8 channel 8 bit analog to digital A D converter 16 bit timer system Three input capture IC channels Four output compare OC channels One additional channel selectable as fourth IC or fifth OC 8 bit pulse accumulator Real time interrupt circuit M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 13 General Description Computer operating properly COP watchdog system 38 general purpose input output I O pins 16 bidirectional I O pins 11 input only pins 11 output only pins Several packaging options 52 plastic leaded chip carrier PLCC 52 windowed ceramic leaded chip carrier CLCC 52 pin plastic thin quad flat pack 10 mm x 10 mm TQFP 64 quad flat pack 48 plastic dual in line package DIP MC68HC811E2 only 56 plastic shrink dual in line package 070 inch lead spacing SDIP 1 3 Structure See Figure 1 1 for a functional diagram of the E seri
168. al read or program mode 1 Erase mode EELAT EEPROM Latch Control Bit 0 EEPROM address and data bus configured for normal reads and cannot be programmed 1 EEPROM address and data bus configured for programming or erasing and cannot be read M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 53 Operating Modes and On Chip Memory EPGM EPROM OTPROM EEPROM Programming Voltage Enable Bit 0 Programming voltage to EEPROM array switched off 1 Programming voltage to EEPROM array switched on During EEPROM programming the ROW and BYTE bits of PPROG are not used If the frequency of the E clock is 1 MHz or less set the CSEL bit in the OPTION register Recall that Os must be erased by a separate erase operation before programming The following examples of how to program an EEPROM byte assume that the appropriate bits in BPROT are cleared PROG LDAB 502 EELAT 1 STAB 103B Set EELAT bit STAA SXXXX Store data to EEPROM address for valid EEPROM address see memory map for each device LDAB 503 EELAT 1 1 103B Turn on programming voltage JSR DLY10 Delay 10 ms CLR 103B Turn off high voltage and set to READ mode 2 5 1 3 EEPROM Bulk Erase This is an example of how to bulk erase the entire EEPROM The CONFIG register is not affected in this example BULKE LDAB 506 EELAT 1 ERASE 1 STAB 103B Set to BULK erase mode STAA SXXXX Store data to any EEPROM address for valid EE
169. ample hold Input capacitance during sample E __ capacitance PE 7 0 20 typical pF Input leakage on A D pins Input leakage PE 7 0 400 nA VRH 1 0 1 Vpp 3 0 Vdc to 5 5 Vdc Vss 0 Ta T to Ty 750 kHz lt E lt 2 0 MHz unless otherwise noted 2 Source impedances greater than 10 affect accuracy adversely because of input leakage M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 167 Electrical Characteristics 10 15 Expansion Bus Timing Characteristics 1 0 MHz 2 0 MHz 3 0 MHz Num istic Symbol Unit Charactenstig y Min Max Min Max Min Max Frequency of operation E clock frequency fo dc 1 0 dc 2 0 3 0 MHz 1 Cycle time 1000 500 333 ns 2 Pulse width E low PWg 1 2 23 ns 477 227 146 ns 3 Pulse width E high 1 2 tcyc 28 ns PWg 472 222 141 ns 4a Eand AS rise time t 20 20 20 ns 4b E and fall time lr 20 20 15 ns 9 Address hold time 9 1 8 tcyc 29 5 ns tay 95 5 33 26 ns 44 Non multiplexed address valid time to E rise t 281 5 54 tay tasp 80 ns d ix 17 Read data setup time tpsR 30 30 30 ns 18 Read data hold time max typ tpHR 0 145 5
170. ams to be downloaded IBM is a registered trademark of International Business Machines Macintosh is a registered trademark of Apple Computers Inc M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 211 Driving Boot Mode from a Personal Computer 47K NORMAL EVBU OPERATION TO 8 XIR PROGRAM PPE EPROM JUMPER 412 25 V PROGRAMMING POWER COMMON Figure 8 PC to MCU Programming Circuit Lines 50 95 read in the small bootloader from DATA statements at the end of the listing The source code for this bootloader is presented in the DATA statements The bootloaded code makes port C bit 0 low initializes the X and Y registers for use by the EPROM programming utility routine contained in the boot ROM and then jumps to that routine The hexadecimal values read in from the DATA statements are converted to binary values by a subroutine The binary values are then saved as one string The next long section of code lines 97 1250 reads the S records from an external disk file in this case BUF34 S19 converts them to integer and saves them in an array The techniques used in this section show how to convert ASCII S records to binary form that can be sent bootloaded to an M68HC11 This S record translator only looks for the S1 records that contain the actual object code All other S record types are ignored When an S1 record is found lines 1000 1024 the
171. ap mode to prevent interference with the user s normal memory space The enable for this ROM is controlled by the read boot ROM RBOOT control bit in the highest priority interrupt HPRIO register The RBOOT bit can be written by software whenever the MCU is in special test or special bootstrap modes when the MCU is in normal modes RBOOT reverts to 0 and becomes a read only bit All other logic in the MCU would be present whether or not there was a bootstrap mode Figure 1 shows the composite memory map of the MC68HC711E9 in its four basic modes of operation including bootstrap mode The active mode is determined by the mode A MDA and special mode SMOD control bits in the HPRIO control register These control bits are in turn controlled by the state of the mode A MODA and mode B MODB pins during reset Table 1 shows the relationship between the state of these pins during reset the selected mode and the state of the MDA SMOD and RBOOT control bits Refer to the composite memory map and information in Table 1 for the following discussion The MDA control bit is determined by the state of the MODA pin as the MCU leaves reset MDA selects between single chip and expanded operating modes When is 0 a single chip mode is selected either normal single chip mode or special bootstrap mode When MDA is 1 an expanded mode is selected either normal expanded mode or special test mode The SMOD control bit is determined by the inverted stat
172. ar the RBOOT bit in the HPRIO register This is normally a write protected bit that is O but in bootstrap mode it is reset to 1 and can be written If the boot ROM is not disabled the checksum routine will read the contents of the boot ROM rather than the user s mask ROM or EPROM at the same addresses Inherent Delays Caused by Double Buffering of SCI Data This problem is troublesome in cases where one MCU is bootloading to another MCU Because of transmitter double buffering there may be one character in the serial shifter as a new character is written into the transmit data register In cases such as downloading in which this 2 character pipeline is kept full a 2 character time delay occurs between when a character is written to the transmit data register and when that character finishes transmitting A little more than one more character time delay occurs between the target MCU receiving the character and echoing it back If the master MCU waits for the echo of each downloaded character before sending the next one the download process takes about twice as long as it would if transmission is treated as a separate process or if verify data is ignored Boot ROM Variations Different versions of the M68HC11 have different versions of the bootstrap ROM program Table 3 summarizes the features of the boot ROMs in 16 members of the M68HC11 Family The boot ROMs for the MC68HC11F1 the MC68HC711K4 and the MC68HC11K4 allow additional choices of baud
173. are register that represents the time the leading edge of the pulse is to occur The output compare circuit is configured to set the appropriate output either high or low depending on the polarity of the pulse being produced After a match occurs the output compare register is reprogrammed to change the output pin back to its inactive level at the next match A value representing the width of the pulse is added to the original value and then written to the output compare register Because the pin state changes occur at specific values of the free running counter the pulse width can be controlled accurately at the resolution of the free running counter independent of software latencies To generate an output signal of a specific frequency and duty cycle repeat this pulse generating procedure The five 16 bit read write output compare registers are TOC1 TOC2 TOC3 and TOC4 and the TI4 O5 TI4 O5 functions under software control as either IC4 or OC5 Each of the OC registers is set to F FFF on reset A value written to an OC register is compared to the free running counter value during each E clock cycle If a match is found the particular output compare flag is set in timer interrupt flag register 1 TFLG1 If that particular interrupt is enabled in the timer interrupt mask register 1 TMSK1 an interrupt is generated In addition to an interrupt a specified action can be initiated at one or more timer output pins For OC 5 2 the pin action is
174. ary for both EEPROM and EPROM OTPROM programming b ELAT and EELAT are mutually exclusive and cannot both equal 1 BYTE Byte Other EEPROM Erase Mode Bit Refer to 2 5 EEPROM ROW EEPROM Erase Mode Bit Refer to 2 5 EEPROM ERASE Erase Mode Select Bit Refer to 2 5 EEPROM EELAT EEPROM Latch Control Bit Refer to 2 5 EEPROM EPGM EPROM OTPROM EEPROM Programming Voltage Enable Bit EPGM can be read any time and can be written only when ELAT 1 for EPROM OTPROM programming or when EELAT 1 for EEPROM programming 0 Programming voltage to EPROM OTPROM EEPROM array disconnected 1 Programming voltage to EPROM OTPROM EEPROM array connected M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 49 Operating Modes and On Chip Memory Address 1036 Bit 7 6 5 4 3 2 1 Bit 0 Read ELAT EXCOL EXROW TO PGM Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 2 15 MC68HC711E20 EPROM Programming Control Register EPROG MBE Multiple Byte Programming Enable Bit When multiple byte programming is enabled address bit 5 is considered a don t care so that bytes with address bit 5 0 and address bit 5 1 both get programmed MBE can be read in any mode and always reads 0 in normal modes MBE can be written only in special modes 0 EPROM array configured for normal programming 1 Program two bytes with the same data Bit 6 Unimplemen
175. at short across J8 and J9 must be cut on the solder side of the printed circuit board to disconnect the normal SCI connections to the RS232 level translator U4 of the EVBU The J8 and J9 connections can be restored easily at a later time by installing fabricated jumpers on the component side of the board A fabricated jumper must be installed across J3 to configure the master MCU for bootstrap mode MC68HC711E9 is first programmed by other means with a desired 12 Kbyte program in its EPROM and a small duplicator program in its EEPROM Alternately the ROM program in an MC68HC11E9 can be copied into the EPROM of a target MC68HC711E9 by programming only the duplicator program into the EEPROM of the master MC68HC11E9 The master MCU is installed in the EVBU at socket U3 A blank MC68HC711E9 to be programmed is placed in the socket in the wire wrap area of the EVBU U6 With the Vpp power switch off power is applied to the EVBU system As power is applied to the EVBU the master MCU U3 comes out of reset in bootstrap mode Target MCU U6 is held in reset by the PB7 output of master MCU U3 The PB7 output of U3 is forced to 0 when U3 is reset The master MCU will later release the reset signal to the target MCU under software control The RxD and TxD pins of the target MCU U6 are high impedance inputs while U6 is in reset so they will not affect the TxD and RxD signals of the master MCU U3 while U3 is coming out of reset Since the target MC
176. atchdog timer See Table 5 1 for specific timeout settings M68HC11E Family Data Sheet Rev 5 1 82 Freescale Semiconductor Effects of Reset 5 2 6 Configuration Control Register Address 103F Bit 7 6 5 4 3 2 1 Bit 0 Read T EE3 EE2 EE1 EEO NOSEC NOCOP ROMON EEON rite Reset 0 0 0 0 1 1 1 1 Figure 5 3 Configuration Control Register CONFIG EE 3 0 EEPROM Mapping Bits EE 3 0 apply only to MC68HC811E2 Refer to Chapter 2 Operating Modes and On Chip Memory NOSEC Security Mode Disable Bit Refer to Chapter 2 Operating Modes and On Chip Memory NOCOP COP System Disable Bit 0 COP enabled forces reset on timeout 1 COP disabled does not force reset on timeout ROMON ROM EPROM Enable Bit Refer to Chapter 2 Operating Modes and On Chip Memory EEON EEPROM Enable Bit Refer to Chapter 2 Operating Modes and On Chip Memory 5 3 Effects of Reset When a reset condition is recognized the internal registers and control bits are forced to an initial state Depending on the cause of the reset and the operating mode the reset vector can be fetched from any of six possible locations Refer to Table 5 2 Table 5 2 Reset Cause Reset Vector and Operating Mode Causeof Reset Normal Mode Special Test Vector or Bootstrap POR or RESET pin FFFE FFFF BFFE BFFF Clock monitor failure FFFC FFFD BFFC BFFD COP Watchdog Timeout FFFA FFFB BFFA BFFB
177. ating modes After reset writing SMOD and MDA in special modes causes the MCU to change operating modes Refer to the description of HPRIO register in Chapter 2 Operating Modes and On Chip Memory for a detailed description of SMOD and MDA The DLY control bit is set to specify that an oscillator startup delay is imposed upon recovery from stop mode The clock monitor system is disabled because CME is cleared 5 4 Reset and Interrupt Priority Resets and interrupts have a hardware priority that determines which reset or interrupt is serviced first when simultaneous requests occur Any maskable interrupt can be given priority over other maskable interrupts The first six interrupt sources are not maskable The priority arrangement for these sources is 1 POR or RESET pin Clock monitor reset COP watchdog reset XIRQ interrupt Illegal opcode interrupt Software interrupt SWI maskable interrupt sources have this priority arrangement IRQ Real time interrupt Timer input capture 1 Timer input capture 2 Timer input capture 3 Timer output compare 1 Timer output compare 2 Timer output compare 3 ONAARWNAT APN 9 Timer output compare 4 10 Timer input capture 4 output compare 5 11 Timer overflow 12 Pulse accumulator overflow 13 Pulse accumulator input edge 14 SPI transfer complete 15 SCI system refer to Figure 5 7 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 85 Resets and Interrupts Any one of these interrup
178. bers in the lower half to help the reader relate the three parts of the figure The shaded area 1 refers to the software and hardware latency in the MCU leading to the transmission of a character in this case the FF The shaded area 2 refers to a similar latency in the host computer in this case leading to the transmission of the first data character to the MCU The overall operation begins when the MCU sends the first character FF to the host computer indicating that it is ready for the first data character The host computer sends the first data byte 3 and enters its main loop The second data character is sent 4 and the host then waits 5 for the first verify byte to come back from the MCU M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 201 EPROM Programming Utility INITIALIZE X PROGRAM TIME Y FIRST ADDRESS BF00 PROGRAM YES PROGRAM BYTE 10 13 POINT TO NEXT LOCATION TO BE PROGRAMMED PROGRAM Utility in MCU DrverProgganinHOST 1 8 SEND ES READY SEND FIRST DATA BYTE 3I e DATA LOOP mmu MORE DATA TO SEND ANY DATA RECEIVED YES READ PROGRAMMED DATA PEL EN AND SEND TO VERIFY 14 VERIFY M rc HOST NORMALLY WAITS FOR FF FROM MCU BEFORE SENDING DATA FOR EPROM PROGRAMMING SEND NEXT DATA 4 6 INDICATE ERROR VERIFY DATA CORRECT MORE TO VERIFY PROGRAM
179. c dio callo mY ga NOD IO NE COO 62 69 00 LO xt C2 CV c O Q LO TONY 23333588 23252315 555825 22222222 54555555 GE 555355425 oo oa ra LL LI LL LL LI 2 2 20 lt lt lt lt lt lt 5 ED Sow lt CO 16 c5 ci m CC CC CC CC CC dp aaaaaaaa 2229 2 a OOOOO0OQ00 masa a mmm DEVICE RAM ROM EPROM EEPROM MC68HC11E0 512 MC68HC11E1 512 512 MC68HC11E9 512 12K 512 MC68HC711E9 512 12K 512 MC68HC11E20 768 20K 512 MC68HC711E20 768 20K 512 MC68HC811E2 256 2048 Vppe applies only to devices with EPROM OTPROM Figure 1 1 M68HC11 E Series Block Diagram M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 15 General Description 7 STRB R W 4L STRA AS MODA LIR 2 MODB Vsray 1101 ss 50 PE7 AN7 49 PE3 AN3 48 PEG ANG 47 PE2 AN2 46 5 45 PET AN1 44 PE4 AN4 43 PEO ANO PCO ADDRO DATAO 9 PC1 ADDR1 DATA1 10 PC2 ADDR2 DATA2 11 PC3 ADDR3 DATAS 12 42 PBO ADDR8 PCA ADDRA DATAM 13 41 PB1 ADDR9 PC5 ADDR5 DATAS 14 M68HC11 E SERIES 40 PB2 ADDR10 PC6 ADDR6 DATAe 15 39 PB3 ADDR11 PC7 ADDR7 DATA7 16 38 PB4 ADDR12 RESE
180. cale Semiconductor 153 Electrical Characteristics 10 8 MC68L11E9 E20 Supply Currents and Power Dissipation Characteristic Symbol 1 MHz 2 MHz Unit Run maximum total supply current Single chip mode Vpp 5 5 V 8 15 Vpp 3 0 V 4 8 mA Expanded multiplexed mode Vpp 5 5 V 14 27 Vpp 5 5 V 7 14 Wait maximum total supply current all peripheral functions shut down Single chip mode Vpp 5 5 V Vpp 3 0 V 1 5 3 En Expanded multiplexed mode Vpp 5 5 V 5 10 Vpp 3 0 V 2 5 5 Stop maximum total supply current Single chip mode no clocks 5 5 V Sipp 50 50 HA Vpp 3 0 V 25 25 Maximum power dissipation Single chip mode 2 MHz 44 85 3 MHz Pp 12 24 mW Expanded multiplexed mode 2 MHz 77 150 3 MHz 21 42 1 Vpp 3 0 to 5 5 Vss 0 Ta T to Ty unless otherwise noted 2 EXTAL is driven with a square wave and tcyc 500 ns for 2 MHz rating 333 ns for 3 MHz rating Vy lt 0 2 V no dc loads M68HC11E Family Data Sheet Rev 5 1 154 Freescale Semiconductor MC68L11E9 E20 Supply Currents and Power Dissipation CLOCKS Vpp 0 8 VOLTS STROBES 0 4 VOLTS 0 4 VOLTS 5 7Vss NOM gt 70 of Vpp INPUTS 20 of Vpp lt NOMINAL TIMING Vpp Vpp 0 8 Volts OUTPUTS 04 Volt Vss PUE DC TESTING 4M CL
181. ccurred Coupled with the four high order bits of TMSK2 the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven system Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position Address 1025 Bit 7 6 5 4 3 2 1 Bit 0 Read RTIF PAOVF PAIF Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 20 Timer Interrupt Flag 2 Register TFLG2 Clear flags by writing a 1 to the corresponding bit position s TOF Timer Overflow Interrupt Flag Set when TCNT changes from FFFF to 0000 RTIF Real Time Periodic Interrupt Flag Refer to 9 5 Real Time Interrupt RTI PAOVF Pulse Accumulator Overflow Interrupt Flag Refer to 9 7 Pulse Accumulator PAIF Pulse Accumulator Input Edge Interrupt Flag Refer to 9 7 Pulse Accumulator Bits 3 0 Unimplemented Always read 0 9 5 Real Time Interrupt RTI The real time interrupt RTI feature used to generate hardware interrupts at a fixed periodic rate is controlled and configured by two bits RTR1 and RTRO in the pulse accumulator control PACTL register The RTII bit the TMSK2 register enables the interrupt capability The four different rates available are a product of the MCU oscillator frequency and the value of bits RTR 1 0 Refer to Table 9 5 which shows the periodic real time interrupt rates Table 9 5 RTI Rates RTR 1 0 E 3MHz E 2MHz E 1MHz E XM
182. ce dd diea dd dice wa dolar dada d fra ae d 79 Fr MW 79 Power On Reset POR 66055046456 79 Enema Ressl RESET HERE OE edd e dac RE qasi ua 80 Computer Operating Properly COP Reset 80 ece 81 System Configuration Options Register 82 Configuration Control Register iss CHOR ORC ERROR ER 83 E SS PRSE cac Pd E KAMP 83 Central Processor Unit CPU eb Cr EORR RR d 83 kemay NED eri erre 84 i err 84 Reak Time NERO RT h yd rdg debel dodge RO OR o ede del RO ER 84 Pulse 84 Computer Operating Properly 84 Serial Communications Interface 6 1 84 Serial Peripheral Interface SPI 84 Analog to Digital A D Converter 85 ereen ara rr a PE ECT pia LER 85 Reseland terrupl PHONY EER 85 Highest Priority Interrupt and Miscellaneous Register 86 E E E E T Gee oe A eee E ee ek T 87 Interrupt Recognition and Register 0
183. cess RAM locations using a 1 byte address operand saving program memory space and execution time depending on the application RAM contents can be preserved during periods of processor inactivity by two methods both of which reduce power consumption They are 1 In the software based stop mode the clocks are stopped while Vpp powers the MCU Because power supply current is directly related to operating frequency in CMOS integrated circuits only a very small amount of leakage exists when the clocks are stopped 2 Inthe second method the MODB V stegy can supply RAM power from a battery backup or from a second power supply Figure 2 8 shows a typical standby voltage circuit for a standard 5 volt device Adjustments to the circuit must be made for devices that operate at lower voltages Using the MODB Vsrpy may require external hardware but can be justified when a significant amount of external circuitry is operating from Vpp If Vstpy is used to maintain RAM contents reset must be held low whenever Vpp is below normal operating level Refer to Chapter 5 Resets and Interrupts M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 39 Operating Modes and On Chip Memory Vpp TO MODB Vsrgy OF M68HC11 4 8 V NiCd Figure 2 8 RAM Standby Connections The bootloader program is contained in the internal bootstrap ROM This ROM which appears as internal memory space at locations BFOO BFFF is
184. character of eight or nine data bits and a stop bit 5 A break defined as the transmission or reception of a logic 0 for some multiple number of frames Selection of the word length is controlled by the M bit of SCI control register SCCR1 7 3 Transmit Operation The SCI transmitter includes a parallel transmit data register SCDR and a serial shift register The contents of the serial shift register can be written only through the SCDR This double buffered operation allows a character to be shifted out serially while another character is waiting in the SCDR to be transferred into the serial shift register The output of the serial shift register is applied to TxD as long as transmission is in progress or the transmit enable TE bit of serial communication control register 2 SCCR2 is set The block diagram Figure 7 1 shows the transmit serial shift register and the buffer logic at the top of the figure M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 105 Serial Communications Interface SCI TRANSMITTER BAUD RATE SCDR Tx BUFFER CLOCK 10 11 BIT Tx SHIFT REGISTER SEE NOTE PIN BUFFER TxD WRITE ONLY 8 FORCE PIN DIRECTION OUT TRANSMITTER CONTROL LOGIC 8 ejr 5 S SCSR INTERRUPT STATUS 8 ac E SCCR2 SCI CONTROL 2 SHIFT ENABLE JAM ENABLE TRANSFER Tx BUFFER PREAMBLE JAM 1s TDRE DRF IDLE SCCR1 SCI CO
185. cillator circuit are specified by the crystal manufacturer and should include all stray layout capacitances M68HC11E Family Data Sheet Rev 5 1 22 Freescale Semiconductor Pin Descriptions EXTAL T 10 MQ 4xE MCU E CRYSTAL XTAL 4 Figure 1 9 Common Parallel Resonant Crystal Connections 4xE EXTAL lt CMOS COMPATIBLE EXTERNAL OSCILLATOR MCU XTAL NC Figure 1 10 External Oscillator Connections 1 4 4 E Clock Output E E is the output connection for the internally generated E clock The signal from E is used as a timing reference The frequency of the E clock output is one fourth that of the input frequency at the XTAL and EXTAL pins When E clock output is low an internal process is taking place When it is high data is being accessed All clocks including the E clock are halted when the is in stop mode To reduce emissions the E clock output of most E series devices can be disabled while operating in single chip modes The E clock signal is always enabled the MC68HC81 1E2 1 4 5 Interrupt Request IRQ The IRQ input provides a means of applying asynchronous interrupt requests to the MCU Either negative edge sensitive triggering or level sensitive triggering is program selectable OPTION register IRQ is always configured to level sensitive triggering at reset When using IRQ in a level sensitive wired OR configuration connect an external pullup resistor typically 4 7
186. control bits select an additional division factor Refer to Table 9 5 9 6 Computer Operating Properly COP Watchdog Function The clocking chain for the COP function tapped off of the main timer divider chain is only superficially related to the main timer system The CR 1 0 bits in the OPTION register and the bit in the CONFIG register determine the status of the COP function One additional register COPRST is used to arm and clear the COP watchdog reset system Refer to Chapter 5 Resets and Interrupts for a more detailed discussion of the COP function 9 7 Pulse Accumulator The M68HC11 Family of MCUs has 8 bit counter that can be configured to operate either as a simple event counter or for gated time accumulation depending on the state of the PAMOD bit in the PACTL register Refer to the pulse accumulator block diagram Figure 9 24 In the event counting mode the 8 bit counter is clocked to increasing values by an external pin The maximum clocking rate for the external event counting mode is the E clock divided by two In gated time accumulation mode a free running E clock divide by 64 signal drives the 8 bit counter but only while the external PAI pin is activated Refer to Table 9 6 The pulse accumulator counter can be read or written at any time Table 9 6 Pulse Accumulator Timing 4 E Clock Cycle Time 64 x 4 0 MHz 1 MHz 1000 ns 64 us 16 384 ms 8 0 MHz 2 MHz 500 ns 32 us 8 192 ms 12 0 MHz 3 MHz 3
187. controlled by pairs of bits OMx and OLx in the TCTL1 register The output action is taken on each successful compare regardless of whether or not the OCxF flag in the TFLG1 register was previously cleared M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 133 Timing Systems is different from the other output compares in that a successful OC1 compare can affect any or all five of the OC pins The OC1 output action taken when a match is found is controlled by two 8 bit registers with three bits unimplemented the output compare 1 mask register OC1M and the output compare 1 data register OC1D OC1M specifies which port A outputs are to be used and OC1D specifies what data is placed on these port pins 9 4 1 Timer Output Compare Registers All output compare registers are 16 bit read write Each is initialized to FFFF at reset If an output compare register is not used for an output compare function it can be used as a storage location A write to the high order byte of an output compare register pair inhibits the output compare function for one bus cycle This inhibition prevents inappropriate subsequent comparisons Coherency requires a complete 16 bit read or write However if coherency is not needed byte accesses can be used For output compare functions write a comparison value to output compare registers 1 4 and TI4 O5 When TCNT value matches the comparison value specified pin actions occur Regis
188. cription 18 PB7 ADDR15 PB6 ADDR14 ci PB2 ADDR10 cd PB1 ADDR9 PBO ADDRB r t PEO ANO i 1 PET AN1 car 12 PES AN5 13 n PA1 1C2 PA2 IC1 H PA3 0C5 IC4 0C1 rPA4 OC4 OC1 1 6 2 1 H PAT PAI OC1 lt _ r3 PD5 SS H PD4 SCK r PD3 MOSI H PD2 MISO H PD1 TxD 49 48 43 42 52 51 50 47 46 44 41 40 21 22 23 26 HU HUH lU HUH CN cO cor gt a z 2 2 Z lt lt lt lt lt K gt 8 marc tc e n pL co o 1 applies only to devices with EPROM OTPROM Figure 1 4 Pin Assignments for 52 Pin TOFP M68HC11E Family Data Sheet Rev 5 1 XIRQ Vppe 1 m RESET PC7 ADDR7 DATA7 PC6 ADDR6 DATA6 M68HC11 E SERIES r1 PC5 ADDR5 DATA5 T PC4 ADDR4 DATA4 H PC3 ADDR3 DATA3 H PC2 ADDR2 DATA2 H PC1 ADDR1 DATA1 Freescale Semiconductor Freescale Semiconductor STRA AS E STRB R W PCO ADDRO DATAO PC1 ADDR1 DATA1 PC2 ADDR2 DATA2 PC3 ADDR3 DATA3 PC4 ADDR4 DATA4 PC5 ADDR5 DATA5 PC6 ADDR6 DATA6 PC7 ADDR7 DATA7 RESET XIROMppe IRQ PDO RxD EVss PD1 TxD PD2 MISO PD3 MOSI PD4 SCK M68HC11 E SERIES Pin Descriptions PE7 AN7 PE3 AN3 PE6 AN6 PE2 AN2 5 PE1 AN1 PE4 AN4 PEO ANO PBO ADDR8 PB1 ADDR9 PB2 A
189. ctor 181 Ordering Information and Mechanical Specifications 11 5 52 Pin Plastic Leaded Chip Carrier Case 778 B 0 007 0 18 T L MO NO u 0 007 0 1885 T L MO NO BD L G1 x 0 010 0 25 9 T L MO VIEW D D NOTES DATUMS L AND N DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE DIMENSION G1 TRUE POSITION TO BE MEASURED 0 007 0 1 8 L M NG AT DATUM SEATING PLANE DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH ALLOWABLE MOLD FLASH IS 0 010 0 250 PER SIDE DIMENSIONING AND TOLERANCING PER ANSI 14 5 1982 0 007 0 18 5 T L MO NO m gt A 0 004 0 100 5 CONTROLLING DIMENSION INCH 6 THE PACKAGE TOP MAY BE SMALLER THAN THE J u SEATING PACKAGE BOTTOM BY UP TO 0 012 0 300 VIEW S DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH TIE BAR BURRS GATE BURRS AND INTERLEAD FLASH BUT INCLUDING 0 010 0 25 T ANY BETWEEN THE AND BOTTOM OF THE PLASTIC BODY DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION THE DAMBAR PROTRUSION S SHALL NOT CAUSE THE H DIMENSION TO BE GREATER
190. data movement in and out of the device through the MOSI and MISO lines Master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles Four possible timing relationships can be chosen by using control bits CPOL and CPHA in the serial peripheral control register SPCR Both master and slave devices must operate with the same timing The SPI clock rate select bits SPR 1 0 in the SPCR of the master device select the clock rate In a slave device SPR 1 0 have no effect on the operation of the SPI 8 5 4 Slave Select The slave select SS input of a slave device must be externally asserted before a master device can exchange data with the slave device SS must be low before data transactions and must stay low for the duration of the transaction The SS line of the master must be held high If it goes low a mode fault error flag MODF is set in the serial peripheral status register SPSR To disable the mode fault circuit write a 1 in bit 5 of the port D data direction register This sets the SS pin to act as a general purpose output rather than the dedicated input to the slave select circuit thus inhibiting the mode fault flag The other three lines are dedicated to the SPI whenever the serial peripheral interface is on The state of the master and slave CPHA bits affects the operation of SS CPHA settings should be identical for master and slave When CPHA 0 the shift clock is the OR of
191. dded to the 8 bit offset provided in an instruction to create an effective address The IX register can also be used as a counter or as a temporary storage register 4 2 3 Index Register Y IY The 16 bit IY register performs an indexed mode function similar to that of the IX register However most instructions using the IY register require an extra byte of machine code and an extra cycle of execution time because of the way the opcode map is implemented Refer to 4 4 Opcodes and Operands for further information 4 2 4 Stack Pointer SP The M68HC11 CPU has an automatic program stack This stack can be located anywhere in the address space and can be any size up to the amount of memory available in the system Normally the SP is initialized by one of the first instructions in an application program The stack is configured as a data structure that grows downward from high memory to low memory Each time a new byte is pushed onto the stack the SP is decremented Each time a byte is pulled from the stack the SP is incremented At any given time the SP holds the 16 bit address of the next free location in the stack Figure 4 2 isa summary of SP operations When a subroutine is called by a jump to subroutine JSR or branch to subroutine BSR instruction the address of the instruction after the JSR or BSR is automatically pushed onto the stack least significant byte first When the subroutine is finished a return from subroutine RTS instruc
192. de e When a port C bit is at logic level it is driven low by the N channel driver e When a port C bit is at logic level 1 the associated pin has high impedance as neither the N channel nor the P channel devices are active It is customary to have an external pullup resistor on lines that are driven by open drain devices Port C can only be configured for wired OR operation when the MCU is in single chip mode Refer to Chapter 6 Parallel Input Output I O Ports for additional information about port C functions M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 27 General Description 1 4 15 Port D Pins PD5 PDO can be used for general purpose I O signals These pins alternately serve as the serial communication interface SCI and serial peripheral interface SPI signals when those subsystems are enabled e PDO is the receive data input RxD signal for the SCI PD1 is the transmit data output TxD signal for the SCI e PD5 PD2 are dedicated to the SPI PD2 is the master in slave out MISO signal PD3is the master out slave in MOSI signal PD4 is the serial clock SCK signal PD5is the slave select SS input 1 4 16 Port E Use port E for general purpose or analog to digital A D inputs CAUTION If high accuracy is required for A D conversions avoid reading port E during sampling as small disturbances can reduce the accuracy of that result M68HC11E Family Data Sheet Rev 5 1 28 Freesca
193. dition Codes Mode Opcode Operand Cycles S X H 1 2 TSTA Test A for Zero 0 INH 4D 2 A or Minus TSTB Test B for Zero B 0 B INH 5D 2 A A or Minus TSX Transfer Stack SP 1 IX INH 30 3 Pointer to X TSY Transfer Stack SP 1 INH 18 30 4 Pointer to Y TXS Transfer X to IX 1 SP INH 35 3 Stack Pointer TYS Transfer Y to IY 12 SP INH 18 35 4 Stack Pointer WAI Wait for Stack Regs amp WAIT INH 3E u Interrupt XGDX Exchange D IX gt D D gt IX INH 8F 3 with X XGDY Exchange D IY gt D D gt Y INH 18 8F 4 with Y Cycle Infinity or until reset occurs 12 cycles are used beginning with the opcode fetch A wait state is entered which remains in effect for an integer number of MPU E clock cycles n until an interrupt is recognized Finally two additional cycles are used to fetch the appropriate interrupt vector 14 n total Operands 8 bit direct address 0000 00FF high byte assumed to be 00 P 8 bit positive offset 00 0 to FF 255 is added to index hh High order byte of 16 bit extended address ii One byte of immediate data 31 High order byte of 16 bit immediate data kk Low order byte of 16 bit immediate data 11 Low order byte of 16 bit extended address mm 8 bit mask set bits to be affected rr Signed relative offset 80 128 to 7F 127 offset relative to address following machine code offset byte Operator
194. dshake mode clear the corresponding DDRC bits Refer to Figure 10 13 3 State Variation of Output Handshake Timing Diagram STRA Enables Output Buffer 0 Input 1 Output 6 5 Port D In all modes port D bits 5 0 can be used either for general purpose I O or with the serial communications interface SCI and serial peripheral interface SPI subsystems During reset port D pins PD 5 0 are configured as high impedance inputs DDRD bits cleared Address 1008 Bit 7 6 5 4 3 2 1 Bit 0 naa 0 0 PD5 PD4 PD3 PD2 PD1 PDO Write Reset Alternate Function PDA eae ins PDI PDO SS SCK MOSI MISO Tx RxD Indeterminate after reset Figure 6 7 Port D Data Register PORTD Address 1009 Bit 7 6 5 4 3 2 1 Bit 0 Read White DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRDO Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 6 8 Port D Data Direction Register DDRD Bits 7 6 Unimplemented Always read 0 DDRD 5 0 Port D Data Direction Bits When DDRD bit 5 is 1 and MSTR 1 in SPCR PD5 SS is a general purpose output and mode fault logic is disabled 0 Input 1 Output M68HC11E Family Data Sheet Rev 5 1 100 Freescale Semiconductor Port E 6 6 Port E Port E is used for general purpose static inputs or pins that share functions with the analog to digital A D converter system When some port E pins are being used for general pu
195. e mode fault does not help protect either one unless one of them selects the other as slave The amount of damage possible depends on the length of time both devices attempt to act as master A write collision error occurs if the SPDR is written while a transfer is in progress Because the SPDR is not double buffered in the transmit direction writes to SPDR cause data to be written directly into the SPI shift register Because this write corrupts any transfer in progress a write collision error is generated The transfer continues undisturbed and the write data that caused the error is not written to the shifter M68HC11E Family Data Sheet Rev 5 1 122 Freescale Semiconductor SPI Registers A write collision is normally a slave error because a slave has no control over when a master initiates a transfer A master knows when a transfer is in progress so there is no reason for a master to generate a write collision error although the SPI logic can detect write collisions in both master and slave devices The SPI configuration determines the characteristics of a transfer in progress For a master a transfer begins when data is written to SPDR and ends when SPIF is set For a slave with CPHA equal to 0 a transfer starts when SS goes low and ends when SS returns high In this case SPIF is set at the middle of the eighth SCK cycle when data is transferred from the shifter to the parallel data register but the transfer is still in progress until
196. e EEPROM array 2 2 2 Expanded Mode In expanded operating mode the MCU can access the full 64 Kbyte address space The space includes The same on chip memory addresses used for single chip mode e Addresses for external peripherals and memory devices The expansion bus is made up of ports B and C and control signals AS address strobe and R W read write R W and AS allow the low order address and the 8 bit data bus to be multiplexed on the same pins During the first half of each bus cycle address information is present During the second half of each bus cycle the pins become the bidirectional data bus AS is an active high latch enable signal for an external address latch Address information is allowed through the transparent latch while AS is high and is latched when AS drives low M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 29 Operating Modes and On Chip Memory The address R W and AS signals are active and valid for all bus cycles including accesses to internal memory locations The E clock is used to enable external devices to drive data onto the internal data bus during the second half of a read bus cycle E clock high R W controls the direction of data transfers R W drives low when data is being written to the internal data bus R W will remain low during consecutive data bus write cycles such as when a double byte store occurs Refer to Figure 2 1 NOTE The write enable signal for an external memory
197. e MC68HC71 1E20 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 175 Electrical Characteristics M68HC11E Family Data Sheet Rev 5 1 176 Freescale Semiconductor Chapter 11 Ordering Information and Mechanical Specifications 11 1 Introduction This section provides ordering information for the E series devices grouped by e Standard devices Custom ROM devices e Extended voltage devices In addition mechanical specifications for the following packaging options 52 plastic leaded chip carrier PLCC 52 windowed ceramic leaded chip carrier CLCC 64 pin quad flat pack 52 pin thin quad flat pack TQFP 56 shrink dual in line package with 070 inch lead spacing SDIP e 48 pin plastic DIP 100 inch lead spacing MC68HC811E2 only 11 2 Standard Device Ordering Information Description CONFIG Temperature Frequency MC Order Number 52 pin plastic leaded chip carrier PLCC 2 MHz MC68HC11E9BCFN2 BUFFALO ROM 0 40 to 85 C 3 MHz MC68HC11E9BCFN3 2 MHz MC68HC11E1CFN2 40 to 85 3 MHz MC68HC11E1CFN3 No ROM 0D 40 C to 105 2 MHz MC68HC11E1VFN2 40 to 125 2 MHz MC68HC11E1MFN2 2 MHz MC68HC11E0CFN2 40 to 85 C 3 MHz MC68HC11E0CFN3 No ROM no EEPROM 0C 40 C to 105 C 2 MHz MC68HC1 1EO0VFN2 40 to 125 2 MHz MC68HC11EOMFN2 Freescale Semiconductor
198. e Register BAUD TCLR Clear Baud Rate Counter Bit Test SCP 2 0 SCI Baud Rate Prescaler Select Bits NOTE SCP2 applies to MC68HC 7 11E20 only When SCP2 1 SCP 1 0 must equal Os Any other values for SCP 1 0 are not decoded in the prescaler and the results are unpredictable Refer to Figure 7 8 and Figure 7 9 RCKB SCI Baud Rate Clock Check Bit Test See Table 7 1 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 113 Serial Communications Interface SCI Table 7 1 Baud Rate Values Crystal Frequency MHz Pr scal p 4 00 4 9152 8 00 10 00 12 00 16 00 Prescaler Selects Divide pi ide Bus Frequency MHz SCP2 SCP1 SCPO SCR2 SCR1 SCRO 1 00 1 23 2 00 2 50 3 00 4 00 0 0 0 0 0 0 1 1 62500 76800 125000 156250 187500 250000 0 0 0 0 0 1 1 2 31250 38400 62500 78125 93750 125000 0 0 0 0 1 0 1 4 15625 19200 31250 39063 46875 62500 0 0 0 0 1 1 1 8 7813 9600 15625 19531 23438 31250 0 0 0 1 0 0 1 16 3906 4800 7813 9766 11719 15625 0 0 0 1 0 1 1 32 1953 2400 3906 4883 5859 7813 0 0 0 1 1 0 1 64 977 1200 1953 2441 2930 3906 0 0 0 1 1 1 1 128 488 600 977 1221 1465 1953 0 0 1 0 0 0 3 1 20833 25600 41667 52083 62500 83333 0 0 1 0 0 1 3 2 10417 12800 20833 26042 31250 41667 0 0 1 0 1 0 3 4 5208 6400 10417 13021 15625 20833 0 0 1 0 1 1 3 8 2604 3200 5208 6510 7813 10417 0 0 1 1 0 0 3 16 1302 16
199. e Vpp is removed and must remain low until Vpp has been restored to a valid level 1 4 8 VnL and VRH These two inputs provide the reference voltages for the analog to digital A D converter circuitry Vp is the low reference typically 0 Vdc Vey is the high reference For proper A D converter operation should be at least 3 Vdc greater than and Vay should be between Vss and Vpp M68HC11E Family Data Sheet Rev 5 1 24 Freescale Semiconductor Pin Descriptions 1 4 9 STRA AS The strobe A STRA and address strobe AS pin performs either of two separate functions depending on the operating mode e In single chip mode STRA performs an input handshake strobe input function Inthe expanded multiplexed mode AS provides an address strobe function AS can be used to demultiplex the address and data signals at port C Refer to Chapter 2 Operating Modes and On Chip Memory 1 4 10 STRB R W The strobe B STRB and read write R W pin act as either an output strobe or as a data bus direction indicator depending on the operating mode In single chip operating mode STRB acts as a programmable strobe for handshake with other parallel devices Refer to Chapter 6 Parallel Input Output I O Ports for further information In expanded multiplexed operating mode R W is used to indicate the direction of transfers on the external data bus A low on the R W pin indicates data is being written to the exter
200. e of the MODB pin as the MCU leaves reset SMOD controls whether a normal mode or a special mode is selected When SMOD is 0 one of the two normal modes is selected either normal single chip mode or normal expanded mode When SMOD is 1 one of the two special modes is selected either special bootstrap mode or special test mode When either special mode is in effect SMOD 1 certain privileges are in effect for instance the ability to write to the mode control bits and fetching the reset and interrupt vectors from BFxx rather than FFxx Table 1 Mode Selection Summary Input Pins Control Bits in HPRIO Mode Selected MODB MODA RBOOT SMOD MDA 1 0 Normal single chip 0 0 0 0 0 Normal expanded 0 0 1 0 0 Special bootstrap 1 1 0 0 1 Special test 0 1 1 M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 195 Boot ROM Firmware The alternate vector locations are achieved by simply driving address bit A14 low during all vector fetches if SMOD 1 For special test mode the alternate vector locations assure that the reset vector can be fetched from external memory space so the test system can control MCU operation In special bootstrap mode the small boot ROM is enabled in the memory map by RBOOT 1 so the reset vector will be fetched from this ROM and the bootloader firmware will control MCU operation RBOOT is reset to 1 in bootstrap mode to enable the small boot ROM In the other three modes R
201. e to AS fall SL 150 _ 25 _ 25 Multiplexed address hold time 1 8 30 ng 2 b 95 33 ns 26 Delay time E to AS rise 1 8 5 ns tasp 120 58 ns 27 Pulse width AS high PWasy 1 4 tcyc 30 ns PWasu 220 95 ns 28 Delay time AS to rise tagen 1 8 5 ns tasep 120 58 ns ime 33a A ipsR tt COR B n 35 MPU access time tacce PWen tpsn tACCE 440 190 ns 46 Multiplexed address delay Previous cycle MPU read 156 _ 88 u tman 30 ns 2 a MAD 1 Vpp 3 0 Vdc to 5 5 Vss 0 Vdc TA T to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 Input clocks with duty cycles other than 50 affect bus performance Timing parameters affected by input clock duty cycle are identified by a and b To recalculate the approximate bus timing values substitute the following expressions in place of 1 8 the above formulas where applicable a 1 1 4 b dc x 1 4 tcvc Where dc is the decimal value of duty cycle percentage high time M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 169 Electrical Characteristics RW ADDRESS NON MULTIPLEXED ADDRESS DATA MULTIPLEXED AS Note Measurement points shown are 20 and 70 of Vpp Figure 10 14 Multiplexed Expansion Bus Timing Diagra
202. eceiver to think the received character was CO or EO 10 at 7812 baud instead of the FF which was sent at 1200 baud The stop bit sample detects a 1 as expected 11 but this detection is actually in the middle of bit 0 of the 1200 baud FF character The SCI receiver is not confused by the rest of the 1200 baud FF character because the receive data line is high 12 just as it would be for the idle condition If a character other than FF is sent as the first character an SCI receive error could result Main Bootloader Program Figure 3 is a flowchart of the main bootloader program in the MC68HC711E9 This bootloader demonstrates the most important features of the bootloaders used on all M68HC11 Family members For complete listings of other M68HC11 versions refer to Listing 3 MC68HC711E9 Bootloader ROM at the end of this application note and to Appendix B of the 68 11 Reference Manual Freescale document order number M68HC11RM AD The reset vector in the boot ROM points to the start 1 of this program The initialization block 2 establishes starting conditions and sets up the SCI and port D The stack pointer is set because there are push and pull instructions in the bootloader program The X index register is pointed at the start of the register block 1000 so indexed addressing can be used Indexed addressing takes one less byte of ROM space than extended instructions and bit manipulation instructions are not available in extended
203. efore leaving the interrupt service routine software must clear PAOVF by writing to the TFLG2 register M68HC11E Family Data Sheet Rev 5 1 146 Freescale Semiconductor Pulse Accumulator PAII and PAIF Pulse Accumulator Input Edge Interrupt Enable Bit and Flag The PAIF status bit is automatically set each time a selected edge is detected at the PA7 PAI OC1 pin To clear this status bit write to the TFLG2 register with a 1 in the corresponding data bit position bit 4 The PAII control bit allows configuring the pulse accumulator input edge detect for polled or interrupt driven operation but does not affect setting or clearing the PAIF bit When PAII is 0 pulse accumulator input interrupts are inhibited and the system operates in a polled mode In this mode the PAIF bit must be polled by user software to determine when an edge has occurred When the PAII control bit is set a hardware interrupt request is generated each time PAIF is set Before leaving the interrupt service routine software must clear PAIF by writing to the TFLG2 register M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 147 Timing Systems M68HC11E Family Data Sheet Rev 5 1 148 Freescale Semiconductor Chapter 10 Electrical Characteristics 10 1 Introduction This section contains electrical specifications for the M68HC11 E series devices 10 2 Maximum Ratings for Standard and Extended Voltage Devices Maximum ratings are the extreme
204. enabled only if the MCU is reset in special bootstrap mode In expanded modes the ROM EPROM OTPROM if present is enabled out of reset and located at the top of the memory map if the ROMON bit in the CONFIG register is set ROM or EPROM is enabled out of reset in single chip and bootstrap modes regardless of the state of ROMON For devices with 512 bytes of EEPROM the EEPROM is located at B600 B7FF and has the same read cycle time as the internal ROM The 512 bytes of EEPROM cannot be remapped to other locations For the MC68HC811E2 EEPROM is located at F800 FFFF and can be remapped to any 4 Kbyte boundary EEPROM mapping control bits EE 3 0 in CONFIG determine the location of the 2048 bytes of EEPROM and are present only on the MC68HC81 1E2 Refer to 2 3 3 1 System Configuration Register for a description of the MC68HC811E2 CONFIG register EEPROM can be programmed or erased by software and an on chip charge pump allowing EEPROM changes using the single Vpp supply 2 3 2 Mode Selection The four mode variations are selected by the logic states of the MODA and MODB pins during reset The MODA and MODB logic levels determine the logic state of SMOD and the MDA control bits in the highest priority I bit interrupt and miscellaneous HPRIO register After reset is released the mode select pins no longer influence the MCU operating mode In single chip operating mode the MODA pin is connected to a logic level 0 In expanded mode MODA
205. es MCUs Differences among devices are noted in the table accompanying Figure 1 1 1 4 Pin Descriptions M68HC11 E series MCUs are available packaged in 52 plastic leaded chip carrier PLCC 52 windowed ceramic leaded chip carrier CLCC 52 plastic thin quad flat pack 10 mm x 10 mm TQFP 64 quad flat pack e 48 plastic dual in line package DIP MC68HC811E2 only 56 plastic shrink dual in line package 070 inch lead spacing SDIP Most pins on these MCUs serve two or more functions as described in the following paragraphs Refer to Figure 1 2 Figure 1 3 Figure 1 4 Figure 1 5 and Figure 1 6 which show the M68HC11 E series pin assignments for the PLCC CLCC QFP TQFP SDIP and DIP packages M68HC11E Family Data Sheet Rev 5 1 14 Freescale Semiconductor Pin Descriptions MODA MODB egy XTAL EXTAL E RESET MODE CONTROL INTERRUPT LOGIC ROM OR EPROM SEE TABLE EEPROM M68HC11 CPU SEE TABLE RAM SEE TABLE CLOCK LOGIC a 5 E z a o a o 2 BUS EXPANSION SERIAL SERIAL A ADDRESS ADDRESS DATA PERIPHERAL COMMUNICATION Von 8 INTERFACE INTERFACE Ves mE n STROBE AND HANDSHAKE PARALLEL I O CONTROL A D CONVERTER PORT E CONTROL PORT D PORT G lt vui x
206. es each Figure 2 5 Memory Map for MC68HC 7 11E20 0000 0000 256 BYTES RAM EXT Y 00 1000 64 REGISTER BLOCK 103F EXT EXT BFoo BOOT BFCO SPECIAL MODES be coss ROM INTERRUPT pore rrr VECTORS Y 2048 BYTES EEPROM 800 F800 FECO NORMAL MODES bonne INTERRUPT FFFF Y FFFF FFFF VECTORS SINGLE EXPANDED BOOTSTRAP SPECIAL CHIP TEST Figure 2 6 Memory Map for MC68HC811E2 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 33 Operating Modes and On Chip Memory Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read Port A Data Register pa pag 4 PA2 PAT 1000 PORTA Write Seepage98 Reset 0 0 0 1001 Reserved R R R R R R R R Parallel 1 0 Control Register Read g STAF CWOM HNDS OIN PLS EGA INVB 1002 PIOC Write See page 102 Reset 0 0 0 0 0 U 1 1 Data Register Read 9 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO 1003 PORTC Write See page 99 Reset Indeterminate after reset Port Data Register Read g PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 1004 PORTB Write 99 Reset O 0 0 0 0 0 0 0 Read Port C Latched Register PCL7 PCl6 PCL5 PCL3 PCL2 PCLO 1005 PORTCL Write See page 99 Reset Indeterminate after reset 1006 Reserved R R R R R R R R Read
207. es that were present before the interrupt occurred The X interrupt mask bit is set only by hardware RESET or XIRQ acknowledge X is cleared only by program instruction TAP where the associated bit of A is 0 or RTI where bit 6 of the value loaded into the CCR from the stack has been cleared There is no hardware action for clearing X 4 2 6 8 STOP Disable S Setting the STOP disable S bit prevents the STOP instruction from putting the M68HC11 into a low power stop condition If the STOP instruction is encountered by the CPU while the S bit is set it is treated as a no operation NOP instruction and processing continues to the next instruction S is set by reset STOP is disabled by default 4 3 Data Types The M68HC11 CPU supports four data types 1 Bit data 2 8 bit and 16 bit signed and unsigned integers 3 16 bit unsigned fractions 4 16 bit addresses A byte is eight bits wide and can be accessed at any byte location A word is composed of two consecutive bytes with the most significant byte at the lower value address Because the M68HC11 is 8 bit CPU there are no special requirements for alignment of instructions or operands M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 69 Central Processor Unit CPU 4 4 Opcodes and Operands The M68HC11 Family of microcontrollers uses 8 bit opcodes Each opcode identifies a particular instruction and associated addressing mode to the CPU Several opcodes
208. eserved 1100 Vg ADR1 1101 va ADR2 1110 2 ADR3 1111 Reserved ADR4 1 Used for factory testing M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 63 Analog to Digital A D Converter 3 10 A D Converter Result Registers These read only registers hold an 8 bit conversion result Writes to these registers have no effect Data in the A D converter result registers is valid when the CCF flag in the ADCTL register is set indicating a conversion sequence is complete If conversion results are needed sooner refer to Figure 3 3 which shows the A D conversion sequence diagram Register name Analog to Digital Converter Result Register 1 Address 1031 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset Indeterminate after reset Register name Analog to Digital Converter Result Register2 Address 1032 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset Indeterminate after reset Register name Analog to Digital Converter Result Register3 Address 1033 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset Indeterminate after reset Register name Analog to Digital Converter Result Register 4 Address 1034 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6
209. f 6 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 103E Reserved R R R R R R R R System Configuration Register Read NOSEC NOCOP EEON 103F CONFIG Write See 43 Reset 0 0 0 0 U U 1 U System Configuration Register ges ges EE EEO NOSEC EEON 103F CONFIG Write 43 Reset 1 1 1 1 U U 1 1 1 Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes 2 MC68HC711E9 only 3 MC68HC811E2 only Unimplemented R Reserved U Unaffected Indeterminate after reset Figure 2 7 Register and Control Bit Assignments Sheet 6 of 6 2 3 1 RAM and Input Output Mapping Hardware priority is built into RAM and I O mapping Registers have priority over RAM and RAM has priority over ROM When a lower priority resource is mapped at the same location as a higher priority resource a read write of a location results in a read write of the higher priority resource only For example if both the register block and the RAM are mapped to the same location only the register block will be accessed If RAM and ROM are located at the same position RAM has priority The fully static RAM can be used to store instructions variables and temporary data The direct addressing mode can ac
210. fAZero Z N V 1 REL 2F rr 3 BLO rel Branch if Lower C 1 REL 25 rr 3 BLS rel Branch if Lower C Z 1 REL 23 rr 3 or Same BLT rel Branch if lt Zero 2 1 REL 20 rr 3 BMI rel Branch if Minus 2 1 REL 2B rr 3 BNE rel Branch if not TZ REL 26 rr 3 Zero BPL rel Branch if Plus 2N 0 REL 2A rr 3 BRA rel Branch Always 9423 REL 20 rr 3 BRCLR opr Branch if 2Memm 0 DIR 13 mm 6 msk Bit s Clear IND X IF irt 7 rel IND Y 18 Jff mm 8 rr ff mm rE BRN rel Branch Never 1 0 REL 21 rr 3 BRSET opr Branch if Bit s mm 0 DIR 12 mm 6 msk Set IND X rr 7 rel IND Y 18 ff mm 8 ff mm rr BSET opr Set Bit s DIR 14 mm 6 es 0 msk IND X 1C ff mm 7 IND Y 18 mm 8 BSR rel Branch to See Figure 3 2 REL 8D 6 Subroutine BVC rel Branch if TM EQ REL 28 rr 3 Overflow Clear BVS rel Branch if 2 1 REL 29 3 Overflow Set CBA Compare A to B A B INH 11 2 A CLC Clear Carry Bit 02C INH 0 2 0 CLI Clear Interrupt 021 INH E 2 0 Mask CLR opr Clear Memory 02M EXT hh 11 6 Ace 0 1 0 0 IND X 6F 6 IND Y 18 6F 7 CLRA Clear 0 4 2 0 1 0 0 Accumulator A CLRB Clear INH 5F 2 0 1 0 0 Accumulator B CLV Clear Overflow 02V INH 0A 2 0 Flag CMPA opr Compare to A M A IMM 81 ii 2 eS A A A A Memory A DIR 91 dd 3 A EXT B1 hh 11 4 A IND X 1
211. framing error FE bit is set FE is set at the same time as the If the byte received causes both framing and overrun errors the processor only recognizes the overrun error The framing error flag inhibits further transfer of data into the SCDR until it is cleared The FE bit is cleared when the SCSR is read with FE equal to 1 followed by a read of the SCDR 7 7 SCI Registers Five addressable registers are associated with the SCI Four control and status registers Serial communications control register 1 SCCR1 Serial communications control register 2 SCCR2 Baud rate register BAUD Serial communications status register SCSR One data register Serial communications data register SCDR The SCI registers are the same for all M68HC11 E series devices with one exception The SCI system for MC68HC 7 11E20 contains an extra bit in the BAUD register that provides a greater selection of baud prescaler rates Refer to 7 7 5 Baud Rate Register Figure 7 8 and Figure 7 9 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 109 Serial Communications Interface SCI 7 7 1 Serial Communications Data Register SCDR is a parallel register that performs two functions The receive data register when it is read The transmit data register when it is written Reads access the receive data buffer and writes access the transmit data buffer Receive and transmit are double buffered Address 102
212. g XIRQ interrupts Thereafter software cannot set the X bit Thus an XIRQ interrupt is a non maskable interrupt Because the operation of the I bit related interrupt structure has no effect on the X bit the internal XIRQ pin remains unmasked In the interrupt priority logic the XIRQ interrupt has a higher priority than any source that is maskable by the bit All I bit related interrupts operate normally with their own priority relationship When an I bit related interrupt occurs the bit is automatically set by hardware after stacking the CCR byte The X bit is not affected When an X bit related interrupt occurs both the X and bits are automatically set by hardware after stacking the CCR A return from interrupt instruction restores the X and l bits to their pre interrupt request state 5 5 3 Illegal Opcode Trap Because not all possible opcodes or opcode sequences are defined the MCU includes an illegal opcode detection circuit which generates an interrupt request When an illegal opcode is detected and the interrupt is recognized the current value of the program counter is stacked After interrupt service is complete reinitialize the stack pointer so repeated execution of illegal opcodes does not cause stack underflow Left uninitialized the illegal opcode vector can point to a memory location that contains an illegal opcode This condition causes an infinite loop that causes stack underflow The stack grows until the sy
213. g data to the shifter The SPI status block represents the SPI status functions transfer complete write collision and mode fault performed by the serial peripheral status register SPSR The SPI control block represents those functions that control the SPI system through the serial peripheral control register SPCR Refer to Figure 8 1 which shows the SPI block diagram 8 3 SPI Transfer Formats During an SPI transfer data is simultaneously transmitted and received A serial clock line synchronizes shifting and sampling of the information on the two serial data lines A slave select line allows individual selection of a slave SPI device slave devices that are not selected do not interfere with SPI bus activities On a master SPI device the select line can optionally be used to indicate a multiple master bus contention Refer to Figure 8 2 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 119 Serial Peripheral Interface SPI gt 5 INTERNAL T IM MCU CLOCK MSB LSB la 8 BITSHIFTREGISTER lt s S DIVIDER READ DATA BUFFER a 2 4 16 32 fe 2 A CLOCK SELECT ao 100 gt M 2 T A A Y d og lt SPI CONTROL lt SRE SPI STATUS REGISTER SPI CONTROL REGISTER INTERNAL
214. h has its own vector 5 2 1 Power On Reset POR A positive transition on Vpp generates a power on reset POR which is used only for power up conditions POR cannot be used to detect drops in power supply voltages 4064 internal clock cycle delay after the oscillator becomes active allows the clock generator to stabilize If RESET is at logical 0 at the end of 4064 the CPU remains in the reset condition until RESET goes to logical 1 The POR circuit only initializes internal circuitry during cold starts Refer to Figure 1 7 External Reset Circuit NOTE It is important to protect the MCU during power transitions Most M68HC 11 systems need an external circuit that holds the RESET pin low whenever Vpp is below the minimum operating level This external voltage level detector or other external reset circuits are the usual source of reset in a system M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 79 Resets and Interrupts 5 2 2 External Reset RESET The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than two E clock cycles after an internal device releases reset When a reset condition is sensed the RESET pin is driven low by an internal device for four E clock cycles then released Two E clock cycles later it is sampled If the pin is still held low the CPU assumes that an external reset has occurred If the
215. hake functions are available only in the single chip operating mode PIOC is a read write register except for bit 7 which is read only Table 6 2 shows a summary of handshake operations Table 6 2 Parallel Control STAF Clearing HNDS OIN PLS EGA Port B Port C Sequence Read Simple PIOC with aN veh dapi STRB pulses strobed STAF 1 0 X X active y on writes mode then read STRA 9 to PORTB PORTCL d 5 Read Full input 0 STRB Inputs latched into Normal output PIOC with hand STAF 1 4 0 active level 1 i PORTCL on any port unaffected shake 1 STRB active edge on in handshake mode active pulse STRA modes PORTCL P o 1 Driven as outputs if Fur pead 0 STRB Y STRA at active Normal output output PIOC with hand 1 1 1 active level PotC level follows port unaffected 1 STRB 4 DDRC in handshake then write active pulse if STRA not at modes mode PORTCL p Follow Active Edge Follow DRC DDRC active level Address 1002 Bit 7 6 5 4 3 2 1 Bit 0 Read STAF STAI CWOM HNDS OIN PLS EGA INVB Write Reset 0 0 0 0 0 U 1 1 102 U Unaffected Figure 6 10 Parallel I O Control Register PIOC STAF Strobe A Interrupt Status Flag STAF is set when the selected edge occurs on strobe A This bit can be cleared by a read of PIOC with STAF set followed by a read of PORTCL si
216. iagram M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 115 Serial Communications Interface SCI EXTAL OSCILLATOR INTERNAL BUS CLOCK PH2 CLOCK GENERATOR gt 4 XTAL 3 4 13 39 eee SCP 2 0 LL AS c 0 0 0 c 0 0 1 C 0 1 0 C 0 1 1 C 1 0 0 e e e e SCR 2 0 0 0 0 e 2 0 0 1 e 2 0 1 0 4 2 0 1 1 1 0 0 e SCI TRANSMIT 2 1 0 1 BAUD RATE 1X 2 1 1 0 e 92 1 1 1 SCI RECEIVE BAUD RATE 16 SCP2 is present only on MC68HC 7 11E20 Figure 7 9 MC68HC 7 11E20 SCI Baud Rate Generator Block Diagram 7 8 Status Flags and Interrupts The SCI transmitter has two status flags These status flags can be read by software polled to tell when the corresponding condition exists Alternatively a local interrupt enable bit can be set to enable each of these status conditions to generate interrupt requests when the corresponding condition is present Status flags are automatically set by hardware logic conditions but must be cleared by software which provides an interlock mechanism that enables logic to know when software has noticed the status indication The software clearing sequence for these flags is automatic Functions that are normally performed in response to the status flags als
217. ical Shi EXT 78 hh 11 6 LL A A A Left lt 0 IND X 68 6 C b7 50 IND Y 18 68 7 LSLA Logical Shi A INH 48 2 Left A 0 C b7 bO LSLB Logical Shi B INH 58 2 A Left B b7 b0 LSLD Logical Shi INH 05 3 Left Double y c err ro C b7A b0 b7 B 00 LSR opr Logical Shi EXT 74 hh 11 6 0 A A A Right iones IND X 64 6 b7 bo C IND Y 18 64 7 LSRA Logical Shi A INH 44 2 0 A A A Right A 0 b7 bo C LSRB Logical Shi B INH 54 2 0 Right B cde b7 bo C M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 75 Central Processor Unit CPU Table 4 2 Instruction Set Sheet 5 of 7 Mnemonic Operation Description Addressing Instruction Condition Codes Operand Cycles H 1 2 C LSRD Logical Shift INH 04 3 0 Right Double mesa b7 A b0 b7 B bO C MUL Multiply 8 by 8 A B gt D INH 3D 10 NEG opr Two s 0 70 hh 11 6 _ Complement IND X 60 6 Memory Byte IND Y 18 60 7 NEGA Two s 0 40 2 Complement A NEGB Two s 0 INH 50 2 A Complement B NOP No
218. ided that PTCON in BPROT is clear To change the value in the CONFIG register complete this procedure 1 Erase the CONFIG register 2 Program the new value to the CONFIG address 3 Initiate reset NOTE Do not initiate a reset until the procedure is complete 2 5 2 EEPROM Security The optional security feature available only on ROM based MCUS protects the EEPROM and RAM contents from unauthorized access A program or a key portion of a program can be protected against unauthorized duplication To accomplish this the protection mechanism restricts operation of protected devices to the single chip modes This prevents the memory locations from being monitored externally because single chip modes do not allow visibility of the internal address and data buses Resident programs however have unlimited access to the internal EEPROM and RAM and can read write or transfer the contents of these memories An enhanced security feature which protects EPROM contents RAM and EEPROM from unauthorized accesses is available in MC68S711E9 Refer to Chapter 11 Ordering Information and Mechanical Specifications for the exact part number For further information these engineering bulletins have been included at the back of this data book e EB183 Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR e EB188 Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR M68
219. ily Data Sheet Rev 5 1 Freescale Semiconductor 163 Electrical Characteristics poo MCU WRITE TO PORT B C D PREVIOUS PORT DATA NEW DATA VALID PORT PREVIOUS PORT DATA NEW DATA VALID Figure 10 8 Port Write Timing Diagram STRA IN PORT C IN Figure 10 9 Simple Input Strobe Timing Diagram DENS MCU WRITE TO PORT B PORT PREVIOUS PORT DATA NEW DATA VALID STRB OUT Figure 10 10 Simple Output Strobe Timing Diagram pes READ Rn Eee E READY STRB 007 thes STRA IN lis tH PORT C IN Notes 1 After reading PIOC with STAF set 2 Figure shows rising edge STRA EGA 1 and high true STRB INVB 1 Figure 10 11 Port C Input Handshake Timing Diagram M68HC11E Family Data Sheet Rev 5 1 164 Freescale Semiconductor MC68L11E9 E20 Peripheral Port Timing WRITE 7 PORTC OUT PREVIOUSPORTDATA XOQQQ NEWDATAVAUD READY STRB N tas STRA IN Notes 1 After reading PIOC with STAF set 2 Figure shows rising edge STRA EGA 1 and high true STRB INVB 1 Figure 10 12 Port C Output Handshake Timing Diagram gt E tpwo PORT OUT DOA READY toes STRB OUT STRA IN Eus 7 i E E DDR 0 OLD DATA XX AL NEW DATA VALID 77 a STRA ACTIVE BEFORE PORTCL WRITE tpoz STRA IN NN lt NEW DATA
220. in the MC68S711E9 MCU The enhancement to the standard security feature protects the EPROM as well as RAM and EEPROM 0 Security enabled 1 Security disabled NOCOP COP System Disable Bit Refer to Chapter 5 Resets and Interrupts 1 COP disabled 0 COP enabled ROMON ROM EPROM OTPROM Enable Bit When this bit is 0 the ROM or EPROM is disabled and that memory space becomes externally addressed In single chip mode ROMON is forced to 1 to enable ROM EPROM regardless of the state of the ROMON bit 0 ROM disabled from the memory map 1 ROM present in the memory map EEON EEPROM Enable Bit When this bit is 0 the EEPROM is disabled and that memory space becomes externally addressed 0 EEPROM removed from the memory map 1 EEPROM present in the memory map 2 3 3 2 RAM and I O Mapping Register The internal registers used to control the operation of the MCU can be relocated on 4 Kbyte boundaries within the memory space with the use of the RAM and I O mapping register INIT This 8 bit special purpose register can change the default locations of the RAM and control registers within the MCU memory map It can be written only once within the first 64 E clock cycles after a reset in normal modes and then it becomes a read only register Address 103D Bit 7 6 5 4 3 2 1 Bit 0 Read iu RAM2 RAM1 RAMO REG3 REG2 REG1 REGO rite Reset 0 0 0 0 0 0 0 1 Figure 2 12 RAM and I O Mapping
221. ion The serial peripheral interface SPI an independent serial communications subsystem allows the MCU to communicate synchronously with peripheral devices such as Frequency synthesizers Liquid crystal display LCD drivers Analog to digital A D converter subsystems Other microprocessors The SPI is also capable of inter processor communication in a multiple master system The SPI system can be configured as either a master or a slave device When configured as a master data transfer rates can be as high as one half the E clock rate 1 5 Mbits per second for a 3 MHz bus frequency When configured as a slave data transfers can be as fast as the E clock rate 3 Mbits per second for a 3 MHz bus frequency 8 2 Functional Description The central element in the SPI system is the block containing the shift register and the read data buffer The system is single buffered in the transmit direction and double buffered in the receive direction This means that new data for transmission cannot be written to the shifter until the previous transfer is complete however received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial character As long as the first character is read out of the read data buffer before the next serial character is ready to be transferred no overrun condition occurs A single MCU register address is used for reading data from the read data buffer and for writin
222. ion Freescale application note AN1060 entitled M68HC1 1 Bootstrap Mode has been included at the back of this document M68HC11E Family Data Sheet Rev 5 1 48 Freescale Semiconductor EPROM OTPROM 2 4 3 EPROM and EEPROM Programming Control Register The EPROM and EEPROM programming control register PPROG enables the EPROM programming voltage and controls the latching of data to be programmed For MC68HC711E9 PPROG is also the EEPROM programming control register For the MC68HC711E20 EPROM programming is controlled by the EPROG register and EEPROM programming is controlled by the PPROG register Address 103B Bit 7 6 5 4 3 2 1 Bit 0 Read 1 Wi ODD EVEN ELAT BYTE ROW ERASE EELAT EPGM rite Reset 0 0 0 0 0 0 0 0 1 MC68HC711E9 only Figure 2 14 EPROM and EEPROM Programming Control Register PPROG ODD Program Odd Rows in Half of EEPROM Test Bit Refer to 2 5 EEPROM EVEN Program Even Rows in Half of EEPROM Test Bit Refer to 2 5 EEPROM ELAT EPROM OTPROM Latch Control Bit When ELAT 1 writes to EPROM cause address and data to be latched and the EPROM OTPROM cannot be read ELAT can be read any time ELAT can be written any time except when EPGM 1 then the write to ELAT is disabled 0 EPROM address and data bus configured for normal reads 1 EPROM address and data bus configured for programming For the MC68HC711E9 EPGM enables the high voltage necess
223. is normally connected to Vpp through a pullup resistor of 4 7 The MODA pin also functions as the load instruction register LIR pin when the MCU is not in reset The open drain active low LIR output pin drives low during the first E cycle of each instruction The MODB pin also functions as standby power input Vstpy which allows RAM contents to be maintained in absence of Vpp Refer to Table 2 1 which is a summary of mode pin operation the mode control bits and the four operating modes M68HC11E Family Data Sheet Rev 5 1 40 Freescale Semiconductor Table 2 1 Hardware Mode Select Summary Input Levels Control Bits in HPRIO at Reset Mode Latched at Reset MODB MODA RBOOT SMOD MDA 1 0 Single chip 0 0 0 1 1 Expanded 0 0 1 0 0 Bootstrap 1 1 0 0 1 Special test 0 1 1 A normal mode is selected when MODB is logic 1 during reset One of three reset vectors is fetched from address FFFA FFFF and program execution begins from the address indicated by this vector If MODB is logic 0 during reset the special mode reset vector is fetched from addresses BFFA BFFF and software has access to special test features Refer to Chapter 5 Resets and Interrupts Address 103 Bit 7 6 5 4 3 2 1 Bit 0 Read FK RBOOT SMOD MDA IRV NE PSEL2 PSELO Resets Single chip 0 0 0 0 0 1 1 0 Expanded 0 0 1 0 0 1 1
224. is the NAND of the E clock and the inverted R W signal PB7 ADDR15 PB6 ADDR14 PB5 ADDR13 4 ADDR12 PB3 ADDR11 PB2 ADDR10 PB1 ADDR9 PBO ADDR8 HC373 PC7 Qi ADDR7 PC6 e p qe ADDR6 PC5 03 Q3 ADDR5 PC4 4 04 ADDR4 PC3 05 Q5 ADDR3 PC2 06 06 ADDR2 PC1 07 Q ADDR1 PCO D8 08 ADDRO AS LE d MCU DATA Figure 2 1 Address Data Demultiplexing 2 2 3 Test Mode Test mode a variation of the expanded mode is primarily used during Freescale s internal production testing however it is accessible for programming the configuration CONFIG register programming calibration data into electrically erasable programmable read only memory EEPROM and supporting emulation and debugging during development 2 2 4 Bootstrap Mode When the MCU is reset in special bootstrap mode a small on chip read only memory ROM is enabled at address BFOO BFFF The ROM contains a bootloader program and a special set of interrupt and reset vectors The fetches the reset vector then executes the bootloader Bootstrap mode is a special variation of the single chip mode Bootstrap mode allows special purpose programs to be entered into internal random access memory RAM When bootstrap mode is selected at reset a small bootstrap ROM becomes present in the memory map Reset and interrupt vectors are M68HC11
225. ister depending on the function chosen for the PAS pin To enable it as an input capture pin set the 14 O5 bit in the pulse accumulator control register PACTL to logic level 1 To use it as an output compare register set the 14 O5 bit to a logic level 0 Refer to 9 7 Pulse Accumulator Register name Timer Input Capture 4 Output Compare 5 High Address 101E Bit 7 6 5 4 3 2 1 Bit 0 Read Write Reset 1 1 1 1 1 1 1 1 Register name Timer Input Capture 4 Output Compare 5 Low Address 101F Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Read Write Reset 1 1 1 1 1 1 1 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 9 7 Timer Input Capture 4 Output Compare 5 Register Pair TI4 O5 9 4 Output Compare Use the output compare OC function to program an action to occur at a specific time when the 16 bit counter reaches a specified value For each of the five output compare functions there is a separate 16 bit compare register and a dedicated 16 bit comparator The value in the compare register is compared to the value of the free running counter on every bus cycle When the compare register matches the counter value an output compare status flag is set The flag can be used to initiate the automatic actions for that output compare function To produce a pulse of a specific duration write a value to the output comp
226. it 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset Indeterminate after reset Figure 9 26 Pulse Accumulator Count Register PACNT 9 7 3 Pulse Accumulator Status and Interrupt Bits The pulse accumulator control bits PAOVI and PAOVF and PAIF are located within timer registers TMSK2 and TFLG2 Address 1024 Bit 7 6 5 4 3 2 1 Bit 0 Read TOI RTII PAOVI PR1 PRO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 27 Timer Interrupt Mask 2 Register TMSK2 Address 1025 Bit 7 6 5 4 3 2 1 Bit 0 Read TOF RTIF PAOVF PAIF Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 28 Timer Interrupt Flag 2 Register TFLG2 PAOVI and PAOVF Pulse Accumulator Interrupt Enable and Overflow Flag The PAOVF status bit is set each time the pulse accumulator count rolls over from FF to 00 To clear this status bit write a 1 in the corresponding data bit position bit 5 of the TFLG2 register The PAOVI control bit allows configuring the pulse accumulator overflow for polled or interrupt driven operation and does not affect the state of PAOVF When PAOVI is 0 pulse accumulator overflow interrupts are inhibited and the system operates in a polled mode which requires that PAOVF be polled by user software to determine when an overflow has occurred When the PAOVI control bit is set a hardware interrupt request is generated each time PAOVF is set B
227. it 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit15 Bit14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 Bit15 Bit14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1 1 1 1 1 1 1 1 Unimplemented R Reserved U Unaffected Indeterminate after reset Figure 2 7 Register and Control Bit Assignments Sheet 2 of 6 M68HC11E Family Data Sheet Rev 5 1 35 Freescale Semiconductor Operating Modes and On Chip Memory Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read Timer Output Compare 2 Register Bit7 Bite Bit5 Bit 4 Bit 3 Bit2 1 Bito 1019 Low TOC2L Write page 134 Reset 1 1 1 1 1 1 1 1 Read Timer Output Compare 3 Register Bit15 Bit14 Bit13 Bit12 Bit9 Bits 101A High TOC3H Write 135 Reset 1 1 1 1 1 1 1 1 Read Timer Output Compare 3 Register Bitz Bite Bits Bit 4 Bit 3 Bit Bit Bito 101B Low TOC3L Write page 135 peser 1 1 1 1 1 1 1 1 Read Timer Output Compare 4 Register 7 Biti5 Bit14 Bit13 Bit12 Bit9 Bits 101C High TOC4H Write 135 Reset 1 1 1 1 1 1 1 1 Read Timer Output Compare 4 Register Bit7 Bite 5 Bit 4 Bit 3 Bit2 Bit Bito 101D Low TOC4L Write
228. itional pin can be configured as either the fourth IC or the fifth OC Any port A pin that is not currently being used for a timer function can be used as either a general purpose input or output line Only port A pins PA7 and PAS have an associated data direction control bit that allows the pin to be selectively configured as input or output Bits DDRA7 and DDRAS located in register control data direction for PA7 and PAS respectively All other port A pins are fixed as either input or output can function as general purpose I O or as timer output compare for OC1 PA7 is also the input to the pulse accumulator even while functioning as a general purpose I O or an OC1 output M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 25 General Description Table 1 1 Port Signal Functions E PAO PAO IC3 PA1 PA1 IC2 PA2 PA2 IC1 PA3 OC5 IC4 OC1 4 PA4 OCA4 OC1 PAS PA5 OC3 OC1 PA6 PA6 OC2 OC1 PA7 PA7 PAI OC1 FBO PBO ADDR8 PB1 PB1 ADDR9 PB2 PB2 ADDR10 PRS PB3 ADDR11 PB4 PB4 ADDR12 5 ADDR13 EBC PB6 ADDR14 PB7 PB7 ADDR15 PC0 PC0 ADDRO DATAO PC1 PC1 ADDR1 DATA1 2 2 ADDR2 DATA2 PC4 PC4 ADDR4 DATA4 heo PC5 ADDRB DATAS PC6 PC6 ADDR6 DATAG PC7 PC7 ADDR7 DATA7 PDO PDO RxD PD1 PD1 TxD PD2 PD2 MISO PD3 PD3 MOSI PD4 PD4 SC
229. ived as a 00 character and cause an immediate jump 4 to the start of the on chip EEPROM B600 in the MC68HC711E9 This feature is useful to pass control to a program in EEPROM essentially from reset Refer to Common Bootstrap Mode Problems before using this feature If the first character is received as FF the baud rate is assumed to be the default rate 7812 baud at a 2 MHz E clock rate If FF was sent at 1200 baud by the host the SCI will receive the character as EO or CO because of the baud rate mismatch and the bootloader will switch to 1200 baud 5 for the rest of the download operation When the baud rate is switched to 1200 baud the delay constant used to monitor the intercharacter delay also must be changed to reflect the new character time At 6 the Y index register is initialized to 0000 to point to the start of on chip RAM The index register Y is used to keep track of where the next received data byte will be stored in RAM The main loop for loading begins at 7 The number of data bytes in the downloaded program can be any number between 0 and 512 bytes the size of on chip RAM This procedure is called variable length download and is accomplished by ending the download sequence when an idle time of at least four character times occurs after the last character to be downloaded In M68HC11 Family members which have 256 bytes of RAM the download length is fixed at exactly 256 bytes plus the leading FF character The
230. k codes generated M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 111 Serial Communications Interface SCI 7 7 4 Serial Communication Status Register The SCSR provides inputs to the interrupt logic circuits for generation of the SCI system interrupt Address 102 Bit 7 6 5 4 3 2 1 Bit 0 Read TDRE TC RDRF IDLE OR NF FE Write Reset 1 1 0 0 0 0 0 0 Unimplemented Figure 7 6 Serial Communications Status Register SCSR TDRE Transmit Data Register Empty Flag This flag is set when SCDR is empty Clear the TDRE flag by reading SCSR with TDRE set and then writing to SCDR 0 SCDR busy 0 SCDR empty TC Transmit Complete Flag This flag is set when the transmitter is idle no data preamble or break transmission in progress Clear the TC flag by reading SCSR with TC set and then writing to SCDR 0 Transmitter busy 1 Transmitter idle RDRF Receive Data Register Full Flag This flag is set if a received character is ready to be read from SCDR Clear the RDRF flag by reading SCSR with RDRF set and then reading SCDR 0 SCDR empty 1 SCDR full IDLE Idle Line Detected Flag This flag is set if the RxD line is idle Once cleared IDLE is not set again until the RxD line has been active and becomes idle again The IDLE flag is inhibited when RWU 1 Clear IDLE by reading SCSR with IDLE set and then reading SCDR 0 RxD line active 1 RxD line idle
231. l or are configured as high impedance inputs pins configured as high impedance inputs have port data that is indeterminate In port descriptions an indicates this condition Port pins that are driven to a known logic level during reset are shown with a value of either 1 or 0 Some control bits are unaffected by reset Reset states for these bits are indicated with a U Freescale Semiconductor M68HC11E Family Data Sheet Rev 5 1 97 Parallel Input Output I O Ports 6 2 Port A Port A shares functions with the timer system and has Three input only pins e Three output only pins e Two bidirectional I O pins Address 1000 Bit 7 6 5 4 3 2 1 Bit 0 Pono PA7 PA4 PA3 PA2 PA1 PAO Write Reset 0 0 0 Alternate function PAI OC2 OC3 OC4 4 0 5 2 IC3 And or OC1 OC1 OC1 OC1 OC1 Indeterminate after reset Figure 6 1 Port A Data Register PORTA Address 1026 Bit 7 6 5 4 3 2 1 Bit 0 Read White DDRA7 PAEWN PAMOD PEDGE DDRA3 14 05 RTR1 RTRO Reset 0 0 0 0 0 0 0 0 Figure 6 2 Pulse Accumulator Control Register PACTL DDRAT Data Direction for Port A Bit 7 Overridden if an output compare function is configured to control the PA7 pin 0 Input 1 Output The pulse accumulator uses port A bit 7 as the PAI input but the pin can also be used as general purpose I O or as an output compare NOTE E
232. lay is required however if a stable external oscillator is being used the DLY control bit can be used to bypass this startup delay The DLY control bit is set by reset and can be optionally cleared during initialization If the DLY equal to 0 option is used to avoid startup delay on recovery from stop then reset should not be used as the means of recovering from stop as this causes DLY to be set again by reset imposing the restart delay This same delay also applies to power on reset regardless of the state of the DLY control bit but does not apply to a reset while the clocks are running M68HC11E Family Data Sheet Rev 5 1 96 Freescale Semiconductor Chapter 6 Parallel Input Output I O Ports 6 1 Introduction All M68HC11 E series MCUs have five input output I O ports and up to 38 I O lines depending on the operating mode Refer to Table 6 1 for a summary of the ports and their shared functions Table 6 1 Input Output Ports Port Input Output Bidirectional Shared Functions Pins Pins Pins Port A 3 3 2 Timer Port B 8 High order address Port C 8 Low order address and data bus Port D E _ 6 Serial communications interface SCI and serial peripheral interface SPI Port E 8 Analog to digital A D converter Port pin function is mode dependent Do not confuse pin function with the electrical state of the pin at reset Port pins are either driven to a specified logic leve
233. le OTP MCU after final assembly Another powerful use of bootstrap mode in a finished assembly is for final test Short programs can be downloaded to check parts of the system including components and circuitry external to the embedded MCU If any problems appear during product development diagnostic programs can be downloaded to find the problems and corrected routines can be downloaded and checked before incorporating them into the main application program M68HC11 Bootstrap Mode Rev 1 1 194 Freescale Semiconductor Bootstrap Mode Logic Bootstrap mode can also be used to interactively calibrate critical analog sensors Since this calibration is done in the final assembled system it can compensate for any errors in discrete interface circuitry and cabling between the sensor and the analog inputs to the MCU Note that this calibration routine is a downloaded program that does not take up space in the normal application program Bootstrap Mode Logic In the M68HC1 1 MCUS very little logic is dedicated to the bootstrap mode Consequently this mode adds almost no extra cost to the MCU system The biggest piece of circuitry for bootstrap mode is the small boot ROM This ROM is 192 bytes in the original MC68HC1 148 but some of the newest members of the M68HC11 Family such as the MC68HC711K4 have as much as 448 bytes to accommodate added features Normally this boot ROM is present in the memory map only when the MCU is reset in bootstr
234. le Semiconductor Chapter 2 Operating Modes and On Chip Memory 2 1 Introduction This section contains information about the operating modes and the on chip memory for M68HC1 1 E series MCUs Except for a few minor differences operation is identical for all devices in the E series Differences are noted where necessary 2 2 Operating Modes The values of the mode select inputs MODB and MODA during reset determine the operating mode Single chip and expanded multiplexed are the normal modes In single chip mode only on chip memory is available Expanded mode however allows access to external memory Each of the two normal modes is paired with a special mode Bootstrap a variation of the single chip mode is a special mode that executes a bootloader program in an internal bootstrap ROM Testis a special mode that allows privileged access to internal resources 2 2 4 Single Chip Mode In single chip mode ports B and C and strobe pins A STRA and B STRB are available for general purpose parallel input output I O In this mode all software needed to control the MCU is contained in internal resources If present read only memory ROM and or erasable programmable read only memory EPROM will always be enabled out of reset ensuring that the reset and interrupt vectors will be available at locations FFCO FFFF NOTE For the MC68HC81 1E2 the vector locations are the same however they are contained in the 2048 byt
235. ler unit MCU The MMDS11 provides bus state analyzer BSA and real time memory windows The unit s integrated development environment includes an editor an assembler user interface and source level debug These features significantly reduce the time necessary to develop and debug an embedded MCU system The unit s compact size requires a minimum of desk space The MMDS 11 is one component of Freescale s modular approach to MCU based product development This modular approach allows easy configuration of the 11 to fit a wide range of requirements It also reduces development system cost by allowing the user to purchase only the modular components necessary to support the particular MCU derivative MMDS 1 1 features include e Real time non intrusive in circuit emulation at the MCU s operating frequency e Real time bus state analyzer 8K x 64 real time trace buffer Display of real time trace data as raw data disassembled instructions raw data and disassembled instructions or assembly language source code Four hardware triggers for commencing trace and to provide breakpoints Nine triggering modes Asmany as 8190 pre or post trigger points for trace data 16 general purpose logic clips four of which can be used to trigger the bus state analyzer sequencer 16 bit time tag or an optional 24 bit time tag that reduces the logic clips traced from 16 to eight Four data breakpoints hardware breakpoints
236. limits to which the microcontroller unit MCU can be exposed without permanently damaging it NOTE This device is not guaranteed to operate properly at the maximum ratings Refer to 10 5 DC Electrical Characteristics 10 6 Supply Currents and Power Dissipation 10 7 MC68L11E9 E20 DC Electrical Characteristics 10 8 MC68L 11E9 E20 Supply Currents and Power Dissipation for guaranteed operating conditions Rating Symbol Value Unit Supply voltage Vpp 0 3 to 47 0 V Input voltage Vin 0 3 to 47 0 V Current drain per pin excluding Vpp Vss AVpp Vni and Ip 25 mA XIRQ Vppe Storage temperature 55 to 150 1 One pin at a time observing maximum power dissipation limits NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields however it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit For proper operation it is recommended that Vi and Vou be constrained to the range Vss Vin Or lt Vpp Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level for example either Vgg or Vpp M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 149 Electrical Characteristics 10 3 Functional Operating Range Rating Symbol Value Unit Operating temperatu
237. m M68HC11E Family Data Sheet Rev 5 1 170 Freescale Semiconductor Serial Peripheral Interface Timing Characteristics 10 17 Serial Peripheral Interface Timing Characteristics E9 E20 Num Characteristic Symbol m TES T TES Unit Frequency of operation f dc 3 0 dc 3 0 MHz E clock E clock period 333 333 ns Operating frequency Master 5 32 1 2 1128 1 2 MHz Slave fopis dc fo dc fo Cycle time 1 Master lcYC m 2 32 2 128 lcvc Slave tcyc s 1 1 ime 2 2 Enable lead time tiead s 1 zT 1 tcyc Slave Enable lag time 3 t 1 1 t Slave lag s CYC Clock SCK high time t 25 t 25 4 Master tw SCKH m 215 16 uo 64 ns Slave tw SCKH s teyc 25 25 Clock SCK low time teve 25 teve 25 5 Master tw SCKL m 16 pa 64 ns Slave tw SCKL s teyc 25 teyc 25 Data setup time inputs 6 Master tsu m 30 30 ns Slave tsu s 30 30 Data hold time inputs 7 Master thim 30 30 ns Slave this 30 30 Slave access time 8 0 ta 0 40 0 40 ns 1 0 40 0 40 Disable time hold time 9 to high impedance state ldis 50 50 ns Slave 10 Data valid after enable edge ty 50 50 ns 11 Data hold time outputs tno 0 5 0 n after enable edge 1 Vpp 5 0 10 Vss 0 TA T to Ty all timing is shown with respect to 20 Vpp a
238. mer Output Compare 3 Register Low Address 101B Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 Figure 9 10 Timer Output Compare 3 Register Pair TOC3 Register name Timer Output Compare 4 Register High Address 101C Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1 1 1 1 1 1 1 1 Register name Timer Output Compare 4 Register Low Address 1010 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 1 1 1 9 4 2 Timer Compare Force Register 1 1 1 1 Figure 9 11 Timer Output Compare 4 Register Pair 4 The CFORC register allows forced early compares FOC 1 5 correspond to the five output compares These bits are set for each output compare that is to be forced The action taken as a result of a forced compare is the same as if there were a match between the OCx register and the free running counter except that the corresponding interrupt status flag bits are not set The forced channels trigger their programmed pin actions to occur at the next timer count transition after the write to CFORC The CFORC bits should not be used on an output compare function that is programmed to toggle its output on a successful compare because a normal compare that occurs immediately before or after the force can result in an undesirable operation Address Read Write Reset Free
239. modes port C pins are multiplexed address data bus and the port C register address is treated as an external memory location Address 91003 Bit 7 6 5 4 3 2 1 Bit 0 Single chip or bootstrap modes Read PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO Write Reset Indeterminate after reset Expanded or special test modes Read ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDRO Write DATA6 DATA4 DATAS3 DATA2 DATA1 DATAO Reset Indeterminate after reset Figure 6 4 Port C Data Register PORTC Address 1005 Bit 7 6 5 4 3 2 1 Bit 0 Read PCL7 PCL6 PCL5 PCL4 PCL3 PCL2 PCL1 PCLO Write Reset Indeterminate after reset Figure 6 5 Port C Latched Register PORTCL M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 99 Parallel Input Output I O Ports PORTCL is used in the handshake clearing mechanism When an active edge occurs on the STRA pin port C data is latched into the PORTCL register Reads of this register return the last value latched into PORTCL and clear STAF flag following a read of PIOC with STAF set Address 1007 Bit 7 6 5 4 3 2 A dre DDRC7 DDRC6 DDRCS DDRC4 DDRC3 DDRC2 DDRC DDRCO Reset 0 0 0 0 0 0 Figure 6 6 Port C Data Direction Register DDRC DDRC 7 0 Port C Data Direction Bits In the 3 state variation of output han
240. mple strobed or full input handshake mode or a write to PORTCL output handshake mode 0 No edge on strobe A 1 Selected edge on strobe STAI Strobe A Interrupt Enable Mask Bit 0 STAF does not request interrupt 1 STAF requests interrupt M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor Parallel I O Control Register CWOM Port C Wired OR Mode Bit affects all eight port C pins It is customary to have an external pullup resistor on lines that are driven by open drain devices 0 Port C outputs are normal CMOS outputs 1 Port C outputs are open drain outputs HNDS Handshake Mode Bit 0 Simple strobe mode 1 Full input or output handshake mode OIN Output or Input Handshake Select Bit HNDS must be set to 1 for this bit to have meaning 0 Input handshake 1 Output handshake PLS Pulsed Interlocked Handshake Operation Bit HNDS must be set to 1 for this bit to have meaning When interlocked handshake is selected strobe B is active until the selected edge of strobe A is detected 0 Interlocked handshake 1 Pulsed handshake Strobe B pulses high for two E clock cycles EGA Active Edge for Strobe A Bit 0 STRA falling edge selected high level activates port C outputs output handshake 1 STRA rising edge selected low level activates port C outputs output handshake INVB Invert Strobe B Bit 0 Active level is logic 0 1 Active level is logic 1 M68HC11E Family Dat
241. n the PLCC socket Connect the EVBU to one of your PC COM ports Apply 5 volts to Vpp and ground to GND on the power connector of your EVBU Also take note of P4 connector 18 In step 5 you will connect a 12 volt at most 12 5 volts programming voltage through a 100 Q current limiting resistor to the XIRQ pin Do not connect this programming voltage until you are instructed to do so in step 5 Step 2 From a DOS command line prompt start PCbug11 with C PCBUG11 gt PCBUG11 E PORT 1 with the EVBU connected to COM1 C PCBUG11 gt PCBUG11 E PORT 2 with the EVBU connected to COM2 PCbug11 only supports COM ports 1 and 2 If you have made the proper connections and have a high quality cable you should quickly get a PCbug11 command prompt If you do receive a Comms fault error check your cable and board connections Most PCbug11 communications problems can be traced to poorly made cables or bad board connections Step 3 e PCbug11 defaults to base 10 for its input parameters change this to hexadecimal by typing CONTROL BASE HEX Step 4 You must declare the addresses of the EPROM array to PCbug11 To do this type EPROM D000 FFFF Step 5 You are now ready to download your program into the EPROM e Connect 12 volts at most 12 5 volts through a 100 Q current limiting resistor to P4 connector pin 18 the XIRQ pin At the PCbug11 command prompt type LOADS C MYPROG ISHERE S19 Substitute the name of
242. nal an external system that it is ready to latch data Port C logic levels are latched into PORTCL when the STRA line is asserted by the external system The MCU then negates STRB The MCU reasserts STRB after the PORTCL register is read In this mode a mix of latched inputs static inputs and static outputs is allowed on port C differentiated by the data direction bits and use of the PORTC and PORTCL registers In full output handshake mode the MCU writes data to PORTCL which in turn asserts the STRB output to indicate that data is ready The external system reads port C data and asserts the STRA input to acknowledge that data has been received In the 3 state variation of output handshake mode lines intended as 3 state handshake outputs are configured as inputs by clearing the corresponding DDRC bits The MCU writes data to PORTCL and asserts STRB The external system responds by activating the STRA input which forces the MCU to drive the data in PORTC out on all of the port C lines After the trailing edge of the active signal on STRA the MCU negates the STRB signal The 3 state mode variation does not allow part of port C to be used for static inputs while other port C pins are being used for handshake outputs Refer to the 6 8 Parallel I O Control Register for further information M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 101 Parallel Input Output I O Ports 6 8 Parallel I O Control Register The parallel hands
243. nal data bus A high on this pin indicates that a read cycle is in progress R W stays low during consecutive data bus write cycles such as a double byte store It is possible for data to be driven out of port C if internal read visibility IRV is enabled and an internal address is read even though R W is in a high impedance state Refer to Chapter 2 Operating Modes and On Chip Memory for more information about IRVNE internal read visibility not E 1 4 11 Port Signals Port pins have different functions in different operating modes Pin functions for port A port D and port E are independent of operating modes Port B and port C however are affected by operating mode Port B provides eight general purpose output signals in single chip operating modes When the microcontroller is in expanded multiplexed operating mode port B pins are the eight high order address lines Port C provides eight general purpose input output signals when the MCU is in the single chip operating mode When the microcontroller is in the expanded multiplexed operating mode port C pins are a multiplexed address data bus Refer to Table 1 1 for a functional description of the 40 port signals within different operating modes Terminate unused inputs and input output I O pins configured as inputs high or low 1 4 12 PortA In all operating modes port A can be configured for three timer input capture IC functions and four timer output compare OC functions An add
244. nd 70 Vpp unless other wise noted 2 Time to data active from high impedance state 3 Assumes 200 pF load on SCK MOSI and MISO pins M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 171 Electrical Characteristics 10 18 MC68L11E9 E20 Serial Peirpheral Interface Characteristics N 1 Symbol ESO Unit um isti mbo ni Characteristic y Min Max Min Max Frequency of operation f de 20 de 20 MHz E clock 9 E clock period 500 500 ns Operating frequency Master fop m 1 32 1 2 128 1 2 2 Slave fop s dc fo dc fo Cycle time 1 Master tcyc m 2 32 2 128 icvc Slave lcvc s 1 1 2 2 Enable lead time tlead s 1 1 Slave Enable lag time 3 t 1 1 t Slave lag s CYC Clock SCk high time t 30 t 30 4 Master tw SCKH m 16 E 64 ns ias IWSCKHs iov c 30 zi 30 i Clock SCK low time teve 30 teve 30 5 Master tw SCKL m 16 e 64 ns Slave tw SCKL s 30 teyc 30 Data setup time inputs 6 Master tsu m 40 40 ns Slave tsu s 40 40 Data hold time inputs 7 Master 40 40 ns Slave this 40 40 aasi Slave access time 8 0 ta 0 50 0 50 ns 1 0 50 0 50 Disable time hold time 9 to high impedance state ldis 60 60 ns Slave 10 Data valid after enable edge ty 60 60 ns Data hold time outputs t _
245. nding but the operation of the CPU continues uninterrupted until the bit is cleared After any reset the bit is set by default and can only be cleared by a software instruction When an interrupt is recognized the bit is set after the registers are stacked but before the interrupt vector is fetched After the interrupt has been serviced a return from interrupt instruction is normally executed restoring the registers to the values that were present before the interrupt occurred Normally the bit is 0 after a return from interrupt is executed Although the bit can be cleared within an interrupt service routine nesting interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism Refer to Chapter 5 Resets and Interrupts 4 2 6 6 Half Carry H The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit during an ADD ABA or ADC instruction Otherwise the H bit is cleared Half carry is used during BCD operations 4 2 6 7 X Interrupt Mask X The XIRQ mask X bit disables interrupts from the XIRQ pin After any reset X is set by default and must be cleared by a software instruction When an XIRQ interrupt is recognized the X and I bits are set after the registers are stacked but before the interrupt vector is fetched After the interrupt has been serviced an RTI instruction is normally executed causing the registers to be restored to the valu
246. ng general purpose I O lines The SCI frame format is initialized to an 8 bit character size The send break and receiver wakeup functions are disabled The TDRE and TC status bits in the SCI status register SCSR are both 1s indicating that there is no transmit data in either the transmit data register or the transmit serial shift register The RDRF IDLE OR NF FE and RAF receive related status bits in the SCI control register 2 SCCR2 are cleared 5 3 8 Serial Peripheral Interface SPI The SPI system is disabled by reset The port pins associated with this function default to being general purpose lines M68HC11E Family Data Sheet Rev 5 1 84 Freescale Semiconductor Reset and Interrupt Priority 5 3 9 Analog to Digital A D Converter The analog to digital A D converter configuration is indeterminate after reset The ADPU bit is cleared by reset which disables the A D system The conversion complete flag is indeterminate 5 3 10 System The EEPROM programming controls are disabled so the memory system is configured for normal read operation PSEL 3 0 are initialized with the value 960110 causing the external IRQ pin to have the highest I bit interrupt priority The IRQ pin is configured for level sensitive operation for wired OR systems The RBOOT SMOD and MDA bits in the HPRIO register reflect the status of the MODB and MODA inputs at the rising edge of reset MODA and MODB inputs select one of the four oper
247. nloading a small program to internal RAM For more information Freescale application note AN1060 entitled M68HC1 1 Bootstrap Mode has been included at the back of this document The downloadable talker will consist of Bulk erase Byte programming e Communication server All of this functionality is provided by PCbug11 which can be found on the Freescale Web site at http www freescale com For more information on using PCbug11 to program an E series device Freescale engineering bulletin EB296 entitled Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU has been included at the back of this document NOTE The CONFIG register on the 68HC11 is an EEPROM cell and must be programmed accordingly Operation of the CONFIG register in the MC68HC811E2 differs from other devices in the M68HC11 E series See Figure 2 10 and Figure 2 11 Address 103F Bit 7 6 5 4 3 2 1 Bit 0 Read NOSEC ROMON EEON Write Resets Single chip 0 0 0 0 U U 1 U Bootstrap 0 0 0 0 U U L U U Expanded 0 0 0 0 1 U U U Test 0 0 0 0 1 U L U U Unimplemented U indicates a previously programmed bit U L indicates that the bit resets to the logic level held in the latch prior to reset but the function of COP is controlled by the DISR bit in TEST1 register Figure 2 10 System Configuration Register CONFIG M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 43 O
248. ny I O pins successful compares All input capture edge detector circuits are configured for capture disabled operation The timer overflow interrupt flag and all eight timer function interrupt flags are cleared All nine timer interrupts are disabled because their mask bits have been cleared The 14 05 bit in the register is cleared to configure the 14 05 function as OC5 however the OM5 OLS control bits in the TCTL1 register are clear so OC5 does not control the pin 5 3 4 Real Time Interrupt RTI The real time interrupt flag RTIF is cleared and automatic hardware interrupts are masked The rate control bits are cleared after reset and can be initialized by software before the real time interrupt RTI system is used 5 3 5 Pulse Accumulator The pulse accumulator system is disabled at reset so that the pulse accumulator input PAI pin defaults to being a general purpose input pin 5 3 6 Computer Operating Properly COP The COP watchdog system is enabled if the NOCOP control bit in the CONFIG register is cleared and disabled if NOCOP is set The COP rate is set for the shortest duration timeout 5 3 7 Serial Communications Interface SCI The reset condition of the SCI system is independent of the operating mode At reset the SCI baud rate control register BAUD is initialized to 04 All transmit and receive interrupts are masked and both the transmitter and receiver are disabled so the port pins default to bei
249. o use bypass capacitors that have good high frequency characteristics and situate them as close to the MCU as possible Bypass requirements vary depending on how heavily the MCU pins are loaded Vpp VDD IN RESET TO RESET MC34 0 1 64 OF M68HC11 GND Vpp Vpp A E 4 7 TO RESET OF M68HC11 RESET MC34064 Vpp GND MANUAL 47 RESET SWITCH 2 IN RESET MC34164 GND OPTIONAL POWER ON DELAY AND MANUAL RESET SWITCH Figure 1 8 External Reset Circuit with Delay M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 21 General Description 1 4 2 RESET A bidirectional control signal RESET acts as an input to initialize the MCU to a known startup state It also acts as an open drain output to indicate that an internal failure has been detected in either the clock monitor or computer operating properly COP watchdog circuit The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than two E clock cycles after a reset has occurred See Figure 1 7 and Figure 1 8 CAUTION Do not connect an external resistor capacitor RC power up delay circuit to the reset pin of M68HC1 1 devices because the circuit charge time constant can cause the device to misinterpret the type of reset that occurred Because the CPU is not able to fetch and execute instructions properly when Vpp falls bel
250. o recalculate the approximate bus timing values substitute the following expressions in place of 1 8 the above formulas where applicable a 1 dc x 1 4 b dc x 1 4 tcvc Where dc is the decimal value of duty cycle percentage high time M68HC11E Family Data Sheet Rev 5 1 168 Freescale Semiconductor 10 16 MC68L11E9 E20 Expansion Bus Timing Characteristics MC68L11E9 E20 Expansion Bus Timing Characteristics Num Characteristic Symbol iene SOME Unit Min Max Min Max Frequency of operation E clock frequency fo dc 1 0 dc 2 0 MHz 1 Cycle time 1000 500 ns 2 Pulse width E low PWg 1 2 25 ns PWzg 475 225 ns 3 Pulse width E high PWey 1 2 30 ns PWg 470 220 ns 4a E and AS rise time t 25 25 ns 4b E and AS fall time 25 25 ns 9 Address hold time 2 ta 1 8 30 ns taH 95 33 ns m Non multiplexed address valid time to E rise t 275 88 M P tay PWg tagp 80 2 dd 17 Read data setup time 30 30 ns 18 Read data hold time max typ tpun 0 150 0 88 ns 19 Write data delay time tppw 1 8 tcyc 70 28 tppw 195 133 ns 21 Write data hold time 1 8 30 ns 2 95 33 ns 55 Multiplexed address valid time to E rise 568 _ 38 15 PWE tasp 90 28 ads 24 eo Woe tim
251. o satisfy the conditions of the clearing sequence M68HC11E Family Data Sheet Rev 5 1 116 Freescale Semiconductor Receiver Flags TDRE and TC flags are normally set when the transmitter is first enabled TE set to 1 The flag indicates there is room in the transmit queue to store another data character in the TDR The TIE bit is the local interrupt mask for TDRE When TIE is 0 TDRE must be polled When TIE and TDRE are 1 an interrupt is requested The TC flag indicates the transmitter has completed the queue The TCIE bit is the local interrupt mask for TC When TCIE is 0 TC must be polled When TCIE is 1 and TC is 1 an interrupt is requested Writing a O to TE requests that the transmitter stop when it can The transmitter completes any transmission in progress before actually shutting down Only an MCU reset can cause the transmitter to stop and shut down immediately If TE is written to O when the transmitter is already idle the pin reverts to its general purpose function synchronized to the bit rate clock If anything is being transmitted when TE is written to 0 that character is completed before the pin reverts to general purpose but any other characters waiting in the transmit queue are lost The TC and TDRE flags are set at the completion of this last character even though TE has been disabled 7 9 Receiver Flags The SCI receiver has five status flags three of which can generate interrupt requests The s
252. of bits resolved by A D converter 8 Bits Non linearity Maximum deviation from the ideal A D transfer __ 1 LSB characteristics Difference between the output of an ideal and an 1 LSB actual for 0 input voltage Eullscale arror Difference between the output of an ideal and an __ ay 1 LSB actual A D for full scale input voltage Total unadjusted Maximum sum of non linearity zero error and E 22 1 2 LSB error full scale error Quantization error Uncertainty because of converter resolution 11 2 LSB Difference between the actual input voltage and Absolute accuracy the full scale weighted equivalent of the binary 2 LSB output code all error sources included Conversion range Analog input voltage range VRL V Maximum analog reference voltage VRL Vpp 0 1 V VRL Minimum analog reference voltage Vss 0 1 VRH V AVR Minimum difference between Vay and 3 0 V Total time to perform a single Conversion ima analog to digital conversion E clock 32 Internal RC oscillator tcvc 32 us Conversion result never decreases with an Monotonicity increase in input voltage and has no missing Guaranteed codes Zero input reading Conversion result when Vin VRL 00 Full scale reading Conversion result when Vi FF Hex Sample acquisition Analog input acquisition sampling time E clock 12 Internal RC oscillator 12 us S
253. olt nominal programming voltage required for EPROM OTPROM programming On devices without EPROM OTPROM this pin is only an XIRQ input CAUTION During EPROM programming of the MC68HC711E9 device the Vppg pin circuitry may latch up and be damaged if the input current is not limited to 10 mA For more information please refer to MC68HC711E9 8 Bit Microcontroller Unit Mask Set Errata 3 Freescale document order number 68HC711E9MSE3 1 4 7 MODA and MODB MODA LIR and During reset MODA and MODB select one of the four operating modes Single chip mode Expanded mode Test mode Bootstrap mode Refer to Chapter 2 Operating Modes and On Chip Memory After the operating mode has been selected the load instruction register LIR pin provides an open drain output to indicate that execution of an instruction has begun A series of E clock cycles occurs during execution of each instruction The LIR signal goes low during the first E clock cycle of each instruction opcode fetch This output is provided for assistance in program debugging The pin is used to input random access memory RAM standby power When the voltage on this pin is more than one MOS threshold about 0 7 volts above the Vpp voltage the internal RAM and part of the reset logic are powered from this signal rather than the Vpp input This allows RAM contents to be retained without Vpp power applied to the MCU Reset must be driven low befor
254. olts to 5 volts and ground to GND on the programmer board s power connector P1 Applying voltage to the Vpp pin is not necessary Step 2 Apply power to the programmer board by moving the 5 volt switch to the ON position From a DOS command line prompt start PCbug11 this way e CAPCBUG11 PCBUG11 PORT 1 when the ESPGMR connected to COM1 or e CAPCBUG11 PCBUG11 PORT 2 when the E9PGMR connected to COM2 PCbug11only supports COM ports 1 and 2 Step 3 PCbug11 defaults to base ten for its input parameters Change this to hexadecimal by typing CONTROL BASE HEX Step 4 Clear the block protect register BPROT to allow programming of the MC68HC811E2 EEPROM At the PCbug11 command prompt type MS 1035 00 Step 5 PCbugl 1 defaults to a 512 byte EEPROM array located at B600 This must be changed since the EEPROM is by default located at F800 on the MC68HC81 1E2 At the PCbug11 command prompt type EEPROM 0 Then type EEPROM F800 FFFF EEPROM 103F 103F This assumes you have not relocated the EEPROM by previously reprogramming the upper 4 bits of the CONFIG register But if you have done this and your S records reside in an address range other than F800 to FFFF you will need to first relocate the EEPROM Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR Rev 0 1 234 Freescale Semiconductor To Execute the Program Step 6 Erase the CONFIG to allow programming of NOSE
255. on 152 MC68L11E9 E20 DC Electrical Characteristics 153 MC68L11E9 E20 Supply Currents and Power Dissipation 154 TImITIB 1 42504 50045 046456 4055940444109 5 0404560484005 156 MCOSLTIEQJ E20 Control etc pue do hacer cheese 157 PON TUBE cond e sade esac 162 MC68L11E9 E20 Peripheral Port Timing 163 Analog to Digital Converter 166 MC68L 11 9 20 Analog to Digital Converter Characteristics 167 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 11 Table of Contents 10 15 Expansion Bus Timing Characteristics _ REEL E 168 10 16 MC68L11E9 E20 Expansion Bus Timing Characteristics 169 10 17 Serial Peripheral Interface Timing Characteristics 171 10 18 MC68L11E9 E20 Serial Peirpheral Interface Characteristics 172 1019 EEPROM 175 10 20 MCOBLTTES E20 EEPROM Characteristics EIER 175 10 21 EPROM EKsREO XAR kiperi St 175 Chapter 11 Orde
256. operation No Operation INH 01 2 ORAA opr OR A M gt A A IMM 8A jii 2 Accumulator A DIR 9A dd 3 A Inclusive A EXT BA hh 11 4 A IND X 4 IND Y 18 AA 5 ORAB opr OR B M gt B B IMM CA jii 2 Accumulator B DIR DA 3 B Inclusive B EXT FA hh 11 4 B IND X EA ff 4 B IND Y 18 EA 5 PSHA Push A onto SIKSP SP 1 A INH 36 3 Stack PSHB Push Bonto SIKSP SP 1 B INH 37 3 Stack PSHX Push X onto IX Stk SP SP 2 INH 3C 4 Stack Lo First PSHY Push Y onto IY Stk SP SP 2 INH 18 3C 5 Stack Lo First PULA Pull A from SPZSP 1 A INH 32 4 Stack PULB Pull B from SPZSP 1 B Stk INH 33 4 Stack PULX Pull X From SPz SP 2 IX Stk INH 38 5 Stack Hi First PULY Pull Y fom SP SP 2 Stk INH 18 38 6 Stack Hi First ROL opr Rotate Left EXT 79 hh 11 6 i A A A IND X 69 6 C 07 50 IND Y 18 69 ff 7 ROLA Rotate Left A A INH 49 2 x5 lt lt b7 b0 ROLB Rotate Left B B INH 59 2 lt C b7 50 ROR Rotate Right EXT 76 hh 11 6 A A ae IND X 66 6 b7 b0 C IND Y 18 66 7 Rotate Right A INH 46 2 A Lm jo b7 b0 C RORB Rotate Right B B INH 56 2 A be o gt b7 b0 C RTI Return from See Figure 3 2 INH 3B 12 A A A A A Interrupt RTS Return from See Figure 3 2 INH 39 5 Subroutine SBA Subtract B f
257. or reference voltage pins voltages above Vpp do not cause a latchup problem although current should be limited according to maximum ratings Refer to Figure 3 2 which is a functional diagram of an input pin 3 2 2 Analog Converter Conversion of an analog input selected by the multiplexer occurs in this block It contains a digital to analog capacitor DAC array a comparator and a successive approximation register SAR Each conversion is a sequence of eight comparison operations beginning with the most significant bit MSB Each comparison determines the value of a bit in the successive approximation register The DAC array performs two functions It acts as a sample and hold circuit during the entire conversion sequence and provides comparison voltage to the comparator during each successive comparison The result of each successive comparison is stored in the SAR When a conversion sequence is complete the contents of the SAR are transferred to the appropriate result register A charge pump provides switching voltage to the gates of analog switches in the multiplexer Charge pump output must stabilize between 7 and 8 volts within up to 100 us before the converter can be used The charge pump is enabled by the ADPU bit in the OPTION register M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 57 Analog to Digital A D Converter 58 ANALOG INPUT PIN ANALOG MUX 8 BIT CAPACITIVE DAC
258. ory for more information MDA Mode Select A Bit The mode select A bit reflects the status of the MODA input pin at the rising edge of reset Refer to Chapter 2 Operating Modes and On Chip Memory for more information IRVNE Internal Read Visibility Not E Bit The IRVNE control bit allows internal read accesses to be available on the external data bus during operation in expanded modes In single chip and bootstrap modes IRVNE determines whether the E clock is driven out an external pin For the MC68HC81 1E2 this bit is IRV and only controls internal read visibility Refer to Chapter 2 Operating Modes and On Chip Memory for more information PSEL 3 0 Priority Select Bits These bits select one interrupt source to be elevated above all other I bit related sources and can be written only while the bit in the CCR is set interrupts disabled M68HC11E Family Data Sheet Rev 5 1 86 Freescale Semiconductor Table 5 3 Highest Priority Interrupt Selection PSEL 3 0 Interrupt Source Promoted 0000 0001 Timer overflow Pulse accumulator overflow 0010 Pulse accumulator input edge 0011 SPI serial transfer complete 0100 SCI serial system 0101 Reserved default to IRQ 0110 IRQ external pin or parallel 0111 Real time interrupt 1000 Timer input capture 1 1001 Timer input capture 2 1010 Timer input capture 3 1011 Timer output compare 1
259. ouse SPGMR11 Serial Programmer for M68HC11 MCUs The SPGMR11 is a modular EPROM EEPROM programming tool for all M68HC11 devices programmer features interchangeable adapters that allow programming of various M68HC11 package types Programmer features include Programs M68HC11 Family devices that contain an EPROM or EEPROM array Can be operated as a stand alone programmer connected to a host computer or connected between a host computer and the M68HC11 modular development system MMDS 1 1 station module Uses plug in programming adapters to accommodate a variety of MCU devices and packages On board programming voltage circuit eliminates the need for an external 12 volt supply Includes programming software and a user s manual Includes a 5 volt power cable and a DB9 to DB25 connector adapter 9 is a registered trademark145 of International Business Machines Corporation M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 189 Development Support M68HC11E Family Data Sheet Rev 5 1 190 Freescale Semiconductor EVBU Schematic Refer to Figure B 1 for a schematic diagram of the M68HC11EVBU Universal Evaluation Board This diagram is included for reference only M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 191 61 44S 3LL9H89IN
260. ow the minimum operating voltage level reset must be controlled A low voltage inhibit LVI circuit is required primarily for protection of EEPROM contents However since the configuration register CONFIG value is read from the EEPROM protection is required even if the EEPROM array is not being used Presently there are several economical ways to solve this problem For example two good external components for LVI reset are 1 The Seiko S0854HN or other S805 series devices a Extremely low power 2 uA a TO 92 package a Limited temperature range 20 to 70 a Available in various trip point voltage ranges 2 The Freescale MC34064 a TO 92 or SO 8 package a Draws about 300 uA a Temperature range 40 C to 85 C a Well controlled trip point a Inexpensive Refer to Chapter 5 Resets and Interrupts for further information 1 4 3 Crystal Driver and External Clock Input XTAL and EXTAL These two pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry The frequency applied to these pins is four times higher than the desired E clock rate The XTAL pin must be left unterminated when an external CMOS compatible clock input is connected to the EXTAL pin The XTAL output is normally intended to drive only a crystal Refer to Figure 1 9 and Figure 1 10 CAUTION In all cases use caution around the oscillator pins Load capacitances shown in the os
261. perating Modes and On Chip Memory Address Read Write Resets Single chip Bootstrap Expanded Test 103F Bit 7 6 5 4 3 2 1 Bit 0 EE3 EE2 EE1 EEO NOSEC NOCOP EEON 1 1 1 1 U U 1 1 1 1 1 1 U U L 1 1 U U U U 1 U 1 U U U U U 1 U L 1 0 Unimplemented U indicates a previously programmed bit U L indicates that the bit resets to the logic level held in the latch prior to reset but the function of COP is controlled by the DISR bit in TEST1 register Figure 2 11 MC68HC811E2 System Configuration Register CONFIG EE 3 0 EEPROM Mapping Bits EE 3 0 apply only to MC68HC811E2 and allow the 2048 bytes of EEPROM to be remapped to any 4 Kbyte boundary See Table 2 3 Table 2 3 EEPROM Mapping 44 EE 3 0 EEPROM Location 0000 0800 0FFF 0001 1800 1FFF 0010 2800 2FFF 0011 3800 3FFF 0100 4800 4FFF 0101 5800 5FFF 0110 6800 6FFF 0111 7800 7FFF 1000 8800 8FFF 1001 9800 9FFF 1010 A800 AFFF 1011 B800 BFFF 1100 C800 CFFF 1101 D800 DFFF 1110 E800 EFFF 1111 F800 FFFF M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor NOSEC Security Disable Bit NOSEC is invalid unless the security mask option is specified before the MCU is manufactured If the security mask option is omitted NOSEC always reads 1 The enhanced security feature is available
262. put high voltage 0 5 Vpp 3 0 V Vpop 0 8 nM V 0 8 Vpp 4 5 V All outputs except XTAL RESET and MODA Output low voltage 1 6 Vpp 5 0V V lLoad 1 0 Vpp 3 0 V OL ae V All outputs except XTAL Input high voltage All inputs except RESET ViH 0 7 xVpp Vpp 0 3 V RESET 0 8 x Vpp Vpp 0 3 Input low voltage all inputs Vi Vss 0 3 0 2 x Vpp V ports 3 state leakage Vin Vin OF Vi PA7 PC 7 0 PD 5 0 AS STRA ies i ah MODA LIR RESET Input leakage current Vin Vpp or Vss d 1 A PA 2 0 IRQ XIRQ E MODBNVsrpy XIRQ on EPROM based devices i RAM standby voltage power down 2 0 Vpp V RAM standby current power down Isp mE 10 Input __ PA 2 0 PE 7 0 IRQ XIRQ EXTAL m l 8 pF 7 PC 7 0 PD 5 0 AS STRA MODA LIR RESET 12 Output load capacitance All outputs except PD 4 1 90 PD 4 1 100 1 3 0 Vdc to 5 5 Vss 0 TA T to Ty unless otherwise noted 2 specification for RESET and MODA is not applicable because they are open drain pins specification not appli cable to ports C and D in wired OR mode 3 Refer to 10 13 Analog to Digital Converter Characteristics and 10 14 MC68L11E9 E20 Analog to Digital Converter Char acteristics for leakage current for port E M68HC11E Family Data Sheet Rev 5 1 Frees
263. quency E clock period 1000 500 333 ns Peripheral data setup time t EN m MCU read of ports A C D and E 199 100 100 du Peripheral data hold time t a MCU read of ports A C D and E REM 30 59 M iz Delay time peripheral data write tPwp 1 4 teyct 100 ns t ns MCU writes to port A PWD 200 200 200 MCU writes to ports B C and D 350 225 183 Port C input data setup time tis 60 60 60 ns Port C input data hold time 100 100 100 ns Delay time E fall to STRB tpEB 1 4 lcyc 100 ns DEB 350 225 183 s Setup time STRA asserted to fall lAES 0 0 0 ns Delay time STRA asserted to port C data output valid tPcp 100 100 100 ns Hold time STRA negated to port C data 10 10 10 ns 3 state hold time 150 150 150 ns 1 Vpp 5 0 10 Vss 0 TA to Ty all timing is shown with respect to 20 Vpp and 70 Vpp unless otherwise noted 2 Ports C and D timing is valid for active drive CWOM and DWOM bits are not set in PIOC and SPCR registers respec tively 3 If this setup time is met STRB acknowledges in the next cycle If it is not met the response may be delayed one more cycle M68HC11E Family Data Sheet Rev 5 1 162 Freescale Semiconductor MC68L11E9 E20 Peripheral Port Timing 10 12 MC68L11E9 E20 Peripheral Port Timing
264. r Low TIC1L See page 132 Timer Input Capture 2 Register High TIC2H See page 132 Timer Input Capture 2 Register Low TIC2L See page 132 Timer Input Capture 3 Register High TIC3H See page 132 Timer Input Capture 3 Register Low TIC3L See page 132 Timer Output Compare 1 Register High TOC1H See page 134 Timer Output Compare 1 Register Low TOC1L See page 134 Timer Output Compare 2 Register High TOC2H See page 134 Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Read Write Reset Memory Map Bit 7 6 5 4 3 2 1 Bit 0 OC1D6 0 105 OC1D4 OC1D3 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit15 Bit14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit15 Bit14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Indeterminate after reset B
265. r enabled PAMOD Pulse Accumulator Mode Bit 0 Event counter 1 Gated time accumulation PEDGE Pulse Accumulator Edge Control Bit This bit has different meanings depending on the state of the PAMOD bit as shown in Table 9 7 Table 9 7 Pulse Accumulator Edge Control PAMOD PEDGE Action on Clock 0 0 PAI falling edge increments the counter 0 1 PAI rising edge increments the counter 1 0 A 0 on PAI inhibits counting 1 1 A 1 on PAI inhibits counting DDRAS3 Data Direction for Port A Bit Refer to Chapter 6 Parallel Input Output I O Ports 14 05 Input Capture 4 Output Compare 5 Bit 0 Output compare 5 function enable no IC4 1 Input capture 4 function enable no 5 RTR 1 0 RTI Interrupt Rate Select Bits Refer to 9 5 Real Time Interrupt RTI M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 145 Timing Systems 9 7 2 Pulse Accumulator Count Register This 8 bit read write register contains the count of external input events at the PAI input or the accumulated count The PACNT is readable even if PAI is not active in gated time accumulation mode The counter is not affected by reset and can be read or written at any time Counting is synchronized to the internal PH2 clock so that incrementing and reading occur during opposite half cycles Address 1027 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 B
266. r supply is required to program on chip EPROM The simplest way to use this utility program is to bootload a 3 byte program consisting of a single jump instruction to the start of the PROGRAM utility program BF00 The bootloader program sets the X and Y index registers to default values before jumping to the downloaded program see 16 at the bottom of Figure 3 When the host computer sees the FF character data to be programmed into the EPROM is sent starting with the character for location 0000 After the last byte to be programmed is sent to the MC68HC711E9 and the corresponding verification data is returned to the host the programming operation is terminated by resetting the MCU The number of bytes to be programmed the first address to be programmed and the programming time can be controlled by the user if values other than the default values are desired To understand the detailed operation of the EPROM programming utility refer to Figure 4 during the following discussion Figure 4 is composed of three interrelated parts The upper left portion shows the flowchart of the PROGRAM utility running in the boot ROM of the MCU The upper right portion shows the flowchart for the user supplied driver program running in the host computer The lower portion of Figure 4 is a timing sequence showing the relationship of operations between the MCU and the host computer Reference numbers in the flowcharts in the upper half of Figure 4 have matching num
267. rammable parts you will need to try again with a new unprogrammed device Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU Rev 0 1 Freescale Semiconductor 239 Programming Procedure Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU Rev 0 1 240 Freescale Semiconductor How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2
268. re range T to Ty MC68HC 7 11Ex 0 to 70 MC68HC 7 11ExC 40 to 85 MC68HC 7 11ExV 40 to 105 MC68HC 7 11ExM T 40 to 125 MC68HC811E2 0 to 70 MC68HC811E2C 40 to 85 MC68HC81 1E2V 40 to 105 MC68HC81 1E2M 40 to 125 MC68L11Ex 20 to 70 Operating voltage range Vpp 5 0 10 V 10 4 Thermal Characteristics Characteristic Symbol Value Unit Average junction temperature Tj Pp x Oya C Ambient temperature User determined Package thermal resistance junction to ambient 48 pin plastic DIP MC68HC81 1E2 only 50 56 pin plastic SDIP o 50 5 52 pin plastic leaded chip carrier 50 SM 52 pin plastic thin quad flat pack TQFP 85 64 pin quad flat pack 85 Pint Total power dissipation Pp 273 w Device internal power dissipation PINT Ipp X Vpp w pin power dissipation User determined Pp x Ta 273 C 3 K A constant Pp 1 This is an approximate value neglecting 2 For most applications lt and be neglected 3 is a constant pertaining to the device Solve for with a known T4 and a measured Pp at equilibrium Use this value of to solve for Pp and TJ iteratively for any value of TA M68HC11E Family Data Sheet Rev 5 1 150 Freescale Semiconductor 10 5 DC Electrical Characteristics Characteristics Symbol DC Electrical Characteristics Min
269. read only status indicator and bit 6 which always reads as 0 Write to ADCTL to initiate a conversion To quit a conversion in progress write to this register and a new conversion sequence begins immediately Address 1030 Bit 7 6 5 4 3 2 1 Bit 0 Read CCF SCAN MULT CD CC CB CA Write Reset 0 0 Indeterminate after reset Unimplemented Figure 3 5 A D Control Status Register ADCTL CCF Conversion Complete Flag A read only status indicator this bit is set when all four A D result registers contain valid conversion results Each time the ADCTL register is overwritten this bit is automatically cleared to 0 and a conversion sequence is started In the continuous mode CCF is set at the end of the first conversion sequence Bit 6 Unimplemented Always reads 0 SCAN Continuous Scan Control Bit M68HC11E Family Data Sheet Rev 5 1 62 Freescale Semiconductor A D Control Status Register When this control bit is clear the four requested conversions are performed once to fill the four result registers When this control bit is set conversions are performed continuously with the result registers updated as data becomes available MULT Multiple Channel Single Channel Control Bit When this bit is clear the A D converter system is configured to perform four consecutive conversions on the single channel specified by the four channel select bits CD CA bits 3 0 of the ADC
270. rence voltage Vss 0 1 VRH V AVR Minimum difference between Vg and 2 3 V Conversion Total time to perform a single A D conversion t ine E clock 32 p Internal RC oscillator tcvc 32 teyct 32 iis Monotonicit Conversion result never decreases with an y increase in input voltage has no missing codes Full scale i It when Vin V reading Conversion result when Vi Vay FF FF Hex Sample Analog input acquisition sampling time t acquisition E clock 12 Fa time Internal RC oscillator 12 12 us Sample hold Input capacitance during sample p capacitance PE 7 0 20 typical pF Input leakage on A D pins Input leakage PE 7 0 400 400 nA 1 0 1 0 uA 1 5 0 10 Vss 0 T to 750 kHz lt E lt 3 0 MHz unless otherwise noted 2 Source impedances greater than 10 kQ affect accuracy adversely because of input leakage 3 Performance verified down to 2 5 V AVg but accuracy is tested and guaranteed at AVg 5 V 10 M68HC11E Family Data Sheet Rev 5 1 166 Freescale Semiconductor MC68L11E9 E20 Analog to Digital Converter Characteristics 10 14 MC68L11E9 E20 Analog to Digital Converter Characteristics Characteristic Parameter Min Absolute Max Unit Resolution Number
271. reset and interrupt process Figure 5 5 illustrates how the CPU begins from a reset and how interrupt detection relates to normal opcode fetches Figure 5 6 is an expansion of a block in Figure 5 5 and illustrates interrupt priorities Figure 5 7 shows the resolution of interrupt sources within the SCI subsystem 5 6 Low Power Operation Both stop mode and wait mode suspend CPU operation until a reset or interrupt occurs Wait mode suspends processing and reduces power consumption to an intermediate level Stop mode turns off all on chip clocks and reduces power consumption to an absolute minimum while retaining the contents of the entire RAM array 5 6 1 Wait Mode The WAI opcode places the MCU in wait mode during which the CPU registers are stacked and CPU processing is suspended until a qualified interrupt is detected The interrupt can be an external IRQ an XIRQ or any of the internally generated interrupts such as the timer or serial interrupts The on chip crystal oscillator remains active throughout the wait standby period The reduction of power in the wait condition depends on how many internal clock signals driving on chip peripheral functions can be shut down The CPU is always shut down during wait While in the wait state the address data bus repeatedly runs read cycles to the address where the CCR contents were stacked The MCU leaves the wait state when it senses any interrupt that has not been masked The free running timer
272. ring Information and Mechanical Specifications dolo lo TE 177 11 2 Standard Device Ordering Information 177 11 3 Custom ROM Device Ordering 1 179 11 4 Extended Voltage Device Ordering Information 3 0 Vdc to 5 5 Vdc 181 11 5 52 Plastic Leaded Chip Carrier Case 778 182 11 6 52 Windowed Ceramic Leaded Chip Carrier Case 778 183 11 7 64 Pin Quad Flat Pack Case 8400C Lube te pe rte e PES PACK IPIPEC I EVER RES RES 184 118 52 Pin Thin Quad Flat Pack Case 8480 185 11 9 56 Pin Dual in Line Package Case 859 186 11 10 48 Pin Plastic DIP Case TP 186 Appendix Development Support A 1 aqa 187 A 2 M68HC11 E Series Development Tools 187 A3 EVS Evaluation 187 4 Modular Development System MMDS11 188 A5 SPGMH11 Serial Programmer for M68HC11 189 Appendix B EVBU Schematic AN1060 M68HC11 Bootstrap Mode Liao x qoae en OR e e C Re 193 EB184 Enabling the Security Feature
273. rnal EEPROM and monitor programming and erase operations This technique could be utilized by an end user to load program information into the EPROM or EEPROM of an M68HC11 before it is installed into an end product As in the burn in setup many 68 1 1s can be gang programmed in parallel This technique can also be used to program the EPROM of finished products after final assembly Freescale also uses bootstrap mode for programming target devices on the M68HC1 1 evaluation modules EVM Because bootstrap mode is a privileged mode like special test the EEPROM based configuration register CONFIG can be programmed using bootstrap mode on the EVM The greatest benefits from bootstrap mode are realized by designing the finished system so that bootstrap mode can be used after final assembly The finished system need not be a single chip mode application for the bootstrap mode to be useful because the expansion bus can be enabled after resetting the MCU in bootstrap mode Allowing this capability requires almost no hardware or design cost and the addition of this capability is invisible in the end product until it is needed The ability to control the embedded processor through downloaded programs is achieved without the disassembly and chip swapping usually associated with such control This mode provides an easy way to load non volatile memories such as EEPROM with calibration tables or to program the application firmware into a one time programmab
274. rom A B gt A INH 10 2 A A A A 76 M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor Table 4 2 Instruction Set Sheet 6 of 7 Instruction Set M ti D ipti Addressing Instruction Condition Codes Mode Opcode Operand Cycles X HII N Z vVI C SBCA opr Subtract with 82 jii 2 Carry from A DIR 92 3 A EXT B2 hh 11 4 A IND X A2 Jff 4 A IND Y 18 A2 ff 5 SBCB opr Subtract with C2 jii 2 Carry from B B DIR 02 3 B EXT F2 hh 11 4 B IND X E2 4 B IND Y 18 E2 5 SEC Set Carry 1 oD 2 1 SEI Set Interrupt 1 1 INH OF 2 1 Mask SEV Set Overflow 12V INH 0B 2 1 Flag STAA opr Store AM A DIR 97 3 UII A 0 Accumulator A EXT B7 hh 11 4 A A IND X A7 4 A IND Y 18 A7 f 5 STAB opr Store BM B DIR 07 3 LT um A 0 Accumulator B EXT F7 hh 11 4 B B IND X E7 ff 4 B IND Y 18 E7 5 STD opr Store A gt M B gt M 1 DIR DD 4 E A A 0 xd Accumulator EXT FD hh 11 5 D IND X ED ff 5 IND Y 18 ED ff 6 STOP Stop Internal INH CF 2 Clocks STS opr Store Stack SP gt M M 1 DIR 9F dd 4 SS oS A A 0 Pointer EXT BF hh 11 5 IND X AF ff 5 IND Y 18 AF ff 6 STX opr Store Index IX2M M 1 DIR DF 4 gm A A 0
275. rpose input and others are being used as A D inputs PORTE should not be read during the sample portion of an A D conversion Address 100 Bit 7 6 5 4 3 2 1 Bit 0 Read PE7 PE6 PE5 PE4 PE3 PE2 PE1 PEO Write Reset Indeterminate after reset Alternate Function AN7 AN6 AN5 AN4 AN3 AN2 AN1 ANO Figure 6 9 Port E Data Register PORTE 6 7 Handshake Protocol Simple and full handshake input and output functions are available on ports B and C pins in single chip mode In simple strobed mode port B is a strobed output port and port C is a latching input port The two activities are available simultaneously The STRB output is pulsed for two E clock periods each time there is a write to the PORTB register The INVB bit in the PIOC register controls the polarity of STRB pulses Port C levels are latched into the alternate port C latch PORTCL register on each assertion of the STRA input STRA edge select flag and interrupt enable bits are located in the PIOC register Any or all of the port C lines can still be used as general purpose I O while strobed input mode Full handshake modes use C pins and the STRA and STRB lines Input and output handshake modes are supported and output handshake mode has a 3 stated variation STRA is an edge detecting input and STRB is a handshake output Control and enable bits are located in the PIOC register In full input handshake mode the MCU asserts STRB to sig
276. rt D pins 0 Normal CMOS outputs 1 Open drain outputs M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 123 Serial Peripheral Interface SPI MSTR Master Mode Select Bit It is customary to have an external pullup resistor on lines that are driven by open drain devices 0 Slave mode 1 Master mode CPOL Clock Polarity Bit When the clock polarity bit is cleared and data is not being transferred the SCK pin of the master device has a steady state low value When CPOL is set SCK idles high Refer to Figure 8 2 and 8 4 Clock Phase and Polarity Controls CPHA Clock Phase Bit The clock phase bit in conjunction with the CPOL bit controls the clock data relationship between master and slave The CPHA bit selects one of two different clocking protocols Refer to Figure 8 2 and 8 4 Clock Phase and Polarity Controls SPR 1 0 SPI Clock Rate Select Bits These two bits select the SPI clock SCK rate when the device is configured as master When the device is configured as slave these bits have no effect Refer to Table 8 1 Table 8 1 SPI Clock Rates Divide Frequency at Frequencyat Frequencyat Frequency at SPR 1 0 E Clock B E 1 MHz E 2 MHz E 3 MHz 4 MHz y Baud Baud Baud Baud 00 2 500 kHz 1 0 MHz 1 5 MHz 2 MHz 01 250 kHz 500 kHz 750 kHz 1 MHz 10 16 62 5 kHz 125 kHz 187 5 kHz 250 kHz 11 32 31 3 kHz 62 5 kHz 93 8 kHz
277. rt D pins except the PD1 TxD pin are configured as high impedance inputs Any port D pin that normally is used as an output should have a pullup resistor so it does not float during the bootloading process M68HC11 Bootstrap Mode Rev 1 1 204 Freescale Semiconductor Driving Boot Mode from Another M68HC11 Driving Boot Mode from Another M68HC11 A second M68HC1 1 system can easily act as the host to drive bootstrap loading of an M68HC11 MCU This method is used to examine and program non volatile memories in target M68HC11s in Freescale EVMs The following hardware and software example will demonstrate this and other bootstrap mode features The schematic in Figure 6 shows the circuitry for a simple EPROM duplicator for the MC68HC711E9 The circuitry is built in the wire wrap area of an M68HC11EVBU evaluation board to simplify construction The schematic shows only the important portions of the EVBU circuitry to avoid confusion To see the complete EVBU schematic refer to the M68HC11EVBU Universal Evaluation Board User s Manual Freescale document order number M68HC11EVBU D The default configuration of the EVBU must be changed to make the appropriate connections to the circuitry in the wire wrap area and to configure the master MCU for bootstrap mode A fabricated jumper must be installed at J6 to connect the XTAL output of the master MCU to the wire wrap connector P5 which has been wired to the EXTAL input of the target MCU Cut traces th
278. rts the sleeping receivers to wake up and evaluate the initial character of the new message Two methods of wakeup are available Idle line wakeup e Address mark wakeup During idle line wakeup a sleeping receiver awakens as soon as the RxD line becomes idle In the address mark wakeup logic 1 in the most significant bit MSB of a character wakes up all sleeping receivers 7 5 1 Idle Line Wakeup To use the receiver wakeup method establish a software addressing scheme to allow the transmitting devices to direct a message to individual receivers or to groups of receivers This addressing scheme can take any form as long as all transmitting and receiving devices are programmed to understand the same scheme Because the addressing information is usually the first frame s ina message receivers that are not part of the current task do not become burdened with the entire set of addressing frames All receivers are awake RWU 0 when each message begins As soon as a receiver determines that the message is not intended for it software sets the RWU bit RWU 1 which inhibits further flag setting until the RxD line goes idle at the end of the message As soon as an idle line is detected by receiver logic hardware automatically clears the RWU bit so that the first frame of the next message can be received This type of receiver wakeup requires a minimum of one idle line frame time between messages and no idle time between frames in a message
279. rupt Enable Bit 0 RTIF interrupts disabled 1 Interrupt requested when RTIF set to 1 PAOVI Pulse Accumulator Overflow Interrupt Enable Bit Refer to 9 7 Pulse Accumulator PAII Pulse Accumulator Input Edge Bit Refer to 9 7 Pulse Accumulator Bits 3 2 Unimplemented Always read 0 PR 1 0 Timer Prescaler Select Bits Refer to Table 9 4 NOTE Bits in TMSk2 correspond bit for bit with flag bits in TFLG2 Bits in TMSK2 enable the corresponding interrupt sources M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor Timing Systems 9 5 2 Timer Interrupt Flag Register 2 Bits of this register indicate the occurrence of timer system events Coupled with the four high order bits of TMSK2 the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven system Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position Address 1025 Bit 7 6 5 4 3 2 1 Bit 0 Read RTIF PAOVF PAIF Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 22 Timer Interrupt Flag 2 Register TFLG2 Clear flags by writing a 1 to the corresponding bit position s TOF Timer Overflow Interrupt Flag Set when TCNT changes from FFFF to 0000 RTIF Real Time Interrupt Flag The RTIF status bit is automatically set to 1 at the end of every RTI period To clear RTIF write a byte to TFLG2 with bit 6 set PAOVF Pulse Accumulator Overflow In
280. s 0 Contents of register shown inside parentheses Is transferred to ft Is pulled from stack U Is pushed onto stack Boolean AND Arithmetic addition symbol except where used as inclusive OR symbol in Boolean formula e Exclusive OR Multiply Concatenation Arithmetic subtraction symbol or negation symbol two s complement Condition Codes Bit not changed Bit always cleared Bit always set Bit cleared or set depending on operation Bit can be cleared cannot become set M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor Chapter 5 Resets and Interrupts 5 1 Introduction Resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched A reset immediately stops execution of the current instruction and forces the program counter to a known starting address Internal registers and control bits are initialized so the MCU can resume executing instructions An interrupt temporarily suspends normal program execution while an interrupt service routine is being executed After an interrupt has been serviced the main program resumes as if there had been no interruption 5 2 Resets The four possible sources of reset are Power on reset POR External reset RESET Computer operating properly COP reset Clock monitor reset POR and RESET share the normal reset vector COP reset and the clock monitor reset eac
281. s slightly higher than Vpp therefore resistors R14 and R15 are less critical No data to be programmed is passed to the target MCU until the master MCU senses that Vpp has been stable for about 200 ms When Vpp is ready the master MCU turns on the red LED light emitting diode and begins passing data to the target MCU EPROM Programming Utility explains the activity as data is sent from the master MCU to the target MCU and programmed into the EPROM of the target The master MCU in the EVBU corresponds to the HOST in the programming utility description and the PROGRAM utility in MCU is running in the bootstrap ROM of the target MCU Each byte of data sent to the target is programmed and then the programmed location is read and sent back to the master for verification If any byte fails the red and green LEDs are turned off and the programming operation is aborted If the entire 12 Kbytes are programmed and verified successfully the red LED is turned off and the green LED is turned on to indicate success The programming of all 12 Kbytes takes about 30 seconds After a programming operation the Vpp switch S2 should be turned off before the EVBU power is turned off M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 207 Listing 1 MCU to MCU Duplicator Program Yop CUT TRACE AS SHOWN RN1D 47K TOMCU XIRQ 4 18 26 i pe o FROM OCS PIN 9 0 459000 5 18 o 410045 2 OF MCU 522 o R
282. scale Semiconductor Unimplemented Figure 9 12 Timer Compare Force Register CFORC M68HC11E Family Data Sheet Rev 5 1 100B Bit 7 6 5 4 3 2 1 Bit 0 FOC1 FOC2 FOC3 FOC4 FOC5 0 0 0 0 0 0 0 0 135 Timing Systems FOC 1 5 Force Output Comparison Bit When the FOC bit associated with an output compare circuit is set the output compare circuit immediately performs the action it is programmed to do when an output match occurs 0 Not affected 1 Output x action occurs Bits 2 0 Unimplemented Always read 0 9 4 3 Output Compare Mask Register Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1 compare The bits of the OC1M register correspond to PA 7 3 Address 100 Bit 7 6 5 4 3 2 1 Bit 0 Read 1 7 1 6 1 5 OC1M4 OC1M3 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 13 Output Compare 1 Mask Register OC1M OC1M 7 3 Output Compare Masks 0 OC1 disabled 1 OC1 enabled to control the corresponding pin of port A Bits 2 0 Unimplemented Always read 0 9 4 4 Output Compare Data Register Use this register with OC1 to specify the data that is to be stored on the affected pin of port A after a successful OC1 compare When a successful OC1 compare occurs a data bit in OC1D is stored in the corresponding bit of port A for each bit that is set in OC1M Address 10
283. secured part would be used Special bootstrap mode is used to disengage the security function only after the contents of EEPROM and RAM have been erased Refer to the M68HC 11 Reference Manual Freescale document order number M68HC11RM AD for additional information on the security mode and complete listings of the boot ROMs that support the EEPROM security functions Automatic Selection of Baud Rate The bootloader program in the MC68HC711E9 accommodates either of two baud rates e The higher of these baud rates 7812 baud at a 2 MHz E clock rate is used in systems that operate from a binary frequency crystal such as 223 Hz 8 389 MHz At this crystal frequency the baud rate is 8192 baud which was used extensively in automotive applications The second baud rate available to the M68HC11 bootloader is 1200 baud at a 2 MHz E clock rate Some of the newest versions of the M68HC11 including the MC68HC11F1 and MC68HC117K4 accommodate other baud rates using the same differentiation technique explained here Refer to the reference numbers in square brackets in Figure 2 during the following explanation NOTE Software can change some aspects of the memory map after reset M68HC11 Bootstrap Mode Rev 1 1 196 Freescale Semiconductor Automatic Selection of Baud Rate Figure 2 shows how the bootloader program differentiates between the default baud rate 7812 baud at a 2 MHz E clock rate and the alternate baud rate 1200 baud at a 2 MHz
284. state of systems and control bits with the state of these systems and control bits when a bootloaded program in RAM starts Between these times the bootloader program is executed which changes the states of some systems and control bits The SCI system 15 initialized and turned on Rx and Tx The SCI system has control of the PDO and PD1 pins Port D outputs are configured for wire OR operation The stack pointer is initialized to the top of RAM Time has passed two or more SCI character times Timer has advanced from its reset count value Users also forget that bootstrap mode is a special mode Thus privileged control bits are accessible and write protection for some registers is not in effect The bootstrap ROM is in the memory map The DISR bit in the TEST1 control register is set which disables resets from the COP and clock monitor systems Since bootstrap is a special mode these conditions can be changed by software The bus can even be switched from single chip mode to expanded mode to gain access to external memories and peripherals M68HC11 Bootstrap Mode Rev 1 1 218 Freescale Semiconductor VIOYOLOW o t eH 090LNV poN densioog LLOHS9IN 6Lc MC68HC811E2 MC68SEC811E2 MC68HC11E0 0000 1 FF MC68HC11E1 0000 1FF MC68HC11E9 0000 1FF MC68SEC11E9 0000 1FF MC68HC711E9 41 MC68HC11F1 42 B 0000 FEO0 0000 3FF Table 2 Summary of Boot ROM Related Features BOOT RO
285. stem crashes The illegal opcode trap mechanism works for all unimplemented opcodes on all four opcode map pages The address stacked as the return address for the illegal opcode interrupt is the address of the first byte of the illegal opcode Otherwise it would be almost impossible to determine whether the illegal opcode had been one or two bytes The stacked return address can be used as a pointer to the illegal opcode so the illegal opcode service routine can evaluate the offending opcode M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 89 Resets and Interrupts 5 5 4 Software Interrupt SWI SWI is an instruction and thus cannot be interrupted until complete SWI is not inhibited by the global mask bits in the Because execution of SWI sets the mask bit once an SWI interrupt begins other interrupts are inhibited until SWI is complete or until user software clears the bit in the CCR 5 5 5 Maskable Interrupts The maskable interrupt structure of the MCU can be extended to include additional external interrupt sources through the IRQ pin The default configuration of this pin is a low level sensitive wired OR network When an event triggers an interrupt a software accessible interrupt flag is set When enabled this flag causes a constant request for interrupt service After the flag is cleared the service request is released 5 5 6 Reset and Interrupt Processing Figure 5 5 and Figure 5 6 illustrate the
286. sume program with instruction which follows the STOP instruction STOP STOP FFF2 FFF3 NEW ENEKE 1 Edge Sensitive IRQ pin IRQE bit 1 2 Level sensitive IRQ pin IRQE bit 0 3 tsTOPDELAY 4064 if DLY bit 1 or 4 if DLY 0 4 XIRQ with X bit in CCR 1 5 IRQ or XIRQ with X bit in CCR 0 Figure 10 4 STOP Recovery Timing Diagram 023 631 11899IN 091 Jojonpuooluleg 4 L S q us 3LL9H89IN IRQ XIRQ OR INTERNAL INTERRUPTS ADDRESS PCL YL YH XL XH STACK REGISTERS RW Note RESET also causes recovery from WAIT Figure 10 5 WAIT Recovery from Interrupt Timing Diagram 9 e9293 40jonpuooluJeg ejeoseaJ4 LOL Lg 4S 4 3LL9H99IN lt lt PWira IRQ 2 XIRA OR INTERNAL INTERRUPT ADDRESS pata Kotte AI ste RM Nf Notes ite 1 Edge sensitive IRQ pin IRQE bit 1 2 Level sensitive IRQ pin IRQE bit 0 Figure 10 6 Interrupt Timing Diagram 10409 023 631 11899IN Electrical Characteristics 10 11 Peripheral Port Timing 1 2 1 0 2 2 0 2 3 0 2 zi E mbo ni Characterietie Y Min Max Min Max Min Max Frequency of operation fo dc 10 dc 20 dc 3 0 MHz E clock fre
287. system is shut down only if the bit is set to 1 and the COP system is disabled by NOCOP being set to 1 Several other systems also can be in a reduced power consumption state depending on the state of software controlled configuration control bits Power consumption by the analog to digital A D converter is not affected significantly by the wait condition However the A D converter current can be eliminated by writing the ADPU bit to 0 The SPI system is enabled or disabled by the SPE control bit The SCI transmitter is enabled or disabled by the TE bit and the SCI receiver is enabled or disabled by the RE bit Therefore the power consumption in wait is dependent on the particular application M68HC11E Family Data Sheet Rev 5 1 90 Freescale Semiconductor Low Power Operation HIGHEST PRIORITY POWER ON RESET POR Y DELAY 4064 E CYCLES EXTERNAL RESET CLOCK MONITOR FAIL WITH CME 1 LOWEST PRIORITY COP WATCHDOG TIMEOUT WITH NOCOP 0 Y LOAD PROGRAM COUNTER LOAD PROGRAM COUNTER LOAD PROGRAM COUNTER WITH CONTENTS OF WITH CONTENTS OF WITH CONTENTS OF SFFFE SFFFF SFFFC FFFD SFFFA SFFFB VECTOR FETCH VECTOR FETCH VECTOR FETCH SET BITS I AND X y RESET MCU HARDWARE BEGIN INSTRUCTION SEQUENCE Y BIT X IN 1 N XIRQ Y PIN LOW N Figure 5 5 Processing Flow Out of Reset Sheet 1 of 2
288. t be enabled by setting the CSEL bit in the OPTION register for EEPROM programming and erasure when the E clock frequency is below 1 0 MHz 10 20 MC68L11E9 E20 EEPROM Characteristics Temperature Range 2 1 Characteristic 20 to 70 C Unit Programming time 3 V E lt 2 0 MHz RCO enabled 25 ms 5 V E lt 2 0 MHz RCO enabled 10 Erase time byte row and bulk 3 V E lt 2 0 MHz RCO enabled 25 ms 5 V Ex 2 0 MHz RCO enabled 10 Write erase endurance 10 000 Cycles Data retention 10 Years T Vpp 3 0 to 5 5 Vdc Vss 0 Vdc TL to Ty 2 The RC oscillator RCO must be enabled by setting the CSEL bit in the OPTION register for EEPROM programming and erasure 10 21 EPROM Characteristics Characteristics Symbol Min Typ Max Unit Programming voltage VPPE 11 75 12 25 12 75 V Programming current 3 10 mA Programming time tEPROG 2 2 4 ms 1 Vpp 5 0 10 2 During EPROM programming of the MC68HC711E9 device the Vppg circuitry may latch up and be damaged if the input current is not limited to 10 mA For more information please refer to MC68HC711E9 8 Bit Microcontroller Unit Mask Set Errata 3 Freescale document order number 68HC711E9MSE3 3 Typically a 1 kQ series resistor is sufficient to limit the programming current for the MC68HC711E9 100 Q series resis tor is sufficient to limit the programming current for th
289. t be set in the variable BOOTCOUNT in line 25 M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 213 Driving Boot Mode from a Personal Computer Operation Configure the EVBU for boot mode operation by putting a jumper at J3 Ensure that the trace command jumper at J7 is not installed because this would connect the 12 V programming voltage to the OC5 output of the MCU Connect the EVBU to its dc power supply When it is time to program the MCU EPROM turn on the 12 volt programming power supply to the new circuitry in the wire wrap area Connect the EVBU serial port to the appropriate serial port on the host system For the Macintosh this is the modem port with a modem cable For the MS DOS computer itis connected to COM1 with a straight through or modem cable Power up the host system and start the BASIC program If the program has not been compiled this is accomplished from within the appropriate BASIC compiler or interpreter Power up the EVBU Answer the prompt for filename with either a RETURN to accept the default shown or by typing in a new filename and pressing RETURN The program will inform the user that it is working on converting the file from S records to binary This process will take from 30 seconds to a few minutes depending on the computer A prompt reading Comm port open will appear at the end of the file conversion This is the last chance to ensure that everything is properly configured on the
290. t circuit that permits pacing the execution of software routines by selecting one of four interrupt rates The COP watchdog clock input E 215 is tapped off of the free running counter chain The COP automatically times out unless it is serviced within a specific time by a program reset sequence If the COP is allowed to time out a reset is generated which drives the RESET pin low to reset the MCU and the external system Refer to Table 9 1 for crystal related frequencies and periods M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 127 Timing Systems OSCILLATOR AND CLOCK GENERATOR DIVIDE BY FOUR PRESCALER 2 4 16 32 SPR 1 0 PRESCALER 1 3 4 13 SCP 1 0 PRESCALER 1 4 8 16 PR 1 0 IC OC SCP2 present on MC68HC 7 11E20 only Figure 9 1 Timer Clock Divider Chains 128 PRESCALER 1 2 4 128 SCR 2 0 PRESCALER 1 2 4 8 RTR 1 0 PRESCALER 1 4 16 64 CR 1 0 CLEAR COP SYSTEM TIMER RESET M68HC11E Family Data Sheet Rev 5 1 AS E CLOCK INTERNAL BUS CLOCK PH2 SPI SCI RECEIVER CLOCK SCI TRANSMIT CLOCK PULSE ACCUMULATOR REAL TIME INTERRUPT FORCE O COP RESET E SERIES TIM DIV CHAIN Freescale Semiconductor Table 9 1 Timer Summary XTAL Frequencies 4 0 MHz 8 0 MHz 12 0 MHz Other Rates Control Bits 1 0 MHz 2 0 MHz 3 0 MHz E PR1 PRO 1000 ns 500 ns 333 ns 1 E Main Timer Count Rates 00 1 count
291. t of stop mode is bypassed and the resumes processing within about four bus cycles 1 A delay of approximately 4000 E clock cycles is imposed as the MCU is started up from the stop power saving mode This delay allows the crystal oscillator to stabilize CME Clock Monitor Enable Bit Refer to Chapter 5 Resets and Interrupts Bit 2 Not implemented Always reads 0 CR 1 0 COP Timer Rate Select Bits The internal E clock is divided by 21 before it enters the COP watchdog system These control bits determine a scaling factor for the watchdog timer Refer to Chapter 5 Resets and Interrupts 2 4 EPROM OTPROM Certain devices in the M68HC11 E series include on chip EPROM OTPROM For instance e The MC68HC711E9 devices contain 12 Kbytes of on chip EPROM OTPROM in non windowed package The MC68HC711E20 has 20 Kbytes of EPROM OTPROM in non windowed package The MC68HC711E32 has 32 Kbytes of EPROM OTPROM in non windowed package Standard MC68HC71E9 and MC68HC711E20 devices are shipped with the EPROM OTPROM contents erased all 1s The programming operation programs zeros Windowed devices must be erased using a suitable ultraviolet light source before reprogramming Depending on the light source erasing can take from 15 to 45 minutes Using the on chip EPROM OTPROM programming feature requires an external 12 volt nominal power supply Vppg Normal programming is accomplished using the EPROM OTPROM programming register
292. tatus flags are set by the SCI logic in response to specific conditions in the receiver These flags can be read polled at any time by software Refer to Figure 7 10 which shows SCI interrupt arbitration When an overrun takes place the new character is lost and the character that was in its way in the parallel RDR is undisturbed RDRF is set when a character has been received and transferred into the parallel RDR The OR flag is set instead of RDRF if overrun occurs A new character is ready to be transferred into RDR before a previous character is read from RDR The NF and FE flags provide additional information about the character in the RDR but do not generate interrupt requests The last receiver status flag and interrupt source come from the IDLE flag The RxD line is idle if it has constantly been at logic 1 for a full character time The IDLE flag is set only after the RxD line has been busy and becomes idle which prevents repeated interrupts for the whole time RxD remains idle M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 117 Serial Communications Interface SCI BEGIN FLAG Y 1 Qe lt 999 Y NO VALID SCI REQUEST VALID SCI REQUEST Figure 7 10 Interrupt Source Resolution Within SCI M68HC11E Family Data Sheet Rev 5 1 118 Freescale Semiconductor Chapter 8 Serial Peripheral Interface SPI 8 1 Introduct
293. ted Always reads 0 ELAT EPROM OTPROM Latch Control Bit When ELAT 1 writes to EPROM cause address and data to be latched and the EPROM OTPROM cannot be read ELAT can be read any time ELAT can be written any time except when PGM 1 then the write to ELAT is disabled 0 EPROM OTPROM address and data bus configured for normal reads 1 EPROM OTPROM address and data bus configured for programming EXCOL Select Extra Columns Bit 0 User array selected 1 User array is disabled and extra columns are accessed at bits 7 0 Addresses use bits 13 5 and bits 4 0 are don t care EXCOL can be read and written only in special modes and always returns in normal modes EXROW Select Extra Rows Bit 0 User array selected 1 User array is disabled and two extra rows are available Addresses use bits 7 0 and bits 13 8 are don t care EXROW can be read and written only in special modes and always returns 0 in normal modes T 1 0 EPROM Test Mode Select Bits These bits allow selection of either gate stress or drain stress test modes They can be read and written only in special modes and always read 0 in normal modes T1 TO Function Selected 0 0 Normal mode 0 1 Reserved 1 0 Gate stress 1 1 Drain stress M68HC11E Family Data Sheet Rev 5 1 50 Freescale Semiconductor EEPROM PGM EPROM Programming Voltage Enable Bit can be read any time and can be written only when ELAT 1
294. ter name Timer Output Compare 1 Register High Address 1016 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 Register name Timer Output Compare 1 Register Low Address 1017 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 Figure 9 8 Timer Output Compare 1 Register Pair TOC1 Register name Timer Output Compare 2 Register High Address 1018 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 Register name Timer Output Compare 2 Register Low Address 1019 Bit 7 6 5 4 3 2 1 Bit 0 Read j Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 Figure 9 9 Timer Output Compare 2 Register Pair TOC2 M68HC11E Family Data Sheet Rev 5 1 134 Freescale Semiconductor Register name Timer Output Compare 3 Register High Read Write Reset Read Write Reset Read Write Reset Read Address 101A Output Compare Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1 1 1 1 1 1 1 1 Register name Ti
295. terrupt Flag Refer to 9 7 Pulse Accumulator PAIF Pulse Accumulator Input Edge Interrupt Flag Refer to 9 7 Pulse Accumulator Bits 3 0 Unimplemented Always read 0 9 5 3 Pulse Accumulator Control Register Bits RTR 1 0 of this register select the rate for the RTI system The remaining bits control the pulse accumulator and IC4 OC5 functions Address 1026 Bit 7 6 5 4 3 2 1 Bit 0 Read WS DDRA7 PAEN PAMOD PEDGE DDRA3 14 05 RTR1 RTRO rite Reset 0 0 0 0 0 0 0 0 Figure 9 23 Pulse Accumulator Control Register PACTL DDRA7 Data Direction for Port A Bit 7 Refer to Chapter 6 Parallel Input Output I O Ports PAEN Pulse Accumulator System Enable Bit Refer to 9 7 Pulse Accumulator PAMOD Pulse Accumulator Mode Bit Refer to 9 7 Pulse Accumulator M68HC11E Family Data Sheet Rev 5 1 142 Freescale Semiconductor Computer Operating Properly COP Watchdog Function PEDGE Pulse Accumulator Edge Control Bit Refer to 9 7 Pulse Accumulator DDRAS3 Data Direction for Port A Bit Refer to Chapter 6 Parallel Input Output I O Ports 14 05 Input Capture 4 Output Compare Bit Refer to 9 7 Pulse Accumulator RTR 1 0 RTI Interrupt Rate Select Bits These two bits determine the rate at which the RTI system requests interrupts The RTI system is driven by an E divided by 213 rate clock that is compensated so it is independent of the timer prescaler These two
296. till char received Leading char for bootload to target MCU Point at program for target Bootload to target Past end Continue till all sent BRK to allow boot related before clearing of 6 cyc loops 3 3 Total loop time 6 cyc Read status RDRF will be set Read SCI data reg to clear RDRF arget to indicate it s ready for ROM FF Wait for RDRF Clear RDRF don t need data Point at start of EPROM Delay counter about 200ms Turn off RED LED 3 Wait for Vpp to be ON 3 Vpp sense is on port E MSB 6 Turn on RED LED 4 3 Total loop time 19 cyc LDY EPSTRT X Tx pointer Y verify pointer BSR SEND1 Send first data to target DATALP CPX 0 X points at 0000 after last BEQ VERF Skip send if no more BSR SEND1 Send another data char VERF BRCLR SCSR RDRF VERF Wait for Rx ready LDAA SCDR Get char and clr RDRF CMPA 0 Y Does char verify BEQ VERFOK Skip error if OK BCLR PORTB RED GREEN Turn off LEDs BRA DUNPRG Done programming failed VERFOK INY Advance verify pointer BNE DATALP Continue till all done BSET PORTB GREEN Grn LED ON M68HC11 Bootstrap Mode Rev 1 1 Freescale Semiconductor 209 Listing 1 MCU to MCU Duplicator Program 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 B666 B666 B669 B66B B66B B66D B671 B673 B674 B675 B677 B67A B67D 150482 20FE A600 132E80FC 972 08 39 8604 71028 7EBFOO
297. tion is executed The RTS pulls the previously stacked return address from the stack and loads it into the program counter Execution then continues at this recovered return address When an interrupt is recognized the current instruction finishes normally the return address the current value in the program counter is pushed onto the stack all of the CPU registers are pushed onto the stack and execution continues at the address specified by the vector for the interrupt M68HC11E Family Data Sheet Rev 5 1 66 Freescale Semiconductor CPU Registers At the end of the interrupt service routine an return from interrupt RTI instruction is executed The RTI instruction causes the saved registers to be pulled off the stack in reverse order Program execution resumes at the return address Certain instructions push and pull the A and B accumulators and the X and Y index registers and are often used to preserve program context For example pushing accumulator A onto the stack when entering a subroutine that uses accumulator A and then pulling accumulator A off the stack just before leaving the subroutine ensures that the contents of a register will be the same after returning from the subroutine as it was before starting the subroutine JSR JUMP TO SUBROUTINE RTI RETURN FROM INTERRUPT
298. to 70 3 MHz MC68HC1 1E9PB3 2 MHz MC68HC11E9CPB2 40 to 85 Custom ROM 3 MHz MC68HC11E9CPB3 40 to 105 C 2 MHz MC68HC11E9VPB2 40 to 125 C 2 MHz MC68HC11E9MPB2 56 pin dual in line package with 0 70 inch lead spacing SDIP 0 to 70 3 MHz MC68HC11E9B3 2 MHz MC68HC11E9CB2 40 to 85 C Custom ROM 3 MHz MC68HC11E9CB3 40 to 105 C 2 MHz MC68HC11E9VB2 40 to 125 C 2 MHz MC68HC11E9MB2 M68HC11E Family Data Sheet Rev 5 1 180 Freescale Semiconductor Extended Voltage Device Ordering Information 3 0 Vdc to 5 5 Vdc 11 4 Extended Voltage Device Ordering Information 3 0 Vdc to 5 5 Vdc Description Temperature Frequency MC Order Number 52 pin plastic leaded chip carrier PLCC Custom ROM 2 MHz im Heli No ROM eoe 2 MHz MC68L11E1FN2 No ROM no EEPROM 2MHz MC68L11E0FN2 64 pin quad flat pack QFP Custom ROM 2 MHz i e MR re NOS 2 MHz MC68L11E1FU2 No ROM no EEPROM 2 MHz MC68L11E0FU2 52 pin thin quad flat pack 10 mm x 10 mm Custom ROM 2 MHz MC68L11E9PB2 No ROM 20 to 70 C 2 MHz MC68L11E1PB2 No ROM no EEPROM 2MHz MC68L11E0PB2 56 pin dual in line package with 0 70 inch lead spacing SDIP Custom ROM 2 MHz MC68L11E9B2 No ROM 20 to 70 C 2 MHz MC68L11E1B2 No ROM no EEPROM 2 MHz MC68L11E0B2 M68HC11E Family Data Sheet Rev 5 1 Freescale Semicondu
299. tor 51 Operating Modes and On Chip Memory Address 1035 Bit 7 6 5 4 3 2 1 Bit 0 Read BPRT3 BPRT2 BPRT1 BPRTO Write Reset 0 0 0 1 1 1 1 1 Unimplemented Figure 2 16 Block Protect Register BPROT Bits 7 5 Unimplemented Always read 0 PTCON Protect CONFIG Register Bit 0 CONFIG register can be programmed or erased normally 1 CONFIG register cannot be programmed or erased BPRT 3 0 Block Protect Bits for EEPROM When set these bits protect a block of EEPROM from being programmed or electronically erased Ultraviolet light however can erase the entire EEPROM contents regardless of BPRT 3 0 windowed packages only Refer to Table 2 6 and Table 2 7 When cleared BPRT 3 0 allow programming and erasure of the associated block Table 2 6 EEPROM Block Protect Bit Name Block Protected Block Size BPRTO B600 B61F 32 bytes BPRT1 B620 B65F 64 bytes BPRT2 B660 B6DF 128 bytes B6E0 B7FF 288 bytes Table 2 7 EEPROM Block Protect in MC68HC811E2 MCUs Bit Name Block Protected Block Size x800 x9FF 512 bytes BPRT1 xAO00 xBFF 512 bytes BPRT2 xC00 xDFF 512 bytes BPRT3 xE00 xFFF 512 bytes 1 x is determined by the value of EE 3 0 in CONFIG register Refer to Figure 2 13 M68HC11E Family Data Sheet Rev 5 1 52 Freescale Semiconductor EEPROM
300. ts The timer prescaler control bits are included in this register Address 1024 Bit 7 6 5 4 3 2 1 Bit 0 Read TOI RTII PAOVI PR1 PRO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 19 Timer Interrupt Mask 2 Register TMSK2 TOI Timer Overflow Interrupt Enable Bit 0 TOF interrupts disabled 1 Interrupt requested when TOF is set to 1 RTII Real Time Interrupt Enable Bit Refer to 9 5 Real Time Interrupt RTI PAOVI Pulse Accumulator Overflow Interrupt Enable Bit Refer to 9 7 3 Pulse Accumulator Status and Interrupt Bits PAII Pulse Accumulator Input Edge Interrupt Enable Bit Refer to 9 7 3 Pulse Accumulator Status and Interrupt Bits Bits 3 2 Unimplemented Always read 0 PR 1 0 Timer Prescaler Select Bits These bits are used to select the prescaler divide by ratio In normal modes PR 1 0 can be written only once and the write must be within 64 cycles after reset Refer to Table 9 1 and Table 9 4 for specific timing values Table 9 4 Timer Prescale PR 1 0 Prescaler 00 1 01 4 10 8 11 16 NOTE Bits in TMSK2 correspond bit for bit with flag bits in TFLG2 Bits in TMSK2 enable the corresponding interrupt sources M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 139 Timing Systems 9 4 10 Timer Interrupt Flag Register 2 Bits in this register indicate when certain timer system events have o
301. ts can be assigned the highest maskable interrupt priority by writing the appropriate value to the PSEL bits in the HPRIO register Otherwise the priority arrangement remains the same An interrupt that is assigned highest priority is still subject to global masking by the bit in the CCR or by any associated local bits Interrupt vectors are not affected by priority assignment To avoid race conditions HPRIO can be written only while I bit interrupts are inhibited 5 4 1 Highest Priority Interrupt and Miscellaneous Register Address 103 Bit 7 6 5 4 3 2 1 Bit 0 Read Wes RBOOT swoD MDA IRVNE PSEL2 PSEL2 PSELO Reset Single chip 0 0 0 0 0 1 1 0 Expanded 0 0 1 0 0 1 1 0 Bootstrap 1 1 0 0 0 1 1 0 Special test 0 1 1 1 0 1 1 0 1 The values of the RBOOT SMOD and MDA reset bits depend on the mode selected at the RESET pin rising edge Refer to Table 2 1 Hardware Mode Select Summary Figure 5 4 Highest Priority I Bit Interrupt and Miscellaneous Register HPRIO RBOOT Read Bootstrap ROM Bit Has meaning only when the SMOD bit is a 1 bootstrap mode or special test mode At all other times this bit is clear and cannot be written Refer to Chapter 2 Operating Modes and On Chip Memory for more information SMOD Special Mode Select Bit This bit reflects the inverse of the MODB input pin at the rising edge of reset Refer to Chapter 2 Operating Modes and On Chip Mem
302. unit ALU performs a carry or borrow during an arithmetic operation The C bit also acts as an error flag for multiply and divide operations Shift and rotate instructions operate with and through the carry bit to facilitate multiple word shift operations 4 2 6 2 Overflow V The overflow bit is set if an operation causes an arithmetic overflow Otherwise the V bit is cleared 4 2 6 3 Zero Z The 7 bit is set if the result of an arithmetic logic or data manipulation operation 1 0 Otherwise the Z bit is cleared Compare instructions do an internal implied subtraction and the condition codes including Z reflect the results of that subtraction A few operations INX DEX INY and DEY affect the Z bit and no other condition flags For these operations only and z conditions can be determined 4 2 6 4 Negative N The N bit is set if the result of an arithmetic logic or data manipulation operation is negative MSB 1 Otherwise the N bit is cleared A result is said to be negative if its most significant bit MSB is a 1 A quick way to test whether the contents of a memory location has the MSB set is to load it into an accumulator and then check the status of the N bit M68HC11E Family Data Sheet Rev 5 1 68 Freescale Semiconductor Data Types 4 2 6 5 Interrupt Mask 1 The interrupt request IRQ mask I bit is a global mask that disables all maskable interrupt sources While the I bit is set interrupts can become pe
303. up of four channels is converted one time each The first result is stored in A D result register 1 ADR1 and the fourth result is stored in ADR4 After the fourth conversion is complete all conversion activity is halted until a new conversion command is written to the ADCTL register 2 When SCAN 1 conversions continue to be performed on the selected group of channels with the fifth conversion being stored in register ADR1 replacing the earlier conversion result for the first channel in the group the sixth conversion overwriting ADR2 and so on 3 8 Operation in Stop and Wait Modes If a conversion sequence is in progress when either the stop or wait mode is entered the conversion of the current channel is suspended When the MCU resumes normal operation that channel is resampled and the conversion sequence is resumed As the MCU exits wait mode the A D circuits are stable and valid results can be obtained on the first conversion However in stop mode all analog bias currents are disabled and it is necessary to allow a stabilization period when leaving stop mode If stop mode is exited with a delay DLY 1 there is enough time for these circuits to stabilize before the first conversion If stop mode is exited with no delay DLY bit in OPTION register 0 allow 10 ms for the A D circuitry to stabilize to avoid invalid results 3 9 A D Control Status Register All bits in this register can be read or written except bit 7 which is a
304. ven when port A bit 7 is configured as an output the pin still drives the input to the pulse accumulator PAEN Pulse Accumulator System Enable Bit Refer to Chapter 9 Timing Systems PAMOD Pulse Accumulator Mode Bit Refer to Chapter 9 Timing Systems PEDGE Pulse Accumulator Edge Control Bit Refer to Chapter 9 Timing Systems DDRAS3 Data Direction for Port A Bit 3 This bit is overridden if an output compare function is configured to control the pin 0 Input 1 Output 14 O5 Input Capture 4 Output Compare 5 Bit Refer to Chapter 9 Timing Systems RTR 1 0 RTI Interrupt Rate Select Bits Refer to Chapter 9 Timing Systems M68HC11E Family Data Sheet Rev 5 1 98 Freescale Semiconductor Port B 6 3 Port B In single chip or bootstrap modes port B pins are general purpose outputs In expanded or special test modes port B pins are high order address outputs Address 1004 Bit 7 6 5 4 3 2 1 Bit 0 Single chip or bootstrap modes Read 7 6 5 4 PB2 PB1 PBO Write Reset 0 0 0 0 0 0 0 0 Expanded or special test modes Read Wis ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 rite Reset 0 0 0 0 0 0 0 0 Figure 6 3 Port B Data Register PORTB 6 4 In single chip and bootstrap modes pins reset to high impedance inputs DDRC bits are set to 0 In expanded and special test
305. when the bootloader firmware starts and this break character can be fed back to the RxD pin to cause the jump to EEPROM Since TxD is configured as an open drain output a pullup resistor is required FF Character Is Required before Loading into RAM The initial character usually FF that sets the download baud rate is often forgotten Original M68HC11 Versions Required Exactly 256 Bytes to be Downloaded to RAM Even users that know about the 256 bytes of download data sometimes forget the initial FF that makes the total number of bytes required for the entire download operation equal to 256 1 or 257 bytes Variable Length Download When on chip RAM surpassed 256 bytes the time required to serially load this many characters became more significant The variable length download feature allows shorter programs to be loaded without sacrificing compatibility with earlier fixed length download versions of the bootloader The end of a download is indicated by an idle RxD line for at least four character times If a personal computer is being used to send the download data to the MCU there can be problems keeping characters close enough together to avoid tripping the end of download detect mechanism Using 1200 as the baud rate rather than the faster default rate may help this problem Assemblers often produce S record encoded programs which must be converted to binary before bootloading them to the MCU The process of reading S record data from
306. ws the A D converter to select one of 16 analog signals Eight of these channels correspond to port E input lines to the MCU four of the channels are internal reference points or test functions and four channels are reserved Refer to Table 3 1 Table 3 1 Converter Channel Assignments Channel Channel Result in ADRx Number Signal if MULT 1 1 ANO ADR1 AN1 ADR2 3 AN2 ADR3 4 ADR4 5 AN4 ADR1 6 AN5 ADR2 7 ADR3 8 AN7 ADR4 9 12 Reserved 13 Vg ADR1 14 VRL ADR2 15 Vgp 2 ADR3 16 Reserved ADR4 1 Used for factory testing 3 6 Single Channel Operation The two types of single channel operation are 1 When SCAN the single selected channel is converted four consecutive times The first result is stored in A D result register 1 ADR1 and the fourth result is stored ADR4 After the fourth conversion is complete all conversion activity is halted until a new conversion command is written to the ADCTL register 2 When SCAN 1 conversions continue to be performed on the selected channel with the fifth conversion being stored in register ADR1 overwriting the first conversion result the sixth conversion overwriting ADR2 and so on M68HC11E Family Data Sheet Rev 5 1 Freescale Semiconductor 61 Analog to Digital A D Converter 3 7 Multiple Channel Operation The two types of multiple channel operation are 1 When SCAN 0 a selected gro
307. y Currents and Power Dissipation Title 154 changed to include the MC68L11E20 10 10 MC68L11E9 E20 Control Timing Title changed to include the 157 MC68L11E20 10 12 MC68L 11E9 E20 Peripheral Port Timing Title changed to include the 163 MC68L11E20 July 2002 4 10 14 MC68L11E9 E20 Analog to Digital Converter Characteristics Title 167 changed to include the MC68L11E20 10 16 MC68L11E9 E20 Expansion Bus Timing Characteristics Title 169 changed to include the MC68L11E20 10 18 MC68L11E9 E20 Serial Peirpheral Interface Characteristics Title 172 changed to include the MC68L11E20 Title changed to include the MC68L11E20 175 11 4 Extended Voltage Device Ordering Information 3 0 Vdc to 5 5 Vdc 181 Updated table to include MC68L 1120 Format updated to current publications standards Throughout 1 4 6 Non Maskable Interrupt XIRQ VPPE Added Caution note pertaining 23 to EPROM programming of the MC68HC711E9 device only June 2003 5 6 4 Port C Clarified description of DDRC 7 0 bits 100 10 21 EPROM Characteristics Added note pertaining to EPROM 175 programming of the MC68HC711E9 device only July 2005 5 1 Updated to meet Freescale identity guidelines Throughout M68HC11E Family Data Sheet Rev 5 1 4 Freescale Semiconductor List of Chapters Chapter T General Deseription sasawa wa w mr sede need sees sand 13 Chapter 2 Operating Modes and On Chip
308. y Data Sheet Rev 5 1 6 Freescale Semiconductor Table of Contents Chapter 1 General Description 1 1 i 1 2 uuu ee ee 1 3 ciuili NCC UM 1 4 aub wis Tn 1 4 1 Vss a ae qued We ie are Rm ee den ee ae 1 4 2 ae red eee eee i idis ee eee 1 4 3 Crystal Driver and External Clock Input XTAL and EXTAL 1 4 4 ce d ES T ere eeepc eet susu usupa ares 1 4 5 Interrupt Request IRQ 1 4 6 Non Maskable Interrupt 1 4 7 MODA and MODB MODA LIR and 1 4 7 1 VnL and qp wwe e bad xod x wd ob d wq Badd 4 1 4 8 Lider keda d kl ad dolo 1 4 9 cilii MER eee 1 4 10 za susya estu eee isnt s uix ai ik c itte 1 4 10 1 EP 1 4 10 2 1 4 10 3 1 4 10 4 ENT ET 1 4 10 5 PENES LL abr Ed Chapter 2 Operating Modes and On Chip Memory 2 1 MONON aua ER dedu HORAE dapib dd d PCR E Red 2 2 22 1 Si gle Ghip Mod 445544 et Ps
309. ycles after reset Table 5 1 COP Timer Rate Select Divid XTAL 4 0 MHz XTAL 8 0 MHz XTAL 12 0 MHz 16 0 MHz e i CR 1 0 E 215 B Timeout Timeout Timeout Timeout y 0 ms 32 8 ms 0 ms 16 4 ms 0 ms 10 9 ms 0 ms 8 2 ms 00 1 32 768 ms 16 384 ms 10 923 ms 8 19 ms 01 4 131 072 ms 65 536 ms 43 691 ms 32 8 ms 10 16 524 28 ms 262 14 ms 174 76 ms 131 ms 11 64 2 098 s 1 049 s 699 05 ms 524 ms E 1 0 MHz 2 0 MHz 3 0 MHz 4 0 MHz M68HC11E Family Data Sheet Rev 5 1 80 Freescale Semiconductor Resets Address 103A Bit 7 6 5 4 3 2 1 Bit 0 Read BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Write Reset 0 0 0 0 0 0 0 0 Figure 5 1 Arm Reset COP Timer Circuitry Register COPRST Complete this 2 step reset sequence to service the COP timer 1 Write 55 to COPRST to arm the COP timer clearing mechanism 2 Write AA to COPRST to clear the COP timer Performing instructions between these two steps is possible as long as both steps are completed in the correct sequence before the timer times out 5 2 4 Clock Monitor Reset The clock monitor circuit is based on an internal resistor capacitor RC time delay If no MCU clock edges are detected within this RC time delay the clock monitor can optionally generate a system reset The clock monitor function is enabled or disabled by the CME control bit in the OPT
310. your program into the command above Use a full path name if your program is not located in the same directory as PCbug11 Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU Rev 0 1 238 Freescale Semiconductor Programming Procedure Step 6 After the programming operation is complete PCbug11 will display this message Total bytes loaded xxxx Total bytes programmed yyyy You should now remove the programming voltage from P4 connector 18 the XIRQ pin Each ORG directive in your assembly language source will cause a pair of these lines to be generated For this operation yyyy will be incremented by the size of each block of code programmed into the EPROM of the MC68HC711E9 e PCbug11 will display the above message whether or not the programming operation was successful As a precaution you should have PCbug11 verify your code Atthe PCbug11 command prompt type VERF C MYPROG ISHERE S19 Substitute the name of your program into the command above Use a full path name if your program is not located in the same directory as PCbug11 If the verify operation fails a list of addresses which did not program correctly is displayed Should this occur you probably need to erase your part more completely To do so allow the MC68HC711E9 to sit for at least 45 minutes under an ultraviolet light source Attempt the programming operation again If you have purchased devices in plastic packages one time prog

M68HC11E Family Data Sheet

Contents

Download Pdf Manuals

Related Search

Related Contents