Fast and Accurate Simulation of the Steady-State of
Contents
1. Scholar Expert Savage Scout Dragon Maverick Guardian Envoy LISA ExpertViews and SFLM are trademarks of Silvaco International The Simulation Standard Page 10 October 2004 Hints Tips and Solutions Colin Shaw Applications and Support Engineer Noise Simulations Introduction A customer had 3 devices with identical current and voltage applied A W L 10um 2um M 4 B W L 40um 2um M 1 C W L 10um 2um 4 devices in parallel 1 Ifthe MOS model file has the parameters noia noib noic Af Kf and nlev 0 will SmartSpice ignore the BSIM III noise parameters noia noib and noic and simply use AK and KF There are various ways to calculate noise if the model card includes the key word nlev then pa rameters Af amp Kf are used If this key word does not appear in the model card then the parameters noia noib and noic are used 2 Ifsmartspice does ignore noia noib noic when nlev is set to nlev 0 then why do these three cases I have in the netlist not have the same identical noise flickernoise KF ids NLEV 0 Cox Leff f flickernoise KF ids NLEV 1 Cox Leff Weff f flickernoise KF gm NLEV 2 or greater Cox Leff Weff f F If I is the current feed to each case A B C then For A ids I 4 For each device B ids I a c ids I s 4 If AF 1 then 4 Ips f Ip 4 1 Case A B C 4 4 October 2004 Then yes the noise level for all 3 c2. 1 2 The number of elementary charges e in the SET island Figure 1 a is supposed to be n 1 0 or 1 This model detailed elsewhere 4 is built on this assumption and the periodicity of the current I V the average I current Figure 2 b is determined as a function of the V and V voltage the temperature and the offset charges q COTE AC RT Y TOTAU 7 t PACT TY COLEEN eetCceOlO eee Cceaeiaaleete aa Ceqqleelttege CO tea a a SPELL SLES SRE SPL i 4a Paes GSS Fe XY gt ETATE INS N OET RERE d 2 alta ey eo eseas te Ce fi 2 t eee oct C3 F PPETI IT TA Bing Steg airs SOS A ite te te teier he oF CREAT UIT n ie RRO ERT PC i 2 ae i if si R 2 A Cig ie Cente CN een fee Cafe WY Figure 1 a Schematic representation of a Single Electron Transistor b Example of current calculated with our model The blockade regions diamond shape can be clearly distinguished The Simulation Standard October 2004 Figure 2 a Example of relative error between MC simulation and our model in the V x 5 e K5 bs Ves diagram In the central region the ac curacy is better than 1 5 b Theoretical limits of validity of our model which correspond to the MC results We have checked that in the dynamic or static regime the difference between ourmodel and MC simulation Figure 2 is less that 1 5 for IV s lt 2e C C C C C
3. Plenum Press 1992 2 K K Likharev Proc of the IEEE Vol 87 Issue 4 pp 606 632 Apr 1999 3 C Le Royer et al Proc of ESSDERC Florence Italy pp 403 406 24 26 Sept 2002 4 C Le Royer PhD Thesis Joseph Fourier University Grenoble France 17 Oct 2003 The Simulation Standard 5 H Inokawa A Fujiwara and Y Takahashi DRC Conference Di gest pp 129 130 2001 6 H Inokawa A Fujiwara and Y Takahashi IEDM pp 147 150 20071 7 A N Korotkov et al Appl Phys Lett Vol 68 N 14 pp 1954 1956 1996 8 C Wasshuber H Kosina S Selberherr Trans Computer Aided Design of Integrated Circuits and Systems Vol 44 pp 937 944 Aug 1997 9 K Uchida etal Jpn J Appl Phys Part 1 Vol 39 N 4 pp 2321 2324 30 Apr 2000 10 S Mahapatra et al IEEE Electron Device Lett Vol 23 N 6 pp 366 368 Jun 2002 11 SmartSpice User s manual Volume 2 Silvaco Data Systems Santa Clara 2002 Voltages V 0 1 0 15 time ms Figure 7 Simulation of the quantizer operation The output voltage V with a staircase shape with respect to the stability points corresponds to the sampling of the triangular voltage V October 2004 A Sophisticated Verilog A Debugger During the elaboration of a Verilog A model debugging a module can be very useful for detecting non physi cal behavior or fine tuning the model The SILVACO Verilog A debugger has been des
4. Silvaco International Inc All Rights Reserved 1 Debug A Build A Output TRANS time 0n Ln 963 Col 1 Interactive Workbench v 1 16 0 Silvaco 2004 Figure 1 Debugger window layout insertion in the Verilog A code using insert remove breakpoint button amp In the first method a break point condition can be set in the condition field This condition can be of several kinds it can include logical relational bitwise shift and arithmetical operators as well as mathematical and simulation related functions shown in Table 1 realtime function can be of a great help for debugging a model on a given time range Supposing now that the Bulk Drain diode current value of a BSIM4 device has to be checked for a time gt 190 ns A breakpoint is set in View breakpoints window at line 2878 the end of the bulk diodes calculations The condition for this breakpoint entered in next figure stops the simulation during a transient analysis if time gt 190 ns The other breakpoints are removed using Delete button in the same window Figure 4 Page 7 bsim4 va adder in x 2690 endcase R 2691 end 2692 end 2693 ff Rae e ee eae oe ak eae ae ee ae ae ae ake ake ale ske akak eae ee ae ae eae ff 2694 ee End of initial step 2695 ff Ra eee te eae ae ake ae she ake ee ae ale ae ake ake oe ake ak ae aleak aese akak ae ate as ff 2696 2697 jeer Calculation of all equations
5. Table 1 gives a comparison of the CPU time between HOSCIL and TRAN depending on the number of sweeping points The speedup is significant even for a single run since HOSCIL computes directly the steady state in the fre Eile Edit View Chart Tools Object Help Oe 6 ee SAS E Aa alARmi Se l l a a e iat Ag u e M in e Legend meas1 tosc X in Y 9472K Vector meas1 fose Figure 4 Oscillation frequency tuning quency domain For parametric simulations with a high number of sweeping points the performance improve ment is even more important Furthermore HOSCIL analysis proposes an efficient small signal noise analysis around the oscillator steady state allowing the extraction of phase noise which is a crictical figure of merit of modern oscillator designs 5 Conclusion In this paper the advantages of the new harmonic bal ance based method HOSCIL for the simulation of oscillators included in SmartSpice RE have been dem onstrated It is definetly more reliable and much faster than regular transient approaches for applications like VCO frequency tuning and it allows easy and accurate phase noise extraction 6 References 1 E Ngoya A Suarez R Sommet R Quere Steady State Analysis of Free or Forced Oscillators by Harmonic Balance and Stability Investigation of Periodic and Quasi Periodic Regimes Int J Micro wave and Millimeter Wave CAD Vol 5 No 3 pp 210 233 1995
6. are attractive candidates for post CMOS VLSI ICs Accurate models are also required in order to efficiently design SET circuits and hybrid circuits We have developed a new physical compact model of SET 3 4 which enables the accurate simulation of SET circuits and hybrid circuits in a SPICE like environment We show advanced examples of applications of our approach simulations of elementary circuits which functionalities have been experimentally demonstrated in the literature 5 6 1 Introduction SETs have attracted much attention because of their low power consumption and small size 1 2 7 Recent works 5 6 show that Single Electron Transistors could enable innovative functionalities if they are associated with MOSFETs However Monte Carlo MC simulation 8 is not adapted to the analysis and the optimization of realistic logic circuits with a large number of devices MOSFETs and SETs In this paper we propose a compact physically based SET model describing SET characteristics accurately over a wide range of temperature and voltages 4 Our approach is simpler and more efficient than those presented in the literature 9 10 Our model has been validated in static and dynamic regimes 4 at both device and logic circuit levels by comparison with the MC simulator SIMON 8 2 SET Modeling Our model is derived on the basis of the orthodox theory of single charge tunnelling and the master equa tion method
7. piya d pllva swept va capacitor va resistor va 7 module yco vin yout 8 inout vin vout 9 electrical vin vout 10 parameter real amp 1 0 11 parameter real center_freq 2 5k 12 parameter real vco_gain 1 0k pliva swept va capgci 13 13 module pll inj o 14 14 input in 15 output out 16 analog begin 46 electrical in oo 17 phase idt center_freq yco_gain V vin 0 0 vout lt anp sin 6 28 phase real phase va aaa resistdrya w 18 ground gnd end 13 a endmodule 20 pd gain 2 options va_mode debug 21 vco yco_gain o 75 3 amp t u 2 center_fregq 2 5k xvd verilog svept va 23 6 verilog pll va 24 resistor 1k rlpf in_f out capacitor 1u clpf out gnd _ 8 LGswvept in nod_swept 25 i 26 endmodule v g yyLGpll in out mod_pl E P 11 nodel mod_pl VLG KODULE pll 12 model mod_swept VLG KODULE swept 13 14 op A 15 tran 10fn 12m T Figure 12 An example of the hierarchy structure of the call stack Conclusion Using a debugger can be of a great help when proto typing a model or when debugging a circuit design which includes Verilog A modules Its great read ability and ease of use allow the user to quickly find physical inconsistency in the model equations or in the circuit design The call stack window helps the user to navigate easily through the des
8. 2 T H Lee The Design of CMOS Radio Frequency Integrated Cir cuits Cambridge University Press 1998 3 K S Kundert Steady State Methods for Simulating Analog and Microwave Circuits Kluwer Academic Publishers May 1990 Eile an View Chart Tools ar alist 10dBe Hz2 15dBe Hz Number of Sweeping Points 1 5 10 20 TRAN CPU time s 12 18 20dBe Hzr HOSCIL CPU time s 3 8 Table 1 Performance comparison between TRAN and HOSCIL analyses 25dBe H2e Figure 5 Relative phase noise plot at output node October 2004 Page 3 The Simulation Standard SET Accurate Compact Model for SET MOSFET Hybrid Circuit Simulation C Le Royer G Le Carval M Sanquer CEA DRT LETI CEA GRE 17 rue des Martyrs 38054 Grenoble Cedex 9 France cyrille leroyer cea fr gilles lecarval cea fr CEA DRFMC 17 rue des Martyrs 38054 Grenoble Cedex 9 France marc sanquer cea fr The following article by Le Royer C Le Carval G San quer M SET Accurate Compact Model for SET MOSFET Hybrid Circuit Simulation In Wachutka G Schrag G eds Simulation of Semiconductor Processes and Devices 2004 Wien New York Springer 2004 http www springer at main book jsp bookID 3 211 22468 8 demonstrates the flexibility of SmartSpice used with its module Verilog A in the simulations of SET circuits and hybrid SET MOSFET circuits Abstract Single Electron Transistors SETs 1 2
9. B e ui ee im el Select SmartView 2 8 0 R Silvaco 2004 Figure 3 Transient output waveform at node 4 After a few seconds the steady state results are avail able The figures 1 and 2 show examples of waveforms and spectra obtained at the point Ctune 1 nF With a regular transient simulation TRAN statement the VCO must be started for example using an initial condition 3 and the steady state is only reached after a lot of simulation time points when all transients have sufficiently vanished It is completely prohibitive for cir cuits with a high Q factor or for circuits containing ele ments like transmission lines which are better described directly in the frequency domain by HOSCIL whereas TRAN uses costful convolution techniques With HOSCIL analysis each pointin the parametric analysis will use the result from a previous run as an initial guess The convergence of the subsequent points is then much faster The fundamental oscillation frequency can be easily extracted for each run through a measure command measure hop sp fosc AMAX vdb 3 Figure 4 shows the oscillation frequency as a function of the control capacitance With TRAN analysis the parametric analyis is equiva lent to as many indepent runs as swept points Besides the oscillation frequency has to be extracted carefully with a subsequent measurement when have we really reached the true steady state
10. Connecting TCAD To Tapeout Simulation Standard A Journal for Circuit Simulation and SPICE Modeling Engineers Fast and Accurate Simulation of the Steady State of Voltage Controlled Oscillators with SmartSpice RF 1 Abstract A novel simulation method of the steady state of oscillators based on Harmonic Balance HB is presented A compari son with regular transient simulations demonstrates its ad vantages on a feedback voltage controlled oscillator VCO 2 Introduction Oscillators are the key components of many radio fre quency RF circuits Simulating their steady state and ex tracting their characteristics oscillation frequency power spectra phase noise has become one of the most critical challenge in the design flow Regular SPICE transient sim ulations suffer from severe drawbacks on these circuits First simulation run times are often prohibitive to reach the steady state particulary for high Q circuits which are the major part of today s RF applications Second it is necessary to manually start the oscillator which is not an easy task and can lead to false steady states Third phase noise characteristics can not be extracted directly from transient results And sweeping a parameter for example to study the oscillation frequency dependance of a VCO is very costful since the simulation time is simply multi plied by the number of sweeping points SmartSpice RF propose a new method which remains f
11. and reports the ratio in decibels 2 v Af L Ao 10log Z The most commonly used unit for phase noise is power below the carrier per Hertz expressed in dB or dBc Hz at some offset frequency Aw from the carrier frequency w One of the possible ways to model phase noise in oscilla tors is a noise mixing analysis The noise at the sidebands on either side of the carrier w Aw is obtained from small signal mixer analysis where noise sources Aw k mix with the oscillator large signals kw to pro duce noise sidebands These noise simulation results are then used to compute the phase noise 4 Example We consider a regular Wien Bridge oscillator circuit which contains two basic sections an RC tuning network and an amplifier In the RC tuning network the capacitance value Ctune can be swept to control the oscillator frequency A UA741 amplifier is used containing 16 BJT transistors The corresponding SPICE netlist is given below Sources Vec vee ond dc 15 Vee vee gnd dc 15 Op Amp XAmpl 1 2 3 ua741 Resistors Ri 2 gnd r 10k Amplitude stabilization network R3 2 2 21k R4 2 4 r 200k The Simulation Standard Page 2 SmartView Elle Edit View Chart Tools Object Help SiH i i 0 amp Fl ARRA Ot oe Ua m e eM le Toe Bl e Ro S Legend hop_sp2 power_dbm D1 4 3 DioN D2 3 4 DioN model DioN D is 1fA Tunable capacitance _param Ct
12. ases is the same but this is a special case and if AF 1 then you get different noise levels for the 3 cases A B amp C In this particular case the customer had a model card that contained the parameter AF 1 72 Under these circumstances a differ ence of which is what was seen in the simulation If I delete nlev 0 in the model file and substitute it with noimod 2 then why are the thermal and flicker 1 F noises of all three cases not identical Large Rawfile Handling in SmartView 1 Files greater than 2Gbyte must be on a local disk of the PC ie C or D not a network drive otherwise SmartView cannot read beyond the 2Gbyte limit This is a OS restriction 2 The incremental loading must be enabled That is SmartView will only load data from the rawfile as it is required This will limit th memory usage of SmartView 3 In 32 bit applications all current PC apps have a 2GByte memory limit No application can use more than 2Gbyte of memory this is a hard limit only a 64bit OS can get round this problem 4 No 32bit application can control more than 2Gbyte of system memory Once the total amount of data loaded reaches 2Gbyte SmartView will stop The 64 bit version on Solaris and Linux will work be yond this point Call for Questions If you have hints tips solutions or questions to contribute please contact our Applications and Support Department Phone 408 567 1000 Fax 408 496 6080 e mail support
13. ast and accurate in all these situations where transient simulation fails or shows poor performance Based on Harmonic Balance the oscillator steady state is computed directly in the frequency domain thanks to a two stages method In the following we first describe briefly the method then shows its application on a feedback VCO and compares its performance to transient simulations 3 Basics of the Method A two stages approach 1 is used to compute the steady state of autonomous circuits It uses the concept of a probe A probe is a special purpose voltage source which behaves as a pure sinusoidal generator at the oscillation Volume 14 Number 10 October 2004 fundamental frequency and an open circuit at all other frequencies This component must be inserted in the circuit to compute the frequency and oscillation level at insertion point First SmartSpice RF uses an initialization procedure to find the probe voltage corresponding to the probe admit tance minimum at the oscillation frequency estimated by the user Then it operates an optimization procedure to compute the oscillation frequency and magnitude of the probe This stage ends when the current across the probe is considered as null the probe is then like discon nected or when the accuracy on oscillation frequency is reached At this frequency the circuit must be an oscillator The method requires a good starting point for the oscilla tion frequency to have good converg
14. ehaviour When the supply voltage Vd is increased October 2004 The Simulation Standard MOSFET b quantizer Figure 5 Schematic circuits proposed by Inokawa a SRAM cell 5 the multiple value memory effect is due to the V I hysteresis b quantizer 6 the signal Vin is sampled with respect to the frequency defined by the Clock MOSFET along the stability points a b f V Volt Figure 6 a Current characteristic I V of the sub circuit of the SRAM cell calculated by hybrid SPICE simulation b Multivalued hysteresis effect of the SRAM cell simulated by our model The simulated results Figure 6 and Figure 7 show a very good agreement with these experimental measure ments 5 6 4 Conclusions In this paper we propose a new compact model for SET dedicated to SPICE simulation for SET circuits and hybrid MOSFET SET circuits After showing the perfor mances of our model we apply it to the simulation of SET Logic gates and hybrid MOSFET SET circuits We demonstrate the accuracy of our model by the good comparisons between the SPICE simulations and the experimental measurements of these circuits 5 6 Acknowledgment The authors would like to acknowledge Silvaco s contri bution which greatly facilitated implementation of these models within SmartSpice and Verilog A References 1 H Grabert and M Devoret Single Charge Tunneling Series B Physics Vol 294 NATO ASI Series
15. ence properties If the user doesn t know accurately enough the expected oscilla tion frequency a linear AC simulation a S parameter simu lation can be run to determine a satisfying initial guess Success and efficiency of analysis depends also on where the probe is connected Typically it should be inserted in parallel with the resonator or in parallel with the load Since the probe must have some effect on the oscillation it should not be placed after the buffer nor in the biasing circuitry SmartSpice RF can handle 1 tone autonomous circuits as well as efficient parametric sweep allowing Continued on page 2 INSIDE SET Accurate Compact Model for SET MOSFET Hybrid Circuit Simulation A Sophisticated Verilog A Debugger Calendar of Events Hints Tips and Solutions SILVACO INTERNATIONAL Eile Edit View Chart Tools Object Help Bae HG FT e a An A a PB Legend i hop_wi2 v 3 i hop_wi2 v 4 Oo B AS Ti GD BT M Ime 1 Figure 1 Output voltage waveforms at node 3 and 4 applications like VCO frequency tuning Additionnally a small signal noise analysis can be performed around the steady state operating point to compute phase noise as well as total output noise Phase noise is usually characterized in terms of the single sideband noise spec tral density The phase noise is defined as mean square noise voltage density to the mean square carrier voltage
16. ign hierarchy The Simulation Standard Calendar of Events October November Bulletin Board 1 1 2 2 3 ____________ _ 3 FSA Model Checkli 4 IEEE SOI Conf Charleston SC 4 Ae EESE e A A aa Aaa As chairman of the FSA Model 9 IEEE SOI Conf Charleston SC 6 Checklist working group within the __ FSA Modeling WS Santa Clara CA 7 FSA MS RF Foundry committee 6 IEEE SOI Conf Charleston SC 8 Silvaco is attempting to duplicate FSA Suppliers Expo San Jose CA 9 the success of the FSA PDK Checklist 7 IEEE SOI Conf Charleston SC 10 with a common document that all 8o N foundries would release with their 9 12 SPICE models The objective of this group is to develop a SPICE Model 10 13 Checklist with recommended circuit 11 14 measurements and reports graphs 12 15 delivered with each foundry model 13 16 to quantify and improve quality of 14 17 extracted foundry digital analog 15 18 and RF models The group has representatives from most of the 16 19 foundries who support mixed signal 17 20 and RF process as well as leading 18 21 MS RF fabless companies To find 19 22 out more about this group e mail 20 23 ken brock silvaco com 21 24 22 25 23 26 24 IEEE Compound Symposium 27 Monterey CA 28 25 IEEE Compound Symposium 29 Monterey CA 30 26 IEEE Compound Symposium 31 Monterey CA 27 IEEE Compound Symposium Monterey CA 28 29 30 If you would like more information or to register for one of our our wor
17. igned to meet these needs It is available since version 2 6 0 R of SmartSpice and works along with SILVACO C Interpreter It allows iteration per iteration Verilog A modules debugging The debugger is tracing all the Verilog A instantiations of the design either instances of the SmartSpice netlist or in other Verilog A modules The BSIM4 Verilog A model bsim4 va and the adder design adder in used as an example are freely available on SILVACO website It can be enabled by setting in the input deck OPTIONS vamode debug The debugger appears when the simulation of this in put deck is launched The simulation stops at the first instruction a breakpoint at the first instruction is always set by default In the case of BSIM4 model the first instruction encountered is the initial_step event in the analog block The layout of the main window at startup is shown in Figure 1 The Verilog A source code is displayed in an editor win dow Syntax highlighting is available and its colors are fully customizable Line numbers can be displayed by checking the Show line number box in the Properties dialog window Edit gt Properties The console window is at the bottom of the main win dow The error messages are printed in this area and the user can enter commands manually In this example Figure 2 The console window a break point has been set at line 2699 the end of the initial_step block and the simulation has been star
18. is the total capacitance of the central island which is two times the limit of the models proposed by Uchida 9 or Mahapatra 10 We have checked that thisresult does not depend on the SET parameters capacitances resistances and isvalidated for a large range of tempera ture kT Ec lt 01 3 Applications to Hybrid MOSFET SET Simulation 3 1 Ring Oscillator with SETs The first logic gates that we have simulated with our model in SmarSpice with Verilog A 11 are ring oscil lators composed of 2p 1 SET inverters 11 Figure 3 The voltages V V and V are the outputs of the 3 invert ers The supply voltages are V and V This circuit generates oscillating signals like in the case of CMOS inverters Figure 4 shows the voltages of the outputs of the three inverters as a function of time obtained by a SmartSpice simulation 11 This proves that our model allows to simulate this oscillating behaviour Voltage V 240 3 2 Hybrid SET MOSFET Circuits We have also simulated the electrical behaviour of two hybrid MOSFET SET circuits a SRAM cell 5 and a quantizer 6 Figure 5 proposed by Inokawa For most simulation parameters we have considered the values extracted by Inokawa from measurements We have used the following values MOSFET L 14um W 12um T 9 45nm SET C 1 8aF C 0 07aF Rt 150kQ q e 2 V 1 04V 5 Figure 4 Simulation of the ring oscillator b
19. kshops please check our web site at http www silvaco com The Simulation Standard circulation 18 000 Vol 14 No 4 April 2004 is copyrighted by Silvaco International If you or someone you know wants a subscription to this free publication please call 408 567 1000 USA 44 1483 401 800 UK 81 45 820 3000 Japan or your nearest Silvaco distributor Simulation Standard TCAD Driven CAD Virtual Wafer Fab Analog Alliance Legacy ATHENA ATLAS MERCURY VICTORY VYPER ANALOG EXPRESS RESILIENCE DISCOVERY CELEBRITY Manufacturing Tools Automation Tools Interactive Tools TonyPlot TonyPlot3D DeckBuild DevEdit DevEdit3D Interpreter ATHENA Interpreter ATLAS Interpreter Circuit Optimizer MaskViews PSTATS SSuprem3 SSuprem4 Elite Optolith Flash Silicides MC Depo Etch MC Implant S Pisces Blaze Blaze3D Device3D TFT2D 3D Ferro SiGe SiC Laser VCSELS Quantum2D 3D Luminous2D 3D Giga2D 3D MixedMode2D 3D FastBlaze FastLargeSignal FastMixedMode FastGiga FastNoise Mocasim Spirit Beacon Frontier Clarity Zenith Vision Radiant TwinSim UTMOST UTMOST II UTMOST UI UTMOST IV PROMOST SPAYN UTMOST IV Measure UTMOST IV Fit UTMOST IV Spice Modeling SmartStats SDDL SmartSpice FastSpice Twister Blast MixSim SmartLib TestChip Promost Rel RelStats RelLib Harm Ranger Ranger3D Nomad QUEST EXACT CLEVER STELLAR HIPEX net HIPEX r HIPEX c HIPEX rc HIPEX cre EM Power IR SI Timing SN Clock
20. ow by inserting the function name with In function box checked ll The Variable Watch Display Once the debugger has reached the desired breakpoint the value of cbd Bulk Drain diode current can be checked Moving mouse cursor over the variable in the source code window prints its value at current SmartSpice engine iteration and current location in the module 2827 else if Cvbd_jet lt vjdmfwd 2826 begin 2829 evbd exp t2 2830 cbd isbd evbd 1 0 gmin vbd_jct 2831 d 2832 sla realcbd 1 641273e 15 Figure 6 Variable value display in edit window Another way to display the cbd variable is to look for this variable in the local variable panel d Local 1 Global La Watch 0 OOOO00e 00 0 OOO OO 0e 00 real 0 OOOO OOe 00 real 1 126044e 36 real 1 6412 3e 145 real 1 OOO OO 0e 00 real 4 440564e 01 real 1 126044e 24 really The local variable panel shows all the variables param eters and branch quantities values in the current context initial block analog block or user defined function These values are updated at each step The panel next to it shows the global variables related to current simu lation The running analysis as well as its parameters the SmartSpice engine iteration counter and the circuit temperature are given GlLocal amp Global fa Watch analysis name Transient Analysis string netlist_ analysis name tran 10ns 600ns st
21. ring finalTime be 7 real step 1e g real naxstep i real mode INITPRED flags Integrate Method TRAPEZOIDAL flag order 2 integer delta 2 ebbbe 0 real delta_min le 1 real iteration i integer temperature 300 750000 real Figure 8 The global variables panel A third way to display cbd value is to use the watch panel next to the global variables panel In this window only the variables asked by the user are displayed To do so the name of the variable must be entered in the watch dialog box 44 Figure 9 The Add Watch dialog window Entering for example cbd variable in the Add Watch window has the effect of adding the variable to the cur rent list of variables in the watch panel see Figure 10 The watch panel F Add watch Varlable Name OK Canc Figure 9 The Add Watch dialog window Analysis type arguments must be DC AC NOISE or TRAN Initial iteration arguments must be DC AC NOISE or TRAN Final iteration arguments must be DC AC NOISE or TRAN Current simulation time in transient analysis Current circuit temperature The Simulation Standard October 2004 2 Q Global a b412 ge 1 real Figure 10 The watch panel By using this latter method the value of cbd can be eas ily monitored during the simulation The values of the asked variables in the watch panel are re evaluated at each deb
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23. ted with the cont command The edit window has now the aspect shown in Figure 3 I Tracing Code in the Source Code Window Verilog A code in a module can be debugged step by step or by using breakpoints Breakpoints can be set by opening the View breakpoints window or by a direct Interactive Workbench version 1 16 0 Thu Jul 22 15 45 36 POT 2004 Copyright C 2004 Silvaco International Inc All Rights Reserved fiw stopat 2699 Breakpoint added 1 bsim4 va 2699 mosfet fiw cont iw Debug A Build A Output Figure 2 The console window October 2004 E Interactive Workbench debug home sebastr BSIM4 bsim4 va H 4 File Edit Tools Debug Help OSE A y bsim4 va adder in ki ee O ES KEL y Call Stack tc xexpby tbh 1 0 ijth isb te gt 1 yvlg x1 x2 x9 yvigd mosfet line 963 bsim4 va evjmovny 0 5 th sgrt tb tb 4 0 tc 0 NETLIST line 16 adder in get_yim nytm InCevjmoyny i end endfunction ae Local Global 3 Watch egin Wt Name Value Type Cinitial_step GMIN je 12 begin PS 0 ad AQ Be P AS 0 al Al a2 A2 AD 0 acde ACDE CGBO 2 56e 1 1 ad AD CGDO 7 43e 10 agid AGIDL caso 7 43e 10 ags AGS ali TYPE 1 lt 0 a x Interactive Workbench version 1 16 0 Thu Jul 22 15 45 36 PDT 2004 Copyright C 2004
24. to define all currents 2698 eeree Definition of the tensions 2699 yds type drainp sourcep 2700 vgs type V gatep sourcep i 2701 ybs type V bulkp sourcep 2702 yges type V gate sourcep 2703 ygms type Y gatem sourcep 2704 ysbs type VCsourceb sourcep 2705 yvdbs type Vdrainb sourcep 2706 yses type VCsource sourcep A El P Figure 3 Editing window The Simulation Standard Condition lanalysis TRAN amp amp realtime 190n Figure 4 Add a condition to a breakpoint By using continue button the simulation continues and the debugger stops when time has reached 190 ns The current analysis and the current step time in the case of a transient analysis are printed at the bottom panel of the main window TRANS time 190 428n Ln 2699 Col 1 Interactive Workbench v 1 16 0 Silvaco 2004 Figure 5 The bottom panel DC AC TRANS or NOISE can be displayed at this loca tion according to the analysis run The simulation step can be the sweep value for DC analysis the time for tran sient or the frequency for AC and NOISE Cursor location information in the source code window is also given step into and step over buttons Pn the upper tool bar can be used to trace into or over the user defined func tions Setting a breakpoint ona given function can be done directly in the View breakpoint wind
25. ugger step lll The Call Stack Display The call stack window displays the debugging location inside the instance hierarchy The following example is a PLL Verilog A module instantiated in the SmartSpice netlist This module is itself composed of other Verilog A modules generator phase detector low pass filter and VCO The hierarchy of the modules is Module pll Module pd phase detector Module vco Voltage Control Oscillator Module capacitor Module resistor Low pass filter Next figure shows the call stack content Call Stack p 2 xvcolyea line 1 veo va T yylgpliiolh line 27 pll va 0 NETLUST line 3 home sebastroll allin Figure 11 The call stack display Each level of the stack is of the following kind level instancename modulename number filename line October 2004 Page 9 The level 0 is the SmartSpice netlist launched with the simulator The other stack levels can be a module instan tiation within another Verilog A module or a user de fined function By double clicking on a level of the stack the associated module is opened in the editor window and the user can see where the next object in the stack is instantiated The last level of the call stack indicates the current debugging location in the object at the bottom of the hierarchy In the case of the PLL example the objects related to the stack are Call Stack 2 xvcotyco line 17 Acova l yvopipl ine ot
26. une 1nF Feedback network subckt FeedbackNet pin pOut pGnd Resistors RA pIn 1 15 8k RB pOut pGnd 15 8k Capacitors CA 1 pOut pOut pGnd Ctune Ctune ends XResl 3 1 gnd FeedbackNet The analysis statement looks like the following HOSCIL probe 3 1 fundosc 12 591kHz nharm 7 fundoscreltol 0 1 sweep Ctune 0 8n 1 2nF 0 05nF A logical choice is to connect the probe in parallel with the RC feedback network probe 3 1 The theoretical center pulsation characterizing the feedback network is equal to 1 RC Let R and C be the resistance and capacitance values of the first sweeping point It is a good choice for the initial oscillation frequency fund_ osc 12 591kHz The specified number of harmonics nharm 7 is chosen so that aliasing which is a common phenomenon to all HB based methods is negligible The required accuracy on the computed oscillation frequency is set to 0 1 Hz fundoscreltol 0 1 The HOSCIL statement propose a lot of other tunable parameters allowing a fine control of both the accuracy and the convergence quality which are beyond the scope of this paper The last line specifies that the capacitance of the RC tuning network Ctune is swept from 0 8 nF to 1 2 nF with steps of 0 05 nF which will induce a sweep of the oscillator frequency October 2004 Eile Edit View Chart Tools Object Help a Neeeiaelaa AIR ABik aadA MEE
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