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1. Characteristic Symbol panes oe Unit Note Core supply voltage Vdd 1 8v 100mv V 1 PLL supply voltage AVdd 1 8v 100mv V 1 L2 DLL supply voltage L2AVdd 1 8v 100mv V 1 Processor bus supply BVSEL 0 OVdd 1 8v 100mv V 1 soles BVSEL HRESET OVdd 2 5v 100mv v 1 BVSEL 1 OVdd 3 3v 165mv V 1 L2 bus supply voltage L2VSEL 0 L20Vdd 1 8v 100mv V 1 L2VSEL HRESET L2OVdd 2 5v 100mv V 1 L2VSEL 1 L20Vdd 3 3v 165mv V 1 Input voltage Processor bus Vin GND to OVdd V 1 L2 Bus Vin GND to L2OVdd V 1 JTAG Signals Vin GND to OVdd V 1 Die junction temperature Tj 0 to 105 C 2 Note 1 These are the recommended and tested operating conditions Proper device operation outside of these conditions is not guaranteed 2 The extended temperature parts have die junction temperature of 40 to 105 C Table 4 provides the package thermal characteristics for the MPC7400 Table 4 Package Thermal Characteristics Characteristic Symbol Value Rating CBGA package thermal resistance junction to case thermal resistance typical zc 0 03 C W CBGA package thermal resistance die junction to lead thermal resistance Or 3 8 C W typical Note Refer to Section 1 8 System Design Information for more details about thermal management The MPC7400 incorporates a thermal management assist unit TAU composed of a thermal sensor digital to analog converter comparator control logic and dedicated special purpose regi
2. suononysuy Z vun yoredsiq ALO AT Anug ZIS LH PIOM 9 lonan uononnsug Anuyq 9 ILA run 3uIss2001dq YPULIg pun uoponnysuj JUIUWJLWEN JOMO d WHA dOO OVLI IANN YO D IJUJIWANI Aq JayuNoD seg WIL e soinjea y RUODIPpY MPC7400 Block Diagram Figure 1 MPC7400 RISC Microprocessor Hardware Specifications PRELIME Or Mor intormation On This Product CE Y MOTOROLA Go to www freescale com Freescale Semiconductor Inc Features 1 2 Features This section summarizes features of the MPC7400 s implementation of the PowerPC architecture Major features of the MPC7400 are as follows Branch processing unit Four instructions fetched per clock One branch processed per cycle plus resolving 2 speculations Upto 1 speculative stream in execution 1 additional speculative stream in fetch 512 entry branch history table BHT for dynamic prediction 64 entry 4 way set associative Branch Target Instruction Cache BTIC for eliminating branch delay slots Dispatch unit Full hardware detection of dependencies resolved in the execution units Dispatch two instructions to eight independent units system branch load store fixed point unit 1 fixed point unit 2 floating point AltiVec permute AltiVec ALU Serialization control predispatch postdispatch execution serial
3. gt EEE or Thermal Interface Material Printed Circuit Board Option Figure 23 Package Exploded Cross Sectional View with Several Heat Sink Options The board designer can choose between several types of heat sinks to place on the MPC7400 There are several commercially available heat sinks for the MPC7400 provided by the following vendors Chip Coolers Inc 800 227 0254 USA Canada 333 Strawberry Field Rd 401 739 7600 Warwick RI 02887 6979 International Electronic Research Corporation IERC 818 842 7277 135 W Magnolia Blvd Burbank CA 91502 Thermalloy 214 243 4321 2021 W Valley View Lane P O Box 810839 Dallas TX 75731 Wakefield Engineering 617 245 5900 60 Audubon Rd Wakefield MA 01880 Aavid Engineering 603 528 3400 One Kool Path Laconia NH 03247 0440 Ultimately the final selection of an appropriate heat sink depends on many factors such as thermal performance at a given air velocity spatial volume mass attachment method assembly and cost 1 8 9 1 Internal Package Conduction Resistance For the exposed die packaging technology shown in Table 3 the intrinsic conduction thermal resistance paths are as follows e The die junction to case or top of die for exposed silicon thermal resistance e The die junction to ball thermal resistance 38 MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PRELINAS Wires HABEAREN This BEGUN OTICE Go to www freescale com Freescale S
4. j lt lt a tL2cLk gt tcc t L2CLK_OUTA L2CLK_OUTB tL2CSKW L2SYNC_OUT L2 Differential Clock Mode a tL2cLk L2CLK_OUTB Mt CHCE gt per OUA cvM KM KYM XX L2SYNC_OUT VM L VM VM VM Midpoint Voltage L2OVdd 2 Figure 7 L2CLK_OUT Output Timing Diagram 1 4 2 4 L2 Bus AC Specifications Table 11 provides the L2 bus interface AC timing specifications for the MPC7400 as defined in Figure 8 and Figure 9 for the loading conditions described in Figure 10 Table 11 L2 Bus Interface AC Timing Specifications At Vdd AVdd L2AVdd 1 8V 100mV 0 lt Tj lt 105 C L2OVdd 3 3V 165mV or L2OVdd 2 5V 100mV or L2OVdd 1 8V 100mV 350 400 MHz Parameter Symbol L2SYNC_IN rise and fall time tracer amp tL2CF 1 0 ns 1 Setup Times ns 2 Data and parity tpyL2CH 1 5 Input Hold Times ns 2 Data and parity tDXL2CH 0 0 E 20 MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PREL INADH N reS HARSH REON Fhe HOWTO TICE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Table 11 L2 Bus Interface AC Timing Specifications Continued At Vdd AVdd L2AVdd 1 8V 100mV 0 lt Tj lt 105 C L2OVdd 3 3V 165mV or L2OVdd 2 5V 100mV or L2OVdd 1 8V 100mV 350 400 MHz Parameter Symbol Notes Min Valid Times tL2CHOV 3 4 All outputs when L2CR 14 15 00 7 All outputs whe
5. This noise must be prevented from reaching other components in the MPC7400 system and the MPC7400 itself requires a clean tightly regulated source of power Therefore it is recommended that the system designer place at least one decoupling capacitor at each Vdd OVdd and L2OVdd pin of the MPC7400 It is also recommended that these decoupling capacitors receive their power from separate Vdd L2 OVdd and GND power planes in the PCB utilizing short traces to minimize inductance These capacitors should have a value of 0 01 uF or 0 1 uF Only ceramic SMT surface mount technology capacitors should be used to minimize lead inductance preferably 0508 or 0603 orientations where connections are made along the length of the part Consistent with the recommendations of Dr Howard AN MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 33 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc System Design Information Johnson in High Speed Digital Design A Handbook of Black Magic Prentice Hall 1993 and contrary to previous recommendations for decoupling PowerPC microprocessors multiple small capacitors of equal value are recommended over using multiple values of capacitance In addition it is recommended that there be several bulk storage capacitors distributed around the PCB feeding the Vdd L2OVdd and OVdd planes to enable quick recharging of the smaller chip capacitors These
6. E12 E8 F4 GND GND GND F6 F10 F14 F16 G9 G11 H5 H8 H10 H12 H15 J9 J11 K4 K6 K8 K10 K12 K14 K16 L9 L11 M5 M8 M10 M12 M15 N9 N11 P4 P6 P10 P14 P16 R8 R12 T4 T6 T10 T14 T16 HIT B5 Low Output vV v vV 6 8 HRESET B6 Low Input V v vV INT Cll Low Input vV v vV L1_TSTCLK F8 High Input vV v vV 2 L2ADDR 0 16 L17 L18 L19 M19 K18 K17 K15 High Output vV v vV J19 J18 J17 J16 H18 H17 J14 J13 H19 G18 L2ADDR 17 K19 High Output vV v vV 8 L2ASPARE W19 High Output vV v vV 8 L2AVDD L13 Input 1 8V 1 8V 1 8V L2CE P17 Low Output vV v vV L2CLKOUTA N15 High Output vV v vV L2CLKOUTB L16 High Output vV v vV L2DATA 0 63 U14 R13 W14 W15 V15 U15 High TO vV v vV W16 V16 W17 V17 U17 W18 V18 U18 V19 U19 T18 T17 R19 R18 R17 R15 P19 P18 P13 N14 N13 N19 N17 M17 M13 M18 H13 G19 G16 G15 G14 G13 F19 F18 F13 E19 E18 E17 E15 D19 D18 D17 C18 C17 B19 B18 B17 A18 A17 A16 B16 C16 A14 A15 C15 B14 C14 E13 L2DP 0 7 V14 U16 T19 N18 H14 F17 C19 High T O vV v vV B15 L20VDD D15 E14 E16 H16 J15 L15 M16 1 8V 2 5V 3 3V 11 K13 P15 R14 R16 T15 F15 L2SYNC_IN L14 High Input vV vV vV L2SYNC_OUT M14 High Output vV v vV L2_TSTCLK F7 High Input vV v V 2 L2VSEL A19 High Input GND HRESET 3 3V 1 3 8 9 L2WE N16 Low Output vV v vV L2ZZ G17 High Output vV v vV A MOTOROLA MPC7400 RISC Microprocessor Hardware
7. Figure 12 JTAG Clock Input Timing Diagram AN MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 23 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Figure 13 provides the TRST timing diagram TRST VM VM lt t _ _ tyrst VM Midpoint Voltage OVpp 2 Figure 13 TRST Timing Diagram Figure 14 provides the boundary scan timing diagram TCK vM K tDXJH BOUNDARY INPUT DATA INPUTS DATA VALID gt LDV gt Dx BOUNDARY OUTPUT DATA VALID DATA OUTPUTS gt Lbz ROUTE ne OUTPUT DATA VALID VM Midpoint Voltage OVpp 2 Figure 14 Boundary Scan Timing Diagram Figure 15 provides the test access port timing diagram TCK V Kiz HK VM tIVJH lt gt tIXJH INPUT TDI TMS rat VALID Lov tiLox TDO OUTPUT DATA VALID Loz TDO OUTPUT DATA VALID y VM Midpoint Voltage OVpp 2 Figure 15 Test Access Port Timing Diagram MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PREL INADH N reS HARSH REON Fhe HOWTO TICE Go to www freescale com 24 Pin Assignments Freescale Semiconductor Inc 1 5 Pin Assignments Figure 16 in part A shows the pinout of the MPC7400 360 CBGA package as viewed from the top surface Part B shows the side profile of the CBGA package to indicate the direction of the to
8. Specifications 27 PRELIME Or Mor intormation On This Product CE Go to www freescale com Freescale Semiconductor Inc Table 13 Pinout Listing for the MPC7400 360 CBGA Package Continued Pinout Listings I F Voltages Supported Signal Name Pin Number Active T O 1 8v 2 5v 3 3v Notes LSSD_MODE F9 Low Input vV vV vV 2 MCP B11 Low Input vV v vV OVDD D5 D8 D12 E4 E6 E9 E11 F5 1 8V 2 5V 3 3V H4 J5 L5 M4 P5 R4 R6 R9 R11 T5 T8 T12 PLL_CFG 0 3 A4 A5 A6 A7 High Input vV vV vV QACK B2 Low Input vV vV vV QREQ J3 Low Output vV v vV RSRV D3 Low Output vV v vV SHDO B3 Low VO vV v vV 8 SHD1 B4 Low I O vV v vV 5 8 SMI A12 Low Input vV v vV SRESET E10 Low Input vV vV vV SYSCLK H9 Input v v v TA Fl Low Input vV v V TBEN A2 High Input vV v vV TBST All Low Output vV v vV TCK B10 High Input vV v vV TDI B7 High Input vV v vV 9 TDO D9 High Output vV vV V TEA Ji Low Input vV v vV TMS C8 High Input vV v V 9 TRST A10 Low Input vV v vV 9 TS K7 Low Y O vV v vV TSIZ 0 2 A9 B9 C9 High Output v v v TT 0 4 C10 D11 B12 C12 F11 High TO v v v WT C3 Low Y O vV y vV VDD G8 G10 G12 J8 J10 J12 L8 L10 1 8V 1 8V 1 8V L12 N8 N10 N12 Notes 1 OVdd supplies power to the processor bus JTAG and all control signals except the L2 cache controls L2CE L2WE and L2ZZ LZOVDD supplies power to th
9. Table 13 to reflect 2 5 V Processor Bus support added in previous rev of document 1 10 Ordering Information Figure 27 provides the Motorola part numbering nomenclature for the MPC7400 Note that the individual part numbers correspond to a maximum processor core frequency For available frequencies contact your local Motorola sales office In addition to the processor frequency the part numbering scheme also consists of a part modifier and application modifier The part modifier indicates any enhancement s in the part from the original production design The bus divider may specify special bus frequencies or application conditions Each part number also contains a revision code This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only MPC 7400 RX XXX X X me oo oo Revision Level Contact Local Motorola Sales Office Product Code a Application Modifier Part Identifier L Full Spec 1 8V 100mV 0 105 C T T Ext Temp Spec 1 8V 100mV 40 105 C T Processor Frequency Package RX BGA Figure 27 Motorola Part Number Key AD MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 43 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc Mfax is a trademark of Motorola Inc The PowerPC name the PowerPC logotype and PowerPC 603e are trademarks of International Business Machines Co
10. Thermal Characteristics Figure 3 provides the SYSCLK input timing diagram SYSCLK tSYSCLK VM Midpoint Voltage OVpp 2 Figure 3 SYSCLK Input Timing Diagram 1 4 2 2 Processor Bus AC Specifications Table 9 provides the processor bus AC timing specifications for the MPC7400 as defined in Figure 4 and Figure 5 Timing specifications for the L2 bus are provided in Section 1 4 2 3 L2 Clock AC Specifications y Table 9 Processor Bus AC Timing Specifications At Vdd AVdd 1 8V 100mV 0 lt Tj lt 105 C OVdd 3 3V 165mV or OVdd 2 5V4100mV or OVdd 1 8V 100mV 350 400 MHz 400 MHz Parameter Symbol Unit Notes Mode select Mode select input setup to HRESET setup to HRESET omv Oe ae 3 4 5 6 Setup Times Address Transfer Attribute Transfer Start TS Data Data Parity ARTRY SHDO SHD1 All Other Inputs Input Hold Times Address Transfer Attribute Transfer Start TS Data Data Parity ARTRY SHDO SHD1 All Other Inputs Valid Times Address Transfer Attribute TS ABB DBB Data Data Parity ARTRY SHDO SHD1 All Other Outputs 14 MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PREL INEO N reS HAG Gor HON ThS BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Table 9 Processor Bus AC Timing Specifications Continued At Vdd AVdd 1 8V 100mV 0 lt Tj lt 105 C OVdd 3 3V4165mV or OVdd 2 5V 100mV or OVdd 1 8V 100mV
11. bulk capacitors should have a low ESR equivalent series resistance rating to ensure the quick response time necessary They should also be connected to the power and ground planes through two vias to minimize inductance Suggested bulk capacitors 100 330 uF AVX TPS tantalum or Sanyo OSCON 1 8 5 Connection Recommendations To ensure reliable operation it is highly recommended to connect unused inputs to an appropriate signal level Unused active low inputs should be tied to OVdd Unused active high inputs should be connected to GND All NC no connect signals must remain unconnected Power and ground connections must be made to all external Vdd OVdd L2OVdd and GND pins of the MPC7400 See Section 1 4 2 3 L2 Clock AC Specifications for a discussion of the L2S YNC_OUT and L2SYNC_IN signals 1 8 6 Output Buffer DC Impedance The MPC7400 60x and L2 I O drivers are characterized over process voltage and temperature To measure Zo an external resistor is connected from the chip pad to OVdd or GND Then the value of each resistor is varied until the pad voltage is OVdd 2 see Figure 20 The output impedance is the average of two components the resistances of the pull up and pull down devices When Data is held low SW2 is closed SW1 is open and Ry is trimmed until the voltage at the pad equals OVdd 2 Ry then becomes the resistance of the pull down devices When Data is held high SW1 is closed SW2 is open and Rp is trimme
12. ey ete F E J L 3j Be a a ee Nate a eae S 5 4 f H J E L 4 r L 4 n Be Tn Re LR ES Ree Se ae NS Se A Se So er ee E Z E J x L 4 2 ets Gee Sh ors So 2 a Se qe bind Sh oh Be ne 5 ae SP et Sey a ees Sete on eS E tr t t t t t t g 0 0 5 1 1 5 2 2 5 3 3 5 Approach Air Velocity m s Figure 26 Thermalloy 2328B Heat Sink to Ambient Thermal Resistance Versus Airflow Velocity Assuming an air velocity of 0 5 m s we have an effective R of 7 C W thus T 30 C 5 C 0 03 C W 1 0 C W 7 C W 5 0 W resulting in a die junction temperature of approximately 75 C which is well within the maximum operating temperature of the component Other heat sinks offered by Chip Coolers IERC Thermalloy Wakefield Engineering and Aavid Engineering offer different heat sink to ambient thermal resistances and may or may not need air flow Though the die junction to ambient and the heat sink to ambient thermal resistances are a common figure of merit used for comparing the thermal performance of various microelectronic packaging technologies one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three dimensional heat flow The final die junction operating temperature is not only a function of the component level thermal resistance but the system level design and its operating conditions In addition to the component s power consumption a nu
13. latched or enabled respectively by the internal L2CLK which is SYSCLK multiplied up to the core frequency and divided down to the L2CLK frequency In other words the AC timings of Table 11 are entirely independent of L2SYNC_IN In a closed loop system where L2S YNC_IN is driven through the board trace by L2SYNC_OUT L2SYNC_IN only controls the output phase of L2CLKOUTA and L2CLKOUTB which are used to latch or enable data at the SRAMs However since in a closed loop system L2S YNC_IN is held in phase alignment with the internal L2CLK the signals of Table 11 are referenced to this signal rather than the not externally visible internal L2CLK During manufacturing test these times are actually measured relative to SYSCLK Table 10 L2CLK Output AC Timing Specifications At recommended operating conditions See Table 3 Parameter L2CLK frequency fL2cLK L2CLK cycle time tL2CLK 2 86 10 ns L2CLK duty cycle Internal DLL relock time tCHCL IL2CLK 640 50 L2CLK DLL capture window 10 ns output skew L2CLKOUT output to tLacskw 50 ps HDi nt wf N L2CLKOUT output jitter 150 150 ps Notes 1 L2CLK outputs are L2ACLK_OUTA L2CLK_OUTB and L2SYNC_OUT pins The L2CLK frequency to core frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or m
14. unit Contains its own 32 entry 128 bit vector register file VRF with 6 renames The vector ALU unit is further sub divided into the vector simple integer unit VSIU the vector complex integer unit VCIU and the vector floating point unit VFPU Fully pipelined e lLoad store unit One cycle load or store cache access byte half word word double word 2 cycle load latency with 1 cycle throughput Effective address generation Hits under misses multiple outstanding misses Single cycle unaligned access within double word boundary Alignment zero padding sign extend for integer register file Floating point internal format conversion alignment normalization Sequencing for load store multiples and string operations Store gathering Executes the cache and TLB instructions Big and little endian byte addressing supported Misaligned little endian supported Supports FXU FPU and AltiVec load store traffic Complete support for all 4 architecture AltiVec DST streams e Level 1 L1 cache structure 32K 32 byte line 8 way set associative instruction cache iL1 32K 32 byte line 8 way set associative data cache dL1 Single cycle cache access Pseudo least recently used LRU replacement Data cache supports AltiVec LRU and transient instructions algorithm Copy back or write through data cache on a page per page basis Supports all PowerPC memory coherency modes Non blocking instruction and data cache Separate copy of dat
15. with thermal grease as a function of contact pressure As shown the performance of these thermal interface materials improves with increasing contact pressure The use of thermal grease significantly reduces the interface thermal resistance That is the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint Heat sinks are attached to the package by means of a spring clip to holes in the printed circuit board see Figure 24 This spring force should not exceed 10 pounds of force Therefore the synthetic grease offers the best thermal performance considering the low interface pressure Of course the selection of any thermal interface material depends on many factors thermal performance requirements manufacturability service temperature dielectric properties cost etc AD MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 39 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc System Design Information Silicone Sheet 0 006 inch Bare Joint L 1 i 1 1 O Floroether Oil Sheet 0 007 i i i O Graphite Oil Sheet 0 005 ini t Synthetic Grease i N S A M D Q O S S S n RZ n Q e4 oN S E 3 E E o 3 D Q n 0 10 20 30 40 50 60 70 80 Contact Pressure psi Figure 25 Thermal Perf
16. 1s Up to 8 outstanding out of order cache misses between dL1 and L2 bus Up to 7 outstanding out of order transactions on the bus Load folding to fold new dL1 misses into older outstanding load and store misses to the same line Store miss merging for multiple store misses to the same line Only coherency action taken i e address only for store misses merged to all 32 bytes of a cache line no data tenure needed 2 entry finished store queue and 4 entry completed store queue between load store unit and dL1 Separate additional queues for efficient buffering of outbound data castouts write throughs etc from dL1 and L2 Bus interface New MPX bus extension to 60X processor interface Mode compatible with 60x processor interface 32 bit address bus 64 bit data bus Bus to core frequency multipliers of 2x 2 5x 3x 3 5x 4x 4 5x 5x 5 5x 6x 6 5x 7x 7 5x 8x supported Selectable interface voltages of 1 8 and 3 3V Power management Low power design with thermal requirements very similar to MPC740 and MPC750 1 8 volt processor core Selectable interface voltages below 3 3V can reduce power in output buffers Three static power saving modes doze nap and sleep Dynamic power management Testability LSSD scan design IEEE 1149 1 JTAG interface Array built in self test ABIST factory test only Redundancy on L1 data arrays and L2 tag arrays Reliability and serviceability Parity checking on 60x and L2 cache buse
17. 3 147 122 105 400 200 160 133 114 100 Note 1 The core and L2 frequencies are for reference only Some examples may represent core or L2 frequencies which are not useful not supported or not tested for by the MPC7400 see Section 1 4 2 3 L2 Clock AC Specifications for valid L2CLK frequencies The L2CR L2SL bit should be set for L2CLK frequencies less than 110 MHz 1 8 2 PLL Power Supply Filtering The AVdd and L2AVdd power signals are provided on the MPC7400 to provide power to the clock generation phase locked loop and L2 cache delay locked loop respectively To ensure stability of the internal clock the power supplied to the AVdd input signal should be filtered of any noise in the 500kHz to 10MHz resonant frequency range of the PLL A circuit similar to the one shown in Figure 18 using surface mount capacitors with minimum Effective Series Inductance ESL is recommended 32 MPC7400 RISC Microprocessor Hardware Specifications AX MOTOROLA PREL INEO N reS HAG Gor HON ThS BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc System Design Information The circuit should be placed as close as possible to the AVdd pin to minimize noise coupled from nearby circuits An identical but separate circuit should be placed as close as possible to the L2AVdd pin It is often possible to route directly from the capacitors to the AVdd pin which is on the periphery of the 360 CBGA footprint without the inductance
18. 350 400 MHz Parameter Symbol Unit Notes Address Transfer Attribute TS ABB DBB Data Data Parity ARTRY SHDO SHD1 All Other Outputs Output Hold Times SYSCLK to Output Enable knoe Cet SYSCLK to Output High Impedance all except TS ABB ae AMON 0 ARTRY SHD DBB DMON 0 SYSCLK to TS ABB AMON 0 DBB DMON 0 High tKHABPZ teil 5 11 13 Impedance after precharge Maximum Maximum Delay to ARTRY SHDO SHDI Precharge gt to ARTRY SHDO SHD1 Precharge tknarp hp ee eee ee 5 12 13 SYSCLK to ARTRY SHDO SHD1 High Impedance Fee eal tKHARPZ feysclk 5 12 13 Precharge re AD MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 15 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Table 9 Processor Bus AC Timing Specifications Continued At Vdd AVdd 1 8V 100mV 0 lt Tj lt 105 C OVdd 3 3V4165mV or OVdd 2 5V 100mV or OVdd 1 8V 100mV 350 400 MHz Parameter Symbol Unit Notes Notes 1 All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal in question All output timings assume a purely resistive 50 ohm load See Figure 4 Input and output timings are measured at the pin time of flight delays must be a
19. Freescale Semiconductor Inc Order Number MPC7400EC D MOTOROLA Rev 1 1 11 2000 Semiconductor Products Sector eWwerPec Advance Information MPC7400 RISC Microprocessor Hardware Specifications The MPC7400 is an implementation of the PowerPC family of reduced instruction set computing RISC microprocessors This document describes pertinent electrical and physical characteristics of the MPC7400 For functional characteristics of the processor refer to the MPC7400 RISC Microprocessor User s Manual This document contains the following topics Topic Page Section 1 1 Overview 2 Section 1 2 Features 4 Section 1 3 General Parameters 7 Section 1 4 Electrical and Thermal Characteristics 7 Section 1 5 Pin Assignments 25 Section 1 6 Pinout Listings 26 Section 1 7 Package Description 29 Section 1 8 System Design Information 31 Section 1 9 Document Revision History 43 Section 1 10 Ordering Information 43 To locate updates for this document refer to the website at http www motorola com sps For the most current part errata document please contact your Motorola Sales Office This document contains information on a new product under development by Motorola Motorola reserves the right to change or discontinue this product without notice ate Digital DNA Motorola Inc 2000 All rights reserved Fram Motorola PRELIMINARY SUBJECT TO CHANGE WITHOUT N
20. Gor HON ThS BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc System Design Information There is no standardized way to number the COP header shown in Figure 22 consequently many different pin numbers have been observed from emulator vendors Some are numbered top to bottom then left to right while others use left to right then top to bottom while still others number the pins counter clockwise from pin one as with an IC Regardless of the numbering the signal placement recommended in Figure 22 is common to all known emulators The QACK signal shown in Table 17 is usually hooked up to the PCI bridge chip in a system and is an input to the MPC7400 informing it that it can go into the quiescent state Under normal operation this occurs during a low power mode selection In order for COP to work the MPC7400 must see this signal asserted pulled down While shown on the COP header not all emulator products drive this signal To preserve correct power down operation QACK should be merged so that it also can be driven by the PCI bridge Table 17 shows the pin definitions Table 17 COP Pin Definitions Pins Signal Connection Special Notes 1 TDO TDO 2 QACK QACK Add 2K pulldown to ground Must be merged with on board QACK if any 3 TDI TDI 4 TRST TRST Add 2K pulldown to ground Must be merged with on board TRST if any See Figure 21 5 RU
21. Hz 75 MHz 100 MHz Multiplier Multiplier ae ef Cm e ea e e EER ER Sr a a a o 1010 300 600 400 idl ed 0111 337 675 450 900 R i S fe Pe 1011 375 750 O l S e a 1001 S l l ee 1101 300 600 400 450 900 O l Pe P 0101 6 5x 2x 325 433 ee l ee o a a i e 0001 7 5x Noell Gel il 9 a a 1100 O i e d 0000 9x 2x 300 450 r e d PLL off SYSCLK clocks core circuitry directly 1x bus to core implied A MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 31 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc System Design Information Table 14 MPC7400 Microprocessor PLL Configuration Continued Example Bus to Core Frequency in MHz VCO Frequency in MHz PLL_CFG z Bus to Core to Bus Bus 0 3 Core vco Bus 33 3 Bas 66 6 Pus Be Multiplier Multiplier peat MHz 29 MHZ MHz FRA 100 MHz 1111 PLL off PLL off no core clocking occurs Notes 1 PLL_CFG 0 3 settings not listed are reserved 2 The sample bus to core frequencies shown are for reference only Some PLL configurations may select bus core or VCO frequencies which are not useful not supported or not tested for by the MPC7400 see Section 1 4 2 1 Clock AC Specifications for valid SYSCLK core and VCO frequencies 3 In PLL bypass mode the SYSCLK input signal clocks the internal processor directly the PLL is disabled and the bus mode is set for 1 1 mode operation This mod
22. L MISSING FROM THE ARRAY E Millimeters DIM MIN MAX A 2 65 3 20 Al 0 79 0 99 A2 L10 1 30 A3 0 6 n A4 0 82 0 9 i b 0 82 0 93 CL L20VDD 1234567 8 9101112131415 16 Cle GND 4 os T y C2 L20VDD PA 7 MN C2 2 GND Gee N A i C3 VDD A gt E C32 GND e L C4 OVDD H A3 lt T C42 GND T ee el a A c5 OVDD D Al C5 2 GND c KIA C6 VDD 4 C6 2 GND D 25 00 BSC e D2 9 6 typ 255X b gt ba e 1 27 BSC le 0 3 C Al B E 25 00 BSC 0 15 lc E2 12 3 typ E3 10 58 J1 0 89 BSC n2 3 2 BSC B 0 68 BSC Kl 6 56 K2 8 13 LI 9 04 L2 747 M 2 00 Figure 17 Mechanical Dimensions and Bottom Surface Nomenclature of the MPC7400 30 MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PRELINAS Wires HABEAREN This BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc System Design Information 1 8 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC7400 1 8 1 PLL Configuration The MPC7400 s PLL is configured by the PLL_CFG 0 3 signals For a given SYSCLK bus frequency the PLL configuration signals set the internal CPU and VCO frequency of operation The PLL configuration for the MPC7400 is shown in Table 14 for example frequencies Table 14 MPC7400 Microprocessor PLL Configuration Example Bus to Core Frequency in MHz VCO Frequency in MHz PLL_CFG io 7 0 3 Te ee Bus Bus Bus Bus yas ss 25 MHz 50 M
23. N STOP No Connect Used on 604e leave no connect for all other processors 6 VDD_SENSE VDD Add 2K pullup to OVDD for short circuit limiting protection only 7 TCK TCK 8 CKSTP_IN CKSTP_IN Optional Add 10K pullup to OVDD Used on several emulator products Useful for checkstopping the processor from a logic analyzer of other external trigger 9 TMS TMS 10 N A 11 SRESET SRESET Merge with on board SRESET if any 12 N A 13 HRESET HRESET Merge with on board HRESET 14 N A Key location pin should be removed 15 CKSTP_OUT CKSTP_OUT Add 10K pullup to OVDD 16 Ground Digital Ground 1 8 9 Thermal Management Information This section provides thermal management information for the ceramic ball grid array CBGA package for air cooled applications Proper thermal control design is primarily dependent upon the system level design the heat sink airflow and thermal interface material To reduce the die junction temperature heat sinks may be attached to the package by several methods adhesive spring clip to holes in the printed circuit board or package and mounting clip and screw assembly see Figure 23 This spring force should not exceed 5 5 pounds of force Y MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 37 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc System Design Information CBGA Package Heat Sink Heat Sink gt Clip Adhesive
24. N3 Low Input vV vV vV ABB L7 Low Output vV vV vV 12 AMON 0 AP 0 3 C4 C5 C6 C7 High vo v v v ARTRY L6 Low I O vV v vV AVDD A8 Input 1 8V 1 8V 1 8V BG H1 Low Input vV vV vV BR E7 Low Output vV v vV BVSEL Wi High Input GND HRESET 3 3V 3 8 9 CHK Kill Low Input v Vv Vv 4 8 9 CI C2 Low T O vV vV CKSTP_IN B8 Low Input vV v vV CKSTP_OUT D7 Low Output vV v vV CLK_OUT E3 High Output v v v DBB K5 Low Output vV vV V 12 DMON 0 DBG K1 Low Input vV v vV DH 0 31 W12 W11 V11 T9 W10 U9 U10 High Vo vV v vV M11 M9 P8 W7 P9 W9 R10 W6 V7 V6 U8 V9 T7 U7 R7 U6 W5 U5 W4 P7 V5 V4 W3 U4 R5 DL 0 31 M6 P3 N4 N5 R3 M7 T2 N6 U2 High vO v v v N7 P11 V13 U12 P12 T13 W13 U13 V10 W8 T11 U11 V12 V8 T1 P1 V1 U1 N1 R2 V3 U3 W2 DP 0 7 L1 P2 M2 V2 M1 N2 T3 R1 High VO v v v DRDY K9 Low Output v Vv Vv 6 8 13 DBWO D1 Low Input vV v vV DTI 0 DTI 1 2 H6 G1 High Input vV v vV 10 13 EMODE A3 Low Input vV vV V 7 10 26 MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PRELIM res HARSH REON Fe HOWTO TICE Go to www freescale com Pinout Listings Freescale Semiconductor Inc Table 13 Pinout Listing for the MPC7400 360 CBGA Package Continued I F Voltages Supported Signal Name Pin Number Active T O 1 8v 2 5v 3 3v Notes GBL B1 Low Y O vV v vV GND D10 D14 D16 D4 D6
25. OLA PRELIM reS HAG Gor HON This BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics The minimum L2CLK frequency of Table 10 is specified by the maximum delay of the internal DLL The variable tap DLL introduces up to a full clock period delay in the L2CLKOUTA L2CLKOUTB and L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase aligned with the next core clock divided by the L2 divisor ratio Do not choose a core to L2 divisor which results in an L2 frequency below this minimum or the L2ACLKOUT signals provided for SRAM clocking will not be phase aligned with the MPC7400 core clock at the SRAMs The maximum L2CLK frequency shown in Table 10 is the core frequency divided by one Very few L2 SRAM designs will be able to operate in this mode Most designs will select a greater core to L2 divisor to provide a longer L2CLK period for read and write access to the L2 SRAMs The maximum L2CLK frequency for any application of the MPC7400 will be a function of the AC timings of the MPC7400 the AC timings for the SRAM bus loading and printed circuit board trace length Motorola is similarly limited by system constraints and cannot perform tests of the L2 interface on a socketed part on a functional tester at the maximum frequencies of Table 10 Therefore functional operation and AC timing information are tested at core to L2 divisors of 2 or greater L2 input and output signals are
26. OTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Overview 1 1 Overview The MPC7400 is the first implementation of the fourth generation G4 of PowerPC microprocessors from Motorola The MPC7400 implements the full PowerPC 32 bit architecture and is targeted at both portable and computing systems applications Some comments on the MPC7400 with respect to MPC750 e The MPC7400 adds an implementation of the new AltiVec technology instruction set e The MPC7400 includes significant improvements in memory subsystem MSS bandwidth and offer s an optional high bandwidth MPX bus interface e The MPC7400 adds full hardware based multiprocessing capability including a 5 state cache coherency protocol 4 MESI states plus a fifth state for shared intervention e The MPC7400 is implemented in a next generation process technology for core frequency improvement e The MPC7400 floating point unit has been improved to make latency equal for double precision and single precision operations involving multiplication e The completion queue has been extended to 8 slots e There are no other significant changes to scalar pipelines decode dispatch completion mechanisms or the branch unit The MPC750 s 4 stage pipeline model is unchanged fetch decode dispatch execute complete writeback Figure 1 shows a block diagram of the MPC7400 MPC7400 RISC Microprocessor Hardware Specificati
27. TSXKH gt lt tpxKH tovKH gt a gt lt t tARVKH gt lt ARXKH VKH gt a PS XKH tky gt lt tkHAX Ea m tkypv gt tkHDPV lt tkupx TET Mm tkHov gt a t ALL OUTPUTS _ KOX ExcepL TS ABB Xx DX X ARTRY DBB tKHOE gt lt gt tkHOZ ALL OUTPUTS Except TS ABB ARTRY DBB KHABPZ tkHTSV gt lt gt KHTSX TS gt tkHTsv ABB AMON 0 DBB DMON 0 lt UKHARPZ kKHARV gt zal Mm IKHARV lt tkHarp gt ARTRY a KHARX SHDO X SHD1 VM Midpoint Voltage OVpp 2 Figure 6 Input Output Timing Diagram 1 4 2 3 L2 Clock AC Specifications The L2CLK frequency is programmed by the L2 Configuration Register L2CR 4 6 core to L2 divisor ratio See Table 15 for example core and L2 frequencies at various divisors Table 10 provides the potential range of L2CLK output AC timing specifications as defined in Figure 7 The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the L2SYNC_IN input of the MPC7400 to synchronize L2CLKOUT at the SRAM with the processor s internal clock LZ2CLKOUT at the SRAM can be offset forward or backward in time by shortening or lengthening the routing of L2ASYNC_OUT to L2SYNC_IN See Motorola Application Note AN179 D PowerPC Backside L2 Timing Analysis for the PCB Design Engineer 18 MPC7400 RISC Microprocessor Hardware Specifications AX MOTOR
28. V 2 5 JTAG Signals V 0 3 to 3 6 V Storage temperature range Tstg 55 to 150 C Notes 1 Functional and tested operating conditions are given in Table 3 Absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed Stresses beyond those listed may affect device reliability or cause permanent damage to the device 2 Caution Vin must not exceed OVdd or L2OVdd by more than 0 3V at any time including during power on reset 3 Caution L2ZOVdd OVdd must not exceed Vdd AVdd L2AVdd by more than 2 0V at any time including during power on reset AN MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 7 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics 4 Caution Vdd AVdd L2AVdd must not exceed L2OVdd OVdd by more than 0 4V at any time including during power on reset In addition operation at nominal Vdd AVdd L2AVdd greater than nominal L2OVdd or OVdd in the 1 8V input threshold select mode can cause erratic operation and AC timing values worse than described in this specification 5 Vin may overshoot undershoot to a voltage and for a maximum duration as shown in Figure 2 Figure 2 shows the undershoot and overshoot voltage on the MPC7400 L2 OVdd 20 L2 OVdd 5 L2 OVdd Gnd Gnd 3V Gnd 0 7V l Notto excee
29. a cache tags for efficient snooping No snooping of instruction cache except for ICBI instruction e Level 2 L2 cache interface Internal L2 cache controller and tags external data SRAMs 512K 1M and 2Mbyte 2 way set associative L2 cache support Copyback or write through data cache on a page basis or for all L2 32 byte 512K 64 byte 1M or 128 byte 2M sectored line size Supports pipelined register register synchronous burst SRAMs and pipelined register register late write synchronous burst SRAMs Core to L2 frequency divisors of 1 1 5 2 2 5 3 3 5 and 4 supported 64 bit data bus Selectable interface voltages of 1 8 2 5 and 3 3V A MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc Features Memory management unit 128 entry 2 way set associative instruction TLB 128 entry 2 way set associative data TLB Hardware reload for TLBs 4 instruction BATs and 4 data BATs Virtual memory support for up to 4 exabytes 25 of virtual memory Real memory support for up to 4 gigabytes 233 of physical memory Snooped and invalidated for TLBI instructions Efficient data flow All data buses between VRF load store unit dL1 iL1 L2 and the bus are 128 bits wide dL1 is fully pipelined to provide 128 bits cycle to from the VRF L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L
30. d 10 q4 of tsyscLK Figure 2 Overshoot Undershoot Voltage The MPC7400 provides several I O voltages to support both compatibility with existing systems and migration to future systems The MPC7400 core voltage must always be provided at nominal 1 8V see Table 3 for actual recommended core voltage Voltage to the L2 I Os and processor interface I Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 2 The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET The output voltage will swing from GND to the maximum voltage applied to the OVdd or L2OVdd power pins Table 2 Input Threshold Voltage Setting BSEL Sigal pec Ra tavseLsiga TAP m Theol a 0 1 8V 0 1 8 1 HRESET 2 5V HRESET 2 5 1 2 1 3 3V 1 3 3 1 Notes 1 Caution The input threshold selection must agree with the OVdd L2OVdd voltages supplied 2 To select the 2 5 volt threshold option L2VSEL BVSEL should be tied to HRESET so that the two signals change state together 8 MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PRELIM reS HAG Gor HON This BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Table 3 provides the recommended operating conditions for the MPC7400 Table 3 Recommended Operating Conditions
31. d until the voltage at the pad equals OVdd 2 Rp then becomes the resistance of the pull up devices Rp and Ry are designed to be close to each other in value OVdd Ry SG sw2 o Pad Data e va Swl Rp OGND Figure 20 Driver Impedance Measurement 34 MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PREL INEO N reS HAG Gor HON ThS BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc System Design Information Table 16 summarizes the signal impedance results The driver impedance values were characterized at 0 C 65 C and 105 C The impedance increases with junction temperature and is relatively unaffected by bus voltage Table 16 Impedance Characteristics Vdd 1 8V OVdd 3 3V Tj 0 105 C Impedance Processor bus L2 bus Symbol Unit Ry 32 43 39 48 Zo Ohms Rp 36 48 41 50 Zo Ohms 1 8 7 Pull up Resistor Requirements The MPC7400 requires high resistive weak 10 KQ pull up resistors on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the MPC7400 or other bus masters These pins are TS ARTRY SHDO and SHD1 In addition the MPC7400 has one open drain style output that requires a pull up resistor weak or stronger 4 7 KQ 10 KQ if it is used by the system This pin is CKSTP_OUT During inactive periods on the bus the address and transfer attrib
32. dded for trace lengths vias and connectors in the system 2 The symbology used for timing specifications herein follows the pattern of t sjsnaly state reference state fOr inputs and U reference state signal state for outputs For example trygy symbolizes the time input signals I reach the valid state V relative to the SYSCLK reference K going to the high H state or input setup time And tgyoy symbolizes the time from SYSCLK K going high H until outputs O are valid V or output valid time Input hold time can be read as the time that the input signal I went invalid X with respect to the rising clock edge KH note the position of the reference and its state for inputs and output hold time can be read as the time from the rising edge KH until the output went invalid OX For additional explanation of AC timing specifications in Motorola PowerPC microprocessors see the application note Understanding AC Timing Specifications for PowerPC Microprocessors 3 The setup and hold time is with respect to the rising edge of HRESET see Figure 5 4 This specification is for configuration mode select only Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the PLL re lock time during the power on reset sequence 5 tsysctk 18 the period of the external clock SYSCLK in nanoseconds ns The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time dura
33. e L2 cache interface L2ADDR 0 16 L2ASPARE L2DATA 0 63 L2DP 0 7 and L2SYNC OUT and the L2 control signals and Vdd supplies power to the processor core and the PLL and DLL after filtering to become AVDD and L2AVDD respectively These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL L2VSEL pin configurations of Table 2 and the voltage supplied For actual recommended value of Vin or supply voltages see Table 3 2 These are test signals for factory use only and must be pulled up to OVdd for normal machine operation 28 MPC7400 RISC Microprocessor Hardware Specifications PRELIM reS HAG Gor ThS BEGUN OTICE Go to www freescale com O MOTOROLA Freescale Semiconductor Inc Package Description 3 To allow for future I O voltage changes provide the option to connect BVSEL and L2VSEL independently to either OVDD selects 3 3v OGND selects 1 8v or to HRESET selects 2 5v The Processor bus and L2 bus support all 3 options See Table 2 Input Threshold Voltage Setting 4 Connect to HRESET to trigger post power on reset por internal memory test 5 Ignored in 60x bus mode 6 Unused output in 60x bus mode 7 Deasserted pulled high at HRESET for 60x bus mode 8 Uses one of 9 existing no connects in MPC750 s 360 BGA package 9 Internal pull up on die 10 Reuses MPC750 s DRTRY DBDIS and TLBISYNC pins DTI1 DTI2 and EMODE respectively 11 Th
34. e VOLTDET pin position on the MPC750 360 CBGA package is now an LZOVDD pin on the MPC7400 360 CBGA package 12 Output only for MPC7400 was I O for MPC750 13 Enhanced mode only 1 7 Package Description The following sections provide the package parameters and mechanical dimensions for the MPC7400 360 CBGA packages 1 7 1 Package Parameters for the MPC7400 The package parameters are as provided in the following list The package type is 25 x 25 mm 360 lead ceramic ball grid array CBGA Package outline 25 x 25 mm Interconnects 360 19 x 19 ball array 1 Pitch 1 27 mm 50 mil Minimum module height 2 65 mm Maximum module height 3 20 mm Ball diameter 0 89 mm 35 mil AD MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 29 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc Package Description 1 7 2 Mechanical Dimensions of the MPC7400 Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the MPC7400 360 CBGA package 2X a o2 NOTES 1 DIMENSIONING AND TOLERANCING D A PER ASME Y14 5M 1994 CORNE DIMENSIONS IN MILLIMETERS TOP SIDE Al CORNER INDEX IS A o METALIZED FEATURE WITH VARIOUS SHAPES BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BAL
35. e is intended for factory use only Note The AC timing specifications given in this document do not apply in PLL bypass mode 4 In PLL off mode no clocking occurs inside the MPC7400 regardless of the SYSCLK input The MPC7400 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock frequency of the MPC7400 The divided down clock is then phase adjusted by an on chip delay lock loop DLL circuit and should be routed from the MPC7400 to the external RAMs A separate clock output L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin L2SYNC_IN so that the rising edge of the clock as seen at the external RAMs can be aligned to the clocking of the internal latches in the L2 bus interface The core to L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register Generally the divisor must be chosen according to the frequency supported by the external RAMs the frequency of the MPC7400 core and the phase adjustment range that the L2 DLL supports Table 15 shows various example L2 clock frequencies that can be obtained for a given set of core frequencies The minimum L2 frequency target is 1OOMHz Table 15 Sample Core to L2 Frequencies Core Frequency in MHz 1 1 5 2 2 5 3 3 5 4 300 300 200 150 120 100 333 333 222 166 133 111 350 175 140 117 100 366 18
36. emiconductor Inc System Design Information Figure 24 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed circuit board External Resistance Radiation Convection Heat Sink Thermal Interface Material HH Die Package Die Junction Internal Resistance Package Leads Printed Circuit Board Radiation Convection External Resistance Note the internal versus external package resistance Figure 24 C4 Package with Heat Sink Mounted to a Printed Circuit Board Heat generated on the active side of the chip is conducted through the silicon then through the heat sink attach material or thermal interface material and finally to the heat sink where it is removed by forced air convection Since the silicon thermal resistance is quite small for a first order analysis the temperature drop in the silicon may be neglected Thus the heat sink attach material and the heat sink conduction convective thermal resistances are the dominant terms 1 8 9 2 Adhesives and Thermal Interface Materials A thermal interface material is recommended at the package lid to heat sink interface to minimize the thermal contact resistance For those applications where the heat sink is attached by spring clip mechanism Figure 25 shows the thermal performance of three thin sheet thermal interface materials silicone graphite oil floroether oil a bare joint and a joint
37. inimum operating frequencies The maximum L2LCK frequency will be system dependent L2CLK_OUTA and L2CLK_OUTB must have equal loading 2 The nominal duty cycle of the L2CLK is 50 measured at midpoint voltage 3 The DLL re lock time is specified in terms of L2CLKs The number in the table must be multiplied by the period of L2CLK to compute the actual time duration in nanoseconds Re lock timing is guaranteed by design and characterization 4 The L2CR L2SL bit should be set for L2CLK frequencies less than 110 MHz This adds more delay to each tap of the DLL A MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 19 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics 5 Allowable skew between L2SYNC_OUT and L2SYNC_IN 6 Guaranteed by design and not tested This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase difference between L2S YNC_IN and the internal L2CLK This number must be comprehended in the L2 timing analysis The input jitter on SYSCLK affects L2CLKOUT and the L2 address data control signals equally and therefore is already comprehended in the AC timing and does not have to be considered in the L2 timing analysis The L2CLK_OUT timing diagram is shown in Figure 7 L2 Single Ended Clock Mode tL2CR tLocr
38. ization Decode Register file access Forwarding control Partial instruction decode Completion 8entry completion buffer Instruction tracking and peak completion of two instructions per cycle Completion of instructions in program order while supporting out of order instruction execution completion serialization and all instruction flow changes Fixed point units FXUs that share 32 GPRs for integer operands Fixed point unit 1 FXU1 multiply divide shift rotate arithmetic logical Fixed point unit 2 FXU2 shift rotate arithmetic logical Single cycle arithmetic shifts rotates logical Multiply and divide support multi cycle Early out multiply Three stage floating point unit and a 32 entry FPR file Support for IEEE 754 standard single and double precision floating point arithmetic 3cycle latency 1 cycle throughput single or double precision Hardware support for divide Hardware support for denormalized numbers Time deterministic non IEEE mode System unit Executes CR logical instructions and miscellaneous system instructions Special register transfer instructions MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PRELIM reS HAG Gor HON This BEGUN OTICE Go to www freescale com Features Freescale Semiconductor Inc e AltiVec Unit Full 128 bit data paths Two dispatchable units vector permute unit and vector ALU
39. l Characteristics 4 Capacitance is periodically sampled rather than 100 tested 5 The leakage is measured for nominal OVdd and Vdd or both OVdd and Vdd must vary in the same direction for example both OVdd and Vdd vary by either 5 or 5 Table 7 provides the power consumption for the MPC7400 Table 7 Power Consumption for MPC7400 Processor CPU Frequency Unit Notes 350 MHz 400 MHz Full On Mode Typical 4 6 5 3 WwW 1 3 Marmori 9 9 11 3 W 1 2 4 Doze Mode Maximum 4 4 5 0 W 1 2 Nap Mode Maximum 1 75 2 0 W 1 2 Sleep Mode Maximum 1 75 2 0 W Y2 Sleep Mode PLL and DLL Disabled Typical 600 600 mW 1 3 Maximum 1 0 1 0 W 1 2 Notes 1 These values apply for all valid processor bus and L2 bus ratios The values do not include T O Supply Power OVdd and L2OVdd or PLL DLL supply power AVdd and L2AVdd OVdd and L2OVdd power is system dependent but is typically lt 10 of Vdd power Worst case power consumption for AVdd 15 mw and L2AVdd 15 mW 2 Maximum power is measured at Vdd 1 9V while running an entirely cache resident contrived sequence of instructions which keep the execution units including AltiVec maximally busy 3 Typical power is an average value measured at Vdd AVdd L2AVdd 1 8V OVdd L2OVdd 3 3V in a system while running a codec application that is AltiVec intensive 4 These values include the use of AltiVec Without AltiVec operation estima
40. mber of factors affect the final operating die junction temperature airflow board population local heat flux of adjacent components heat sink efficiency heat sink attach heat sink placement next level interconnect technology system air temperature rise altitude etc Due to the complexity and the many variations of system level boundary conditions for today s microelectronic equipment the combined effects of the heat transfer mechanisms radiation convection and conduction may vary widely For these reasons we recommend using conjugate heat transfer models for the board as well as system level designs 42 MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PREL INEO N reS HAG Gor HON ThS BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc Document Revision History 1 9 Document Revision History Table 18 provides a revision history for this hardware specification Table 18 Document Revision History Document Revision Substantive Change s Rev 0 Initial release Rev 1 Added 2 5 V support for Processor Bus Raised Min Core Frequency and lowered Max Sysclk Frequency in Table 8 Reduced L2 Output Hold Time for L2CR 14 15 00 from 0 6ns to 0 4ns in Table 11 Reduced 400 MHz SYSCLK from 133 MHz to 10O0MHz in Table 8 Rev 1 1 Table 3 adds notes on extended temperature parts Figure 27 adds Application Modifier for extended temperature Figure 17 adds capacitor pad dimensions Fixed
41. n L2CR 14 15 01 All outputs when L2CR 14 15 10 F All outputs when L2CR 14 15 11 Output Hold Times tL2CHOX 3 All outputs when L2CR 14 15 00 0 4 All outputs when L2CR 14 15 01 D i All outputs when L2CR 14 15 10 1 8 z All outputs when L2CR 14 15 11 L2SYNC_IN to high impedance tLocHoz ns All outputs when L2CR 14 15 00 2 0 All outputs when L2CR 14 15 01 ar All outputs when L2CR 14 15 10 z 3 5 All outputs when L2CR 14 15 11 Notes 1 Rise and fall times for the L2SYNC_IN input are measured from 20 to 80 of L2OVdd 2 All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input L2SYNC_IN see Figure 8 Input timings are measured at the pins 3 All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the signal in question The output timings are measured at the pins All output timings assume a purely resistive 50 ohm load See Figure 10 4 The outputs are valid for both single ended and differential L2CLK modes For pipelined registered synchronous burst RAMs L2CR 14 15 00 is recommended For pipelined late write synchronous burst SRAMs L2CR 14 15 10 is recommended Figure 8 shows the L2 bus input timing diagrams for the MPC7400 tLacr L2SYNC_IN tDvL2cHu gt tDXL2CH L2 DATA AND D PARITY INPUTS VM Midpoint Voltage LZOVp
42. nt Comments FAX 512 895 2638 Attn RISC Applications Engineering World Wide Web Addresses http www motorola com PowerPC http www motorola com netcomm http www motorola com Coldfire MPC7400EC D AA MOTOROLA For More Information On This Product Go to www freescale com
43. of vias The L2AVdd pin may be more difficult to route but is proportionately less critical 10 Q Vdd WN oe pa AVdd or L2AVdd 2 2 uF 2 2 uF Low ESL surface mount capacitors GND Figure 18 PLL Power Supply Filter Circuit 1 8 3 Power Supply Voltage Sequencing The notes in Table 1 contain cautions about the sequencing of the external bus voltages and core voltage of the MPC7400 when they are different These cautions are necessary for the long term reliability of the part If they are violated the ESD Electrostatic Discharge protection diodes will be forward biased and excessive current can flow through these diodes If the system power supply design does not control the voltage sequencing one or both of the circuits of Figure 19 can be added to meet these requirements The MUR420 Schottky diodes of Figure 19 control the maximum potential difference between the external bus and core power supplies on power up and the 1N5820 diodes regulate the maximum potential difference on power down 3 3V 1 8V 2 5V 1 8V ace eee eee MUR420 MUR420 A A A 1N5820 1N5820 1N5820 1N5820 Figure 19 Example Voltage Sequencing Circuits 1 8 4 Decoupling Recommendations Due to the MPC7400 s dynamic power management feature large address and data buses and high operating frequencies the MPC7400 can generate transient power surges and high frequency noise in its power supply especially while driving large capacitive loads
44. on to case thermal resistance intis the adhesive or interface material thermal resistance Osa is the heat sink base to ambient thermal resistance P is the power dissipated by the device During operation the die junction temperatures Tj should be maintained less than the value specified in Table 3 The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet An electronic cabinet inlet air temperature T may range from 30 to 40 C The air temperature rise within a cabinet T may be in the range of 5 to 10 C The thermal resistance of the thermal interface material 0 is typically about 1 C W Assuming a T of 30 C a Trof 5 C a CBGA package 8 0 03 and a power consumption Pg of 5 0 watts the following expression for T is obtained Die junction temperature Tj 30 C 5 C 0 03 C W 1 0 C W Osa 5 0 W For a Thermalloy heat sink 2328B the heat sink to ambient thermal resistance 0 versus airflow velocity is shown in Figure 26 AD MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 41 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc System Design Information 8 H t T f Thermalloy 2328B Pin fin Heat Sink J inl Degas ao al a 25 x28 x 15 mm I T GE E A Fe 5 fF E 9 L 4 A e cus ts ease Sanne
45. ons O MOTOROLA PRELIM reS HAG Gor HON This BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc Overview lt sng Bed CT Wa 8cl 79 z ai NNO We TT uonoesuely SSI ZIT ee TT wun pu sng 7T sng SSoIppV CT g 61 3 sng Bed XVN Wa 8cl Snd LWA X09 NQ V9 onond suoneIodo T uonon ysu sng SsoIppV XVW X09 TE QLL PLoPA anand PIO peo anand peopy anand AQL uononysu pLopy eq propey ea yun 2U sng J209 Jad suoyonnsur 0M 0 dn g jdwos 07 Aq y nug 8 Jojjng Iaplooy xun uonetduiog wYOSdH 3101S poyo durod X wun mod Sueo Soffa gd URU 9 uoneys UOTVAIOSOY Anug Z UOLIS UOTCAIOSIY WE 8CI T uN T xun siaygng OUILUDY 9 IQUI 193U uoneis uOTRAIOSOY uones uonPAlasay uoneys UOTRAIOSOY NIDA NAISA xun amud 1I0 99A siojgng MTN OREA WLU 9 A AA uonels UONPAIASOY uones UOTRAIOSOY suononysu 7 Wq 79 4 CUISLIO SAS MmOpeyS SAS NWN vononnsuy
46. ormance of Select Thermal Interface Material The board designer can choose between several types of thermal interface Heat sink adhesive materials should be selected based upon high conductivity yet adequate mechanical strength to meet equipment shock vibration requirements There are several commercially available thermal interfaces and adhesive materials provided by the following vendors Dow Corning Corporation 517 496 4000 Dow Corning Electronic Materials PO Box 0997 Midland MI 48686 0997 Chomerics Inc 617 935 4850 77 Dragon Court Woburn MA 01888 4850 Thermagon Inc 216 741 7659 3256 West 25th Street Cleveland OH 44109 1668 Loctite Corporation 860 571 5100 1001 Trout Brook Crossing Rocky Hill CT 06067 AI Technology e g EG7655 609 882 2332 1425 Lower Ferry Rd Trent NJ 08618 40 MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PREL INEO N reS HAG Gor HON ThS BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc System Design Information 1 8 9 3 Heat Sink Selection Example The following section provides a heat sink selection example using one of the commercially available heat sinks For preliminary heat sink sizing the die junction temperature can be expressed as follows T Ta T Oje Oint Osa Pa Where T is the die junction temperature T is the inlet cabinet ambient temperature T is the air temperature rise within the computer cabinet Oje is the juncti
47. ow in the first clock following AACK will then go to high Z for one clock before precharging it high during the second cycle after the assertion of AACK The nominal precharge width for ARTRY is 1 0 tyy ci i e it should be high Z as shown in Figure 6 before the first opportunity for another master to assert ARTRY Output valid and output hold timing is tested for the signal asserted Output valid time is tested for precharge The high Z behavior is guaranteed by design 13 Guaranteed by design and not tested 16 MPC7400 RISC Microprocessor Hardware Specifications AX MOTOROLA PREL INEO N reS HAG Gor HON ThS BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Figure 4 provides the AC test load for the MPC7400 OUTPUT Zo 502 JNNA OVdd 2 RL 502 Figure 4 AC Test Load Figure 5 provides the mode select input timing diagram for the MPC7400 HRESET VM tuyru gt gt twxRH VM Midpoint Voltage OVpp 2 Figure 5 Mode Input Timing Diagram AD MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications PRELIME Gr Mor intormation On This product CE Go to www freescale com 17 Freescale Semiconductor Inc Electrical and Thermal Characteristics Figure 6 provides the input output timing diagram for the MPC7400 SYSCLK VM VM VM tavKH e FAXKH t trsvkH gt 7e
48. p 2 Figure 8 L2 Bus Input Timing Diagrams AD MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 21 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Figure 9 shows the L2 bus output timing diagrams for the MPC7400 L2SYNC_IN tL2CHOV gt gt lt tL2CHOX ALL OUTPUTS tL2CHOZ L2DATA BUS VM Midpoint Voltage L2ZOVpp 2 Figure 9 L2 Bus Output Timing Diagrams Figure 10 provides the AC test load for L2 interface of the MPC7400 Ry 502 Figure 10 AC Test Load for the L2 Interface 1 4 2 5 IEEE 1149 1 AC Timing Specifications Table 12 provides the IEEE 1149 1 JTAG AC timing specifications as defined in Figure 12 Figure 13 Figure 14 and Figure 15 Table 12 JTAG AC Timing Specifications Independent of SYSCLK At recommended operating conditions See Table 3 Parameter Symbol Min Max Unit Notes TCK frequency of operation fTCLK 0 33 3 MHz TCK cycle time t TCLK 30 ns TCK clock pulse width measured at 1 4V tye 15 ns TCK rise and fall times typ amp typ 0 2 ns TRST assert time trrst 25 ns 2 Input Setup Times ns Boundary scan data tpyJg 4 3 TMS TDI tryyq 0 Input Hold Times ns Boundary scan data tpxyyq 20 3 TMS TDI trxj 25 22 MPC7400 RISC Microprocessor Hardware Specification
49. p surface view Part A Part B Y MOTOROLA 2 lt CH WUZ ZTA TTA TDM BVA gt 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 OOO OOOO VOODOO OO0OO OOO OOOO OOO OC OOOO OOOOC OOO OOOOOOOC MOO OOOO O0OO 0OOCOO00 BOO OO OOOO O0OO OOOO OPOO0 000 C18 8 O18 8 O1 166 OS Oe OODDOCOCOOCOQMHOCCCOC0O 0101010101010010 210100101001010 0101010101010 2101010101010000 ODOC 00 BHO OOOOCOCCOOC0CO OOO OBO OO OOOOOOOO0O0O0 OO QGRBOOCOCOCOOO0COCCO0C0OO OPO OOCOCOCDOOOOOCCOCO0O SUOG OOOO OO OOUOO OOO C OOOO 6 9 6 818 8 Oe 208 GC 2 ee 6 Oe CO Oe C819 269 So Oe AOOOOO OO OOOOOO COCO OOOOOOCOO OOO OO OCC OOO Not to Scale Substrate Assembly View Encapsulant Figure 16 Pinout of the MPC7400 360 CBGA Package as Viewed from the Top Surface MPC7400 RISC Microprocessor Hardware Specifications PRELIME Or Mor intormation On This Product CE Go to www freescale com Freescale Semiconductor Inc 1 6 Pinout Listings Table 13 provides the pinout listing for the MPC7400 360 CBGA package Table 13 Pinout Listing for the MPC7400 360 CBGA Package Pinout Listings I F Voltages Supported Signal Name Pin Number Active T O 1 8v 2 5v 3 3v Notes A 0 31 A13 D2 H11 C1 B13 F2 C13 E5 High Vo vV v vV D13 G7 F12 G3 G6 H2 E2 L3 G5 L4 G4 J4 H7 E1 G2 F3 J7 M3 H3 J2 J6 K3 K2 L2 AACK
50. r purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and amp are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Literature Distribution Centers USA EUROPE Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 Tel 1 800 441 2447 or 1 303 675 2140 World Wide Web Address http Idc nmd com JAPAN Nippon Motorola Ltd SPD Strategic Planning Office 4 32 1 Nishi Gotanda Shinagawa ku Tokyo 141 Japan Tel 81 3 5487 8488 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po New Territories Hong Kong Mfax RMFAX0 email sps mot com TOUCHTONE 1 602 244 6609 US amp Canada ONLY 800 774 1848 World Wide Web Address http sps motorola com mfax INTERNET http motorola com sps Technical Information Motorola Inc SPS Customer Support Center 1 800 521 6274 electronic mail address crc wmkmail sps mot com Docume
51. ristics for the MPC7400 Table 6 DC Electrical Specifications At recommended operating conditions See Table 3 Nominal Characteristic Bus Symbol Min Max Unit Notes Voltage Input high voltage all inputs except 1 8 Vin 0 65 L2 OVdd 0 3 V 2 3 SYSCLK L2 OVdd Input low voltage all inputs except 18 Vn 03s fosstovad jy Jo oo p f o sev E C vf 330 CV p03 3 Input leakage current Vip L2O0Vdd OVdd Hi Z off state leakage current Vin Irs 2 3 5 L2OVdd OVdd a fpo h Eo pr e fa e E e 10 MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PREL INEO N reS HAG Gor HON ThS BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Table 6 DC Electrical Specifications Continued At recommended operating conditions See Table 3 Nominal Characteristic Bus Symbol Min Max Unit Notes Voltage Output low voltage Io 6 mA Capacitance Vin 0 V f 1 MHz Notes 1 Nominal voltages See Table 3 for recommended operating conditions 2 For processor bus signals the reference is OVdd while L2OVd4d is the reference for the L2 bus signals 3 Excludes test signals LSSD_MODE L1_TSTCLK L2_TSTCLK and IEEE 1149 1 boundary scan JTAG signals AD MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 11 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc Electrical and Therma
52. rporation used by Motorola under license from International Business Machines Corporation Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the Suitability of its products for any particular purpose nor does Motorota assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buye
53. s MPC7400 RISC Microprocessor Hardware Specifications AX MOTOROLA PREL INEO N reS HAG Gor HON ThS BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc General Parameters 1 3 General Parameters The following list provides a summary of the general parameters of the MPC7400 Technology 0 20 um CMOS six layer metal Die size 7 86 mm x 10 58 mm 83 mm Transistor count 10 5 million Logic design Fully static Packages Surface mount 360 ceramic ball grid array CBGA Core power supply 1 8V 100 mV dc nominal see Table 3 for recommended operating conditions T O power supply 1 8V 100 mV dc or 2 5V 100 mV dc or 3 3V 5 input thresholds are configuration pin selectable 1 4 Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7400 1 4 1 DC Electrical Characteristics The tables in this section describe the MPC7400 DC electrical characteristics Table 1 provides the absolute maximum ratings Table 1 Absolute Maximum Ratings Characteristic Symbol Maximum Value Unit Note Core supply voltage Vdd 0 3 to 2 1 V 4 PLL supply voltage AVdd 0 3 to 2 1 V 4 L2 DLL supply voltage L2AVdd 0 3 to 2 1 V 4 Processor bus supply voltage OVdd 0 3 to 3 465 V 3 L2 bus supply voltage L20Vdd 0 3 to 3 465 V 3 Input voltage Processor bus V 0 3 to OVdd 0 3V V 2 5 L2 Bus Vi 0 3 to L2ZOVdd 0 3V
54. s O MOTOROLA PRELIM reS HAARO Fe HOWTO TICE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Table 12 JTAG AC Timing Specifications Independent of SYSCLKk Continued At recommended operating conditions See Table 3 Parameter Symbol Min Max Unit Notes Valid Times ns Boundary scan data ty py 4 20 4 TDO ttov 4 25 Output Hold Times Boundary scan data ty px TDO ty ox TCK to output high impedance ns Boundary scan data ty pz 3 19 4 5 TDO ty oz 3 9 i Notes 1 All outputs are measured from the midpoint voltage of the falling rising edge of TCLK to the midpoint of the signal in question The output timings are measured at the pins All output timings assume a purely resistive 50 ohm load See Figure 11 Time of flight delays must be added for trace lengths vias and connectors in the system 2 TRST is an asynchronous level sensitive signal The setup time is for test purposes only 3 Non JTAG signal input timing with respect to TCK 4 Non JTAG signal output timing with respect to TCK 5 Guaranteed by design and characterization Figure 11 provides the AC test load for TDO and the boundary scan outputs of the MPC7400 OUTPUT Zo 50Q AIAS OVdd 2 Ri 50Q Figure 11 Alternate AC Test Load for the JTAG Interface Figure 12 provides the JTAG clock input timing diagram TCLK VM Midpoint Voltage OVpp 2
55. sters SPRs See the MPC7400 RISC Microprocessor User s Manual for more information on the use of this feature Specifications for the thermal sensor portion of the TAU are found in Table 5 Table 5 Thermal Sensor Specifications At recommended operating conditions See Table 3 Characteristic Min Max Unit Notes Temperature range 0 127 C 1 Comparator settling time 20 us 2 A MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 9 PRELIME Gr Mor intormation On This product CE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Table 5 Thermal Sensor Specifications At recommended operating conditions See Table 3 Characteristic Min Max Unit Notes Resolution 4 C 3 Accuracy 12 12 C Notes 1 The temperature is the junction temperature of the die The thermal assist unit s raw output does not indicate an absolute temperature but it must be interpreted by software to derive the absolute junction temperature For information about the use and calibration of the TAU see Motorola application note Programming the Thermal Assist Unit in the MPC750 Microprocessor order AN1800 D 2 The comparator settling time value must be converted into the number of CPU clocks that need to be written into the THRM3 SPR 3 Guaranteed by design and characterization Table 6 provides the DC electrical characte
56. switches then the COP reset signals must be merged into these signals with logic The arrangement shown in Figure 21 allows the COP to independently assert HRESET or TRST while insuring that the target can drive HRESET as well The pull down resistor on TRST ensures that the JTAG scan chain is initialized during power on if a JTAG interface cable is not attached if it is it is responsible for driving TRST when needed MPC7400 HRESET as From Target HRESET Board Sources QACK T QACK ACK TRST SKa 2KQ COP Header _ Figure 21 Suggested TRST connection The COP header shown in Figure 21 adds many benefits breakpoints watchpoints register and memory examination modification and other standard debugger features are possible through this interface and can be as inexpensive as an unpopulated footprint for a header to be added when needed The COP interface has a standard header for connection to the target system based on the 0 025 square post 0 100 centered header assembly often called a Berg header The connector typically has pin 14 removed as a connector key as shown in Figure 22 TOP VIEW Pins 10 12 and 14 are no connects Pin 14 is not physically present KEY 16 No pin Ground CHKSTP_IN Figure 22 COP Connector Diagram 36 MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PREL INEO N reS HAG
57. t OVdd 2 SYSCLK jitter 150 150 ps 5 Internal PLL relock time 100 100 us 6 Notes 1 Caution The SYSCLK frequency and PLL_CFG 0 3 settings must be chosen such that the resulting SYSCLK bus frequency CPU core frequency and PLL VCO frequency do not exceed their respective maximum or minimum operating frequencies Refer to the PLL_CFG 0 3 signal description in Section 1 8 1 PLL Configuration for valid PLL_CFG 0 3 settings 2 Rise and fall times for the SYSCLK input measured from 0 4V to 2 4V when OVdd 3 3V nominal 3 Rise and fall times for the SYSCLK input measured from 0 4V to 1 4V when OVdd 1 8V nominal 4 Timing is guaranteed by design and characterization 5 This represents total input jitter short term and long term combined and is guaranteed by design 6 Relock timing is guaranteed by design and characterization PLL relock time is the maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the power on reset sequence This specification also applies when the PLL has been disabled and subsequently re enabled during sleep mode Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time during the power on reset sequence AD MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications PRELIME Gr Mor intormation On This product CE Go to www freescale com 13 Freescale Semiconductor Inc Electrical and
58. te a 25 decrease 1 4 2 AC Electrical Characteristics This section provides the AC electrical characteristics for the MPC7400 After fabrication functional parts are sorted by maximum processor core frequency as shown in Section 1 4 2 1 Clock AC Specifications and tested for conformance to the AC specifications for that frequency The processor core frequency is determined by the bus SYSCLK frequency and the settings of the PLL_CFG 0 3 signals Parts are sold by maximum processor core frequency see Section 1 10 Ordering Information 12 MPC7400 RISC Microprocessor Hardware Specifications O MOTOROLA PRELIM reS HAG Gor HON This BEGUN OTICE Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics 1 4 2 1 Clock AC Specifications Table 8 provides the clock AC timing specifications as defined in Figure 3 Table 8 Clock AC Timing Specifications At recommended operating conditions See Table 3 Maximum Processor Core Frequency Characteristic Symbol nit Notes 350 MHz 400 MHz Min Max Min Max Processor frequency foore 300 350 300 400 MHz 1 VCO frequency fyco 600 700 600 800 MHz 1 SYSCLK frequency fsyscLK 25 100 25 100 MHz 1 SYSCLK cycle time tsyscLK 10 40 7 5 40 ns SYSCLK rise and fall time tkr amp txp 1 0 1 0 fns 2 tKR amp txp 0 5 0 5 ns 3 SYSCLK duty cycle tkuKL tsyscLK 40 60 40 60 4 measured a
59. tion in nanoseconds of the parameter in question 6 Mode select signals are BVSEL EMODE L2VSEL PLL_CFG 0 3 7 Address Transfer Attribute signals are composed of the following A 0 31 AP 0 3 TT 0 4 TBST TSIZ 0 2 GBL WT CI 8 Data signals are composed of the following DH 0 31 DL 0 31 Data Parity signals are composed of DP 0 7 9 All other input signals are composed of the following AACK BG CKSTP_IN DBG DBWO DTI 0 DTI 1 2 HRESET INT MCP QACK SMI SRESET TA TBEN TEA TLBISYNC 10 All other output signals are composed of the following BR CKSTP_OUT DRDY HIT QREQ RSRV 11 According to the 60x bus protocol TS ABB and DBB are driven only by the currently active bus master They are asserted low then precharged high before returning to high Z as shown in Figure 6 The nominal precharge width for TS ABB or DBB is 0 5 tgyscyx i e less than the minimum tsysc x period to ensure that another master asserting TS ABB or DBB on the following clock will not contend with the precharge Output valid and output hold timing is tested for the signal asserted Output valid time is tested for precharge The high Z behavior is guaranteed by design 12 According to the 60x bus protocol ARTRY can be driven by multiple bus masters through the clock period immediately following AACK Bus contention is not an issue since any master asserting ARTRY will be driving it low Any master asserting it l
60. tion Signals Boundary scan testing is enabled through the JTAG interface signals BSDL descriptions of the MPC7400 are available on the internet at www mot com PowerPC teksupport The TRST signal is optional in the IEEE 1149 1 specification but is provided on all PowerPC implementations While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals more reliable power on reset performance will be obtained if the TRST signal is asserted during power on reset Since the JTAG interface is also used foraccessing the common on chip processor COP function of PowerPC processors simply tying TRST to HRESET isn t practical The common on chip processor COP function of PowerPC processors allows a remote computer system typically a PC with dedicated hardware and debugging software to access and control the internal operations of the processor The COP interface connects primarily through the JTAG port of the processor with some additional status monitoring signals The COP port requires the ability to independently assert AN MOTOROLA MPC7400 RISC Microprocessor Hardware Specifications 35 PRELIME Or Mor intormation On fnis Product CE Go to www freescale com Freescale Semiconductor Inc System Design Information HRESET or TRST in order to fully control the processor If the target system has independent reset sources such as voltage monitors watchdog timers power supply failures or push button
61. utes may not be driven by any master and may therefore float in the high impedance state for relatively long periods of time Since the MPC7400 must continually monitor these signals for snooping this float condition may cause excessive power draw by the input receivers on the MPC7400 or by other receivers in the system It is recommended that these signals be pulled up through weak 10 KQ pull up resistors by the system or that they may be otherwise driven by the system during inactive periods of the bus The snooped address and transfer attribute inputs are A 0 31 AP 0 3 TT 0 4 and GBL The data bus input receivers are normally turned off when no read operation is in progress and therefore do not require pull up resistors on the bus Other data bus receivers in the system however may require pullups or that those signals be otherwise driven by the system during inactive periods by the system The data bus signals are D 0 63 DP 0 7 If address or data parity is not used by the system and the respective parity checking is disabled through HIDO the input receivers for those pins are disabled and those pins do not require pull up resistors and should be left unconnected by the system If all parity generation is disabled through HIDO then all parity checking should also be disabled through HIDO and all parity pins may be left unconnected by the system The L2 interface does not normally require pull up resistors 1 8 8 JTAG Configura

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