EVBUM2091 - NBSG111 Evaluation Board User`s Manual
Contents
1. Channel 1 Voc 2 0 V Channel 2 Signal Generator Channel 3 Vcc CLKO Channel 4 Amplitude 500 mV CLKO Offset 660 mV Digital Oscilloscope Channel 5 Channel 6 TRIGGER Vee 1 3 V 3 3 V op Vee 0 5 V 2 5 V op NOTE All differential cable pairs must be matched Due to simplification of the block diagram CLK1 CLK1 and Q1 Q8 connections are not shown Channel 7 Channel 8 TRIGGER QO Q9 Ouputs Figure 2 NBSG111 Board Setup Time Domain Differential Mode hitp onsemi com 2 NBSG111BAEVB Setup continued Step 3 Setup Input Signals Step 4 Connect Output Signals 3a Set the signal generator amplitude to 500 mV 4a Connect the outputs of the device Q0 Q1 to the NOTE The signal generator amplitude can vary from 75 mV to Oscilloscope The oscilloscope sampling head must have 900 mV to produce a 400 mV DUT output internal 50 Q termination to ground 3b Set the signal generator offset to 660 mV the center of NOTE Where a single output is being used the unconnected output a nominal RSECL PECL output for the pair must be terminated to Vr through a 50 Q resistor for best operation Unused pairs may be left unconnected Since Vrr OV a standard 50 Q SMA termination is recommended NOTE The Vincmr Input High Voltage Common Mode Range allows the signal generat2. PARTS LIST NBSG111BA 2 5V 3 3V SiGe Differential 1 10 Clock Data ON Semiconductor http www onsemi com NBSG111 Driver with RSECL Outputs 32K243 40ME3 Gold plated connector http www rosenberger de CO6BLBB2X5UX 2 MHz 30 GHz capacitor Dielectric Laboratories http Awww dilabs com Table 6 BOARD MATERIAL e e 12 5 mil 7 1 37 mil Dielectric 5 0 mil Thick Copper Base Figure 7 Board Stack up PIN 1 Og Figure 8 Layout Mask for NBSG111 hitp onsemi com 7 NBSG111BAEVB EXAMPLE MEASUREMENTS IN TIME DOMAIN 10 0 y 9 0 8 0 f 7 0 6 0 RMS JITTER ps OUTPUT VOLTAGE AMPLITUDE mV INPUT FREQUENCY GHz Figure 9 Output Voltage Amplitude Voutpp RMS Jitter vs Input Frequency fin at Ambient Temperature Typical Figure 10 NBSG111 Eye Diagram at 6 Gbps with PRBS 2 31 1 Total Pk Pk system jitter including signal generator is 28 ps Device Pk Pk jitter is typically 14 ps hitp onsemi com 8 NBSG111BAEVB ADDITIONAL EVALUATION BOARD INFORMATION www onsemi com References In all cases the most up to date information can be found NBSG111 D Data Sheet NBSGI1I 2 5 V 3 3 V SiGe 1 10 on our website Differential Clock Data Driver with RSECL Outputs Sample orders for devices and boards AND8077 D Application Note GigaComm SiGe New Product updates SPICE Modeling Kit Literature download order AND8075 D Application Note Board Mountin
3. HIS AREA NOTE 5 000 6000 49X b NOTE3 Z 0 20 C ee EATE CAB NOTE 4 C 0000 0 08 C ile capa SEATING oo000 PLANE iz 000 Al 0 12 a Fe ee eg oe DETAILA ROTATED 90 C W VIEW Z Z GigaComm is a trademark of Semiconductor Components Industries LLC ON Semiconductor and are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to s
4. NBSG111BAEVB NBSG111 Evaluation Board User s Manual Description This document describes the NBSG111 evaluation board and the appropriate lab test setups It should be used in conjunction with the NBSG111 data sheet which contains full technical details on the device specifications and operation The evaluation board is designed to facilitate a quick evaluation of the NBSG111 GigaComm 1 10 clock data driver The NBSG111 allows selection between two inputs and fan out 10 identical differential outputs The Reduced Swing ECL RSECL output ensures minimal noise and fast switching edges The evaluation board is implemented in two layers for higher performance For standard lab setup and test a split dual power supply is required enabling the 50 Q impedance from the scope to be used as termination of the ECL signals Vrr Vcc 2 0 V in split power supply setup Vrr is the system ground y w w v d gt v v g w w ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL What measurements can you expect to make With this evaluation board the following measurements could be performed in single ended Note 1 or differential modes of operation e Jitter Output Skew Gain Return Loss Eye Pattern Generation Frequency Performance Output Rise and Fall Time Vincmr Input High Common Mode Range Single ended measurements can only be made at Voc Vee 3 3 V using this board set
5. g e IBIS and Spice models Considerations for the FCBGA Packages Table 7 ORDERING INFORMATION NBSG111BA 2 5 V 3 3 V SiGe Differential 1 10 Clock Data Driver with RSECL Outputs 100 Units Tray FCBGA 49 NBSG111BA 2 5 V 3 3 V SiGe Differential 1 10 Clock Data Driver with RSECL Outputs 4x4 mm 500 Units Reel FCBGA 49 NBSG111BAEVB NBSG111 Evaluation Board tFor information on tape and reel specifications including part orientation and tape sizes please refer to our Tape and Reel Packaging Specification Brochure BRD8011 D hitp onsemi com 9 NBSG111BAEVB PACKAGE DIMENSIONS FCBGA 49 BA SUFFIX PLASTIC 8x8 mm 1 0 mm pitch BGA FLIP CHIP PACKAGE CASE 489A 02 ISSUE A NOTES A lt A 1 CONTROLLING DIMENSION MILLIMETER D 2 DIMENSIONS AND TOLERANCES PER ASME B A2 Y14 5M 1994 TERMINAL A1 CORNER 3 DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO DATUM Z PLANE C 4 DATUM C SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS 5 PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE 6 489A 01 OBSOLETE NEW STANDARD 489A 02 MILLIMETERS DIM MIN MAX A 140 IN a 03 05 A2 0 91 REF y Z b 040 0 60 4x DETAIL A oo D 8 00 BSC D1 6 00 BSC QA 0 15 C E 8 00 BSC E1 6 00 BSC e 1 00 BSC FEDUCIAL FOR PIN A1 IDENTIFICATION IN T
6. hree power levels must be provided to the board for Vcc VEE and GND via the surface mount clips Using the split power supply mode GND Vrr Vcc 2 0 V Step 2 Input Setup 2a Calibrate VNA from 1 0 GHz to 12 GHz 2b Set input level to 35 dBm at the output of the 180 Table 4 POWER SUPPLY CONNECTIONS Hybrid coupler input of the DUT Step 3 Output Setup 3a Set display to measure S21 and record data Vt GND Vit GND NOTE For frequency domain measurements 2 5 V power supply is Step 2 Input Setup not recommended because additional equipment bias tee 2a Calibrate VNA from 1 0 GHz to 12 GHz etc is needed for proper operation The input signal has to be properly offset to meet Vincmp range of the device 2b Set input levels to 2 0 dBm 500 mV at the input of DUT Step 3 Output Setup 3a Set display to measure S21 and record data PORT 1 Vector Network Analyzer PORT 2 f Voc Float GND ND Voc 2 0 V eke cc Fs pales ViT 0 V 50 Q 50 Q Vcc SEL SEL GND CLKO ao 180 Hybrid ae _fi Coupler 50 Q min GND CLKO 50 Q NOTE All differential cable pairs VEE ETA must be matched EN EN GND Due to simplifcation of the 50Q block diagram CLK1 CLK1 mine alea and Q1 Q8 connections Vee 1 3V V r 0V GND lt i are not shown 3 3 V op Voc Float QO Q9 Outputs Figure 4 NBSG111 Board Se
7. or offset to vary as long as Vip is within the Viycmr range Refer to the device data sheet for further information 3c Set the generator output for a PRBS data signal or for a square wave clock signal with a 50 duty cycle Channel 1 Voc 2 0 V Channel 2 Signal Generator Channel 3 Voc AC_Coupling CLKo Channel 4 OUT mf a Digital Oscilloscope o m i Amplitude 500 mV CLKO Channel 5 Offset 660 mV 509 Vee Channel 6 TRIGGER Channel 7 Channel 8 TRIGGER NOTE All differential cable pairs must be matched Due to simplifcation of the block diagram CLK1 CLK1 and Q1 Q8 connections are not shown QO Q9 Outputs Figure 3 NBSG111 Board Setup Time Domain Single ended Mode hitp onsemi com 3 NBSG111BAEVB SETUP FOR FREQUENCY DOMAIN MEASUREMENTS Table 3 Basic Equipment Description Example Equipment Note 4 Quantity 1 Power Supply with 2 outputs HP 6624A Vector Network Analyzer VNA R amp S ZVK 10 MHz to 40 GHz Bias Tee with 50 Q Resistor Termination Picosecond Model 5542 219 Matched high speed cables with SMA connectors Storm Semflex Power Supply cables with clips Eee 180 Hybrid Coupler Krytar Model 4010180 4 Equipment used to generate example measurements Setup Setup Test Configurations for Differential Operation Step 1 Connect Power A Small Signal Setup la T
8. s Representative EVBUM2091 D
9. tup Frequency Domain Differential Mode hitp onsemi com 4 NBSG111BAEVB Setup Test Configurations for Single ended Operation A Single ended Mode Small Signal B Single ended Mode Large Signal Step 2 Input Setup Step 2 Input Setup 2a Calibrate VNA from 1 0 GHz to 12 GHz 2a Calibrate VNA from 1 0 GHz to 12 GHz 2b Set input level to 35 dBm at the input of DUT 2b Set input levels to 2 dBm 500 mV at the input of DUT Step 3 Output Setup Step 3 Output Setup 3a Set display to measure S21 and record data 3a Set display to measure 21 and record data Vector Network Analyzer PORT 1 PORT 2 Voc Float GND VogEEIN Vm 0V 509 VooL__SEE SEL np CLKO RO geniy 50Q GND o 50 Q GND Nb Qg GND 50 Q Vee 1 3 V 3 3 V op Vit 0V GND Voc Float NOTE All differential cable pairs must be matched Q0 Q9 Outputs Due to simplifcation of the block diagram CLK1 CLK1 and Q1 Q8 connections are not shown Figure 5 NBSG111 Board Setup Frequency Domain Single ended Mode http onsemi com 5 NBSG111BAEVB MORE INFORMATION ABOUT EVALUATION BOARD Design Considerations for gt 10 GHz operation While the NBSG111 is specified to operate at 12 GHz this evaluation board is designed to support operating frequencies up to 20 GHz The following considerations played a key role to ensure this evaluation board achieves high end micro
10. up e s Figure 1 NBSG111 Evaluation Board Semiconductor Components Industries LLC 2012 March 2012 Rev 1 Publication Order Number EVBUM2091 D NBSG111BAEVB SETUP FOR TIME DOMAIN MEASUREMENTS Table 1 BASIC EQUIPMENT Description Power Supply with 2 outputs Oscilloscope Differential Signal Generator Matched high speed cables with SMA connectors Example Equipment Note 2 Quantity HP6624A TDS8000 with 80E01 Sampling Head Note 3 Storm Semflex Power Supply cables with clips HP 8133A Advantest D3186 10 2 Equipment used to generate example measurements within this document 3 50 GHz sample module used for effective rise fall and jitter performance measurement Setup Step 1 Connect Power la Three power levels must be provided to the board for Vcc VEE and GND via the surface mount clips Using the split power supply mode GND Vrr Vcc 2 0 V Table 2 POWER SUPPLY CONNECTIONS 3 3 V Setup 2 5 V Setup Voc 2 0 V Vcc 2 0 V Vt GND Vrr GND Vee 1 3 V Vee 0 5 V Step 2 Connect Inputs For Differential Mode 3 3 V and 2 5 V operation 2a Connect the differential output of the generator to the differential input of the device CLKO and CLKO For Single Ended Mode 3 3 V operation only 2a Connect the AC coupled single ended output generator to input NOTE For best results unconnected input should be terminated to Vr through 50 Q resistor
11. upport or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 eens 3 Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sale
12. wave performance Optimal SMA connector launch Minimal insertion loss and signal dispersion Accurate Transmission line matching 50 ohms Surface Mount Clip VTEN Surface Mount Clip Surface Mount Clip VTCLKO 0 ROSENBERGER SMA si EL CLKO qo ROSENBERGER SMA TLKO VTCLKO _L9O l0 1 gen CLKI ROSENBERGER SMA 1 om 1 CLKT ROSENBERGER SMA 0 VTSEL _L9 Surface Mount Clip 1 SEL O T8 1 SEL Surface Mount Clip Oo 0 VTSEL NOTE C4 Co Decoupling Cap Tx 50 Q Transmision Line Distributed effects while bypassing and noise filtering Voc C 1 ROSENBERGER SMA 5 n 1 ROSENBERGER SMA 1 ROSENBERGER SMA Open Circuit Stub Eps ROSENBERGER SMA 2 a j 1 cr ROSENBERGER SMA H a C2 4 1 r ROSENBERGER SMA 1 po ROSENBERGER SMA 1po ROSENBERGER SMA 1T 7 ROSENBERGER SMA 13 ROSENBERGER SMA NBSG111 io ROSENBERGER SMA 1 ROSENBERGER SMA 1m ROSENBERGER SMA ae ROSENBERGER SMA ET ROSENBERGER SMA Cc 0 ea ROSENBERGER SMA 1 po 6 ROSENBERGER SMA o ircuit Stub Ipa 2 pen Circuit Stu lt 12 4 ROSENBERGER SMA 1 m T ROSENBERGER SMA 7S T2 ROSENBERGER SMA VEE 7 Surface Mount Clip QO Q9 Outputs Figure 6 Evaluation Board Schematic hitp onsemi com 6 NBSG111BAEVB Table 5
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