DE2 Development and Education Board User Manual
Contents
1. AO OA ONU NEON EE DETO TadasiC ID UDO OD UDO OD UDO DL http www dsp tdi com www terasic com Terasic Multimedia Touch Panel Daughter Board MTDB User Manual Preliminary Version 1 0 Copyright 2007 Terasic Technologies Inc Terasic Multimedia Touch Panel Daughter Board UN AAA nn A 1 1 1 PCR A e E A l 1 2 Gene LIC Di e o UE E re 2 Chapter 2 MTDB Hardware Specification rias 3 2 1 OU CC OO DE Sa een ee essen 3 22 Block Dao cai OC MIDE aa aa mn nasa 6 Chapter 3 gt MTDB Bus Controller ban inn as 9 3 1 MIDB Bus Controller Introducir 9 3 2 Block Design of the MTDB Bus Controller WoW mna 9 3 3 Timing Protocol of the LCD TDM Controller Woo 10 3 4 Bidirechonal levelshift MCT AC ane eat AE Rona Hanan ssi 11 Chapter GW simo the MED cuna cds 14 4 1 Configuring the Cyclone III Starter Board ooo aa 14 42 Using the 4 3 LCD Touch Panel Module ooooW Wana 15 4 3 SION CN uo EE ee 20 44 Using the 24 bit Audio CODEC c ocococcnnnnnnnnoonnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnos 23 4 5 RS 212 S PO a A mts 24 4 6 PS IO ee re 25 4 7 Ethernet Physical Layer ans Net ee dnss 26 4 8 DIS Ita IV Do de e om om nam mn ama A 27 4 9 DES EERROM ee 29 IB A na ab 29 Chapter 5 Examples of Advanced Demonstration ooooooooooooooooooooooooooooooooooo oo oo oooooo 31 5 1 SD Card IVS Player one mob na an een 31 32 Music Synthesizer Demonstration ee aa na2. reererrtrrey Nii iissteee et FREE ior ooe La cme PELIN GRE MEE rl fr Volume Down Volume Up Next Song Figure 5 2 Man Machine Interface of the SD Music Player Demonstration 32 MTDB User Manual Source Code E Overview All of the source codes in this demo program are included in the MPTD SYSTEM CD The demo project s developed under Quartus II 7 2 and Nios II EDS 7 2 The Quartus project s located at the folder MTDB_Demonstration MTDB_SD_Card_Audio and the NIOS II project s at MTDB_Demonstration MTDB_SD_Card_Audio software The demonstration program includes both hardware and software parts The hardware part s built by SOPC Builder and the software part s built by Nios II EDS m Hardware The hardware is built by SOPC builder The hardware block diagram is shown in Figure 5 3 In this SOPC a NIOS II processor s added to control the whole system The NIOS II C program is stored in the SSRAM of the Cyclone III starter board JTAG UART is added for debug and shows prompt messages for this demonstration A user defined SOPC component called AUDIO_DAC_MATER is provided for streaming audio signal data from NIOS II to the audio codec chip There is a 16x256 byte DAC FIFO in the controller to queue audio data for playing This component directly interfaces the audio chip and communicates the audio chip with the three pins BCLK DACDAT and DACLRCK Also it provides the input
3. R2IN T1OUT T20UT T1IN T2IN 1U ADM3202 VCC GND C1 C2 V V C29 C30 dei Figure 4 8 ADM3202 RS 232 schematic 24 MTDB User Manual ET HC_UART_RXD ns las UART_RXD U5 12 UART Receiver HC_UART_TXD na 616 UART IXD U5 11 2 UART Transmitter Notes 1 U5 12 connects to pin 3 on the RS 232 connector J6 via U5 13 2 US 11 connects to pin 2 on the RS 232 connector J6 via U5 14 Table 4 8 RS 232 pin assignments 4 6 PS 2 Serial Port The MTDB includes a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 4 9 shows the schematic of the PS 2 circuit Instructions for using a PS 2 mouse or keyboard can be found by performing an appropriate search on various educational web sites The pin assignments for the associated interface are shown in Table 4 9 VCC5 VCC5 O O R53 R54 2K 2K PS2 DAT R56 120 PS2DAT S PS2 CLK SA AE IS lt gt VCC5 O D3 D4 BAT54S BAT54S BC34 0 1U a O O VCC33 VCC33 Figure 4 9 PS 2 schematic HC PS2 CLK U10 3 1 U10 12 1 PS2 CLK e HC_PS2_DAT U10 4 1 U10 11 1 PS2 DAT Notes 1 These signals do not go through the MAX II chip They pass through the MAX3378 level translator chip U10 25 MTDB User Manual Table 4 9 PS 2 pin assignments 4 7 Ethernet Physical Layer Transceiver The MTDB board provides Ethernet support via the National Semicondu
4. 3 800x480 LCD Touch panel Module and Touch Screen Digitizer Equipped with Toppoly TDO43MTEA active matrix color TFT LCD module Uses the Analog Devices AD7843 touch screen digitizer Support 24 bit parallel RGB interface 3 wire register control for display and function selection Built in contrast brightness and gamma modulation SD card socket MTDB User Manual e Accessible as memory in both SPI and 1 bit SD modes Clock inputs e 100 MHz oscillator Audio CODEC e Wolfson WM8731 24 bit sigma delta audio CODEC e Line level input line level output and microphone input jacks e Sampling frequency 8 to 96 KHz e Applications for MP3 players and recorders PDAs smart phones voice recorders etc VGA output e Uses the ADV7123 240 MHz triple 10 bit high speed video DAC e With 15 pin high density D sub connector NTSC PAL TV decoder circuit e Uses the ADV7180 Multi format SDTV Video Decoder e Supports worldwide NTSC PAL SECAM color demodulation e One 10 bit ADC 4X over sampling for CVBS e Supports Composite Video CVBS RCA jack input e Supports digital output formats 8 bit ITU R BT 656 YCrCb 4 2 2 output HS VS and FIELD e Applications DVD recorders LCD TV Set top boxes Digital TV and Portable video devices Ethernet Physical Layer Transceiver e Uses the DP83848C Single Port 10 100 Mb s Ethernet Physical Layer Transceiver e Supports both 100Base T and 10Base T Ethernet protocols e Supports Auto M
5. 7 VGA green data bus bit 6 20 VGA blue data bus bit 6 46 VGA red data bus bit 7 VGA green data bus bit 7 21 VGA blue data bus bit 7 gt N VGA red data bus bit 8 VGA green data bus bit 8 22 VGA blue data bus bit 8 4 VGA red data bus bit 9 4 oO VGA green data bus bit 9 2 oo VGA blue data bus bit 9 11 VGA BLANK 12 VGA SYNC 24 VGA TDM Clock Table 4 6 ADV7123 pin assignments 22 MTDB User Manual 44 Using the 24 bit Audio CODEC The MTDB provides high quality 24 bit audio via the Wolfson VVM8731 audio CODEC ENCoder DECoder This chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz The VVM8731 is controlled by a serial I2C bus interface which is connected to pins on the HSMC connector A schematic diagram of the audio circuitry is shown in Figure 4 7 and the pin assignments are listed in Table 4 4 Detailed information for using the WM8 31 codec is available in its datasheet which can be found on the Datasheet folder of the MTDB System CD ROM or from the manufacturers web site Note that the direction of the signals HC AUD BLCR HC_AUD_DACLRCK and HC AUD ADCLRCR in the MAXII CPLD are from HSMC connector to the WM8731 codec Therefore the WM8731 codec only works in Slave mode If users need the WM8731 codec works in the Master mode users can modify the direction of the HC AUD BCLR in the MAXII CPLD RTL code which can be found in the MIDB_Bus_Con
6. FAT16 file system In this module only read function is implemented The WAVE module implements WAVE file decode function All access to Avalon bus is performed through the both fundamental system calls IOWR and IORD which are defined in lt io h gt When the program starts it configures the audio chip through I2C protocol The audio chip is configured as v Slave Mode v 48K Over Sampling v 16 bits Left Justified Format v Enable BYPASS mode Then 1t checks whether SDCARD is existed If yes 1t will build a play list by searching the root folder of the SD card and finding those wave files supported by this program If the play list is not empty 1t starts to play first wave file by reading audio signal data from SDCARD and sending the audio data to the audio chip Each time it reads 512 bytes audio data from SDCARD and sends the data to DAC FIFO if it is not full 34 MTDB User Manual In the interval of streaming 512 bytes audio data the main program polls the button status If users press BUTTON3 or BUTTON to adjust audio volume the main program will configure the audio chip volume through I2C protocol immediately If users press BUTTON4 to select next song it will close current wave file and open next wave file for new audio playing Software Architecture WAVE DC FAT16 SDCARD IOWR IORD Figure 5 4 Software Block diagram of the SD Music Player Demonstration 5 2 Music Synthesizer Demonstration This dem
7. m El El Zz le 82 oN a wo wo O c9 BC11 R30 49 9 E Pa SI GREEN 10U Ms E AGND f RJASINTLED gt all OE kes BC14 BC15 BC12 BC13 0 1U 0 1U lt TX EN R32 33 R37 E AGND E AGND E AGND 2 2K TXpo R33 33 TXD1 R34 33 O Txp2 R35 33 CC33 bg R36 33 Figure 4 10 Fast Ethernet schematic 26 MTDB User Manual 2 z N 00 oO e E O e 0 a gt 108 G7 RXD2 4 MII Receive Data bit 2 15 F4 RXD3 4 MII Receive Data bit 3 Notes 1 These signals do not go through the MAX II chip They pass through the MAX3378 level translator 219 90 Ol polal chip U10 Table 4 10 Fast Ethernet pin assignments 4 8 Digital TV Decoder The MTDB is equipped with an Analog Devices ADV7180 TV decoder chip The ADV7180 is an integrated video decoder that automatically detects and converts a standard analog baseband television signal NTSC PAL and SECAM into 4 2 2 component video data which s compatible with 8 bit CCIR601 CCIR656 The ADV7180 is compatible with a broad range of video devices including DVD players tape based sources broadcast sources and security surveillance cameras The registers in the TV decoder can be programmed by a serial I2C bus which is connected to the HSMC connector as indicated in Figure 4 11 The pin assignments are listed in Table 4 11 Detailed information on the ADV7180 is available on the Datasheet folder of the MTDB System CD RO
8. the highest resolution 800x480 to provide users the best display quality for developing applications The LCD panel supports 24 bit parallel RGB data interface and provides 3 wire serial port interface to control the display function registers The MTDB Board is also equipped with an Analog Devices AD7843 touch screen digitizer chip The AD7843 is a 12 bit analog to digital converter ADC for digitizing x and y coordinates of touch points applied to the touch screen Also the coordinates of the touch point can be read through the serial port interface on the AD7843 However because of the limited I Os of the HSMC connector the clock signal of the serial port interface for the LCD panel and AD7843 shares the same HSMC connector I O called HC_ADC_DCLK users must not control both LCD panel and AD7843 at the same time To display images on the LCD panel correctly the first thing users need to do s that the RGB color data and synchronization signals need to follow the timing specification of the LCD Touch panel as shown in Figure 4 2 Figure 4 3 Table 4 1 and Table 4 2 After that because of the number of user IOs of the HSMC connector are limited The LCD RGB data and synchronization signals outputted to the MTDB board need to be multiplex to fit the input timing specification of the LCD TDM Controller on the MTDB board as mention in the Section 3 3 Finally the associated schematic of the LCD touch panel module is given in Figure 4 4 and
9. the pin assignments are listed in Table 4 3 Detailed information for using the LCD panel and AD7843 are available in their datasheets which can be found on the Datasheet folder of the MTDB System CD ROM or form the manufacturers web site 15 MTDB User Manual Char gt i ja TT NCLR RO R7 G0 G7 B0 B7 t hbp Figure 4 2 LCD horizontal timing specification Panel Resolution 800xRGBx480 480xRGBx272 400xRGBx240 NCLK Frequency NCLK Frequency FNCLK Horizontal valid data 1 Horizontal Line 29 HSYNC Pulse VVidth Hsync back porch Hsync front porch DEN Enable Time ag Table 4 1 LCD horizontal timing parameters 16 MTDB User Manual RO R7 G0 G7 B0 B7 tva 1 Vertical Line tv ven Vertical valid data Vertical period VSYNC Pulse Width en Max Vertical back porch 5 Spa EEC Table 4 2 LCD vertical timing parameters 17 MTDB User Manual R O 7 VCC33 U6 O G 0 7 ADC_DCLK CGH O ETA SD CPL BI0 7 ADC CS n CPL2 Cc X RIGHT CS A al VCOW p ADC DIN 6 x LEET X DIN EI Si EE Y TOP ADC BUSY e DN g Y BOTTOM Y BUSY NCLK Y ADC_DOUT BO DOUT Bi ZA Ng B2 8 NA PENIRO a B3 R57 33 B gt VREF OVCC33 B5 U7 B6 AD7843 ca B7 E Go Gi G2 G3 G4 G5 GE G7 6 VCC330 Bea RO Bere R1 299 29 R2 30 30 C31 R3 TE VCC33 R4 Des esi R5 alas R5 10K HVDE R6 Pe aan Rs 10K SDA eel 5Vo_ VD TP _AGND R6 10K_ADC
10. 1 Configuring the Cyclone III Starter Board The procedure for downloading a circuit from a host computer to the Cyclone III Starter board is described in the Cyclone III Starter Kit User Manual This tutorial is found in the Cyclonelll Starter Kit folder of the MTDB System CD ROM and it is also available on the Altera Cyclone III Starter Kit web pages The user is encouraged to read the tutorial first and to treat the information below as a short reference Figure 4 1 illustrates how to connect your MTDB to a Cyclone III Starter board To download a configuration bit stream into the Cyclone III FPGA perform the following steps e Ensure that power is applied to the Cyclone III Starter board e Connect the supplied USB cable to the USB Blaster port on the Cyclone III Starter board e The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof filename extension e lt lt a Os AED on on 7 I qe dra ik Figure 4 1 Connection of a MTDB Board and a Cyclone III Starter Board 14 MTDB User Manual Users can find the default demonstration project under the Demonstrations default folder n the MTDB System CD ROM Users are also encouraged to examine the top level RTL code when reading the following sections 4 2 Using the 4 3 LCD Touch Panel Module The MTDB provides a 4 3 Toppoly TDO43MTEA 1 active matrix color TFT LCD panel The LCD Touch Panel module has
11. C Bir bus block provides bidirectional control for I2C Serial EEPROM data bus MTDB User Manual MAXI CPLD LCD Touch Panel amp AD converter LCDR data LCD Color Data Bus RGB LCD G data LCD TDM et la PEPE ie LCD Timing Control Bus LCD Timins Control Bus VGA R data GA Color Data Bus RGB VGA G data decos ontroller VGA Timing Control Bus VGA Timing Control Bus HSMC IC EEPROM Interface RC bir bus Connector Controller nn Other uni directional I Os Ethernet PHY Pe opal IOs Bi directional Level SD Card Soket Translator U10 U11 RS232 PS 2 Ports LCD Touch Panel Module VGA DAC RC EEPROM TV Decoder Figure 3 1 The Block Diagram of MTDB Bus Controller The RTL code of the MTDB Bus Controller can be found in the MTDB Bus Controller default folder of the MTDB System CD ROM 3 3 Timing Protocol of the LCD TDM Controller Figure 3 2 describes the input timing waveform information of the LCD TDM Controller The 8 bit wide HC LCD DATA signal is presumed to contain a stream of color pixel data with each pixel represented by three successive clock cycles of the stream The data is presented as BGR The LCD TDM Controller uses the HC HD pulse to determine the position of the BLUE color sample and thus the start of each three clock pixel period State transitions on HC HD 0 gt 1 or 1 gt 0 coincide with the presentation of BLUE color on the HC LCD DATA input The GREEN and RED values for
12. DIX for 10 100 Mb s Serial ports e One RS 232 port e One PS 2 port e DB 9 serial connector for the RS 232 port e PS 2 connector for connecting a PS2 mouse or keyboard to the MTDB board I2C serial EEPROM e Use one 128 bit EEPROM e Supports 2 wire serial interface I2C compatible 8 MTDB User Manual Chapter 3 MTDB Bus Controller The MTDB comes with a bus controller that allows a user to access all components on the board through the HSMC connector without being limited by the number of user IOs of the HSMC connector This chapter describes its structure in block diagram form and finally describes its capabilities 3 1 MTDB Bus Controller Introduction The two major functions of the MTDB Bus Controller are listed l Provide time division multiplexing functions to the LCD and VGA color data bus 2 Provide level shifting feature for the 2 5V Cyclone III FPGA and 3 3V the MTDB side domains 3 2 Block Design of the MTDB Bus Controller Figure 3 1 shows the block diagram of MTDB Bus Controller Both the LCD and VGA TDM blocks are simple 8 bit to 24 bit and 10 bit to 30 bit data de multiplexing functions respectively which are final logic driving the LCD panel and VGA DAC In the LCD TDM block the 8 bit input data successive BGR color data comes in at 3 times the rate of the 24 bit output data bus 8 bit B 8bit G 8bit R we drive to the LCD panel This function can reduce the pin count of the HS MC connector The I2
13. D_DATA 5 1146 B15 1 2 HC LCD DATA 6 1150 B14 3 2 HC LCD DATAI7 152 3 140 2 ol oO da 144 2 ao 1 SCEN LCD 3 Wire Serial Interface Enable 5 U11 5 1 U11 10 1 SDA J10 44 LCD 3 Wire Seriallnterface Data AD7843 LCD 3 Wire Serial ADC_DCLK U6 16 Interface Clock AD7843 Serial Interface ADC_DIN U6 14 Data In AD7843 Serial Interface CS U6 15 Chip Select Input AD7843 Serial Interface y U6 12 Data Out ADC PENIRQ _njU6 11 AD7843 pen Interrupt hi 157 B18 3 155 B16 N 143 D18 122 E13 HC ADC PENIRQ n 156 A14 3 120 au on M2 L I E I I I I H gt x gt gt E e i gt gt gt gt gt ep P O U U U U U U O Vv gt u m za 8 18 2 8 I D m lt sj A N U6 13 AD7843 Serial Interface Busy Notes 1 These signals do not go through the MAX II chip They pass through the MAX3378 level translator chip Ull Table 4 3 Pin assignments for the LCD Touch Panel Module 19 MTDB User Manual 4 3 Using VGA The MTDB includes a 16 pin D SUB connector for VGA output The VGA synchronization signals are provided directly from the Cyclone III FPGA and the Analog Devices ADV7123 triple 10 bit high speed video DAC is used to produce the analog data signals red green and blue The associated schematic is given in Figure 4 5 VGA AVCC VGA RJ0 9 O EK R68 4 7K Pec Si en Akaa ataata Ta Pa Ss are RSE
14. M 27 or from the manufacturers web site RCA JACK VCC33 O VCC18 AV VCC18 PV VCC18 J11 36 CVBS1 IN C49 0 1U RA TD RESET V AGND C50 0 1U C51 52 0 1Ul 0 1U ADV7180 28MHz I2C ADDRESS IS 0x40 VCC33 O 12 SCLK I2C SDAT s TD DO TD BI TD D2 TD D3 TD D4 TD DS TD D6 TD_D7 120 TD VS VS FIELD Tag 120 TD HS Figure 4 11 Digital TV Decoder schematic Eh TD 27MHZ 11 mz ro meser I 12 U10 13 1 ll2C DATA 33 11 um fecscu Im 33 10 2 1 34 84 SIUICISIGOGJADE IS aa gt I ss loa lR L oo MTDB User Manual EE TD D O 7 o gt gt 28 63636MHz Video Decoder Data 7 Video Decoder Data 6 Video Decoder Data 5 Video Decoder Data 4 Video Decoder Data 3 Video Decoder Data 2 Video Decoder Data 1 Video Decoder Data 0 I2C Clock Video Decoder Reset I2C Data Video Decoder Clock Input Video Decoder V SYNC Video Decoder H SYNC Notes 1 These signals do not go through the MAX II chip They pass through the MAX3378 level translator chip U10 Table 4 11 TV Decoder pin assignments 28 MTDB User Manual 4 9 IRC Serial EEPROM The MTDB uses a Microchip 128 bit IC serial EEPROM to store the MAC address and the boundary parameters of the touch panel for the Ethernet operation and touch panel respectively The EEPROM is programmed by I2C serial Interface which is connected through the CPLD to the HSMC connec
15. SD 1 bit Mode Command Line SPI Mode Data HC_SD_CMD 44 SD_CMD J4 2 In SD 1 bit Mode Data Line SPI Mode Data Out HC_SD_DAT SD_DAT Table 3 1 The timing diagram shows the output side of the LCD TDM Controller LCD 3 Wire Serial Interface Data Figure 3 4 The timing diagram shows the output side of the LCD TDM Controller TV HC RC SDAT DC SDAT Decoder gt gt Audio DAC HC PS2 CLK Level PS2 CLK l gt Translator gt U10 HC PS2 DAT oy ps2 DAT PS 2 Port HC_MDIO MDIO Ethernet lt gt PHY HSMC Connector HC SD DAT3 SD DAT3 adm gt gt HC SD CMD SD CMD SD Card Soket HC SD DAT eea Translator SD_DAT s U11 LCD HC SDA SDA Touch coea gt gt Panel Module LA VCC25 U10 VCC33 Lo VCCA da HC I2C SDAT HC PS2 DAT HC MDIO VCO R43 2 2K LF EN EN VCC25 HC_SD_DAT3 HC_SD_CMD HC_SD_DAT HC SDA gt SC LF EN BEN I2C SDAT PS2 DAT Figure 3 5 Bidirectional level shift interface schematic 13 MTDB User Manual MTDB User Manual Chapter 4 Using the MTDB This chapter gives instructions for using MTDB and describes each of its I O devices The MTDB s designed for an Altera FPGA board with a HSMC connector The demonstration projects illustrated here are using MTDB with the latest Cyclone III Starter Board 4
16. T R69 560 SISISISISISISISISIS BC43 BC44 j 0 1U 0 1U VGA GO VGA G1 VGA G2 P VGA R VGA G3 4 8 VGA G VGA G4 lao 1 PCE VGAB VGA G5 A 7 VGA G6 ADV7123 VGA_G7 8 9 A R70 R71 R72 VGA G8 9 8 VGA G9 i 75 75 75 rig VGA BLANK G9 a L PGA SYNC LA 0 SR LES AR VGA AGND VGA AGND VGA AGND VGA HS R73 47 VGA VS R74 17 Pr x O ol latolzliotleolxololO y fan faa fajajajajaja laa VGA_AGND Pa bas Dag Dag pad bas bat bag pd ba Pra olololololejolcicicks gt gt gt gt gt gt gt gt gt gt O VGA_AVCC Figure 4 5 VGA circuit schematic The timing specification for VGA synchronization and RGB red green blue data can be found on various educational web sites for example search for VGA signal timing Figure 4 6 illustrates the basic timing requirements for each row horizontal that is displayed on a VGA monitor An active low pulse of specific duration time a in the figure s applied to the horizontal synchronization Async input of the monitor which signifies the end of one row of data and the start of the next The data RGB inputs on the monitor must be off driven to O V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there s a time period called the front porch d where the RGB signals must a
17. _PENIRQ_n VA syo VDDN 8130 VCC3320 HVDE a x R6 10K ADC CS n 40 os oa R62 A 10K_SCEN HEE N ap ADC DCLR 43 oe DA re VDDN lt gt Tyas 44 C42 10N E FB UTA X RIGHT 37 vecsso VMP C43 10N VMN Y_TOP C38 011 VMP aE C44 10N CGL X_LEFT C39 Y_TOP VMN X LEFT C45 10N a Y BOTTOM X RIGHT een VDDN 4 CGL D5 PMEG2010ABE LED B 0 LED B O res FPC 60B CONNECTOI Figure 4 4 Schematic diagram of the LCD Touch Panel Module e LCD RGB Data Enable G 0 LCD green data bus bit 0 HC_LCD_DATA O 145 D17 o o LCD blue data bus bit O LCD red data bus bit 1 LCD green data bus bit 1 LCD blue data bus bit 1 18 HC LCD DATAH 1149 C17 MTDB User Manual AS 2 ao oO LCD red data bus bit 2 HC_LCD_DATA 2 1151 Icie Tl 4 LCD green data bus bit 2 LCD blue data bus bit 2 LCD red data bus bit 3 LCD green data bus bit 3 LCD blue data bus bit 3 LCD red data bus bit 4 LCD green data bus bit 4 LCD blue data bus bit 4 LCD red data bus bit 5 LCD green data bus bit 5 B 5 LCD blue data bus bit 5 LCD red data bus bit 6 G 6 LCD green data bus bit 6 LCD blue data bus bit 6 R 7 LCD red data bus bit 7 G 7 LCD green data bus bit 7 GREST LCD Global Reset Low Active 2 4 HC_LCD_DATA S 1126 D13 gt gt gt aolaa ao a a ao a2 2 5 5 a al 2 2 8 3 Nip cal 8 8 ep C lt 4 2 3 3 HC_LCD_DATA 4 1128 D15 2 1 3 HC_LC
18. a ba Besa 35 5 3 ECD EE Don nio A ae Un ae Son nana at Usa nenas aa 39 Chapter Ape el nana 42 6 1 PR GY 1S CON ENS COTY now on nm oa E ne on ana 42 MTDB User Manual Chapter 1 Ihe Package The Multimedia Touch Panel Daughter board MTDB package contains all components needed for MTDB in conjunction with an Altera FPGA board with HSMC connector 1 1 Package Contents The MTDB package includes e The Terasic Multimedia Touch Panel daughter board e MTDB System CD ROM e Optional Components to assemble the MTDB with a Cyclone III Starter Board into a BRICK format as shown in Figure 1 1 The detailed instructions on how to assemble MTDB with a Cyclone III Starter board into a BRICK format can be found in the Cyclonelll_Starter_Board BRICK folder on the MTDB System CD ROM Figure 1 1 The BRICK form of combining the MTDB to an Altera Cyclone III Starter Board 1 2 Getting Help Here are the addresses where you can get help f you encounter problems e Altera Corporation 101 Innovation Drive San Jose California 95134 USA Email mysupport altera com e Terasic Technologies No 356 Sec 1 Fusing E Rd Jhubei City HsinChu County Taiwan 302 Email support terasic com Web www terasic com Apa EXTEEH ro Y LI By ES E mail sour T 198 0063 RRA Ateh 35 955 TEL 0428 77 7000 FAX 0428 77 7010 URL http www dsp tdi com MTDB User Manual MTDB User Manual Chapter 2 MTDB Hardware Specification Th
19. able 4 13 SD card interface pin assignments 30 MTDB User Manual Chapter 5 Examples of Advanced Demonstration This chapter provides a few examples of advanced circuits implemented using MTDB and a Cyclone III Starter board These circuits provide demonstrations of the major features on the board such as its audio and video capabilities and SD card connectivity For each demonstration the Cyclone III FPGA configuration file is provided as well as the full source code in Verilog HDL code All of the associated files can be found in the MTDB_demonstrations folder from the MTDB System CD ROM For each demonstration described in the following sections we give the name of the project directory for its files which are subdirectories of the MTDB_demonstrations folder 5 1 SD Card Music Player Introduction Many commercial media audio players use a large external storage device such as an SD card or CF card to store music or video files Such players may also include high quality DAC devices to produce good audio quality The Cyclone III Starter board and MTDB board provide the hardware and software needed for SD card access and professional audio performance so that 1t is possible to design advanced multimedia products using the Cyclone Ill Starter board and MTDB board Demonstration Operation Refer to Figure 5 1 and 5 2 follow the procedure below to operate the demonstration l Make sure Quartus II 7 2 and Nios2 II EDS 7 2 are in
20. crystal for the audio chip In this demonstration the audio chip 1s configured as slave mode so external circuitry must provide the ADC DAC serial bit clock BCK and left right channel clock LRCK to the audio CODEC The sample rate is configured as 48K over sampling so a clock 18 432MHz 48K x 384 must be provided to the XTI MCLK pin of the audio chip The BYPASS mode of the audio chip s enabled so line out will mix the data from microphone in and line in for the Karaoke style effects Two PIO pins are used to implement I2C protocol for configuring the audio codec chip For SDCARD Four PIO pins are used to implement I bit mode SD MODE protocol for reading data from SD CARD Buttons and LEDs on the Cyclone III starter board are also controlled by the PIO controller 33 MTDB User Manual MTDB Board SD CARD Socket 7 PIO I2C a a MAC In Controller IN Audio DAC E oi Controller gt Line Out 9118 J YIJIMS UOJLAY Memory Controller LED Button Figure 5 3 Hardware Block diagram of the SD card Music Player Demonstration MH Software The software is implemented by C and the software architecture is shown in Figure 5 4 In the block diagram the Audio DAC module provides functions to check whether DAC FIFO is full and be in charge of sending audio data to the DAC FIFO The I2C module implements the I2C protocol The SDCARD module implements the 1 bits SD MODE protocol The FAT16 module implements
21. ctor DP83848C Ethernet Physical Layer Transceiver chip The DP83848C is a one port Fast Ethernet PHY Transceiver supporting IEEE 802 3 physical layer applications at 10Mbps and 100Mbps The DP83848C provides Media Independent Interface MII to connect DP83848C to a MAC in 10 100Mbps systems Figure 4 10 shows the schematic for the Ethernet Physical Layer Transceiver interface and the associated pin assignments are listed in Table 4 10 For detailed information on how to use the DP83848C please refer to its datasheet and application note which are available on the Datasheet folder of the MTDB System CD ROM or from the manufacturers web site VCC33 O R11 VCC33 O 1 5K MDIO BC5 a EN vec H pee GND OUT ETH_RESET_N 25MHZ VCC33 _ ia ACT R12 120 ACTIVITY ACTIVITY c6 BC6 SPE R13 120 SPEE 100Mbps TXDIO 3 CEDA DUPLEX Le 10u 0 1U DUPLEX R14 KO MR ovccag DUPLEX RXDIO 3 HAB L E AVCC33 A A 9 PFBOUT d d y q oj d N o PFBOUT u2 BC7 c7 BC8 c8 BC9 lt lt BX_CLK RIS 93 0 1U 10U 0 1U 10U 0 1U A aa E AGND y R24 4 7K RX cRS R17 33 o PFBIN2 RBIAS lt _ TA RX_CLK PFBOUT a Bene E ARNO a ul ner st aaa an E 6 A 0 el RX COL R19 83 5 DIX_EN gt 7 DP83848C H soo jou DE AGND ES ACTIVITY RXDO 0 33 Ad a TD RXD1 R21 33 TD mara ERE 1D 7 6 RXD 3 PHYAD4 AGND aa E AA YELLOW D4 R22 33 LI OGND RXD2 VCC33 Be IOVDD33 D2 PE SPEED a OVCC33 RXD3 R23 33 TXD_3 SNI_MODE PWR_DOWN INT 0
22. er values of the TV Decoder chip will be configured via the 2C_AV_Config block which uses the I2C protocol to communicate with the TV Decoder chip on the MTDB board Upon the power on sequence the TV Decoder chip will be unstable for a time period the Lock Detector is responsible for detecting this instability The TU R 656 Decoder block extracts YCrCb 4 2 2 YUV 4 2 2 video signals out of the TU R 656 data stream which s sent by the TV Decoder It also generates a data valid control signal indicating the valid period of data output Because the video signal from the TV Decoder is interlaced we need to perform de interlacing on the data source We used Frame Buffer and a field selection multiplexerMUX which s controlled by the LCD controller to perform the de interlacing operation Internally the LCD Controller generates data request and odd even selected signals to the Frame Buffer and filed selection multiplexer MUX The YUV422 to YUV444 block converts the selected YCrCb 4 2 2 YUV 4 2 2 video data to the YCrCb 4 4 4 YUV 4 4 4 video data format The YCrCb_to_RGB block converts the YCrCb data into RGB output The LCD Timing Controller block generates standard LCD sync signals LCD HD and LCD VD to the LCD TDM block The LCD TDM Controller block will take these sync signals and RGB data as input and multiplex these signals to the MAXII CPLD device on the MTDB board via the HSMC connector Finally the LCD TDM Controller block in t
23. gain be off before the next hsync pulse coming up The timing of the vertical synchronization vsync is same as shown in Figure 4 6 except that a vsync pulse signifies the end of one frame and the start of the next The data refers to a set of rows in the frame horizontal timing Table 4 4 and Table 4 5 show for different resolutions the durations of time periods a b c and d for both horizontal and vertical timing Note that because of the number of user IOs of the HSMC connector are limited users need to multiplex the VGA synchronization signals and RGB data to fit the input timing specification of the VGA TDM block as mention in Section 3 3 20 MTDB User Manual Detailed information for using the ADV 7123 video DAC is available in its datasheet which can be found on the manufacturer s web site and from the Datasheet folder of the MTDB System CD ROM The pin assignments are listed in Table 4 6 An example of code that drives a VGA display s described in Sections 5 2 and 5 3 Back porch b Front porch d Display interval c DATA HSYNC m Sync a Figure 4 6 VGA horizontal timing specification Sowom mono Lo 19 mens won ren mm er Ta Tos T m mn caro Poma Der es vse 06 o cote Doos sa Par far os e vna Sona meer Dia 2 108 os on coo anna ima 19 a ma Fa va vano Table 4 4 VGA horizontal timing specification EEC onen om 1 Soma omen gt om 1 MEE
24. he MAXI CPLD device will de multiplex the LCD RGB data and the sync signals before sending them to the LCD Touch panel module for display Figure 5 8 illustrates the setup for this demonstration 39 MTDB User Manual Cyclone III Starter Board MTDB Board DLYO To Control the m mikason en TD_HS MAXII TD_HS tinti cti dl CPLD Initiation an Detector TD VS 4 TD VS Sequence ea TV Decoder Frame ITU R 656 lt TD DATA TD_DATA 7180 Buff er Data Valid Decoder RC SCLR RC SCLK RC AV za RC SDAT RC SDAT Config dd gt to e Timing EGB gt ton Lop Lop RGB Controller VGA_HS E ur LCD HD TDM LCD HD Touch ttf ontroller VP Controll MP l VGA_VS LCD_VD LCD_VD ent p is Figure 5 7 Block diagram of LCD TV design Demonstration Setup File Locations and Instructions e Project directory MTDB LCD TV e Bit stream used MTDB LCD TV sof or MTDB LCD TVpof e Connect a DVD player s composite video output yellow plug to the Video IN RCA jack J11 of the MTDB board The DVD player has to be configured to provide o NTSC output o 60 Hz refresh rate o 4 3 aspect ratio e Connect the audio output of the DVD player to the line in port of the MTDB board and connect a speaker to the line out port If the audio output jacks fro
25. is chapter presents the features and design characteristics of the MTDB hardware 2 1 Layout and Components A photograph of the MTDB is shown in Figure 2 1 Figure 2 2 Figure 2 3 and Figure 2 5 These pictures depict the layout of the board and indicate the location of the connectors and key components A IA m Tn gr eS i r E i MN Figure 2 1 The MTDB Top View MTDB User Manual al Figure 2 2 The MTDB Connector view 1 Figure 2 3 The MTDB Connector view 2 MTDB User Manual Micin Linein Line Out Video in VGA Video Port RS 232 Port P SEK GI VGA 10 bit DAC VIDEO IN regi a pit u A rel Lg Cr mE As mn E L El e PS2 lt gt PS 2 Keyboard 24 bit Audio Codec ua len ik i m ees re 2 3 Br Mouse Port TV Decoder J ET Fiss Lee El BE a NTSC PAL joc gt Ethernet 10 100M Port El E 3 Ak ik Altera MAX II 2210 CPLD device lt SD Card Slot MOSS 5 CARD Si ug i A Jet A Ba a la iit ge terosic com 1 ql Hi TO lA ali 500001 Pod SOS rn de H EE a El E o 85 1 Ethernet 10 100m PHY 50 MHz Oscillator Touch Panel Connector EEPROM Figure 2 4 The MTDB PCB and Component diagram HSMC Connector p res Bl Fa Le _ 133 4083 PE 2 suv 0 0724 Figure 2 5 The MTDB Back side HSMC connector view MTDB User Manual The MTDB board has many features that allow users to implemen
26. izer pof e Connect a PS 2 Keyboard to the MTDB board e Connect the VGA output of the MTDB board to a VGA monitor e Connect the Line out of the MTDB board to a speaker e Load the bit stream into FPGA on the Cyclone III Starter board e Press BUTTON 1 on the Cyclone III Starter board to reset the circuit e Press BUTTON 2 on the Cyclone III Starter board to start the music demo Table 5 1 and 5 2 illustrate the usage of the switches pushbuttons BUTTONS and PS 2 Keyboard e Switches and Pushbuttons Press BUTTON 2 Demo Music Mode BUTTON 2 Release BUTTON 2 PS2 Keyboard Mode BUTTON 4 Reset Keyboard Table 5 1 Usage of the switches and pushbuttons BUTTONS e PS 2 Keyboard 36 MTDB User Manual Table 5 2 Usage of the PS 2 Keyboard s keys 37 MTDB User Manual VGA Out Figure 5 6 The Setup of the Music Synthesizer Demonstration 38 MTDB User Manual 5 3 LCD TV Demonstration This demonstration plays video and audio input from a DVD player using the LCD Touch panel module audio CODEC and one TV decoder on the MTDB board Figure 5 7 shows the block diagram of the design There are two major blocks in the circuit called 2C AV Config and TV to VGA The TV to VGA block consists of ITU R 656 Decoder SDRAM Frame Buffer YUV422 to YUV444 YCrCb to RGB and VGA Controller As soon as the bit stream is downloaded into the FPGA on the Cyclone III starter board the regist
27. m the DVD player are of RCA type then an adaptor will be needed to convert to the mini stereo plug supported on the MTDB board this 1s the same type of plug supported on most computers e Load the bit stream into FPGA on the Cyclone III Starter board e Press BUTTONI on the MTDB board to reset the circuit 40 MTDB User Manual lt a Line Out Line In CVBS S Video Audio Output YPbPr Output Video In dica rings F Bimer mai ivy SET XD ar F A F PHS 38 ies a ee CEA ha den g mE mi ti l Ed 3 mi Ti nn ei Be eal rm ME CEE a l Y Lp ntar TT FR a ab El a a en q do A Figure 5 8 The setup for the LCD TV demonstration 41 MTDB User Manual Chapter 6 Appendix 6 1 Revision History Version Date Change Log 2007 11 28 Initial Version Preliminary 42
28. mon a a wm ann ame em ES aan ame em eo Table 4 5 WGA vertical timing specification Zi U7 OD al HC VGA DATA O0 N16 lt 4 I 7 lt 7 HC VGA DATA 1 O SQ M16 4 7 HC VGA DATA 2 N M18 3 6 HC_VGA_DATA 3 M17 2 5 6 VGA_R4 HC_VGA_DATA 4 L17 VGA G4 4 VGA_B4 6 VGA_R5 HC VGA DATAJ5I L18 VGA G5 5 VGA B5 5 VGA R6 HC VGA DATAISI 00 oo L16 VGA_G6 5 VGA B6 5 VGA R7 HC VGA DATAI7I 00 O1 A N N N W Mi K16 P10 VGA_G7 4 VGA_B7 5 VGA_R8 HC VGA DATA 8 152 K18 R10 VGA G8 6 VGA B8 4 VGA R9 HC VGA DATA 9 J18 11 VGA G9 6 VGA B9 HC VGA BLANR 59 HC VGA SYNC 6 7 97 4 z z Ola nN HC_VGA_CLOCK lt lt lt lt lt lt lt lt lt lt lt lt OIOI OIOI OIOI OIOI OI OJOJ O a E m a a ia gt W s alalslels s e 8 g 2 VGA_BLANK VGA_SYNC VGA_CLOC MTDB User Manual 39 von red data bus bit O VGA green data bus bit O 14 40 VGA red data bus bit 1 2 VGA green data bus bit 1 15 a VGA red data bus bit 2 8 VGA green data bus bit 2 16 vor blue data bus bit 2 a2 VGA red data bus bit 3 a VGA green data bus bit 3 17 von blue data bus bit 3 43 VGA red data bus bit 4 5 VGA green data bus bit 4 e foroen enanss 45 VGA red data bus bit 6 lt lt Q Q gt gt o e Cc Cc D D o o je eb p je je o o Cc Cc nm Mm D D F O
29. onstration shows how to implement a Multi tone Electronic Keyboard using Cyclone HI Starter board and MTDB board with a PS 2 Keyboard and a speaker PS 2 Keyboard 1s used as a piano keyboard for input The FPGA on the Cyclone III Starter board serves as a Music Synthesizer to generate music and tones The VGA connected to the MTDB board 1s used to display which key 1s pressed during the playing of the music Figure 5 5 shows the block diagram of the design of the Music Synthesizer There are four major blocks in the circuit DEMO_SOUND PS2 KEYBOARD STAFF and TONE_GENERATOR The DEMO_SOUND block stores a demo sound for user to play PS2 KEYBOARD handles the users input from PS 2 keyboard The STAFF block draws the corresponding keyboard diagram on VGA monitor when key s on the PS 2 Keyboard are pressed The TONE_GENERATOR is the core of music synthesizer User can switch the music source either from PS2_KEYBOAD or the DEMO_SOUND block using BUTTON2 Figure 5 6 illustrates the setup for this demonstration 25 MTDB User Manual Cyclone III Starter Board amp FPGA MTDB Board VGA_HS DEMO1_CODE gt VGA_VS VGA CLOCR VGA R DEMO1_CODE VGA_G SEAL VGA B REY1 CODE SOUND1 KEY1_ CODE BUTTON2 Figure 5 5 Block diagram of the Music Synthesizer design Demonstration Setup File Locations and Instructions e Project directory MTDB_Synthesizer e Bit stream used MTDB_Synthesizer sof or MTDB_Synthes
30. stalled Connect Line Out to a speaker or earphone Connect Cyclone HI Starter board and host computer with an USB cable Power on the Cyclone III Starter board Execute the demo batch file sdcard_audio bat 1 Insert a SD card which has wave files located in the root folder 2 Use BUTTON4 to select desired wave file and BUTTON3 BUTTON2 to adjust audio volume 3 1 The batch file is located in the folder MTDB SD Card AudiolDemo Batch 2 The SDCARD should be formatted as FAT16 and the wave file WAV must be stereo 16 bits 48K sample rate and with short file name 3 LED2 will be flashing when the SD card is not inserted in SD card socket LEDI will be flashing while the demonstration is playing music oe Se ON 31 MTDB User Manual o with music files wav Figure 5 1 Setup of the SD Card Music Player Demonstration Altera Cyclone Ii Starter Board sel Ut 8 las 1 Ne wi d 0 0 3 Wa Saat a i be JG 3 sii P a 1 gem We aad It a0 ala 2 7 155 bracar fona eure afe og e ee lien ZNO RA eo ee Ci dA i i Be er ut w em i S wwwW citera com E 3 ar ter FRITZ he intel ahii PLE Ut erosic com at ii m 7 N CI i AMAN 48 40 un EE EL MM an mann Pol ny coon a Ma Pi u Br Ma un cate AUT Va ua TA y ep Ta Insert SDCARD E u gelben 44 TIER Indicator E pee ya LOGT I tereererey x Play Indicator
31. t a wide range of designed circuits from simple circuits to various multimedia projects with touch panel applications The following hardware is provided on the MTDB board Altera MAX II 2210 CPLD device SD Card socket 100 MHz oscillator for clock sources 24 bit CD quality audio CODEC with line in line out and microphone in jacks VGA DAC 10 bit high speed triple DACs with VGA out connector TV Decoder NTSC PAL SECAM and TV n connector 10 100 Ethernet Physical Layer Transceiver RS 232 transceiver and 9 pin connector PS 2 mouse keyboard connector 800x480 Active matrix color TFT LCD Touch Panel module DC Serial EEPROM To use the MTDB the user has to be familiar with the Quartus II software 2 2 Block Diagram of the MTDB Figure 2 6 gives the block diagram of the MTDB To provide maximum flexibility for the user all connections are made through the HSMC connector device Thus the user can configure the FPGA on the mother board to implement any system design MTDB User Manual MAXII CPLD amp Level Shift 24 bit AUDIO CODEC VGA 10 bit Video DAC TV decoder PS2 amp RS232 Ports HSMC BUS Connector Controller LCD Touch Panel module 10 100 Ethernet PHY SD Card IC EEPROM 100M Hz OSC Figure 2 6 Block diagram of the MTDB board Following is more detailed information about the blocks in Figure 2 6 MAX II 2210 CPLD 2210 LEs 272 user YO pins FineLine BGA 324 pin package 4
32. that same pixel are presented on the next two clock cycles Figure 3 3 shows the timing information from the output side The LCD TDM block will generate a NCLK clock and 24 bit RGB data to the LCD panel The NCLK signal runs at 1 3 freguency of the incoming clock HC NCLR In addition the timing protocol of the VGA TDM controller is very similar to the LCD TDM controller The input color data bus HC VGA DATA changes from 8 bit to 10 bit and the 10 MTDB User Manual VGA TDM controller uses the HC_VGA_HS to determine the position of the BLUE color sample HC_NCLK HC LCD DATA HC HD Figure 3 2 The timing diagram shows the input side of the VGA TDM Controller HC NCLK LCD R G B Color data HD VD DEN Syot Siennie HD VD DEN HD VD DEN NCLK ES N Figure 3 3 The timing diagram shows the output side of the LCD TDM Controller 3 4 Bidirectional level shift interface The board provides bidirectional level shift feature for the 2 5V input Cyclone III FPGA and 3 3V required by many of the interface chips via two Maxim MAX3378 level translators Table 3 1 lists bidirectional level shift interface reference and manufacturing information Figure 3 4 shows the block diagram and pinout of the bidirectional level shift interface on the board respectively Figure 3 5 shows the Level Shift Interface schematic 11 MTDB User Manual SD 1 bit Mode Card Detect SPI Mode Chip SD_DAT3 Select Active Low
33. tor Figure 4 12 shows the schematic of the I2C Serial EEPROM and the associated pin assignments are listed in Table 4 12 Detailed information for using the I2C EEPROM is available in its datasheet which can be found on the Datasheet folder of the MTDB System CD ROM or from the manufacturers web site 24LC00 Figure 4 12 I2C Serial EEPROM schematic HC ID I2CSCL om 7 HC ID I2CDAT P18 Table 4 12 I2C Serial EEPROM pin assignments N3 ID I2CSCL 6 EEPROM I2C Clock P3 ID_I2CDAT EEPROM I2C Data 4 10 SD Card Interface The MTDB includes a SD card socket and provides both SPI and SD 1 bit mode for SD Card access Instructions for using SD card can be found by performing an appropriate search on various educational web sites Figure 4 13 show the schematic of the SD card interface and the associated pin assignments are listed in Table 4 13 29 MTDB User Manual VCC33 VCC33 VCC33 O O O R38 R39 4 7K 4 7K SD_DAT3 SD_CLK 5 SD DAT oo VU 0 Figure 4 13 SD card interface schematic SD 1 bit Mode Card Detect HC SD DAT3 53 U11 2 1 U11 13 1 ISD DAT3 SPI Mode Chip Select Active Low SD 1 bit Mode Command Line HC SD CMD 44 U11 3 1 U11 12 1 ISD CMD SPI Mode Data In i 4 2 SD 1 bit Mode Data Line SPI HC_SD_DAT U11 4 1 U11 11 1 JSD_DAT 7 Mode Data Out Notes 1 These signals do not go through the MAX II chip They pass through the MAX3378 level translator chip U11 T
34. troller default folder on the MTDB System CD ROM VCC33 VCC33 O O R6 330 2K 2K Vo N AGND AGND I2C SDAT J1 MIC IN 2 20 SCLK J 5 U1 PHONE JACK P R7 680 0 Cal 10U NZ pia O c5 R8 AGND Q OA_VCC33 O A VCC33 sf yY AGND AGND Figure 4 7 Audio CODEC schematic 23 HC_AUD_BCLK HO AUD DACAT Enz HC_AUD_DACLRCK 107 H18 HC_AUD_ADCDAT 40 R15 HC_AUD_ADCLRCK 103 H16 HC I2C SCLK P15 Notes 1 translator chip U10 AUD_DACDAT EN Audio CODEC DAC Data MTDB User Manual Audio CODEC Bit Stream Clock AUD_BCLK AUD_XCK Audio CODEC Chip Clock Audio CODEC DAC LR Clock AUD_DACLRCK AUD ADCDAT AUD pr y I2C SCLK Audio CODEC ADC Data Audio CODEC ADC LR Clock I2C Data I2C Clock These signals do not go through the MAX II chip They pass through the MAX3378 level Table 4 7 Audio CODEC pin assignments 45 RS 232 Serial Port The MTDB board uses the ADM3202 transceiver chip and a 9 pin D SUB connector for RS 232 communications For detailed information on how to use the transceiver please refer to the datasheet which is available on the Datasheet folder of the MTDB System CD ROM or from the manufacturers web site Figure 4 8 shows the related schematics and Table 4 8 lists the HSMC pin assignments UART RXD lt UART TXD C27 EE Te RXDp 4 LEDR R75 330 UART RXD vo me LEDG Ed 330 UART TXD U5 R1OUT R2OUT R1IN
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