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MC68030UM-P1 - Freescale Semiconductor

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1. LONG WORD OPERAND WRITE Figure 7 16 Misaligned Write Cycles to Long Word Port MOTOROLA For More Information Un Hiis Albroduct Tel Go to www freescale com Bus Operation Freescale Semiconductor Inc 31 LONG WORD OPERAND REGISTER 0 CU a o os A 31 CACHE ENTRIES 0 EID XE 31 0 oF o EE T EEE DATA BUS D31 DO AN LONG Ki MEMORY MC68EC030 MEMORY CONTROL MSB UMB LMB LSB SIZ1 SIZO A2 At A0 DSACK1 DSACKO PR2 PR1 PR OPO 0 O s03 A 1 L L OP1 OP2 OP3 N 1 1 1 0 0 L L Figure 7 17 Misaligned Cachable Long Word Transfer from Long Word Bus 7 2 4 Address Size and Data Bus Relationships The data transfer examples show how the MC68030 drives data onto or receives data from the correct byte sections of the data bus Table 7 7 shows the combinations of the size signals and address signals that are used to generate byte enable signals for each of the four sections of the data bus for noncachable read cycles and all write cycles if the addressed device requires them The port size also affects the generation of these enable signals as shown in the table The four columns on the right correspond to the four byte enable signals Letters B W and L refer to port sizes B for 8 bit ports W for 16 bit ports and L for 32 bit ports The letters B W and L imply that the byte enable signal should be true for that port size A dash implies that the byte enable signal does not apply The MC68030 always drive
2. Similarly CBACK can be asserted independently of the assertion of CBREQ If a cache burst is not requested the assertion of CBACK is ignored The assertion of CIIN is ignored when the appropriate cache is not enabled or when cache inhibit out CIOUT is asserted It is also ignored during write cycles or translation table searches NOTE STERM and DSACKx should never be asserted during the same bus cycle 7 3 DATA TRANSFER CYCLES The transfer of data between the processor and other devices involves the following signals e Address Bus A0 A31 Data Bus DO D31 Control Signals The address and data buses are both parallel nonmultiplexed buses The bus master moves data on the bus by issuing control signals and the asynchronous synchronous bus uses a handshake protocol to insure correct movement of the data In all bus cycles the bus master is responsible for de skewing all signals it issues at both the start and the end of the cycle In addition the bus master is responsible for de skewing the acknowledge and data signals from the slave devices The following paragraphs define read write and read modify write cycle operations An additional paragraph describes burst mode transfers For Mare formation Un This Product MOS EA Go to www freescale com Freescale Semiconductor Inc Bus Operation Each of the bus cycles is defined as a succession of states These states apply to the bus operation and are different fr
3. Programming Model Data Types and Addressing Modes ee eeee Instruction Set Overview roses Sie Gs ara eee E RAS Virtual Memory and Virtual Machine Concepts o ar ag naka ta eda toe do Seba ie dut ies e rne e et Mt eth Virtual Machine ta veru paga A e RR OR NAN ire a E The Memory Management Unit eee eee Pip lined Architecture 224 225 Jone eee tabs TEENS The Cache Memories iio rete e Ron RR ORC eae Section 2 Data Organization and Addressing Capabilities Instruction OperandS s uuo esee erat Sb tul YA NAA PANAMA Organization of Data in Registers 2 0000 eee eee Data Registers ser euros ii ecce ers deas Address Regist X ec ere vote taa Control Beglslers 6 AA ieee dhe ORDEDES Organization of Data in Memory sells Addressing Modes lt 2 oA cre Bete eee ase eee ee EIER Data Register Direct Mode 0 00 eee mm Address Register Direct Mode oooooooooooooo Address Register Indirect Mode oooooooooooo Address Register Indirect with Postincrement Mode Address Register Indirect with Predecrement Mode Address Register Indirect with Displacement Mode Address Register Indirect with Index 8 Bit Displacement Mode Address Register Indirect with Index Base Displacement Mode Memory Indirect Postindexed Mode Memory Indirect Preindexed Mode 20000005 Prog
4. GENERATION EA PC Xn dg ASSEMBLER SYNTAX dg PC Xn SIZE SCALE MODE 111 REGISTER 011 31 0 PROGRAM COUNTER M ADDRESS OF EXTENSION WORD 31 7 0 DISPLACEMENT SIGN EXTENDED men 0 31 0 7 0 31 Y 0 NUMBER OF EXTENSION WORDS 1 2 16 MC 0 USER S MANUAL MOTOROLA For Ma ion U NAE Product Go to www freescale com Freescale Semiconductors dne Addressing Capabilities 2 4 13 Program Counter Indirect with Index Base Displacement Mode This mode is similar to the address register indirect with index base displacement mode described in 2 4 8 Address Register Indirect with Index Base Displacement Mode but the PC is used as the base register It requires an index register indicator and an optional 16 or 32 bit sign extended base displacement The operand is in memory The address of the operand is the sum of the contents of the PC the scaled contents of the sign extended index register and the base displacement The value of the PC is the address of the first extension word The reference is a program space reference and is only allowed for reads refer to 4 2 Address Space Types In this mode the PC the index register and the displacement are all optional However the user must supply the assembler notation ZPC zero value is taken for the PC to indicate that the PC is not used This allows the user to access the program space without using the PC in calculating the effective address The user can access th
5. l lille 11 48 MC68030 USER S MANUAL MOTOROLA For More Information On This Product Go to www freescale com Paragraph Number 11 6 16 11 6 17 11 6 18 11 7 11 7 1 11 7 2 11 8 11 9 12 1 12 1 1 12 1 2 12 1 3 12 2 12 3 12 4 12 4 1 12 4 2 12 5 12 5 1 12 5 2 12 5 3 12 6 12 6 1 12 6 2 12 7 12 7 1 12 7 2 12 8 13 1 13 2 MOTOROLA Freescale Semiconductor Inc TABLE OF CONTENTS Continued Control Instructions MN RE Pr p Exception Related Instructions and Operations Save and Restore Operations a Address Translation Tree Search Timing MMU Effective Address Calculation MMU Instruction Timing csse RR RE Interrupt ESEODCY wax tai cite oe ea ok tps Qr as Pu oe PP eal ae Nsa Bus Arbitration Latency s bs soe ek EE X Eee oa eR as Section 12 Applications Information Adapting the MC68030 to MC68020 Designs A O see aa eed eR Ee edicion uns Hardware Differences cece eee eee Software Differences 0 00 Floating Point IMIG cei dnd as ot dod a cette iuo ES TRES Byte Select Logic for the MC68030 000 MEMOry NIGH ACG vv otv cd tee ete he he a od eb ied d iocos Access Time Calculations llli Burst Mode Cycles s od etie ge RISQUE Pad endi ied RO Static RAM Memory Banks 2327 e DER rbd id PUER A Two Clock Synchronous Memory Bank Using SRAMS A 2 1
6. 9 41 Table Search Initialization Flowchart 0002000 eee eae 9 42 ATC Entry Creation Flowchart err croco a i ee ac d 9 42 Limit Check Procedure Flowchart cee eee eee eee 9 43 Detailed Flowchart of Descriptor Fetch Operation 9 44 Logical Address Map Using Function Code Lookup 9 45 Example Translation Tree Using Function Code Lookup 9 46 Example Translation Tree Structure for Two TaskS 9 47 Exmple Logical Address Map with Shared Supervisor and User Address Spaces core tossed ed eee DE St 9 49 Exmple Translation Tree Using S and WP Bits to Set Protection 9 50 Root Pointer Register CRP SRP Format 25 9 54 Translation Control Register TC Format 0 0005 9 54 Transparent Translation Register TTO and TT1 Format 9 57 MC68030 USER S MANUAL MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LIST OF ILLUSTRATIONS Continued Figure Page Number me Number 9 38 MMU Status Register MMUSR Format 2 00 0085 9 59 9 39 MMU Status Interpretation PTEST Level0 005 9 62 9 40 MMU Status Interpretation PTEST Level 7 0 0 a 9 63 10 1 F Line Coprocessor Instruction Operation Word 10 4 10 2 Asynchronous Non DMA M68000 Coprocessor Interface Signal Usage 10 6 10 3 MC68030 CPU S
7. Go to www freescale com Data Organization and add ARGEFAA 2emiconductor Inc 2 4 11 Program Counter Indirect with Displacement Mode In this mode the operand is in memory The address of the operand is the sum of the address in the PC and the sign extended 16 bit displacement integer in the extension word The value in the PC is the address of the extension word The reference is a program space reference and is only allowed for reads refer to 4 2 Address Space Types GENERATION EA PC d16 ASSEMBLER SYNTAX d16 PC MODE 111 REGISTER 010 PROGRAM COUNTER BI 15 0 DISPLACEMENT 4 SIGN EXTENDED INTEGER 31 0 MEMORY ADDRESS OPERAND NUMBER OF EXTENSION WORDS 1 2 4 12 Program Counter Indirect with Index 8 Bit Displacement Mode This mode is similar to the address register indirect with index 8 bit displacement mode described in 2 4 7 Address Register Indirect with Index 8 Bit Displacement Mode but the PC is used as the base register The operand is in memory The address of the operand is the sum of the address in the PC the sign extended displacement integer in the lower eight bits of the extension word and the sized scaled and sign extended index operand The value in the PC is the address of the extension word This reference is a program space reference and is only allowed for reads The user must include the displacement the PC and the index register when specifying this addressing mode
8. H BASE DISPLACEMENT SIGN EXTENDED VALUE INDEX REGISTER SIGN EXTENDED VALUE MEMORY ADDRESS OPERAND NUMBER OF EXTENSION WORDS 1 2 OR3 MOTOROLA For Mo matias ion On AUS Product 299 Go to www freescale com Data Organization and adari RGEFA A Semiconductor Inc 2 4 9 Memory Indirect Postindexed Mode In this mode the operand and its address are in memory The processor calculates an intermediate indirect memory address using the base register An and base displacement bd The processor accesses a long word at this address and adds the index operand Xn SIZE SCALE and the outer displacement to yield the effective address Both displacements and the index register contents are sign extended to 32 bits In the syntax for this mode brackets enclose the values used to calculate the intermediate memory address All four user specified values are optional Both the base and outer displacements may be null word or long word When a displacement is omitted or an element is suppressed its value is taken as zero in the effective address calculation GENERATION ASSEMBLER SYNTAX EA bd An Xn SIZE SCALE od MODE bd An Xn SIZE SCALE od ADDRESS REGISTER 110 31 0 eos 31 0 BASE DISPLACEMENT SIGN EXTENDED VALUE 31 POINTS TO 31 0 VALUE AT INDIRECT MEMORY ADDRESS 31 0 7 0 Y 31 0 31 Y 0 NUMBER OF EXTENSION WORDS 1 2 3 4 OR5 2 14 MC 0 USER S MANUAL MOTOROLA For Ma ion
9. Identify an indirect address in memory When the addressing mode uses a register the register field of the operation word specifies the register to be used Other fields within the instruction specify whether the register selected is an address or data register and how the register is to be used 2 4 1 Data Register Direct Mode In the data register direct mode the operand is in the data register specified by the effective address register field GENERATION EA Dn ASSEMBLER SYNTAX Dn MODE 000 REGISTER n 31 0 NUMBER OF EXTENSION WORDS 0 moe For Mold jetorimatien On This Product 29 Go to www freescale com Data Organization and adari tag EG AA 2emiconductor Inc 2 4 2 Address Register Direct Mode In the address register direct mode the operand is in the address register specified by the effective address register field GENERATION EA An ASSEMBLER SYNTAX An MODE 001 REGISTER n 31 0 NUMBER OF EXTENSION WORDS 0 2 4 3 Address Register Indirect Mode In the address register indirect mode the operand is in memory and the address of the operand is in the address register specified by the register field GENERATION EA An ASSEMBLER SYNTAX An MODE 010 REGISTER n 31 0 ADDRESS REGISTER An MEMORY ADDRESS 31 0 MEMORY ADDRESS OPERAND NUMBER OF EXTENSION WORDS 0 2 4 4 Address Register Indirect with Postincrement Mode In the address register indirect with posti
10. X destination An 8 NBCD ea 8 0 destination y X destination PACK An An 16 58 unpackaged source immediate data packed data destination Dn Dn data 16 58 SBCD Dn Dn 8 destination y source X destination An An 8 UNPK An 8 516 packed source unpacked source data unpacked source immediate data gt Dn Dn data 8216 unpacked destination I For More information On This Product eee ye Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary 3 2 8 Program Control Instructions A set of subroutine call and return instructions and conditional and unconditional branch instructions perform program control operations The no operation instruction NOP may be used to force synchronization of the internal pipelines Table 3 8 summarizes these instructions Table 3 8 Program Control Operations Instruction Operand Syntax Operand Size Operation Integer and Floating Point Conditional Bcc label 8 16 32 if condition true then PC d PC DBcc Dn label 16 if condition false then Dn 1 gt Dn if Dn 1 then PC d gt PC Scc ea 8 if condition true then 1 s gt destination else 0 s gt destination Unconditional BRA label 8 16 32 PC d gt PC BSR label 8 16 32 SP 4 gt SP PC gt SP PC d gt PC JMP ea none destination PC JSR ea none SP 4 5 SP PC gt
11. lille 3 5 3 2 Integer Arithmetic Operations 0000 0c eee eee 3 6 3 3 Logical Operations aeann qa s qoe ed SOR HERR US Qua dcn UN 3 7 3 4 Shift and Rotate Operations paa amma aaahhh ADA dada E ERE 3 8 3 5 Bit Manipulation Operations llle 3 9 3 6 BIEEIBId ODGFAIIOIS aia ae chs adc S Wette oe ee 3 9 3 7 BCD Operations 3 3 24 dd odo gue sitet oils ub tedio sedo opo bk ey he 3 10 3 8 Program Control Operations cece eee eee 3 11 3 9 System Control Operations ee 3 12 3 10 MMU Instructions 23 2 Sentus e SU EID neon eee dub t bor EG LA 3 13 3 11 Multiprocessor Operations Read Modify Write 3 13 3 12 Condition Code Computations Sheet 1 of 2 3 15 3 13 Conditional Tests duo PEE BANANA aie el eee ee Seed a deut ds 3 17 3 14 Instruction Set Summary Sheet 1 of 5 00000 3 20 4 1 Address Space EncodinuVs cock x es A Dee eee NG 4 5 5 1 Signal Index Sheet 1 of 2 pag at asas ee es ete eed he keke 5 2 5 2 Signal Summary sa va cnet ANAKAN EN QUE sce oe diu idle a ise 5 12 7 1 DSACK Codes and ResultS 0 00 eee eee 7 7 7 2 Size Signal Erncodifig s siu fin eet yee once Seg bos kda Ken Pana 7 9 7 3 Address OsetEncodings tica is 7 9 7 4 Data Bus Requirements for Read Cycles 7 10 7 5 MC68030 Internal to External Data Bus 7 11 7 6 Memory Alignment and Port Size Influence on Write Bus Cyc
12. ot LINA NOILOO3X3 sna SS3uaav Ss3uaaqv sna SS340dv NOILONYLSNI AHOVO NOILONY LSNI uHvO ualsib3u ONICTOH 3HOYO Jdid NOILONYLSNI 91901 TOHINOD AYOLS TOHINOD TOHILNOO ANY HIOINANOASOHIIN S vd SS3H40OY sna SS3ddaqv Figure 1 1 Block Diagram MOTOROLA MANWAL Product 0 USE S ormation Go to www freescale com fre For male 1 2 Freescale Semiconductor Inc introduction 1 1 FEATURES The features of the MC68030 microprocessor are Both Object Code Compatible with the MC68020 and Earlier M68000 Microprocessors Complete 32 Bit Nonmultiplexed Address and Data Buses 16 32 Bit General Purpose Data and Address Registers Two 32 Bit Supervisor Stack Pointers and 10 Special Purpose Control Registers 256 Byte Instruction Cache and 256 Byte Data Cache Can Be Accessed Simulta neously Paged MMU that Translates Addresses in Parallel with Instruction Execution and Inter nal Cache Accesses Two Transparent Segments Allow Untranslated Access to Physical Memory To Be D fined for Systems That Transfer Large Blocks of Data between Predefined Physical Ad dresses e g Graphics Applications Pipelined Architecture with Increased Parallelism Allows Accesses to Internal Caches To Occur in Parallel with Bus Transfers and Instruction Execution To Be Overlapped Enhanced Bus Controller Supports Asynchronous Bus
13. 10 32 10 22 Coprocessor Response Primitive Format a 10 35 10 23 Busy Primitive Format position rein EDU USE IS 10 36 10 24 Null Primitive Format o o ooooooooooon eee eee 10 37 10 25 Supervisor Check Primitive Format 0c eee eee 10 40 10 26 Transfer Operation Word Primitive Format 2 0055 10 41 10 27 Transfer from Instruction Stream Primitive Format 10 41 10 28 Evaluate and Transfer Effective Address Primitive Format 10 42 10 29 Evaluate Effective Address and Transfer Data Primitive 10 43 10 30 Write to Previously Evaluated EffectiveAddress Primitive Format 10 46 10 31 Take Address and Transfer Data Primitive Format 10 48 10 32 Transfer To From Top of Stack Primitive Format 10 49 10 33 Transfer Single Main Processor Register Primitive Format 10 50 10 34 Transfer Main Processor Control Register Primitive Format 10 51 10 35 Transfer Multiple Main Processor Registers Primitive Format 10 52 10 36 Register Select Mask Format 0 000 cee eee eee 10 52 10 37 Transfer Multiple Coprocessor Registers Primitive Format 10 53 MOTOROLA MC68030 USER S MANUAL xli For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LIST OF ILLUSTRATIONS Concluded Figure Title Number 10 38 Operand Format in Memory for Transfer
14. Bus Operation Freescale Semiconductor Inc State 1 One half clock later in S1 the processor asserts AS indicating that the address on the address bus is valid The processor also asserts DBEN during S1 which can enable external data buffers In addition the ECS and OCS if asserted signal is negated during S1 State 2 During S2 the processor places the data to be written onto the DO D31 and samples DSACKx at the end of S2 State 3 The processor asserts DS during S3 indicating that the data is stable on the data bus As long as at least one of the DSACKx signals is recognized by the end of S2 meeting the asynchronous input setup time requirement the cycle terminates one clock later If DSACKx is not recognized by the start of S3 the processor inserts wait states instead of proceeding to S4 and S5 To ensure that wait states are inserted both DSACKO and DSACK1 must remain negated throughout the asynchronous input setup and hold times around the end of S2 If wait states are added the processor continues to sample the DSACKx signals on the falling edges of the clock until one is recognized The selected device uses R W DS SIZO SIZ1 and A0 A1 to latch data from the appropriate byte s of the data bus D24 D31 D16 D23 D8 D15 and DO D7 SIZO SIZ1 and A0 A1 select the bytes of the data bus If it has not already done so the device asserts DSACKx to signal that it has successfully stored the data State 4 The proc
15. Coprocessor label 16 32 if cpcc true then PC d gt PC cpDBcc label Dn 16 if cpcc false then Dn 1 gt Dn if Dn z 1 then PC d gt PC cpGEN User Defined User Defined operand coprocessor cpRESTORE ea none restore coprocessor state from ea cpSAVE ea none save coprocessor state at ea cpScc ea 8 if cpcc true then 1 s gt destination else O s gt destination cpTRAPcc none none if coc true then TRAPcc exception data 16 32 moe For Mold jetorimatien On This Product a Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc 3 3 INTEGER CONDITION CODES The CCR portion of the SR contains five bits which indicate the results of many integer instructions Program and system control instructions use certain combinations of these bits to control program and system flow The first four bits represent a condition resulting from a processor operation The X bit is an operand for multiprecision computations when it is used it is set to the value of the C bit The carry bit and the multiprecision extend bit are separate in the M68000 Family to simplify programming techniques that use them refer to Table 3 8 as an example The condition codes were developed to meet two criteria Consistency across instructions uses and instances Meaningful Results no change unless it provides useful information Consistency across instructions means that all instructions tha
16. SP gt PC SP 4 gt SP RTS SP PC SP 45 SP RTS SBCD _ Destination Source X gt Destination SBCD Dx Dy SBCD Ax Ay Scc If condition true Scc ea then 1s gt Destination else Os gt Destination STOP If supervisor state STOP data then Immediate Data gt SR STOP else TRAP SUB Destination Source gt Destination SUB ea Dn SUB Dn ea SUBA Destination Source gt Destination SUBA ea An SUBI Destination Immediate Data gt Destination SUBI data ea SUBQ Destination Immediate Data gt Destination SUBA data ea SUBX Destination Source X gt Destination SUBX Dx Dy SUBX Ax Ay SWAP Register 31 16 gt Register 15 0 SWAP Dn TAS Destination Tested gt Condition Codes 1 gt bit 7 of Destination TAS ea TRAP SSP 2 gt SSP Format Offset gt SSP TRAP vector SSP 4 gt SSP PC gt SSP SSP 2 gt SSP SR gt SSP Vector Address PC TRAPcc If cc then TRAP TRAPcc TRAPcc W data TRAPcc L data TRAPV IfV then TRAP TRAPV TST Destination Tested gt Condition Codes TST ea UNLK An gt SP SP gt An SP 45 SP UNLK An UNPK Source Packed BCD adjustment Destination Unpacked BCD UNPACK Ax Ay adjustment UNPACK Dx Dy adjustment NOTES 1 Specifies either the instruction IC data DC or IC DC caches 2 Where r is rounding precision S or D 3 A list of any combination of the eight floating point data regist
17. 0d Immediate 111 100 X X data These categories are sometimes combined forming new categories that are more restrictive Two combined classifications are alterable memory or data alterable The former refers to those addressing modes that are both alterable and memory addresses and the latter refers to addressing modes that are both data and alterable 2 6 PROGRAMMER S VIEW OF ADDRESSING MODES Extensions to the indexed addressing modes indirection and full 32 bit displacements provide additional programming capabilities for both the MC68020 and the MC68030 This section describes addressing techniques that exploit these capabilities and summarizes the addressing modes from a programming point of view eu For IC ORO USERS MANYAL product MOTOROLA Go to www freescale com Freescale Semiconductors dne Addressing Capabilities Several of the addressing techniques described in this section use data registers and address registers interchangeably While the MC68030 provides this capability its performance has been optimized for addressing with address registers The performance of a program that uses address registers in address calculations is superior to that of a program that similarly uses data registers The performance has been optimized for addressing registers in address calculations is superior to that of a program that similarly uses data registers The specification of addresses with data registers should be used sp
18. 20 eeee eee eee 7 59 Bus Arbitration Flowchart for Single Request 7 60 Bus Arbitration Operation Timing 00 eee eee eee 7 61 Bus Arbitration State Diagram 00 00 eee 7 62 Single Wire Bus Arbitration Timing Diagram 055 7 63 Bus Arbitration Operation Bus Inactive o ooocoooooooo 7 64 Initial Reset Operation Timing ooooocoooococrnncon 7 65 Processor Generated Reset Operation ee eee 8 1 Reset Operation Flowchart 8 2 Interrupt Pending Procedure 002 e eee eee eee 8 3 Interrupt Recognition Examples 20000 eee eee eee 8 4 Assertion ol IPEND o lad ord tie betes neato dae se sie kan 8 5 Interrupt Exception Processing Flowchart o o o oooooooo 8 6 Examples of Interrupt Recognition and Instruction Boundaries 8 7 Breakpoint Instruction Flowchart 000 cece eee eee eee MOTOROLA MC68030 USER S MANUAL For More Information On This Product Go to www freescale com Page Number XXXIX xl Freescale Semiconductor Inc LIST OF ILLUSTRATIONS Continued Page qe Number RTE Instruction for Throwaway Four Word Frame 8 26 Special Status Word SSW ee 8 28 MMU Block Diagram ss scion a eta 9 3 MMU Programming Model s ostia Ge eee sual 9 4 Translation Table Trees 3626 chee peace enr Ng tbe ie 9 5 Example Translation Table Tre
19. SR see Figure 1 4 stores the processor status It contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program The condition codes are extend X negative N zero Z overflow V and carry C The user byte containing the condition codes is the only portion of the status register information available in the user privilege level and it is referenced as the CCR in user programs In the supervisor privilege level software can access the full status register including the interrupt priority mask three bits as well as additional control bits These bits indicate whether the processor is in 1 One of two trace modes T1 TO 2 Supervisor or user privilege level S 3 Master or interrupt mode M The vector base register VBR contains the base address of the exception vector table in memory The displacement of an exception vector is added to the value in this register to access the vector table MOTOROLA For Mo matias ion On AUS Product id Go to www freescale com iditoduction Freescale Semiconductor Inc Alternate function code registers SFC and DFC contain 3 bit function codes Function codes can be considered extensions of the 32 bit linear address that optionally provide as many as eight 4 Gbyte address spaces Function codes are automatically generated by the processor to select address spaces for data and program at the user and super
20. System software executing at the supervisor level uses the control registers of the supervisor level to perform supervisor functions For Mars formation Un This Product MOS EA Go to www freescale com Freescale Semiconductor Inc introduction Figure 1 2 shows the user programming model consisting of 16 32 bit general purpose reg isters and two control registers e General Purpose 32 Bit Registers DO D7 AO A7 32 Bit Program Counter PC 8 Bit Condition Code Register CCR The supervisor programming model consists of the registers available to the user plus 14 control registers Two 32 Bit Supervisor Stack Pointers ISP and MSP 16 Bit Status Register SR 32 Bit Vector Base Register VBR 32 Bit Alternate Function Code Registers SFC and DFC 32 Bit Cache Control Register CACR 32 Bit Cache Address Register CAAR 64 Bit CPU Root Pointer CRP 64 Bit Supervisor Root Pointer SRP 32 Bit Translation Control Register TC 32 Bit Transparent Translation Registers TTO and TT1 16 Bit MMU Status Register MMUSR The user programming model remains unchanged from previous M68000 Family microprocessors The supervisor programming model supplements the user programming model and is used exclusively by the MC68030 system programmers who utilize the supervisor privilege level to implement sensitive operating system functions I O control and memory management subsystems The supervisor programming model contains al
21. These three state outputs provide the address for the current bus cycle except in the CPU address space Refer to 4 2 Address Space Types for more information on the CPU address space A31 is the most significant address signal Refer to 7 1 2 Address Bus for information on the address bus and its relationship to bus operation 5 4 DATA BUS D0 D31 These three state bidirectional signals provide the general purpose data path between the MC68030 and all other devices The data bus can transfer 8 16 24 or 32 bits of data per bus cycle D31 is the most significant bit of the data bus Refer to 7 1 4 Data Bus for more information on the data bus and its relationship to bus operation 5 5 TRANSFER SIZE SIGNALS SIZO SIZ1 These three state outputs indicate the number of bytes remaining to be transferred for the current bus cycle With AO A1 DSACKO DSACK1 and STERM SIZO and SIZ1 define the number of bits transferred on the data bus Refer to 7 2 1 Dynamic Bus Sizing for more information on the size signals and their use in dynamic bus sizing zn For More itor BR Un his Product MOTOROLA C Go to www freescale com Freescale Semiconductor Inc Signal Description 5 6 BUS CONTROL SIGNALS The following signals control synchronous bus transfer operations for the MC68030 5 6 1 Operand Cycle Start OCS This output signal indicates the beginning of the first external bus cycle for an instruction prefetch or a data operand tra
22. paragraphs Systems having several devices that can become bus master require external circuitry to assign priorities to the device so that when two or more external devices attempt to become bus master at the same time the one having the highest priority becomes bus master first The sequence of the protocol is 1 An external device asserts the bus request signal 2 The processor asserts the bus grant signal to indicate that the bus will become avail able at the end of the current bus cycle 3 The external device asserts the bus grant acknowledge signal to indicate that it has assumed bus mastership BR may be issued any time during a bus cycle or between cycles BG is asserted in response to BR it is usually asserted as soon as BR has been synchronized and recognized except when the MC68030 has made an internal decision to execute a bus cycle Then the assertion of BG is deferred until the bus cycle has begun Additionally BG is not asserted until the end of a read modify write operation when RMC is negated in response to a BR signal When the requesting device receives BG and more than one external device can be bus master the requesting device should begin whatever arbitration is required The external device asserts BGACK when it assumes bus mastership and 2x For MAS RA USOS UA NIAE Product Moreno Go to www freescale com Bus Operation Freescale Semiconductor Inc maintains BGACK during the entire bus cycle or cyc
23. three of the encodings are implemented as shown in Figure 7 42 All unused values are reserved by Motorola for future additional CPU space types EINS NON ADDRESS BUS CODE 2 0 31 l23 19 16 4 2 0 KNOWLEDGE 00000000000 0 000 00000000000 0 mers o o EON 1 t1 00000000000 0 0000 0000000000 o Be 31 15 3 4 0 COPROCEBSON 11 1 000000000000 01010 CPD 000000 00 CPREG 31 3 10 INTERRUPT e TIN EA Ea E A EA AA A NUT CPU SPACE TYPE FIELD Figure 7 42 MC68030 CPU Space Address Encoding 7 4 1 Interrupt Acknowledge Bus Cycles When a peripheral device signals the processor with the IPLO IPL2 signals that the device requires service and the internally synchronized value on these signals indicates a higher priority than the interrupt mask in the status register or that a transition has occurred in the case of a level 7 interrupt the processor makes the interrupt a pending interrupt Refer to 8 1 9 Interrupt Exceptions for details on the recognition of interrupts The MC68030 takes an interrupt exception for a pending interrupt within one instruction boundary after processing any other pending exception with a higher priority The following paragraphs describe the various kinds of interrupt acknowledge bus cycles that can be executed as part of interrupt exception processing NOR For mo IRALA Product P Go to www freescale com Bus Operation Freescale Semiconductor Inc 7 4 1 1 INTERRUPT ACKNOWLEDGE CYCLE TERMINATE
24. www freescale com Bus Operation Freescale Semiconductor Inc As E EAST e AA AA oe ee VOLTS lt t gt 520 CLOCKS gt gt Voc RESET E 1 lt 4 CLOCKS gt AS lt 4cLocks gt CVG Es AX XXX XXX XXX XXX ENTIRE ALL CONTROL SIGNALS BUS HIGH INACTIVE DATA BUS IN IMPEDANCE READ MODE ADDRESS ISP XXX BUS STATE UNKNOWN BUS DRIVEN READ STARTS Figure 7 64 Initial Reset Operation Timing Resetting the processor causes any bus cycle in progress to terminate as if DSACKx BERR or STERM had been asserted In addition the processor initializes registers appropriately for a reset exception Exception processing for a reset operation is described in 8 1 1 Reset Exception When a reset instruction is executed the processor drives the RESET signal for 512 clock cycles In this case the processor resets the external devices of the system and the internal registers of the processor are unaffected The external devices connected to the RESET signal are reset at the completion of the reset instruction An external RESET signal that is asserted to the processor during execution of a reset instruction must extend beyond the reset period of the instruction by at least eight clock cycles to reset the processor Figure 7 65 shows the timing information for the reset instruction i For MUS RA USOS UA NIAE Product MOTOR Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2
25. 1 1 Addressing Modes Addressing Modes Syntax Register Direct Data Register Direct Dn Address Register Direct An Register Indirect Address Register Indirect An Address Register Indirect with Postincrement An Address Register Indirect with Predecrement An Address Register Indirect with Displacement dig An Register Indirect with Index Address Register Indirect with Index 8 BitDisplacement dg An Xn Address Register Indirect with Index Base Displacement bd An Xn Memory Indirect Memory Indirect Postindexed Memory Indirect Preindexed bd An Xn od pd An Xn od Program Counter Indirect with Displacement dig PC Program Cou nter Indirect with IndexPC Indirect with Index 8 Bit Displacement PC Indirect with Index Base Displacement dg PC Xn bd PC Xn Program Counter Memory Indirect PC Memory Indirect Postindexed bd PC Xn od bd PC Xn od PC Memory Indirect Preindexed Absolute Absolute Short xxx W Absolute Long xxx L Immediate data NOTES Dn Data Register DO D7 An Address Register AO A7 8 416 A twos complement or sign extended displacement added as part of the effective address calculation size is 8 dg or 16 d45 bits when omitted assemblers use a value of zero Xn Address or data register used as an index register form is Xn SIZE SCALE where SIZE is W or L indicates index register size and SCALE is 1
26. 1 1 Burst Mode Memory Bank Using SRAMS A 3 1 1 1 Burst Mode Memory Bank Using SRAMS External Gaclies o5 sote to hehe eto tmt atn nates Be at le Se ruo Cache Implementation busco a a e ea Instruction Only External Cache Implementations Deb gging Aids oia acia batas MR Status and Refill sc pw Bran AER Real Time Instruction Trace 20 eee eee eee Power and Ground Considerations o oooocccooooo Section 13 Electrical Characteristics Maxim m FAS tata dte Sum qux iod cete tr ieu be cast b Thermal Characteristics PGA Package MC68030 USER S MANUAL For More Information On This Product Go to www freescale com Page Number 11 49 11 50 11 51 11 51 11 58 11 60 11 61 11 62 XXXV Freescale Semiconductor Inc TABLE OF CONTENTS Concluded Paragraph i Page Number Title Number Section 14 Ordering Information and Mechanical Data 14 1 Standard MC68030 Ordering Information 14 1 14 2 Pin Assignments Pin Grid Array RC Suffix 14 2 14 3 Pin Assignments Ceramic Surface Mount FE Suffix 14 3 14 4 Package DImetsionis 2s kPREIERRA ELIO SR PRESS RAPERE 14 4 Appendix A M68000 Family Summary xxxvi MC68030 USER S MANUAL MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LIST OF ILLUSTRATIONS Figure Page amber one Number 1 1 Block Diagr
27. 1 9 Interrupt Exceptions for interrupt information Also refer to 7 4 1 Interrupt Acknowledge Bus Cycles for bus information related to interrupts 5 8 3 Autovector AVEC This input signal indicates that the MC68030 should generate an automatic vector during an interrupt acknowledge cycle Refer to 7 4 1 2 Autovector Interrupt Acknowledge Cycle for more information about automatic vectors 5 9 BUS ARBITRATION CONTROL SIGNALS The following signals are the three bus arbitration control signals used to determine which device in a system is the bus master 5 9 1 Bus Request BR This input signal indicates that an external device needs to become the bus master This is typically a wire ORed input but does not need to be constructed from open collector devices Refer to 7 7 Bus Arbitration for more information s For More informatio ion a YANYAL Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Signal Description 5 9 2 Bus Grant BG This output indicates that the MC68030 will release ownership of the bus master when the current processor bus cycle completes Refer to 7 7 2 Bus Grant for more information 5 9 3 Bus Grant Acknowledge BGACK This input indicates that an external device has become the bus master Refer to 7 7 3 Bus Grant Acknowledge for more information 5 10 BUS EXCEPTION CONTROL SIGNALS The following signals are the bus exception control signals for the MC68030 5 10 1 Reset RE
28. 2 4 or 8 index register is multiplied by SCALE use of SIZE and or SCALE is optional bd A twos complement base displacement when present size can be 16 or 32 bits od Outer displacement added as part of effective address calculation after any memory indirection use is optional with asize of 16 or 32 bits PC Program Counter dat Immediate value of 8 16 or 32 bits Effective Address Use as indirect access to long word address 030 USER S MOTOROLA For mace ormation MANWAL Product Go to www freescale com Freescale Semiconductor Inc introduction 1 6 VIRTUAL MEMORY AND VIRTUAL MACHINE CONCEPTS The full addressing range of the MC68030 is 4 Gbytes 4 294 967 296 bytes in each of eight address spaces Even though most systems implement a smaller physical memory the system can be made to appear to have a full 4 Gbytes of memory available to each user program by using virtual memory techniques In a virtual memory system a user program can be written as if it has a large amount of memory available when the physical memory actually present is much smaller Similarly a system can be designed to allow user programs to access devices that are not physically present in the system such as tape drives disk drives printers terminals and so forth With proper software emulation a physical system can appear to be any other M68000 computer system to a user program and the program can be given full access to all of the resour
29. 6 1 3 Cache Filling 7 3 4 Synchronous Read Cycle 7 3 5 Synchronous Write Cycle and 7 3 7 Burst Operation Cycles which discuss in detail the required bus cycles PES For More tora BR Un his Product MOTOROLA C Go to www freescale com Freescale Semiconductor Inc Bus Operation 7 2 7 Cache Interactions The organization and requirements of the on chip instruction and data caches affect the interpretation of the DSACKx and STERM signals Since the MC68030 attempts to load all data operands and instructions that are cachable into the on chip caches the bus may operate differently when caching is enabled Specifically on cachable read cycles that terminate normally the low order address signals AO and A1 and the size signals do not apply The slave device must supply as much aligned data on the data bus as its port size allows regardless of the requested operand size This means that an 8 bit port must supply a byte a 16 bit port must supply a word and a 32 bit port must supply an entire long word This data is loaded into the cache For a 32 bit port the slave device ignores AO and A1 and supplies the long word beginning at the long word boundary on the data bus For a 16 bit lz port the device ignores AO and supplies the entire word beginning at the lower word boundary on D16 D31 of the data bus For a byte port the device supplies the addressed byte on D24 D31 If the addressed device cannot supply port sized
30. 7 5 3 Halt Operation When HALT is asserted and BERR is not asserted the MC68030 halts external bus activity at the next bus cycle boundary HALT by itself does not terminate a bus cycle Negating and reasserting HALT in accordance with the correct timing requirements provides a single step bus cycle to bus cycle operation The HALT signal affects external bus cycles only thus a program that resides in the instruction cache and performs no data writes or reads that miss in the data cache may continue executing unaffected by the HALT signal 7 93 Go to www freescale com For More information Un This Product UNE Bus Operation Freescale Semiconductor Inc S0 Si S2 SI S0 Si S2 SI S4 RW Figure 7 56 Late Retry Operation for a Burst The single cycle mode allows the user to proceed through and debug external processor operations one bus cycle at a time Figure 7 57 shows the timing requirements for a single cycle operation Since the occurrence of a bus error while HALT is asserted causes a retry operation the user must anticipate retry cycles while debugging in the single cycle mode The single step operation and the software trace capability allow the system debugger to trace single bus cycles single instructions or changes in program flow These processor capabilities along with a software debugging package give complete debugging flexibility as For IC ORO USERS MANWAL product MOTOROLA
31. 7 60 shows that BG is negated a few clock cycles after the transition of the BGACK signal However if bus requests are still pending after the negation of BG the processor asserts another BG within a few clock cycles after it was negated This additional assertion of BG allows external arbitration circuitry to select the next bus master before the current bus master has finished with the bus The following paragraphs provide additional information about the three steps in the arbitration process Bus arbitration requests are recognized during normal processing RESET assertion HALT assertion and even when the processor has halted due to a double bus fault nG For MUS RR USTOS BANAL Product MOTOROLA Go to www freescale com Bus Operation Freescale Semiconductor Inc CONTROLLER REQUESTING DEVICE REQUEST THE BUS GRANT BUS ARBITRATION 1 ASSERT BUS REQUEST BR 1 ASSERT BUS GRANT BG ACKNOWLEDGE BUS MASTERSHIP EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE NEXT BUS MASTER ASSERTS BUS GRANT ACKNOWLEDGE BGACK TO BECOME NEW MASTER TERMINATE ARBITRATION BUS MASTER NEGATES BR 1 NEGATE BG AND WAIT FOR BGACK TO PENEGATED OPERATE AS BUS MASTER 1 PERFORM DATA TRANSFERS READ AND WRITE CYCLES REARBITRATE OR RESUME RELEASE BUS MASTERSHIP CONTROLLER OPERATION 1 NEGATE BGACK Figure 7 59 Bus Arbitration Flowchart for Single Request 7 7 1 B
32. 8 31 8 3 Coprocessor Considerations 5 359 xr xd doe be ey Su ka had 8 32 8 4 Exception Stack Frame Formats cece eeeeee 8 32 Section 9 Memory Management Unit 9 1 Translation Table Structure 0 2 00 eee eee eee 9 6 9 1 1 Translation Control eise Sot reed alee ee he seda 9 8 9 1 2 Translation Table Descriptors is 5 25 xx re ed tees i3 9 10 9 2 Address TranslallOli 205 oe SEE e aaa 9 13 9 2 1 General Flow for Address Translati0N ooo oo 9 13 9 2 2 Effect of RESET On MM s enc doge haar ta eruere E x Ea 9 15 9 2 3 Effect of MMUDIS On Address Translation 9 15 9 3 Transparent Translatlofis x a 2m e EE bass ERUREE 9 16 9 4 Address Translation Cache sells 9 17 9 5 Translation Table Detalles ata ass Ep ee A Qr ue ang aag 9 20 9 5 1 Descriptor Details str lada Rabe iE bbws bs e Poe tte tO des 9 20 9 5 1 1 Descriptor Field Definitions ooooooooooo 9 20 9 5 1 2 Root Pointer Descriplot oro utu y voe reet ers 9 23 9 5 1 3 Short Format Table Descriptor ooooocccoooooo 9 24 9 5 1 4 Long Fomat Table Descriptor oooooocooooo 9 24 9 5 1 5 Short Format Early Termination Page Descriptor 9 25 9 5 1 6 Long Format Early Termination Page Descriptor 9 25 9 5 1 7 Short Format Page Descriptor s an anaana a 9 26 9 5 1 8 Long Format Page Descriptor a asana aaaeeeaa 9 26 9 5 1 9 Short Format Invalid Descriptor
33. Bcc instruction description as an example For Mo matias ion On AUS Product 3 19 Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc Table 3 14 Instruction Set Summary Sheet 1 of 5 Opcode Operation Syntax ABCD Source3p Destination X gt Destination ABCD Dy Dx ABCD Ay Ax ADD Source Destination gt Destination ADD ea Dn ADD Dn ea ADDA Source Destination gt Destination ADDA ea An ADDI Immediate Data Destination gt Destination ADDI data ea ADDQ Immediate Data Destination gt Destination ADDQ data ea ADDX Source Destination X Destination ADDX Dy Dx ADDX Ay Ax AND Source A Destination Destination AND ea Dn AND Dn ea ANDI Immediate Data A Destination gt Destination ANDI data ea ANDI Source A CCR gt CCR ANDI data CCR to CCR ANDI If supervisor state ANDI data SR to SR then Source ASR gt SR else TRAP ASL ASR Destination Shifted by count gt Destination ASd Dx Dy ASd data Dy ASd ea Bcc If condition true then PC d gt PC Bcc label BCHG number of Destination gt Z BCHG Dn ea BCHG data ea number of Destination gt bit number of Destination BCLR bit number of Destination gt Z BCLR Dn ea BCLR data ea 0 2 bit number of Destination BFCHG bit field of Destination bit field of
34. D ELSE GO TO E 1 NEGATE STERM O UNLOCK BUS 1 NEGATE RMC START NEXT CYCLE Figure 7 35 Synchronous Read Modify Write Cycle Flowchart MOTOROLA For Mol4Qp3030 USER ion On AUS Product TS Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 St S2 S3 Si Si S4 S5 S6 S7 CLK T mu AN CBREO eT aww y Figure 7 36 Synchronous Read Modify Write Cycle Timing CIIN Asserted State 0 The processor asserts ECS and OCS in SO to indicate the beginning of an external operand cycle The processor also asserts RMC in SO to identify a read modify write cycle The processor places a valid address on A0 A31 and valid function codes on FCO FC2 The function codes select the address space for the operation SIZ0 SIZ1 become valid in SO to indicate the operand size The processor drives R W high for a read cycle me For MUS ARO USOS BANAL Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bus Operation and sets CIOUT to the value of the MMU CI bit in the address translation descriptor or in the appropriate TTx register The processor drives DBEN inactive to disable the data buffers State 1 One half clock later in S1 the processor asserts AS indicating that the address on the address bus is valid The processor also asserts DS during S1 In addition the ECS and OCS if asserted signal is negated during S1 State 2 The selected device uses R W
35. D1 CAS2L DO D1 D1 D1 A0 A1 IF STILL POINT TO ENTRY TO BE DELETED THEN UPDATE HEAD AND FORWARD POINTERS BNE SDLOOP IF NOT TRY AGAIN SDEMPTY SUCCESSFUL DELETION ADDRESS OF DELETED ENTRY IN DO MAY BE NULL BEFORE DELETING AN ELEMENT J Le Ll e AFTER DELETING AN ELEMENT Lale Figure 3 3 Linked List Deletion HEAD AS For Mold jetorimatien On This Product sa Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc The CAS2 instruction can also be used to correctly maintain a first in first out doubly linked list A doubly linked list needs two controlled locations LIST PUT and LIST GET which contain pointers to the last element inserted in the list and the next to be removed respectively If the list is empty both pointers are NULL 0 The code fragment shown in Figure 3 4 illustrates the insertion of an element in a doubly linked list The first two instructions load the effective addresses of LIST PUT and LIST GET into registers AO and A1 respectively The next instruction moves the address of the new element into register D2 Another MOVE instruction moves the address in LIST PUT into register DO At label DILOOP a TST instruction tests the value in DO and the BEQ instruction branches to the MOVE instruction when DO is equal to zero Assuming the list is empty this MOVE instruction is executed next it moves the zero in DO into the NEXT and LAST pointers of the new element Then the C
36. D8 D15 and DO D7 SIZO SIZ1 and A0 A1 select the data bus sections The device asserts STERM when it has successfully stored the data If the device does not assert STERM by the rising edge of S2 the processor inserts wait states until it is recognized The processor asserts DS at the end of S2 if wait states are inserted For zero wait state synchronous write cycles DS is not asserted MOTOROLA For Mol4Qp3030 USER ion On AUS Product ER Go to www freescale com Bus Operation Freescale Semiconductor Inc State 3 The processor negates AS and DS if necessary during S3 It holds the address and data valid during S3 to simplify memory interfaces R W SIZO SIZ1 FCO FC2 and DBEN also remain valid throughout S3 The addressed device must negate STERM within two clock periods after asserting it or the processor may use STERM for the next bus cycle 7 3 6 Synchronous Read Modify Write Cycle A synchronous read modify write operation differs from an asynchronous read modify write operation only in the terminating signal of the read and write cycles and in the use of CLK instead of DS latching data in the write cycle Like the asynchronous operation the synchronous read modify write operation is indivisible Although the operation is synchronous the burst mode is never used during read modify write cycles Figure 7 35 is a flowchart of the synchronous read modify write operation Timing for the cycle is shown in Figure 7 3
37. DATA 1 ASSERT BUS ERRROR BERR TO INITIATE 2 NEGATE AS AND DS EXCEPTION PROCESSING 3 GOTO A IF BERR ASSERTED 1 NEGATE AS AND DS 2 GOTO 1 PLACE LATCHED DATA IN INSTRUCTION SLAVE NEGATES DSACKx STERM OR BERR PIPELINE 2 CONTINUE PROCESSING 1 INITIATE ILLEGAL INSTRUCTION PROCESSING fe Figure 7 46 Breakpoint Operation Flow 7 5 BUS EXCEPTION CONTROL CYCLES The MC68030 bus architecture requires assertion of either DSACKx or STERM from an external device to signal that a bus cycle is complete DSACKx STERM or AVEC is not asserted if The external device does not respond No interrupt vector is provided Various other application dependent errors occur External circuitry can provide BERR when no device responds by asserting DSACKx STERM or AVEC within an appropriate period of time after the processor asserts AS This allows the cycle to terminate and the processor to enter exception processing for the error condition The MMU can also detect an internal bus error This occurs when the processor attempts to access an address in a protected area of memory a user program attempts to access supervisor data for example or after the MMU receives a bus error while searching the address table for an address translation description NOR For mo RISLEY Product Pu Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2 S4 S0 S2 S4 S0 S2 eec E Tes AEn gr deg qp ese qr p
38. DBEN 1 REMOVE DATA FROM D31 D0 2 NEGATE DSACK START NEXT CYCLE Figure 7 19 Asynchronous Long Word Read Cycle Flowchart CONTROLLER EXTERNAL DEVICE ADDRESS DEVICE 1 ASSERT ECS OCS FOR ONE HALF CLOCK 2 SET R W TO READ 3 DRIVE ADDRESS ON A31 A0 4 DRIVE FUNCTION CODE ON FC2 FCO PRESENT DATA DRIVE SIZE SIZ1 SIZO FOUR BYTES 1 DECODE ADDRESS 7 8 9 CACHE INHIBIT OUT CIOUT BECOMES VALID ASSERT ADDRESS STROBE AS id DSTA ASSERT DATA STROBE DS aie DEOR ASSERT DATA BUFFER ENABLE DBEN D7 DO BASED ON A1 A0 CACHE AND BUS WIDTH 3 ASSERT DATA TRANSFER AND SIZE oes ACKNOWLEDGE DSACKx 1 SAMPLE CACHE INHIBIT IN CIIN 2 LATCH DATA 3 NEGATE AS AND DS 4 NEGATE DBEN TERMINATE CYCLE 1 REMOVE DATA FROM D31 D0 2 NEGATE DSACK START NEXT CYCLE Figure 7 20 Asynchronous Byte Read Cycle Flowchart fe For Mare formation Un This Product MOTOBOLA Go to www freescale com Freescale Semiconductor Inc Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 S4 A1 N A0 wi NL WORD BYTE SIZO RW DSACKt EE EN d CEN uS MN DSACKO Vo oa HA CNET ue DEUM DBEN D31 D24 OP2 D23 D16 OP3 D15 D8 OP3 D7 DO OP3 lt WORD READ gt lt BYTE READ x BYTE READ x Figure 7 21 Asynchronous Byte and Word Read Cycles 32 Bit Port DE For Mo jetormatien On This Product Go to www freescale com 7 33 Freescale Semiconductor Inc Bus Operation SIZ
39. Destination BFCHG ea offset width BFCLR 0 gt bit field of Destination BFCLR lt ea offset width BFEXTS bit field of Source gt Dn BFEXTS lt ea offset width Dn BFEXTU bit offset of Source gt Dn BFEXTU ea offset width Dn BFFFO bit offset of Source Bit Scan gt Dn BFFFO ea foffset width Dn BFINS Dn bit field of Destination BFINS Dn ea offset width BFSET 1s gt bit field of Destination BFSET ea offset width BFTST bit field of Destination BFTST ea offset width BKPT Run breakpoint acknowledge cycle BKPT data TRAP as illegal instruction BRA PC d gt PC BRA label BSET bit number of Destination gt Z BSET Dn ea BSET data ea 1 gt bit number of Destination BSR SP 4 SP PC gt SP PC d PC BSR label BTST bit number of Destination gt Z BTST Dn ea BTST data ea 3 20 MOTOROLA For More Information Un This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary Table 3 14 Instruction Set Summary Sheet 2 of 5 Opcode Operation Syntax CAS CAS Destination Compare Operand gt cc CAS Dc Du ea CAS2 CAS2 if Z Update Operand Destination Dc1 Dc2 Du1 Du2 Rn1 Rn2 else Destination Compare Operand CAS2 Destination 1 Compare 1 gt cc if Z Destination 2 Compare gt cc if Z Update 1 gt Destination 1 Update 2 gt Destination 2 else Destinatio
40. ED E BUS E EE D31 D16 A WORD MEMORY MC68EC030 MEMORY CONTROL MSB LSB sizi SIZO A2 At AO DSACKi DSACKO XXX OP2 1 o 0 0 14 L H OP3 XXX o 1 0 14 0 L H Figure 7 14 Example of Misaligned Cachable Word Transfer from Word Bus 15 LONG WORD OPERAND 0 D31 DATA BUS DO LONG WORD MEMORY MC68EC030 MEMORY CONTROL MSB UMB LMB LSB SIZ1 SIZO A2 At A0 DSACKT DSACKO XXX XXX XXX OPO Qc 0 0 1 1 L L OP1 OP OP3 XXX i odo op L L Figure 7 15 Misaligned Long Word Transfer to Long Word Port Table 7 6 shows that the processor always prefetches instructions by reading a long word from a long word address A1 A0 00 regardless of port size or alignment When the required instruction begins at an odd word boundary the processor attempts to fetch the entire 32 bits and loads both words into the instruction cache if possible although the second one is the required word Even if the instruction access is not cached the entire 32 bits are latched into an internal cache holding register from which the two instructions words can subsequently be referenced Refer to Section 11 Instruction Execution Timing for a complete description of the cache holding register and pipeline operation ce For MALE USER ion a YANYAL Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bus Operation S0 S2 S4 S0 S2 S4 JON A0 N FC2 FCO X X SIZ1 SIZO D15 D8 OP1 OP3 BYTE WRITE 3 BYTE WRITE
41. MOVEC Move Control Register ADDA Add Address MOVEM Move Multiple Registers ADDI Add Immediate MOVEP Move Periphral ADDQ Add Quick MOVEQ Move Quick ADDX Add with Extend MOVES Move Alternate Address Space AND Logical AND MULS Signed Multiply ANDI Logical AND Immediate MULU Unsigned Multiply ASL ASR Arithmatic Shift Left and Right NBCD Negate Decimal with Extend Bcc Branch Conditionally NEG Negate BCHG Test Bit and Change NEGX Negate with Extend BCLR Test Bit and Clear NOP No Operation BFCHG Test Bit Feild and Change NOT Logical Compliment BFCLR Test Bit Feild and Clear OR Logical Inclusive OR BFEXTS Signed Bit Feild Extract ORI Logical Inclusive OR Immediate BFEXTU Unsigned Bit Feild Extract ORI CCR Logical Inclusive OR Immediate to BFFO Bit Feild Find First One Condition Codes BFINS Bit Feild Insert ORI SR Logical Inclusive OR Immediate to BFSET Test Bit Feild and Set Status Register BFTST Test Bit Feild PACK Pack BCD BKPT Breakpoint PEA Push Effective Address BRA Branch PFLUSH Flush Entry ies in the ATC BSET Test Bit and Set PFLUSHA Flush All Entries in the ATC BSR Branch to Subroutine PLOADR Load Entry into the ATC BTST Test Bit PLOADW CAS Compare and Swap Operands PMOVE Move to from MMU Registers CAS 2 Compare and Swap Dual Operands PMOVEFD Move to from MMU Registers with CHK Check Register Against Bound Flush Disable CHK2 Check Register Against Upper and PTESTR Test a Logical Address Lower Bounds PTESTW CLR Clear RESET Reset External Device
42. Packed BCD a MSB First Digit e MSB Second Digit 31 8 7 6 5 4 3 2 1 0 a b c d e f g h Data Organization in Data Registers VOTERA For Mold jetorimatien On This Product ee Go to www freescale com Data Organization and add k RG EH AA Remiconductor Inc 2 2 2 Address Registers Each address register and stack pointer is 32 bits wide and holds a 32 bit address Address registers cannot be used for byte sized operands Therefore when an address register is used as a source operand either the low order word or the entire long word operand is used depending upon the operation size When an address register is used as the destination operand the entire register is affected regardless of the operation size If the source operand is a word size it is first sign extended to 32 bits and then used in the operation to an address register destination Address registers are used primarily for addresses and to support address computation The instruction set includes instructions that add to subtract from compare and move the contents of address registers The following example shows the organization of addresses in address registers 31 16 15 0 Sign Extended 16 Bit Address Operand A A AA A A AA el Full 32 Bit Address Operand Address Organization in Address Registers 2 2 3 Control Registers The control registers described in this section contain control information for s
43. S4 S0 S2 po XC e LX AA Ny rr a NA E RESET AA AS lt gt lt RESET INTERNAL RESUME NORMAL Lin 512 CLOCKS OPERATION Figure 7 65 Processor Generated Reset Operation IDE For More Information On This Product eee Go to www freescale com
44. SP destination PC NOP none none PC 2 gt PC Returns RTD d 16 SP PC SP 4 d SP RTR none none SP gt CCR SP 2 gt SP SP gt PC SP 4 gt SP RTS none none SP gt PC SP 4 5 SP Letters cc in the integer instruction mnemonics Bcc DBcc and Scc specify testing one of the following conditions CC Carry clear GE Greater or equal LS Lower or same PL Plus CS Carry set GT Greater than LT Less than T Always true EQ Equal HI Higher MI Minus VC Overflow clear E Never true LE Less or equal NE Not equal VS Overflow set Not applicable to the Bcc instructions MOTOROLA Go to www freescale com For More eee On llus Product s Instruction Set Summary Freescale Semiconductor Inc 3 2 9 System Control Instructions Privileged instructions trapping instructions and instructions that use or modify the condition code register CCR provide system control operations Table 3 9 summarizes these instructions The TRAPcc instruction uses the same conditional tests as the corresponding program control instructions All of these instructions cause the processor to flush the instruction pipe Table 3 9 System Control Operations Instruction Operand Syntax Operand Size Operation Privileged data SR 16 immediate data A SR gt SR data SR immediate data x SR SR ea SR source gt SR SR ea SR de
45. The PFLUSH instructions flush the address translation caches ATCs and can optionally select only nonglobal entries for flushing PTEST performs a search of the address translation tables storing results in the MMU status register and loading the entry into the ATC Table 3 10 summarizes these instructions Table 3 10 MMU Instructions Instruction Operand Syntax Operand Size Operation PFLUSHA none none Invalidate all ATC entries PFLUSHA N none none Invalidate all nonglobal ATC entries PFLUSH An none Invalidate ATC entries at effective address PFLUSH N An none Invalidate nonglobal ATC entries at effective address PTEST An none Information about logical address MMU status register 3 2 11 Multiprocessor Instructions The TAS CAS and CAS instructions coordinate the operations of processors in multiprocessing systems These instructions use read modify write bus cycles to ensure uninterrupted updating of memory Coprocessor instructions control the coprocessor operations Table 3 11 lists these instructions Table 3 11 Multiprocessor Operations Read Modify Write Instruction Operand Syntax OperandSize Operation Read Modify Write CAS Dc Du ea 8 16 32 destination Dc gt CC if Z then Du gt destination else destination gt Dc CAS2 Dc1 Dc2 Du1 Du2 8 16 32 dual operand CAS Rn Rn Tas a 8 l destination 0 set condition codes 1 destination 7
46. a burst operation that is deferred because the entire operand does not correspond to the same cache line Figure 7 41 shows a burst operation aborted by CIIN Because CBACK corresponds to the next cycle three long words are transferred even though CBACK is only asserted for two clock periods The burst operation sequence begins with states S0 S3 which are very similar to those states for a synchronous read cycle except that CBREQ is asserted S4 S9 perform the final three reads for a complete burst operation State 0 The burst operation starts with SO The processor drives ECS low indicating the beginning of an external cycle When the cycle is the first cycle of a read operation OCS is driven low at the same time During SO the processor places a valid address on A0 A31 and valid function codes on FCO FC2 The function codes select the address space for the cycle The processor drives R W high indicating a read cycle and drives DBEN inactive to disable the data buffers SIZ0 SIZ1 become valid indicating the number of operand bytes to be transferred CIOUT also becomes valid indicating the state of the MMU Cl bit in the address translation descriptor or in the appropriate TTx register State 1 One half clock later in S1 the processor asserts AS to indicate that the address on the address bus is valid The processor also asserts DS during S1 CBREQ is also asserted indicating that the MC68030 can perform a burst operat
47. accesses are mixed it is possible to see multiple successive ECS assertions on the external bus if the processor is hitting in both caches and if the bus controller is free Note that if the bus controller is executing other cycles these aborted cycles due to cache hits may not be seen externally Also OCS is asserted for the first external cycle of an operand transfer Therefore in the case of a misaligned data transfer where the first portion of the operand results in a cache hit but the bus controller did not begin an external cycle and then abort it and the second portion in a cache miss OCS is asserted for the second portion of the operand NOR For mo IRALA Product ae Go to www freescale com Bus Operation Freescale Semiconductor Inc e LMD e LLD e e e e UD A0 A1 SIZO e UUD UPPER UPPER DATA 32 BIT PORT UMD UPPER MIDDLE DATA 32 BIT PORT LMD LOWER MIDDLE DATA 32 BIT PORT SIZ1 e LLD LOWER LOWER DATA 32 BIT PORT UD UPPER DATA 16 BIT PORT gt LD LOWER DATA 16 BIT PORT RAW NOTE These select lines can be combined with the address decode circuitry or all can be generated within the same programmed array logic unit Figure 7 18 Byte Data Select Generation for 16 and 32 Bit Ports qo For MUS RA USOS BANAL Product MOTOROLA Go to www freescale
48. and OP3 The single byte of a byte length operand is OP3 These designations are used in the figures and descriptions that follow MOTOROLA For More iniormatiar ion on This Product d Go to www freescale com Bus Operation Freescale Semiconductor Inc 31 0 LONG WORD OPERAND oro OP1 OP2 OP3 15 0 WORD OPERAND OP2 OP3 7 0 BYTE OPERAND OP3 Figure 7 3 Internal Operand Representation Figure 7 4 shows the required organization of data ports on the MC68030 bus for 8 16 and 32 bit devices The four bytes shown in Figure 7 4 are connected through the internal data bus and data multiplexer to the external data bus This path is the means through which the MC68030 supports dynamic bus sizing and operand misalignment Refer to 7 2 2 Misaligned Operands for the definition of misaligned operand The data multiplexer establishes the necessary connections for different combinations of address and data sizes The multiplexer takes the four bytes of the 32 bit bus and routes them to their required positions For example OPO can be routed to D24 D31 as would be the normal case or it can be routed to any other byte position to support a misaligned transfer The same is true for any of the operand bytes The positioning of bytes is determined by the size SIZO and SIZ1 and address A0 and A1 outputs The SIZO and SIZ1 outputs indicate the remaining number of bytes to be transferred during the current bus cycle as shown in Table 7 2 The
49. arte praes 6 4 6 1 2 Data Cache PP LA IAEA A 6 6 6 1 2 1 Write AllOCanon aae ewe Kad RS sese Ra Ode a che LA 6 8 6 1 2 2 Read Modify Write Accesses 00 2000 cee eee 6 10 6 1 3 Cache PI e Eon 22b bu sh pe eee ere iei ee a Se 6 10 6 1 3 1 Single Entry Mode ps eed Reet ce sede ae REN 6 10 6 1 3 2 Burst Mode Filling dak hp nd Dede doo oet tar bd EN 6 15 6 2 Cache Reset cud aos Cia eA ce O ee Mee ce re at 6 20 6 3 Gache Control ad ese dee vt SS DR etes ee ER ER Edd 6 20 6 3 1 Cache Control Register sesos spas pa vU a 6 20 6 3 1 1 Write Allocate iesta nha soos Bethe Se ULE Boek ode dr EA 6 21 6 3 1 2 Data Burst Enable es uomo ors dee ct o ao ga ral enr orar E ee a 6 21 6 3 1 3 Clear Data Gabi ada lidia da 6 21 6 3 1 4 Clear Entry in Data Cache imi pk eee sees ae ee 6 21 6 3 1 5 Freeze Data Cache xi kasi ee Showa a ka eee ade ee 6 22 6 3 1 6 Enable Data Gaelic exu dpa ated ta a veces aera Ok Bee gues Rie ees 6 22 6 3 1 7 Instruction Burst Enable aa a e m whe RE 6 22 6 3 1 8 Clear Instruction Cache 0 6 22 6 3 1 9 Clear Entry in Instruction Cache a 6 22 6 3 1 10 Freeze Instruction Cache 0 000 c eee eee 6 23 6 3 1 11 Enable Instruction Cache a estais kot tia Rex mE HANNA 6 23 6 3 2 Cache Address Register 2 cece eee eee eee 6 23 Section 7 Bus Operation 7 1 Bus Transfer SIQMAlS s Lue pira tado eb Rg ak een Bd 7 1 7 1 1 BUS Control ola llores De Yee oet metes 7 3 7 1 2 Address
50. data cache reduces the number of external bus cycles when the data operand required by an instruction is already in the data cache Performance is enhanced further because the on chip caches can be internally accessed in a single clock cycle In addition the bus controller provides a two clock cycle synchronous mode and burst mode accesses that can transfer data in as little as one clock per long word The MC68030 enhanced microprocessor contains an on chip MMU that allows address translation to operate in parallel with the CPU core the internal caches and the bus controller Additional signals support emulation and system analysis External debug equipment can disable the on chip caches and the MMU to freeze the MC68030 internal state during breakpoint processing In addition the MC68030 indicates The start of a refill of the instruction pipe Instruction boundaries Pending trace or interrupt processing BS Xd N Exception processing 5 Halt conditions This status and control information allows external debugging equipment to trace the MC68030 activity and interact nonintrusively with the MC68030 to effectively reduce system debug effort 1 3 PROGRAMMING MODEL The programming model of the MC68030 consists of two groups of registers the user model and the supervisor model This corresponds to the user and supervisor privilege levels User programs executing at the user privilege level use the registers of the user model
51. error occurs during the first cycle of a burst the data is ignored the entire cache line is marked invalid and the burst operation is aborted If the cycle is for an instruction fetch a bus error exception is made pending This bus error is processed only if the execution unit attempts to use either of the two words latched during the bus cycle If the cycle is for a data fetch the bus error exception is taken immediately Refer to Section 11 Instruction Execution Timing for more information about pipeline operation NEC For mo ARIA RIN DANHA Product n Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2 Sw Sw Sw Sw S3 S0 S2 WRITE WITH BUS ERROR ASSERTED INTERNAL 3 STACK WRITE PROCESSING Figure 7 51 Late Bus Error with STERM Exception Taken When a bus error occurs after the burst mode has been entered that is on the second access or later the processor terminates the burst operation and the cache entry corresponding to that cycle is marked invalid but the processor does not take an exception see Figure 7 52 If the second cycle is for a portion of a misaligned operand fetch the processor runs another read cycle for the second portion with CBREQ negated as shown in Figure 7 53 If BERR is asserted again the MC68030 then takes an exception The MC68030 supports late bus errors during a burst fill operation the timing is the same relative to STERM and the clock as for a lat
52. for modes that do not use registers EFFECTIVE ADDRESS x MODE REGISTER X Figure 2 3 Single Effective Address Many instructions imply the addressing mode for one of the operands The formats of these instructions include appropriate fields for operands that use only one addressing mode Se For More informatio ion a YANYAL Product MOTOROLA Go to www freescale com Freescale Semiconductor dne Addressing Capabilities The effective address field may require additional information to fully specify the operand address This additional information called the effective address extension is contained in an additional word or words and is considered part of the instruction Refer to 2 5 Effective Address Encoding Summary for a description of the extension word formats The notational conventions used in the addressing mode descriptions in this section are EA Effective address An Address register n Example A3 is address register 3 Dn Data register n Example D5 is data register 5 Xn SIZE SCALE Denotes index register n data or address the index size W for word L for long word and a scale factor 1 2 4 or 8 for no word long word or quad word scaling respectively PC The program counter dn Displacement value n bits wide bd Base displacement od Outer displacement L Long word size W Word size Identify an indirect address in a register
53. function code signals are valid while AS is asserted At the beginning of a bus cycle the size signals SIZO and SIZ1 are driven along with ECS and the FCO FC2 SIZO and SIZ1 indicate the number of bytes remaining to be transferred during an operand cycle consisting of one or more bus cycles or during a cache fill operation from a device with a port size that is less than 32 bits Table 7 2 shows the encoding of SIZO and SIZ1 These signals are valid while AS is asserted The read write R W signal determines the direction of the transfer during a bus cycle This signal changes state when required at the beginning of a bus cycle and is valid while AS is asserted R W only transitions when a write cycle is preceded by a read cycle or vice versa The signal may remain low for two consecutive write cycles The read modify write cycle signal RMC is asserted at the beginning of the first bus cycle of a read modify write operation and remains asserted until completion of the final bus cycle of the operation The RMC signal is guaranteed to be negated before the end of state 0 for a bus cycle following a read modify write operation 7 1 2 Address Bus The address bus signals A0 A31 define the address of the byte or the most significant byte to be transferred during a bus cycle The processor places the address on the bus at the beginning of a bus cycle The address is valid while AS is asserted 7 1 3 Address Strobe AS is a timing sig
54. if the processor finds the required program or data item in an on chip cache if a miss occurs in the address translation cache ATC of the memory management unit MMU or if the MMU finds a fault with the access the processor aborts the cycle before asserting AS ECS can be used to initiate various timing sequences that are eventually qualified with AS Qualification with AS may be required since in the case of an internal cache hit an ATC miss or an MMU fault a bus cycle may be aborted after ECS has been asserted The assertion of AS ensures that the cycle has not been aborted by these internal conditions During the first external bus cycle of an operand transfer the operand cycle start OCS signal is asserted with ECS When several bus cycles are required to transfer the entire operand OCS is asserted only at the beginning of the first external bus cycle With respect to OCS an operand is any entity required by the execution unit whether a program or data item The function code signals FCO FC2 are also driven at the beginning of a bus cycle These three signals select one of eight address spaces refer to Table 4 1 to which the address applies Five address spaces are presently defined Of the remaining three one is reserved MOTOROLA For More datori atrar ion on This Product P Go to www freescale com Bus Operation Freescale Semiconductor Inc for user definition and two are reserved by Motorola for future use The
55. ion a YANYAL Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bus Operation LONG WORD OPERAND REGISTER OP3 CACHE ENTRIES DATA BUS j D31 D16 WORD MEMORY MC68EC030 MEMORY CONTROL MSB LSB SIZ1 SIZO M A0 A0 DSACK1 DSACKO 0 0 0 0 1 L H 1 1 0 1 0 L H 0 1 1 0 0 L H 1 0 1 1 0 L H Figure 7 11 Misaligned Cachable Long Word Transfer from Word Port Example WORD OPERAND DATA BUS WORD MEMORY MC68030 MEMORY CONTROL MSB LSB SIZi SIZO A2 Al AO DSACKi DSACKO 1 0 0 0 1 L H 0 1 0 10 L H Figure 7 12 Misaligned Word Transfer to Word Port Example MOTOROLA For Mo NAO USER On Tus P Product TIT Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2 S4 S0 S2 S4 IN 7 ss SIZ1 au se SIZO RW ECS a e DSACK1 N N DSACKO D31 D24 OP2 OP3 D23 D16 OP2 OP3 D15 D8 OP3 OP3 D7 D0 OP2 OP3 WORD WRITE BYTE WRITE 3 X WORD OPERAND WRITE TO A1 A0 01 9 Figure 7 13 Misaligned Word Transfer to Word Port ine For More Information On This Product ad Go to www freescale com Freescale Semiconductor Inc Bus Operation Figures 7 15 and 7 16 show an example of a long word transfer to an odd address in long word organized memory In this example a long word access is attempted beginning at the least significant byte of a long word organized memory Only one byt
56. or low that they repre sent The audience of this manual includes systems designers systems programmers and applications programmers Systems designers need some knowledge of all sections with particular emphasis on Sections 1 5 6 7 13 14 and Appendix A Designers who implement a coprocessor for their system also need a thorough knowledge of Section 10 MOTOROLA For Mo matias ion On AUS Product me Go to www freescale com Freescale Semiconductor Inc Systems programmers should become familiar with Sections 1 2 3 4 6 8 9 11 and Appendix A Applications programmers can find most of the information they need in Sections 1 2 3 4 9 11 12 and Appendix A From a different viewpoint the audience for this book consists of users of other M68000 Family members and those who are not familiar with these microprocessors Users of the other family members can find references to similarities to and differences from the other Motorola microprocessors throughout the manual However Section 1 and Appendix A specifically identify the MC68030 within the rest of the family and contrast its differences ann For Mare formation Un This Product MOTOBOLA Go to www freescale com Paragraph Number h h ll ll 00 40000 Oi n 2 5 MOTOROLA Freescale Semiconductor Inc TABLE OF CONTENTS Title Section 1 Introduction BEIC iis wie clon Pa oan Wane TCR MC68030 Extensions to the M68000 Family
57. read modify write sequence but can cause system integrity problems if used improperly The alternate bus master must guarantee the integrity of the read modify write sequence by not altering the contents of memory locations accessed by the read modify write sequence Note that for the method to operate properly AS must be observed to be negated high on two consecutive clock edges before the alternate bus master takes the bus Waiting for this condition ensures that any current or pending bus activity has completed or has been pre empted Hot For MUS RA USOS BANAL Product MOTOR Go to www freescale com Bus Operation Freescale Semiconductor Inc lt SEE NOTE gt DO NOT TAKE BUS gt CLK BGACK lt gt AD NOTE The alternate bus master must sample AS high on two consecutive rising edges of the clock after BGACK is recognized low before taking the bus Figure 7 62 Single Wire Bus Arbitration Timing Diagram A timing diagram of the bus arbitration sequence during a processor bus cycle is shown in Figure 7 60 The bus arbitration sequence while the bus is inactive i e executing internal operations such as a multiply instruction is shown in Figure 7 63 7 8 RESET OPERATION RESET is a bidirectional signal with which an external device resets the system or the processor resets external devices When power is applied to the system external circuitry should assert RESET for a minim
58. signals the dynamic bus sizing capabilities of the MC68030 are available In addition the minimum cycle time for these cycles is also three clocks To support those systems that use the system clock to generate DSACKx and other asynchronous inputs the asynchronous input setup time parameter 47A and the asynchronous input hold time parameter 47B are given If the setup and hold times are met for the assertion or negation of a signal such as DSACKx the processor can be guaranteed to recognize that signal level on that specific falling edge of the system clock If the assertion of DSACKx is recognized on a particular falling edge of the clock valid data is latched into the processor for a read cycle on the next falling clock edge provided the data meets the data setup time parameter 27 In this case parameter 31 for asynchronous operation can be ignored The timing parameters referred to are described in MC68030EC D MC68030 Electrical Specifications If a system asserts DSACKx for the required window around the falling edge of S2 and obeys the proper bus protocol by maintaining DSACKx and or BERR HALT until and throughout the clock edge that negates AS with the appropriate asynchronous input hold time specified by parameter 47B no wait states are inserted The bus cycle runs at its maximum speed three clocks per cycle for bus cycles terminated with DSACKx is For More Information Un This Product UNE C Go to www freescale
59. su 11 5 Memory Management Unit 00 0c eee eee 11 6 Instruction Execution Timing Calculations 11 6 Instruction Cache Case 222i ves oie cee ee ead BS SES 11 6 Overlap and Best Case 000 eee 11 7 Average No Cache Case 22 0c eee ee eee 11 8 Actual Instruction Cache Case Execution Time Calculations 11 11 Effect of Dala Cache oco EL su mts ot bac la nts 11 16 Effect ot Wait States d ds oet ur ru ect oe ated owes 11 18 Instruction Timing Tables x cecilia dret ee eke hans 11 24 Fetch Effective Address fea ooooooooooooo 11 26 Fetch Immediate Effective Address fiea 11 28 Calculate Effective Address cea 11 30 Calculate Immediate Effective Address ciea 11 32 Jump Effective Address 00 e eee eee ee 11 35 MOVE Instruction Er Spe bars wr ete eh IAN REPAS 11 37 Special Purpose Move Instruction llle 11 39 Arithmetical Logical Instructions o ooooooooo o 11 40 Immediate Arithmetical Logical Instructions 11 42 Binary Coded Decimal and Extended Instructions 11 43 single Operand Instructions host dy e NAG BA T ERIS 11 44 Shift Rotate Instructions e siria Stee ah Se eet 11 45 Bit Manipulation Instructions eie eae Bee RETE 11 46 Bit Field Manipulation InstructiONS oooooooooooo 11 47 Conditional Branch Instructions
60. target address space for every bus cycle with the function code signals according to the type of access required In addition to distinguishing between supervisor user and program data the processor can identify special processor cycles such as the interrupt acknowledge cycle and the memory management unit can control accesses and translate addresses appropriately Table 4 1 lists the types of accesses defined for the MC68030 and the corresponding values of function codes FCO FC2 Table 4 1 Address Space Encodings FC2 FC1 FCO Address Space 0 0 0 Undefined Reserved 0 0 User Data Space 0 1 0 User Program Space 0 1 1 Undefined Reserved 1 0 0 Undefined Reserved 1 0 1 Supervisor Data Space 1 1 0 Supervisor Program Space 1 1 1 CPU Space Address space 3 is reserved for user definition whereas 0 and 4 are reserved for future use by Motorola The memory locations of user program and data accesses are not predefined Neither are the locations of supervisor data space During reset the first two long words beginning at memory location zero in the supervisor program space are used for processor initialization No other memory locations are explicitly defined by the MC68030 A function code of 7 FC2 FC0 111 selects the CPU address space This is a special address space that does not contain instructions or operands but is reserved for special processor functions The processor uses a
61. the negation of AS or DS whichever it detects first The device must remove its data and negate DSACKx within approximately one clock period after sensing the negation of AS or DS DSACKx signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle MOTOROLA For Mol4Qp3030 USER ion On AUS Product Up Go to www freescale com Bus Operation Freescale Semiconductor Inc 7 3 2 Asynchronous Write Cycle During a write cycle the processor transfers data to memory or a peripheral device Figure 7 24 is a flowchart of a write cycle operation for a long word transfer The following figures show the functional write cycle timing diagrams specified in terms of clock periods Figure 7 25 shows two write cycles between two read cycles with no idle time for a 32 bit port Figure 7 26 shows byte and word write cycles to a 32 bit port Figure 7 27 shows a long word write cycle to an 8 bit port Figure 7 28 shows a long word write cycle to a 16 bit port CONTROLLER EXTERNAL DEVICE ADDRESS DEVICE 1 ASSERT ECS OCS FOR ONE HALF CLOCK 2 DRIVE ADDRESS ON A31 A0 3 DRIVE FUNCTION CODE ON FC2 FCO 4 DRIVE SIZE SIZ1 SIZ0 FOUR BYTES 5 SET RW TO WRITE 6 CACHE INHIBIT OUT CIOUT BECOMES VALID 7 8 9 0 ASSERT ADDRESS STROBE AS ASSERT DATA BUFFER ENABLE DBEN DRIVE DATA LINES D31 DO ACCEPT DATA ASSERT DATA STROBE DS 1 DECODE ADDRSS 2 STORE DATA FROM D31 D0 3 ASSERT DATA TRANSFER A
62. the next clock cycle case 6 The memory controller can then correct the RAM prior to or during the automatic retry 7 5 1 Bus Errors The bus error signal can be used to abort the bus cycle and the instruction being executed BERR takes precedence over DSACKx or STERM provided it meets the timing constraints described in MC68030EC D MC68030 Electrical Specifications If BERR does not meet these constraints it may cause unpredictable operation of the MC68030 If BERR remains asserted into the next bus cycle it may cause incorrect operation of that cycle When the bus error signal is issued to terminate a bus cycle the MC68030 may enter exception processing immediately following the bus cycle or it may defer processing the exception The instruction prefetch mechanism requests instruction words from the bus controller and the instruction cache before it is ready to execute them If a bus error occurs on an instruction fetch the processor does not take the exception until it attempts to use that instruction word Should an intervening instruction cause a branch or should a task switch occur the bus error exception does not occur di For MUSEU USER S MANYAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bus Operation The bus error signal is recognized during a bus cycle in any of the following cases DSACKx or STERM and HALT are negated and BERR is asserted HALT and BERR are negated and DSACKx
63. the sign extended contents of the index register possibly scaled The user must specify the displacement the address register and the index register in this mode GENERATION EA An XN dg dg An Xn SIZE SCALE ASSEMBLER SYNTAX 110 MODE n REGISTER An 31 0 ADDRESS REGISTER gt MEMORY ADDRESS is Lu d DISPLACEMENT Lo SIGNEXTENDED _ INTEGER 31 0 INDEX REGISTER 7 0 SCALE SCALE VALUE 31 0 MEMORY ADDRESS OPERAND NUMBER OF EXTENSION WORDS 1 vitia For Mare formation Un This Product IA Go to www freescale com Freescale Semiconductor dne Addressing Capabilities 2 4 8 Address Register Indirect with Index Base Displacement Mode This addressing mode requires an index register indicator and an optional 16 or 32 bit sign extended base displacement The index register indicator includes size and scaling information The operand is in memory The address of the operand is the sum of the contents of the address register the scaled contents of the sign extended index register and the base displacement In this mode the address register the index register and the displacement are all optional If none is specified the effective address is zero This mode provides a data register indirect address when no address register is specified and the index register is a data register Dn GENERATION EA An Xn bd ASSEMBLER SYNTAX bd An Xn SIZE SCALE MODE 110 REGISTER n 31 0 31 0
64. to www freescale com Freescale Semiconductor Inc cio Set Summary The next code see Figure 3 3 fragment shows the use of a CAS2 instruction to delete an element from a linked list The first LEA instruction loads the effective address of HEAD into A0 The MOVE instruction loads the address in pointer HEAD into DO The TST instruction checks for an empty list and the BEQ instruction branches to a routine at label SDEMPTY if the list is empty Otherwise a second LEA instruction loads the address of the NEXT pointer in the newest element on the list into A1 and the following MOVE instruction loads the pointer contents into D1 The CAS2 instruction compares the address of the newest structure to the value in HEAD and the address in D1 to the pointer in the address in A1 If no element has been inserted or deleted by another routine while this routine has been executing the results of these comparisons are equal and the CAS instruction stores the new value into location HEAD If an element has been inserted or deleted the CAS2 instruction loads the new address in location HEAD into DO and the BNE instruction branches to the TST instruction to try again SDELETE LEA HEAD A0 LOAD ADDRESS OF HEAD POINTER INTO A0 MOVEL A0 DO MOVE VALUE OF HEAD POINTER INTO DO SDLOOP TSTL DO CHECK FOR NULL HEAD POINTER BEQ SDEMPTY IF EMPTY NOTHING TO DELETE LEA NEXT DO A1 LOAD ADDRESS OF FORWARD LINK INTO A1 MOVE L A1 D1 PUT FORWARD LINK VALUE IN
65. to address 08 then 0C and last 00 This addressing is compatible with existing nibble mode dynamic RAMs and can be supported by page and static column modes with an external modulo 4 counter for A2 and A3 UNABLE TO LOCATE ART Figure 6 12 Burst Filling Wraparound Example The MC68030 does not assert CBREQ during the first portion of a misaligned access if the remainder of the access does not correspond to the same cache line Figure 6 13 shows an example in which the first portion of a misaligned access is at address 0F With a 32 bit port the first access corresponds to the cache entry at address 0C which is filled using a single entry load operation The second access at address 10 corresponding to the second cache line requests a burst fill and the processor asserts CBREQ During this burst operation long words 10 14 18 and 1C are all filled in that order UNABLE TO LOCATE ART Figure 6 13 Deferred Burst Filling Example MOTOROLA For Mo matias ion On AUS Product 6 13 Go to www freescale com On Chip Cache Memories Freescale Semiconductor Inc The processor does not assert CBREQ if any of the following conditions exist The appropriate cache is not enabled Burst filling for the cache is not enabled The cache freeze bit for the appropriate cache is set The current operation is the read portion of a read modify write operation The MMU has inhibited caching for the current page The
66. to be transferred with an address offset A2 A0 of 010 The next two bytes are transferred during this cycle The processor then initiates the third cycle with the size signals indicating one byte remaining to be transferred The address offset A2 A0 is now 100 the port latches the final byte and the operation is complete Figure 7 10 shows the associated bus transfer signal timing Figure 7 11 shows the equivalent operation for a cachable data read cycle Figures 7 12 and 7 13 show a word transfer to an odd address in word organized memory This example is similar to the one shown in Figures 7 9 and 7 10 except that the operand is word sized and the transfer requires only two bus cycles Figure 7 14 shows the equivalent operation for a cachable data read cycle 31 LONG WORD OPERAND 0 D31 DATA BUS D16 WORD MEMORY MC68EC030 MEMORY CONTROL SIZ1 SIZO Al A0 A0 DSACK1 DSACKO 0 0 0 0 1 L H 1 1 0 1 0 L H 0 1 1 0 0 L H Figure 7 9 Misaligned Long Word Transfer to Word Port Example MOTOROLA For Mo matias ion On AUS Product JAS Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2 S4 S0 S2 S4 S0 S2 S4 IN YOON o O SIZO RW A AA DS DSACK1 N N N DBEN N N N BYTE WRITE WORD WRITE BYTE WRITE 93 ag LONG WORD OPERAND WRITE Figure 7 10 Misaligned Long Word Transfer to Word Port Aao For MACRO USER
67. vector number supplied in an autovector operation is derived from the interrupt level of the current interrupt When AVEC is asserted instead of DSACK or STERM during an interrupt acknowledge cycle the MC68030 ignores the state of the data bus and internally generates the vector number the sum of the interrupt level plus 24 18 There are seven distinct autovectors that can be used corresponding to the seven levels of interrupt available with signals IPLO IPL2 Figure 7 45 shows the timing for an autovector operation NOR For mo RISLEY Product mm Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2 S4 S0 S2 S4 S0 S2 ECS LE DO IEEE LT uu Paro gt iPEND KS TA mg READ CYCLE INTERRUPT y lug WRITE STACK ACKNOWLEDGE Figure 7 44 Interrupt Acknowledge Cycle Timing pa For MS ORO USERS MANYAL Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bus Operation eeo KN c r a GEN PIU egg so JN RW o 2 N PEP A OF IPL2 IPLO X lA _ _ _ __n AVEC INTERRUPT READ CYCLE ACKNOWLEDGE 5 4 WRITE STACK AUTOVECTORED Figure 7 45 Autovector Operation Timing NOR For mo IRALA Product ae Go to www freescale com Bus Operation Freescale Semiconductor Inc 7 4 1 3 SPURIOUS INTERRUPT CYCLE When a device does not respond to an interrupt acknowledge cycle with AVEC STERM or DSACKx the external logic
68. 0 otherwise HEAD contains the address of the element most recently added to the list The code fragment shown in Figure 3 2 illustrates the code for inserting an element The MOVE instructions load the address in location HEAD into DO and into the NEXT pointer in the element being inserted and the address of the new element into D1 The CAS instruction stores the address of the inserted element into location HEAD if the address in HEAD remains unaltered If HEAD contains a new address the instruction loads the new address into DO and branches to the second MOVE instruction to try again The CAS2 instruction is similar to the CAS instruction except that it performs two comparisons and updates two variables when the results of the comparisons are equal If the results of both comparisons are equal CAS2 copies new values into the destination addresses If the result of either comparison is not equal the instruction copies the values in the destination addresses into the compare operands SINSERT ALLOCATE NEW ENTRY ADDRESS IN A1 MOVE L HEAD DO MOVE HEAD POINTER VALUE TO DO SILOOP MOVE L DO NEXT A1 ESTABLISH FORWARD LINK IN NEW ENTRY MOVE L A1 D1 MOVE NEW ENTRY POINTER VALUE TO D1 CAS L DO D1 HEAD IF WE STILL POINT TO TOP OF STACK UPDATE THE HEAD POINTER BNE SILOOP IF NOT TRY AGAIN BEFORE INSERTING AN ELEMENT NEW HEAD E E AFTER INSERTING AN ELEMENT Figure 3 2 Linked List Insertion is For MUS RA USOS BANAL Product Moreno Go
69. 0000 moa ONO geweoNEMODNG fo wee XX LSENPONNABER O O 0000000 Of me X A f cru sace NN tye _ _ CC Ey mm BERR FINEM MM HALT vo YY BREAKPOINT FETCHED pa READ CYCLE ra ACKNOWLEDGE 3 INSTRUCTION INSTRUCTION WORD EXECUTION FETCH Figure 7 47 Breakpoint Acknowledge Cycle Timing PS For Mare formation Un this Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Bus Operation S0 S2 Sw Sw Sw S4 S0 S2 S4 e A woes XX sam XX pW HALT INTERNAL lt READ WITH BUS ERROR ASSERTED gt lt PROCESSING gt lt STACK WRITE Figure 7 48 Breakpoint Acknowledge Cycle Timing Exception Signaled Another signal that is used for bus exception control is HALT This signal can be asserted by an external device for debugging purposes to cause single bus cycle operation or in combination with BERR a retry of a bus cycle in error NOR For mo IRALA Product m Go to www freescale com Bus Operation Freescale Semiconductor Inc To properly control termination of a bus cycle for a retry or a bus error condition DSACKx BERR and HALT can be asserted and negated with the rising edge of the MC68030 clock This assures that when two signals are asserted simultaneously the required setup time 47A and hold time 47B for both of them is met for the same falling edge of the processor clock Refer to MC68030EC D MC68030 Elec
70. 00000 BYTE 00000001 BYTE 00000002 BYTE 00000003 LONG WORD 00000004 WORD 00000004 WORD 00000006 BYTE 00000004 BYTE 00000005 BYTE 00000006 BYTE 00000007 LONG WORD FFFFFFFC WORD FFFFFFFC WORD FFFFFFFE BYTE FFFFFFFC BYTE FFFFFFFD BYTE FFFFFFFE BYTE SFFFFFFFF Figure 2 1 Memory Operand Address PE For IC ORO USERS MANYAL product MOTOROLA Go to www freescale com Freescale Semicondygtorsdnsiu Addressing Capabilities BIT DATA 7 0 7 017 0 7 0 Brren 1 76 5 4 2 0 BYIEn 1 BYTEn 42 TE BASE ADDRESS BIT NUMBER BIT FIELD DATA BASE BIT 7 017 0 7 0 BYTE n 1 BYTE n OFFSET OFFSET gt WIDTH gt 324 012 BASE ADDRESS BYTE INTEGER DATA 7 017 017 017 0 BYTEn 1 MSB BYTEn LSB BYTE n 1 BYTE n 2 ADDRESS WORD INTEGER DATA 7 017 017 017 0 7 0 BYTEn 1 WORD INTEGER BYTEn 2 BYTEn 43 ADDRESS 7 0 7 017 017 017 0 7 0 BYTEn 1 LONG WORD INTEGER BYTEn 4 ADDRESS ADDRESS QUAD WORD DATA 0 7 7 0 BYTE n 1 BYTEn 8 PACKED BINARY CODED DATA 7 017 413 0 7 0 7 0 BYTE n 1 MSD LSD BYTEn 1 BYTE n 2 ADDRESS UNPACKED BINARY CODED DATA BYTE n 1 BYTE n 2 ADDRESS XX USER DEFINED VALUE Figure 2 2 Memory Data Organization MOTOROLA For Mo matias ion On AUS Product Go to www freescale com 2 7 Data Organization and Add kRG SHAME
71. 1 N LONG WORD 3 BYTE WORD BYTE SIZO N RW ECS N N N N OCS N CIOUT N DSACK1 DSACKO N D31 D24 oro OP1 OP OP3 oo jp vso yA D7 D0 T ooo BYTE READ aa BYTE READ x BYTE READ Pa BYTE READ 3 r LONG WORD OPERAND READ FROM 8 BIT PORT gt Figure 7 22 Long Word Read 8 Bit Port with CIOUT Asserted iia For More Information On This Product TR Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2 S4 S0 S2 S4 S0 S2 S4 Al X A0 SIZ1 N LONG WORD WORD LONG WORD SIZO DSACK1 DSACKO DBEN D31 D24 oro y OP2 OPO D23 D16 OP1 OP3 OP1 D15 D8 OP2 D7 DO OP3 WORD READ o WORD READ LONG WORD READ gt FROM 32 BIT PORT LONG WORD OPERAND READ FROM 16 BIT PORT gt Figure 7 23 Long Word Read 16 Bit and 32 Bit Port is For More Information Un This Product UNE Go to www freescale com Freescale Semiconductor Inc Bus Operation State 1 One half clock later in state 1 S1 the processor asserts AS indicating that the address on the address bus is valid The processor also asserts DS also during S1 In addition the ECS and OCS if asserted signal is negated during S1 State 2 During state 2 S2 the processor asserts DBEN to enable external data buffers The selected device uses R W SIZO SIZ1 AO A1 CIOUT and DS to place its information on the data b
72. 1 10 31 10 31 10 32 10 32 10 33 10 33 10 33 10 34 10 35 10 36 10 37 10 40 10 40 10 41 10 42 10 43 10 46 10 48 10 49 10 50 10 50 10 52 10 52 10 55 10 56 10 58 10 60 10 61 10 61 10 62 10 63 10 63 10 64 10 64 10 65 10 65 10 68 10 69 10 69 10 70 xxxiii Paragraph Number 10 5 2 6 10 5 2 7 10 5 2 8 10 5 3 10 6 11 1 11 2 11 2 1 11 2 2 11 2 3 11 2 4 11 2 5 11 2 5 1 11 2 5 2 11 2 5 3 11 2 6 11 3 11 3 1 11 3 2 11 3 3 11 3 4 11 4 11 5 11 6 11 6 1 11 6 2 11 6 3 11 6 4 11 6 5 11 6 6 11 6 7 11 6 8 11 6 9 11 6 10 11 6 11 11 6 12 11 6 13 11 6 14 11 6 15 Xxxiv Freescale Semiconductor Inc TABLE OF CONTENTS Continued Page Title Number IMSS a tee Puer AA ds 10 71 Format EROESS La ad n ace ha Anar eo OS ep ios ates Oe 10 71 Address and Bus ETORRI 10 72 Coprocessor Hesel as Led OR AA ed 10 72 Coprocessor SUMMANY 23 5 mama rds toe Pada ma one opens 10 72 Section 11 Instruction Execution Timing Performance Tradeoffs xev rve ua 11 1 Resource SCheduIN 77 2 3 ma eee Sed ate i n part os Eke KANA 11 2 Mittosequenter o ener Bamba BAAL tk eto E EIER 11 2 NSTUCHON PIDE sustratos ATA AA 11 2 Instruction Cache es vain sa 11 4 Data Cabe elle ds a td of coe E a eE 11 4 Bus Controller Resources ooococccccoocoo 11 4 Instruction Fetch Pending Buffer o o o ooo 11 5 Write Pending Buffer lt 3a arpa 11 5 Micro Bus Controller euer tee Ref eere rita
73. 1 DECODE ADDRESS 2 PLACE DATA ON D31 D0 3 ASSERT SYNCHRONOUS TERMINATION STERM 4 ACQUIRE DATA ASSERT CACHE BURST ACKNOWLEDGE CBACK 1 SAMPLE CACHE INHIBIT IN CIIN AND CACHE BURST ACKNOWLEDGE CBACK 2 LATCH DATA TERMINATE CYCLE 1 REMOVE DATA FROM D31 D0 2 NEGATE STERM IF NECESSARY 3 NEGATE CBACK IF NECESSARY WHEN 4 LONG WORDS TRANSFERRED UNTIL 4 LONG WORDS TRANSFERRED END OF BURST 1 NEGATE AS AND DS 2 NEGATE DBEN START NEXT CYCLE Figure 7 37 Burst Operation Flowchart Four Long Words Transferred not to be cached CIIN must be asserted at the same time as STERM The assertion of IIN also has the effect of aborting the burst operation em For IC ORO USERS MANYAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bus Operation S0 S1 S2 Sw Sw Sw Sw Sw Sw SI Sw Sw S4 S5 Sw Sw S6 S7 Sw Sw S8 S9 CLK A31 A4 X A3 A2 A0 FC2 FCO X SIZ1 SIZO R W CIOUT CBREQ N CBACK DBEN 01 10 11 00 VALUE OF A3 A2 INCREMENTED BY THE SYSTEM HARDWARE Figure 7 38 Long Word Operand Request from 07 with Burst Request and Wait Cycle MOTOROLA For More Information Un This Albroduct 19 Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2 S4 S6 CLK A3 N A2 A0 uU a FC2 FCO X SIZ1 SIZO VALUE OF CBACK eee hae CONTROL NEXT CYCLE VALUE OF A3 A2 INCREMENTED BY THE SYSTEM
74. 14 is a 32 bit register that can be written or read by the MOVEC instruction or indirectly modified by a reset Five of the bits 4 0 control the instruction cache six other bits 13 8 control the data cache Each cache is controlled independently of the other although a similar operation can be performed for both caches by a single MOVEC instruction For example loading a long word in which bits 3 and 11 are set into the CACR clears both caches Bits 31 14 and 7 5 are reserved for Motorola definition They are currently read as zeros and are ignored when written For future compatibility writes should not set these bits 31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000000000000000000 WA DBE CD CED FD ED 0 0 0 IBE Cl CEl Fl EI WA Write Allocate DBE Data Burst Enable CD Clear Data Cache CED Clear Entry in Data Cache FD Freeze Data Cache ED Freeze Data Cache IBE Instruction Burst Enable CI Clear Instruction Cache CEI Clear Entry in Instruction Cache Fl Freeze Instruction Cache El Enable Instruction Cache Figure 6 14 Cache Control Register VOTERA For Mole A nton On this Product one Go to www freescale com On Chip Cache Memories Freescale Semiconductor Inc 6 3 1 1 WRITE ALLOCATE Bit 13 the WA bit is set to select the write allocation mode refer to 6 1 2 1 Write Allocation for write cycles Clearing this bit selects the no write allocation mode A reset operation clears this bit The supervi
75. 2 12 Example Two Clock Read and Write Memory Bank 12 13 Example PAL Equation for Two Clock Read and Write Memory Bank 12 14 Example 2 1 1 1 Burst Mode Memory Bank at 20 MHz 256K Bytes 12 15 Example 3 1 1 1 Pipelined Burst Mode Memory Bank at 20 MFIZ 256K BIOS sii nere s EO RC PR arua gra Sra ns 12 16 Additional Memory Enable Circuits llli ee eee 12 17 Example MC68030 Hardware Configuration with External Physical Cache scort e ERE uve RR RT qoe bee 12 18 Example Early Termination Control Circuit o o oo ooo 12 19 Normal Instruction Boundaries 2 000 0 eee eee eee 12 20 Trace or Interrupt Exception 0 002 e eee eee 122211 Other EXCBDIOLDIS Soi edt ent eke hoe aa wes ad eae eee was 2225 Processor Halted pitsas 244 G meri eee andl oe e REESE 12 23 Trace Interface Circuit 7222421625 26 sos mie ee ees Pee Ep REIS 12 24 PAL Pin DEfNtion a era ne atu xr CE ad 12 25 Logic Equations s eoo te tec ipe da teak LAGA RSEN ban xlii MC68030 USER S MANUAL For More Information On This Product Go to www freescale com Page Number MOTOROLA Freescale Semiconductor Inc LIST OF TABLES Page Number ome Number 1 1 Addressing MOdBS esa hubs d E ERO RORIS BANA NARE 1 11 1 2 Instruction Set ana 255 4c o rect donc Poeti BR RU ec rb doe bod equ tr 1 13 2 1 IS I IS Memory Indirection Encodings sells 2 22 3 1 Data Movement Operations
76. 32 bit MC68020 MC68030 microprocessors are shown in Figure 2 15 Notice the encoding for SCALE used by the MC68020 MC68030 is a compatible extension of the M68000 architecture A value of zero for SCALE is the same encoding for both extension words hence software that uses this encoding is both upward and downward compatible across all processors in the product line However the other values of SCALE are not found in both extension formats thus while software can be easily migrated in an upward compatible direction only nonscaled addressing is supported in a downward fashion If the MC68000 were to execute an instruction that encoded a scaling factor the scaling factor would be ignored and not access the desired memory address The earlier microprocessors have no knowledge of the extension word formats implemented by newer processors while they do detect illegal instructions they do not decode invalid encodings of the extension words as exceptions 2 8 OTHER DATA STRUCTURES Stacks and queues are widely used data structures The MC68030 implements a system stack and also provides instructions that support the use of user stacks and queues 2 8 1 System Stack Address register seven A7 is used as the system stack pointer SP Any of the three system stack registers is active at any one time The M and S bits of the status register determine which stack pointer is used When S 0 indicating user mode user privilege level the user s
77. 32 bits CIIN must be asserted at the same time as STERM In addition the state of CBACK is latched when STERM is recognized Since CIIN CBACK and STERM are synchronous signals they must meet the synchronous input setup and hold times for all rising edges of the clock while AS is asserted If STERM is negated at the beginning of S2 wait states are inserted after S2 and STERM is sampled on every rising edge thereafter until it is recognized Once STERM is recognized data is latched on the next falling edge of the clock corresponding to the beginning of S3 State 3 The processor negates AS DS and DBEN during S3 It holds the address valid during S3 to simplify memory interfaces R W SIZO SIZ1 and FCO FC2 also remain valid throughout S3 The external device must keep its data asserted throughout the synchronous hold time for data from the beginning of S3 The device must remove its data within one clock after asserting STERM and negate STERM within two clocks after asserting STERM otherwise the processor may inadvertently use STERM for the next bus cycle 7 3 5 Synchronous Write Cycle A synchronous write cycle is terminated differently from an asynchronous write cycle and the data strobe may not be useful Otherwise the cycles assert and respond to the same signal in the same sequence STERM is asserted by the external device to terminate a synchronous write cycle The discussion of STERM in the preceding s
78. 6 For Mars formation Un This Product MOTOBOLA Go to www freescale com Freescale Semiconductor Inc Bus Operation CONTROLLER EXTERNAL DEVICE LOCK BUS 1 ASSERT READ MODIFY WRITE CYCLE RMC START INPUT TRANSFER ASSERT ECS OCS FOR ONE HALF CLOCK DRIVE R W TO READ DRIVE FUNCTION CODE ON FC2 FCO DRIVE ADDRESS ON A31 A0 DRIVE SIZE SIZ1 SIZ0 CACHE INHIBIT OUT CIOUT BECOMES VALID ASSERT ADDRESS STROBE AS ASSERTDATASTROBE DS PRESENT DATA ASSERT DATA BUFFER ENABLE DBEN 1 DECODE ADDRESS 2 PLACE DATA ON D31 D0 3 ASSERT SYNCHRONOUS TERMINATE INPUT TRANSFER TERMINATION STERM SAMPLE CACHE INHIBIT IN CIIN 1 2 LATCHDATA IF CAS2 INSTRUCTION 3 NEGATE AS AND DS AND ONLY ONE OPERAND 4 NEGATE DBEN READ THEN GO TO A 5 START DATA MODICIATION TERMINATE CYCLE IF OPERANDS DO NOT MATCH THE 1 REMOVE DATA FROM D31 D0 2 NEGATE STERM START OUTPUT TRANSFER 1 ASSERT ECS OCS FOR ONE HALF CLOCK 2 SET R W TO WRITE 3 DRIVE ADDRESS ON A31 A0 IF DIFFERENT 4 DRIVE SIZE SIZ1 SIZO 5 CIOUT BECOMES VALID 6 7 8 9 ASSERT AS ASSERT DBEN PLACE DATA ON D31 D0 ASSERT DS IF WAIT STATES ACCEPT DATA 1 DECODE ADDRESS 2 STORE DATA FROM D31 DO TERMINATE OUTPUT TRANSFER 3 ASSERT STERM D e a IF CAS2 INSTRUCTION 1 NEGATE AS AND DS AND ONLY ONE 2 REMOVE DATA FROM D31 D0 OPERAND 3 NEGATE DBEN TERMINATE CYCLE WRITTEN THEN GO TO
79. 7 4 3 Coprocessor Communication Cycles The MC68030 coprocessor interface provides instruction oriented communication between the processor and as many as seven coprocessors The bus communication required to support coprocessor operations uses the MC68030 CPU space with a type field of 2 Coprocessor accesses use the MC68030 bus protocol except that the address bus supplies access information rather than a 32 bit address The CPU space type field A16 A19 for a coprocessor operation is 2 A13 A15 contain the coprocessor identification number CpID and AO A4 specify the coprocessor interface register to be accessed Coprocessor accesses to a CpID of zero correspond to MMU instructions and are not generated by the MC68030 as a result of the coprocessor interface These cycles can only be generated by the MOVES instruction Refer to Section 10 Coprocessor Interface Description for further information d For More Information Un This Product UTER C Go to www freescale com Freescale Semiconductor Inc Bus Operation CONTROLLER EXTERNAL DEVICE BREAKPOINT ACKNOWLEDGE 1 SET RAW TO READ 2 SET FUNCTION CODE TO CPU SPACE 3 PLACE CPU SPACE TYPE 0 ON A19 A16 4 PLACE BREAKPOINT NUMBER ON A4 A2 5 8 SET SIZE TO WORD 1 PLACE REPLACEMENT OPCODE ON DATA ASSERT ADDRESS STROBE AS AND DATA BUS STROBE DS 2 ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE DSACKx SYNCHRONOUS TERMINATION STERM IF DSACKx OR STERM oneer 1 LATCH
80. 8 Long Word Operand Request from 07 with Burst Request and Wait Cycle 0 eee eee eee 7 39 Long Word Operand Request from 07 with Burst Request CBACK Negated Early 2000 0005 7 40 Long Word Operand Request from 0E Burst Fill Deferred 7 41 Long Word Operand Request from 07 with Burst Request CBACK and CIIN Asserted 7 42 MC68030 CPU Space Address Encoding 00 0055 7 43 Interrupt Acknowledge Cycle Flowchart eee 7 44 Interrupt Acknowledge Cycle Timing eee eee eee 7 45 Autovector Operation Timing 2c eee eee eee eee 7 46 Breakpoint Operation Flow 0000 eee 7 47 Breakpoint Acknowledge Cycle Timing llle 7 48 Breakpoint Acknowledge Cycle Timing Exception Signaled 7 49 Bus Error without DGACKX pana Kaka kh awe at e ER PY mE Etat ete 7 50 Late Bus Error with DBACKx 000 cee eee 7 51 Late Bus Error with STERM Exception Taken 7 52 Long Word Operand Request Late BERR on Third Access 7 53 Long Word Operand Request BERR on Second Access 7 54 Asynchronous Late Retryz s ossis senate tees ALAALA ica 7 55 Synchronous Late ROI v vetus gere vea ee v tre e ERES 7 56 Late Retry Operation for a Burst a 7 57 Halt Operation Timing co make Jat bene pein ad oe ur t om foe Cae cae 7 58 Bus Synchronization Example
81. A For More Information On This Product Go to www freescale com Paragraph Number 10 1 10 1 1 10 1 2 10 1 3 10 1 4 10 1 4 1 10 1 4 2 10 1 4 3 10 2 10 2 1 10 2 1 1 10 2 1 2 10 2 2 10 2 2 1 10 2 2 1 1 10 2 2 1 2 10 2 2 2 10 2 2 2 1 10 2 2 2 2 10 2 2 3 10 2 2 3 1 10 2 2 3 2 10 2 2 4 10 2 2 4 1 10 2 2 4 2 10 2 3 10 2 3 1 10 2 3 2 10 2 3 2 1 10 2 3 2 2 10 2 3 2 3 10 2 3 2 4 10 2 3 3 10 2 3 3 1 10 2 3 3 2 10 2 3 4 10 2 3 4 1 10 2 3 4 2 10 3 10 3 1 10 3 2 10 3 3 xxxii Freescale Semiconductor Inc TABLE OF CONTENTS Continued Page Hie Number Inga diee D A ated beads Bese 10 1 Interface FEATURES arica Gina dna RA Lire ee bots equ e 10 2 Concurrent Operation Support eee eee eee 10 3 Coprocessor Instruction Format ooo occcocoooo 10 4 Coprocessor System Interface ooo occococooooo o 10 5 Coprocessor Classification llli 10 5 Processor Coprocessor Interface 10 6 Coprocessor Interface Register Selection 10 8 Coprocessor Instruction Types is kap ha a ada 10 9 Coprocessor General InstructiONS oooooooooooo 10 9 FON soa derit ee dete Ges tig Boa A EO hat et ne ae Sass aes 10 10 ETOLODOL 25 2 3 Ana tie A e S d pace pon sh ht epi i oL 10 11 Coprocessor Conditional Instructions 10 12 Branch On Coprocessor Condition Instruction 10 13 A NA SANG Ronee ents es BOAT
82. AS2 instruction moves the address of the new element into both LIST PUT and LIST GET assuming that both of these pointers still contain zero If not the BNE instruction branches to the TST instruction at label DILOOP to try again This time the BEQ instruction does not branch and the following MOVE instruction moves the address in DO to the NEXT pointer of the new element The CLR instruction clears register D1 to zero and the MOVE instruction moves the zero into the LAST pointer of the new element The LEA instruction loads the address of the LAST pointer of the most recently inserted element into register A1 Assuming the LIST PUT pointer and the pointer in At have not been changed the CAS instruction stores the address of the new element into these pointers The code fragment to delete an element from a doubly linked list is similar see Figure 3 5 The first two instructions load the effective addresses of pointers LIST PUT and LIST GET into registers AO and A1 respectively The MOVE instruction at label DDLOOP moves the LIST GET pointer into register D1 The BEQ instruction that follows branches out of the routine when the pointer is zero The MOVE instruction moves the LAST pointer of the element to be deleted into register D2 Assuming this is not the last element in the list the Z condition code is not set and the branch to label DDEMPTY does not occur The LEA instruction loads the address of the NEXT pointer of the element at the addr
83. AT on 10 14 Protocol cu its as We ah ES a es a Oe ae bE bud 10 15 Set On Coprocessor Condition Instruction 10 15 FOLITISL c ieee ANAN RANG nen O td ut ose i Me ea 10 15 Protocol 25952773 T i Wh ab pas Ta AND A Bera B aru Boa roto oe TG sd ie 10 16 Test Coprocessor Condition Decrement and Branch Instruction 10 17 EOI c rer tr eoe A oa ese ae a RE dad 10 17 A PAA 10 18 Trap On Coprocessor Conditi0N o oo oooooo 10 18 Formati a EA 10 18 a A AA AE RSA 10 19 Coprocessor Save and Restore Instructions 10 20 Coprocessor Internal State Frames 10 20 Coprocessor Formal Words ss estaa a 10 22 Empty Reset Format Word ooooccccocccccoc oo 10 22 Not Ready Format Word o 10 23 Invalid Format Word a nn da di a 10 23 Valid Format Word ace pd decirse ax Eme 8 73 NA Pert 10 24 Coprocessor Context Save Instruction 10 24 OUI Ab aka ERES 10 24 PIOIDGOl e un ses oink tah East er eia NS Ushcaeth Re tS 10 25 Coprocessor Context Restore Instruction 10 27 Format Su to a Gras Seas ute ere prese gone rater eut cu feit pA Me 10 27 Protocol iat iso cte edo ii dez dd eie dus cd 10 28 Coprocessor Interface Register Set 10 29 Response OI o hah se ciue kaaa baka ta br Ba tet de ee iet 10 29 Comolli PA 10 30 Save CPG TTE 10 30 MC68030 USER S MANUAL MOTOROLA For More Information On This Product Go to www f
84. BCLR Z Dn BFTST BFCHG BFSET 0 0 N Dm BFCLR Z DmADM 1A ADO BFEXTS BFEXTU BFFFO 0 O N Sm Z SmASm 1A AS0 BFINS 0 0 N Dm Z Dm ADWN 1 A ADO ASL ies eee V Dm A Dm 1 V V Dm r V Dm A Dm 1 V Dm r C Dm r 1 ASL R 0 1 10 0 LSL ROXL e 10 2 C Dm 1 1 LSR r 0 1 1 0 0 ROXL r 0 0 2 C X ROL 0 2 C Dm 1 ROL r 0 0 0 ASR LSR ROXR 1 QO C Dr 1 ASR LSR r 0 ojo ROXR r 0 0 2 C X ROR 0 C Dr 1 ROR r 0 0 0 Not Affected Rm Result Operand Most Significant Bit U Undefined Result Meaningless R Register Tested Other See Special Definition n Bit Number General Case r Shift Count X C LB Lower Bound N Rm UB Upper Bound Z RmA ARO Boolean AND Sm Destination Operand Most Significant Bit V Boolean OR Dm Destination Operand Most Significant Bit Rm NOT Rm 1 M ANUAL MOTOROLA oe For MALE US RR Wa NIA Product Hone Go to www freescale com Freescale Semiconductor INC struction Set Summary 3 3 2 Conditional Tests Table 3 13 lists the condition names encodings and tests for the conditional branch and set instructions The test associated with each condition is a logical formula using the current states of the condition codes If this formula evaluates to one the condition is true If the formula e
85. BUST bie Ges AN Sas SER BT o et ee AS 7 4 7 1 3 Address AA e ale dod ere aia 7 4 7 1 4 Data Bus gt kaanak sc a x hoe Meee amd A E EE ete hae NG a i See 7 5 7 1 5 Data OIODB Lu qv cence AA A APA 7 5 7 1 6 Data Buffer Enable d iure al ete eis Na ed uth aoe RC t 7 5 7 1 7 Bus Cycle Termination Signals ooooooooooo o 7 5 7 2 Data Transfer Mechanism 0 0c cece ee eee eee 7 6 7 2 1 Dynamic BUS SI ci el esas 7 6 xxviii MC68030 USER S MANUAL MOTOROLA For More Information On This Product Go to www freescale com Paragraph Number 7 2 2 7 2 3 7 2 4 7 2 5 7 2 6 7 2 7 7 2 8 7 2 9 7 2 10 7 3 7 3 1 7 3 2 7 3 3 7 3 4 7 3 5 7 3 6 7 3 7 7 4 7 4 1 7 4 1 7 4 1 7 4 1 7 4 2 7 4 3 7 5 7 5 1 7 5 2 7 5 3 7 5 4 7 6 7 7 7 7 1 7 7 2 7 7 3 7 7 4 7 8 ON 8 1 8 1 1 8 1 2 MOTOROLA Freescale Semiconductor Inc TABLE OF CONTENTS Continued Misaligned Operands 0000 eee ees Effects of Dynamic Bus Sizing and Operand Misalignment Address Size and Data Bus Relationships MC68030 versus MC68020 Dynamic Bus Sizing Cache Filling 65 consta E EIER 6 teases ae eee eens Cache Interactions 35 Eee eee koh deL ve toh ovine Asynchronous ODGOFABlOL edo ce os ewe oe ee ener awe Synchronous Operation with DBACKx o o oooooooooo Synchronous Operation with STERM Data Transfer Cycles caera cis bee bie ve ays deer
86. CR ORI data CCR to CCR ORI If supervisor state ORI data SR to SR then Source V SR gt SR else TRAP PACK Source Unpacked BCD adjustment Destintion PACK Ax Ay adjustment Packed BCD PACK Dx Dy adjustment PEA Sp 4 gt SP ea gt SP PEA ea PFLUSH If supervisor state then invalidate instruction and data ATC entries for destination address else TRAP PLOAD If supervisor state then entry gt ATC else TRAP PMOVE If supervisor state then Source gt MRn or MRn gt Destination PTEST If supervisor state then logical address status MMUSR entry gt ATC else TRAP RESET If supervisor state RESET then Assert RSTO Line else TRAP ROL ROR Destination Rotated by count gt Destination ROd Rx Dy ROd data Dy ROd ea ROXL Destination Rotated with X by count Destination ROXd Dx Dy ROXR ROXd data Dy ROXd ea A 3 23 META For Mo matias ion VORAUS Product Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc Table 3 14 Instruction Set Summary Concluded Opcode Operation Syntax RTD SP PC SP 4 d gt SP RTD displacement RTE If supervisor state RTE then SP gt SR SP 2 gt SP SP gt PC SP 4 gt SP restore state and deallocate stack according to SP else TRAP RTM Reload Saved Module State from Stack RTM Rn RTR SP gt CCR SP 25 SP RTR
87. Cycles three clocks minimum Synchronous Bus Cycles two clocks minimum and Burst Data Transfers one clock minimum all to the Physical Address Space Dynamic Bus Sizing Supports 8 16 32 Bit Memories and Peripherals Support for Coprocessors with the M68000 Coprocessor Interface e g Full IEEE Floating Point Support Provided by the MC68881 MC68882 Floating Point Coproces sors 4 Gbyte Logical and Physical Addressing Range Implemented in Motorola s HCMOS Technology That Allows CMOS and HMOS High Density NMOS Gates to be Combined for Maximum Speed Low Power and Optimum Die Size Processor Speeds Beyond 20 MHz improved performance and increased functionality result from the on chip implementation of the MMU and the data and instruction caches The enhanced bus controller and the internal parallelism also provide increased system performance Finally the improved bus interface the reduction in physical size and the lower power consumption combine to reduce system costs and satisfy cost performance goals of the system designer MOTOROLA For Mo matias ion On AUS Product is Go to www freescale com idiroduction Freescale Semiconductor Inc 1 2 MC68030 EXTENSIONS TO THE M68000 FAMILY In addition to the on chip instruction cache present in the MC68020 the MC68030 has an internal data cache Data that is accessed during read cycles may be stored in the on chip cache where it is available for subsequent accesses The
88. D NORMALLY When the MC68030 processes an interrupt exception it performs an interrupt acknowledge cycle to obtain the number of the vector that contains the starting location of the interrupt service routine Some interrupting devices have programmable vector registers that contain the interrupt vectors for the routines they use The following paragraphs describe the interrupt acknowledge cycle for these devices Other interrupting conditions or devices cannot supply a vector number and use the autovector cycle described in 7 4 1 2 Autovector Interrupt Acknowledge Cycle The interrupt acknowledge cycle is a read cycle It differs from the asynchronous read cycle described in 7 3 1 Asynchronous Read Cycle or the synchronous read cycle described in 7 3 4 Synchronous Read Cycle in that it accesses the CPU address space Specifically the differences are 1 FCO FC2 are set to seven FCO FC1 FC2 111 for CPU address space 2 A1 A2 and A3 are set to the interrupt request level the inverted values of IPLO iPL1 and IPL2 respectively 3 The CPU space type field A16 A19 is set to F the interrupt acknowledge code 4 A20 A31 A4 A15 and AO are set to one The responding device places the vector number on the data bus during the interrupt acknowledge cycle Beyond this the cycle is terminated normally with either STERM or DSACKx Figure 7 43 is the flowchart of the interrupt acknowledge cycle dc For More Information Un This Produ
89. DBEN N N D23 D16 OP1 OP3 m WORD WRITE ge WORD WRITE 3 lt LONG WORD OPERAND WRITE TO 16 BIT PORT 3 Figure 7 6 Long Word Operand Write Timing 16 Bit Data Port Figure 7 7 shows a word transfer to an 8 bit bus port Like the preceding example this example requires two bus cycles Each bus cycle transfers a single byte The size signals for the first cycle specify two bytes for the second cycle one byte Figure 7 8 shows the associated bus transfer signal timing ie For Mare formation Un This Product IA Go to www freescale com Freescale Semiconductor Inc Bus Operation 15 WORD OPERAND 0 OP2 OP3 D31 DATABUS D24 BYTE MEMORY MC68EC030 MEMORY CONTROL SIZ1 SIZO A1 A0 DSACK1 DSACKO 1 OP2 0 0 0 H L 0 1 0 1 H L OP3 Figure 7 7 Example of Word Transfer to Byte Port 7 2 2 Misaligned Operands Since operands may reside at any byte boundaries they may be misaligned A byte operand is properly aligned at any address a word operand is misaligned at an odd address a long word is misaligned at an address that is not evenly divisible by four The MC68000 MC68008 and MC68010 implementations allow long word transfers on odd word boundaries but force exceptions if word or long word operand transfers are attempted at odd byte addresses Although the MC68030 does not enforce any alignment restrictions for data operands including PC relative data addresses some performance degradati
90. EGISTER W L SCALE 0 DISPLACEMENT Full Format Extension Word s 15 14 12 11 10 9 8 7 6 5 4 3 2 0 D A REGISTER W L SCALE 1 BS IS BD SIZE 0 IS BASE DISPLACEMENT 0 1 OR 2 WORDS OUTER DISPLACEMENT 0 1 OR 2 WORDS Field Definition Field Definition Instruction BS Base Register Suppress Register General Register Number 0 Base Register Added Extensions 1 Base Register Suppressed Register Index Register Number Is Index Suppress D A Index Register Typ 0 Evaluate and Add Index 0 Dn Operand 1 An 1 Suppress Index Operand W L Word Long Word Index Size BD SIZE Base Displacement Size 0 Sign Extended Word 00 Reserved 1 Long Word 01 Null Displacement Scale Scale Factor 10 Word Displacement 00 1 11 Long Displacement 01 2 I IS Index Indirect Selection 10 4 Indirect and Indexing Operand 11 8 Determined in Conjunction with Bit 6 Index Suppress Figure 2 4 Effective Address Specification Formats Effective address modes are grouped according to the use of the mode They can be classified as follows Data A data addressing effective address mode is one that refers to data operands Memory A memory addressing effective address mode is one that refers to memory operands Alterable An alterable addressing effective address mode is one that refers to alterable writable operands Control A control addressing effective address mode is one that refers to memory operan
91. FORE DELETING ENTRY LIB UN LIST PUT LIST GET m Pagan LIST GET DELETED ENTRY Figure 3 5 Doubly Linked List Deletion AFTER DELETING ENTRY LIST PUT 3 5 2 Nested Subroutine Calls The LINK instruction pushes an address onto the stack saves the stack address at which the address is stored and reserves an area of the stack Using this instruction in a series of subroutine calls results in a linked list of stack frames The UNLK instruction removes a stack frame from the end of the list by loading an address into the stack pointer and pulling the value at that address from the stack When the operand of the instruction is the address of the link address at the bottom of a stack frame the effect is to remove the stack frame from the stack and from the linked list s For MUS RA USOS BANAL Product Moreno Go to www freescale com Freescale Semiconductor Inc cio set Summary 3 5 3 Bit Field Operations One data type provided by the MC68030 is the bit field consisting of as many as 32 consecutive bits A bit field is defined by an Ole from an effective address and a width value The offset is a value in the range of 2 through 2 1 from the most significant bit bit 7 at the effective address The width is a positive number 1 32 The most significant bit of a bit field is bit 0 the bits number in a direction opposite to the bits of an integer The instruction set includes eight instructions that have bit field oper
92. Figure 6 9 is a read of a misaligned long word operand from devices that return 16 bit DSACKx encodings The processor accepts the first portion of the operand the word from address 06 and requests a word from address 04 to fill the cache entry Next the processor reads the word at address 08 the second portion of the operand and stores it in the cache also Finally the processor accesses the word at 0A to fill the second long word cache entry UNABLE TO LOCATE ART Figure 6 9 Single Entry Mode Operation Misaligned Long Word and 16 Bit Port Two read cycles are required for a misaligned long word operand transfer from devices that return 32 bit DBACKx encodings As shown in Figure 6 10 the first read cycle requests the long word at address 06 and latches the long word at address 04 The second read cycle requests and latches the long word corresponding to the second cache entry at address 08 Two read cycles are also required if S TERM is used to indicate a 32 bit port instead of the 32 bit DSACKx encoding UNABLE TO LOCATE ART Figure 6 10 Single Entry Mode Operation Misaligned Long Word and 32 Bit DSACKx Port If all bytes of a long word are cachable CIIN must be negated for all bus cycles required to fill the entry If any byte is not cachable CIIN must be asserted for all corresponding bus cycles The assertion of the CIIN signal prevents the caches from being updated during read cycles Write cycles includin
93. For example the processor attempts to stack several words containing information about the state of the machine while processing a bus error exception If a bus error exception occurs during the stacking operation the second error is considered a double bus fault Only an external reset operation can restart a halted processor However bus arbitration can still occur refer to 7 7 Bus Arbitration The MC68030 indicates that a double bus fault condition has occurred by continuously asserting the STATUS signal until the processor is reset The processor asserts STATUS for one two or three clock periods to signal other microsequencer status indications Refer to Section 12 Applications Information for a description of the interpretation of the STATUS signal A second bus error or address error that occurs after exception processing has completed during the execution of the exception handler routine or later does not cause a double bus fault A bus cycle that is retried does not constitute a bus error or contribute to a double bus fault The processor continues to retry the same bus cycle as long as the external hardware requests it 22 For MUS RA USOS BANAL Product MOTOR Go to www freescale com Bus Operation Freescale Semiconductor Inc 7 6 BUS SYNCHRONIZATION The MC68030 overlaps instruction execution that is during bus activity for one instruction instructions that do not use the external bus can be executed Due to the independ
94. Freescale Semiconductor Inc MOTOROLA MC68030 ENHANCED 32 BIT MICROPROCESSOR USER S MANUAL Third Edition MOTOROLA INC 1992 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PREFACE The MC68030 User s Manual describes the capabilities operation and programming of the MC68030 32 bit second generation enhanced microprocessor The manual consists of the following sections and appendix For detailed information on the MC68030 instruction set refer to M68000PM AD M68000 Family Programmer s Reference Manual Section 1 Introduction Section 2 Data Organization and Addressing Capabilities Section 3 Instruction Set Summary Section 4 Processing States Section 5 Signal Description Section 6 On Chip Cache Memories Section 7 Bus Operation Section 8 Exception Processing Section 9 Memory Management Unit Section 10 Coprocessor Interface Description Section 11 Instruction Execution Timing Section 12 Applications Information Section 13 Electrical Characteristics Section 14 Ordering Information and Mechanical Data Appendix A M68000 Family Summary Index NOTE In this manual assertion and negation are used to specify forc ing a signal to a particular state In particular assertion and as sert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level high
95. Frequencies Less Than or Equal to the CPU Maximum Frequency Rating 12 4 Microsequencer STATUS Indications 12 5 RISTO Pals osas a rede dar ATA ana or 12 6 AS and ECSC Indicates edo EE ARNAN ADA NAY 12 7 Voc and GND Pin Assignments aaa xliv MC68030 USER S MANUAL For More Information On This Product Go to www freescale com Page Number MOTOROLA Freescale Semiconductor Inc SECTION 1 INTRODUCTION The MC68030 is a second generation full 32 bit enhanced microprocessor from Motorola The MC68030 is a member of the M68000 Family of devices that combines a central processing unit CPU core a data cache an instruction cache an enhanced bus controller and a memory management unit MMU in a single VLSI device The processor is designed to operate at clock speeds beyond 20 MHz The MC68030 is implemented with 32 bit registers and data paths 32 bit addresses a rich instruction set and versatile addressing modes The MC68030 is upward object code compatible with the earlier members of the M68000 Family and has the added features of an on chip MMU a data cache and an improved bus interface It retains the flexible coprocessor interface pioneered in the MC68020 and provides full IEEE floating point support through this interface with the MC68881 or MC68882 floating point coprocessor Also the internal functional blocks of this microprocessor are designed to operate in parallel allowing instruction ex
96. Go to www freescale com Bus Operation Freescale Semiconductor Inc N RAW vessen F DSACK1 DSACKO lm E I ae e a cr BERR HATe e oo lt READ gt lt HALT gt X ARBITRATION PERMITTED WHILE THE CONTROLLER IS HALTED Figure 7 57 Halt Operation Timing is For Mars formation Un This Product Go to www freescale com MOTOROLA Bus Operation Freescale Semiconductor Inc When the processor completes a bus cycle with the HALT signal asserted the data bus is placed in the high impedance state and bus control signals are driven inactive not high impedance state the address function code size and read write signals remain in the same state The halt operation has no effect on bus arbitration refer to 7 7 Bus Arbitration When bus arbitration occurs while the MC68030 is halted the address and control signals are also placed in the high impedance state Once bus mastership is returned to the MC68030 if HALT is still asserted the address function code size and read write signals are again driven to their previous states The processor does not service interrupt requests while it is halted but it may assert the IPEND signal as appropriate 7 5 4 Double Bus Fault When a bus error or an address error occurs during the exception processing sequence for a previous bus error a previous address error or a reset exception the bus or address error causes a double bus fault
97. HALT N A 5 STERM NA A Terminate and retry when HALT negated BERR A S HALT A S S 6 STERM A Terminate and retry when HALT negated BERR A HALT A LEGEND N The number of current even bus state e g S2 S4 etc A Signal is asserted in this bus state NA Signal is not asserted in this state X Don t care S Signal was asserted in previous state and remains asserted in this state State N 2 not part of bus cycle EXAMPLE A A system uses a watchdog timer to terminate accesses to an unpopulated address space The timer asserts BERR after timeout case 3 NOR For mo IRALA Product Hs Go to www freescale com Bus Operation Freescale Semiconductor Inc EXAMPLE B A system uses error detection and correction on RAM contents The designer may 1 Delay DSACKx until data is verified assert BERR and HALT simultaneously to indi cate to the processor to automatically retry the error cycle case 5 or if data is valid assert DSACKx case 1 2 Delay DSACKx until data is verified and assert BERR with or without DSACKx if data is in error case 3 This initiates exception processing for software handling of the condition 3 Return DSACKx prior to data verification If data is invalid BERR is asserted on the next clock cycle case 4 This initiates exception processing for software handling of the condition 4 Return DSACKx prior to data verification if data is invalid assert BERR and HALT on
98. HARDWARE NOTES 1 Assertion of CBACK causes data to be placed on D31 DO 2 Continued assertion of CBACK causes data to be placed on D31 DO 3 Negation of CBACK causes AS to be negated Figure 7 39 Long Word Operand Request from 07 with Burst Request CBACK Negated Early s For MUS RA USOS BANAL Product MOTOR Go to www freescale com Freescale Semiconductor Inc Bus Operation S0 Si S2 Sw Sw SI SO S1 S2 Sw Sw SI Sw Sw S4 S5 Sw Sw S6 S7 Sw Sw S8 S9 CLK A31 A5 X ex Cf A3 A1 A0 FC2 FCO X X SIZ1 SIZO DBEN PREVIOUS CACHE BLOCK NEXT CACHE BLOCK START BURST CYCLE ma Figure 7 40 Long Word Operand Request from 0E Burst Fill Deferred NOR For mo IRALA Product ie Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2 S4 CLK A31 A0 X FC2 FCO X SIZ1 SIZO ws f BURST MODE ENDS 01 10 T DATA NOT CACHED VALUE OF A3 A2 INCREMENTED BY THE SYSTEM HARDWARE Figure 7 41 Long Word Operand Request from 07 with Burst Request CBACK and CIIN Asserted fs For MUS ARO USOS UA TIAE Product MOTOR Go to www freescale com Freescale Semiconductor Inc Bus Operation Since CIIN CBACK and STERM are synchronous signals they must meet the synchronous input setup and hold times for all rising edges of the clock while AS is asserted If STERM is negated at the beginning of S2 wait states are inserted afte
99. Insti lobis aces eo carts Sr DD es Ui ete ae cbs ee NG sg 3 6 3 2 4 Shift and Rotate Instructions essi Pep IA REY cur pes 3 7 3 2 5 Bit Manipulation Instructions i25 ho e LES RE 3 8 3 2 6 Bit Field ODSEAtlOlTS 19 sueco sr ee ae BAGA oct iste ode eger KN 3 9 3 2 7 Binary coded Decimal Instructi0NS ooooooooo o 3 10 3 2 8 Program Control Instructions a 29 5 5E Ao 3 11 3 2 9 System Control Instructions 0 00000 cece eee eee 3 12 3 2 10 Memory Management Unit Instructi0NS 3 13 3 2 11 Multiprocessor Instructions liliis 3 13 3 3 Integer Condition Codes 0 00 ccc eee 3 14 3 3 1 Condition Code Computation 2 eee eee 3 15 3 3 2 Conditional TESIS 2 55 vx ae eee hod at se ras 3 17 3 4 Instruction Set Summary s 2422 2 05220 Aees th ted ame ke as 3 18 3 5 Instruction Examples rug ate teres fue ets eredi edo eh ore s 3 25 3 5 1 Using the CAS and CAS2 Instructions 3 25 3 5 2 Nested Subroutine Calls n ananuna a 3 30 3 5 3 Bit Field Operations a ka em tt ee leed ends 3 31 3 5 4 Pipeline Synchronization with the Nop Instruction 3 32 Section 4 Processing States 4 1 Privilege Levels aaa Na Aba AA ds bt hee phen lapina ed 4 2 4 1 1 Supervisor Privilege Level oooooocococooooo o 4 2 4 1 2 User Privilege Level 0 000 eee ees 4 3 4 1 3 Changing Privilege Levels uisus betwee ALA aba 4 4 4 2 Address Sp
100. L L ea Dr Dg32 32 gt 32r 32q EOR Source Destination gt Destination EOR Dn ea EORI Immediate Data Destination gt Destination EORI data ea MOTOROLA ER 3 21 For Mo aeRO US ER MANGA Product Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc Table 3 14 Instruction Set Summary Sheet 3 of 5 Opcode Operation Syntax EORI Source CCR gt CCR EORI data CCR to CCR EORI If supervisor state EORI data SR to SR then Source 6 SR gt SR else TRAP EXG Rx o Ry EXG Dx Dy EXG Ax Ay EXT EXTB Destination Sign Extended Destination EXT W Dn extend byte to word EXT L L Dn extend word to long word EXTB L Dn extend byte to long word ILLEGAL SSP 2 gt SSP Vector Offset 2 SSP SSP 4 gt SSP PC gt SSP SSP 2 gt SSP SR gt SSP Illegal Instruction Vector Address gt PC ILLEGAL Destination Address gt PC LEA LINK SP 4 gt SP PC gt SP Destination Address PC LEA ea An SP 45 SP An SP SP gt An SP d SP LINK An displacement LSL LSR Destination Shifted by count gt Destination LSd Dx Dy LSd data Dy LSd ea MOVE Source gt Destination MOVE ea ea MOVEA Source gt Destination MOVEA ea An MOVE from CCR CCR gt Destination MOVE CCR ea MOVE to CCR Source gt CCR MOVE ea CCR MOVE from SR If supervisor state then SR D
101. LO IPL2 Provides an encoded interrupt level to the processor Interrupt Pending IPEND Indicates that an interrupt is pending Autovector AVEC Requests an autovector during an interrupt acknowledge cycle Bus Request BR Indicates that an external device requires bus mastership Bus Grant BG Indicates that an external device may assume bus mastership Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus mastership Reset HESET System reset Halt HALT Indicates that the processor should suspend bus activity Bus Error BERR Indicates that an erroneous bus operation is being attempted Cache Disable CDIS Dynamically disables the on chip cache to assist emulator support MMU Disable MMUDIS Dynamically disables the translation mechanism of the MMU Pipe Refill REFILL Indicates when the MC68030 is beginning to fill pipeline Microsequencer Status STATUS Indicates the state of the microsequencer Clock CLK Clock input to the processor Power Supply Vcc Power supply Ground GND Ground connection MOTOROLA For Mo matias ion On Tus Product 53 Go to www freescale com Signal Description Freescale Semiconductor Inc 5 2 FUNCTION CODE SIGNALS FC0 FC2 These three state outputs identify the address space of the current bus cycle Table 4 1 shows the relationship of the function code signals to the privilege levels and the address spaces Refer to 4 2 Address Space Types for more information 5 3 ADDRESS BUS A0 A31
102. MMU control register SRP URP TC DTTO DTT1 ITTO ITT1 MMUSR MMU status register specifies a signed integer data type twos complement of byte word or long word single precision real data format 32 bits double precision real data format 64 bits extended precision real data format 96 bits 16 bits unused packed BCD real data format 96 bits 12 bytes any floating point data register FP7 FPO floating point system control register FPCR FPSR or FPIAR a twos complement signed integer 64 to 17 that specifies the format of a number to be stored in the packed BCD format displacement d4g is a 16 bit displacement effective address list of registers for example D3 DO immediate data a literal integer bit field selection assemble program label bit m of an operand bits m through n of operand For Mo matias ion On AUS Product oe Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc X extend X bit in CCR N negative N bit in CCR Z Zero Z bitin CCR V overflow V bit in CCR C carry C bitin CCR arithmetic addition or postincrement indicator arithmetic subtraction or predecrement indicator x arithmetic multiplication arithmetic division or conjunction symbol invert operand is logically complemented A logical AND V logical OR logical exclusive OR Dc data register D7 DO used during compare Du data register D7 DO used duri
103. Miconductor Inc A bit field operand is specified by 1 A base address that selects one byte in memory 2 A bit field offset that indicates the leftmost base bit of the bit field in relation to the most significant bit of the base byte and 3 A bit field width that determines how many bits to the right of the base bit are in the bit field The most significant bit of the base byte is bit field offset 0 the least significant bit of the base byte is bit field offset 7 and the least significant bit of the previous byte in memory is bit offset 1 Bit field offsets may have values in the range of 2 to 2 1 and bit field widths may range between 1 and 32 bits 2 4 ADDRESSING MODES The addressing mode of an instruction can specify the value of an operand with an immediate operand a register that contains the operand with the register direct addressing mode or how the effective address of an operand in memory is derived An assembler syntax has been defined for each addressing mode Figure 2 3 shows the general format of the single effective address instruction operation word The effective address field specifies the addressing mode for an operand that can use one of the numerous defined modes The eaL designation is composed of two 3 bit fields the mode field and the register field The value in the mode field selects one or a set of addressing modes The register field specifies a register for the mode or a submode
104. ND SIZE ACKNOWLEDGE DSACKx 1 TERMINATE OUTPUT TRANSFER 1 NEGATE AS AND DS 2 REMOVE DATA FROM D31 D0 3 NEGATE DBEN TERMINATE CYCLE START NEXT CYCLE Figure 7 24 Asynchronous Write Cycle Flowchart 1 NEGATE DSACKx ba For More information Un This Product UNE Go to www freescale com Freescale Semiconductor Inc Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 Sw Sw S4 ane oT dtp qn e p ES bp UAE EST p se ESI ES E Al A0 N SIZ1 LONG WORD SIZO a X Ne f7 LL c MEME CEN I EN GER QN gt CP n 7 7 N N lt READ gt lt WRITE na WRITE a READ WITH WAIT STATES gt Figure 7 25 Asynchronous Read Write Read Cycles 32 Bit Port State 0 The write cycle starts in SO The processor drives ECS low indicating the beginning of an external cycle When the cycle is the first external cycle of a write operation OCS is driven low at the same time During SO the processor places a valid address on A0 A31 and valid function codes on FCO FC2 The function codes select the address space for the cycle The processor drives R W low for a write cycle SIZO SIZ1 become valid indicating the number of bytes to be transferred CIOUT also becomes valid indicating MOTOROLA For Mon matias ion On AUS Product 183 Go to www freescale com Bus Operation Freescale Semiconductor Inc the state of the MMU CI bit in the address translation descriptor or in the appropriate TTx register i
105. ON A31 A0 DRIVE FUNCTION ON FC2 FCO DRIVE SIZE SIZ1 SIZ0 FOUR BYTES CACHE INHIBIT OUT CIOUT BECOMES VALID ASSERT ADDRESS STROBE AS ASSERT CACHE BURST REQUEST CBREQ IF BURST POSSSIBLE ASSERT DATA STROBE DS ASSERT DATA BUFFER ENABLE DBEN 0 NO O Bb O N PRESENT DATA DECODE ADDRESS PLACE DATA ON D31 DO ASSERT SYNCHRONOUS TERMINATION STERM ACQUIRE DATA ASSERT CACHE BURST ACKNOWLEDGE CBACK 1 SAMPLE CACHE INHIBIT IN CIIN AND CACHE BURST ACKNOWLEDGE CBACK 2 LATCH DATA 3 NEGATE AS AND DS 4 NEGATE DBEN TERMINATE CYCLE 1 REMOVE DATA FROM D31 D0 2 NEGATE STERM START NEXT CYCLE Figure 7 31 Synchronous Long Word Read Cycle Flowchart No Burst Allowed State 0 The read cycle starts with SO The processor drives ECS low indicating the beginning of an external cycle When the cycle is the first cycle of a read operand operation OCS is driven low at the same time During SO the processor places a valid address on A0 A31 and valid function codes on FCO FC2 The function codes select the address space for the cycle The processor drives R W high for a read cycle and drives DBEN inactive to disable the data buffers SIZ1 SIZO become valid indicating the number of bytes to be transferred CIOUT also becomes valid indicating the state of the MMU CI bit in the address translation descriptor or in the appropriate TTx register State 1 One half clock later in S1 the proce
106. ON WORD ONE WORD SPECIFIES OPERATION AND MODES SPECIAL OPERAND SPECIFIERS IF ANY ONE OR TWO WORDS IMMEDIATE OPERAND OR SOURCE EFFECTIVE ADDRESS EXTENSION IF ANY ONE TO SIX WORDS DESTINATION EFFECTIVE ADDRESS EXTENSION IF ANY ONE TO SIX WORDS Figure 3 1 Instruction Word General Format moe For Mold iteration On This Product ai Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc Besides the operation code which specifies the function to be performed an instruction defines the location of every operand for the function Instructions specify an operand location in one of three ways 1 Register Specification A register field of the instruction contains the number of the register 2 Effective Address An effective address field of the instruction contains address mode information 3 Implicit Reference The definition of an instruction implies the use of specific regis ters The register field within an instruction specifies the register to be used Other fields within the instruction specify whether the register selected is an address or data register and how the register is to be used Section 1 Introduction contains register information Effective address information includes the registers displacements and absolute addresses for the effective address mode Section 2 Data Organization and Addressing Capabilities describes the effective address modes in detail C
107. Output High Yes Operand Cycle Start OCS Output Low No External Cycle Start ECS Output Low No Read Write R W Output High Low Yes Read Modify Write Cycle RMC Output Low Yes Address Strobe AS Output Low Yes Data Strobe DS Output Low Yes Data Buffer Enable DBEN Output Low Yes Data Transfer and Size DSACKO Input Low Acknowledge DSACK1 Synchronous Termination STERM Input Low Cache Inhibit In CIIN Input Low Cache Inhibit Out CIOUT Output Low Yes Cache Burst Request CBREQ Output Low Yes Cache Burst Acknowledge CBACK Input Low Interrupt Priority Level TPLO IPL2 Input Low Interrupt Pending IPEND Output Low No Autovector AVEC Input Low Bus Request BR Input Low Bus Grant BG Output Low No Bus Grant Acknowledge BGACK Input Low Reset RESET Input Output Low No Halt HALT Input Low Bus Error BERR Input Low Cache Disable CDIS Input Low MMU Disable MMUDIS Input Low Pipeline Refill REFILL Output Low No Microsequencer Status STATUS Output Low No Clock CLK Input Power Supply VCC Input Ground GND Input For MISA USES UA PHA product MOTOROLA Freescale Semiconductor Inc SECTION 6 ON CHIP CACHE MEMORIES The MC68030 microprocessor includes a 256 byte on chip instruction cache and a 256 byte on chip data cache that are accessed by logical virtual addresses These caches improve performance by reducing external bus activity and increasing instruction throughput Reduced external bus a
108. R For mo IRALA Product ba Go to www freescale com Bus Operation Freescale Semiconductor Inc For STERM the bus cycle terminations are summarized as follows case numbers refer to Table 7 9 Normal Termination STERM is asserted BERR and HALT remain negated case 1 Halt Termination HALT is asserted before STERM and BERR remains negated case 2 Bus Error Termination BERR is asserted in lieu of at the same time or before STERM case 3 or after STERM case 4 and HALT remains negated BERR is negated at the same time or after STERM Retry Termination HALT and BERR are asserted in lieu of at the same time or before STERM case 5 or after STERM case 6 BERR is negated at the same time or after STERM HALT may be negated at the same time or after BERR lt Ce For More information Un This Product UNE C Go to www freescale com Freescale Semiconductor Inc Bus Operation Table 7 9 STERM BERR and HALT Assertion Results Case Control Asserted on Rising No Signal Edge of State Reset N N 2 1 STERM A Normal cycle terminate and continue BERR NA HALT NA 2 STERM NA A Normal cycle terminate and halt Continue when HALT BERR NA NA negated HALT A S S 3 STERM NA A Terminate and take bus error exception possibly BERR A S S deferred HALT NA NA 4 STERM A Terminate and take bus error exception possibly BERR A deferred
109. RY BNE DILOOP IF NOT TRY AGAIN DIDONE SUCCESSFUL LIST ENTRY INSERTION BEFORE INSERTING NEW ENTRY EE p esp A NEW ENTRY LIST PUT LIST GET AFTER INSERTING NEW ENTRY LIST PUT LIST GET X Figure 3 4 Doubly Linked List Insertion When the list contains only one element the routine branches to the CAS2 instruction at label DDEMPTY after moving a zero pointer value into D2 This instruction checks the addresses in LIST PUT and LIST GET to verify that no other routine has inserted another element or deleted the last element Then the instruction moves zero into both pointers and the list is empty VOTERA For Mold jetorimatien On This Product i Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc DDELETE LEA LIST PUT A0 GET ADDRESS OF HEAD POINTER IN A0 LEA LIST GET A1 GET ADDRESS OF TAIL POINTER IN A1 DDLOOP MOVE L A1 D1 MOVE TAIL POINTER INTO D1 BEQ DDDONE F NO LIST QUIT MOVE L LAST D1 D2 PUT BACKWARD POINTER IN D2 BEQ DDEMPTY F ONLY ONE ELEMENT UPDATE POINTERS LEA NEXT D2 A2 PUT ADDRESS OF FORWARD POINTER IN A2 CLR L DO PUT NULL POINTER VALUE IN DO CAS2 L D1 D1 D2 D0 A1 A2 F BOTH POINTERS STILL POINT TO THIS ENTRY UPDATE THEM BNE DDLOOP F NOT TRY AGAI BRA DDDONE DDEMPTY CAS2 L Dt D1 D2 D2 A1 A0 F STILL FIRST ENTRY SET HEAD AND TAIL POINTERS TO NULL BNE DDLOOP F NOT TRY AGAI DDDONE SUCCESSFUL ENTRY DELETION ADDRESS OF DELETED ENTRY IN D1 MAY BE NULL BE
110. SET This bidirectional open drain signal is used to initiate a system reset An external reset signal resets the MC68030 as well as all external devices A reset signal from the processor asserted as part of the RESET instruction resets external devices only the internal state of the processor is not altered Refer to 7 8 Reset Operation for a description of reset bus operation and 8 1 1 Reset Exception for information about the reset exception 5 10 2 Halt HALT The halt signal indicates that the processor should suspend bus activity or when used with BERR that the processor should retry the current cycle Refer to 7 5 Bus Exception Control Cycles for a description of the effects of HALT on bus operations 5 10 3 Bus Error BERR The bus error signal indicates that an invalid bus operation is being attempted or when used with HALT that the processor should retry the current cycle Refer to 7 5 Bus Exception Control Cycles for a description of the effects of BERR on bus operations MOTOROLA For More iniormatiar ion on This Product A Go to www freescale com Signal Description Freescale Semiconductor Inc 5 11 EMULATOR SUPPORT SIGNALS The following signals support emulation by providing a means for an emulator to disable the on chip caches and memory management unit and by supplying internal status information to an emulator Refer to Section 12 Applications Information for more detailed information on emulation supp
111. SIZ1 AO and A1 for the bus cycle The PRn and the Nn bytes correspond to the previous and next bytes in memory respectively that must be valid on the data bus for the specified port size long word or word so that the internal caches operate correctly For cachable accesses the MC68030 assumes that all portions of the data bus for a given port size are valid This same table applies to noncachable read cycles except that the bytes labeled PRn and Nn are not required and can be replaced by don t cares Table 7 2 Size Signal Table 7 3 Address Offset Encoding Encodings SIZ1 SIZO Size A1 A0 Offset 0 1 Byte 0 0 0 Bytes 1 0 Word 0 1 1 Byte 1 1 3 Bytes 1 0 2 Bytes 0 0 Long Word 1 1 3 Bytes weve For More information On This Product pm Go to www freescale com Bus Operation Freescale Semiconductor Inc Table 7 4 Data Bus Requirements for Read Cycles Table did not make it over in the conversion from Word Table 7 5 lists the combinations of SIZO SIZ1 AO and A1 and the corresponding pattern of the data transfer for write cycles from the internal multiplexer of the MC68030 to the external data bus Figure 7 5 shows the transfer of a long word operand to a word port In the first bus cycle the MC68030 places the four operand bytes on the external bus Since the address is long word aligned in this example the multiplexer follows the pattern in the entry of Ta
112. SIZO SIZ1 AO A1 and CIOUT to place its information on the data bus Any or all of the byte sections D24 D31 D16 D23 D8 D15 and DO D7 are selected by SIZO SIZ1 and A0 A1 During S2 the processor drives DBEN active to enable external data buffers In systems that use two clock synchronous bus cycles the timing of DBEN may prevent its use At the beginning of S2 the processor samples the level of STERM If STERM is recognized the processor latches the incoming data If the selected data is not to be cached for the current cycle or if the device cannot supply 32 bits CIIN must be asserted at the same time as STERM Since CIIN and STERM are synchronous signals they must meet the synchronous nput setup and hold times for all rising edges of the clock while AS is asserted If STERM is negated at the beginning of S2 wait states are inserted after 52 and STERM is sampled on every rising edge thereafter until it is recognized Once STERM is recognized data is latched on the next falling edge of the clock corresponding to the beginning of S3 MOTOROLA For Mol4Qp3030 USER ion On AUS Product pes Go to www freescale com Bus Operation Freescale Semiconductor Inc State 3 The processor negates AS DS and DBEN during S3 If more than one read cycle is required to read in the operand s S0 S3 are repeated accordingly When finished with the read cycle the processor holds the address R W and FCO FC2 valid in p
113. T ADDITIONAL PROCESSOR STATE INFORMATION 2 6 12 OR 42 WORDS IF NEEDED Figure 4 1 General Exception Stack Frame VOTERA For Mold jetorimatien On This Product a7 Go to www freescale com Freescale Semiconductor Inc SECTION 5 SIGNAL DESCRIPTION This section contains brief descriptions of the input and output signals in their functional groups as shown in Figure 5 1 Each signal is explained in a brief paragraph with reference to other sections that contain more detail about the signal and the related operations IPLO FUNCTION CODES FC2 FCO PL PE INTERRUPT ADDRESS BUS A31 A0 IPEND CONTROL DATA BUS DI AVEC SIZO ag BB TRANSFER BG BUS ARBITRATION SIZE SIZ1 BGACK CONTROL CEA OCS c RESET ECs HALT BUS EXCEPTION E 4 RAN BERR CONTROL RMC ASYNCHRONOUS AS STERM SYNCHRONOUS BUS CONTROL DS BUS CONTROL DBEN REFILL DSACKO y STATUS EMULATOR DSACK1 CDS SUPPORT CIIN CIOUT CLK CACHE CONTROL CBREQ Vcc 10 CBACK OND 14 Figure 5 1 Functional Signal Groups MOTOROLA M 30 USER UA 5 1 For Mo aeRO US FR SMANUA Product Go to www freescale com Signal Description Freescale Semiconductor Inc NOTE In this section and in the remainder of the manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inac tive o
114. T AS ASSERT DBEN PLACE DATA ON D31 DO ASSERT DS ACCEPT DATA 0 NO O Bb O N 1 DECODE ADDRESS 2 STORE DATA FROM D31 D0 3 ASSERT DSACKx TERMINATE OUTPUT TRANSFER IF CAS2 INSTRUCTION 1 NEGATE AS AND DS AND ONLY ONE OPERAND 2 REMOVE DATA FROM D31 D0 WRITTEN THEN GO TO 3 NEGATE DBEN TERMINATE CYCLE D ELSE GO TO B 1 NEGATE DSACKx e UNLOCK BUS START NEXT CYCLE Figure 7 29 Asynchronous Read Modify Write Cycle Flowchart ds For MESSER VANE Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bus Operation State 2 During state 2 S2 the processor drives DBEN active to enable external data buffers The selected device uses R W SIZO SIZ1 A0 A1 and DS to place information on the data bus Any or all of the bytes D24 D31 D16 D23 D8 D15 and DO D7 are selected by SIZO SIZ1 and A0 A1 Concurrently the selected device may assert the DSACKx signals State 3 As long as at least one of the DSACKx signals is recognized by the end of S2 meeting the asynchronous input setup time requirement data is latched on the next falling edge of the clock and the cycle terminates If DSACKx is not recognized by the start of S3 the processor inserts wait states instead of proceeding to S4 and S5 To ensure that wait states are inserted both DSACKO and DSACK1 must remain negated throughout the asynchronous input setup and hold times around the en
115. TERM are met Burst mode operation requires the use of STERM to terminate each of its cycles The first cycle of any burst transfer must be a synchronous cycle as described in the preceding paragraph The exact timing of this cycle is controlled by the assertion of STERM and wait cycles can be inserted as necessary However the minimum cycle time is two clocks If a burst operation is initiated and allowed to terminate normally the second third and fourth cycles latch data on successive falling edges of the clock at a minimum Again the exact timing for these subsequent cycles is controlled by the timing of STERM for each of these cycles and wait cycles can be inserted as necessary MOTOROLA For Mol4Qp3030 USER ion On AUS Product ga Go to www freescale com Bus Operation Freescale Semiconductor Inc Although the synchronous input signals STERM CIIN and CBACK must be stable for the appropriate setup and hold times relative to every rising edge of the clock during which AS is asserted the assertion or negation of CBACK and CIIN is internally latched on the rising edge of the clock for which STERM is asserted in a synchronous cycle The STERM signal can be generated from the address bus and function code value and does not need to be qualified with the AS signal If STERM is asserted and no cycle is in progress even if the cycle has begun ECS is asserted and then the cycle is aborted STERM is ignored by the MC68030
116. TRUCTURE POINTER LIST WITH OUTER DISPLACEMENT DATA ITEM Figure 2 14 Postindexed Indirect Addressing with Outer Displacement 2 6 2 General Addressing Mode Summary The addressing modes described in the previous section are derived from specific combinations of options in the indexing mode or a selection of two alternate addressing modes For example the addressing mode called register indirect Rn assembles as the address register indirect if the register is an address register If Rn is a data register the assembler uses the address register indirect with index mode using the data register as the indirect register and suppresses the address register by setting the base suppress bit in the effective address specification Assigning an address register as Rn provides higher performance than using a data register as Rn Another case is bd An which selects an addressing mode depending on the size of the displacement If the displacement is 16 bits or less the address register indirect with displacement mode d46 An is used When a 32 bit displacement is required the address register indirect with index bd An Xn is used with the index register suppressed ee For Mare formation Un This Product MOS EA Go to www freescale com Freescale Semiconductors dne Addressing Capabilities It is useful to examine the derived addressing modes available to a programmer without regard to the MC68030 effective addressing m
117. U NAE Product Go to www freescale com Freescale Semiconductor dne Addressing Capabilities 2 4 10 Memory Indirect Preindexed Mode In this mode the operand and its address are in memory The processor calculates an intermediate indirect memory address using the base register An a base displacement bd and the index operand Xn SIZE SCALE The processor accesses a long word at this address and adds the outer displacement to yield the effective address Both displacements and the index register contents are sign extended to 32 bits In the syntax for this mode brackets enclose the values used to calculate the intermediate memory address All four user specified values are optional Both the base and outer displacements may be null word or long word When a displacement is omitted or an element is suppressed its value is taken as zero in the effective address calculation GENERATION ASSEMBLER SYNTAX EA bd An Xn SIZE SCALE od MODE bd An Xn SIZE SCALE od ADDRESS REGISTER 110 31 0 An gt MEMORY ADDRESS 31 0 BASE DISPLACEMENT SIGN EXTENDED VALUE O 31 0 SIGN EXTENDED VALUE 7 0 Y SCALE VALUE X J 4t 31 Y 0 INDEX REGISTER INDIRECT MEMORY ADDRESS POINTS TO 31 Y 0 SCALE VALUE AT INDIRECT MEMORY ADDRESS 31 0 OUTER DISPLACEMENT SIGN EXTENDED VALUE 31 0 EFFECTIVE ADDRESS OPERAND NUMBER OF EXTENSION WORDS 1 2 3 4 OR5 MOTOROLA M 30 USER UA 2 15 For Mo LRO US FR SMANUA Product
118. VALID DATA TO 9 P EXECUTION UNIT Spec NA b gt CACHE CONTROL LOGIC ly COMPARATOR 99 9 LINE HIT CACHE SIZE 64 LONG WORDS LINE SIZE 4 LONG WORDS SET SIZE Figure 6 3 On Chip Data Cache Organization 6 1 2 1 WRITE ALLOCATION The supervisor program can configure the data cache for either of two types of allocation for data cache entries that miss on write cycles The state of the write allocation WA bit in the cache control register specifies either no write allocation or write allocation with partial validation of the data entries in the cache on writes When no write allocation is selected WA 0 write cycles that miss do not alter the data cache contents In this mode the processor does not replace entries in the cache during write operations The cache is updated only during a write hit When write allocation is selected WA 1 the processor always updates the data cache on cachable write cycles but only validates an updated entry that hits or an entry that is updated with long word data that is long word aligned When a tag miss occurs on a write of long word data that is long word aligned the corresponding tag is replaced and only the long word being written is marked as valid The other three entries in the cache line are invalidated when a tag miss occurs on a misaligned long word write or on a byte or word write the data is not written in the cache the tag is unaltered and the valid bit s are clea
119. Word Read Cycles 32 Bit Port 7 22 Long Word Read 8 Bit Port with CIOUT Asserted 7 23 Long Word Read 16 Bit and 32 Bit Port 7 24 Asynchronous Write Cycle Flowchart oo ooooooo 7 25 Asynchronous Read Write Read Cycles 32 Bit Port 7 26 Asynchronous Byte and Word Write Cycles 32 Bit Port 7 27 Long Word Operand Write 8 Bit Port 7 28 Long Word Operand Write 16 Bit Port 7 29 Asynchronous Read Modify Write Cycle Flowchart 7 30 Asynchronous Byte Read Modify Write Cycle 32 Bit Port TAS Instruction with CIOUT or CIIN Asserted 7 31 Synchronous Long Word Read Cycle Flowchart No Burst Allowed aa a ma it KA SD a aes 7 32 Synchronous Read with CIIN Asserted and CBACK Negated 7 33 Synchronous Write Cycle Flowchart o ooooooocooo 7 34 Synchronous Write Cycle with Wait States CIOUT Asserted xxxviii MC68030 USER S MANUAL For More Information On This Product Go to www freescale com Page Number MOTOROLA Freescale Semiconductor Inc LIST OF ILLUSTRATIONS Continued Figure Title Number 7 395 Synchronous Read Modify Write Cycle Flowchart 7 36 Synchronous Read Modify Write Cycle Timing CIIN Asserted 7 37 Burst Operation Flowchart Four Long Words Transferred 7 3
120. a or in a data register Register operands are 32 bits long and memory operands are 8 bits long In Table 3 5 the summary of the bit manipulation operations Z refers to bit 2 the zero bit of the status register d For IC ORO USERS MANYAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc cio Set Summary Table 3 5 Bit Manipulation Operations Instruction Operand Syntax Operand Size Operation BCHG Dn ea 8 32 bit number of destination gt Z gt bit of destination data ea 8 32 BCLR Dn ea 8 32 bit number of destination gt Z data ea 8 32 0 bit of destination BSET Dn ea 8 32 bit number of destination gt Z data ea 8 32 1 gt bit of destination BTST Dn ea 8 32 bit number of destination 2 Z data ea 8 32 3 2 6 Bit Field Operations The MC68030 supports variable length bit field operations on fields of up to 32 bits The bit field insert BFINS instruction inserts a value into a bit field Bit field extract unsigned BFEXTU and bit field extract signed BFEXTS extract a value from the field Bit field find first one BFFFO finds the first bit that is set in a bit field Also included are instructions that are analogous to the bit manipulation operations bit field test BFTST bit field test and set BFSET bit field test and clear BFCLR and bit field test and change BFCHG Table 3 6 is a summary of the bit field opera
121. abled the bus controller requests a burst mode fill operation in either of these cases e A read cycle for either the instruction or data cache misses due to the indexed tag not matching e A read cycle tag matches but all long words in the line are invalid The bus controller requests a burst mode fill operation by asserting the cache burst request signal CBREQ The responding device may sequentially supply one to four long words of cachable data or it may assert the cache inhibit input signal CIIN when the data in a long word is not cachable If the responding device does not support the burst mode and it terminates cycles with STERM it should not acknowledge the request with the assertion of the cache burst acknowledge CBACK signal The MC68030 ignores the assertion of CBACK during cycles terminated with DSACKx The cache burst request signal CBREQ requests burst mode operation from the referenced external device To operate in the burst mode the device or external hardware must be able to increment the low order address bits if required and the current cycle must be a 32 bit synchronous transfer STERM must be asserted as described in Section 7 Bus Operation The device must also assert CBACK at the same time as STERM at the end of the cycle in which the MC68030 asserts CBREQ CBACK causes the processor to continue driving the address and bus control signals and to latch a new data value for the next cache entry at the
122. ace TYPES uui ee eie eer de ieee DARAGA 4 5 4 3 Exception PIOCOSSITDO s t deo do Glide e eh etn eee See 4 6 xxvi MC68030 USER S MANUAL MOTOROLA For More Information On This Product Go to www freescale com Paragraph Number 4 3 1 4 3 2 5 11 1 5 11 2 5 11 3 5 11 4 MOTOROLA Freescale Semiconductor Inc TABLE OF CONTENTS Continued Exception VECIOIS 0 x quss ERG tate edad decade ROBUR Exception Stack Frame 0 0 2 c eee eee elles Section 5 Signal Description Signal MOOG uou tecto ob hehe sie ens WO ads ine AG e E Ra E Ed Function Code Signals FCO FC2 2000 cece eee Address Bus 1A0 A31 ets ahha epe Data B s D0 D 31 iei nidos an ei BAG Me E a ee dios reds Transfer Size Signals SIZO SIZ1 AA Bus Control Signals 5 3259 E ABA NAA AGE KEN Sov AED Operand Cycle Start OCS cee cR RR RR External Cycle Start ECS a Read Write RAW Read Modify Write Cycle RMC 0002 eee eee Address Strobe AS cao euo etuer da fgets ds Vere Sy am Data Strobe DS vo ade eos e E EE heats oes eS lak DISC Data Buffer Enable DBEN 14224 KANG GG ka Vi Data Transfer and Size Acknowledge DSACKO DSACK1 Synchronous Termination STERM 00 0055 Cache Control Signals llle Cache Inhibit Input CMN 0c sese oth o Cache Inhibit Output CIOUT xs ga ws iz dr bre ee Cache Burst Request CBREQ 2 2 2 Cache Burst Ac
123. address offset indicated by AO and A1 for cachable accesses Otherwise dynamic bus sizing is identical in the two processors 7 2 6 Cache Filling The on chip data and instruction caches described in Section 6 On Chip Cache Memories are each organized as 16 lines of four long word entries each For each line a tag contains the most significant bits of the logical address FC2 instruction cache or FCO FC2 data cache and a valid bit for each entry in the line An entry fill operation loads an entire long word accessed from memory into a cache entry This type of fill operation is performed when one entry of a line is not valid and an access is cachable A burst fill operation is requested when a tag miss occurs for the current cycle or when all four entires in the cache line are invalid provided the cache is enabled and burst filling for the cache is enabled The burst fill operation attempts to fill all four entries in the line To support burst filling the slave device must have a 32 bit port and must have a burst mode capability that is it must acknowledge a burst request with the cache burst acknowledge CBACK signal It must also terminate the burst accesses with STERM and place a long word on the data bus for each transfer The device may continue to supply successive long words asserting STERM with each one until the cache line is full For further information about filling the cache both entry fills and burst mode fills refer to
124. after a reset operation All supervisor stack pointer references access the interrupt stack pointer ISP in this mode The value of the M bit in the status register does not affect execution of privileged instructions both master and interrupt modes are at the supervisor privilege level Instructions that affect the M bit are MOVE to SR ANDI to SR EORI to SR ORI to SR and RTE Also the processor automatically saves the M bit value and clears it in the SR as part of the exception processing for interrupts All exception processing is performed at the supervisor privilege level All bus cycles generated during exception processing are supervisor references and all stack accesses use the active supervisor stack pointer 4 1 2 User Privilege Level The user level is the lower privilege level The privilege level is determined by the S bit of the status register if the S bit is clear the processor executes instructions at the user privilege level Most instructions execute at either privilege level but some instructions that have important system effects are privileged and can only be executed at the supervisor level For instance user programs are not allowed to execute the STOP instruction or the RESET instruction To prevent a user program from entering the supervisor privilege level except in a controlled manner instructions that can alter the S bit in the status register are privileged The TRAP n instruction provides controlled acc
125. aligned Operands for the case of a word or byte address If the port responds that it is 32 bits wide the MC68030 latches all 32 bits of data and continues with the next operation If the port responds that it is 16 bits wide the MC68030 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits The operation for an 8 bit port is similar but requires four read cycles The addressed device uses the DSACKx signals to indicate the port width For instance a 32 bit device always returns DSACKx for a 32 bit port regardless of whether the bus cycle is a byte word or long word operation Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed A 32 bit port must reside on data bus bits 0 31 a 16 bit port must reside on data bus bits 16 32 and an 8 bit port must reside on data bus bits 24 31 This requirement minimizes the number of bus cycles needed to transfer data to 8 and 16 bit ports and ensures that the MC68030 correctly transfers valid data The MC68030 always attempts to transfer the maximum amount of data on all bus cycles for a long word operation it always assumes that the port is 32 bit wide when beginning the bus cycle The bytes of operands are designated as shown in Figure 7 3 The most significant byte of a long word operand is OPO and OP3 is the least significant byte The two bytes of a word length operand are OP2 most significant
126. ally cpGEN Coprocessor General Instruction cpTRAPcc Trap Conditionally 1 6 2 Virtual Machine A typical use for a virtual machine system is the development of software such as an operating system for a new machine also under development and not yet available for programming use In a virtual machine system a governing operating system emulates the hardware of the new machine and allows the new software to be executed and debugged as though it were running on the new hardware Since the new software is controlled by the governing operating system it is executed at a lower privilege level than the governing operating system Thus any attempts by the new software to use virtual resources that are not physically present and should be emulated are trapped to the governing operating system and performed by its software In the MC68030 implementation of a virtual machine the virtual application runs at the user privilege level The governing operating system executes at the supervisor privilege level and any attempt by the new operating system to access supervisor resources or execute privileged instructions causes a trap to the governing operating system Instruction continuation is used to support virtual I O devices in memory mapped input output systems Control and data registers for the virtual device are simulated in the memory map An access to a virtual register causes a fault and the function of the register is emulated b
127. along with BERR and HALT provides a relinquish and retry operation The MC68030 does not relinquish the bus during a read modify write operation except during the first read cycle Any device that requires the processor to give up the bus and retry a bus cycle during a read modify write cycle must either assert BERR and BR only HALT must not be included or use the single wire arbitration method discussed in 7 7 4 Bus Arbitration Control The bus error handler software should examine the read modify write bit in the special status word refer to 8 2 1 Special Status Word SSW and take the appropriate action to resolve this type of fault when it occurs MOTOROLA For Mol4Qp3030 USER ion On AUS Product ta Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 Si S2 SI Sw Sw S4 S5 S0 S2 S4 A31 A0 X FC2 FC0 X SIZ1 SIZO X RW ECS N NV ocs AS DS DSACK1 N N DSACKO N N 44 DATA BUS NOT DRIVEN ___ gt D31 D0 BERR N lt WRITE CYCLE RETRY SIGNALED gt lt HALT RETRY CYCLE 3 Figure 7 54 Asynchronous Late Retry i For Mare formation Un This Product IA Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 Si S2 SI S0 Si S2 SI A31 A0 X FC2 FC0 X SIZ1 SIZ0 X HALT READ CYCLE RETRY SIGNALED HALT RETRY CYCLE gt Figure 7 55 Synchronous Late Retry
128. am ia sce teaches di 1 2 1 2 User Programming Model tm ios cdi ib NAG LG NG Pw RR ER 1 6 1 3 Supervisor Programming Model Supplement 205 1 7 1 4 Stalis Registers tio det Ao Roda aaa aa ene sus 1 8 2 1 Memory Operand Address 000 eee eee eee 2 6 2 2 Memory Data Organization x ttem anes oe m Pao wars 2 7 2 3 Single Effective Address vods wie bh eee EE ERR ek he a REA 2 8 2 4 Effective Address Specification Formats ooocooooooo 2 23 2 5 Using SIZE in the Index Selection oooooccococoooo 2 25 2 6 Using Absolute Address with Indexes 0ooo ooooooo 2 26 2 7 Addressing Array Items 00 0 ee ee 2 27 2 8 Using Indirect Absolute Memory Addressing 2 28 2 9 Accessing an Item in a Structure Using a Pointer 2 28 2 10 Indirect Addressing Suppressed Index Register 2 29 2 11 Preindexed Indirect Addressing 0002 eee eee eee 2 29 2 12 Postindexed Indirect Addressing 2000 cee eee eee eee 2 30 2 13 Preindexed Indirect Addressing with Outer Displacement 2 30 2 14 Postindexed Indirect Addressing with Outer Displacement 2 31 2 15 M68000 Family Address Extension Words 0 0 aaa 2 37 3 1 Instruction Word General Format 0000 eee eee eee 3 1 3 2 Linked List Insertion 22 7 eve sete man tacts DEL AKALA AR 3 26 3 3 LinkedList Dell deeem AS Mae D
129. ands The insert bit field BFINS instruction inserts a bit field stored in a register into a bit field The extract bit field signed BFEXTS instruction loads a bit field into the least significant bits of a register and extends the sign to the left filling the register The extract bit field unsigned BFEXTU also loads a bit field but zero fills the unused portion of the destination register The set bit field BFSET instruction sets all the bits of a field to ones The clear bit field BFCLR instruction clears a field The change bit field BFCHG instruction complements all the bits in a bit field These three instructions all test the previous value of the bit field setting the condition codes accordingly The test bit field BFTST instruction tests the value in the field setting the condition codes appropriately without altering the bit field The find first one in bit field BFFFO instruction scans a bit field from bit 0 to the right until it finds a bit set to one and loads the bit offset of the first set bit into the specified data register If no bits in the field are set the field offset and the field width is loaded into the register An important application of bit field instructions is the manipulation of the exponent field in a floating point number In the IEEE standard format the most significant bit is the sign bit of the mantissa The exponent value begins at the next most significant bit position the exponent field does no
130. ands used by instructions and describes the registers and their use as operands Next the section describes the organization of data in memory and the addressing modes available to access data in memory Last the section describes the system stack and user program stacks and queues 2 1 INSTRUCTION OPERANDS The MC68030 supports a general purpose set of operands to serve the requirements of a large range of applications Operands of MC68030 instructions may reside in registers in memory or within the instructions themselves An instruction operand might also reside in a coprocessor An operand may be a single bit a bit field of from 1 to 32 bits in length a byte 8 bits a word 16 bits a long word 32 bits or a quad word 64 bits The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation Coprocessors are designed to support special computation models that require very specific but widely varying data operand types and sizes Hence coprocessor instructions can specify operands of any size moe For Mold jetorimatien On This Product ed Go to www freescale com Data Organization and adari AR EG AA Semiconductor Inc 2 2 ORGANIZATION OF DATA IN REGISTERS The eight data registers can store data operands of 1 8 16 32 and 64 bits addresses of 16 or 32 bits or bit fields of 1 to 32 bits The seven address registers and the three stack pointers are us
131. anization and adari tag Ef AA 2emiconductor Inc 2 4 16 Absolute Short Addressing Mode In this addressing mode the operand is in memory and the address of the operand is in the extension word The 16 bit address is sign extended to 32 bits before it is used GENERATION ASSEMBLER SYNTAX MODE REGISTER FIELD EXTENSION WORD MEMORY ADDRESS NUMBER OF EXTENSION WORDS EA GIVEN xxx W 111 000 15 0 SIGN EXTENDED MEMORY ADDRESS 31 0 OPERAND 1 2 4 17 Absolute Long Addressing Mode In this mode the operand is in memory and the address of the operand occupies the two extension words following the instruction word in memory The first extension word contains the high order part of the address the low order part of the address is the second extension word GENERATION ASSEMBLER SYNTAX MODE REGISTER FIELD FIRST EXTENSION WORD SECOND EXTENSION WORD MEMORY ADDRESS NUMBER OF EXTENSION WORDS 2 20 For More Information Un This Product EA GIVEN xxx L 111 001 15 0 RM ADDRESS HIGH 15 0 gt ADDRESS LOW 31 0 CONCATENATION OPERAND MOTOROLA Go to www freescale com Freescale Semiconductors dne Addressing Capabilities 2 4 18 Immediate Data In this addressing mode the operand is in one or two extension words Byte Operation Operand is in the low order byte of the extension word Word Operation Operand is in the extension word L
132. are optional However the user must supply the assembler notation ZPC zero value is taken for the PC to indicate that the PC is not used This allows the user to access the program space without using the PC in calculating the effective address Both the base and outer displacements may be null word or long word When a displacement is omitted or an element is suppressed its value is taken as zero in the effective address calculation GENERATION EA bd PC Xn SIZE SCALE od ASSEMBLER SYNTAX bd PC Xn SIZE SCALE od MODE 111 REGISTER FIELD 011 31 0 PROGRAM COUNTER gt 31 0 BASE DISPLACEMENT SIGN EXTENDED VALUE 31 0 INDIRECT MEMORY ADDRESS POINTS TO 31 0 VALUE AT INDIRECT MEMORY ADDRESS IN PROGRAM SPACE 31 0 INDEX REGISTER SIGN EXTENDED VALUE 7 0 SCALE VALUE Oma 31 0 OUTER DISPLACEMENT SIGN EXTENDED VALUE H lt be 31 0 NUMBER OF EXTENSION WORDS 1 2 3 4 OR5 218 For MISA USERS BANAL Product MOTOROLA Go to www freescale com Freescale Semiconductor dne Addressing Capabilities 2 4 15 Program Counter Memory Indirect Preindexed Mode This mode is similar to the memory indirect preindexed mode described in 2 4 10 Memory Indirect Preindexed Mode but the PC is used as the base register Both the operand and operand address are in memory The processor calculates an intermediate indirect memory address by adding the PC contents a base displacement bd and the scaled contents o
133. aringly if at all particularly in programs that require maximum performance 2 6 1 Addressing Capabilities In both the MC68020 and the MC68030 setting the base register suppress BS bit in the full format extension word see Figure 2 4 suppresses use of the base address register in calculating the effective address This allows any index register to be used in place of the base register Since any of the data registers can be index registers this provides a data register indirect form Dn The mode could be called register indirect Rn since either a data register or an address register can be used This addressing mode is an extension to the M68000 Family because the MC68030 and MC68020 can use both the data registers and the address registers to address memory The capabilities of specifying the size and scale of an index register Xn SIZE SCALE in these modes provides additional addressing flexibility Using the SIZE parameter either the entire contents of the index register can be used or the least significant word can be sign extended to provide a 32 bit index value refer to Figure 2 5 0 pu a 31 16 15 0 am RAN USED IN ADDRESS CALCULATION Figure 2 5 Using SIZE in the Index Selection MOTOROLA For MONROE WANA product 226 Go to www freescale com Data Organization and adari tag Ef AA 2emiconductor Inc For both the MC68020 and the MC68030 the register indirect modes can be extended further Since displa
134. ationship of STERM to bus operation For Mors Ra BR Un his Product MOTOROLA C Go to www freescale com Freescale Semiconductor Inc Signal Description 5 7 CACHE CONTROL SIGNALS The following signals relate to the on chip caches 5 7 1 Cache Inhibit Input CIIN This input signal prevents data from being loaded into the MC68030 instruction and data caches It is a synchronous input signal and is interpreted on a bus cycle by bus cycle basis CIIN is ignored during all write cycles Refer to 6 1 On Chip Cache Organization and Operation for information on the relationship of CIIN to the on chip caches 5 7 2 Cache Inhibit Output CIOUT This three state output signal reflects the state of the Cl bit in the address translation cache entry for the referenced logical address indicating that an external cache should ignore the bus transfer When the referenced logical address is within an area specified for transparent translation the Cl bit of the appropriate transparent translation register controls the state of CIOUT Refer to Section 9 Memory Management Unit for more information about the address translation cache and transparent translation Also refer to Section 6 On Chip Cache Memories for the effect of CIOUT on the internal caches 5 7 3 Cache Burst Request CBREQ This three state output signal requests a burst mode operation to fill a line in the instruction or data cache Refer to 6 1 3 Cache Filling for filling
135. ble 7 5 corresponding to SIZO_SIZ1_AO_A1 0000 The port latches the data on bits D16 D31 of the data bus asserts DSACK1 DSACKO remains negated and the processor terminates the bus cycle It then starts a new bus cycle with SIZO SIZ1 AO A1 1010 to transfer the remaining 16 bits SIZO and SIZ1 indicate that a word remains to be transferred AO and A1 indicate that the word corresponds to an offset of two from the base address The multiplexer follows the pattern corresponding to this configuration of the size and address signals and places the two least significant bytes of the long word on the word portion of the bus D16 D31 The bus cycle transfers the remaining bytes to the word size port Figure 7 6 shows the timing of the bus transfer signals for this operation ius For More Information Un This Product UNE C Go to www freescale com MOTOROLA Freescale Semiconductor Inc Bus Operation Table 7 5 MC68030 Internal to External Data Bus Table did not make it over in the conversion from Word 31 LONG WORD OPERAND 0 D31 DATA BUS D16 WORD MEMORY MC68EC030 MEMORY CONTROL MSB LSB SZ SZ0 At Ao DSACKi DSACKO 0 0 0 0 L H P P1 pa y 1 0 1 0 L H OP OP3 Figure 7 5 Example of Long Word Transfer to Word Port For More Information Un Hiis Albroduct 7 11 Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2 S4 S0 S2 S4 A1 N A0 SIZ1 SIZO DSACK1 N N DSACKO
136. bytes The address N of a long word data item corresponds to the address of the most significant byte of the highest order word The lower order word is located at address N 2 leaving the least significant byte at address N 3 refer to Figure 2 1 Notice that the MC68030 does not require data to be aligned on word boundaries refer to Figure 2 but the most efficient data transfers occur when data is aligned on the same byte boundary as its operand size However instruction words must be aligned on word boundaries MOTOROLA For More datori atrar ion on This Product a Go to www freescale com Data Organization and add ARGEFAA 2emiconductor Inc The data types supported in memory by the MC68030 are bit and bit field data integer data of 8 16 or 32 bits 32 bit addresses and BCD data packed and unpacked These data types are organized in memory as shown in Figure 2 2 Note that all of these data types can be accessed at any byte address Coprocessors can implement any data types and lengths up to 255 bytes For example the MC68881 MC68882 floating point coprocessors support memory accesses for quad word sized items double precision floating point values Figure 2A bit operand is specified by a base address that selects one byte in memory the base byte and a bit number that selects the one bit in this byte The most significant bit of the byte is bit 7 LONG WORD 00000000 WORD 00000000 WORD 00000002 BYTE 000
137. cachable this operation results in four bus cycles The first cycle requested by the MC68030 reads a byte from address 03 The 8 bit DSACKx response causes the MC68030 to fetch the remainder of the long word starting at address 00 The bytes are latched in the following order b3 bO b1 and b2 Note that during cache loading operations devices must indicate the same port size consistently throughout all cycles for that long word entry in the cache Figure 6 6 shows the access of a byte data operand from a 16 bit port This operation requires two read cycles The first cycle requests the byte at address 03 If the device responds with a 16 bit DSACKx encoding the word at address 02 including the requested byte is accepted by the MC68030 The second cycle requests the word at address 00 Since the device again responds with a 16 bit DSACKx encoding the remaining two bytes of the long word are latched and the cache entry is filled UNABLE TO LOCATE ART Figure 6 5 Single Entry Mode Operation 8 Bit Port UNABLE TO LOCATE ART Figure 6 6 Single Entry Mode Operation 16 Bit Port With a 32 bit port the same operation is shown in Figure 6 7 Only one read cycle is required All four bytes including the requested byte are latched during the cycle UNABLE TO LOCATE ART Figure 6 7 Single Entry Mode Operation 32 Bit Port If a requested access is misaligned and spans two cache entries the bus controller attempts to fill b
138. case it terminates the cycle and indicates that the transfer was made to a 32 bit port Refer to 7 3 2 Asynchronous Write Cycle for timing relationships of STERM The bus error BERR signal is also a bus cycle termination indicator and can be used in the absence of DSACKx or STERM to indicate a bus error condition It can also be asserted in conjunction with DSACKx or STERM to indicate a bus error condition provided it meets the appropriate timing described in this section and in MC68030EC D MC68030 Electrical Specifications Additionally the BERR and HALT signals can be asserted together to indicate a retry termination Again the BERR and HALT signals can be asserted simultaneously in lieu of or in conjunction with the DSACKx or STERM signals Finally the autovector AVEC signal can be used to terminate interrupt acknowledge cycles indicating that the MC68030 should internally generate a vector number to locate an interrupt handler routine AVEC is ignored during all other bus cycles 7 2 DATA TRANSFER MECHANISM The MC68030 architecture supports byte word and long word operands allowing access to 8 16 and 32 bit data ports through the use of asynchronous cycles controlled by DSACKO and DSACKT It also supports synchronous bus cycles to and from 32 bit ports terminated by STERM Byte word and long word operands can be located on any byte boundary but misaligned transfers may require additional bus cycles regar
139. ccesses in this space to communicate with external devices for special purposes For example all M68000 processors use the CPU space for interrupt acknowledge cycles The MC68020 and MC68030 also generate CPU space accesses for breakpoint acknowledge and coprocessor operations Supervisor programs can use the MOVES instruction to access all address spaces including the user spaces and the CPU address space Although the MOVES instruction can be used to generate CPU space cycles this may interfere with proper system operation Thus the use of MOVES to access the CPU space should be done with caution VOTERA For Mold iteration On This Product T9 Go to www freescale com Processing States Freescale Semiconductor Inc 4 3 EXCEPTION PROCESSING An exception is defined as a special condition that pre empts normal processing Both internal and external conditions cause exceptions External conditions that cause exceptions are interrupts from external devices bus errors coprocessor detected errors and reset Instructions address errors tracing and breakpoints are internal conditions that cause exceptions The TRAP TRAPcc TRAPV cpTRAPcc CHK CHK2 RTE and DIV instructions can all generate exceptions as part of their normal execution In addition illegal instructions privilege violations and coprocessor protocol violations cause exceptions Exception processing which is the transition from the normal processing of a program to the
140. ce FC 7 including those references made with PC relative addressing modes and accesses made with the MOVES instruction Operation of the data cache is similar to that of the instruction cache except for the address comparison and cache filling operations The tag of each line in the data cache contains function code bits FCO FC1 and FC2 in addition to address bits A31 A8 The cache control circuitry selects the tag using bits A7 A4 and compares it to the corresponding bits of the access address to determine if a tag match has occurred Address bits A3 A2 select the valid bit for the appropriate long word in the cache to determine if an entry hit has occurred Misaligned data transfers may span two data cache entries In this case the processor checks for a hit one entry at a time Therefore it is possible that a portion of the access results in a hit and a portion results in a miss The hit and miss are treated independently Figure 6 3 illustrates the organization of the data cache The operation of the data cache differs for read and write cycles A data read cycle operates exactly like an instruction cache read cycle when a miss occurs an external cycle is initiated to obtain the operand from memory and the data is loaded into the cache if the access is cachable In the case of a misaligned operand that spans two cache entries two long words are required from memory Burst mode operation may also be initiated to fill an entire line of th
141. cements can be 32 bits wide they can represent absolute addresses or the results of expressions that contain absolute addresses This allows the general register indirect form to be bd Rn or bd An Rn when the base register is not suppressed Thus an absolute address can be directly indexed by one or two registers refer to Figure 2 6 SYNTAX bd An Rn Figure 2 6 Using Absolute Address with Indexes Scaling provides an optional shifting of the value in an index register to the left by zero one two or three bits before using it in the effective address allocation the actual value in the index register remains unchanged This is equivalent to multiplying the register by one two four or eight or direct subscripting into an array of elements of corresponding size using an arithmetic value residing in any of the 16 general registers Scaling does not add to the effective address calculation time However when combined with the appropriate derived modes it produces additional capabilities Arrayed structures can be addressed absolutely and then subscripted bd Rn scale Another variation that can be derived is An Rn scale In the first case the array address is the sum of the contents of a register and a displacement as shown in Figure 2 7 In the second example An contains the address of an array and Rn contains a subscript de For MUS ARO USOS UA TIAE Product MOTOROLA Go to www freescale com Freescale Semic
142. ces of that emulated system Such an emulated system is called a virtual machine 1 6 1 Virtual Memory A system that supports virtual memory has a limited amount of high speed physical memory that can be accessed directly by the processor and maintains an image of a much larger virtual memory on a secondary storage device such as a large capacity disk drive When the processor attempts to access a location in the virtual memory map that is not resident in physical memory a page fault occurs The access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory The suspended access is then either restarted or continued The MC68030 uses instruction continuation to support virtual memory When a bus cycle is terminated with a bus error the microprocessor suspends the current instruction and executes the virtual memory bus error handler When the bus error handler has completed execution it returns control to the program that was executing when the error was detected reruns the faulted bus cycle when required and continues the suspended instruction moe For Mold jetorimatien On This Product Pu Go to www freescale com Introduction Freescale Semiconductor Inc Table 1 2 Instruction Set Mnemonic Description Mnemonic Description ABCD Add Decimal with Extend MOVE USP Move User Stack Pointer ADD Add
143. ck pointer aligned to a word boundary GENERATION An An SIZE EA An ASSEMBLER SYNTAX An MODE 100 REGISTER n 31 0 OPERAND LENGTH 1 2 OR 4 ve 31 Y 0 NUMBER OF EXTENSION WORDS 0 MOTOROLA M 30 USER UA 2 11 For Mo aeRO US FR SMANUA Product Go to www freescale com Data Organization and adari tag EAR Semiconductor Inc 2 4 6 Address Register Indirect with Displacement Mode In the address register indirect with displacement mode the operand is in memory The address of the operand is the sum of the address in the address register plus the sign extended 16 bit displacement integer in the extension word Displacements are always sign extended to 32 bits prior to being used in effective address calculations GENERATION EA An d46 ASSEMBLER SYNTAX d4 An MODE 101 REGISTER 31 0 n ADDRESS REGISTER AD MEMORY ADDRESS A a 15 0 DISPLACEMENT SIGN EXTENDED INTEGER E 31 0 MEMORY ADDRESS OPERAND NUMBER OF EXTENSION WORDS 1 2 4 7 Address Register Indirect with Index 8 Bit Displacement Mode This addressing mode requires one extension word that contains the index register indicator and an 8 bit displacement The index register indicator includes size and scale information In this mode the operand is in memory The address of the operand is the sum of the contents of the address register the sign extended displacement value in the low order eight bits of the extension word and
144. cle but from a 16 bit port State 0 The read cycle starts in state O SO The processor drives ECS low indicating the beginning of an external cycle When the cycle is the first external cycle of a read operand operation operand cycle start OCS is driven low at the same time During SO the processor places a valid address on A0 A31 and valid function codes on FCO FC2 The function codes select the address space for the cycle The processor drives R W high for a read cycle and drives DBEN inactive to disable the data buffers SIZO SIZ1 become valid indicating the number of bytes requested to be transferred CIOUT also becomes valid indicating the state of the MMU CI bit in the address translation descriptor or in the appropriate TTx register MOTOROLA For Mol4Qp3030 USER ion On AUS Product Tal Go to www freescale com Bus Operation Freescale Semiconductor Inc CONTROLLER EXTERNAL DEVICE ADDRESS DEVICE 1 ASSERT ECS OCS FOR ONE HALF CLOCK 2 SET RIWTO READ 3 DRIVE ADDRESS ON A31 A0 4 DRIVE FUNCTION CODE ON FC2 FCO 5 DRIVE SIZE SIZ1 SIZ0 FOUR BYTES 6 7 8 9 CACHE INHIBIT OUT CIOUT BECOMES VALID ASSERT ADDRESS STROBE AS PRESENT DATA ASSERT DATA STROBE DS ASSERT DATA BUFFER ENABLE DBEN 1 DECODE ADDRESS 2 PLACE DATA ON D31 D0 3 ASSERT DATA TRANSFER AND SIZE ACQUIRE DATA ACKNOWLEDGE DSACKx 1 SAMPLE CACHE IN CIN 2 LATCHDATA 3 NEGATE AS AND DS TERMINATE CYCLE 4 NEGATE
145. com Freescale Semiconductor Inc Bus Operation 7 2 8 Asynchronous Operation The MC68030 bus may be used in an asynchonous manner In that case the external devices connected to the bus can operate at clock frequencies different from the clock for the MC68030 Asynchronous operation requires using only the handshake line AS DS DSACK1 DSACKO BERR and HALT to control data transfers Using this method AS signals the start of a bus cycle and DS is used as a condition for valid data on a write cycle Decoding the size outputs and lower address lines AO and A1 provides strobes that select the active portion of the data bus The slave device memory or peripheral then responds by placing the requested data on the correct portion of the data bus for a read cycle or latching the data on a write cycle and asserting the DSACK1 DSACKO combination that corresponds to the port size to terminate the cycle If no slave responds or the access is invalid external control logic asserts the BERR or BERR and HALT signal s to abort or retry the bus cycle respectively The DSACKx signals can be asserted before the data from a slave device is valid on a read cycle The length of time that DSACKx may precede data is given by parameter 31 and it must be met in any asynchronous system to insure that valid data is latched into the processor Refer to MC68030EC D MC68030 Electrical Specifications for timing parameters Notice that no maximum time is
146. com Freescale Semiconductor Inc Bus Operation To assure proper operation in a synchronous system when BERR or BERR and HALT is asserted after DSACKx BERR and HALT must meet the appropriate setup time parameter 27A prior to the falling clock edge one clock cycle after DSACKx is recognized This setup time is critical and the MC68030 may exhibit erratic behavior if it is violated When operating synchronously the data in setup and hold times for synchronous cycles may be used instead of the timing requirements for data relative to the DS signal The value of CIIN is latched on the rising edge of bus cycle state 4 for all cycles terminated with DSACKx 7 2 10 Synchronous Operation with STERM The MC68030 supports synchronous bus cycles terminated with STERM These cycles for 32 bit ports only are similar to cycles terminated with DSACKx The main difference is that STERM can be asserted and data can be transferred earlier than for a cycle terminated with DSACKx causing the processor to perform a minimum access time transfer in two clock periods However wait cycles can be inserted by delaying the assertion of STERM appropriately Using STERM instead of DSACKx in any bus cycle makes the cycle synchronous Any bus cycle is synchronous if 1 Neither DSACKx nor AVEC is recognized during the cycle 2 The port size is 32 bits 3 Synchronous input setup and hold time requirements specifications 60 and 61 for S
147. completion of each subsequent cycle as defined by STERM for a total of up to four cycles until four long words have been read When a cache burst is initiated the first cycle attempts to load the cache entry corresponding to the instruction word or data item explicitly requested by the execution unit The subsequent cycles are for the subsequent entries in the cache line In the case of a misaligned transfer when the operand spans two cache entries within a cache line the first cycle corresponds to the cache entry containing the portion of the operand at the lower address Figure 6 11 illustrates the four cycles of a burst operation and shows that the second third and fourth cycles are run in burst mode A distinction is made between the first cycle of a burst operation and the subsequent cycles because the first cycle is requested by the microsequencer and the burst fill cycles are requested by the bus controller Therefore when data from the first cycle is returned it is immediately available for the execution unit EU However data from the burst fill cycles is not available to the EU until the burst operation is complete Since the microsequencer makes two separate requests for misaligned data operands only the first portion of the misaligned operand returned during a eMe For Mare formation Un This Product MOS EA Go to www freescale com Freescale Semiconductor Inc chio Cache Manhid burst operation is available to
148. ct UNE C Go to www freescale com Freescale Semiconductor Inc Bus Operation CONTROLLER INTERRUPTING DEVICE ACKNOWLEDGE INTERRUPT REQUEST INTERRUPT 1 INTERRUPT PENDING IPEND RECOGNIZED BY CURRENT INSTRUCTION WAIT FOR INSTRUCTION BOUNDARY 2 SET R W TO READ 3 SET FUNCTION CODE TO CPU SPACE 4 PLACE INTERRUPT LEVEL ON A1 A2 AND A3 TYPE FIELD INTERRUPT ACKNOWLEDGE IACK 5 SET SIZE TO BYTE 6 NEGATE IPEND 7 ASSERT ADDRESS STROBE AS AND DATA STROBE DS PROVIDE VECTOR INFORMATION 1 PLACE VECTOR NUMBER ON LEAST SIGNIFICANT BYTE OF DATA PORT DEPENDS ON PORT SIZE 2 ASSERT DATA AND SIZE ACKNOWLEDGE DSACKx OR ASSERT SYNCHRONOUS TERMINATION ACQUIRE VECTOR NUMBER STERN 1 LATCH VECTOR NUMBER 2 NEGATE AS AND DS RELEASE 1 REMOVE VECTOR NUMBER FROM DATA BUS CONTINUE INTERRUPT EXCEPTION PROCESSING 2 NEGATE DEAN Figure 7 43 Interrupt Acknowledge Cycle Flowchart Figure 7 44 shows the timing for an interrupt acknowledge cycle terminated with DSACKx 7 4 1 2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE When the interrupting device cannot supply a vector number it requests an automatically generated vector or autovector Instead of placing a vector number on the data bus and asserting DSACKx or STERM the device asserts the autovector signal AVEC to terminate the cycle Neither STERM nor DSACKx may be asserted during an interrupt acknowledge cycle terminated by AVEC The
149. ctivity increases overall performance by increasing the availability of the bus for use by external devices in systems with more than one bus master such as a processor and a DMA device without degrading the performance of the MC68030 An increase in instruction throughput results when instruction words and data required by a program are available in the on chip caches and the time required to access them on the external bus is eliminated Additionally instruction throughput increases when instruction words and data can be accessed simultaneously As shown in Figure 6 1 the instruction cache and the data cache are connected to separate on chip address and data buses The address buses are combined to provide the logical address to the memory management unit MMU The MC68030 initiates an access to the appropriate cache for the requested instruction or data operand at the same time that it initiates an access for the translation of the logical address in the address translation cache of the MMU When a hit occurs in the instruction or data cache and the MMU validates the access on a write the information is transferred from the cache on a read or to the cache and the bus controller on a write When a hit does not occur the MMU translation of the address is used for an external bus cycle to obtain the instruction or operand Regardless of whether or not the required operand is located in one of the on chip caches the address translation cache of
150. cycle is for the first access of an operand that spans two cache lines crosses a modulo 16 boundary Additionally the assertion of CIIN and BERR and the premature negation of CBACK affect burst operation as described in the following paragraphs The assertion of CIIN during the first cycle of a burst operation causes the data to be latched by the processor and if the requested operand is aligned the entire operand is latched in the first cycle the data is passed on to the instruction pipe or execution unit However the data is not loaded into its corresponding cache In addition the MC68030 negates CBREQ and the burst operation is aborted If a portion of the requested operand remains to be read due to misalignment a second read cycle is initiated at the appropriate address with CBREQ negated The assertion of CIIN during the second third or fourth cycle of a burst operation prevents the data during that cycle from being loaded into the appropriate cache and causes CBREQ to negate aborting the burst operation However if the data for the cycle contains part of the requested operand the execution unit uses that data The premature negation of the CBACK signal during the burst operation causes the current cycle to complete normally loading the data successfully transferred into the appropriate cache However the burst operation aborts and CBREQ negates A bus error occurring during a burst operation also causes the burst operation
151. d of S2 If wait states are added the processor continues to sample the DSACKx signals on the falling edges of the clock until one is recognized State 4 The processor samples the level of CIIN at the beginning of S4 At the end of S4 the processor latches the incoming data State 5 The processor negates AS DS and DBEN during S5 If more than one read cycle is required to read in the operand s SO S5 are repeated for each read cycle When finished reading the processor holds the address R W and FCO FC2 valid in preparation for the write portion of the cycle The external device keeps its data and DSACKx signals asserted until it detects the negation of AS or DS whichever it detects first The device must remove the data and negate DSACKx within approximately one clock period after sensing the negation of AS or DS DSACKx signals that remain asserted beyond this limit may be prematurely detected for the next portion of the operation Idle States The processor does not assert any new control signals during the idle states but it may internally begin the modify portion of the cycle at this time S6 S11 are omitted if no write cycle is required If a write cycle is required the R W signal remains in the read mode until S6 to prevent bus conflicts with the preceding read portion of the cycle the data bus is not driven until S8 MOTOROLA For Mol4Qp3030 USER ion On AUS Product ne Go to www freescale com Bus Operation Freesca
152. d user so the supervisor can protect system resources from uncontrolled access The processor uses the privilege level indicated by the S bit in the status register to select either the user or supervisor privilege level and either the user stack pointer or a supervisor stack pointer for stack operations The processor identifies a bus access Supervisor or user mode via the function codes so that differentiation between supervisor and user can be maintained The memory management unit uses the indication of privilege level to control and translate memory accesses to protect supervisor code data and resources from access by user programs In many systems the majority of programs execute at the user level User programs can access only their own code and data areas and can be restricted from accessing other information The operating system typically executes at the supervisor privilege level It has access to all resources performs the overhead tasks for the user level programs and coordinates their activities 4 1 1 Supervisor Privilege Level The supervisor level is the higher privilege level The privilege level is determined by the S bit of the status register if the S bit is set the supervisor privilege level applies and all instructions are executable The bus cycles for instructions executed at the supervisor level are normally classified as supervisor references and the values of the function codes on FCO FC2 refer to supervisor addre
153. data or if the data should not be cached the device must assert cache inhibit in CIIN as it terminates the read cycle If the bus cycle terminates abnormally the MC68030 does not cache the data For details of interactions of port sizes misalignments and cache filling refer to 6 1 3 Cache Filling The caches can also affect the assertion of AS and the operation of a read cycle The search of the appropriate cache by the processor begins when the microsequencer requires an instruction or a data item At this time the bus controller may also initiate an external bus cycle in case the requested item is not resident in the instruction or data cache If the bus is not occupied with another read or write cycle the bus controller asserts the ECS signal and the OCS signal if appropriate If an internal cache hit occurs the external cycle aborts and AS is not asserted This makes it possible to have ECS asserted on multiple consecutive clock cycles Notice that there is a minimum time specified from the negation of ECS to the next assertion of ECS refer to MC68030EC D MC68030 Electrical Specifications Instruction prefetches can occur every other clock so that if after an aborted cycle due to an instruction cache hit the bus controller asserts ECS on the next clock this second cycle is for a data fetch However data accesses that hit in the data cache can also cause the assertion of ECS and an aborted cycle Therefore since instruction and data
154. dless of port size When the processor requests a burst mode fill operation it asserts the cache burst request CBREQ signal to attempt to fill four entries within a line in one of the on chip caches This mode is compatible with nibble static column or page mode dynamic RAMs The burst fill operation uses synchronous bus cycles each terminated by STERM to fetch as many as four long words 7 2 1 Dynamic Bus Sizing The MC68030 dynamically interprets the port size of the addressed device during each bus cycle allowing operand transfers to or from 8 16 and 32 bit ports During an asynchronous operand transfer cycle the slave device signals its port size byte word or long word and indicates completion of the bus cycle to the processor through the use of the DSACKx inputs Refer to Table 7 1 for DSACKx encodings and assertion results i For More RORO NS BR Un his Product MOTOROLA C Go to www freescale com Freescale Semiconductor Inc Bus Operation Table 7 1 DSACK Codes and Results DSACK1 DSACKO Result H Insert Wait States in Current Bus Cycle H L Complete Cycle Data Bus Port Size is 8 Bits L H Complete Cycle Data Bus Port Size is 16 Bits L L Complete Cycle Data Bus Port Size is 32 Bits For example if the processor is executing an instruction that reads a long word operand from a long word aligned address it attempts to read 32 bits during the first bus cycle Refer to 7 2 2 Mis
155. ds without an associated size NO For Mo ARIA RIN OM ANNE Product Go to www freescale com Data Organization and adari RGEFA A 2emiconductor Inc Table 2 2 shows the categories to which each of the effective addressing modes belong Addressing Modes Mode Register Data Memory Control Alterable red Data Register Direct 000 reg no X X Dn Address Register Direct 001 reg no X An Address Register Indirect 010 reg no X X X X An Address Register Indirect with Postincrement 011 reg no X X X An Address Register Indirect with Predecrement 100 reg no X X X An Address Register Indirect with Displacement 101 reg no X X X X di6 An Address Register Indirect with Index 8 Bit Displacement 110 reg no X X X X dg An Xn Address Register Indirect with Index Base Displacement 110 reg no X X X X bd An Xn Memory Indirect Postindexed 110 reg no X X X X bd An Xn od Memory Indirect Preindexed 110 reg no X X X X bd An Xn od Absolute Short 111 000 X X X X xxx W Absolute Long 111 001 X X X X xxx L Program Counter Indirect with Displacement 111 010 X X X d45 PC Program Counter Indirect with Index 8 Bit Displacement 111 011 X X X dg PC Xn Program Counter Indirect with Index Base Displacement 111 011 X X X bd PC Xn PC Memory Indirect Postindexed 111 011 X X X bd PC Xn od PC Memory Indirect Preindexed 111 011 X X X bd PC Xn
156. e Source contents Destination Destination contents Vector Location of exception vector inf Positive infinity inf Negative infinity fmt Operand data format byte B word W long L single S double D extended X or packed P FPm One of eight floating point data registers always specifies the source register FPn One of eight floating point data registers always specifies the destination register Notation for subfields and qualifiers bit of operand Selects a single bit of the operand ea offset width Selects a bit field operand The contents of the referenced location operand g The operand is binary coded decimal operations are per formed in decimal address register The register indirect operation address register Indicates that the operand register points to the memory address register Location of the instruction operand the optional mode qualifiers are d and d ix xxx or data Immediate data that follows the instruction word s are For More Information On This Product me Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary Notations for operations that have two operands written operand op operand where op is one of the following gt ce E T V e E A shifted by rotated by The source operand is moved to the destination operand Th
157. e Asynchronous Read Cycle susct NA Bee eee tae ees ee ws Asynchronous Write Cycle llle Asynchronous Read Modify Write Cycle synchronous Read Cycle pev a Synchronous Write Cycle sac basar Re cee Synchronous Read Modify Write Cycle o o o Burst Operation Oycl8s cere E sage Ecke de a GPW Space Cycles c r ER pta pra e Red d aed eto Rota Interrupt Acknowledge Bus Cycles 200000005 Interrupt Acknowledge Cycle Terminated Normally Autovector Interrupt Acknowledge Cycle Spurious Interrupt Cycle x4 tre oe A Breakpoint Acknowledge Cycle eee eee Coprocessor Communication Cycles ooooooocooo Bus Exception Control Cycles 00000 c eee eee eee BUS cio ENS a a a ed e PE ASA nananana ec se Sed hae Hae PRG eee oS Halt CDOFallOEls e ANG E eee seek ede E NS dts Double Bus Falls obio ro donor tede edic bk bcd owe eR oF Bus S nchronization s gant chores aicut p oso her SE na n BUS Arbitrato miat aa E DENS BUS Bi AA AA rp Biis Eas o oleo 2 0 dyes AA DA EAE toda Bus Grant Acknowledge cee ee eee ees Bus Arbitration Control esaet ack tal ta ee e Mee dud eed ash uo deus Reset Operation cared ow A Ee pe win dw Gree eR RR Section 8 Exception Processing Exception Processing Sequence 00 aa Reset EXCODLHOLDI geet ma eee oo atone elias ee KAN Bus Error Exc
158. e taa daa wale 9 7 Example Translation Tree Layout in Memory aaa 9 8 Derivation of Table Index FieldS oo oooococooooo 9 9 Example Translation Tree Using Different Format Descriptors 9 12 Address Translation General Flowchart 0000 0 ee aes 9 14 Root Pointer Descriptor Format 0 0 0 0 eee ee eee 9 23 Short Format Table Descriptor oooooocoooocorrnno 9 24 Long Format Table Descriptor 0c eee eee 9 24 Short Format Page Descriptor and Short Format Early Termination Page Descriptor 2e mE RS det nin 9 25 Long Format Early Termination Page Descriptor 9 25 Long Format Page Descriptor 0 0 0 eee ee eee 9 26 Short Format Invalid Descriptor liliis 9 26 Long Format Invalid Descriptor 000 e eee eee eee 9 27 short Format Indirect Descriptor 2 4 Sa nies e e REDE REI EA 9 27 Long Format Indirect Descriptor oocoooocococoooo oo 9 28 Simplified Table Search Flowchart cee eee eens 9 29 Five Level Table Search acco tar e dacs oes bee vare Ges 9 31 Example Translation Tree Using Contiguous Memory 9 35 Example Translation Tree Using Indirect Descriptors 9 36 Example Translation Tree Using Shared Tables 9 38 Example Translation Tree with Nonresident Tables 9 39 Detailed Flowchart of MMU Table Search Operation
159. e this three state output indicates that an external device should place valid data on the data bus During a write cycle the data strobe indicates that the MC68030 has placed valid data on the bus During two clock synchronous write cycles the MC68030 does not assert DS Refer to 7 1 5 Data Strobe for more information about the relationship of DS to bus operation 5 6 7 Data Buffer Enable DBEN This output is an enable signal for external data buffers This signal may not be required in all systems The timing of this signal may preclude its use in a system that supports two clock synchronous bus cycles Refer to 7 1 6 Data Buffer Enable for more information about the relationship of DBEN to bus operation 5 6 8 Data Transfer and Size Acknowledge DSACKO DSACK1 These inputs indicate the completion of a requested data transfer operation In addition they indicate the size of the external bus port at the completion of each cycle These signals apply only to asynchronous bus cycles Refer to 7 1 7 Bus Cycle Termination Signals for more information on these signals and their relationship to dynamic bus sizing 5 6 9 Synchronous Termination STERM This input is a bus handshake signal indicating that the addressed port size is 32 bits and that data is to be latched on the next falling clock edge for a read cycle This signal applies only to synchronous operation Refer to 7 1 7 Bus Cycle Termination Signals for more information about the rel
160. e FD bit is set to freeze the data cache When the FD bit is set and a miss occurs during a read or write of the data cache the indexed entry is not replaced However write cycles that hit in the data cache cause the entry to be updated even when the cache is frozen When the FD bit is clear a miss in the data cache during a read cycle causes the entry or line to be filled and the filling of entries on writes that miss are then controlled by the WA bit A reset operation clears the FD bit 6 3 1 6 ENABLE DATA CACHE Bit 8 the ED bit is set to enable the data cache When it is cleared the data cache is disabled A reset operation clears the ED bit The supervisor normally enables the data cache but it can clear ED for system debugging or emulation as required Disabling the data cache does not flush the entries If it is enabled again the previously valid entries remain valid and can be used 6 3 1 7 INSTRUCTION BURST ENABLE Bit 4 the IBE bit is set to enable burst filling of the instruction cache Operating systems and other software set this bit when burst filling of the instruction cache is desired A reset operation clears the IBE bit 6 3 1 8 CLEAR INSTRUCTION CACHE Bit 3 the CI bit is set to clear all entries in the instruction cache Operating systems and other software set this bit to clear instructions from the cache prior to a context switch The processor clears all valid bits in the instruction cache at the time a MOVEC ins
161. e bus error in a normal synchronous cycle re For MUS RA USTOS BANAL Product Moreno Go to www freescale com Freescale Semiconductor Inc Bus Operation S0 S2 S4 S6 CLK A3 A2 A0 m FC2 FCO X SIZ1 SIZO RW ECS N BERR N HALT Uk LATE BERR ENDS BURST 0111 1000 1100 NO EXCEPTION TAKEN VALUE OF A3 A0 INCREMENTED BY THE SYSTEM HARDWARE Figure 7 52 Long Word Operand Request Late BERR on Third Access peace For More Information On This Product T Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 St S2 Sw Sw Sw Sw Sw Sw S3 Sw Sw Sw Sw S4 S5 S0 St S2 SI Sw Sw Sw Sw S4 S5 CLK ears XX SIZ1 SIZO rw o E E _ lt lt s A HALT BURST ABORTED gt RERUN CYCLE TO GET LAST BUS ERROR ASSERTED INTERNAL 3 BYTES OF OPERAND 0111 1000 PROCESSING VALUE OF A3 A0 INCREMENTED BY THE SYSTEM HARDWARE Figure 7 53 Long Word Operand Request BERR on Second Access a For MUS ARO USER MANWAL Product Moreno Go to www freescale com Freescale Semiconductor Inc Bus Operation 7 5 2 Retry Operation When the BERR and HALT signals are both asserted by an external device during a bus cycle the processor enters the retry sequence A delayed retry similar to the delayed bus error signal described previously can also occur both for synchronous and asynchronous cycles The processor
162. e can be transferred in the first bus cycle The second bus cycle then consists of a three byte access to a long word boundary Since the memory is long word organized no further bus cycles are necessary Figure 7 17 shows the equivalent operation for a cachable data read cycle 7 2 3 Effects of Dynamic Bus Sizing and Operand Misalignment The combination of operand size operand alignment and port size determines the number of bus cycles required to perform a particular memory access Table 7 6 shows the number of bus cycles required for different operand sizes to different port sizes with all possible alignment conditions for write cycles and noncachable read cycles Table 7 6 Memory Alignment and Port Size Influence on Write Bus Cycles A1 A0 Number of Bus Cycles 00 01 10 11 Instruction 1 2 4 N A N A N A Byte Operand 1 1 1 1 1 1 1 1 1 1 1 1 Word Operand 1 1 2 1 2 2 1 1 2 2 2 2 Long Word Operand 1 2 4 2 3 4 2 2 4 2 3 4 Data Port Size 32 Bits 16 Bits 8 Bits Instruction prefetches are always two words from a long word boundary This table shows that bus cycle throughput is significantly affected by port size and alignment The MC68030 system designer and programmer should be aware of and account for these effects particularly in time critical applications NO For Mo ARIA RIN OM ANNE Product a Go to www freescale com Bus Operation Freescale Semiconductor Inc 15 WORD OPERAND REGISTER a
163. e data cache Read accesses from the CPU address space and address translation table search accesses are not stored in the data cache The data cache on the MC68030 is a writethrough cache When a hit occurs on a write cycle the data is written both to the cache and to external memory provided the MMU validates the access regardless of the operand size and even if the cache is frozen If the MMU determines that the access is invalid the write is aborted the corresponding entry is invalidated and a bus error exception is taken Since the write to the cache completes before the write to external memory the cache contains the new value even if the external write terminates in a bus error The value in the data cache might be used by another instruction before the external write cycle has completed although this should not have any adverse consequences Refer to 7 6 Bus Synchronization for the details of bus synchronization dl For MUSEU USER S MANYAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc chip Cache Memories LONG WORD SELECT TAG INDEX FFF A AAAAAAAAAAAAAAAAAAAAAAAA CCCII3 ewe 22221111111111000000000 O ACCESS ADDRESS 210 1 321098765432109876543210 AA AAA AAA TAG o e e e e e e e e 1 OF 16 e e e e e SELECT e e e e e e e e e A 1 1 1 1 CACHE DATA BUS TAG REPLACE
164. e is entered If an external memory system requires incrementing of the long word base address to supply successive long words of information this function must be performed by external hardware Additionally in the case of burst transfers that cross a 16 byte boundary i e the first long word transferred is not located at A3 A2 00 the external hardware must correctly control the continuation or termination of the burst transfer as desired The burst may be terminated by negating CBACK during the transfer of the most significant long word of the 16 byte image A3 A2 11 or may be continued with CBACK asserted by providing the long word located at A3 A2 00 i e the count sequence wraps back to zero and continues as necessary The MC68030 caches assume the higher order address lines A4 A31 remain unchanged as the long word accesses wrap back around to A3 A2 00 7 4 CPU SPACE CYCLES FCO FC2 select user and supervisor program and data areas as listed in Table 4 1 The area selected by FCO FC2 7 is classified as the CPU space The interrupt acknowledge breakpoint acknowledge and coprocessor communication cycles described in the following sections utilize CPU space oe For More information Un This Product irc C Go to www freescale com Freescale Semiconductor Inc Bus Operation The CPU space type is encoded on A16 A19 during a CPU space operation and indicates the function that the processor is performing On the MC68030
165. e program space with a data register indirect access by placing ZPC in the instruction and specifying a data register Dn as the index register GENERATION EA PC Xn bd ASSEMBLER SYNTAX bd PC Xn SIZE SCALE MODE 111 REGISTER 011 31 0 PROGRAM COUNTER gt ADDRESS OF EXTENSION WORD 31 0 BASE DISPLACEMENT SIGN EXTENDED VALUE G 31 0 7 0 SCALE DD 31 Y 0 NUMBER OF EXTENSION WORDS 1 20R3 MOTOROLA M 30 USER A 2 17 For Mol din ER OR Lus Product Go to www freescale com Data Organization and adari ARGEFAA 2emiconductor Inc 2 4 14 Program Counter Memory Indirect Postindexed Mode This mode is similar to the memory indirect postindexed mode described in 2 4 9 Memory Indirect Postindexed Mode but the PC is used as the base register Both the operand and operand address are in memory The processor calculates an intermediate indirect memory address by adding a base displacement bd to the PC contents The processor accesses a long word at that address and adds the scaled contents of the index register and the optional outer displacement od to yield the effective address The value of the PC used in the calculation is the address of the first extension word The reference is a program space reference and is only allowed for reads refer to 4 2 Address Space Types In the syntax for this mode brackets enclose the values used to calculate the intermediate memory address All four user specified values
166. e since AS remains asserted during the entire operation If the HALT signal is asserted during a burst operation the processor halts at the end of the operation Refer to 7 5 3 Halt Operation for more information about the halt operation An alternate bus master requesting the bus with BR may become bus master at the end of the operation provided BR is asserted early enough to be internally synchronized before another processor cycle begins Refer to 7 7 Bus Arbitration for more information about bus arbitration dn For More Information Un This Product irc C Go to www freescale com Freescale Semiconductor Inc Bus Operation The simultaneous assertion of BERR and HALT during a bus cycle normally indicates that the cycle should be retried However during the second third or fourth cycle of a burst operation this signal combination indicates a bus error condition which aborts the burst operation In addition the processor remains in the halted state until HALT is negated For information about bus error processing refer to 7 5 1 Bus Errors Figure 7 37 is a flowchart of the burst operation The following timing diagrams show various burst operations Figure 7 38 shows burst operations for long word requests with two wait states inserted in the first access and one wait cycle inserted in the subsequent accesses Figure 7 39 shows a burst operation that fails to complete normally due to CBACK negating prematurely Figure 7 40 shows
167. e two operands are exchanged The operands are added The destination operand is subtracted from the source operand The operands are multiplied The source operand is divided by the destination operand Relational test true if source operand is less than destina tion operand Relational test true if source operand is greater than des tination operand Logical OR Logical exclusive OR Logical AND The source operand is shifted or rotated by the number of positions specified by the second operand Notation for single operand operations operand operand sign extended operand tested Notation for other operations TRAP STOP If condition then operations else operations MOTOROLA The operand is logically complemented The operand is sign extended all bits of the upper portion are made equal to the high order bit of the lower portion The operand is compared to zero and the condition codes are set appropriately Equivalent to Format Offset Word SSP SSP 2 gt SSP PC gt SSP SSP 4 5 SSP SR SSP SSP 2 5 SSP vector gt PC Enter the stopped state waiting for the interrupts The condition is tested If true the operations after then are performed If the condition is false and the optional else clause is present the opera tions after else are performed If the condition is false and else is omitted the instruction performs no operation Refer to the
168. e window time period the level recognized by the processor is not predictable however the processor always resolves the latched level to either a logic high or low before using it In addition to meeting input setup and hold times for deterministic operation all input signals must obey the protocols described in this section pe For IC ORO USER S MANWAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bus Operation tsu Ho da CLK ISOLDA YY SAMPLE WINDOW Figure 7 2 Asynchronous Input Sample Window A device with a 32 bit port size can also provide a synchronous mode transfer In synchronous operation input signals are externally synchronized to the processor clock and the synchronizing delay is not incurred Synchronous inputs STERM CBACK and CIIN must remain stable during a sample window for all rising edges of the clock during a bus cycle i e while address strobe AS is asserted regardless of when the signals are asserted or negated to ensure proper operation This sample window is defined by the synchronous input setup and hold times see MC68030EC D MC68030 Electrical Specifications 7 1 1 Bus Control Signals The external cycle start ECS signal is the earliest indication that the processor is initiating a bus cycle The MC68030 initiates a bus cycle by driving the address size function code read write and cache inhibit out outputs and by asserting ECS However
169. ea An 8 16 32 source destination 16 32 gt 32 list ea list 16 32 listed registers destination 16 32 gt 32 source gt listed registers MOVEP Dn d4g An 16 32 Dn 31 24 gt An d Dn 23 16 gt An d 2 Dn 15 8 gt An d 4 Dn 7 0 gt An d 6 d45 An Dn An d gt Dn 31 24 An d 2 gt Dn 23 16 An d 4 gt Dn 15 8 An d 6 gt Dn 7 0 MOVEQ data Dn 8 5 32 immediate data destination PEA ea 32 SP 4 5 SP ea SP UNLK An 32 An gt SP SP gt An SP 4 gt SP 3 2 2 Integer Arithmetic Instructions The integer arithmetic operations include the four basic operations of add ADD subtract SUB multiply MUL and divide DIV as well as arithmetic compare CMP CMPM CMP2 clear CLR and negate NEG The instruction set includes ADD CMP and SUB instructions for both address and data operations with all operand sizes valid for data operations Address operands consist of 16 or 32 bits The clear and negate instructions apply to all sizes of data operands Signed and unsigned MUL and DIV instructions include Word multiply to produce a long word product Long word multiply to produce and long word or quad word product Division of a long word divided by a word divisor word quotient and word remainder Division of a long word or quad word dividend by a long word divisor long word quo tient and long word remainder A set of extended instructions pro
170. eceive three bytes in the current bus cycle A 16 or 8 bit lz slave can only receive one byte The table defines the byte enables for all port sizes Byte data strobes can be obtained by combining the enable signals with the data strobe signal Devices residing on 8 bit ports can use the data strobe by itself since there is only one valid byte for every transfer These enable or strobe signals select only the bytes required for write cycles or for noncachable read cycles The other bytes are not selected which prevents incorrect accesses in sensitive areas such as I O Figure 7 18 shows a logic diagram for one method for generating byte data enable signals for 16 and 32 bit ports from the size and address encodings and the read write signal NO For Mo ARIA RIN OM ANNE Product MS Go to www freescale com Bus Operation Freescale Semiconductor Inc 7 2 5 MC68030 versus MC68020 Dynamic Bus Sizing The MC68030 supports the dynamic bus sizing mechanism of the MC68020 for asynchronous bus cycles terminated with DSACKx with two restrictions First for a cachable access within the boundaries of an aligned long word the port size must be consistent throughout the transfer of each long word For example when a byte port resides at address 00 addresses 01 02 and 03 must also correspond to byte ports Second the port must supply as much data as it signals as port size regardless of the transfer size indicated with the size signals and the
171. ection applies to write cycles as well as to read cycles DS is not asserted for two clock synchronous write cycles therefore the clock CLK may be used as the timing signal for latching the data In addition there is no time from the latest assertion of AS and the required assertion of STERM for any two clock synchronous bus cycle The system must qualify a memory write with the assertion of AS to ensure that the write is not aborted by internal conditions within the MC68030 MOTOROLA For Mol4Qp3030 USER ion On AUS Product fes Go to www freescale com Bus Operation Freescale Semiconductor Inc Figure 7 33 is a flowchart of a synchronous write cycle Figure 7 34 is a functional timing diagram of this operation with wait states CONTROLLER EXTERNAL DEVICE ADDRESS DEVICE ASSERT ECS OCS FOR ONE HALF CLOCK DRIVE ADDRESS ON A31 A0 DRIVE FUNCTION ON FC2 FCO DRIVE SIZE SIZ1 SIZ0 FOUR BYTES SET RAW TO WRITE CACHE INHIBIT OUT CIOUT BECOMES VALID ASSERT ADDRESS STROBE AS ASSERT DATA BUFFER ENABLE DBEN ASSERT DATA BUFFER ENABLE DBEN DRIVE DATA LINES D31 DO ACCEPT DATA ASSERT DATA STROBE DS IF WAIT STATES xo NO O Bb OI N o o 1 DECODE ADDRESS 2 STORE DATA ON D31 D0 3 ASSERT SYNCHRONOUS TERMINATION STERM TERMINATE OUTPUT TRANSFER 1 NEGATE AS AND DS 2 REMOVE DATA FROM D31 0 3 NEGATE DBEN TERMINATE CYCLE 1 NEGATE STERM START NEXT CYCLE Figure 7 33 Synchron
172. ecution to be overlapped In addition to instruction execution the internal caches the on chip MMU and the external bus controller all operate in parallel The MC68030 fully supports the nonmultiplexed bus structure of the MC68020 with 32 bits of address and 32 bits of data The MC68030 bus has an enhanced controller that supports both asynchronous and synchronous bus cycles and burst data transfers It also supports the MC68020 dynamic bus sizing mechanism that automatically determines device port sizes on a cycle by cycle basis as the processor transfers operands to or from external devices A block diagram of the MC68030 is shown in Figure 1 1 The instructions and data required by the processor are supplied from the internal caches whenever possible The MMU translates the logical address generated by the processor into a physical address utilizing its address translation cache ATC The bus controller manages the transfer of data between the CPU and memory or devices at the physical address MOTOROLA For More datori atrar ion on This Product v Go to www freescale com Freescale Semiconductor Inc Introduction STVNDIS lOH1NOO SNA sna SQvd ylva vivd sna ylva TVNW3ANI sna SSquadav viva d3X3ld WU3TIOHLNOO SNAOHIIN u3d4ng gina ONIGNAd HO13338d ONIGNAd SLIM YATIOYLNOO SNA LNAWND NOILOAS NOLLO3S YSLNNOO Ss3uadav
173. ed for address operands of 16 or 32 bits The control registers SR VBR SFC DFC CACR CAAR CRP SRP TC TT0 TT1 and MMUSR vary in size according to function Coprocessors may define unique operand sizes and support them with on chip registers accordingly 2 2 1 Data Registers Each data register is 32 bits wide Byte operands occupy the low order 8 bits word operands the low order 16 bits and long word operands the entire 32 bits When a data register is used as either a source or destination operand only the appropriate low order byte or word in byte or word operations respectively is used or changed the remaining high order portion is neither used nor changed The least significant bit of a long word integer is addressed as bit zero and the most significant bit is addressed as bit 31 For bit fields the most significant bit is addressed as bit zero and the least significant bit is addressed as the width of the field minus one If the width of the field plus the offset is greater than 32 the bit field wraps around within the register The following illustration shows the organization of various types of data in the data registers Quad word data consists of two long words for example the product of 32 bit multiply or the quotient of 32 bit divide operations signed and unsigned Quad words may be organized in any two data registers without restrictions on order or pairing There are no explicit instructions for the managment of t
174. eee eee 9 54 9 7 3 Transparent Translation Registers 00 20000eee 9 57 9 7 4 MMU Status Register 2 5 y sundae LADDER eS Ern rns 9 59 9 7 5 Register Programming Considerations 9 61 9 7 5 1 Register Side Effects au oe br toler ee ie oe eee eit 9 61 9 7 5 2 MMU Status Register Decoding s an anaana 9 61 9 7 5 3 MMU Configuration Exception s s s aaaea 9 62 9 8 Mmu Instructions o S rn erreurs tro Ete eei ae a ish a Seog 9 63 9 9 Defining and Using Page Tables in An Operating System 9 65 9 9 1 Root Pointer Registers orar bw Se ee Ra AB Pah 9 65 9 9 2 Task Memory Map Definition aaea 9 66 9 9 3 Impact of MMU Features On Table Definition 9 68 9 9 3 1 Number of Table Levels 000 e eee eee 9 68 9 9 3 2 Ama SUG OU ME na dates natus dor coe vie o eee ree gb eed B acea 9 69 9 9 3 3 Limit Fields CREER CLERI OL LII TT 9 70 9 9 3 4 Early Termination Page Descriptors 9 70 9 9 3 5 Indirect DESTINO RS ees emet o Id dose font Eis 9 71 9 9 3 6 Using Unused Descriptor Bits o oooocoooooooo 9 71 9 10 An Example of Paging Implementation in an Operating System 9 72 9 10 1 System Description ee a ana ah Ra ate See nya npe lae 9 72 9 10 2 Allocation BOB unu dedos d Sar a e Serie 9 78 9 10 3 Bus Error Handler Routine 00 0 2 cee sues 9 82 Section 10 Coprocessor Interface Description xxxi MC68030 USER S MANUAL MOTOROL
175. en CIOUT is asserted the data cache is completely ignored even on write cycles operating in the write allocation mode Also note that since the CIIN signal is ignored on write cycles cache entries may be created for noncachable data when CIIN is asserted on a write when operating in the write allocation mode Figure 6 4 shows the manner in which each mode operates in five different situations TAG LOGICAL ADDRESS FC2 FCO A31 A8 A7 A4 A3 A2 LINE SELECT USER DATA 000010 b0 b3 VO 1 b4 b7 V1 20 b8 bB V2 1 bC bF V3 1 5 TAG NO WRITE ALLOCATE WRITE ALLOCATE EXAMPLE 1 USER WORD WRITE OF b2 b3 to 00001052 A START EXTERNAL CYCLE A START EXTERNAL CYCLE CACHE HIT ALWAYS UPDATE CACHE AND MEMORY B b2 b3 lt b2 b3 B b2 b3 lt b2 b3 EXAMPLE 2 A START EXTERNAL CYCLE A START EXTERNAL CYCLE B b8 b9 lt b8 b9 B b8 b9 lt b8 b9 USER LONG WORD WRITE OF b6 b9 to 00001056 TAG MATCH LONG WORD DATA MISALIGNED b6 b7 RESULT IN A CACHE MISS b8 b9 RESULT IN A CACHE HIT Figure 6 4 No Write Allocation and Write Allocation Mode Examples dde For MUSEU USER S MANYAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc chio Cache Membres 6 1 2 2 READ MODIFY WRITE ACCESSES The read portion of a read modify write cycle is always forced to miss in the data cache However if the system allows internal caching of read modify write cycle opera
176. ent operation of the on chip caches relative to the operation of the bus controller many subsequent instructions can be executed resulting in seemingly nonsequential instruction execution When this is not desired and the system depends on sequential execution following bus activity the NOP instruction can be used The NOP instruction forces instruction and bus synchronization in that it freezes instruction execution until all pending bus cycles have completed An example of the use of the NOP instruction for this purpose is the case of a write operation of control information to an external register where the external hardware attempts to control program execution based on the data that is written with the conditional assertion of BERR If the data cache is enabled and the write cycle results in a hit in the data cache the cache is updated That data in turn may be used in a subsequent instruction before the external write cycle completes Since the MC68030 cannot process the bus error until the end of the bus cycle the external hardware has not successfully interrupted program execution To prevent a subsequent instruction from executing until the external cycle completes a NOP instruction can be inserted after the instruction causing the write In this case bus error exception processing proceeds immediately after the write before subsequent instructions are executed This is an irregular situation and the use of the NOP instruction for this
177. eptii eri erori minina a tes DA DEN ot tte RR MC68030 USER S MANUAL For More Information On This Product Go to www freescale com Page Number 7 13 7 19 7 22 7 24 7 24 7 26 7 27 7 28 7 29 7 30 7 31 7 37 7 43 7 48 7 51 7 54 7 59 7 68 7 69 7 70 7 71 7 74 7 74 7 74 7 75 7 82 7 89 7 91 7 94 7 95 7 96 7 98 7 99 7 100 7 100 7 103 XXIX Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Page Number Title Number 8 1 3 Address Error Exception 000 0c eee eee o 8 8 8 1 4 Instruction Trap Exception 0000 cece eee eee ee 8 9 8 1 5 Illegal Instruction and Unimplemented Instruction Exceptions 8 9 8 1 6 Privilege Violation Exception c s optar 8 11 8 1 7 race EXOSDIIOE o s ou Ghee en ooo p o t ees E dp e ions 8 12 8 1 8 Format Error Exception aceto beret os Feet eese ties 8 14 8 1 9 Interrupt Exceptions vacuo d dere ori ora re Paths Ress 8 14 8 1 10 MMU Configuration Exception s asasan cee eee eee 8 21 8 1 11 Breakpoint Instruction Exception 0000e ee eae 8 22 8 1 12 Multiple EXCepliGns ti dinette tease es em Robe on Ee Pee gis 8 23 8 1 13 Retur from EXeepllOh ne sena sie oe Bee ant Lee EE Ere 8 24 8 2 Bus Fault Recovery Xa enc bine a Re a NN 8 27 8 2 1 Special Status Word SSW 2 0 2 2 8 28 8 2 2 Using Software to Complete the Bus Cycles 8 29 8 2 3 Completing the Bus Cycles with Rte ooooooooo
178. er displacements for both addresses However coprocessor instructions can have any number of extension words Refer to the coprocessor instruction formats in Section 10 Coprocessor Interface Description For effective addresses that use the full format the index suppress IS bit and the index indirect selection I IS field determine the type of indexing and indirection Table 2 1 lists the indexing and indirection operations corresponding to all combinations of IS and I IS values Table 2 1 IS 1 1S Memory Indirection Encodings IS Index Indirect Operation 0 000 No Memory Indirection 0 001 Indirect Preindexed with Null Outer Displacement 0 010 Indirect Preindexed with Word Outer Displacement 0 011 Indirect Preindexed with Long Outer Displacement 0 100 Reserved 0 101 Indirect Postindexed with Mull Outer Displacement 0 110 Indirect Postindexed with Word Outer Displacement 0 111 Indirect Postindexed with Long Outer Displacement 1 000 No Memory Indirection 1 001 Memory Indirect with Mull Outer Displacement 1 010 Memory Indirect with Word Outer Displacement 1 011 Memory Indirect with Long Outer Displacement 1 100 111 Reserved aw For More Information On This Product USOS Go to www freescale com Freescale Semicondygtorsdnsiu Addressing Capabilities Single Effective Address Instruction Format 15 14 13 12 11 10 9 8 7 6 5 0 EFFECTIVE ADDRESS MODE REGISTER Brief Format Extension Word 15 14 12 11 10 9 8 7 0 D A R
179. ers with individual register names separated by a slash and or contiguous blocks of registers specified by the first and last register names separated by a dash 4 A list of any combination of the three floating point system control registers FPCR FPSR and FPIAR with indvidual register names separated by a slash 5 Where d is direction L or R 3 24 MOTOROLA For Mare formation Un This Product Go to www freescale com Freescale Semiconductor INC struction Set Summiary 3 5 INSTRUCTION EXAMPLES The following paragraphs provide examples of how to use selected instructions 3 5 1 Using the CAS and CAS2 Instructions The CAS instruction compares the value in a memory location with the value in a data register and copies a second data register into the memory location if the compared values are equal This provides a means of updating system counters history information and globally shared pointers The instruction uses an indivisible read modify write cycle after CAS reads the memory location no other instruction can change that location before CAS has written the new value This provides security in single processor systems in multitasking environments and in multiprocessor environments In a single processor system the operation is protected from instructions of an interrupt routine In a multitasking environment no other task can interfere with writing the new value of a system variable In a multiprocessor e
180. ertain instructions operate on specific registers These instructions imply the required registers 3 2 INSTRUCTION SUMMARY The instructions form a set of tools to perform the following operations Data Movement Bit Field Manipulation Integer Arithmetic Binary Coded Decimal Arithmetic Logical Program Control Shift and Rotate System Control Bit Manipulation Multiprocessor Communications Each instruction type is described in detail in the following paragraphs a For MUSEU USERS MANYAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary The following notations are used in this section In the operand syntax statements of the instruction definitions the operand on the right is the destination operand An Dn Rn CCR cc SR SP USP ISP MSP SSP DFC SFC Rc MRc MMUSR B W L D FPm FPn PFcr k d ea list data offset width label m m n MOTOROLA any address register A7 AO any data register D7 DO any address or data register condition code register lower byte of status register condition codes from CCR status register active stack pointer user stack pointer supervisor interrupt stack pointer supervisor master stack pointer supervisor master or interrupt stack pointer destination function code register source function code register control register VBR SFC DFC CACR
181. ess in D2 into register A2 The next instruction a CLR instruction clears register DO to zero The CAS2 instruction compares the address in D1 to the LIST GET pointer and to the address in register A2 If the pointers have not been updated the CAS2 instruction loads the address in D2 into the LIST GET pointer and zero into the address in register A2 For Mare formation Un This Product MOS EA Go to www freescale com Freescale Semiconductor Inc cio Set Summary DINSERT ALLOCATE NEW LIST ENTRY LOAD ADDRESS INTO A2 LEA LIST PUT A0 LOAD ADDRESS OF HEAD POINTER INTO A0 LEA LIST GET A1 LOAD ADDRESS OF TAIL POINTER INTO A1 MOVE A2 D2 LOAD NEW ENTRY POINTER INTO D2 MOVE L A0 DO LOAD POINTER TO HEAD ENTRY INTO DO TST L DO IS HEAD POINTER NULL 0 ENTRIES IN LIST DILOOP BEQ DIEMPTY IF SO WE NEED ONLY TO ESTABLISH POINTERS MOVE L DO NEXT A2 PUT HEAD POINTER INTO FORWARD POINTER OF NEW ENTRY CLRL D1 PUT NULL POINTER VALUE INTO D1 MOVE L D1 LAST A2 PUT NULL POINTER IN BACKWARD POINTER OF NEW ENTRY LEA LAST D0 A1 LOAD BACKWARD POINTER OF OLD HEAD ENTRY INTO A1 CAS2 L D0 D1 D2 D2 A0 A1 IF WE STILL POINT TO OLD HEAD ENTRY UPDATE POINTERS BNE DILOOP IF NOT TRY AGAIN BRA DIDONE DIEMPTY MOVE L DO NEXT A2 PUT NULL POINTER IN FORWARD POINTER OF NEW ENTRY MOVE L DO LAST A2 PUT NULL POINTER IN BACKWARD POINTER OF NEW ENTRY CAS2 L D0 D0 D2 D2 A0 A1 IF WE STILL HAVE NO ENTRIES SET BOTH POINTERS TO THIS ENT
182. ess to operating system services for user programs moe For Mold jetorimatien On This Product 49 Go to www freescale com Processing States Freescale Semiconductor Inc The bus cycles for an instruction executed at the user privilege level are classified as user references and the values of the function codes on FCO FC2 specify user address spaces The memory management unit of the processor when it is enabled uses the value of the function codes to distinguish between user and supervisor activity and to control access to protected portions of the address space While the processor is at the user level references to the system stack pointer implicitly or to address register seven A7 explicitly refer to the user stack pointer USP 4 1 3 Changing Privilege Level To change from the user to the supervisor privilege level one of the conditions that causes the processor to perform exception processing must occur This causes a change from the user level to the supervisor level and can cause a change from the master mode to the interrupt mode Exception processing saves the current values of the S and M bits of the status register along with the rest of the status register on the active supervisor stack and then sets the S bit forcing the processor into the supervisor privilege level When the exception being processed is an interrupt and the M bit is set the M bit is cleared putting the processor into the interrupt mode Execution
183. essor issues no new control signals during S4 State 5 The processor negates AS and DS during S5 It holds the address and data valid during S5 to provide address hold time for memory systems R W SIZO SIZ1 FCO FC2 and DBEN also remain valid throughout S5 The external device must keep DSACKx asserted until it detects the negation of AS or DS whichever it detects first The device must st negate DSACKx within approximately one clock period after sensing the negation of AS or DS DSACKx signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle s For More informatio ion a YANYAL Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bus Operation 7 3 3 Asynchronous Read Modify Write Cycle The read modify write cycle performs a read conditionally modifies the data in the arithmetic logic unit and may write the data out to memory In the MC68030 processor this operation is indivisible providing semaphore capabilities for multiprocessor systems During the entire read modify write sequence the MC68030 asserts the RMC signal to indicate that an indivisible operation is occurring The MC68030 does not issue a bus grant BG signal in response to a bus request BR signal during this operation The read portion of a read modify write operation is forced to miss in the data cache because the data in the cache would not be valid if another processor had altered the value be
184. estination else TRAP MOVE SR ea MOVE to SR If supervisor state then Source gt SR else TRAP MOVE ea SR MOVE USP If supervisor state then USP gt An or An gt USP else TRAP MOVE USP An MOVE An USP MOVEC If supervisor state then Rc gt Rn or Rn gt Rc else TRAP MOVEC Rc Rn MOVEC Rn Rc Registers Destination Source gt Registers MOVEM register list ea MOVEM ea register list MOVEP Source Destination MOVEP Dx d Ay MOVEP d Ay Dx MOVEQ Immediate Data Destination MOVEQ data Dn Se For Mor information On this Product HU Go to www freescale com Freescale Semiconductor Inc cio set Summary Table 3 14 Instruction Set Summary Sheet 4 of 5 Opcode Operation Syntax MOVES If supervisor state MOVES Rn ea MOVES ea Rn then Rn gt Destination DFC or Source SFC gt Rn else TRAP MULS Source y Destination gt Destination MULS W ea Dn 16x16 gt 32 MULS L ea DI 32 x 32 gt 32 MULS L ea Dh DI 32 x 32 gt 64 MULU Source y Destination gt Destination MULU W ea Dn 16 x 16 gt 32 MULU L ea DI 32 x 32 gt 32 MULU L ea Dh DI 32 x 32 gt 64 0 Destination10 X gt Destination 0 Destination Destination 0 Destination X Destination OR Source V Destination Destination OR ea Dn OR Dn ea ORI Immediate Data V Destination gt Destination ORI data ea ORI Source V CCR C
185. f an index register The processor accesses a long word at that address and adds the optional outer displacement od to yield the effective address The value of the PC is the address of the first extension word The reference is a program space reference and is only allowed for reads refer to 4 2 Address Space Types In the syntax for this mode brackets enclose the values used to calculate the intermediate memory address All four user specified values are optional However the user must supply the assembler notation ZPC zero value is taken for the PC to indicate that the PC is not used This allows the user to access the program space without using the PC in calculating the effective address Both the base and outer displacements may be null word or long word When a displacement is omitted or an element is suppressed its value is taken as zero in the effective address calculation GENERATION EA bd PC Xn SIZE SCALE od ASSEMBLER SYNTAX bd PC Xn SIZE SCALE 0d MODE 111 REGISTER FIELD 011 31 0 31 0 BASE DISPLACEMENT SIGN EXTENDEDVALUE VALUE O INDEX REGISTER SIGN EXTENDEDVALUE EXTENDED VALUE SCALEVALUE VALUE IO 0 INDIRECT MEMORY X RENS POINTS TO 31 0 VALUE AT INDIRECT MEMORY ADDRESS IN PROGRAM SPACE 0 31 OUTER DISPLACEMENT SIGN EXTENDED VALUE 31 0 NUMBER OF EXTENSION WORDS 1 2 3 40R5 MOTOROLA For mo Rae RR on Aus P Product enm Go to www freescale com Data Org
186. g the write portion of a read modify write cycle ignore the assertion of the CIIN signal and may cause the data cache to be altered depending on the state of the cache whether or not the write cycle hits the state of the WA bit in the CACR and the conditions indicated by the MMU The occurrence of a bus error while attempting to load a cache entry aborts the entry fill operation but does not necessarily cause a bus error exception If the bus error occurs on a read cycle for a portion of the required operand not the remaining bytes of the cache entry to be loaded into the data cache the processor immediately takes a bus error exception If MOTOROLA For Mo matias ion On AUS Product geh Go to www freescale com On Chip Cache Memories Freescale Semiconductor Inc the read cycle in error is made only to fill the data cache the data is not part of the target operand no exception occurs but the corresponding entry is marked invalid For the instruction cache the processor marks the entry as invalid but only takes an exception if the execution unit attempts to use the instruction word s 6 1 3 2 BURST MODE FILLING Burst mode filling is enabled by bits in the cache control register The data burst enable bit must be set to enable burst filling of the data cache Similarly the instruction burst enable bit must be set to enable burst filling of the instruction cache When burst filling is enabled and the corresponding cache is en
187. he execution of any instructions can cause exceptions External conditions such as interrupts bus errors and some coprocessor responses also cause exceptions Exception processing provides an efficient transfer of control to handlers and routines that process the exceptions A catastrophic system failure occurs whenever the processor receives a bus error or generates an address error while in the exception processing state This type of failure halts the processor For example if during the exception processing of one bus error another bus error occurs the MC68030 has not completed the transition to normal processing and has not completed saving the internal state of the machine so the processor assumes that the system is not operational and halts Only an external reset can restart a halted processor When the processor executes a STOP instruction it is in a special type of normal processing state one without bus cycles It is stopped not halted moe For Mold iteration On This Product td Go to www freescale com Processing States Freescale Semiconductor Inc 4 1 PRIVILEGE LEVELS The processor operates at one of two levels of privilege the user level or the supervisor level The supervisor level has higher privileges than the user level Not all processor or coprocessor instructions are permitted to execute in the lower privileged user level but all are available at the supervisor level This allows a separation of supervisor an
188. he transfer and the type of cycle The selected device then controls the length of the cycle with the signal s used to terminate the cycle Strobe signals one for the address bus and another for the data bus indicate the validity of the address and provide timing information for the data MOTOROLA For More datori atrar ion on This Product p Go to www freescale com Bus Operation Freescale Semiconductor Inc The bus can operate in an asynchronous mode identical to the MC68020 bus for any port width The bus and control input signals used for asynchronous operation are internally synchronized to the MC68030 clock introducing a delay This delay is the time period required for the MC68030 to sample an asynchronous input signal synchronize the input to the internal clocks of the processor and determine whether it is high or low Figure 7 1 shows the relationship between the clock signal and the associated internal signal of a typical asynchronous input SYNC DELAY gt Figure 7 1 Relationship between External and Internal Signals Furthermore for all asynchronous inputs the processor latches the level of the input during a sample window around the falling edge of the clock signal This window is illustrated in Figure 7 2 To ensure that an input signal is recognized on a specific falling edge of the clock that input must be stable during the sample window If an input makes a transition during th
189. his data type although the MOVEM instruction can be used to move a quad word into or out of the registers Binary coded decimal BCD data represents decimal numbers in binary form Although many BCD codes have been devised the BCD instructions of the M68000 Family support formats which the four least significant bits consist of a binary number having the numeric value of the corresponding decimal number Two BCD formats are used In the unpacked BCD format a byte contains one digit the four least significant bits contain the binary value and the four most significant bits are undefined Each byte of the packed BCD format contains two digits the least significant four bits contain the least significant digit s For More RORO NS BR Un his Product MOTOROLA C Go to www freescale com Freescale Semiconductors dne Addressing Capabilities Bit lt 0 Modulo Offset 31 Offset of 0 MSB 31 30 29 1 0 MSB eee LSB Byte 31 24 23 16 15 8 7 0 High Order Byte Middle High Byte Middle Low Byte Low Order Byte 16 Bit Word 31 16 15 0 High Order Word Low Order Word Long Word 31 0 Long Word Quad Word 63 62 32 MSB Any Dx 31 0 Offset MSB LSB Bit Field 0 lt Offset lt 32 0 lt Width lt 32 31 0 Long Word Note If width offset lt 32 bit filed wraps around within the register Unpacked BCD a MSB 31 8 7 6 5 4 3 2 1 0
190. hould continue and the assertion of CIIN indicates that the data latched at the end of S4 should not be cached and that the burst should abort State 5 The processor maintains all the signals on the bus driven throughout S5 for continuation of the burst The same hold times for STERM and data described for S3 apply here State 6 This state is identical to S4 except that once STERM is recognized the third long wordof data for the burst is latched at the end of S6 MOTOROLA For Mol4Qp3030 USER ion On AUS Product 169 Go to www freescale com Bus Operation Freescale Semiconductor Inc State 7 During this state the processor negates CBREQ and the memory device may negate CBACK Aside from this all other bus signals driven by the processor remain driven The same hold times for STERM and data described for S3 apply here State 8 This state is identical to S4 except that CBREQ is negated indicating that the processor cannot continue to accept more data after this The data latched at the end of S8 corresponds to the fourth long word of the burst State 9 The processor negates AS DS and DBEN during S9 It holds the address RW SIZ0 SIZ1 and FCO FC2 valid throughout S9 The same hold times for data described for S3 apply here Note that the address bus of the MC68030 remains driven to a constant value for the duration of a burst transfer operation including the first transfer before burst mod
191. information and 7 3 7 Burst Operation Cycles for bus cycle information pertaining to burst mode operations 5 7 4 Cache Burst Acknowledge CBACK This input signal indicates that the accessed device can operate in the burst mode and can supply at least one more long word for the instruction or data cache Refer to 7 3 7 Burst Operation Cycles for information about burst mode operation MOTOROLA For More iniormatiar ion on This Product n Go to www freescale com Signal Description Freescale Semiconductor Inc 5 8 INTERRUPT CONTROL SIGNALS The following signals are the interrupt control signals for the MC68030 5 8 1 Interrupt Priority Level Signals These input signals provide an indication of an interrupt condition and the encoding of the interrupt level from a peripheral or external prioritizing circuitry IPL2 is the most significant bit of the level number For example since the IPLn signals are active low IPLO IPL2 equal to 5 corresponds to an interrupt request at interrupt level 2 Refer to 8 1 9 Interrupt Exceptions for information on MC68030 interrupts 5 8 2 Interrupt Pending IPEND This output signal indicates that an interrupt request has been recognized internally and exceeds the current interrupt priority mask in the status register SR This output is for use by external devices coprocessors and other bus masters for example to predict processor operation on the following instruction boundaries Refer to 8
192. ing read However read modify write cycles may alter the contents of the data cache as described in 6 1 2 Data Cache No burst filling of the data cache occurs during a read modify write operation The test and set TAS and compare and swap CAS and CAS2 instructions are the only MC68030 instructions that utilize read modify write operations Depending on the compare results of the CAS and CAS2 instructions the write cycle s may not occur Table search accesses required for the MMU are always read modify write cycles to the supervisor data space During these cycles a write does not occur unless a descriptor is updated No data is internally cached for table search accesses since the MMU uses physical addresses to access the tables Refer to Section 9 Memory Management Unit for information about the MMU Figure 7 29 is a flowchart of the asynchronous read modify write cycle operation Figure 7 30 is an example of a functional timing diagram of a TAS instruction specified in terms of clock periods State 0 The processor asserts ECS and OCS in SO to indicate the beginning of an external operand cycle The processor also asserts RMC in SO to identify a read modify write cycle The processor places a valid address on A0 A31 and valid function codes on FCO FC2 The function codes select the address space for the operation SIZ0 SIZ1 become valid in SO to indicate the operand size The processor drives R W high for the read cycle and set
193. ion into one of its caches and can read in four long words In addition ECS and OCS if asserted is negated during S1 State 2 The selected device uses R W SIZO SIZ1 A0 A1 and CIOUT to place the data on the data bus The first cycle must supply the long word at the corresponding long word boundary All of the byte sections D24 D31 D16 D23 D8 D15 and DO D7 of the data bus must be driven since the burst operation latches 32 bits on every cycle During S2 the processor drives DBEN active to enable external data buffers In systems that use two clock synchronous bus cycles the timing of DBEN may prevent its use At the beginning of S2 the processor tests the level of STERM If STERM is recognized the processor latches the incoming data at the end of S2 For the burst operation to proceed CBACK must be asserted when STERM is recognized If the data for the current cycle is MOTOROLA For Mol4Qp3030 USER ion On AUS Product 708 Go to www freescale com Bus Operation Freescale Semiconductor Inc CONTROLLER EXTERNAL DEVICE ADDRESS DEVICE 1 ASSERT ECS OCS FOR ONE HALF CLOCK 2 DRIVE R W TO READ 3 DRIVE ADDRESS ON A31 A0 4 DRIVE FUNCTION ON FC2 FCO 5 DRIVE SIZE SIZ1 SIZO FOUR BYTES 6 CACHE INHIBIT OUT CIOUT BECOMES VALID 7 ASSERT ADDRESS STROBE AS 8 ASSERT CACHE BURST REQUEST CBREQ 9 ASSERT DATA STROBE DS PRESENT DATA 0 1 ASSERT DATA BUFFER ENABLE DBEN
194. is asserted BERR is then asserted within one clock cycle HALT remains negated BERR is asserted and recognized on the next falling clock edge following the rising clock edge on which STERM is asserted and recognized HALT remains negated When the processor recognizes a bus error condition it terminates the current bus cycle in the normal way Figure 7 49 shows the timing of a bus error for the case in which neither DSACKx nor STERM is asserted Figure 7 50 shows the timing for a bus error that is asserted after DSACKx Exceptions are taken in both cases Refer to 8 1 2 Bus Error Exception for details of bus error exception processing When BERR is asserted during a read cycle that supplies data to either on chip cache the data in the cache is marked invalid However when a write cycle that writes data into the data cache results in an externally generated bus error the data in the cache is not marked invalid In the second case where BERR is asserted after DSACKx is asserted BERR must be asserted within specification 48 refer to MC68030EC D MC68030 Electrical Specifications for purely asynchronous operation or it must be asserted and remain stable during the sample window defined by specifications 27A and 47B around the next falling edge of the clock after DSACKx is recognized If BERR is not stable at this time the processor may exhibit erratic behavior BERR has priority over DSACKx In this case data may be p
195. ith subscript addr An Rn scale Absolute address subscript with variable index Program Relative d For More RORO NS BR Un his Product MOTOROLA C Go to www freescale com Freescale Semiconductors dne Addressing Capabilities disp PC Simple PC relative disp PC Rn PC relative with variable index disp PC Rn scale PC relative with subscript Memory Pointer preindexed Memory pointer directly to data operand preindexed disp Memory pointer as base with displacement to data operand postindexed Rn Memory pointer with variable index postindexed disp Rn Memory pointer with constant and variable index postindexed Rn scale Memory pointer subscripted postindexed disp Rn scale Memory pointer subscripted with constant index MOTOROLA For Mo matias ion On AUS Product 299 Go to www freescale com Data Organization and add ARGEFAA Semiconductor Inc 2 7 M68000 FAMILY ADDRESSING COMPATIBILITY Programs can be easily transported from one member of the M68000 Family to another in an upward compatible fashion The user object code of each early member of the family is upward compatible with newer members and can be executed on the newer microprocessor without change The address extension word s are encoded with the information that allows the MC68020 MC68030 to distinguish the new address extension words for the early MC68000 MC68008 MC68010 microprocessors and for the newer
196. jetorimatien On This Product No Go to www freescale com Freescale Semiconductor Inc SECTION 2 DATA ORGANIZATION AND ADDRESSING CAPABILITIES Most external references to memory by a microprocessor are either program references or data references they either access instruction words or operands data items for an instruction Program references are references to the program space the section of memory that contains the program instructions and any immediate data operands that reside in the instruction stream Refer to M68000PM AD M68000 Programmer s Reference Manual for descriptions of the instructions in the program space Data references refer to the data space the section of memory that contains the program data Data items in the instruction stream can be accessed with the program counter relative addressing modes and these accesses are classified as program references A third type of external reference used for coprocessor communications interrupt acknowledge cycles and breakpoint acknowledge cycles is classified as a CPU space reference The MC68030 automatically sets the function codes to access the program space the data space or the CPU space for special functions as required The function codes can be used by the memory management unit to organize separate program read only and data read write memory areas This section describes the data organization and addressing capabilities of the MC68030 It lists the types of oper
197. knowledge CBACK Interrupt Control Signals 0 ine Dx ER Yaw Eee wee Interrupt Priority Level Signals llle Interrupt Pending IPEND 2i seii APRhenti bebe ocean es Autovector AVEC un sand ota brote tese ird t Sean OP y teda Bus Arbitration Control Signals is ao a EX ERES Bus Request BR 0 00 cc ccc cece cence eens Bus Grant BG 225 rok wae Naa wal ted teh ewe bea A Leia ei E Bus Grant Acknowledge BGACK 00000 eee eee Bus Exception Control SignalS oocococconnooo HSSOL THESE Ista niece Mee ore eee bab ont ole ie es alb EAT hens ca ara O tren tart abo ust oS BUS Bor BERE iS BUNGA MUS E hace eR Emulator Support Signals cee eee eee Cache Disable CDIS 1 4 ecco be ene a fhe hs be canes ks MMU Disable MMUDIS Kawa hes win Pt Rr eee Pipeline Refill REFERS maan eame RETI A REPE IT Internal Microsequencer Status STATUS MC68030 USER S MANUAL For More Information On This Product Go to www freescale com Page Number 4 6 4 7 5 10 5 10 5 10 5 10 5 10 xxvii Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Page NE Title Number 5 12 ee Sif quor 5 11 5 13 Power Supply Connections a 5 11 5 14 Signal Summa rese A Gane e se eru ra a 5 11 Section 6 On Chip Cache Memories 6 1 On Chip Cache Organization and Operation 6 3 6 1 1 I isirictien Cache astas Bote
198. l the controls to access and enable the special features of the MC68030 This segregation was carefully planned so that all application software is written to run at the nonprivileged user level and migrates to the MC68030 from any M68000 platform without modification Since system software is usually modified by system programmers when ported to a new design the control features are properly placed in the supervisor programming model For example the transparent translation feature of the MC68030 is new to the family supervisor programming model for the MC68030 and the two translation registers are new additions to the family supervisor programming model for the MC68030 Only supervisor code uses this feature and user application programs remain unaffected MOTOROLA For More datori atrar ion on This Product a Go to www freescale com Introduction Freescale Semiconductor Inc Registers DO D7 are used as data registers for bit and bit field 1 to 32 bits byte 8 bit word 16 bit long word 32 bit and quad word 64 bit operations Registers A0 A6 and the user interrupt and master stack pointers are address registers that may be used as software stack pointers or base address registers Register A7 shown as A7 and A7 in Figure 1 3 is a register designation that applies to the user stack pointer in the user privilege level and to either the interrupt or master stack pointer in the supervisor privilege level In the supervisor
199. le Semiconductor Inc lt INDIVISIBLE CYCLE gt lt NEXT CYCLE Figure 7 30 Asynchronous Byte Read Modify Write Cycle 32 Bit Port TAS Instruction with CIOUT or CIIN Asserted 5i For MUS ARO USOS UA NIAE Product Moreno Go to www freescale com Freescale Semiconductor Inc Bus Operation State 6 The processor asserts ECS and OCS in S6 to indicate that another external cycle is beginning The processor drives R W low for a write cycle CIOUT also becomes valid indicating the state of the MMU Cl bit in the address translation descriptor or in a relevant TTX register Depending on the write operation to be performed the address lines may change during S6 State 7 In S7 the processor asserts AS indicating that the address on the address bus is valid The processor also asserts DBEN which can be used to enable data buffers during S7 In addition the ECS and OCS if asserted signal is negated during S7 State 8 During S8 the processor places the data to be written onto DO D31 State 9 The processor asserts DS during S9 indicating that the data is stable on the data bus As long as at least one of the DSACKx signals is recognized by the end of S8 meeting the asynchronous input setup time requirement the cycle terminates one clock later If DSACKx is not recognized by the start of S9 the processor inserts wait states instead of proceeding to S10 and S11 To ensure that wait states are inserted b
200. ler requests a burst mode operation to replace an entire cache line The cache control register CACR is accessible by supervisor programs to control the operation of both caches System hardware can assert the cache disable CDIS signal to disable both caches The assertion of CDIS disables the caches regardless of the state of the enable bits in CACR CDIS is primarily intended for use by in circuit emulators Another input signal cache inhibit in CIIN inhibits caching of data reads or instruction prefetches on a bus cycle by bus cycle basis Examples of data that should not be cached are data for I O devices and data from memory devices that cannot supply a full port width of data regardless of the size of the required operand Subsequent paragraphs describe how CIIN is used during the filling of the caches An output signal cache inhibit out CIOUT reflects the state of the cache inhibit Cl bit from the MMU of either the address translation cache entry that corresponds to a specified logical address or the transparent translation register that corresponds to that address Whenever the appropriate CI bit is set for either a read or a write access and an external bus cycle is required CIOUT is asserted and the instruction and data caches are ignored for the access This signal can also be used by external hardware to inhibit caching in external caches Whenever a read access occurs and the required instruction word or data o
201. les 7 19 7 7 Data Bus Write Enable Signals for Byte Word and Long Word Ports 7 23 7 8 DSACK BERR and HALT Assertion Results 7 79 7 9 STERM BERR and HALT Assertion Results 7 81 8 1 Exception Vector Assignments Sheet20f2 8 2 8 2 Exception Vector Assignments Sheet 1 0f2 8 3 8 3 Microsequencer STATUS Indications a 8 4 8 4 Tracing Control fics Je area aout bok ee NING SS EE eis She KA 8 13 8 5 Interrupt Levels and Mask Values 2 2 2 8 16 8 6 Exception Priority Groups sere Ad Sele Bee Ka MES etes 8 24 MOTOROLA MC68030 USER S MANUAL xlii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LIST OF TABLES Continued Table Title Number 9 1 Size Restrictions llli 9 2 Translation Tree Selection eese 9 3 MMUSR Bit Definitions lille 10 1 OD TRHAPOOODIIDUS 23 ke paaa Kam ABA ae 10 2 Coprocessor Format Word Encodings 10 3 Null Coprocessor Response Primitive Encodings 10 4 Valid EffectiveAddress Codes 10 5 Main Processor Control Register 10 6 Exceptions Related to Primitive Processing 12 1 Data Bus Activity for Byte Word and Long Word Ports 12 2 Memory Access Time Equations at 20 MHz 12 3 Calculated taypy Values for Operation at
202. les for which it is bus master The following conditions must be met for an external device to assume mastership of the bus through the normal bus arbitration procedure It must have received BG through the arbitration process AS must be negated indicating that no bus cycle is in progress and the external device must ensure that all appropriate processor signals have been placed in the high imped ance state by observing specification 7 in MC68030EC D MC68030 Electrical Spec ifications The termination signal DSACKx or STERM for the most recent cycle must have be come inactive indicating that external devices are off the bus optional refer to 7 7 3 Bus Grant Acknowledge BGACK must be inactive indicating that no other bus master has claimed ownership of the bus Figure 7 59 is a flowchart showing the detail involved in bus arbitration for a single device Figure 7 60 is a timing diagram for the same operation This technique allows processing of bus requests during data transfer cycles The timing diagram shows that BR is negated at the time that BGACK is asserted This type of operation applies to a system consisting of the processor and one device capable of bus mastership In a system having a number of devices capable of bus mastership the bus request line from each device can be wire ORed to the processor In such a system more than one bus request can be asserted simultaneously The timing diagram in Figure
203. me sequence STERM rather than DSACKx is asserted by the addressed external device to terminate a synchronous read cycle Since STERM must meet the synchronous setup and hold times with respect to all rising edges of the clock while AS is asserted it does not need to be synchronized by the processor Only devices with 32 bit ports may assert STERM STERM is also used with the CBREQ and CBACK signals during burst mode operation It provides atwo clock minimum bus cycle for 32 bit ports and single clock minimum burst accesses although wait states can be inserted for these cycles as well Therefore a synchronous cycle terminated with STERM with one wait cycle is a three clock bus cycle However note that STERM is asserted one half clock later than DSACKx would be for a similar asynchronous cycle with zero wait cycles also three clocks Thus if dynamic bus sizing is not needed STERM can be used to provide more decision time in an external cache design than is available with DSACKx for three clock accesses Figure 7 31 is a flowchart of a synchronous long word read cycle Byte and word operations are similar Figure 7 32 is a functional timing diagram of a synchronous long word read cycle For Mare formation Un This Product MOTOBOLA Go to www freescale com Freescale Semiconductor Inc Bus Operation CONTROLLER EXTERNAL DEVICE ADDRESS DEVICE ASSERT ECS OCS FOR ONE HALF CLOCK DRIVE RW TO READ DRIVE ADDRESS
204. n 1 gt Compare 1 Destination 2 gt Compare 2 CHK If Dn 0 or Source then TRAP CHK ea Dn CHK2 If Rn lower bound or CHK2 ea Rn Rn gt upper bound then TRAP CLR 0 gt Destination CLR ea CMP Destination Source cc CMP ea Dn CMPA Destination Source CMPA ea An CMPI Destination Immediate Data CMPI data ea CMPM Destination Source gt cc CMPM Ay Ax CMP2 Compare Rn lower bound or CMP2 ea Rn Rn upper bound and Set Condition Codes cpBcc If cpcc true then scanPC d gt PC cpBcc label cpDBcc If cpcc false then Dn 1 gt Dn cpDBcc Dn label if Dn z 1 then scanPC d gt PC cpGEN Pass Command Word to Coprocessor cpGEN parameters as defined by coprocessorL cpRESTORE If supervisor state cpRESTORE ea then Restore Internal State of Coprocessor else TRAP cpSAVE If supervisor state cpSAVE save the Save Internal State of Coprocessor else TRAP cpScc If cpcc true then 1s gt Destination else Os gt Destination cpTRAPcc _ If cpcc true then TRAP cpTRAPcc cpTRAPcc data DBcc If condition false then Dn 1 gt Dn DBcc Dn label If Dn 1 then PC d PC DIVS Destination Source gt Destination DIVS W ea Dn32 16 gt 16r 16q DIVSL DIVS L ea Dq 32 32 gt 32q DIVS L ea Dr Dq 64 32 gt 32r 32q DIVSL L ea Dr Dq32 32 gt 32r 32q DIVU Destination Source Destination DIVU W ea Dn32 16 gt 16r 16q DIVUL DIVU L ea Dq 32 32 gt 32q DIVU L ea Dr Dq 64 32 gt 32r 32q DIVU
205. n a few clocks of the negation of BG as described in the 7 7 4 Bus Arbitration Control Note that the processor does not perform any external bus cycles before it reasserts BG in this case 7 7 4 Bus Arbitration Control The bus arbitration control unit in the MC68030 is implemented with a finite state machine As discussed previously all asynchronous inputs to the MC68030 are internally synchronized in a maximum of two cycles of the processor clock As shown in Figure 7 61 input signals labeled R and A are internally synchronized versions of the BR and BGACK signals respectively The BG output is labeled G and the internal high impedance control signal is labeled T If T is true the address data and control buses are placed in the high impedance state after the next rising edge following the negation of AS and RMC All signals are shown in positive logic active high regardless of their true active voltage level e For More Information Un This Product irc C Go to www freescale com Bus Operation Freescale Semiconductor Inc R BUS REQUEST A BUS GRANT ACKNOWLEDGE G BUS GRANT T THREE STATE CONTROL TO BUS CONTROL LOGIC X DONT CARE NOTE The BG output will not be asserted while RMC is asserted Figure 7 61 Bus Arbitration State Diagram State changes occur on the next rising edge of the clock after the internal signal is valid The BG signal transitions on the falling edge of the clock after a sta
206. n has completed RMC is asserted to indicate 5e For MUS RR USOS VANE Product OTORGA Go to www freescale com Bus Operation Freescale Semiconductor Inc that the bus is locked In the case an internal decision to execute another bus cycle BG is deferred until the bus cycle has begun BG may be routed through a daisy chained network or through a specific priority encoded network The processor allows any type of external arbitration that follows the protocol 7 7 3 Bus Grant Acknowledge Upon receiving BG the requesting device waits until AS DSACKx or synchronous termination STERM and BGACK are negated before asserting its own BGACK The negation of the AS indicates that the previous master releases the bus after specification 7 refer to MC68030EC D MC68030 Electrical Specifications The negation of DSACKx or STERM indicates that the previous slave has completed its cycle with the previous master Note that in some applications DSACKx might not be used in this way General purpose devices are then connected to be dependent only on AS When BGACK is asserted the device is the bus master until it negates BGACK BGACK should not be negated until all bus cycles required by the alternate bus master are completed Bus mastership terminates at the negation of BGACK The BR from the granted device should be negated after BGACK is asserted If a BR is still pending after the assertion of BGACK another BG is asserted withi
207. naasna a 9 26 9 5 1 10 Long Format Indirect Descriptor o oooooooooo 9 27 9 5 1 11 Short Format Indirect Descriptor o ooooooooo 9 27 XXX MC68030 USER S MANUAL MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Concluded Paragraph i Page Sambar Title Number 9 5 1 12 Long Format Indirect Descriptor 00 0055 9 28 9 5 2 General Table Search 0000 eee 9 28 9 5 3 Variations in Translation Table Structure 9 33 9 5 3 1 Early Termination and Contiguous Memory 9 33 9 5 3 2 indirection MEC 9 34 9 5 3 3 Table Sharing Between Tasks 0a 9 37 9 5 3 4 Padging or Tables oo gue vive bee ore Pe ee Rees 9 37 9 5 3 5 Dynamic Allocation of Tables oooooccoooooooo 9 40 9 5 4 Detail of Table Search Operations 9 40 9 5 5 Protection iore ard opcs E E m E e AE AE NE eee 9 43 9 5 5 1 Function Code Lookup 22 2705 argued Sawn xe eee NG te 9 45 9 5 5 2 Supervisor Translation Tree 0 00 0c eee eee eee 9 48 9 5 5 3 SUMSIVISOD OM one oe 7 ng rss NA NOE Be a tM oe bn ee 9 48 9 5 5 4 A A A ean gis des deren 9 48 9 6 MC68030 and MC68851 Mmu Differences 9 51 9 7 Aa te C A re aie eine eed Dab Shed eral 9 52 9 7 1 Root Pointer Registers ce oerte ba Dapa lang as 9 52 9 7 2 Translation Control Register 00 eee
208. nal that indicates the validity of an address on the address bus and of many control signals It is asserted one half clock after the beginning of a bus cycle iS For More RORO NS BR Un his Product MOTOROLA C Go to www freescale com Freescale Semiconductor Inc Bus Operation 7 1 4 Data Bus The data bus signals DO D31 comprise a bidirectional nonmultiplexed parallel bus that contains the data being transferred to or from the processor A read or write operation may transfer 8 16 24 or 32 bits of data one two three or four bytes in one bus cycle During a read cycle the data is latched by the processor on the last falling edge of the clock for that bus cycle For a write cycle all 32 bits of the data bus are driven regardless of the port width or operand size The processor places the data on the data bus one half clock cycle after AS is asserted in a write cycle 7 1 5 Data Strobe The data strobe DS is a timing signal that applies to the data bus For a read cycle the processor asserts DS to signal the external device to place data on the bus It is asserted at the same time as AS during a read cycle For a write cycle DS signals to the external device that the data to be written is valid on the bus The processor asserts DS one full clock cycle after the assertion of AS during a write cycle 7 1 6 Data Buffer Enable The data buffer enable signal DBEN can be used to enable external data buffers while data is
209. ncrement mode the operand is in memory and the address of the operand is in the address register specified by the register field After the operand address is used it is incremented by one two or four depending on the size of the operand byte word or long word Coprocessors may support incrementing for any size of operand up to 255 bytes If the address register is the stack pointer and the operand size is byte the address is incremented by two rather than one to keep the stack pointer aligned to a word boundary GENERATION EA An An An SIZE ASSEMBLER SYNTAX An MODE 011 REGISTER n ADDRESS REGISTER An gt MEMORY ADDRESS OPERAND LENGTH 1 2 OR 4 gt lt 31 0 MEMORY ADDRESS OPERAND NUMBER OF EXTENSION WORDS 0 ds For MESSER VANE Product NOTDROER Go to www freescale com Freescale Semiconductors dne Addressing Capabilities 2 4 5 Address Register Indirect with Predecrement Mode In the address register indirect with predecrement mode the operand is in memory and the address of the operand is in the address register specified by the register field Before the operand address is used it is decremented by one two or four depending on the operand size byte word or long word Coprocessors may support decrementing for any operand size up to 255 bytes If the address register is the stack pointer and the operand size is byte the address is decremented by two rather than one to keep the sta
210. nd adari tag EH AA Semiconductor Inc SYNTAX bd An Xn POINTER LIST DATA ITEM POINTER Figure 2 11 Preindexed Indirect Addressing aa For MUS RR USTOS BANAL Product MOTOR Go to www freescale com Freescale Semiconductors dne Addressing Capabilities The postindexed indirect mode see Figure 2 12 uses the contents of An as an index to the pointer list at the displacement Register Xn is used as an index to the structure of data items located at the address specified by the pointer Figure 2 13 shows the preindexed indirect addressing with outer displacement mode SYNTAX bd An Xn POINTER LIST POSTINDEXED STRUCTURE gt 5 Xn Y Y POINTER DATA ITEM Figure 2 12 Postindexed Indirect Addressing SYNTAX bd An Xn od POINTER LIST STRUCTURE Y POINTER DATA ITEM Figure 2 13 Preindexed Indirect Addressing with Outer Displacement NO For Mo ARIA RIN OM ANNE Product 2 Go to www freescale com Data Organization and adari RGEFA A 2emiconductor Inc The postindexed indirect mode with outer displacement see Figure 2 14 uses the contents of An as an index to the pointer list at the displacement Register Xn is used as an index to the structure of data structures at the address in the pointer The outer displacement od is the displacement of the data item within the selected data structure SYNTAX bd An Xn od POSTINDEXED S
211. nds CIOUT and CIIN both negated the processor either uses the data read from memory to update a matching entry in the data cache or creates a new entry with the read data in the case of no matching entry The write portion of a read modify write operation also updates a matching entry in the data cache In the case of a cache miss on the write the allocation of a new cache entry for the data being written is controlled by the WA bit Table search accesses however are completely ignored by the data cache it is never updated for a table search access 6 1 3 Cache Filling The bus controller can load either cache in either of two ways Single entry mode Burst fill mode In the single entry mode the bus controller loads a single long word entry of a cache line In the burst fill mode an entire line four long words can be filled Refer to Section 7 Bus Operation for detailed information about the bus cycles required for both modes 6 1 3 1 SINGLE ENTRY MODE When a cachable access is initiated and a burst mode operation is not requested by the MC68030 or is not supported by external hardware the bus controller transfers a single long word for the corresponding cache entry An entire long word is required If the port size of the responding device is smaller than 32 bits the MC68030 executes all bus cycles necessary to fill the long word When a device cannot supply its entire port width of data regardless of the size of the transfe
212. ng update Dr Dq data registers remainder or quotient of divide Dh DI data registers high or loeorder 32 bits of product MSW most significant word LSW least significant word MSB most significant bit FC function code R W read or write indicator An address extensions 3 2 1 Data Movement Instructions The MOVE instructions with their associated addressing modes are the basic means of transferring and storing addresses and data MOVE instructions transfer byte word and long word operands from memory to memory memory to register register to memory and register to register Address movement instructions MOVE or MOVEA transfer word and long word operands and ensure that only valid address manipulations are executed In addition to the general MOVE instructions there are several special data movement instructions move multiple registers MOVEM move peripheral data MOVEP move quick MOVEQ exchange registers EXG load effective address LEA push effective address PEA link stack LINK and unlink stack UNLK us For More RORO NS BR Un his Product MOTOROLA C Go to www freescale com Freescale Semiconductor INC struction Set Summary Table 3 1 is a summary of the integer and floating point data movement operations Table 3 1 Data Movement Operations Instruction Operand Syntax Operand Size Operation LINK mso 16 32 Sp 4 SP An gt SP SP An SP D SP ea
213. nsfer OCS is not asserted for subsequent cycles that are performed due to dynamic bus sizing or operand misalignment 7 1 1 Bus Control Signals for information about the relationship of OCS to bus operation 5 6 2 External Cycle Start ECS This output signal indicates the beginning of a bus cycle of any type 7 1 1 Bus Control Signals for information about the relationship of ECS to bus operation 5 6 3 Read Write R W This three state output signal defines the type of bus cycle A high level indicates a read cycle a low level indicates a write cycle Refer to 7 1 1 Bus Control Signals for information about the relationship of R W to bus operation 5 6 4 Read Modify Write Cycle RMC This three state output signal identifies the current bus cycle as part of an indivisible read modify write operation it remains asserted during all bus cycles of the read modify write operation Refer to 7 1 1 Bus Control Signals for information about the relationship of RMC to bus operation 5 6 5 Address Strobe AS This three state output indicates that a valid address is on the address bus The function code size and read write signals are also valid when AS is asserted Refer to 7 1 3 Address Strobe for information about the relationship of AS to bus operation MOTOROLA For More iniormatiar ion on This Product BS Go to www freescale com Signal Description Freescale Semiconductor Inc 5 6 6 Data Strobe DS During a read cycl
214. nt for a data access the MC68030 may attempt to fill two cache entries The processor may also assert CBREQ to request a burst fill operation That is the processor can fill additional entries in the line The MC68030 allows a burst of as many as four long words The mechanism that asserts the CBREQ signal for burstable cache entries is enabled by the data burst enable DBE and instruction burst enable IBE bits of the cache control register CACR for the data and instruction caches respectively Either of the following conditions cause the MC68030 to initiate a cache burst request and assert CBREQ for a cachable read cycle The logical address and function code signals of the current instruction or data fetch do not match the indexed tag field in the respective instruction or data cache All four long words corresponding to the indexed tag in the appropriate cache are marked invalid However the MC68030 does not assert CBREQ during the first portion of a misaligned access if the remainder of the access does not correspond to the same cache line Refer to 6 1 3 1 Single Entry Mode for details MOTOROLA For Mol4Qp3030 USER ion On AUS Product De Go to www freescale com Bus Operation Freescale Semiconductor Inc If the appropriate cache is not enabled or if the cache freeze bit for the cache is set the processor does not assert CBREQ CBREQ is not asserted during the read or write cycles of any read modify write o
215. number of bytes transferred during a write or noncachable read bus cycle is equal to or less than the size indicated by the SIZO and SIZ1 outputs depending on port width and operand alignment For example during the first bus cycle of a long word transfer to a word port the size outputs indicate that four bytes are to be transferred although only two bytes are moved on that bus cycle Cachable read cycles must always transfer the number of bytes indicated by the port size AO and A1 also affect operation of the data multiplexer During an operand transfer A2 A31 indicate the long word base address of that portion of the operand to be accessed AO and A1 indicate the byte offset from the base Table 7 3 shows the encodings of AO and A1 and the corresponding byte offsets from the long word base dd For MUSEU USER S MANWAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bus Operation REGISTER MULTIPLEXER INTERNAL TO EXTERNAL THE MC68ECO30 _ DATA BUS EXTERNAL BUS ADDRESS XXXXXXXX0 32 BIT PORT INCREASING MEMORY ADDRESSES XXXXXXXX0 BYTE 0 BYTE 1 16 BIT PORT 2 BYTE 2 BYTE 3 XXXXXXXX0 8 BIT PORT FIG 7 4 Figure 7 4 MC68030 Interface to Various Port Sizes Table 7 4 lists the bytes required on the data bus for read cycles that are cachable The entries shown as OPn are portions of the requested operand that are read or written during that bus cycle and are defined by SIZO
216. nvironment the other processors must wait until the CAS instruction completes before accessing a global pointer The following code fragment shows a routine to maintain a count in location SYS_CNTR of the executions of an operation that may be performed by any process or processor in a system The routine obtains the current value of the count in register DO and stores the new count value in register D1 The CAS instruction copies the new count into SYS_CNTR if it is valid However if another user has incremented the counter between the time the count was stored and the read modify write cycle of the CAS instruction the write portion of the cycle copies the new count in SYS_CNTR into DO and the routine branches to repeat the test The following code sequence guarantees that SYS_CNTR is correctly incremented MOVE W SYS_CNTR DO get the old value of the counter INC_LOOP MOVE W D0 D1 make a copy of it ADDQ W Le Del and increment it CAS W DO D1 SYS_CNTR if countr value is still the same update it BNE INC_LOOP if not try again weve For More information On This Product ne 3 Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc The CAS and CAS2 instructions together allow safe operations in the manipulation of system linked lists Controlling a single location HEAD in the example manages a last in first out linked list see Figure 3 2 If the list is empty HEAD contains the NULL pointer
217. o distinguish between user and supervisor accesses and the four valid bits one corresponding to each long word Refer to Figure 6 2 for the instruction cache organization Address bits A7 A4 select one of 16 lines and its associated tag The comparator compares the address and function code bits in the selected tag with address bits A31 A8 and FC2 from the internal prefetch request to determine if the requested word is in the cache A cache hit occurs when there is a tag match and the corresponding valid bit selected by A3 A2 is set On a cache hit the word selected by address bit A1 is supplied to the instruction pipe When the address and function code bits do not match or the requested entry is not valid a miss occurs The bus controller initiates a long word prefetch operation for the required Moe For Mole jetorimatien On This Product em Go to www freescale com On Chip Cache Memories Freescale Semiconductor Inc instruction word and loads the cache entry provided the entry is cachable A burst mode operation may be requested to fill an entire cache line If the function code and address bits match and the corresponding long word is not valid but one or more of the other three valid bits for that line are set a single entry fill operation replaces the required long word only using a normal prefetch bus cycle or cycles no burst 6 1 2 Data Cache The data cache stores data references to any address space except CPU spa
218. ode actually encoded because the programmer need not be concerned about these decisions The assembler can choose the more efficient addressing mode to encode In the list of derived addressing modes that follows common programming terms are used The following definitions apply pointer base index disp subscript relative addr psaddr preindexed postindexed long Word value in a register or in memory which represents an address A pointer combined with a displacement to represent an address A constant or variable value added into an effective address calcula tion A constant index is a displacement A variable index is always represented by a register containing the value Displacement a constant index The use of any of the data or address registers as a variable index subscript into arrays of items 1 2 4 or 8 bytes in size An address calculated from the program counter contents The address is position independent and is in program space All other addresses but psaddr are in data space An absolute address An absolute address in program space All other addresses but PC relative are in data space All modes from absolute address through program counter relative Any of the following modes addr Absolute address in data space psaddr ZPC Absolute address in program space An Register pointer with constant displacement disp An Register pointer with constant displacement addr An Absol
219. of instructions continues at the supervisor level to process the exception condition To return to the user privilege level a system routine must execute one of the following instructions MOVE to SR ANDI to SR EORI to SR ORI to SR or RTE The MOVE ANDI EORI and ORI to SR and RTE instructions execute at the supervisor privilege level and can modify the S bit of the status register After these instructions execute the instruction pipeline is flushed and is refilled from the appropriate address space This is indicated externally by the assertion of the REFILL signal The RTE instruction returns to the program that was executing when the exception occurred It restores the exception stack frame saved on the supervisor stack If the frame on top of the stack was generated by an interrupt trap or instruction exception the RTE instruction restores the status register and program counter to the values saved on the supervisor stack The processor then continues execution at the restored program counter address and at the privilege level determined by the S bit of the restored status register If the frame on top of the stack was generated by a bus fault bus error or address error exception the RTE instruction restores the entire saved processor state from the stack 7 For IC ORO USERS MANYAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Processing States 4 2 ADDRESS SPACE TYPES The processor specifies a
220. ointer independently of supervisor stack requirements To keep data on the system stack aligned for maximum efficiency the active stack pointer is automatically decremented or incremented by two for all byte sized operands moved to or from the stack In long word organized memory aligning the stack pointer on a long word address signed significantly increases the efficiency of stacking exception frames subroutine calls and returns and other stacking operations NO For Mo ARIA RIN OM ANNE Product 2 Go to www freescale com Data Organization and adari ARGEFAA Semiconductor Inc 2 8 2 User Program Stacks The user can implement stacks with the address register indirect with postincrement and predecrement addressing modes With address register An n 0 6 the user can implement a stack that is filled wither from high to low memory or from low to high memory Important considerations are Use the predecrement mode to decrement the register before its contents are used as the pointer to the stack Use the postincrement mode to increment the register after its contents are used as the pointer to the stack e Maintain the stack pointer correctly when byte word and long word items are mixed in these stacks To implement stack growth from high to low memory use An to push data on the stack An to pull data from the stack For this type of stack after either a push or a pull operation register An points to the top i
221. om the processor states described in Section 4 Processing States The clock cycles used in the descriptions and timing diagrams of data transfer cycles are independent of the clock frequency Bus operations are described in terms of external bus states 7 3 1 Asynchronous Read Cycle During a read cycle the processor receives data from a memory coprocessor or peripheral device If the instruction specifies a long word operation the MC68030 attempts to read four bytes at once For a word operation it attempts to read two bytes at once and for a byte operation one byte For some operations the processor requests a three byte transfer The processor properly positions each byte internally The section of the data bus from which each byte is read depends on the operand size address signals A0 A1 CIIN and CIOUT whether the internal caches are enabled and the port size Refer to 7 2 1 Dynamic Bus Sizing 7 2 2 Misaligned Operands and 7 2 6 Cache Filling for more information on dynamic bus sizing misaligned operands and cache interactions Figure 7 19 is a flowchart of an asynchronous long word read cycle Figure 7 20 is a flowchart of a byte read cycle The following figures show functional read cycle timing diagrams specified in terms of clock periods Figure 7 21 corresponds to byte and word read cycles from a 32 bit port Figure 7 22 corresponds to a long word read cycle from an 8 bit port Figure 7 23 also applies to a long word read cy
222. on occurs when additional bus cycles are required for long word or word operands that are misaligned For maximum performance data items should be aligned on their natural boundaries All instruction words and extension words must reside on word boundaries Attempting to prefetch an instruction word at an odd address causes an address error exception NO For Mo ARIA RIN OM ANNE Product HG Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2 S4 S0 S2 S4 A31 A2 X X Al AO FC2 FCO X X SIZ1 N SIZ0 RW ECS N OCS N DSACK1 DSACKO DBEN D31 D24 OP2 OP3 D23 D16 OP3 OP3 D15 D8 OP2 OP3 D7 DO OP3 lt BYTE WRITE ye BYTE WRITE 7 x WORD OPERANDWRITE 3 Figure 7 8 Word Operand Write Timing 8 Bit Data Port Bu For More informatio ion a YANYAL Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bus Operation Figure 7 9 shows the transfer of a long word operand to an odd address in word organized memory which requires three bus cycles For the first cycle the size signals specify a long word transfer and the address offset A2 A0 is 001 Since the port width is 16 bits only the first byte of the long word is transferred The slave device latches the byte and acknowledges the data transfer indicating that the port is 16 bits wide When the processor starts the second cycle the size signals specify that three bytes remain
223. onductors dne Addressing Capabilities SYNTAX MOVE W AS A6 L SCALE A7 WHERE A5 ADDRESS OF ARRAY STRUCTURE A6 INDEX NUMBER OF ARRAY ITEM A7 STACK POINTER SIMPLE ARRAY RECORD OF 2 WORDS SCALE 1 SCALE 2 15 0 15 0 A6 1 2 A6 1 gt 3 2 gt 4 gt RECORD OF 4 WORDS RECORD OF 8 WORDS SCALE 4 SCALE 8 15 0 15 0 AG 1 UY gt 9 2 2 gt NOTE Regardless of array structure software increments index by the appropriate amount to point to next record Figure 2 7 Addressing Array Items 2 27 MOTOROLA For Mo matias ion On AUS Product Go to www freescale com Data Organization and Add kRG SHAME Miconductor Inc The memory indirect addressing modes use a long word pointer in memory to access an operand Any of the modes previously described can be used to address the memory pointer Because the base and index registers can both be suppressed the displacement acts as an absolute address providing indirect absolute memory addressing refer to Figure 2 8 The outer displacement od available in the memory indirect modes is added to the pointer in memory The syntax for these modes is bd An Xn od and bd An Xn od When the pointer is the address of a structure in memory and the outer displacement is the offset of an item in the structure the memory indirect modes can access the item efficiently refer to Figu
224. ong Word Operation The high order 16 bits of the operand are in the first extension word the low order 16 bits are in the second extension word Coprocessor instructions can support immediate data of any size The instruction word is followed by as many extension words as are required Generation Operand given Assembler Syntax XXX Mode Field 111 Register Field 100 Number of Extension Words lor 2 except for coprocessor instructions MIA For More information On This Product e Go to www freescale com Data Organization and Add k RG ERAMReMIconductor Inc 2 5 EFFECTIVE ADDRESS ENCODING SUMMARY Most of the addressing modes use one of the three formats shown in Figure 2 4 The single effective address instruction is in the format of the instruction word The encoding of the mode field of this word selects the addressing mode The register field contains the general register number or a value that selects the addressing mode when the mode field contains 111 Table 2 2 shows the encoding of these fields Some indexed or indirect modes use the instruction word followed by the brief format extension word Other indexed or indirect modes consist of the instruction word and the full format of extension words The longest instruction for the MC68030 contains 10 extension words It is a MOVE instruction with full format extension words for both source and destination effective addresses and with 32 bit base displacements and 32 bit out
225. ontrolled by the synchronous termination signal STERM can only be used to transfer data to and from 32 bit ports The MC68030 allows byte word and long word operands to be located in memory on any byte boundary For a misaligned transfer more than one bus cycle may be required to complete the transfer regardless of port size For a port less than 32 bits wide multiple bus cycles may be required for an operand transfer due to either misalignment or a port width smaller than the operand size Instruction words and their associated extension words must be aligned on word boundaries The user should be aware that misalignment of word or long word operands can cause the MC68030 to perform multiple bus cycles for the operand transfer therefore processor performance is optimized if word and long word memory operands are aligned on word or long word boundaries respectively 7 1 BUS TRANSFER SIGNALS The bus transfers information between the MC68030 and an external memory coprocessor or peripheral device External devices can accept or provide 8 bits 16 bits or 32 bits in parallel and must follow the handshake protocol described in this section The maximum number of bits accepted or provided during a bus transfer is defined as the port width The MC68030 contains an address bus that specifies the address for the transfer and a data bus that transfers the data Control signals indicate the beginning of the cycle the address space and the size of t
226. ort 5 11 1 Cache Disable CDIS The cache disable signal dynamically disables the on chip caches to assist emulator support Refer to 6 1 On Chip Cache Organization and Operation for information about the caches refer to Section 12 Applications Information for a description of the use of this signal by an emulator CDIS does not flush the data and instruction caches entries remain unaltered and become available again when CDIS is negated 5 11 2 MMU Disable MMUDIS The MMU disable signal dynamically disables the translation of addresses by the MMU Refer to 9 4 Address Translation Cache for a description of address translation refer to Section 12 Applications Information for a description of the use of this signal by an emulator The assertion of MMUDIS does not flush the address translation cache ATC ATC entries become available again when MMUDIS is negated 5 11 3 Pipeline Refill REFILL The pipeline refill signal indicates that the MC68030 is beginning to refill the internal instruction pipeline Refer to Section 12 Applications Information for a description of the use of this signal by an emulator 5 11 4 Internal Microsequencer Status STATUS The microsequencer status signal indicates the state of the internal microsequencer The varying number of clocks for which this signal is asserted indicates instruction boundaries pending exceptions and the halted condition Refer to Section 12 Applications Information for a de
227. oth DSACKO and DSACK1 must remain negated throughout the asynchronous input setup and hold times around the end of S8 If wait states are added the processor continues to sample DSACKx signals on the falling edges of the clock until one is recognized The selected device uses RW DS SIZO SIZ1 and A0 A1 to latch data from the appropriate section s of the data bus D24 D31 D16 D23 D8 D15 and DO D7 SIZO SIZ1 and A0 A1 select the data bus sections If it has not already done so the device asserts DSACKx when it has successfully stored the data State 10 The processor issues no new control signals during S10 MOTOROLA For Mol4Qp3030 USER ion On AUS Product TS Go to www freescale com Bus Operation Freescale Semiconductor Inc State 11 The processor negates AS and DS during S11 It holds the address and data valid during S11 to provide address hold time for memory systems R W and FCO FC2 also remain valid throughout S11 If more than one write cycle is required S6 S11 are repeated for each write cycle The external device keeps DSACKx asserted until it detects the negation of AS or DS whichever it detects first The device must remove its data and negate DSACKx within approximately one clock period after sensing the negation of AS or DS 7 3 4 Synchronous Read Cycle A synchronous read cycle is terminated differently from an asynchronous read cycle otherwise the cycles assert and respond to the same signals in the sa
228. oth associated long word cache entries An example of this is an operand request for a long word on an odd word boundary The MC68030 first fetches the initial byte s of the operand residing in the first long word and then requests the remaining bytes to fill that cache entry if the port size is less than 32 bits before it requests the remainder of the operand and corresponding long word to fill the second cache entry If the port size is 32 bits the processor performs two accesses one for each cache entry For Mare formation Un This Product MOS EA Go to www freescale com Freescale Semiconductor Inc chio GachelMeinbrizs Figure 6 8 shows a misaligned access of a long word at address 06 from an 8 bit port requiring eight bus cycles to complete Reading this long word operand requires eight read Cycles since accesses to all eight addresses return 8 bit port size encodings These cycles fetch the two cache entries that the requested long word spans The first cycle requests a long word at address 06 and accepts the first requested byte b6 The subsequent transfers of the first long word are performed in the following order b7 b4 b5 The remaining four read cycles transfer the four bytes of the second cache entry The sequence of access for the entire operation is b6 b7 b4 b5 b8 b9 bA and bB UNABLE TO LOCATE ART Figure 6 8 Single Entry Mode Operation Misaligned Long Word and 8 Bit Port The next example shown in
229. ous Write Cycle Flowchart State 0 The write cycle starts with SO The processor drives ECS low indicating the beginning of an external cycle When the cycle is the first cycle of a write operation OCS is driven low at the same time During SO the processor places a valid address on A0 A31 and valid function codes on FCO FC2 The function codes select the address space for the cycle The processor drives R W low for a write cycle SIZO SIZ1 become valid indicating the number of bytes to be transferred CIOUT also becomes valid indicating the state of the MMU Cl bit in the address translation descriptor or in the appropriate TTx register State 1 One half clock later in S1 the processor asserts AS indicating that the address on the address bus is valid The processor also asserts DBEN during S1 which may be used to enable the external data buffers In addition the ECS and OCS if asserted signal is negated during S1 mn For IC ORO USERS MANYAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bus Operation S0 81 S2 Sw Sw S3 CLK A31 A0 X FC2 FC0 X SIZ1 N SIZO RW ECS CBREQ CBACK DBEN N Figure 7 34 Synchronous Write Cycle with Wait States CIOUT Asserted State 2 During S2 the processor places the data to be written onto DO D31 The selected device uses R W CLK SIZO SIZ1 and A0 A1 to latch data from the appropriate section s of the data bus D24 D31 D16 D23
230. pace Address Encodings 20 05 10 7 10 4 Coprocessor Address Map in MC68030 CPU Space 10 8 10 5 Coprocessor Interface Register Set Map 10 9 10 6 Coprocessor General Instruction Format CpGEN 10 10 10 7 Coprocessor Interface Protocol for General Category Instructions 10 11 10 8 Coprocessor Interface Protocol for Conditional Category Instructions 10 13 10 9 Branch on Coprocessor Condition Instruction cpBcc W 10 14 10 10 Branch On Coprocessor Condition Instruction cpBcc L 10 14 10 11 Set On Coprocessor Condition CpSCC oooooccooomoo 10 15 10 12 Test Coprocessor Condition Decrement and Branch Instruction Format COD BCC nens eee aes ic e bere d 10 17 10 13 Trap On Coprocessor Condition cpTRAPCC 220000 10 18 10 14 Coprocessor State Frame Format in Memory 0 10 21 10 15 Coprocessor Context Save Instruction Format CpSAVE 10 25 10 16 Coprocessor Context Save Instruction Protocol 10 26 10 17 Coprocessor Context Restore Instruction Format CpRESTORE 10 27 10 18 Coprocessor Context Restore Instruction Protocol 10 28 10 19 GONTONGIA Format 2a a eral Nad Eri o eta arp co 10 30 10 20 Condition CIR Format ise eee ante eee ee OR RR E RC eS hark REGES 10 31 10 21 Operand Alignment for Operand CIR Accesses
231. perand is resident in the appropriate on chip cache no external bus cycle is required the MMU is completely ignored unless an invalid translation resides in the MMU at that time see next two paragraphs Therefore the state of the corresponding Cl bits in the MMU are also ignored The MMU is used to validate all accesses that require external bus cycles an address translation must be available and valid protections are checked and the CIOUT signal is asserted appropriately MOTOROLA For More jadorinatrar ion on This Product s Go to www freescale com On Chip Cache Memories Freescale Semiconductor Inc An external access is defined as cachable for either the instruction or data cache when all the following conditions apply The cache is enabled with the appropriate bit in the CACR set The CDIS signal is negated The CIIN signal is negated for the access The CIOUT signal is negated for the access The MMU validates the access Because both the data and instruction caches are referenced by logical addresses they should be flushed during a task switch or at any time the logical to physical address mapping changes including when the MMU is first enabled In addition if a page descriptor is currently marked as valid and is later changed to the invalid type due to a context switch or a page replacement operation entries in the on chip instruction or data cache corresponding to the physical page must be firs
232. peration The MC68030 allows burst filling only from 32 bit ports that terminate bus cycles with STERM and respond to CBREQ by asserting CBACK When the MC68030 recognizes STERM and CBACK and it has asserted CBREQ it maintains AS DS R W A0 A31 FCO FC2 SIZO SIZ1 in their current state throughout the burst operation The processor continues to accept data on every clock during which STERM is asserted until the burst is complete or an abnormal termination occurs CBACK indicates that the addressed device can respond to a cache burst request by supplying one more long word of data in the burst mode It can be asserted independently of the CBREQ signal and burst mode is only initiated if both of these signals are asserted for a synchronous cycle If the MC68030 executes a full burst operation and fetches four long words CBREQ is negated after STERM is asserted for the third cycle indicating that the MC68030 only requests one more long word the fourth cycle CBACK can then be negated and the MC68030 latches the data for the fourth cycle and completes the cache line fill The following conditions can abort a burst fill CIIN asserted BERR asserted or e CBACK negated prematurely The processing of a bus error during a burst fill operation is described in 7 5 1 Bus Errors For the purposes of halting the processor or arbitrating the bus away from the processor with BR a burst operation is a single cycl
233. possibly BERR A S deferred HALT NA NA 4 DSACKx A X Terminate and take bus error exception possibly BERR NA A deferred HALT NA NA 5 DSACKx NA A X Terminate and retry when HALT negated BERR A S HALT A S S 6 DSACKx A X Terminate and retry when HALT negated BERR NA A HALT NA A LEGEND N The number of current even bus state e g S2 S4 etc A Signal is asserted in this bus state NA Signal is not asserted in this state X Don tcare S Signal was asserted in previous state and remains asserted in this state Table 7 8 shows various combinations of control signal sequences and the resulting bus cycle terminations To ensure predictable operation BERR and HALT should be negated according to the specifications in MC68030EC D MC68030 Electrical Specifications DSACKx BERR and HALT may be negated after AS If DSACKx or BERR remain asserted into S2 of the next bus cycle that cycle may be terminated prematurely The termination signal for a synchronous cycle is STERM An analogous set of bus cycle termination cases exists in relationship to STERM assertion Note that STERM and DSACKx must never both be asserted in the same cycle STERM has setup time 60 and hold time 61 requirements relative to each rising edge of the processor clock while AS is asserted Bus error and retry terminations during burst cycles operate as described in 6 1 3 2 Burst Mode Filling 7 5 1 Bus Errors and 7 5 2 Retry Operation NO
234. present on the data bus During a read operation DBEN is asserted one clock cycle after the beginning of the bus cycle and is negated as DS is negated In a write operation DBEN is asserted at the time AS is asserted and is held active for the duration of the cycle In a synchronous system supporting two clock bus cycles DBEN timing may prevent its use 7 1 7 Bus Cycle Termination Signals During asynchronous bus cycles external devices assert the data transfer and size acknowledge signals DSACKO and or DSACK1 as part of the bus protocol During a read cycle the assertion of DSACKx signals the processor to terminate the bus cycle and to latch the data During a write cycle the assertion of DSACKx indicates that the external device has successfully stored the data and that the cycle may terminate These signals also indicate to the processor the size of the port for the bus cycle just completed as shown in Table 7 1 Refer to 7 3 1 Asynchronous Read Cycle for timing relationships of DSACKO and DSACK1 MOTOROLA For More datori atrar ion on This Product Go to www freescale com Bus Operation Freescale Semiconductor Inc For synchronous bus cycles external devices assert the synchronous termination signal STERM as part of the bus protocol During a read cycle the assertion of STERM causes the processor to latch the data During a write cycle it indicates that the external device has successfully stored the data In either
235. previously valid entries remain valid and may be used 6 3 2 Cache Address Register The CAAR is a 32 bit register shown in Figure 6 15 The index field bits 7 2 contains the address for the clear cache entry operations The bits of this field correspond to bits 7 2 of addresses they specify the index and a long word of a cache line Although only the index field is used currently all 32 bits of the register are implemented and are reserved for use by Motorola 31 8 7 2 1 0 CACHE FUNCTION ADDRESS INDEX Figure 6 15 Cache Address Register For Mare formation Un This Product MOTOBOLA Go to www freescale com Freescale Semiconductor Inc SECTION 7 BUS OPERATION This section provides a functional description of the bus the signals that control it and the bus cycles provided for data transfer operations It also describes the error and halt conditions bus arbitration and the reset operation Operation of the bus is the same whether the processor or an external device is the bus master the names and descriptions of bus cycles are from the point of view of the bus master For exact timing specifications refer to Section 13 Electrical Characteristics The MC68030 architecture supports byte word and long word operands allowing access to 8 16 and 32 bit data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge inputs DSACKO and DSACK1 Synchronous bus cycles c
236. privilege level the active stack pointer interrupt or master is called the supervisor stack pointer SSP In addition the address registers may be used for word and long word operations All of the 16 general purpose registers DO D7 A0 A7 may be used as index registers 31 16 15 8 7 0 DO D1 D2 D3 DATA D4 REGISTERS D5 D6 D7 31 16 15 0 A0 Al A2 SH A4 A5 A6 31 16 15 0 EL nm NR 2 0 PROGRAM Ce j Se IT d 0 CONDITION r O jo po Sa Seen eS REGISTER Figure 1 2 User Programming Model x For More Information On This Product SE Go to www freescale com Freescale Semiconductor Inc Production The program counter PC contains the address of the next instruction to be executed by the MC68030 During instruction execution and exception processing the processor automatically increments the contents of the PC or places a new value in the PC as appropriate wo 16 15 INTERRUPT STACK POINTER o 16 15 MASTER STACK T ISP ed POINTER 15 8 7 0 ew js STATUS REGISTER wo VECTOR BASE REGISTER o CODE REGISTERS LLL D wo CACHE CONTROL CACR REGISTER wo CACHE ADDRESS REGISTER ACCESS CONTROL REGISTER 0 ACCESS CONTROL REGISTER 1 CAAR o wo d E de ALTERNATE FUNCTION i i hg NG ACU STATUS ACUSR rae Figure 1 3 Supervisor Programming Model Supplement Ili The status register
237. processing required for the exception condition involves the exception vector table and an exception stack frame The following paragraphs describe the vector table and a generalized exception stack frame Exception processing is discussed in detail in Section 8 Exception Processing Coprocessor detected exceptions are discussed in detail in Section 10 Coprocessor Interface Description 4 3 1 Exception Vectors The vector base register VBR contains the base address of the 1024 byte exception vector table which consists of 256 exception vectors Exception vectors contain the memory addresses of routines that begin execution at the completion of exception processing These routines perform a series of operations appropriate for the corresponding exceptions Because the exception vectors contain memory addresses each consists of one long word except for the reset vector The reset vector consists of two long words the address used to initialize the interrupt stack pointer and the address used to initialize the program counter The address of an exception vector is derived from an 8 bit vector number and the VBR The vector numbers for some exceptions are obtained from an external device others are supplied automatically by the processor The processor multiplies the vector number by four to calculate the vector offset which it adds to the VBR The sum is the memory address of the vector All exception vectors are located in supervisor data space e
238. purpose is not required by most systems Note that even in a system with error detection correction circuitry the NOP is not required for this synchronization Since the MMU always checks the validity of write cycles before they proceed to the data cache and are executed externally the MC68030 is guaranteed to write correct data to the cache Thus there is no danger in subsequent instructions using erroneous data from the cache before an external bus error signals an error A bus synchronization example is given in Figure 7 58 id For Mare formation Un This Product MOTOBOLA Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 Sw EXTERNAL WRITE WRITE TO D CACHE D CACHE READ MOVE L DO A0 MOVE L A0 D1 Ik NOP PREVENTS EXECUTION OF SUBSEQUENT INSTRUCTIONS UNTIL MOVE L DO A0 WRITE CYCLE COMPLETES Figure 7 58 Bus Synchronization Example 7 7 BUS ARBITRATION The bus design of the MC68030 provides for a single bus master at any one time either the processor or an external device One or more of the external devices on the bus can have the capability of becoming bus master Bus arbitration is the protocol by which an external device becomes bus master the bus controller in the MC68030 manages the bus arbitration signals so that the processor has the lowest priority External devices that need to obtain the bus must assert the bus arbitration signals in the sequences described in the following
239. r the responding device must consistently assert the cache inhibit input CIIN signal For example a 32 bit port must always supply 32 bits even for 8 and 16 bit transfers a 16 bit port must supply 16 bits even for 8 bit transfers The MC68030 assumes that a 32 bit termination signal for the bus cycle indicates availability of 32 valid data bits even if only 16 or 8 bits are requested Similarly the processor assumes that a 16 bit termination signal indicates that all 16 bits are valid If the device cannot supply its full port width of data it must assert CIIN for all bus cycles corresponding to a cache entry MOTOROLA For More datori atrar ion on This Product s Go to www freescale com On Chip Cache Memories Freescale Semiconductor Inc When a cachable read cycle provides data with both CIIN and BERR negated the MC68030 attempts to fill the cache entry Figure 6 5 shows the organization of a line of data in the caches The notation bO b1 b2 and so forth identifies the bytes within the line For each entry in the line a valid bit in the associated tag corresponds to a long word entry to be loaded Since a single valid bit applies to an entire long word a single entry mode operation must provide a full 32 bits of data Ports less than 32 bits wide require several read cycles for each entry Figure 6 5 shows an example of a byte data operand read cycle starting at byte address 03 from an 8 bit port Provided the data item is
240. r S2 and STERM is sampled on every rising edge of the clock thereafter until it is recognized Once STERM is recognized data is latched on the next falling edge of the clock corresponding to the beginning of S3 State 3 The processor maintains AS DS and DBEN asserted during S3 It also holds the address valid during S3 for continuation of the burst R W SIZO SIZ1 and FCO FC2 also remain valid throughout S3 The external device must keep the data driven throughout the synchronous hold time for data from the beginning of S3 The device must negate STERM within one clock after asserting STERM otherwise the processor may inadvertently use STERM prematurely for the next burst access STERM need not be negated if subsequent accesses do not require wait cycles State 4 At the beginning of S4 the processor tests the level of STERM This state signifies the beginning of burst mode and the remaining states correspond to burst fill cycles If STERM is recognized the processor latches the incoming data at the end of S4 This data corresponds to the second long word of the burst If STERM is negated at the beginning of S4 wait states are inserted instead of S4 and S5 and STERM is sampled on every rising edge of the clock thereafter until it is recognized As for synchronous cycles the states of CBACK and CIIN are latched at the time STERM is recognized The assertion of CBACK at this time indicates that the burst operation s
241. r false These terms are used independently of the voltage level high or low that they represent 5 1 SIGNAL INDEX The input and output signals for the MC68030 are listed in Table 5 1 Both the names and mnemonics are shown along with brief signal descriptions For more detail on each signal refer to the paragraph in this section named for the signal and the reference in that paragraph to a description of the related operations Guaranteed timing specifications for the signals listed in Table 5 1 can be found in M68030EC D MC68030 Electrical Specifications Table 5 1 Signal Index Sheet 1 of 2 Signal Name Mnemonic Function Function Codes FCO FC2 3 bit function code used to identify the address space of each bus cycle Address Bus A0 A31 32 bit address bus Data Bus DO D31 32 bit data bus used to transfer 8 16 24 or 32 bits of data per bus cycle SIZO SIZ1 Indicates the number of bytes remaining to be transferred for this cycle These signals together with AO and A1 define the active sections of the data bus Operand Cycle Start Identical operation to that of ECS except that OCS is asserted only during the first bus cycle of an operand transfer External Cycle Start Provides an indication that a bus cycle is beginning Read Write Defines the bus transfer as a processor read or write Read Modify Write Cycle Provides an indicator that the current bus cycle is part of an indivisible read modify write ope
242. r points to the next item to be removed from the queue and the unchanged put address register points to the next available space in the queue This is illustrated as LOW MEMORY LAST GET FREE GET Am NEXT GET LAST PUT PUT An FREE HIGH MEMORY To implement the queue as a circular buffer the relevant address register should be checked and adjusted if necessary before performing the put or get operation The address register is adjusted by subtracting the buffer length in bytes from the register NO For Mo ARIA RIN OM ANNE Product P Go to www freescale com Data Organization and AdarkARG EH AA Semiconductor Inc To implement growth of the queue from high to low memory use An to put data into the queue Am to get data from the queue After a put operation the put address register points to the last item place din the queue and the unchanged get address register points to the last item removed from the queue After a get operation the get address register points to the last item removed from the queue and the unchanged put address register points to the last item placed in the queue This is illustrated as LOW MEMORY FREE PUT An LAST PUT NEXT GET GET Am gt LAST GET FREE HIGH MEMORY To implement the queue as a circular buffer the get or put operation should be performed first and then
243. ram Counter Indirect with Displacement Mode Program Counter Indirect with Index 8 Bit Displacement Mode Program Counter Indirect with Index Base Displacement Mode Program Counter Memory Indirect Postindexed Mode Program Counter Memory Indirect Preindexed Mode Absolute Short Addressing Mode 0a Absolute Long Addressing Mode 0 000e ee Immediate IATA ch ka Kahi aa beim das er npe oov is Gust Aira Moh E dd Effective Address Encoding Summary n sssaaa saanen nann MC68030 USER S MANUAL For More Information On This Product Go to www freescale com Page Number Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph i Page NE Title Number 2 6 Programmer s View of Addressing Modes 2 24 2 6 1 Addressing CapabilitieS ooooooooooommmoo 2 25 2 6 2 General Addressing Mode Summary 000 0055 2 31 2 7 M68000 Family Addressing Compatibility 2 36 2 8 Other Data Structures 2 durior soe eye eet eu cn pte s 2 36 2 8 1 System tackle Mni C i De eL eee te 2 36 2 8 2 User Program Stacks ots crm ccce o o 2 38 2 8 3 QUEUES P 2 39 Section 3 Instruction Set Summary 3 1 Instruction atii proa toe Dr 3 1 3 2 Instruction SUMMAaryY a eec cma us dos den ia heo aa 3 2 3 2 1 Data Movement Instructions o 3 4 3 2 2 Integer Arithmetic Instructions llle 3 5 3 2 3 Logical
244. ration Address Strobe Indicates that a valid address is on the bus Data Strobe Indicates that valid data is to be placed on the data bus by an external device or has been placed on the data bus by the MC68030 Data Buffer Enable DBEN Provides an enable signal for external data buffers M ANUAL MOTOROLA 22 For MALE US RS U NAL Product OTORO Go to www freescale com Freescale Semiconductor Inc Signal Description Table 5 1 Signal Index Sheet 2 of 2 Signal Name Mnemonic Function Data Transfer and DSACKO Bus response signals that indicate the requested data transfer operation Size Acknowledge DSACK1 is completed In addition these two lines indicate the size of the external bus port on a cycle by cycle basis and are used for asynchronous transfers Synchronous Bus response signal that indicates a port size of 32 bits and that data Termination may be latched on the next falling clock edge Cache Inhibit In Prevents data from being loaded into the MC68030 instruction and data caches Cache Inhibit Out CIOUT Reflects the Cl bit in ATC entries or TTx register indicates that external caches should ignore these accesses Cache Burst Request CBREQ Indicates a burst request for the instruction or data cache Cache Burst CBACK Indicates that the accessed device can operate in burst mode Acknowledge Interrupt Priority Level TP
245. re 2 9 Memory indirect addressing modes are used with a base displacement in five basic forms bd An Indirect suppressed index register pd An Xn Preindexed indirect pd An Xn Postindexed indirect pd An Xn od Preindexed indirect with outer displacement bd An Xn od Postindexed indirect with outer displacement Qu de qe oc SYNTAX bd POINTER DATA ITEM Figure 2 8 Using Indirect Absolute Memory Addressing The indirect suppressed index register mode see Figure 2 10 uses the contents of register An as an index to the pointer located at the address specified by the displacement The actual data item is at the address in the selected pointer The preindexed indirect mode see Figure 2 11 uses the contents of An as an index to the pointer list structure at the displacement Register Xn is the index to the pointer which contains the address of the data item x For More Information Un This Product iced cd C Go to www freescale com Freescale Semiconductors dne Addressing Capabilities SYNTAX An od MEMORY STRUCTURE An gt POINTER od Y DATA ITEM Figure 2 9 Accessing an Item in a Structure Using a Pointer SYNTAX bd An POINTER LIST bd 3 An Y POINTER DATA ITEM Figure 2 10 Indirect Addressing Suppressed Index Register NO For Mo ARIA RIN OM ANNE Product x Go to www freescale com Data Organization a
246. re Roe a 3 27 3 4 Doubly Linked List Insertion 0 0c eee eee 3 29 3 5 Doubly Linked List DelGlOns e202 0h025408 004114 aos 3 30 4 1 General Exception Stack Frame cee eee eee ees 4 7 5 1 Functional Signal Groups oie uh bien a oh AG ou cute e uin 5 1 6 1 Internal Caches and the MC68080 aaa 6 2 6 2 On Chip Instruction Cache Organization 0000 eee eee 6 5 6 3 On Chip Data Cache Organization eee eee eee 6 7 6 4 No Write Allocation and Write Allocation Mode Examples 6 9 6 5 Single Entry Mode Operation 8 Bit Port 0 6 11 6 6 Single Entry Mode Operation 16 Bit Port 6 12 6 7 Single Entry Mode Operation 32 BitPort 6 12 6 8 Single Entry Mode Operation Misaligned Long Word and 8 Bit Port 6 13 6 9 Single Entry Mode Operation Misaligned Long Word and 16 Bit Port 6 14 6 10 Single Entry Mode Operation Misaligned Long Word and 32 Bit DSACISCPOR asunto ace Eo A aa ee NR RR 6 15 MOTOROLA MC68030 USER S MANUAL xxxvii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LIST OF ILLUSTRATIONS Continued Figure Title Number 6 11 Burst Operation Cycles and Burst Mode 6 12 Burst Filling Wraparound Example 200000 00 ae 6 13 Deferred Burst Filing Example ooooooocoooo o 6 14 Cache Con
247. red Thus an aligned long word data write may replace a previously valid entry whereas a misaligned data write or a write of data that is not long word may invalidate a previously valid entry or entries MOTOROLA ER For Mo aeRO US ER MANGA Product Go to www freescale com 6 7 On Chip Cache Memories Freescale Semiconductor Inc Write allocation eliminates stale data that may reside in the cache because of either of two unique situations multiple mapping of two or more logical addresses to one physical address within the same task or allowing the same physical location to be accessed by both supervisor and user mode cycles Stale data conditions can arise when operating in the no write allocation mode and all the following conditions are satisfied Multiple mapping object aliasing is allowed by the operating system e A read cycle loads a value for an aliased physical address into the data cache A write cycle occurs referencing the same aliased physical object as above but using a different logical address causing a cache miss and no update to the cache has the same page offset The physical object is then read using the first alias which provides stale data from the cache In this case the data in the cache no longer matches that in physical memory and is stale Since the write allocation mode updates the cache during write cycles the data in the cache remains consistent with physical memory Note that wh
248. reescale com Paragraph Number 10 3 4 10 3 5 10 3 6 10 3 7 10 3 8 10 3 9 10 3 10 10 3 11 10 4 10 4 1 10 4 2 10 4 3 10 4 4 10 4 5 10 4 6 10 4 7 10 4 8 10 4 9 10 4 10 10 4 11 10 4 12 10 4 13 10 4 14 10 4 15 10 4 16 10 4 17 10 4 18 10 4 19 10 4 20 10 5 10 5 1 10 5 1 1 10 5 1 2 10 5 1 3 10 5 1 4 10 5 1 5 10 5 2 10 5 2 1 10 5 2 2 10 5 2 3 10 5 2 4 10 5 2 5 MOTOROLA Freescale Semiconductor Inc TABLE OF CONTENTS Continued Restore GIEU od coe ay tod d ED did dci Operation Word CIR alos wait a ee eR REO ii Command Gba ura a aae ardet ce both eie RR ea EU erate COT dion CIR au seas o a uta se red dod dn part de s Operan GB 12 292 a pP pA apos ua vor ela Pee a mae ae he eas Register Select CIR 26 oie bone SR ana Banal ie tal ete Instruction Address EL AA a etd e ia Operand Address CIRC i dug pada uox e a IECUR OR TE UNA Coprocessor Response PrimitiVeS ooooo ooooo le a CA TYPEN Coprocessor Response Primitive General Format Busy PHEMNVG naka mapagana Hayaan KIS ab be beh pa Ghar Boas N ll Sda LALA PARA PAA Supervisor Check Primitive o ooooooooooooooo Transfer Operation Word Primitive o o ooooooo Transfer from Instruction Stream Primitive Evaluate and Transfer Effective Address Primitive Evaluate Effective Address and Transfer Data Primitive Write to Previously Evaluated Effective Address Primi
249. reparation for the write portion of the cycle The external device must keep its data asserted throughout the synchronous hold time for data from the beginning of S3 The device must remove the data within one clock cycle after asserting STERM to avoid bus contention It must also negate STERM within two clocks after asserting STERM otherwise the processor may inadvertently use STERM for the next bus cycle Idle States The processor does not assert any new control signals during the idle states but it may begin the modify portion of the cycle at this time The R W signal remains in the read mode until S4 to prevent bus conflicts with the preceding read portion of the cycle the data bus is not driven until S6 State 4 The processor asserts ECS and OCS in S4 to indicate that an external cycle is beginning The processor drives R W low for a write cycle CIOUT also becomes valid indicating the state of the MMU Cl bit in the address translation descriptor or in the appropriate TTx register Depending on the write operation to be performed the address lines may change during S4 State 5 In state 5 S5 the processor asserts AS to indicate that the address on the address bus is valid The processor also asserts DBEN during S5 which can be used to enable external data buffers State 6 During S6 the processor places the data to be written onto the DO D31 The selected device uses R W CLK SIZO SIZ1 and A0 A1 to latch da
250. resent on the bus but may not be valid This sequence may be used by systems that have memory error detection and correction logic and by external cache memories The assertion of BERR described in the third case recognized after STERM has requirements similar to those described in the preceding paragraph BERR must be stable throughout the sample window for the next falling edge of the clock as defined by specifications 27A and 28A Figure 7 51 shows the timing for this case MOTOROLA For Mol4Qp3030 USER ion On AUS Product TER Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2 S4 S0 S2 S4 S0 S2 ge opere d qp se pe qo D oe ere 0000 moms XN Bkearpoirencopne o mom X X SEMONNMER OX A1 A0 a reo XX WORD c o L M NN GR EM ET DLL ca cedo ff sawo S ANa AN HALT BREAKPOINT FETCHED lt READ CYCLE a ACKNOWLEDGE 3 lt _ INSTRUCTION BUS ERROR EXECUTION ASSERTED Figure 7 49 Bus Error without DSACKx in For MUS ARO USOS BANAL Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bus Operation DD CO CA reo XO o Xo saso KK LX LLL A S ES NS DSACK1 N NENNEN DSACKO m ss INTERNAL y lt WRITE WITH BUS ERROR ASSERTED gt PROCESSING STACK WRITE Figure 7 50 Late Bus Error with DSACKx A bus error occurring during a burst fill operation is a special case If a bus
251. rs SFC and DFC are 32 bit registers with only bits 2 0 implemented that contain the address space values FCO FC2 for the read or write operands of MOVES PLOAD PFLUSH and PTEST instructions The MOVEC instruction is used to transfer values to and from the alternate function code registers These are long word transfers the upper 29 bits are read as zeros and are ignored when written The remaining control registers in the supervisor programming model are used by the memory management unit MMU The CPU root pointer CRP and supervisor root pointer SRP contain pointers to the user and supervisor address translation trees Transfers of data to and from these 64 bit registers are quad word transfers The translation control register TC contains control information for the MMU The MC68030 always uses long word transfers to access this 32 bit register The transparent translation registers TTO and TT1 also contain 32 bits each they identify memory areas for direct addressing without address translation Data transfers to and from these registers are long word transfers The MMU status register MMUSR stores the status of the MMU after execution of a PTEST instruction It is a 16 bit register and transfers to and from the MMUSR are word transfers Refer to Section 9 Memory Management Unit for more detail 2 3 ORGANIZATION OF DATA IN MEMORY Memory is organized on a byte addressable basis where lower addresses correspond to higher order
252. s The memory management function performed by the MMU is called demand paged memory management Since a task specifies the areas of memory it requires as it executes Memory allocation is supported on a demand basis If a requested access to memory is not currently mapped by the system then the access causes a demand for the operating system to load or allocate the required memory image The technique used by the MC68030 is paged memory management because physical memory is managed in blocks of a specified number of bytes called page frames The logical address space is divided into fixed size pages that contain the same number of bytes as the page frames Memory management assigns a physical base address to a logical page The system software then transfers data between secondary storage and memory one or more pages at a time RE For More RORO NS BR Un his Product MOTOROLA C Go to www freescale com Freescale Semiconductor Inc introduction 1 8 PIPELINED ARCHITECTURE The MC68030 uses a three stage pipelined internal architecture to provide for optimum instruction throughput The pipeline allows as many as three words of a single instruction or three consecutive instructions to be decoded concurrently 1 9 THE CACHE MEMORIES Due to locality of reference instructions and data that are used in a program have a high probability of being reused within a short time Additionally instructions and data operands that reside in proximi
253. s CMP Compare ROL ROR Rotate Left and Right CMPA Compare Address ROXL ROXR Rotate With Extend Left and Right CMPI Compare Immediate RTD Return and Deallocate CMPM Compare Memory to Memory RTE Return from Exception CMP2 Compare Registre Against Upper and RTR Return and Restore Codes Lower Bounds RTS Return from Subroutine DBcc Test Condition Decrement and Branch SBCD Subtract Decimal With Extend DIVS DIVSL Signed Divide Scc Set Conditionally DIVU DIVUL Unsigned Divide STOP Stop EOR Logical Exclusive OR SUB Subtract EORI Logical Exclusive OR Immediate SUBA Subtract Immediate EXG Exchange Registers SUBI Subtract Quick EXT EXTB Sign Extend SUBQ Subtract with Extend ILLEGAL Take Illegal Instruction Trap SUBX Swap Register Words JMP Jump SWAP Test Operand and Set JSR Jump to Subroutine TAS Trap LEA Load Effective Address TRAP Trap Conditionally LINK Link and Allocate TRAPcc Trap on Overflow LSL LSR Logical Shift Left and Right TRAPV Test on Overflow MOVE Move TST Test Operand MOVEA Move Address MOVE CCR Move Condition Code Register Aah HUA MOVE SR Move Status Register INE Unpack BCD nie For More Information On This Product meee Go to www freescale com Freescale Semiconductor Inc Production Mnemonic Description Mnemonic Description cpBcc Branch Conditionally cpRESTORE Restore Internal State of Coprocessor cpDBcc Test Coprocessor Condition cpSAVE Save Internal State of Coprocessor Decrement and Branch cpScc Set Condition
254. s 4 according to the value of the MMU CI bit in the address translation descriptor or in the appropriate TTx register State 1 One half clock later in S1 the processor asserts AS indicating that the address on the address bus is valid The processor asserts DS during S1 In addition the ECS and OCS if asserted signal is negated during S1 MOTOROLA For Mol4Gp3030 USER ion On AUS Product TS Go to www freescale com Bus Operation Freescale Semiconductor Inc CONTROLLER EXTERNAL DRIVE LOCK BUS 1 ASSERT READ MODIFY WRITE CYCLE RMC ADDRESS DEVICE ASSERT ECS OCS FOR ONE HALF CLOCK SET R W TO READ DRIVE ADDRESS ON A31 A0 DRIVE FUNCTION CODE ON FC2 FCO DRIVE SIZE SIZ1 SIZO CACHE INHIBIT OUT CIOUT BECOMES VALID ASSERT ADDRESS STROBE AS ASSERT DATA STROBE DS PRESENT DATA ASSERT DATA BUFFER ENABLE DBEN O 0 NOD O BB ON 1 DECODE ADDRESS 2 PLACE DATA ON D31 D0 3 ASSERT DATA TRANSFER AND ACQUIRE DATA SIZE ACKNOWLEDGE DSACKx SAMPLE CACHE INHIBIT IN IF CAS2 INSTRUCTION LATCH DATA AND ONLY ONE OPERAND 1 2 3 NEGATE AS AND DS READ THEN GO TO 4 5 NEGATE DBEN IF OPERANDS DO NOT START DATA MODIFICATION TERMINATE CYCLE MATCH THEN GO TO C ELSE GO TO 1 REMOVE DATA FROM D31 DO 2 NEGATE DSACKx START OUTPUT TRANSFER ASSERT ECS OCS FOR ONE HALF CLOCK DRIVE ADDRESS ON A31 A0 IF DIFFERENT DRIVE SIZE SIZ1 SIZ0 SET R W TO WRITE ASSER
255. s For MUS RA USOS BANAL Product MOTOR Go to www freescale com Freescale Semiconductor Inc Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 S4 Al A0 N SIZ1 N WORD BYTE SIZO DBEN N D31 D24 OP2 OP3 OP3 D23 D16 OP3 OP3 OP3 D7 DO OP3 OP3 OP3 lt WORD WRITE gt BYTE WRITE gt lt BYTE WRITE gt Figure 7 26 Asynchronous Byte and Word Write Cycles 32 Bit Port MOTOROLA For Mo EASELS SUAM product 74 Go to www freescale com Bus Operation Freescale Semiconductor Inc SIZ1 N LONG WORD 3 BYTE WORD BYTE SIZ0 N N RW ECS N N OCS N D31 D24 o0 OP1 OP OP3 D23 D16 OP1 OP1 OP3 OP3 D15 D8 OP2 OP2 OP2 o lt BYTE WRITE ya BYTE WRITE 4 BYTE WRITE BYTE WRITE 3 LONG WORD OPERAND READ TO 8 BIT PORT gt Figure 7 27 Long Word Operand Write 8 Bit Port GAE For Mars formation Un This Product MOS EA Go to www freescale com Freescale Semiconductor Inc Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 S4 KK A OS NW A0 N LONG WORD WORD LONG WORD SIZ0 N R W OCS _ DSACK1 DSACKO DBEN D7 DO OP3 OP3 lt WORD WRITE scr reac WORD WRITE gt lt LONG WORD WRITE 3 TO 32 BIT PORT LONG WORD OPERAND WRITE TO 16 BIT PORT Figure 7 28 Long Word Operand Write 16 Bit Port MOTOROLA For Mo MG83030 U ER SANYA Albroduct T9 Go to www freescale com
256. s all sections of the data bus because at the start of a write cycle the bus controller does not know the port size The byte enable signals in the table apply only to read operations that are not to be internally cached and to write operations For cachable read cycles during which the data is cached the addressed port must drive all sections of the bus on which it resides TE For Mars formation Un This Product IA Go to www freescale com Freescale Semiconductor Inc Bus Operation Table 7 7 Data Bus Write Enable Signals for Byte Word and Long Word Ports Transfer Data Bus Active Sections Size xai aed p Byte B Word W Long Word L Ports D31 D24 D23 D16 D15 D8 D7 DO Byte 0 1 0 0 BWL 0 1 0 1 B WL 0 1 1 0 BW L 0 1 1 1 B W L Word 1 0 0 0 BWL WL 1 0 0 1 B WL L 1 0 1 0 BW W L L 1 0 1 1 B W L 3 Byte 1 1 0 0 BWL WL L 1 1 0 1 B WL L L 1 1 1 0 BW W L L 1 1 1 1 B W L Long Word 0 0 0 0 BWL WL L L 0 0 0 1 B WL L L 0 0 1 0 BW W L L 0 0 1 1 B W L The table shows that the MC68030 transfers the number of bytes specified by the size signals to or from the specified address unless the operand is misaligned or the number of bytes is greater than the port width In these cases the device transfers the greatest number of bytes possible for the port For example if the size is four bytes and the address offset A1 A0 is 01 a 32 bit slave can only r
257. scription of the use of this signal by an emulator For Mare formation Un This Product IA Go to www freescale com Signal Description Freescale Semiconductor Inc 5 12 CLOCK CLK The clock signal is the clock input to the MC68030 It is a TTL compatible signal Refer to Section 12 Applications Information for suggestions on clock generation 5 13 POWER SUPPLY CONNECTIONS The MC68030 requires connection to a Vcc power supply positive with respect to ground The Vcc connections are grouped to supply adequate current for the various sections of the processor The ground connections are similarly grouped Section 14 Ordering Information and Mechanical Data describes the groupings of Vcc and ground connections and Section 12 Applications Information describes a typical power supply interface 5 14 SIGNAL SUMMARY Table 5 2 provides a summary of the electrical characteristics of the signals discussed in this section T For More tora BR Un his Product MOTOROLA C Go to www freescale com Signal Description Freescale Semiconductor Inc Table 5 2 Signal Summary Go to www freescale com Signal Function Signal Name Input Output Active State Three State Function Codes FCO FC2 Output High Yes Address Bus A0 A31 Output High Yes Data Bus DO D31 Input Output High Yes Transfer Size SIZO SIZ1
258. sor should set this bit when it shares data with the user task or when any task maps multiple logical addresses to one physical address If the data cache is disabled or frozen the WA bit is ignored 6 3 1 2 DATA BURST ENABLE Bit 12 the DBE bit is set to enable burst filling of the data cache Operating systems and other software set this bit when burst filling of the data cache is desired A reset operation clears the DBE bit 6 3 1 3 CLEAR DATA CACHE Bit 11 the CD bit is set to clear all entries in the data cache Operating systems and other software set this bit to clear data from the cache prior to a context switch The processor clears all valid bits in the data cache at the time a MOVEC instruction loads a one into the CD bit of the CACR The CD bit is always read as a zero 6 3 1 4 CLEAR ENTRY IN DATA CACHE Bit 10 the CED bit is set to clear an entry in the data cache The index field of the CAAR see Figure 6 15 corresponding to the index and long word select portion of an address specifies the entry to be cleared The processor clears only the specified long word by clearing the valid bit for the entry at the time a MOVEC instruction loads a one into the CED bit of the CACR regardless of the states of the ED and FD bits The CED bit is always read as a zero eae For TES 3030 USER ion n YANYAL Product MOTOROLA Go do www freescale com Freescale Semiconductor Inc chio Cache Memories 6 3 1 5 FREEZE DATA CACHE Bit 9 th
259. specified from the assertion of AS to the assertion of DSACKx Although the processor can transfer data in a minimum of three clock cycles when the cycle is terminated with DSACKx the processor inserts wait cycles in clock period increments until DSACKx is recognized The BERR and or HALT signals can be asserted after the DSACKx signal s is asserted BERR and or HALT must be asserted within the time given as parameter 48 after DBACKx is asserted in any asynchronous system If this maximum delay time is violated the processor may exhibit erratic behavior MOTOROLA For Mol4Qp3030 USER ion On AUS Product Tet Go to www freescale com Bus Operation Freescale Semiconductor Inc For asynchronous read cycles the value of CIIN is internally latched on the rising edge of bus cycle state 4 Refer to 7 3 1 Asynchronous Read Cycle for more details on the states for asynchonous read cycles During any bus cycle terminated by DSACKx or BERR the assertion of CBACK is completely ignored 7 2 9 Synchronous Operation with DSACKx Although cycles terminated with the DSACKx signals are classified as asynchronous and cycles terminated with STERM are classified as synchronous cycles terminated with DSACKx can also operate synchronously in that signals are interpreted relative to clock edges The devices that use these cycles must synchronize the responses to the MC68030 clock to be synchronous Since they terminate bus cycles with the DSACKx
260. ss spaces In a multitasking operating system it is more efficient to have a supervisor stack space associated with each user task and a separate stack space for interrupt associated tasks The MC68030 provides two supervisor stacks master and interrupt the M bit of the status register selects which of the two is active When the M bit is set to one supervisor stack pointer references either implicit or by specifying address register A7 access the master stack pointer MSP The operating system sets the MSP for each task to point to a task related area of supervisor data space This separates task related supervisor activity from asynchronous l O related supervisor tasks that may be only coincidental to the currently executing task The master stack MSP can separately maintain task control information for each currently executing user task and the software updates the MSP when a task switch is performed providing an efficient means for transferring task related stack items The other supervisor stack ISP can be used for interrupt control information and workspace area as interrupt handling routines require iis For IC ORO USERS MANYAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Processing States When the M bit is clear the MC68030 is in the interrupt mode of the supervisor privilege level and operation is the same as in the MC68000 MC68008 and MC68010 supervisor mode The processor is in this mode
261. ssor asserts AS indicating that the address on the address bus is valid The processor also asserts DS during S1 If the burst mode is enabled for the appropriate on chip cache and all four long words of the cache entry are invalid i e four long words can be read in CBREQ is asserted In addition the ECS and OCS if asserted signal is negated during S1 MOTOROLA For More Information Un This Albroduct Ba Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2 CLK A31 A0 X FC2 FCO X SIZ1 SIZO RW ECS N CIIN CIOUT CBREQ CBACK DBEN Figure 7 32 Synchronous Read with CIIN Asserted and CBACK Negated State 2 The selected device uses R W SIZO SIZ1 A0 A1 and CIOUT to place its information on the data bus Any or all of the byte sections of the data bus D24 D31 D16 D23 D8 D15 and DO D7 are selected by SIZO SIZ1 and A0 A1 During S2 the processor drives DBEN active to enable external data buffers In systems that use two clock synchronous bus cycles the timing of DBEN may prevent its use At the beginning of S2 the processor samples the level of STERM If STERM is recognized the processor latches the incoming data at the end of S2 If the selected data is not to be cached for the Ps For Mars formation Un This Product IA Go to www freescale com Freescale Semiconductor Inc Bus Operation current cycle or if the device cannot supply
262. stination USP An An USP Rc Rn Rn Rc Rn ea Rn gt destination using DFC ea Rn source using SFC gt Rn data SR immediate data V SR gt SR RESET none none assert RESET line RTE none none SP gt SR SP 2 gt SP SP gt PC SP 4 gt SP Restore stack according to format STOP data 16 immediate data SR STOP Trap Generating BKPT data none run breakpoint cycle then trap as illegal instruction CHK ea Dn 16 32 if Dn lt 0 or Dn gt ea then CHK exception CHK2 ea Rn 8 16 32 if Rn lt lower bound or Rn gt upper bound then CHK exception ILLEGAL none none SSP 2 gt SSP Vector Offset gt SSP SSP 4 gt SSP PC gt SSP SSP 2 2 SSP SR gt SSP Illegal Instruction Vector Address gt PC TRAP data none SSP 2 5 SSP Format and Vector Offset gt SSP SSP 4 gt SSP PC gt SSP SSP 2 gt SSP SR gt SSP Vector Address gt PC TRAPcc none none if cc true then TRAP exception data 16 32 TRAPV none none if V then take overflow TRAP exception Condition Code Register ANDI data CCR 8 immediate data A CCR gt CCR EORI data CCR 8 immediate data CCR gt CCR MOVE ea CCR 16 source gt CCR CCR lt ea 16 CCR destination ORI data CCR 8 immediate data V CCR CCR ae For More Information On This Product A Go to www freescale com Freescale Semiconductor INC struction Set Sima 3 2 10 Memory Management Unit Instructions
263. t are special cases of more general instructions affect the condition codes in the same way Consistency across instances means that all instances of an instruction affect the condition codes in the same way Consistency across uses means that conditional instructions test the condition codes similarly and provide the same results regardless of whether the condition codes are set by a compare test or move instruction In the instruction set definitions the CCR is shown as follows where X extend Set to the value of the C bit for arithmetic operations Otherwise not affected or set to a specified result N negative Set if the most significant bit of the result is set Cleared otherwise Z zero Set if the result equals zero Cleared otherwise V overflow Set if arithmetic overflow occurs This implies that the result cannot be represented in the operand size Cleared otherwise C carry Set if a carry out of the most significant bit of the operand occurs for an addition Also set if a borrow occurs in a subtraction Cleared otherwise i For IC ORO USERS MANWAL product MOTOROLA Go to www freescale com Freescale Semiconductor INC struction Set Sima 3 3 1 Condition Code Computation Most operations take a source operand and a destination operand compute and store the result in the destination location Single operand operations take a destination operand compute and store the result in the destination loca
264. t begin on a byte boundary The extract bit field BFEXTU instruction and the BFTST instruction are the most useful for this application but other bit field instructions can also be used Programming of input and output operations to peripherals requires testing setting and inserting of bit fields in the control registers of the peripherals which is another application for bit field instructions However control register locations are not memory locations therefore it is not always possible to insert or extract bit fields of a register without affecting other fields within the register MOTOROLA For Mo matias ion On AUS Product 29 Go to www freescale com Freescale Semiconductor INC struction Set Simay Another widely used application for bit field instructions is bit mapped graphics Because byte boundaries are ignored in these areas of memory the field definitions used with bit field instructions are very helpful 3 5 4 Pipeline Synchronization with the Nop Instruction Although the no operation NOP instruction performs no visible operation it serves an important purpose It forces synchronization of the integer unit pipeline by waiting for all pending bus cycles to complete All previous integer instructions and floating point external operand accesses complete execution before the NOP begins The NOP instruction does not synchronize the FPU pipeline floating point instructions with floating point register operand destina
265. t cleared invalidated Otherwise if on chip cache entries are valid for pages with descriptors in memory marked invalid processor operation is unpredictable Data read and write accesses to the same address should also have consistent cachability status to ensure that the data in the cache remains consistent with external memory For example if CIOUT is negated for read accesses within a page and the MMU configuration is changed so that CIOUT is subsequently asserted for write accesses within the same page those write accesses do not update data in the cache and stale data may result Similarly when the MMU maps multiple logical addresses to the same physical address all accesses to those logical addresses should have the same cachability status 6 1 1 Instruction Cache The instruction cache is organized with a line size of four long words as shown in Figure 6 2 Each of these long words is considered a separate cache entry as each has a separate valid bit All four entries in a line have the same tag address Burst filling all four long words can be advantageous when the time spent in filling the line is not long relative to the equivalent bus cycle time for four nonburst long word accesses because of the probability that the contents of memory adjacent to or close to a referenced operand or instruction is also required by subsequent accesses Dynamic RAMs supporting fast access modes page nibble or static column are easily emplo
266. ta destination data ea 8 16 32 Dn Dn 8 16 32 destination source X destination An An 8 16 32 3 2 3 Logical Instructions The logical operation instructions AND OR EOR and NOT perform logical operations with all sizes of integer data operands A similar set of immediate instructions ANDI ORI and EORI provide these logical operations with all sizes of immediate data The TST instruction compares the operand with zero arithmetically placing the result in the condition code register Table 3 3 summarizes the logical operations e For More RORO USER ion a YANYAL Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc cio Set Summary Table 3 3 Logical Operations Instruction Operand Syntax Operand Size Operation AND ea Dn 8 16 32 source A destination destination Dn ea 8 16 32 ANDI data ea 8 16 32 immediate data A destination destination EOR Dn data ea 8 16 32 source O destination gt destination EORI data ea 8 16 32 immediate data x destination destination NOT ea 8 16 32 destination destination OR ea Dn 8 16 32 source V destination destination Dn ea 8 16 32 ORI data ea 8 16 32 immediate data V destination gt destination TST ea 8 16 32 source 0 to set condition codes 3 2 4 Shift and Rotate Instructions The arithmetic shift ins
267. ta from the appropriate byte s of the data bus D24 D31 D16 D23 D8 D15 and DO D7 SIZO SIZ1 and A0 A1 select the data bus sections The device asserts STERM when it has successfully stored the data If the device does not assert STERM by the rising edge of S6 the processor inserts wait states until it is recognized The processor asserts DS at the end of S6 if wait states are inserted Note that for zero wait state synchronous write cycles DS is not asserted For Mare formation Un This Product IA Go to www freescale com Freescale Semiconductor Inc Bus Operation State 7 The processor negates AS and DS if necessary during S7 It holds the address and data valid during S7 to simplify memory interfaces R W and FCO FC2 also remain valid throughout S7 If more than one write cycle is required S8 S11 are repeated for each write cycle The external device must negate STERM within two clock periods after asserting it or the processor may inadvertently use STERM for the next bus cycle 7 3 7 Burst Operation Cycles The MC68030 supports a burst mode for filling the on chip instruction and data caches The MC68030 provides a set of handshake control signals for the burst mode When a miss occurs in one of the caches the MC68030 initiates a bus cycle to obtain the required data or instruction stream fetch If the data or instruction can be cached the MC68030 attempts to fill a cache entry Depending on the alignme
268. table structure The transparent translation registers TTO and TT1 can each specify separate blocks of memory as directly accessible without address translation Logical addresses in these areas become the physical addresses for memory access Function codes and the eight most significant bits of the address can be used to define the area of memory and type of access either read write or both types of memory access can be directly mapped The transparent translation feature allows rapid movement of large blocks of data in memory or I O space without disturbing the context of the on chip address translation cache or incurring delays associated with translation table lookups This feature is useful to graphics controller and real time applications i For IC ORO USERS MANYAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc introduction The MMU status register MMUSR contains memory management status information resulting from a search of the address translation cache or the translation tree for a particular logical address 1 4 DATA TYPES AND ADDRESSING MODES Seven basic data types are supported 1 Bits Bit Fields Fields of consecutive bits 1 32 bits long BCD Digits Packed 2 digits byte Unpacked 1 digit byte Byte Integers 8 bits Word Integers 16 bits Long Word Integers 32 bits 7 Quad Word Integers 64 bits In addition the instruction set supports operations on other data types s
269. tack pointer USP is the active system stack pointer and the master and interrupt stack pointers cannot be referenced When S 1 indicating supervisor mode at supervisor privilege level and M 1 the master stack pointer MSP is the active system stack pointer When S 1 and M 0 the interrupt stack pointer ISP is the active system stack pointer This mode is the MC68030 default mode after reset and corresponds to the MC68000 MC68008 and MC68010 supervisor mode The term supervisor stack pointer SSP refers to the master or interrupt stack pointers depending on the state of the M bit When M 1 the term SSP or A7 refers to the MSP address register When M 0 the term is implicitly referenced by all instructions that use the system stack Each system stack fills from high to low memory For Mars formation Un This Product IA Go to www freescale com Freescale Semiconductors dne Addressing Capabilities UNABLE TO LOCATE ART MUST BE RECREATED Figure 2 15 M68000 Family Address Extension Words A subroutine call saves the program counter on the active system stack and the return restores it from the active system stack During the processing of traps and interrupts both the program counter and the status register are saved on the supervisor stack either master or interrupt Thus the execution of supervisor code is independent of user code and the condition of the user stack conversely user programs use the user stack p
270. tate 0 to state 4 BGACK alone can be used to place the processor s external bus buffers in the high impedance state providing single wire arbitration capability The read modify write sequence is normally indivisible to support semaphore operations and multiprocessor synchronization During this indivisible sequence the MC68030 asserts the RMC signal and causes the bus arbitration state machine to ignore bus requests assertions of BR that occur after the first read cycle of the read modify write sequence by not issuing bus grants asserting BG In some cases however it may be necessary to force the MC68030 to release the bus during an read modify write sequence One way for an alternate bus master to force the MC68030 to release the bus applies only to the first read cycle of an read modify write sequence The MC68030 allows normal bus arbitration during this read cycle a normal relinquish and retry operation asserting BERR HALT and BR at the same time is used Note that this method applies only to the first read cycle of the read modify write sequence but this method preserves the integrity of the read modify write sequence without imposing any constraint on the alternate bus master A second method is single wire arbitration the timing of which is shown in Figure 7 62 An alternate master forces the MC68030 to release the bus by asserting BGACK and waits for AS to negate before taking the bus It applies to all bus cycles of a
271. te is reached during which G changes The bus control signals controlled by T are driven by the processor immediately following a state change when bus mastership is returned to the MC68030 State 0 at the top center of the diagram in which G and T are both negated is the state of the bus arbiter while the processor is bus master Request R and acknowledge A keep the arbiter in state O as long as they are both negated When a request R is received both grant G and signal T are asserted in state 1 at the top left The next clock causes a change to state 2 at the lower left in which G and T are held The bus arbiter remains in that state until acknowledge A is asserted or request R is negated Once either occurs the arbiter changes to the center state state 3 and negates grant G The next clock takes the arbiter to state 4 at the upper right in which grant G remains negated and signal T remains asserted With acknowledge A asserted the arbiter remains in state 4 until A is negated or request R is nio For MUS ARO USOS UA TIAE Product MOTOROLA Go to www freescale com Bus Operation Freescale Semiconductor Inc again asserted When A is negated the arbiter returns to the original state state 0 and negates signal T This sequence of states follows the normal sequence of signals for relinquishing the bus to an external bus master Other states apply to other possible sequences of combinations of R and A As shown by the path from s
272. tem on the stack This is illustrated as LOW MEMORY An yg FREE TOP OF STACK e BOTTOM OF STACK HIGH MEMORY To implement stack growth from low to high memory use An to push data on the stack An to pull data from the stack a For MUS ARO USOS UA TIAE Product MOTOR Go to www freescale com Freescale Semiconductor dne Addressing Capabilities In this case after either a push or pull operation register An points to the next available space on the stack This is illustrated as LOW MEMORY BOTTOM OF STACK e e e TOP OF STACK An FREE HIGH MEMORY 2 8 3 Queues The user can implement queues with the address register indirect with postincrement or predecrement addressing modes Using a pair of address registers who of A0 A6 the user can implement a queue which is filled either from high to low memory or from low to high memory Two registers are used because queues are pushed from one end and pulled from the other One register An contains the put pointer the other Am the get pointer To implement growth of the queue from low to high memory use An to put data into the queue Am to get data from the queue After a put operation the put address register points to the next available space in the queue and the unchanged get address register points to the next item to be removed from the queue After a get operation the get address registe
273. terminates the bus cycle places the control signals in their inactive state and does not begin another bus cycle until the HALT signal is negated by external logic After a synchronization delay the processor retries the previous cycle using the same access information address function code size etc The BERR signal should be negated before S2 of the read cycle to ensure correct operation of the retried cycle Figure 7 54 shows a retry operation of an asynchronous cycle and Figure 7 55 shows a retry operation of a synchronous cycle The processor retries any read or write cycle of a read modify write operation separately RMC remains asserted during the entire retry sequence On the initial access of a burst operation a retry indicated by the assertion of BERR and HALT causes the processor to retry the bus cycle and assert CBREQ again Figure 7 56 shows a late retry operation that causes an initial burst operation to be repeated However signaling a retry with simultaneous BERR and HALT during the second third or fourth cycle of a burst operation does not cause a retry operation even if the requested operand is misaligned Assertion of BERR and HALT during a subsequent cycle of a burst operation causes independent BERR and HALT operations The external bus activity remains halted until HALT is negated and the processor acts as previously described for the bus error during a burst operation Asserting BR
274. the EU after the first cycle is complete The microsequencer must wait for the burst operation to complete before requesting the second portion of the operand Normally the request for the second portion results in a data cache hit unless the second cycle of the burst operation terminates abnormally BURST OPERATION gt gt CYCLE 1 CYCLE 2 CYCLE 3 CYCLE 4 FIRST ACCESS OF BURST OPERATION REQUIRED BURST FILL CYCLE BURST FILL CYCLE BURST FILL CYCLE OPERAND OR PREFETCH BURST MODE REQUESTED AND BURST MODE BEGINS HERE ACKNOWLEDGED Figure 6 11 Burst Operation Cycles and Burst Mode The bursting mechanism allows addresses to wrap around so that the entire four long words in the cache line can be filled in a single burst operation regardless of the initial address and operand alignment Depending on the structure of the external memory system address bits A2 and A3 may have to be incremented externally to select the long words in the proper order for loading into the cache The MC68030 holds the entire address bus constant for the duration of the burst cycle Figure 6 12 shows an example of this address wraparound The initial cycle is a long word access from address 6 Because the responding device returns CBACK and STERM signaling a 32 bit port the entire long word at base address 04 is transferred Since the initial address is 06 when CBREQ is asserted the next entry to be burst filled into the cache should correspond
275. the MMU performs logical to physical address translation in parallel with the cache lookup in case an external cycle is required moe For Mold jetorimatien On This Product ai Go to www freescale com On Chip Cache Memories Freescale Semiconductor Inc V1Va 83dina STVNOIS TOULNOO SN aHOWO U3TIOHINOO viva sng SNBOHOIN SSIYOOY u344n8 ONIGNAd HO13438d ONIGNAd 3 LIHM HATIOUL sna X SS3uaav O Q sna savd LOA NOILO3S NOLLOAS viva viva 3718 VIVA SS3udav Ss3uaav 9 C9 sna SS3udav LINA NOLLOO3X3 NOLLONELSNI AHOVO NOILONYLSNI sna vivd TWNYALNI HHY9 Y31SI038 ONIG1OH 3HOVI TOHINOD ANY YJONINOISOHINN 3dld NOILONYLSNI SQvd Ssduqaqv sna Ss3qadav Figure 6 1 Internal Caches and the MC68030 MOTOROLA MANWAL Product 0 USE S ormation Go to www freescale com Sine For male 6 2 Freescale Semiconductor Inc chio Cache Memories 6 1 ON CHIP CACHE ORGANIZATION AND OPERATION Both on chip caches are 256 byte direct mapped caches each organized as 16 lines Each line consists of four entries and each entry contains four bytes The tag field for each line contains a valid bit for each entry in the line each entry is independently replaceable When appropriate the bus control
276. the relevant address register should be checkout and adjusted if necessary The address register is adjusted by adding the buffer length in bytes to the register contents 2 For MUS RA USOS BANAL Product MOTOR Go to www freescale com Freescale Semiconductor Inc SECTION 3 INSTRUCTION SET SUMMARY This section briefly describes the MC68030 instruction set Refer to the MC68000PM AD MC68000 Programmer s Reference Manual for complete details on the MC68030 instruction set The following paragraphs include descriptions of the instruction format and the operands used by instructions followed by a summary of the instruction set The integer condition codes and floating point details are discussed Programming examples for selected instructions are also presented 3 1 INSTRUCTION FORMAT All MC68030 instructions consist of at least one word some have as many as 11 words see Figure 3 1 The first word of the instruction called the operation word specifies the length of the instruction and the operation to be performed The remaining words called extension words further specify the instruction and operands These words may be floating point command words conditional predicates immediate operands extensions to the effective address mode specified in the operation word branch displacements bit number or bit field specifications special register specifications trap operands pack unpack constants or argument counts OPERATI
277. tion Table 3 12 lists each instruction and how it affects the condition code bits Table 3 12 Condition Code Computations Sheet 1 of 2 Operations X N Z V C Special Definition ABCD C Decimal Carry Z ZARmA ARO ADD ADDI ADDQ V Sm A Dm A Rm V Sm A Dm A Rm C Sm A Dm V Rm A Dm V Sm A Rm V Sm A Dm A Rm V Sm A Dm A Rm C Sm A Dm V Rm A Dm V Sm A Rm Z ZARmA ARO AND ANDI EOR EORI MOVEQ MOVE OR ORI CLR EXT NOT TAS TST CHK CHK2 CMP2 Z R 2 LB V R UB C LB lt UB A IR lt LB V R gt UB V UB LB A R UB A R LB SUB SUBI SUBQ V2 Sm A Dm A Rm V Sm A Dm A Rm C Sm A Dm V Rm A Dn V Sm A Rm SUBX 2 V2 Sm A Dm A Rm V Sm A Dm A Rm C Sm A Dm V Rm A Dm V Sm A Rm Z ZARmA ARO CAS CAS2 CMP CMPI V Sm A Dm A Rm V Sm A Dm A Rm CMPM C Sm A Dm V Rm A Dm V Sm A Rm DIVS DUVI p EL ENG V Division Overflow MULS MULU 7 0 V Multiplication Overflow SBCD NBCD U U C Decimal Borrow Z ZARmA ARO NEG 2 V DmARm C Dm V Rm NEGX 2 2 V DmARm C Dm V Rm Z ZARmA ARO MIA For More information On This Product sue Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc Table 3 12 Condition Code Computations Continued Operations X IN Z V C Special Definition BTST BCHG BSET
278. tions Table 3 6 Bit Field Operations Instruction Operand Syntax Operand Size Operation BFCHG ea offset width 1 32 Field Field BFCLR ea offset width 1 322 0 s gt Field BFEXTS ea offset width Dn 1 32 Field Dn Sign Extended BFEXTU ea offset width Dn 1 32 Field gt Dn Zero Extended BFFFO ea offset width Dn 1 32 Scan for first bit set in field offset gt Dn BFINS Dn ea offset width 1 32 Dn gt Field BFSET ea offset width 1 32 1 s gt Field BFTST ea offset width 1 32 Field MSB gt N OR of all bits in field gt Z NOTE All bit field instructions set the N and Z bits as shown for BFTST before performing the specified operation VOTERA For Mold jetorimatien On This Product 99 Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc 3 2 7 Binary coded Decimal Instructions Five instructions support operations on binary coded decimal BCD numbers The arithmetic operations on packed BCD numbers are add decimal with extend ABCD subtract decimal with extend SBCD and negate decimal with extend NBCD PACK and UNPACK instructions aid in the conversion of byte encoded numeric data such as ASCII or EBCDIC strings to BCD data and vice versa Table 3 7 is a summary of the BCD operations Table 3 7 BCD Operations Instruction Operand Syntax Operand Size Operation ABCD Dn Dn 8 source y destination
279. tions can be executing when the NOP begins moe For Mold jetorimatien On This Product 99s Go to www freescale com Freescale Semiconductor Inc SECTION 4 PROCESSING STATES This section describes the processing states of the MC68030 It describes the functions of the bits in the supervisor portion of the status register and the actions taken by the processor in response to exception conditions Unless the processor has halted it is always in either the normal or the exception processing state Whenever the processor is executing instructions or fetching instructions or operands it is in the normal processing state The processor is also in the normal processing state while it is storing instruction results or communicating with a coprocessor NOTE Exception processing refers specifically to the transition from normal processing of a program to normal processing of system routines interrupt routines and other exception handlers Ex ception processing includes all stacking operations the fetch of the exception vector and filling of the instruction pipe caused by an exception It has completed when execution of the first in struction of the exception handler routine begins The processor enters the exception processing state when an interrupt is acknowledged when an instruction is traced or results in a trap or when some other exceptional condition arises Execution of certain instructions or unusual conditions occurring during t
280. tive Take Address and Transfer Data Primitive Transfer to from Top of Stack Primitive Transfer Single Main Processor Register Primitive Transfer Main Processor Control Register Primitive Transfer Multiple Main Processor Registers Primitive Transfer Multiple Coprocessor Registers Primitive Transfer Status Register and ScanPC Primitive Take Pre Instruction Exception Primitive Take Mid Instruction Exception Primitive Take Post Instruction Exception Primitive EXGODIOLIS x ese des Shoe cl cien s d eu ARAN Bagana dee eife A A MEN Coprocessor Detected Exceptions aa Coprocessor Detected Protocol Violations Coprocessor Detected Illegal Command or Condition Words Coprocessor Data Processing Exceptions Coprocessor System Related Exceptions Format ENDS ka dobla E a o bdo rico Main Processor Detected Exceptions Protocol Violations aos dox doo ia ha ees dile F Line Emulator Exceptions aanne Privilege Violations nannaa hee deme i ahahhaha tn e cpTRAPcc Instruction Traps xu opes rure sr rex EE Trace EXCODIIODS S voce pi DE 4 te eked GN EEUU DEP A MC68030 USER S MANUAL For More Information On This Product Go to www freescale com Page Number 10 31 10 3
281. to An 10 39 Transfer Status Register and ScanPC Primitive Format 10 40 Take Pre Instruction Exception Primitive Format 10 41 MC68030 Pre Instruction Stack Frame aaa 10 42 Take Mid Instruction Exception Primitive Format 10 43 MC68030 Mid Instruction Stack Frame 200000 00s 10 44 Take Post Instruction Exception Primitive Format 10 45 MC68030 Post Instruction Stack Frame 11 1 Block Diagram Eight Independent Resources 11 2 Simultaneous Instruction Execution 11 3 Derivation of Instruction Overlap Time 11 4 Processor Activity Even Alignment 11 5 Processor Activity Odd Alignment 0 0 005 12 1 Signal Routing for Adapting the MC68030 to MC68020 Designs 12 2 32 Bit Data Bus Coprocessor Connection 05 12 3 Chip Select Generation PAL 0 00022 e eee eee 12 4 PAL Equations cue ioa oo Bees oh Ghat ie doe irap 12 5 Bus Cycle Timing Diagram 0 002 eee 12 6 Example MC68030 Byte Select PAL System Configuration 12 7 MC68030 Byte Select PAL Equations 005 12 8 Access Time Computation Diagram 000 0c eee eee 12 9 Example Two Clock Read Three Clock Write Memory Bank 12 10 Example PAL Equations for Two Clock Memory Bank 12 11 Additional Memory Enable Circuits ooooocooooooo o 1
282. to abort If the bus error occurs during the first cycle of a burst i e before burst mode is entered the data read from the bus is ignored and the entire associated cache line is marked invalid If the access is a data cycle exception processing proceeds immediately If the cycle is for an instruction fetch a bus error exception is made pending This bus error is processed only if the execution unit attempts to use either instruction word Refer to 11 2 2 Instruction Pipe for more information about pipeline operation For either cache when a bus error occurs after the burst mode has been entered that is on the second cycle or later the cache entry corresponding to that cycle is marked invalid but the processor does not take an exception the microsequencer has not yet requested the data In the case of an instruction cache burst the data from the aborted cycle is completely ignored Pending instruction prefetches are still pending and are subsequently run by the processor If the second cycle is for a portion of a misaligned data operand fetch and a bus error occurs the processor terminates the burst operation and negates CBREQ Once the burst terminates the microsequencer requests a read cycle for the second portion Since the burst terminated abnormally for the second cycle of the burst the data cache is For IC ORO USERS MANWAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc chio Cache Membres resul
283. trical Specifications for timing requirements This or some equivalent precaution should be designed into the external circuitry that provides these signals The acceptable bus cycle terminations for asynchronous cycles are summarized in relation to DSACKx assertion as follows case numbers refer to Table 7 8 Normal Termination DSACKx is asserted BERR and HALT remain negated case 1 Halt Termination HALT is asserted at same time or before DSACKx and BERR remains negated case 2 Bus Error Termination BERR is asserted in lieu of at the same time or before DSACKx case 3 or after DSACKx case 4 and HALT remains negated BERR is negated at the same time or after DSACKx Retry Termination HALT and BERR are asserted in lieu of at the same time or before DSACKx case 5 or after DSACKx case 6 BERR is negated at the same time or after DSACKx HALT may be negated at the same time or after BERR For Mare formation Un This Product MOTOBOLA Go to www freescale com Freescale Semiconductor Inc Bus Operation Table 7 8 DSACK BERR and HALT Assertion Results Case Control Asserted on Rising Result No Signal Edge of State N N 2 1 DSACKx A S Normal cycle terminate and continue BERR NA NA HALT NA X 2 DSACKx A S Normal cycle terminate and halt Continue when HALT BERR NA NA negated HALT A S S 3 DSACKx NA A X Terminate and take bus error exception
284. trol Register o oo ed eae Eran rtm LL Ets 6 15 Cache Address Register ooooooooooooomnmmo 7 1 Relationship between External and Internal Signals 7 2 Asynchronous Input Sample Window 200000 7 3 Internal Operand Representati0N ooooooccocoooo 7 4 MC68030 Interface to Various Port Sizes 7 5 Example of Long Word Transfer to Word Port 7 6 Long Word Operand Write Timing 16 Bit Data Port 7 7 Example of Word Transfer to Byte Port 7 8 Word Operand Write Timing 8 Bit Data Port 7 9 Misaligned Long Word Transfer to Word Port Example 710 Misaligned Long Word Transfer to Word Port 7 11 Misaligned Cachable Long Word Transfer from Word Port Example 7 12 Misaligned Word Transfer to Word Port Example 7 13 Misaligned Word Transfer to Word Port aaa 7 14 Example of Misaligned Cachable Word Transfer from Word Bus 7 15 Misaligned Long Word Transfer to Long Word Port 716 Misaligned Write Cycles to Long Word Port 7 17 Misaligned Cachable Long Word Transfer from Long Word Bus 7 18 Byte Data Select Generation for 16 and 32 Bit Ports 7 19 Asynchronous Long Word Read Cycle Flowchart 7 20 Asynchronous Byte Read Cycle Flowchart 7 21 Asynchronous Byte and
285. truction loads a one into the Cl bit of the CACR The Cl bit is always read as a zero 6 3 1 9 CLEAR ENTRY IN INSTRUCTION CACHE Bit 2 the CEI bit is set to clear an entry in the instruction cache The index field of the CAAR see Figure 6 15 corresponding to the index and long word select portion of an address specifies the entry to be cleared The processor clears only the specified long word by clearing the valid bit for the entry at the time a MOVEC instruction loads a one into the CEI bit of the CACR regardless of the states of the El and FI bits The CEI bit is always read as a zero MOTOROLA For Mo matias ion On AUS Product oe Go to www freescale com On Chip Cache Memories Freescale Semiconductor Inc 6 3 1 10 FREEZE INSTRUCTION CACHE Bit 1 the FI bit is set to freeze the instruction cache When the FI bit is set and a miss occurs in the instruction cache the entry or line is not replaced When the FI bit is cleared to zero a miss in the instruction cache causes the entry or line to be filled A reset operation clears the FI bit 6 3 1 11 ENABLE INSTRUCTION CACHE Bit 0 the El bit is set to enable the instruction cache When it is cleared the instruction cache is disabled A reset operation clears the El bit The supervisor normally enables the instruction cache but it can clear El for system debugging or emulation as required Disabling the instruction cache does not flush the entries If it is enabled again the
286. tructions ASR and ASL and logical shift instructions LSR and LSL provide shift operations in both directions The ROR ROL ROXR and ROXL instructions perform rotate circular shift operations with and without the extend bit All shift and rotate operations can be performed on either registers or memory Register shift and rotate operations shift all operand sizes The shift count may be specified in the instruction operation word to shift from 1 8 places or in a register modulo 64 shift count Memory shift and rotate operations shift word length operands one bit position only The SWAP instruction exchanges the 16 bit halves of a register Performance of shift rotate instructions is enhanced so that use of the ROR and ROL instructions with a shift count of eight allows fast byte swapping Table 3 4 is a summary of the shift and rotate operations moe For Mold jetorimatien On This Product 37 Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc Table 3 4 Shift and Rotate Operations 9p AA P NEN 3 2 5 Bit Manipulation Instructions Bit manipulation operations are accomplished using the following instructions bit test BTST bit test and set BSET bit test and clear BCLR and bit test and change BCHG All bit manipulation operations can be performed on either registers or memory The bit number is specified as immediate dat
287. ts in a miss and a second external cycle is required If BERR is again asserted the MC68030 then takes an exception On the initial access of a burst operation a retry indicated by the assertion of BERR and HALT causes the processor to retry the bus cycle and assert CBREQ again However signaling a retry with simultaneous BERR and HALT during the second third or fourth cycle of a burst operation does not cause a retry operation even if the requested operand is misaligned Assertion of BERR and HALT during burst fill cycles of a burst operation causes independent bus error and halt operations The processor remains halted until HALT is negated and then handles the bus error as described in the previous paragraphs 6 2 CACHE RESET When a hardware reset of the processor occurs all valid bits of both caches are cleared The cache enable bits burst enable bits and the freeze bits in the cache control register CACR for both caches refer to Figure 6 14 are also cleared effectively disabling both caches The WA bit in the CACR is also cleared 6 3 CACHE CONTROL Only the MC68030 cache control circuitry can directly access the cache arrays but the supervisor program can set bits in the CACR to exercise control over cache operations The supervisor also has access to the cache address register CAAR which contains the address for a cache entry to be cleared 6 3 1 Cache Control Register The CACR shown in Figure 6
288. ty to the instructions and data currently in use also have a high probability of being utilized within a short period To exploit these locality characteristics the MC68030 contains two on chip logical caches a data cache and an instruction cache Each of the caches stores 256 bytes of information organized as 16 entries each containing a block of four long words 16 bytes The processor fills the cache entries either one long word at a time or during burst mode accesses four long words consecutively The burst mode of operation not only fills the cache efficiently but also captures adjacent instruction or data items that are likely to be required in the near future due to locality characteristics of the executing task The caches improve the overall performance of the system by reducing the number of bus cycles required by the processor to fetch information from memory and by increasing the bus bandwidth available for other bus masters in the system Addition of the data cache in the MC68030 extends the benefits of cache techniques to all memory accesses During a write cycle the data cache circuitry writes data to a cached data item as well as to the item in memory maintaining consistency between data in the cache and that in memory However writing data that is not in the cache may or may not cause the data item to be stored in the cache depending on the write allocation policy selected in the cache control register CACR moe For Mold
289. typically returns BERR The MC68030 automatically generates the spurious interrupt vector number 24 instead of the interrupt vector number in this case If HALT is also asserted the processor retries the cycle 7 4 2 Breakpoint Acknowledge Cycle The breakpoint acknowledge cycle is generated by the execution of a breakpoint instruction BKPT The breakpoint acknowledge cycle allows the external hardware to provide an instruction word directly into the instruction pipeline as the program executes This cycle accesses the CPU space with a type field of zero and provides the breakpoint number specified by the instruction on address lines A2 A4 If the external hardware terminates the cycle with DSACKx or STERM the data on the bus an instruction word is inserted into the instruction pipe replacing the breakpoint opcode and is executed after the breakpoint acknowledge cycle completes The breakpoint instruction requires a word to be transferred so that if the first bus cycle accesses an 8 bit port a second cycle is required If the external logic terminates the breakpoint acknowledge cycle with BERR i e no instruction word available the processor takes an illegal instruction exception Figure 7 46 is a flowchart of the breakpoint acknowledge cycle Figure 7 47 shows the timing for a breakpoint acknowledge cycle that returns an instruction word Figure 7 48 shows the timing for a breakpoint acknowledge cycle that signals an exception
290. uch as memory addresses The coprocessor mechanism allows direct support of floating point operations with the MC68881 and MC68882 floating point coprocessors as well as specialized user defined data types and functions D Ci WwW N The 18 addressing modes shown in Table 1 1 include nine basic types 1 Register Direct Register Indirect Register Indirect with Index Memory Indirect Program Counter Indirect with Displacement Program Counter Indirect with Index Program Counter Memory Indirect Absolute 9 Immediate ON DO FB O N The register indirect addressing modes can also postincrement predecrement offset and index addresses The program counter relative mode also has index and offset capabilities As in the MC68020 both modes are extended to provide indirect reference through memory In addition to these addressing modes many instructions implicitly specify the use of the condition code register stack pointer and or program counter 1 5 INSTRUCTION SET OVERVIEW The instructions in the MC68030 instruction set are listed in Table 1 2 The instruction set has been tailored to support structured high level languages and sophisticated operating systems Many instructions operate on bytes words or long words and most instructions can use any of the 18 addressing modes MOTOROLA For More datori atrar ion on This Product e Go to www freescale com Introduction Freescale Semiconductor Inc Table
291. um of 520 clocks after Vcc is within tolerance Figure 7 64 is a timing diagram of the powerup reset operation showing the relationships between RESET Vee and bus signals The clock signal is required to be stable by the time Vcc reaches the minimum operating specification During the reset period the entire bus three states except for non three statable signals which are driven to their inactive state Once RESET negates all control signals are driven to their inactive state the data bus is in read mode and the address bus is driven After this the first bus cycle for reset exception processing begins nio For MUS RA USOS BANAL Product Hoon Go to www freescale com Bus Operation Freescale Semiconductor Inc S4 S0 RAM AU AN Eq ns ECS DSACK1 DSACKO AA aaa a oL BGACK N BUS INACTIVE CONTROLLER ARBITRATION PERMITTED yy ALTERNATE MASTER lt CONTROLLER WHILE THE CONTROLLER IS INACTIVE OR HALTED Figure 7 63 Bus Arbitration Operation Bus Inactive The external RESET signal resets the processor and the entire system Except for the initial reset RESET should be asserted for at least 520 clock periods to ensure that the processor resets Asserting RESET for 10 clock periods is sufficient for resetting the processor logic the additional clock periods prevent a reset instruction from overlapping the external RESET signal dls For MUS ARO USOS VANE Product MOTOROLA Go to
292. upervisor functions and vary in size With the exception of the user portion of the status register CCR they are accessed only by instructions at the supervisor privilege level The status register SR shown in Figure 1 4 is 16 bits wide Only 12 bits of the status register are defined all undefined values are reserved by Motorola for future definition The undefined bits are read as zeros and should be written as zeros for future compatibility The lower byte of the status register is the CCR Operations to the CCR can be performed at the supervisor or user privilege level All operations to the status register and CCR are word sized operations but for all CCR operations the upper byte is read as all zeros and is ignored when written regardless of privilege level i For IC ORO USER S MANWAL product MOTOROLA Go to www freescale com Freescale Semiconductors dne Addressing Capabilities The supervisor programming model see Figure 1 3 shows the control registers The cache control register CACR provides control and status information for the on chip instruction and data caches The cache address register CAAR contains the address for cache control functions The vector base register VBR provides the base address of the exception vector table All operations involving the CACR CAAR and VBR are long word operations whether these registers are used as the source or the destination operand The alternate function code registe
293. us and drives CIIN if appropriate Any or all of the bytes D24 D31 D16 D23 D8 D15 and D0O D7 are selected by SIZO SIZ1 and A0 A1 Concurrently the selected device asserts DSACKx State 3 As long as at least one of the DSACKx signals is recognized by the end of S2 meeting the asynchronous input setup time requirement data is latched on the next falling edge of the clock and the cycle terminates If DSACKx is not recognized by the start of state 3 S3 the processor inserts wait states instead of proceeding to states 4 and 5 To ensure that wait states are inserted both DSACKO and DSACK1 must remain negated throughout the asynchronous input setup and hold times around the end of S2 If wait states are added the processor continues to sample the DSACKx signals on the falling edges of the clock until one is recognized State 4 The processor samples CIIN at the beginning of state 4 S4 Since CIIN is defined as a synchronous input whether asserted or negated it must meet the appropriate synchronous input setup and hold times on every rising edge of the clock while AS is asserted At the end of S4 the processor latches the incoming data State 5 The processor negates AS DS and DBEN during state 5 S5 It holds the address valid during S5 to provide address hold time for memory systems R W SIZO SIZ1 and FCO FC2 also remain valid throughout S5 The external device keeps its data and DSACKx signals asserted until it detects
294. us Request External devices capable of becoming bus masters request the bus by asserting BR This can be a wire ORed signal although it need not be constructed from open collector devices that indicates to the processor that some external device requires control of the bus The processor is effectively at a lower bus priority level than the external device and relinquishes the bus after it has completed the current bus cycle if one has started If no acknowledge is received while the BR is active the processor remains bus master once BR is negated This prevents unnecessary interference with ordinary processing if the arbitration circuitry inadvertently responds to noise or if an external device determines that it no longer requires use of the bus before it has been granted mastership i For MUS RA USOS BANAL Product Moreno Go to www freescale com Bus Operation Freescale Semiconductor Inc S0 S2 S4 S0 S2 RW MW SY ECS OCS DSACK1 DSACKO D31 DO _ y NT T BGACK N CONTROLLER pas DMA DEVICE x lt CONTROLLER Figure 7 60 Bus Arbitration Operation Timing 7 7 2 Bus Grant The processor asserts BG as soon as possible after receipt of BR This is immediately following internal synchronization except during a read modify write cycle or following an internal decision to execute a bus cycle During a read modify write cycle the processor does not assert BG until the entire operatio
295. ute address with single variable name disp Pc Simple PC relative The addressing modes defined in programming terms which are derivations of the addressing modes provided by the MC68030 architecture are as follows Immediate Data data The data is a constant located in the instruction stream Register Direct Rn The contents of a register contain the operand Scanning Modes An MOTOROLA For Mold jetorimatien On This Product is Go to www freescale com Data Organization and Addk LRG ERAMReMiconductor Inc Address register pointer automatically incremented after use An Address register pointer automatically decremented before use Absolute Address addr Absolute address in data space psaddr ZPC Absolute address in program space Symbol ZPC suppresses the PC but retains PC relative mode to directly access the program space Register Pointer Rn Register as a pointer disp Rn Register as a pointer with constant index or base address Indexing An Rn Register pointer An with variable index Rn disp An Rn Register pointer with constant and variable index or a base address with a variable index addr Rn Absolute address with two variable indexes Subscripting An Rn scale Address register pointer subscript disp An Rn scale Address register pointer subscript with constant displacement or base address with subscript addr Rn scale Absolute address w
296. valuates to zero the condition is false For example the T condition is always true and the EQ condition is true only if the Z bit condition code is currently true Table 3 13 Conditional Tests Mnemonic Condition Encoding True 0000 False 0001 High Low or Same Carry Clear T F HI LS CC HS CS LO Carry Set NE Not Equal EQ Equal VC VS PL MI GE LT GT Overflow Clear Overflow Set Ola Z lt lt N IN olo NIN Plus Minus N Greater or Equal NeV NeV Less Than NeV NeV Greater Than 1110 NeVeZ NeVez LE Less or Equal 1111 Z NeViNeV Boolean AND Boolean OR N Boolean NOT N Not available for the Bcc instruction moe For Mold jetorimatien On This Product d Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc 3 4 INSTRUCTION SET SUMMARY Table 3 14 provides a alphabetized listing of the MC68030 instruction set listed by opcode operation and syntax Table 3 14 use notational conventions for the operands the subfields and qualifiers and the operations performed by the instructions In the syntax descriptions the left operand is the source operand and the right operand is the destination operand The following list contains the notations used in Table 3 14 Notation for operands PC Program counter SR Status register V Overflow condition code Immediate Data Immediate data from the instruction Sourc
297. vides multiprecision and mixed size arithmetic These instructions are add extended ADDX subtract extended SUBX sign extended EXT and negate binary with extend NEGX Refer to Table 3 2 for a summary of the integer arithmetic operations VOTERA For Mold jetorimatien On This Product 35 Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc Table 3 2 Integer Arithmetic Operations Instruction Operand Syntax Operand Size Operation ADD Dn ea 8 16 32 source destination gt destination ea Dn 8 16 32 ADDA ea An 16 32 ADDI data ea data 8 16 32 immediate data destination destination ea Dn Dn An An ea Dn ea An data ea destination immediate data An An destination source ea Rn 16 lower bound lt Rn lt upper bound DIVS DIVU ea Dn 32 16 gt 16 16 destination source destination signed or unsigned ea Dr Dq 64 32 32 32 ea Dq 32 32 32 DIVSL DIVUL ea Dr Dq 32 32 gt 32 32 EXT Dn 8 516 sign extended destination destination Dn 16 5 32 Dn 8 gt 32 MULS MULU ea Dn 16x16 gt 32 source y destination destination signed or unsigned ea DI 32x32 gt 32 ea Dh DI 32x32 64 ea 8 16 32 0 destination destination ea 8 16 32 0 destination X destination ea Dn 8 16 32 destination source destination Dn ea 8 16 32 ea An 16 32 data ea 8 16 32 destination immediate da
298. visor privilege levels and a CPU address space for processor functions e g coprocessor communications Registers SFC and DFC are used by certain instructions to explicitly specify the function codes for operations USER BYTE SYSTEM BYTE CONDITION CODE REGISTER TRACE ENABLE INTERRUPT PRIORITY MASK CARRY OVERFLOW ZERO NEGATIVE EXTEND SUPERVISOR USER STATE MASTER INTERRUPT STATE Figure 1 4 Status Register The cache control register CACR controls the on chip instruction and data caches of the MC68030 The cache address register CAAR stores an address for cache control functions The CPU root pointer CRP contains a pointer to the root of the translation tree for the currently executing task of the MC68030 This tree contains the mapping information for the task s address space When the MC68030 is configured to provide a separate address space for supervisor routines the supervisor root pointer SRP contains a pointer to the root of the translation tree describing the supervisor s address space The translation control register TC consists of several fields that control address translation These fields enable and disable address translation enable and disable the use of SRP for the supervisor address space and select or ignore the function codes in translating addresses Other fields define the size of memory pages the number of address bits used in translation and the translation
299. xcept the reset vector which is located in supervisor program space Only the initial reset vector is fixed in the processor s memory map once initialization is complete there are no fixed assignments Since the VBR provides the base address of the vector table the vector table can be located anywhere in memory it can even be dynamically relocated for each task that is executed by an operating system Details of exception processing are provided in Section 8 Exception Processing and Table 8 1 lists the exception vector assignments i For MUSEU USERS MANYAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Processing States 4 3 2 Exception Stack Frame Exception processing saves the most volatile portion of the current processor context on the top of the supervisor stack This context is organized in a format called the exception stack frame This information always includes a copy of the status register the program counter the vector offset of the vector and the frame format field The frame format field identifies the type of stack frame The RTE instruction uses the value in the format field to properly restore the information stored in the stack frame and to deallocate the stack space The general form of the exception stack frame is illustrated in Figure 4 1 Refer to Section 8 Exception Processing for a complete list of exception stack frames SP STATUS REGISTER PROGRAM COUNTER FORMAT VECTOR OFFSE
300. y software moe For Mold jetorimatien On This Product e Go to www freescale com idiroduction Freescale Semiconductor Inc 1 7 THE MEMORY MANAGEMENT UNIT The MMU supports virtual memory systems by translating logical addresses to physical ad dresses using translation tables stored in memory The MMU stores address mappings in an address translation cache ATC that contains the most recently used translations When the ATC contains the address for a bus cycle requested by the CPU a translation table search is not performed Features of the MMU include Multiple Level Translation Tables with Short and Long Format Descriptors for Efficient Table Space Usage Table Searches Automatically Performed in Microcode 22 Entry Fully Associative ATC Address Translations and Internal Instruction and Data Cache Accesses Performed in Parallel Eight Page Sizes Available Ranging from 256 to 32K Bytes Two Optional Transparent Blocks User and Supervisor Root Pointer Registers Write Protection and Supervisor Protection Attributes Translations Enabled Disabled by Software Translations Can Be Disabled with External MMUDIS Signal Used and Modified Bits Automatically Maintained in Tables and ATC Cache Inhibit Output CIOUT Signal Can Be Asserted on a Page by Page Basis 32 Bit Internal Logical Address with Capability To Ignore as many as 15 Upper Address Bits 3 Bit Function Code Supports Separate Address Spaces 32 Bit Physical Addres
301. yed to support the MC68030 burst mode i For IC ORO USERS MANYAL product MOTOROLA Go to www freescale com Freescale Semiconductor Inc chip cache Memories LONG WORD SELECT TAG INDEX ACCESS ADDRESS o0 oo e e e e e e e e 1 OF 16 e e e SELECT e e E Tl 1 CHA amio TAG REPLACE VALID DATA TO INSTRUCTION e e gt CACHE HOLDING REGISTER 4 ENTRYHIT _d gt CACHE CONTROL LOGIC LES COMPARATOR LINE HIT CACHE SIZE 64 LONG WORDS LINE SIZE 4 LONG WORDS SET SIZE 1 Figure 6 2 On Chip Instruction Cache Organization When enabled the instruction cache is used to store instruction prefetches instruction words and extension words as they are requested by the CPU Instruction prefetches are normally requested from sequential memory addresses except when a change of program flow occurs e g a branch taken or when an instruction is executed that can modify the status register in which cases the instruction pipe is automatically flushed and refilled The output signal REFILL indicates this condition For more information on the operation of this signal refer to Section 12 Applications Information In the instruction cache each of the 16 lines has a tag consisting of the 24 most significant logical address bits the FC2 function code bit used t

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