ML67Q5260 Preliminary
Contents
1. I A a E A tcLkouT 18 22 PEDL67Q5260 02 OKI SEMICONDUCTOR ML67Q5260 POWER ON OFF SEQUENCE Power ON sequence Core and IO power should be on at the same time or IO power should be on after Core on Power ON Sequence 3 3 V VDDIO VDDCORE VDDPLL OV lt Power OFF sequence Core and IO power should be off at the same time or Core power should be off after IO off Power OFF Sequence 3 3 1 8 V VDDCORE VDDPLL 19 22 PEDL67Q5260 02 OKI SEMICONDUCTOR ML6705260 PACKAGE DIMENSIONS a 408 o0s s a os PRELIMINARY ae HA E 00000000la 0000 0000l7 5 90000000l 5 T CO O00000 y STO 00010000 4 E 000 0000l3 O0000 0000l O0IOO0O0Ol1 FOE DC BA 0 02 254005 0 25 0 05 20 05 S aB S 0 20 S So o a a s o x4 H G INDEX MARK 210 05 ul o oa 0 40 y a ur a r aa ar a r eee Se a a a er ae me fa 0 08 S i i x AFE F SMI PRAOUETRET 5 NOTES x THE TERMINAL PITCH MEANS THE DISTANCES BETWEEN THE TERMINAL CENTERS Unit mm Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales person for the product name package name pin number package code a2. P Built in ROM Porto 2 PU I B6 RTCK O JTAG Return Clock 4mA JO L B7 TCK JTAG Test Clock PU I C5 TMS P JTAG Test Mode State RU l f C6 TDI _ JTAG Test Data In os 11 PU 1 C7 TDO O JTAG Test Data Out 4mA O H C8 NTRST IN JTAG Test Reset PU 1 B5 PA12 I O General Purpose Port A12 SIO Receive Data 4mA 1 B4 PA11 I O General Purpose Port A11 O SIO Transmit Data 4mA 1 G6 PA10 I O General Purpose Port A10 1 O SSIO Communication Clock 4mA 1 H6 PAO9 I O General Purpose Port A9 SSIO Receive Data 4mA 1 H7 PA08 I O General Purpose Port A8 O SSIO Transmit Data 4mA 1 C4 PAO7 I O General Purpose Port A7 VO SPI Clock for CH1 4mA 1 El PAO6 I O General Purpose Port A6 N SPI Slave Select for CH1 4mA 1 SPI Data for CH1 D2 PAO5 I O General Purpose Port A5 V0 Master Receive Slave Transmit 4mA 1 SPI Data for CH1 B3 PA04 I O General Purpose Port A4 O Master Transmit Slave Receive 4mA 1 C2 PAO3 I O General Purpose Port A3 I O SPI Clock for CHO 4mA 1 A3 PA02 I O General Purpose Port A2 L 4 N SPI Slave Select for CHO 4mA 1 SPI Data for CHO A2 PAO1 I O General
3. 10 000 cycle 1 Please supply from same power source to both Vpp coreg pins and Vpp pit pin 8 22 PEDL67Q5260 02 OKI SEMICONDUCTOR ML67Q5260 ELECTRICAL CHARACTERISTICS DC Characteristics DC characteristics Core IO Vop_core 1 62 to 1 98 V Vooo 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Condition Min Typ Max Unit H input voltage Vin 2 0 Von o 0 3 L input voltage Vi 0 3 0 8 Schmitt trigger Vr 20 input threshold voltage Schmitt trigger Vr 20 x input threshold voltage 5 V tolerant Vr 0 6 H output voltage Vou loo 4 mA 2 4 L output voltage VoL lo 4 mA 0 4 e Vin Vpop io 10 High level input current 1 7 pul don 10 62 val vy IH VDD IO pa 1 High level input current 2 V2 5 5 V Y 30 uA y Vi 0V 10 Low level input current 1 ik puiki 140 78 20 Low level input current 2 Vi 0 V 10 i Vou Vpp_10 10 OZH 3 state output leakage current pull aowg 10 Be ia uA loz Vor 0V 10 pull up 140 78 20 Ipps1_CORE 80 1500 Supply current during STOP 4 lbpsi_1o 3 4 20 uA Ipps1_ PLL a 2 10 Supply current during operation lbpo_cors cll ue 5 Ippo_10 fBuscLk 32 0 MHz NO load 5 10 mA lobo PLL 1 3 1 Pi
4. Purpose Port A1 I O Master Receive Slave Transmit 4mA 1 SPI Data for CHO C3 PAOO I O General Purpose Port AO I O Master Transmit Slave Receive 4mA H4 PB11 I O General Purpose Port B11 O Clock Output for sensor 4mA 1 G2 PB10 I O General Purpose Port B10 a id a a aE S 4mA T I F3 PBO9 1 O General Purpose Port B09 External Interrupt Input for IRQ 28 S 4mA 1 E4 PBO8 l O General Purpose Port B08 External Interrupt Input for IRQ 30 S 4mA 1 G1 PBO7 I O General Purpose Port B07 External Interrupt Input for FIQ S 4mA 1 D8 PBO6 O General Purpose Port B06 O Smartcard IF Clock 4mA 1 D5 PBO5 O General Purpose Port B05 O N Smartcard IF Reset 4mA 1 E8 PB04 I O General Purpose Port B04 I O Smartcard IF Serial Data 4mA 1 F8 PBO3 I O General Purpose Port B03 O Smartcard IF Power Control 4mA 1 E5 PB02 I O General Purpose Port B02 O Smartcard IF Voltage Control 1 4mA 1 G8 PBO1 I O General Purpose Port B01 O Smartcard IF Voltage Control 0 4mA 1 G7 PBOO I O General Purpose Port BOO O Smartcard IF Card Detection 4mA 1 G3 DM A USB dev D I F4 DP A USB dev D 1 G5 PUCTL O P
5. channel Channel priority fixed mode round robin mode DMA transfer mode cycle steal mode burst mode DMA request type software requests hardware requests Maximum transfer count 65 536 Data transfer size 8 bits 16 bits 32 bits Transfer request source CPU SPI Synchronous SIO Smartcard IF e GPIO 13 bits x 1 channel 12 bits x 1 channel Enable to setting input mode or output mode for each bit Enable to setting as interruption source for each bit Interruption mode level edge and positive logic negative logic e Timer 16 bit auto reload timer x 4 channel e Watch dog timer WDT 16 bit timer 8 389 seconds max when CPU operating frequency is 32 MHz Enables generation of interrupt or reset by setting e SIO UART Full duplex asynchronous mode Built in baud rate generator e SPI 2 channels of full duplex serial peripheral interfaces Operating mode master mode slave mode Data transfer size 8 bits byte 16 bits word Built in 16 byte 16 word FIFO on the transmission side and the reception side Supports DMA transfer master slave mode e Synchronous SIO SSIO Clock synchronous serial port x 1 channel Data transfer size 8 bits byte Selectable clock polarity Selectable LSB first or MSB first Operation mode master mode slave mode Supports DMAC transfer in master mode only e Smart Card interface Smartcard IF ISO UART x 1 channel Built in 16 byte FIFO Built
6. in parity error counter in receive mode and transmit mode at automatic retransmission Supports asynchronous protocol of T 0 and T 1 according to ISO7816 and EMV Built in error detection code generation and error detection functions by hardware Supports DMA transfer e USB2 0 full speed device Compliant with Universal Serial Bus USB 2 0 Full speed 12 Mbps x 1 port End points 5 or 6 Supports all data transfer types control transfer bulk transfer interrupt transfer isochronous transfer Built in SOP generation and CRC5 16 generation functions Access size to data transfer FIFOs 8 bits 16 bits 32 bits PEDL67Q5260 02 ML67Q5260 2 22 PEDL67Q5260 02 OKI SEMICONDUCTOR ML67Q5260 e Random number generator RANDOM Generates 8 bit random numbers e Clock Input clock 12 MHz oscillator connected System clock CPU operating clock 32 MHz System clock is generated by PLL using 12MHz clock Output clock 6 12 MHz for fingerprint sensor e Power management Power saving mode Individual module clock stop mode Clock operation stop can be set for each functional block HALT mode Only CPU clock is stopped STOP mode All clocks are stopped and start stop of internal PLL and oscillator circuit are selectable e Package 63 pin WCSP Package S UFLGA63 4 03x4 01 0 50 W 3 22 PEDL67Q5260 02 OKI SEMICONDUCTOR ML67Q5260 BLOCK DIAGRAM Built in Flash ROM Working RAM Built
7. memory is required when a slide sensor is used High speed authentication besides low power consumption The highly optimized fingerprint authentication accelerator achieves high speed authentication using a low speed clock Authentication lt 0 8 seconds 1 1 authentication lt 1 8 seconds 1 45 authentication Enrollment lt 2 seconds finger Applicable fingerprint sensor Slide sensor AuthenTec AES1711 128 x 8 pixels AuthenTec AES1751 128 x 8 pixels e CPU 32 bit RISC CPU ARM7TDML S Little endian format Instruction system A high density 32 bit instruction and a 16 bit instruction of high object efficiency which is the subset of the 32 bit instruction can be executed in mixed mode General purpose register 32 bits x 31 registers Built in barrel shifter ALU and barrel shift operation can be executed by one instruction Built in debugging function JTAG interface The JTAG interface pin is shared with GPIO e Built in Memories 16 Kbyte working RAM for CPU 128 Kbyte Flash ROM for application program and fingerprint template data whose erase rewrite times are maximum 10 000 8 Kbyte Mask ROM for update of program in the Built in Flash ROM e Interrupt control 1 FIQ resource External 1 20 IRQ resources External 3 Internal 17 7 priority levels for each source OKI SEMICONDUCTOR e DMA controller DMAC 2 channels Enable to allocate multiple DMA transfer request sources for each
8. to 85 C Parameter Symbol Condition Min Typ Max Unit Serial clock cycle T 62 5 Output data delay time tsssop CL 30 pF 40 Se Input data setting time tsssis 20 Input data retained time tsss H 20 SSIOCLK tsssop gt SSIOTX tsssis tsssiH SSIORX Serial clock Positive polarity 16 22 PEDL67Q5260 02 OKI SEMICONDUCTOR ML67Q5260 GPIO PA PB Access Timing Von core 1 62 to 1 98 V Von lo 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Condition Min Typ Max Unit PAn PBm input H duration TGPIOIH teuscLk x2 ns PAn PBm input L duration Tapio tBusc k x2 ns Note 1 n 12 to 0 m 11 to 0O O PAn PBm input timing n 12 to 0 m 11 to 0 TepioiH Tarro PAn PBm 17 22 PEDL67Q5260 02 OKI SEMICONDUCTOR ML67Q5260 Clock Output Secondary Function of PB11 Pin Timing Vpp_CoRE 1 62 to 1 98 V Von lo 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Condition Min Typ Max Unit 45 50 55 Clock output High duration teLkouT H a ve E ns teLkour teLkour teLkour 45 o 0 M Clock output Low duration teLkouT L SA caine PA ns teLkourT teLkour teLkour tc_kout 1s the cycle time of the 6 MHz or 12 MHz clock generated by 2 clock sources and the frequency divide ratio Clock output secondary function of PB11 pin timing AY tcLkOUT_H teLKOUT_L i
9. MICONDUCTOR ML67Q5260 Characteristics of slave mode timing Vpp_coRE 1 62 to 1 98 V Vo lo 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Condition Min Typ Max Unit Serial clock cycle time tsck T B D teuscLk Serial clock High Low time twsck T B D teuscLk Data delay time output top 25 ns Data setup time input tsp 25 ns Data hold time input tuo CL 30 pF 25 ns SSN SCK lead time tleap 25 ns SCK SSN lag time tLaG tBuscLk 15 ns Slave data invalid time tois uE 25 ns SPI bus I O rise fall time tr t T B D ns SPI slave mode timing CPHA 0 SPINSSN fo Input I SPInSCK j I CPOL 0 Input AS twsck twsck SPInSCK CPOL 1 Input a l tois gt K top SPInMISO LSB MSB Output ts tho SPInMOSI l Input LSB 1 1 MSB n 0 1 SPI slave mode timing CPHA 1 SPInSSN Input mw tlean x tsck a fy foe NY T gt O SPInSCK CPOL 0 Input i twsck twsck SPINSCK 1 gt CPOL 1 Input l zi 7 too SPINMISO Output LSB MSB Eto tao SPINMOSI Input LSB MSB n 0 1 15 22 PEDL67Q5260 02 OKI SEMICONDUCTOR ML67Q5260 Synchronous SIO Access Timing Switching betwee
10. OKI PEDLSTOSDSL OKI SEMICONDUCTOR Issue Date Jul 2010 ML67Q5260 Preliminary DFT Based Fingerprint Authentication LSI GENERAL DESCRIPTION The ML67Q5260 is a single chip LSI that executes fingerprint authentication without external memory by using the embedded fingerprint authentication accelerator This fingerprint authentication accelerator uses DFT Discrete Fourier Transform based algorithm licensed from Precise Biometrics and supports AuthenTec s slide sensors and certain touch sensors from several sensor manufacturers Besides the ML67Q5260 has the secure circuit to protect enrolled fingerprint data from unauthorized access Thus this LSI helps customers quickly design new products that offer convenient security as far as high performance fingerprint authentication low cost small size and high level of security FEATURES e Fingerprint authentication DFT Discrete Fourier Transform based algorithm licensed from Precise Biometrics This DFT based algorithm achieves a lower FTE False To Enrollment rate and a higher authentication accuracy especially when a slide sensor is used as compared to the minutiae algorithm Easy to use The fingerprint authentication is performed by the fingerprint authentication accelerator which does not ask customers for so complicated control No external memory Customer s application program and up to 45 fingerprint data can be stored in the embedded Flash memory on the ML67Q5260 No external
11. R ML67Q5260 SPI Access Timing Characteristics of master mode timing Vpp_CoRE 1 62 to 1 98 V Von lo 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Condition Min Typ Max Unit Data delay time output top 25 ns Data setup time input tsp 25 ns Data hold time input to CL 30 pF 0 1 ns SSN SCK lead time tleap 0 5 tsck 15 0 5 tsok 15 ns SCK SSN lag time tLac 0 5 tscx 15 0 5 tscx 15 ns 1 Although actual values may become negative depending on the external load input the serial data so that the data hold time can be guaranteed 2 tSCK is the cycle time of the serial clock for SPI transferring which is obtained by dividing the frequency of the bus clock whose cycle time is tBUSCLK SPI master mode timing CPHA 0 SPInSSN Output tlean A tsck Lo l SPInSCK PA ft E CPOL 0 Output j SPInSCK NN CPOL 1 Output i y to to Ly I SPInMISO H Input A LSB p MSB too E too SPINMOSI l Output A 18B 4 fo MSB n 0 1 SPI master mode timing CPHA 1 SPInSSN Output 1 f SPInSCK CPOL 0 Output j SPInSCK I CPOL 1 Output CT A po pete SPInMISO ha Input ts MSB I fl SPInMOSI A Output LSB l MSB n 0 1 i 14 22 PEDL67Q5260 02 OKI SE
12. USB dev Pull up Control 4mAl JOJL H8 TESTF A FLASH Test Pin A A8 BSEL1 P Boot Device Select 1 PD 1 H5 AFSEL P JTAG Select ARM FLASH PD I D1 TESTE P Test Mode Select PD l j PEDL67Q5260 02 OKI SEMICONDUCTOR ML67Q5260 Description gt F o Primary function Secondary function 3 2 E Z Elo lt SS S gt gt Sia 6 aon a Al gt o lag a Q S Description Q S Description al 2 Z 5 38 a a B8 E7 H3 VDDCORE 1 8V Power Supply for CORE Ls E el la A4 B1 E6 D6 A5 GNDCORE Ground for CORE E s P E EE G4 A1 A7 F7 B2 VDDIO 3 3V Power Supply for lO 0 E e E2 A6 F6 GNDIO Ground for IO e gi fie a C1 F2 VDDPLL 1 8V Power Supply for PLL ais Sp 5 00 eal i Fi GNDPLL Ground for PLL gt A on ee H2 VDDUSB 3 3V Power Supply for USB a a faf H1 GNDUSB Ground for PLL a E reia 1 PU PD column PU Pulled up with a built in resistor PD Pulled down with a built in resistor 2 This pin is used in the Built in ROM for an update function of the Built in FlashROM For details see the User s manual for USB firmware update function T
13. ermination of Pins Not Used Pin name Pin termination DM DP PUCTL Open PAOO 12 PBOO 11 Pulled down TDO RTCK Open TCK TMS TDI NTRST Pulled up TESTF Must be used as open 7 22 OKI SEMICONDUCTOR PEDL67Q5260 02 ML67Q5260 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Digital power supply voltage CORE 1 8 V Von core 03t0 25 PLL power supply voltage 1 8 V VoD PLL Digital power supply voltage I O 3 3 V Vop_10 E 0 3 to 44 6 USB power supply voltage I O 3 3 V Vpp_usB i Input voltage normal buffer 0 3 to Vpp_10 0 3 Y Vi Voo lo 3 0 V to 3 6 V 0 3 to 6 0 I V tol nput voltage 5 V tolerant Von 10 lt 3 0 V 70 3 to Von 10 0 3 Output voltage Vo 0 3 to Vop_10 0 3 Input allowable current l 10 to 10 H output allowable current loH 10 mA L output allowable current loL 10 Power dissipation Pp Ta 85 C 600 mW Storage temperature TsTG 50 to 150 C GUARANTEED OPERATING RANGES GND 0 V Parameter Symbol Condition Min Typ Max Unit Digital power supply voltage CORE 1 Vop_core 1 62 1 8 1 98 PLL power supply voltage 1 Vpop PLL 1 62 1 8 1 98 y Digital power supply voltage I O Voo_lo 3 0 3 3 3 6 USB power supply voltage Vop usa 3 0 3 3 3 6 Ambient temperature Ta 40 25 85 C Flash write count Cwr
14. in ROM CPU 128 KB 16KB 8KB AHB I O Interrupt Fingerprint DMA controller controller Accelerator 2ch APB I O PLL Clock Reset Power Memory LSI controller Built in FlashROM Saving control Management controller GPIO Smart USB Timer sae 29 SIO spi SSIO cardiF FS RAN 4ch 25 bits 2ch Ich ich Device DOM Figure 1 Block Diagram 4 22 PEDL67Q5260 02 OKI SEMICONDUCTOR ML67Q5260 PIN LAYOUT TESTE vena MUCHO EDT a a een reper Suc VDDIO VDDCORE PRO TDO TCK VDDIO en Ren GNDIO GNDCORE GNDCORE TDI RTCK GNDIO AFSEL PUCTL Se i een TMS ene GNDCORE cit oncore or ft oa htt att ocon A nese 20 iM lien fa venus e VOUEI i eee E MO Eho vee anol Ea GNDUSB ha GNDPLL ie TESTE GNDIO VDDCORE GNDCORE H G F E D C B A S UFLGA61 4 03x4 01 0 50 W Bottom View 5 22 PEDL67Q5260 02 OKI SEMICONDUCTOR ML67Q5260 PIN LIST Description gt o Primary function Secondary function 6 E 2 9 9 E le g SgS Z E Q o QS z gt gt Ss El Ella o a Q E Description Q 3 Description E a 2 2 E Ed 2 6 E D4 xI Oscillation Pin l j D3 XO Oscillation Pin O E3 RESETN N System Reset S PU l D7 PRO
15. it Reset pulse width trstw 6 0 ms RESETN When power on release the reset after the clock oscillation stabilization 11 22 OKI SEMICONDUCTOR PEDL67Q5260 02 ML67Q5260 Main Clock Timing Vpp_coRE 1 62 to 1 98 V Von lo 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Condition Min Typ Max Unit Main clock XI XO frequency fsysc 12 x 0 9975 12 12 x 1 0025 MHz f 83 33 x 83 33 x Main clock XI XO cycle tsysc 0 9975 83 33 1 0025 ns 0 55 x Main clock XI XO H pulse width tsyscH 0 45 x tsysc t ns SYSC 0 55 x Main clock XI XO L pulse width tsyscL 0 45 x tsysc t ns SYSC Bus clock frequency 1 feuscLk 32 MHz Bus clock cycle 1 teuscLk 31 25 ns 1 Main system bus clock within the LSI and operating clocks of CPU DMA etc XI XO A tsysc teuscLk BUSCLK 12 22 OKI SEMICONDUCTOR USB Access Timing Full Speed PEDL67Q5260 02 ML67Q5260 Vpp_CoRE 1 62 to 1 98 V Vo lo 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Condition Min Typ Max Unit Applied pin Rise time Tr CL 50 pF 4 20 ns Fall time Tr CL 50 pF 4 20 ns Output signal crossover Vers CL 50 pF 0 8 25 V DP DM voltage Average bit rate i M Data rate TDRATE 12Mbps 0 25 11 97 12 03 bps 13 22 PEDL67Q5260 02 OKI SEMICONDUCTO
16. n master mode and slave mode can be set for this synchronous SIO by the software register setting Serial clock polarity can be switched When clock polarity is set to positive data is transmitted shifted out on the falling edge of the clock and is received shifted in on the rising edge of the clock At completion of 8 bit data transmission reception the clock stops at a high level and the last data is retained for data output When clock polarity is set to negative data is transmitted shifted out on the rising edge of the clock and is received shifted in on the falling edge of the clock At completion of 8 bit data transmission reception the clock stops at a low level and the last data is retained for data output The following waveforms show the cases where the clock polarity is positive Master mode Vop_core 1 62 to 1 98 V Voo io 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Condition Min Typ Max Unit Output data delay time tussop 20 Input data setting time tussis CL 30 pF 30 ns Input data retained time tussiH 10 Note 11 clock outputs for transferring is selectable from 2 synchronous SIO clock sources and the frequency divide ratios SSIOCLK tmssop lt _ SSIOTX SSIORX Serial clock Positive polarity Slave mode Voo_core 1 62 to 1 98 V Vooo 3 0 to 3 6 V Ta 40
17. nd desired mounting conditions reflow method temperature and times 20 22 PEDL67Q5260 02 OKI SEMICONDUCTOR ML67Q5260 REVISION HISTORY Page Document No Date Previous Current Description Edition Edition PEDL67Q5260 01 Aug 18 2009 Preliminary edition 1 PEDL67Q5260 02 Jul 15 2010 Preliminary edition 2 21 22 PEDL67Q5260 02 OKI SEMICONDUCTOR ML67Q5260 NOTICE 1 The information contained herein can change without notice owing to product and or technical improvements Before using the product please make sure that the information being referred to is up to date 2 The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product When planning to use the product please ensure that the external conditions are reflected in the actual circuit assembly and program designs 3 When designing your product please use our product below the specified maximum ratings and within the specified operating ranges including but not limited to operating voltage power dissipation and operating temperature 4 OKI Semiconductor assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse neglect improper installation repair alteration or accident improper handling or unusual physical or electrical stress including but not limited
18. necessary steps at their own expense for these 8 No part of the contents contained herein may be reprinted or reproduced without our prior permission Copyright 2009 2010 Oki Semiconductor Co Ltd 22 22
19. ns other than 5 V tolerant pins 2 5 V tolerant pins 3 Input ports VDD_IO or 0 V Other ports No load excluding the current flowing in pull up pull down resistors 4 LSI supply current when going into LSI stop mode by stopping clock oscillation PLL operation and random number generator operation and setting USB power down mode 5 The current supplied to the LSI when fingerprint authentication is executed without USB operation under the conditions that the programs are stored in the built in Flash ROM and no external memory are connected 9 22 OKI SEMICONDUCTOR DC characteristics USB PEDL67Q5260 02 ML67Q5260 Vpp_coRE 1 62 to 1 98V Vpp_10 3 0 to 3 6V Ta 40 to 85 C Parameter Symbol Condition Min Typ Max Unit Absolute value of the Differential input sensitivity Vor difference between the DP 0 2 V and DM pins Differential common mode range Vom Includes VDI range 0 8 2 5 V Single end input threshold voltage Vse 0 8 2 0 V High level output voltage VoH iki P 2 8 V Low level output voltage VoL 1 5K W RL to 3 6 V 0 3 V Hi Z state input output leakage Lo O V lt VIN lt 3 3 V 40 10 UA current Driver output resistance Zorv Steady state 28 44 Q 10 22 PEDL67Q5260 02 OKI SEMICONDUCTOR ML67Q5260 AC Characteristics Reset Timing Voo core 1 62 to 1 98 V Vooo 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Condition Min Typ Max Un
20. to exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range 5 Neither indemnity against nor license of a third party s industrial and intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof 6 The products listed in this document are intended for use in general electronics equipment for commercial applications e g office automation communication equipment measurement equipment consumer electronics etc These products are not unless specifically authorized by OKI Semiconductor authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans Such applications include but are not limited to traffic and automotive equipment safety devices aerospace equipment nuclear power control medical equipment and life support systems 7 Certain products in this document may need government approval before they can be exported to particular countries The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and
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