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ATCA-7370/ATCA-7370-S Installation and Use

1. ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 239 FRU Information and Sensor Data Records Table 9 3 Sensor Data Records continued Event Sensor Event Reading Data Event Threshold Assertion Number Sensor Name Sensor Type Type Byte 1 Event Data Byte 2 Event Data Byte3 Description Deassertion Rearm 39 Reset Source OEM OxDA Sensor Ox0 7 OS reset payload 7 2 Reserved 0x0 Payload Reset Asrt Auto specific 0x1 req 1 PMC Pre detected Cause discrete ox2 6 BIOS reset Timout a in Event Ox6F ox3 Payload req 0 IPMC yte 2 0x4 5 FPGA Watchdog Watchdog Reset Timeout 0x5 4 Push Button 0x6 Reset RTM 0x7 3 IPMC reset 0x8 payload req 0x9 2 Pus Button Reset OxA front oxg 1 5 reserved oxc 0 7 Payload Power on reset 0xD OxE 40 CPU Status Processor Sensor Ox1 OxFF OxFF 0x1 Thermal Trip Asrt Auto 0x07 specific OxA OxA ProcHot discrete Ox6F 41 ACPI State System Sensor 0x0 UNF OxFF 0x0 SO Asrt Auto ACPI Power specific 0x3 0x3 53 State discrete 0x5 0x5 5 0x22 Ox6F 240 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Chapter 10 Firmware Upgrade EN 10 1 10 1 1 10 1 2 10 1 2 1 10 1 3 HPM 1 Firmware Upgrade Overview The primary update mechanism for the ATCA 7370 blades is the FCU tool which is delivered with the BBS package for the b
2. 8 3 2 2 Get Serial Output Command The Get Serial Output Command provides a way to determine which serial output source goes to a particular serial port connector AA N d Currently only BIOS output is supported ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 201 Supported IPMI Commands Thefollowing table lists the request and response data applicable to the Get Serial Output command Table 8 26 Get Serial Output Command Byte Data Field Request Data 1 3 Artesyn IANA Number 0065CDh LSB first 4 Serial connector type 0 Front panel connector 1 Backplane connector All other values are reserved 5 Serial connector instance number A value of 00h shall be used all other values are reserved Response Data 1 Completion code 2 4 Artesyn IANA Number 0065CDh LSB first 5 Serial output selector 0 payload interface All other values are reserved 8 3 3 OEM Set Get ACPI Power Commands This command can be used to change payload s power state Table 8 27 OME Set Get ACPI Power Commands NetFn Command name Request Response CMD Description OEM Set ACPI Power State Ox2E Ox2F 0x17 OEM Get ACPI Power State Ox2E Ox2F 0x18 202 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands 8 3 3 1 OEM Set ACPI Power State 0x17 Table 8 28 OEM Set ACPI Power State Command Data Request Data LSB of Artesyn IANA Enterpri
3. IPMC Power Level Register Payload Power Control Register 12C Switch Control Register SIS pr 0x0A OE OxOF 0x10 0x11 ENS Payload Power button Register Reserved Reset Mask Register Reset Function Register IPMC Reset Payload Request Register BIOS Reset Payload Request Register OS Reset Payload Request Register Payload Reset Source for IPMC Register Payload Reset Source for BIOS Register Payload Reset Source for OS Register IPMC Watchdog Timeout Register For LPC HO access add the LPC UO Base Address 0x600 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 149 Maps and Registers Table 6 42 FPGA Register Map Overview continued LPC IPMC Address Offset I O SPI Description oas In TI IPMC Watchdog Timeout for BIOS Register pox w li IPMC Watchdog Timeout for OS Register 0x1A rw FPGA Payload Watchdog Threshold Low byte Register 0x1B rw FPGA Payload Watchdog Threshold High byte Register oac In li FPGA Payload Watchdog Clear Register OxID 1E E Reserved Ox1F FPGA IPMC Watchdog Threshold Register 0x20 2D Reserved Ox2E HFI Mode Enable Register Ox2F 32 HFI Mode POL Control Registers L EE 0x33 36 HFI Mode Reset Control Registers 0x37 3F Reserved rw Flash Control Register Reserved IPMC Scratch Register 0 rw RTM Status and Control Register Han Reserved Blue LED Status and Control Register Ox4B 5
4. ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 163 Maps and Registers 6 3 12 11 IPMC Watchdog Timeout for OS Register M 164 When the corresponding bits in DC Watchdog Timeout Register changes from 0 to 1 this register will have its bits set to 1 The OS software can clear certain bits by writing 1 to it This register is only used for communication between the IPMC and the OS software FPGA will not use these bits by itself BIOS should never write to this register Table 6 62 IPMC Watchdog Timeout for OS Register Address Offset 0x19 IPMC Watchdog Timeout LPC r w1c 1 IPMC Watchdog Timeout occurred IPMC Watchdog Pre Timeout LPC r w1c 1 IPMC Watchdog Pre Timeout occurred 72 Reserved 000000 6 3 12 12 FPGA Payload Watchdog Threshold Register Payload software writes to this register to set the timeout threshold of a 16 bit internal watchdog reserved for future payload use Unit is one msec with a maximum time of 65535 ms When 0 is written into it the watchdog will be disabled and never bite Address Offset Watchdog will be cleared each time when writing new threshold registers Watchdog will be cleared during power up reset and cold reset Table 6 63 FPGA Payload Watchdog Threshold Low byte Register Address Offset Ox1A Description Default Access 7 0 Low byte of timeout threshold for FPGA OxFF LPC r w Payload Watchdog unit is one msec ATCA 7370 ATCA 7370 S Installatio
5. ATCA 7370 ATCA BLADE DUAL INTEL XEON E5 2600 SERIES 8 CORE PROCESSOR OGB 10G SUPPORT NSN VARIANT ATCA 7370 0GB S Single Board Variant As ofthe printing date of this manual the following board accessories are available Table 1 4 Blade Accessories Ordering Information Accessory Description RTM ATCA 737x RTM for the ATCA 737x product series 2X GBE SFP 2X slot for optional HDD NSN variant ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 43 Introduction Table 1 4 Blade Accessories Ordering Information continued Accessory Description ATCA 7370 ACCEL MOD Single coprocessor module to accelerate cryptography data compression and pattern matching 1 7 Product Identification The Figure 1 2 on page 42 shows the location of the serial number label 44 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Chapter 2 Hardware Preparation and Installation EMI 2 1 2 2 Unpacking and Inspecting the Blade This section describes the procedure for packing and inspecting the blade Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten its life Before touching the blade or electronic components make sure that you are working in an ESD safe environment Shipment Inspection To inspect the shipment perform the following steps 1 Verify that you have received all items of your shipment e Printed Quic
6. Table 6 44 Version Register Address Offset 0x01 Bit Description Default Access Serial Redirection Console Register The BIOS sets the corresponding bit which is used for serial direction The IPMC uses this information to route the corresponding port serial IPMC interface in case of serial over lan SOL BIOS should never set both status bits Table 6 45 Serial Redirection Control Register Address Offset 0x03 Bit Description Default Access COMI used for serial redirection 0 COMI not used for serial redirection 1 COM1 used for serial redirection 1 COM2 use for serial redirection 0 LPC r w 0 COM2 not used for serial redirection IPMC r 1 COM2 used for serial redirection 7 2 Reserved 0 r ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers 6 3 6 Serial Over LAN SOL Control Register The IPMC software can route the serial data from serial port 1 COM71 or serial port 2 COM2 to the IPMC When both control bits are enabled bit 1 is ignored V 4 Table 6 46 SOL Control Register Address Offset 0x04 Bit Description Default Access SOL over COM1 enable 0 disabled 1 enabled COM1 is forwarded to IMPC SOL over COM2 enable 0 disabled 1 enabled COM2 is forwarded to IMPC LN Oi 6 3 7 Serial Routing Register Table 6 47 Serial Routing Register Address Offset 0x05 Bit Description Default Access 00 COMI to Faceplate
7. 136 Table 6 35 Line Control Register CR 137 12 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G List of Tables Table 6 36 Modem Control Register MCR cece cece eee ee eee eee e teen eee eeneeeas 139 Table 6 37 Line Status Register LSR u cena kn ey NNN NN e nee esr sk 141 Table 6 38 Modem Status Register Ma 145 Table 6 39 Scratch Register SCR each u pr 147 Table 6 40 Divisor Latch LSB Register DLL DA 148 Table 6 41 Divisor Latch MSB Register DLM if DLAB 1 0c cece cece ene 148 Table 6 42 FPGA Register Map Overview 0 cece cece HH 149 Table 6 43 Module Identification Register 151 Table 6 44 Version Register u mn ae eh 152 Table 6 45 Serial Redirection Control Register 152 Table 6 46 SOL Control Register dE n hpi EK CREE Xa Y RETE aU ERA ER eben 153 Table 6 47 SeriallRouting Register sissies ows ee et 153 Table 6 48 IPMC Power Level Register 154 Table 6 49 Payload Power Control Register 155 Table 6 50 I2C Switch Control Register 155 Table 6 51 Payload Power Button Register 156 Table 6 52 Reset Mask Register reram ore eben e RR elk rie aee RR RR die eie eg 156 Table 6 53 Reset Function Register e xr RR ber OY X ea 157 Table 6 54 IPMC Reset Payload Request Register 158 Table 6 55 BIOS Reset Payload Request Register 159 Table 6 56 OS Reset Payload Request Register ccc cece cece e eee eee eee n ences 159 Table 6 57 Payload Re
8. F000 0000 FFFF FFFF Flash range RCRB register APIC register etc E000 0000 EFFE FFFF 256MB PCle extend memory space 0000 0000 CFFF_FFFF 3 25GB available physical memory space e Thememorytestis in the Intel Memory Reference Code MRC and uses hardware controller intrinsic functions The MRC is described in the in chapter 7 13 of Intel Xeon Processor E5 1600 2400 2600 4600 Product Families System Agent BIOS Specification 1 01 document document number 489625 Artesyn recommends inserting memory modules of the same type into all slots of the ATCA 7370 With mixed memory like different model voltage or frequency the system may run in a degraded performance Though not recommended a certain combination is possible with the following restrictions Amix of different sizes Amixof1 5V and 1 35V modules all will be configured with 1 5V Amixof 1600MHz and 1333MHz all will run with 1333MHz 78 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G BIOS 4 1 3 4 1 4 4 1 5 4 1 5 1 4 1 5 2 Interrupt Routing The BIOS provides the interrupt routing to the operating system through the following interfaces e PCIIRQ Routing Table non ACPI environment e Multi Processor Table non ACPI environment ACPI PRT packages ACPI environment e ACPI Multiple APIC Description Table ACPI environment PCI Initialization The BIOS supports PCI BIOS Specification Revision 2 1 During power up self test
9. Get Feature Configuration Ox2E Ox2F Ox1F ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands 8 3 1 1 Set Feature Configuration Command This command can be used to set the IPMI feature Table 8 21 Set Feature Configuration Command Request Data Artesyn IANA Number 0065CDh LSB first Feature Selector For details please see Table Feature Selector Assignments on page 200 Feature Configuration 00h disabled Feature Selector E2h 01h enabled Feature Selector E2h Default 02h FFh reserved Persistency Duration 00h volatile Actual duration depends on implementation 01h FFh reserved Response Data Completion Code Generic plus the following command specific completion codes 80h feature selector not supported 81h feature configuration not supported 82h configuration persistency duration not supported Artesyn IANA Number 0065CDh LSB first 8 3 1 2 Get Feature Configuration Command This command can be used to retrieve the IPMI feature set being configured Table 8 22 Get Feature Configuration Command Byte Data Field Request Data Artesyn IANA Number 0065CDh LSB first Feature Selector for details see Table 8 23 on page 200 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54C 199 Supported IPMI Commands 8 3 2 200 Table 8 22 Get Feature Configuration Command continued Byte Data Field Res
10. SFP SFP Modules 34 Gefahr von Verletzungen sowie von Besch digung des RTMs und SFP Modulen Die Installation und der Betrieb von SFP Modulen welche nicht zertifiziert sind und welche nicht den Sicherheitsstandards entsprechen kann Verletzungen zur Folge haben sowie zur Besch digung des RTMs und von SFP Modulen f hren Verwenden Sie daher nur SFP Module die zertifiziert sind und die den Sicherheitsstandards entsprechen Verletzungsgefahr Optische SFP Module k nnen als Laserprodukte klassifiziert sein Wenn Sie solche SFP Module installieren und betreiben so gelten die entsprechenden Bestimmungen f r Laserprodukte f r das gesamte RTM Werden diese Bestimmungen nicht eingehalten so k nnen Verletzungen die Folge sein Wenn Sie SFP Module betreiben die als Laserprodukte klassifiziert sind stellen Sie sicher dass die entsprechenden Bestimmungen f r Laserprodukte eingehalten werden Verletzungsgefahr der Augen Optische SFP Module k nnen Laserstrahlen aussenden wenn kein Kabel angeschlossen ist Blicken Sie daher nicht direkt in die ffnung eines SFP Moduls um Verletzungen der Augen zu vermeiden ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Sicherheitshinweise Besch digung von SFP Modulen Die Schutzkappe eines SFP Modules dient dazu die sensible Optik des SFP Modules gegen Staub und Schmutz zu sch tzen Entfernen Sie die Schutzkappe nur dann wenn Sie beabsichtigen ein Kabel anzuschlie en Andernf
11. SPD PECI MAX6618 0x54 SoL DC BUF IPMB B MGMT DC IPMB A BUF Note On the single processor variant the processor and its DIMM sockets are populated on the upper side of the board Components associated with the second processor are not populated on this product variant ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 111 Functional Description 5 15 112 The IPMC can access the thermal information of DIMM SPD At beginning of boot CPU dedicated memory I2C bus owns the DIMM SPD for memory parameter reading IPMC can access the DIMM SPD for DIMM thermal information through mux control signal Glue Logic FPGA The Glue Logic FPGA is a programmable logic device used for Power sequence control LPC interface under PCH for internal register access SPI Interface under IPMC for internal register and BIOS access Reset control logic Interruption control logic BIOS bank selection control Dual UART controller with routing control ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers 6 1 Interrupt Structure The ATCA 7370 supports NON APIC legacy PIC Mode and APIC mode of Interrupt delivery to the CPUs The 8259 PIC mode interrupt concentrator supports 16 interrupts 8 external signal inputs The IO APIC device supports 24 interrupt sources In APIC mode the C604 chipset supports only Front side bus interrupt delivery notthe serial APIC mode T
12. e BIOS Source boot flash device bank USB 2 0 Ports The ATCA 7370 supports three external 2 0 ports All USB ports support low speed full speed and high speed using the USB 2 0 Enhanced Host Controller Interface EHCI Supported Operating Systems Thefollowing operating systems are supported by the ATCA 7370 DOS is used for debugging e WRS PNE LE 4 3 Linux and higher e Red Hat Enterprise Linux 6 x ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 4 1 16 4 1 17 4 1 17 1 BIOS SPI Boot Flash The SPI boot flash contains a descriptor mode image with all required parameters as described in Intel amp Patsburg chipset SPI Flash Programming Guide Revision 1 6 Intel Confidential Serial Console and BIOS Printouts The BIOS initializes the serial port and uses the serial port as output console The default settings for the serial port are 9600 bps 8 data bits no parity 1 stop bits no flow control The BIOS printout does not cause any significant delay to boot up Default terminal emulation is VT 100 The ATCA 7370 vendor Phoenix specifies and documents the terminal hot keys and keystroke mapping for VT 100 ANSI and VT UTF8 The BIOS prints all errors found during BIOS phase In addition to errors BIOS prints the information contained in the Board Information to console BIOS Printouts to DRAM BIOS console printouts are stored in a specific area of the DRAM The printouts are accessible by the OS allowing
13. e Recessed reset button ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 61 Controls Indicators and Connectors eee tee Figure 3 1 Faceplate LEDs 62 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Controls Indicators and Connectors The meaning of these LEDs is described in the following table Table 3 1 Faceplate LEDs Out of Service Red or Out of Service ATCA LED1 Amber Red optional Amber controlled by IPMC This LED is controlled by higher layer software such as middleware or applications Red On after power up and lamp test finished Turned OFF by OS startup script or application In Service Green or In Service ATCA LED2 Red Red green controlled by IPMC If both red and green are lit it may look amber This LED is controlled by higher layer software such as middleware or applications Off after power up and lamp test finished Turned green ON by OS startup script or application Attention Amber Attention ATCA LED3 Amber This LED is controlled by higher layer software such as middleware or applications Off after power up and lamp test finished Base Ethernet Green ON Link up Blinking Shows activity OFF Link down The two LEDs are for the base Ethernet interface and are multiplexed with U1 and U2 using the signal FP BASE LED EN N signal controlling from FPGA U1 U2 U3 Red User LED Red user defined LED by FPGA register 0x57
14. B 2 Artesyn Embedded Technologies Embedded Computing Documentation The publications listed below are referenced in this manual You can obtain electronic copies of Artesyn Embedded Technologies Embedded Computing publications by contacting your local Artesyn sales office For released products you can also visit our Web site for the latest copies of our product documentation 1 Goto www artesyn com computing support product technical documentation php 2 Under FILTER OPTIONS click the Document types drop down list box to select the type of document you are looking for 3 Inthe Search text box type the product name and click GO Table B 1 Artesyn Embedded Technologies Embedded Computing Publications Document Title Publication Number ATCA 7370 ATCA 7370 S Quick Start Guide 6806800P66 ATCA 7370 ATCA 7370 S Safety Notes Summary 6806800P67 Related Specifications For additional information refer to the following table for related specifications As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table B 2 Related Specifications Organization Document Title PCI SIG PCI Local Bus Specification Revision 2 2 PCI X Addendum to the PCI Local Bus Specification 1 0 PICMG PICMG 3 0 Revision 2 0 Advanced TCA Base Specification PICMG 3 1 Revision 1 0 Specification Ethernet Fiber C
15. Operating Voltage 39 VDC to 72 VDC Exception in the US and Canada 39 VDC to 60 VDC Max power consumption of ATCA 7370 260W typ 220W with ATCA 7370 ACC Module and with RTM ATCA 737x including 2 SAS HDDs Max power consumption of ATCA 7370 220W typ 180W without ATCA 7370 ACC Module and without RTM Max power consumption of ATCA 7370 s without 140W typ 120W ATCA 7370 ACCEL MOD and without RTM ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 49 Hardware Preparation and Installation 50 The blade provides two independent power inputs according to the AdvancedTCA Specification Each input has to be equipped with an additional fuse of max 90 A located either in the shelf where the blade is installed or the power entry module PEM The power consumption has been measured using specific boards in a configuration considered to represent the worst case with RTM ATCA 737x and SAS HDD maximum memory population ACC 7370 module and with software simultaneously exercising as many functions and interfaces as possible This includes a particular load software provided by Intel designed to stress the processors to reach their theoretical maximum power specification Any difference in the system configuration or the software executed by the processors may affect the actual power dissipation Depending on the actual operating configuration and conditions customers may see slightly higher power dissipatio
16. Table 1 2 Mechanical Data Feature Value Dimensions width x height x depth Single slot ATCA 30mm x351mm x 312mm 8U form factor Net weight 2930g without DIMMs 2496g with 4x 8GB DIMMs Weight including Artesyn standard 4105 g without DIMMs 4318 g with 8x 8GB DIMMs packaging ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 41 Introduction 1 4 Mechanical Layout Thefollowing graphics illustrate the mechanical layout of the blade Figure 1 2 Mechanical Layout S N Label Note On the single processor variant the processor and its DIMM sockets are populated on the upper side of the board Components associated with the second processor are not populated on this product variant 42 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Introduction 1 5 MeanTime Between Failures The following table specifies the Mean Time Between Failures MTBF data ATCA 7370 blade 5470 fit 182 815 hours RTM 7370 blade 950 fit 1 052 631 hours Standard for calculation SR332 The following table specifies the environmental conditions required for the blade Quality Level Quality Level Il is most common Environment Typically Ground Fixed Controlled Assembly Ambient Temperature 40 C Confidence Level 60 1 6 Ordering Information As ofthe printing date of this manual this guide supports the models listed below Table 1 3 Blade Variants Ordering Information
17. 08h Bit 11 Can instead be routed to generate an SCI through the NMI2SCI EN bit Device 31 Function 0 TCO Base 08h Bit 11 SECSTS Register Device 31 Function FO Offset 1Eh Bit 8 DEV STS Register Device 31 Function FO Offset 06h Bit 8 This is enabled by the Parity Error Response Bit PER at Device 30 Function 0 Offset 04 Bit 6 GPIO 15 0 When configured as a General Purpose input and routed as NMI by GPIO ROUT at Device 31 Function 0 Offset B8 The GPIO 15 0 can generate NMI On the ATCA 7370 the GPIO3 of PCH connects to the FPGA The IPMC can request an NMI interrupt through controlling the GPIO3 of PCH connect to FPGA ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers The chipset has NMI Status and Control Register and the NMI Enable Register Both can be used to configure the relevant settings and get the status report Software can also set NMI2SMI EN bit in TCO1 Control Register to force all NMIs to instead cause SMI The functionality of this bit is dependent upon the settings of the NMI EN bit and the GBL SMI EN bit as detailed in the succeeding table gota No SMi at all because GBL SMI EN 0 SMI will be caused due to NMI events 1b 0b No SMI at all because GBL_SMI_EN 0 1b 1b No SMI due to NMI because NMI_EN 1 IPMC can initiate a NMI request to processor to cause a warm reset when the Payload Watchdog in IPMC is timeout or when IP
18. 244 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Firmware Upgrade FPGA and BIOS upgrade may last from fifteen minutes up to two hours The time varies with the selected programming interface A power cycle is required after the BIOS FPGA update 10 4 Upgrade Package The HPM upgrade package for this release contains the following files Table 10 1 HPM Upgrade Package Filename atca7370 em bios xx yy zzzz hpm Description Contains BIOS HPM 1 image with version xx yy zzzz atca7370 em fpga xx zzzz hpm Contains FPGA HPM 1 image with version xx yy zzzz atca7370 em ibbl xx yy zzzz hpm atca7370 em ipmc xx yy zzzz hpm Contains IPMC boot loader image with version xx yy zzzz Contains IPMC firmware with version xx yy zzzz ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 245 Firmware Upgrade EN s ee 246 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Troubleshooting A 1 Error List This chapter can be taken as an error list for detecting erroneous configurations and strange behaviors It cannot replace a serious and sophisticated pre and post sales support during application development If itis not possible to fix a problem with the help of this chapter contact your local sales representative or Field Application Engineer FAE for further support A 1 1 CPU Blade is Not Functioning Properly The following table lists the errors reasons and solutions for
19. 6 3 12 1 156 Payload Power Button Register Table 6 51 Payload Power Button Register Address Offset 0x09 o FPGA_PCH_PWRBTN_N IPMC r w 7 1 0 r Reserved Reset Registers Reset Mask Register The reset mask register enables or disables forwarding of a reset source to reset output signal Only Push Button Resets requests are affected by the reset mask register The register default values are latched when RST_N is asserted This register can be read or written by the host CPU Aone in the register bit indicates that the associated reset is enabled A zero indicates that the associated reset source is masked Table 6 52 Reset Mask Register Address Offset OxOF Bit Description Default Access RSR Reserved H Enable front board push button reset payload 1 enabled 0 disabled Enable IPMC reset payload 1 enabled 0 disabled ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers Table 6 52 Reset Mask Register continued Address Offset OxOF Bit Description Default Access Enable RTM push button reset payload 1 enabled 0 disabled Enable FPGA Watchdog reset payload 1 enabled 0 disabled Enable BIOS reset payload 1 enabled 0 disabled Enable OS reset payload 1 enabled 0 disabled 6 3 12 2 Reset Function Register The reset function register selects the reset function for a certain reset source among warm reset and co
20. LPC I O Address Ox4E INDEX Configuration Index LPC r w Table 6 12 Super I O Configuration Data Register LPC I O Address Ox4F Description Default Access DATA Configuration Data 6 2 3 1 Entering the Configuration State The device enters the Configuration State by the following contiguous sequence 1 Write 80H to Configuration Index Port 2 Write 86H to Configuration Index Port 6 2 3 2 Exiting the Configuration State The device exits the configuration state by the following contiguous sequence 1 Write 68 to Configuration Index Port 2 Write 08 to Configuration Index Port 124 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers 6 2 3 3 M 6 2 3 4 6 2 3 4 1 Configuration Mode The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports The desired configuration registers are accessed in two steps 1 Write the index of the Logical Device Number Configuration Register i e 07 to the INDEX PORT and then write the number of the desired logical device to the DATA PORT 2 Write the address of the desired configuration register within the logical device to the INDEX PORT and then write or read the configuration register through the DATA PORT e Ifaccessing the Global Configuration Registers step 1 is not required The Super IO returns to the RUN State e Only two states are defined
21. Options Disabled and Enabled Default is Enabled Memory ECC Error Log Select ECC Runtime errors type to be logged in SMBIOS event log Select type include Correctable Error CE Uncorrectable Error UC both CE and UC error Both Options Disabled CE UC and Both Default is Both ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 95 BIOS 4 2 2 6 4 2 2 6 1 96 Table 4 12 Memory Configuration Description continued Field Description Correctable ECC Logging Enter the correctable error threshold value if Runtime Error Logging Threshold option is enabled Range 1 32767 Default is 1 Correctable ECC Flooding Enter the Error Logging Limit value if Runtime Error Logging option is Threshold enabled Range 1 65535 Default is 20 South Bridge Configuration Table 4 13 lists the South Bridge Configuration options Table 4 13 South Bridge Configuration Description Field Description SB USB Config Set USB configuration See SB USB Configuration SB USB Configuration Table 4 14 lists the SB USB Configuration options Table 4 14 SB USB Configuration Description Field Description USB1 Control Enable or disable Front Panel USB port 1 Options Disabled and Enabled Default is Enabled USB2 Control Enable or disable Front Panel USB port 2 Options Disabled and Enabled Default is Enabled RTM USB Control Enable or disable RTM USB port Options
22. PCIE_CPU1_ PCIE_CPU1_ PCIE_CPU1 PCIE_CPUI_T PCIE_CPU1_T RX8 RX8 TX8 TX8 RX9 _RX9 X9 x9 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 67 Controls Indicators and Connectors Table 3 8 Zone 3 Connector J31 Pin Assignment PCIE_CPU1_ PCIE_CPU1_ PCIE CPUT PCIE_CPU1_ PCIE_CPU1_ PCIE_CPU1 PCIE_CPU1_T PCIE_CPU1_T RX10 RX10 TX10 TX10 RX11 _RX11 X11 X11 PCIE_CPU1_ PCIE_CPU1_ PCIE CPUT PCIE_CPU1_ PCIE_CPU1_ PCIE_CPU1 PCIE_CPU1_T PCIE_CPU1_T RX12 RX12 TX12 TX12 RX13 _RX13 X13 X13 PCIE_CPU1_ PCIE_CPU1_ PCIE CPUT PCIE_CPU1_ PCIE_CPU1_ PCIE CPUT PCIE_CPU1_T PCIE_CPU1_T RX14 RX14 TX14 TX14 RX15 _RX15 X15 X15 CLK_100M_A CLK_100M_ CLK_100M_ CLK_100M_ B AB CD CD Table 3 9 Zone 3 Connector J32 Pin Assignment Col AB Col CD Col EF Col GH PCIE9_RP 0 PCIE9 RN PCIE9 TP PCIE9 T PCIES_RP 1 PCIE9 RN 1 PCIE9 TP 1 PCIE9 TN 1 PCIE9 RP 2 PCIE9 RN PCIE9 TP PCIE9 TN 2 PCIE9 Rp PCIE9 RN PCIE9 TP 3 PCIE9 TN 3 PCIE8_RP O BOES RN PCIE8 TP PCIE8_TN O PCIE8 RP PCIE8_RN PCIE8_TP 1 PCIE8_TN 1 PCIE8_RP 2 PCIE8_RN PCIE8_TP PCIE8_TN 2 PCES Rp PCIE8_RN PCIE8_TP 3 PCIE8_TN 3 PCIE7 RP 0 PCIE7_RN PCIE7 TP PCIE7_TN O PCIE7 RP PCIE7 RN PCIE7 TP 1 PCIE7 TN 1 PCIE7 RP 2 PCIE7_RN PCIE7 TP PCIE
23. 122 6 2 1 2 SPI Register Decoding sesessseee nennen nenn 123 6 2 2 POST Code Redister rss nee einen ERAS 123 6 2 3 Super lO Configuration Register 124 6 2 3 1 Entering the Configuration State 124 6 2 3 2 Exiting the Configuration State 124 6 2 3 3 Configuration Mode 125 6 2 3 4 Superl O Configuration Register 125 6 2 4 UARTI and UART2 Register Map 131 6 2 4 1 UART Register Overview eessseeee eee eee nee ees 131 6 2 5 UART Registers DLAB 0 snenie pranane cee eee e nen 132 6 2 5 1 Receiver Buffer Register 132 6 2 5 2 Transmitter Holding Register THR eee ee eee teen ence eee 132 6 2 5 3 Interrupt Enable Register ERT 133 6 2 5 4 Interrupt Identification Register UR 134 6 2 5 5 FIFO Control Register FCR ccc cece cece eee eee een ee 136 6 2 5 6 Line Control Register ch 137 6 2 5 7 Modem Control Register MCR cece eee eee e eee ree 139 6 2 5 8 Line Status Register Lab 140 6 2 5 9 Modem Status Register MSR cece eee cece eet nee 144 6 2 5 10 Scratch Register SCH 147 6 2 6 Programmable Baud Rate Generator 147 6 3 FPGA Register Mapping 2 42 u ke e ee nase 148 6 3 1 EPCT O ReaisterMap nero bie RI Ae Rr t EIE Dag e asd 148 6 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Contents 6 3 2 IPMCSPI Register Map as e 22 00 20 an an 149 6 3 3 Module Identification Register nennen 151 6 3 4 VersionR
24. 124 Table 6 13 Global Configuration Register Summary 125 Table 6 14 Super IO Logical Device Number Register 126 Table 6 15 Super IO Device Revision Register 126 Table 6 16 Super IO LPC Control Register 126 Table 6 17 Global Super IO SERIRQ and Pre divide Control Register 127 Table 6 18 Logical Device Configuration Register Summary 127 Table 6 19 Logical Device Enable Register 128 Table 6 20 Logical Device Base IO Address MSB Register 128 Table 6 21 Logical Device Base IO Address LSB Register eee cece e eee e eee e nent eee 128 Table 6 22 Logical Device Common Decode Range 129 Table 6 23 Logical Device Primary Interrupt Register 129 Table 6 24 Logical Device 0x74 Reserved Register 130 Table 6 25 Logical Device 0x75 Reserved Register 00 cece e cence eee tenet e 130 Table 6 26 Logical Device OxFO Reserved Register 130 Table 6 27 UART Register OvervieW ERENNERT a 131 Table 6 28 Receiver Buffer Register RBR if DLAB O 0 cece cece cence e 132 Table 6 29 Transmitter Holding Register THR if DLAB O sce e eee e eee eee eens 132 Table 6 30 Interrupt Enable Register IER if DLAB O eee eee cece eee eee ene eee 133 Table 6 31 UART Interrupt Priorities u esse NEE EEN 134 Table 6 32 Interrupt Identification Register IR 134 Table 6 33 Interrupt Identification Register Decode cece cece ence eee teen ences 135 Table 6 34 FIFO Control Register ECH
25. 148 A Divisor value of 0 in the Divisor Latch Register is not allowed Table 6 40 Divisor Latch LSB Register DLL if DLAB 1 LPC IO Address Base Divisor Latch LSB DLL Undef LPC r w Table 6 41 Divisor Latch MSB Register DLM if DLAB 1 LPC IO Address Base 1 Bit Description Default Access FPGA Register Mapping LPC IJO Register Map The FPGA registers may be accessed via LPC I O cycles in the UO address range REGISTERS See Table 6 42 FPGA Register Map Overview For an LPC register access use the base address 0x600 and add the Address Offset An LPC I O write access to an address not listed in this table or marked with a in the LPC HO column is ignored A corresponding read access delivers always zero Note LPC I O Address 0x600 Address Offset ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers 6 3 2 IPMCSPI Register Map The FPGA registers may be accessed using the IPMC SPI transactions with the signal BMC SPI S0 Nasserted See Table 6 42 FPGA Register Map Overview A SPI write access to an address not listed in this table or marked with a in the IPMC SPI column is ignored A corresponding read access delivers always zero Table 6 42 FPGA Register Map Overview LPC IPMC 0x00 r r Module Identification Register FPGA Version Register es f e Serial Redirection Control Register Serial over LAN SOL Control Register Serial Routing Register
26. 90 Figure 4 3 Security Men cesset E bb epe Dep ern peer desde lan 98 Figure 4 4 Giele TEE Eds d 99 Figure 4 5 Save and Exit Menu 100 Figure 5 1 Block Diagram u erede ee ee sh 103 Figure 5 2 Intel Xeon Processor E5 2648L C604 Chipset Platform Overview 104 Figure 5 3 PCH Block Diagramm 106 Figure 5 4 Overall SMBus Connections 111 Figure 6 1 Interrupt Structure on ATCA 7370 issssesseeee eee eens 113 Figure 7 1 SOL OVERVIOW dee NEE ee ese Re 175 Figure 8 1 System Boot Options Parameter 100 Information Flow Overview 189 Figure 9 1 Block Diadtarm ege 2 ere ee e OR einen e heb EUR RH Rec 229 Figure 10 1 IPMC Component Elements 243 Figure 10 2 SPI Busses Connection 2 cece ccc ee ee eee enhn 244 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 17 List of Figures me TTT 18 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G About this Manual EN Overview of Contents This manual is intended for users qualified in electronics or electrical engineering Users must have a working understanding of Peripheral Component Interconnect PCI AdvancedTCA and telecommunications The manual contains the following chapters and appendices About this Manual on page 19 lists all conventions and abbreviations used in this manual and outlines the revision history Safety Notes on page 25 lists safety notes applicable to the blade Sicherheitshinweise on page 31 p
27. ATA controller compliant to SATA 2 0 specification All ports can support data transfer rate of 3 0Gbps and two ports PortO and Port1 can support SATA 3 0 6 0Gbps ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 109 Functional Description 5 12 IPMI Over LAN IPMI messages can be transferred over LAN Base interface using the RMCP protocol as defined in the IPMI v1 5 specification or using the RMCP protocol extension as defined in the IPMI v2 0 specification The RMCP RMCP packets are formatted to contain IPMI request and response messages plus additional messages for discovery and authentication The IPMI over LAN functionality is supported at a level that allows the Serial over LAN feature to be implemented 5 13 USB 2 0 Interface The C604 chipset provides internal USB1 1 USB 2 0 host controllers with up to 14 USB2 0 ports Two ports are routed to the faceplate one port is routed to the RTM on ATCA 7370 The ports available at the faceplate are routed to a dual stacked connector The ports are USB 2 0 compliant 110 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Functional Description 5 14 SMBus Connections The following figure shows the overall SMBus connections on ATCA 7370 Figure 5 4 Overall SMBus Connections 0xD2 Head XDP 0xD8 XDP PCH_SMB d PCH DC SEL VR1546M VR1536M DDR AB0 CPUO OxE2 OxEO IDDR CDi DDR CD0 CPU1 OxF4 OxE4 OxEE B MEM DC C01
28. Area BDA The following BDA bytes are required by the OS 40 00 I O addresses of four COM ports 40 72 BIOS warm reset flag 40 DO BIOS warm reset counter 4 1 18 2 BIOS CLI Tool IPMIBPAR The IPMIBPAR tool can be used to change the IPMI Boot Parameter list when Linux is up and running It supports the following options Table 4 3 BIOS CLI Tool IPMIBPAR a Xx IPMB Address if not present local IPMC is used i Get device ID g Get IPMI Boot Parameter USER area 86 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G BIOS 4 2 Table 4 3 BIOS CLI Tool IPMIBPAR Option Description s file Store IPMI Boot Parameter USER area read from file Setup Utility The BIOS incorporates a Setup utility that allows you to alter a variety of system options This section describes the operation of the Setup utility which explains the various options available through a set of hierarchical menus All options are not available with the product and some options depend on BIOS customizations The current settings are stored in the NVRAM area and any changes can be copied back to this area through the Exit menu To start the Setup utility press F2 key during the early stages of POST after the power up This functionality operates when the USB keyboard is enabled and through the console redirection facility enabled The following table briefly describes the Primary Menus options and most of the Primar
29. N output LPC r 0 DEF SPI WP N output high IPMC r w 1 DEF SPI WP N output low Inverted of REC SPI WP N output LPC r 0 REC SPI WP N output high IPMC r w 1 REC SPI WP N output low 1 7 Payload Boot SPI Flash select LPC r 0 Default Boot Flash linked to PCH Recovery IPMC r w one to IPMC 1 Recovery Boot Flash linked to PCH Default one to IPMC 6 3 14 RTM Status and Control Register Table 6 67 RTM Status and Control Register Address Offset Ox4A Bit Description Default Access mM RTM Pei N Ext RTM ALL PG Ext 2 RTM MP PG Ext r 3 RTM PP PG Ext r 166 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers Table 6 67 RTM Status and Control Register continued Address Offset Ox4A Bit Description Default Access FPGA RTM ENN FPGA RTM MP EN FPGA RTM PR EN Reserved 6 3 15 Blue LED Status and Control Register Table 6 68 User LED Status and Control Register Address Offset 0x56 Software set Blue LED mode 00 Solid on 01 Long blinking 10 Short blinking 11 Off Blue LED master selection 0 Software control Blue LED with bit1 0 setting in this register 1 FPGA control Blue LED according to handle status long blinking if handle is closed or solid on if it is open ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 167 Maps and Registers 6 3 16 User LED Status and Control Regi
30. POST the BIOS identifies all PCI to PCI bridges and all PCI devices with a header Type 1 in the system It then initializes them according to their resource requirements If the PCI s option ROM is detected it will be executed and its function implemented The network option ROM adds new boot option to the BIOS boottable The SAS option ROM shows SAS configuration utility menu which lets the end user create RAID volume IJO Device Configuration Serial Ports The ATCA 7370 supports two serial ports in OS but supports only one serial port for console redirection in BIOS The default value is 3F8h IRQ4 Integrated SATA Controller The BIOS provides setup items to configure the embedded serial ATA controller for debugging purposes Hard disk autotyping is also supported The BIOS automatically determines the proper geometry for hard disks by reading the information from the drive ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 79 BIOS 4 1 6 4 1 6 1 80 Boot Options The ATCA 7370 supports BIOS Boot Specification 1 01 The BIOS identifies all IPL BAID BEV devices and BCV devices hard drives USB sticks in the system and will attempt to boot them in the order specified in startup Thefollowing boot devices are integrated in the BIOS e USB devices sticks hard drives CD ROM e Network BEV e SAS HDD connected to C604 chipset e SATAconnected to C604 chipset e EFI Shell The default boot order is as foll
31. Run and Configuration In the Run State the Super IO is always ready to enter the Configuration State Super UO Configuration Registers Address locations that are not listed are considered reserved register locations Reads to reserved registers may return non zero values Writes to reserved locations may cause system failure Global Control Configuration Registers The Super IO Global Registers lie in the address range 0x00 Ox2F All eight bits of the ADDRESS Port are used for register selection All non implemented registers and bits ignore writes and return zero when read The INDEX PORT is used to select a configuration register in the chip The DATA PORT is then used to access the selected register These registers are accessible only in the Configuration Mode Table 6 13 Global Configuration Register Summary Index Address Description Super IO Logical Device Number 0x21 Super IO Device Revision ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 125 Maps and Registers 126 Table 6 13 Global Configuration Register Summary continued Index Address Description Super IO SERIRQ and Pre divide Control Table 6 14 Super IO Logical Device Number Register Index Address 0x07 m Iesele em Logical Device Number LPC r w 0x04 Logical Device 4 UART 1Serial Port 1 0x05 Logical Device 5 UART2 Serial Port 2 Awrite to this register selects the current logical device This allows access to the
32. The address can be found out in the MAC address record of the FRU Establishing a SOL Session To start a SOL session the following requirements must be fulfilled e An Ethernet LAN connection to the onboard Gigabit Ethernet controller of the ATCA 7370 must exist ATCA 7370 IPMC firmware must correspond to version 2 0 1 and above Procedure To establish a SOL session proceed as follows 1 Make sure that the requirements detailed above are fulfilled 2 Compile and install the ipmitool on your target which is destined for opening the SOL session on the ATCA 7370 For details refer to Installing the ipmitool on page 173 3 Apply an IP address to the ATCA 7370 SOL interface For details refer to Configuring SOL Parameters on page 176 4 If necessary change user and password Default user is soluser and password is solpasswd 5 Configure the network between the ATCA 7370 and your target which is destined for opening the SOL session so that the SOL IP address is accessible ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 179 Serial Over LAN 6 Start ATCA 7370 SOL session on your target with the ipmitool and the configured IP address for the ATCA 7370 SOL interface ipmitool C 1 I lanplus H 172 16 0 221 U soluser P solpasswd k gkey sol activate For details on the command parameters refer to the ipmitool documentation available on http ipmitool sourceforge net MI To access BIOS setup screen it is
33. a control input from the Modem changes state They are reset to logic 0 when the processor reads the Modem Status register ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers When bits 0 1 2 or3 are set to logic 1 a Modem Status interrupt is generated if bit 3 of the Interrupt Enable Register is set Table 6 38 Modem Status Register MSR LPC IO Address Base 6 Change in clear to send DCTS indicator DCTS indicates that the CTS input has changed state since the last time it was read by the CPU When DCTS is set autoflow control is not enabled and the modem status interrupt is enabled a modem status interrupt is generated When autoflow control is enabled DCTS is cleared no interrupt is generated 1 Change in state of CTS input since last read 0 No change in state of CTS input since last read Change in data set ready DDSR indicator DDSR indicates that the DSR input has changed state since the last time it was read by the CPU When DDSR is set and the modem status interruptis enabled a modem status interrupt is generated 1 Change in state of DSR input since last read 0 No change in state of DSR input since last read 2 Trailing edge of the ring indicator TERI 0 LPC r w detector TERI indicates that the RI input to the chip has changed from alow to a high level When TERI is set and the modem status interrupt is enabled a modem status interrupt is genera
34. and COM2 to RTM 01 COMI to RTM and COM2 to Faceplate 10 BMC to Faceplate and COM2 to RTM 11 BMC to Faceplate and COM1 to RTM ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 153 Maps and Registers M 6 3 8 154 Table 6 47 Serial Routing Register Address Offset 0x05 Bit Description Default Access ma mee d d When bit1 in this register is 0 FPFGA_COM_SW outputs high level When it is in 1 it outputs to low level IPMC Power Level Register Table 6 48 IPMC Power Level Register Address Offset 0x06 Bit Description Default Access 7 0 IPMC Power Level IPMC writes a value which 0x00 IPMC r w represents a defined power level LPC r Whenever the IPMC writes and data into this register it should also produce an 8 ms negative pulse on FPGA DCH GPIOS to notify payload ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers 6 3 9 Payload Power Control Register Table 6 49 Payload Power Control Register Address Offset 0x07 IPMC turn on payload power request IPMC r w 1 Payload power on 0 Payload power off 7 1 Reserved 0 r 6 3 10 I2CSwitch Control Register Table 6 50 I2C Switch Control Register Address Offset 0x08 Description Default Access Bit 0 FPGA SPD MUX S 0 1 FPGA SPD MUX S 1 FPGA DCH I2C SEL ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 155 Maps and Registers 6 3 11 6 3 12
35. and Use 6806800P54G 6 2 4 6 2 4 1 Maps and Registers UART1 and UART2 Register Map UART Register Overview Table 6 1 Interrupt Source Signals List shows the registers and their addresses as offsets of a base address for one or two UART The most significant bit of the Serial Line Control Register SCR is the Divisor Latch Bit DLAB Its state effects the selection of certain UART registers The DLAB bit must be set high by the system software to access the Baud Rate Generator Divisor Latches DLL and DLM Table 6 27 UART Register Overview Bae o Receiver Buffer RBR Read Only Base Transmitter Holding THR Write Only Base 1 Interrupt Enable Register IER Base 2 Interrupt Identification Register IIR Read Only Base 2 FIFO Control be Write Only x zl x x ojo Base 5 Line Status Register Read os Modem Status Register MSR Read Only Scratch Pad Register SCR Base Divisor Latch LSB LS Base 6 x x Xx Base 7 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54C 131 Maps and Registers 6 2 5 6 2 5 1 6 2 5 2 132 UART Registers DLAB 0 Receiver Buffer Register In non FIFO mode the Receiver Buffer Register RBR holds the character received by the UART s Receive Shift Register If less than 8 bits are received the bits are right justified and the leading bits are zeroed Reading the register empties the register and resets the
36. control and configuration registers for each logical device Table 6 15 Super IO Device Revision Register Index Address 0x21 Device Revision 0x01 LPC r Table 6 16 Super IO LPC Control Register Index Address 0x28 Bit Description Default Access LPC Bus Wait States 1 Long wait states sync 6 Reserved ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers Table 6 17 Global Super IO SERIRQ and Pre divide Control Register Index Address 0x29 Bit Description Default Access SERIRQ enable 0 disabled Serial interrupts disabled 1 enabled Logical devices participate in interrupt generations SERIRQ Mode 1 Continuous Mode UART Clock pre divide 00 divide by 1 01 divide by 8 10 divide by 26 CLK_UART is 48 MHz 11 reserved 7 4 Reserved 0 LPC r 6 2 3 4 2 Logical Device Configuration Registers Use to access the registers that are assigned to each logical unit The Super IO supports two logical units and has two sets of logical device registers The two logical devices are UART1 Logical Number 4 and UART2 Logical Number 5 A separate set bank of control and configuration registers exists for each logical device and is selected with the Logical Device Number Register The INDEX PORT is used to select a specific logical device register These registers are then accessed through the DATA PORT The Logical Device registers are acce
37. data ready DR bit in the line status register to zero Other bits errors or otherwise are not cleared In FIFO mode this register latches the value of the data byte at the top of the FIFO Table 6 28 Receiver Buffer Register RBR if DLAB 0 LPC IO Address Base Bit Description Default Access Transmitter Holding Register THR This register holds the next data byte to be transmitted When the transmit shift register becomes empty the contents of the THR is loaded into the shift register The transmit data request TDRQ bit in the line status register is set to one Table 6 29 Transmitter Holding Register THR if DLAB 0 LPC IO Address Base Transmitter Holding register THR Undef LPC w Writing to THR while in FIFO mode puts THR to the top The data at the bottom of the FIFO is loaded to the shift register when it is empty ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers 6 2 5 3 Interrupt Enable Register IER This register enables four types of interrupts which independently activate the int signal and sets a value in the Interrupt Identification Register Each of the four interrupt types can be disabled by resetting the appropriate bit ofthe IER register Similarly by setting the appropriate bits selected interrupts can be enabled Table 6 30 Interrupt Enable Register IER if DLAB 0 LPC IO Address Base 1 Bit Description Default Access Receive data
38. end of the boot parameter data is indicated by two zero bytes Supported name value pairs are blade specific Details are given below n 1 n 2 16 bit zero checksum of the boot options data section LSB first Set Selector and Block Selector are used for the convenience of read write of the boot options Set Selector is used to select the storage area default area or user area The Block Selector is used to specify the offset into the storage area of the boot options in multiples of 16 bytes Table 8 13 System Boot Options Parameter 100 SET Command Usage Byte Description Request Data 1 Parameter Selector 7 1b the storage area is locked Ob the storage area is unlocked 6 0 parameter selector must be 100 2 Set Selector Oh user area All other values are reserved 190 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands Table 8 13 System Boot Options Parameter 100 SET Command Usage continued Byte Description Block Selector Offset into the storage area of the boot options in multiples of 16 bytes 4 n n lt 19 Response Data Boot Options Data to be written Should not exceed 16 bytes to be written at a time 1 Completion Code Generic plus the following command specific completion codes 80h parameter not supported 81h storage area is locked by another software entity 82h illegal write access Table
39. key It does not save changes and then exits setup configure driver Finally resets the system automatically Load Setup Defaults This option is same as pressing F9 key Loads standard default values Discard Changes Loads the original value of the boot time but does not load the default setup value Save Changes Saves all changes of all menus but does not reset the system ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 101 BIOS 102 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Chapter 5 Functional Description 5 1 Block Diagram Figure5 1 Block Diagram 4 DDR3 VLP DIMM Slots ATCA 7370 0GB PCle x16 Port2a b c d Control Power yf 4x USB SANDY BRIDGE EP 1 e aes gen PCle x4 a EAE Eh el 30 PCle QPI Connector _4 DDR3 VLP DIMM Slots aum eri d 4 gt Zones SANDY BRIDGE EP 0 u n ech Patsburg B Zone to RTM 2x USB J32 Zone2 Es to i MO297 SSD yptional Back plane J20 2x SAS UC3 4 100 I J S ix GbE X PO UCO Base T 1 Dual GbE T P2 3 Base 1000 oo P Base T Powerville Zone Quad GbE yPual Sero p Rest 4 J TN 4 4 Gu Pena Back plane Button 82599 Dual 1 10GbE X Fabric J23 Serial Dual 10
40. necessary to reset the payload SOL session is only available if the payload is powered on and initialized by the BIOS 180 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands Chapter 8 8 1 8 1 1 8 1 2 Standard IPMI Commands TheIPMC is fully compliant to the Intelligent Platform Management Interface v1 5 This section provides information about the supported IPMI commands Global IPMI Commands The IPMC supports the following global IPMI commands Table 8 1 Supported Global IPMI Commands Command NetFn Request Response CMD Get Device ID 0x06 0x07 0x01 Cold Reset 0x06 0x07 0x02 Get Device GUID 0x06 0x07 0x08 System Interface Commands The IPMC supports the following IPMI commands to support the system messaging interfaces Table 8 2 Supported System Interface Commands Command Set BMC Global Enables NetFn Request Response CMD 0x06 0x07 Get BMC Global Enables 0x06 0x07 Clear Message Flags 0x06 0x07 Get Message Flags Get Message Send Message Set Channel Access 0x06 0x07 0x06 0x07 0x06 0x07 0x06 0x07 0x40 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 181 Supported IPMI Commands 8 1 3 182 Table 8 2 Supported System Interface Commands continued NetFn Command Request Response CMD Get Channel Access 0x06 0x07 Set User Access 0x06 0x07 Get User Access 0x0
41. not reset bit is self clearing 0 No effect Transmit FIFO reset 1 Bytes in receiver FIFO and counter are reset Shift register is not reset bit is self clearing 0 No effect Access ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 6 2 5 6 Maps and Registers Table 6 34 FIFO Control Register FCR continued LPC IO Address Base 2 Bit Description Default Access ER S uev Receiver FIFO interrupt trigger level LPC w 00 1 byte 01 4 bytes 10 8 bytes 11 14 bytes Line Control Register LCR The system programmer of the LCR specifies the format of the asynchronous data communications exchange The serial data format consists of a start bit logic 0 five to eight data bits an optional parity bit and one or two stop bits logic 1 The LCR has bits for accessing the Divisor Latch and causing a break condition The programmer can also read the contents of the Line Control Register The read capability simplifies system programming and eliminates the need for separate storage in system memory Table 6 35 Line Control Register LCR LPC IO Address Base 3 Bit Description Default Access Serial character WORD length 00 5 bits 01 6 bits 10 7 bits 11 8 bits Stop bit length 1 1 5 stop bits for 5 bit WORD length 1 2 stop bits for 6 7 and 8 bit WORD length 0 1 stop bit for any serial character WORD length ATCA 7370 ATCA 7370 S Installat
42. number For example BIOS and Linux will assign sequence number as following Physical port BIOS Linux P2 SAS2 sdc P3 SAS3 sdd Network Boot The BIOS contains a classic PXE Option ROM OpROMs The following table summarizes the network boot support status Table 4 1 Network Boot Support Status Ethernet Interface PXE Boot Support Base Network Interface 1 i350 1 YES Base Network Interface 2 i350 2 YES Front Panel Network Interface i350 3 YES Update Channel Network Interface i350 4 No Fabric Network Interface 1 82599EB 1 YES Fabric Network Interface 2 82599EB 2 YES ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 81 BIOS 4 1 7 4 1 8 4 1 9 4 1 10 82 UO Redirection Console Redirection Console redirecton or I O redirection to a COM port allows to configure BIOS through the setup menu even in the absence of a VGA adapter The following option is configurable through the BIOS setup Baudrate 9600 baud 19200 baud 38400 baud and 115200 baud are supported The default value is 9600 Serial port 1 is fully compliant to industry standard 16550 asynchronous communication controllers and is integrated in the Glue Logic FPGA Serial Over LAN SOL The BIOS writes to an FPGA register in the COM port number where the console redirection is done The BIOS sets FPGA register 0x603 bit 0 to high Serial reduction control register to indicate th
43. on page 51 ATCA 7370 ATCA 7370 S supports low voltage DDR3 memory This is available upon request NOTICE Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten its life Before touching the module or electronic components make sure that you are working in an ESD safe environment ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Hardware Preparation and Installation Installation Procedure To install a DIMM module 1 2 Remove blade from system as described in Installing and Removing the Blade on page 57 Open locks of memory module socket Press module carefully into socket As soon as the memory module has been fully inserted the locks automatically close If applicable repeat steps 2 to 3 to install further modules Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten its life Before touching the module or electronic components make sure that you are working in an ESD safe environment Removal Procedure To remove a DIMM module 1 2 Remove blade from system as described in Installing and Removing the Blade on page 57 Open locks of socket at both sides The memory module is automatically lifted up Remove module from socket Repeat steps 2 to 3 in order to remove further memory modules ATCA 7370 ATCA 7370 S Installation and Use
44. request 0 LPC r w1c 1 Reset occurred 162 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers 6 3 12 9 IPMC Watchdog Timeout Register The IPMC SW sets the corresponding bit to signal an IPMC watchdog timeout event When the IPMC Watchdog Timeout bit is set from low to high the corresponding bits in Table 6 61 IPMC Watchdog Timeout for BIOS Register and Table 6 62 IPMC Watchdog Timeout for OS Register are set Table 6 60 IPMC Watchdog Timeout Register Address Offset 0x17 Bit Description Default Access IPMC Watchdog Timeout 0 No IPMC Watchdog Timeout 1 IPMC Watchdog Timeout occurred IPMC Watchdog Pre Timeout 0 No IPMC Watchdog Pre Timeout 1 IPMC Watchdog Pre Timeout occurred 6 3 12 10 IPMC Watchdog Timeout for BIOS Register When the corresponding bits in PMC Watchdog Timeout Register changes from 0 to 1 this register will have its bits set to 1 The BIOS software can clear certain bits by writing 1 to it This register is only used for communication between the IPMC and the BIOS software FPGA will not use these bits by itself OS should never write to this register Table 6 61 IPMC Watchdog Timeout for BIOS Register Address Offset 0x18 Bit Description Default Access 0 IPMC Watchdog Timeout 0 LPC r w1c 1 IPMC Watchdog Timeout occurred 1 IPMC Watchdog Pre Timeout 0 LPC r w1c 1 IPMC Watchdog Pre Timeout occurred 7 2 Reserved 000000 LPC r
45. rollback the user area in case of mis configuration To load the default settings can be done typically by an on board switch to clear the CMOS The number of boot options stored in the IPMC may differ from project to project Changing a boot option in the firmware setup menu changes the boot option in the user area as well if the same option is defined both in the user area and the set up menu Details are given below Thefollowing figure explains the basic information flow related to the system boot options parameter 100 Figure8 1 System Boot Options Parameter 100 Information Flow Overview IPMC LLL ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 189 Supported IPMI Commands The boot options are stored in the form of as a sequence of zero terminated strings The following table describes in detail the format of the parameter data for the System Boot Options parameter 100 Table 8 12 Systern Boot Options Parameter 100 Data Format Byte Description 0 1 Number of bytes of the boot options LSB first The number of bytes must be calculated and written into this field by the software which writes boot options into the storage area The values of 0x0000 and OxFFFF indicate that no valid data in the storage area 2 n Boot options The boot options are stored in the form of ASCII texts with the following format name value where all name value pairs are separated by one zero byte The
46. shall be used 5 ACPI System Power State 7 2 reserved 1 0 System Power State enumeration 00h set SO working 01h set S3 typically equates to suspend to RAM 02h S5 soft off 03h unknown 8 3 4 OEM Set Get Performance Commands Table 8 30 OEM Set Get Performance Commands NetFn Request Response OEM Set Performance Mode Ox2E Ox2F 0x21 204 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands Table 8 30 OEM Set Get Performance Commands NetFn Command name Request Response CMD Description OEM Get Performance Mode Ox2E Ox2F mail 8 3 4 1 OEM Set Performance Mode 0x21 This command can be used to change the performance mode through the P State of CPU including normal performance mode and reduced performance mode Table 8 31 OEM Set Performance Mode Command Data Field Request Data LSB of NSN IANA Enterprise Number A value of 2Ah shall be used 2nd byte of NSN IANA Enterprise Number A value of 6Fh shall be used MSB of NSN IANA Enterprise Number A value of 00h shall be used 00h OFh FRU ID Oh for ACPI5 A Power performance mode level 7 1 Reserved 0 Power State Mode Level Oh normal performance mode 1h reduced performance mode Response Data Completion Code Generic completion codes 81h failed to change performance mode 82h already in the desired performance mode LSB of NSN IANA Enterprise Number A value of 2Ah
47. the current debug level of the IPMC firmware Table 8 38 Get Debug Level Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 OA byte 2 40 byte 3 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Bit 7 IPMB L Dump Enable If set to 1 the IPMC provides a trace of IPMB L messages that are arriving to going from the IPMC via IPMB L Bit 6 n a Bit 5 KCS Dump Enable If set to 1 the IPMC provides a trace of KCS messages that are arriving to going from the IPMC via KCS Bit 4 IPMB Dump Enable If set to 1 the IPMC provides a trace of IPMB messages that are arriving to going from the IPMC via IPMB O Bit 3 n a Bit 2 Alert Logging Enable If set to 1 the IPMC outputs important alert messages onto the serial debug interface Bit 1 Low level Error Logging Enable If set to 1 the IPMC outputs low level error diagnostic messages onto the serial debug interface Bit 0 Error Logging Enable If set to 1 the IPMC outputs error diagnostic messages onto the serial debug interface ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 213 Supported IPMI Commands 8 4 5 Set Debug Level Command The Set Debug Level command sets the current debug level of the IPMC firmwar
48. the use of the startup information for debugging and troubleshooting Storing the optional ROM printouts is not required All printouts from the serial console are logged into the DRAM buffer A simple structure is used to locate the printouts buffer and define its size This floating structure is located between addresses E000h and FFFFFh Table 4 2 Printout Floating Structure Offset in Length in Field bytes bits bits Description SIGNATURE The ASCII string represented by CH which serves as a search key for locating the pointer structure RE Version low byte minor high byte major Version 1 00 0100h is defined NE ADDRESS The address of the beginning of the CP table All POINTER zeros if the CP table does not exist BUFFER SIZE In 16 Printouts buffer size in bytes ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 85 BIOS Table 4 2 Printout Floating Structure continued Offset in Length in Field bytes bits bits Description LENGTH The length of the floating pointer structure table in bytes Theversion 1 00 structureis 14 bytes long so this field contains OEh CHECKSUM A checksum of the complete pointer structure All bytes specified by the length field including CHECKSUM and reserved bytes must add up to zero 4 1 18 BIOS Interface towards OS 4 1 18 1 Proprietary BIOS Data Area BDA Bytes BIOS provides control for warm or cold reset types through the BIOS Data
49. upgrade The count of the simultaneous upgrades is limited because of the bus speed Example from shelf manger Prompt gt ipmitool t 0x92 hpm upgrade file Example with RMCP Prompt ipmitool I lan H 192 168 34 8 U Administrator P Administrator t 0x92 hpm upgrade file IPMI Over LAN BASE The IPMI over LAN interface uses the BASE Ethernet controller to do firmware upgrades The interface has to be configured before the first use Configuring this interface is described in Chapter 7 Configuring SOL Parameters on page 176 Example Prompt gt Ipmitool I lan H 172 16 0 221 U P hpm upgrade file ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Firmware Upgrade 10 2 IPMC Upgrade The IPMC component is fully HPM 1 compatible and contains three elements as shown in the figure below Figure 10 1 IPMC Component Elements 0x00000 Boot Loader 0x04000 Active Firmware 0x20000 Backup Firmware 0x3C000 There are images for the boot loader and the firmware There is also a combined image containing the boot loader and the firmware The Boot loader update should only be done if it s required The boot loader does not perform any upgrade action The boot loader is able to boot either of two redundant copies ofthe firmware in the flash depending on the current value of the special partition status byte that is stored in the internal IPMC EEPROM The boot loader can fall back to the backup
50. 0 1 to 25 5 seconds Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 218 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands 8 4 12 Enable Payload Control Command The Enable Payload Control command enables payload control from the serial debug interface Table 8 46 Enable Payload Control Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 8 4 13 Disable Payload Control Command The Disable Payload Control command disables payload control from the serial debug interface Table 8 47 Disable Payload Control Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 219 Supported IPMI Commands 8 4 14 Reset IPMC Command The Reset IPM
51. 0 ATCA 7370 S Installation and Use 6806800P54G Safety Notes EMC This section provides warnings that precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed during all phases of operation service and repair of this equipment You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment Artesyn Embedded Technologies intends to provide all necessary information to install and handle the product in this manual Because of the complexity of this product and its various uses we do not guarantee that the given information is complete If you need additional information ask your Artesyn representative The product has been designed to meet the standard industrial safety requirements It must not be used except in its specific area of office telecommunication industry and industrial control Only personnel trained by Artesyn or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the product The information given in this manual is meantto complete the knowledge of a specialist and must not be used as replacement for qualified personnel Keep away from live circuits inside the equipment Operating personnel must n
52. 0 Commands The Artesyn Embedded Technologies IPMC is a fully compliant AdvancedTCA Intelligent Platform Management Controller It supports all required and mandatory AdvancedTCA commands as defined in the PICMG 3 0 R3 0 specification and AMC O R2 0 specification Table 8 19 Supported PICMG 3 0 Commands Command Request Response CMD Get PICMG Properties 0x2C 0x2D 0x00 Get Address Info 0x2C 0x2D 0x01 FRU Control 0x2C 0x2D 0x04 Get FRU LED Properties 0x2C 0x2D 0x05 0x2C 0x2D 0x06 0x2C 0x2D 0x07 Get FRU LED State 0x2C 0x2D 0x08 Set IPMB State 0x2C 0x2D 0x09 Set FRU Activation Policy 0x2C 0x2D Ox0A Get FRU Activation Policy 0x2C 0x2D 0x0B 0x2C 0x2D Ox0C 0x2C 0x2D OxOD Set Port State 0x2C 0x2D OxOE Get Port State 0x2C 0x2D OxOF Compute Power Properties 0x2C 0x2D 0x10 Set Power Level 0x2C 0x2D 0x11 0x2C 0x2D 0x12 0x2C 0x2D 0x18 Set AMC Port State 0x2C 0x2D 0x19 Get AMC Port State 0x2C 0x2D Ox1A Get FRU Control Capabilities 0x2C 0x2D Ox1E Get target upgrade capabilities 0x2C 0x2D Ox2E 196 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands Table 8 19 Supported PICMG 3 0 Commands continued NetFn Command Request Response CMD 0x2C 0x2D Ox2F Abort firmware upgrade 0x2C 0x2D 0x30 Initiate upgrade action 0x2C 0x2D 0x31 Upload firmware block 0x2C 0x2D 0x32 Finish firmware upload 0x2C 0x2D 0x33 Get upgrade status 0x2C 0x2D 0x34 Acti
53. 00000000OOOUC XXXXXXXXXXXXXXXXXXOOOOOOOOOOOOOOOOOOOOO OCOC OCOXCXOXX XXX XXXOOOOOOOOOOOOOOOOOOOCOOOOOOO0OOO0O0O0O00O0OOOO OOOOOOCO OCGXE d vlt 0900000000000000000000000000000000000000000000000 30O000000000000000000000000000000000000000000000000 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54C Indicates a property damage message No danger encountered Pay attention to important information 23 About this Manual Summary of Changes Publication Date Description 6806800P54A August 2012 Initial Version 6806800P54B August 2012 Updated DoC 6806800P54C April 2013 This version of the document contains information about ATCA 7370 Single board variant Consequently the title has been updated to reflect this change Updated Chapter 1 Introduction on page 37 Chapter 2 Hardware Preparation and Installation on page 45 Chapter 5 Functional Description on page 103 Figure 9 1 on page 227 6806800P54D August 2013 Updated Chapter 2 Hardware Preparation and Installation on page 45 Table 2 1 and Table 2 2 Added Figure 2 1 6806800P54E December 2013 Updated Safety Notes 6806800P54F June 2014 Re branded to Artesyn 6806800P54G September 2014 Updated the descriptive text in the note for Figure 1 2 on page 42 Figure 2 2 on page 51 Figure 2 3 on page 54 Figure 5 1 on page 103 Figure 5 2 on page 104 Figure 5 4 on page 111 and Figure 9 1 on page 229 24 ATCA 737
54. 00A 16394 Pigeon Point Systems LSB Byte first byte 2 OA byte 3 40 byte 4 00 8 4 16 Graceful Reset Command The IPMC supports the Graceful Reboot option of the FRU Control command On receiving such a command the IPMC sets the Graceful Reboot Request bit of the IPMC status sends a status update notification to the payload and waits for the Graceful Reset command from the payload If the IPMC receives such a command before the payload communication time out time it sends the 0x00 completion code Success to the shelf manager Otherwise the OxCC completion code is sent The IPMC does not reset the payload upon receiving the Graceful Reset command or time out Ifthe IPMC participation is necessary the payload must request the IPMC to perform a payload reset The Graceful Reset command is also used to notify the IPMC about the completion of the payload shutdown sequence Table 8 50 Graceful Reset Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 OA byte 2 40 byte 3 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 OA byte 3 40 byte 4 00 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 221 Supported IPMI Commands 8 4 17 Get Payload Shutdown Time Out Command 222 When the shelf manager comm
55. 208 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands Table 8 35 Get Status Command Description continued Type Byte Data Field Bit 7 Graceful Reboot Request If set to 1 indicates that the payload is requested to initiate the graceful reboot sequence Bit 6 Diagnostic Interrupt Request If set to 1 indicates that a payload diagnostic interrupt request has arrived Bit 5 Shutdown Alert If set to 1 indicates that the payload is going to be shutdown Bit 4 Reset Alert If set to 1 indicates that the payload is going to be reset Bit 3 Sensor Alert If set to 1 indicates that at least one of the IPMC sensors detects a threshold crossing Bits 2 1 Mode The current IPMC modes are defined as 0 Normal 1 Standalone for a description refer to Table 8 34 2 Manual Standalone for a description refer to Table 8 34 Bit 0 Control If set to 0 the IPMC control over the payload is disabled Bits 4 7 Metallic Bus 2 Events These bits indicate pending Metallic Bus 2 requests arrived from the shelf manager 0 Metallic Bus 2 Query 1 Metallic Bus 2 Release 2 Metallic Bus 2 Force 3 Metallic Bus 2 Free Bits 0 3 Metallic Bus 1 Events These bits indicate pending Metallic Bus 1 requests arrived from the shelf manager 0 Metallic Bus 1 Query 1 Metallic Bus 1 Release 2 Metallic Bus 1 Force 3 Metallic Bus 1 Free ATCA 7370 ATCA 7370 S Instal
56. 4 3 2 1 Faceplate Connectors cece eee nee eee e eh m mere 64 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 3 Contents 3 2 2 Backplane Connectors emn 65 3 2 3 Mezzanine Card Connector sssssessssssessssssees eese een 69 3 2 4 Onboard Connectors ikesect reb ev pre e pe hessen 71 3 2 4 1 IPM Head EINEN lebe tenerte ae en 71 3 2 4 2 FPGAJTAG Head NEEN KR NENNEN eere e e Re EN Ee 72 3 3 ee LEET 72 33M POR Le NEE 72 KE ee EENEG 73 A BIOS P ee 75 AMNES c cc 75 4 1 1 Update and Recovery ehe heh hn 76 4 1 2 DRAM SUPPOM an nn a OU UD LES EE KEY Y A DUE PS eS 77 4 1 3 interrupt Routing 2e dre ree eeUUHUe Her dE ERE REPRE E PRDC DERE ERE NER E 79 4 1 4 PCI initialization 2 2 sn ee ec Rer anna han es 79 4 1 5 I O Device Configuration 0c cece cence nee eee hem n 79 41 5 1 SerialPorts u sun se EEN e EEN RR nennen 79 4 1 5 2 Integrated SATA Controller 79 4 1 6 BOOtL OPtIONs un E CC HC RCPUPPR RE ER Ex DE DRE Races 80 4 1 6 1 Boot Support for the SAS Controller 00 c cee eee eee eee ences 80 A 1 6 2 lt Network BoOt cesses nen rer eR NN det CS kn ea be 81 4 7 l ORedirection 2 nen ee ee an ELE a een ER 4 1 8 ConsoleRedirecton ehh nhe hh 82 4 1 9 Serial Over LAN SOL 0 ccc ccc cece cence HH 82 4 1 10 PMI Support once nen ee RP RF m Pe edes 82 4 1 10 1 Watchdogs 1icsner tpe ere RR RR RR ERES ERU RA daewoo 83 4 1 11 SMBI
57. 5 Funchonal Description kenne REESEN sam Ke ENDE M Se 103 5 1 jBlockDi grdin eccle rhet eR ea 103 Bid PROCESS OF CHE 104 5 3 M MOLY cr essere nier eR A eec exo dd ad bee or VARI UE usce 105 5 3 1 DDR3 Main M use RR RR UR RE TR RU RE aa aden 105 5 4 Network nenne e ERE ERE ne eh NEE EE Heme ed Eee 105 5 5 reell re EE 105 Sp Ethernet Ports ees e be nn reb OPERE LEY adi etes 107 5 6 1 ATCA3 0 Base Interface 107 5 6 2 Fabric Interface Ach 107 5 6 3 Faceplate Ethernet botz 107 5 6 4 Update Channel Ethernet 0 cece cece e eee nee m 108 5 7 SLOldQG aeri divs Hin hick ted NP eO peated doth rade CODD UUPD er ena en Debbie 108 5 8 EE 108 5 9 SerialRedirection EE 109 5 10 Real Time ClOCK oor ee a Hr a a PR es 109 SDK EICH KEE 109 5 12 IPM Over ah ebe een an ERES EE e eR cn recen 110 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 5 Contents 5 13 USB Z O Inter QR siccccee ceduEERE DUREE RII EE 110 5 14 SMBUS Connections Ee EE See ke eU P DE RSS 111 5 15 Glue Logic FPGA A seggt 20a en pe 112 6 Maps aNd Registers seem dtr ERR ERGEEEUSEERREE S EN 113 6 1 Interrupt Structure ee e EE a DICE REF ENEE 113 6 1 1 PIC Non APIC D31 FO Interrupt Mapping III 115 6 1 2 APIC D31 FO Interrupt Mapping sseeee RII 116 6 1 3 Non Maskable Interrupt Generation 118 6 2 Registeis ETT 120 6 2 1 Register Decodllg rre un een ea eek ad 121 6 2 1 1 LPE Decoding eege Jene ea
58. 5 User LED Status and Control Register MISC Status and Control Register Debug Switch and LED Status Register CPU Error Status Register IER Cave Creek Module Status and Control Register For LPC HO access add the LPC UO Base Address 0x600 ACPI Status and Control Register 150 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers Table 6 42 FPGA Register Map Overview continued LPC IPMC Address Offset I O SPI Description 0x5E 5F w Interface Control Registers 0 1 Z 0x60 63 rw PCA9555 0 Registers 0x64 67 rw PCA9555 1 Registers 0x68 6B rw PCA9555 2 Registers Ox6C 6F rw PCA9555 3 Registers E La 0x70 73 nm PCA9555 4 Registers 0x74 75 fr Thermal Event Registers 0 1 rw r LPC Scratch Registers 0 7 r rw IPMC Scratch Register 1 r r POST Code Register For LPC HO access add the LPC UO Base Address 0x600 6 3 3 Module Identification Register The Module Identification Registers identifies the ATCA 7370 Table 6 43 Module Identification Register Address Offset 0x00 Description Default ATCA 7370 Module Identification ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Access 151 Maps and Registers 6 3 4 6 3 5 152 Version Register The version register provides the version of the FPGA bit stream The initial value starts at 0x01 and will be incremented with each new release
59. 54G Maps and Registers Table 6 35 Line Control Register LCR continued LPC IO Address Base 3 Bit Description Default Access 7 Divisor latch access bit DLAB 0 LPC r w Bit 7 must be set to access the divisor latches of the baud generator during a read or write Bit 7 must be cleared during a read or write to access the RBR THR or IER 1 Access to DLL and DLM registers 0 Access to RBR THR and IER registers 6 2 5 7 Modem Control Register MCR The MCR is an 8 bit register that controls the interface with the modem or data set or any peripheral device emulating a modem Table 6 36 Modem Control Register MCR LPC IO Address Base 4 Description Default Access Data terminal ready DTR output control 1 DTR output in low active state 0 DTR output in high state 0 LPC r w Request to send RTS output control 0 LPC r w 1 RTS output in low active state 0 RTS output in high state 2 User output control signal OUT1 0 LPC r w 1 OUT1 output in high state 0 OUT1 output in low state Not supported 3 User output control signal OUT2 0 LPC r w 1 OUT2 output in high state 0 OUT2 output in low state Not supported ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 139 Maps and Registers Table 6 36 Modem Control Register MCR continued LPC IO Address Base 4 Description Default Access Local loop back diagnosti
60. 6 0x07 Set User Name 0x06 0x07 Get User Name 0x06 0x07 Set User PayloadAccess 0x06 0x07 Get User Payload Access 0x06 0x07 Ox4D Master Write Read 0x06 0x07 0x52 Set Channel Security Keys 0x06 0x07 0x56 BMC Watchdog Commands The watchdog commands are supported by blades providing a system interface and a watchdog type 2 sensor The options of pre timeout and power cycle are not supported Table 8 3 Supported Watchdog Commands Command NetFn Request Response CMD Reset Watchdog Timer 0x06 0x07 Set Watchdog Timer 0x06 0x07 Get Watchdog Timer 0x06 0x07 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands 8 1 4 SEL Device Commands Table 8 4 Supported SEL Device Commands Command NetFn Request Response CMD Get SEL Info 0x0A 0x0B 0x40 Reserve SEL 0x0A 0x0B 0x42 Get SEL Entry 0x0A 0x0B Add SEL Entry 0x0A 0x0B Clear SEL 0x0A 0x0B Get SEL Time 0x0A 0x0B Set SEL Time 0x0A 0x0B 0x49 8 1 5 FRU Inventory Commands Table 8 5 Supported FRU Inventory Commands Command NetFn Request Response CMD Get FRU Inventory Area Info 0x0A 0x0B Read FRU Data 0x0A 0x0B Write FRU Data 0x0A 0x0B ATCA 7370 ATCA 7370 S Installation and Use 6806800P54C 183 Supported IPMI Commands 8 1 6 8 1 7 184 Sensor Device Commands Table 8 6 Supported Sensor Device Commands NetFn Command Request Response Get Device SDR Info 0x04 0x05 Get Devic
61. 6806800P54G 53 Hardware Preparation and Installation 2 4 2 CaveCreek Module This section describes the steps to install remove the Cave Creek module The following figure illustrates the location of the Cave Creek module Figure 2 3 Cave Creek Module AVE CREEK MODEL 54 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Hardware Preparation and Installation Note On the single processor variant the processor and its DIMM sockets are populated on the upper side of the board Components associated with the second processor are not populated on this product variant Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten its life Before touching the module or electronic components make sure that you are working in an ESD safe environment Cave Creek Module Installation To install the Cave Creek module 1 Remove the blade from the system as described in Installing and Removing the Blade on page 57 2 Align and fasten the four M2 5x 8mm standoffs from bottom side of Cave Creek module using the four M2 5x 4mm screws 3 Insertthe Cave Creek module in the socket so that the module s standoffs fit in the blade s mounting holes ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 55 Hardware Preparation and Installation 4 Fasten the Cave Creek module to the blade using the four M2 5x 4mm screws 5 Reinstall the blade into the
62. 7 Hardware Preparation and Installation 58 Installation Procedure Thefollowing procedure describes the installation of the blade It assumes that your system is powered on If your system is not powered on you can disregard the blue LED and thus skip the respective step In this case itis purely a mechanical installation 1 Ensure that the top and bottom ejector handles are in the outward position by squeezing the lever and the latch together 2 Insert blade into the shelf by placing the top and bottom edges of the blade in the card guides of the shelf Ensure that the guiding module of shelf and blade are aligned properly 3 Apply equal and steady pressure to the blade to carefully slide the blade into the shelf until you feel resistance Continue to gently push the blade until the blade connectors engage 4 Squeeze the lever and the latch together and hook the lower and the upper handle into the shelf rail recesses 5 Fully insert the blade and lock it to the shelf by squeezing the lever and the latch together and turning the handles towards the faceplate If your shelf is powered on as soon as the blade is connected to the backplane power pins the blue LED is illuminated ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Hardware Preparation and Installation 2 5 2 When the blade is completely installed the blue LED starts to blink This indicates that the blade announces its presence to the shelf manage
63. 7_TN 2 PCIE7 RP PCIE7 RN PCIE7 TP 3 PCIE7_TN 3 PCIE6_RP O PCIE6 RN PCIEG TP PCIE6_TN O PCIEG RP PCIE6_RN PCIE6_TP 1 PCIE6_TN 1 PCIE6_RP 2 PCIE6_RN PCIE6_TP PCIE6_TN 2 PCIEG RP PCIE6_RN PCIE6_TP 3 PCIE6_TN 3 9 PCIE PCIE9 CLKP PCIE9 CLKN PCIE8_CLKP PCIE8_CLKN PCIE7 CLKP PCIE7_CLKN PCIEG CLKP PCIE6_CLKN 10 V12P V12P V12P PSO N 68 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Controls Indicators and Connectors 3 2 3 Mezzanine Card Connector Table 3 10 Mezzanine Card Connector Signals Signal C Signal B Signal A Signal 1 SMB_SDA i SMB SCI from GBE Refclk N GBE Refclk P IPMC CRU_Refclk_N DN CRU Refclk P PCle refclk N PCle refclk P GND GND 1 3 4 4 GND 4 GND PCle_TX1_N 5 PCle TX1 P 5 PCle TXO N 5 PCle TXO P PCle_RX1_N 6 PCle_RX1_P 6 PCle_RXO_N 6 PCle RXO P 7 7 7 GND PCle TX3 N 8 PCle TX3 P 8 PCle TX2 N 8 PCle_TX2_P PCle_RX3_N Ea PCle_RX3_P a PCle RX2 N Eq PCle RX2 P GND 10 GND 10 GND 10 GND PCle TX5 N PCle TX5 P PCle TX4 N PCle TX4 P PCle RX5 N PCle RX5 P PCle RX4 N PCle RX4 P GND 13 GND 13 GND 13 GND 14 PCle TX7 N PCle_TX7_P PCle_TX6_N PCle_TX6_P 15 PCle_RX7_N PCle_RX7_P PCle_RX6_N PCle_RX6_P 16 GND 16 GND 16 GND 16 GND 17 2 EN 4 5 6 7 EN EE 10 11 12 LA ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 69 Controls Indica
64. 8 Table 1 2 Mechanical Data er ee a a needy GaGa HEE Ere aes 41 Table 1 3 Blade Variants Ordering Information 43 Table 1 4 Blade Accessories Ordering Information 43 Table 2 1 Environmental Requirements 0 ec cece eee eee mme 46 Table 2 2 Power Requirements 12 us bea than ads Edad sak Geeta ER RE E REIR nae KEEPS 49 Table 3 1 Faceplate LEDs deer ee an ee a e 63 Table 3 2 RJ45 Console Connector Pinout hme 64 Table 3 3 USB Connector PINOUT sosise renens LEX RU ve Sen DERE IER Cape bed recs 65 Table 3 4 Zone 1 Connector P1 Pin Asslonment 0 cece eee e ene eens 65 Table 3 5 Zone 2 Connector J20 Pin Assignment 0 eee eee eee eee een eee nee 66 Table 3 6 Zone 2 Connector J23 Pin Assignment cee eee eee e nee aee 66 Table 3 7 Zone 3 Connector J30 Pin Assignment eee eee cece eee eee nee aee 67 Table 3 8 Zone 3 Connector J31 Pin Assignment eee eee eee eee nee 67 Table 3 9 Zone 3 Connector J32 Pin Assignment 0 cece eee eee nee nee nee 68 Table 3 10 Mezzanine Card Connector Signals 0 cece eee eee eee e eee e nee eee 69 Table 3 11 Se ERT H EEN 72 Table 3 12 Switch TE LEE 73 Table 3 13 Switch S7 Setting EEN 73 Table 4 1 Network Boot Support Status 81 Table 4 2 Printout Floating Structure 85 Table 4 3 BIOS CLI Tool IPMIBPAR 86 Table 4 4 Primary Menu Description 87 Table 4 5 SCT Navigation Keys EEN ted pinto se eee rx eee ER URP de Be
65. 8 14 System Boot Options Parameter 100 GET Command Usage Byte Request Data Description Parameter Selector 7 reserved 6 0 parameter selector must be 100 Set Selector Oh user area 1h default area All other values are reserved Block Selector Offset into the storage area ofthe boot options in multiples of 16 bytes Response Data 1 Completion Code Generic plus the following command specific completion codes 80h parameter not supported ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 191 Supported IPMI Commands 192 Table 8 14 System Boot Options Parameter 100 GET Command Usage continued Byte Description 7 4 reserved 3 0 parameter version 1h is returned Parameter Valid 7 1b the storage area is locked Ob the storage area is unlocked 6 0 parameter selector must be 100 Boot Option Data To detect the size of the whole storage area a series of read commands can be issued with the block selector in 1 increment Once the error code C9 is returned the limit has been reached and the total available space of the storage area can be determined by the block selector of the last issued command This is supported by HPI for details refer to the System Management Interface Based on HPI B User s Guide related to your system environment The following table lists the boot parameters that can be configured for the
66. A Secondary legacy mode 16 PIRQ A For other internal devices see the chipset documentation 17 PIRQ B 18 PIRQ C 19 PIRQ D 20 PIRQ E GPIO Option for SCI TCO and HPET Timer For other internal devices see the chipset documentation 21 PIRQ F GPIO 22 PIRQ G GPIO 23 PIRQ H GPIO In APIC mode the PCI Interrupts A H are mapped to IRQ 16 23 YE When programming the polarity of internal interrupt sources on the APIC interrupts 0 M through 15 receive active high internal interrupt sources interrupts 16 through 23 receive active low internal interrupt sources ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 117 Maps and Registers 6 1 3 118 Non Maskable Interrupt Generation Non Maskable Interrupt NMI is used to force a non Maskable interrupt to the processor The processor detects an NMI when it detects a rising edge on NMI NMI is reset by setting the corresponding NMI source enable disable bit in the NMI Status and Control register UO Register 61h The chipset can generate NMI by several sources which are described in following table Table 6 4 NMI Sources Cause of NMI SERR goes active either internally externally using SERR signal or using message from processor IOCHK goes active using SERIRQ stream ISA System Error Comment Can instead be routed to generate an SCI through the NSI2SCI EN bit Device 31 Function 0 TCO Base
67. ATCA 7370 ATCA 7370 S Installation and Use P N 6806800P54G September 2014 EEE 9 Copyright 2014 Artesyn Embedded Technologies Inc All rights reserved Trademarks Artesyn Embedded Technologies Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc 2014 Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries Java and all other Java based marks are trademarks or registered trademarks of Oracle America Inc in the U S and other countries Microsoft Windows and Windows Me are registered trademarks of Microsoft Corporation and Windows XP is a trademark of Microsoft Corporation PICMG CompactPCI AdvancedTCA and the PICMG CompactPCI and AdvancedTCA logos are registered trademarks of the PCI Industrial Computer Manufacturers Group UNIX is a registered trademark of The Open Group in the United States and other countries Notice While reasonable efforts have been made to assure the accuracy of this document Artesyn assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Artesyn reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Ar
68. ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 63 Controls Indicators and Connectors Table 3 1 Faceplate LEDs continued Indicator Color Description Hot Swap Blue FRU State Machine During blade installation Blue Onboard IPMC powers up Blue blinking Blade is communicating with the shelf manager Off Blade is active During blade removal Blue blinking Blade is notifying the shelf manager that it is going to deactivate Blue Blade is ready to be extracted The Out of service In Service and Attention LEDs are directly controlled by IPMC A higher application software can issue set get FRU LED state command to the IPMC to access them 3 2 Connectors 3 2 1 Faceplate Connectors Table 3 2 RJ45 Console Connector Pinout Signal RTS DTR TXD GND GND RXD DSR CTS 64 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Controls Indicators and Connectors Table 3 3 USB Connector Pinout Signal VP5 USB USB x D USB x D GND 3 2 2 Backplane Connectors Table 3 4 Zone 1 Connector P1 Pin Assignment IPMC ISC PCO Hardware Address Bit 0 IPMC ISC PC1 Hardware Address Bit 1 IPMC ISC PC2 Hardware Address Bit 2 IPMC ISC PC3 Hardware Address Bit 3 C IPMC ISC PD4 Hardware Address Bit 4 IPMC ISC PD5 Hardware Address Bit 5 IPMC ISC PD6 Hardware Address Bit 6 IPMC ISC PD7 Hardware Address Bit 7 IPMC IMC PDO IPMB Clock Po
69. ATCA 7370 blade using the system boot option parameter 100 Artesyn Embedded Technologies provides the tool named ipmibpar which is included in the BBS to interpret the boot options stored in the IPMC The boot parameters and their values mentioned here are all case sensitive All boot options listed in the following table are set by the BIOS setup menu and can be configured using the System Boot options command 100 The IPMC and BIOS software automatically synchronize the settings made in the BIOS setup menu and the settings specified using the System Boot Options command 100 Changing a parameter in either of these automatically changes the respective value in the other ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands Table 8 15 System Boot Options Parameter 100 Supported Parameters Parameter Options Default values ansi vt100 vt100 utf8 baudrate 9600 19200 38400 57600 115200 frontnet_boot on off basenet_boot on off artm_sas_boot on off bios wdt timeout numeric 180 6000 os boot wdt on off os boot wdt timeout numeric 180 6000 en cmp all 1 2 3 4 5 6 7 ratio value numeric 12 30 en xd on off virtualization on off speedstep on off Em em m vtd support on off clk_spreadspec on off artm_pwr_policy on off ddr3_refresh auto 7 8 3 9 mew font jm ATCA 7370 ATCA 7370 S Installation and Use 6806800P54
70. Address Command Description Type Request Data Byte Data Field PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 8 4 7 SetHardware Address Command The Set Hardware Address command allows the user to override the hardware address read from the hardware when the IPMC operates in manual standalone mode for a description referto Table 8 34 Table 8 41 Set Hardware Address Command Description Type Request Data Response Data Byte Data Field PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Hardware Address If set to 00 the ability to override the hardware address is disabled NOTE A hardware address change only takes effect after an IPMC reset Completion Code ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 215 Supported IPMI Commands 8 4 8 216 Table 8 41 Set Hardware Address Command Description continued Type Byte Data Field PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Get Handle Switch Command The Get Handle Switch command reads the state of the ho
71. B enabled 234 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Table 9 3 Sensor Data Records continued FRU Information and Sensor Data Records Event Sensor Event Reading Data Event Threshold Assertion Number Sensor Name Sensor Type Type Byte 1 Event Data Byte 2 Event Data Byte3 Description Deassertion Rearm 28 BMC Watchdog 2 Sensor 0x0 SeeIPMI Spec OxFF 0x0 Timer expired Asrt Auto Watchdog 0x23 specific 0x1 0x1 Hard Reset discrete 0x2 0x2 Power Down Ox6F 0x3 0x3 Power Cycle 0x4 0x8 Timer 0x8 Interrupt 29 IPMC POST Manageme digital 0x0 OxFF OxFF 0x0 Performance Asrt Auto nt Discrete 0x1 Met Subsystem 0x06 0x1 Performance Health Lags 0x28 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 235 FRU Information and Sensor Data Records Table 9 3 Sensor Data Records continued Event Sensor Event Reading Data Event Threshold Assertion Number Sensor Name Sensor Type Type Byte 1 Event Data Byte 2 Event Data Byte3 Description Deassertion Rearm 30 Ver Change Version Sensor 0x0 Change type OxFF 0x0 Hardware Asrt Auto Change specific 0x1 change Ox2B discrete 0x2 0x1 Firmware or Ox6F 0x3 software change 0x4 0x2 Hardware incompatibility mes 0x3 Firmware or 0x6 software 0x7 incompatibility 0x4 Entity is of an invalid hardware version 0x5 Entity contains invalid F W software 0x6 H
72. Bit 7 Echo On If this bit is set the IPMC enables echo for the given serial interface Bits 6 4 Reserved Bits 3 0 Baud Rate ID The baud rate ID defines the interface baud rate as follows 0 9600 bps 1 19200 bps 2 38400 bps 3 57600 bps unsupported 4 115200 bps unsupported ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 211 Supported IPMI Commands 8 4 3 SetSerial Interface Properties Command The Set Serial Interface Properties command is used to set the properties of a particular serial interface Table 8 37 Set Serial Interface Properties Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 OA byte 2 40 byte 3 00 Interface ID 0 Serial Debug Interface Bit 7 Echo On If this bitis set the IPMC enables echo for the given serial interface Bits 6 4 Reserved Bits 3 0 Baud Rate ID The baud rate ID defines the interface baud rate as follows 0 9600 bps 1 19200 bps 2 38400 bps 3 57600 bps unsupported 4 115200 bps unsupported Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 212 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands 8 4 4 Get Debug Level Command The Get Debug Level command gets
73. Block Diagram Note Onthe single processor variant the processor and its DIMM sockets are populated on the upper side of the board Components associated with the second processor are not populated on this product variant 9 3 Sensor Data Records The sensors available on the blades are detailed in the table below ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 229 FRU Information and Sensor Data Records For sensor threshold definition please use the ipmitool found on http sourceforge net projects ipmitool files ipmitool with the parameter sensor Table 9 3 Sensor Data Records Event Sensor Event Reading Data Event Threshold Assertion Number Sensor Name Sensor Type Type Byte 1 Event Data Byte 2 Event Data Byte3 Description Deassertion Rearm 0 HS Carrier HotSwap Sensor 0x0 7 4 Cause FRU ID 0x0 MO Asrt Auto OxFO specific Ox1 3 0 Previous State 0x1 M1 discrete 0x2 0x2 M2 Ox6F 0x3 0x3 M3 0x4 0x4 M4 0x5 0x5 M5 0x6 0x6 M6 0x7 0x7 M7 1 HotSwap HotSwap Sensor 0x0 1 7 4 Cause FRU ID 0x0 MO Asrt Auto RTM OxFO specific Ox1 3 0 Previous State 0x1 M1 discrete 0x2 0x2 M2 Ox6F 0x3 0x3 M3 0x4 0x4 M4 0x5 0x5 M5 0x6 0x6 M6 0x7 0x7 M7 2 48V A Volts Voltage Threshold reading threshold unr uc Inr lc Asrt Deass Auto 0x02 0x01 3 48V B Volts Voltage Threshold reading threshold unr uc Inr lc Asrt Deass Auto 0x02 0x01 230 A
74. C command allows the payload to reset the IPMC over the KCS host interface Table 8 48 Reset IPMC Command Description Type Request Data Byte Data Field PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data Reset Type Code 0x00 Cold IPMC reset to the current mode 0x01 Cold IPMC reset to the Normal mode 0x02 Cold IPMC reset to the Standalone mode for a description refer to Table 8 34 0x03 Cold IPMC resetto the Manual Standalone mode for a description refer to Table 8 34 0x04 Reset the IPMC and enter Upgrade mode Completion Code 8 4 15 Hang IPMC Command PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 The IPMC provides a way to test the watchdog timer support by implementing the Hang IPMC command which simulates firmware hanging by entering an endless loop Table 8 49 Hang IPMC Command Description Type Request Data Response Data 220 Byte 1 3 Data Field PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 OA byte 2 40 byte 3 00 Completion Code ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands Table 8 49 Hang IPMC Command Description continued Type Byte Data Field PPS IANA Private Enterprise ID 0x004
75. CI Serial ATA Port 0 Hard DiskO Displays the identity of the device attached Serial ATA Port 1 Hard Disk 1 Displays the identity of the device attached Serial ATA Port 2 Hard Disk 2 Displays the identity of the device attached SAS HDD 1 Displays the identity of the device attached ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G BIOS Table 4 11 HDD Configuration Description Field Description SAS HDD 2 Displays the identity of the device attached SAS HDD 3 Displays the identity of the device attached SAS HDD A Displays the identity of the device attached 4 2 2 5 Memory Configuration Table 4 12 lists the Memory Configuration options Table 4 12 Memory Configuration Description Field Description DDR Refresh Allows override selection of the DDR3 refresh rate for normal operation Options Auto 7 8us and 3 9us Default is Auto DDR Vdd Limit Select DDR Vdd voltage When DDR Vdd Limit is set to auto then based on the following conditions the memory voltage can be either 1 5V or 1 35V If all memory modules support 1 5V then the BIOS set memory voltage to 1 5V If all memory modules support 1 35V then the BIOS set memory voltage to 1 35V If some of the memory module support 1 35V and other support 1 5V then the BIOS set memory voltage to 1 5V Options Auto and 1 5V Default is Auto ECC Support Error Correction And Checking ECC mechanism support
76. D Status Register Table 6 71 Debug Switch and LED Status Register Address Offset 0x59 Duc SO 7 4 Ext r FPGA DBG LED N 3 0 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 169 Maps and Registers 6 3 19 6 3 20 6 4 170 Scratch Register Table 6 72 LPC Scratch Registers Address Offset 0x76 7D 7 0 LPC Scratch bits 0x00 LPC r w IPMC r POST Code Register The FPGA provides an 8 bit wide register to store POST codes to the LPC I O address 0x80 The two nibbles of the register are converted to seven segment codes and are displayed as two hex values by two seven segment LED displays which can be read by IPMC at SPI address Ox7F Table 6 73 POST Code Register Address Offset Ox7F POST codes from host 0x00 IPMC r Standard Status Codes Table 6 74 Component Status Codes Status Code Code Symbol 0x20 POSTCODE CC VARIABLE SERVICES 0x21 POSTCODE CC KEYBOARD CONTROLLER 0x22 POSTCODE CC BOOT MODE 0x23 POSTCODE CC 53 SUPPORT ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers Table 6 74 Component Status Codes Status Code Code Symbol 0x24 POSTCODE CC TCG 0x25 POSTCODE CC HDD PASSWORD 0x26 POSTCODE CC CPU IO POSTCODE CC BOOT SCRIPT POSTCODE CC STATUS CODE POSTCODE CC DATA HUB POSTCODE CC HII DATABASE Ox2B POSTCODE CC RESET 0x2C POSTCODE CC METRONOME POSTCODE CC INTERRUPT CONTROLLER POSTCODE CC DIAGNOS
77. Disabled and Enabled Default is Enabled ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G BIOS 4 2 2 SMBIOS Event Log Table 4 15 lists the SMBIOS Event Log options Table 4 15 SMBIOS Event Log Description Event Log Enable or disable SMBIOS Event Log Option Disabled and Enabled Default is Enabled View SMBIOS event log View SMBIOS event log Mark SMBIOS events as Mark SMBIOS events as read Marked SMBIOS events will not be displayed read Clears SMBIOS events Clears SMBIOS events ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 97 BIOS eee EEE 4 2 3 Security Menu Figure 4 3 shows the Security Menu options Figure 4 3 Security Menu Set Supervisor Password Table 4 16 Security Menu Description Set Supervisor Password Set Setup Supervisor Password Set User Password Set Setup User Password 98 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G BIOS 4 2 4 Boot Menu Figure 4 4 shows the Boot Menu options Figure 4 4 Boot Menu Mam Advanced Boot Priority Order FDD Drive USB Drive SASHDD Drive SATA HDD Drive Network Card Internal Shell Item Specific Help Keys used to view or Configure devices f and i arrows select a device and move the device up or down Shift 1 enables or disables a device Del deletes an unprotected device Table 4 17 Boot Menu Description Boot Priority Order Sets the ord
78. E S dump Intel Xeon E5 Intel Xeon E5 SATA 2648L 2648L Socket R Socket R o lS a J Ei amp X16 X16 Note Onthe single processor variant the processor and its DIMM sockets are populated on the upper side of the board Components associated with the second processor are not populated on this product variant ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Functional Description 3 3 5 3 1 5 4 5 5 Memory DDR3 Main Memory ATCA 7370 provides a dual Intel Xeon Processor E5 2648L CPU with Integrated Memory Controller IMC Each IMC supports four independent 72 bit 64 bit Data 8 bit ECC wide DDR3 memory channels ATCA 7370 supports one VLP DIMM sockets for each memory channel resulting in a total of eight DDR3 DIMM sockets Supported DDR3 speeds are DDR3 800 DDR3 1066 DDR3 1333 and DDR3 1600 DDR3 signaling voltage level is 1 35 V 1 5 V Higher DDR3 memory speed may be supported by the next generation processor Network IJO Controller Intel C604 chipset is PCH that is used with Intel Xeon E5 2648L Processor It provides the following interfaces e x4lane DMI connect to CPU e Eight lanes PCle Gen2 e Four ports SAS Six serial ATA SATA interfaces e Fourteen USB 2 0 interfaces e SPI Interface for BIOS e 32 bit PCI Interface e SMbus ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 105 Functional Description T
79. FO and there was no activity fora time period Non FIFO mode Transmit Holding Register Empty FIFO mode Reading bytes until Receiver FIFO drops below trigger level or setting RESETRF bit in FCR register Reading the Receiver FIFO or setting RESETRF bit in FCR register Reading the IIR Register if the source ofthe interrupt or writing into the Transmit Holding Register ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 135 Maps and Registers 6 2 5 5 136 Table 6 33 Interrupt Identification Register Decode continued oe Interrupt Set Reset Function Reading the IIR Register if the source of the interrupt or writing to the Transmitter FIFO FIFO mode Transmit FIFO has half or less than half data 0b0000 4 Modem Clearto Send Data Set Ready Status Ring Indicator Received Line Signal Detect FIFO Control Register FCR Reading the modem status register FCR is a write only register that is located at the same address as the IIR IIR is a read only register FCR enables disables the transmitter receiver FIFOs clears the transmitter receiver FIFOs and sets the receiver FIFO trigger level Table 6 34 FIFO Control Register FCR LPC IO Address Base 2 Bit Description Default FIFO enable disable 1 Transmitter and Receiver FIFO enabled 0 FIFO disabled Receiver FIFO reset 1 Bytes in receiver FIFO and counter are reset Shift register is
80. Fn Command Request Response CMD Reset Carrier SDR repository Table 8 56 on page 226 Ox2E Ox2F Some ofthe following commands refer to IPMC modes which are defined as follows Table 8 34 IPMC Modes Mode Description Standalone In standalone mode the carrier IPMC disconnects from IPMB 0 but keeps on listening to the serial debug and payload interfaces and serving requests coming from them as well as managing the modules AMC point to point P2P and clock E keying Standalone mode is intended for debugging purposes and or operation in a non ATCA environment In standalone mode the carrier IPMC automatically activates and deactivates the on carrier payload and modules whenever it does not violate any carrier limitations Manual standalone Manual standalone mode is equivalent to standalone mode with only one exception carrier IPMC control over the on carrier payload is automatically disabled in manual standalone mode 8 4 1 Get Status Command The Get Status command can be used by the payload software to retrieve the status of the IPMC Table 8 35 Get Status Command Description Type Byte Data Field PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Request Data 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID
81. G 193 Supported IPMI Commands Table 8 15 System Boot Options Parameter 100 Supported Parameters continued Parameter Options Default values ecc log option off ce ue both celog threshold numeric 1 32767 ceflood threshold numeric 1 65535 usb1 on usb2 on rtm_usb on smbios_event_log on boot_option_3 usb1 usb2 usbartm boot_option_4 basenet0 basenet1 boot_option_5 sashdd boot_option_6 frontnetO frontnet1 Table 8 16 boot order Devices Device Description SAS HDD mounted on the RTM basenet1 Base1 Network usb1 USB frontpanel 1 usb2 USB frontpanel 2 usbartm USB artm usbfdd USB floppy disk efishell Built in UEFI shell 194 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 8 1 3 Event Commands Table 8 17 Supported Event Commands Supported IPMI Commands Command Set Event Receiver Get Event Receiver NetFn Request Response 0x04 0x05 0x04 0x05 CMD Platform Event 0x04 0x05 0x02 8 1 9 LAN Device Commands Table 8 18 Supported LAN Device Commands Command Set LAN Configuration Parameters NetFn Request Response OxOC OxOD Get LAN Configuration Parameters OxOC OxOD 0x02 Set SOL Configuration Parameters OxOC OxOD 0x21 Get SOL Configuration Parameters OxOC OxOD 0x22 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 195 Supported IPMI Commands 8 2 PICMG 3
82. GbE gt Console 48V Handle On board Power Switch Supplies amp Hot p Zonet Swap Circuitry to Back plane IPMB A w 4 IPMB B gt Note On the single processor variant the processor and its DIMM sockets are populated on the upper side of the board Components associated with the second processor are not populated on this product variant ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 103 Functional Description 5 2 104 Processor The Intel Xeon E5 2648L Processor is an eight core processor based on 32 nm process technology with LGA 2011 package Socket R The processor features two Intel Quick Path Interconnect point to point links capable of up to 8 0 GT S 20 MB of shared Last Level cache L3 40 Lanes Gen3 PCle and four channels Integrated Memory Controller IMC The processor support all the existing Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions 3 SSE3 and Streaming SIMD Extensions 4 SSE4 The processor supports several Advanced Technologies Execute Disable Bit Intel 64 Technology Enhanced Intel SpeedStep Technology Intel Virtualization Technology and Simultaneous Multi Threading SMT The following figure shows the Intel Xeon E5 2648L processor block diagram Figure5 2 Intel Xeon Processor E5 2648L C604 Chipset Platform Overview ELE S655 EE EM SS m gr gr er 18 C Ethernet a A 3 5
83. Indicators and Connectors Table 3 6 Zone 2 Connector 23 Pin Assignment continued 123 5 Base Channel 1 BIT DAF BIT_DA RECH BIT_DB BIT_DC BIT DC BI DD TBI DD 6 BaseChanne2 BI2 DA BI2_DA BI2_DB BI2_DB BI2_DC SG DC B2_DD BI2 DD 7 Ina NC NC NC NC NC NC NC NC 8 Toi NC NC NC NC NC NC NC NC 9 nja NC NC NC NC NC NC NC NC 10 Inia NC NC NC NC NC NC NC NC COM RXD NC RTM PG SAS2 TX P SAS2 TX N SAS2 RX P SAS3 RX N SASO TX P SASO TX N SASO RX P SAS1_RX_N USB_P USB_N SATA_RX PICE2 0x4 Port10 PCI PCI PCI PCI PCI PCI E1O_RP O E10 RN 0 E10 TP O E10 TN O E10 TP 1 E10 TN 1 PCI PCI PCI PCI PCI PCI PCI PCI E10_RP 2 E10_RN 2 E10 TP 2 E10_TN 2 E10_RP 3 E10_RN 3 E10_TP 3 E10 TN 3 PCI E CLOCK PCI PCI PCI E_RST NC NC NC NC NC E10_CLKP E10_CLKN MISC IPMB_L_SCL IPMB L SDA V3P3 M PSO N RTM PB N RTM_GRST_ N C V12P RTM ENN SMB CLK SMB DAT Col GH PCIE_CPU1_ PCIE_CPU1_ PCIE_CPU1_ PCIE_CPUI_T PCIE_CPU1_T RXO RXO TXO X1 X1 PCIE_CPU1_ PCIE_CPU1_ i PCIE CPU1 T PCIE CPU RX2 RX2 X3 X3 3 PCIE_CPU1_ PCIE_CPU1_ PCIE CPUT PCIE_CPU1_ PCIE_CPU1_ PCIE_CPU1 PCIE_CPU1_T PCIE_CPU1_T RX4 RX4 TX4 TX4 RX5 _RX5 X5 X5 4 PCIE_CPU1_ PCIE_CPU1_ PCIE CPUT PCIE_CPU1_ PCIE_CPU1_ PCIE_CPU1 PCIE_CPU1_T PCIE_CPU1_T RX6 RX6 TX6 TX6 RX7 _RX7 X7 X7 5 PCIE_CPU1_ PCIE_CPU1_ PCIE CPUT
84. MC receives a command from shelf manager In Intel Xeon E5 2648L Processor either SMI or NMI interrupts can be enabled in MC SM CNTRL register The type of interrupt trigger is based on the following conditions or scenarios e ADIMM error counter exceeds the threshold e Redundancy is lost on a mirrored configuration or A sparing operation completes e Warm reset request This register is set by hardware once operation is complete Bit is cleared by hardware when a new operation is enabled An SMI is generated when this bit is set due to a sparing copy completion event ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 119 Maps and Registers 6 2 120 Following table defines how to determine the cause of an interrupt in the processor Table 6 5 Causes of Interrupt Recommended Platform Condition Cause Software Response MC SM DIMM ERROR STATU The register has one bit foreach Examine the associated S DIMM error counter that MC COR ECC CNT X register DIMM ERROR OVERFLOW ST exceeds threshold Determine the time since the ATUS 0 This can happen at the same counter has been cleared If a time as any of the other SMI spare channel exists and the events Sparring complete threshold has been exceeded redundancy lost in Mirror faster than would expected Mode given the background rate of correctable errors sparing should be initiated The counter should be cleared to reset the overflow bit MC RA
85. O is half or more than half empty in non FIFO mode THR is read already Modem Status one or more of the modem input signals has changed state LPC IO Address Base 2 i Interrupt status bit EN 1 no interrupt pending 0 interrupt pending 2 1 Interrupt priority level and source LPC r 11 Receiver line status 10 Receiver data available 01 Transmitter holding register empty 00 Modem status 3 Time Out Detected 0 LPC r 0 No time out interrupt is pending 1 Charactertime out indication FIFO mode only ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Table 6 32 Interrupt Identification Register IIIR Maps and Registers LPC IO Address Base 2 Description Default Access eee DE e FIFO Mode Enable bits 00 Default mode 01 Reserved 10 Reserved 11 FIFO mode EE Table 6 33 Interrupt Identification Register Decode oe Interrupt Set Reset Function 0b0001 None No Interrupt is pending 0b0110 0b0100 Receiver Line Status Received Data Available Overrun Error Parity Error Framing Error Break Interrupt Non FIFO mode Receive Buffer is full Reading the Line Status Register Non FIFO mode Reading the Receiver Buffer Register 0b1100 0b0010 Character Timeout indication 3 Transmit FIFO Data Request FIFO mode Trigger level was reached FIFO Mode only At least 1 character is in receiver FI
86. OS Support 83 4 1 12 LED Behavior During be 84 4 1 13 BIOS Setup Layout leise c reme re NEEN eere re exe ee er 84 4 1 13 1 Board Information Display 84 AV VA USB 2 0 Ports ceo se eee e ele UR e RP b Los le RR Resa 84 4 1 15 Supported Operating Systems 84 4 1 16 SPI BootElashi ex 2er ee ln Br a a eie 85 4 1 17 Serial Console and BIOS Printouts cece cece ee ee 85 4 1 17 1 BIOS Printouts to DRAM s sseeeeeeeee nennen nenne 85 4 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Contents 4 1 18 BIOS Interface towards OS 86 4 1 18 1 Proprietary BIOS Data Area BDA Bytes 0c cece e eee eee ee 86 4 1 18 2 BIOS CLI Tool IPMIBPAR 0 0 cece eee e eee IIR nennen 86 4 2 Setup Utility u geg dE t eee t yh CR Cni A e ea e tele e ee 87 4 2 1 MaimMefl sop p ECC UE ER SERO AE PETS 89 4 22 Advariced Menue cer ee pee n ER NIE Ie ENNER 90 4 2 2 1 Boot Confiouration eee hn 91 4 2 2 2 Processor Configuration 0 cece cece eee eee e teen eee eens 93 4 2 2 3 Peripheral Configuration 0 e cece eee e cence eene 94 4 2 2 4 HDD Conftguration 0 cece ccc ehe eee 94 4 2 2 5 Memory Configuration 0 c cece cece ence teen hee 95 4 2 2 6 South Bridge Configuration 96 4 2 2 7 SMBIOS Event Log lessen hn 97 4 2 3 Securnty MENU ii Deed Td eer eee E Rede Us 98 4 2 4 Boot Menu rre ee ee 99 4 2 5 SaveapdEvicMen 12 een DE ER I han 100
87. S STATUS REDUNDANC One channel of a mirrored pair Raise an indication that a reboot Y LOSS 1 had an uncorrectable errorhas should be scheduled possibly been lost replace the failed DIMM specified in the MC SMI DIMM ERROR STATU S register MC SSRSTATUS CMPLT 1 Asparring copy operationsetup Advance to the next step in the by software has completed sparing flow Registers For register description the convention shown in Table 6 7 Register Access Type and Table 6 7 Register Access Type are used Table 6 6 Register Default Not applicable or undefined Default value after RST_N is valid or after DCH PLTRST deassertion Undefined value ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 6 2 1 Maps and Registers Table 6 6 Register Default continued Default Description Default value after deassertion of the reset signal reset External Reset Source Default depends on external logic level Table 6 7 Register Access Type Read only Write only Read and write Write 1 to clear ignore bit while reading Read and write 1 to clear write O has no effect Read and write 1 to set write 0 has no effect r wit Read and write 1 to toggle write 0 has no effect LPC The prefix LPC signals that the access is restricted to the LPC interface E g LPC r w means that the register bit is read writable from the LPC interface IPMC The prefix IPMC si
88. STCODE_PC_IPL_EXIT OxE9 POSTCODE PC DXE ENTRY OxEA POSTCODE PC DXE EXIT OxEB POSTCODE EC DEI MEMORY OxEC POSTCODE EC PEI IPL OxED POSTCODE EC IPL DXE OxEE POSTCODE EC IPL PPI OxEF POSTCODE EC DXE ARCH 174 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Serial Over LAN 7 1 Overview Serial Over LAN SOL is a mechanism that you can use to redirect the serial console from the blade via an IPMI session over the network SOL uses the RMCP protocol The IPMC is used to establish and control the SOL session SOL is only available on the base interface The sideband interface of the Intel 350 in pass through mode is used to transmit receive its terminal characters via the base interface Figure 7 1 SOL Overview D 3 a E D uw Intel 350 Ethernet You can configure the SOL parameters using the standard IPMI commands or via an open source tool called ipmitool 7 2 Installing the ipmitool You can download the open source tool ipmitool from http ipmitool sourceforge net at the time of publishing this manual the current version is 1 8 11 Documentation for this tool is also available on this site ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 175 Serial Over LAN 7 3 7 3 1 176 Procedure To install the ipmitool proceed as follows 1 2 Download the ipmitool tar file from http ipmitool sourceforge net to your blade Extract the source code prompt gt tar x
89. TCA 7370 ATCA 7370 S Installation and Use 6806800P54G Table 9 3 Sensor Data Records continued FRU Information and Sensor Data Records Event Sensor Event Reading Data Event Threshold Assertion Number Sensor Name Sensor Type Type Byte 1 Event Data Byte 2 Event Data Byte3 Description Deassertion Rearm 4 48V Current Current Threshold reading threshold unr uc unc Asrt Deass Auto 0x03 0x01 5 HoldUp Volts Voltage Threshold reading threshold unr uc Inr Ic Asrt Deass Auto 0x02 0x01 6 Input Power Other Units Threshold reading threshold unr uc unc Asrt Deass Auto based 0x01 Sensor OxOB ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 231 FRU Information and Sensor Data Records Table 9 3 Sensor Data Records continued Event Sensor Event Reading Data Event Threshold Assertion Number Sensor Name Sensor Type Type Byte 1 Event Data Byte 2 Event Data Byte3 Description Deassertion Rearm 7 PWR Status OEM Sensor Ox0 Synchor Pwr Entr 7 6 Pwr Entry 0x0 Pwr Entry Asrt Auto 0xD7 specific Module Module Module Status discrete 6 VOUT_low 0 Synchor Change detected Ox6F 5 Hotswap 1 Emerson 4 Holdup Emerson Pwr 2 Alarm Entry Module 1 Enable B 2 DIG EnableA 0 Enable A 1 DIG EnableB Emerson Pwr Entry 0 Mcu Fault Module All other bits are 7 DIG Fault r
90. TIC SUMMARY POSTCODE CC SMBIOS POSTCODE CC SMM COMMUNICATION 0x31 POSTCODE CC SMM RUNTIME 0x32 POSTCODE CC SMM SERVICES POSTCODE CC FIRMWARE DEVICE POSTCODE CC CAPSULE SERVICES POSTCODE CC MONOTONIC COUNTER POSTCODE CC SMBIOS EVENT LOG 0x37 POSTCODE CC RTC 0x38 POSTCODE CC BOOT MANAGER POSTCODE CC VGA POSTCODE CC HII FORMS BROWSER POSTCODE CC BOOT MENU POSTCODE CC USER MANAGER Ox3D POSTCODE CC TIMER Ox3E POSTCODE CC PCI BUS ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 171 Maps and Registers Table 6 74 Component Status Codes Status Code Code Symbol Ox3F POSTCODE CC ISA BUS 0x40 POSTCODE CC IDE BUS 0x41 POSTCODE_CC_AHCI_BUS POSTCODE CC SCSI BUS POSTCODE CC USB BUS POSTCODE CC FLOPPY POSTCODE CC SERIAL PORT 0x46 POSTCODE CC PS2 MOUSE 0x47 POSTCODE CC PS2 KEYBOARD POSTCODE CC EHCI POSTCODE CC XHCI POSTCODE CC UHCI POSTCODE CC OHCI O0x4C POSTCODE CC USB KEYBOARD Ox4D POSTCODE CC USB MOUSE POSTCODE CC USB MASS STORAGE POSTCODE CC CONSOLE SPLITTER POSTCODE CC GRAPHICS CONSOLE POSTCODE CC SERIAL CONSOLE 0x52 POSTCODE CC TEXT CONSOLE 0x53 POSTCODE CC DISK IO POSTCODE CC PARTITION POSTCODE CC SETUP POSTCODE CC LEGACY BIOS POSTCODE CC BLOCK IO THUNK 0x58 POSTCODE CC CRYPTO 0x59 POSTCODE CC XHCI RESET 172 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers Ta
91. X4 on Port 0 3 of the fabric channels 1 2 The two 10GBase BX4 and the two 1000Base BX interfaces are connected to the ATCA backplane s Fabric Interface on connector P23 rows 4 3 Fabric Channel 1 Port 0 3 and rows 2 1 Fabric Channel 2 Port 0 3 Faceplate Ethernet Ports The ATCA 7370 provides two RJ45 on its front panel for Gigabit Ethernet The RJ45 0 the lower one on front panel can support 10 100 1000 BASE T ethernet The RJ45 1 the lower one on front panel share the same controller in 1350 with update channel GE interface The update channel is active currently so the RJ45 1 is reserved and cannot been used now ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 107 Functional Description 5 6 4 5 7 5 8 108 Update Channel Ethernet The ATCA 7370 supports one Gigabit Ethernet on update channel on P20 of Zone2 connector It uses SerDes interface and occupies the port 0 of update channles Storage ATCA 7370 supports the following types of storage e Front panel USB DISK up to two ports e Storage RTM with SATA SAS support IPMC The blade features an Intelligent Platform Management Controller IPMC compliant to PICMG 3 0 and IPMI 1 5 and 2 0 SOL only The IPMC is a management subsystem providing monitoring event logging and recovery control The IPMC serves as the gateway for management applications to access the payload hardware The IPMC firmware FW is stored in two independent memory images Cr
92. ad its thermal information such as LM75 Handle switch This signal route to IPMC interrupt to process board insertion or removing event SoLI2C Sol ALERT N SoL message interrupt to IPMC PCIE devices MSI PCIE endpoint Devices such as 82599 1350 use MSI in band interrupt mode 114 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers 6 1 1 PIC Non APIC D31 FO Interrupt Mapping Table 6 2 Non APIC PIC mode 8259 Mode Interrupt Mapping 8259 IRQ Typical Interrupt Source Internal Keyboard Master Interrupt Source 8254 Counter 0 Timer 0 HPET IRQ1 via SERIRQ Internal Slave 8259 INTR output Serial Port A IRQ3 via SERIRQ PIRQ Serial Port B Parallel Generic Floppy IRQ4 via SERIRQ PIRQ IRQS via SERIRQ PIRQ IRQ6 via SERIRQ PIRO IRQ7 via SERIRQ PIRQ Internal RTC Timer 1 HPET Generic IRQ9 via SERIRQ SCI TCO or PIRO IRQ10 via SERIRQ SCI TCO or PIRQ Generic 1 2 3 A H Parallel Generic 8 Internal RTC 9 Generic 10 11 12 PS 2 Mouse IRQ11 via SERIRQ SCI TCO or PIRQ or Timer 2 HPET IRQ12 via SERIRQ SCI TCO or PIRQ or Timer 3 HPET 13 Internal State Machine output based on processor FERR assertion May optionally be used for SCI or TCO interrupt if FERR not needed ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 115 Maps and Registe
93. alls belassen Sie die Schutzkappe auf dem SFP Modul Schaltereinstellungen Fehlfunktion des Blades Schalter die mit Reserved gekennzeichnet sind k nnen mit produktionsrelevanten Funktionen belegt sein Das ndern dieser Schalter kann im normalen Betrieb St rungen ausl sen Verstellen Sie nur solche Schalter die nicht mit Reserved gekennzeichnet sind Pr fen und ndern Sie die Einstellungen der nicht mit Reserved gekennzeichneten Schalter bevor Sie das Blade installieren Besch digung der Blade Das Verstellen von Schaltern w hrend des laufenden Betriebes kann zur Besch digung des Blades f hren Pr fen und ndern Sie die Schaltereinstellungen bevor Sie das Blade installieren Batterie Besch digung des Blades Ein unsachgem er Einbau der Batterie kann gef hrliche Explosionen und Besch digungen des Blades zur Folge haben Verwenden Sie deshalb nur den Batterietyp der auch bereits eingesetzt wurde und befolgen Sie die Installationsanleitung Umweltschutz Entsorgen Sie alte Batterien und oder Blades Systemkomponenten RTMs stets gem der in Ihrem Land g ltigen Gesetzgebung und den Empfehlungen des Herstellers ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 35 Sicherheitshinweise eee TTT 36 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Chapter 1 Introduction E 1 1 Features The ATCA 7370 is a high performance dual processor AdvancedTCA Server blade and AdvancedTCA Nod
94. amage Operating the blade without forced air cooling may lead to blade overheating and thus blade damage When operating the blade make sure that forced air cooling is available on the shelf ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 47 1 Temperature Spot 1 on Power Entry Module Max 90 C exact location on top of the transformer 2 Temperature Spot 2 on 48V 12V DC DC Module Max 100 C exact location in the geometric middle of the heat spreader 48 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Hardware Preparation and Installation 2 2 2 Power Requirements The blade s power requirements depend on the installed hardware accessories If you want to install accessories on the blade the load of the respective accessory has to be added to that of the blade Forinformation on the accessories power requirements refer to the documentation delivered together with the respective accessory or consult your local Artesyn Embedded Technologies representative for further details The blade must be connected to a TNV 2 or a safety extra low voltage SELV circuit A TNV 2 circuit is a circuit whose normal operating voltages exceed the limits for a SELV circuit under normal operating conditions and which is not subject to over voltages from telecommunication networks Table 2 2 Power Requirements Characteristic Value Rated Voltage 48 VDC to 60 VDC Exception in the US and Canada 48 VDC
95. ande 204 Table 8 30 OEM Set Get Performance Commande 204 14 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G List of Tables Table 8 31 OEM Set Performance Mode Commande 205 Table 8 32 OEM Get Performance Mode Commande 206 Table 8 33 Pigeon Point Extension Commande 207 Table 8 34 IPMCIMOGes euren pepe tbe bL ADSINT HUP nen al 208 Table 8 35 Get Status Command Description 208 Table 8 36 Get Serial Interface Properties Command Description 211 Table 8 37 Set Serial Interface Properties Command Description 212 Table 8 38 Get Debug Level Command Description 213 Table 8 39 Set Debug Level Command Description 214 Table 8 40 Get Hardware Address Command Description 215 Table 8 41 Set Hardware Address Command Description 215 Table 8 42 Get Handle Switch Command Description 216 Table 8 43 Set Handle Switch Command Description 217 Table 8 44 Get Payload Communication Time Out Command Description Ls 217 Table 8 45 Set Payload Communication Time Out Command Description LL 218 Table 8 46 Enable Payload Control Command Description 219 Table 8 47 Disable Payload Control Command Description 219 Table 8 48 Reset IPMC Command Description 220 Table 8 49 Hang IPMC Command Description 220 Table 8 50 Graceful Reset Command Description 221 Table 8 51 Get Payload Shutdown Time Out Command Description 222 Table 8 52 Set Payload Shutdown Time Out Command Des
96. ands the IPMC to shut down the payload i e sends the Activate Deactivate FRU command the IPMC notifies the payload by forwarding the command Activate Deactivate FRU to the KCS interface Provided the OpenIPMI driver has registered this command for notification the payload gets notified Upon receiving this notification the payload software is expected to initiate the payload shutdown sequence After performing this sequence the payload should send the Graceful Reset command to the IPMC over the payload Interface to notify the IPMC that the payload shutdown is complete To avoid deadlocks that may occur if the payload software does not respond the IPMC provides a special time out for the payload shutdown sequence If the payload does not send the Graceful Reset command within a definite period of time the IPMC assumes that the payload shutdown sequence is finished and resets the payload Table 8 51 Get Payload Shutdown Time Out Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 OA byte 3 40 byte 4 00 Time Out measured in hundreds of milliseconds LSB first ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands 8 4 18 Set Payload S
97. ardware Change successful 0x7 Software or F W change successful 31 FW Progress System Sensor 0x0 See IPMI Spec See IPMI Spec 0x0 System Asrt Auto Firmware SPecific 0x1 Firmware Error Progress discrete 0x2 Ox1 System OxOF Ox6F Firmware Hang 0x2 System Firmware Progress 236 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G FRU Information and Sensor Data Records Table 9 3 Sensor Data Records continued Event Sensor Event Reading Data Event Threshold Assertion Number Sensor Name Sensor Type Type Byte 1 Event Data Byte 2 Event Data Byte3 Description Deassertion Rearm 32 OS Boot OS Boot Sensor 0x0 UNF OxFF 0x0 A boot Asrt Auto Ox1F specific 0x1 completed discrete 0x2 0x1 C boot Ox6F 0x3 completed 0x4 0x2 PXE boot completed mes 0x3 Diagnostic 0x6 boot completed 0x4 CD ROM boot completed 0x5 ROM boot completed 0x6 boot completed 33 Boot Error BootError Sensor 0x0 OxFF OxFF 0x0 No Bootable Asrt Auto Ox1E specific 0x1 media discrete 0x2 0x1 Non bootable Ox6F 0x3 diskette 0x4 0x2 PXE Server not found 0x3 Invalid boot sector 0x4 Timout waiting for user selection ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 237 FRU Information and Sensor Data Records Table 9 3 Sensor Data Records continued Event Sensor Event Reading Data Event Threshold Assertion Number Sensor Name Se
98. aser products make sure to comply to the respective regulations Eye Damage Optical SFP modules may emit laser radiation when no cable is connected This laser radiation is harmful to your eyes Do not look into the optical lens at any time SFP Module Damage The optical port plug protects the optical fibres against dirt and damage Dirt and damage can render the SFP module inoperable Only remove the optical plug when you are ready to connect a cable to the SFP module When no cable is connected cover the port with an optical port plug RJ 45 Connectors The RJ 45 connectors on the face plate must only be used for twisted pair Ethernet TPE and serial console connections according to face plate marking TPE and serial connections are considered SELV circuits Connecting a telephone line TNV circuit to such a connector may destroy your telephone as well as your board Therefore e Clearly mark TPE connectors near your working area as network connectors e Only connect TPE bushing of the system to safety extra low voltage SELV circuits e Make sure thatthe length of the electric cable connected to a TPE bushing does not exceed 100 m If you have further questions ask your system administrator 28 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Safety Notes Switch Settings Battery Blade Malfunction Switches marked as reserved might carry production related functions and can cause the blade to malfunctio
99. atische Entladung und unsachgem fser Ein und Ausbau von Blades kann Schaltkreise besch digen oder ihre Lebensdauer verk rzen Bevor Sie Blades oder elektronische Komponenten ber hren vergewissern Sie sich da Sie in einem ESD gesch tzten Bereich arbeiten Datenverlust Wenn Sie das Blade aus dem Shelf herausziehen und die blaue LED blinkt noch gehen Daten verloren Warten Sie bis die blaue LED durchgehend leuchtet bevor Sie das Blade herausziehen ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Sicherheitshinweise Besch digung des Blades und von Zusatzmodulen Fehlerhafte Installation von Zusatzmodulen kann zur Besch digung des Blades und der Zusatzmodule f hren Lesen Sie daher vor der Installation von Zusatzmodulen die zugeh rige Dokumentation RJ 45 Stecker Betrieb Die RJ 45 Stecker auf der Frontblende d rfen nur f r Twisted Pair Ethernet TPE oder f r Serielle Konsole Verbindungen verwendet werden entsprechend der Markierung an der Frontblende TPE und Serielle Verbindungen sind SELV Kreise Beachten Sie dass ein versehentliches AnschliefSen einer Telefonleitung TNV Kreis an einen solchen TPE Stecker sowohl das Telefon als auch das Board zerst ren kann Beachten Sie deshalb die folgenden Hinweise e Kennzeichnen Sie TPE Anschl sse in der N he Ihres Arbeitsplatzes deutlich als Netzwerkanschl sse e Schlie en Sie an TPE Buchsen ausschlie lich SELV Kreise Sicherheitskleinspannungsstromkre
100. be EE 88 Table 4 6 Main Menu Description sun ann ob CR RE ESA e 89 Table 4 7 Advanced Menu Description 90 Table 4 8 Boot Configuration Description 91 Table 4 9 Processor Configuration Description 93 Table 4 10 Peripheral Configuration Description 94 Table 4 11 HDD Configuration Description 94 Table 4 12 Memory Configuration Description 95 Table 4 13 South Bridge Configuration Description 96 Table 4 14 SB USB Configuration Description 96 Table 4 15 SMBIOS Event Log Description 97 Table 4 16 Security Menu Desen Dot iue 1 8 en ri 98 Table 4 17 Boot Menu Description 99 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 11 List of Tables Table 4 18 Save and Exit Menu Description 100 Table 6 1 Interrupt Source Signals Uert 114 Table 6 2 Non APIC PIC mode 8259 Mode Interrupt Mapping seseeeeeeeeeeees 115 Table 6 3 APIC Mode Interrupt Mapping 116 Table 6 4 NMI SOURCES ui nop eet erre ea oa et ls e ered scare dd 118 Table 6 5 Causes of Interrupt cece cece cece eee e rn hn 120 Table 6 6 Register Default 2 nee ee an 120 Table 6 7 Register Access JIDEREEN reellen 121 Table 6 8 LPC I O Register Map Overview 122 Table 6 9 IPME SPI Registe csti nesies io eur DUREE OCEODDERDEEM RUE RR ERU ITE and 123 Table 6 10 POST Code Register e necem a4 be ae rar en 123 Table 6 11 Super UO Configuration Index Reglster nennen 124 Table 6 12 Super UO Configuration Data Register
101. ble 6 74 Component Status Codes Status Code Code Symbol OxAO0 POSTCODE CC PLATFORM STAGEO POSTCODE CC PLATFORM STAGET OxA2 POSTCODE_CC_PLATFORM_STAGE2 POSTCODE_CC_PLATFORM_SMM POSTCODE_CC_PLATFORM_FLASH POSTCODE_CC_PLATFORM_CSM POSTCODE_CC_MEMORY_CONTROLLER OxC1 POSTCODE CC PCIE OxC2 POSTCODE_CC_MANAGEMENT_ENGINE POSTCODE_CC_PCH POSTCODE_CC_SATA POSTCODE_CC_FLASH_CONTROLLER POSTCODE_CC_FLASH_DEVICE 0xD3 POSTCODE_CC_FINGERPRINT_SENSOR OxD4 POSTCODE CC CLOCK CONTROLLER OxD5 POSTCODE CC EMBEDDED CONTROLLER OxD6 POSTCODE CC SERIAL CONTROLLER Table 6 75 Progress Status Codes Status Code Code Symbol POSTCODE PC COMP PEI BEGIN POSTCODE PC COMP PEI END POSTCODE PC COMP DXE BEGIN POSTCODE PC COMP DXE END POSTCODE PC COMP SUPPORTED POSTCODE PC COMP START POSTCODE PC COMP STOP ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 173 Maps and Registers Table 6 75 Progress Status Codes Status Code Code Symbol POSTCODE PC COMP SMM INIT POSTCODE EC DEVICE ERROR POSTCODE EC RESOURCE ERROR OxOB POSTCODE EC DATA CORRUPT Table 6 76 Architectural Status Codes Status Code Code Symbol OxEO POSTCODE PC SEC ENTRY OxE1 POSTCODE PC SEC EXIT OxE2 POSTCODE PC PEI ENTRY OxE3 POSTCODE PC PEI EXIT OxE4 POSTCODE_PC_IPL_DXE OxE5 POSTCODE PC IPL S3 OxE6 POSTCODE_PC_S3_OS OxE7 POSTCODE PC IPL RECOVERY OxE8 PO
102. by the CPU In the FIFO mode THRE is set when the transmit FIFO is empty it is cleared when at least one byte is written to the transmit FIFO 1 THR Transmit FIFO empty 0 THR Transmit FIFO contains data LPC r ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 143 Maps and Registers 6 2 5 9 144 Table 6 37 Line Status Register LSR continued LPC IO Address Base 5 Bit Description Transmitter Empty TEMT indicator TEMT bit is set when the THR and the TSR are both empty When either the THR or the TSR contains a data character TEMT is cleared In the FIFO mode TEMT is set when the transmitter FIFO and shift register are both empty 1 THR Transmit FIFO TSR empty 0 THR Transmit FIFO TSR contains data FIFO data error Inthe FIFO mode LSR7 is set when there is at least one parity framing or break errorinthe FIFO It is cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO If FIFO is not used bit always reads 0 1 FIFO data error encountered 0 No FIFO error encountered Modem Status Register MSR Default Access The MCRis an 8 bit register that provides the current state of the control lines from the modem or data set or a peripheral device emulating a modem to the processor In addition to this current state information four bits of the Modem Status register provide change information Bits 03 00 are set to a logic 1 when
103. byte 2 0A byte 3 40 byte 4 00 8 4 10 Get Payload Communication Time Out Command The Get Payload Communication Time Out command reads the payload communication time out value Table 8 44 Get Payload Communication Time Out Command Description Type Request Data Byte Data Field PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 217 Supported IPMI Commands Table 8 44 Get Payload Communication Time Out Command Description continued Type Byte Data Field Payload Time out Payload communication time out measured in hundreds of milliseconds Thus the payload communication time out may vary from 0 1 to 25 5 seconds 8 4 11 SetPayload Communication Time Out Command The Set Payload Communication Time Out command sets the payload communication time out value Table 8 45 Set Payload Communication Time Out Command Description Data Field Request Data PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 OA byte 2 40 byte 3 00 4 Payload Time out Payload communication time out measured in hundreds of milliseconds Thus the payload communication time out may vary from
104. c Asrt Deass Auto 0x01 0x01 19 12 0V Temp Threshold reading threshold unr uc Inr lc Asrt Deass Auto 0x01 0x01 20 3 3V Temp Threshold reading threshold unr uc Inr lc Asrt Deass Auto 0x01 0x01 21 1 1VPCH Voltage Threshold reading threshold unr uc Inr lc Asrt Deass Auto 0x02 0x01 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 233 FRU Information and Sensor Data Records Table 9 3 Sensor Data Records continued Event Sensor Event Reading Data Event Threshold Assertion Number Sensor Name Sensor Type Type Byte 1 Event Data Byte 2 Event Data Byte3 Description Deassertion Rearm 22 1 8V CPU PLL Voltage Threshold reading threshold unr uc Inr lc Asrt Deass Auto 0x02 0x01 23 VTT CPU Voltage Threshold reading threshold unr uc Inr lc Asrt Deass Auto 0x02 0x01 24 VSA CPU Voltage Threshold reading threshold unr uc Inr lc Asrt Deass Auto 0x02 0x01 25 VCC CPU Voltage Threshold reading threshold unr uc Inr lc Asrt Deass Auto 0x02 0x01 26 1 5V DDR3 Voltage Threshold reading threshold unr uc Inr lc Asrt Deass Auto 0x02 0x01 27 IPMBOLink Physical Sensor 0x0 7 4 Channel reading 0x0 IPMB A Asrt Deass Auto IPMB 0 specific ox1 Number disabled IPMB B OxF1 discrete Ox2 3 0 Reserved disabled Ox6F 0x1 IPMB A enabled IPMB B disabled 0x2 IPMB A disabled IPMB B enabled 0x3 IPMB A enabled IPMB
105. c control 0 LPC r w When loop back is activated Transmitter TXD is set high Receiver RXD is disconnected Output of Transmitter Shift register is looped back into the receiver shift register input Modem control inputs are disconnected Modem control outputs are internally connected to modem control inputs Modem control outputs are forced to the inactive high levels 1 Loop back mode activated 0 Normal operation Autoflow control enable AFE 0 LPC r w 1 Autoflow control enabled auto RTS and auto CTS or auto CTS only enabled 0 Autoflow control disabled Reserved 0 LPC r 6 2 5 8 Line Status Register LSR This register provides status information to the processor concerning the data transfers Bits 5 and 6 show information about the transmitter section The rest of the bits contain information about the receiver In non FIFO mode three of the LSR register bits parity error framing error and break interrupt show the error status of the character that has just been received In FIFO mode these three bits of status are stored with each received character in the FIFO LSR shows the status bits of the character at the top of the FIFO When the character at the top of the FIFO has errors the LSR error bits are set and are not cleared until software reads LSR even if the character in the FIFO is read and a new character is now atthe top of the FIFO Bits one through four are the error conditions that pr
106. coding All SPI accesses from the IPMC towards the FPGA with the SPI select signal BMC SPI SO N asserted are for the internal registers Table 6 9 IPMC SPI Register SPI Address Range Address Range Name 0x00 Ox7F REGISTERS FPGA Registers 6 2 2 POST Code Register The FPGA provides and 8 bit wide register to store POST codes to the LPC HO address 0x80 The IPMC may read the POST code using the SPI interface with the signal BMC SPI S0 N asserted and the SPI address Ox7F Table 6 10 POST Code Register LPC I O Address 0x80 IPMC SPI Address 0x7f Description Default Access 7 0 POST codes from host LPC r w IPMC r ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 123 Maps and Registers 6 2 3 Super I0 Configuration Register After a LPC Reset ICH_PLTRST_is asserted or Power On Reset the Super IO is in the Run Mode with the UARTs disabled They may be configured using the LPC IO Address Range SIW INDEX and DATA by placing the Super IO into Configuration Mode The BIOS uses these configuration addresses to initialize the logical devices at POST The INDEX and DATA addresses are only valid when the Super IO is in Configuration State The INDEX and DATA addresses are effective only when the Super IO is in the Configuration State When the Super IO is not in the Configuration State reads return OxFF and write data is ignored Table 6 11 Super I O Configuration Index Register
107. copy by booting the alternate partition The boot loader manages both active and backup firmware partitions It is responsible for detecting if the active firmware is invalid or has failed In either case the Boot loader will switch to the backup partition After switching the partitions change their roles Switching of the partitions also takes place when the firmware is upgraded and activated using the HPM 1 upgrade procedure The firmware image is the regular firmware and change with every update ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 243 Firmware Upgrade 10 3 BIOS FPGA Update Both BIOS and FPGA components have two independent boot banks Both BIOS and FPGA boot banks can be upgraded with HPM 1 IPMC support automatic boot bank switching which is mandaory for HPM 1 to activate The newly upgrade firmware can be activated with a payload power cycle if you upgraded the firmware with activate option Payload always has access to the active boot bank and the IPMC always has access to the inactive boot bank All HPM 1 commands are directed to the inactive boot bank this includes get component properties The following figure shows the connection of the SPI busses which are switched with Set System Boot Options gt Boot Bank parameter 0x96 Description can be found in the System Boot Options Parameter 96 on page 186 Figure 10 2 SPI Busses Connection Bootbank 0 SPI Flash Bootbank 1 SPI Flash
108. cription 223 Table 8 53 Get Module State Command Description 223 Table 8 54 Enable Module Site Command Description 225 Table 8 55 Disable Module Site Command Description 225 Table 8 56 Reset Carrier SDR Repository Command Description 226 Table 9 1 FRU Information 3222232 per aa DU ERA RARE ss 227 Table 9 2 Power Configuratio 225 200 ihrer UE ER Ea ee it bee EE balade E e RU RU rds 228 Table 9 3 Sensor Data Records erede R IEREN EE Ree dena 230 Table 10 1 HPM Upgrade Package 245 Table B 1 Artesyn Embedded Technologies Embedded Computing Publications 249 Table B 2 Related Specifications 249 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 15 List of Tables eee TTT M 16 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G List of Figures EN Figure 1 1 Declaration of Conformity 0 eee e cece cence erent ee 40 Figure 1 2 Mechanical Layout u wa de an a 42 Figure 2 1 Location of Critical Temperature Spots Blade Top Side Luis 48 Figure 2 2 Blade Layout tege ner rure EE reece DU RP UE RR 51 Figure 2 3 Cave Creek Module ttr e ee EES deed 54 Figure 2 4 Cave Creek Module Installation 56 Figure 3 1 Faceplate DEDs 55 212 Al en bet ENN ne TR V Een 62 Figure 3 2 TPM Connector PIMOUE 6 esc eerie rhet ne hee lest 71 Figure 3 3 USB 2 0 Flash Disk Module Connector Pinout s esee esee 72 Figure 4 1 WEISE 89 Figure 4 2 Advanced Menu
109. d For further details refer Chapter 8 Supported IPMI Commands on page 181 The BIOS used on the blade is based on the Phoenix SecureCore Tiano SCT UEFI BIOS with several Artesyn extensions integrated Its main features are e Initialize CPU chipset and memory e Initialize PCI devices e Setup utility for setting configuration data e IPMC support e Serial console redirection for remote blade access e Boot operation system The BIOS complies with the following specifications e UEFI Specification 2 0 e Plug and Play BIOS Specification 1 0A e PCIBIOS Specification 2 1 e SMBIOS Specification 2 3 e BIOS Boot Specification 1 01 e PXE2 1 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 75 BIOS e SMP1 4 e ACH AO YE The BIOS contains online documentation which describes in detail the available menu M options Therefore the description in this manual is limited to the main BIOS functions The BIOS setup program is required to configure the blade hardware This configuration is necessary for operating the blade and connected peripherals The configuration data are stored in the same flash device from which the board boots When you are not sure about configuration settings restore the default values This option is provided in case a value has been changed and you wish to reset settings To restore the default values press F9 in Setup Yr Loading the BIOS default values will affect all set up items and w
110. dule Site Commande 225 8 4 21 Disable Module Site Commande 225 8 4 22 Reset Carrier SDR Repository Commande 226 9 FRU Information and Sensor Data Records 227 9 1 FRU Information nenne SWR RE eh 227 9 2 Power Configuration NEE nee a an 228 9 3 Sensor Data Records 229 10 Firmware Upgrades 25329090 4122413 DE DIR 241 10 1 HPM 1 Firmware Upgrade 241 10 11 Overview erre be bee ebbe re ener E abe nee Lia RR RR e 241 10 1 2 Installing the ipmitool 0 cee cece me 241 10 1 2 1 Update Procedure 241 19 13 Interface a De Gehaw daw 241 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 9 Contents 10 1 3 T KES Interface ee nt TR Spe a tan 242 UNE AO 242 10 1 3 3 IPM Over LAN BASE ee cent edidere enge sepe be debe iU RI ERR Rt 242 10 2 IPMG Upgrade 15252 ce ene cs meh E ER eR a 243 10 3 BIOS EPGA Update ete iir e neien e ee tee ln 244 10 4 Upgrade Package ccc cece cece ence ence ehh hn hh hs 245 A Troubleshooting 2 e o nn nn 247 AJ EITORLISE 2 2 een eoe nS in ea d dei dod hate mde eee cs 247 A 1 1 CPU Blade is Not Functioning Properly 0 c cece eee e eee nee 247 B Related Documentation 249 BI Artesyn Embedded Technologies Embedded Computing Documentation 249 B 2 Related Specifications cece cece eee nee it ENEE hh heh mee 249 10 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G List of Tables EN Table 1 1 Standard Tue 3
111. e Table 8 39 Set Debug Level Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB byte first byte 1 0A byte 2 40 byte 3 00 4 Bit 7 IPMB L Dump Enable If set to 1 the IPMC provides a trace of IPMB L messages that are arriving to going from the IPMC via IPMB L Bit 6 n a Bit 5 KCS Dump Enable If set to 1 the IPMC provides a trace of KCS messages that are arriving to going from the IPMC via KCS Bit 4 IPMB Dump Enable If set to 1 the IPMC provides a trace of IPMB messages that are arriving to going from the IPMC via IPMB O Bit 3 n a Bit 2 Alert Logging Enable If set to 1 the IPMC outputs important alert messages onto the serial debug interface Bit 1 Low level Error Logging Enable If set to 1 the IPMC outputs low level error diagnostic messages onto the serial debug interface Bit 0 Error Logging Enable If set to 1 the IPMC outputs error diagnostic messages onto the serial debug interface Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB byte first byte 2 0A byte 3 40 byte 4 00 214 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands 8 4 6 Get Hardware Address Command The Get Hardware Address command reads the hardware address of the IPMC Table 8 40 Get Hardware
112. e BIOS uses serial port 1 for SOL function The further steps to initialize SOL is done by IPMC IPMI Support The ATCA 7370 BIOS provides the following IPMI support e Checks if the IPMI controller is active If not it will display an appropriate error message e Reads self test result from the IPMI controller display It will display an error message if the self test fails e Setsinitial timestamp Sends system firmware progress to the IPMI Logs boot errors to the IPMI event log ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G BIOS 4 1 10 1 4 1 11 e Sends OS boot events e Reads slot information from the IPMI controller and fills the DMI structure Type 1 UUID The only supported interface is Keyboard Controller Style KCS The IPMI base address and interrupt is provided to OS via SMBIOS structure type38 and is tested with Linux OpenIPMI driver Watchdogs The watchdogs in ATCA 7370 are implemented by BMC watchdog BIOS uses BMC watchdog in two phases e BIOS phase e OSphase BMC watchdog for BIOS phase is started by the BMC automatically after the payload board is powered on BIOS can disable BMC watchdog through the BIOS setup menu If BMC watchdog for BIOS is enabled it will be disabled when BIOS setup menu is invoked bootto shell or boot to OS Timer value for BIOS phases is also configurable through BIOS setup menu The default time value is set to three minutes and the BMC watchdog for BIOS p
113. e SDR 0x04 0x05 CMD Reserve Device SDR Repository 0x04 0x05 Get Sensor Reading Factors 0x04 0x05 Set Sensor Hysteresis 0x04 0x05 Get Sensor Hysteresis 0x04 0x05 Set Sensor Threshold 0x04 0x05 Get Sensor Threshold 0x04 0x05 Set Sensor Event Enable 0x04 0x05 Get Sensor Event Enable 0x04 0x05 Get Sensor Event Status 0x04 0x05 Get Sensor Reading 0x04 0x05 Ox2D Get Sensor Type 0x04 0x05 Ox2F Chassis Device Commands Table 8 7 Supported Chassis Device Commands Command NetFn Request Response CMD Chassis Control 0x00 0x01 0x02 Set System Boot Options 0x00 0x01 0x08 Get System Boot Options 0x00 0x01 0x09 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands 8 1 7 1 System Boot Options Commands The Set system boot options commands allow you to control the boot process of a blade by setting boot parameters of the blade s boot firmware BIOS The boot firmware interprets the boot parameters and executes the boot process accordingly Each boot parameter addresses a particular functionality and consists of one or more bytes The parameters 0 to 7 are standard parameters defined by the IPMI specification The And parameters 96 to 127 are OEM specific When using the Get Set System Boot Options command with parameter selector of 96 97 98 the Set Selector and the Block Selector should be set to 0x00 When using the Get Set System Boot Options comma
114. e Site ID Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 225 Supported IPMI Commands 8 4 22 Reset Carrier SDR Repository Command The Reset Carrier SDR Repository command is used to clear and rebuild the carrier SDR repository Table 8 56 Reset Carrier SDR Repository Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 226 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Chapter 9 FRU Information and Sensor Data Records 9 1 FRU Information The blade provides the following FRU information in FRU ID 0 Table 9 1 FRU Information Internal use area Not used Board info area Mfg date time According to Platform Management FRU information Storage Definition v1 0 Board product name Board serial number Board part number Product info area Product manufacturer EMERSON Product part number Defined by Artesyn Network Power Embedded Computing Product serial number Defined by Artesyn Network Power Embedded C
115. e board designed according to PICMG 3 0 Revision 3 0 Advanced TCA Base Specification ATCA 7370 is a single board computer that offers a complex powerful processing through a dual eight core Intel Xeon E5 2648L processor and support for up to 128 GByte DDR3 memory and a single processor version Furthermore ATCA 7370 provides local storage standard UO and redundant Ethernet connections to the back plane s Base Interfaces PICMG3 0 and Fabric Interfaces PICMG 3 1 Option1 9 Another important feature is that ATCA 7370 provides system management capabilities and is hot swap compatible based on the ATCA specification A single processor variant of the ATCA 7370 is also available It is called ATCA 7370 S Thefollowing are the main features of ATCA 7370 e Form factor Single slot ATCA 280mm x 322mm e Processor Intel Xeon E5 2648L eight core processor e PCH chipset C604 chipset e Memory Total of eight DDR3 DIMM slots supports up to 128 GB memory with speed rate up to DDR3 1600 and 4 slots in case of single processor variant e Base interface Dual 10 100 1000Base T Ethernet e Fabric Interface Dual 1G 10Gbps Ethernet interfaces support PICMG3 1 option 1 and 9 e Cave Creek Mezzanine card for compression decompression or security optional e FrontPanel OneRJ45 GE Ethernet Port the other RJ45 GE port the lower one is reserved Two USB2 0 Ports One serial console Reset button e Onboard IPMI management controller IPMC imple
116. e payload when the timer expires Table 8 11 System Boot Options Parameter 98 Description Timeout for GRACEFUL SHUTDOWN MSB given in 100 msec Timeout for GRACEFUL SHUTDOWN LSB given in 100 msec The System Boot Options parameter 98 is non volatile It survives the IPMC power cycle reset and may survive the IPMC firmware upgrades System Boot Options Parameter 100 The system boot options parameter 100 can be used to configure the blade s boot firmware and thus control the boot process The boot options that can be configured using this parameter are typically a subset of the boot options which you can configure in the boot firmware directly for example using a setup menu The IPMC contains a storage area for the payload boot options When the blade boots the boot firmware reads out these boot options from the IPMC interprets them and executes the boot process accordingly Note that the boot options stored in the IPMC have higher priority than that stored in the local area of the boot firmware itself ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands The storage area for the boot options in the IPMC is divided into two parts the default area and the user area The user area is readable and settable It contains the boot options that are used by the boot firmware during the boot process The default area is readable only It contains the default value of the boot options and is used to
117. edium Access Controller MMC Module Management Controller Module This term is used to refer to the Module card in this document MP Management Power MTBF Mean Time Between Failures NEBS Network Equipment Building System NMI Non maskable Interrupt NT Non transparent NVRAM Non volatile Random Access Memory OEM Original Equipment Manufacturer PCB Printed Circuit Board PCI E PCI Express PICMG PCI Industrial Computer Manufacturers Group PLL Phase Locked Loop POST Power on Self Test pP Payload Power RIC Real Time Clock Rx Receive line of a duplex serial communication interface SATA Serial AT Attachment high speed serial interface standard for storage devices SCT SecureCore Tiano SDR Sensor Data Record SDRAM Synchronous Dynamic Random Access Memory SEIV Safety Extra Low Voltage SIMD Single Instruction Multiple Data ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 21 About this Manual Abbreviation Definition SMBus System Management Bus System Management Interrupt Serial Presence Detect Transmit line of a duplex serial communication interface UART Universal Asynchronous Receiver Transmitter Conventions The following table describes the conventions used throughout this manual Notation Description 0x00000000 Typical notation for hexadecimal numbers digits are O through F for example used for addresses and offsets 0b0000 Same for binary numbers digi
118. ee cease 169 6 3 18 Debug Switch and LED Status Register cece eee eee eee ence eee eae 169 6 3 19 Scratch Register u ne dec tr ERROR De 170 6 3 20 POST Code Register ccc cece cece ne eee e cence cent ee tn een nenn 170 6 4 Standard Status Code 170 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 7 Contents 7 JSerialOVWVerLAN usos sd ope ge REESEN nee 175 13 SOVEIVIEW nee ss nee 175 7 2 Anstalling the ipMitool nen TERR RexCHOE VE PEN FEES 175 7 3 Configuring SOL Parameters 0 0c cece cence eee eee he ee eee 176 7 3 1 Using Standard IPMI Commande 176 7 3 2 Usingipmitool u ara Eher e me A ai 177 7 4 Establishing a SOL Session 179 8 Supported IPMI Commands 181 8 1 Standard IPMI Commande 181 8 1 4 GloballPMI Commande 181 8 1 2 System Interface Commande 181 8 1 3 BMC Watchdog Commande 182 8 1 4 SELDevice Commande 183 8 1 5 FRU Inventory Commande 183 8 1 6 Sensor Device Commande 184 8 1 7 Chassis Device Commande 184 8 1 7 1 System Boot Options Commande 185 8 1 8 Event Commands ccereexnbeses en een Vice ede EID een a 195 8 1 9 LAN Device Commande 195 82 PICMG3 0 Commands EE 196 8 3 Artesyn Embedded Technologies Specftc Commande 198 8 3 1 Set Get Feature Configuration Commande 198 8 3 1 1 Set Feature Configuration Commande 199 8 3 1 2 Get Feature Configuration Commande 199 8 3 2 Serial Output Commande 200 8 3 2 1 Set Serial Output Co
119. ee section Peripheral Configuration HDD Configuration Set hard drive and controller configuration See section HDD Configuration Memory Configuration Displays and provides options to change the memory settings See section Memory Configuration South Bridge Configuration Set south bridge configuration See section South Bridge Configuration 90 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G BIOS Table 4 7 Advanced Menu Description continued Field Description SMBIOS Event Log Set SMBIOS configuration See section SMBIOS Event Log 4 2 2 1 Boot Configuration Table 4 8 lists the Boot Configuration options Table 4 8 Boot Configuration Description Field Description System Reset Type Enable Warm Reset support which controls next reset type Set to Cold Reset to change next reset type to cold reset Set to Warm Reset to change next reset type to warm reset Options Warm Reset and Cold Reset Default is Warm Reset Warm Reset Counter Sets the default value of Warm Reset Counter Range 0 65535 Default is 5 RPB Terminal Type Emulation ANSI Extended ASCII char set VT100 ASCII char set VT100 Extends VT100 to support color function keys etc UTF8 Uses UTF8 encoding to map Unicode chars onto 1 or more bytes Options ANSI VT100 VT100 and UTF8 Default is VT100 RPB Baudrate Selects serial port transmission speed The speed must be matched on the other side Long
120. egister anne en cha 152 6 3 5 Serial Redirection Console Register lees 152 6 3 6 Serial Over LAN SOL Control Register 0c cece cece eee eee nee 153 6 3 7 Serial Routing Register 153 6 3 8 IPMC Power Level Register 154 6 3 9 Payload Power Control Register 155 6 3 10 I2C Switch Control Register 155 6 3 11 Payload Power Button Register 156 6 3 12 Reset Reglsters cente 20a RUN cs 156 6 3 12 1 Reset Mask Register 156 6 3 12 2 Reset Function Register 157 6 3 12 3 IPMC Reset Payload Request Register 158 6 3 12 4 BIOS Reset Payload Request Register 159 6 3 12 5 OS Reset Payload Request Register 159 6 3 12 6 Payload Reset Source for IPMC Register 160 6 3 12 7 Payload Reset Source for BIOS Register 0 eee eee eee ee eee eee 160 6 3 12 8 Payload Reset Source for OS Regester 161 6 3 12 9 IPMC Watchdog Timeout Register 0 cece e eee eens 163 6 3 12 10IPMC Watchdog Timeout for BIOS Register 163 6 3 12 11IPMC Watchdog Timeout for OS Register 164 6 3 12 12FPGA Payload Watchdog Threshold Register 164 6 3 12 13FPGA Payload Watchdog Clear Register 165 6 3 12 14FPGA IPMC Watchdog Threshold Register 165 6 3 13 Flash Control Register 166 6 3 14 RTM Status and Control Register 166 6 3 15 Blue LED Status and Control Register 167 6 3 16 User LED Status and Control Register 168 6 3 17 Miscellaneous Status and Control Register 0 eee eee cece eee ence e
121. ent power is disabled 1 Management power is enabled Bit 3 0 Management power is bad 1 Management power is good Bit 4 0 Payload power is disabled 1 Payload power is enabled Bit 5 0 Payload power is bad 1 Payload power is good Bit 6 0 IPMB L buffer is not attached 1 IPMB L buffer is attached Bit 7 0 IPMB L buffer is not ready 1 IPMB L buffer is ready 224 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands 8 4 20 Enable Module Site Command The Enable Module Site command is used to enable a module site Table 8 54 Enable Module Site Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Module Site ID Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 8 4 21 Disable Module Site Command The Disable Module Site command is used to disable a module site If a module site is disabled the IPMC firmware ignores the module inserted and acts as if the module is not present Table 8 55 Disable Module Site Command Description Type Byte Data Field Request Data i PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Modul
122. equirements Y2K compliance NEBS Standard GR 63 CORE NEBS Standard GR 1089 CORE NEBS level three Project is designed to support NEBS level three The compliance tests must be done with the customer target system ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 39 Introduction Figure 1 1 Declaration of Conformity Declaration of Conformity DoC According to EN 17050 1 2004 Manufacturer s Name Artesyn Embedded Technologies Manufacturer s Address Artesyn Embedded Technologies GmbH Lilienthalstrasse 17 19 85579 Neubiberg Germany Declares that the following product Product ATCA Blade with Rear Transition Modules Model Names Numbers ATCA 7370 ATCA 7370 Cxx ATCA 7370 S ATCA 7370 S Cxx RTM ATCA 737X RTM ATCA 737X Cxx x in model name can be 0 to 9 and defines configuration in accordance with the requirements of 2004 108 EC 2006 95 EC amp 2011 65 EU and their amending directives has been designed and manufactured to the following specifications EN 60950 1 2006 A12 2011 EN 55022 2010 Class A EN 55024 2010 ETSI EN 300 386 V1 6 1 2012 09 2011 65EU RoHS Directive Kai Holz Director Engineering Issue Date 12 May 2014 Sox E M NC EMBEDDED TECHNOLOGIES 40 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Introduction 1 3 Mechanical Data Thefollowing table provides details about the blade s mechanical data such as dimensions and weight
123. er of the devices group CD DVD Drive Sets the order of the CD DVD devices in CD DVD group FDD Drive Sets the order of the USB floppy drive devices in floppy group USB Drive Sets the order of the USB HDD devices in USB group SAS HDD Drive Sets the order of the SAS HDD devices in SAS HDD group SATA HDD Drive Sets the order of the SATA HDD devices in SATA HDD group ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 99 BIOS 4 2 5 100 Table 4 17 Boot Menu Description continued Field Description Network Card Sets the order of the Network Card devices in Network Card group Internal Shell Sets the order of internal UEFI shell Save and Exit Menu Figure 4 5 shows the Save and Exit Menu options Figure4 5 Save and Exit Menu Advanced Security Boot Exit tem Specific Help xit Discarding Changes qual to F 10 save all Load Setup Defaults onfigure driver Finally resets the system automatically Table 4 18 Save and Exit Menu Description Field Description Exit Saving Changes This option is same as pressing lt F10 gt key Saves all changes of all menus then exits the setup configure driver The option finally resets the system automatically ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G BIOS Table 4 18 Save and Exit Menu Description continued Field Description Exit Discarding Changes This option is same as pressing lt ESC gt
124. es Table 6 22 Logical Device Common Decode Ranges Ox3F8 Ox3FF COMI Ox2F8 Ox2FF COM2 Ox2E8 OX2EF COM3 Ox3E8 Ox3EF COM4 Table 6 23 Logical Device Primary Interrupt Register Index Address 0x70 Interrupt level is used for Primary Interrupt LPC r w 0x0 no interrupt selected 0x1 IRQ1 0x2 IRQ2 0x3 IRQ3 0x4 IRQ4 0x5 IRQ5 0x6 IRQ6 0x7 IRQ7 0x8 IRQ8 0x9 IRQ9 OxA IRQ10 OxB IRQ11 OxC IRQ12 OxD IRQ13 OxE IRQ14 OxF IRQ15 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 129 Maps and Registers 130 Table 6 23 Logical Device Primary Interrupt Register continued Index Address 0x70 Bit Description Default Access t Reed a An Interrupt is activated by enabling this device offset 0x30 setting this register to a non zero value and setting any combination of bits 0 4 in the corresponding UART IER and the occurrence of the corresponding UART event i e Modem Status Change Receiver Line Error Condition Transmit Data Request Receiver Data Available or Receiver Time Out and setting the OUT2 bit in the MCR Table 6 24 Logical Device 0x74 Reserved Register Index Address 0x74 Table 6 25 Logical Device 0x75 Reserved Register Index Address 0x75 Description Default Access Reserved Table 6 26 Logical Device OxFO Reserved Register Index Address OxFO He Ree ERR ATCA 7370 ATCA 7370 S Installation
125. eserved 6 HUCapEngage 5 Hotswap_Enable 4 HUCap Switch 3 Alarm_Control 1 DIG_Alarm 0 Sec_MCU_Fault All other bits are reserved 8 Inlet Temp Temp Threshold reading threshold unr uc unc Asrt Deass Auto 0x01 0x01 9 Outlet Temp Temp Threshold reading threshold unr uc unc Asrt Deass Auto 0x01 0x01 10 Board Temp Temp Threshold reading threshold unr uc unc Asrt Deass Auto 0x01 0x01 232 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G FRU Information and Sensor Data Records Table 9 3 Sensor Data Records continued Event Sensor Event Reading Data Event Threshold Assertion Number Sensor Name Sensor Type Type Byte 1 Event Data Byte 2 Event Data Byte3 Description Deassertion Rearm 11 CPUO VR Temp Threshold reading threshold unr uc unc Asrt Deass Auto Temp 0x01 0x01 12 DDR VRO Temp Threshold reading threshold unr uc unc Asrt Deass Auto Temp 0x01 0x01 13 DDR VR1 Temp Threshold reading threshold unr uc unc Asrt Deass Auto Temp 0x01 0x01 14 CPUOTemp Temp Threshold reading threshold unr uc unc Asrt Deass Auto 0x01 0x01 15 DDR 1 Temp Temp Threshold reading threshold unr uc unc Asrt Deass Auto 0x01 0x01 16 DDR 2 Temp Temp Threshold reading threshold unr uc unc Asrt Deass Auto 0x01 0x01 17 DDR3 Temp Temp Threshold reading threshold unr uc unc Asrt Deass Auto 0x01 0x01 18 DDR 4 Temp Temp Threshold reading threshold unr uc un
126. ess Offset 0x14 Description Default Access Payload Power on reset IPMC r wic 1 Reset occurred Reserved IPMC r wic Front board push button reset payload IPMC r wic request 1 Reset occurred IPMC reset payload request IPMC r wic 1 Reset occurred RTM push button reset request IPMC r wic 1 Reset occurred FPGA Watchdog reset payload request IPMC r wic 1 Reset occurred BIOS reset payload request IPMC r wic 1 Reset occurred 7 OS reset payload request IPMC r wic 1 Reset occurred 6 3 12 7 Payload Reset Source for BIOS Register The BIOS Reset Source Register stores the source of the most recent reset A one in the register bit indicates that the associated reset has occurred If more than one reset occurs from different sources without clearing the corresponding register bits one can not determine the most recent reset source since more than one bit will be set The same situation will happen if two reset sources go active at the same time 160 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers The operating system should never write to this register Table 6 58 Payload Reset Source for BIOS Register Address Offset 0x15 Payload Power on reset RST N 1 LPC r wic 1 Reset occurred Reserved Reserved le LPC r w1c m board push button reset payload LPC r w1c request 1 Reset occurred 3 IPMC reset payload request LPC r w1c 1 Reset occu
127. gnals that the access is restricted to the IPMC SPI interface E g IPMC r w means that the register bit is read writable from IPMC SPI interface Register Decoding The FPGA registers may be accessed from the host or the IPMI For the host the LPC bus interface is used The IPMC uses an SPI interface ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 121 Maps and Registers 6 2 1 1 6 2 1 1 1 6 2 1 1 2 6 2 1 1 3 122 LPC Decoding The LPC bus supports different protocols LPC I O Decoding The LPC interface responds to LPC I O accesses listed in the Table 6 8 All other LPC I O accesses are ignored Table 6 8 LPC I O Register Map Overview Address Base Range Address Address Size Name Description SIW Super IO Configuration Registers for Index and Date POSTCODE POST Code Register COM UART1 Serial Port 1 Logical Device 4 BASE1 address is set up during Super IO Configuration BASE2 8 COM2 UART2 Serial Port 2 Logical Device 4 BASE2 address is set up during Super IO Configuration 0x600 128 REGISTERS FPGA Registers All LPC I O accesses to the address range REGISTERS are decoded by the LPC core LPC Memory Decoding The LPC interface never responds to LPC Memory accesses LPC Firmware Decoding The LPC interface never responds to LPC Firmware accesses ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers 6 2 1 2 SPI Register De
128. hannel for AdvancedTCA Systems ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 249 Related Documentation ee 250 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G A mS YN Z wm E Eu E EMBEDDED TECHNOLOGIES Artesyn Embedded Technologies Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners 9 2014 Artesyn Embedded Technologies Inc
129. hase is enabled by default The BIOS can disable the BMC watchdog for OS loading phases through the BIOS setup Timer value for OS loading phases is also configurable through BIOS setup The default timer value is five minutes and the BMC watchdog for OS phase is disabled by default If BMC watchdog times out in the BIOS phase BMC will switch the BIOS bank SMBIOS Support The BIOS includes SMBIOS structures according to SMBIOS 2 4 and IPMI1 5 specifications ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 83 BIOS 4 1 12 4 1 13 4 1 13 1 4 1 14 4 1 15 84 LED Behavior During POST After power up reset and while BIOS runs the LEDs are used to signalize the power up BIOS phases The state of LEDs is defined so that in case of a hang the LEDs clearly indicate in which boot up phase the hang occurred In general to indicate that the POST is in progress the BIOS toggles the user LED for every POST task it executes After the POST has been completed the BIOS switches off the LEDs The LEDs marked with B1 U1 B2 U2 and U3 will be used for this purpose BIOS Setup Layout The BIOS Setup default is aligned with the ATCA 7370 BIOS defaults Board Information Display The BIOS displays the following board related information in the BIOS setup under Board Info e Current System label for the loaded BIOS defaults set e BIOS version e BIOS build date e PMIFirmware Version e FPGA Version Onboard FPGA version
130. he following figure and tables summarize the interrupt sources and mappings for ATCA 7370 APIC mode is configured through BIOS after boot up phase which is done in legacy PIC mode Thefollowing diagram shows the interrupt signals connection and possible interrupt resources Figure6 1 Interrupt Structure on ATCA 7370 CPU Inband IRQ FPGA_IPMC_IRQO_N through DMI FPGA IPMC IRQ1 N PCH PIRQA N PCH PIRQB N IPMC FPGA IPMC IRQ2 N DCH GPIO3 for NMI PCH SPI Bus request Interrupt SCH GPIOS for SMI TOPON PCH_NMI_N HDL SW N SoL Alert N FPGA VR12 0 HOT N VR12 1 HOT N CPUO DIMMS HOT N 82599 CPU1 DIMMS HOT N PCH HOT N PCI E MSI 82599 HOT N nband Interrupt RTM PCI E Devices ALL PWR OK Signals ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 113 Maps and Registers Thefollowing table list interrupt resources Table 6 1 Interrupt Source Signals List This is a FPGA register bit written by IPMC through SPI bus to request a NMI interrupt to PCH this register bit can connect to GPIO3 of PCH to cause a PCH NMI interrupt Thermal event VR12 0 HOT N These thermal signals description please refer to VR12 1 HOT N chapter 15 Thermal Management CPUO DIMMS HOT N Thesethermalcan be arranged into FPGA register And when one signal is assert and isn t masked it can cause a interrupt to IPMC or PCH this feature can be reserved and some devices thermal management maybe be through acquire mode to re
131. he following figure shows the I O functions provided by C604 chipset and those used on ATCA 7370 ATCA 7370 S Figure 5 3 DCH Block Diagram Intel C604 Chipset i Boot SPI Boot SPI Flash 0 Flash 1 106 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Functional Description 5 6 5 6 1 5 6 2 5 6 3 Ethernet Ports ATCA 3 0 Base Interface The dual Base interface of the ATCA 7370 Node board is from two ports of Intel 1350 quad ports Gigabit Ethernet Controller The device offers quad 10 100 1000Base T and quad 1000Base X interfaces A serial EEPROM is used for storage of configuration parameters such as the MAC addresses The two 10 100 1000Base T interfaces of the Intel 1350 are directly connected to the transformers and providing the ATCA Base interface on connector P23 rows 5 and 6 Node Board This redundant connection provides the Dual Star Base Interface configuration required according to ATCA 3 0 specification Base Interface is always Dual Star 10 100 1000Base T Fabric Interface ATCA 3 1 The ATCA 7370 Fabric Interface is provided by Intel 82599 Niantic It is in accordance to ATCA subsidiary specification 3 1 Ethernet for ATCA Systems Either two10GBase BX4 or two 1000Base BX Ethernet interfaces are connected to the fabric channel 1 and 2 in the Zone 2 providing support for ATCA 3 1 Option 1 and 9 e Option 1 one 1000Base BX on Port 0 of the fabric channels 1 2 e Option 9 one 10GBase B
132. hen other function keys become available they are displayed at the right of the screen keys along with their intended function F1 General Help F9 Load Optimized Defaults F10 Save ESC and Exit 88 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G BIOS eee TTT MM 4 2 1 Main Menu Figure 4 1shows the Main Menu options Figure 4 1 Main Menu Table 4 6 Main Menu Description Field System Date System Time System Information Description Sets the time and date month day year format To change these values go to each field and enter the desired value Press the lt Tab gt key to move from hour to minute minute to second month to day or day to year There is no default value Gives the BIOS version CPU type memory type size etc ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 89 BIOS 4 2 2 Advanced Menu Figure 4 2 shows the Advanced Menu options Figure4 2 Advanced Menu Item Specific Help Processor Configuration Set Boot Configuration Peripheral Configuration HDD Configuration Memory Configuration South Bridge Configuration SMBIOSEvent Log Table 4 7 Advanced Menu Description Field Description Boot Configuration Set boot configuration See section Boot Configuration Processor Configuration Set CPU configuration See section Processor Configuration Peripheral Configuration Set system peripheral configuration S
133. hitecture Basic Blade Services BIOS Basic Input Output System DDR Dual Data Rate type of SDRAM DDR3 Double Data Rate 3 synchronous dynamic random access memory SDRAM is the name of the new DDR memory standard that is being developed as the successor to DDR2 SDRAM Dynamic Random Access Memory Error Correction Code Error Detection and Correction EEPROM Electrically Erasable Programmable Read Only Memory E EMC Electro magnetic Compatibility SD Electro static Discharge FRU Field Replaceable Unit GPIO General Purpose Input Output IMC Inter Integrated Circuit Bus 2 wire serial bus and protocol 2C I O Input Output ICH I O Control Hub also called South Bridge Integrated Memory Controller IPMB Intelligent Plattorm Management Bus IPMB L The IPMB connecting the carrier IPMC to the AMC module Intel amp QuickPath Interconnect Intel amp QPI IPMC A cache coherent link based Interconnect specification for Intel processors chipsets and I O bridge components Intelligent Plattorm Management Controller IPMI Intelligent Platform Management Interface ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G About this Manual Abbreviation Definition JTAG Joint Test Action Group test interface for digital logic circuits KCS Keyboard Controller Style LPC Low Pin Count MAC M
134. hutdown Time Out Command The Set Payload Shutdown Time Out command is defined as follows Table 8 52 Set Payload Shutdown Time Out Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 OA byte 2 40 byte 3 00 Time Out measured in hundreds of milliseconds LSB first Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 8 4 19 Get Module State Command The Get Module State command is used to query the state of a module RTM with site ID1 using any of the external interfaces Table 8 53 Get Module State Command Description Type Byte Data Field Request Data P PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Module Site ID Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54C 223 Supported IPMI Commands Table 8 53 Get Module State Command Description continued Type Byte Data Field Module Status Bit 0 0 Module site is enabled 1 Module site is disabled Bit 1 0 Module is not present 1 Module is present Bit 2 0 Managem
135. icht beachten kann das Verletzungen oder Sch den am Produkt zur Folge haben Artesyn Embedded Technologies ist darauf bedacht alle notwendigen Informationen zum Einbau und zum Umgang mit dem Produkt in diesem Handbuch bereit zu stellen Da es sich jedoch um ein komplexes Produkt mit vielf ltigen Einsatzm glichkeiten handelt k nnen wir die Vollst ndigkeit der im Handbuch enthaltenen Informationen nicht garantieren Falls Sie weitere Informationen ben tigen sollten wenden Sie sich bitte an die f r Sie zust ndige Gesch ftsstelle von Artesyn Das System erf llt die f r die Industrie geforderten Sicherheitsvorschriften und darf ausschlie lich f r Anwendungen in der Telekommunikationsindustrie und im Zusammenhang mit Industriesteuerungen verwendet werden Einbau Wartung und Betrieb d rfen nur von durch Artesyn ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgef hrt werden Die in diesem Handbuch enthaltenen Informationen dienen ausschlie lich dazu das Wissen von Fachpersonal zu erg nzen k nnen dieses jedoch nicht ersetzen Halten Sie sich von stromf hrenden Leitungen innerhalb des Produktes fern Entfernen Sie auf keinen Fall Abdeckungen am Produkt Nur werksseitig zugelassenes Wartungspersonal oder anderweitig qualifiziertes Wartungspersonal darf Abdeckungen entfernen um Komponenten zu ersetzen oder andere Anpassungen vorzunehmen Installieren Sie keine Ersatzteile oder f hren Sie ke
136. ill reset options NN previously altered e Ifyou set the default values the displayed default values takes effect only after the BIOS setup is saved and closed 4 1 1 Update and Recovery The ATCA 7370 has two different ways to update the BIOS e Flashtool FCU and ipmitool in Linux Used for normal upgrade mode e USB CD ROM or USB flash device This is used in BIOS recovery modes 76 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G BIOS 4 1 2 DRAM Support The BIOS supports the following features of the memory controller e Autosizing The BIOS reads the Serial Presence Detect SPD data from the memory modules and automatically configures the chipset accordingly e ECC Support Single Bit Errors SBE can be detected corrected and logged Multi Bit Errors MBE can be detected but not corrected By default BIOS enables ECC support in the chipset However the BIOS setup menu provides an option to enable or disable ECC ECC Error Report Support ATCA 7370 supports ECC error reporting When an ECC error occurs the memory controller hardware increments an ECC error count and triggers the SMI interrupt to let BIOS or OS handle the ECC error The ECC counter is cleared at power cycle reset The counter is preserved during a cold reset warm reset and S3 suspend resume The SMI routine is used to handle ECC error report on both the BIOS and OS The ECC error log is stored in the BIOS SPI Flash After Linu
137. ine unerlaubten Ver nderungen am Produkt durch sonst verf llt die Garantie Wenden Sie sich f r Wartung oder Reparatur bitte an die f r Sie zust ndige Gesch ftsstelle von Artesyn So stellen Sie sicher dass alle sicherheitsrelevanten Aspekte beachtet werden ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 31 Sicherheitshinweise EMV Das Blade wurde in einem Artesyn Standardsystem getestet Es erf llt die f r digitale Ger te der Klasse A g ltigen Grenzwerte in einem solchen System gem den FCC Richtlinien Abschnitt 15 bzw EN 55022 Klasse A Diese Grenzwerte sollen einen angemessenen Schutz vor St rstrahlung beim Betrieb des Blades in Gewerbe sowie Industriegebieten gew hrleisten Das Blade arbeitet im Hochfrequenzbereich und erzeugt St rstrahlung Bei unsachgem em Einbau und anderem als in diesem Handbuch beschriebenen Betrieb k nnen St rungen im Hochfrequenzbereich auftreten Warnung Dies ist eine Einrichtung der Klasse A Diese Einrichtung kann im Wohnbereich Funkst rungen verursachen In diesem Fall kann vom Betreiber verlangt werden angemessene Ma nahmen durchzuf hren Die nachfolgend aufgef hrten Schnittstellen sind Wartungsschnittstellen USB1 USB2 und COM W hrend des Normalbetriebs darf an diesen Schnittstellen kein Kabel angeschlossen sein Im Wartungsfall angeschlossene Kabel d rfen eine L nge von 3m nicht berschreiten Installation 32 Besch digung von Schaltkreisen Elektrost
138. interrupt enable disable 1 receive data interrupt enabled 0 receive data interrupt disabled Transmitter holding register empty THRE interrupt enable disable 1 THRE interrupt enabled 0 THRE interrupt disabled Receiver line status interrupt enable disable 1 receiver line status interrupt enabled 0 receiver line status interrupt disabled Modem status interrupt enable disable 1 modem status interrupt enabled 0 modem status interrupt disabled Da eem 00000 9 uer ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 133 Maps and Registers 6 2 5 4 134 Interrupt Identification Register IIR In order to minimize software overhead during data character transfers UART prioritizes interrupts into four levels and records these in the IIIR The IIIR stores information indicating that a prioritized interrupt is pending as well as the source of that interrupt The four levels are listed in the succeeding table Table 6 31 UART Interrupt Priorities2 Priority Level Interrupt Source 1 highest Receiver Line Status One or more error bits were set ol Received Data is available In FIFO mode trigger level was reached in non FIFO mode RBR has data Receiver Time out occurred It happens in FIFO mode only when there is data in the Table 6 32 Interrupt Identification Register IIIR receive FIFO but no activity for a time period Transmitter requests data In FIFO mode the transmit FIF
139. ion and Use 6806800P54G 137 Maps and Registers 138 Table 6 35 Line Control Register LCR continued LPC IO Address Base 3 Bit Description Default Access 3 Parity enable disable LPC r w When bit 3 is set a parity bit is generated in transmitted data between the last data WORD bit and the first stop bit In received data if bit 3 is set parity is checked When bit 3 is cleared no parity is generated or checked 1 Parity enabled 0 Parity disabled 4 Parity even odd 0 LPC r w When parity is enabled and bit 4 is set even parity an even number of logic ones in the data and parity bits is selected When parity is disabled and bit 4 is cleared odd parity an odd number of logic ones is selected 1 Even parity 0 Odd parity 5 Stick parity 0 LPC r w When bits 3 4 and 5 are set the parity bit is transmitted and checked as cleared When bits 3 and 5 are set and bit 4 is cleared the parity bit is transmitted and checked as set If bit 5 is cleared stick parity is disabled 1 Stick parity enabled 0 Stick parity disabled 6 Break control bit 0 LPC r w Bit 6 is set to force a break condition i e a condition where TXD is forced to the spacing cleared state When bit 6 is cleared the break condition is disabled and has no affect on the transmitter logic It only effects TXD 1 Break condition enabled 0 Break condition disabled ATCA 7370 ATCA 7370 S Installation and Use 6806800P
140. is not available if the O S Watchdog is disabled Options Disabled and Enabled Default is Disabled O S Boot Watchdog Timeout Choose Timeout value for O S Boot Watchdog Timer Range 180 6000 Default is 300 92 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G BIOS 4 2 2 2 Processor Configuration Table 4 9 lists the Processor Configuration options Table 4 9 Processor Configuration Description Active Processor Cores Intel R HT Technology Number of cores to enable in each processor package Options ALL 1 2 3 4 5 6 7 Default is ALL Enabled for Windows XP and Linux OS optimized for Hyper Threading Technology and Disabled for other OS OS not optimized for Hyper Threading Technology When disabled only one thread per enabled core is enabled Options Disabled and Enabled Default is Disabled CPU Flex Ratio Override Enable or Disable CPU Flex Ratio Programming Option Disabled and Enabled Default is Disabled CPU Flex Ratio Settings Allows for selecting the CPU Ratio value this value must be between Max efficiency ratio and Max non turbo ratio Range 12 30 If CPU Flex Ratio Override is disabled the CPU Flex Ratio Settings menu item is hidden To view this menu item set Advanced Processor Configuration gt CPU Flex Ratio Override to enable Default is 18 Enabled XD Enabled Execute Disabled functionality Also known as Data Execution Preventio
141. ise an e Diel ngedes mit dem Board verbundenen Twisted Pair Ethernet Kabels darf 100 m nicht berschreiten Besch digung des Blades Hohe Luftfeuchtigkeit und Kondensat auf der Oberfl che des Blades k nnen zu Kurzschl ssen f hren Betreiben Sie das Blade nur innerhalb der angegebenen Grenzwerte f r die relative Luftfeuchtigkeit und Temperatur Stellen Sie vor dem Einschalten des Stroms sicher dass sich auf dem Blade kein Kondensat befindet berhitzung und Besch digung des Blades Betreiben Sie das Blade ohne Zwangsbel ftung kann das Blade berhitzt und schlie lich besch digt werden Bevor Sie das Blade betreiben m ssen Sie sicher stellen dass das Shelf ber eine Zwangsk hlung verf gt ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 33 Sicherheitshinweise Wenn Sie das Blade in Gebieten mit starker elektromagnetischer Strahlung betreiben stellen Sie sicher dass das Blade mit dem System verschraubt ist und das System durch ein Geh use abgeschirmt wird Verletzungen oder Kurzschl sse Blade oder Stromversorgung Falls die ORing Dioden des Blades durchbrennen kann das Blade einen Kurzschluss zwischen den Eingangsleitungen A und B verursachen In diesem Fall ist Leitung A immer noch unter Spannung auch wenn sie vom Versorgungskreislauf getrennt ist und umgekehrt Pr fen Sie deshalb immer ob die Leitung spannungsfrei ist bevor Sie Ihre Arbeit fortsetzen um Sch den oder Verletzungen zu vermeiden
142. isis recovery control is provided to allow reboot of the IPMC from a second image if the upgraded FW image is corrupted FW images can be upgraded via HPM 1 IPMI using either IPMB or KCS interface The IPMC supports the initiation of a graceful shutdown of the host CPU The IPMC can force the CPU to reset It also controls the power and reset of the payload The IPMC provides a watchdog that supervises the payload If enabled the payload software needs to retrigger the Watchdog to prevent time out A watchdog time out can generate a NMI a payload reset or disabling cycling of the payload power The watchdog settings including enable disable can be changed by payload software setup menu Time out values can be selected from as short as seconds to as long as minutes The IPMC is supervised by a separate hardware Watchdog which can not be disabled IPMC FW retriggers the Watchdog timer ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Functional Description 5 9 5 10 5 11 The IPMC monitors the Port 80 POST codes generated by the payload CPU The IPMC is connected to various sensors on the Blade that provide temperature sensor readings at all major devices and voltage sensor readings of all major voltages The IPMC monitors reset events caused by devices like Watchdog IPMI command and reset button The FRU information of the various modules including front board RTM and other modules can be read via the IPMC and if neces
143. jvf ipmitool lt version gt tar bz2 Gotothe directory to which you have extracted the ipmitool prompt cd path ipmitool version Build the ipmitool prompt configure amp amp make amp amp make install Configuring SOL Parameters You can configure the following SOL parameters Table 7 1 SOL Parameters Parameter Description Set LAN Configuration Parameter IP Use this command to set the IP and MAC address address MAC address Set Channel Access Privilege level Use this command to set the privilege level Set User Name Default value is soluser Set User Password Default value is solpasswd You can use standard IPMI commands or the ipmitool to modify the parameters Using Standard IPMI Commands T his example shows how to set up the SOL configuration parameter with standard IPMI commands Ipmicmd is used on the local IPMC and the IP is configured ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Serial Over LAN 7 3 2 Sample Procedure To set the IP address proceed as follows 1 Establish an IPMI connection to the blade 2 Set LAN Configuration Parameter Set In Progress Lock ipmicmd k f0c110 1 smi O 3 Set LAN Configuration Parameter Set IP 172 16 10 11 on channel 1 ipmicmd k f 0 c 11 3 ac 10 Oa dd smi 0 4 Set LAN Configuration Parameter Set In Progress Commit ipmicmd k f O c 1 1 0 2 smi O Using ipmitool The example below shows how to setup a LAN configu
144. k Start Guide and Safety Notes Summary ATCA 7370 blade e Any optional items ordered 2 Check for damage and report any damage or differences to the customer service 3 Remove the desiccant bag shipped together with the blade and dispose of it according to your country s legislation The blade is thoroughly inspected before shipment If any damage occurred during transportation or any items are missing please contact our customer service immediately Environmental and Power Requirements In order to meet the environmental requirements the blade has to be tested in the system in which it is to be installed ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 45 Hardware Preparation and Installation Before you power up the blade calculate the power needed according to your combination of blade upgrades and accessories 2 2 1 Environmental Requirements The environmental conditions must be tested and proven in the shelf configuration used The conditions refer to the surrounding of the blade within the user environment Table 2 1 Environmental Requirements Requirement Temperature Operating 5 C 41 F to 40 C 104 F normal operation according to NEBS Standard GR 63 CORE 5 C 23 F to 55 C 131 F exceptional operation according to NEBS Standard GR 63 CORE Non Operating 40 C 40 F to 70 C 158 F may be further limited by installed accessories Temp Change Re
145. l Humidity 0 25 C min according to NEBS Standard GR 63 CORE 5 to 90 non condensing according to Artesyn internal environmental requirements 0 25 C min 5 to 95 non condensing according to Artesyn internal environmental requirements Vibration 0 1 g from 5 to 100 Hz and back to 5 Hz at a rate of 0 1 octave minute 5 20 Hz at 0 01 g Hz 20 200 Hz at 3 0 dB octave Random 5 20 Hz at 1 m Se Random 20 200 Hz at 3 m Sec Shock Half sine 11 m Sec 30mSec Sec Blade level packaging Half sine 6 mSec at 180 m Sec Free Fall 46 1 200 mm all edges and corners 1 0 m packaged per ETSI 300 019 2 2 blade level packaging 100 mm unpacked per GR 63 CORE ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Hardware Preparation and Installation vii The environmental requirements of the blade may be further limited down due to ew installed accessories such as hard disks with more restrictive environmental requirements Operating temperatures refer to the temperature of the air circulating around the blade and not to the actual component temperature NOTICE Blade Surface and Blade Damage High humidity and condensation on the blade surface causes short circuits Do not operate the blade outside the specified environmental limits Make sure the blade is completely dry and there is no moisture on any surface before applying power Blade Overheating and Blade D
146. lation and Use 6806800P54G 209 Supported IPMI Commands Table 8 35 Get Status Command Description continued Type Byte Data Field Bits 4 7 Clock Bus 2 Events These bits indicate pending Clock Bus 2 requests arrived from the shelf manager 0 Clock Bus 2 Query 1 Clock Bus 2 Release 2 Clock Bus 2 Force 3 Clock Bus 2 Free Bits 0 3 Clock Bus 1 Events These bits indicate pending Clock Bus 1 requests arrived from the shelf manager 0 Clock Bus 1 Query 1 Clock Bus 1 Release 2 Clock Bus 1 Force 3 Clock Bus 1 Free Bits 4 7 Reserved Bits 0 3 Clock Bus 3 Events These bits indicate pending Clock Bus 3 requests arrived from the shelf manager 0 Clock Bus 3 Query 1 Clock Bus 3 Release 2 Clock Bus 3 Force 3 Clock Bus 3 Free 210 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands 8 4 2 GetSerial Interface Properties Command The Get Serial Interface Properties command is used to get the properties of a particular serial interface Table 8 36 Get Serial Interface Properties Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Interface ID 0 Serial Debug Interface Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00
147. ld reset If a cold reset is on going a warm reset request will be ignored Table 6 53 Reset Function Register Address Offset 0x10 Description Default Access Reserved CERCLE Select the function of front board push LPC r w button payload request IPMC r 1 Warm reset 0 Cold reset ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 157 Maps and Registers Table 6 53 Reset Function Register continued Address Offset 0x10 Bit Description Select the function of IPMC reset payload request 1 Warm reset 0 Cold reset Default Access Selectthe function of RTM push button reset payload request 1 Warm reset 0 Cold reset Select the function of FPGA watchdog reset 1 Warm reset 0 Cold reset Select the function of BIOS reset payload request 1 Warm reset 0 Cold reset Select the function of OS reset payload request 1 Warm reset 0 Cold reset 6 3 12 3 IPMCReset Payload Request Register 158 IPMC software writes a magic word 0x55 into this address will launch a payload reset request If related bit in Reset Mask Register is high a warm or cold reset will occur basing on Reset Function Register bit Table 6 54 IPMC Reset Payload Request Register Address Offset Ox11 Description Default Access 7 0 Writing magic word 0x55 will cause a reset IPMC w request ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Register
148. le 6 39 Scratch Register SCR LPC IO Address Base 7 Scratch Register SCR Undefined LPC r w The scratch register is an 8 bit register that is intended for the programmer s use as a scratch pad in the sense that it temporarily holds the programmer s data without affecting any other ACE operation Programmable Baud Rate Generator The UART contains a programmable Baud Rate Generator that is capable of taking the UART_CLK input and dividing it by any divisor from 1 to 2 16 1 The output frequency of the Baud Rate Generator is 16 times the baud rate Two 8 bit latches store the divisor in a 16 bit binary format These Divisor Latches must be loaded during initialization to ensure proper operation of the Baud Rate Generator If both Divisor Latches are loaded with 0 the 16X output clock is stopped Upon loading either of the Divisor latches a 16 bit baud counter is immediately loaded This prevents long counts on initial load Access to the Divisor latch can be done with a word write The UART_CLK is the CLK UART 48MHz input divided by the pre divider set by the Super IO Configuration Register Offset 0x29 The baud rate of the data shifted in out of the UART is given by Baud Rate UART_CLK 16X Divisor For example if the pre divider is 26 the UART_CLK is 1 8461538MHz When the divisor is 12 the baud rate is 9600 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 147 Maps and Registers 6 3 6 3 1
149. ment controller If an RTM is connected to the front blade make sure that the handles of both the RTM and the front blade are closed in order to power up the blade s payload 6 Wait until the blue LED is switched off then tighten the faceplate using the handles which secures the blade to the shelf The switched off blue LED indicates that the blade s payload has been powered up and that the blade is active 7 Connect cables to the faceplate if applicable Removing the Blade This section describes how to remove the blade from an AdvancedTCA system Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten its life Before touching the blade or electronic components make sure that you are working in an ESD safe environment Blade Malfunctioning Incorrect blade installation and removal can result in blade malfunctioning When plugging the blade in or removing it do not press on the faceplate but use the handles ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 59 Hardware Preparation and Installation 60 I Removal Procedure Thefollowing procedure describes how to remove the blade from a system It assumes thatthe system is powered on If the system is not powered on you can disregards the blue LED and thus skip the respective step In that case it is a purely a mechanical procedure 1 Unlatch the lower handle by squeezing the lever and
150. ments IPMI version 1 5 e Onboard Glue Logic FPGA for IPMC extension and onboard Control register ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 37 Introduction e RTM Interface Total 36 PCI E Lanes on three Zone3 connectors 4x SAS port 1x USB interfaces PMI Management bus e BIOS Chip Up to 8MB onboard Boot and 8 MB Recovery Boot Flash SPI 1 2 Standard Compliances The product is designed to meet the following standards Table 1 1 Standard Compliances Standard Description SN29500 8 Reliability requirements MIL HDBK 217F TR NWT 000357 IEC 60068 2 1 2 3 13 14 Climatic environmental requirements The product can only be used in a restricted temperature range IEC 60068 2 27 32 35 Mechanical environmental requirements IEC 60950 1 EN 60950 1 UL CSA Safety requirements 60950 1 UL 94V 0 1 Oxygen index for PCBs Flammability below 28 38 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Introduction Table 1 1 Standard Compliances continued Standard EN 55022 EN 55024 EN 300 386 v1 4 1 2008 FCC Part 15 Subpart B ICES 003 2004 VCCI V 3 2011 04 AS NZS CISPR22 2009 ANSI IPC A 610 Rev B Class 2 ANSI IPC R 700B ANSI 001 003 ISO 8601 Description EMC requirements on system level Attention ATCA boards require CISPR 22 Class A on conducted emissions EMC immunity requirements industrial EMC for telecom equipment Manufacturing r
151. mmande 201 8 3 2 2 GetSerial Output Command 0c cece eee eee rreren rreren 201 8 3 3 OEM Set Get ACPI Power Commande 202 8 3 3 1 OEM Set ACPI Power State 0x17 0 0 ccc cece cece cece ete ee 203 8 3 3 2 OEM Get ACPI Power State 0x18 0 cece cece cece eee en ees 203 8 3 4 OEM Set Get Performance Commandes 204 8 3 4 1 OEM Set Performance Mode 0x21 0c cece cece e eee e een e eens 205 8 3 4 2 OEM Get Performance Mode 0x22 ccc cece cece ence een e eens 206 8 4 Pigeon Point Specific Commande 207 8 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Contents 8 4 1 Get Stat s Command ii isset Rer e dns 208 8 4 2 Get Serial Interface Properties Commande 211 8 4 3 Set Serial Interface Properties Commande 212 8 4 4 Get Debug Level Commande 213 8 4 5 Set Debug Level Commande 214 8 4 6 Get Hardware Address Commande 215 8 4 7 Set Hardware Address Commande 215 8 4 8 Get Handle Switch Commande 216 8 4 9 Set Handle Switch Commande 217 8 4 10 Get Payload Communication Time Out Commande 217 8 4 11 Set Payload Communication Time Out Commande 218 8 4 12 Enable Payload Control Commande 219 8 4 13 Disable Payload Control Commande 219 8 4 14 Reset IPMC Commande 220 8 4 15 Hang IPMC Commande 220 8 4 16 Graceful Reset Commande 221 8 4 17 Get Payload Shutdown Time Out Commande 222 8 4 18 Set Payload Shutdown Time Out Commande 223 8 4 19 Get Module State Commande 223 8 4 20 Enable Mo
152. n DEP Options Disabled and Enabled Default is Disabled Intel R Virtualization Technology Intel R SpeedStep tm When enabled a VMM can utilize the additional hardware capabilities Options Disabled and Enabled Default is Enabled Enable processor performance states P States Options Disabled and Enabled Default is Enabled Turbo Mode Enable Processor Turbo Mode TM must also be enabled Options Disabled and Enabled Default is Disabled ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 93 BIOS 4 2 2 3 4 2 2 4 94 Table 4 9 Processor Configuration Description continued Field Description CStates Enable processor idle power saving states C States Options Disabled and Enabled Default is Enabled Peripheral Configuration Table 4 10 lists the Peripheral Configuration options Table 4 10 Peripheral Configuration Description Spread Spectrum Clock Enable Disable Spread Spectrum Options Disabled and Enabled Default is Enabled RTM power policy Select RTM power policy Disable for RTM as an independent FRU or enable for RTM Activate Deactivate with front board Options Disabled and Enabled Default is Disabled HDD Configuration Table 4 11 lists the HDD Configuration options Table 4 11 HDD Configuration Description Description SATA Interface Combination Selectthe SATA controllers operation mode Options IDE and AHCI Default is AH
153. n or it may even be significantly lower There is also a dependency on the batch variance of the major components like the processor and DIMMs used Hence Artesyn does not represent or warrant that measurement results of a specific board provide guaranteed maximum values for a series of boards Note This power requirement is under room temperature 25 C ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Hardware Preparation and Installation 2 3 Blade layout Figure 2 2 Blade Layout Note On the single processor variant the processor and its DIMM sockets are populated on the upper side of the board Components associated with the second processor are not populated on this product variant ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 51 Hardware Preparation and Installation 2 4 2 4 1 52 Installing the Blade Accessories The following additional components are available for the blade e DIMM memory modules e Cave Creek module They are described in detail in the following sections For order numbers refer to section Ordering Information on page 43 DIMM Memory Modules The blade provides eight memory slots for main memory DIMM modules You may install and or remove DIMM memory modules in orderto adaptthe main memory sizeto your needs The corresponding installation removal procedures are described in this section The location of the DIMM Memory Modules are shown in Figure Blade Layout
154. n and Use 6806800P54G Maps and Registers Ox1B BitDescriptionDefaultAccess 7 0High byte of timeout threshold for FPGA Payload Watchdog unit is one msecOxFFLPC r w 6 3 12 13 FPGA Payload Watchdog Clear Register Any write done by the payload software to this register will be treated as feed and restarts the FPGA Payload Watchdog Table 6 64 FPGA Payload Watchdog Clear Register Address Offset Ox1C Writing any data will clear the FPGA Payload LPC w Watchdog 6 3 12 14 FPGA IPMC Watchdog Threshold Register The FPGA has an internal watchdog which monitors how the IPMC is normally running If the IPMC fails to feed the FPGA according to the time set by this register the latter will issue a cold reset to the former Payload will not be affected by the reset of the IPMC The IPMC software writes this register to set the timeout threshold of the FPGA IPMC Watchdog Unit is one second maximum time is 255s When 0 is written to it the watchdog will be disabled and will never bite Writing and other data will enable and restart the FPGA IPMC Watchdog Table 6 65 FPGA IPMC Watchdog Threshold Register Address Offset Ox1F Timeout threshold the FPGA IPMC IPMC r w Watchdog unit is one second ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 165 Maps and Registers 6 3 13 Flash Control Register Table 6 66 Flash Control Register Address Offset 0x40 0 Inverted of DEF SPI WP
155. n if their setting is changed Therefore do not change settings of switches marked as reserved The setting of switches which are not marked as reserved has to be checked and changed before blade installation Blade Damage Setting resetting the switches during operation can cause blade damage Therefore check and change switch settings before you install the blade Blade Damage Wrong battery installation may result in hazardous explosion and blade damage Therefore always use the same type of Lithium battery as is installed and make sure the battery is installed as described in this manual Environment Always dispose of used blades system components and RTMs according to your country s legislation and manufacturer s instructions ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 29 Safety Notes me TTT 30 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Sicherheitshinweise EN Dieses Kapitel enth lt Hinweise die potentiell gef hrlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind Beachten Sie unbedingt in allen Phasen des Betriebs der Wartung und der Reparatur des Systems die Anweisungen die in diesen Hinweisen enthalten sind Sie sollten au erdem alle anderen Vorsichtsma nahmen treffen die f r den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind Wenn Sie diese Vorsichtsma nahmen oder Sicherheitshinweise die an anderer Stelle diese Handbuchs enthalten sind n
156. nd with parameter selector of 100 the Set Selector and the Block Selector have a specific meaning Details are given in System Boot Options Parameter 100 on page 188 for details The following table lists which boot properties can be configured and the corresponding boot parameter number Table 8 8 Configurable System Boot Option Parameters Configurable Boot Property Corresponding Boot Parameter Number Selection between BIOS and FPGA boot 96 POST Type 97 Timeout for graceful shutdown 98 BIOS boot parameters 100 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 185 Supported IPMI Commands 8 1 7 1 1 System Boot Options Parameter 96 This boot parameter is an Artesyn specific OEM boot parameter as defined in the following table Table 8 9 System Boot Options Parameter 96 1 1 Bits 7 2 Reserved Bit 1 FPGA configuration stream load 0 Load configuration stream from default boot flash 1 Load configuration stream from backup boot flash Note The new FPGA configuration stream is loaded into the FPGA at the next power cycle of the payload Bit 0 Default backup boot flash selection 0 Boot from default boot flash 1 Boot from backup boot flash Note the newly selected boot flash is connected to the payload immediately which means writing to the flash is possible Its image is executed after the next power up or cold reset of the payload The System Boot Options parameter 96 is non volatile It s
157. ndicated to the CPU as soon as it happens The character in the shift register is overwritten but it is not transferred to the FIFO 1 Overrun error occurred 0 No overrun error ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 141 Maps and Registers Table 6 37 Line Status Register LSR continued LPC IO Address Base 5 Bit 2 Description Parity Error PE indicator When PE is set it indicates that the parity of the received data character does not match the parity selected in the LCR bit 4 PE is cleared every time the CPU reads the contents of the LSR In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the CPU when its associated character is at the top of the FIFO 1 Parity error occurred 0 No parity error Default Access 0 LPC r Framing Error FE indicator When FE is set it indicates that the received character did not have a valid set stop bit FEis cleared every time the CPU reads the contents of the LSR In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the CPU when its associated character is at the top of the FIFO The ACE tries to resynchronize after a framing error To accomplish this it is assumed that the framing error is due to the next start bit The ACE samples this start bit twice and then accep
158. nsor Type Type Byte 1 Event Data Byte 2 Event Data Byte3 Description Deassertion Rearm 34 Bootlnited System Sensor 0x0 OxFF OxFF 0x0 Initiated by Asrt Auto Boot specific 0x1 power up Initiated discrete 0x2 0x1 Initiated by 0x1D Ox6F 0x3 hard E 0x4 0x2 Initiated by warm reset 0x3 User requested PXE boot 0x4 Automatic boot to diagnostic 35 POST Code OEM Sensor 0x0 OxFF Reading according 0x0 BIOS POST Asrt Auto 0xD1 specific 0x1 to EFI BIOS port80 Code discrete 0x2 status codes 0x3 209 Ox6F 0x3 0x4 OEM 0x4 0xD1 0x5 0x6 OxFF 0x6 0x7 Reading 0x7 according to EFI BIOS port80 status codes 238 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G FRU Information and Sensor Data Records Table 9 3 Sensor Data Records continued Event Sensor Event Reading Data Event Threshold Assertion Number Sensor Name Sensor Type Type Byte 1 Event Data Byte 2 Event Data Byte 3 Description Deassertion Rearm 36 IPMC Status OEM Sensor 0x0 0x0 Watchdog Auto 0xD5 specific 0x1 Reset discrete 0x2 0x1 Software Ox6F 0x3 Reset 0x4 0x2 Power Failure 0x3 Hard Boot ae 0x4 Cold B 0x6 x4 Cold Boot 0x5 Warm Boot 0x6 Reserved 37 Power Good Power Sensor 0x0 See IPMI Spec OxFF 0x0 Presence Asrt Auto Supply specific 0x1 detected 0x08 discrete 0x1 Power Supply Ox6F Failure detected 38 Boot Bank OEM Sensor 0x0 OxFF OxFF 0x0 BootBankA Asrt Auto 0xD2 specific discrete Ox6F
159. oard However the ATCA 7370 board family also supports upgrade of the firmware with the HPM 1 specification Upgradable components of the board include the BIOS flash FPGA flash and IPMC flash For update it is recommended to use the Pigeon Point System modified Ipmitool Installing the ipmitool Refer Installing the ipmitool on page 175 for installing the ipmitool procedure Update Procedure The Ipmitool HPM update requires two steps for an update 1 Upgrade the component Example ipmitool hpm upgrade lt file gt 2 Activate the component Example ipmitool hpm activate Both steps can also be integrated into one command ipmitool hpm upgrade file activate Interface The HPM 1 upgrade supports three different interfaces for upgrading the firmware These are KCS IPMB 0 and LAN over BASE The LAN interface is only supported when the payload is powered on M4 The BASE Ethernet controller also has to be powered on for this feature ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 241 Firmware Upgrade 10 1 3 1 10 1 3 2 10 1 3 3 242 KCS Interface The standard way to upgrade the firmware of the payload is through the KCS interface Upgrade through this interface is the fastest HPM 1 upgrade The images and the ipmitool need to be on the payload to be upgraded Example Prompt gt ipmitool hpm upgrade file IPMB 0 This interface represents the backplane IPMI bus and allows remote firmware
160. oduce a receiver line status interrupt when any of the corresponding conditions are detected and the interrupt is enabled These bits are not cleared by reading the erroneous byte from the FIFO or receive buffer 140 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers They are cleared only by reading LSR In FIFO mode the line status interrupt occurs only when the erroneous byte is at the top of the FIFO If the erroneous byte being received is not at the top ofthe FIFO an interrupt is generated only after the previous bytes are read and the erroneous byte is moved to the top of the FIFO Table 6 37 Line Status Register LSR LPC IO Address Base 5 Bit Description Default Access 0 Receiver data ready DR indicator 0 LPC r DR is set whenever a complete incoming character has been received and transferred into the RBR or the FIFO DR is cleared by reading all of the data in the RBR or the FIFO 1 New data received 0 No new data 1 Overrun error OE indicator 0 LPC r When OE is set it indicates that before the character in the RBR was read it was overwritten by the next character transferred into the register OE is cleared every time the CPU reads the contents of the LSR If the FIFO mode data continues to fill the FIFO beyond the trigger level an overrun error occurs only after the FIFO is full and the next character has been completely received in the shift register An overrun error is i
161. omputing Multi record info area PICMG Blade Point To This multi record area contains the Point Connectivity ATCA blade Point to Point Record Area Connectivity Record according to PICMG 3 0 Rev 1 0 Carrier information Defined by AMC 0 R2 0 Spec Record PICMG Carrier Activation Defined by AMC O R2 0 Spec and Current Management PICMG Carrier Point to Defined by AMC 0 R2 0 Spec Point Connectivity Record PICMG AMC Point to Defined by AMC 0 R2 0 Spec Point Connectivity ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 227 FRU Information and Sensor Data Records 9 2 228 Table 9 1 FRU Information continued Area Description Value Access OEM MAC Address r Record Power Configuration Table 9 2 Power Configuration Dynamic power While the blade is powered it reconfiguration support supports only one power level Dynamic power configuration The power level is fixed and does not change Number of power draw levels The amount of possible power levels Early Power Draw Levels Watt Complete early power level including IPMC Steady state Power Draw Levels Complete steady power Watt consumption including IPMC Transition from early to steady 0s levels sec ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G FRU Information and Sensor Data Records Thefollowing figure shows the locations of all temperature sensors available on board Figure9 1
162. ontrols Indicators and Connectors 3 3 2 FPGA Switch Table 3 12 Switch SW1 Setting Default Switch Function Manual power enable of Payload of front board OFF IPMC control payload power ON force payload power on when the board get inserted Note The S7 1 should also be ON in order to force the payload power on No definition No definition Table 3 13 Switch S7 Setting Switch Function Default ON Reset IPMC OFF IPMC operates normally Note when forcing board power on ordownloading FPGA through cable the IPMC should be in reset state S7 2 FPGA image flash BANK selection OFF when using cable to download FPGA image ON select recovery BANK U150 OFF select default BANK U151 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 73 Controls Indicators and Connectors eee TTT 74 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G BIOS EE 4 1 Features TheBasic Input Output System BIOS provides an interface between the operating system and the hardware of the blade It is used for hardware configuration Before loading the operating system BIOS performs basic hardware test known as power on self tests POST and prepares the blade for the initial boot up procedure During blade production identical BIOS images are programmed into both boot flash banks It is possible to select boot flash as device to boot from This is done via an IPMI comman
163. or noisy lines may require lower speeds Options 9600 19200 38400 57600 and 115200 Default is 9600 Front Network Boot Controls execution of the Option ROM forthe Front Panel Ethernet controller Options Disabled and Enabled Default is Disabled ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 91 BIOS Table 4 8 Boot Configuration Description continued Field Description Base Network Boot Controls execution of the Option ROM for the Base Ethernet controller Options Disabled and Enabled Default is Enabled Fabric Network Boot Controls execution of the Option ROM for the Fabric Interface Ethernet Options Disabled and Enabled Default is Disabled ARTM Network Boot Controls execution of the Option ROM for the Ethernet on the ARTM Options Disabled and Enabled Default is Disabled ARTM SAS Boot Controls execution of the Option ROM for the SAS controller on the ARTM Options Disabled and Enabled Default is Enabled Boot from USB Devices Enable or Disable booting from USB Devices Options Disabled and Enabled Default is Enabled BIOS Watchdog Enable or Disable BIOS POST Watchdog Options Disabled and Enabled Default is Enabled BIOS Watchdog Timeout Choose Timeout value for BIOS POST Watchdog Expiration value It is not available if the BIOS Watchdog is disabled Range 180 6000 Default is 180 O S Boot Watchdog Enable or Disable O S Watchdog Timer It
164. ot remove equipment covers Only factory authorized service personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not install substitute parts or perform any unauthorized modification of the equipment or the warranty may be voided Contact your local Artesyn representative for service and repair to make sure that all safety features are maintained The blade has been tested in a standard Artesyn system and found to comply with the limits for a Class A digital device in this system pursuant to part 15 of the FCC Rules EN 55022 Class A respectively These limits are designed to provide reasonable protection against harmful interference when the system is operated in a commercial environment ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 25 Safety Notes This is a Class A product based on the standard of the Voluntary Control Council for Interference by Information Technology Interference VCCI If this equipment is used in a domestic environment radio disturbance may arise When such trouble occurs the user may be required to take corrective actions The blade generates and uses radio frequency energy and if not installed properly and used in accordance with this guide may cause harmful interference to radio communications Operating the system in a residential area is likely to cause harmful interference in which case the user
165. ows e Attached USB CD ROM e Attached USB devices on the external USB port e SAS HDD e SATAHDD e Base Ethernet Interfaces If BIOS does not find any ready bootable device it will loop on the source list until a boot device becomes ready After 10 loops the BIOS initiates a cold reset and retries again or when configured the BMC watchdog bites BIOS organizes the devices in groups CD ROM HDD network floppy SAS HDD Any device can be set as the first boot device by raising it to the first boot device of its device group then raising that group to the first boot group The boot order for a certain device and its device group can be set even in the absence of that device The order is preserved When the device is added later it will be available at the specified boot order Boot Support for the SAS Controller The BIOS contains an option ROM SAS controller on the payload Legacy boot from SAS HDDs is supported ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G BIOS 4 1 6 2 The ATCA 7370 supports four SAS ports Two local SAS ports are located in the RTM module the other two SAS ports are connected to the external ports of the RTM The SAS physical port number is assigned as follows e PO0 LocalSAS 1 which is far from RTM zone 3 connector e P1 Local SAS 2 which is near from RTM zone 3 connector e P2 External SAS 1 e P3 External SAS 2 The BIOS and Linux follow the SAS port physical number to assign sequence
166. ponse Data Completion Code Generic plus the following command specific completion codes 80h feature selector not supported Artesyn IANA Number 0065CDh LSB first Feature Configuration Persistency Duration Table 8 23 Feature Selector Assignments Boot Firmware Automatic Switchover Function Enable Disable Serial Output Commands Table 8 24 Serial Output Commands Command Name NetFn Request Response CMD Description Set Serial Output Ox2E Ox2F See Set Serial Output Command on page 201 Get Serial Output Ox2E Ox2F 0x16 See Get Serial Output Command on page 201 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands 8 3 2 1 Set Serial Output Command The Set Serial Output command selects the serial port output source for a serial port connector The following table lists the request and response data applicable to the Set Serial Output command Table 8 25 Set Serial Output Command Byte Data Field Request Data 1 3 Artesyn IANA Number 0065CDh LSB first 4 Serial connector type 0 Front panel connector 1 Backplane connector All other values are reserved 5 Serial connector instance number a value of 00h shall be used all other values are reserved 6 Serial output selector 0 payload interface 2 IPMC debug console All other values are reserved Response Data 1 Completion code 2 4 Artesyn IANA Number 0065CDh LSB first
167. ration parameter for a potential SOL session with ipmitool for base 1 channel 1 n0s70 ipmitool lan set 1 ipaddr 172 16 0 221 Setting LAN IP Address to 172 16 0 221 n0s70 4 The following example shows how to query the LAN parameters that are currently in use for a potential SOL session for base 1 channel 1 and base 2 channel 2 root localhost ipmitool lan print 1 Set in Progress Set Complete Auth Type Support Auth Type Enable Callback User Operator Admin ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 177 Serial Over LAN 178 OEM IP Address Source Unspecified IP Address f 1 72 16 0 221 Subnet Mask 2 2554 255 0 0 MAC Address 00 00 00 00 00 00 Default Gateway IP t 172 164 0 1 Default Gateway MAC 00 00 00 00 00 00 RMCP Cipher Suites S 152 373 Cipher Suite Priv Max Not Available root localhost ipmitool lan print 2 Set in Progress Set Complete Auth Type Support Auth Type Enable Callback User Operator Admin OEM IP Address Source Unspecified IP Address GE 2 20 Subnet Mask 255 255 0 0 MAC Address 00 00 00 00 00 00 Default Gateway IP 172 17 0 41 Default Gateway MAC 00 00 00 00 00 00 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Serial Over LAN 7 4 RMCP Cipher Suites gt 152 353 Cipher Suite Priv Max Not Available root localhost MAC Address 00 00 00 00 00 00 means the address is shared between base and SOL interface
168. rovides the German translation ofthe safety notes section Introduction on page 37 describes the main features of the blade Hardware Preparation and Installation on page 45 outlines the installation requirements hardware accessories switch settings installation and removal procedures Controls Indicators and Connectors on page 61 describes external interfaces of the blade This includes connectors and LEDs BIOS on page 75 describes the features and setup of BIOS Functional Description on page 103 describes the functional blocks of the blade in detail This includes a block diagram description of the main components used and so on Maps and Registers on page 113 provides information on the blade s maps and registers Serial Over LAN on page 175 provides information on how to establish a serial over LAN session on your blade Supported IPMI Commands on page 181 lists all supported IPMI commands FRU Information and Sensor Data Records on page 227 provides information on the blade s FRU information and sensor data Troubleshooting on page 247 lists the errors and describes the reasons and solutions to the problems Related Documentation on page 249 provides links to further blade related documentation ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 19 About this Manual Abbreviations 20 This document uses the following abbreviations Abbreviation Definition ATCA BBS Advanced Telecom Computing Arc
169. rred RTM push button reset request LPC r w1c 1 Reset occurred FPGA Watchdog reset payload request LPC r w1c 1 Reset occurred 6 BIOS reset payload request 0 LPC r w1c 1 Reset occurred 7 OS reset payload request 0 LPC r w1c 1 Reset occurred 6 3 12 8 Payload Reset Source for OS Register The OS Reset Source Register stores the source of the most recent reset as it is done in the BIOS Reset Source Register A one in the register bit indicates that the associated reset has occurred If more than one reset occurs from different sources without clearing the corresponding register bits one can not determine the most recent reset source since more than one bit will be set The same situation will happen if two reset sources go active at the same time ATCA 7370 ATCA 7370 S Installation and Use 6806800P54C 161 Maps and Registers Note BIOS should never write to this register Table 6 59 Payload Reset Source for OS Register Address Offset 0x16 Payload Power on reset RST N 1 LPC r wic 1 Reset occurred Reserved mn Juenwic pc die c m board Co __ button reset payload NC r wic request 1 Reset occurred IPMC reset payload request ME r wic 1 Reset occurred RTM push button reset payload request weg r wic 1 Reset occurred FPGA Watchdog reset payload request LPC r w1c 1 Reset occurred 6 BIOS reset payload request 0 LPC r w1c 1 Reset occurred 7 OS reset payload
170. rs Table 6 2 Non APIC PIC mode 8259 Mode Interrupt Mapping 8259IRQ Typical Interrupt Source Interrupt Source SATA Primary legacy mode or via SERIRQ or PIRQ 15 SATA SATA Secondary legacy mode or via SERIRQ or PIRQ 6 1 2 116 IRQO 1 2 8 and 13 must not be used for PCI interrupts external inputs PIRQ A H which are only reserved for future usage routing If an interrupt is used for PCI IRQ A H SCI or TCO it must not be used for ISA legacy style interrupts via SERIRQ In PIC Mode 8259 mode PCI interrupts are mapped to IRQ3 7 9 12 14 or 15 If IRQ11 is used for Timer 2 software must ensure IRQ11 is not shared with any other devices to guarantee the proper operation of Timer 2 The chipset does not prevent the sharing of IRQ11 Interrupts can individually be programmed to be edge or level except for IRQO IRQ2 IRQ8 and IRQ13 APIC D31 F0 Interrupt Mapping Table 6 3 APIC Mode Interrupt Mapping IRQ Interrupt Source Notes 0 Cascade from 8259 1 1 2 8254 Counter 0 Timer 0 legacy mode 3 4 5 6 7 8 RTC Timer 1 legacy mode ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers Table 6 3 APIC Mode Interrupt Mapping continued IRQ Interrupt Source Notes 9 Option for TCI TCO 10 Option for TCI TCO 11 Timer 2 Option for TCI TCO 12 Timer 3 13 FERR logic 14 SATA Primary legacy mode 15 SAT
171. rt A IPMC IMC PD1 IPMB Data Port A IPMC ISC PC5 IPMB Clock Port B IPMC ISC PC4 IPMB Data Port B 17 24 Not used Not used 25 Shelf Ground Shelf Ground 26 Logic Ground Logic Ground 27 Power Building Block Enable B ATCA 7370 ATCA 7370 S Installation and Use 6806800P54C 65 Controls Indicators and Connectors Table 3 4 Zone 1 Connector P1 Pin Assignment Contact Number Destination Description Power Building Block Voltage Return A Power Building Block Voltage Return B Power Building Block Early 48V A Early 48V B Power Building Block Enable A 48V A 48V B Power Building Block Power Building Block Power Building Block Table 3 5 Zone 2 Connector J20 Pin Assignment J20 Backplane Clock CLK1A CLK1A CLK1B CLK1B CLK2A CLK2A 2 Update Channel SAS UPD_P4_T UPD_P4_T UPD_P4_R UPD_P4_R amp GE Redundancy X X X X UPD_P2_T UPD_P2_T UPD_P2_R UPD_P2_R UPD_P3_T UPD_P3_T UPD_P3_R UPD_P3_R X X X X X X X X UPD_GE_T UPD_GE_ UPD GE UPD GER UPD P1 T UPD_PI_T UPD_PI_R UPD_PI_R X TX RX X X X X X 5 LA 7 LL 9 10 Table 3 6 Zone 2 Connector J23 Pin Assignment Row 1 66 Interface Fabric Channel 2 Col AB LoT T 123 Col CD Col EF Col GH PL prese nns nrc recs mcs rms mms nme ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Controls
172. rted FRU Inventory Commande 183 Table 8 6 Supported Sensor Device Commande 184 Table 8 7 Supported Chassis Device Commande 184 Table 8 8 Configurable System Boot Option Parameters 185 Table 8 9 System Boot Options Parameter 96 186 Table 8 10 System Boot Options Parameter A0 187 Table 8 11 System Boot Options Parameter 98 188 Table 8 12 System Boot Options Parameter 100 Data Format 0 eee ee eee eee 190 Table 8 13 System Boot Options Parameter 100 SET Command Usage 190 Table 8 14 System Boot Options Parameter 100 GET Command Usage 191 Table 8 15 System Boot Options Parameter 100 Supported Parameters 193 Table 8 16 boot order Devices u upset me Eee ab Rm eg E Ress ENEE 194 Table 8 17 Supported Event Commande 195 Table 8 18 Supported LAN Device Commande 195 Table 8 19 Supported PICMG 3 0 Commands ssssssseeseeee nenn 196 Table 8 20 Set Get Feature Configuration Commande 198 Table 8 21 Set Feature Configuration Commande 199 Table 8 22 Get Feature Configuration Commande 199 Table 8 23 Feature Selector Assignments 00 2 c cece eee c ett e cence en nennen 200 Table 8 24 Serial Output Commande 200 Table 8 25 Set Serial Output Commande 201 Table 8 26 Get Serial Output Commande 202 Table 8 27 OME Set Get ACPI Power Commande 202 Table 8 28 OEM Set ACPI Power State Commande 203 Table 8 29 OEM Get ACPI Power State Comm
173. s 6 3 12 4 6 3 12 5 BIOS Reset Payload Request Register When the BIOS software writes 0xA5 to this address it will launch a payload request reset If the related bit in the reset mark register is high either a warm or cold reset will occur based on the reset function register bit Table 6 55 BIOS Reset Payload Request Register Address Offset 0x12 Writing magic word 0xA5 will causeareset LPC w request OS Reset Payload Request Register The OS software writes 0x5A to this address and launches a payload reset request If the related bit in Reset Mask Register is high a warm o cold reset will occur based on the reset function register bit Table 6 56 OS Reset Payload Request Register Address Offset 0x13 Description Default Access 7 0 Writing magic word 0x5A will cause a reset LPC w request ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 159 Maps and Registers 6 3 12 6 Payload Reset Source for IPMC Register The IPMC Reset Source Register stores the source of the most recent reset A one in the register bit indicates that the associated reset has occurred If more than one reset occurs from different sources without clearing the corresponding register bits one cannot determine the most recent reset source since more than one bit will be set The same situation will occur is two reset sources are active at the same time Table 6 57 Payload Reset Source for IPMC Register Addr
174. sary upgraded through the IPMC The IPMC features Serial over LAN SOL for the payload CPU serial console The SOL interface is available via the ATCA Base I F SOL is activated by specific IPMI commands Serial Redirection The CPU serial redirection reroutes the console input and output that is the text output to the text screen and input from the standard keyboard Typically the console is used by the BIOS setup menus BIOS initialization and boot routines OS boot loaders and loaded OS The serial console of the payload CPU is available via SOL In addition to the SOL capability the serial console is also available on the blade faceplate using a RJ45 connector with Cisco pin out If a SOL session is established only the output is available on the faceplate Input is not possible during this time via the faceplate Alternatively to the CPU serial console the IPMC serial console is also available on the faceplate serial connector It can be selected via specific IPMI OEM command Real Time Clock An external 32 768 kHz crystal sources the internal real time clock inside C604 chipset with a frequency tolerance of 20 PPM The RTC is fully DS1287 MC14618 PC87911 and Y2K compliant and provides 256 bytes of backed up CMOS RAM of which 14 bytes containing the RTCtime and date info and RTC configuration The default power down backup method uses a Super CAP with a 1 Farad capacity Serial ATA Intel C604 chipset includes a six port serial
175. se Number A value of CDh shall be used 2nd byte of Artesyn IANA Enterprise Number A value of 65h shall be used MSB of Artesyn IANA Enterprise Number A value of 00h shall be used ACPI System Power State to set Power states are mutually exclusive Only one state can be set at atime 7 1b set system power state always with 1 6 1 Reserved 0 System Power State enumeration 00h set SO working 01h set S3 typically equates to suspend to RAM Response Data Completion Code Generic completion codes LSB of Artesyn IANA Enterprise Number A value of CDh shall be used 2nd byte of Artesyn IANA Enterprise Number A value of 65h shall be used MSB of Artesyn IANA Enterprise Number A value of 00h shall be used 8 3 3 2 OEM Get ACPI Power State 0x18 This command can be used to retrieve current ACPI power state ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 203 Supported IPMI Commands Table 8 29 OEM Get ACPI Power State Command Request Data 1 LSB of Artesyn IANA Enterprise Number A value of CDh shall be used 2 2nd byte of Artesyn IANA Enterprise Number A value of 65h shall be used 3 MSB of Artesyn IANA Enterprise Number A value of 00h shall be used 2 LSB of Artesyn IANA Enterprise Number A value of CDh shall be used 3 2nd byte of Artesyn IANA Enterprise Number A value of 65h shall be used BEE MSB of Artesyn IANA Enterprise Number A value of 00h
176. set Source for IPMC Register 160 Table 6 58 Payload Reset Source for BIOS Register 161 Table 6 59 Payload Reset Source for OS Register 0 eee cece cece eee eee nennen 162 Table 6 60 IPMC Watchdog Timeout Register 163 Table 6 61 IPMC Watchdog Timeout for BIOS Register 163 Table 6 62 IPMC Watchdog Timeout for OS Register 164 Table 6 63 FPGA Payload Watchdog Threshold Low byte Register 164 Table 6 64 FPGA Payload Watchdog Clear Register 165 Table 6 65 FPGA IPMC Watchdog Threshold Register 165 Table 6 66 Flash Control REGISEED vu une ne NEEN 166 Table 6 67 RTM Status and Control Register 0 eee e cece e eee eee eee nennen 166 Table 6 68 User LED Status and Control Register 167 Table 6 69 User LED Status and Control Register 168 Table 6 70 Miscellaneous Status and Control Register 169 Table 6 71 Debug Switch and LED Status Register 169 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 13 List of Tables Table 6 72 LPC Scratch Registers us ee e dE 170 Table 6 73 POST Code Register ceret ee a 170 Table 6 74 Comiporient Status Cod s uns es CHER ERR ERE 170 Table 6 75 Progress Status Code 173 Table 6 76 Architectural Status Codes 174 Table 7 1 SOL Pardmeters EE 176 Table 8 1 Supported Global IPMI Commande 181 Table 8 2 Supported System Interface Commande 181 Table 8 3 Supported Watchdog Commande 182 Table 8 4 Supported SEL Device Commande 183 Table 8 5 Suppo
177. shall be used 2nd byte of NSN IANA Enterprise Number A value of 6Fh shall be used MSB of NSN IANA Enterprise Number A value of 00h shall be used ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 205 Supported IPMI Commands 8 3 4 2 OEM Get Performance Mode 0x22 This command can be used to retrieve current performance mode Table 8 32 OEM Get Performance Mode Command Data Field LSB of NSN IANA Enterprise Number A value of 2Ah shall be used 2nd byte of NSN IANA Enterprise Number A value of 6Fh shall be used MSB of NSN IANA Enterprise Number A value of 00h shall be used 00h OFh FRU ID Oh for ACPI5 A Request Data Response Data Completion Code LSB of NSN IANA Enterprise Number A value of 2Ah shall be used 2nd byte of NSN IANA Enterprise Number A value of 6Fh shall be used MSB of NSN IANA Enterprise Number A value of 00h shall be used Power performance mode 7 1 Reserved 0 Power State Mode Level Oh normal performance mode 1h reduced performance mode Power draw value of reduced performance mode the unit is watt LS byte first Power draw value of normal performance mode the unit is watt LS byte first 206 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 8 4 Supported IPMI Commands Pigeon Point Specific Commands The IPMC supports additional IPMI commands that are specific to Pigeon Point This sec
178. ssible only when the device is in the Configuration state Table 6 18 Logical Device Configuration Register Summary Enable Base IO Address MSB Base IO Address LSB Primary Interrupt Select ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 127 Maps and Registers 128 Table 6 18 Logical Device Configuration Register Summary continued Index Address Description The logical register addresses are shown in the tables below Table 6 19 Logical Device Enable Register Index Address 0x30 Bit Description Default Access 0 Logical Device Enable 1 LPC r w 0 disabled Currently selected device is inactive 1 enabled The currently selected device is enabled 7 1 Reserved 0 LPC r Table 6 20 Logical Device Base IO Address MSB Register Index Address 0x60 Logical Device Base IO Address MSB In LPC rjw Table 6 21 Logical Device Base IO Address LSB Register Index Address 0x61 Description Default Access 2 0 Bits 0 to 2 are read only Decode is on 8 Byte LPC r boundary Logical Device Base IO Address LSB Bits 3 to EE LPC r w 7 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers Registers 0x60 MSB and 0x61 LSB set the Logical Device Base IO for this logical device For example for Base IO address Ox3F8 the content of Register 0x60 is 0x03 and the content of Register Ox61is OxF8 See table below for Common Decode Rang
179. ster 168 Table 6 69 User LED Status and Control Register Address Offset 0x57 Control user LED 3 green color output Signal LED USER3 GRN N 0 LED_USER3_GRN_N is driven high 1 LED_USER3_GRN_N is driven low Control user LED 3 red color output Signal LED_USER3_RED_N 0 LED_USER3_RED_N is driven high 1 LED_USER3_RED_N is driven low Control user LED 1 red color output Signal LED_USER1_RED_N 0 LED_USER1_RED_N is driven high 1 LED_USER1_RED_N is driven low Control user LED 2 red color output Signal LED_USER2_RED_N 0 LED_USER2_RED_N is driven high 1 LED_USER2_RED_N is driven low 0 LPC r w IPMC r Control BI LED enable output Signal LED BL ENN 0 LED BI EN Nis driven high 1 LED BI EN Nis driven low 7 5 Reserved 000 r ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 6 3 17 6 3 18 Maps and Registers Miscellaneous Status and Control Register The Miscellaneous register provides the status of hardware signals for IPMC to monitor like the occupation status of both CPU sockets Table 6 70 Miscellaneous Status and Control Register Address Offset 0x58 Bit Description Default Access CPU SKTOCC N 1 0 Ext CPU IVY N Ext PCH HOT N Ext Reserved 0 IPMC to payload NMI request 1 NMI active 0 NMI inactive Note FPGA_PCH GPIO3 signal will also be controlled by warm reset procedure Debug Switch and LE
180. system as described in Installing and Removing the Blade on page 57 Figure 2 4 Cave Creek Module Installation Cave Creek Module Removal To remove the Cave Creek module 1 Remove the blade from the system as described in Installing and Removing the Blade on page 57 2 Remove the four screws that holds the Cave Creek module 56 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Hardware Preparation and Installation 2 5 2 5 1 3 Remove the Cave Creek module from the blade 4 Reinstall the blade into the system as described in Installing and Removing the Blade on page 57 Installing and Removing the Blade The blade is fully compatible to the AdvancedTCA standard and is designed to be used in AdvancedTCA shelves The blade can be installed in any AdvancedTCA node slot Do not install it in an AdvancedTCA hub slot NOTICE Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten its life Before touching the blade or electronic components make sure that you are working in an ESD safe environment Blade Malfunctioning Incorrect blade installation and removal can result in blade malfunctioning When plugging the blade in or removing it do not press on the faceplate but use the handles Installing the Blade To install the blade into an AdvancedTCA shelf proceed as follows ATCA 7370 ATCA 7370 S Installation and Use 6806800P54C 5
181. t swap handle of the IPMC Overriding of the handle switch state is allowed only if the IPMC operates in manual standalone mode for a description refer to Table 8 34 Table 8 42 Get Handle Switch Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 1 Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Handle Switch Status 0x00 The handle switch is open 0x01 The handle switch is closed 0x02 The handle switch state is read from hardware ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands 8 4 9 Set Handle Switch Command The Set Handle Switch command sets the state of the hot swap handle switch in manual standalone mode for a description refer to Table 8 34 Table 8 43 Set Handle Switch Command Description Type Request Data Byte Data Field PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 OA byte 2 40 byte 3 00 Handle Switch Status 0x00 The handle switch is open 0x01 The handle switch is closed 0x02 The handle switch state is read from hardware Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first
182. ted Not supported ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 145 Maps and Registers Table 6 38 Modem Status Register MSR continued LPC IO Address Base 6 Bit Description Default Access Change in data carrier detect DDCD indicator DDCD indicates that the DCD input to the chip has changed state since the last time it was read by the CPU When DDCD is set and the modem status interrupt is enabled a modem status interrupt is generated Not supported Complement of the clear to send CTS input When the Asynchronous Communications Element ACE is in diagnostic test mode LOOP MCR4 1 this bit is equal to the MCR bit 1 RTS Complement of the data set ready DSR input When the ACE is in the diagnostic test mode LOOP MCR4 1 this bit is equal to the MCR bit 0 DTR Complement of the ring indicator RI input When the ACE is in the diagnostic test mode LOOP MCR4 1 this bit is equal to the MCR bit 2 OUT1 Not supported Complement of the data carrier detect DCD input When the ACE is in the diagnostic test mode LOOP MCR4 1 this bit is equal to the MCR bit 3 OUT2 Not supported 146 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers 6 2 5 10 Scratch Register SCR 6 2 6 This 8 bit read write register has no effect on the UART It is intended as a scratchpad register for use by the programmer Tab
183. tesyn to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to an Artesyn website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Artesyn It is possible that this publication may contain reference to or information about Artesyn products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Artesyn intends to announce such Artesyn products programming or services in your country Limited and Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Artesyn Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Contact Address Artesyn Embedded Technologies Artesyn Embedded Technologies Marketing Communications Lilienthalstr 17 19 2900 S Diablo Way Suite 190 85579 Neubiberg Munich Tempe Arizona 85282 Germany Contents E About this Man
184. the latch together and turning the handle outward just enough to unlatch the handle from the faceplate Do not rotate the handle fully outward The blue LED blinks indicating that the blade power down process is ongoing 2 Wait until the blue LED is illuminated permanently then unlatch the upper handle and rotate both handles fully outward If the LED continues to blink a possible reason may be that the upper layer software rejected the blade extraction request Data Loss Removing the blade with the blue LED still blinking causes data loss Wait until the blue LED is permanently illuminated before removing the blade 3 Remove the faceplate cables if applicable 4 Rotate handle of the faceplate until the blade is detached from the shelf 5 Remove the blade from the shelf ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Chapter 3 Controls Indicators and Connectors EEUU 3 1 Faceplate Figure 3 1 shows the connectors keys and LEDs available at the Faceplate The blade design provides the possibility to cover unused faceplate elements like LEDs or push buttons behind a custom overlay foil 3 13 1 LEDs and Interfaces The blade s faceplate provides the following interfaces and control elements e Two USB 2 0 ports Serial console port to connect to either payload or IPMC serial I F e Out of Service In Service Attention User U1 U2 U3 LEDS and Hot Swap LEDs IPMC control Two Ethernet ports
185. tion provides detailed descriptions of those extensions Table 8 33 Pigeon Point Extension Commands Command Get Status Table 8 35 on page 208 NetFn Request Response Ox2E Ox2F CMD 0x00 Get Serial Interface Properties Table 8 36 on page 211 0x01 Set Serial Interface Properties Table 8 37 on page 212 Get Debug Level Table 8 38 on page 213 Set Debug Level Table 8 39 on page 214 Get Hardware Address Table 8 40 on page 215 0x02 0x03 0x04 0x05 Set Hardware Address Table 8 41 on page 215 0x06 Get Handle Switch Table 8 42 on page 216 0x07 Set Handle Switch Table 8 43 on page 217 Get Payload Communication Time Out Table 8 44 on page Set Payload Communication Time Out Table 8 45 on page 218 0x08 0x09 0x0A Enable Payload Control Table 8 46 on page 219 0x0B Disable Payload Control Table 8 47 on page 219 Reset IPMC Table 8 48 on page 220 Hang IPMC Table 8 49 on page 220 Graceful Reset Table 8 50 on page 221 0x0C 0x0D OxOE 0x11 Get Payload Shutdown Time Out Table 8 51 on page 222 0x15 Set Payload Shutdown Time Out Table 8 52 on page 223 0x16 Get Module State Table 8 53 on page 223 Enable Module Site Table 8 54 on page 225 Disable Module Site Table 8 55 on page 225 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 0x27 0x28 0x29 207 Supported IPMI Commands Table 8 33 Pigeon Point Extension Commands continued Net
186. tors and Connectors Table 3 10 Mezzanine Card Connector Signals continued Signal C Signal B Signal A Signal 28 RESET N 28 PRSNT_N 28 PWR EN 28 PWR GD 29 VCC12 29 VCC12 29 VCC3V3 29 VCC3V3 30 GND 30 GND 30 GND 30 GND 70 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Controls Indicators and Connectors m TTT 3 2 4 Onboard Connectors 3 2 4 1 TPM Head One TPM head is installed on the board and can be used for a Port 80 card for debug monitor It can also be reserved for a TPM module customization The head pin pitch is 2 54 mm Figure 3 2 TPM Connector Pinout VCC3V3 LPC_ADO SMB_CLK VCC3_STB GND TPM PD N LPC LDRQ N ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 71 Controls Indicators and Connectors 3 2 4 2 3 3 3 3 1 72 FPGA JTAG Head A single row six pin heads for FPGA programming through JTAG is provided on the board Figure3 3 USB 2 0 Hash Disk Module Connector Pinout Switch Settings OOOOOO VCC2V5 MGMT GND TCK Switches reside on the component side 1 of the board and are not covered by any other component Its pin 1 is clearly marked on the PCB and by default are OFF PCH Switch Table 3 11 Switch SW2 Settings Switch PCH GPIO6 Function ON Load default BIOS setting Default GPIO7 ON BIOS Crisis Recovery ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G C
187. ts are 0 and 1 bold Used to emphasize a word Screen Used for on screen output and code related elements or commands in body text Courier Bold Used to characterize user input and to separate it from system output Reference Used for references and for table and figure descriptions File gt Exit Notation for selecting a submenu lt text gt Notation for variables and keys text Notation for software buttons to click on the screen and parameter description Repeated item for example node 1 node 2 node 12 Omission of information from example command that is not necessary at the time being 22 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G About this Manual Notation A Ee DOCCOCIORLCOCOOUOCOOQUOCIONXOIOC OUQCOOOO00O00O00000000000000000 KEREN DEN DK ICH NED ERIK CK DK NENNEN NOKIA OCKQOOULOODOUOCQUOR X00 XCOC GQUOOQCUKOOUOCGQUCOOOODOOOQ0OOUUCOCKE Description Ranges for example 0 4 means one of the integers 0 1 2 3 and 4 used in registers Logical OR Indicates a hazardous situation which if not avoided could result in death or serious injury 300O0O0OO0000O00000000000O000000000000000000000000000 C KKK X OOKOCUOC X UOCGOU RRE OO OOOO IIE KAAAKKAAKAAAKAAXKAAKKAAXKKAAKKAXKAAXKAAXKKAAXKAAKK Indicates a hazardous situation which if not avoided may result in minor or moderate injury XXXXXXXOOOOOOOOOOOOOOOOOOOOOOOOOO0O0000
188. ts the input data 1 Framing error occurred 0 No framing error 0 LPC r 142 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Maps and Registers Table 6 37 Line Status Register LSR continued LPC IO Address Base 5 Bit 4 Description Break Interrupt Bl indicator When Bl is set it indicates that the received data input was held low for longer than a full word transmission time A full word transmission time is defined as the total time to transmit the start data parity and stop bits Bl is cleared every time the CPU reads the contents of the LSR In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the CPU when its associated character is at the top of the FIFO When a break occurs only one 0 character is loaded into the FIFO The next character transfer is enabled after RXD goes to the marking state for at least two Receiver CLK samples and then receives the next valid start bit 1 Full WORD transmission time exceeded 0 Normal operation Access LPC r Transmit Holding Register Empty THRE indicator THRE is set when the THR is empty indicating that the ACE is ready to accept a new character If the THRE interrupt is enabled when THRE is set an interrupt is generated THRE is set when the contents of the THR are transferred to the TSR THRE is cleared concurrent with the loading of the THR
189. ual one rns EENS EE ENEE PE NEE ENN e EE 19 Safety Notes si 25 KS EE EN 1 Introduction c ccio oce e n o ht n Rh ORI rh ua EE EES EES YES 37 Tedd d EE 37 1 2 Standard Combplianc s eie sese EN revue xr re A eR ace 38 1 3 Mechanical Data eu ERENNERT a es en ner 41 1 4 Mechanical Layout nee me ae ee ber 42 1 5 Mean Time Between Failures 222eseseeeseeeseeeenenenenen ernennen seen nenne 43 1 6 Ordering Information ac nee en ne 43 1 7 Product Identification 0 ccc cee nent n een ene eneeeneeeas 44 2 Hardware Preparation and Installation 0c cece cece cere cece e eee nnn 45 2 1 Unpacking and Inspecting the Blade 45 2 2 Environmental and Power Requirements 0 cece eee eee cece e eee hn 45 2 2 1 Environmental Requirements 0 cece cece serenan rrer eee rreren 46 2 2 2 PowerRequiremetts unse 49 2 3 Blade layotlt ere t hae RETE a Pa REN Ue CUPIS ERR 51 2 4 Installing the Blade Accessories 52 2 4 1 DIMM Memory Module 52 2 4 2 Cave Creek Module ne ame RH eet 54 2 5 Installing and Removing the Blade 0 eee eect eee I 57 2 5 1 Installing the Blade ccc ccc ec e Ime 57 2 5 2 Removing the Blade cece eee ence hh emen 59 3 Controls Indicators and Connectors eeeeeeeeeee eene nnn 61 SZT Faceplate sss EES ko eer phe HERI egi tek Ee ie ee rere Abee deed 61 3 1 1 LEDsand Tue EE 61 3 2 CONNECTORS sie ciee e peo RE etsy beet en 6
190. urvives IPMC power cycle reset and V7 ew maysurvive the IPMC firmware upgrades Activating new upgraded IPMC firmware may lead to FPGA BIOS boot bank change back to default boot bank if the NVRAM variables of the new upgraded IPMC firmware are different from the previous active version 186 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Supported IPMI Commands 8 1 7 1 2 M 8 1 7 1 3 System Boot Options Parameter 97 This is an Artesyn specific OEM parameter as defined in the following table Table 8 10 System Boot Options Parameter 97 1 POST Type Data 1 Set Selector This is the processor ID for which the boot option is to be set 2 Data 2 POST Type Selector This parameter is used to specify the POST type that the IPMC will execute 0x00 Short POST 0x01 Long POST 0x02 to OxFF Not used The System Boot Options parameter 97 is non volatile It survives the IPMC power cycle reset and may survive the IPMC firmware upgrades System Boot Options Parameter 93 This is an Artesyn specific OEM parameter ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 187 Supported IPMI Commands ML 8 1 7 1 4 188 It defines a timeout value for the graceful shutdown of the payload which means how long the IPMC waits forthe payload to shut down gracefully If the payload software is not configured to be notified by the graceful shutdown requests the IPMC will shut down th
191. us blade damage When operating the blade make sure that forced air cooling is available in the shelf When operating the blade in areas of electromagnetic radiation ensure thatthe blade is bolted on the system and the system is shielded by enclosure Injuries or Short Circuits Blade or power supply In case the ORing diodes of the blade fail the blade may trigger a short circuit between input line A and input line B so that line A remains powered even if it is disconnected from the power supply circuit and vice versa To avoid damage or injuries always check that there is no more voltage on the line that has been disconnected before continuing your work SFP SFP Modules Personal Injury and Damage of the RTM and SFP Modules Installing and using SFP modules which are not fully certified and which do not meet all relevant safety standards may damage the RTM and the SFP modules and may lead to personal injury Only use and install SFP modules which are fully certified and which meet all relevant safety standards ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 27 Safety Notes Personal Injury Optical SFP modules may be classified as laser products When installing and using any of these SFP modules the regulations which correspond to the respective laser class apply to the whole RTM Not complying to these regulations may lead to personal injury When installing and using optical SFP modules which are classified as l
192. vate firmware 0x2C 0x2D 0x35 Query self test results 0x2C 0x2D 0x36 Query rollback status 0x2C 0x2D 0x37 Initiate manual rollback 0x2C 0x2D 0x38 YE The firmware upgrade commands supported by the blade are implemented according to the PICMG HPM 1 Revision 1 0 specification The boot block can be updated with PICMG HPM 1 specific commands ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 197 Supported IPMI Commands 8 3 ML 8 3 1 198 Artesyn Embedded Technologies Specific Commands The Artesyn Embedded Technologies IPMC supports several commands which are not defined in the IPMI or PICMG 3 0 specification but are introduced by Artesyn Embedded Technologies serial output commands e Before sending any of these commands the shelf management software must check whetherthe receiving IPMI controller supports Artesyn Embedded Technologies specific IPMI commands by using the IPMI command Get Device ID Sending Artesyn Embedded Technologies specific commands to IPMI controllers which do not support these IPMI commands will lead to no or undefined results e Proper handling of these commands is required to write a portable application Set Get Feature Configuration Commands This command can be used to enable disable features within the IPMC during runtime Table 8 20 Set Get Feature Configuration Commands NetFn Command Name Request Response CMD Description Set Feature Configuration Ox2E Ox2F
193. which the CPU blade is not functioning properly Errors Possible Reasons Solution The embedded software in the Verify the software is The power good LED is not hardware units is not consistent consistent with the product lit with the product release release The out of service LED is lit The blade is not properly seated Make sure that the blade is The hot swap LED is not lit properly seated when the hot swap latchis One of the memory modulesis Make sure that the memory opened or lits when the not properly seated module is properly seated latch is closed eer One of the cables is not properly Connect the cable properly does not display BIOS post Connected The BIOS output does not The FRU data of the blade is Verify the FRU data of the include the expected data incorrect blade The blade does not answer One of the voltages is too highor Make sure the voltage is as to ping low per the board requirements There is an IPMI alarm One of the temperatures je too Make sure the temperature is high as per the board requirements There is a fault in the DC Verify the DC converter converter The IP address of the blade is Verify the IP address of the incorrect blade ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 247 Troubleshooting en ee 248 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Appendix B Related Documentation EE B 1
194. will be required to correct the interference at his own expense The USB1 USB2 ports and the COM port are considered as debug maintenance ports During normal operation no cables must be connected to these ports Cables attached to these ports during maintenance must not exceed a length of 3m Installation Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before touching the blade or electronic components make sure that you are working in an ESD safe environment Data Loss Removing the blade with the blue LED still blinking causes data loss Wait until the blue LED is permanently illuminated before removing the blade Damage of Blade and Additional Devices and Modules Incorrect installation of additional devices or modules may damage the blade or the additional devices or modules Before installing or removing an additional device or module read the respective documentation 26 ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Safety Notes Operation Blade Damage Blade surface High humidity and condensation on the blade surface causes short circuits Do not operate the blade outside the specified environmental limits Make sure the blade is completely dry and there is no moisture on any surface before applying power Blade Overheating and Blade Damage Operating the blade without forced air cooling may lead to blade overheating and th
195. x is booted up the Error Detection and Correction Module EDAC is also used to count the ECC error Correctable ECC Logging and Threshold setting in BIOS setup Advanced Menu Item Default Memory ECC Error Log Description This item selects the ECC Runtime errors which are to be logged in the SMBIOS event log This item is used to enter the correctable error threshold value if Memory ECC Error Log is not disabled The logging threshold is based per memory rank not per DIMM or overall Correctable ECC Logging Threshold ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Memory Configuration Correctable ECC Flooding Threshold This item is used to set the error logging limit value per second if Memory ECC Error Log is not disabled If the number of correctable ECC error logs produced per second reaches the flood threshold the correctable ECC error reporting is disabled The flood threshold is an overall setting 77 BIOS Example Set threshold to 10 Given a dual rank DIMM and if 5 errors occur in rank 0 DIMM and 5 errors in rank 1 DIMM then no ECC event is recorded Given a dual rank DIMM and if all the 10 errors occur in one single rank i e either rank 0 or rank 1 DIMM then an ECC event is recorded e Available memory space below the 4G boundary The ATCA 7370 provides 3 25 GB memory space below the 4 GB boundary The memory map below AGB is listed in the following table
196. y Menus have sub menus Table 4 4 Primary Menu Description Provides system information date and time Advanced Advanced features including Boot Processor Peripheral USB Memory South Bridge and SMBIOS event log settings Security Supervisor and User password options Boot Boot priority order ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 87 BIOS Table 4 4 Primary Menu Description continued Menu Options Save with or without changes Loads or saves default settings The Phoenix SecureCore Tiano SCT navigation can be accomplished using a combination of the keys These keys include the function keys Enter Esc Arrow keys etc The following table describes the SCT navigation keys Table 4 5 SCT Navigation Keys Key Description ENTER The Enter key allows to select an option to edit its value or access a sub menu gt lt The Left and Right lt Arrow gt keys allow to select a screen or menu Left Right For example Main screen Advanced screen Exit screen etc v The Up and Down Arrow keys allow to select an item or sub screen Up Down The Plus and Minus keys allow to change the field value of a particular setup item Plus Minu For example Date and Time s Tab The Tab key allows to select fields ESC The Esc key allows to discard any changes made and exit the SCT Setup When you are in a submenu The Esc key allows you to exit to the upper menu Function W

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