XSA Board V1.1, V1.2 User Manual
Contents
1. 5822225222292929 WRITE 9 C5 C5 C5 CO C5 CO C5 Co C5 Co C5 Co C5 Co C5 BUSY DOUT 3 3V 2 5V COMPANY XESS Corporation TITLE XSA Board Spartan FPGA RELEASED XCBUSL001 144 0 01uF xsal_2 sch 2 Mon Feb 11 08 37 19 2002 N 05 XCBUSO60 8 5 K xcRus043 12 o TCK Kk xcRuson2 06 06 D7 XCBUSO6 CE XCBUSO4 CS TDI BUSO BSY BUSO CCL BUSO WRITE TDO XCB 19 U2 As raison XC9572XL VQ64 M A7 XCBUSORS A6 Kk xcRus076 A4 Kk xcRus074 A3 Kk xcRus027 A2 Kk xcRusn2R A1 xcausn20 1 0 Kk xcRusn4n DO Kk xcRusnig D1 Kk xcRus044 02 D3 K xcRusn4o D4 xcRus057 C17 C18 C19 0 01uF 0 01uF 0 01uF COMPANY XESS Corporation XSA Board CPLD Interface RELEASED DATED SHEET OF PROGRAM DONE XCBUS 001 144 C20 0 01uF xsal_2 sch 3 Mon Feb 11 08 37 19 2002 49 002 01 4O 01 4 C42 4 GNO XCBUS054 XCB 4 5063 Kk 101 XCBUS056 Kk xcausns amp 6 XCBUS 001 144 XESS Corporation XSA Board Flash RAM RELEASED DATED SHEET xsal_2 sch 4 Mon Feb 11 08 37 19 2002 04 SDRAM 256MB XCBUSL001 144 COMPANY XESS Corporation XSA Board Sync DRAM DRAWN DATED REV RE2. 108 2 FPGA M2 PROTO12 112 SDRAM Q12 144 710 5 11 116 SDRAM Q10 o SDRAM Q9 L M Er e E L L 1 MEN 124 SDRAM QMH 126 O CTRDY SDRAM CAS 128 GND 130 SDRAM RAS 132 O VREF7 SDRAM CS 134 SDRAM BAO 136 SDRAM A11 138 SDRAM AQ 144 SDRAM A8 142 TMS FPGA TMS 18 PROTO17 144 Connections Between the CPLD and Other XSA Board Components Switch and the XST 2 x Board CPLD CPLD Pin Function Net Name Proto Pin LEDs Button IDE Intfc Stereo Codec Serial Port 1 PROTO57 LED2 C IDE INTRQ 2 FPGA DIN DO PROTO71 BARLED9 IDE IORDY 3 VCCINT 4 FPGA D1 PROTO40 BARLED2 IDE D1 5 FPGA D2 PROTO39 BARLED3 IDE D2 6 FPGA D3 PROTO38 BARLED4 IDE D3 7 FPGA D4 PROTO35 BARLED5 IDE D4 8 FPGA D5 PROTO80 BARLED7 IDE D6 RS232 RD 9 FPGA D6 PROTO81 BARLED6 IDE D5 RS232 CTS 10 FPGA D7 PROTO10 BARLED8 IDE D7 11 PROTO65 12 PROTO61 IDE D9 13 FPGA TCK PROTO16 14 GND 15 GCK1 FPGA CS PROTO68 IDE RESET 15 GCK1 FPGA TDI PROTO15 16 GCK2 FPGA CCLK PROTO73 17 GCK3 PROG OSC 18 FPGA DOUT BSY PROTO45 LED2 DP IDE DMACK 18 FPGA TMS
3. lt lt lt lt XC9572XL CPLD Spartan ll FPGA 4 7 3 6 6 7 2 1 8 4 5 4 5 4 4 5 5 4 2 4 5 6 7 8 9 Seven Segment LED The XSA Board has a 7 segment LED digit for use by the FPGA or the CPLD The segments of this LED are active high meaning that a segment will glow when a logic high is applied to it The LED shares the same pins as the eight bits of the Flash RAM data bus XSA BOARD V1 1 V1 2 USER MANUAL 23 Four Position DIP Switch The XSA Board has a bank of four DIP switches accessible from the CPLD and FPGA When closed or ON each switch pulls the connected pin of the FPGA and CPLD to ground Otherwise the pin is pulled high through a resistor when the switch is open or OFF When not being used the DIP switches should be left in the open or OFF configuration so the pins of the FPGA and CPLD are not tied to ground and can freely move between logic low and high levels The DIP switches also share the same pins as the uppermost four bits of the Flash RAM address bus If the Flash RAM is programmed with several FPGA bitstreams then the DIP switches can be used to select a particular bitstreams which will be loaded into the FPGA by the CPLD on power up However this fe
4. 9 ESS Corporation XSA Board V1 1 V1 2 User Manual How to install test and use your new XSA Board RELEASE DATE 3 17 2004 Copyright 2001 2004 by Engineering Software Systems Corporation All XS prefix product designations are trademarks of XESS Corp All XC prefix product designations are trademarks of Xilinx All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise without the prior written permission of the publisher Printed in the United States of America XSA BOARD V1 1 V1 2 USER MANUAL 1 Table of Contents XSA BOARD V1 1 V1 2 USER MANUAL 2 XSA BOARD V1 1 V1 2 USER MANUAL Preliminaries Here are some places to get help if you encounter problems If you can t get the XSA Board hardware to work send an e mail message describing our problem to help xess com or submit a problem report at http www xess com help html Our web site also has m answers to frequently asked questions m example designs application notes and tutorials for the XS Boards m a place to sign up for our email forum where you can post questions to other XS Board users If you can t get your Xilinx WebPACK software tools installed properly send an e mail message describing your problem to hotline xilinx com or check their web site at http www xilinx com support s
5. XSTOOLS installation This brings up the window shown below Then select the type of XS Board you are using and the parallel port to which it is connected as follows X gxsload x Board Type 5 100 Load Port FPGA CPLD Flash EEPROM IT High Address Low Address Upload Format HEX XSA BOARD V1 1 V1 2 USER MANUAL 12 After setting the board type and parallel port you can download BIT or SVF files to the Spartan Il FPGA XC9572XL CPLD on your XSA Board simply by dragging them to the FPGA CPLD area of the GXSLOAD window as shown below X gxsload Once you release the left mouse button and drop the file the highlighted file name appears the FPGA CPLD area and the Load button in the GXSLOAD window is enabled Clicking on the Load button will begin sending the highlighted file to the XSA Board through the parallel port connection BIT files contain configuration bitstreams that are loaded into the FPGA while SVF files will go to the CPLD GXSLOAD will reject any non downloadable files ones with a suffix other than BIT or SVF During the downloading process GXSLOAD will display the name of the file and the progress of the current download X gxsload XSA BOARD V1 1 V1 2 USER MANUAL 13 You can drag amp drop multiple files into the FPGA CPLD area Clicking your mouse on a filename will highlight the name and selec
6. is uploaded through the parallel port 3 The uploaded data is stored in a file named FLSHUPLD with an extension that reflects the file format X gxsload x Board Type ksa 00 Load FPGA CPLD Flash EEPROM u 00 High Address oxarFFF Low Address g Upload Format HEX The uploaded data be stored the following formats MCS Intel hexadecimal file format This is the same format generated by the promgen utility with the p mcs option Identical to MCS format EXO 16 Motorola S record format with 16 bit addresses suitable for 64 KByte uploads only 24 Motorola S record format with 24 bit addresses This is the same format generated by the promgen utility with the p exo option 32 Motorola S record format with 32 bit addresses XSA BOARD V1 1 V1 2 USER MANUAL 16 XESS 16 XESS hexadecimal format with 16 bit addresses This is simplified file format that does not use checksums XESS 24 XESS hexadecimal format with 24 bit addresses XESS 32 XESS hexadecimal format with 32 bit addresses After the data is uploaded from the Flash the CPLD on the XSA Board is left with the Flash interface programmed into it You will need to reprogram the CPLD with either the parallel port or Flash configuration circuit before the board will function again The CPLD configuration bitstreams are stored in the following files XSTOOLS XSA
7. 30 and the XST 2 x Board Connections Between the FPGA and Other XSA Board Components FPGA FPGA Pin Net Name CPLD Parallel eps lt Switch SDRAM Flash VGA 5 2 LEDs Switeh SRAM IDE Intfe Stereo Codec USB Serial Port Pin Function Pin Port Button Button 1 VCCO 3 3V PROTO54 2 FPGA TCK 13 PROTO16 SDRAM A7 4 SDRAM A1 5 0 SDRAM A6 6 O VREFO SDRAM A2 Te 00 SDRAM A5 8 GND PROTO52 9 VCCINT 22 10 vo SDRAM A3 11 SDRAM A4 12 VO VREFO VGA REDO PROTO27 18 VGA RED1 PROTO28 14 VCCINT 15 GCK3 FPGA GCK3 PROTO31 16 VCCO 17 48 GCK2 FPGA GCK2 PROTO1 19 VGA GREENO PROTO29 20 VGA GREEN1 PROTO32 21 VGA BLUEO PROTO33 22 VGA BLUE1 PROTO34 23 O VGA HSYNC PROTO36 PUSHB4 24 VCCINT 25 GND 26 VGA VSYNCH PROTO37 PUSHB3 27 1 62 FLASH A3 PROTO50 LED2 B RAM AO IDE DMARQ 28 O VREF1 63 85 FLASH A2 PROTOS1 LED2 E RAM A10 USB INT 29 o 64 PP S4 FLASH A1 PROTOS6 2 RAM A11 USB SUSPEND 30 FPGA WR 19 PROTO69 DIPSW1 31 VO CS FPGA CS 15 PROTO68 ID
8. PROTO17 19 FPGA WR PROTO69 19 FPGA TDO PROTO30 20 PPORT S4 21 GND 22 PPORT D7 23 24 25 26 VCCIO 27 28 TDI 29 TMS 30 TCK 31 32 33 34 35 36 0 PROTO14 37 VCCINT 38 FPGA INIT PROTO41 BARLED1 39 FPGA PROG PROTO55 40 FPGA DONE PROTO53 41 GND 42 MASTER CLK PROTO13 43 59 LED2 D IDE D10 44 PROTO60 LED2 A IDE D11 45 PROTO78 LED1 G IDE D12 46 PROTO79 LED1 B IDE D13 47 PROTO82 LED1 F IDE CSO 48 PROTO83 LED1 A IDE CS1 49 PROTO62 IDE D14 50 PROTO66 BARLED10 AUDIO LRCK 51 PROTO84 LED1 DP IDE DA2 52 PROTO3 LED1 D IDE DAO 53 TDO 54 GND 55 VCCIO 56 PROTO4 IDE D15 57 PROTO58 IDE D8 58 5 IDE DA1 59 PROTO6 AUDIO SDTO 60 PROTO77 AUDIO SCLK 61 PROTO70 AUDIO SDTI 62 50 IDE DMARQ 63 PROTO51 USB INT 64 29 PP S4 FLASH A1 PROTO56 LED2 G RAM A11 USB SUSPEND Connections Between the FPGA and Other XSA Board Components and the XST 1 x Board FPGA FPGA Pin CPLD Parallel Switch Net LEDs SDRAM Flash VGA PS 2 Proto Pin LEDs Switch Button SRAM VGA Stereo Codec PS 2 Xchecker Pin Function Pin Port Button 1 vcco 3 3V PROTO54 2 13 PROTO16 XCHK TCK ES VO SDRAM A7 4 1 0 SDRAM A1 5x VO V
9. S6 RAM A14 49 VO D3 FPGA D3 6 LED S6 FLASH D3 PROTO38 BARLED4 RAM D3 50 45 PP DO FLASH A8 PROTO78 LLED S3 RAM A3 51 VO IRDY 46 PP D5 FLASH A13 PROTO79 LLED S4 RAM A4 52 GND 53 vcco 54 VO TRDY 47 DIPSW1A FLASH A14 PROTO82 LLED S5 5 55 56 VO 48 DIPSW1D FLASH A17 PROTO83 LLED S6 RAM A6 57 VO D4 FPGA D4 T LED S5 FLASH D4 PROTO35 BARLED5 RAM D4 58 I O VREF3 49 PP D6 FLASH WE PROTO62 RAM WE 59 VO 50 FLASH RESET PROTO66 DIPSW7 CODEC LRCK 60 0 05 FPGA D5 8 LED S3 FLASH D5 PROTO80 BARLED7 RAM D6 61 GND 62 1 0 D6 FPGA D6 9 LED S2 FLASH D6 PROTO81 BARLED6 RAM D5 63 VO VREF3 51 DIPSW1C FLASH A16 PROTO84 LLED DP RAM A7 64 VO 52 DIPSW1B FLASH A15 PROTO3 LLED SO RAM AO 65 56 PP D4 FLASH A12 PROTO4 LLED S1 RAM A1 66 VO 58 FLASH A7 PROTOS LLED S2 RAM A2 677 0 07 FPGA D7 10 LED SO FLASH D7 PROTO10 BARLED8 RAM D7 68 VO INIT FPGA INIT 38 PROTO41 BARLED1 RAM DO XCHK INIT 69 PROG FPGA PROG 39 55 PUSH PROG XCHK PROG 70 VCCO 71 72 DONE FPGA DONE 40 PROTO53 XCHK DONE 73 GND 74 VO 61 FLASH A4 PROTO70 DIPSW6 CODEC SDIN WESS VO 60 FLASH A5 PROTO77 DIPSW5 CODEC SCLK 76 VO 59 FLASH A6 PROTO6 DIPSW4 CODEC SDOUT TA 4 9 DIPSW3 CODEC MCLK 78 gt VO PP S6 PROTO67 PUSH SPARE X VGA VSYNC WESS 4 PROTO7 DIPSW1 RAM LCE XCHK TRIG 80 VO 8 DIPSW2 RAM RCE XCHK RST 81 GND 82 VCCINT 83
10. This is the main interface for passing configuration bitstreams and data to and from the XSA Board PS 2 Port A keyboard or mouse can interface to the XSA Board through this port VGA Port The XSA Board can send signals to display graphics on a VGA monitor through this port XSA BOARD V1 1 V1 2 USER MANUAL 19 Prototyping Header Many of the FPGA I O pins connected to the 84 pins on the bottom of the XSA Board that are meant to mate with solderless breadboards Parallel Port 2 PPDO XC9572XL 25100 015 00 07 00 1 12 0 RAS CAS CS WE DQML 5 2 Port TMS i 3 PPD1 4 PPD2 5 PPD3 6 PPD4 7 PPD5 8 PPD6 9 PPD7 17 PPC3 14 PPCT PPS7 12 PPS5 13 PPS4 15 PPS3 Edd 1 PPCO 10 PPS6 4 e Figure 3 XSA Board programmer s model VGA Connector Programmable logic FPGA and XC9572XL CPLD The XSA Board contains two programmable logic chips m A50 Kgate XC2S50 or 100 Kgate Xilinx 25100 FPGA in a 144 pin PQFP package The FPGA is the main repository of programmable logic on the XSA Board m A Xilinx XC9572XL CPLD is used to manage the configuration of the FPGA via the parallel port The CPLD also controls the programming of the Flash RAM o
11. dwnidpar svf Drag amp drop this file into the FPGA CPLD area and click on the Load button to put the XSA in a mode where it will configure the FPGA through the parallel port XSTOOLS XSA fenfg svf Drag amp drop this file into the FPGA CPLD area and click on the Load button to put the XSA in a mode where it will configure the FPGA with the contents of the Flash device upon power up Downloading and Uploading Data to the SDRAM in Your XSA Board The XSA 100 Board contains a 16 MByte synchronous DRAM 8M x 16 SDRAM whose contents can be downloaded and uploaded by GXSLOAD The XSA 50 has an 8 MByte SDRAM organized as 4M x 16 This is useful for initializing the SDRAM with data for use by the FPGA and then reading the SDRAM contents after the FPGA has operated upon it The SDRAM is loaded with data by dragging amp dropping one or more EXO MCS HEX and or XES files into the RAM area of the GXSLOAD window and then clicking on the Load button This activates the following sequence of steps 1 The Spartan II FPGA on the XSA Board is reprogrammed to create an interface between the RAM device and the PC parallel port This interface is stored in the ram100 bit or ram50 bit bitstream file located within the XSTOOLS XSA folder CPLD must have previously been loaded with the dwnldpar svf file found in the same folder 2 The contents of the EXO MCS HEX or XES files are downloaded into the SDRAM through the parallel port Th
12. e e e e e 2 e 0 1 e e e e e e e e e e e e 2 84 e im 4 1 e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e 22 A subset of the 144 pins on the FPGA s TQFP package connects to the prototyping header The number of the FPGA pin connected to a given header pin is printed next to the header pin on the board This makes it easier to find a given FPGA pin when you want to connect it to an external system While most of the FPGA pins are already used to support functions of the XSA Board they can also be used to interface to external systems through the prototyping header The FPGA pins can be grouped into the various categories shown below Pins denoted with are useable as general purpose I O pins denoted with can be used as general purpose I O only if the CPLD interface is reprogrammed with the alternate parallel port interface stored in the dwnldpa2 svf file pins with no marking cannot be used as general purpose at all XSA BOARD V1 1 V1 2 USER MANUAL 28 Configuration Pins 30 31 37 38 39 44 46 49 57 60 62 67 68 69 72 106 109 111 These pins used to load the Spartanll FPGA with configuration bitstream Some of these pins are dedicated to the configuration process and cannot be used as general purpose 37 69 72 106 109 111 The rest be used as general p
13. 09 L 1 12 XCBUSO44 1 61 XCBUS111 XCBUS046 Ji 40 XCBUS142 J 21 XPBUSDIT 91 39 91 17 XCBUS048 E 4599 41 60 i XCHUSBSG O 11 38 i 31 42 censor 31 78 4 91 43 XCBUSGER 91 79 i 44 NEBUSUSE O 31 82 i 31 46 XCHISUET O vi 83 i 5 47 XEHUSHER O 31 35 il 31 48 91 62 OO 31 49 SEEUSORO 1 66 i 3 OO 72 91 81 i 74 i 75 i 76 XCBUS 001 144 COMPANY XESS Corporation XSA Board Prototyping Header RELEASED
14. 4 lt 1 THO DONE 12 PPS5 4 9 TER 13 PPS4 4 TMS 15 PPS3 4 VVV Sd OSC 2 cese 10 PPS6 4 After the Spartanll FPGA is configured with a bitstream and the DONE pin goes high the CPLD switches into a mode that connects the parallel port data and status pins to the FPGA This lets you pass data to the FPGA over the parallel port data lines while receiving data from the FPGA over the status lines The connections between the FPGA and the parallel port are shown below XSA BOARD V1 1 V1 2 USER MANUAL 26 256 O TOON r 00295923025 DNMDDw wcao RANA XC9572XL CPLD a FPGA 5V WwW 0 52 5 54 51 50 9pp I FPGA sends data back to the PC by driving logic levels onto pins 40 29 28 which pass through the CPLD and onto the parallel port status lines S3 S4 and S5 respectively Conversely the PC sends data to the FPGA on parallel port data lines DO D7 and the data passes through the CPLD and ends up on FPGA pins 50 48 42 47 65 51 58 and 43 respectively The FP
15. 5 gt 53 U9A U9E J8 3 gt 1 gt T gt aoe 18 16 gt 741514 741514 48 4 gt PP C2 J8 17 gt PP D2 J8 5 gt gt PP C3 J8 18 gt mi gt PP D3 48 6 gt PP D4 MES J8 7 gt gt PP D5 J8 8 gt PP D6 pn 48 9 gt PP D7 48 10 gt XCBUSO78 J8 23 gt USF z NO 12 13 J8 11 gt Pt O 57 48 24 gt 9 EN 74LS14 d OO 54 48 15 gt 18 27 gt Er 1 R13 2 98 26 gt C30 JE COMPANY XESS Corporation XSA Board Parallel Port Interface RELEASED DATED SHEET xsal_2 sch 9 Mon Feb 11 08 37 20 2002 XCBUS002 05065 XCBUSO12 i s16 XCBUSO64 201 84 XCBUSO13 1 27 XCBUS065 L 3 XCBUSO15 L 41 28 XCBUSO66 L 0 4 XCBUSO18 1 31 XCBUS067 I 15 XCBUSO19 O s XCBUS068 2201 10 5020 1 29 XCBUS069 ma XCBUSO21 11 32 XCBUS072 41 55 XCBUS022 ann XCBUSO74 H 53 5023 L 01 54 XCBUSO75 L 0 70 XCBUS026 XCBUSO76 9 77 XCBUS027 1 37 XCBUS077 I 41 6 XCBUS028 L 1 50 XCBUS078 O J 9 5029 01 51 XCBUSO79 1 67 XCBUS030 L 1 56 XCBUSO80 L 7 XCBUSO31 L 21 69 XCBUSOB3 XCBUS032 L 1 68 XCBUSO84 L 5034 XCBUS085 01 19 XCBUS037 5086 XCBUS038 H eds XCBUS087 01223 XCBUS039 XCBUSO88 01 24 XCBUSO40 en XCBUS093 E 41 38 XCBUSO41 1 57 XCBUS094 L J1 25 5042 1 65 XCBUS106 01 26 XCBUS043 ES 1 58 XCBUS1
16. E RESET 2 FPGA TDI 15 PROTO15 33 GND 34 FPGA TDO 19 PROTO30 35 vcco 36 37 CCLK FPGA CCLK 16 PROTO73 28 O DOUT BSY FPGA DOUT BSY 18 PROTO45 LED2 DP RAM AT 39 0 00 FPGA DIN DO 2 LED 81 FLASH DO PROTO71 BARLEDS 46 IDE IORDY 40 1 PP S3 FLASH AO PROTO57 LED2 C RAM A9 IDE INTRQ 41 VO VREF2 11 FLASH CE PROTO65 42 57 PP D2 FLASH A10 PROTO58 LED2 F RAM AB IDE D8 43 ljO VREF2 12 PP D7 FLASH OE PROTO61 RAM OE IDE D9 44 10 01 FPGA D1 4 LED DP FLASH D1 PROTO40 BARLED2 RAM D6 IDE D1 45 GND 46 10 02 FPGA D2 5 LED S4 FLASH D2 PROTO39 BARLED3 RAM D5 IDE D2 47 43 PP D3 FLASH A11 PROTOS9 2 0 1 010 48 O VREF2 44 PP D1 FLASH AQ PROTO60 LED2 A RAM A15 IDE D11 49 0 53 FPGA D3 6 LED S6 FLASH D3 PROTO38 BARLEDA RAM D4 IDE D3 50 45 PP DO FLASH A8 PROTO78 LED1 G RAM A14 IDE D12 51 VO RDY 46 PP D5 FLASH A13 PROTO79 LED1 B 12 IDE D13 52 53 vcco 54 VO TRDY 47 DIPSW1A FLASH A14 PROTO82 RAM A7 80 55 VCCINT 56 48 DIPSW1D FLASH A17 PROTO83 LEDI A RAM A6 _ IDE CS1 57 10 04 FPGA D4 7 LED S5 FLASH D4 PROTO35 BARLEDS RAM D3 DE D4 58 gt O VREF3 49 PP D6 FLASH WE PROTO62 DIPSW2 RAM WE IDE D14 59 1 0 50 FLASH RESET PROTO66 BARLED10 AUDIO LRCK 60 10 05 FPGA D5 8 LED S3 FLASH D5 PROTO80 BARLED7 RAM DO 06 RS232 RD GND 62 10 06 FPGA D6 9
17. GA should never drive these pins unless it is accessing the Flash RAM otherwise the CPLD and or the FPGA could be damaged The CPLD can sense when the FPGA lowers the Flash RAM chip enable and it will release the data lines so the FPGA can drive the address output enable and write enable pins of the Flash RAM without contention The CPLD also drives the decimal point of the LED display to indicate when the FPGA is configured with a valid bitstream Unless it is accessing the Flash RAM the FPGA should never drive pin 44 to a low logic level or it may damage itself or the CPLD But when the FPGA lowers the Flash RAM chip enable the CPLD will stop driving the LED decimal point to allow the FPGA access to data D1 of the Flash RAM XSA BOARD V1 1 V1 2 USER MANUAL 27 terface application note Prototyping Header The pins of the FPGA are accessible through the 84 pin prototyping header on the underside of the XSA Board Pin 1 of the header denoted by a square pad is located in the middle of the left hand edge of the board and the remaining 83 pins are arranged counter clockwise around the periphery The physical dimensions of the prototyping header and the pin arrangement are shown below For more details on how the CPLD manages the interface between the parallel port and the Spartanll FPGA both before and after device configuration see the KSA Parallel Port 1 75 o 64 4 e e e e e e e e e
18. LEASED DATED SHEET xsal_2 sch 5 Mon Feb 11 08 37 19 2002 R2C RED1 XCBUS013 3 AAN 6 330 REDO 05012 6 NU 3 680 R2B GREEN 05020 2 ANN 7 330 R1B GREENO 05019 7 A AP 680 R2A BLUE1 05022 1 2 8 530 RIA BLUEO 05021 8 VVV 680 HSYNC XCBUS023 VSYNC XCBUSO26 R3E 4 7K R3D NG 4 7K 12 R2D 330 XCBUS094 PS2 CLK RID Ann 4 XCBUS093 PS2 DATA 680 02 54 XCBUSO46 6 SW PUSH NO 5 2 43 13 03 56 XCBUS049 5 ANNE D4 S5 XCBUS057 4 ANNE EPA 05 53 XCBUSO60 3 14 06 52 XCBUS062 2 ANNE 07 50 XCBUS067 1 ANNE 10 00 51 05039 8 AAN 9 D1 DP XCBUSO44 7 10 XCBUSL001 144 COMPANY XESS Corporation mE XSA Board PS 2 Port VGA Port LED DRAWN DATED REV V1 2 RELEASED DATED SHEET OF xsal_2 sch 6 Mon Feb 11 08 37 19 2002 PP CO 41 64 11 PROG OSC 0 01uF 0 01uF ale Ll XSA Board Programmable Oscillator xsal_2 sch 7 Mon Feb 11 08 37 20 2002 PWRPLUG 95 5 SWITCH 1N4148 1N4148 COMPANY XESS Corporation XSA Board Regulated Power Supplies xsal_2 sch 8 Mon Feb 11 08 37 20 2002 U9C U9D 5 89 o8 C PP CO 741514 741514 U9B 3 gt gt PP C1 J8 14 gt 74LS14 J8 2 gt gt PP DO 48 1
19. LED S2 FLASH D6 PROTO81 BARLED6 RAM D1 IDE D5 RS232 CTS 63 VO VREF3 51 DIPSWIG FLASH A16 PROTOS4 LEDi DP 5 IDE DA2 64 52 DIPSW1B FLASH A15 PROTO3 LED1 D RAM A4 IDE DAO 65 VO VREF3 56 04 FLASH A12 PROTO4 15 66 58 FLASH A7 PROTOS DIPSWS RAMA2 IDE DA1 67 10 07 FPGA D7 10 LED SO FLASH D7 PROTO10 BARLED8 RAM D2 IDE D7 68 O INIT amp 38 PROTO41 BARLED1 RAM D7 00 69 PROG FPGA PROG 39 PROTO55 PUSHB1 70 VCCO Fi VCCO 72 DONE FPGA DONE 40 PROTOS3 73 GND 74 61 FLASH A4 PROTO70 DIPSW3 AUDIO SDTI 75 60 FLASH A5 PROTO77 DIPSW4 AUDIO SCLK 76 59 FLASH A6 PROTO6 LEDI E AUDIO SDTO 77 PROTOS DIPSWE AUDIO MCLK 78 PP S6 PROTO67 PUSHB2 79 O VREF4 PROTO7 DIPSW8 80 PROTOS DIPSW7 RS232 RTS 81 82 83 PROTO18 RS232 TD Connections Between the FPGA Other XSA Board Components and the XST 2 x Board FPGA Net Name CPLD Parallel SDRAM Flash VGA PSi2 Proto Pin LEDs Sitch spay IDE Intfe Stereo Codec USB Serial Port Pin Function Pin Port Button PROTO19 USB SCL IDE DIOR I GCKO MASTER CLK 90 VCCO 92 VCCINT 94 5 i PS2 CLK 26 96 SDRAM Q15 98 GND 100 VO VREFS SDRAM Q14 102 VO VREFS SDRAM Q13 NIC zu m IN ee
20. LL c 4M 16 SDRAM XSA 50 8M X 16 SDRAM XSA 100 SO B 00 O C0 O1 1 I P O00 O C2 Co CO Co Co gt The Flash RAM organizations and manufacturer used on the XSA Boards are given in the following table Flash RAM Board Organization Manufacturer amp Part No XSA 50 128K x 8 Atmel AT49F001 Flash RA XSA 100 256K x 8 Atmel AT49F002 Flash XSA BOARD V1 1 V1 2 USER MANUAL 22 The Flash RAM is connected so both the FPGA CPLD have access Typically the CPLD will program the Flash with data passed through the parallel port If the data is an FPGA configuration bitstream then the CPLD can be configured to program the FPGA with the bitstream from Flash whenever the XSA Board is powered up See the apcication note RBA Flash Broctanrining eed tor more this After power up the FPGA can read and or write the Flash Of course the CPLD and FPGA have to be programmed such that they do not conflict if both are trying to access the Flash The Flash is disabled by raising the CE pin to a logic 1 thus making the I O lines connected to the Flash available for general purpose communication between the FPGA and the CPLD 128K x 8 Flash RAM XSA 50 256K x 8 Flash RAM XSA 100 ONONO SO P r NYO lt lt lt lt
21. O26 26 84 xcBUSOR4 TET VREF4_3 86 7 BUSO28 g 87 RUSQ40 40 3 xcausnai 7 RUSD4 az VREF5_1 5 yerpusnas 1 43 96 4 RISO4 47 VREF2 2 59 815050 So VREFZ 3 T VREF5_2 yreuisiot 1 RUSO 51 102 xcBus102 4 Ben 54 XC2S TQFP144 VREF5_3 103 03 815056 56 12 2 4 R7 5 113 xcBusns 4 CBUS088 88 CCLKO L4 7 BUSOG VREF6_I IE Lion BLSA 15 GCLK2 vree 2 Ply xcausiiz 4 XCR 39 120 xcRUS120 4 RUS044 44 DN 00 121 xcBust21 A XCRUSD4 46 0 122 XCRUSI22 4 XCBUS Dd 49 02 VREF63 1253 XCBUISI23 4 3 3V XCR 57 09 124 12472 XC 6004 126 126 4 RBF 4 XC 82 129 xcBusi28 4 BAA AA KCB 67 06 130 xcaustio 4 15038 38 131 xcBusiat 4 XCR PR DOUT 132 2 g RBH 4 7K 30 WRITE VREF7 1 122 132 BUSO68 A xcBUSO6R 68 Kir 134 xcBusi34 4 R8G 47 B XCBUSO 72 DONE 136 XCBUSI38 A ra 37 PROGRAM VREF7 2 138 XcRust38 1 SG ES CCLK vrer7 139 4 7 xcausi09 109 o 3 140 xcausi4n 2 XCRUSIII 141 xcBuSi41 4 RSH 4 7 06 XCB 06 106 2 500 2 XCRUS142 142 5 XCRUSO 92 TDI nco HOS TDO
22. One of the A C E protoboards from is a good choice Once plugged in many of the pins of the FPGA are accessible to other circuits XSA BOARD V1 1 V1 2 USER MANUAL 6 on the protoboard numbers printed next to the rows of pins your XSA Board correspond to the pin numbers of the FPGA Power can still be supplied to your XSA Board though jack J5 or power can be applied directly through several pins on the underside of the board Just connect 5V 3 3V 2 5V and ground to the pins of your XSA Board listed in e Table 1 Power supply pins for the XSA Board Voltage Pin Note 5V 2 3 3V 22 Remove the shunt from jumper J7 if you wish to use your own 3 3V supply Leave the shunt on jumper J7 to generate the 3 3V supply from the 5V supply 2 5V 54 Remove the shunt from jumper J2 if you wish to use your own 2 5V supply Leave the shunt on jumper J2 to generate the 2 5V supply from the 3 3V supply GND 52 Parallel Port e Figure 1 External connections to the XSA Board XSA BOARD V1 1 V1 2 USER MANUAL PC Parallel Port Extemal Clock Input 100 MHz Osc Pushbutton Flash RAM 5V Spartan II FPGA SDRAM Pushbutton 2 5V PS 2 Mouse Monitor or Keyboard e Figure 2 Arrangement of components on the XSA Board Connecting a PC to Your XSA Board The 6 DB25 male to male cab
23. REFO SDRAM A6 6 0 SDRAM A2 ve VO SDRAM A5 8 GND PROTO52 9 VCCINT 2 5V PROTO22 10 VO SDRAM A3 11 VO SDRAM A4 12 VGA REDO PROTO27 137 VO VGA RED1 PROTO28 RLED DP RAM A15 14 VCCINT 15 GCK3 FPGA GCK3 PROTO31 16 VCCO AF GND 18 GCK2 FPGA GCK2 PROTO1 19 VO VGA GREENO PROTO29 20 VO VGA GREEN1 PROTO32 XCHK RT VO VREF1 VGA BLUEO PROTO33 22 VO VGA BLUE1 PROTO34 29 VO VGA HSYNC PROTO36 24 VCCINT 25 GND 26 gt VO VGA VSYNC PROTO37 PUSH RESET VO VREF1 62 FLASH A3 50 RLED S4 RAM A12 28 63 55 FLASH A2 PROTOS1 RLED S2 RAM A10 29 VO 64 PP S4 FLASH A1 56 RLED S3 RAM A11 30 V O WRITE FPGA WR 19 PROTO69 DIPSW8 X PS2 DATA 31 VO CS FPGA CS 15 68 X PS2 CLK 32 TDI FPGA TDI 15 PROTO15 XCHK TDI 33 GND 34 TDO FPGA TDO 19 PROTO30 XCHK RD 35 vcco 36 VCCO 37 CCLK FPGA CCLK 16 PROTO73 XCHK CCLK 38 O DOUT BSY FPGA DOUT BSY 18 PROTO45 SIE 1 0 D0 FPGA DIN DO 2 LED S1 FLASH DO PROTO71 XCHK DIN 40 VO 1 PP S3 FLASH AO PROTO57 RLED S1 RAM A9 41 VO VREF2 11 FLASH CE PROTO65 RAM CE 42 57 PP D2 FLASH A10 58 RLED S5 RAM A13 43 2 12 PP D7 FLASH OE PROTO61 RAM OE 44 V O D1 FPGA D1 4 LED DP FLASH D1 PROTO40 BARLED2 RAM D1 45 GND 46 2 FPGA D2 5 LED S4 FLASH D2 PROTO39 BARLED3 RAM D2 47 43 PP D3 FLASH A11 PROTO59 RLED SO 8 48 2 44 PP D1 FLASH A9 PROTO60 RLED
24. TA FPGA TDO XCHK RD PPORT S4 PPORT D7 PPORT D6 PPORT D5 PPORT D4 PPORT D3 PPORT C3 PPORT C2 PPORT C1 PPORT D2 PPORT D1 PPORT DO PPORT S3 PPORT S5 FPGA MO FPGA INIT XCHK INIT FPGA PROG PUSH PROG XCHK PROG FPGA DONE XCHK DONE MASTER CLK XCHK CLKI DIPSW1A DIPSW1D FLASH RESET DIPSW7 CODEC LRCK DIPSW1C FLASH A16 DIPSW1B FLASH A15 PPORT S7 FLASH A12 LLED S1 RLED S5 LLED S2 DIPSW4 DIPSW5 DIPSW6 RLED S4 RLED S2 FLASH A1 RLED S3 XSA Schematics The following pages show the detailed schematics for the XSA Board XSA BOARD V1 1 V1 2 USER MANUAL 31 xsal_2 sch 1 Mon Feb 11 08 37 19 2002 3 5 2 5V CONO Xu CN 77 5 83338333888 888558855 3 gt gt 50900 n 89004 UA TTSSSSSUb 155 B 83 XCBUS051 ANT 2 VREFO 1 VREF3_2 RUSOD7 VREF0_2 65 XCRUSQB amp R 010 10 VREF3_3 X 066 RUSO xcauso74 7 BUSO Sr REFUS 76 Xcauso8 X b RUSD20 20 78 xcRUSD7R 1 B 79 079 4 RUSO Da 2 80 xcausnan RUSO 23 B3 xcBUSOR3 4 BUS
25. VO PROTO18 X VGA RED1 84 VO PROTO19 X VGA HSYNC 85 VO VREF4 PROTO20 X VGA GREEN1 Connections Between the FPGA and Other XSA Board Components and the XST 1 x Board O VREF5 ivo VREF5 TO VREF5 vo VREF6 VO VREF7 MASTER CLK FPGA M2 FPGA TMS SDRAM Q15 SDRAM Q12 SDRAM 124 SDRAM QMH 126 SDRAM CAS GND E vO PS2 CLK PROTO13 PROTO12 PROTO17 PROTO26 X VGA BLUE1 FPGA FPGA Pin Net Name CPLD Parallel Switch SDRAM Flash PSI2 Proto Pin LEDs Switch Button Stereo Codec PSI2 Xchecker Pin Function Pin Port Button 86 PROTO23 X VGA REDO XCHK CLKI 114 SDRAM Q1i 118 SDRAM QS 28 XCHK TMS CPLD Pin CPLD Pin Function Net Name FPGA Pin Parallel Port Switch Button Connections Between the CPLD and Other XSA Board Components LEDs Switch Button Stereo Codec and the XST 1 x Board Xchecker 40 83 RLED S1 39 gt XCHK DIN 44 46 49 57 60 gt PWM 62 67 41 43 2 XCHK TCK 31 X PS2 CLK 32 XCHK TDI 37 XCHK CCLK FPGA DOUT BSY FPGA TMS XCHK TMS FPGA WR DIPSW8 X PS2 DA
26. ature is not currently supported by the CPLD configuration that loads the FPGA from the Flash RAM XSTOOLS XSA fcnfg svf PS 2 Port A PS 2 port provides the FPGA with an interface to either a keyboard or a mouse FPGA receives two signals from the PS 2 interface a clock signal and a serial data stream that is synchronized with the falling edge of the clock For more details on using the PS 2 port and a simple circuit for receiving keystroke information from a keyboard see this application note 5V A Spartan ll ok_ PS 2 FPGA data Connector J4 o Pushbutton o SW2 The XSA Board has a single pushbutton that shares the FPGA pin connected to the data line of the PS 2 port The pushbutton applies a low level to the FPGA pin when pressed and a resistor pulls the pin to a high level when the pushbutton is not pressed XSA BOARD V1 1 V1 2 USER MANUAL 24 VGA Monitor Interface The FPGA can generate a video signal for display on a VGA monitor The FPGA outputs two bits each of red green and blue color information to a simple resistor ladder DAC This provides a palette of 2 x 22 x 2 64 colors The outputs of the DAC are sent to the RGB inputs of a VGA monitor The FPGA also generates the horizontal and vertical sync pulses HSYNC VSYNC See this Losses aml or more details on a simple circuit for generating VGA signals that displays an image stored in SDRAM vsyn
27. c gt hsync REDO AAA RED1 Spartan ll ANN gt red Sce FPGA WW GREEN AAA green J3 BLUEO BLUE AAA Parallel Port Interface The parallel port is the main interface for communicating with the XSA Board Control line CO goes directly to the 051075 oscillator and is used for setting the divisor as described previously and status line S6 connects directly to the FPGA for use as a communication line from the FPGA back to the PC The CPLD handles the fifteen remaining active lines of the parallel port as follows Three of the parallel port control lines C1 C3 connect to the JTAG pins through which the CPLD is programmed The C1 control line clocks configuration data presented on the C3 line into the CPLD while the C2 signal steers the actions of the CPLD programming state machine Meanwhile information from the CPLD returns to the PC through status line S7 The eight data lines 00 07 and the remaining three status lines 53 55 connect to general purpose pins of the CPLD The CPLD can be programmed to act as an interface between the FPGA and the parallel port the dwnldpar svf file is an example of such an interface Schmitt trigger inverters are inserted into the D1 line so it can carry a clean clock edge for use by any state machine programmed into the CPLD The CPLD connects to the configuration pins of the Spartan Il FPGA so it can pass bitstreams from the parallel port to the FPGA The actual
28. can use your XSA Board in three ways distinguished by the method you use to apply power to the board Only use one of these methods to power your XSA Board Supplying power from multiple sources can damage the board and or power supplies Using 9VDC wall mount power supply You can use your XSA Board all by itself to experiment with logic designs Just place the XSA Board on a non conducting surface as shown in Figure 1 Then apply power to jack J5 of the XSA Board from a 9V DC wall mount power supply with a 2 1 mm female center positive plug See Figure 2 the location of jack J5 on your XSA Board The on board voltage regulation circuitry will create the voltages required by the rest of the XSA Board circuitry Be carefull The voltage regulators on the XSA Board will become hot Attach a heat sink to them if necessary Powering Through the PS 2 Connector You can use your XSA Board with a laptop PC by connecting a PS 2 male to male cable from the PS 2 port of the laptop to the J4 connector You must also have a shunt across pins 1 and 2 of jumper J7 The on board voltage regulation circuitry will create the voltages required by the rest of the XSA Board circuitry Many PS 2 ports cannot supply more than 0 5A so large fast FPGA designs may not work when using this power source Solderless Protoboard Installation The two rows of pins from your XSA Board can be plugged into a solderless protoboard with holes spaced at 0 1 intervals
29. configuration data is presented to the FPGA on the same 8 bit bus that also connects to the Flash RAM and seven segment LED The CPLD also drives the configuration pins CCLK PROGRAM CS and WR of the FPGA that control the loading of a bitstream The CPLD uses the MO input of the FPGA to select either the slave serial or master select configuration mode M1 and M2 are already hard wired to VCC and GND respectively The CPLD can monitor the status of the bitstream download through the INIT DONE and BSY DOUT pins of the FPGA XSA BOARD V1 1 V1 2 USER MANUAL 25 CPLD also has access to the FPGA s JTAG pins TMS TDI The TMS TDI and TDO pins share the connections with the BSY DOUT CS and WR pins With these connections the CPLD can be programmed with an interface that allows configuration of the Spartan Il FPGA through the Xilinx IMPACT software Jumper J9 allows the connection of status pin S7 to the general purpose CPLD pin that also drives status pin S5 This is required by the iMPACT software so it can check for the presence of the downloading cable FLASH RAM B XC9572XL Spartan ll FPGA Parallel Port D7 DO 2 PPDO 3 PPD o o 4 PPD2 CCLK 5 PPD3 PROGRAM 6 PPD4 7 PPD5 MO 8 PPD6 A AN M1 9 PPD7 M2 47 PRS TDI zm 16 PPC2 TMS AUR 14 PPC1 gt gt BSY DOUT 11 PPS7
30. e data in the files will overwrite each other if their address ranges overlap 3 If any file is highlighted in the FPGA CPLD area then this bitstream is loaded into the FPGA or CPLD on the XSA Board Otherwise the FPGA remains configured as an interface between the PC and the SDRAM You can also examine the contents of the SDRAM device by uploading it to the PC To upload data from an address range in the SDRAM type the upper and lower bounds of the range into the High Address and Low Address fields below the RAM area and select the format in which you would like to store the data using the Upload Format pulldown list Then click on the file icon and drag amp drop it into any folder This activates the following sequence of steps XSA BOARD V1 1 V1 2 USER MANUAL 17 1 FPGA on the XSA Board is reprogrammed to create an interface between the RAM device and the PC parallel port This interface is stored in the ram100 bit ram50 bit bitstream file located within the XSTOOLS XSA folder 2 The SDRAM data between the high and low addresses inclusive is uploaded through the parallel port 3 The uploaded data is stored in a file named RAMUPLD with an extension that reflects the file format X gxsload The 16 bit data words in the SDRAM are mapped into the eight bit data format of the MCS EXO and XES files using a Big Endian style That is the 16 bit word a
31. inx IMPACT software reprogramming the clock frequency on your XSA Board see page 1 changing the power sources for the XSA supply voltages XSA BOARD V1 1 V1 2 USER MANUAL 9 J10 e Table 2 Jumper settings for XSA Boards Setting Purpose On A shunt should be installed if the 2 5V supply voltage is derived from the 3 3V supply default Off The shunt should be removed if the 2 5V supply voltage is applied from an external source through pin 22 of the XSA Board labeled 2 5V at the lower right hand corner of the board 1 2 set shunt should be installed on pins 1 and 2 set when setting the frequency of the programmable oscillator 2 3 osc shunt should be installed on pins 2 and 3 osc during normal operations when the programmable default oscillator is generating a clock signal 1 2 The shunt should be installed on pins 1 and 2 if the 3 3V supply voltage is derived from the 5V default supply 2 3 The shunt should be installed on pins 2 and if the 3 3V supply voltage is derived from the 9VDC supply applied through jack J5 1 2 xi The shunt should be installed on pins 1 and 2 xi if the XSA Board is to be downloaded using the Xilinx IMPACT software 2 3 xs The shunt should be installed on pins 2 and 3 xs if the XSA Board is to be downloaded using the default XESS GXSLOAD software N A This is a header that provides access to the 5V and GND references
32. le included with your XSA Board connects it to a PC One end of the cable attaches to the parallel port on the PC and the other connects to the female DB 25 connector J8 at the top of the XSA Board as shown in Connecting a VGA Monitor to Your XSA Board You can display images on a VGA monitor by connecting it to the 15 pin J3 connector at the bottom of your XSA Board see Figure 1 You will have to create a VGA driver circuit for your XSA Board to actually display an image See for details on the VGA port circuitry and creating a VGA display circuit Connecting a Mouse or Keyboard to Your XSA Board You can accept inputs from a keyboard or mouse by connecting it to the PS 2 port at the bottom of your XSA Board see You will have to create a keyboard or mouse XSA BOARD V1 1 V1 2 USER MANUAL interface circuit to actually receive information on keystrokes or mouse movements See this section for details on the PS 2 port circuitry and creating a keyboard interface Inserting the XSA Board into an XStend Board If you purchased the optional XST 2 x Board then the XSA Board is inserted as shown below Refer to the XST 2 x Board Manual for more details Setting the Jumpers on Your XSA Board The default jumper settings shown Table 2 configure your XSA Board for use in a logic design environment You will need to change the jumper settings only if you are m downloading FPGA bitstreams to your XSA Board using the Xil
33. n Your XSA Board The Spartan ll FPGA on the XSA Board stores its configuration in an on chip SRAM which is erased whenever power is removed Once your design is finished you may want to store the bitstream in the 256 KByte Flash device on the XSA Board which configures the FPGA for operation as soon as power is applied Before downloading to the Flash the FPGA BIT file must be converted into a EXO or MCS format using one of the following commands promgen 0 file bit p exo s 256 promgen 0 file bit p mcs s 256 In the commands shown above the bitstream in the file bit file is transformed into an EXO or MCS file format starting at address zero and proceeding upward until an upper limit of 256 KBytes is reached Before attempting to program the Flash you must place all four DIP switches into the OFF position After the EXO or MCS file is generated it is loaded into the Flash device by dragging it into the Flash EEPROM area and clicking on the Load button This activates the following sequence of steps 1 The entire Flash device is erased 2 The CPLD on the XSA Board is reprogrammed to create an interface between the Flash device and the PC parallel port This interface is stored in the fintf svf bitstream file located within the XSTOOLSWSA folder 3 The contents of the EXO or MCS file are downloaded into the Flash through the parallel port 4 The CPLD is reprogrammed to create a circuit that config
34. n the XSA Board 100 MHz Programmable Oscillator A Dallas 051075 programmable oscillator provides a clock signal to both the FPGA and the CPLD The DS1075 has a maximum frequency of 100 MHz that is divided to provide frequencies of 100 MHz 50 MHz 33 3 MHz 25 MHz 48 7 KHz The clock signal from the DS1075 is connected to a dedicated clock input of the CPLD The CPLD passes the clock signal on to the FPGA This allows the CPLD to control the clock source for the FPGA XSA BOARD V1 1 V1 2 USER MANUAL 20 set the divisor value the 051075 must be placed its programming mode This is done by pulling the clock output to 5V on power up with a shunt across pins 1 and 2 of jumper J6 Then programming commands to set the divisor are sent to the DS1075 through control pin CO of the parallel port The divisor is stored in EEPROM in the DS1075 so it will be retained even when power is removed from the XSA Board The shunt on jumper J6 must be across pins 2 and 3 to make the oscillator output a clock signal upon power up The clock signal enters a dedicated clock input of the CPLD Then the CPLD can output a clock signal to a dedicated clock input of the FPGA To get a precise frequency value or to sync the XSA circuitry with an external system you can insert an external clock signal of up to 50 MHz through pin 64 of the prototyping header This external clock takes the place of the internal 100 MHz clock source in the DS1075 o
35. on the board No shunt should be placed on this header Testing Your XSA Board Once your XSA Board is installed and the jumpers are in their default configuration you can test the board using the GUI based GXSTEST utility as follows You start GXSTEST by clicking on the icon placed on the desktop during the XSTOOLS installation This brings up the window shown below X gxstest Board Type x51 00 Port Ga Exit Next you select the parallel port that your XSA Board is connected to from the Port pulldown list GXSTEST starts with parallel port LPT1 as the default but you can also select LPT2 or LPT3 depending upon the configuration of your PC After selecting the parallel port you select either the XSA 50 or XSA 100 item in the Board Type pulldown list Then click on the TEST button to start the testing procedure GXSTEST will configure the FPGA to perform a test procedure on your XSA Board Within thirty seconds you will see a O displayed on the LED digit if the test completes successfully Otherwise an E will be displayed if the test fails A status window will also appear on your PC screen informing you of the success or failure of the test XSA BOARD V1 1 V1 2 USER MANUAL 10 If your XSA Board fails the test you will be shown checklist of common causes for failure If none of these causes applies to your situation then test the XSA Board using another PC In our experience 99 9 of all problems are due
36. scillator You must use the GXSSETCLK software utility to enable the external clock input of the DS1075 Clock signals can also be directly applied to two of the dedicated clock inputs of the FPGA through the pins of the prototyping header 5V A PP CO gt 14 J6 Pin 64 1075 2 3 17 42 88 18 Pin 1 pia XC9572XL Spartan Il 5 CPLD FPGA 15 Pin 31 Synchronous DRAM The various SDRAM organizations and manufacturers used on the XSA Boards are given in the following table SDRAM Board Organization Manufacturer amp Part No 4M x 16 nix HY57V641620HGT XSA 50 4M x 16 Samsung K4S641632F TC75000 8M x 16 HY57V281620HCT XSA 100 8M x 16 Samsung 45281632 75000 XSA BOARD V1 1 V1 2 USER MANUAL 21 The SDRAM is connected to the FPGA as shown below Currently FPGA 133 drives no connect pin of the SDRAM but this could be used in the future as the thirteenth row column address bit of a larger SDRAM Also the SDRAM clock signal is re routed back to a dedicated clock input of the FPGA to allow synchronization of the FPGA s internal operations with the SDRAM operations This describes an SDRAM controller that makes the SDRAM appear like a simple static RAM to the rest of the circuitry in the FPGA BO0OO0 NP N OO lt O A
37. select either XSA 50 or XSA 100 in the Board Type pulldown list Next you enter a divisor between 1 and 2052 into the Divisor text box and then click on the SET button Then follow the sequence of instructions given by XSSETCLK for moving shunts and removing and restoring power during the oscillator programming process At the completion of the process the new frequency will be programmed into the DS1075 An external clock signal can be substituted for the internal 100 MHz oscillator of the DS1075 Checking the External Clock checkbox will enable this feature in the programmable oscillator chip If this option is selected you are then responsible for providing the external clock to the XSA Board through pin 64 labeled CLK at the upper left hand corner of the board XSA BOARD V1 1 V1 2 USER MANUAL 11 Programming This section will show you how to download a logic designs into the FPGA and CPLD of your XSA Board and how to download and upload data to and from the SDRAM and Flash devices on the board Downloading Designs into the FPGA and CPLD of Your XSA Board Downloading Using GXSLOAD During the development and testing phases you will usually connect the XSA Board to the parallel port of a PC and download your circuit each time you make changes to it You can download a Spartan Il FPGA design into your XSA Board using the GXSLOAD utility as follows You start GXSLOAD by clicking on the icon placed on the desktop during the
38. t address N in the SDRAM is stored in the eight bit file with the upper eight bits at location 2N and the lower eight bits at location 2N 1 This byte ordering applies for both RAM uploads and downloads XSA BOARD V1 1 V1 2 USER MANUAL 18 Programmer s Models This section describes the various sections of the XSA Board and shows how the of the FPGA and CPLD are connected to the rest of the circuitry The schematics which follow are less detailed so as to simplify the descriptions Please refer to the complete schematics at the end of this document if you need more details The XSA Board contains the following components XSA Board Organization 2550 or XC28100 Spartan Ill FPGA This is the main repository of programmable logic on the XSA Board XC9572XL CPLD This CPLD manages the interface between the PC parallel port and the rest of the XSA Board Osc A programmable oscillator generates the master clock for the XSA Board Flash A 128 or 256 KByte Flash device provides non volatile storage for data and configuration bitstreams SDRAM An 8 or 16 MByte SDRAM provides volatile data storage accessible by the FPGA LED A seven segment LED allows visible feedback as the XSA Board operates DIP switch A four position DIP switch passes settings to the XSA Board or controls the upper address bits of the Flash device Pushbutton A single pushbutton sends momentary contact information to the FPGA Parallel Port
39. t it for downloading Only one file at a time can be selected for downloading X gxsload ram 00 bit dwnidpar Double clicking the highlighted file will deselect it so no file will be downloaded Doing this disables the Load button X gxsload Downloading Using Xilinx iMPACT You can use the Xilinx iMPACT software to download bitstreams to the XSA Board The iMPACT programming tool downloads bitstreams through the JTAG interface of the FPGA so we need to change the parallel port interface by reprogramming the CPLD Drag amp drop the p3jtag svf file from the XSTOOLS XSA 50 folder into the FPGA CPLD pane of the GXSLOAD window Then click on the Load button and the CPLD will be reprogrammed in less than a minute Then move the shunt on jumper J9 from the XS to the XI position At this point you can start iMPACT it will believe it is connected to the XSA BOARD V1 1 V1 2 USER MANUAL 14 XSA Board through Xilinx Parallel Cable III in boundary scan mode Follow the instructions for IMPACT to download bitstreams to the FPGA Note that the CPLD only needs to be reprogrammed once to support iMPACT because it retains its configuration even when power is removed from the board If you want to go back to using the GXSLOAD programming utility just must move the shunt on J9 back to the XS position and download the XSTOOLS XSA 50 dwnidpar svf file into the CPLD Storing Non Volatile Designs i
40. to the parallel port If you cannot get your board to pass the test even after taking these steps then contact XESS Corp for further assistance As a result of testing the XSA Board the CPLD is programmed with the standard parallel port interface found in the dwnldpar svf bitstream file located within the XSTOOLS XSA folder This is the standard interface that should be loaded into the CPLD when you want to use it with the GXSLOAD utility Setting the XSA Board Clock Oscillator Frequency The XSA Board has a 100 MHz programmable oscillator a Dallas Semiconductor DS1075Z 100 100 MHz master frequency can be divided by factors of 1 2 up to 2052 to get clock frequencies of 100 MHz 50 MHz down to 48 7 KHz respectively The divided frequency is sent to the rest of the XSA Board circuitry as a clock signal The divisor is stored in non volatile memory in the oscillator chip so it will resume operation at its programmed frequency whenever power is applied to the XSA Board You can store a particular divisor into the oscillator by using the GUI based GXSSETCLK as follows You start GXSSETCLK by clicking on the icon placed on the desktop during the XSTOOLS installation This brings up the window shown below Board Type XS4 100 SET Port 21 Divisor External Clock E Your next step is to select the parallel port that your XSA Board is connected to from the Port pulldown list Then
41. upport htm If you need help using the WebPACK software to create designs for your XSA Board then check out this kutorial Take notice The XSA Board requires an external power supply to operate It does not draw power through the downloading cable from the PC parallel port If you are connecting a 9VDC power supply to your XSA Board please make sure the center terminal of the plug is positive and the outer sleeve is negative Do not power your XSA Board with a battery This will not provide enough current to insure reliable operation of the XSA Board XSA BOARD V1 1 V1 2 USER MANUAL 4 Packing List Here is what you should have received in your package an XSA Board m a6 cable with a 25 pin male connector on each end m anXSTOOLS CDROM with software utilities and documentation for using the XSA Board XSA BOARD V1 1 V1 2 USER MANUAL 5 Installation Installing the XSTOOLS Utilities and Documentation Xilinx currently provides the WebPACK tools for programming their CPLDs and Spartan ll FPGAs The XESS CDROM contains a version of WebPACK that will generate bitstream configuration files compatible with your XSA Board You can also the most current version of the WebPACK tools from the Xilinx website In addition XESS Corp provides the XSTOOLS utilities for interfacing a PC to your XSA Board Run the SETUP EXE program on the XSTOOLS CDROM to install these utilities Applying Power to Your XSA Board You
42. ures the FPGA with the contents of the Flash when power is applied to the XSA Board This configuration loader is stored in the fcnfg svf bitstream file located within the XSTOOLS XSA folder Multiple files can be stored in the Flash device just by dragging them into the Flash EEPROM area highlighting the files to be downloaded and clicking the Load button Note that anything previously stored in the Flash will be erased by each new download XSA BOARD V1 1 V1 2 USER MANUAL 15 This is useful if you need to store information in the Flash in addition to the FPGA bitstream Files are selected and de selected for downloading just by clicking on their names in the Flash EEPROM area The address ranges of the data in each file should not overlap or this will corrupt the data stored in the Flash device You can also examine the contents of the Flash device by uploading it to the PC To upload data from an address range in the Flash type the upper and lower bounds of the range into the High Address and Low Address fields below the Flash EEPROM area and select the format in which you would like to store the data using the Upload Format pulldown list Then click on the file icon and drag amp drop it into any folder This activates the following sequence of steps 1 The CPLD on the XSA Board is reprogrammed to create an interface between the Flash device and the PC parallel port 2 The Flash data between the high and low addresses inclusive
43. urpose I O after the FPGA is configured If external logic is connected to these pins you may have to disable it during the configuration process The DONE pin 72 can be used for this purpose since it goes to a logic high only after the configuration process is completed Flash RAM Pins 27 28 29 39 40 41 42 43 44 46 47 48 49 50 5177 54 56 57 58 59 60 62 63 64 65 66 67 74 75 76 These pins are used by the FPGA to access the Flash RAM They can be used for general purpose I O under the following conditions When the FPGA is configured from the Flash the CPLD drives all these pins so any external logic should be disabled using the DONE pin Also after the configuration the Flash chip enable 41 should be driven high to disable the Flash RAM so it doesn t drive the data bus pins In addition the standard parallel port interface loaded into the CPLD dwnldpar svf will drive eight of the Flash RAM pins 42 43 47 48 50 51 58 65 with the logic values found on the eight data lines of the parallel port If this is not desired then use the alternate parallel port interface dwnldpa2 svf which does not drive these pins VGA Pins 12 13 19 20 217 22 23 26 When not used to drive a VGA monitor these pins be used for general purpose I O through the prototyping header When used as I O the REDO RED1 12 13 GREENO GREEN 1 19 20 and BLUEO BLUE1 21 22 pairs ha
44. ve an impedance of approximately 1 KO between them due to the presence of the resistor ladder DAC circuitry PS 2 Pins 93 94 When not used to access the PS 2 keyboard mouse port these pins can be used as general purpose I O through the prototyping header Global Clock Pins 15 18 These pins can be used as global clock inputs general purpose inputs They cannot be used as outputs Free Pins 77 78 79 80 83 84 85 86 87 These pins are not connected to any other devices on the XSA Board so they can be used without restrictions as general purpose I O through the prototyping header JTAG Pins 2 32 34 142 These pins are used to access the JTAG features of the FPGA They cannot be used as general purpose pins XSA BOARD V1 1 V1 2 USER MANUAL 29 XSA Pin Connections The following tables list the pin numbers of the FPGA and CPLD along with the pin names of the other chips that they connect to on the XSA Board and the XStend Board The first two tables correspond to an XSA Board XST 2 x combination while the last two tables correspond to an XSA Board XST 1 x combination Pins marked with are useable as general purpose I O pins denoted with can be used as general purpose I O only if the CPLD interface is reprogrammed with the alternate parallel port interface stored in the dwnldpa2 svf file pins with no marking cannot be used as general purpose I O at all XSA BOARD V1 1 V1 2 USER MANUAL
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