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bdiGDB User Manual

1. from target system ees ze i e m e Switch ON the power supply for the BDI again and wait untilthe INIT MODE LED MODE blinks fast S We e Turn the power supply OFF again ae DEFAULT e Return the jumper to the DEFAULT position e Reassemble the unit as described in Appendix Maintenance Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC8 amp 5xx User Manual 17 2 6 Testing the BDI2000 to host connection After the initial setup is done you can test the communication between the host and the BDI2000 There is no need for a target configuration file and no TFTP server is needed on the host e If not already done connect the BDI2000 system to the network e Power up the BDI2000 e Start a Telnet client on the host and connect to the BDI2000 the IP address you entered dur ing initial configuration e If everything is okay a sign on message like BDI Debugger for Embedded PowerPC and a list of the available commands should be displayed in the Telnet window 2 7 TFTP server for Windows The bdiGDB system uses TFTP to access the configuration file and to load the application program Because there is no TFTP server bundled with Windows Abatron provides a TFTP server application tftpsrv exe This WIN32 console application runs as normal user application not as a system ser vice Command line syntax tftpsrv p w
2. BDI Type BDI2000 Rev C SN 92152150 Loader V1 05 Firmware V1 00 bdiGDB for MPC8500 Logic V1 02 PPC6xx PPC7xx MAC 00 Oc 01 92 15 21 IP Addr 151 120 25 101 Subnet t 25525532555255 Gateway 255 255 255 255 Host IP lt 151 120 25 118 Config mpc8560 cfg The Mode LED should go off and you can try to connect to the BDI via Telnet root LINUX_1 bdisetup telnet 151 120 25 101 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 15 2 5 2 Configuration with a Windows host First make sure that the BDI is properly connected see Chapter 2 1 to 2 4 A To avoid data line conflicts the BDI2000 must be disconnected from the target system while programming the logic for an other target CPU see Chapter 2 1 1 BDI2000 Update Setup r Connect BDI2Z000 Loader gt Channel SN 95111242 C Port cOM2 7 MAC 000C01951112 Speed 115200 e m BDI2000 Firmware Logic Current Newest Loader 1 05 Current Firmware 1 04 1 04 Logic 1 05 1 05 Jpdate Configuration BDI IP Address 151 120 25 101 Subnet Mask 255 255 255 255 Default Gateway 255 255 255 255 Config Host IP Address 151 120 25 119 Configuration file E cygwinhome bdidemoe500 cds8548 cfg Cancel Ok Transmit Writing setup data passed dialog box BDIZ000 Update Setup Before you can use the BDI2000 together with the GNU debugger you must
3. activate BDI2000 loader Get configuration file via TFTP Power OFF Process target init list Load program code via TFTP and set the PC RUN selected Start loaded program code Process GDB request Power OFF Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 19 Breakpoints There are 3 breakpoint modes supported One of them SOFT is implemented by replacing applica tion code with a TRAP instruction The other HARD uses the built in breakpoint logic If HARD is used only 2 breakpoint can be active at the same time The third mode LOOP replaces the code with an endless loop the processor does not enter debug mode until it is halted via Telnet of GDB The breakpoint mode LOOP does not depend on valid code at the Debug Interrupt Vector The following example selects SOFT as the breakpoint mode BREAKMODE SOFT SOFT HARD or LOOP HARD uses PPC hardware breakpoints Debug Interrupt IVOR15 Debugging via JTAG and flash programming with workspace works only if the Debug Interrupt Vector contains a valid instruction that can be fetched by the e500 core This because the e500 core does first interrupt processing before it halts If IVPR IVOR15 do not point to a valid and fetchable MMU instruction the e500 will crash If necessary for example for flash
4. RI lt nbr gt lt name gt lt value gt modify general purpose or user defined register RMSPR lt number gt lt value gt modify special purpose register RMPMR lt number gt lt value gt modify performance monitor register DCACHE lt addr set gt display L1 data cache content ICACHE lt addr setz display L1 inst cache content L2CACHE lt set gt display L2 cache content L2SRAM lt addr gt display L2 SRAM content L2TLB lt from gt lt to gt display L2 TLBO entry L2CAM lt from gt lt to gt display L2 TLB1 entry UPMR lt MxMR gt lt MDR gt lt addr gt read selected UPM array RESET LOOP HALT RUN time reset the target system change startup mode BREAK SOFT HARD display or set current breakpoint mode GO lt pc gt set PC and start target system TI lt pc gt trace on instuction single step TC lt pc gt trace on change of flow HALT force target to enter debug mode BI lt addr gt set instruction hardware breakpoint CE lt id gt clear instruction hardware breakpoint s BD R W lt addr gt set data watchpoint CD lt id gt clear data watchpoint s INFO display information about the current state LOAD lt offset gt lt file gt lt format gt load program file to target memory VERIFY lt offset gt lt file gt lt format gt verify a program file to target memory PROG lt offset gt lt file gt lt format gt program flash
5. Reinstallation 5 1 Slide back carefully the print Check that the LEDs align with the holes in the back panel 5 2 Push carefully the front panel and the red elastig sealing on the casing Check that the LEDs align with the holes in the front panel and that the position of the sealing is as shown in the figure below casing NS elastic sealing back panel ff front panel 5 3 Mount the screws do not overtighten it 5 4 Mount the two plastic caps that cover the screws 5 5 Plug the cables A ks Observe precautions for handling Electrostatic sensitive device Unplug the cables before opening the cover Use exact fuse replacement Microfuse MSF 1 6 AF Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 49 C Trademarks All trademarks are property of their respective holders Copyright 1997 2006 by ABATRON AG Switzerland V 1 05
6. MMU XLAT kb PTBASE addr 64BIT REGLIST list This parameter defines how single step instruction step is implemented The alternate step mode HWBP may be useful when stepping instruc tions that causes a TLB miss exception JTAG This is the default mode Single step is implemented by using the JTAG single step feature HWBP In this mode a hardware breakpoint on the next instruc tion is used to implement single stepping ICMP In this mode single step is implemented via the instruc tion complete ICMP debug event Example STEPMODE HWBP In order to support Linux kernel debugging when MMU is on the BDI translates effective virtual to physical addresses This translation is done based on the current MMU configuration page tables If this configuration line is present the BDI translates the addresses received from GDB be fore it accesses physical memory The optional parameter defines the ker nel virtual base address default is OxCO000000 and is used for default address translation For more information see also chapter Embedded Linux MMU Support Addresses entered at the Telnet are never translat ed Translation can be probed with the Telnet command PHYS If not zero the 12 lower bits of kb defines the position of the page present bit in a page table entry By default 0x800 is assumed for the page present bit The position may depend on the Linux kernel version kb The kernel virtual base address KERNELBASE
7. 8 none 1 10 BASE T up to 16 Mbit s 1 8 5 0 V 3 0 5 0 V with Rev B 5 60 C 20 65 C lt 90 rF 190 x 110 x 35 mm 420g 2 5m Specifications subject to change without notice Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 44 5 Environmental notice A Ga Disposal of the equipment must be carried out at a designated disposal site 6 Declaration of Conformity CE LE DECLARATION OF CONFORMITY This declaration is valid for following product Type of device BDM JTAG Interface Product name BDI2000 The signing authorities state that the above mentioned equipment meets the requirements for emission and immunity according to EMC Directive 89 336 EEC The evaluation procedure of conformity was assured according to the following standards EN 50081 2 EN 50082 2 This declaration of conformity is based on the test report no QNL E853 05 8 a of QUINEL Zug accredited according to EN 45001 Manufacturer ABATRON AG St ckenstrasse 4 CH 6221 Rickenbach Authority VOL LY yew ZG Ss MMMM CE Max Vock Ruedi Dummermuth Marketing Director Technical Director Rickenbach May 30 1998 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 45 7 Warranty ABATRON Switzerland warrants the physical diskette cable BDI2000 and physi
8. PowerPC MPC85xx User Manual 22 RM8 address value Read a byte 8bit from the selected memory place address the memory address Example RM8 0x00000000 RM16 address value Read a half word 16bit from the selected memory place address the memory address Example RM16 0x00000000 RM32 address value Read a word 32bit from the selected memory place address the memory address Example RM32 0x00000000 RM64 address value Read a double word 64bit from the selected memory place address the memory address Example RM64 0x00000000 SUPM memadar mdraddr Starts a sequence of writes to the UPM RAM array MPC85xx memaddr an address in the UPM memory range mdradadr the address of the MDR register Example WM32 0x40005018 0x10000081 BR3 WM32 0x40005070 0x10000000 MAMR setup SUPM 0x10000000 0x40005088 WUPM dummy data Write to the UPM RAM array mdraddr data memaddr 0 dummy this value is not used here use 0 data this value is written to the UPM data register Example WUPM 0 OxOFFFEC04 TSZ1 start end Defines a memory range with 1 byte maximal transfer size Normally when the BDI reads or writes a memory block it tries to access the memory with a burst access The TSZx entry allows to define a maxi mal transfer size for up to 8 address ranges start the start address of the memory range end the end address of the memory range Example TSZ1 0xFF000000 OxFFFFFFFF PCI ROM space TSZ2 start end Defines a memory range with
9. The firmware can not be loaded Possible reasons e The BDI is not correctly connected with the target system see chapter 2 e The power supply of the target system is switched off or not in operating range 4 75 VDC 5 25 VDC gt MODE LED is OFF or RED e The built in fuse is damaged gt MODE LED is OFF e The BDI is not correctly connected with the Host see chapter 2 e A wrong communication port Com 1 Com 4 is selected Problem No working with the target system loading firmware is ok Possible reasons e Wrong pin assignment BDM JTAG connector of the target system see chapter 2 e Target system initialization is not correctly gt enter an appropriate target initialization list e An incorrect IP address was entered BDI2000 configuration BDM JTAG signals from the target system are not correctly short circuit break e The target system is damaged Problem Network processes do not function loading the firmware was successful Possible reasons e The BDI2000 is not connected or not correctly connected to the network LAN cable or media converter e An incorrect IP address was entered BDI2000 configuration Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 47 B Maintenance The BDI needs no special maintenance Clean the housing with a mild detergent only Solvents such as gasoline may damage it If the BDI is connected correctly and
10. write UPM array WUP 0x00000000 Oxaba00001 WUP 0x00000000 Oxaba00002 WUP 0x00000000 Oxaba00003 WUP 0x00000000 Oxaba00004 WUP 0x00000000 Oxaba0003A WUP 0x00000000 Oxaba0003B WUP 0x00000000 Oxaba0003C WUP 0x00000000 Oxaba0003D WUP 0x00000000 Oxaba0003E WUP 0x00000000 Oxaba0003F WM32 0x40005070 0x00000000 MAMR setup for normal mode Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 24 3 2 2 Part TARGET The part TARGET defines some target specific values CPUTYPE type JTAGCLOCK value POWERUP delay RESET type time WAKEUP time This value gives the BDI information about the connected CPU type 8540 8560 8555 8541 8548 8547 8545 8543 Example CPUTYPE 8560 With this value you can select the JTAG clock rate the BDI2000 uses when communication with the target CPU value 0 16 6 MHz 4 500 kHz 7 50 kHz 1 8 3 MHz 5 200 kHz 8 20 kHz 2 4 1 MHz 6 100 kHz 9 10 kHz 3 1 0 MHz 10 5 kHz Example CLOCK 1 JTAG clock is 8 3 MHz When the BDI detects target power up HRESET is forced immediately This way no code from a boot ROM is executed after power up The value entered in this configuration line is the delay time in milliseconds the BDI waits before it begins JTAG communication This time should be longer than the on board reset circuit asserts HRESET delay the power up start delay in milliseconds Example POWE
11. 48 pidl SPR 633 pid2 SPR 634 spefscr SPR 512 tlb0cfg SPR 688 tlblicfg SPR 689 Local Bus Controller bro CCSR 0x05000 br1 CCSR 0x05008 br2 CCSR 0x05010 br3 CCSR 0x05018 lteatr CCSR 0x050BC ltear CCSR 0x050C0 lbcr CCSR 0x050D0 IGF CCSR 0x050D4 Now the defined registers can be accessed by name via the Telnet interface BDI gt rd csrr0 BDI gt rm brO 0x00000801 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 86 3 3 Debugging with GDB Because the target agent runs within BDI no debug support has to be linked to your application There is also no need for any BDI specific changes in the application sources Your application must be fully linked because no dynamic loading is supported 3 3 1 Target setup Target initialization may be done at two places First with the BDI configuration file second within the application The setup in the configuration file must at least enable access to the target memory where the application will be loaded Disable the watchdog and setting the CPU clock rate should also be done with the BDI configuration file Application specific initializations like setting the timer rate are best located in the application startup sequence 3 3 2 Connecting to the target As soon as the target comes out of reset BDI initializes it and loads your application code If RUN is selected the application is immediately started otherwise only the targ
12. 7 RTS 8 CTS 9 RI XXX BDI Output m The configuration parameter SIO is used to enable this serial I O routing The used framing parameters are 8 data 1 stop and not parity The BDI asserts RTS and DTR when a TCP connection is established Ethernet 10 BASE T E TARGET SIO 7 9600 Enable SIO via TCP port 7 at 9600 baud Warning Once SIO is enabled connecting with the setup tool to update the firmware will fail In this case either disable SIO first or disconnect the BDI from the LAN while updating the firmware Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 89 3 3 6 Embedded Linux MMU Support The bdiGDB system supports Linux kernel debugging when MMU is on The MMU configuration pa rameter enables this mode of operation In this mode all addresses received from GDB are assumed to be virtual Before the BDI accesses memory it translates this address into a physical one based on information found in the kernel user page table In order to search the page tables the BDI needs to know the start addresses of the first level page table The configuration parameter PTBASE defines the physical address where the BDI looks for the virtual address of an array with two virtual addresses of first level page tables The first one points normally to the kernel page table the second one can point to the curre
13. chips e g 28F800C3 28F160C3 28F320C3 power up with all blocks in locked state In order to erase program those flash chips use the init list to unlock the appropriate blocks WM16 OxFFF00000 0x0060 unlock block 0 WM16 OxFFF00000 0x00D0 WM16 OxFFF 10000 0x0060 unlock block 1 WM16 OxFFF10000 0x00D0 WM16 OxFFF00000 OxFFFF select read mod or use the Telnet Unlock command UNLOCK lt addr gt lt delay gt addr This is the address of the sector block to unlock delay A delay time in milliseconds the BDI waits after sending the unlock com mand to the flash For example clearing all lock bits of an Intel J3 Strata flash takes up to 0 7 seconds If unlock is used without any parameter all sectors in the erase list with the UNLOCK option are processed To clear all lock bits of an Intel J3 Strata flash use for example BDI gt unlock OxFF000000 1000 To erase or unlock multiple continuos flash sectors blocks of the same size the following Telnet commands can be used ERASE lt addr gt lt step gt lt count gt UNLOCK lt addr gt lt step gt lt count gt addr This is the address of the first sector to erase or unlock step This value is added to the last used address in order to get to the next sec tor In other words this is the size of one sector in bytes count The number of sectors to erase or unlock The following example unlocks all 256 sectors of an Intel Strata flash 28F256K3 tha
14. it is still not responding then the built in fuse might be damaged in cases where the device was used with wrong supply voltage or wrong polarity To exchange the fuse or to perform special initialization please proceed according to the following steps A ks Observe precautions for handling Electrostatic sensitive device Unplug the cables before opening the cover Use exact fuse replacement Microfuse MSF 1 6 AF 1 1 Unplug the cables Swiss Made BDI2000 AG F 2 1 Remove the two plastic caps that cover the screws on target front side e g with a small knife 2 2 Remove the two screws that hold the front panel BDI OPTION BDI MAIN BDI TRGT MODE 3 1 While holding the casing remove the front panel and the red elastig sealing casing NS elastic sealing front panel Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 l for BDIZ000 PowerPC MPC85xx User Manual 48 4 1 While holding the casing slide carefully the print in position as shown in figure below mag Jumper settings o We om DEFAULT INIT MODE Fuse Position Fuse Position Version B Version A e BS Pull out carefully the fuse and replace it a Type Microfuse MSF 1 6AF Manufacturer Schurter
15. memory lt format gt SREC BIN AOUT or ELF ERASE lt address gt lt mode gt erase a flash memory sector chip or block lt mode gt CHIP BLOCK or SECTOR default is sector ERASE lt addr gt lt step gt lt count gt erase multiple flash sectors UNLOCK lt addr gt lt delay gt unlock a flash sector UNLOCK lt addr gt lt step gt lt count gt unlock multiple flash sectors FLASH lt type gt lt size gt lt bus gt change flash configuration DELAY lt ms gt delay for a number of milliseconds HOST lt ip gt change IP address of program file host PROMPT lt string gt defines a new prompt string CONFIG display or update BDI configuration CONFIG lt file gt lt hostIP gt lt bdiIP gt lt gateway gt lt mask gt HELP display command list BOOT reset the BDI and reload the configuration QUIT terminate the Telnet session Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 43 4 Specifications Operating Voltage Limiting Power Supply Current RS232 Interface Baud Rates Data Bits Parity Bits Stop Bits Network Interface Serial Transfer Rate between BDI and Target Supported target voltage Operating Temperature Storage Temperature Relative Humidity noncondensing Size Weight without cables Host Cable length RS232 5 VDC 0 25 V typ 500 mA max 1000 mA 9 600 19 200 38 400 57 600 115 200
16. programming setup a valid Debug Interrupt Vector via some init list entries Setup flash programming workspace in L2SRAI WM32 0x40020000 0x68010000 L2CTL WM32 0x40020100 Ox 0000000 L2SRBARO WM32 0x40020000 0xA8010000 L2CTL WSPR 63 Oxf0000000 IVPR to workspace WSPR 415 0x0001500 IVOR15 Debug exception WM32 0x 0001500 0x48000000 jwrite valid instruction Because a Debug Interrupt writes to CSRRO and CSRR1 it is not possible to debug the entry exit code of a critical interrupt handler with breakpoint mode SOFT or HARD Target Reset Sequence STARTUP LOOP mode In order to get control of the core immediately out of reset the BDI uses a special startup sequence where L2SRAM is mapped to the initial boot page and an endless loop is written to Oxfffffffc This is done while the core is still kept in reset state Then the core is released and starts executing this loop at Oxfffffffc until the BDI halts it via the appropriate JTAG command Therefore after a reset sequence L2SRAM is mapped to OxfffcO000 Oxffffffff To disable this mapping enter the appropriate init list en try that disables LAESRAM WM32 OxFF720000 0x20000000 L2CTL disable L2SRAM Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 20 3 2 Configuration File The configuration file is automatically read by the BDI after every power on The syntax of this file is as follows comment
17. store the initial config uration parameters in the BDI2000 flash memory The following options allow you to do this Port Select the communication port where the BDI2000 is connected during this setup session Speed Select the baudrate used to communicate with the BDI2000 loader during this setup session Connect Click on this button to establish a connection with the BDI2000 loader Once connected the BDI2000 remains in loader mode until it is restarted or this dialog box is closed Current Press this button to read back the current loaded BDI2000 software and logic versions The current loader firmware and logic version will be displayed Update This button is only active if there is a newer firmware or logic version present in the execution directory of the bdiGDB setup software Press this button to write the new firmware and or logic into the BDI2000 flash mem ory programmable logic Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 16 BDI IP Address Subnet Mask Default Gateway Config Host IP Address Configuration file Transmit Enter the IP address for the BDI2000 Use the following format XXX XXX XXX XXX 9 151 120 25 101 Ask your network administrator for assigning an IP address to this BDI2000 Every BDI2000 in your network needs a different IP address Enter the subnet mask of the network where the BDI is connected to Use the follow
18. the AMD status bit 5 Exceeded Timing Limits Only the AMD and AT49 algorithm support chip erase Block erase is only supported with the AT49 algorithm If the algorithm does not support the selected mode sector erase is performed If the chip does not support the selected mode erasing will fail The erase command sequence is different only in the 6th write cycle Depending on the selected mode the following data is written in this cycle see also flash data sheets 0x10 for chip erase 0x30 for sector erase 0x50 for block erase To speed up programming of Intel Strata Flash and AMD MirrorBit Flash an additional algorithm is implemented that makes use of the write buffer This algorithm needs a workspace otherwise the standard Intel AMD algorithm is used The following table shows some examples Chipsize Am29F010 AM29F 5 S 0x020000 Am29F800B AM29BX8 AM29BX16 S 0x100000 Am29DL323C AM29BX8 AM29BX16 0x400000 Am29PDL128G AM29DX16 AM29DX32 0x01000000 Intel 28F032B3 I28BX8 S S 0x400000 Intel 28F640J3A STRATAX8 STRATAX16 0x800000 Intel 28F320C3 128BX16 E 0x400000 AT49BV040 AT49 0x080000 AT49BV1614 AT49X8 AT49X16 S 0x200000 M58BW016BT M58X32 0x200000 SST39VF160 AT49X16 0x200000 Am29LV320M MIRRORX8 MIRRORX16 S 0x400000 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 33 Note Some Intel flash
19. 0 ERASE OxFF9c0000 Flash type D D The size of one flash chip in bytes e g AM29F010 0x20000 The width of the flash memory bus in bits 8 16 32 64 workspace in dual port RAM FILE E gnu demo ads8260 bootrom hex The file to program erase sector 4 of flash SIMM LH28F016SCT erase sector 5 of flash SIM erase sector 6 of flash SIM erase sector 7 of flash SIM the above erase list maybe replaces with ERASE OxFF 900000 Ox40000 4 erase sector 4 to 7 of flash SIMM Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 32 Supported Flash Memories There are currently 3 standard flash algorithm supported The AMD Intel and Atmel AT49 algorithm Almost all currently available flash memories can be programmed with one of this algorithm The flash type selects the appropriate algorithm and gives additional information about the used flash For 8bit only flash AM29F MIRROR I28BX8 AT49 For 8 16 bit flash in 8bit mode AM29BX8 MIRRORX8 I28BX8 STRATAX8 AT49X8 For 8 16 bit flash in 16bit mode AM29BX16 MIRRORX16 I28BX16 STRATAX16 AT49X16 For 16bit only flash AM29BX16 I28BX16 AT49X16 For 16 32 bit flash in 16bit mode AM29DX16 For 16 32 bit flash in 32bit mode AM29DX32 For 32bit only flash M58X32 The AMD and AT49 algorithm are almost the same The only difference is that the AT49 algorithm does not check for
20. 006 by ABATRON AG Switzerland V 1 05 ldi for BDIZ000 PowerPC MPC85xx User Manual 42 The Telnet commands PHYS lt address gt converts an effective to a physical address MD lt address gt lt count gt display target memory as word 32bit MDD lt address gt lt count gt display target memory as double word 64bit MDH lt address gt lt count gt display target memory as half word 16bit MDB lt address gt lt count gt display target memory as byte 8bit DUMP lt addr gt lt size gt lt file gt dump target memory to a file MM lt addr gt lt value gt lt cnt gt modify word s 32bit in target memory MMD lt addr gt lt value gt lt cnt gt modify double word s 64bit in target memory MMH lt addr gt lt value gt lt cnt gt modify half word s 16bit in target memory MMB lt addr gt lt value gt lt cnt gt modify byte s 8bit in target memory MC lt address gt lt count gt calculates a checksum over a memory range MV verifies the last calculated checksum RD lt name gt display general purpose or user defined register RDUMP lt file gt dump all user defined register to a file RDSPR lt number gt display special purpose register RDP lt number gt display performance monitor register
21. 2 byte maximal transfer size TSZ4 start end Defines a memory range with 4 byte maximal transfer size TSZ8 start end Defines a memory range with 8 byte maximal transfer size MMAP start end Because a memory access to an invalid memory space via JTAG can lead to a deadlock this entry can be used to define up to 32 valid memory rang es If at least one memory range is defined the BDI checks against this range s and avoids accessing of not mapped memory ranges start the start address of a valid memory range end the end address of this memory range Example MMAP OxFFEQ0000 OxFFFFFFFF Boot ROM Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 23 EXEC addr time This entry cause the processor to start executing the code at addr The op tional second parameter defines a time in us how long the BDI let the pro cessor run until it is halted By default the BDI let it run for 500 us This EXEC function maybe used to create TLB entries via some helper code addr the start address of the code to execute time the time the BDI let the processor run micro seconds Example EXEC OxFFFFFOOO write the TLB entry Example how to write to the UPM array WM32 0x4000501C OxFF000000 7 OR3 WM32 0x40005018 0x10000081 BR3 WM32 0x40005070 0x10000000 MAMR setup for array write SUP 0x10000000 0x40005088 set address of UPM range and MDR WUP 0x00000000 Oxaba00000
22. 90 2599 255 Gateway 255 255 255 255 Host IP 255 255 255 255 Config 22222222222222722 3 Load Update the BDI firmware logic With bdisetup u the firmware is loaded and the CPLD within the BDI2000 is programmed This con figures the BDI for the target you are using Based on the parameters a and t the tool selects the correct firmware logic files If the firmware logic files are in the same directory as the setup tool there is no need to enter a d parameter root LINUX_1 bdisetup bdisetup u p dev ttyS0O b57 aGDB tMPC8500 Connecting to BDI loader Erasing CPLD Programming firmware with b20pwsgd 100 Programming CPLD with copjed21 102 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 14 4 Transmit the initial configuration parameters With bdisetup c the configuration parameters are written to the flash memory within the BDI The following parameters are used to configure the BDI BDI IP Address The IP address for the BDI2000 Ask your network administrator for as signing an IP address to this BDI2000 Every BDI2000 in your network needs a different IP address Subnet Mask The subnet mask of the network where the BDI is connected to A subnet mask of 255 255 255 255 disables the gateway feature Ask your network administrator for the correct subnet mask If the BDI and the host are in the same subnet it is not necessary t
23. Example MMU XLAT enable address translation MMU XLAT 0xC0000800 page present bit is 0x800 This parameter defines the physical memory address where the BDI looks for the virtual address of the array with the two page table pointers For more information see also chapter Embedded Linux MMU Support If the additional 64BIT option is present the BDi assume a 64 bit PTE addr Physical address of the memory used to store the virtual address of the array with the two page table pointers Example PTBASE Oxf0 This parameter defines the registers paket that is sent to GDB in response to a register read command By default STD and FPR are read and trans ferred This default is compatible with older GDB versions The following names are use to select a register group or paket format STD The standard old register block The FPR registers are not read from the target but transferred You can t disable this register group FPR The floating point registers are read and transferred E500 The register paket is sent as expected by GDB for a PowerPC E500 target Example REGLIST STD only standard registers REGLIST E500 send E500 register set Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 27 SIO port baudrate When this line is present a TCP IP channel is routed to the BDI s RS232 connector The port parameter defines the TCP port used for this BDI to host communication You m
24. PC Unix Host Im The following explains the meanings of the built in LED lights Ethernet 10BASE T LED Name Description LI Link When this LED light is ON data link is successful between the UTP port of the BDI2000 and the hub to which it is connected TX Transmit When this LED light BLINKS data is being transmitted through the UTP port of the BDI2000 RX Receive When this LED light BLINKS data is being received through the UTP port of the BDI2000 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 12 2 5 Initial configuration of the bdiGDB system On the enclosed diskette you will find the BDI configuration software and the firmware logic required for the BDI2000 For Windows users there is also a TFTP server included The following files are on the diskette b20pq3gd exe Configuration program 16bit Windows application b20pq3gd hlp Windows help file for the configuration program b20pq3gd xxx Firmware for the BDI2000 copjed20 xxx JEDEC file for the BDI2000 Rev B logic device when working with a COP target copjed21 xxx JEDEC file for the BDI2000 Rev C logic device when working with a COP target tftpsrv exe TFTP server for Windows WIN32 console application cfg Configuration files def Register definition files bdisetup zip ZIP Archive with the Setup Tool sources for Linux UNIX hosts Overview of an instal
25. RUP 5000 Start delay after power up Normally the BDI drives the HRESET line during startup If reset type is NONE the BDI does not assert a hardware reset during startup This entry can also be used to change the default reset time type NONE HARD default time The time in milliseconds the BDI assert the reset signal Example RESET NONE no reset during startup RESET HARD 1000 assert RESET for 1 second This entry in the init list allows to define a delay time in ms the BDI inserts between releasing the COP HRESET line and starting communicating with the target This init list entry may be necessary if COP HRESET is de layed on its way to the PowerPC reset pin time the delay time in milliseconds Example WAKEUP 3000 insert 83sec wake up time Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 25 STARTUP mode runtime This parameter selects the target startup mode The following modes are supported LOOP This default mode forces the target to debug mode im mediately out of reset For this L2ESRAM is mapped to the inital boot page with an endless loop at Oxfffffffc HALT Also this mode forces the target to debug mode immedi ately out of reset but without mapping L2SRAM This works only if the processor can fetch a valid opcode from the boot address at Oxfffffffc STOP In this mode the BDI lets the target execute code for runtime milliseconds after reset
26. S eege 34 3 3 Debugging with GDB E 36 KC e Target 22 0 6 EE 36 3 3 2 Connecting to the TANI CT x olotes ietestetey aceon ential ecg eee ee 36 3 3 3 Breakpoint Handling EE 37 3 3 4 GDB monitor command TE 37 3 3 5 Target serial O via BDI cccdccciccacstnrorenneteaecnivtactdenescentwtscnsroinotsdeeetdinnancsderssneteurmatoneadant 38 3 3 6 Embedded Linux MMU Support sett ieee 39 3 4 Telnet IEN eesgebeeenegeegeE EE 41 4 Specifications E 43 5 Environmental note eet e ENNEKEKNAENNE ANS EEKEERERNNEKRKSEKREANKESSNEESNNEKRRR ONE EEEARNKEAEEAER EK eENNEE 44 6 Declaration of Conformity CE sissisciesiecsossaceitacsnsecseceuvnsscenunansansussnsneentaceuntuedersesusbnenedeeucaneusawased 44 FT AR 45 Appendices PA Troubleshooting s ass cases ccs cass cscs adem aaaea aaaeeeaa naana eanecbedandivedaascancenebaccnubededenceess 46 B Natpteuanggessueseeseseeeeese deeg EES 47 C TWACeR ATS sass tassel 49 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 3 1 Introduction bdiGDB enhances the GNU debugger GDB with JTAG COP debugging for PowerPC MPC85xx based targets With the built in Ethernet interface you get a very fast code download speed No target communication channel e g serial line is wasted for debugging purposes Even better you can use fast Ethernet debugging with target systems without network capability The host to BDI communica tion uses the standard GDB rem
27. This mode is useful when monitor code should initialize the target system RUN After reset the target executes code until stopped by the Telnet halt command Example STARTUP STOP 3000 let the CPU run for 3 seconds BDIMODE mode param This parameter selects the BDI debugging mode The following modes are supported LOADONLY Loads and starts the application core No debugging via JTAG port AGENT The debug agent runs within the BDI There is no need for any debug software on the target This mode accepts a second parameter If RUN is entered as a second pa rameter the loaded application will be started immedi ately otherwise only the PC is set and BDI waits for GDB requests Example BDIMODE AGENT RUN BREAKMODE mode This parameter defines how breakpoints are implemented The current mode can also be changed via the Telnet interface SOFT This is the normal mode Breakpoints are implemented by replacing code with a TRAP instruction HARD In this mode the PPC breakpoint hardware is used Only 2 breakpoints at a time is supported LOOP In this mode breakpoints are implemented by replacing code with an endless loop 0x48000000 Maybe useful for special debug tasks The processor does not auto matically enter debug mode it has to be halted manually via Telnet or GDB Example BREAKMODE HARD Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 26 STEPMODE mode
28. WSPR 27 0x00001002 SRR1 ME RI WREG name value Write value to the selected CPU register by name name the register name MSR CR XER LR CTR DSISR value the value to write into the register Example WREG MSR 0x00001002 DELAY value Delay for the selected time A delay may be necessary to let the clock PLL lock again after a new clock rate is selected value the delay time in milliseconds 1 30000 Example DELAY 500 delay for 0 5 seconds WMB8 address value Write a byte 8bit to the selected memory place address the memory address value the value to write to the target memory Example WM8 OxFFFFFA21 0x04 SYPCR watchdog disable WM16 address value Write a half word 16bit to the selected memory place address the memory address value the value to write to the target memory Example WM16 0x02200200 0x0002 TBSCR WM32 address value Write a word 32bit to the selected memory place address the memory address value the value to write to the target memory Example WM32 0x02200000 0x01632440 SIUMCR WM64 address value Write a double word 64bit to the selected memory place This entry is mainly used to unlock flash blocks The pattern written is generated by du plicating the value 0x12345678 gt 0x123456781 2345678 address the memory address value the value used to generate the pattern Example WM64 0xFFF00000 0x00600060 unlock block 0 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000
29. accordance with the PowerPC COP connector specification In order to ensure reliable operation of the BDI EMC runtimes etc the target cable length must not exceed 20 cm 8 Target System MPC 1 15 i a gt x z z x a z lt COP JTAG Connector T j Wa 2 16 3 TDI 4 TRST 6 Vcc Target 7 TCK A TARGET B 15 1 9 TMS ae ee ee ee e ee HEKEEKKE 11 SRESET 16 2 12 GROUND 13 HRESET The green LED TRGT marked light up when target is powered up 16 GROUND For BDI TARGET B connector signals see table on next page Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 6 BDI TARGET B Connector Signals Describtion JTAG Test Data Out This input to the BDI2000 connects to the target TDO pin General purpose I O Currently not used JTAG Test Data In This output of the BDI2000 connects to the target TDI pin JTAG Test Reset This output of the BDI2000 resets the JTAG TAP controller on the target General purpose Input Currently not used Vcc Target 1 8 BON This is the target reference voltage It indicates that the target has power and it is also used to create the logic level reference for the input comparators It also controls the output logic levels to the target It is normally connected to Vdd I O on the target board 3 0 5 0V with Re
30. am execution e Programming and Erasing Flash memory During debugging with GDB the Telnet is mainly used to reboot the target generate a hardware reset and reload the application code It may be also useful during the first installation of the bdiGDB sys tem or in case of special debug needs How to enter 64bit values The syntax for 64 bit parameters is lt high word gt _ lt low word gt The high word and low word can be entered as decimal or hexadecimal They are handled as two separate values concatenated with an underscore Examples 0x01234567_0x89abcdef gt gt 0x0123456789abcdef 10 gt gt 0x0000000100000000 256 gt gt 0x0000000000000100 3_0x1234 gt gt 0x0000000300001234 0x80000000_0 gt gt 0x8000000000000000 Example of a Telnet session BDI gt info Target CPU MPC8548 Rev 1 Target state halted Debug entry cause COP halt Current PC Ox0ffeOdlc Current CR 0x20004082 Current MSR 0x00021200 Current LR Ox0ffe0d4c Current CCSRBAR Ox0_e0000000 BDI gt md Oxfffff000 O_fffff000 7c1f42a6 3c208020 60210010 7c000800 B lt O_fffff010 40820020 38002000 7c11f3a6 3c401000 8 lt Notes The DUMP command uses TFTP to write a binary image to a host file Writing via TFTP on a Linux Unix system is only possible if the file already exists and has public write access Use man tftpd to get more information about the TFTP server on your host Copyright 1997 2
31. an appropriate hardware breakpoint The BDI assumes that this is a Set Breakpoint action when memory write length is 4 bytes and the pattern to write is Ox7D821008 tw 12 r2 r2 GDB version gt V5 x GDB version gt 5 x uses the Z packet to set breakpoints watchpoints For software breakpoints the BDI replaces code with 0x7D821008 tw 12 r2 r2 When breakpoint mode HARD is selected the BDI sets an appropriate hardware breakpoint 3 3 4 GDB monitor command The BDI supports the GDB V5 x monitor command Telnet commands are executed and the Telnet output is returned to GDB This way you can for example switch the BDI breakpoint mode from within your GDB session gdb target remote bdi2000 2001 Remote debugging using bdi2000 2001 0x10b2 in start gdb monitor break Breakpoint mode is SOFT gdb mon break hard gdb mon break Breakpoint mode is HARD gdb Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 88 3 3 5 Target serial I O via BDI A RS232 port of the target can be connected to the RS232 port of the BDI2000 This way it is possible to access the target s serial I O via a TCP IP channel For example you can connect a Telnet session to the appropriate BDI2000 port Connecting GDB to a GDB server stub running on the target should also be possible Target System RS232 Connector 1 CD 2 RXD 3 TXD 4 DTR 5 GROUND 6 DSR
32. and the initial configuration of the BDI2000 is done with a command line utility In the ZIP Archive bdisetup zip are all sources to build this utility More information about this utility can be found at the top in the bdisetup c source file There is also a make file included Starting the tool without any parameter displays information about the syntax and parameters A To avoid data line conflicts the BDI2000 must be disconnected from the target system while programming the logic for an other target CPU see Chapter 2 1 1 Following the steps to bring up a new BDI2000 1 Build the setup tool The setup tool is delivered only as source files This allows to build the tool on any Linux Unix host To build the tool simply start the make utility root LINUX_1 bdisetup make cc 02 c o bdisetup o bdisetup c cc 02 c o bdicnf o bdicnf c cc 02 c o bdidll o bdidll c cc s bdisetup o bdicnf o bdidll o o bdisetup 2 Check the serial connection to the BDI With bdisetup v you may check the serial connection to the BDI The BDI will respond with infor mation about the current loaded firmware and network configuration Note Login as root otherwise you probably have no access to the serial port root LINUX_1 bdisetup bdisetup v p dev ttyS0O b57 BDI Type BDI2000 Rev C SN 92152150 Loader V1 05 Firmware unknown Logic unknown MAC 00 Oc 01 92 15 21 IP Addr 255 255 255 255 Subnet 295 25
33. are swapped This is useful to access little endian ordered registers e g PCI bridge configuration reg isters The following entries are supported in the REGS part of the configuration file FILE filename DMMh base IMMn addr data Remark The name of the register definition file This name is used to access the file via TFTP The file is loaded once during BDI startup filename the filename including the full path Example FILE C bdi regs mpc8260 def This defines the base address of direct memory mapped registers This base address is added to the individual offset of the register base the base address Example DMM1 0x01000 This defines the addresses of the memory mapped address and data reg isters of indirect memory mapped registers The address of a IMMn regis ter is first written to addr and then the register value is access using data as address addr the address of the Address register data the address of the Data register Example DMM1 0x04700000 The registers msr cr iar and acc and are predefined Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 35 Example for a register definition Entry in the configuration file REGS FILE E cygwin home bdidemo e500 reg8560 def The register definition file name type addr size sp GPR 1 Carr SPR 58 csrrl SPR 59 ctr SPR 9 dacl SPR 316 dac2 SPR 317 dbcro SPR 308 pido SPR
34. ay choose any port except 0 and the default Telnet port 23 On the host open a Telnet session using this port Now you should see the UART output in this Telnet session You can use the normal Telnet connection to the BDI in parallel they work completely inde pendent Also input to the UART is implemented port The TCP IP port used for the host communication baudrate The BDI supports 2400 115200 baud Example SIO 7 9600 TCP port for virtual lO Daisy chained JTAG devices The BDI can also handle systems with multiple devices connected to the JTAG scan chain In order to put the other devices into BYPASS mode and to count for the additional bypass registers the BDI needs some information about the scan chain layout Enter the number count and total instruction register irlen length of the devices present before the PowerPC chip Predecessor Enter the ap propriate information also for the devices following the PowerPC chip Successor SCANPRED countirlen This value gives the BDI information about JTAG devices present before the PowerPC chip in the JTAG scan chain count The number of preceding devices irlen The sum of the length of all preceding instruction regis ters IR Example SCANPRED 1 8 one device with an IR length of 8 SCANSUCC count irlen This value gives the BDI information about JTAG devices present after the PowerPC chip in the JTAG scan chain count The number of succeeding devices irlen The sum of the le
35. cal documentation to be free of defects in materials and workmanship for a period of 24 months following the date of purchase when used under normal conditions In the event of notification within the warranty period of defects in material or workmanship ABATRON will replace defective diskette cable BDI2000 or documentation The remedy for breach of this warranty shall be limited to replacement and shall not encompass any other damages includ ing but not limited loss of profit special incidental consequential or other similar claims ABATRON Switzerland specifically disclaims all other warranties expressed or implied including but not limited to implied warranties of merchantability and fitness for particular purposes with respect to defects in the diskette cable BDI2000 and documentation and the program license granted here in including without limitation the operation of the program with respect to any particular application use or purposes In no event shall ABATRON be liable for any loss of profit or any other commercial damage including but not limited to special incidental consequential or other damages Failure in handling which leads to defects are not covered under this warranty The warranty is void under any self made repair operation except exchanging the fuse Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 46 Appendices A Troubleshooting Problem
36. chapter 2 2 1 External Power Supply To avoid data line conflicts the BDI2000 must be disconnected from the target system while programming the logic for an other target CPU Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 8 2 2 Connecting the BDI2000 to Power Supply The BDI2000 needs to be supplied with 5 Volts max 1A via the POWER connector The available power supply from Abatron option or the enclosed power cable can be directly connected In order to ensure reliable operation of the BDI2000 keep the power supply cable as short as possible A For error free operation the power supply to the BDI2000 must be between 4 75V and 5 25V DC The maximal tolerable supply voltage is 5 25 VDC Any higher voltage or a wrong polarity might destroy the electronics POWER Connector 1 Vcc 1 Vcc 5V 3 GROUND The green LED BDI marked light up when 5V power is connected to the BDI2000 Please switch on the system in the following sequence e 1 gt external power supply e 2 gt target system Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 9 2 3 Status LED MODE The built in LED indicates the following BDI states MODE LED BDI STATES The BDI is ready for use the firmware is already loaded The power supply for th
37. dRootDirectory Without any parameter the server starts in read only mode This means only read access request from the client are granted This is the normal working mode The bdiGDB system needs only read access to the configuration and program files The parameter p enables protocol output to the console window Try it The parameter w enables write accesses to the host file system The parameter d allows to define a root directory tftpsrv p Starts the TFTP server and enables protocol output tftpsrv p w Starts the TFTP server enables protocol output and write accesses are allowed tftpsrv dC tftp Starts the TFTP server and allows only access to files in C tftp and its subdirectories As file name use relative names For example bdi mpc750 cfg accesses C tftp bdi mpc750 cfg You may enter the TFTP server into the Startup group so the server is started every time you login Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 18 3 Using bdiGDB 3 1 Principle of operation The firmware within the BDI handles the GDB request and accesses the target memory or registers via the JTAG interface There is no need for any debug software on the target system After loading the code via TFTP debugging can begin at the very first assembler statement Whenever the BDI system is powered up the following sequence starts initial configuration valid no
38. e BDI2000 is lt 4 75VDC The BDI loader mode is active an invalid firmware is loaded or loading firmware is active Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 70 2 4 Connecting the BDI2000 to Host 2 4 1 Serial line communication Serial line communication is only used for the initial configuration of the bdiGDB system The host is connected to the BDI through the serial interface COM1 COM4 The communication cable included between BDI and Host is a serial cable There is the same connector pinout for the BDI and for the Host side Refer to Figure below RS232 Connector Target System for PC host MPC Rm 2 RXD data from host 3 TXD data to host RS232 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 77 2 4 2 Ethernet communication The BDI2000 has a built in 10 BASE T Ethernet interface see figure below Connect an UTP Un shilded Twisted Pair cable to the BD2000 For thin Ethernet coaxial networks you can connect a commercially available media converter BNC gt 10 BASE T between your network and the BDI2000 Contact your network administrator if you have questions about the network Target System 10 BASE T MPC Connector 1 TD 2 TD 3 RD LI TX RX 10 BASE T 6 RD BDI2000
39. et PC is set BDI now waits for GDB request from the debugger running on the host After starting the debugger it must be connected to the remote target This can be done with the fol lowing command at the GDB prompt gdb target remote bdi2000 2001 bdi2000 This stands for an IP address The HOST file must have an appropriate entry You may also use an IP address in the form xxx xXxx XXX XXX 2001 This is the TCP port used to communicate with the BDI If not already suspended this stops the execution of application code and the target CPU changes to background debug mode Remember every time the application is suspended the target CPU is freezed During this time no hardware interrupts will be processed Note For convenience the GDB detach command triggers a target reset sequence in the BDI gdb gdb detach Wait until BDI has resetet the target and reloaded the image gdb target remote bdi2000 2001 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 37 3 3 3 Breakpoint Handling GDB versions before V5 0 GDB inserts breakpoints by replacing code via simple memory read write commands There is no command like Set Breakpoint defined in the GDB remote protocol When breakpoint mode HARD is selected the BDI checks the memory write commands for such hidden Set Breakpoint actions If such a write is detected the write is not performed and the BDI sets
40. g of multiple flash sectors easier you can enter an erase list All entries in the erase list will be processed if you enter ERASE at the Telnet prompt without any parameter This list is also used if you enter UNLOCK at the Telnet without any parameters With the in crement and count option you can erase multiple equal sized sectors with one entry in the erase list address Address of the flash sector block or chip to erase increment If present the address offset to the next flash sector count If present the number of equal sized sectors to erase mode BLOCK CHIP UNLOCK Without this optional parameter the BDI executes a sec tor erase If supported by the chip you can also specify a block or chip erase If UNLOCK is defined this entry is also part of the unlock list This unlock list is processed if the Telnet UNLOCK command is entered without any parameters wait The wait time in ms is only used for the unlock mode Af ter starting the flash unlock the BDI waits until it pro cesses the next entry Example ERASE Oxff040000 erase sector 4 of flash ERASE Oxff060000 erase sector 6 of flash ERASE Oxff000000 CHIP erase whole chip s ERASE Oxff010000 UNLOCK 100 unlock wait 100ms ERASE Oxff000000 0x10000 7 erase 7 sectors Example for the ADS8260 flash memory FLASH CHIPTYPE I28BX8 CHIPSIZE 0x200000 BUSWIDTH 32 WORKSPACE 0x04700000 ERASE OxFF 900000 ERASE OxFF 940000 ERASE OxFF 98000
41. in bits 8 16 32 64 Example BUSWIDTH 16 The default name of the file that is programmed into flash using the Telnet prog command This name is used to access the file via TFTP If the file name starts with a this is replace with the path of the configuration file name This name may be overridden interactively at the Telnet interface filename the filename including the full path or for relative path Example FILE F gnu ppc bootrom hex FILE bootrom hex The format of the file and an optional address offset The optional param eter offset is added to any load address read from the program file You get the best programming performance when using a binary format BIN AOUT ELF or IMAGE format SREC BIN AOUT ELF or IMAGE Example FORMAT BIN 0x10000 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC8 amp 5xx User Manual 31 WORKSPACE address If a workspace is defined the BDI uses a faster programming algorithm that runs out of RAM on the target system Otherwise the algorithm is pro cessed within the BDI The workspace is used for a 1kByte data buffer and to store the algorithm code There must be at least 2kBytes of RAM avail able for this purpose address the address of the RAM area Example WORKSPACE 0x00000000 ERASE addr increment count mode wait The flash memory may be individually erased or unlocked via the Telnet interface In order to make erasin
42. ing format xxx xxx xxX XxxX 9 255 255 255 0 A subnet mask of 255 255 255 255 disables the gateway feature Ask your network administrator for the correct subnet mask Enter the IP address of the default gateway Ask your network administra tor for the correct gateway IP address If the gateway feature is disabled you may enter 255 255 255 255 or any other value Enter the IP address of the host with the configuration file The configura tion file is automatically read by the BDI2000 after every start up Enter the full path and name of the configuration file e g D gnu config bdi ads8260bdi cnf For information about the syntax of the configuration file see the bdiGDB User manual This name is transmitted to the TFTP server when reading the configuration file Click on this button to store the configuration in the BDI2000 flash memory 2 5 3 Recover procedure In rare instances you may not be able to load the firmware in spite of a correctly connected BDI error of the previous firmware in the flash memory Before carrying out the following procedure check the possibilities in Appendix Troubleshooting In case you do not have any success with the tips there do the following e Switch OFF the power supply for the BDI and open the unit as described in Appendix Maintenance e Place the jumper in the INIT MODE position e Connect the power cable or target cable if the BDI is powered
43. lation configuration process e Create a new directory on your hard disk e Copy the entire contents of the enclosed diskette into this directory e Linux only extract the setup tool sources and build the setup tool e Use the setup tool to load update the BDI firmware logic Note A new BDI has no firmware logic loaded e Use the setup tool to transmit the initial configuration parameters IP address of the BDI IP address of the host with the configuration file Name of the configuration file This file is accessed via TFTP Optional network parameters subnet mask default gateway Activating BOOTP The BDI can get the network configuration and the name of the configuration file also via BOOTP For this simple enter 0 0 0 0 as the BDI s IP address see following chapters If present the subnet mask and the default gateway router is taken from the BOOTP vendor specific field as defined in RFC 1533 With the Linux setup tool simply use the default parameters for the c option root LINUX_1 bdisetup bdisetup c p dev ttyS0O b57 The MAC address is derived from the serial number as follows MAC 00 0C 01 xx xx xx repace the xx xx xx with the 6 left digits of the serial number Example SN 93123457 gt gt 00 0C 01 93 12 34 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 13 2 5 1 Configuration with a Linux Unix host The firmware logic update
44. ldi JTAG debug interface for GNU Debugger DaweDC HONG 2x User Manual Manual Version 1 05 for BDI2000 AAR N 1997 2006 by Abatron AG d for BDIZ000 PowerPC MPC85xx User Manual 2 UI Tu E 3 SE B 21010 EE 3 1 2 BDI Configuration E 4 A EE E 5 2 1 Connecting the BDI2000 Ee arcsec access eA aac etc eats ees areata eee 5 2 1 1 Changing Target Processor Type ENNEN 7 2 2 Connecting the BDIZ000 to Power SUPP sscscccccissicsceesactscesttesin EES Ne dactecessnevnenandacceeana eens 8 2 3 Status LED eI Ere crcastereecaccaacesacsananneyiati ounecasascetemess auteriaaceimetescansteanpniacsertatoisesmscemaaasies 9 2 4 Connecting the BD12000 to Host EE 10 2 4 1 Serial line communication ANNE 10 24 2 Ethernet communication stets E aR REENE RE KT AN A ENEEIER R 11 2 5 Initial configuration of the bdiGDB ovstem ee eeeeneeeeeeeeeeeeeeeaeeeeeseaaeeeeeea 12 2 5 1 Configuration with a Linux UNIX NOSt eect eeeeeene ee eeeceeeeeeeeeeeeeeeeaeeeeeeenaaeeeenee 13 2 5 2 Configuration with a Windows host cise tncsiiecterededeetenedeatieies ss acted estieesteeiteescicceedee 15 2 5 3 Recover ge E E 16 2 6 Testing the BDI2000 to host connection ctag2iin ecasigerin Ge acters aie atic cencee 17 2 7 TFTP server EEN 17 3 Using bdiGDB EE 18 3 1 Principle of operatiON EE 18 3 2 Gonfig ration A EE 20 321 Part TIR RE 21 3 22 Part TARGET EN 24 3 2 9 Par HOST EE 28 32 A Rart FLASH irena mn en nr eee ee eee eee es 30 3 25 Part REG
45. msync WM32 Oxfffff008 0x48000000 Loop WSPR 624 0x10030000 MASO TLB1 Index 3 WSPR 625 0x80000800 MAS1 valid 64 Mbyte WSPR 626 0x00000008 MAS2 0x00000000 I WSPR 627 0x0000003f MAS3 0x00000000 UX SX UW SW UR SR EXEC Oxfffff000 TARGET CPUTYPE 8560 the CPU type JTAGCLOCK al use 8 MHz JTAG clock BREAKMODE SOFT SOFT or HARD HARD uses PPC hardware breakpoint HOST iP Sch E CIS FILE E cygwin home demo e500 fibo elf FORMAT ELF LOAD MANUAL load code MANUAL or AUTO after reset FLASH CHIPTYPE STRATAX16 CHIPTYPE AM2 9BX16 CHIPSIZE 0x800000 The size of one flash chip in bytes BUSWIDTH 32 The width of the flash memory bus in bits 8 16 32 WORKSPACE 0x40080000 workspace in dual port RAM FILE E cygwin home bdidemo e500 ads8560 cfg FORMAT BIN OxFF800000 ERASE OxFF800000 erase sector 0 REGS FILE E cygwin home bdidemo e500 reg8560 def Based on the information in the configuration file the target is automatically initialized after every re set Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 5 2 Installation 2 1 Connecting the BDI2000 to Target The cable to the target system is a 16 pin flat ribbon cable In case where the target system has an appropriate connector the cable can be directly connected The pin assignment is in
46. ngth of all succeeding instruction reg isters IR Example SCANSUCC 2 12 two device with an IR length of 8 4 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 28 3 2 3 Part HOST The part HOST defines some host specific values IP ipaddress The IP address of the host ipaddress the IP address in the form xxx xxx xxX XXX Example IP 151 120 25 100 FILE filename The default name of the file that is loaded into RAM using the Telnet load command This name is used to access the file via TFTP If the filename starts with a this is replace with the path of the configuration file name filename the filename including the full path or for relative path Example FILE F gnu demo ppc test elf FILE test elf FORMAT format offset The format of the image file and an optional load address offset If the im age is already stored in ROM on the target select ROM as the format The optional parameter offset is added to any load address read from the im age file format SREC BIN AOUT ELF IMAGE or ROM Example FORMAT ELF FORMAT ELF 0x10000 LOAD mode In Agent mode this parameters defines if the code is loaded automatically after every reset mode AUTO MANUAL Example LOAD MANUAL START address The address where to start the program file If this value is not defined and the core is not in ROM the address is taken from the image file If this val ue is n
47. nt user page table As long as the base pointer or the first entry is zero the BDI does only L2 CAM L2 TLB1 and default trans lation Default translation maps a 128 Mbyte range starting at KERNELBASE to 0x00000000 The second page table is only searched if its address is not zero and there was no match in the first one The pointer stucture is as follows PTBASE physical address gt PTE pointer pointer virtual or physical address gt PTE kernel pointer virtual or physical address PTE user pointer virtual or physical address Newer versions of arch ppc kernel head S support the automatic update of the BDI page table in formation structure Search head S for abatron and you will find the BDI specific extensions Extract from the configuration file INIT wun 0x000000f 0 0x00000000 invalidate page table bas TARGET MMU XLAT translate effective to physical address PTBASE Ox000000f0 here is the pointer to the page table pointers Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 40 To debug the Linux kernel when MMU is enabled you may use the following load and startup se quence e Load the compressed linux image e Set a hardware breakpoint with the Telnet at a point where MMU is enabled For example at start_kernel BDI gt BI 0xC0061550 e Start the code with GO at the Telnet e The Linux kernel i
48. o enter a subnet mask Default Gateway Enter the IP address of the default gateway Ask your network administra tor for the correct gateway IP address If the gateway feature is disabled you may enter 255 255 255 255 or any other value Config Host IP Address Enter the IP address of the host with the configuration file The configura tion file is automatically read by the BDI2000 after every start up Configuration file Enter the full path and name of the configuration file This file is read via TFTP Keep in mind that TFTP has it s own root directory usual tftpboot You can simply copy the configuration file to this directory and the use the file name without any path For more information about TFTP use man tftpd root LINUX_1 bdisetup bdisetup c p dev ttySO b57 gt 1151 120 25 101 gt h151 120 25 118 gt fmpc8560 cfg Connecting to BDI loader Writing network configuration Writing init list and mode Configuration passed 5 Check configuration and exit loader mode The BDI is in loader mode when there is no valid firmware loaded or you connect to it with the setup tool While in loader mode the Mode LED is flashing The BDI will not respond to network requests while in loader mode To exit loader mode the bdisetup v s can be used You may also power off the BDI wait some time 1min and power on it again to exit loader mode root LINUX_1 bdisetup bdisetup v p dev ttyS0O b57 s
49. ode add this entry to the configuration file mode ECHO default NOECHO or LINE Example TELNET NOECHO use old line mode Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 30 3 2 4 Part FLASH The Telnet interface supports programming and erasing of flash memories The bdiGDB system has to know which type of flash is used how the chip s are connected to the CPU and which sectors to erase in case the ERASE command is entered without any parameter CHIPTYPE type CHIPSIZE size BUSWIDTH width FILE filename FORMAT format offset This parameter defines the type of flash used It is used to select the cor rect programming algorithm format AM29F AM29BX8 AM29BX 16 I28BX8 I28BX16 AT49 AT49X8 AT49X16 STRATAX8 STRATAX16 MIRROR MIRRORX8 MIRRORX16 M58X32 AM29DX16 AM29DX32 Example CHIPTYPE AM29F The size of one flash chip in bytes e g AM29F010 0x20000 This value is used to calculate the starting address of the current flash memory bank size the size of one flash chip in bytes Example CHIPSIZE 0x80000 Enter the width of the memory bus that leads to the flash chips Do not enter the width of the flash chip itself The parameter CHIPTYPE carries the information about the number of data lines connected to one flash chip For example enter 16 if you are using two AM29F010 to build a 16bit flash memory bank with the width of the flash memory bus
50. ot defined and the core is already in ROM the PC will not be set before starting the program file This means the program starts at the nor mal reset address OxFFFO00100 address the address where to start the program file Example START 0x1000 DEBUGPORT port The TCP port GDB uses to access the target port the TCP port number default 2001 Example DEBUGPORT 2001 Special IMAGE load format The IMAGE format is a special version of the ELF format used to load a Linux boot image into target memory When this format is selected the BDI loads not only the loadable segment as defined in the Program Header it also loads the rest of the file up to the Section Header Table The relationship between load address and file offset will be maintained throughout this process This way the com pressed Linux image and a optional RAM disk image will also be loaded Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 29 PROMPT string This entry defines a new Telnet prompt The current prompt can also be changed via the Telnet interface Example PROMPT PPC_2 gt DUMP filename The default file name used for the Telnet DUMP command filename the filename including the full path Example DUMP dump bin TELNET mode By default the BDI sends echoes for the received characters and supports command history and line editing If it should not send echoes and let the Telnet client in line m
51. ote protocol An additional Telnet interface is available for special debug tasks e g force a hardware reset program flash memory The following figure shows how the BDI2000 interface is connected between the host and the target Target System COP Interface BDI2000 GNU Debugger GDB Ethernet 10 BASE T 1 1 BDI2000 The BDI2000 is the main part of the bdiGDB system This small box implements the interface be tween the JTAG pins of the target CPU and a 10Base T Ethernet connector The firmware and the programmable logic of the BDI2000 can be updated by the user with a simple Windows based con figuration program The BDI2000 supports 1 8 5 0 Volts target systems 3 0 5 0 Volts target sys tems with Rev B Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 4 1 2 BDI Configuration As an initial setup the IP address of the BDI2000 the IP address of the host with the configuration file and the name of the configuration file is stored within the flash of the BDI2000 Every time the BDI2000 is powered on it reads the configuration file via TFTP Following an example of a typical configuration file bdiGDB configuration file for MPC8560ADS DH DH INIT init core register DH DH load TIB entries helper code Oxfffff000 WM32 OxfffffO00 O0x7c0007a4 tlbwe WM32 OxfffffO04 Ox7c0004ac
52. part name identifier parameterl parameter2 parameterN comment identifier parameterl parameter2 parameterN part name identifier parameterl parameter2 parameterN identifier parameterl parameter2 parameterN etc Numeric parameters can be entered as decimal e g 700 or as hexadecimal 0x80000 Note about how to enter 64bit values The syntax for 64 bit parameters is lt high word gt _ lt low word gt The high word optional and low word can be entered as decimal or hexadecimal They are han dled as two separate values concatenated with an underscore Examples 0x01234567_0x89abcdef gt gt 0x0123456789abcdef 10 gt gt 0x0000000100000000 256 gt gt 0x0000000000000100 3_0x1234 gt gt 0x0000000300001234 0x80000000_0 gt gt 0x8000000000000000 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 27 3 2 1 Part INIT The part INIT defines a list of commands which should be executed every time the target comes out of reset The commands are used to get the target ready for loading the program file WGPR register value Write value to the selected general purpose register register the register number 0 31 value the value to write into the register Example WGPR 0 5 WSPR register value Write value to the selected special purpose register register the register number value the value to write into the register Example
53. s decompressed and started e The system should stop at the hardware breakpoint e g at start_kernel e Disable the hardware breakpoint with the Telnet command Cl e If not automatically done by the kernel setup the page table pointers for the BDI e Start GDB with vmlinux as parameter e Attach to the target e Now you should be able to debug the Linux kernel To setup the BDI page table information structure manually set a hardware breakpoint at start_kernel and use the Telnet to write the address of swapper_pg_dir to the appropriate place BDI gt bi 0xc0061550 BDI gt go BDI gt ci BDI gt mm Oxf0 OxcOQO0000 8 BDI gt mm Oxf8 0xc0057000 BDI gt mm Oxfc 0x00000000 set breakpoint at start_kernel target stops at start_kernel Let PTBASE point to an array of two pointers write address of swapper_pg_dir to first pointer clear second user pointer Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 47 3 4 Telnet Interface A Telnet server is integrated within the BDI The Telnet channel is used by the BDI to output error messages and other information Also some basic debug commands can be executed Telnet Debug features e Display and modify memory locations e Display and modify general and special purpose registers e Single step a code sequence e Set hardware breakpoints e Load a code file from any host e Start Stop progr
54. t is mapped to 0x00000000 In case there are two flash chips to get a 32bit system double the step parameter BDI gt unlock 0x00000000 0x20000 256 Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 bd for BDIZ000 PowerPC MPC8 amp 5xx User Manual 34 3 2 5 Part REGS In order to make it easier to access target registers via the Telnet interface the BDI can read ina register definition file In this file the user defines a name for the register and how the BDI should access it e g as memory mapped memory mapped with offset The name of the register defi nition file and information for different registers type has to be defined in the configuration file The register name type address offset number and size are defined in a separate register definition file An entry in the register definition file has the following syntax name type addr name type addr size SWAP size SWAP The name of the register max 15 characters The register type GPR General purpose register SPR Special purpose register CCSR Relative to CCSRBAR memory mapped register The BDI knows the current position of the CCSR space MM Absolute direct memory mapped register DMM1 DMM4 Relative direct memory mapped register IMM1 IMM4 Indirect memory mapped register The address offset or number of the register The size 8 16 32 of the register default is 32 If present the bytes of a 16bit or 32bit register
55. v B This input to the BDI2000 is used to detect if the target is powered up If there is a current limiting resistor between this pin and the target Vdd it should be 100 Ohm or less JTAG Test Clock This output of the BDI2000 connects to the target TCK pin 108 General purpose I O This output of the BDI2000 connects to the target CKSTP_IN pin Currently not used TMS JTAG Test Mode Select This output of the BDI2000 connects to the target TMS line 1010 General purpose I O Currently not used SRESET Soft Reset This open collector output of the BDI2000 connects to the target SRESET pin GROUND System Ground HRESET Hard Reset This open collector output of the BDI2000 connects to the target HRESET pin lt reseved gt IN General purpose Input This input to the BDI2000 connects to the target CKSTP_OUT pin Currently not used GROUND System Ground Copyright 1997 2006 by ABATRON AG Switzerland V 1 05 d for BDIZ000 PowerPC MPC85xx User Manual 7 2 1 1 Changing Target Processor Type Before you can use the BDI2000 with an other target processor type e g CPU32 lt gt PPC a new setup has to be done see chapter 2 5 During this process the target cable must be disconnected from the target system The BDI2000 needs to be supplied with 5 Volts via the BDI OPTION connec tor Version A or via the POWER connector Version B For more information see

bdiGDB User Manual

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