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DSTni User Guide

1. Table 2 22 INT1 or Ethernet MAC 1 Interrupt Control Register Definitions Bits Field Name Description 15 5 W Reserved 4 LTM Level Trigger Mode Sets the respective interrupt source 1 enable level triggered mode An interrupt generates when the external interrupt signal is HIGH 0 enable edge triggered mode default For both settings the level must remain HIGH until the interrupt is acknowledged 3 MSK Mask Interrupt 1 mask respective interrupt request default 0 enable respective interrupts 2 0 PR 2 0 Programmable Priority Level The programmable priority level for the respective interrupt source 111 lowest priority default 000 highest priority 21 Ethernet MAC 0 INTO Interrupt Control Register Table 2 23 Ethernet MAC 0 INTO Interrupt Control Register BIT 45 414 43 12111 10 9 8 OFFSET 38h FIELD Ill 5 N o FIS J RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 2 24 Ethernet MAC 0 INTO Interrupt Control Register Definitions Bits Field Name Description 15 5 W Reserved 4 LTM Level Trigger Mode Sets the respective interrupt source 1 enable level triggered mode An interrupt generates when the external interrupt signal is HIGH 0 enable edge triggered mode default For both sett
2. Table 2 38 Priority Mask Register Definitions Bits Field Name Description 15 3 Reserved 2 1 PR 2 1 Minimum Priority Level an Interrupt Request Must Have to be Recognized An interrupt request is processed by the interrupt controller if its priority level is greater than or equal to the priority in this register 111 lowest priority default 000 highest priority 0 TMR Logical OR of All Timer Interrupt Requests The individual timer interrupt request bits are contained in the interrupt status register This bit cannot be written 27 Interrupt Mask Register BIT Table 2 39 Interrupt Mask Register OFFSET FIELD RESET RW Bits 15 28h Ill l6 D3 D2 E pa js P I3 12 11 lO D1 DO Ill TMR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 R R R R R R R R R R R R R R RW RW W W W W W 1 wit W W W W W WWW Field Name Table 2 40 Interrupt Mask Register Definitions Description Reserved 14 16 Logical OR Connected to Both CANO and CAN1 1 mask CAN 0 and CAN 1 default 0 do not mask CAN 0 and CAN 1 13 D3 Mask DMA Channel 3 Interrupt 1 mask DMA channel 3 default 0 do not mask DMA channel 3 12 D2 Mask DMA Channel 2 Interrupt 1 mask DMA channel 2 default 0 do not mask DMA channel 2 11 SP3 Asynchronous Serial Port 3 1 mask asynchronous s
3. Parameter Sym Min Max Units Core Supply Voltage VDD1 8 0 5 2 5 V IO Supply Voltage VDD3 3 0 5 4 6 V Input Voltage Vi 0 5 6 V Output Voltage Vo 0 5 6 V ESD Performance 23K HBM 300 MM 1000 CDM V Latch Up current llatch 2500 mA Operating Temperature TOPT 40 125 C Storage Temperature TSTG 65 150 C Thermal Resistance Case Osc 7 6 C W Thermal Resistance Ambient Oya 30 C W Package Dissipation 105Deg C Ta 0 67 W Package Dissipation 95 Deg C Ta 1 W Package Dissipation 85 Deg C Ta 1 33 W Package Dissipation 70 Deg C Ta 1 83 W Note Long term exposure to absolute maximum ratings may affect device reliability and permanent damage may occur if operation exceeds the rating The device should be operated under recommended operating conditions 49 Recommended Operating Conditions Table 5 2 Recommended Operating Conditions Parameter Min Typ Max Unit Core Supply Voltage 10 1 62 1 8 1 98 V IO Supply Voltage 1096 3 0 3 3 3 6 V T Junction Temperature 40 25 125 C VIL Input Low Voltage 0 3 Ill 0 8 V VIH Input High Voltage 2 0 Ill 5 5 V VT Threshold Point non Schmitt Input 1 46 1 60 1 76 V VT Schmitt trig low to high threshold point 1 50 wc 1 55 1 55 bc V VT Schmitt trig high to low threshold point 0 88 wc 0 95 0 98 bc V Il Input leakage current Vi 3 3V or OV Ill 10na 1ua Ill
4. Mnemonic Opcode Description 186 486 DSTni r m16 imm8 with r m word AND 20 Ir AND byte register with r m byte 3 10 1 1 1 4 r m8 r8 AND 21 r AND word register with r m word 3 10 11 1 4 r m16 r16 AND 22 Ir AND r m byte with byte register 3 10 Y 1 4 r8 m8 AND 23 r AND r m word with word register 3 10 Y 1 4 r16 r m16 BOUND 62 r Check to see if word register is 33 35 7 50 24 r16 m16 amp 16 within bounds CALL E8 cw Call near displacement relative to 15 3 8 rel16 next instruction CALL FF 2 Call near register indirect memory 13 19 5 5 3 J r m16 indirect 8 CALL 9A cd Call far to full address given 23 18 6 J ptr16 16 11 CALL FF 3 Call far to address at m16 16 word 38 17 T J m16 16 12 CBW 98 Put signed extension of AL in AX 2 3 1 CLC F8 Clear Carry Flag 2 2 1 CLD FC Clear Direction Flag so the Source 2 2 1 Index SI and or the Destination Index DI registers will increment during instructions CLI FA Clear Interrupt Enable Flag 2 5 1 CMC F5 Complement Carry Flag 2 2 1 CMP 3C ib Compare immediate byte to AL 3 1 1 AL imm8 CMP 3D iw Compare immediate word to AX 4 1 1 AX imm16 CMP 80 7 ib Compare immediate byte to r m 3 10 Y 1 4 r m8 imm8 byte CMP 81 7 iw Compare immediate word to r m 3 10 Y 1 4 r m16 imm16 word CMP 83 7 ib Compare sign extended immediate 3 10 Y 1 4 r m16 imm8 byte to r m word CMP 38 r Compare byte register to r m byte 3 10 Y 1 4 r m8 r8 CMP 39 r Compare word register to r m word 3 10 Y 1 4 r
5. 52 Power Curve Diagrams Figure 5 3 shows the current for both power supplies of a typical part Figure 5 3 DSTni Current DSTni EX Current 160 140 120 2 1 8V Current ma E 100 Temp case C E 80 Ambient C 5 60 gt Differential C E E 40 3 3V Current ma 20 0 0 50 100 150 Frequency Mhz 53 Figure 5 4 shows shows the power dissipation of a worse case device at four different ambient temperatures Figure 5 4 DSTni Power Curve DSTni_EX Power 1 35 Watts 70 105 95 85 Temperature 54 6 Applications This appendix identifies various DSTni applications Topics in this chapter include 9 9999999999999 Timing see page 56 Data see page 57 Reset see page 58 XTAL see page 59 Burst Flash 3 wire see page 60 Burst Flash 2 Wire see page 61 Page Flash see page 62 Serial Flash see page 63 Static RAM see page 64 SDRAM see page 65 External DMA see page 66 ARDY see page 67 PHY 10 100 Mbit see page 68 Fibre 100 Mbit see page 69 LED Functionality see page 70 55 T iming I M iCHML m CHMH i 1 bod i l i I R HPL m icHPH U 1 pog MCSn PCSn RDn I l l 1 M ICHRDL gt tcHRDH WRn l l l 1 IICLWL e e tCHWH WRxn l i 1 I 1 E 1 N R T
6. M ICHAV re CHAV DB15 0 Read Dala N M tCHRH gt CHRDS 4 DB15 0 Write Data M lICHWDV r tcHwDv omm Byte Enabled 1 La ADDRESS DATA BUS WRHn UBn WRLn LBn CPUCLK UCSn Word Word Word Byte Byte MCSx Write Write Read Write Write WRn RDn CSBE 0 Address Bit 12 pulled low WRHn High e Low WRLn Byte 0 Wait 1 Wait 0 Wait 0 Wait CSBE 1 Address Bit 12 not pulled low SRAM access time is SRAM Access tcHAV tCHRDS Example 50Mhz clock 20ns want to use 45ns SRAM 45ns Ins 3ns 49ns lt 3 20ns 2 wait states wait states 1 tCHCH Note By design the WRxn signals always return high a minimum 0 5ns before the address or data bus changes 64 SDRAM 16Mbit 64Mbit 128Mbit DSTni EX CKE should be pulled high Word Word Byte Byte MCSOn Write Read Write Write X wate ANOOP X Read KNOOPX white ANOOP X white X All SDRAM commands are passed through the Address lines Delays between SDRAM memory cycles are dependent on internal wait states and page hits Addr NOOP 65 External DMA DSTni EX DATA BUS BUS Master l l l CPUCLK I I HOLD i RDn WRxn I I tcHHS m LCSn i i t I l CLLS cHLS A23 1 addfess i l tcHDAS gt l tCHDAH DB15 0 Write Dia ta I 1 H CHDDS gt 4 tCHDDH I DB15 0 I
7. Serial Port 3 Interrupt Control Register Table 2 9 Serial Port 3 Interrupt Control Register FARENE OFFSET P 46h FIELD Ill S cee ae Al cee dee RESET olo 0 0 0 0 0 0 0 olol o 1 1 1 1 RW R RW R RW T RW T RW T RW T R TR T R TR TRWT RI RI RT R W W W 1 W T W 1 Ww W 1 W T W W 16 Table 2 10 Serial Port 3 Interrupt Control Register Definitions Bits Field Name Description 15 5 MW Reserved 4 LTM Level Trigger Mode Sets the respective interrupt source 1 enable level triggered mode An interrupt generates when the external interrupt signal is HIGH 0 enable edge triggered mode default For both settings the level must remain HIGH until the interrupt is acknowledged 3 MSK Mask Interrupt 1 mask respective interrupt request default 0 enable respective interrupts 2 0 PR 2 0 Programmable Priority Level The programmable priority level for the respective interrupt source 111 lowest priority default 000 highest priority Serial Port 0 Interrupt Control Register Table 2 11 Serial Port 0 Interrupt Control Register BIT 12 1141 10 OFFSET 44h FIELD E 11 ollre gt A A A RESET 0 To Jo Jo 0 0 olo mime 1 T T i 1 RW R RW R RW RW T RW T RW T RI RI R RIRW I R TR TRT R Ww W w W 1 W iw WIWIW W Table 2 12 Serial Port 0 Interrupt Con
8. DMA 3 Interrupt Control Register Table 2 5 DMA 3 Interrupt Control Register BIT 12 11 10 OFFSET 4Ah FIELD x q Ill olg rig z DL DL DL RESET 0 o 0 0 0 0 0 mo fle fe Te 1 1 1 1 RW R RW R T RW RW T RW RW R TR TR T R TRWT RT RI RIR W W WIW IWI W WIWIWI NW 15 Table 2 6 DMA 3 Interrupt Control Register Definitions Bits Field Name Description 15 4 MW Reserved 3 MSK Mask Interrupt 1 mask respective interrupt request default 0 enable respective interrupts 2 0 PR 2 0 Programmable Priority Level The programmable priority level for the respective interrupt source 111 lowest priority default 000 highest priority DMA 2 Interrupt Control Register Table 2 7 DMA 2 Interrupt Control Register BIT 12 11 10 OFFSET 48h FIELD X olg rig z DL DL DL RESET olo 0 0 0 0 0 0 0 oloo 1 1 1 1 RW R RW R RW T RW T RW T RW R T R T R RI RW RI RI RIR W W WWW W WWW W Table 2 8 DMA 2 Interrupt Control Register Definitions Bits Field Name Description 15 4 MW Reserved 3 MSK Mask Interrupt 1 mask respective interrupt request default 0 enable respective interrupts 2 0 PR 2 0 Programmable Priority Level The programmable priority level for the respective interrupt source 111 lowest priority default 000 highest priority
9. DESCRIPTION This function will program a chip select register after setting the se appropriate wait state bits The caller of the function provides the bit values for the upper 11 bits of the chip select register KEKE KKK KKK KEKE KEKE KKK KKK KEKE KEK KEK KKK KKK KEKE KEKE KKK KKK KEKE KKK ck ck o ck ck ck ck ck ck ck ko ko ko ko ko Av void vSetChipSelect U16 ul6Reg U16 ul6Val U32 u32CpuSpeed U16 ul6DeviceNs Initially make sure the chip select bits are all zero ul6Val amp OXFFEO Set the wait state bits per CPU speed and device speed ul6Val ui6GetWaitStateBits u32CpuSpeed ul6DeviceNs Write to the chip select register outport ul6Reg ul6Val checksum c This source file contains sample code that demonstrates the use of the DSTni EX hardware checksum adder 103 KKK G KKK U16 L while ul6Len de sta sta ie Kk a a KR KEK KKK KKK KKK KKK KK KKK KKK KKK KK KKK KK KK KKK KKK KKK KKK KKK KKK KKK ERK FUNCTION U16 ul6CalcChecksum U16 pul6Data U16 ul6Len ARGUMENTS 2 pul6Data pointer to the buffer of data for which the checksum is to be computed ul6Len Number of 16 bit words to add ETURNS U16 containing the checksum ESCRIPTION This function perform a byte swapped checksum over a range of data using the hardware checksum generator of the DSTni EX
10. W o LED2 e Die ENC Dle SEN Dle LED1 Diol LEDO Table 3 7 LED Control Register Definitions Bits FieldName Description 15 6 Il Reserved Read only as O 5 ENC Encoding 0 lt the LED signals are driven directly with no encoding 1 the LED signals are driven through an encoder to allow connection to two wire Bi color LED s The un encoded signals are active LOW The encoded signals are shown with an E in front SEN 0 the LED signals are driven from the PHY 1 the LED signals are driven from this register LED3 LED3 Control Line Normally this bit connects to duplex signal If SEN 0 the LED3 signal is driven from the PHY and reading LED3 indicates the PHY status When duplex is 0 the PHY is in full duplex mode If SEN 1 the LED3 signal is driven from this register See Table 3 8 LED2 LED2 Control Line Normally this bit connects to the activity signal If SEN 7 0 the LED2 signal is driven from the PHY and reading LED2 indicates the PHY status Activity is 0 when the PHY detects or generates valid Ethernet traffic If SEN 1 the LED2 signal is driven from this register See Table 3 8 LED1 LED1 Control Line Normally this bit connects to the link signal If SEN 0 the LED1 signal is driven from the PHY and reading LED indicates the PHY status Link is 0 when the PHY has a valid link If SEN lt 1 the LED1 signal is driven from t
11. 13 End of Interrupt Write to the EOI Register When an interrupt service routine completes a program must write to the EOI register to reset the in service IS bit There are two types of writes to the EOI register specific EOI and non specific EOI see End of Interrupt Write to the EOI Register on page 14 Non specific EOI does not specify which IS bit is to be reset Instead the interrupt controller automatically resets the IS bit of the highest priority source with an active service routine Specific EOI requires the program to send the interrupt type to the interrupt controller to indicate the source IS bit that is to be reset Specific reset is applicable when interrupt nesting is possible or when the highest priority IS bit that was set does not belong to the service routine in progress Interrupt Controller Register Summary Hex Offset 4C 4A 48 46 44 Table 2 2 Interrupt Controller Register Summary Description CAN Interrupt Control register DMA 3 Interrupt Control register DMA 2 Interrupt Control register Serial Port 3 Interrupt Channel register Serial Port O Interrupt Channel register Page 15 15 16 16 17 42 Serial Port 1 Interrupt Channel register 17 40 Serial Port 2 Interrupt Channel register 18 3E INT3 or USB Interrupt Control register 19 3C INT2 SPI I7C Interrupt Control register 19 3A INT1 or Ethernet MAC 1 Interrupt Control register 21
12. 38 Ethernet MAC 0 INTO Interrupt Control register 22 36 34 DMA 1 Interrupt Control register DMA 0 Interrupt Control register 23 23 32 30 Timer Interrupt Control register Interrupt Status register 23 24 2E Interrupt Request register 25 2C In Service register 26 2A Priority Mask register 27 28 Interrupt Mask register 28 26 Poll Status register 29 24 Poll register 29 22 End of Interrupt EOI register 14 30 Register Definitions CAN Interrupt Control Register BIT 12 OFFSET Table 2 3 CAN Interrupt Control Register 11 10 FIELD 0 0 R R W W Table 2 4 CAN Interrupt Control Register Definitions Bits Field Name 15 5 Description Reserved 4 LTM Level Trigger Mode Sets the respective interrupt source 1 enable level triggered mode An interrupt generates when the external interrupt signal is HIGH 0 enable edge triggered mode default For both settings the level must remain HIGH until the interrupt is acknowledged 3 MSK 2 0 PR 2 0 0 enable respective interrupts Mask Interrupt 1 mask respective interrupt request default Programmable Priority Level The programmable priority level for the respective interrupt source 111 lowest priority default 000 highest priority
13. Acceptance code 0 LL Acceptance mask 1 L E TSE Acceptance code 1 TT f XI Acceptance mask 2 14 ey UE cd me Acceptance code 2 X Le Arb Lost Cap Reg Error Capture Reg Frame Refer Reg Ok kK o kx o xk ox Xk xk Ok ek o kx k kK xk xk Hi ID bits Lo ID bits Hi Data bits e ao She Lo Data bits Length Control 89 x DST DST DST DST DST DST DST DST DST_CAN1 DST_CAN1 DST_CAN1 DST_CAN1 DST CANT DST CANT DST_CAN1 DST_CAN1 DST_CAN1 DST_CAN1 DST_CAN1 DST CANT DST CANT DST CANT DST_CAN1 DST_CAN1 DST_CAN1 DST_CAN1 DST CANI1 DST_CAN1_ DST CANT DST_CAN1_ DST_CAN1 DST_CAN1 DST_CAN1 DST CANT DST CANT DST_CAN1 DST_CAN1 DST_CAN1 DST_CAN1 DST_CAN1 DST_CAN1 DST CANT DST_CAN1 DST_CAN1 DST_CAN1 DST_CAN1 DST_CAN1 DST CANT DST_CAN1_ DST CANT DST_CAN1 DST_CAN1 DST_CAN1 DST_CAN1 Transmit message 1 define DST_REG_CAN1_TX1_ID28_13 define DST REG CAN1 TX1 ID12 00 define DST REG CAN1 TX1 D63 48 define DST REG CANT TX1 DAT 32 define DST REG CAN1 TX1 D31 16 define DST REG CAN1 TX1 D15 00 define DST REG CAN1 TX1 LEN define DST REG CANT T
14. Auxiliary control define DST REG SP3BAUD DST REG PCB 0x00E8 Baud rate divisor define DST_REG_SP3RD DST REG PCB 0x00E6 Receive Data define DST REG SP3TD DST REG PCB 0x00E4 Transmit Data define DST_REG_SP3STS DST REG PCB 0x00E2 Status define DST REG SP3CT DST REG PCB 0x00EO0 Control Serial Port 0 registers define DST_REG_SPOAUX DST EG_PCB 0x008A Auxiliary control define DST_REG_SPOBAUD DST PCB 0x0088 Baud rate divisor define DST_REG_SPORD DST PCB 0x0086 Receive Data define DST_REG_SPOTD DST PCB 0x0084 Transmit Data define DST_REG_SPOSTS DS PCB 0x0082 Status define DST_REG_SPOCT DST PCB 0x0080 fe Control Serial Port 1 registers define DST_REG_SP1AUX DST_REG_PCB 0x001A RS422 RS485 Control define DST_REG_SP1BAUD l REG PCB 0x0018 Baud rate divisor define DST REG SP1RD G_PCB 0x0016 Receive Data define DST_REG_SP1TD E G_PCB 0x0014 Transmit Data define DST_REG_SP1STS G_PCB 0x0012 Status define DST_REG_SP1CT y G_PCB 0x0010 Control Serial Port 2 registers define DST_REG_SP2AUX DST REG PCB 0x000A Auxiliary control define DST REG SP2BAUD G_PCB 0x0008 Baud rate divisor define DST_REG_SP2RD D PCB 0x0006 Receive Data define DST_REG_SP2TD l REG PCB 0x0004 Transmit Data define DST REG SP2STS N _PCB 0x0002 Status define DST_REG_SP
15. Error Capture Reg Frame Ref Reg Xo WES es uk ee TAU Re AA A A A SE Ke k ke X X X ck ck o kK ox ox Xk X High byte of counter Low byte of counter BASE 0x10 BASE 0x12 BASE 0x14 BASE 0x16 BASE 0x18 BASE 0x1A _BASE 0x1C _BASE 0x1E _BASE 0x20 _BASE 0x22 _BASE 0x24 BASE 0x26 BASE 0x28 BASE 0x2A _BASE 0x2C _BASE 0x2E _BASE 0x30 _BASE 0x32 BASE 0x34 BASE 0x36 BASE 0x38 BASE 0x3A _BASE 0x3C _BASE 0x3E _BASE 0x40 BASE 0x42 BASE 0x44 _BASE 0x46 _BASE 0x48 _BASE 0x4A _BASE 0x4C _BASE 0x4E BASE 0x50 _BASE 0x52 BASE 0x54 _BASE 0x56 _BASE 0x58 _BASE 0x5A _BASE 0x5C _BASE 0x5E BASE 0x60 BASE 0x62 BASE 0x64 _BASE 0x66 _BASE 0x68 _BASE 0x6A _BASE 0x6C _BASE 0x6E _BASE 0x70 _BASE 0x72 _BASE 0x74 _BASE 0x76 _BASE 0x78 _BASE 0x7A k k Ox0A 0x08 0x06 90 Slave Select define define define DST DS DST 2 9 zu EG SPISTAT EG SPICTRL EG SPIDATA deu oce we Wee ce ues TAS n AE Oe P P s e USB Controller Registers kk E define define define define define define define define define define define define define define define define define define define define define define define define define define define def
16. Overload condition Receiver overrun Bit error during tx or rx Stuffing error during tx or rx Ack error during tx or rx Format error during tx or rx CRC error during tx or rx CAN is in bus off state Message 0 sent Message 1 sent Message 2 sent At least 1 tx buffer empty At least 1 rx message available Place controller to RUN mode Place controller to passive mode Internal loopback mode Sync on recessive to dom edge Sync on both edges Sample mode 0 1 point Sample mode 1 3 points Sync Jump width 1 Sync Jump width 2 Sync Jump width 3 Sync Jump width 4 Auto restart Overwrite last message Enable filter 0 Enable filter 1 Enable filter 2 Frame reference field mask Mask bit vector Mask bit vector Receiving data Transmitting data Frame reference field mask Error code field mask Ey Mask bit vector Transmitting data Receiving data Frame reference field mask Current bit state on trans line Current bit state on rec line Stuff bit inserted 99 El define define define define define define x xy define define define define define define define define define define define define define define define define define define define define define define define d
17. Wait i xCSn i 1 states 2 a Rey 1 states 2 a Rdy U l 1 2 Wait EN 2 Wait m SROV int i states i states i R ARDY i ARDYS int Note ARDY is internally synchronized on the falling edge of the CPUCLK For a normally ready system and an access cycle set for 0 wait the peripheral cannot respond in time to cause the CPU to wait If the system is normally not ready this can be accomplished with difficulty By adding 1 wait to the access cycle the system can respond in time to cause the CPU to wait However less than Ye clock time is needed and can be difficult to generate on faster systems By adding 2 waits the system can easily respond in time to cause the CPU to wait in all systems 67 PHY 10 100 Mbit The following figure shows two different but equivalent ways to attach DSTni to an RJ 45 connection 68 Fibre 100 Mbit C12 3 4 7uF C4 5 6 7 10nF 11 2 1uh R1 2 9 10 820hm R3 4 11 12 1300hm R7 8 1500hm R5 6 500hm IF FIBER MODULE has PECL SD R13 10Kohm R14 open IF FIBER MODULE has LVTTL SD R13 open R14 0 ohm Note If Fiber is not used leave all pins open 69 LED Functionality This section shows the LEDs associated with DSTni and describes their functions Figure 6 1 LEDs 1 2 Blinking full duplex y Solid 100Base T link Tx Rx activity 3 Blinking Error Indication 4 5 Blinking full duplex y Solid 100Bas
18. define DST CAN TXFL TRX 0x0001 Initiate transmit define DST CAN TXFL TXAB 0x0002 Abort transmit CAN Receive status masks define DST CAN RXST DLC OxOO0F Data length code define DST CAN RXST IDE 0x0010 Extended identifier bit define DST CAN RXST RTR 0x0020 Remote bit define DST CAN RXST AFI O0 0x0100 Acceptance filter 0 indicator define DST CAN RXST AFI 1 0x0200 Acceptance filter 1 indicator define DST CAN RXST AFI 2 0x0400 Acceptance filter 2 indicator CAN Error status register define DST CAN ERST STATE BOFF 0x0002 Bus off bit 0 is don t care define DST CAN ERST STATE ACT 0x0000 Error active normal operation define DST CAN ERST STATE PAS 0x0001 Error passive define DST CAN ERST TXGTE96 0x0004 Tx error count exceeds 96 define DST CAN ERST RXGTE96 0x0008 Rx error count exceeds 96 CAN Transmit Fifo interrupt levels define DST CAN TXFIFO LVLO 0x0000 Interrupt when all tx buffers MT define DST CAN TXFIFO LVL1 0x0001 ie when at least 2 buffers empty define DST_CAN_TXFIFO_LVL2 0x0002 pe when at least 3 buffers empty 98 CAN Receive Fifo interrupt levels define DST_CAN_RXFIFO_LVLO define DST_CAN_RXFIFO_LVL1 define DST_CAN_RXFIFO_LVL2 define DST_CAN_RXFIFO_LVL3 CAN Interrupt requests define DST CAN IRQ ARBLOSS define DST CAN IRQ OVRLOAD define DST define DST_ define DST define DST_ define
19. maul6WaitBits ul6WaitStates else ul6RetVal maul6WaitBits 15 Force the Ignore Ready bit on return ul6RetVal 0x0004 102 KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK ck kk FUNCTION ul6GetWaitStateBits U32 u32CpuSpeed U16 ul6DeviceNs ARGUMENTS 2 Ed u32CpuSpeed clock speed of the CPU in units of Hertz ul6DeviceNs device access time in units of nanoseconds RETURNS U16 The bit pattern for the wait states for the given combination of CPU Speed and device access time DESCRIPTION i This function given a CPU speed and device access time will compute b the required wait states for that device and return the appropriate wait state bit pattern KKK KK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KEK KK KKK KEK KK KK KKK kckckck ck kok U16 ul6GetWaitStateBits U32 u32CpuSpeed U16 ul6DeviceNs return ul6WaitStateBits ul6CalcWaitStates u32CpuSpeed ul6DeviceNs kkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FUNCTION vSetChipSelect U16 ul6Reg U16 ul6Val U32 u32CpuSpeed U16 ul6DeviceNs ARGUMENTS 4 E ul6Reg The 1 0 address of the register to be programmed 5 ul6Val The value other than wait states and ready bit m to write to the register N u32CpuSpeed The speed of the CPU in units of Hertz gt ul6DeviceNs device access time in units of nanoseconds RETURNS None
20. 2 75ns 3ns 85 75ns lt 5 20ns 4 wait states wait states 1 tCHCH Burst 24ns 10ns 2 75ns 3ns 38 75ns lt 2 20ns 1 wait states wait states 1 tCHCH 61 Page Flash CPUCLK ADDRESS UCSn kei UM re tent E DATA BUS bini Mise aa 7 o l tcHRDL m CHRDH w FTX d I I on e und A I e Fr ec a tCHWH I tGHWL WL CPUCLK i A231 Address UCSn 2 Wait States O wai M lCHAV l M CHAV 0 I I I Page Address Loaded Valid Page DB15 ReadDaja I r lCHRH b tours DB15 0 Write Data WM lCHWDV re tcHwov Flash access time is Initial Flash Access tcHAV tCHRDS Flash access time is Burst Flash Access tcHAv tCHRDS Example 50Mhz clock 20ns want to use 70ns flash 25ns page Initial 7Ons 1ns 3ns 74ns lt 4 20ns 3 wait states wait states 1 tCHCH Burst 25ns ins 3ns 29ns lt 2 20ns 1 wait states wait states 1 tcHCH 62 Serial Flash SP3_CTS_N SP3_TXD SP3_RTS_N DSTni EX Serial Flash SP3 RXD so RSTOUTn RSTn SPIEN 1 bit CSn 7 6 5 4 3 2 1 0 cs 7 6 5 4 3 2 1 0 bit NMN 1 S NN v NUUAM DAN s NAM Mai AXUUAM Static RAM Static RAM pog Async tcHRDL re tCHRDH DSTni EX 16 bit WRn ICLWL 1 8 W tCHWH I ween tin mo il ia A cr tqHwL tcLwL I Address
21. Clock Divider 1 0000 to 16 1111 Default 1 Note The USB clock must be 48 MHz for USB to work properly in high speed mode and 6 MHz for some low speed modes This may limit the CPU clock speeds that can be used if the USB is used If the USB is not used set the divider to the maximum to minimize power 35 Table 3 12 Divider Bits and Corresponding Values PLLMULT VCO Divider FB Divider USB Clock MHz 6 5 4 3 2 1 1 20r4 Divider USB CPU Notes Gray rows show values that can be used to run the USB at standard 1 2Mbit data rates The internal 256K bytes of memory use different internal refresh timing Therefore when the clock speed exceeds 63 MHz fewer internal refresh cycles can be performed This reduces the amount of power used by the internal memory These refresh cycles are transparent to the user and do not effect memory access speeds This register controls that timing If the internal PLL is bypassed and the CPU clock frequency exceeds 63 MHz this register must be programmed for 64 MHZ If the internal PLL is bypassed and the CPU clock frequency is 63 MHz or less program this register to 24 MHz Clock frequencies above 115 MHz are not guaranteed across all DSTni design specifications 36 Figure 3 1 PLL and Clock Generator 25 Mhz t
22. Each instruction includes an instruction mnemonic and zero or more operands A placeholder is shown for operands that must be provided The placeholder indicates the size and type of operand that is allowed The Operand Is a placeholder for imm8 An immediate byte a signed number between 128 and 127 imm16 An immediate word a signed number between 32768 and 32767 m An operand in memory m8 A byte string in memory pointed to by DS SI or ES DI m16 A word string in memory pointed to by DS SI or ES DI m16 amp 16 A pair of words in memory m16 16 A doubleword in memory that contains a signed relative offset displacement moffs8 A byte in memory that contains a signed relative offset displacement ptr16 16 A full address segment offset r8 A general byte register AL BL CL DL AH BH CH or DH r16 A general word register AX BX CX DX BP SP DI or SI r m8 A general byte register or a byte in memory 81 r m16 rel8 rel16 sreg Parameter 0 7 Ir sr cb cd CW A general word register or a word in memory A signed relative offset displacement between 128 and 127 A signed relative offset displacement between 32768 and 32767 A segment register Indicates that The Auxiliary field in the Operand Address byte specifies an extension from 0 to 7 to the opcode instead of a register The Auxiliary field in the Operand Address byte specifies a register instead of an opcode extension If the Opcode byte
23. VSS RSTINn tRIHROH RSTOUTn CLKOUT CPUCLK is ignored while RSTINn is driven low Power On Reset with no external connections is 200ms RSTOUTn is synchronized with the internal CLKOUT before it goes inactive External components Cdelay and Rdelay can extend RSTOUTn if needed The RSTINn input is LVTTL and TTL compatible 58 ATAL X1 X2 Rf Crystal Cx1 Cx2 25Mhz Fundamental Mode 25Mhz Fundamental Mode Quartz Crystal 100PPM Ceramic Resonator 100PPM Power On Oscillator Startup time is 50us maximum DSTni requires this crystal to be 25 MHz to use either the internal PLL or Ethernet PHY If using an external CPUCLK input PLLBYP 0 this crystal still is required at 25 MHz to use the Ethernet PHY If an external oscillator is used it is connected to the X1 input and X2 is left open CLKOUT cannot be used to drive X1 The capacitors Cx1 and Cx2 include PCB capacitance 59 Burst Flash 3 wire DATA BUS m ba ucsn 3 e tomb p U I RDn So an gt M lCHRDL 9 1 tcHRDH U i 3 Wire Burst oy rain Rre l a NA Ieu 9 to wd L it MIC dit Ap ienn t HwL tcLwL I ma i I M lCHAV K icHAV DB15 0 Read Dala 1 R CHRH 5 tcHRDS t mer TL ELI LE LE LIL ee tcHwov r tcHwov BCLK I BCLK i l pos AMD ferre IICLBCH i tcHBCL 1 14 LBAn j i I I gt M CHLBL TCHLBH BAAn bl
24. define DST REG CAN1 ACR2 D63 48 Analysis registers define DST REG CAN1 ALCR define DST REG CAN1 ECR define DST REG CAN1 FRR J kk Serial Peripheral Inteface registers kk aN define DST define define define DST DST DST PIO_BASE EG_SPICTRHI EG_SPICTRLO EG_SPISSEL 0xB800 DST SPIO BASI DST SPIO BASI DST SPIO BASI KR Ck Ck Ck ok Ck Ck Ck X X X X ck k ko KK ox ox ox k ox D uu CANT l CANT l CANT l CANT l CANT l CANT l CANT l CANT Hi ID bits Lo ID bits Hi Data bits XL E Lo Data bits Length Control Hi ID bits Lo ID bits Hi Data bits MI UA Lo Data bits Length Control Hi ID bit Lo ID bits Hi Data bits E aia TT Lo Data bits Length Control k f El kE Rx Tx err count Error Stat count Msg Level Thresh Interrupt Flags Interrupt enable Operating mode XL Filter enables Acceptance mask 0 A SE Acceptance code 0 XI PA Acceptance mask 1 i XL ZE oi Acceptance code 1 o XL T E Acceptance mask 2 75 A Li RES Acceptance code 2 TE El Arb Lost Cap Reg
25. 0x0080 Selects RTS mode SP2 RTR RTS pin define DST_AUXCON_ENRX1 0x0040 Selects ENRX mode SP1 CTS ENRX define DST_AUXCON_DTE1 0x0020 Selects RTS mode SP1 RTR RTS pin define DST AUXCON ENRXO 0x0010 Selects ENRX mode SPO CTS ENRX pin define DST AUXCON DTEO 0x0008 Selects RTS mode SPO RTR RTS pin PCB SYSCON System Configuration read only define DST SYSCON MCSO 0x4000 Enable MSCO over entire MCS range define DST SYSCON CD 0x0100 Disable clock output DCR DSTni Configuration Register define DST DCR BROMEN 0x4000 Boot ROM enabled define DST DCR ADDR24 0x2000 Extended address mode enabled define DST DCR WDOGEN 0x1000 Watchdog enabled define DST DCR SPIBOOT 0x0800 Boot from SPI enabled define DST R SPIEN 0x0400 SPI pins enabled in PIO define DST R ETHBOOT 0x0200 Ethernet boot enabled define DST R E HAN 0x0100 Ethernet channel 1 selected define DST R BICOLOR 0x0080 Using encoded LEDs define DST R PARBOOT Ox0040 Boot from parallel flash enabled define DST R PHYBYPASS 0x0020 Do not access Ethernet PHY via MII define DST R BYTEMODE 0x0010 Select hi lo byte read define DST DCR SERBOOT 0x0008 Enable boot via serial port define DST DCR SERCHAN 0x0004 Select serial port 0 or 1 for boot define DST DCR SERSPEED 0x0002 Select 9600 baud serial speed define DST DCR DEBUG 0x0001 Enable boot debug messages
26. All interrupt request bits are reset to 0 All mask MSK bits are set to 1 All interrupts are masked All cascade C bits are reset to 0 non cascade The interrupt priority mask is set to 7 permitting interrupts of all priorities O NO Qr de 5 The interrupt controller is initialized to master mode Polled Environments The interrupt controller can be used in polled mode if interrupts are not desired When polling interrupts are disabled and software polls the interrupt controller as required The interrupt controller is polled by reading the Poll Status register see Poll Status Register on page 29 Bit 15 indicates to the microprocessor that an interrupt of high enough priority is requesting service Bits 4 0 indicate to the microprocessor the interrupt type of the highest priority source requesting service After determining that an interrupt is pending software reads the Poll register see Poll Register on page 29 which causes the in service bit of the highest priority source to be set To enable reading of the Poll register information without setting the indicated in service bit DSTni provides a Poll Status register in addition to the Poll register The Poll Status register contains the same information in the Poll register however the Poll Status register can be read without setting the associated in service bit These registers are located in two adjacent memory locations in the peripheral control block
27. DEICE INsStructiONS ooooonnnccnnnnocanononcccnnnoncncnnnannnn non nennen e enne enne 44 Table 5 1 Absolute Maximum Ratings sss sese eee eee eee eee 49 Table 5 2 Recommended Operating Conditions ccccccceeceeceeeeeeeeeeeaeeeeeeeeeeeeeaeeeeeeeeeeeees 50 Table 5 3 I O Characteristics Xin Xout Pins tenete 51 Table 5 4 PHY Receiver Input Characteristics oooooocccinnnnnnnnncccnnnoncncnonacnnnnonnccnan nc nrnnnn emm 51 Table 5 5 100Base TX Transceiver Characteristics see 51 Table 5 6 100Base FX Transceiver Characteristics eee eee ee 51 Table 5 7 100Base T Transceiver Characteristics eee eee eee 52 Table 5 8 100Base T Link Integrity Timing Characteristics 52 Table 9 1 Baud Rate Calculations Using a CPU Clock Speed of 20 MHZ uu eee 107 Table 9 2 Baud Rate Calculations Using a CPU Clock Speed of 24 MHZ uu eee 108 Table 9 3 Baud Rate Calculations Using a CPU Clock Speed of 25 MHZ uu eee 109 Table 9 4 Baud Rate Calculations Using a CPU Clock Speed of 36 MHZ 109 Table 9 5 Baud Rate Calculations Using a CPU Clock Speed of 48 MHZ 110 Table 9 6 Baud Rate Calculations Using a CPU Clock Speed of 60 MHZ 110 Table 9 7 Baud Rate Calculations Using a CPU Clock Speed of 72 MHZ sese 111 Table 9 8 Baud Rate Calculations Using a CPU Clock Speed of 84 MHZ 111 Table 9 9 Baud Rate Calculations Us
28. DST define DST_ L define DST CAN IRQ BUS OFF define DST CAN IRQ TX XMITO define DST CAN TRO TX XMIT1 define DST CAN IRQ TX XMIT2 define define DST CAN IRO TX DON DST CAN IRO RX DON Mu vu CAN Interrupt enable define DST CAN IEN GENRL define DST_ IEN ARBLOSS define DST IEN OVRLOAD define DST_ IEN RX OVR define DST_ IEN BIT ERR define DST_ IEN STUF define DST define DST_ define DST define DST_ define DST define DST_ define DST define DST define DST CAN operating mode define DST CAN OPMOD RUN define DST CAN OPMOD PAS define DST CAN OPMOD LOOP CAN Configuration define DST CAN CFG SYNC RTOD define DST CAN CFG SYNC BOTH define DST CAN CFG SAMPL 0 define DST CAN CFG SAMPL 1 define DST CAN CFG SJW 1 define DST CAN CFG SJW 2 define DST CAN CFG SJW 3 define DST CAN CFG SJW 4 define DST CAN CFG AUTO RE define DST CAN CFG OVR MSG CAN acceptance filter enable define DST CAN FIL define DST CAN FILT define DST CAN FILT d CAN arbitration lost capture define DST CAN ALCR FRAME MSK define DST CAN ALCR BIT MSK CAN Error capture define DST CAN ECR BIT MSK define DST CAN ECR RXMOD define DST CAN ECR TXMOD define DST CAN ECR FRAME MSK define DST CAN ECR ERRCOD MSK CAN frame reference define DST CAN FRR BIT MSK define DST CAN FRR TXMOD define DST CAN FRR RXMO de
29. DST 7 define define define define define define define define define define PCB T1CON define DST 7 define DST 7 define DST 7 define DST 7 define DST 7 define define define define define DST 4 DST 1 DST_1 PCB T2CON define DST 7 define DST 7 define DST 1 define DST 7 DST T1 DST T1 l OCON ENABLE l OCON DISABLI q l OCON INT ENABLI l OCON RIU l OCON MC TOCON_RTG CON P TOCON_EXT TOCON_ALT l OCON CONT Timer 1 Control l1CON ENABLE 1CON_DISABLI q 1CON_INT_ENABLI T1CON_RIU l lCON MC D RTG T1CON_P EXT 1CON ALT 1CON CONT Timer 2 Control l ACON ENABLE 2CON_DISABLI q l 2ACON INT ENABLI D2 CON MC define DST_1 define define define define define define define define define define define define define define define define define define PCB REQST 2CON_CONT RV_CAN RV_DMA3 RV_DMA2 RV_SP3 RV_INT5 RV_SPO RV_SP1 RV_SP2 RV_USB RV_INT3 RV_SPI RV_I2C RV_MAC1 RV_INT1 RV_MACO RV_DMA1 RV_DMAO RV_TMR Al LET LS LR LE A LET LET S T ST El LET Gub A La DI Xf 0x2000 x 0x2000 Xf 0x2000 PCB INSERV Interrupt in service DST INSI DST INSI DST INSI DST INSI DST INSI DST INSI DST INSI DST INSI DST INSI DST INSI DST INSI DST INSI DST INSI DST INSI DST INSI DST INSI DST INSI DST
30. DST REG DOSRCH DST REG PCB 0x00C2 Source hi byte define DST REG DOSRCL DST REG PCB 0x00C0 Source lo byte 86 DMA 1 control registers define DST_REG_D1CON DST PCB OxOODA Control define DST_REG_D1TC DST PCB 0x00D8 Terminal Count define DST_REG_D1DSTH DST _PCB 0x00D6 Destination hi byte define DST_REG_D1DSTL DST PCB 0x00D4 Destination lo byte define DST_REG_D1SRCH DST PCB 0x00D2 Source hi byte define DST_REG_D1SRCL DST_ _PCB 0x00D0 Source lo byte DMA 2 control registers define DST_REG_D2CON DST_REG_PCB 0x009A Control define DST_REG_D2TC l REG PCB 0x0098 Terminal Count define DST REG D2DSTH G_PCB 0x0096 Destination hi byte define DST_REG_D2DSTL D G_PCB 0x0094 Destination lo byte define DST_REG_D2SRCH N G_PCB 0x0092 Source hi byte define DST_REG_D2SRCL D G_PCB 0x0090 Source lo byte DMA 3 control registers define DST_REG_D3CON DST_RE 0x00BA Pt Control y define DST_REG_D3TC DST_RI 0x00B8 Terminal Count define DST_REG_D3DSTH DST_RE 0x00B6 Destination hi byte define DST_REG_D3DSTL DST_RI 0x00B4 Destination lo byte define DST_REG_D3SRCH DST_RE 0x00B2 Source hi byte define DST_REG_D3SRCL DST_RI 0x00B0 Source lo byte Serial Port 3 registers define DST_REG_SP3AUX DST REG PCB 0x00EA
31. I RDV troz CPUCLK HOLD HLDA LCSn RDn WRHn l e Note WRn is not used as an input for the external DMA interface Wait states for the internal memory are not used for external DMA The RDn and WRxn signals are leading edge level sensitive Memory reads and writes always complete internally in one clock cycle following the leading edge detection Therefore the address bus is ignored after the rising edge of CPUCLK after the first leading edge of RDn and WRxn The external DMA can hold the RDn signal LOW as long as needed for data to be read properly The RDn can be released asynchronous to the CPUCLK For reads the data is latched from the memory after one clock and continues to be driven out the DATA BUS until released by RDn going HIGH The external DMA can hold the WRxn signal as long as necessary However the data is only written on the first rising edge of CPUCLK after the WRxn goes LOW 66 ARDY CPUCLK ARDY l l lCLARS I I CLARH Normally Ready System Normally Not Ready System CPUCLK xCSn a Rdy a Rdy s 0 Wait H 0 Wait G SRDY int states H states i ARDYS int i i Wait Wait xCSn 1 states a Rdy 1 states a Rdy i 1 i 1 Wait 1 Wait SROY int states U states i i i ARDYS int ARDY i i v e m ee L a a m e e a a a a L an m m r m r m m e s m l Wait
32. Jump short if not greater 13 4 3 1 2 J JNGE rel8 7C cb Jump short if not greater or equal 13 4 3 1 2 J JNL rel8 7D cb Jump short if not less 13 4 3 1 24J JNLE rel8 TF cb Jump short if not less or equal 13 4 3 1 2 J JNO rel8 71 cb Jump short if not overflow 13 4 3 1 2 J JNP rel8 7B cb Jump short if not parity 13 4 3 1 2 J JNS rel8 79 cb Jump short if not sign 13 4 3 1 2 J JNZ rel8 75 cb Jump short if not zero 13 4 3 1 2 J JO rel8 70 cb Jump short if overflow 13 4 3 1 2 J JP rel8 7A cb Jump short if parity 13 4 3 1 2 J JPE rel8 7A cb Jump short if parity even 13 4 3 1 2 J JPO rel8 7B cb Jump short if parity odd 13 4 3 1 2 J JS rel8 78 cb Jump short if sign 13 4 3 1 24J JZ rel8 74 cb Jump short if zero 13 4 3 1 2 J LAHF 9F Load AH with low byte of Processor 2 3 1 Status Flags register LDS C5 r Load DS r16 with segment offset 18 6 12 8 r16 m16 16 from memory LEA 8D r Load offset for m16 word in 16 bit 6 1 2 2 r16 m16 register LEAVE C9 Destroy procedure stack frame 8 5 5 74 Mnemonic Opcode Description 186 486 DSTni LES CA Ir Load ES r16 with segment offset 18 6 12 8 from memory LOCK FO Asserts LOCK during an instruction 1 1 0 execution LODS m8 AC Load byte segment SI in AL 12 5 4 LODS m16 AD Load word segment SI in AX 12 5 4 LODSB AC Load byte segment SI in AL 12 5 4 LODSW AD Load word segment SI in AX 12 5 4 LOOP
33. MACs This bit is the in service bit 7 13 Logical OR Connected to External Interrupt 3 and the USB Controller This bit is the in service bit for this interrupt source 6 12 Logical OR Connected to the SPI Controller and the IC Controller This bit is the in service bit for this interrupt source 5 11 Logical OR Connected to External Interrupt 1 and Ethernet MAC 1 This bit is the in service bit for this interrupt source 4 10 Ethernet MAC 0 This bit is the in service bit for this interrupt source 3 2 D 1 0 In Service Bits for DMA Channels DMA1 0 1 Ill Reserved 0 TMR Logical OR of All Timer Interrupt Requests The individual timer interrupt request bits are contained in the interrupt status register This bit cannot be written 25 In Service Register Table 2 35 In Service Register BIT OFFSET 2Ch FIELD Il l6 D3 D2 ES 25 P D I3 I2 11 lO D1 DO TMR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R RW Wi wi wt wi WW 1 W W W W wt wl wit wie wt W Table 2 36 In Service Register Definitions Bits Field Name Description 15 W Reserved 14 16 Logical OR Connected to Both CANO and CAN1 This bit is the in service bit for this interrupt source 13 12 D 3 0 Interrupt Request Bits for the DMA Channels DMA3 0 Setting any of these bits generates an interrupt request on the correspond
34. SAL D2 4 Multiply r m byte by 2 CL times 5 n 3 4 4 n r m8 CL 17 n SAL CO 4 ib Multiply r m byte by 2 imm8 times 5 n 2 4 4 n 78 Mnemonic Opcode Description 186 486 DSTni r m8 imm8 17 n SAL D1 4 Multiply r m word by 2 once 2 15 3 4 1 r m16 1 SAL D3 4 Multiply r m word by 2 CL times 5 n 3 4 4 n r m16 CL 17 n SAL C1 4 ib Multiply r m word by 2 imm8 times 5 n 2 4 4 n r m16 imm8 17 n SAR DO 7 Perform a signed division of r m 2 15 3 4 1 r m8 1 byte by 2 once SAR D2 7 Perform a signed division of r m 5 n 3 4 4 n r m8 CL byte by 2 CL times 17 n SAR CO 7 ib Perform a signed division of r m 5 n 2 4 4 n r m8 imm8 byte by 2 imme times 17 n SAR D1 7 Perform a signed division of r m 2 15 3 4 1 r m16 1 word by 2 once SAR D3 7 Perform a signed division of r m 5 n 3 4 4 n r m16 CL word by 2 CL times 17 n SAR C1 7 ib Perform a signed division of r m 5 n 2 4 4 n r m16 imm8 word by 2 imm8 times 17 n SBB 1C ib Subtract immediate byte from AL 3 1 1 AL imm8 with borrow SBB 1D iw Subtract immediate word from AX 4 1 1 AX imm16 with borrow SBB 80 3 ib Subtract immediate byte from r m 4 16 1 3 1 4 r m8 imm8 byte with borrow SBB 81 3 iw Subtract immediate word from r m 4 16 1 3 1 4 r m16 imm16 word with borrow SBB 83 3 ib Subtract sign extended immediate 4 16 1 3 1 4 r m16 imm8 byte from r m w
35. Token define DST_USB_TOKEN_P define DST USB CTL ODD define DST USB ADDR LS E define DST USB ADDR MASK RST EN I T Ox10 define DST USB TOKEN P define DST USB TOKEN P D O ID I ID S TUP USB Endpoint control define DST USB EP CTL define DST USB EP CTL define DST USB EP CTL Bit 5 is reserved define DST USB EP CTL define DST USB EP CTL define DST USB EP CTL define DST USB EP CTL 7 p Ed D pu endif waitstates c Wait 06 May 2003 WD include lt dos h gt include DstTypes h include lt math h gt Author 0x80 0x20 0x10 Data 0x04 CRC5 0x02 0x01 0x80 0x20 0x10 0x08 f Bit stuff error DMA error Bus turn around timeout field not 8 bits CRC16 error error host mode only EOF error peripheral mode only PID check failed Enable int on BTS error Enable in Enable in Enable in on DMA error on Bus timeout on data not 8 bits Ct ct c Enable int on CRC16 failure 0x02 0x02 0x01 Mask 0x08 on CRC5 error on EOF error on PID check error Enable in Enable in Enable in CEE ct the endpoint bits Buf desc table updated by TX Buf desc updated in odd bank 0x80 0x20 0x20 0x10 0x08 0x04 0x02 0x01 0x80 O
36. bit count range the maximum value of all ones is stored The current value of the TRACE buffer pointer is available in the upper eight bits of the TRACE_CTL scan chain You can set the current address by scanning in a value into this register After a trigger has occurred the register reflects the current pointer in the TRACE buffer Each time the TRACE scan chain is read the pointer automatically increments to the next value Consequently if the trace buffer size is 256 reading the TRACE scan chain 256 times reads all values in the buffer The value scanned into the TRACE scan chain is also written into that location of the TRACE buffer This lets you initialize the entire buffer to make it easier to verify that the TRACE buffer contains valid data Typically the TRACE_CTL scan chain is set to 0x00 and the TRACE scan chain is read N times where N is the size of the trace buffer while 48 bits of zeros are shifted in during the read This initializes the entire TRACE buffer with zeroes The desired trace mode is then selected via the TRACE_CTL and the HW_BKPT scan chains After a trigger occurs the TRACE buffer is read N times The first value read is the oldest value stored in the buffer the second value read is the next oldest and the last value read is the most recent value Any values that are all zeroes are probably unused values Table 4 3 TRACE Buffer Field Name Description TRACE Buffer TRACE Buffer Address Address 7 6
37. from defects in material and workmanship for a period specified on the product warranty registration card after the date of shipment During this period if a customer is unable to resolve a product problem with Lantronix Technical Support a Return Material Authorization RMA will be issued Following receipt of an RMA number the customer shall return the product to Lantronix freight prepaid Upon verification of warranty Lantronix will at its option repair or replace the product and return it to the customer freight prepaid If the product is not under warranty the customer may have Lantronix repair the unit on a fee basis or return it No services are handled at the customer s site under this warranty This warranty is voided if the customer uses the product in an unauthorized or improper way or in an environment for which it was not designed Lantronix warrants the media containing its software product to be free from defects and warrants that the software will operate substantially according to Lantronix specifications for a period of 60 DAYS after the date of shipment The customer will ship defective media to Lantronix Lantronix will ship the replacement media to the customer In no event will Lantronix be responsible to the user in contract in tort including negligence strict liability or otherwise for any special indirect incidental or consequential damage or loss of equipment plant or power system cost of capital
38. in pairs to specify an address range as follows HW BKPT 1 ADDR gt Current ADDR gt HW BKPT 2 ADDR 41 If CTL 7 6 11 the breakpoint is a simple address and cycle type comparison The cycle type can be optionally enabled with the low 3 bits of the CTL register This mode simply compares the current address on the bus with the value in the ADDR field of the HW_BKPT The DATA field is ignored If CTL 2 0 is not equal to 11 the desired cycle type must also match before the breakpoint triggers Note that this mode compares the value on the address bus and triggers on instruction queue fills If CTL 5 1 the breakpoint is set to Opcode Execute Breakpoint Mode In this mode the ADDR field is compared with the segment register and instruction pointer and a breakpoint is initiated when the ADDR matches the physical address pointed to by the segment register and instruction pointer The comparison is NOT on the ADDR bus but directly on the execution units Instruction Pointer This stops the CPU typically on the bus cycle when the opcode is about to be executed This mode is ideal for breaking on specific opcodes as it will not break on the prefetch of an opcode In this mode CTL 7 6 are ignored If CTL 4 1 the breakpoint is in Trace Qualifier mode In this mode the value in the ADDR field or the ADDR and DATA values in a register pair is used as a qualifier to store data into the TRACE buffer The COUNT field counts the
39. l imm8 by immediate byte INTO CE Generate interrupt 4 if Overflow 48 4 28 3 2 l Flag OF is 1 IRET CF Return from interrupt handler to 28 15 7 interrupted procedure JA rel8 77 cb Jump short if above 13 4 3 1 2 J JAE rel8 73 cb Jump short if above or equal 13 4 3 1 2 J JB rel8 72 cb Jump short if below 13 4 3 1 24J JBE rel8 76 cb Jump short if above or equal 13 4 3 1 2 J JC rel8 72 cb Jump short if carry 13 4 3 1 3 J JCXZ rel8 E3 cb Jump short if above 15 5 8 5 2 J JE rel8 74 cb Jump short if equal 13 4 3 1 2 J JG rel8 TF cb Jump short if greater 13 4 3 1 2 J JGE rel8 7D cb Jump short if greater or equal 13 4 3 1 2 J JL rel8 7C cb Jump short if less 13 4 3 1 2 J JLE rel8 TE cb Jump short if less or equal 13 4 3 1 2 J JMP EB cb Jump short direct displacement 14 3 2 J rel8 relative to next instruction JMP E9 cw Jump near direct displacement 14 3 2 J rel16 relative to next instruction JMP FF 4 Jump near indirect displacement 11 17 5 2 J r m16 relative to next instruction JMP EA cd Jump far direct to doubleword 14 17 2 J ptr16 16 immediate address JMP FF 5 Jump m16 16 indirect and far 26 13 2 J m16 16 JNA rel8 76 cb Jump short if not above 13 4 3 1 24J JNAE rel8 72 cb Jump short if not above or equal 13 4 3 1 2 J JNB rel8 73 cb Jump short if not below 13 4 3 1 2 J JNBE rel8 77 cb Jump short if not below or equal 13 4 3 1 2 J JNC rel8 73 cb Jump short if not carry 13 4 3 1 24J JNE rel8 75 cb Jump short if not equal 13 4 3 1 2 J JNG rel8 7E cb
40. loss of profits or revenues cost of replacement power additional expenses in the use of existing software hardware equipment or facilities or claims against the user by its employees or customers resulting from the use of the information recommendations descriptions and safety notations supplied by Lantronix Lantronix liability is limited at its election to refund of buyer s purchase price for such affected products without interest repair or replacement of such products provided that the buyer follows the above procedures There are no understandings agreements representations or warranties express or implied including warranties of merchantability or fitness for a particular purpose other than those specifically set out above or by any existing contract between the parties Any such contract states the entire obligation of Lantronix The contents of this document shall not become part of or modify any prior or existing agreement commitment or relationship For details on the Lantronix warranty replacement policy go to our web site at http www lantronix com support warranty index html Contents A Ww a o Copyright amp Trademark Warranty Contents List of Figures List of Tables About This User Guide Intended Audience Conventions Navigating Online Organization Interrupt Controller Overview Theory of Operation Interrupt Controller Register Summary Register Definitions Miscellaneous R
41. number of occurrences that the trigger condition must be met before the processor is halted 0 disables the breakpoint 1 halts on the first occurrence Oxff halts on the 255t occurrence Z To enable a breakpoint the desired breakpoint condition is scanned into the HW_BKPT scan chain Then the BREAKPT_ENB instruction should be executed and the target processor is then allowed to run by issuing a RUN instruction To stop the processor deassert control signals to the CPU after the breakpoint condition is recognized The breakpoint cannot stop on the actual breakpoint condition due to pipeline restrictions Consequently the processor stops at an instruction boundary When the breakpoint is in Opcode Execute Mode the processor stops before the instruction is executed In the other breakpoint modes the processor is stopped on the next instruction boundary after the desired bus cycle has been detected Trace Buffer The TRACE scan chain is a 48 bit chain that provides access to the 256x48 bit trace buffer in the CPUDICE core The TRACE scan chain is also identical to the DATA scan chain Each word in the TRACE buffer corresponds to one bus cycle The TRACE buffer operates in three different modes Normal TRACE mode Branch history mode and Timer mode In normal TRACE mode each word in the TRACE buffer corresponds to a single bus cycle Trace mode can optionally use the four hardware breakpoints as qualifiers for the data to be stored
42. ok k k kK kK ox Xk X control control control control control control control control control control 10 control 11 control 12 control 13 control 14 control LO O 1O0YU1 i CONO LA OO Ct Ct ct ct ct ct ct ct ct ct ct ct ct ct ct cf 15 control E S El T x El A x ef A x SU x El xy Software Reset Extended Slave Addr Clock Control Status 7 Control Data kf Address 91 o ck ck ck ck ko oko ck o E E E ko ck Ck o Ok Co Uk ko Ck o oko ko Ck E E E ko ko ko ko E E E E E ce koc Register field defines and masks kk x e PCB RELREG Relocation Register define DST_RELREG_PCB_IN_MEM 0x1000 Puts PCB in memory space define DST RELREG PCB IN IO 0x0000 Puts PCB in I O space PRL Processor Revision Level define DST PRL MSK REV OxFFOO Revision Number define DST_PRL_MSK_CPU Ox00FF CPU number PCB AUXCON Auxiliary Configuration define DST_AUXCON_ENRX3 0x0400 Selects ENRX mode SP3 CTS ENRX define DST_AUXCON_DTE3 0x0200 Selects RTS mode SP3 RTR RTS define DST_AUXCON_ENRX2 0x0100 Selects ENRX mode SP2 CTS ENRX define DST_AUXCON_DTE2
43. rel8 E2 Decrement count jump short if CX 16 6 7 6 3 J 0 LOOPE rel8 E1 cb Decrement count jump short if CX 16 6 9 6 3 J 0 and ZF 1 LOOPNE E0 cb Decrement count jump short if CX 16 6 9 6 3 J 0 and ZF 0 LOOPNZ EO cb Decrement count jump short if CX 16 6 9 6 3 J 0 and ZF 0 LOOPZ E1 cb Decrement count jump short if CX 16 6 9 6 3 J 0 and ZF 1 MOV 88 r Copy register to r m byte 2 1 1 r m8 r8 MOV 89 r Copy register to r m word 12 1 1 r m16 r16 MOV 8A r Copy r m byte to register 2 1 1 4 r8 r m8 MOV 8B r Copy r m word to register 9 1 1 4 r16 r m16 MOV BC sr Copy segment register to r m word 2 11 3 1 r m16 sreg MOV BE sr Copy r m word to segment register 2 9 3 9 1 4 sreg r m16 MOV AO Copy byte at segment offset to AL 8 1 1 AL moffs8 MOV A1 Copy word at segment offset to AX 8 1 1 AX moffs16 MOV A2 Copy AL to byte at segment offset 9 1 1 moffs8 AL MOV A3 Copy AX to word at segment offset 9 1 1 moffs16 AX MOV BO rb Copy immediate byte to register 3 1 1 r8 imm8 MOV B8 rw Copy immediate word to register 3 1 1 r16 imm16 MOV C6 0 Copy immediate byte to r m byte 12 1 1 r m8 imm8 MOV C7 0 Copy immediate word to r m word 12 1 1 r m16 imm16 MOVS A4 Copy byte segment Sl to ES DI 14 7 3 m8 m8 MOVS A5 Copy word segment Sl to ES DI 14 7 3 m16 m16 MOVSB A4 Copy byte segment SI to ES DI 14 7 3 MOVSW A5 Copy word segment SI to ES DI 14 7 3 MUL F6 4 AX r m byte AL 26 2
44. source to a unique priority level Note 1 Generated as a result of an instruction execution Note 2 Performed the same way as the 8086 Note 3 All three timers make up a single interrupt request from the interrupt controller and share the same priority level However each timer has a defined priority with respect to the other Priority level 2A is the highest followed by 2B and 2C Interrupt Type An 8 bit interrupt type identifies each of the 256 possible interrupts Software exceptions internal peripherals and non cascaded external interrupts supply the interrupt type through the internal interrupt controller Cascaded external interrupts and slave mode external interrupts get the interrupt type from the external interrupt controller by means of interrupt acknowledge cycles on the bus Interrupt Vector Table The interrupt vector table is a 1K memory area that starts at address 00000h It has up to 256 four byte address pointers containing the address for the interrupt service routine for each possible interrupt type For each interrupt an 8 bit interrupt type identifies the appropriate interrupt vector table entry Interrupts 00h to 5Ch are reserved see Table 2 1 on page 7 The microprocessor calculates the index to the interrupt vector table by shifting the interrupt type left two bits multiplying by 4 Maskable Nonmaskable Interrupts Interrupt types 08h through 1Fh are maskable Of these only 08h through 14h ar
45. specifies a byte register the registers are assigned as follows AL 0 CL 1 DL 2 BL 3 AH 4 CH 5 DH 6 and BH 7 If the Opcode byte specifies a word register the registers are assigned as follows AX 0 CX 1 DX 2 BX 3 SP 4 BP 5 SI 6 and DI 7 The Auxiliary field in the Operand Address byte specifies a segment register as follows ES 0 CS 1 SS 2 and DS 3 The byte following the Opcode byte specifies an offset The doubleword following the Opcode byte specifies an offset and in some cases a segment The word following the Opcode byte specifies an offset and in some cases a segment The parameter is an immediate byte The Opcode byte determines whether it is interpreted as a signed or unsigned number The parameter is an immediate word The Opcode byte determines whether it is interpreted as a signed or unsigned number The byte register operand is specified in the Opcode byte To determine the Opcode byte for a particular register add the hexadecimal value on the left of the plus sign to the value of rb for that register as follows AL 0 CL 1 DL 2 BL 3 AH 4 CH 5 DH 6 and BH 7 The word register operand is specified in the Opcode byte To determine the Opcode byte for a particular register add the hexadecimal value on the left of the plus sign to the value of rw for that register as follows AX 0 CX 1 DX 2 BX 3 SP 4 BP 5 SI 6 and DI 7 This number of clocks required for a register operand is different the numb
46. target Pin Signal ie Active Comments 1 Ill Ill Ill The target should not connect to these pins 2 DBRESET OUT HIGH Driven HIGH by the debugger to reset the target system Typically hooked into the target power on reset circuit 3 RESET IN HIGH Input to debugger informs debugger that a target reset has occurred 4 GND Signal reference 5 Ill Ill Ill The target should not connect to these pins 6 VCC IN Ill Used by debugger to determine target power on state Debugger does not draw significant current from this pin 7 Ill Ill Ill The target should not connect to these pins 8 GND Ill Ill Signal reference 9 Ill Ill Ill The target should not connect to these pins 10 GND Ill Ill Signal reference 11 Ill Ill Ill The target should not connect to these pins 12 TDI OUT HIGH JTAG signal 13 TDO IN HIGH JTAG signal 14 TMS OUT HIGH JTAG signal 15 GND Ill Ill Signal reference 111 Ill 111 16 TCK OUT HIGH JTAG signal 17 GND Signal reference 18 TRST OUT LOW JTAG signal optional 19 DBINST OUT LOW Driven low by the debugger 20 BSEN OUT LOW Driven low by the debugger Notes When designing in a target system connector for the debugger pay close attention to the TCK signal TCK is an edge sensitive signal where ringing is undesirable DBRESET can be active HIGH or LOW Configurable by the FS2 debugger The RSTIN is active LOW BSCEN must be HIGH for JTAG
47. test error Incoming frame was lost Frame received in RX ring Frame has been transmitted Initialization block read Logical or of MISS MFCO RCVCCO Interrupt enable Enable receiver Enable transmitter Force poll of RX amp TX rings Stop activity Start activity Load initialization block Mask missed frame interrupt Mask received frame interrupt Mask transmit done interrput Mask initialization done interrupt Disable transmit 2 part deferral 97 Ethernet Features control CSR4 define DST_ETHFEAT_DPOLL 0x1000 Disable transmit polling define DST_ETHFEAT_APADTX 0x0800 Pad frames shorter than 64 bytes define DST_ETHFEAT_MFCO 0x0200 Missed frame counter overflow define DST_ETHFEAT_MFCOM 0x0100 Mask MFCO interrupt define DST_ETHFEAT_RPA 0x0080 Enable runt packet reception define DST_ETHFEAT_RCVCCO 0x0020 Receive collision counter overflow define DST_ETHFEAT_RCVCCOM 0x0010 Mask RCVCCO interrupt define DST_ETHFEAT_TXSTRT 0x0008 Transmit has started define DST_ETHFEAT_TXSTRTM 0x0004 Mask TXSTRT interrupt define DST_ETHFEAT_PAUSE 0x0002 Pause control frame received define DST_ETHFEAT_PAUSEM 0x0001 Mask PAUSE interru
48. the external interrupt signal is HIGH 0 enable edge triggered mode default For both settings the level must remain HIGH until the interrupt is acknowledged 3 MSK Mask Interrupt 1 mask respective interrupt request default 0 enable respective interrupts 2 0 PR 2 0 Programmable Priority Level The programmable priority level for the respective interrupt source 111 lowest priority default 000 highest priority 18 INT3 or USB Interrupt Control Register Table 2 17 INT3 or USB Interrupt Control Register 412 11 10 9 ead 8Eh FIELD Ill Se ll E sae ete Bh sE RESET olo 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RW R IRWIR RW T RW T RW T RW RI RI R TR TRWT RI RI RIR W W W 1 W T W 1 Ww W wi wiw Table 2 18 Serial Port 2 Interrupt Control Register Definitions Bits Field Name Description 15 5 W Reserved 4 LTM Level Trigger Mode Sets the respective interrupt source 1 enable level triggered mode An interrupt generates when the external interrupt signal is HIGH 0 enable edge triggered mode default For both settings the level must remain HIGH until the interrupt is acknowledged 3 MSK Mask Interrupt 1 mask respective interrupt request default 0 enable respective interrupts 2 0 PR 2 0 Programmable Priority Level The programmable priority level for the respective interrupt source 111 lowest pr
49. 0 DST_REQST_INT5 DST_IMASK_SPO 0x0400 DST_IMASK_SP1 0x0200 DST_IMASK_SP2 0x0100 DST_IMASK_USB 0x0080 DST_IMASK_INT3 0x0080 DST_IMASK_SPI 0x0040 DST IMASK I2C 0x0040 DST IMASK INT1 0x0020 DST IMASK MAC1 DST IMASK MACO 0x0010 DST IMASK DMA1 0x0008 DST IMASK DMAO 0x0004 DST IMASK TMR 0x0001 DST IMASK ALL PCB PRIMSK Interrupt priority mask DST PRIMSK L7 DST PRIMSK L6 DST PRIMSK L5 DST PRIMSK L4 DST PRIMSK L3 DST PRIMSK L2 DST PRIMSK L1 DST PRIMSK L0 PCB INSTS Interrupt status DST INTSTS DHLT DST INTSTS TMR2 DST INTSTS TMR1 DST INTSTS TMRO PCB xxxCON Peripheral interrupt control DST PERCON MSK DST PERCON PRI L7 DST ERCON_PRI_L6 DST ERCON_PRI_L5 DST ERCON_PRI_L4 DST ERCON_PRI_L3 DST ERCON_PRI_L2 DST ERCON_PRI_L1 DST ERCON_PRI_LO apa el 9999999 Q PCB IxCON Interrupt 5 0 control DST_IXCON_LTM DST_IXCON_MSK DST_IXCON_PRI_L7 DST_IXCON_PRI_L6 DST_IXCON_PRI_L5 DST_IXCON_PRI_L4 DST_IXCON_PRI_L3 DST_IXCON_PRI_L2 DST_IXCON_PRI_L1 DST_IXCON_PRI_LO EOI End of interrupt define PCB define define DST_EOI_NONSPEC DST POLL IRO DST POLL VECTOR MSK 0x001F DMA channel 3 DMA channel 2 LE TD 0x0800 15 13 LE uu 3 prota PY TZ fr pus 0x0020 TO serial port 3 I5 Extneral INT5 pin Serial Port 0 Serial Port 1 Serial Port 2 USB 7 External IN
50. 0 136 137 38602 94 38321 17 0 53 021 28800 182 183 28846 15 28688 52 0 16 0 39 19200 273 274 19230 77 19160 58 0 16 0 21 9600 546 547 9615 385 9597 806 0 16 0 02 7200 729 730 7201 646 7191 781 0 02 0 11 4800 1093 1094 4803 294 4798 903 0 07 0 02 2400 2187 2188 2400 549 2399 452 0 02 0 02 1200 4375 4376 1200 1199 726 0 00 0 02 111 Table 9 9 Baud Rate Calculations Using a CPU Clock Speed of 96 MHz Baud Rate Divisor Low Divisor High Freq High Freq Low High Error Low Error 112
51. 001 Unmask the timer interrupt outport DST REG IMASK inport DST REG IMASK amp DST IMASK TMR Restore interrupt state asm popf H kkkkxkkkkxkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FUNCTION void vTmrInt void ARGUMENTS 0 zal ETURNS none IS ESCRIPTION This is the interrupt handler for the timer It will check the software timers for watchdog serial port and LEDs KR KEK KEK KKK KEK KK KKK KK KK KKK RK KK KKK RK KK KKK KKK KKK KKK KKK KKK KKK KKK KEKE 105 static void interrupt vTmrInt void Clear the Max Count bit outport DST REG T1CON 0x2009 Bump the system clock mu32SysTime Clear the interrupt outport DST REG EOI DST IVECT TMR1 H kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FUNCTION void vDstTimerHalt void ARGUMENTS 0 RETURNS void DESCRIPTION Halts operation of the timer KEKE KKK KKK KKK KEKE KKK KKK KEKE KKK KKK KKK KKK KKK KKK KKK KEKE KEKE KKK ck ck ck ck ck ck ko ko ko ko ko void vDstTimerHalt void Make sure timers are stopped by clearing the EN bit outport DST REG T1CON 0x4000 outport DST REG T2CON 0x4000 Mask the timer interrupt outport DST REG IMASK inport DST REG IMASK DST IMASK TMR Clear any timer interrupts that may be pending
52. 2 0 Valid settings are 000 interrupt ACK 001 read IO 010 write IO 011 halt 100 instruction fetch 1012 read memory 110 write memory 111 7 idle CTL 3 sixteen 0 8 bit cycle 1 16 bit cycle CTL 4 IQ flush for APPLYs CTL 5 DATA for APPLYs The following bits are used only in HW_BKPT chains CTL 4 TR_QUAL mode CTL 5 OP_EXEC mode CTL 7 6 MODE 40 STATUS Scan Chain The STATUS scan chain consists of a single 8 bit register with some status information as listed in the table below Table 4 2 STATUS Scan Chain Bits Field Name Description 7 4 Ill Reserved 3 Middle of Cycle Middle of Cycle 1 only the first half of a two part bus cycle has completed This condition can happen if the processor is stopped on the first bus cycle of a 16 bit access to an odd address Do not to insert any bus cycles when this bit is set the processor must first be single stepped one bus cycle to compete the access before any bus cycles are forced by the JTAG debugger 2 OP_FETCH OP_FETCH 1 processor is expecting to fetch an opcode This lets the debugging software know that the processor is about to fetch an opcode Software can then substitute its own opcodes in place of the ones from the system to interrogate or change the value of any register 1 Breakpoint Flag Breakpoint Flag 1 the breakpoint is currently being searched It is set when the ENB_BKPT instruction is loaded into
53. 2 iw Add immediate word to r m byte 4 16 1 3 1 4 r m16 imm16 with carry ADC 83 2 ib Add sign extended immediate byte 4 16 1 3 1 4 r m16 imm8 to r m word with carry ADC 10 r Add byte register to r m byte with 3 10 1 1 1 4 r m8 r8 carry ADC 11 r Add word register to r m word with 3 10 1 1 1 4 r m16 r16 carry ADC 12 r Add r m byte to byte register with 3 10 Y 1 4 r8 r m8 carry ADC 13 r Add r m word to word register with 3 10 Y 1 4 r16 r m16 carry ADD 04 ib Add immediate byte to AL 3 1 1 AL imm8 ADD 05 iw Add immediate word to AX 4 1 1 AX imm16 ADD 80 0 ib Add immediate byte to r m byte 4 16 1 3 1 4 r m8 imm8 ADD 81 0 iw Add immediate word to r m word 4 16 1 3 1 4 r m16 imm16 ADD 83 0 ib Add sign extended immediate byte 4 16 1 3 1 4 r m16 imm8 to r m word ADD 00 r Add byte register to r m byte 3 10 1 1 1 4 r m8 r8 ADD 01 r Add word register to r m word 3 10 1 1 1 4 r m16 r16 ADD 02 r Add r m byte to byte register 3 10 Y 1 4 r8 r m8 ADD 03 r Add r m word to word register 3 10 Y 1 4 r16 r m16 AND 24 ib AND immediate byte with AL 3 1 1 AL imm8 AND 25 iw AND immediate word with AX 4 1 1 AX imm16 AND 80 4 ib AND immediate byte with r m byte 4 16 1 3 1 4 r m8 imm8 AND 81 4 iw AND immediate word with r m word 4 16 1 3 1 4 r m16 imm16 AND 83 4 ib AND sign extended immediate byte 4 16 1 3 1 4 71
54. 2CT D _PCB 0x0000 Control LED Control Register define DST_REG_LEDC DST REG PCB 0x007E Programmable I O Bank 1 bits 31 16 registers define DST REG PIODATA1 DST REG PCB 0x007A Input Output Data define DST_REG_PIODIR1 DST_REG_PCB 0x0078 Direction Select define DST_REG_PIOMODE1 DST_REG_PCB 0x0076 Mode Select Programmable I O Bank 0 bits 15 registers define DST_REG_PIODATAO DST_REG_PCB 0x0074 Input Output Data define DST_REG_PIODIRO DST_REG_PCB 0x0072 Direction Select define DST_REG_PIOMODEO DST_REG_PCB 0x0070 Mode Select 87 k x KK Ok ko ck k kK kK X k o k xk KK Ok Ok k k kK kK ox k k OK Ethernet Controller Registers KO Ok kK kx X ok k ko koX o ck ck ck oco ko ko ko oko E Uk ko ko ck Ck Ok ko Uk ko Ck ko ko ck E E E H ko ko ko Ok C ko ko ko ko Aoc Peripheral device I O addresses These are the peripheral devices not part Ke k k X X ok ck k kK dede ox ox xk Ke k X kK X ok ck k RK kK ox ox ox X of the Peripheral Control Block KO Ok kK X X ok ck ck o X Kk Xk k k ox OK define DST ETHO BASE 0x9000 define DST ETH1 BASE 0x9100 define DST RE
55. 469 469 4807 692 4797 441 0 16 0 05 2400 937 938 2401 281 2398 721 0 05 0 05 1200 1875 1876 1200 1199 36 0 00 0 05 109 Table 9 5 Baud Rate Calculations Using a CPU Clock Speed of 48 MHz Baud Rate DivisorLow Divisor High Freq High High Error Low Error 921600 3 4 1000000 750000 8 51 18 62 460800 6 7 500000 4285714 8 51 6 99 230400 13 14 230769 2 214285 7 0 16 6 99 115200 26 27 115384 6 111111 1 0 16 3 59 76800 39 40 76923 08 75000 0 16 2 34 57600 52 33 57692 3 56603 77 0 16 1 73 56000 53 54 56603 77 55555 56 1 08 0 79 38400 78 79 38461 54 37974 68 0 16 1 11 28800 104 105 28846 15 28571 43 0 16 0 79 19200 156 157 19230 77 19108 28 0 16 0 48 9600 312 213 9615 385 9584 665 0 16 0 16 7200 416 417 7211 538 7194 245 0 16 0 08 4800 625 626 4800 4792 332 0 00 0 16 2400 1250 1251 2400 2398 082 0 00 0 08 1200 2500 2501 1200 1199 52 0 00 0 04 Table 9 6 Baud Rate Calculations Using a CPU Clock Speed of 60 MHz Baud Rate Divisor Low Divisor High High Error Low Error 921600 4 5 937500 750000 1 73 18 62 460800 8 9 468750 416666 7 1 73 9 58 230400 16 17 234375 220588 2 1 73 4 26 115200 32 33 117187 5 113636 4 15735 1 36 76800 48 49 78125 76530 61 1 73 0 35 57600 65 66 57692 31 56818 18 0 16 1 36 56000 66 67 56818 18 55970 15 1 46 0 05 38400 97 98 38659 79 38265 31 0 68 0 35 28800 130 131 28846 15 28625 95 0 16 0 60 19200 195 196 19230 77 19132 65 0 16 0 35
56. 5 TRACE SIZE TRACE SIZE Read Only III Reserved 1 256 words 0 16 words Trace Buffer Test Mode Trace Buffer Test Mode 1 no writes to trace buffer allowed when bus cycles execute 0 writes to trace buffer allowed when bus cycles execute 3 2 Mode Mode Mode 00 normal 01 branch history 10 timer mode 11 reserved Ill Reserved 43 DEICE Instructions The Instruction register selects certain modes of operation and scan chains as described in Table 4 4 All instructions require the least significant two bits to be 01 which require the INST register to be set to the appropriate settings per the 1149 1 specification Table 4 4 DEICE Instructions Instruction Hex Scan Chain Description EXTEST 00 Required by IEEE 1149 1 STOP 11 ADDR Forces READY low CPU stops execution immediately Remains halted until the RUN instruction is executed RUN 21 ADDR Releases the processor from HALT ENB_BKPT 31 STATUS Run until the breakpoint is reached STATUS 41 STATUS Select the STATUS scan chain ONE_OP 51 ADDR Execute one opcode ONE_CLK 61 ADDR Execute one processor bus cycle OP_ADDR 71 ADDR Capture the address of the next opcode fetch ADDR 81 ADDR Select the ADDR scan chain DATA 91 DATA Select the DATA scan chain TRACE A1 TRACE Select the TRACE scan chain TRACE CTL B1 TR CTL Select the TRACE Control scan chain BR
57. 8 5 5 12 15 r m8 32 34 MUL F7 4 DX AX r m word AX 35 37 5 6 20 23 r m16 41 43 NEG F6 3 Perform a two s complement 3 10 1 3 1 4 r m8 negation of r m byte 75 Mnemonic Opcode Description 186 486 DSTni NEG F7 3 Perform a two s complement 3 10 1 3 1 4 r m16 negation of r m word NOP 90 Perform no operation 3 1 1 NOT F6 2 Complement each bit in r m byte 3 10 1 3 1 4 r m8 NOT F7 12 Complement each bit in r m word 3 10 1 3 1 4 r m16 OR OC ib OR immediate byte with AL 3 1 1 AL imm8 OR OD iw OR immediate word with AX 4 1 1 AX imm16 OR 80 1 ib OR immediate byte with r m byte 4 16 1 3 1 4 r m8 imm8 OR 81 1 iw OR immediate word with r m word 4 16 1 3 1 4 r m16 imm16 OR 83 1 ib OR immediate byte with r m word 4 16 1 3 1 4 r m16 imm8 OR 08 r OR byte with r m byte 3 10 1 3 1 4 r m8 r8 OR 09 r OR word with r m word 3 10 1 3 1 4 r m16 r16 OR OA r OR r m byte with byte register 3 10 1 3 1 4 r8 r m8 OR 0B r OR r m word with word register 3 10 1 3 1 4 r16 r m16 OUT E6 ib Output AL to immediate port 9 19 4 imm8 AL OUT E7 ib Output AX to immediate port 9 19 4 imm8 AX OUT EE Output AL to port in DX 7 19 1 DX AL OUT EF Output AX to port in DX 7 19 1 DX AX OUTS 6E Output byte DS SI to port in DX 14 14 4 DX m8 OUTS 6F Output word DS SI to port in DX 14 14 4 DX m16 OUTSB 6E
58. 8 0x0400 Transmit Bit 8 DST_SPXCT_FC_EN 0x0200 Enable flow control DST_SPXCT_TXIE 0x0100 Transmitter empty interrupt enable DST_SPXCT_RXIE 0x0080 Receive data interrupt enable DST_SPXCT_TMOD 0x0040 Enable transmitter DST_SPXCT_RMOD 0x0020 Enable receiver DST_SPXCT_PARITY_EVN 0x0018 Select even parity DST_SPXCT_PARITY_ODD 0x0008 Select odd parity DST_SPXCT_PARITY_NONE 0x0000 Select no parity DST_SPXCT_MODE_1 0x0001 Select mode 1 DST_SPXCT_MODE_2 0x0002 Select mode 2 DST_SPXCT_MODE_3 0x0003 Select mode 3 DST_SPXCT_MODE_4 0x0004 Select mode 4 DST_SPXCT_MODE_5 0x0005 Select mode 4 PxSTS Serial port status DST_SPXSTS_BRK1 0x0400 Long break detected DST_SPXSTS_BRKO 0x0200 Short break detected DST_SPXSTS_RB8 0x0100 Receive bit 8 DST_SPXSTS_RDR 0x0080 Receive data ready DST_SPXSTS_THRE 0x0040 Transmit holding register empty DST_SPXSTS_FER 0x0020 Framing error DST_SPXSTS_OER 0x0010 Overrun error DST_SPXSTS_PER 0x0008 Parity error DST_SPXSTS_TEMT 0x0004 Transmitter empty DST_SPXSTS_HSO 0x0002 Handshake 0 CTS active PxAUX Serial port Aux control DST_SPXAUX_BRGO 0x0800 Connect RTS out to baud generator DST_SPXAUX_FIFO_1 0x0000 Set FIFO depth to 1 byte DST_SPXAUX_FIFO_2 0x0020 Set FIFO depth to 2 bytes DST_SPXAUX_FIFO_3 0x0040 Set FIFO depth to 3 bytes DST_SPXAUX_FIFO_4 0x0060 Se
59. 9600 390 391 9615 385 9590 793 0 16 0 10 7200 520 521 7211 538 7197 697 0 16 0 03 4800 781 782 4801 536 4795 396 0 03 0 10 2400 1562 1563 2400 768 2399 232 0 03 0 03 1200 3125 3126 1200 1 199 616 0 00 0 03 110 Table 9 7 Baud Rate Calculations Using a CPU Clock Speed of 72 MHz Baud Rate DivisorLow Divisor High Freq High Freq Low High Error Low Error 921600 4 5 1125000 900000 22 07 2 34 460800 9 10 500000 450000 8 51 2 34 230400 19 20 236842 1 225000 2 80 2 34 115200 39 40 115384 6 112500 0 16 2 34 76800 58 59 77586 21 76271 19 1 02 0 69 57600 78 79 57692 31 56962 03 0 16 Sah 56000 80 81 56250 55555 56 0 45 0 79 38400 117 118 38461 54 38135 59 0 16 0 69 28800 156 157 28846 15 28662 42 0 16 0 48 19200 234 235 19230 77 19148 94 0 16 0 27 9600 468 469 9615 385 9594 883 0 16 0 05 7200 625 626 7200 7188 498 0 00 0 16 4800 937 938 4802 561 4797 441 0 05 0 05 2400 1875 1876 2400 2398 721 0 00 0 05 1200 3750 3751 1200 1 199 68 0 00 0 03 Table 9 8 Baud Rate Calculations Using a CPU Clock Speed of 84 MHz Baud Rate Divisor Low Divisor High Freq High FreqLow High Error Low Error 921600 5 6 1050000 875000 13 93 5 06 460800 11 12 477272 7 437500 3 57 5 06 230400 22 23 238636 4 228260 9 3 57 0 93 115200 45 46 116666 7 114130 4 27 0 93 76800 68 69 77205 88 76086 96 0 53 0 93 57600 91 92 57692 31 57065 22 0 16 0 93 56000 93 94 56451 61 55851 06 0 81 0 27 3840
60. BYP N PLL Bypass Pin 1 PLL is being used to generate CPUCLK 0 PLL is being bypassed and CPUCLK is receiving a clock to use as CPUCLK 12 LOCKED PLL LOCKED 1 7 indicates the PLL has locked onto the desired frequency set by PLLMULT 0 PLL is trying to change to the desired frequency For frequencies below 13 MHZ lock may not be possible because of PLL jitter 11 4 PLLMULT PLL Multiplier x1 01h to x7Fh Default x18h 24 MHz The PLL Multiplier sets the value that the PLL uses to multiply the input clock With a 25 MHz crystal the frequency will be a multiple of 1 MHz The maximum clock rate is limited by the CPU cycle time Exceeding this value causes unpredictable results The PLL output is connected directly to the CPU Clock unless the PLLBYP PLL Bypass is pulled LOW The clock is sourced from the CLKOUT pin which is then tri stated by PLLBYP_n being LOW in this case the PLL is not used and should be run as slowly as possible to minimize power Be aware of the impact the clock frequency has on Flash access time and serial baud rates and adjust the other appropriate register values 3 0 USBDIV USB Clock Divider These four bits set the USB clock divider from the PLL output clock frequency to the USB block The input clock to the USB divider is 2 times the CPUCLK rate when the PLL is used PLLBYP_n 1 The input to the USB divider is connected to CLKOUT signal directly when PLL is disabled PLLBYP_n 0 See Table 3 12
61. CHWH WL tawl 1 Address I B m icHAV m tcHav l I 1 l 1 tCHRH l l h lCHRDS I D8150 ed Write Data J M CHWDV m tcHWDV X TMRINx DRQx 1 l CHIH m m tchiL TMROUTx LN I Il CHTOH 1 m tcHTOL R PIO 31 0 in y l l CHPIS m l m CHPIH l l l l lCHPOV Note All input signals are synchronized before use inside the DSTni EX All outputs use the rising edge of CPUCLK to generate the output signals Any signals that use the falling edge of CPUCLK are shown on specific application diagrams For slow digital signals hidden behind PIO pins or not shown above use tCHPIS for setup tCHPIH for hold and tCHPOV for output delay 56 Data Name Description Min Typ Max units IN 50 OUT 5096 tphi Note For non tri state I O cells the propagation delay is measured from the 50 point of the input waveform to the 50 point of the output waveform For tri state I O cells since the tri state status may not exhibit any change in the output waveform we define the propagation delay disable time as the time form 50 of the disable signal to the turning on off threshold level of the n and p MOS transistors 57 Reset VDD VDD Internal Pull Up Resistor 56 122Kohms Dbetay RSTINn RSTOUTn Internal Reset Delay CDelay coco Internal to ASIC n
62. CPU Limitations This is designed to perform computation over an even number of bytes The buffer is expected to start on an even byte boundary Extra logic would be required to adjust for odd byte length or odd byte boundaries Because this function uses a hardware resource it must be protected from reentrancy or corrupted sums can result kkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk ul6CalcChecksum U16 pul6Data U16 ul6Len Initialize the checksum adder make sure it s zeroed outport DST_REG_CAR 0 outport DST_REG_CDR 0 7 outport DST REG CAR pul6Data ul6Len Get the result return inport DST_REG_CDR timer c This source file demonstrates the use of a two stage timer This may be needed when the DSTni EX is set to run at a high clock speed and a slow timer tick is needed For example if you want a timer tick to occur 100 times per second 10ms per tick and the CPU is set to run at 48 MHz a timer divisor of 120 000 would be required Because the timer only supports 16 bits the value cannot be programmed In this case set up Timer 2 to act as a pre scale to one of the other timers fine TMR_TICKS_PER_SEC 200 5ms per tick tic void interrupt vTmrint void tic U32 mu32SysTime Number of ticks since reset kkkkxkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk UNCTION vDstTimerInit U32 u32CpuSpeed RGUMENTS 1 u32CpuSp
63. DCR DST REG PCB define DST REG RCR DST REG PCB define DST REG PRL DST REG PCB define DST REG AUXCON DST REG PCB 0x00F2 define DST REG SYSCON DST REG PCB Chip select registers define DST REG CAR DST REG PCB define DST REG CDR DST REG BCB define DST_REG_PRCS DST_REG_PCB define DST_REG_MPCS DST_REG_PCB define DST_REG_MMCS DST_REG_PCB define DST_REG_PACS DST_REG_PCB define DST_REG_LMCS DST_REG_PCB define DST_REG_UMCS DST REG PCB 0x00A0 Relocation Register 0x00F8 DSTni Configuration Reg OxOOF6 Reset Configuration Reg 0x00F4 Processor Release Reg EJ Auxiliary Configuration Ox00FO System Configuration ia Ox00AE Checksum Adder Ox00AC Checksum Data Ox00AA Page Chip Select x 0x00A8 Memory Peripheral Ctrl 0x00A6 Mid Memory Chip Select 0x00A4 Peripheral Chip Select f 0x00A2 Lower Memory Chip Select Upper Memory Chip Select 85 Phase lock loop CPU clock and SPI control define DST_REG_PLLCLKUSB DST REG PCB 0x006E Watchdog define DST imer register EG WDTCON DST R a T za G_PCB 0x006C Random number generator Linear counter define DST_REG_RNG DST REG PCB 0x006A SDRAM control define DST REG SDRAMCTRL DST REG PCB 0x0068 Control register define DST REG REFMAX DST REG PCB 0x0064 Refresh maxcount Timer 2 registers d
64. DST USBO BAS DST USBO BAS DST USBO BAS DST USBO BAS DST USBO BAS DST USBO BAS DST USBO BAS BASI BASI BASI BASI BASI BASI BASI BAS BASE BASE 0x04 0x02 0x00 Ok Ok kK ok xk Eg Ed DE Dd wae 0x08 0x09 0x0B 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 Ox1A Ox1B Ox1C Ox1D Ox1E ce Status FE Control Write Read data de ue Gn e es us en h P ROA RR LM E EL EE E E E NE ME 0x07 tthe eat o x e Ww Interrupt status Interrupt enable Error Int status Error Int enable Status Control Address Buf descr table Frame num 7 0 Frame num 10 8 Ox0A Token SOF Thres 15 8 0x0C SOF Threshold 7 0 Endpoin Endpoin Endpoin Endpoin Endpoin Endpoin Endpoin Endpoin Endpoin Endpoin Endpoin Endpoin Endpoin Endpoin DST_USBO_BAS DST_USBO_BAS Ej Ej E D D Dd Ed Dd Dub Dd D D pd pd Dd Dd bGRO RR RR RO B o R o RR o LEE EL EE E E E E OxD000 DST I2CO BAS Ox1F kK Ok Ok k ok Ok DST_I2C0_BAS DST_I2C0_BASI DST I2CO BAS DST I2CO BAS DST I2CO BAS DST I2CO BAS RR AM Ed Ed Ed Dd Dd Dd Du Endpoin Endpoin LOK A E T E M E EL NE NE ME Ke X X X X
65. EAKPT1 C1 BREAKPT1 Select BREAKPOINT 1 scan chain BREAKPT2 D1 BREAKPT2 Select BREAKPOINT 2 scan chain BREAKPT3 E1 BREAKPT3 Select BREAKPOINT 3 scan chain BREAKPT4 F1 BREAKPT4 Select BREAKPOINT 4 scan chain MEM_WRIT 05 DATA Initiates a MEMORY WRITE cycle E MEM_READ 15 DATA Initiates a MEMORY READ cycle IO WRITE 25 DATA Execute an IO WRITE cycle IO READ 35 DATA Execute an IO READ Cycle APPLY 45 DATA Apply the scanned in vector for 1 bus cycle APPLY CP 55 DATA Apply the scanned in vector for 1 bus cycle only to the CPU Hold U WRN WRLN WRHN and RDN inactive to external logic APPLY EXT 65 DATA Apply the scanned in vector for 1 bus cycle only to external logic The CPU remains inactive RESET 75 DATA Assert reset to the CPU and external peripherals BYPASS FF BYPASS This instruction required by IEEE 1149 1 The BYPASS opcode is automatically loaded into the INSTRUCTION register when RESET is asserted 44 FS2 Target Connection Figure 4 1 shows a typical connection from the CPU core to the First Silicon Solutions Debugger Figure 4 1 Typical FS2 Target Connection DSTni EX FS2 Debugger 45 Excerpt From First Silicon Solutions VSA186 Debugger User s Guide The standard target connection is the 20 position flat ribbon cable with the AMP System 50 connector This mates to AMP connector 104549 2 vertical surface mount 104069 1 right angle through hole or 104068 1 vertical through hole mounted on the
66. EN DST REG CANT TXO CTRL f Ke kK kK ok ok Ck Ck Ck KK X X KK ko KK oxk ok k k ox ox DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI Xj Lr 9 Lr Dr Y Dn E L LLL LLL M DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BAS DST CANO BAS DST CANO BAS Lj t Ln E E RR Ay DH DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BAS DU UE Ce Ta RERBA DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BAS DST CANO BAS DST CANO BAS Lj p D D p El LE LL L DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI DST CANO BASI Lj Dj Lg D c E DST CANO BASI DST_CAN1_BASI DST CANT BASI DST_CAN1_BASI DST_CAN1_BASI DST_CAN1_BASI DST_CAN1_BASI DST_CAN1_BASI dt m Xj rj Ln Dr Dr Ln Dn Du teehee tebe eet ko o xk ox ko oxk ox DST_CAN1_BASI Hi ID bit Lo ID bits Hi Data bits XL EA EA Lo Data bits Length JE Control Rx Tx err count Err Status count Msg Level Thresh Interrupt Flags Interrupt enable Operating mode LEEN PE Filter enables Acceptance mask 0 F k A EAE A
67. G ETHO RDP DST ETHO BASE 0x0010 Register Data Port define DST REG ETHO RAP DST ETHO BASE 0x0012 Register Access Port define DST REG ETHO RST DST ETHO BASE 0x0014 Reset Port define DST REG ETHO MII DST ETHO BASE 0x0018 MII Port define DST REG ETH1 RDP DST ETH1 BASE 0x0010 Register Data Port define DST REG ETH1 RAP DST ETH1 BASE 0x0012 Register Access Port define DST REG ETH1 RST DST_ETH1_BASE 0x0014 Reset Port define DST REG ETH1 MII DST ETH1 BASE 0x0018 MII Port kk xk CAN 0 Registers kk 7 Ey define DST_CANO_BASE 0xA800 define DST CAN1 BASE 0xA900 Transmit message 0 define DST_REG_CANO_TX0_1D28_13 DST_CANO_BASE 0x00 Hi ID bits define DST_REG_CANO_TX0_1D12_00 DST_CANO_BASE 0x02 Lo ID bits define DST_REG_CANO_TX0_D63_48 DST_CANO_BASE 0x04 Hi Data bits define DST_REG_CANO_TX0_D47_32 DST_CANO_BASE 0x06 XI define DST REG CANO TXO0 D31 16 DST CANO BASE 0x08 5 XI define DST_REG_CANO_TX0_D15_00 DST_CANO_BASE 0x0A Lo Data bits define DST_REG_CANO_TXO_LEN DST_CANO_BASE 0x0C Length define DST_REG_CANO_TXO_CTRL DST CANO BASE 0x0E Control Transmit message 1 define DST REG CANO TX1 ID28 13 DST CANO BASE 0x10 Hi ID bits define DST
68. INSI Interrupt request define DST REQST DMA3 define DST REQST DMA2 define DST REQST SP3 define DST REQST INT5 define DST REQST SPO define DST REQST SP1 define DST REQST SP2 define DST REQST USB define DST REQST INT3 define DST REQST SPI define DST REQST I2C define DST REQST INT1 define DST REQST MAC1 define DST REQST MACO define DST REQST DMA1 define DST_REQST_DMAO define DST REQST TMR 0x2000 0x1000 0x0800 0x0400 0x0200 0x0100 0x0080 0x0080 0x0040 0x0040 0x0020 0x0010 0x0008 0x0004 0x0001 0xC000 Enables Timer 0x4000 Disables Timer Enable interrupts 0x1000 0 maxcount A in use else maxcnt B 0x0020 If 1 maxcount has been reached 0x0010 Use TMRINO to reset count 0x0008 Use Timer 2 as prescale 0x0004 Use TMRINO as external clock source 0x0002 Alternate between Maxcount A and B 0x0001 Run in continuous mode 0xC000 Enables Timer 0x4000 Disables Timer Enable interrupts 0x1000 0 maxcnt A in use else maxcnt B 0x0020 Tf 1 maxcnt has been reached 0x0010 Use TMRINO to reset count 0x0008 Use Timer 2 as prescale 0x0004 Use TMRINO as external clock source 0x0002 Alternate between Maxcnt A and B 0x0001 Run in continuous mode 0xC000 Enables Timer 0x4000 Disables Timer Enable interrupts 0x0020 If 1 maxcount has been reach
69. IOZ Tri state output leakage current Vo 3 3V Ill 10na 1ua Ill IOZ Tri state output leakage current 3 Vo 0V Ill 10na 1ua 111 RPU Pull up Resistor 56K 77K 122K Q RPD Pull down Resistor 51K 69K 127K Q Ball Input Capacitance 111 4 Ill pf VOL Output low voltage IOL max Ill Ill 0 4 V VOH Output high voltage IOH max 24 Ill Ill V IOL Low level output current VOL 0 4V 2mA 2 2 3 5 4 3 mA IOL Low level output current VOL 0 4V 4mA 4 4 7 1 8 5 mA IOL Low level output current VOL 0 4V 8mA 8 8 14 1 17 0 mA IOL Low level output current VOL 0 4V 12mA 13 2 21 2 25 5 mA IOL Low level output current VOL 0 4V 16mA 17 6 28 2 34 0 mA IOL Low level output current VOL 0 4V 24mA 24 2 38 8 46 7 mA IOH High level output current VOH 2 4V 2mA 3 2 6 4 10 0 mA IOH High level output current VOH 2 4V 4mA 6 4 12 8 20 0 mA IOH High level output current VOH 2 4V 8mA 12 8 25 7 40 0 mA IOH High level output current VOH 2 4V 12mA 19 1 38 5 60 0 mA IOH High level output current VOH 2 4V 16mA 28 7 57 7 90 0 mA IOH High level output current VOH 2 4V 24mA 38 2 76 9 119 9 mA Input Rise and fall time 10 lt gt 90 Ill Ill 8 ns CPUCLK 0 wait internal RAM 1 Ill 100 Mhz CPUCLK 1 wait internal RAM 1 Ill 115 Mhz VDD1 8 Current 1Mhz Ill 15 20 mA VDD1 8 Current 127Mhz 111 150 200 mA VDD3 3 Current Ill 150 200 mA PLL Jitter p p over 200 cycles Ill 48 200 ps PLL Lock Time 20 Ill 150 us Typical values are at 25 C and are for design info
70. N TXSTRT PAUSE ENA XON CSR3 0x0000 0x00E0 0x00C0 0x00A0 0x0080 0x0060 0x0040 0x0020 0x0001 LJ K LA O CS CS CS 15 24 LES 30 31 46 CS 76 78 88 89 CSR112 114 0x8000 0x2000 0x1000 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 0x1000 0x0400 0x0200 0x0100 0x0010 EL Serial peripheral interface slave select HIFT HIFT HIFT HIFT HIFT HIFT HIFT HIFT ELECT Select 8 bit transfer Select 7 bit transfer Select 6 bit transfer Select 5 bit transfer Select 4 bit transfer Select 3 bit transfer Select 2 bit transfer Select 1 bit transfer Drive SLVSEL pin active ALA A AA A ROR o E Ke kK X ok ok ok k k k ox ox CSRO Status CSR1 initialization addr low word CSR2 initialization addr high word CSR3 interrupt mask CSR4 features control MAC address bits 15 0 MAC address bits 31 16 MAC address bits 47 32 CSR15 Mode control CSR24 RX ring base addr low word RX ring base addr high word CSR30 TX ring base addr low word CSR31 TX ring base addr high word CSR46 Poll time counter Poll interval CSR76 Receive ring length CSR78 Transmit length CSR88 Chip ID low word CSR89 Chip ID high word Missed frame count CSR114 Received collision count Logical or of CERR MISS SQE
71. NT ENB TOK DNE DST USB INT ENB SOF TOK DST USB INT ENB ERROR 0x02 DST USB INT ENB USB RST used in ALCR ECR amp FRR 0x0000 Stopped 0x0001 Synchronize 0x0005 Interframe 0x0006 Bus Idle 0x0007 Start of frame 0x0008 Arbitration 0x0009 7 Control 7 0x000A Data 0x000B CRC 0x000C Acknowledge 0x000D End of frame 0x0010 Error flag 0x0011 Error echo 0x0012 Error Delay 0x0018 Overload flag 0x0019 Overload echo 0x001A Overload delay Ok Ok ek KOK Ok k oxk ox 0x80 0x40 0x20 0x10 0x08 0x04 KO OK de dede ok dn A de de Xk Xk k ox KO Ok wk X X X ok ok k kK ox x Xk Xk k k OK Interrupt Enable I2C Enable Send start condition Send stop condition Interrupt flag Send acknowledge KO OK k X Kk X ok Ck Ck k X X X X KK KK kK ox ox X KO Ok kK X X X ok ck Ck k X X X Xk KK KK kK ox ox X 0x80 px 0x40 PE 0x20 Vea 0x10 0x08 yes 0x04 des 0x02 JA 0x01 0x80 0x40 Ed 0x20 fA 0x10 yat 0x08 Ved 0x04 E Enable 0x01 JE Transaction completed or stalled USB peripheral attached A USB bus idle for 3 ms Current token processing done Start of frame token received Error see ERR STAT register USB reset decoded Enable stall interrupt Enable attach interru
72. Output byte DS SI to port in DX 14 14 4 OUTSW 6F Output word DS SI to port in DX 14 14 4 POP 8F 0 Pop to word of stack into memory 20 5 5 m16 word POP 58 rw Pop to word of stack into word 10 1 5 r16 register POP DS 1F Pop to word of stack into DS 8 4 5 POP ES 07 Pop to word of stack into ES 8 4 5 POP SS 17 Pop to word of stack into SS 8 4 5 POPA 61 Pop DI SI BP BX DX CX and AX 51 9 14 POPF 9D Pop top word of stack into 8 9 6 5 Processor Status Flags register PUSH m16 FF 6 Push memory word onto stack 16 4 2 PUSH r16 50 rw Push register word onto stack 10 1 2 PUSH imm8 6A Push sign extended immediate 10 1 2 byte onto stack PUSH imm16 68 Push immediate word onto stack 10 1 2 PUSH CS OE Push CS onto stack 9 4 2 PUSH SS 16 Push SS onto stack 9 4 2 PUSH DS 1E Push DS onto stack 9 4 2 PUSH ES 06 Push ES onto stack 9 4 2 76 Mnemonic Opcode Description 186 486 DSTni PUSHA 60 Push AX CX DX BX original SP 36 11 14 BP Sl and DI PUSHF 9C Push Processor Status Flags 9 4 3 2 register RCL DO 2 Rotate 9 bits of CF and r m byte left 2 15 3 4 1 r m8 1 once RCL D2 2 Rotate 9 bits of CF and r m byte left 5 n 3 4 4 n r m8 CL CL times 17 n RCL CO 2 ib Rotate 9 bits of CF and r m byte left 5 n 2 4 4 n r m8 imm8 imm8 times 17 n RCL D1 2 Rotate 17 bits of CF and r m word 2 15 3 4 1 r m16 1 left once RCL D3 2 Rot
73. PCB WDTCON Watchdog control define DST WDTCON ENA 0x8000 Enable timer define DST WDTCON WRST 0x4000 Cause a reset upon timeout define DST WDTCON RSTFLAG 0x2000 Set if a WD reset has happened define DST WDTCON NMIFLAG 0x1000 Set if a NMI event occurred define DST WDTCON UNLOCK 0x0800 Unlock reg for further writes define DST WDTCON EXP 10 0x0001 Set WDT timer exponent to 10 define DST WDTCON EXP 20 0x0002 Set WDT timer exponent to 20 define DST WDTCON EXP 21 0x0004 Set WDT timer exponent to 21 define DST WDTCON EXP 22 0x0008 Set WDT timer exponent to 22 define DST WDTCON EXP 23 0x0010 Set WDT timer exponent to 23 define DST WDTCON EXP 24 0x0020 Set WDT timer exponent to 24 define DST WDTCON EXP 25 0x0040 Set WDT timer exponent to 25 define DST WDTCON EXP 26 0x0080 Set WDT timer exponent to 26 define DST WDTCON EXP 27 0x0100 Set WDT timer exponent to 27 define DST WDTCON EXP 28 0x0200 Set WDT timer exponent to 28 define DST WDTCON EXP 29 0x0400 Set WDT timer exponent to 29 define DST WDTCON RESET 1 OxAAAA First of 2 reset steps define DST WDTCON RESET 2 0x5555 Second of 2 reset steps define DST_WDTCON_OPEN_1 0x3333 First of 2 open for write steps define DST_WDTCON_OPEN_2 OxCCCC Second of 2 open for write steps 92 PCB TOCON Timer 0 Control DST 1 DST 1 DST 1 DST 1 DST 1 DST 1 DST 1 DST A DST 4
74. REG CANO TX1 ID12 00 DST CANO BASE 0x12 Lo ID bits define DST REG CANO TX1 D63 48 DST CANO BASE 0x14 Hi Data bits define DST REG CANO TX1 DAT 32 DST CANO BASE 0x16 P XL define DST_REG_CANO_TX1_D31_16 DST_CANO_BASE 0x18 LR 9 ER define DST_REG_CANO_TX1_D15_00 DST CANO BASE 0x1A Lo Data bits define DST REG CANO TX1 LEN DST CANO BASE 0x1C Length define DST REG CANO TX1 CTRL DST CANO BASE 0x1E Control Transmit message 2 define DST REG CANO TX2 ID28 13 DST CANO BASE 0x20 Hi ID bits define DST REG CANO TX2 ID12 00 DST CANO BASE 0x22 Lo ID bits define DST REG CANO TX2 D63 48 DST CANO BASE 0x24 Hi Data bits define DST_REG_CANO_TX2_D47_32 DST_CANO_BASE 0x26 E Ef define DST_REG_CANO_TX2_D31_16 DST_CANO_BASE 0x28 les XI define DST_REG_CANO_TX2_D15_00 DST_CANO_BASE 0x2A Lo Data bits define DST_REG_CANO_TX2_LEN DST_CANO_BASE 0x2C Length define DST_REG_CANO_TX2_CTRL DST_CANO_BASE 0x2E Control 88 Receive define DST_REG_CANO_RX_ID28_13 define DST_REG_CANO_RX_ID12_00 define DST_REG_CANO_RX_D63_48 define DST_REG_CANO_RX_D47_32 define DST_REG_CANO_RX_D31_16 define DST_REG_CANO_RX_D15_00 define DST_REG_CANO_RX_LEN define DST_REG_CANO_RX_FLAGS Status IRQ registers define DST_REG_CANO_ERR_CNT define DST REG CANO ERR STAT CNT define DST REG CANO MSG LEVEL define DST REG CANO IRQ FLAGS
75. RV DST_REG_PCB define DST EG_PRIMSK DST EG_PCB define DST EG_IMASK DST EG_PCB define DST EG_POLLST DST EG_PCB define DST EG POLL DST EG PCB define DST REG EOI DST REG PCB CAN 1 amp I6 control DMA 3 interrupt control DMA 2 interrupt control SP3 interrupt control Serial Port 0 int ctrl Serial Port 1 int ctrl Serial Port 2 int ctrl INT3 interrupt control USB interrupt control SPI interrupt control EI I2C interrupt control INT1 interrupt control 0x003A MAC1 interrupt control S MACO interrupt control DMA 1 interrupt control DMA 0 interrupt control Timer Counter Unit t Interrupt Status Interrupt Request In Service Priority mask f Interrupt mask kE Interrupt poll status Interrupt poll k End Of Interrupt 0x0034 0x0032 0x0030 0x002E T T ict AAA AA AAA A ese AA i a S AA AAA A AA AA A AA A A ia a ad A EEE EEE Ree Robo o C x e e Ww 00 DMA 0 control registers define DST_REG_DOCON DST_REG_PCB 0x00CA Control define DST REG DOTC DST REG PCB 0x00C8 Terminal Count define DST REG DODSTH DST REG PCB 0x00C6 Destination hi byte define DST REG DODSTL DST REG PCB 0x00C4 Destination lo byte define
76. SR Interrupts from the same source are disabled so long as the corresponding bit in the interrupt in service register is set Theory of Operation Interrupt Vector Table Table 2 1 provides information about the reserved interrupts Table 2 1 Interrupt Vectors Interrupt Name Vector Type Vector Address Default Related Priority Instructions Divide Error Exception 0 00h 1 DIV DIV See Note 1 Single Step Interrupt 1 04h 1A All See Note 2 Non Maskable NMI 2 08h 1 INT Breakpoint Interrupt 3 OCh 1 INT See Note 1 INTO Detected Overflow Exception 4 10h 1 INTO Array Bounds Exception 5 14h 1 BOUND See Note 1 Unused Opcode Exception 6 18h 1 Undefined See Note 1 Opcodes ESC Opcode Exception 7 1Ch 1 ESC See Note 1 Time 0 Interrupt 8 20h 2A See Note 3 Reserved 9 24h DMA 0 Interrupt 10 28h 4 DMA 1 Interrupt 11 2Ch 5 Ethernet MAC 0 INTO Interrupt 12 30h 6 INT1 or Ethernet MAC 1 Interrupt 13 34h 7 INT2 or SPI C Interrupt 14 38h 8 INT3 or USB Interrupt 15 3Ch 9 UART 2 Interrupt 16 40h 10 UART 1 Interrupt 17 44h 15 Timer 1 Interrupt 18 48h 2B See Note 3 Timer 2 Interrupt 19 4Ch 2C See Note 3 UART 0 Interrupt 20 50h 15 INT5 or UART 3 Interrupt 21 54h 11 DMA 2 Interrupt 22 58h 12 DMA 3 Interrupt 23 5Ch 13 CAN Interrupts 24 60h 14 Default priorities for interrupt sources are used only if you do not program each
77. Suspend instruction execution 2 4 1 IDIV F6 7 AL AX r m byte AH remainder 44 52 19 20 15 18 I r m8 50 58 IDIV F7 7 AX DX AX r m word 53 61 27 28 23 26 l r m16 DX remainder 59 67 IMUL F6 5 AX r m byte AL 25 28 5 5 12 15 r m8 31 34 IMUL F7 15 DX AX r m word AX 34 37 5 6 20 23 r m16 40 43 IMUL 6B r ib word register r m word sign 22 25 5 5 20 23 r16 r m16 imm extended byte integer 8 IMUL 69 r iw word register r m word sign 29 32 5 6 20 23 r16 r m16 imm extended word integer 16 IN EA ib Input byte from immediate port to 10 17 6 AL imm8 AL IN E5 ib Input word from immediate port to 10 17 6 AX imm8 AX IN EC Input byte from port in DX to AL 8 17 4 AL DX IN ED Input word from port in DX to AX 8 17 4 AX DX INC FE 0 Increment r m byte by 1 3 15 1 3 1 4 r m8 INC FF 0 Increment r m word by 1 3 15 1 3 1 4 r m16 INC 40 rw Increment word register by 1 3 1 1 r16 INS 6C Input byte from port in DX to 14 15 3 m8 DX ES DI INS 6D Input word from port in DX to 14 15 3 m16 DX ES DI INSB 6C Input byte from port in DX to 14 15 3 ES DI 73 Mnemonic Opcode Description 186 486 DSTni INSW 6D Input word from port in DX to 14 15 3 ES DI INT 3 CC Generate interrupt 3 trap to 45 26 2 debugger INT CD ib Generate type of interrupt specified 47 30 2
78. T SPI I2C External INT id id P293 pin Tl pin I1 Ethernet MAC1 Ethernet MACO DMA channel 1 DMA channel 0 Timer Ox7FFD 0x0007 0x0006 0x0005 0x0004 0x0003 0x0002 0x0001 0x0000 0x8000 0x0004 0x0002 0x0001 timer 0x0008 0x0007 0x0006 0x0005 0x0004 0x0003 0x0002 0x0001 0x0000 0x0010 0x0008 0x0007 0x0006 0x0005 0x0004 0x0003 0x0002 0x0001 0x0000 0x8000 0x8000 94 0 y 1 or 2 Mask all interrupt sources Enable Enable Enable Enable Enable Enable Enable Enable Halts Timer Timer Timer serial dm POLL POLLST Interrupt Poll and Poll Status Mask t Set in Set in Set in Set in Set in Set in Set in Set in Select Mask t Set in Set in Set in Set in Set in Set in Set in Set in all priority levels 0 7 levels 0 through levels 0 through levels 0 through levels 0 through levels 0 through levels 0 through level 0 DMA activi 6 PNWAU S El Xy El A x ty when set 2 is requesting an interrupt 1 is requesting an interrupt 0 is requesting an interrupt a Spi his in terrup terrup terrup terrup terrup terrup terrup terrup Ct ch cock GT CEE ET cts level terrupt terrup terrup terrup terrup terrup te
79. TS 2 u32CpuSpeed clock speed of the CPU in units of Hertz ul6DeviceNs device access time in units of nanoseconds a ETURNS U16 The number of wait states required for the correct operation of the memory device IS ESCRIPTION This function computes the number of wait states required for a memory device given the clock speed of the CPU and the read access time of the device The returned value will be in the range of 0 to 15 AA Ok FF F FF HF HF o6 HF ox KEKE KKK KKK KEKE KKK KKK KKK KEKE KEKE KEK KK KKK KEKE KKK KKK KKK KKK KEKE KK ck ck ck ck ck ck ck ko ko ko ko ko m U16 ul6CalcWaitStates U32 u32CpuSpeed U16 ul6DeviceNs float fWaits fWaits float ul6DeviceNs 1000000000 0 float u32CpuSpeed return U16 ceil fWaits s KKK KKK KEK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KEK ckckokckckckck ckckokckckckck kckckck ck kok FUNCTION ul6WaitStateBits Ul6 ul6WaitStates ARGUMENTS 1 ul6WaitStates a ETURNS U16 The bit pattern for the selected number of wait states IS ESCRIPTION This function given the desired number of wait states will perform a lookup in the wait state bit table and return the wait state bit pattern corresponding to the value Xo X OR 0k FF F HF HF HF 2 KR KEK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KEK f U16 ul6WaitStateBits U16 ul6WaitStates U16 ul6RetVal if ul6WaitStates 15 ul6RetVal
80. X1 CTRL Transmit message 2 define DST REG CAN1 TX2 ID28 13 define DST REG CAN1 TX2 ID12 00 define DST REG CANT TX2 D63 48 define DST REG CANT TX2 DAT 32 define DST REG CAN1 TX2 D31 16 define DST REG CANT TX2 D15 00 define DST REG CAN1 TX2 LEN define DST REG CAN1 TX2 CTRL Receive define DST REG CAN1 RX ID28 13 define DST REG CANT RX ID12 00 define DST REG CAN1 RX D63 48 define DST REG CAN1 RX D47 32 define DST REG CAN1 RX D31 16 define DST REG CAN1 RX D15 00 define DST REG CAN1 RX LEN define DST REG CAN1 RX FLAGS Status IRQ registers define DST REG CAN1 TX ERR CNT define DST REG CAN1 ERR STAT CNT define DST REG CANT MSG LEVEL define DST REG CAN1 IRQ FLAGS define DST REG CAN1 IRQ ENABLE CAN Configuration define DST REG CAN1 MODE define DST REG CAN1 BITRATE define DST REG CAN1 TIMING Acceptance mask and code registers define DST REG CAN1 FILTER ENA define DST REG CAN1 AMRO ID28 13 define DST REG CAN1 AMRO ID12 00 define DST REG CANT AMRO D63 48 define DST REG CANT ACRO ID28 13 define DST REG CANT ACRO ID12 00 define DST REG CANT ACRO D63 48 define DST REG CANT AMR1 ID28 13 define DST REG CAN1 AMR1 ID12 00 define DST REG CANT AMR1 D63 48 define DST REG CANT ACR1 ID28 13 define DST REG CANT ACR1 ID12 00 define DST REG CANT ACR1 D63 48 define DST REG CAN1 AMR2 ID28 13 define DST REG CAN1 AMR2 ID12 00 define DST REG CAN1 AMR2 D63 48 define DST REG CAN1 ACR2 ID28 13 define DST REG CAN1 ACR2 ID12 00
81. ate 17 bits of CF and r m word 5 n 3 4 4 n r m16 CL left CL times 17 n RCL C1 2 ib Rotate 17 bits of CF and r m word 5 n 2 4 4 n r m16 imm8 left imm8 times 17 n RCR DO 3 Rotate 9 bits of CF and r m byte 2 15 3 4 1 r m8 1 right once RCR D2 3 Rotate 9 bits of CF and r m byte 5 n 3 4 4 n r m8 CL right CL times 17 n RCR CO 3 ib Rotate 9 bits of CF and r m byte 5 n 2 4 4 n r m8 imm8 right imm8 times 17 n RCR D1 3 Rotate 17 bits of CF and r m word 2 15 3 4 1 r m16 1 right once RCR D3 3 Rotate 17 bits of CF and r m word 5 n 3 4 4 n r m16 CL right CL times 17 n RCR C1 3 ib Rotate 17 bits of CF and r m word 5 n 2 4 4 n r m16 imm8 right imm8 times 17 n REP INS F3 6C Input CX bytes from port in DX to 8 8n 19 11D 4 m8 DX ES DI D 3 n REP INS F3 6D Input CX words from port in DX to 8 8n 19 11D 4 m16 DX ES DI D 3 n REP LODS F3 AC Load CX bytes from segment SI in 6 11n 5 4 m8 AL 7 4D D 3 n REP LODS F3 AD Load CX words from segment SI 6 11n 5 4 m16 in AX 7 4D D 3 n REP MOVS F3 A4 Copy CX bytes from segment SI 8 8n 5 4 m8 m8 in ES DI 12 3D D 3 n REP MOVS F3 A5 Copy CX words from segment SI 8 8n 5 4 m16 m16 in ES DI 12 3D D 3 n REP OUTS F3 6E Output CX bytes from DS SI to 8 8n 20 8D 4 DX m8 port in DX D 3 n REP OUTS F3 6F Output CX words from DS SI to 8 8n 20 8D 4 DX m16 port in DX D 3 n REP STOS F3 AA Fill CX bytes at ES DI with AL 6 9n 5 4 ms 7 4D D 3 n REP STOS F3 AB Fill CX words at ES DI wit
82. bit positions multiplied by 4 to generate the index into the interrupt vector table Interrupt Servicing A valid interrupt transfers execution to a new program location based on the vector in the interrupt vector table The next instruction address CS IP and the microprocessor status flags are pushed onto the stack The interrupt enable flag IF clears after the microprocessor status flags are pushed on the stack disabling maskable interrupts during the interrupt service routine ISR The segment offset values from the interrupt vector table are loaded into the code segment CS and the instruction pointer IP and execution of the ISR begins Returning from an Interrupt The interrupt return IRET instruction pushes the microprocessor status flags and the return address off the stack Program execution resumes at the point where the interrupt occurred The interrupt enable flag IF is restored by the IRET instruction along with the remaining microprocessor status flags If the IF flag was set before the interrupt was serviced interrupts are re enabled when the IRET is executed If there are valid interrupts pending when the IRET is executed the instruction at the return address is not executed Instead the new interrupt is serviced immediately If an ISR intends to modify the value of any of the saved flags permanently it must modify the copy of the microprocessor status flags register that was pushed onto the stack 10 In
83. channel 0 define DST IVECT TMRO 8 Timer 0 Interrupt vectors software define DST IVECT DIVIDE 0 Divide error define DST IVECT SSTEP 1 Single Step define DST IVECT NMI 2 Non Maskable Interrupt define DST IVECT BREAKPT 3 Software breakpoint define DST IVECT INTO 4 INTO instruction OF flag set define DST IVECT BOUNDS 5 Array bounds exception define DST_IVECT_INV_OP 6 Unused opcode define DST_IVECT_ESC_OP 7 Escape ESC trap PCB DMA DMA control define DST_DMA_DST_MEM 0x8000 Destination is in memory space define DST_DMA_DST_IO 0x0000 Destination is in I O space define DST_DMA_DST_DEC 0x4000 Decrement dst pointer define DST_DMA_DST_INC 0x2000 Increment dst pointer define DST_DMA_SRC_MEM 0x1000 Source is in memory space define DST_DMA_SRC_IO 0x0000 Source is in I O space define DST_DMA_SRC_DEC 0x0800 Decrement src pointer define DST_DMA_SRC_INC 0x0400 Increment src pointer define DST_DMA_TC 0x0200 Stop DMA when count reaches 0 define DST_DMA_INT_ENABLE 0x0100 Generate interrupt on termination define DST_DMA_SYNC_NO 0x0000 No synchronization define DST_DMA_SYNC_DST 0x0080 Destination sync define DST_DMA_SYNC_SRC 0x0040 Source sync define DST_DMA_PRI_HI 0x0020 Select high priority define DST_DMA_PRI_LO 0x0000 Sele
84. cribes DSTni s packaging and electrical characteristics Section 6 Applications Describes DSTni s packaging and electrical characteristics Section 6 Instruction Clocks Describes the DSTni instruction clocks Section 6 DSTni Sample Code Section 6 Baud Rate Calculations Provides baud rate calculation tables 2 Interrupt Controller This chapter describes the DSTni interrupt controller Topics in this chapter include Overview on page 6 Z Theory of Operation on page 7 Interrupt Controller Register Summary on page 14 Z Register Definitions on page 15 Overview DSTni can receive interrupt requests from a variety of internal and external sources DSTni s internal interrupt controller arranges these requests by priority and presents them one at a time to the microprocessor There are 15 interrupt sources available on DSTni The timers use three The UARTS use four The DMA channels use four The peripherals use four INTO connects to Ethernet MAC 0 INT1 is Ethernet MAC 1 ORed with external 1 INT2 connects to both the SPI controller and the I C controller INT3 connects to both the USB controller and an external input pin INT6 is both CAN channels Interrupts are automatically disabled when an interrupt is taken Interrupt service routines ISRs can re enable interrupts by setting the IF flag This allows interrupts of equal or greater priority to interrupt the currently executing I
85. ct low priority define DST_DMA_TDRQ 0x0010 Timer 2 provides request define DST_DMA_START 0x0006 Start DMA operation define DST_DMA_STOP 0x0004 Stop DMA operation define DST_DMA_XFER_WORD 0x0001 Select word transfers define DST_DMA_XFER_BYTE 0x0000 Select byte transfers 95 PCB S define define define define define define define define define define define define define define define define define define define define define define define PCB S define define define define define define define define define define PCB S define define define define define define define define define define PCB S define define define define define define define define define define PCB S define define define define define 96 PxCT Serial port control DST_SPXCT_DMA_MODE_0 0x0000 DMA Mode 0 DST SPXCT DMA MODE 1 0x2000 DMA Mode 1 DST SPXCT DMA MODE 2 0x4000 DMA Mode 2 No DMA mode 3 DST SPXCT DMA MODE 4 0x8000 DMA Mode 4 DST SPXCT DMA MODE 5 OxA000 DMA Mode 5 DST_SPXCT_DMA_MODE_6 0xC000 DMA Mode 6 DST SPXCT DMA MODE 7 OxE000 DMA Mode 7 DST_SPXCT_RSIE 0x1000 Receive Status Interrupt Enable DST_SPXCT_BRK 0x0800 Generate Break DST_SPXCT_TB
86. cteristics Table 5 6 100Base FX Transceiver Characteristics Parameter Sym Min Typ Max Unit Test Conditions Transmitter Peak Differential Output Voltage VP 0 6 Ill 1 5 V Ill Signal Rise Fall Time 2pF load TRF Ill MH IES ns 10 lt gt 90 Jitter measured differentially Ill Il Ill 1 3 ns Ill Receiver Peak Differential Input Voltage VIP 0 55 Ill 1 5 V Ill Common Mode Input Range VCMIR Ill Il WDD 0 7 V Ill 51 100Base T Transceiver Characteristics Table 5 7 100Base T Transceiver Characteristics Parameter Sym Min Typ Max Unit Test Conditions Transmitter Peak Differential Output VOP 2 2 2 5 2 8 V With Transformer line replaced Voltage by 1000 resistor Transition Timing Jitter Ill 0 2 11 ns After line model specified by added by the MAU and IEEE 802 3 for 1OBASE T MAU PLS sections Receiver Receive Input Voltage ZIN Ill 3 6 Ill kQ Il Differential Squelch VDS 300 420 585 mV HI Threshold 100Base T Link Integrity Timing Characteristics Table 5 8 100Base T Link Integrity Timing Characteristics Parameter Sym Min Typ Max Units Test Conditions Time Link Loss Receive TLL 50 Ill 150 ms Ill Link Pulse TLP 2 Ill 7 Link Pulses Ill Link Min Receive Timer TLR Min 2 Ill 7 ms Ill Link Max Receive Timer TLR Max 50 Ill 150 ms Ill Link Transmit Period TLT 8 Ill 24 ms Ill Link Pulse Width TLPW 60 Ill 150 ms Ill
87. define DST REG CANO IRQ ENABLE CAN Configuration define DST REG CANO MODE define DST REG CANO BITRATE define DST REG CANO TIMING Acceptance Mask and Code registers define DST REG CANO FILTER ENA define DST REG CANO AMRO ID28 13 define DST REG CANO AMRO ID12 00 define DST REG CANO AMRO D63 48 define DST REG CANO ACRO ID28 13 define DST REG CANO ACRO ID12 00 define DST REG CANO ACRO D63 48 define DST REG CANO AMR1 ID28 13 define DST REG CANO AMR1 ID12 00 define DST REG CANO AMR1 D63 48 define DST REG CANO ACR1 ID28 13 define DST REG CANO ACR 1 ID12 00 define DST REG CANO ACR1 D63 48 define DST REG CANO AMR2 ID28 13 define DST REG CANO AMR2 ID12 00 define DST REG CANO AMR2 D63 48 define DST REG CANO ACR2 ID28 13 define DST REG CANO ACR2 ID12 00 define DST REG CANO ACR2 D63 48 Analysis registers define DST REG CANO ALCR define DST REG CANO ECR define DST REG CANO FRR x y Trans define define define define define define define define CAN 1 Registers Ke X k Ck X ck Ck o KK X X KK KK Xk Xk KK k KK mit message 0 DST REG CANT TXO ID28 13 DST REG CANT TXO ID12 00 DST REG CANT TXO D63 48 DST REG CANT TXO DA7 32 DST REG CANT TXO D31 16 DST REG CANT TXO D15 00 DST REG CANT TX0 L
88. e T link Tx Rx activity 6 Blinking Power Indication 1 Blinks when transmitting or receiving packets with full duplex LAN connection 2 Solid when the link is established with a 100Base T connection 3 Blinks to indicate error detection A pause equal to two blinking intervals is required between the x times If the link is good the LED color for the pause interval is yellow or green depending on the 10 or 100M link If the link is not good the LED is OFF during the pause interval Blinks 1 time hardware error Blinks 2 times duplicated IP address on the network Blinks 3 times faulty network connection Blinks 4 times no DHCP response received 4 Blinks when transmitting or receiving packets with half duplex LAN connection 5 Solid when the link is established with a 10Base T connection 6 Blinks when powered on When a 10Base T link is detected the LED changes to solid green 70 7 Instruction Clocks Mnemonic Opcode Description 186 486 DSTni AAA 37 ASCII adjust AL after addition 8 3 4 AAD D5 OA ASCII adjust AX before division 15 14 5 AAM D4 0A ASCII adjust AL after multiplication 19 15 5 AAS 3F ASCII adjust AL after subtraction 7 3 4 ADC 14 ib Add immediate byte to AL with 3 1 1 AL imm8 carry ADC 15 iw Add immediate word to AX with 4 1 1 AX imm16 carry ADC 80 2 ib Add immediate byte to r m byte 4 16 1 3 1 4 r m8 imm8 with carry ADC 81
89. e actually used see Table 2 1 on page 7 The maskable interrupts are enabled and disabled by the interrupt enable flag IF in the microprocessor status flags however the INT command can execute any interrupt regardless of the setting of IF Interrupt types 00h through 07h and all software interrupts the INT instruction are nonmaskable The nonmaskable interrupts are not affected by the setting of the IF flag DSTni provide two ways to mask and unmask maskable interrupt sources Each interrupt source has an interrupt control register that contains a mask bit specific to that interrupt n addition the interrupt mask register is provided as a single source to access all of the mask bits If the interrupt mask register is written while interrupts are enabled an interrupt can occur while the register is in an undefined state This can cause interrupts to be accepted even though they were masked before and after the write to the interrupt mask register As a result the interrupt mask register should only be written when interrupts are disabled Mask bits in the individual interrupt control registers can be written while interrupts are enabled without erroneous interrupt operation Interrupt Enable Flag The interrupt enable flag IF is part of the microprocessor status flags fIF lt 1 maskable interrupts are enabled and can cause microprocessor interrupts Individual maskable interrupts can still be disabled by means of the
90. e interrupts are set to a programmable priority of seven on reset the overall priority of the interrupts determines the priority in which each interrupt is granted by the interrupt controller until programmable priorities are changed by reconfiguring the control registers The default priority levels shown in Table 2 1 on page 7 are not the same as the programmable priority level associated with each maskable hardware interrupt Each of the maskable hardware interrupts has a programmable priority from 0 to 7 with 0 being the highest priority see Table 2 1 on page 7 For example if the INT4 INTO interrupts are all changed to programmable priority 6 and no other programmable priorities are changed from the reset value of seven the INT4 INTO interrupts take precedence over all other maskable interrupts Within INT4 INTO the hierarchy is as follows INTO gt INT1 gt INT2 gt INT3 gt INT4 Software Exceptions Traps and NMI The following predefined interrupts cannot be masked by programming Divide Error Exception Interrupt Type 00h Generated when a DIV or IDIV instruction quotient cannot be expressed in the number of destination bits Trace Interrupt Interrupt Type 01h If the trace flag TF in the microprocessor status flags register is set the trace interrupt is generated after most instructions This interrupt lets program execute in single step mode The interrupt is not generated after prefix instructions like REP instruct
91. ed 0x0001 Run in continuous mode 0x4000 16 CAN1 and CANO 0x2000 DMA channel 3 0x1000 DMA channel 2 0x0800 15 serial port 3 0x0800 15 Extneral INT5 pin 0x0400 Serial Port 0 0x0200 Serial Port 1 0x0100 Serial Port 2 0x0080 I3 USB 0x0080 I3 External INT 3 pin 0x0040 I2 SPI 0x0040 I2 I2C 0x0020 I1 Ethernet MAC1 0x0020 Il External INTL pin 0x0010 I0 Ethernet MACO 0x0008 DMA channel 1 0x0004 DMA channel 0 0x0001 Timer 0 10r 2 DMA channel 3 DMA channel 2 I5 serial port 3 0x0800 I5 Extneral INT5 pin Serial Port 0 Serial Port 1 Serial Port 2 4 13 USE 13 External INT 3 pin I2 SPI LE LD LAC 7 7 11 External INT1 pin 0x0020 11 Ethernet MAC1 I0 Ethernet MACO DMA channel 1 DMA channel 0 Timer 0 10r 2 93 PCB IMASK Interrupt mask define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define PCB DST_IMASK_DMA3 0x2000 DST_IMASK_DMA2 0x1000 DST_IMASK_SP3 0x080
92. ed in the interrupt status register This bit cannot be written 28 Poll Status Register Note These bits are only valid if IRQ 1 Differences between the Poll Status and Poll registers Reading the Poll register generates a software poll This sets the in service bit for the highest priority pending interrupt Reading the Poll Status register does not set the in service bit for the highest priority pending interrupt Table 2 41 Poll Status Register BIT OFFSET FIELD RW RW RW Table 2 42 Poll Status Register Definitions Bits Field Name Description 15 IRQ Pending Interrupt Determines whether an interrupt request is pending 1 interrupt request is present 0 interrupt request is reset default 14 5 Ill Reserved 4 0 S 4 0 Highest Priority Interrupt Source Contain the encoded vector type of the highest priority interrupt source Poll Register Table 2 43 Poll Register BIT 15 14 13 OFFSET 24h FIELD Ill S4 S3 S2 S1 SO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R RW RW RW RW R R R R R R R RW Ww WwW VW W W W W W W W Table 2 44 Poll Register Definitions Bits Field Name Description 15 IRQ Pending Interrupt Determines whether an interrupt request is pending 1 interrupt request is present 0 interrupt request is reset defaul
93. eed CPU clock speed in units of Hertz ETURNS None ESCRIPTION Initializes Timer and starts it ticking Timer 2 is set to provide a constant 1000 Hz clock to Timer 1 The divisor for Timer 2 is computed based on the given CPU speed A LA A dA RA L KKK KKK KK KK KKK KKK KKK KKK KEK KKK KKK KKK KKK k A ck kck kckokck 104 R void vDstTimerInit U32 u32CpuSpeed U16 far pul6Vect U16 ul6T2Div U16 ul6T1Div Save current interrupt state and block interrupts asm pushf asm cli Clear the tick counter mu32SysTime 0 Make sure timer is stopped by clearing the EN bit outport DST_REG_T2CON 0x4000 outport DST REG T1CON 0x4000 Clear the current counter outport DST REG T2CNT 0 outport DST REG T1CNT 0 Set the comparators We want Timer 2 to feed Timer 1 a 1000 Hz clock We want Timer 1 to generate an interrupt 200 times per second That s 5ms per tick K ul6T2Div U16 u32CpuSpeed 4UL 1 ul6T1Div 1000 U16 TMR_TICKS_PER_SEC Set the timer divisors outport DST REG T2CMPA ul6T2Div outport DST REG T1CMPA ul6T1Div Set up the timer interrupt handler pul6Vect U16 MK FP 0 DST IVECT TMR1 4 pul6Vect 0 FP OFF vTmrInt pul6Vect 1 _CS Start timer 1 with timer 2 as prescale outport DST REG T1CON 0xE009 Start timer 2 in continuous mode outport DST REG T2CON 0xC
94. efine define define define define define define define define define Frame reference field definitions DST CAN FRAMREF STOP DST CAN FRAMREF SYNC DST CAN FRAMREF IFRAMI DST CAN FRAMREF BUSIDL DST CAN FRAMREF SOF DST CAN FRAMREF ARB DST CAN FRAMREF C DST CAN FRAMREF DST CAN FRAMREF DST CAN FRAMRE DST CAN FRAM DST CAN FRAM DST CAN FRAM DST CAN FRAM DST CAN FRAM DST CAN FRAM DST CAN FRAM e IE E tz a QU T ATA R _AC EF EF EF EF EF OV EF OVRI EF OV T T x Er Du T O R R R Al ZU WO pO pO HU JU JU vU JU DU pO VO PO ZU JU EU E D Kk X kK Kk k K OK I2C Register Constants ek k kK k K OK Control Register DST_I2C_CNTR_IEN DST_I2C_CNTR_ENAB DST I2C CNTR STA DST I2C CNTR STP DST I2C CNTR IFLG DST I2C CNTR AAK KO OK kK Ck X ok ck Ck k ko k X ok o k k ko X USB Register Constants KO Ok X X X ok ck Ck k X X ox ok k k ox X USB Interrupt Status DST USB INT STAT STALL DST USB INT STAT ATTACH DST USB INT STAT UME DST USB INT STAT SLEEP DST USB INT STAT DST USB INT STAT DST USB INT STAT DST USB INT STAT xl JUN FA le o wat Ad Q BiU Hu ug nyoo nj wW n Hd USB Interrupt Enable DST USB INT ENB STALL DST USB INT ENB ATTACH DST USB INT ENB RESUME DST USB INT ENB SLEEP DST USB I
95. efine DST REG T2CON DST REG PCB 0x0066 Control El define DST_REG_T2CMPA DST REG PCB 0x0062 Compare A E No Compare B for T2 define DST_REG_T2CNT DST REG PCB 0x0060 Count EE Timer 1 Registers define DST_REG_T1CON DST_REG_PCB 0x005E Control ba define DST_REG_T1CMPB DST_REG_PCB 0x005C Compare B define DST_REG_T1CMPA DST_REG_PCB 0x005A Compare A define DST_REG_T1CNT DST REG PCB 0x0058 Count el Timer 0 Registers define DST REG TOCON DST REG PCB 0x0056 Control n define DST REG TOCMPB DST REG PCB 0x0054 Compare B define DST REG TOCMPA DST REG PCB 0x0052 Compare A define DST REG TOCNT DST REG PCB 0x0050 Count XI Interrupt controller Master Mode registers define DST_REG_CANCON DST_REG_PCB 0x004C define DST EG_DMA3CON DST EG_PCB 0x004A define DST_REG_DMA2CON DST_REG_PCB 0x0048 define DST_REG_SP3CON DST_REG_PCB define DST_REG_SPOCON DST_REG_PCB define DST_REG_SP1CON DST_REG_PCB define DST_REG_SP2CON DST_REG_PCB define DST_REG_I3CON DST_REG_PCB define DST_REG_USBCON DST_REG_PCB define DST_REG_SPICON DST_REG_PCB define DST_REG_I2CCON DST_REG_PCB define DST_REG_I1CON DST_REG_PCB define DST_REG_MAC1CON DST_REG_PCB define DST_REG_MACOCON DST_REG_PCB define DST_REG_DMA1CON DST_REG_PCB define DST_REG_DMAOCON DST_REG_PCB define DST_REG_TCUCON DST_REG_PCB define DST_REG_INTSTS DST_REG_PCB define DST_REG_REQST DST_REG_PCB define DST_REG_INSE
96. egisters Debugging In circuit Emulator Delce Theory of Operation FS2 Target Connection Packaging and Electrical Packaging Recommended Circuit Board Layout Electrical Specifications Power Curve Diagrams Applications Timing Data Reset XTAL Burst Flash 3 wire Burst Flash 2 Wire Page Flash Serial Flash Static RAM SDRAM External DMA ARDY PHY 10 100 Mbit Fibre 100 Mbit LED Functionality T Instruction Clocks 8 DSTni Sample Code 9 Baud Rate Calculations 107 List of Figures List of Tables Figure 3 1 Figure 4 1 Figure 5 1 Figure 5 2 Figure 5 3 PLL and Clock Generator croce inniti crt e clean 37 Typical FS2 Target Connection siisii 45 DS TMP ACK AGG P 47 Recommended Circuit Board Layout sss sese ene 48 DS Tint Current T 53 Figure 5 4 DSTni Power CUIVG iiciccici riec ninio irc cia lidia 54 Fig re 6 1 prc 70 Table 2 1 Interr pt Vectors eee re etre tette da Vo ROGER EE ERE RUE ba Table 2 2 Interrupt Controller Register Summary seem Table 2 3 CAN Interrupt Control Register sese eee eee eee Table 2 4 CAN Interrupt Control Register Definitions se m Table 2 5 DMA 3 Interrupt Control Register sees eee eee Table 2 6 DMA 3 Interrupt Control Register Definitions sss sese eee ee ee eee eee eee Table 2 7 DMA 2 Interrupt Cont
97. egrates an IEEE 1149 1 JTAG Test Access Port TAP or slave controller that is typically connected to a JTAG debugger The CPUDICE architecture has two submodules BRKPTS which contains the logic for four hardware breakpoints TRCEBUFF which contains a trace buffer of 256 instructions Overview Generally users of the CPU will rely on First Silicon Solutions JTAG debugger or Paradigm software to control the CPUDICE core This section is provided for advanced users who want to understand and extend the CPUDICE architecture features The CPUDICE architecture provides the logic to stop single step read write memory interrogate the state of the CPU The CPUDICE controls the CPU via JTAG instructions and the scan chains described below The CPUDICE controls the CPU at the bus cycle level This means it can force feed any byte or word into the CPU and stop the processor between any bus cycle The CPUDICE cannot stop in the middle of instructions only bus cycles any memory or IO operation The CPUDICE can also insert any memory or I O read or write into the stream while the processor is stopped or while it is running The CPUDICE core provides access and control of the CPU via JTAG instructions and scan chains ADDR Scan Chain The ADDR scan chain consists of only the 24 bits of the CPUs address bus The address bus is setup as a separate chain to allow rapid polling of the address bus during real time operation for generating hist
98. ent ways 4 The internal interrupt controller can provide the interrupt type An external interrupt controller can provide the interrupt type The microprocessor requires the interrupt type as an index into the interrupt vector table When the internal interrupt controller is supplying the interrupt type no interrupt acknowledge bus cycles are generated The only external indication that an interrupt is being serviced is the microprocessor reading the interrupt vector table When an external interrupt controller supplies the interrupt type the microprocessor generates two interrupt acknowledge bus cycles The external interrupt controller writes the interrupt type to the AD7 ADO lines during the second bus cycle Interrupt acknowledge bus cycles have the following characteristics 4 The two interrupt acknowledge cycles are locked Two idle states are always inserted between the two interrupt acknowledge cycles Z Wait states are inserted if READY is not returned to the microprocessor Interrupt Controller Reset Conditions On reset the interrupt controller performs the following actions 1 All special fully nested mode SFNM bits are reset implying fully nested mode 2 All priority PR bits in the various control registers are set to 1 This places all sources at the lowest priority level 7 All level triggered mode LTM bits are reset to 0 resulting in edge triggered mode All interrupt in service bits are reset to 0
99. er required for an operand located in memory The number to the left corresponds with a register operand The number to the right corresponds with an operand located in memory The number of clocks depends on the result of the condition tested The number to the left corresponds with a True or Pass result and the number to the right corresponds with a False or Fail result The number of clocks depends on the number of times the instruction is repeated n is the number of repetitions Interrupt handler jump 18 Jump queue init 5 Duration of instruction repeated 82 83 8 DSTni Sample Code 10 Tf de ExStd h This header file defines the values used for all DSTni standard constant EX module code development DEC 2002 WD Author creation Revision 1 00 kk X kK KK KK KK KK X KK k X X X X KK KKK Xk kk kk ox ox ox ox k k ox defined DSTEXSTD H fine DSTEXSTD H include DstExConfig h if defined DST REG PCB define DST REG PCB OxFFOO endif x x k k AI k ces E E oec ose oe k eoe ode E E TR E A ET Gel RAE el ET e RA A Peripheral Control Block register addresses Base address defined in DstLxConfig h de dk de cde ccce RE EE e e Che AR E E E E ce ces cn REE E kkk kk We ces e de RO System control and configuration registers define DST REG RELREG DST REG PCB Ox0OFE define DST REG
100. erial port 3 default 0 do not mask asynchronous serial port 3 10 SPO Asynchronous Serial Port 0 1 mask asynchronous serial port O default 0 do not mask asynchronous serial port 0 SP1 Asynchronous Serial Port 1 1 mask asynchronous serial port 1 default 0 do not mask asynchronous serial port 1 SP2 Asynchronous Serial Port 2 1 mask asynchronous serial port 2 default 0 do not mask asynchronous serial port 2 Logical OR Connected to External Interrupt 3 and USB Controller 1 mask external interrupt 3 and USB controller default 0 do not mask external interrupt 3 and USB controller Logical OR Connected to the SPI Controller and the FC Controller 1 mask the SPI controller and 1 C controller default 0 do not mask the SPI controller and C controller Logical OR Connected to External Interrupt 1 and Ethernet MAC 1 1 mask external interrupt 1 and Ethernet MAC 1 default 0 do not mask external interrupt 1 and Ethernet MAC 1 Ethernet MAC 0 1 mask Ethernet MAC 0 default 0 do not mask Ethernet MAC 0 D1 Mask DMA Channel 1 Interrupt 1 mask DMA channel 1 default 0 do not mask DMA channel 1 DO Mask DMA Channel 0 Interrupt 1 mask DMA channel 0 default 0 do not mask DMA channel 0 Ill TMR Reserved Logical OR of All Timer Interrupt Requests The individual timer interrupt request bits are contain
101. espective interrupt source 111 lowest priority default 000 highest priority 23 Timer Interrupt Control Register Table 2 29 Timer Interrupt Control Register oFFsET 32h FIELD i 5 ry EIE z Dn Dn A RESET olo 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RW R IRWIR RW RW T RW T RW RI RI R TR TRWT RI RI RIR W W W 1 W T W 1 Ww W wi iwiw Table 2 30 Timer Interrupt Control Register Definitions Bits Field Name Description 15 4 W Reserved 3 MSK Mask Interrupt 1 mask respective interrupt request default 0 enable respective interrupts 2 0 PR 2 0 Programmable Priority Level The programmable priority level for the respective interrupt source 111 lowest priority default 000 highest priority Interrupt Status Register Table 2 31 Interrupt Status Register BIT 13 12 11 10 9 OFFSET 30h FIELD Ill e ides G x x x 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 2 32 Interrupt Status Register Definitions Bits Field Name Description 15 DHLT Halt DMA Operations 1 halt all DMA operations 0 do not halt all DMA operations default Automatically set when an NMI occurs and resets when an IRET instruction executes By suspending DMA operations during an NMI the microprocessor can q
102. fine DST CAN FRR FRAM define DST CAN FRR TXBIT define DST CAN FRR RXBIT define DST CAN FRR STUFIND HU MSK d xy 0x0000 0x0004 0x0008 0x000C 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 0x0400 0x0800 0x1000 0x2000 0x4000 0x8000 0x0001 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 0x0400 0x0800 0x1000 0x2000 0x4000 0x8000 0x0001 0x0002 0x0004 0x0000 0x0001 0x0000 0x0002 0x0000 0x0004 0x0008 0x000C 0x0010 0x8000 Ox1F00 0x003F 0x003F 0x0040 0x0080 Ox1F00 0xE000 0x003F 0x0040 0x0080 Ox1F00 0x2000 0x4000 0x8000 0x0001 0x0002 0x0004 Interrupt when at least 1 msg when at least 2 messages when at least 3 messages when at least 4 messages Arbitration lost during tx Overload condition Receiver overrun Bit error during tx or rx Stuffing error during tx or rx Ack error during tx or rx Format error during tx or rx CRC error during tx or rx CAN is in bus off state Message 0 sent Message 1 sent Message 2 sent At least 1 tx buffer empty At least 1 rx message available General enable Arbitration lost during tx
103. g chapters and appendixes Section 1 Introduction Describes the DSTni architecture design benefits theory of operations ball assignments packaging and electrical specifications This chapter includes a DSTni block diagram Section 2 Microprocessor Describes the DSTni microprocessor and its control registers Section 2 SDRAM Describes the DSTni SDRAM and the registers associated with it Section 3 Serial Ports Describes the DSTni serial ports and the registers associated with them Section 3 Programmable Input Output Describes DSTni s Programmable Input Output PIO functions and the registers associated with them Section 3 Timers Describes the DSTni timers Section 4 Ethernet Controllers Describes the DSTni Ethernet controllers Section 4 Ethernet PHY Describes the DSTni Ethernet physical layer core Section 5 SPI Controller Describes the DSTni Serial Peripheral Interface SPI controller Section 5 I2C Controller Describes the DSTni l C controller Section 5 USB Controller Describes the DSTni USB controller Section 5 CAN Controllers Describes the DSTni Controller Area Network CAN bus controllers Section 6 Interrupt Controller Describes the DSTni interrupt controller Section 6 Miscellaneous Registers Describes DSTni registers not covered in other chapters of this Guide Section 6 Debugging In circuit Emulator Delce Section 6 Packaging and Electrical Des
104. g implementation costs Increasing performance and functionality while maintaining quality and cost effectiveness Streamlining development by reducing programming effort and debugging time Z Enabling solution providers to bring their products to market faster These advantages make DSTni the ideal solution for designs requiring x86 compatibility increased performance serial programmable I O Ethernet and USB communications and a glueless bus interface Intended Audience This User Guide is intended for use by hardware and software engineers programmers and designers who understand the basic operating principles of microprocessors and their systems and are considering designing systems that utilize DSTni Conventions This User Guide uses the following conventions to alert you to information of special interest The symbols and n are used throughout this Guide to denote active LOW signals Notes Notes are information requiring attention Navigating Online The electronic Portable Document Format PDF version of this User Guide contains hyperlinks Clicking one of these hyper links moves you to that location in this User Guide The PDF file was created with Bookmarks and active links for the Table of Contents Tables Figures and cross references Organization This User Guide contains information essential for system architects and design engineers The information in this User Guide is organized into the followin
105. gment S 7 7D D 3 n REPZ SCAS F3 AE Find non AL byte starting at ES DI 5 15n 5 4 m8 7 5D D 3 n REPZ SCAS F3 AF Find non AX word starting at 5 15n 5 4 m16 ES DI 7 5D D 3 n RET C3 Return near to calling procedure 16 5 3 RET CB Return far to calling procedure 22 13 5 RET C2 iw Return near pop imm16 18 5 7 imm16 parameters RET CA iw Return far pop imm16 25 14 9 imm16 ROL DO 0 Rotate 8 bits of r m byte left once 2 15 3 4 1 r m8 1 ROL D2 0 Rotate 8 bits of r m byte left CL 5 n 3 4 4 n r m8 CL times 17 n ROL CO 0 ib Rotate 8 bits of r m byte left imm8 5 n 2 4 4 n r m8 imm8 times 17 n ROL D1 0 Rotate 8 bits of r m word left once 2 15 3 4 1 r m16 1 ROL D3 0 Rotate 8 bits of r m word left CL 5 n 3 4 4 n r m16 CL times 17 n ROL C1 0 ib Rotate 8 bits of r m word left imm8 5 n 2 4 4 n r m16 imm8 times 17 n ROR DO 1 Rotate 8 bits of r m byte right once 2 15 3 4 1 r m8 1 ROR D2 1 Rotate 8 bits of r m byte right CL 5 n 3 4 4 n r m8 CL times 17 n ROR CO 1 ib Rotate 8 bits of r m byte rightimm8 5 n 2 4 4 n r m8 imm8 times 17 n ROR D1 1 Rotate 8 bits of r m word right once 2 15 3 4 1 r m16 1 ROR D3 1 Rotate 8 bits of r m word right CL 5 n 3 4 4 n r m16 CL times 17 n ROR C1 1 ib Rotate 8 bits of r m word right 5 n 2 4 4 n r m16 imm8 imme times 17 n SAHF 9E Store AH in low byte of the 3 2 1 Processor Status Flags register SAL DO 4 Multiply r m byte by 2 once 2 15 3 4 1 r m8 1
106. h AX 6 9n 5 4 m16 7 4D D 3 n REPE CMPS F3 A6 Find nonmatching bytes in ES DI 5 22n 5 4 m8 m8 and segment SI 7 7D D 3 n REPE CMPS F3 A7 Find nonmatching words in ES DI 5 22n 5 4 m16 m16 and segment S 7 7D D 3 n REPE SCAS F3 AE Find non AL byte starting at ES DI 5 15n 5 4 m8 7 5D D 3 n REPE SCAS F3 AF Find non AX word starting at 5 15n 5 4 m16 ES DI 7 5D D 3 n REPNE CMPS F2 A6 Find matching bytes in ES DI and 5 22n 5 4 m8 m8 segment SI 7 7D D 3 n REPNE CMPS F2 A7 Find matching words in ES DI and 5 22n 5l 4t 77 Mnemonic Opcode Description 186 486 DSTni m16 m16 segment SI 7 7D D 3 n REPNE SCAS F2 AE Find AL byte starting at ES DI 5 15n 5 4 m8 7 5D D 3 n REPNE SCAS F2 AF Find AX word starting at ES DI 5 15n 5 4 m16 7 5D D 3 n REPNZ CMPS F2 A6 Find matching bytes in ES DI and 5 22n 5 4 m8 m8 segment SI 7 7D D 3 n REPNZ CMPS F2 A7 Find matching words in ES DI and 5 22n 5 4 m16 m16 segment SI 7 7D D 3 n REPNZSCAS F2 AE Find AL byte starting at ES DI 5 15n 5 4 m8 7 5D D 3 n REPNZ SCAS F2 AF Find AX word starting at ES DI 5 15n 5 4 m16 7 5D D 3 n REPZ CMPS F3 A6 Find nonmatching bytes in ES DI 5 22n 5 4 m8 m8 and segment SI 7 7D D 3 n REPZ CMPS F3 A7 Find nonmatching words in ES DI 5 22n 5 4 m16 m16 and se
107. his register See Table 3 9 LEDO LEDO Control Line Normally this bit connects to the 100Mbit signal If SEN 0 the LEDO signal is driven from the PHY and reading LEDO indicates the PHY status 100Mbit is 0 when in 100Mbit mode If SEN 1 the LEDO signal is driven from this register See Table 3 9 33 Table 3 8 LED Bits 3 and 2 LED3 LED2 ELED2 ELED3 Function Duplex Activity Green R Yellow R 1 1 0 0 No activity 1 0 0 1 Half duplex 0 1 0 0 No activity 0 0 1 0 Full duplex Table 3 9 LED Bits 1 and 0 LEDO ELEDO ELED1 Function 100Mbps Green L Yellow L No link 1 0 0 0 No link 0 1 0 1 10 Mbit link 0 0 1 0 100 Mbit link Note The ELED signals in Table 3 8 and Table 3 9 stand for Encoded LEDs and are enabled by ENC bit 5 in the LED Control register The other LED signals in these tables apply when ENC is off 34 PLL CLK Control Register PLL CLK Control is the Phase Lock Loop Clock Control register Table 3 10 PLL CLK Control Register BIT 14 13 12 11 10 OFFSET 6Eh FIELD E Il a jg Ill A 5 PLLMULT USBDIV d O a Jn o O O 1 mmm o o oOo 0 RW RW RW R R RW RW R RW R TRWT R TR R TR T R W W W W 1 W W 1 W 1 Ww Default 00xx 18h 0 Table 3 11 PLL CLK Control Register Definitions Bits Field Name Description 15 14 Ill Reserved 13 PLL
108. i Qridconnect DSTni EX User Guide Section Six Part Number 900 335 Revision A 3 04 Copyright amp Trademark 2003 Lantronix Inc All rights reserved Lantronix and the Lantronix logo and combinations thereof are registered trademarks of Lantronix Inc DSTni is a registered trademark of Lantronix Inc Ethernet is a registered trademark of Xerox Corporation All other product names company names logos or other designations mentioned herein are trademarks of their respective owners Am186 is a trademark of Advanced Micro Devices Inc Ethernet is a registered trademark of Xerox Corporation SPI is a trademark of Motorola Inc No part of this guide may be reproduced or transmitted in any form for any purpose other than the purchaser s personal use without the express written permission of Lantronix Inc Lantronix 15353 Barranca Parkway Irvine CA 92618 USA Phone 949 453 3990 Fax 949 453 3995 Technical Support Phone 630 245 1445 Fax 630 245 1717 Master Distributor Grid Connect 1841 Centre Point Circle Suite 143 Naperville IL 60563 Phone 630 245 1445 www gridconnect com Am186 is a trademark of Advanced Micro Devices Inc Ethernet is a registered trademark of Xerox Corporation SPI is a trademark of Motorola Inc REV Changes Released Date A Reformat Add changes from Design 3 24 04 Spec 1 1 Warranty Lantronix warrants each Lantronix product to be free
109. ine define define DST_USBO_BASE DST_REG_USB_INT_STAT DST_REG_USB_INT_ENB DST_REG_USB_ERR_STAT DST_REG_USB_ERR_ENB DST_REG_USB_STAT DST_REG_USB_CTL DST_REG_USB_ADDR DST_REG_USB_BDT_PAGE DST_REG_USB_FRM_NUML DST_REG_USB_FRM_NUMH DST_REG_USB_TOKEN DST_REG_USB_SOF_THLDL DST_REG_USB_SOF_THLDH DST_REG_USB_ENDPTO DST_REG_USB_ENDPT1 DST_REG_USB_ENDPT2 DST_REG_USB_ENDPT3 DST_REG_USB_ENDPT4 DST_REG_USB_ENDPT5 DST_REG_USB_ENDPT6 DST_REG_USB_ENDPT7 DST_REG_USB_ENDPT8 DST_REG_USB_ENDPT9 DST_REG_USB_ENDPT10 DST_REG_USB_ENDPT11 DST_REG_USB_ENDPT12 DST_REG_USB_ENDPT13 DST_REG_USB_ENDPT14 DST_REG_USB_ENDPT15 CAE AE ESE E E e RRE RAE I2C Controller Registers kk tdefine tdefine tdefine tdefine tdefine tdefine tdefine tdefine DST_I2C0_BAS DST DST DST DST DST DST DST q EG_I2CSRST EG I2CXADDR EG I2CCCR EG I2CSTAT EG I2CCNTR EG I2CDATA EG I2CADDR DST SPIO BASE DST SPIO BASE DST SPIO BASE des e des Ge es ue de ESO E LIMEN EC EL E E M E 0x9800 DST USBO DST USBO DST USBO DST USBO DST USBO DST USBO DST USBO DST USBO DST USBO BASE DST USBO BASE DST USBO DST USBO BASE DST USBO DST USBO BAS DST USBO BAS DST USBO BAS DST USBO BAS DST USBO BAS DST USBO BAS DST USBO BAS
110. ing DMA channel interrupt request line Resetting any of these bits removes the interrupt request 11 8 SP 3 0 State of the Asynchronous Serial Port Interrupt Requests These bits are set when the respective serial port generates an interrupt request These bits clear when the respective interrupt acknowledge cycle occurs D3 0 In service bits for DMA channels DMA3 0 10 Logical OR connected to both internal MACs This bit is the in service bit 7 13 Logical OR Connected to External Interrupt 3 and the USB Controller This bit is the in service bit for this interrupt source 6 12 Logical OR Connected to the SPI Controller and the FC Controller This bit is the in service bit for this interrupt source 5 11 Logical OR Connected to External Interrupt 1 and Ethernet MAC 1 This bit is the in service bit for this interrupt source 4 10 Ethernet MAC 0 This bit is the in service bit for this interrupt source 3 2 D 1 0 In Service Bits for DMA Channels DMA1 0 1 Ill Reserved 0 TMR Logical OR of All Timer Interrupt Requests The individual timer interrupt request bits are contained in the interrupt status register This bit cannot be written 26 Priority Mask Register Table 2 37 Priority Mask Register BIT 13 12 11 10 EON OFFSET 2Ah FIELD Ill gt Y amp a a a RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
111. ing a CPU Clock Speed of 96 MHZ 112 1 About This User Guide This User Guide describes the technical features and programming interfaces of the Lantronix DSTni EX chip hereafter referred to as DSTni DSTni is an Application Specific Integrated Circuit ASIC based single chip solution SCS that integrates the leading edge functionalities needed to develop low cost high performance device server products On a single chip the DSTni integrates an x186 microprocessor 16K byte ROM 256K byte SRAM programmable input output I O and serial Ethernet and Universal Serial Bus USB connectivity key ingredients for device server solutions Although DSTni embeds multiple functions onto a single chip it can be easily customized based on the comprehensive feature set designed into the chip Providing a complete device server solution on a single chip enables system designers to build affordable full function solutions that provide the highest level of performance in both processing power and peripheral systems while reducing the number of total system components The advantages gained from this synergy include Simplifying system design and increased reliability Minimizing marketing and administration costs by eliminating the need to source products from multiple vendors Eliminating the compatibility and reliability problems that occur when combining separate subsystems Z Dramatically reducin
112. ings the level must remain HIGH until the interrupt is acknowledged 3 MSK Mask Interrupt 1 mask respective interrupt request default 0 enable respective interrupts 2 0 PR 2 0 Programmable Priority Level The programmable priority level for the respective interrupt source 111 lowest priority default 000 highest priority 22 DMA 1 Interrupt Control Register Table 2 25 DMA 1 Interrupt Control Register OFFSET FIELD Table 2 26 DMA 1 Interrupt Control Register Definitions Bits Field Name Description 15 4 MW Reserved 3 MSK Mask Interrupt 1 mask respective interrupt request default 0 enable respective interrupts 2 0 PR 2 0 Programmable Priority Level The programmable priority level for the respective interrupt source 111 lowest priority default 000 highest priority DMA 0 Interrupt Control Register Table 2 27 DMA 0 Interrupt Control Register BIT 12 11 10 OFFSET 34h FIELD 0 R W 0 R W 0 R W 0 R W Table 2 28 DMA 0 Interrupt Control Register Definitions Bits Field Name Description 15 4 Reserved 3 MSK Mask Interrupt 1 mask respective interrupt request default 0 enable respective interrupts 2 0 PR 2 0 Programmable Priority Level The programmable priority level for the r
113. into the TRACE buffer In Branch History mode the 48 bit bus is split into two 24 bit words The low 24 bit word corresponds to the physical address pointed to by the segment register and Instruction Pointer value before the branch was taken the SOURCE address The high 24 bit word corresponds to the CS IP value after the branch is taken the TARGET address The NEWIP signal from the CPU core is active high when the IP is about to be reloaded The IP bus on the CPU is the Instruction Pointer value from within the CPU execution unit The IP bus is latched while NEWIP is active to capture the SOURCE address The clock after NEWIP is active the IP bus will be latched again to capture the TARGET address Note The SOURCE address always points to the last byte of the opcode Therefore software must read the SOURCE address then disassemble the code at that address and look a few bytes backwards to find the instruction that caused the branch If an interrupt was taken then TARGET address indicates that an interrupt was taken and as a result the SOURCE address will point to the address of the return address after the interrupt has been serviced 42 Bits 15 8 Timer mode also splits the 48 bit TRACE buffer into two 24 bit words In this mode each 24 bit word corresponds to the number of clock cycles divided by 8 between triggers The most significant 2 bits indicate which trigger caused a store to the TRACE buffer If the counter overflows the 22
114. ions that modify segment registers like POP DS or the WAIT instruction Taking the trace interrupt clears the TF bit after the microprocessor status flags are pushed onto the stack The IRET instruction at the end of the single step interrupt service routine restores the microprocessor status flags and the TF bit and transfers control to the next instruction to be traced Trace mode is initiated by pushing the microprocessor status flags onto the stack then setting the TF flag on the stack and then popping the flags 11 Nonmaskable Interrupt NMI Interrupt Type 02h This pin tells DSTni that an interrupt request has occurred The NMI signal is the highest priority hardware interrupt and unlike the INT4 INTO pins cannot be masked DSTni always transfers program execution to the location specified by the nonmaskable interrupt vector in the DSTni interrupt vector table when NMI is asserted Although NMI is the highest priority interrupt source it does not participate in the priority resolution process of the maskable interrupts There is no bit associated with NMI in the interrupt in service or interrupt request registers This means that a new NMI request can interrupt an executing NMI interrupt service routine As with all hardware interrupts the IF interrupt flag clears when the microprocessor takes the interrupt disabling the maskable interrupt sources However if maskable interrupts are re enabled by software in the NMI inte
115. iority default 000 highest priority INT2 SPI C Interrupt Control Register Table 2 19 INT2 SPC Interrupt Control Register BIT 15 14 13 12 11 10 OFFSET 3Ch FIELD Ill i Zisizisg BS RR amp RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Bits 15 5 Field Name Table 2 20 INT2 SPI C Interrupt Control Register Definitions Description Reserved 4 LTM Level Trigger Mode Sets the respective interrupt source 1 enable level triggered mode An interrupt generates when the external interrupt signal is HIGH 0 enable edge triggered mode default For both settings the level must remain HIGH until the interrupt is acknowledged MSK Mask Interrupt 1 mask respective interrupt request default 0 enable respective interrupts 2 0 PR 2 0 Programmable Priority Level The programmable priority level for the respective interrupt source 111 lowest priority default 000 highest priority 20 INT1 or Ethernet MAC 1 Interrupt Control Register Table 2 21 INT1 or Ethernet MAC 1 Interrupt Control Register BIT 45 14 413 1412 11 10 9 8 OFFSET 3Ah FIELD Ill 5 N o FIS J RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
116. m word 4 10 1 2 1 4 r m16 imm16 TEST 84 r AND byte register with r m byte 3 10 1 2 1 4 r m8 r8 TEST 85 r AND word register with r m word 3 10 1 2 1 4 r m16 r16 WAIT 9B Performs a NOP XCHG 90 rw Exchange word register with AX 3 3 3 AX r16 XCHG 90 rw Exchange AX with word register 3 3 3 r16 AX 80 Mnemonic Opcode Description 186 486 DSTni XCHG 86 r Exchange byte register with r m 4 17 3 5 3 7 r m8 r8 byte XCHG 86 r Exchange r m byte with byte 4 17 3 5 3 7 r8 r m8 register XCHG 87 Ir Exchange word register with r m 4 17 3 5 3 7 r m16 r16 word XCHG 87 Ir Exchange r m word with word 4 17 3 5 3 7 r16 r m16 register XLAT D7 Set AL to memory byte 11 4 5 m8 segment BX unsigned AL XLATB D7 Set AL to memory byte 11 4 5 segment BX unsigned AL XOR 34 ib XOR immediate byte with AL 3 1 1 AL imm8 XOR 35 iw XOR immediate word with AX 4 1 1 AX imm16 XOR 80 6 ib XOR immediate byte with r m byte 4 16 1 3 1 4 r m8 imm8 XOR 81 6 iw XOR immediate word with r m word 4 16 1 3 1 4 r m16 imm16 XOR 83 6 ib XOR sign extended immediate 4 16 1 3 1 4 r m16 imm8 word with r m word XOR 30 r XOR byte register with r m byte 3 10 1 3 1 4 r m8 r8 XOR 31 r XOR word register with r m word 3 10 1 3 1 4 r m16 r16 XOR 32 Ir XOR r m byte with byte register 3 10 1 3 1 4 r8 r m8 XOR 33 r XOR r m word with word register 3 10 1 3 1 4 r16 r m16
117. m16 r16 CMP 3A Jr Compare r m byte to byte register 3 10 Y 1 4 r8 r m8 CMD 3B r Compare r m word to word register 3 10 Y 1 4 r16 r m16 CMPS A6 Compare byte ES DI to byte 22 8 5 m8 m8 segment SI CMPS AT Compare word ES DI to word 22 8 5 m16 m16 segment SI CMPSB A6 Compare byte ES DI to byte 22 8 5 DS SI CMPSW AT Compare word ES DI to word 22 8 5 DS SI CWD 99 Put signed extension of AX in 4 3 1 DX AX DAA 27 Decimal adjust AL after addition 4 2 2 DAS 2F Decimal adjust AL after subtraction 4 2 2 DEC FE 1 Subtract 1 from r m byte 3 15 1 3 1 4 72 Mnemonic Opcode Description 186 486 DSTni r m8 DEC FF 1 Subtract 1 from r m word 3 15 1 3 1 4 r m16 DEC 48 rw Subtract 1 from word register 3 1 1 r16 DIV F6 6 AL AX r m byte AH remainder 29 35 16 16 13 16 l r m8 DIV F7 6 AX DX AX r m word 38 44 24 24 21 2441 r m16 DX remainder ENTER C8 iw ib Create stack frame for nested 22 14 9 imm16 imm8 procedure 16 n 1 6 n 1 ENTER C8 iw 00 Create stack frame for non nested 15 14 7 imm16 0 procedure ENTER C8 iw 01 Create stack frame for nested 25 17 9 6 n 1 imm16 1 procedure ESC m D8 0 Takes trap 7 2 2 l D9 1 Takes trap 7 2 2 2 l DA 2 Takes trap 7 2 DB 3 Takes trap 7 2 1 DC 4 Takes trap 7 2 1 DD 5 Takes trap 7 2 2 l DE 6 Takes trap 7 2 2 2 l DF 7 Takes trap 7 2 1 HLT F4
118. mask bit in each control register IfIF 0 all maskable interrupts are disabled The IF flag does not affect the NMI or software exception interrupts interrupt types 00h to 07h or the execution of any interrupt through the INT instruction Interrupt Mask Bit Each interrupt control register for the maskable interrupts contains a mask bit MSK If MSK 7 1 for a particular interrupt that interrupt is disabled regardless of the IF setting Interrupt Priority The column titled Default Priority in Table 2 1 on page 7 shows the priority for the interrupts at power on reset The nonmaskable interrupts 00h through 07h are always prioritized ahead of the maskable interrupts To reprioritize the maskable interrupts reconfigure the PR2 PRO bits in the interrupt control registers The PR2 PRO bits in all the maskable interrupts are set to priority level 7 at power on reset Software Interrupts Software interrupts can be initiated by the INT instruction Any of the 256 possible interrupts can be initiated by the INT instruction INT 21h causes an interrupt to the vector located at 00084h in the interrupt vector table INT FFh causes an interrupt to the vector located at 003FCh in the interrupt vector table Software interrupts are not maskable and are not affected by the setting of the IF flag Software Exceptions A software exception interrupt occurs when an instruction causes an interrupt due to a condition in the mic
119. ming some code execution The linear number consists of two 16 bit registers with RS 1 being the most significant 16 bits Table 3 13 Random Number Generator Register BIT 12 11 10 OFFSET IM Don t Care RS LI DATA 15 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R Ww Ww Table 3 14 Random Number Generator Register Definitions Bits Field Name Description 15 2 Ill Don t Care 1 RS Register Select 0 register 0 1 register 1 Only used in Linear Number mode See Table 3 15 0 LI Linear 0 selects Pseudo Random number in a 16 bit register 1 7 selects Linear numbers in a 32 register See Table 3 15 15 0 DATA 15 0 Random Number Generator Data A counter running at the current CPU clock frequency that continuously updates on each clock Table 3 15 RS LI Combinations RS LI Description l 0 0 Pseudo Random Number 16 bits 0 1 Linear Clock Counter lower 16 bits 1 0 1 1 Reserved Linear Clock Counter Upper 16 bits 38 4 Debugging In circuit Emulator Delce This chapter describes the Debugging In circuit Emulator Delce Topics in this chapter include Theory of Operation on page 39 FS2 Target Connection on page 45 Theory of Operation The CPU has an integrated Joint Test Action Group JTAG DeBugger In Circuit Emulator called CPUDICE CPUDICE int
120. nitions ceeeicisesceieesesie tenens tinent hn inantea 29 Table 2 45 End of Interrupt Register ennemi 30 Table 2 46 End of Interrupt Register Definitions se e 30 Table 3 1 Miscellaneous Register Summary sse ene 31 Table 3 2 Checksum Adder Register sse eee 32 Table 3 3 Checksum Adder Register Definitions ssee e 32 Table 3 4 Checksum Data Register sss enm eene 32 Table 3 5 Checksum Data Register Definitions e em 32 Table 3 6 LED Control Register seene 33 Table 3 7 LED Control Register Definitions ss em 33 Table 3 8 LED Bits 3 and 2 erri cdit ito 34 Table 3 9 LED Bits 1 and 0 eriperet toten eene ca etae Ln en ron itn 34 Table 3 10 PLL CLK Control Register ssssseeene emm eene rre 35 Table 3 11 PLL CLK Control Register Definitions eeses e 35 Table 3 12 Divider Bits and Corresponding Values see 36 Table 3 13 Random Number Generator Register sees eee 38 Table 3 14 Random Number Generator Register Definitions sese ee eee eee eee eee ee 38 Table 3 15 RS LI Combinations TTT 38 Table 4 1 ADDR DATA and STAT Scan Chain eee eee 40 Table 4 2 STATUS Scan Chain c oooonooccccnnociconononcnnnoncncnononcnn conc nnnnno nn rra rn 41 Table 4 3 TRAGE B ffer iii taria 43 Table 4 4
121. nsigned r m word by 2 CL 5 n 3 4 4 n r m16 CL times 17 n SHR C1 5 ib Divide unsigned r m word by 2 5 n 2 4 4 n r m16 imm8 imme times 17 n STC F9 Set the Carry Flag to 1 2 2 1 STD FD Set the Direction Flag so the 2 2 1 Source Index SI and or the destination Index DI registers will decrement during string instructions STI FB Enable maskable interrupts after 2 5 1 the next instruction STOS m8 AA Store AL in byte ES DI Update DI 10 5 2 STOS m16 AB Store AX in word ES DI Update 10 5 2 DI STOSB AA Store AL in byte ES DI Update DI 10 5 2 STOSW AB Store AX in word ES DI Update 10 5 2 DI SUB 2C ib Subtract immediate byte from AL 3 1 1 AL imm8 SUB 2D iw Subtract immediate word from AX 4 1 1 AX imm16 SUB 80 5 ib Subtract immediate byte from r m 4 16 1 3 1 4 r m8 imm8 byte SUB 81 5 iw Subtract immediate word from r m 4 16 1 3 1 4 r m16 imm16 word SUB 83 5 ib Subtract sign extended immediate 4 16 1 3 1 4 r m16 imm8 byte from r m word SUB 28 Ir Subtract byte register from r m byte 3 10 1 3 1 4 r m8 r8 SUB 29 Ir Subtract word register from r m 3 10 1 3 1 4 r m8 r16 word SUB 2A Ir Subtract r m byte from byte register 4 16 1 3 1 4 r8 r m8 SUB 2B r Subtract r m word from word 4 16 1 3 1 4 r16 r m16 register TEST A8 ib AND immediate byte with AL 3 1 1 AL imm8 TEST A9 iw AND immediate word with AX 4 1 1 AX imm16 TEST F6 0 ib AND immediate byte with r m byte 4 10 1 2 1 4 r m8 imm8 TEST F7 0 iw AND immediate word with r
122. ntroller Constants KK Ok Ck Ck Ck Ck k Ck X ck Ck Ck Ck o X X ck ck k ko X X Xk ok k k ox ox d Ethernet Here are define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define 3 d 3 C P INTMSK EATURE zl 3 C S C d 3 d gl d El El C El 2l d 3 U HU U U U U U U U U U U el 3 C HH Ed Dd Dd D Du Du Dd Dr D Dd Dd Dd Dj Du Du Dd Dd Dd D CT i SSSS SSS SESS SSS SS SS SS amp Ethernet E C 3 30 WH ui ui i JHA 171 HH aZ 3d gl Jg o Z E pd DE D D Dd Ed 9 d 314343 3 HI Zz un A 2909 HD UGQ 0 JH G gl El 3 3 E p E QQQ Dd Ethernet B 333 3H S d Ej pd DE D D Hi 3 PR Pa O 2 DMD TOP RT p INIT errupt mask IMSK_MISSM IMSK_RINTM IMSK_TINTM IMSK_IDONM IMSK_DTX2PD P Register Address Port ters accessible via RAP RDP P_STATUS 00 12 16 13 32 14 25 POLL INTVL 47 RXLEN UXLEN P MISSD FRM 112 P_RCV_COL tus register bits CSR0 RR ERR O
123. o PHY K Tope USB Divider 3 0 PLL To internal ls T ones Register Clock PLL PEL amp USB Oscillator Pre Divider Md Multiplier aez BYPASS Clock To internal 25Mz Fixed at 25 CLK 10 127 MUX gt Divider CLKUSB DR eu Default 24 1 16 0 Default 1 Frequency Range PLL s 20 254Mhz oa PLL Multiplier 6 0 Post Divider A Fixed at 2 PLLBYP n PLLBYP_n DA To External gt CLKOUT M Devices PLLCLK 2 Frequency Range 10 127Mhz P dil jc Input Clock is fixed at 25Mhz PLLCLK is the PLL output clock and is programmable by PLL Multiplier CLK WRT 20 254Mhz Final output frequency 1 5ns before CLK_CPU l after post divider is 10 127Mhz If d ca PLLBYP is high then the CLKOUT is Lo ticas used as an input and output to the BYPASS internal WRTCLK and USBCLK MUX CLK_WRT CLK CPU so CLOCK TREE s a PLEBYP n PLLBYP Clock Generator Rev B 37 Random Number Generator Register The Random Number Generator register provides a random number for use in the TCPIP or MAC as an address The random number generator is a counter running at the current CPU clock frequency and continuously updates on each clock The data read is a 16 bit data field Writes to this register are to bits 1 and 0 Writes to this register control which type number is returned The random numbers are not affected by these writes The linear version of the random number can also be used to indicate the number of clocks that have passed for ti
124. ograms The chain is 24 bits long with bit O shifted out first and bit 23 shifted out last The address is the linear address generated after the offset is added to the segment register 39 DATA Scan Chain The DATA scan chain consists of the 16 bit DATA bus and 8 bits of control status information These 24 bits are appended to the front of the ADDR scan chain Bits 2 0 indicate the type of cycle requested or captured as defined in the CPU STATUS signals Bit 3 has two different meanings depending on whether data is being captured or cycles are being initiated When bus cycles are being captured bit 3 is a one when a DMA cycle has been captured Z When performing MEMREAD MEMWRITE IOREAD or IOWRITE JTAG instructions program bit 3 with either a 1 when a 16 bit cycle is desired or a zero when an 8 bit cycle is desired When using the APPLY_CPU instruction bits 5 and 4 in the control chain have special meaning When bit 4 is set and the APPLY_CPU instruction is used the CPU s instruction queue is flushed before the scanned in vector is applied Bit 5 is a select for opcodes versus data When applying data for an opcode fetch bit 5 should be clear When applying data for a memory or I O read anything but an opcode fetch bit 5 should be set Table 4 1 ADDR DATA and STAT Scan Chain Field Name Description 23 0 ADDR 23 0 ADDR 23 0 39 24 DATA 15 0 Data 15 0 47 40 STAT 2 0 STAT
125. ord with borrow SBB 18 r Subtract byte register from r m byte 3 10 1 3 1 4 r m8 r8 with borrow SBB 19 r Subtract word register from r m 3 10 1 3 1 4 r m16 r16 word with borrow SBB 1A r Subtract r m byte from byte register 3 10 1 3 1 4 r8 r m8 with borrow SBB 1B r Subtract r m word from word 3 10 1 3 1 4 r16 r m16 register with borrow SCAS AE Compare byte AL to ES DI 15 6 4 m8 Update DI SCAS AF Compare word AX to ES DI 15 6 4 m16 Update DI SCASB AE Compare byte AL to ES DIT 15 6 4 Update DI SCASW AF Compare word AX to ES DI 15 6 4 Update DI SHL DO 4 Multiply r m byte by 2 once 2 15 3 4 1 r m8 1 SHL D2 4 Multiply r m byte by 2 CL times 5 n 3 4 4 n r m8 CL 17 n SHL CO 4 ib Multiply r m byte by 2 imm8 times 5 n 2 4 4 n r m8 imm8 17 n SHL D1 4 Multiply r m word by 2 once 2 15 3 4 1 r m16 1 SHL D3 4 Multiply r m word by 2 CL times 5 n 3 4 4 n r m16 CL 17 n SHL C1 4 ib Multiply r m word by 2 imm8 times 5 n 2 4 4 n r m16 imm8 17 n SHR DO 5 Divide unsigned r m byte by 2 2 15 3 4 1 r m8 1 once 79 Mnemonic Opcode Description 186 486 DSTni SHR D2 5 Divide unsigned r m byte by 2 CL 5 n 3 4 4 n r m8 CL times 17 n SHR CO 5 ib Divide unsigned r m byte by 2 5 n 2 4 4 n r m8 imm8 imm times 17 n SHR D1 5 Divide unsigned r m word by 2 2 15 3 4 1 r m16 1 once SHR D3 5 Divide u
126. outport DST REG EOI DST IVECT TMR1 C P FUNCTION U32 u32DstGetTime void ARGUMENTS 0 RETURNS U32 Number of elapsed ticks DESCRIPTION Returns number of clock ticks since the last reset kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk U32 u32DstGetTime void U32 u32Time Since this is a 16 bit CPU we need to protect against the long word SysTime being changed in the middle of a copy That s why we disable interrupts during the copy asm pushf asm cli u32Time mu32SysTime asm popf return u32Time 106 9 Baud Rate Calculations This appendix shows the baud rate calculations for the following CPU clock speeds 20 MHz see page 107 24 MHz see page 108 25 MHz see page 109 36 MHz see page 109 48 MHz see page 110 60 MHz see page 110 72 MHZ see page 111 84 MHz see page 111 96 MHz see page 112 Using this information you can calculate valid baud rate values for the CPU clock speed s you want to use The acceptable error rate is 3 or 2 5 9 6 48 490 900 Legend Table 9 1 Baud Rate Calculations Using a CPU Clock Speed of 20 MHz Baud Rate DivisorLow Divisor High Freq High Freq Low High Error Low Error 107 Table 9 2 Baud Rate Calculations Using a CPU Clock Speed of 24 MHz Baud Rate DivisorLow Divisor High Freq High FreqLow High Error Low E
127. p BAAn a nn I gt M iCHBAL CHBAH UCSn 2 Wait States D Wait n RSTOn RSTn LBAn Flash access time is Initial Flash Access tCHCL tcLBCH tCHRDS Flash access time is Burst Flash Access CHCL tcLBCH CHRDS Example 50Mhz clock 20ns want to use 70ns flash 24ns burst Initial 70ns 10ns 2 75ns 3ns 85 75ns lt 5 20ns 4 wait states wait states 1 tCHCH Burst 24ns 10ns 2 75ns 3ns 38 75ns lt 2 20ns 1 wait states wait states 1 tCHCH Note AMD burst flash devices require 2 clocks during an address load operation Therefore connect CPUCLK to CLK on these devices 60 Burst Flash 2 Wire ADDRESS ucsn y i fe tcHuH M ICHUL I L tcHkoL gt tCHRDH 2 Wire Burst Fog rere E wN tem e tenw Wa ay ro I Ron o Ri diat on enn Www we LL taHw I l Address Fg l b CH V w icHAV DB15 0 ReadDaja gt CHRH rua f Lf lT Ln tcHRDS e BCLK tcHwov r tcHwDv Address Loaded Address Incremented BCLK l i i I LBAn IICLBCH m m tcHBCL UCSn 2 Wait States D Wait I M CHLBL m tcHLBH A231 Flash access time is Initial Flash Access tcHCL tcLBCH tCHRDS Flash access time is Burst Flash Access tCHCL tcLBCH tCHRDS Example 50Mhz clock 20ns want to use 70ns flash 24ns burst Initial 70ns 10ns
128. pt Ethernet Mode CSR15 define DST_ETHMODE_PROM 0x8000 Enable promiscuous mode define DST_ETHMODE_DRXBC 0x4000 Disable multicast receive define DST_ETHMODE_DRXPA 0x2000 Disable receive physical address define DST_ETHMODE_DPAUSE 0x0800 Disable automatic pause define DST_ETHMODE_DRTY 0x0020 Disable transmit retries define DST_ETHMODE_DTXFCS 0x0008 Disable CRC generation define DST_ETHMODE_DTX 0x0002 Disable transmit operation define DST_ETHMODE_DRX 0x0001 Disable receive operation kk k Ethernet Media Independent Interface MII constants kk k AN define DST_ETHMII_FDEN 0x8000 Full duplex enable define DST_ETHMII_MDI 0x0100 Management data in bit define DST_ETHMII_MDOE 0x0080 MDIO pin output enable define DST_ETHMII_MDC 0x0002 Management data clock define DST_ETHMII_MDO 0x0001 Management data out bit kk w e CAN Register Constants kk e we y CAN Transmit message data length amp control define DST CAN TXMSG IDE 0x0010 Extended identifier bit define DST CAN TXMSG RTR 0x0020 Remote bit CAN Transmit control flags
129. pt Enable resume interrupt Enable sleep interrupt Enable token done interrupt Enable start of frame interrupt error interrupt Enable reset interrupt 100 USB Error Interrupt Status define DST_USB_ERR_STAT_BTS_ERR Bit 6 define DST_USB H un reserved R_STAT_DMA_ERR define DST_USB R_STAT_BTO_ERR define DST_USB_ define DST_USB_ define DST_USB define DST_USB define DST_USB E E E DE Dd Ed Dd U 0 0 0 0 0 YO R_STAT_DFN8 0x08 R_STAT_CRC16 R_STAT_CRC5 0x02 R_STAT_EOF R_STAT_PID_ERR USB Error Interrupt Enable define DST_USB_ERR_ENB_BTS_ERR Bit 6 is reserved define DST_USB_ERR_ENB_DMA_ERR define DST_USB_ERR_ENB_BTO_ERR define DST_USB_ERR_ENB_DFN8 define DST_USB_ERR_ENB_CRC16 0x04 define DST_USB_ERR_ENB_CRC5 define DST_USB_ERR_ENB_EOF define DST_USB_ERR_ENB_PID_ERR USB Status define DST_USB_STAT_ENDP_MSK 0xF0 define DST_USB_STAT_ENDP_TX define DST_USB_STAT_ENDP_ODD 0x04 USB Control J define DST USB CTL SEO define DST USB CTL TXD define DST USB CTL JSTATE define DST USB CTL TOK xi SUSPEND N BUSY 3 n define DST_USB_CTL_HOS define DST USB CTL RESI MODE EN define DST USB CTL RES d H ml ME define DST_USB_CTL_USB USB Address USB
130. pt Control Register 0 02 eee eee 23 Table 2 26 DMA 1 Interrupt Control Register Definitions sss sese eee eee ee ee eee e eee 22 Table 2 27 DMA 0 Interrupt Control Register sss 23 Table 2 28 DMA 0 Interrupt Control Register Definitions sss eee eee eee eee eee eee 23 Table 2 29 Timer Interrupt Control REGiSter 0 seee sese esseeeesseee ees ee eee esser eonenn eem 24 Table 2 30 Timer Interrupt Control Register Definitions sese ee eee eee eee eee eee eee 24 Table 2 31 Interrupt Status Register 0 0 ee esseocszsoss esse segzss sos cez ose2os idrica iiis 24 Table 2 32 Interrupt Status Register Definitions ee eee eee eee ee eee e 24 Table 2 33 Interrupt Request Register ssgssessseesssecsegse ess essss es ecse eee eesg eene nene 25 Table 2 34 Interrupt Request Register Definitions e e 25 Table 2 35 In Service Register cion nte 26 Table 2 36 In Service Register Dehnitiong sese eee eee eee eee eee eee 26 Table 2 37 Priority Mask Reglster onore teta tenth rh e Rr rep ala aia aia 27 Table 2 38 Priority Mask Register Definitions sees eee ee eee eee eee eee 27 Table 2 39 Interrupt Mask RegiSteT ooocooonncnnncccinnnoccccnonannnnnonnccnnno nc nc nono enne ennemi 28 Table 2 40 Interrupt Mask Register Definitions eee eee eee eee eee eee eee 28 Table 2 41 Poll Status Register eee eee 29 Table 2 42 Poll Status Register Definitions 29 Table 2 43 e Tel T 29 Table 2 44 Poll Register Defi
131. rmation only and are not guaranteed and not production tested Note DSTni EX uses two power supply voltages one for core logic 1 8V and another for I O 3 3V If the 3 3V supply is powered and the 1 8V core logic is not powered current in excess of 350ma will flow into the chip This is not a problem for short periods not to exceed 1 minute Longer periods could overheat DSTni and cause device failure 50 I O Characteristics Xin Xout Pins Table 5 3 I O Characteristics Xin Xout Pins Parameter Sym Min Typ Max Units Input Clock Frequency Tolerance Af Ill Ill 100 ppm Input Clock Duty Cycle TDC 35 Ill 65 Input Capacitance CIN Ill 3 0 Ill pF PHY Receiver Input Characteristics Item Table 5 4 PHY Receiver Input Characteristics Spec Units Comments Full Scale Input voltage 3 0 Differential pk to pk Input Common Mode Gain dependent 100Base TX Transceiver Characteristics Table 5 5 100Base TX Transceiver Characteristics Parameter Sym Min Typ Max Units Peak Differential Output Voltage VP 0 95 Ill 1 05 V 100M TX mid level Ill 50 Ill 50 mV Signal Amplitude Symmetry VSS 98 Ill 102 Signal Rise Fall Time TRF 3 0 Ill 5 0 ns Rise Fall Time Symmetry TRFS Ill Ill 0 5 ns Duty Cycle Distortion DCD 35 50 65 Overshoot Undershoot VOS Ill Ill 5 Jitter measured differentially Ill Ill Ill 1 4 ns 100Base FX Transceiver Chara
132. rol Register sees eee eee Table 2 8 DMA 2 Interrupt Control Register Definitions sss ec eee eee ee ee eee eee Table 2 9 Serial Port 3 Interrupt Control Register eee eee eee Table 2 10 Serial Port 3 Interrupt Control Register Definitions sse sese eee eee eee eee eee Table 2 11 Serial Port O Interrupt Control Register sese sese eee eee Table 2 12 Serial Port 0 Interrupt Control Register Definitions sse eee eee eee eee eee eee Table 2 13 Serial Port 1 Interrupt Control Register ieee eee eee Table 2 14 Serial Port 1 Interrupt Control Register Definitions sse sese eee eee eee eee ee Table 2 15 Serial Port 2 Interrupt Control Register sese eee eee eee Table 2 16 Serial Port 2 Interrupt Control Register Definitions sees eee eee eee eee eee eee Table 2 17 INT3 or USB Interrupt Control Register sse Table 2 18 Serial Port 2 Interrupt Control Register Definitions sse eee ee eee eee ee eee ee Table 2 19 INT2 SPI C Interrupt Control Register ee eee eee Table 2 20 INT2 SPI I C Interrupt Control Register Definitions Table 2 21 INT1 or Ethernet MAC 1 Interrupt Control Register sese eee eee Table 2 22 INT1 or Ethernet MAC 1 Interrupt Control Register Definitions 21 Table 2 23 Ethernet MAC 0 INTO Interrupt Control Register sse eee eee eee 22 Table 2 24 Ethernet MAC 0 INTO Interrupt Control Register Definitions 22 Table 2 25 DMA 1 Interru
133. roprocessor Interrupt types 00h 01h 03h 04h 05h 06h and 07h are software exception interrupts Software exceptions are not maskable and are not affected by the setting of the IF flag Interrupt Conditions and Sequence The following sections describe how interrupts are serviced Nonmaskable Interrupts The following nonmaskable interrupts are serviced regardless of the setting of the interrupt enable flag IF in the microprocessor status flags Z The trace interrupt The NMI interrupt Z Software interrupts both user defined INT and software exceptions Maskable Hardware Interrupts For maskable hardware interrupt requests to be serviced The STI instruction must set the IF flag must be set and 4 The mask bit associated with each interrupt must be reset Interrupt Request When an interrupt is requested DSTni s internal interrupt controller verifies that the interrupt is enabled and that there are no higher priority interrupt requests being serviced or pending If the interrupt request is granted the interrupt controller uses the interrupt type to access a vector from the interrupt vector table see Table 2 1 on page 7 Each interrupt type has a four byte vector available in the interrupt vector table The interrupt vector table is located in the 1024 bytes from 00000h to 003FFh Each four byte vector consists of a 16 bit offset IP value and a 16 bit segment CS value The 8 bit interrupt type is shifted left 2
134. rror 108 Table 9 3 Baud Rate Calculations Using a CPU Clock Speed of 25 MHz Baud Rate Divisor Low Divisor High Freq High FreqLow High Error Low Error 921600 1 2 1562500 781250 69 54 15 23 460800 3 4 520833 3 390625 13 03 1523 230400 6 7 260416 7 223214 3 13 03 3 12 115200 13 14 120192 3 111607 1 4 33 3 12 76800 20 21 78125 74404 76 1 73 3 12 57600 27 28 57870 37 55803 57 0 47 3 12 56000 27 28 57870 37 55803 57 3 34 0 35 38400 40 4 39062 5 38109 76 1 73 0 76 28800 54 55 28935 19 28409 09 0 47 1 36 19200 81 82 19290 12 19054 88 0 47 0 76 9600 162 163 9645 062 9585 89 0 47 0 15 7200 217 218 7200 461 7167 431 0 01 0 45 4800 325 326 4807 692 4792 945 0 16 0 15 2400 651 652 2400 154 2396 472 0 01 0 15 1200 1302 1303 1200 077 1199 156 0 01 0 07 Table 9 4 Baud Rate Calculations Using a CPU Clock Speed of 36 MHz Baud Rate Divisor Low Divisor High Freq High FreqLow High Error Low Error 921600 zi 3 1125000 750000 22 07 18 62 460800 4 5 562500 450000 22 07 2 34 230400 9 10 250000 225000 8 51 2 34 115200 19 20 118421 1 112500 2 80 2 34 76800 29 30 77586 21 75000 1 02 2 34 57600 39 40 57692 31 56250 0 16 2 34 56000 40 4l 56250 54878 05 0 45 2 00 38400 58 59 38793 1 38135 59 1 02 0 69 28800 78 79 28846 15 28481 01 0 16 1 11 19200 NK 118 19230 77 19067 8 0 16 0 69 9600 234 235 9615 385 9574 468 0 16 0 27 7200 312 313 7211 538 7188 498 0 16 0 16 4800
135. rrup terrup Ct ct TEE GT GEE E xy errupt priority priority priority priority priority priority priority priority priority priority priority priority priority priority priority priority 7 6 5 4 3 2 T 0 7 6 5 4 3 2 T 0 lowest x ef highest triggering his interrupt lowest K x f highest Non specific end of interrupt Set if interrupt is pending Mask off the interrupt vector Interrupt vectors devices define DST_IVECT_CAN 24 I6 CAN1 amp CANO define DST_IVECT_DMA3 23 DMA channel 3 define DST_IVECT_DMA2 22 DMA channel 2 define DST IVECT SP3 21 I5 Serial port 3 define DST IVECT INT5 21 I5 External INT5 pin define DST IVECT SPO 20 Serial Port Q define DST IVECT TMR2 19 Timer 2 define DST IVECT TMR1 18 Timer 1 define DST IVECT SP1 17 Serial Port 1 define DST IVECT SP2 16 Serial port 2 define DST IVECT USB T5 I3 USB controller define DST IVECT INT3 15 I3 External INT3 pin define DST IVECT SPI 14 I2 SPI controller define DST IVECT I2C 14 I2 I2C controller define DST IVECT TNT 13 I1 External INT1 pin define DST IVECT MAC1 13 I1 Ethernet MAC1 define DST IVECT MACO 12 INTO Ethernet MACO define DST IVECT DMA1 11 DMA channel 1 define DST IVECT DMAO 10 DMA
136. rrupt service routine via the STI instruction for example the NMI currently in service does not affect the priority resolution of maskable interrupt requests For this reason the NMI interrupt service routine should not enable the maskable interrupts Breakpoint Interrupt Interrupt Type 03h An interrupt caused by the 1 byte version of the INT instruction INT3 INTO Detected Overflow Exception Interrupt Type 04h Generated by an INTO instruction if the OF bit is set in the Processor Status Flags F register Array BOUNDS Exception Interrupt Type 05h Generated by a BOUND instruction if the array index is outside the array bounds The array bounds are located in memory at a location indicated by one of the instruction operands The other operand indicates the value of the index to be checked Unused Opcode Exception Interrupt Type 06h Generated if execution is attempted on undefined opcodes ESC Opcode Exception Interrupt Type 07h Generated if execution of ESC opcodes D8h DFh is attempted DSTni does not check the escape opcode trap bit The return address of this exception points to the ESC instruction that caused the exception If a segment override prefix preceded the ESC instruction the return address points to the segment override prefix Note All numeric coprocessor opcodes cause a trap DSTni does not support the numeric coprocessor interface 12 Interrupt Acknowledge Interrupts can be acknowledged in two differ
137. t 14 5 111 Reserved 4 0 S 4 0 Highest Priority Interrupt Source Contain the encoded vector type of the highest priority interrupt source 29 End of Interrupt Register Table 2 45 End of Interrupt Register BIT 15 14 13 12 EN OFFSET 22h FIELD m 111 S4 S3 S2 S1 SO N RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R RW RW RW RW R R R R R R R RW wi VY 1 WW 1 W wi wy wy WN 1 VN 1 WW 1 VV Table 2 46 End of Interrupt Register Definitions Bits Field Name Description 15 SPC Type of EOI command 1 issue a non specific EOI command in S4 S0 0 issue a specific EOI command in S4 S0 default 14 5 Ill Reserved 4 0 S 4 0 Highest Priority Interrupt Source Contain the encoded vector type of the highest priority interrupt source 30 3 Miscellaneous Registers Table 3 1 Miscellaneous Register Summary Hex Mnemonic Register Description Page Offset AC COR Checksum Data register 2 A IT GNU R PLLCLK Phase Lock Loop Clock register S RNG Random Number Generator register 31 Checksum Adder Register Always write a value to the Checksum Data register to initialize it before using the Checksum Adder Register Note The Checksum Adder register is a single hardware resource that must be protected from being accessed simultaneously by multiple application threads Table 3 2 Checks
138. t FIFO depth to 4 bytes DST_SPXAUX_RTSZ 0x0010 Forcr RTS inactive DST_SPXAUX_RTS 0x0008 Force RTS active DST_SPXAUX_RXM 0x0004 Force receiver to half duplex DST_SPXAUX_CTSM 0x0002 Force CTS active internally DST_SPXAUX_RTSP 0x0001 Invert RTS polarity PICTRL Serial peripheral interface control DST_SPICTRL_IRQEN 0x0080 Enable interrupt DST_SPICTRL_AUTODRV 0x0040 Enable Autodrv DST_SPICTRL_INVCS 0x0020 Invert Chip Select DST_SPICTRL_PHASE_0 0x0000 Select Phase 0 DST_SPICTRL_PHASE_1 0x0010 Select Phase 1 DST_SPICTRL_CKPOL_HI 0x0008 Select high clock idle DST_SPICTRL_CKPOL_LO 0x0000 Select low clock idle DST_SPICTRL_WOR_EN 0x0004 Enable wire or operation DST_SPICTRL_MSTE 0x0002 Assert mastery of bus DST_SPICTRL_ALT 0x0001 Select alternate I O pinout PISTAT Serial peripheral interface status DST_SPISTAT_IRQ 0x0080 Interrupt has occurred DST_SPISTAT_OVERRUN 0x0040 Transmit overrun DST_SPISTAT_COL 0x0020 Collision between bus masters DST_SPISTAT_TXRUN 0x0002 Master mode operation in progress DST_SPISTAT_SLVSEL 0x0001 External master is active on bus PCB S define define define define define define define define define KK OK Ck Ck Ck Ck X X X ok Ck k X X X X ok o k o Xk Xk Xk Xk k k k ox ox guuuuuuutu O PD NU iS 01000 Ethernet Co
139. terrupt Priority Table 2 1 on page 7 shows DSTni s predefined interrupt types and default priority structure Nonmaskable interrupts interrupt types 0 7 always have a higher priority than maskable interrupts However maskable interrupts have a programmable priority that can override the default priorities relative to one another The levels of interrupt priority are Interrupt priority for nonmaskable interrupts and software interrupts Interrupt priority for maskable hardware interrupts Nonmaskable Interrupts and Software Interrupt Priority The nonmaskable interrupts from 00h to 07h and software interrupts INT instruction always take priority over the maskable hardware interrupts Within the nonmaskable and software interrupts the trace interrupt has the highest priority followed by the NMI interrupt and the remaining nonmaskable and software interrupts After the trace interrupt and the NMI interrupt the remaining software exceptions are mutually exclusive and can only occur one at a time obviating the need for a further priority breakdown Maskable Hardware Interrupt Priority Starting with interrupt type 8 timer 0 interrupt the maskable hardware interrupts have both a default priority see Table 2 1 on page 7 and a programmable priority The programmable priority is the primary priority for maskable hardware interrupts The overall priority is the secondary priority for maskable hardware interrupts Since all maskabl
140. the instruction register 0 breakpoint has been found 0 JTAG HALT JTAG HALT 1 target CPU is halted Hardware Breakpoints There are four hardware BREAKPOINT scan chains Each BREAKPOINT chain is identical to the DATA scan chain described above except with some additional features in the CTL field and an 8 bit COUNT field is added The hardware breakpoint chains can be used as four individual breakpoints or they can be used in pairs for specifying either address ranges or ina value mask pair The control byte is as follows Bits 3 0 of the control byte must match for the desired cycle to trigger If CTL 2 0 111 then the cycle type field is ignored and a trigger will occur on any type of cycle The hardware breakpoints can be used in pairs for masking or to specify ranges HW_BKPT 1 can be paired with HW PKPT 2 and HW_BKPT 3 can be paired with HW_BKPT 4 If HW BKPT 1 or 3 is programmed with CTL 7 6 00 the trigger condition in HW BKPT 1 must be met then HW BKPT 2 is enabled and must also be met before the processor is halted Only the ADDR is compared in this mode If HW BKPT 1 or 3 is programmed with CTL 7 6 01 the value on the ADDR DATA and STATUS busses are logically ANDed with value in HW BKPT 2 or 4 and the result is compared with value in HW BKPT 1 or 3 The CTL byte in HW BKPT 2 or 4 is ignored when used as a pair If HW BKPT 1 or 3 is programmed with a 10 the breakpoints are used
141. to work with the debugger 46 5 Packaging and Electrical This chapter describes the DSTni packaging and electrical characteristics Packaging The DSTni EX package is a 12 by 12 mm LFBGA with 0 8mm ball pitch The part has four thermal balls in the center to increase heat dissipation Die size is 4 1 x 5 4 mm in 0 18u TSMC process Figure 5 1 describes the package Figure 5 1 DSTni Package 1 50 1195 00000000000 900000000000 000000000000 NO 0O0O0mmorczarzzv o o o o o o o 123456789 11 13 Bottom View 10 12 14 U 80 pem 12 184 Ball Grid Array 47 Recommended Circuit Board Layout Figure 5 2 Recommended Circuit Board Layout 48 Recommended PCB Design Rules Component Land Pad Diameter 0 35 Solder Land L Diameter 0 33 Opening in Solder Mask M Diameter 0 44 Solder Ball Land Pitch e 0 80 Line Width en Via and Land w 0 13 Distance Between Via andLand D 0 56 Via Land VL Diameter 0 51 Through Hole VH Diameter 0 25 Pad ArrayMatrix or External Row 14 x 14 Periphery Rows 5 Note 3x3 matrix shown for illustration only one land pad shown with via connection The component land pad diameter refers to the pad opening on the component side solder mask defined The package has solder balls in the center in addition to periphery rows of balls Electrical Specifications Absolute Maximum Ratings Table 5 1 Absolute Maximum Ratings
142. trol Register Definitions Bits Field Name Description 15 4 MW Reserved 3 MSK Mask Interrupt 1 mask respective interrupt request default 0 enable respective interrupts 2 0 PR 2 0 Programmable Priority Level The programmable priority level for the respective interrupt source 111 lowest priority default 000 highest priority Serial Port 1 Interrupt Control Register Table 2 13 Serial Port 1 Interrupt Control Register BIT 12 11 10 OFFSET FIELD 17 Table 2 14 Serial Port 1 Interrupt Control Register Definitions Bits Field Name Description 15 4 W Reserved 3 MSK Mask Interrupt 1 mask respective interrupt request default 0 enable respective interrupts 2 0 PR 2 0 Programmable Priority Level The programmable priority level for the respective interrupt source 111 lowest priority default 000 highest priority Serial Port 2 Interrupt Control Register Table 2 15 Serial Port 2 Interrupt Control Register BIT 12 11 10 9 OFFSET FIELD x 0 1 R W 0 R W 0 R W W Table 2 16 Serial Port 2 Interrupt Control Register Definitions Bits Field Name Description 15 5 W Reserved 4 LTM Level Trigger Mode Sets the respective interrupt source 1 enable level triggered mode An interrupt generates when
143. uickly service the NMI request Programmers can also set this bit 14 3 W Reserved 2 0 IRT 2 0 Timer Interrupt Request Bits Lets software differentiate between timer interrupts as the TMR bit in the Interrupt Request register is the logical OR of all timer requests Setting any of these bits generates a timer interrupt request 24 Interrupt Request Register Table 2 33 Interrupt Request Register BIT OFFSET FIELD SP l6 D3 D2 13 12 11 lO D1 DO TMR 3 0 1 2 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R wi iwi wy WW W 1 WW 1 W 1 wy W wy wy wy wy w Table 2 34 Interrupt Request Register Definitions 5 a e ame Ue elite 15 Reserved 14 16 Logical OR Connected to Both CANO and CAN1 This bit is the in service bit for this interrupt source 13 12 D 3 0 Interrupt Request Bits for the DMA Channels DMA3 0 Setting any of these bits generates an interrupt request on the corresponding DMA channel interrupt request line Resetting any of these bits removes the interrupt request 11 8 SP 3 0 State of the Asynchronous Serial Port Interrupt Requests These bits are set when the respective serial port generates an interrupt request These bits clear when the respective interrupt acknowledge cycle occurs D3 0 In service bits for DMA channels DMA3 0 10 Logical OR connected to both internal
144. um Adder Register BIT OFFSET AEh FIELD DATA 7 0 DATA 15 8 Hia o o o o o o 0 0 mmm o o oO Oo RW R TRW TR T R T RW T RW TRW T RW T R T R T RT R TR TRT RIR W wiw W w w w w w wiw Table 3 3 Checksum Adder Register Definitions Field Name Description 15 0 DATA 15 0 Writing to this register adds the byte swapped data to the Checksum register with carry The data is byte swapped during this write This register is to be used with TCPIP checksum generation Reading this register shows the data in the adder Checksum Data Register Table 3 4 Checksum Data Register BIT OFFSET ACh FIELD DATA 15 0 Table 3 5 Checksum Data Register Definitions Field Name Description 15 0 DATA 15 0 Writing to this register sets the checksum value Typically this can be a starting value Reading this register shows its current value after any writes to the Checksum Adder register 32 LED Control Register The LEDs normally connect to four control outputs from the internal PHY To control the LEDs by software set SEN to 1 Note The reset value for this register 0000h is read as 000Dh because the LED signals initially are driven from the PHY Table 3 6 LED Control Register d U 9 O 6 d 7Eh Ill Alo Alo Alo A Ao A A Ao Ao A So LED3
145. x7F Live differential receiver 0x40 Single ended zero Target packet TX RX disabled Host executing USB token Generate USB reset Enable host mode Resume signalling Reset all BDT to even bank Enable USB Low speed enable Address in low 7 bits Perform out transaction 0x90 OxDO 0x80 0x40 0x10 0x08 0x04 0x02 0x01 Perform in transaction Perform setup Enable low speed w o hub Do not retry NAK d transact Disable control transfers Enable RX transfers enable TX transfers The endpoint is stalled Perform handshaking state generation for the DSTni EX creation Revision 1 00 101 This table maps the 16 possible wait state values to the correct bit pattern for the wait state portion of the DSTni EX chip select registers kk Note that bit position 2 is the Ignore Ready bit which is left cleared in this table 27 static U16 maul6WaitBits 16 0x0018 0x0019 0x001A 0x001B f 0x0010 0x0011 0x0012 0x0013 0x0008 0x0009 0x000A 0x000B 0x0000 0x0001 0x0002 0x0003 pt ve KEKE KKK KKK KKK KEKE KKK KKK KEKE KEK KEK KKK KKK KEKE KEKE KKK KKK KEKE ck ck ck ck ck o ck ck ck ck ck ck ck ko ko ko ko ko FUNCTION ul6CalcWaitStates U32 u32CpuSpeed U16 ul6DeviceNs duce ond ct By 0 7 El 95 Os Ley 35 14 15 7 NORO 1 ARGUMEN

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