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DE0-Nano-SoC User Manual 1 www.terasic.com August 31, 2015

1. 10 Ox 70 80 J AXI Slave EMAC Module EMACI Figure 6 3 GPIO address map B Software API Developers can use the following software API to access the register of GPIO controller open open memory mapped device driver mmap map physical memory to user space alt read word read a value from a specified register alt write word write a value into a specified register munmap clean up memory mapping close close device driver Developers can also use the following MACRO to access the register alt setbits word set specified bit value to one for a specified register alt clrbits word set specified bit value to zero for a specified register The program must include the following header files to use the above API to access the registers of GPIO controller include lt stdio h gt include lt unistd h gt include lt fcntl h gt DEO Nano SoC 57 www terasic com Tijasic User Manual August 31 2015 www terasic com include lt sys mman h gt include hwlib h include socal socal h include socal hps h include socal alt_gpio h B LED and KEY Control Figure 6 4 shows the HPS users LED and KEY pin assignment for the DEO NANO SoC board The LED is connected to HPS_GPIO53 and the KEY is connected 5 54 They are controlled by the controller which also controls HPS_GPIO29 HPS_GPIOS57 A20 HPS LED HPS GPIO53 HPS GPlIo54 218 HPS_K
2. August 31 2015 ANU UNIVERSITY PROGRAM GPIO O 28 GPIO O 29 GPIO 0 30 GPIO 0 31 GPIO 0 32 GPIO 0 33 GPIO O 34 GPIO 0 35 GPIO 1 0 GPIO 1 1 GPIO 1 2 GPIO 1 3 GPIO 1 4 GPIO 1 5 GPIO 1 6 GPIO 1 7 GPIO 1 8 GPIO 1 9 GPIO 1 10 GPIO 1 11 GPIO 1 12 GPIO 1 13 GPIO 1 14 GPIO 1 15 GPIO 1 16 GPIO 1 17 GPIO 1 18 GPIO 1 19 GPIO 1 20 GPIO 1 21 GPIO 1 22 GPIO 1 23 GPIO 1 24 GPIO 1 25 GPIO 1 26 GPIO 1 27 GPIO 1 28 GPIO 1 29 GPIO 1 30 GPIO 1 31 GPIO 1 32 GPIO 1 33 GPIO 1 34 GPIO 1 35 www terasic com PIN AD10 PIN AE9 PIN AD11 PIN AF10 PIN AD12 PIN AE11 PIN AF11 PIN AE12 PIN Y15 PIN AG28 PIN AA15 PIN AH27 PIN AG26 PIN AH24 PIN AF23 PIN AE22 PIN AF21 PIN AG20 PIN AG19 PIN AF20 PIN AC23 PIN AG18 PIN AH26 PIN AA19 PIN AG24 PIN AF25 PIN AH23 PIN AG23 PIN AE19 PIN AF18 PIN AD19 PIN AE20 PIN AE24 PIN AD20 PIN AF22 PIN AH22 PIN AH19 PIN 21 PIN AG21 PIN AH18 PIN AD23 PIN AE23 PIN AA18 PIN AC22 DEO Nano SoC User Manual GPIO Connection O 28 GPIO Connection 0 29 GPIO Connection 0 30 GPIO Connection 0 31 GPIO Connection 0 32 GPIO Connection 0 33 GPIO Connection 0 34 GPIO Connection 0 35 GPIO Connection 1 0 GPIO Connection 1 1 GPIO Connection 1 2 GPIO Connection 1 3 GPIO Connection 1 4 GPIO Connection 1 5 GPIO Connection 1 6 GPIO Connection 1 7 GPIO Connection 1 8 GPIO Connection 1
3. DATA 0 PIN A14 GMII and MII receive data 0 3 3V HPS ENET RX DATA 1 PIN A11 GMII and MII receive data 1 3 3V HPS ENET RX DATA 2 PIN C15 GMII and MII receive data 2 3 3V HPS ENET RX DATA 3 PIN A9 GMII and MII receive data 3 3 3V HPS RX CLK PIN J12 GMII and MII receive clock 3 3V HPS ENET RESET N PIN B14 Hardware Reset Signal 3 3V HPS ENET MDIO PIN E16 Management Data 3 3V HPS ENET MDC PIN A13 Management Data Clock Reference 3 3V HPS INT PIN B14 Interrupt Open Drain Output 3 3V HPS GTX PIN J15 GMII Transmit Clock 3 3V There are two LEDs green LED LEDG and yellow LED LEDY which represent the status of Ethernet PHY KSZ9031RN The LED control signals are connected to the LEDs on the RJ45 connector The state and definition of LEDG and LEDY are listed in Table 3 15 For instance the connection from board to Gigabit Ethernet 1s established once the LEDG lights on DEO Nano SoC 33 User Manual www August 31 2015 www terasic com Table 3 15 State and Definition of LED Mode Pins LED State LED Definition Link Activity LEDG LEDY LEDG LEDY H H OFF OFF Link off L H ON OFF 1000 Link No Activity Toggle H Blinking OFF 1000 Link Activity RX TX H L OFF ON 100 Link No Activity H Toggle OFF Blinking 100 Link Activity RX TX L L ON ON 10 Link No Activity Toggle Toggle Blinking Blinking 10 Link Activity RX TX 3 7 3 UART The board has one UART in
4. DEO Nano SoC 37 www terasic com User Manual August 31 2015 www terasic com 3 7 6 USB 2 0 OTG PHY The board provides USB interfaces using the SMSC USB3300 controller A SMSC USB3300 device in a 32 QEN package device 1 used to interface to a single Type Micro USB connector This device supports UTMI Low Pin Interface ULPI to communicate to USB 2 0 controller in HPS As defined by OTG mode the PHY can operate in Host or Device modes When operating in Host mode the interface will supply the power to the device through the Micro USB interface Figure 3 24 shows the connections of USB PTG PHY to the HPS Table 3 19 lists the pin assignment of USB OTG PHY to the HPS NOS RYAN Cyclone SoC HPS Signal Name HPS USB CLKOUT HPS USB DATA 0 HPS USB DATA 1 HPS USB 2 HPS USB DATA 3 HPS USB DATA 4 HPS USB DATA 5 HPS USB DATA 6 HPS USB DATA 7 HPS USB DIR HPS USB NXT HPS USB RESET HPS USB STP DEO Nano SoC User Manual www terasic com HPS USB DATA T 0 HPS USB CLKOUT HPS USB NXT HPS USB DIR HPS USB STP CLK USB 24 U31 _ HPS RESET N TPS3831 FPGA Pin No PIN G4 PIN C10 PIN F5 PIN C9 PIN C4 PIN C8 PIN D4 PIN C7 PIN F4 PIN E5 PIN D5 PIN H12 PIN C5 DATA 7 0 CPEN CLKOUT 5 NXT VBUS Table 3 19 Pin Assignment of USB OTG PHY Description 60MHz Reference Clock Output HPS USB DATA O HPS USB DATA 1 HPS USB
5. DEO Nano Soc USER MANUAL S THER HERNE T E a t Sd k a UNIVERSITY www PROGRAM Copyright 2003 2015 Terasic Inc All Rights Reserved CONTENTS racc c occa c Chapter 1 DEO Nano SoC Development 4 Jl T O Ka EC OMI NUS 5 L2 EOIN AO uuu uuu l 5 oe o 6 2 Introduction of the DEO Nano SoC Board T L Layo and lt ONION MIS u uuu u uu 7 2 2 Block Diagram of the DE0 Nano SoC Board 9 Chapter 3 Using the DEO Nano SoC 12 3 1 Settings of FPGA Configuration Mode 12 3 2 Configuration of Cyclone SoC FPGA on DE0 Nano SoC 13 3 3 Board Status Elements uuu uu uu uasaasesasaqasoqaskussesasasassasaqsssasasqaaseqaskasasqsqasayssastassctasqssssqasqska 19 E T 20 SE ies BART T UTE 21 3 6 Peripherals Connected to the FPGA 22 3 6 1 User Push buttons Switches
6. 1011 Arduino Reset IE GND VCC5 ADC_INO INT 3 ADC_IN2 ADC_IN3 5 ADC_IN4 ADC IN5 IN6 IN7 5 io GND Figure 3 20 Connections between the FPGA 2x5 header and the A D converter Table 3 12 Pin Assignment of ADC Signal Name FPGA Pin No Description 0 Standard ADC CONVST Conversion Start 3 3V PIN_AC4 Serial Data Input FPGA to ADC PIN_AD4 Serial Data Out ADC to FPGA PNU PIN V10 Serial Data Clock DEO Nano SoC 31 www terasic com Tijasic User Manual August 31 2015 www terasic com 3 7 Peripherals Connected to Hard Processor System HPS This section introduces the interfaces connected to the HPS section of the Cyclone V SoC FPGA Users can access these interfaces via the HPS processor 3 7 1 User Push buttons and LEDs similar to the FPGA the HPS also has its set of switches buttons LEDs and other interfaces connected exclusively Users can control these interfaces to monitor the status of HPS Table 3 13 gives the pin assignment of all the LEDs switches and push buttons Table 3 13 Pin Assignment of LEDs Switches and Push buttons FPGA Pin No HPS Register bit PIN J18 GPIO54 GPIO1 25 PIN A20 GPIO53 GPIO1 24 Signal Name Function 3 7 2 Gigabit Ethernet The board supports Gigab
7. SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class www terasic com August 31 2015 UNIVERSITY PROGRAM HPS DDRS3 DN 3 PIN AB28 HPS DDR3 Data Mask 3 SSTL 15 Class HPS DDR3 PIN J25 HPS DDR3 Data 0 SSTL 15 Class HPS DDR3_DQ 1 PIN J24 HPS DDR3 Data 1 SSTL 15 Class HPS DDR3_ DQ 2 PIN E28 HPS DDR3 Data 2 SSTL 15 Class HPS DDR3 DQ 3 PIN D27 HPS DDR3 Data 3 SSTL 15 Class HPS DDR3 DQ 4 PIN J26 HPS DDR3 Data 4 SSTL 15 Class HPS DDR3 DQ 5 PIN K26 HPS DDR3 Data 5 SSTL 15 Class HPS DDR3 DQ 6 PIN G27 HPS DDR3 Data 6 SSTL 15 Class HPS DDR3 PIN F28 HPS DDR3 Data 7 SSTL 15 Class HPS DDR3_DQJ 8 PIN K25 HPS DDR3 Data 8 SSTL 15 Class HPS DDR3 DQ 9 PIN L25 HPS DDR3 Data 9 SSTL 15 Class HPS DDR3 DQ 10 PIN J27 HPS DDR3 Data 10 SSTL 15 Class HPS DDR3 DQ 11 PIN J28 HPS DDR3 Data 11 SSTL 15 Class HPS DDR3 DQ 12 PIN M27 HPS DDR3 Data 12 SSTL 15 Class HPS DDR3 DQ 13 PIN M26 HPS DDR3 Data 13 SSTL 15 Class HPS DDR3 DQ 14 PIN M28 HPS DDR3 Data 14 SSTL 15 Class HPS DDR3 DQ 15 PIN N28 HPS DDR3 Data 15 SSTL 15 Class HPS DDR3 DQ 16 PIN N
8. Signal Name HPS DDR3 A 0 HPS DDR3 A 1 HPS DDR3 A 2 HPS DDR3 A 3 HPS DDR3 A 4 HPS DDR3 A 5 HPS DDR3 A 6 HPS DDR3 7 HPS DDR3_A 8 HPS DDR3_A 9 HPS DDR3_A 10 HPS DDR3 A 11 HPS DDR3 A 12 HPS DDR3 A 13 HPS DDR3 A 14 HPS DDR3 0 HPS DDR3 BA 1 HPS DDR3 BA 2 HPS DDR3 CAS n HPS DDR3 CKE HPS DDR3 CK n HPS DDR3 CK p HPS DDR3 CS n HPS DDR3 DM 0 HPS DDR3_DM 1 HPS DDR3_DM 2 www terasic com Table 3 17 Pin Assignment of DDR3 Memory FPGA Pin No PIN C28 PIN B28 PIN E26 PIN D26 PIN J21 PIN J20 PIN C26 PIN B26 PIN F26 PIN F25 PIN A24 PIN B24 PIN D24 PIN C24 PIN G23 PIN A27 PIN H25 PIN G25 PIN A26 PIN L28 PIN N20 PIN N21 PIN 121 PIN G28 PIN P28 PIN W28 DEO Nano SoC User Manual Description HPS DDR3 Address 0 HPS DDR3 Address 1 HPS DDR3 Address 2 HPS DDR3 Address 3 HPS DDR3 Address 4 HPS DDR3 Address 5 HPS DDR3 Address 6 HPS DDR3 Address 7 HPS DDR3 Address 8 HPS DDR3 Address 9 HPS DDR3 Address 10 HPS DDR3 Address 11 HPS DDR3 Address 12 HPS DDR3 Address 13 HPS DDR3 Address 14 HPS DDR3 Bank Address 0 HPS DDR3 Bank Address 1 HPS DDR3 Bank Address 2 DDR3 Column Address Strobe HPS DDR3 Clock Enable HPS DDR3 Clock HPS DDR3 Clock p HPS DDR3 Chip Select HPS DDR3 Data Mask 0 HPS DDR3 Data Mask 1 HPS DDR3 Data Mask 2 35 Standard SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class
9. DEO Nano SoC 13 User Manual www teraSic com August 31 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM JTAG programming It is named after the IEEE standards Joint Test Action Group The configuration bit stream is downloaded directly into the Cyclone V SoC FPGA The FPGA will retain its current status as long as the power keeps applying to the board the configuration information will be lost when the power is off 2 AS programming The other programming method is Active Serial configuration The configuration bit stream is downloaded into the serial configuration device EPCS128 which provides non volatile storage for the bit stream The information is retained within EPCS 128 even if the DEO Nano SoC board is turned off When the board is powered on the configuration data in the EPCS128 device is automatically loaded into the Cyclone V SoC FPGA B JTAG Chain on DEO Nano SoC Board The FPGA device can be configured through JTAG interface on DEO Nano SoC board but the JTAG chain must form a closed loop which allows Quartus II programmer to the detect FPGA device Figure 3 2 illustrates the JTAG chain on DEO Nano SoC board HPS TDO ANU S RAN reca lt A FPGA TDO qu As USB Figure 3 2 Path of the JTAG chain B Configure the FPGA in JTAG Mode There are two devices FPGA and HP5 on the JTAG chain The following s
10. Table 3 6 Pin Assignment of Slide Switches O Standard 3 3V 3 3V 3 3V 3 3V O Standard 3 3V 3 3V Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V Signal Name FPGA Pin No Description PIN 110 Slide Switch 0 SW 1 PIN L9 Slide Switch 1 SW 2 PIN_H6 Slide Switch 2 SW S PIN H5 Slide Switch 3 Table 3 7 Pin Assignment of Push buttons Signal Name FPGA Pin No Description KEY 0 PIN AH17 Push button 0 KEY 1 PIN AH16 Push button 1 Table 3 8 Pin Assignment of LEDs Signal Name FPGA Pin No Description LED 0 PIN W15 LED 0 LED 1 PIN AA24 LED 1 LED 2 PIN V16 LED 2 LED 3 PIN V15 LED 3 LED 4 PIN AF26 LED 4 LED 5 PIN AE26 LED 5 LED 6 PIN Y16 LED 6 LED 7 PIN_AA23 LED 7 DEO Nano SoC 25 User Manual www terasic com 3 3V www August 31 2015 3 6 2 2x20 GPIO Expansion Headers The board has two 40 pin expansion headers Each header has 36 user pins connected directly to the Cyclone V SoC FPGA It also comes with DC 5V VCC5 DC 3 3V VCC3P3 and two GND pins The maximum power consumption allowed for a daughter card connected to one or two GPIO ports is shown in Table 3 9 Supplied Voltage 5V 3 3V Signal Name GPIO O 0 GPIO O 1 GPIO O 2 0 3 GPIO O 4 GPIO O 5 GPIO O 6 0 7 GPIO O 8 GPIO O 9 GPIO 0 10 0 11 GPIO 0 12 GPIO 0 13 GPIO 0 14 GPIO 0 15 GPIO O 16 0 17
11. Data Strobe p 2 Differential 1 5 V SSTL Class HPS DDR3 DQS 3 PIN U19 HPS DDR3 Data Strobe p 3 Differential 1 5 V SSTL Class HPS DDR3 ODT PIN D28 HPS DDR3 On die Termination SSTL 15 Class HPS DDR3 RAS n PIN A25 DDR3 Row Address Strobe SSTL 15 Class HPS DDR3 RESET n PIN V28 HPS DDR3 Reset SSTL 15 Class Nano 36 User Manual hugust 31 2016 www terasic com ANU RA UNIVERSITY PROGRAM HPS DDR3 WE PIN E25 HPS DDR3 Write Enable SSTL 15 Class HPS DDR3 RZQ PIN D25 External reference ball for 1 5 V output drive calibration 3 7 5 Micro SD Card Socket The board supports Micro SD card interface with x4 data lines It serves not only an external storage for the HPS but also an alternative boot option for DEO Nano0 SoC board Figure 3 23 shows signals connected between the HPS and Micro SD card socket Table 3 1 lists the pin assignment of Micro SD card socket to the HPS SD CLK 5 SD CMD 3 SoC T d tt Figure 3 23 Connections between the FPGA and SD card socket Table 3 18 Pin Assignment of Micro SD Card Socket Signal Name FPGA Pin No Description Standard HPS SD CLK PIN B8 HPS SD Clock mE 3 3V HPS SD PIN D14 HPS SD Command Line 3 3V HPS SD DATA O PIN C13 HPS SD Data 0 3 3V HPS SD DATA 1 PIN B6 HPS SD Data 1 3 3V HPS SD DATA 2 PIN B11 HPS SD Data 2 3 3V HPS SD DATAT 3 PIN B9 HPS SD Data 3 3 3V
12. HPS GSENSOR INT PIN A17 HPS GSENSOR Interrupt Output 3 3V HPS 2 0 SCLK PIN C18 HPS 12 0 Clock 3 3V HPS 12 SDAT PIN A19 HPS 12 0 Data 3 3V 3 7 8 LTC Connector The board has a 14 pin header which 1s originally used to communicate with various daughter cards from Linear Technology It is connected to the SPI Master and I2C ports of HPS The communication with these two protocols is bi directional The 14 pin header can also be used for GPIO SPI or I2C based communication with the HPS Connections between the HPS and LTC DEO Nano SoC 39 www terasic com User Manual August 31 2015 www terasic com connector are shown in Figure 3 26 and the pin assignment of LTC connector is listed in Table 3 21 VCC9 VCC3P3 HPS SPIM HPS SPIM SS NO S HPS SPIM MOSI CycloneE HPS SPIM MISO VCC3P3 HPS I2C1 SDAT HPS I2C1 SCLK 0 ohm HPS HPS LTC GPIO T U2 GN HPS_SPIM_MOSI HPS I2C1 SDAT MOSI SDA HPS SPIM CLK HPS I2C1 SCLK HPS LTC GPIO 4 TS3A5018 Figure 3 26 Connections between the HPS and LTC connector Table 3 21 Pin Assignment of LTC Connector HPS_LTC_GPIO PINHI3 HPS LTC GPIO HPS I2C1 SCLK PIN B21 HPSI2CI Clock HPS I2C1 SDAT PIN A21 HPSI2CI Data SPI Clock SPI Master Input Slave Output SPI Master Output Slave Input HPS_SPIM_SS PIN_C16 SPI Slave Select Standard DEO Nano SoC 40 www terasic c
13. HPS NPOR KEY 4 DEV_CLRN HPS ENET_RESET N GPIO43 HPS RST GPIO42 10 100 1000 Base T Ethernet PHY RSZ9031RN RESET_N USB 2 0 OTG PHY 0583300 RESET HPS RESET PHY Inverter Figure 3 12 HPS reset tree on DEO Nano SoC board 3 5 Clock Circuitry Figure 3 13 shows the default frequency of all external clocks to the Cyclone V SoC FPGA A clock generator is used to distribute clock signals with low jitter The two 50MHz clock signals connected to the FPGA are used as clock sources for user logic Three 25MHz clock signal are connected to two HPS clock inputs and the other one 1s connected to the clock input of Gigabit Ethernet Transceiver One 24M Hz clock signal is connected to the USB controller for USB Blaster II circuit and FPGA One 24MHz clock signals are connected to the clock inputs of USB PHY The associated pin assignment for clock inputs to FPGA I O pins is listed in Table 3 5 DEO Nano SoC 21 www terasic com Tijasic User Manual August 31 2015 www terasic com CDCE937 ANU S FPGA CLK1 50 50MHz FPGA CLK2 50 50MHz crx FPGA CLK3 50 50MHz HPS CLK1 25 25MHz CLK4P HPS CLK2 25 25MHz E 2 USB Blaster CLK UB2 24 24MHz Gigabit Ethernet CLK_ENET_25 25MHz nm CLK USB 24 24MHz X USB OTG PHY Figure 3 13 Block diagram of the clock distribution on DEO Nano SoC Table 3 5 Pin Assignmen
14. a 2x5 header as shown in Figure 3 19 DEO Nano SoC 20 www terasic com User Manual August 31 2015 www terasic com zl 5065 t PESE B 808885 VCC5 ADC INO T or m ADC_IN1 ADC_IN2 A 3 IN3 ADC_IN4 ADC IN5 ADC IN6 ADC IN7 GND Figure 3 19 Signals of the 2x5 Header These Analog inputs are shared with the Arduino s analog input pin INO ADC_INS Figure 3 20 shows the connections between the FPGA 2x5 header Arduino Analog input and the A D converter More information about the A D converter chip is available in its datasheet It can be found on manufacturer s website or in the directory Datasheet ADC of DEO Nano SoC system CD DEO Nano SoC 30 www terasic com Tijasic User Manual August 31 2015 www terasic com Analog Vref GND Arduino 1013 Arduino 1012 Arduino 1011 Arduino 1010 Arduino 109 Arduino 108 NC IOREF Arduino Reset n VCC3P3 VCC5 GND GND VCC9 Arduino Arduino 107 106 Arduino 105 CONVST INO INO Arduino 104 lt ADC_IN1 ADC IN1 _ 4 ADC IN2 1 3 ADC IN2 Arduino_lO2 ADC_SDO lt ADC_IN4 ADC_IN3 IN5 ADC SDI IN6 imis le Arduino OO lt IN7 neces Arduino 1012 i P of dPoote ee 5 LTC2308 Arduino 1 1 5 1 1 i 2
15. and Figure 2 2 shows a photograph of the board It depicts the layout of the board and indicates the location of the connectors and key components FPGA FPGA Configuration HPS Mode Switch 2X20 GPIO FPGA LTC 2x7 Header System a 9 i LJ a r c Arduino Header USB PHY USB 5V DC i USB Micro AB Power Jack C HPS DDR3 Altera 28 nm 2 mu LS E oe BEER UART to USB Cyclone V FPGA Y 4 XN USB with ARM Cortex A9 re sent SIT UART to USB USB Blaster 11 WI E i IT A Controller tI G Sensor USB HM ER OC c Ethernet PHY HPS Gigabit Ethernet WARM RST HPS User Button HPS RST LED x8 dessas Clock Generator MAX Slide Switch x4 2x5 ADC Header Button x2 Pd 2x20 GPIO FPGA HPS User LED Figure 2 1 DEO Nano SoC development board top view DEO Nano SoC 7 www terasic com Tijasic User Manual August 31 2015 www terasic com i 14120023 72 AIL E E E M 0 E M M D Geaa SIE A IESE qe 20077 e paw SES ces adis ii MicroSD Card Socket f 3 Ete Figure 2 2 DEO Nano SoC development board bottom view The DEO Nano SoC board has many features that al
16. and LEDSs 23 30 2 2x20 GPIO Expansion He Ue ES Tee 26 3 6 3 Arduino Uno Expansion Header 28 3 6 4 A D Converter and Analog Input 20 3 7 Peripherals Connected to Hard Processor System HPS 32 adr User Pusnsbuttons amd LEDS mata 32 Dade EE A 32 SW E E 34 2 7205 DDOR MINON an 35 DEO Nano SoC 1 www terasic com User Manual August 31 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM SMS SDD Cand SOC x ee T Um mc 37 SE 0 38 TE om 39 SN 39 Chapter 4 DEO Nano SoC System Builder 41 d MAO 0 oos ee gas es trovate dM dE E 4 il AT T HU 4 4 3 Using DEO Nano SoC System Builder 42 Chapter5 Examples For FPGOA 48 5 1 DE0 Nano SoC Factory 48 3 2
17. gnueabihf FLAGS g Uall I SOCEDS DEST ROOT ip altera hps altera hps hwlib include DFLAGS g Wall CROSS COMPILE ARCH arm build TARGET TARGET main o LDFLAacs o 8 tD k c n CC CFLAGS e lt o 38 PHONY clean clean rm TARGET 4 B Compile Please launch Altera SoC EDS Command Shell to compile a project by executing C altera 14 0 embedded Embedded_Command_Shell bat The cd command can change the current directory to where the Hello World project is located asic DEO Nano SoC 53 www terasic com tert User Manual August 31 2015 UNIVERSITY PROGRAM The make command will build the project The executable file my first hps will be generated after the compiling process 15 successful The clean all command removes all temporary files B Demonstration Source Code e Build tool Altera SoC EDS 14 0 e Project directory Demonstration SoC my_first_hps e Binary file first hps e Build command make make clean to remove all temporary files e Execute command my first hps B Demonstration Setup e Connect a USB cable to the USB to UART connector J4 on the DEO Nano SoC board and the host PC e Copy the demo file my first hps into a microSD card under the home root folder in Linux e Insert the booting microSD card into the DEO Nano SoC board e Power on the DEO Nano SoC board e Launch PuTTY and
18. 1 MSELO ON 0 SW10 2 MSEL1 Use th ned tthe OFF 1 SW10 3 MSEL2 A ON 0 Configuration scheme SW10 4 MSEL3 OFF 1 SW10 5 MSEL4 ON 0 SW10 6 N A N A N A Table 3 2 shows MSEL 4 0 setting for FPGA configure and default setting is FPPx32 mode on DEO Nano SoC When the board is powered and MSEL 4 0 set to 10010 the FPGA is configured from EPCS which is pre programmed with the default code If developers wish to configure FPGA from an application software running on Linux the MSEL 4 0 needs to be set to 01010 before the programming process begins If developers using the Linux Console with frame buffer or Linux LXDE Desktop SD Card image the MSEL 4 0 needs to be set to 00000 before the board is powered on Table 3 2 MSEL Pin Settings for FPGA Configure of DEO Nano SoC SW10 1 SW10 2 SW10 3 SW10 4 SW10 5 SW10 6 u Configuration Description MSELO MSEL1 MSEL2 MSEL3 MSEL4 AS ON OFF ON ON OFF FPGA configured from EPCS FPGA configured from HPS software Linux default FPGA configured from HPS software U Boot with image stored on the SD card like LXDE Desktop or console Linux with frame buffer edition FPPx32 Default ON OFF ON OFF ON N A FPPx16 ON ON ON ON ON N A 3 2 Configuration of Cyclone V SoC FPGA on DEO Nano SoC There are two types of programming method supported by DEO Nano SoC
19. 24 HPS DDR3 Data 16 SSTL 15 Class HPS DDR3 DQ 17 PIN N25 HPS DDR3 Data 17 SSTL 15 Class HPS DDR3 DQ 18 PIN T28 HPS DDR3 Data 18 SSTL 15 Class HPS DDR3 DQ 19 PIN U28 HPS DDR3 Data 19 SSTL 15 Class HPS DDR3 DQ 20 PIN N26 HPS DDR3 Data 20 SSTL 15 Class HPS DDR3 DQ 21 PIN N27 HPS DDR3 Data 21 SSTL 15 Class HPS DDR3 DQ 22 PIN R27 HPS DDR3 Data 22 SSTL 15 Class HPS DDR3 DQ 23 PIN V27 HPS DDR3 Data 23 SSTL 15 Class HPS DDR3 DQ 24 PIN R26 HPS DDR3 Data 24 SSTL 15 Class HPS DDR3 DQ 25 PIN R25 HPS DDR3 Data 25 SSTL 15 Class HPS DDR3 DQ 26 PIN AA28 HPS DDR3 Data 26 SSTL 15 Class HPS DDR3 DQ 27 PIN W26 HPS DDR3 Data 27 SSTL 15 Class HPS DDR3 DQ 28 PIN R24 HPS DDR3 Data 28 SSTL 15 Class HPS DDR3 DQ 29 PIN T24 HPS DDR3 Data 29 SSTL 15 Class HPS DDR3 DQ 30 PIN Y27 HPS DDR3 Data 30 SSTL 15 Class HPS DDR3 DQ 31 PIN AA27 HPS DDR3 Data 31 SSTL 15 Class HPS DDR3_DQS n 0 PIN 16 HPS DDR3 Data Strobe n 0 Differential 1 5 V SSTL Class HPS DDRS3 DQS n 1 PIN R18 HPS DDR3 Data Strobe n 1 Differential 1 5 V SSTL Class HPS DDR3 DQS 2 PIN T18 HPS DDR3 Data Strobe n 2 Differential 1 5 V SSTL Class HPS DDR3 DQS n 3 PIN T20 HPS DDR3 Data Strobe n 3 Differential 1 5 V SSTL Class HPS DDRS3 DQS p 0 PIN R17 HPS DDR3 Data Strobe p 0 Differential 1 5 V SSTL Class HPS DDR3 DQS p 1 PIN R19 HPS DDR3 Data Strobe p 1 Differential 1 5 V SSTL Class HPS DDRS3 DQS p 2 PIN T19 HPS DDR3
20. 9 GPIO Connection 1 10 GPIO Connection 1 11 GPIO Connection 1 12 GPIO Connection 1 13 GPIO Connection 1 14 GPIO Connection 1 15 GPIO Connection 1 16 GPIO Connection 1 17 GPIO Connection 1 18 GPIO Connection 1 19 GPIO Connection 1 20 GPIO Connection 1 21 GPIO Connection 1 22 GPIO Connection 1 23 GPIO Connection 1 24 GPIO Connection 1 25 GPIO Connection 1 26 GPIO Connection 1 27 GPIO Connection 1 28 GPIO Connection 1 29 GPIO Connection 1 30 GPIO Connection 1 31 GPIO Connection 1 32 GPIO Connection 1 33 GPIO Connection 1 34 GPIO Connection 1 35 21 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www August 31 2015 ANU S RYA UNIVERSITY PROGRAM 3 6 3 Arduino Uno R3 Expansion Header The board provides Arduino Uno revision 3 compatibility expansion header which comes with four independent headers The expansion header has 17 user pins 16pins and I pin Reset connected directly to the Cyclone V SoC FPGA 6 pins Analog input connects to ADC and also provides DC 9V VCC9 DC 5 VCC5 DC 3 3V VCC3P3 and IOREF and three GND pins Please refer to Figure 3 18 for detailed pin out information The blue font represents the Arduino Uno R3 board pin
21. D TXD illuminate when data is transferred from FT232R to USB Host RXD UART RXD when data is transferred from USB Host to FT232R 3 4 Board Reset Elements There are two HPS reset buttons on DEO Nano SoC HPS cold reset and HPS warm reset as shown in Figure 3 11 Table 3 4 describes the purpose of these two HPS reset buttons Figure 3 12 is the reset tree for DEO Nano SoC _ m p p pu pos 1 fe 5 AL gt 9 SVAOC pras pans 9 USB BLASTER TI GPIO 1 J VUspPT AZAgTF0TITPa Fw B 5 RST 5 Figure 3 11 HPS cold reset and warm reset buttons on DEO Nano SoC Table 3 4 Description of Two HPS Reset Buttons DE0 Nano SoC Board Reference Signal Cold reset to the HPS Ethernet PHY and USB host device KEYA HPS RESET N HPSRESETN 90 low input which resets all HPS logics that can be reset Active low i ff h KEY3 HPS WARM RST N arm reset to the is block Active low input affects the system reset domain for debug purpose DEO Nano SoC 20 www terasic com Tijasic User Manual August 31 2015 www terasic com VCC3P3 Cyclone V SoC KEY HPS FPGA Am HPS WARM RST N Sra gt 5 5 WARM_RST HPS RESET
22. DATA 2 HPS USB DATA 3 HPS USB DATA 4 HPS USB DATA 5 HPS USB DATA 6 HPS USB DATA 7 Direction of the Data Bus Throttle the Data HPS USB PHY Reset Stop Data Stream on the Bus 38 U7 USB VCC5 OUT FAULT_N TPS2553DRVR USB_EXTVBUS USB Micro AB Connector Figure 3 24 Connections between the HPS and USB OTG PHY Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www August 31 2015 3 7 7 G sensor The board comes with a digital accelerometer sensor module ADXL345 commonly known as G sensor This G sensor is a small thin ultralow power assumption 3 axis accelerometer with high resolution measurement Digitalized output 15 formatted as 16 bit two s complement and can be accessed through I2C interface The I2C address of G sensor is 7 More information about this chip can be found in its datasheet which is available on manufacturer s website or in the directory Datasheet G Sensor folder of DEO Nano SoC system CD Figure 3 25 shows the connections between the HPS and G sensor Table 3 20 lists the pin assignment of G senor to the HPS U19 HPS I2CO0 SCLK gt SCLK gt enn SDI SDIO SoC HPS GSENSOR INT INITA HPS ADXL345 Figure 3 25 Connections between Cyclone V SoC FPGA and G Sensor Table 3 20 Pin Assignment of G senor Signal Name FPGA Pin No Description Standard
23. DC 49 Chapter 6 Examples for HPS SOC 52 Ill T O iu uuu gee ic Deere 27 LED G u UU E 54 60 Chapter 7 Examples for using both HPS SoC and 64 ES Wim 64 Chapter 8 Programming the EPCS Device 68 5 1 Before Programming uuu bn PPP IER Pam HF das opi ese DU 68 SA Boo Bind NOM gill uu u uu u 69 5 2 Write JIC File the EPCS 73 aS ou cs 74 8 5 Nios II Boot from EPCS Device in Quartus II v14 1 76 Chapter9 Appendix uu u UU asa arrainen naia 78 AN TCV ISI Ue E o 78 DEO Nano SoC 2 www terasic com User Manual August 31 2015 www terasic com ANU RAN UNIVERSITY PROGRAM 9 2 Copyright Statement DEO Nano SoC 3 www terasic com User Manual August 31 2015 Chapter 1 DEO Nano SoC Development kit The DEO Nano SoC Development Kit presents a robust hardware design platform built around the Altera System on Chip SoC FPGA which com
24. DC IN2 ADC IN3 ADC_IN4 ADC_IN5 IN6 ADC IN7 GND Figure 5 3 Pin distribution of the 2x5 Header for the ADC DEO Nano SoC 50 www terasic com User Manual August 31 2015 www terasic com B System Requirements The following items are required for this demonstration e DEO Nano SoC board x1 e Trimmer Potentiometer x1 e Wire Strip x3 B Demonstration File Locations e Hardware project directory DEO SOC ADC e Bitstream used DEO SOC ADC sof e Software project directory DEO SOC ADC software e Demo batch file DEO SOC ADC Memo batch DEO SOC ADC bat B Demonstration Setup and Instructions e Connect the trimmer to corresponding ADC channel on the 2x5 header as shown in Figure 5 4 as well as the 5V and GND signals The setup shown above is connected ADC channel 0 e Execute the demo batch file DEO SOC ADcC bat to load the bitstream and software execution file to the FPGA e The Nios II console will display the voltage of the specified channel voltage result information Figure 5 4 Hardware setup for the ADC reading demonstration DEO Nano SoC 51 www terasic com Tijasic User Manual August 31 2015 www terasic com Chapter 6 Examples for HPS SoC This chapter provides several C code examples based on the Altera SoC Linux built by Yocto project These examples demonstrate major features of peripherals connected to HPS interface on DEO Nano
25. EY Figure 6 4 Pin assignment of LED and KEY Figure 6 5 shows the gpio swporta ddr register of the controller The 61 0 controls the pin direction of HPS_GPIO29 The bit 24 controls the pin direction of HPS_GPIO53 which connects to HPS_LED the bit 25 controls the pin direction of HPS_GPIO54 which connects to HPS_KEY and so on The pin direction of HPS_LED and HPS_KEY are controlled by the bit 24 and bit 25 in the gpio_swporta_ddr register of the GPIOI controller respectively Similarly the output status of HPS_LED is controlled by the bit 24 in the gpio_swporta_dr register of the GPIOI controller The status of KEY can be queried by reading the value of bit 24 in the ext porta register of GPIOI controller GPIO1 Controller gpio swporta ddr register Controls the Direction of HPS GPIO29 Controls the Direction of HPS GPIO30 Controls the Direction of HPS GPIO31 Controls the Direction of GPIOSS3 HPS LED Controls the Direction of HPS GPIOS54 HPS KEY Controls the Direction of HPS_GPIO55 Controls the Direction of HPS_GPIO56 Controls the Direction of HPS GPIO57 Figure 6 5 gpio swporta ddr register in the GPIO1 controller DEO Nano SoC 58 www terasic com Tijasic User Manual August 31 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM The following mask is defined in the demo code to control LED and KEY direction and LED s output value define USER IO DIR 0x01000000 de
26. GPIO O 18 GPIO 0 19 GPIO 0 20 GPIO 0 21 GPIO 0 22 GPIO 0 23 GPIO O 24 GPIO 0 25 GPIO O 26 GPIO 0 27 www terasic com Max Current Limit Table 3 9 Voltage and Max Current Limit of Expansion Header s 1A depend on the power adapter specification 1 5A Table 3 10 Pin Assignment of Expansion Headers Standard FPGA Pin No PIN V12 PIN AF7 PIN W12 PIN AF8 PIN Y8 PIN ABA PIN W8 PIN Y4 PIN Y5 PIN U11 PIN T8 PIN T12 PIN AH5 PIN AH6 PIN 4 PIN AG5 PIN AH3 PIN AH2 PIN 4 PIN AG6 PIN AF5 PIN AE4 PIN T13 PIN T11 PIN AE7 PIN AF6 PIN AF9 PIN AE8 DEO Nano SoC User Manual Description GPIO Connection O 0 GPIO Connection O 1 GPIO Connection O 2 GPIO Connection O 3 GPIO Connection O 4 GPIO Connection O 5 GPIO Connection O 6 GPIO Connection 0 7 GPIO Connection O 8 GPIO Connection O 9 GPIO Connection 0 10 GPIO Connection 0 11 GPIO Connection 0 12 GPIO Connection 0 13 GPIO Connection 0 14 GPIO Connection 0 15 GPIO Connection 0 16 GPIO Connection 0 17 GPIO Connection O 18 GPIO Connection 0 19 GPIO Connection O 20 GPIO Connection 0 21 GPIO Connection 0 22 GPIO Connection 0 23 GPIO Connection O 24 GPIO Connection O 25 GPIO Connection O 26 GPIO Connection 0 27 26 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www
27. N UNIVERSITY PROGRAM DEO Nano SoC V1 0 0 ATERA System Configuration UNIVERSITVI OM das c Project Name PROGRAM DEO NANO SOC DEO Nano SoC FPGA Board Ex EB CLOCK 8 Button x 2 Switch x 4 4 ADC 2x5 Header Arduino Header O HPS GPIO 0 Header 5 5M Pixel Camera X Prefix Name GPIO 1 Header None X Prefix Name Figure 4 5 GPIO expansion group The Prefix Name is an optional feature that denote the pin name of the daughter card assigned in your design Users may leave this field blank B Project Setting Management The DEO Nano SoC System Builder also provides the option to load a setting or save users current board configuration in cfg file as shown in Figure 4 6 DEO Nano SoC 46 www terasic com Tijasic User Manual August 31 2015 www terasic com UNIVERSITY PROGRAM DEO Nano SoC V1 0 0 Sm SYA System Confiquration p ea Li om Project Name DEO_NANO_SOC DEO Nano SoC FPGA Board was CLOCK vl LEDx8 Button x 2 Switch x 4 ADC 2 5 Header Arduino Header HPS GPIO 0 Header None X Prefix Name GPIO 1 Header Prefix Name Load Setting Exit Figure 4 6 Project Settings B Project Generation When users press the Generate button the DEO Nano SoC System Builder will generate the corresponding Quartus II files and documents as listed in Table 4 1 Table 4 1 Files ge
28. Nano SoC 9 www terasic com www terasic com User Manual August 31 2015 ANU S RYA UNIVERSITY PROGRAM CLOCK 25MHz 5V 2A N CONI USB Mini B n 5V DC Jack Micro SD Ethernet USB OTG ee AN Micro AB 1GB DDR3 2 chip x32 MSEL 4 0 1 2 4 5 EPCS128 CLOCK SOMHz Cyclo ety 5CSEMA4U23C6 2x20 pin GPIO quu USB Mini B Accelerometer 2x20 pin GPIO Digital Arduino Header Analoc ADC LTC 2x7 Header 2x5 Header n A 5 22884848488 HPS HPS HPS WARM Push Button 2 Slide Switch x4 LED x8 imd Figure 2 3 Block diagram of DEO Nano SoC Detailed information about Figure 2 3 are listed below FPGA Device Cyclone V SoC 5CSEMA4U23CON Device Dual core ARM Cortex A9 HPS 40K programmable logic elements 2 460 Kbits embedded memory 5 fractional PLLs 2 hard memory controllers Configuration and Debug Serial configuration device EPCSI28 on FPGA Onboard USB Blaster II Mini B USB connector DEO Nano SoC 10 www terasic com Tijasic User Manual August 31 2015 www terasic com Memory Device IGB 2x256Mx16 DDR3 SDRAM on HPS Micro SD card socket on HPS Communication One USB 2 0 OTG ULPI interface with USB Micro AB connector UART to USB USB Mini B connector e 10 100 1000 Ethernet Connectors Tw
29. PGA as shown in Figure 3 16 These switches are DEO Nano SoC 23 www terasic com User Manual August 31 2015 www terasic com UNIVERSITY PROGRAM not debounced and to be used as level sensitive data inputs to a circuit Each switch 1s connected directly and individually to the FPGA When the switch 15 set to the DOWN position towards the edge of the board it generates a low logic level to the FPGA When the switch 1 set to the UP position a high logic level 15 generated to the FPGA ANU S pP AN V SoC fir Logic SW3 SW2 SW1 SWO Logic 0 Figure 3 16 Connections between the slide switches and the Cyclone V SoC FPGA There are also eight user controllable LEDs connected to the FPGA Each LED 15 driven directly and individually by the Cyclone V SoC FPGA driving its associated pin to a high logic level or low level to turn the LED on or off respectively Figure 3 17 shows the connections between LEDs and Cyclone V SoC FPGA Table 3 6 Table 3 7 and Table 3 8 list the pin assignment of user push buttons switches and LEDs DEO Nano SoC 24 www terasic com User Manual August 31 2015 www terasic com PIN W15 PIN AA24 PIN V16 JA DTE RYAN pm vis Cyclone y 25 SoC PIN AE26 PIN Y16 PIN AA23 Figure 3 17 Connections between the LEDs and the Cyclone V SoC FPGA LEDO LED1 LED2 LED3 LED4 LEDS LED6 LED LEDO LED1 LED2 LED3 LED4 LEDS LED6 LEDY
30. RE RE ERE RE RE ERE E E EE RE E ERE E ERE E RE RE RE Please enter your choise 1 2 3 4 Figure 5 1 Command line of the batch file to program the FPGA and EPCS device 5 2 ADC Reading This demonstration illustrates steps to evaluate the performance of the 8 channel 12 bit A D Converter LTC2308 The DC 5 0V on the 2x5 header is used to drive the analog signals by a trimmer potentiometer The voltage can be adjusted within the range between O and 4 096V The 12 bit voltage measurement is displayed on the NIOS II console Figure 5 2 shows the block diagram of this demonstration If the input voltage is 2 0V 2 0V a pre scale circuit can be used to adjust it to 0 DEO Nano SoC User Manual www terasic com 49 www teraSic com August 31 2015 FPGA o 2 o A 50 MHz s tt 193uuoo1 lu uigjes S Old lt gt ADC Controller emm Conor 2x5 Header 1 Figure 5 2 Block diagram of ADC reading Figure 5 3 depicts the pin arrangement of the 2x5 header This header is the input source of ADC convertor in this demonstration Users can connect a trimmer to the specified ADC channel ADC INO ADC_IN7 that provides voltage to the ADC convert The FPGA will read the associated register in the convertor via serial interface and translates it to voltage value to be displayed on the Nios II console VCC5 ADC INO ADC IN1 A
31. S device are 1 Set MSEL 4 0 10010 2 Choose Programmer from Tools menu and the Chain cdf window will appear 3 Click Auto Detect and then select correct device both FPGA device and HPS will detected See Figure 8 7 4 Double click the red rectangle region shown in Figure 8 7 and the Select New Programming File page will appear Select the correct jic file 5 Erase the EPCS device by clicking the corresponding Erase box A factory default SFL image will be loaded as shown in Figure 8 9 DEO Nano SoC 74 www terasic com Tijasic User Manual August 31 2015 www terasic com JA DTE RYA UNIVERSITY PROGRAM X Programmer D SVN DEO nano DEO SOC Default DEO SOC Default DEO SOC Default DEO SOC Default cdf File Edit View Processing Tools Window 5 Search altera com 3 Hardware Setup DE SoC USB 1 Mode JTAG Enable real time ISP to allow background programming when available File Device Checksum Usercode Program Verify Blank Examine Security Erase Check Bit lt none gt SOCVHPS 00000000 lt none gt Factory default enhanced SCSEMA4 OOSBDA6A dli Auto Detect output file jic EPCS128 m Stop Figure 8 9 Erase the EPCS device in Quartus II Programmer 6 Click Start to erase the EPCS device 8 5 EPCS Programming nios 2 flash programmer Before programm
32. SoC board such as users LED KEY I2C interfaced G sensor All the associated files can be found in the directory Demonstrations SOC of the DEO Nano SoC System CD Please refer to Chapter 5 Running Linux on the DE0 Nano SoC board from the DEO Nano SoC Getting Started Guide pdf to run Linux on DEO Nano SoC board B Installation of the Demonstrations To install the demonstrations on the host computer Copy the directory Demonstrations into a local directory of your choice Altera SoC EDS v14 0 is required for users to compile the c code project 6 1 Hello Program This demonstration shows how to develop first HPS program with Altera SoC EDS tool Please refer to First HPS pdf from the system CD for more details The major procedures to develop and build HPS project are Install Altera SoC EDS on the host PC Create program c h files with a generic text editor Create a Makefile with a generic text editor Build the project under Altera SoC EDS DEO Nano SoC 52 www terasic com ter www terasic com User Manual August 31 2015 ANU S RYA UNIVERSITY PROGRAM B Program File The main program for the Hello World demonstration 15 finclude lt stdio h gt int maini int argc char arcqgv printf i Hello World r m returni B Makefile A Makefile is required to compile a project The Makefile used for this demo 15 TARGET my first ROSS COMPILE arm linux
33. TAG and Flash interfaces The SFL Megafunction is available in Quartus II Figure 3 9 shows the programming method when adopting SFL solution Please refer to Chapter 8 Steps of Programming the Serial Configuration Device for the basic programming instruction on the serial configuration device DEO Nano SoC 18 www terasic com Tijasic User Manual August 31 2015 www terasic com PROG M Quartus SFL Image Programmer i AS x1 g USB Blaster to Bridge gt ae Circuit The JTAG 1 and ASMI Figure 3 9 Programming a serial configuration device with SFL solution 3 3 Board Status Elements In addition to the 9 LEDs that FPGA HPS device can control there are 6 indicators which can indicate the board status See Figure 3 10 please refer the details in Table 3 3 UART TXD RXD JTAG TX RX CONF DONE 3 3V Power Figure 3 10 LED Indicators on DEO Nano SoC Table 3 3 LED Indicators Board Reference LED Name Description LED9 3 3 V Power Illuminate when 3 3V power is active DONE when the FPGA is successfully configured LED10 DEO Nano SoC 19 www terasic com Tijasic User Manual August 31 2015 www terasic com LED11 JTAG TX Illuminate when data is transferred from JTAG to USB Host LED12 JTAG RX Illuminate when data is transferred from USB Host to JTAG Tx
34. ame Load Setting Exit Figure 4 3 Enter the project name B System Configuration Users are given the flexibility in the System Configuration to include their choice of components in the project as shown in Figure 4 4 Each component onboard is listed and users can enable or disable one or more components at will If a component is enabled the DEO Nano SoC System Builder will automatically generate its associated pin assignment including the pin name pin location pin direction and I O standard DEO Nano SoC 44 www terasic com Tijasic User Manual August 31 2015 www terasic com JA DTE RYA UNIVERSITY PROGRAM DEO Nano SoC V1 0 0 gt System Configuration Project Name DEO NANO SOC v CLOCK LEDx8 Button x 2 Switch x 4 ADC 2x5 Header Arduino Header HPS GPIO 0 Header Mone Prefix Name GPIO 1 Header Mone X Prefix Name Figure 4 4 System configuration group B GPIO Expansion If users connect any Terasic GPIO based daughter card to the GPIO connector s on DEO Nano SoC the DEO Nano SoC System Builder can generate a project that include the corresponding module as shown in Figure 4 5 It will also generate the associated pin assignment automatically including pin name pin location pin direction and I O standard DEO Nano SoC 45 www terasic com Tijasic User Manual August 31 2015 www terasic com JAN DTE n A
35. an be derived from the DATA X0 0x32 DATAX1 0x33 DATAYO 0x34 DATAY 1 0x35 DATAZO 0x36 DATAX1 0x37 registers The DATA XO represents the least significant byte and the DATAXI represents the most significant byte It is recommended to perform multiple byte read of all registers to prevent change in data between sequential registers read The following statement reads 6 bytes of X Y or Z value read file szData8 sizeof szData8 where szData is an array of six bytes B Demonstration Source Code e Build tool Altera SoC EDS v14 0 e Project directory Demonstration SoC hps_gsensor e Binary file gsensor e Build command make make clean to remove all temporal files e Execute command gsensor loop count B Demonstration Setup e Connect a USB cable to the USB to UART connector J4 on the DEO Nano SoC board and the host PC e Copy the executable file esensor into the microSD card under the home root folder in Linux e Insert the booting microSD card into the DEO Nano SoC board e Power on the DEO Nano SoC board DEO Nano SoC 62 www terasic com User Manual August 31 2015 www terasic com RYA UNIVERSITY PROGRAM e aunch PuTTY to establish connection to the UART port of DEO Nano SoC board Type root to login Yocto Linux e Execute gsensor in the UART terminal of PuTTY to start the G sensor polling e The demo program will show the X Y and Z values in the PuTTY as show
36. bines the latest dual core Cortex A9 embedded cores with industry leading programmable logic for ultimate design flexibility Users can now leverage the power of tremendous re configurability paired with a high performance low power processor system Altera s SoC integrates an ARM based hard processor system HPS consisting of processor peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high bandwidth interconnect backbone The DEO Nano SoC development board is equipped with high speed DDR3 memory analog to digital capabilities Ethernet networking and much more that promise many exciting applications The DEO Nano SoC Development Kit contains all the tools needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later In addition DEO Nano SoC Kit is also called Atlas SoC Kit in Altera s Rockboard org Linux community http www rocketboards org atlas soc The hardware of DEO Nano SoC Kit and Atlas SoC Kit are exactly the same however this community provides different development resource from DEO Nano SoC Kit The details of kit contents can be found in the Appendix chapter DEO Nano SoC 4 www terasic com User Manual August 31 2015 www terasic com 1 1 Package Contents Figure 1 1 shows a photograph of the DEO Nano SoC package DEO Nano SoC Board DEO Nano SoC Quick Start Guide Type A to Mini B USB Cable x1 Type A to Micro B USB Cable x1 Powe
37. duino 103 3 3 V Arduino 104 PIN U14 Arduino 104 3 3 V Arduino 105 PIN U13 Arduino 105 3 3 V Arduino 106 PIN AG8 Arduino 106 3 3 V Arduino 107 PIN 8 Arduino 107 3 3 V Arduino 108 PIN AF17 Arduino 108 3 3 V Arduino 109 PIN AE15 Arduino 109 3 3 V Arduino 1010 AF15 Arduino 1010 SS 3 3 V Arduino 1011 PIN AG16 Arduino 1011 MOSI 3 3 V Arduino 1012 PIN AH11 Arduino 1012 MISO 3 3 V Arduino 1013 PIN AH12 Arduino 1013 SCK 3 3 V Arduino 1014 PIN AH9 Arduino 1014 SDA 3 3 V Arduino 1015 PIN AG11 Arduino 1015 SCL 3 3 V Arduino Reset PIN AH7 Reset signal low active 3 3 V Besides 16 pins for digital GPIO there are also 6 analog inputs on the Arduino Uno R3 Expansion Header ADC_INO 115 Consequently we use ADC LTC2308 from Linear Technology the board for possible future analog to digital applications We will introduce in the next section 3 6 4 A D Converter and Analog Input The DEO Nano SoC has an analog to digital converter LT C2308 The LTC23068 is a low noise 500ksps 8 channel 12 bit ADC with a SPI MICROWIRE compatible serial interface This ADC includes an internal reference and a fully differential sample and hold circuit to reduce common mode noise The internal conversion clock allows the external serial output data clock SCK to operate at any frequency up to 40MHz It can be configured to accept eight input signals at inputs ADC_INO through ADC_IN7 These eight input signals are connected to
38. e DEO Nano SoC kit resources on the Atlas SoC kit and vice versa For more details on the Atlas SoC kit please visit http www rocketboards org atlas soc DEO Nano SoC 77 www terasic com ter User Manual August 31 2015 www terasic com Chapter 10 Appendix B 10 1 Revision History Change Log Initial Version Preliminary Minor corrections fixing typos and broken links V1 2 Minor corrections fixing typos and broken links and adding Altera Atlas kit s description Minor corrections fixing Table 3 2 Copyright O 2015 Terasic Inc All rights reserved DEO Nano SoC 78 www terasic com Tijasic User Manual August 31 2015 www terasic com
39. ection to the UART port of Putty Type root to login Altera Yocto Linux e Type hps gpio in the UART terminal of PuTTY to start the program e HPS LED will flash twice and users can control the user LED with push button e Press 5 KEY to light up 5 LED e Press CTRL C to terminate the application 6 3 I2C Interfaced G sensor This demonstration shows how to control the G sensor by accessing its registers through the built in I2C kernel driver in Altera Soc Yocto Powered Embedded Linux B Function Block Diagram Figure 6 6 shows the function block diagram of this demonstration The G sensor on the DEO Nano SoC board is connected to the 12 0 controller in HPS The G Sensor I2C 7 bit device address 15 0x53 The system I2C bus driver 1 used to access the register files in the G sensor The G sensor interrupt signal 15 connected to the PIO controller This demonstration uses polling method to read the register data asic DEO Nano SoC 60 www terasic com Mgjas e User Manual August 31 2015 FPGA SoC DDR3 ARM Program HPS Linux User Mode M G Sensor B 2 address 0x53 Interrupt Figure 6 6 Block diagram of the G sensor demonstration B 2 Driver The procedures to read a register value from G sensor register files by the existing I2C bus driver in the system are 1 Open I2C bus driver dev 12c 0 file open dev 12c 0 O_RDWR 2 Specify G sensor s I2C address 0
40. establish connection to the UART port of Putty Type root to login Altera Yocto Linux e my first in the UART terminal of PuTTY to start the program and the Hello World message will be displayed in the terminal 6 2 Users LED and KEY This demonstration shows how to control the users LED and KEY by accessing the register of GPIO controller through the memory mapped device driver The memory mapped device driver allows developer to access the system physical memory B Function Block Diagram Figure 6 1 shows the function block diagram of this demonstration The users LED and KEY are connected to the GPIOI controller in HPS The behavior of GPIO controller is controlled by the register in GPIO controller The registers can be accessed by application software through the memory mapped device driver which is built into Altera SoC Linux DEO Nano SoC 54 www User Manual August 31 2015 www terasic com FPGA SoC DDR3 ARM Program HPS Linux User Mode Linux Kernel Mode Figure 6 1 Block diagram of GPIO demonstration LED B Block Diagram of GPIO Interface The HPS provides three general purpose I O GPIO interface modules Figure 6 2 shows the block diagram of Interface GPIO 28 0 is controlled by the GPIOO controller and GPIO 57 29 is controlled by the GPIOI controller GPIO 70 58 and input only GPI 13 0 are controlled by the GPIO2 co
41. fine LED 0x01000000 define BUTTON MASK 0x02000000 The following statement is used to configure the LED associated pins as output pins alt setbits word virtual base Cuint32 t X ALT SWPORTA DDR ADDR amp uint32 t HW REGS MASK USER IO DIR The following statement 1s used to turn on the LED alt setbits word virtual base Cuint32 t X ALT SWPORTA DR ADDR amp uint32 t HW REGS MASK LED The following statement is used to read the content of gpio ext porta register The bit mask is used to check the status of the key alt read word virtual base Cuint32 ALT EXT PORTA ADDR amp uint32 t MASK B Demonstration Source Code e Build tool Altera SoC EDS V14 0 e Project directory Demonstration SoC hps_gpio e Binary file e Build command make make clean to remove all temporal files e Execute command hps_gpio B Demonstration Setup e Connect a USB cable to the USB to UART connector J4 on the DEO Nano SoC board and the host PC e Copy the executable file hps_gpio into the microSD card under the home root folder in Linux DEO Nano SoC 59 www terasic com ter User Manual August 31 2015 www terasic com UNIVERSITY PROGRAM e Insert the booting micro SD card into the DEO Nano SoC board e Power the DEO Nano SoC board e Launch PuTTY and establish conn
42. gure 4 1 The DEO Nano SoC System Builder will generate two major files a top level design file v and a Quartus II setting file qsf after users launch the DEO Nano SoC System Builder and create a new project according to their design requirements The top level design file contains a top level Verilog HDL wrapper for users to add their own design logic The Quartus II setting file contains information such as FPGA device type top level pin assignment and the I O standard for each user defined I O pin Finally the Quartus II programmer 15 used to download sof file to the development board via JTAG interface Start Launch Quartus II Launch DEO Nano SOC and Open Project System Builder Add User Create New DEO Nano SOC Design Logic System Builder Project Compile to Generate Quartus II generate SOF Project and Document Configure FPGA End Figure 4 1 Design flow of building a project from the beginning to the end 4 3 Using DEO Nano SoC System Builder This section provides the procedures in details on how to use the DEO Nano SoC System Builder DEO Nano SoC 42 www terasic com User Manual August 31 2015 www terasic com UNIVERSITY PROGRAM B Install and Launch the DE0 Nano SoC System Builder The DEO Nano SoC System Builder is located in the directory Tools VSSystemBuilder of the DEO Nano SoC System CD Users can copy the entire folder to a host computer without installing the utili
43. he output value of first I O pin in the associated GPIO controller the second bit controls the output value of second I O pin in the associated GPIO controller and so on The value 1 in the register bit indicates the output value is high and the value 0 indicates the output value 15 low The status of KEY can be queried by reading the value of gpio_ext_porta register The first bit represents the input status of first IO pin in the associated GPIO controller and the second bit represents the input status of second IO pin in the associated GPIO controller and so on The value 1 1n the register bit indicates the input state is high and the value 0 indicates the input state 15 low B GPIO Register Address Mapping The registers of HPS peripherals are mapped to HPS base address space with 64K B size The registers of the controller are mapped to the base address OXFF708000 with 4KB size and the registers of the GPIO2 controller are mapped to the base address OxFF70A000 with 4KB size as shown in Figure 6 3 DEO Nano SoC 56 www terasic com User Manual August 31 2015 www terasic com HPS Identifier HPS Access R W Description Address map for the HHP HPS system domain Reserved QSPI Flash Controller Module QSPIREGS OxFF705000 OxFF705100 n nw Ve m ACP IL Reserved 1070 Reserved
44. hows how the FPGA 15 programmed in JTAG mode step by step Open the Quartus II programmer and click Auto Detect as circled in Figure 3 3 DEO Nano SoC 14 www terasic com User Manual August 31 2015 www terasic com Checksum Usercode Figure 3 3 Detect FPGA device in JTAG mode Select detected device associated with the board as circled in Figure 3 4 Figure 3 4 Select 5CSEMA4 device DEO Nano SoC 15 www terasic com Tijasic User Manual August 31 2015 www terasic com DE 5aC USB 1 Enable real time ISP to allow background programming when available Checksum Usercode 4 gt 00000000 lt none gt Stop 00000000 Delete Add File Figure 3 5 FPGA and HPS detected in Quartus programmer Right click on the FPGA device and open the sof file to be programmed as highlighted in Figure 3 6 lp Programmer Chain1 File Edit View Processing Tools Window Help Search altera com Hardware Setup DE SoC 5 1 Enable real time ISP to allow background programming when available 1 Save File 5 Add IPS File ice f Change IPS File yi Delete IPS File Add Programming File Down Change PR Programming File Delete PR Programming File Figure 3 6 Open the sof file to be programmed into the FPGA device DEO Na
45. ing the EPCS via nios 2 flash programmer users must add an EPCS patch file nios flash override txt into the Nios II EDS folder The patch file 1s available in the folder DemonstationEPCS Patch of DEO Nano SoC System CD Please copy this file to the folder QuartusInstalledFolder nios2edsVbin e g C altera 14 I nios2eds bin If the patch file is not included into the Nios II EDS folder an error will occur as shown in Figure 8 10 Using cable USBEB Blaster CUSB 81 device 1 instance 8x88 T TE d uen Z m EPCS layout data looking For section LEPGOS H1IB216 Unable to use EPCS device Leaving target processor paused Figure 8 10 Error Message No EPCS Layout Data DEO Nano SoC 13 www terasic com User Manual August 31 2015 www terasic com 8 6 Nios ll Boot from EPCS Device in Quartus ll v14 1 There is a known problem in Quartus II software that the Quartus Programmer must be used to program the EPCS device on DEO Nano SoC board Please refer to Altera s website here with details step by step asic DEO Nano SoC 76 www terasic com User Manual August 31 2015 Chapter 9 Appendix A 9 1 What s different between the DEO Nano SoC kit and the Atlas SoC kit The hardware is the same for the DEO Nano SoC kit and the Atlas SoC kit The only difference 1s the getting started process for the two kits Users can freely use th
46. ion setup files Output programming file Programming file type Ours J es gt File name output file jic Remote _ocal update difference file NONE Create Memory Map File Generate output file map Create CvP files Generate output file periph jic and output file core rbf Create config data RPD Generate output file auto rpd area 5CSEMA4 sof Page 4 SOF Data Page 0 auto gt Add Device DEO SOC Default sof SCSEMASU23 Remove Up Down Properties Figure 8 6 Convert Programming Files page after selecting the device DEO Nano SoC 72 www terasic com Tijasic User Manual August 31 2015 www terasic com 8 3 Write JIC File into the EPCS Device When the conversion of SOF to JIC file is complete please follow the steps below to program the EPCS device with the jic file created in Quartus II Programmer 1 Set MSEL 4 0 10010 2 Choose Programmer from the Tools menu and the Chain cdf window will appear 3 Click Auto Detect and then select the correct device 6CSEMAA Both FPGA device and HPS should be detected as shown in Figure 8 7 4 Double click the red rectangle region shown in Figure 8 7 and the Select New Programming File page will appear Select the jic file to be programmed 5 Program the EPCS device by clicking the corresponding Program Configure box A factory default SFL image will be loaded as shown in Figure 8 8 6 Click Start t
47. it Ethernet transfer by an external Micrel KSZ9031 RN PHY chip and HPS Ethernet MAC function The KSZ9031RN chip with integrated 10 100 1000 Mbps Gigabit Ethernet transceiver also supports MAC interface Figure 3 21 shows the connections between the HPS Gigabit Ethernet PHY and RJ 45 connector The pin assignment associated to Gigabit Ethernet interface is listed in Table 3 14 More information about the KSZ9031 RN PHY chip and its datasheet as well as the application notes which are available on the manufacturer s website DEO Nano SoC 32 www terasic com User Manual August 31 2015 www terasic com HPS TX DATA 3 0 HPS ENET GTX CLK oU GR HPS ENET TX EN HPS RX DATA 3 0 ATERA x F m yclone V HPS HPS _ _ Mpio T HPS INT NTN IOE E Hc HPS ENET RESET TN CLK_ENET_25 y KSZ9031RN 45 Figure 3 21 Connections between the HPS and Gigabit Ethernet Table 3 14 Pin Assignment of Gigabit Ethernet PHY Signal Name FPGA Pin No Description Standard HPS ENET TX EN PIN A12 GMII and MII transmit enable 3 3V HPS TX DATA O PIN A16 MII transmit data 0 3 3V HPS ENET TX DATA 1 PIN 14 MII transmit data 1 3 3V HPS TX DATA 2 PIN A15 MII transmit data 2 3 3V HPS ENET TX DATA 3 PIN D17 MII transmit data 3 3 3V HPS ENET RX DV PIN J13 GMII and MII receive data valid 3 3V HPS
48. lashing Figure 7 3 Running result in the terminal of PuTTY e Press CTRL C to terminate the program DEO Nano SoC 67 www terasic com User Manual August 31 2015 www terasic com Chapter 8 Programming the EPCS Device This chapter describes how to program the serial configuration EPCS device with Serial Flash Loader SFL function via the JTAG interface Users can program EPCS devices with a JTAG indirect configuration jic file which is converted from a user specified SRAM object file sof in Quartus The sof file is generated after the project compilation is successful The steps of converting sof to jic in Quartus II are listed below 8 1 Before Programming Begins The FPGA should be set to AS x1 mode i e MSEL 4 0 10010 to use the Flash as a FPGA configuration device as shown in Figure 8 1 Figure 8 1 DIP switch SW10 setting of Active Serial AS mode DEO Nano SoC 68 www terasic com User Manual August 31 2015 www terasic com 8 2 Convert SOF File to JIC File 1 Choose Convert Programming Files from the File menu of Quartus II as shown in Figure 8 2 New Project Wizard Open Project Save Project Close Project Save Save All File Properties Convert Programming Files Page Setup Figure 8 2 File menu of Quartus ll 2 Select JTAG Indirect Configuration File jic from the Programming file type field in the dialog of Convert Prog
49. low users to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the board B FPGA Altera Cyclone amp V SE 5CSEMAAU23CON device Serial configuration device EPCS 128 USB Blaster II onboard for programming JTAG Mode 2 push buttons 4 slide switches 5 green user LEDs Three 50MHz clock sources from the clock generator Two 40 expansion header One Arduino expansion header Uno R3 compatibility can connect with Arduino shields One 10 Analog input expansion header shared with Arduino Analog input DEO Nano SoC 8 www terasic com User Manual August 31 2015 www terasic com JAN DTE RYA U e i NIVERSITY ROGRAM A D converter 4 wire SPI interface with FPGA Hard Processor System 925MHz Dual core ARM Cortex A9 processor 1GB DDR3 SDRAM 32 bit data bus 1 Gigabit Ethernet PHY with RJ45 connector port USB OTG USB Micro AB connector Micro SD card socket Accelerometer I2C interface interrupt UART to USB USB Mini B connector Warm reset button and cold reset button One user button and one user LED LTC 2x7 expansion header 2 2 Block Diagram of the DEO Nano SoC Board Figure 2 3 15 the block diagram of the board the connections are established through the Cyclone V SoC FPGA device to provide maximum flexibility for users Users can configure the FPGA to implement any system design DEO
50. mporal files e Execute app command 5 CONTROL FPGA LED B Demonstration Setup e Quartus II and SoCEDS must be installed on the host PC e The MSEL 4 0 15 set to 00000 e Connect a USB cable to the USB to UART connector J4 on the DEO Nano SoC board and the host PC Copy the executable files 5 CONTROL LED and the FPGA configuration file HPS CONTROL FPGA LED rbf into the microSD card under the home root folder in Linux e Insert the booting microSD card into the DEO Nano SoC board Please refer to the chapter 5 Running Linux the DEO Nano SoC board on DEO Nano SoC Getting Started Guide pdf on how to build a booting microSD card image e Power on the DEO Nano SoC board e aunch PuTTY to establish connection to the UART port of the DEO Nano SoC board Type root to login Altera Yocto Linux e Execute dd if HPS CONTROL LED rbf of dev fpga0 in the UART terminal of PuTTY to configure the FPGA through the FPGA manager After the configuration is successful the message shown in Figure 7 2 will be displayed in the DEO Nano SoC 66 www terasic com ter User Manual August 31 2015 www terasic com ANU RYAN UNIVERSITY PROGRAM terminal Figure 7 2 Running command to configure the FPGA e Execute HPS CONTROL FPGA LED in the UART terminal of PuTTY to start the program e The message shown in Figure 7 3 will be displayed in the terminal The LED 7 0 will be f
51. n in Figure 6 8 D Cn LEJ L Cn I LEJ LEJ A I Figure 6 8 Terminal output of the G sensor demonstration e Press CTRL C to terminate the program DEO Nano SoC 63 www terasic com User Manual www terasic com August Ol 2015 Chapter 7 Examples for using both HPS SoC and FGPA Although HPS and FPGA can operate independently they are tightly coupled via a high bandwidth system interconnect built from high performance ARM AXITM bus bridges Both FPGA fabric and HPS can access to each other via these interconnect bridges This chapter provides demonstrations on how to achieve superior performance and lower latency through these interconnect bridges when comparing to solutions containing a separate FPGA and discrete processor 7 1 HPS Control FPGA LED This demonstration shows how HPS controls the FPGA LED through Lightweight HPS to FPGA Bridge The FPGA is configured by HPS through FPGA manager in HPS B A brief view on FPGA manager The FPGA manager in HPS configures the FPGA fabric from HPS It also monitors the state of FPGA and drives or samples signals to or from the FPGA fabric The command 1 provided to configure FPGA through the FPGA manager The FPGA configuration data 15 stored in the file with rbf extension The MSEL 4 0 must be set to 00000 before executing the command on HPS B Function Block Diagram Figure 7 1 shows the block diagram of this demons
52. nerated by the DEO0 Nano SoC System Builder Filename Description Project name gt qpf Quartus Project File Project name gt qsf Quartus ll Setting File ii Project name gt sdc Synopsis Design Constraints file for Quartus ll Project name gt htm Pin Assignment Document Users can add custom logic into the project in Quartus II and compile the project to generate the SRAM Object File sof DEO Nano SoC 47 www terasic com Tijasic User Manual August 31 2015 www terasic com Chapter 5 Examples For FPGA This chapter provides examples of advanced designs implemented by RTL or Qsys on the DEO Nano SoC board These reference designs cover the features of peripherals connected to the FPGA such as A D Converter All the associated files can be found in the directory Demonstrations FPGA of DEO Nano SoC System CD B Installation of Demonstrations Install the demonstrations on your computer Copy the folder Demonstrations to a local directory of your choice It 15 important to make sure the path to your local directory contains NO space Otherwise it will lead to error in Nios II Note Quartus II v14 0 or later is required for all DEO Nano SoC demonstrations to support Cyclone V SoC device 5 1 DEO Nano SoC Factory Configuration The DEO Nano SoC board has a default configuration bit stream pre programmed which demonstrates some of the basic features on board The setup required for thi
53. no SoC 16 www terasic com Tijasic User Manual August 31 2015 www terasic com ANU S RYAN UNIVERSITY PROGRAM Select the sof file to be programmed as shown in Figure 3 7 xn Select New Programming Fil 16 0 jicFile 2014 12 29 09 24 43 3 8 sofFile 2014 12 26 02 11 01 File name DEO SOC Default sof Files of type Programming Files sof pof jam jbc ekp jic Figure 3 7 Select the sof file to be programmed into the FPGA device Click Program Configure check box and then click Start button to download the sof file into the FPGA device as shown in Figure 3 8 DEO Nano SoC 17 www terasic com Tijasic User Manual August 31 2015 www terasic com File Edit View Processing Tools Window Help lt none gt SOCVHPS 00000000 D DED SOC Def 5CSEMA4U23 D0440CB8 us Change File al Save File SOCVHPS pu Down Figure 3 8 Program sof file into the FPGA device B Configure the FPGA in AS Mode The DEO Nano SoC board uses a serial configuration device EPCS128 to store configuration data for the Cyclone V SoC FPGA This configuration data 15 automatically loaded from the serial configuration device chip into the FPGA when the board is powered up Users need to use Serial Flash Loader SFL to program the serial configuration device via JTAG interface The FPGA based SFL 15 a soft intellectual property IP core within the FPGA that bridge the J
54. ntroller GPI 13 0 Interface Reset gpio rst n n Interrupt amp Manager gt Control Cortex A9 Subsystem Core Generic Interrupt Controller gpioO Intr In Register Manager GPIO 28 0 que amp gt GPIO 57 29 Interface GPIO 70 58 L4 Peripheral Bus Figure 6 2 Block diagram of GPIO Interface GPIO Register Block DEO Nano SoC 55 www terasic com Tijasic User Manual August 31 2015 www terasic com UNIVERSITY PROGRAM The behavior of I O pin 1s controlled by the registers in the register block There are three 32 bit registers in the GPIO controller used in this demonstration The registers are pio swporta dr write output data to output I O pin pio swporta ddr configure the direction of I O pin pio ext porta read input data of I O input pin The gpio swporta ddr configures the LED pin as output pin and drives it high or low by writing data to the gpio swporta dr register The first bit least significant bit of gpio swporta dr controls the direction of first IO pin in the associated GPIO controller and the second bit controls the direction of second IO pin the associated controller and so The value 1 in the register bit indicates the I O direction is output while the value 0 in the register bit indicates the I O direction is input The first bit of gpio_swporta_dr register controls t
55. o 40 pin expansion headers Arduino expansion header One 10 pin ADC input header One LTC connector one Serial Peripheral Interface SPI Master one I2C and one GPIO interface ADC 12 Bit Resolution 500Ksps Sampling Rate SPI Interface 8 Channel Analog Input Input Range OV 4 096V Switches Buttons and Indicators 3 user Keys FPGA x2 HPS x1 4 user switches FPGA x4 9 user LEDs FPGA x8 HPS x 1 2 HPS reset buttons HPS RESET n and HPS WARM RST n Sensors G Sensor on HPS Power 5V DC input DEO Nano SoC 11 www terasic com ter User Manual August 31 2015 www terasic com Chapter 3 Using the DEO Nano SoC Board This chapter provides an instruction to use the board and describes the peripherals 3 1 Settings of FPGA Configuration Mode When the DEO Nano SoC board is powered on the FPGA can be configured from EPCS or HPS The MSEL 4 0 pins are used to select the configuration scheme It is implemented as a 6 pin DIP switch SW10 on the DEO Nano SoC board as shown in Figure 3 1 we ir ET ve lt FE 4 Figure 3 1 DIP switch SW10 setting of FPP x32 mode 12 www teraSic com August 31 2015 DEO Nano SoC User Manual www terasic com Table 3 1 shows the relation between MSEL 4 0 and DIP switch SW10 Table 3 1 FPGA Configuration Mode Switch SW10 Board Reference Signal Name Description Default SW10
56. o program the EPCS device p Programmer D SVN DEO nano DEO SOC Default DEO SOC Default DEO SOC Default E ws File Edit View Processing Tools Window Hep Search altera com DE SoC use vode mees j Enable real time ISP to allow background programming when available Checksum Usercode Program Verify Blank ipu Start Configure Check 00000000 lt none gt 00000000 lt none gt wit Stop x amp Delete Change File ie Save File I Down Figure 8 7 Two devices are detected in the Quartus Programmer DEO Nano SoC 73 www terasic com User Manual August 31 2015 www terasic com UNIVERSITY PROGRAM Programmer D SVN DEO nano DEO SOC Default DEO SOC Default DEO SOC Default o File Edit View Processing Tools Window Help Search altera com alt 5 Hardware Setup DE SoC USB 1 Enable real time ISP to allow background programming when available Device Checksum Usercode Program Configure gt SOCVHPS 00000000 nonez Factory default enhanced SCSEMA4 05 5 n Change File n Save File pu Down Figure 8 8 Quartus programmer window with jic file 8 4 Erase the EPCS Device The steps to erase the existing file in the EPC
57. om Tijasic User Manual August 31 2015 www terasic com Chapter 4 DEO Nano SoC System Builder This chapter describes how users can create a custom design project with the tool named DEO Nano SoC System Builder 4 1 Introduction The DEO Nano SoC System Builder is a Windows based utility It 15 designed to help users create a Quartus II project for DEO Nano SoC within minutes The generated Quartus II project files include e Quartus II project file qpf e Quartus II setting file qsf e Top level design file v e Synopsis design constraints file sdc e Pin assignment document htm The above files generated by the DEO Nano SoC System Builder can also prevent occurrence of situations that are prone to compilation error when users manually edit the top level design file or place pin assignment The common mistakes that users encounter are e Board 15 damaged due to incorrect bank voltage setting or pin assignment e Board is malfunctioned because of wrong device chosen declaration of pin location or direction 1s incorrect or forgotten e Performance degradation due to improper pin assignment 4 2 Design Flow This section provides an introduction to the design flow of building a Quartus II project for DEO Nano SoC 41 www terasic com User Manual August 31 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM DEO Nano SoC under the DEO Nano SoC System Builder The design flow is illustrated in Fi
58. onvert Programming File D SVN DEO SOC Default DEO SOC Default DEO 5 57 wz Search altera com Output programming file Options File name output Remote Local update difference file NONE Create Memory Map File Generate output file map ww Create CvP files Generate output file periph jic and output file core rbf Create config data Generate output file auto rpd File Data area Flash Loader SOF Data Page DEO SOC Default sof B5CSEMA3 123 Remove up Down Properties Figure 8 4 Click on the Flash Loader 12 Select the targeted FPGA to be programed into the EPCS as shown in Figure 8 5 13 Click OK and the Convert Programming Files page will appear as shown in Figure 8 6 14 Click Generate 2 2 2050 www terasic com User Manual August 31 2015 www Lterasic com JA DTE RYA UNIVERSITY PROGRAM 3p Select Devices Arria II GX Arria II GZ Export Arria V Arria V GZ Cydone Remove Cydone Cydone Uncheck All Cydone III LS Cydone IV E Cydone IV GX Cydone V II HardCopy III HardCopy IV 10 FPGA MAX II Import Edit Figure 8 5 Select Devices page qu 2 wr ii Convert Programming File D SVN DEO nano DEO SOC Default DEO SOC Default DEO S w Search altera com a Convers
59. out definition SCL SCL SDA SDA Analog Vref NC GND IOREF Arduino 1013 D13 SCK Reset Arduino Reset N Arduino 1012 D12 MISO VCC3P3 Arduino 1011 D11 MOS VCC5 Arduino 1010 010 55 GND Arduino 1 9 D9 GND Arduino 108 D8 VCC9 Arduino Arduino 107 07 106 06 ADC INO Arduino 105 D5 A1 ADC IN1 104 D4 2 2 Arduino D3 Arduino 102 D2 Arduino 101 D1 TX Arduino IOO DO RX A3 IN3 4 1 4 5 IN5 D12 MISO Arduino 1012 1 1 i f 1 i VCC5 D13 SCK Arduino_ 013 P je Arduino 1011 D11 MOSI Arduino Reset n 3 fe GND Figure 3 18 lists the all the pin out signal name of the Arduino Uno connector The blue font represents the Arduino pin out definition The 16 GPIO pins are provided to the Arduino Header for digital I O Table 3 11 lists the all the pin assignments of the Arduino Uno connector digital signal names relative to the Cyclone V SoC FPGA DEO Nano SoC 28 www terasic com User Manual August 31 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM Table 3 11 Pin Assignments for Arduino Uno Expansion Header connector Schematic mm Specific features FPGA Pin No Description Standard Signal Arduino 100 PIN AG13 Arduino 100 RXD 3 3 V Arduino 101 PIN AF13 Arduino 101 TXD 3 3 V Arduino 102 PIN AG10 Arduino 102 3 3 V Arduino 103 PIN AG9 Ar
60. r DC Adapter 5v Q 4GB microSD card installed Figure 1 1 The DEO Nano SoC package contents The DEO Nano SoC package includes The DEO Nano SoC development board DEO Nano SoC Quick Start Guide USB cable Type A to Mini B for FPGA programming or UART control USB cable Type A to Micro B for USB OTG connect to PC 5V 2A DC power adapter 4GB microSD Card Installed 1 2 DEO Nano SoC System CD The DEO Nano SoC System CD contains all the documents and supporting materials associated with DEO Nano SoC including the user manual system builder reference designs and device datasheets Users can download this system CD from the link http cd deO nano soc terasic com DEO Nano SoC 5 www terasic com User Manual August 31 2015 www terasic com 1 3 Getting Help Here are the addresses where you can get help if you encounter any problems Altera Corporation 101 Innovation Drive San Jose California 95134 USA Email university altera com Terasic Technologies No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City 30070 Taiwan Email support terasic com Tel 886 3 575 0880 Website deO nano soc terasic com DEO Nano SoC 6 User Manual www terasic com www August 31 2015 Chapter 2 Introduction of the DEO Nano SoC Board This chapter provides an introduction to the features and design characteristics of the board 2 1 Layout and Components Figure 2 1
61. r mapping can be retrieved by ALT LWFPGASLVS OFST which is defined in altera hps hardware library The slave IP connected to the bridge can then be accessed through the base address and the register offset in these IPs For instance the base address of the PIO slave IP in this system is 0x0001 0040 the direction control register offset is 0x01 and the data register offset is 0x00 The following statement is used to retrieve the base address of PIO slave IP DEO Nano SoC 65 www terasic com User Manual August 31 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM h2p_lw_led_addr virtual_base unsigned long ALT_LWFPGASLVS_OFST LED_PIO_BASE amp unsigned long REGS MASK Considering this demonstration only needs to set the direction of PIO as output which is the default direction of the PIO IP the step above can be skipped The following statement is used to set the output state of the PIO alt_write_word h2p_lw_led_addr Mask The Mask in the statement decides which bit in the data register of the PIO IP is high or low The bits in data register decide the output state of the pins connected to the LED B Demonstration Source Code e Build tool Altera SoC EDS V14 0 e Project directory Demonstration SoC FPGAMMPS CONTROL LED e FPGA configuration file 5 CONTROL LED rbf e Binary file HPS CONTROL FPGA LED e Build app command make make clean to remove all te
62. ramming Files 3 Choose EPCS128 from the Configuration device field 4 Choose Active Serial from the Mode filed 5 Browse to the target directory from the File name field and specify the name of output file 6 Click on the SOF data in the section of Input files to convert as shown in Figure 8 3 DEO Nano SoC 69 www terasic com User Manual August 31 2015 www terasic com Search altera com a Specify the input files to convert and the type of programming file to generate You can also import input file information from other files and save the conversion setup information created here for future use Output programming file Programming file type JT AG Indirect Configuration File jic Options Configuration device Mode File name output file jic Remote Local update difference file NONE Create Memory Map File Generate output_file map Create CvP files Generate output file periph jic and output file core rbf Create config data Generate output file auto rpd Figure 8 3 Dialog of Convert Programming Files 7 Click Add File 8 Select the sof to be converted to a jic file from the Open File dialog 9 Click Open 10 Click on the Flash Loader and click Add Device as shown in Figure 8 4 11 Click OK and the Select Devices page will appear DEO Nano SoC 70 www terasic com Tijasic User Manual August 31 2015 www terasic com ANU S RYA UNIVERSITY PROGRAM a E a po C
63. s demonstration and the location of its files are shown below B Demonstration Setup File Locations and Instructions e Project directory DEO SOC Default e Bitstream used DEO SOC Default sof or DEO SOC Default jic e Power on the DEO Nano SoC board with the USB cable connected to the USB Blaster II port If necessary that is if the default factory configuration is not currently stored in the EPCS device download the bit stream to the board via JTAG interface e You should now be able to observe the LEDs are blinking e For the ease of execution demo batch folder 1 provided in the project It 1 able to not only DEO Nano SoC 48 www terasic com User Manual August 31 2015 www terasic com JAN DTE UNIVERSITY PROGRAM load the bit stream into the FPGA in command line but also program or erase file to the EPCS by executing the test bat file shown in Figure 5 1 If users want to program a new design into the EPCS device the easiest method 15 to copy the new sof file into the demo batch folder and execute the test bat Option 2 will convert the sof to and option 3 will program jic file into the EPCS device E C Windows system32 cmd exe Hakezure MSELI4 H is set to Plesase T ku jj choose your operation programming sof to FPGA converting sof to jic programming jic to EPCS erasing jic From EPCS RE RE
64. t of Clock Inputs VO Standard 50 MHz clock input FPGA CLK2 50 PIN Yi3 50 MHz clock input FPGA CLK3 50 PIN Et1 50 MHZ clock input share with FPGA CLK1 50 HPS CLK1 25 E20 25 MHz clockinput O HPS CLK2 25 D20 25MHzclokinpt 3 6 Peripherals Connected to the FPGA This section describes the interfaces connected to the FPGA Users can control or monitor different interfaces with user logic from the FPGA asic DEO Nano SoC 22 www terasic com User Manual August 31 2015 3 6 1 User Push buttons Switches and LEDs The board has two push buttons connected to the FPGA as shown in Figure 3 14 Connections between the push buttons and the Cyclone V SoC FPGA Schmitt trigger circuit is implemented and act as switch debounce in Figure 3 15 for the push buttons connected The two push buttons named KEYO and KEY1 coming out of the Schmitt trigger device are connected directly to the Cyclone V SoC FPGA The push button generates low logic level or high logic level when it 1 pressed not respectively Since the push buttons are debounced they can be used as clock or reset inputs in a circuit VCC3P3 KEYO KEY1 TAAUC17 e Aui CYCIone V SoC Figure 3 14 Connections between the push buttons and the Cyclone V SoC FPGA n hbutton depressed n hbutton released Before Debouncing Schmitt Trigger Debounced Figure 3 15 Switch debouncing There are four slide switches connected to the F
65. terface connected for communication with the HPS This interface doesn t support HW flow control signals The physical interface is implemented by UART USB onboard bridge from a FT232R chip to the host with an USB Mini B connector More information about the chip is available on the manufacturer s website or in the directory Datasheets UART_TO_USB of DEO Nano SoC system CD Figure 3 22 shows the connections between the HPS FT232R chip and the USB connector Table 3 16 lists the pin assignment of UART interface connected to the HPS FT232 DP amp rH Cyclone V 232_ gt HPS USB Mini B Connector Figure 3 22 Connections between the HPS and FT232R Chip DEO Nano SoC 34 www terasic com User Manual August 31 2015 www terasic com Signal Name HPS UART RX HPS UART TX HPS CONV USB N Table 3 16 Pin Assignment of UART Interface FPGA Pin No Description PIN A22 HPS UART Receiver PIN B21 HPS UART Transmitter PIN C6 Reserve 3 7 4 DDR3 Memory Standard 3 3V 3 3V 3 3V The DDR3 devices connected to the HPS are the exact same model as the ones connected to the FPGA The capacity is IGB and the data bandwidth is in 32 bit comprised of two x16 devices with a single address command bus The signals are connected to the dedicated Hard Memory Controller for HPS I O banks and the target speed is 400 MHz Table 3 17 lists the pin assignment of DDR3 and its description with I O standard
66. tration The HPS uses Lightweight HPS to FPGA AXI Bridge to communicate with FPGA The hardware in FPGA part is built into Qsys The data transferred through Lightweight HPS to FPGA Bridge is converted into Avalon MM DEO Nano SoC 64 www terasic com ter User Manual August 31 2015 www terasic com UNIVERSITY PROGRAM master interface The PIO Controller works as Avalon MM slave in the system They control the associated pins to change the state of LED This is similar to a system using Nios II processor to control LED HPS FPGA lt amp H Control Block User App Memory Mapped PIO ED Driver Controller Figure 7 1 FPGA LED are controlled by HPS B LED Control Software Design The Lightweight HPS to FPGA Bridge is a peripheral of HPS The software running on Linux cannot access the physical address of the HPS peripheral The physical address must be mapped to the user space before the peripheral can be accessed Alternatively a customized device driver module can be added to the kernel The entire CSR span of HPS is mapped to access various registers within that span The mapping function and the macro defined below can be reused if any other peripherals whose physical address 15 also in this span define HW REGS BASE ALT STM OFST fdefine HW REGS SPAN 0 04000000 define HW REGS MASK HW REGS SPAN 1 The start address of Lightweight HPS to FPGA Bridge afte
67. ty A window will pop up as shown in Figure 4 2 after executing the DEO Nano SoC SystemBuilder exe on the host computer cm uw di cw ww DEO Nano SoC V1 0 0 NB S RYAN System Configuration SE Wd www Project DEO SOC DEO Nano SoC FPGA Board _ CLOCK LED x 8 Button x 2 Switch x 4 ADC 2x5 Header 4 Arduino Header HPS GPIO 0 Header p P T SEES Mate SER L gt ih 1 vv1 1 EB F I aem 7 n 4 L ny LL 1 gt at Ms ee To None M gt d 3 Prefix Name GPIO 1 Header Prefix Name Load Setting Exit Figure 4 2 The GUI of DEO Nano SoC System Builder B Enter Project Name Enter the project name in the circled area as shown in Figure 4 3 The project name typed in will be assigned automatically as the name of your top level design entity DEO Nano SoC 43 www terasic com User Manual August Ol 2015 JA DTE RYA UNIVERSITY PROGRAM DEO Nano SoC V1 0 0 gt Sr System Configuration Project Name DEO NANO SOC CLOCK VILED x8 Button x 2 Switch x 4 ADC 2x5 Header 4 Arduino Header O HPS GPIO 0 Header None v Prefix Name GPIO 1 Header Prefix N
68. x53 ioctl file I2C_SLAVE 0x53 3 Specify desired register index in g sensor write file amp Addr8 sizeof unsigned char 4 Read one byte register value read file amp Data8 sizeof unsigned char The G sensor I2C bus is connected to the I2CO controller as shown in the Figure 6 7 The driver name given 15 dev 12c 0 2 SDA A19 HPS I2CO0 SDAT Ii2CO scL C18 5 I2C0 SCLK Figure 6 7 Connection of HPS 2 signals The step 4 above can be changed to the following to write a value into a register write file amp Data8 sizeof unsigned char The step 4 above can also be changed to the following to read multiple byte values read file amp szData8 sizeof szData 8 where szData 15 an array of bytes The step 4 above can be changed to the following to write multiple byte values DEO Nano SoC 61 www terasic com User Manual August 31 2015 www terasic com write file amp szData8 sizeof szData8 where szData is an array of bytes B G sensor Control The ADI ADXL345 provides I2C and SPI interfaces I2C interface 1s selected by setting the CS pin to high on the DEO Nano SoC board The ADI ADXL345 G sensor provides user selectable resolution up to 13 bit 16g The resolution can be configured through the DATA FORAMT 0x31 register The data format in this demonstration is configured as Full resolution mode lt 16g range mode Left justified mode The X Y Z data value c

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