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Xilinx UG534 ML605 Hardware, User Guide

1. U1 FPGA Pin Schematic Netname J1 SODIMM G20 DDR3_D25 59 E19 DDR3_D26 67 F20 DDR3 D27 69 A20 DDR3 D28 56 A21 DDR3 D29 58 E22 DDR3 D30 68 E23 DDR3 D31 70 G21 DDR3 D32 129 B21 DDR3 D33 131 A23 DDR3 D34 141 A24 DDR3 D35 143 C20 DDR3 D36 130 D20 DDR3 D37 132 J20 DDR3 D38 140 G22 DDR3 D39 142 D26 DDR3 D40 147 F26 DDR3 D41 149 B26 DDR3 D42 157 E26 DDR3 D43 159 C24 DDR3 D44 146 D25 DDR3 D45 148 D27 DDR3 D46 158 C25 DDR3 D47 160 C27 DDR3 D48 163 B28 DDR3 D49 165 D29 DDR3 D50 175 B27 DDR3 D51 177 G27 DDR3 D52 164 A28 DDR3 D53 166 E24 DDR3 D54 174 G25 DDR3 D55 176 F28 DDR3 D56 181 B31 DDR3 D57 183 ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com Detailed Description 17 Chapter 1 ML605 Evaluation Board 18 Table 1 4 DDR3 SODIMM Connections Conta U1 FPGA Pin Schematic Netname J1 SODIMM H29 DDR3 D58 191 H28 DDR3 D59 193 B30 DDR3 D60 180 A30 DDR3 D61 182 E29 DDR3 D62 192 F29 DDR3 D63 194 E11 DDR3 DMO 11 B11 DDR3 DM1 28 E14 DDR3 DM2 46 D19 DDR3_DM3 63 B22 DDR3_DM4 136 A26 DDR3_DM5 153 A29 DDR3_DM6 170 A31 DDR3_DM7 187 E12 DDR3_DOS0_N 10 D12 DDR3_DOS0_P 12 J12 DDR3_DQS1_N 27 H12 DDR3_DQS1_P 29 Al4 DDR3_DQS2_N 45 A13 DDR3 DQS2 P 47 H20 DDR3_DQS3_N 62 H19 DDR3_DQS3_P 64 C23 DDR3_DQS4_N 135 B23 DDR3_DQS4_P
2. Table 1 1 ML605 Features Cont d Number Feature Notes schematic Page Close generatitin 200 MHz OSC oscillator socket SMA 30 connectors a 200 MHz oscillator Epson 200 MHz 2 5V LVDS OSC 30 7 b Oscillator socket single Anm Components 66 MHz 2 5V 30 ended c SMA connectors SMA pair 30 8 GTX RX TX port SMA x4 30 PCIe Genl 8 lane 9 Gen 4 lane Card edge connector 8 lane 21 10 SFP connector and cage AMP 136073 1 23 11 Ethernet 10 100 1000 with li rvell M88E1111 EPHY 24 SGMII 12 USB MiniB USB to UART cuco Labs CP2103GM bridge 33 bridge 13 USB A Host USB Mini B Cypress CY7C67300 100AXI 27 peripheral connectors controller 14 Video DVI connector Chrontel CH7301C TF Video codec 28 29 15 IIC NV EEPROM 8 Kb ST Microelectronics M24C08 32 on backside WDW6TP Status LEDs 13 24 31 i eine Right angle link rate and direction 24 b FPGA INIT DONE Init red Done green 31 c System ACE CF status Status green Error red 13 User I O 31 a User LEDs green 8 User I O active High 31 b User pushbuttons N O l in mentar 5 User I O active High 31 17 c User LEDs green 5 User I O active High 31 d User DIP switch 8 pole User I O active High 31 e User GPIO SMA connectors SMA pair 30 PEED decades Iesse Be 33 display www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description
3. Table 1 1 ML605 Features Cont d Number Feature Notes mena Page Switches 39 13 a Power On Off Slide switch 39 b FPGA_PROG_B l 18 pushbutton active Low 13 Soya E CE image 4 pole DIP switch active High 25 Select d Mode Switch 6 pole DIP switch active High 25 19 FMC HPC connector Samtec ASP 134486 01 16 19 20 FMC LPC connector Samtec ASP 134603 01 20 Power management 35 44 a PMBus controllers 2 x TI UCD9240PFC 35 40 21 b Voltage regulators 2 x PTD08A020W 3 x PTDO8A010W 38 pa 44 c 12V power input connector 6 pin Molex mini fit connector 39 d 12V power input connector 4 pin ATX disk type connector 39 22 l A i 2x6 DIP male pin header 34 connector 1 Virtex 6 XC6V LX240T 1FFG1156 A Virtex 6 XC6VLX240T 1FFG1156 FPGA is installed on the embedded development board Keep Out areas and drill holes are defined around the FPGA to support an Ironwood Electronics SG BGA 6046 FPGA socket Referenc es See the Virtex 6 FPGA data sheet at http www xilinx com support documentation virtex 6 htm Configuration The ML605 supports configuration in the following modes e Slave SelectMAP using Platform Flash XL with the onboard 47 MHz oscillator e Master BPI Up using Linear Flash BPI device e JTAG using the included USB A to Mini B cable e JTAG using System ACE CF and CompactFlash card ML605 Hardware User Guide UG534 v1 0 August 17 2009 www x
4. pg n H U8 n E W8 n a V8 n H L8 n e AE8 gt AD8 x AF8 H N8 n gt D22 H C22 x 21 H L20 i C18 H B18 H K22 H K21 fi AC22 AC24 AE22 AE23 AB23 AG23 AE24 AD24 AP24 AE21 AH27 n H AH28 n A AD21 n H 1G26 hi G17 A19 H ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 97 Appendix D ML605 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET GPIO SW S GPIO SW W IIC SCL DVI IIC SCL MAIN LS IIC SCL SFP IIC SDA DVI IIC SDA MAIN LS IIC SDA SFP LCD DB4 LS LCD DB5 LS LCD DB6 LS LCD DB7 LS LCD E LS LCD RS LS LCD RW LS P30 CS SEL PCIE 100M MGTO N PCIE 100M MGTO P PCIE 250M MGTI N PCIE 250M MGTI P PCIE PERST B LS PCIE RXO N PCIE RXO P PCIE RX1 N PCIE RX1 P PCIE RX2 N PCIE RX2 P PCIE RX3 N PCIE RX3 P PCIE RXA N PCIE RXA P PCIE RX5 N PCIE RX5 P PCIE RX6 N PCIE RX6 P PCIE RX7 N PCIE RX7 P PCIE TXO N PCIE TXO P PCIE TX1 N PCIE TX1 P PCIE TX2 N PCIE TX2 P PCIE TX3 N PCIE TX3 P PCIE TXA N PCIE TX4 P PCIE
5. On SFP Disabled Test Point J53 SFP MOD DETECT High Module Not Present Low Module Present Jumper J54 SFP RT SEL Jumper Pins 1 2 Full Bandwidth Jumper Pins 2 3 Reduced Bandwidth Test Point J51 SFP_LOS High Loss of Receiver Signal Low Normal Operation ML605 Hardware User Guide www xilinx com 35 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board Table 1 9 SFP Module Connections XILINX U1 FPGA Pin Schematic Netname P4 SFP Module Connector Pin E3 SFP RX P 13 E4 GER RX N 12 C3 SFP TX P 18 C4 SFP_TX_N 19 V23 SFP_LOS 8 AP12 SFP TX DISABLE 3 Notes 1 TheSFP TX Disable pin 3 is driven by transistor Q22 the base of which is driven by the FPGA signal GER TX DISABLE FPGA NET SFP RX P LOC E3 NET SFP_RX N LOC E4 NET SFP TX P LOC C3 NET SFP TX N LOC C4 NET SFP_LOS LOC V23 NET SFP TX DISABLE FPGA LOC AP12 Figure 1 18 UCF Location Constraints for SFP Module Connector 11 10 100 1000 Tri Speed Ethernet PHY The ML605 utilizes the onboard Marvell Alaska PHY device 88E1111 for Ethernet communications at 10 100 or 1000 Mb s The board supports MII GMI RGMII and SGMII interfaces from the FPGA to the PHY Table 1 10 The PHY connection to a user provided Ethernet cable is through a Halo HFJ11 1G01E RJ 45 connector with built in magnetics Table 1 10 PHY D
6. 59 19 VITA 57 1 FMC HPC Connector a esias ee nnn nee 60 20 VITA 57 1 FMC LPC Connector res 67 21 Power Management orere EELER get et aio E 70 AC Adapter and Input Power Jack Switch eee 70 Onboard Power Regulation 71 22 System MOnitot si si iii rl A FO e Sa 73 Configuration Options e ER o are a ERE REX VERE E E embers 78 Appendix A References Appendix B Default Switch and Jumper Settings Appendix C VITA 57 1 FMC Connections Appendix D ML605 Master UCF www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Preface About This Guide This manual accompanies the Virtex 6 FPGA ML605 Evaluation Board and contains information about the ML605 hardware and software tools Guide Contents This manual contains the following chapters e Chapter 1 ML605 Evaluation Board provides an overview of the embedded development board and details the components and features of the ML605 board e Appendix A References e Appendix B Default Switch and Jumper Settings e Appendix C VITA 57 1 FMC Connections Additional Support Resources To search the database of silicon and software questions and answers or to create a technical support case in WebCase see the Xilinx website at http www xilinx com support Conventions This document uses the following conventions An example illustrates each convention Typographical The follow
7. 36 35 CONFIG DCI CASCADE 26 25 Table 1 4 shows the connections and pin numbers for the DDR3 SODIMM Table 1 4 DDR3 SODIMM Connections U1 FPGA Pin Schematic Netname J1 SODIMM L14 DDR3_A0 98 A16 DDR3_A1 97 B16 DDR3_A2 96 E16 DDR3_A3 95 D16 DDR3_A4 92 J17 DDR3_A5 91 A15 DDR3_A6 90 B15 DDR3_A7 86 G15 DDR3_A8 89 F15 DDR3_A9 85 M16 DDR3_A10 107 M15 DDR3_A11 84 ML605 Hardware User Guide www xilinx com 15 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board 16 Table 1 4 DDR3 SODIMM Connections Cont d U1 FPGA Pin Schematic Netname J1 SODIMM H15 DDR3_A12 83 J15 DDR3_A13 119 D15 DDR3_A14 80 C15 DDR3_A15 78 K19 DDR3_BA0 109 J19 DDR3 BA1 108 L15 DDR3 BA2 79 J11 DDR3_D0 5 E13 DDR3_D1 7 F13 DDR3_D2 15 K11 DDR3_D3 17 L11 DDR3_D4 4 K13 DDR3_D5 6 K12 DDR3_D6 16 D11 DDR3_D7 18 M13 DDR3_D8 21 J14 DDR3_D9 23 B13 DDR3_D10 33 B12 DDR3_D11 35 G10 DDR3_D12 22 M11 DDR3_D13 24 C12 DDR3_D14 34 A11 DDR3_D15 36 G11 DDR3_D16 39 F11 DDR3_D17 41 D14 DDR3_D18 51 C14 DDR3_D19 53 G12 DDR3_D20 40 G13 DDR3_D21 42 F14 DDR3_D22 50 H14 DDR3_D23 52 C19 DDR3_D24 57 www xilinx com XILINX ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Table 1 4 DDR3 SODIMM Connections Conta
8. AH32 AH33 AD27 AE27 AE29 AE28 AH30 AH29 AG28 AG27 AD26 AD25 AK31 AL31 AF21 AF20 AL19 AK19 AD20 AC20 AD19 AC19 AE19 AF19 AH22 AG22 AG21 AG20 AJ21 AK21 AJ22 AK22 AL18 AM18 AL20 AM20 AN22 AM22 AL21 AM21 AN18 AP19 AN20 AN19 AL23 AM23 AN23 AP22 AM27 AN27 AJ25 AH25 AN24 AN25 AL24 ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 65 Chapter 1 ML605 Evaluation Board XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET FMC HPC LA20 P FMC HPC LA21 N FMC HPC LA21 P FMC HPC LA22 N FMC HPC LA22 P FMC HPC LA23 N FMC HPC LA23 P FMC HPC LA24 N FMC HPC LA24 Pn FMC HPC LA25 N FMC HPC LA25 P FMC HPC LA26 N FMC HPC LA26 P FMC HPC LA27 N FMC HPC LA27 P FMC HPC LA28 N FMC HPC LA28 P FMC HPC LA29 N FMC HPC LA29 P MC HPC LA30 N FMC_HPC_LA30_P FMC_HPC_LA31_N FMC_HPC_LA31_P FMC_HPC_LA32_N FMC HPC LA32 P FMC HPC LA33 N FMC HPC LA33 P y LOC AK23 LOC AP29 LOC AN29 LOC AP26 LOC AP27 LOC AM26 LOC AL26 LOC AM30 LOC AN30 LOC AM28 LOC AN28 LOC AL25 LOC AM25 LOC AP31 LOC AP30 LOC AJ2
9. L10 x M10 H AC8 i AM15 n 7 AJ17 AJ16 AP16 AG16 AH15 n H AF16 AN15 n ji AC15 ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 99 Appendix D ML605 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET SYSACE MPAOT SYSACE MPA02 SYSACE MPA03 SYSACE MPA04 SYSACE MPA05 SYSACE MPAO06 SYSACE MPBRDY SYSACE MPCE SYSACE MPIRQ SYSACE MPOE SYSACE MPWE SYSCLK N SYSCLK P USB 1 CTS USB 1 RTS USB 1 RX USB 1 TX USB An LS USB A1 LS USB CS B LS USB DO LS USB D1 LS USB D2 LS USB D3 LS USB DA LS USB D5 LS USB D6 LS USB D7 LS USB D8 LS USB D9 LS USB D10 LS USB D11 LS USB D12 LS USB D13 LS USB D14 LS USB D15 LS USB INT LS USB RD B LS B LS USB WR B LS USB RESET USER CLOCK USER SMA CLOCK N USER SMA CLOCK P USER SMA GPIO N USER SMA GPIO P VAUX CURR NI VAUX CURR P VAUX VOLT N VAUX VOLT P LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC
10. Prior to using the ML605 Evaluation Board users should be familiar with Xilinx resources See Appendix A References for a direct link to Xilinx documentation See the following locations for additional documentation on Xilinx tools and solutions e SE www xilinx com ise e EDK www xilinx com edk e Intellectual Property www xilinx com ipcenter e Answer Browser www xilinx com support 10 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description Detailed Description Figure 1 2 shows a board photo with numbered features corresponding to Table 1 1 and the section headings in this document IITIIII AS e fi e s ec FEGITSOA SE o Figure 1 2 ML605 Board Photo The numbered features in Figure 1 2 correlate to the features and notes listed in Table 1 1 Table 1 1 ML605 Features Number Feature Notes SE Page 1 Virtex 6 FPGA XC6VLX240T 1FFG1156 2 12 2 DDR 3 SODIMM Micron 512 MB MT4JSF6464HY 1G1 15 3 128 Mb Platform Flash XL Xilinx XCF128X FTG64C 25 4 Linear Flash BPI Numonyx JS28F256P30T95 26 System ACE CF controller CF Xilinx XCCACE TO144I 5 13 connector bottom of board 6 J TAG cable connector USB USB JTAG download circuit 46 Mini B ML605 Hardware User Guide www Xilinx com 11 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board 12 XILINX
11. AM5 H AP2 APL H APE i APS x AD5 H ADE hi AK5 H AK6 hi AF33 AE33 AC29 AD29 AC25 AB25 Y26 TAA25 n H AC28 AB28 AC27 ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 63 Chapter 1 ML605 Evaluation Board XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET FMC HPC HAO5 P FMC HPC HAO6 N FMC HPC HAO6 P FMC_HPC_HA07_N FMC_HPC_HA07_P FMC_HPC_HA08_N FMC_HPC_HA08_P FMC_HPC_HA09_N FMC_HPC_HA09_P FMC_HPC_HA10_N FMC_HPC_HA10_P FMC HPC HA11 N FMC HPC HA11 P FMC HPC HA12 N FMC HPC HA12 P FMC HPC HA13 N FMC HPC HA13 P FMC HPC HA14 N FMC HPC HA14 P FMC HPC HA15 N FMC HPC HA15 P FMC HPC HA16 N FMC HPC HA16 P FMC HPC HA17 CC N FMC HPC HA17 CC P FMC HPC HA18 N FMC HPC HA18 P FMC HPC HA19 N FMC HPC HA19 P FMC HPC HA20 N FMC HPC HA20 P FMC HPC HA21 N FMC HPC HA21 P FMC HPC HA22 N FMC HPC HA22 P FMC HPC HA23 N FMC HPC HA23 P FMC HPC HBOO CC N FMC HPC HBOO CC P FMC HPC HBO1 N FMC HPC HBO1 P FMC HPC HBO2 Hu FMC HPC HBO2 P FMC HPC HBO3 N FMC HPC HBO3 P FMC_HPC_HB04_N
12. D27 C25 C27 B28 D29 B27 G27 A28 E24 G25 F28 B31 H29 H28 B30 A30 E29 F29 E11 B11 E14 D19 B22 A26 A29 A31 Figure 1 4 UCF Location Constraints for DDR3 SDRAM Data I O Pins ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 21 Chapter 1 ML605 Evaluation Board XILINX Control Figure 1 5 provides the UCF constraints for the DDR3 SDRAM control pins NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET Figure 1 5 UCF Location Constraints for DDR3 CAS B DDR3 CKEO DDR3_CKE1 DDR3_CLKO_N DDR3 CLKO P DDR3_CLK1_N DDR3_CLK1_P DDR3_DQSO_N DDR3 DQSO P DDR3_DQS1_N DDR3 DQS1 P DDR3 DQS2 N DDR3 DQS2 P DDR3 DQS3 Nu DDR3 DQS3 P DDR3_DQS4_N DDR3_DQS4_P DDR3_DQS5_N DDR3 DQS5 P DDR3 DQS6 Nu DDR3 DQS6 P DDR3 DQS7 N DDR3 DQS7 P DDR3 ODTO DDR3 ODTI DDR3 RAS B DDR3 RESET B DDR3 S0 B DDR3 S1 B DDR3 WE B References A Micron compatible 512MB SODIMM MT4JSF6464HY 1G1 is provided with the ML605 A data sheet is available at http www micron com products partdetail part MT4J5F6464HY 1G1 DDR3_TEMP_EVENT LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC D
13. FMC HPC LA11 P FMC HPC LA12 N FMC HPC LA12 P FMC HPC LA13 N FMC HPC LA13 P FMC HPC LA14 N FMC HPC LA14 P FMC HPC LA15 Hu FMC HPC LA15 P FMC HPC LA16 N FMC HPC LA16 P FMC HPC LA17 CC N FMC HPC LA17 CC P FMC HPC LA18 CC N FMC HPC LA18 CC P FMC HPC LA19 N FMC HPC LA19 P FMC HPC LA20 N FMC HPC LA20 P FMC HPC LA21 N FMC HPC LA21 P FMC HPC LA22 N FMC HPC LA22 P FMC HPC LA23 N FMC HPC LA23 P FMC HPC LA24 N FMC HPC LA24 P FMC HPC LA25 N FMC HPC LA25 P FMC HPC LA26 N FMC HPC LA26 P FMC HPC LA27 N FMC HPC LA27 P FMC HPC LA28 N FMC HPC LA28 P FMC HPC LA29 N FMC HPC LA29 P FMC HPC LA30 N FMC HPC LA30 P FMC HPC LA31 N FMC HPC LA31 P FMC HPC LA32 N FMC HPC LA32 P FMC HPC LA33 N FMC HPC LA33 P FMC HPC PG M2C LS FMC HPC PRSNT M2C L FMC LPC CLKO M2C FMC LPC CLKO M2C P FMC LPC CLK1 M2C N LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC AJ21 AK21 AJ22 AK22 AL18 AM18 AL20 AM20 AN22 AM22 AL21 AM21 AN18 AP19 AN20 AN19 AL23 AM23 AN23 AP22 AM27 AN27 AJ25 AH25 n ji AN24 AN
14. GNO Nzwi duo quo dzwi avo quo Nzw1 ano Nam dow quo deoi gno quo Now GNO Neo drow quo dem GNO rhel N zov REI 99 Non dzo auo 99 Ament GNO QNO QNO ano QNO QNO QNO QNO duo Fe QNO f zZz am am am z rad z OO a a a a a a a El a a e ej ix AS E OO o o o O O e O O O O eo O Amt Om UG534_072009_27 FMC HPC Connector Pinout Figure 1 40 ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 62 XILINX Detailed Description NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET FMC HPC CLKO M2C N FMC HPC CLKO M2C P FMC HPC CLK1 M2C N FMC HPC CLK1 M2C P FMC HPC CLK2 M2C IO N FMC HPC CLK2 M2C IO P FMC HPC CLK2 M2C MGT C N FMC HPC CLK2 M2C MGT C P FMC HPC CLK3 M2C IO N FMC HPC CLK3 M2C IO P FMC HPC CLK3 M2C MGT C N FMC HPC CLK3 M2C MGT C P FMC HPC DPO C2M N FMC HPC DPO C2M P FMC HPC DPO M2C N FMC HPC DPO M2C P FMC HPC DP1 C2M N FMC HPC DP1 C2M P FMC HPC DP1 M2C N FMC HPC DP1 M2C P FMC HPC DP2 C2M N
15. H15 i 1J15 H D15 C15 H K19 J19 x 215 H O17 i M18 H M17 x H18 h G18 L16 H K16 J11 E13 i F13 A K11 H L11 hi K13 H K12 hi D11 H M13 J14 H B13 A ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 89 Appendix D ML605 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET DDR3 D11 DDR3 D12 DDR3 D13 DDR3 D14 DDR3 D15 DDR3 D16 DDR3 D17 DDR3 D18 DDR3 D19 DDR3 D20 DDR3 D21 DDR3 D22 DDR3 D23 DDR3 D24 DDR3 D25 DDR3 D26 DDR3 D27 DDR3 D28 DDR3 D29 DDR3 D30 DDR3 D31 DDR3 D32 DDR3 D33 DDR3 D34 DDR3 D35 DDR3 D36 DDR3 D37 DDR3 D38 DDR3 D39 DDR3 D40 DDR3 D41 DDR3 D42 DDR3 D43 DDR3 D44 DDR3 D45 DDR3 D46 DDR3 D47 DDR3 D48 DDR3 D49 DDR3 D50 DDR3 D51 DDR3 D52 DDR3 D53 DDR3 D54 DDR3 D55 DDR3 D56 DDR3 D57 DDR3 D58 DDR3 D59 DDR3 D60 DDR3 Dein DDR3 D62 DDR3 D63 DDR3 DMO DDR3 DM1 DDR3 DM2 DDR3 DM3 DDR3 DM4 DDR3 DM5 LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LO
16. NET NET NET NET NET NET NET NET NET NET NET NET NET NET FMC LPC LA25 N FMC LPC LA25 P FMC LPC LA26 N FMC LPC LA26 P FMC LPC LA27 N FMC LPC LA27 P FMC LPC LA28 N FMC LPC LA28 P FMC LPC LA29 N FMC LPC LA29 P FMC LPC LA30 N FMC LPC LA30 P FMC LPC LA31 N FMC LPC LA31 P FMC LPC LA32 N FMC LPC LA32 P FMC LPC LA33 N FMC LPC LA33 P FMC LPC PRSNT M2C L FPGA CCLK FPGA DONE FPGA DX N FPGA DX P FPGA FCS B FPGA FOE B FPGA FWE B FPGA INIT B FPGA MO FPGA M1 FPGA M2 FPGA PROG B FPGA TCK FPGA TDI FPGA TMS FPGA VBATT GPIO DIP SWI GPIO DIP SW2 GPIO DIP SW3 GPIO DIP SWa GPIO DIP SW5 GPIO DIP SW6 GPIO DIP SW7 GPIO DIP SW8 GPIO LED 0 GPIO LED 1 GPIO LED 2 GPIO LED 3 GPIO LED 4 GPIO LED 5 GPIO LED 6 GPIO LED 7 GPIO LED C GPIO LED E GPIO LED N GPIO LED S GPIO LED W GPIO SW C GPIO SW E GPIO SW N LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC P30 P31 M32 33 RD R3JI M33 N33 p34 N34 M27 M26 L31 M31 M25 N2514 K31 E3215 ADO K8 UE R8 d W17 W18 Wy 24 s AA24 AF23
17. W ty3 9 s ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 93 Appendix D ML605 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET FMC HPC HA21 P FMC HPC HA22 N FMC HPC HA22 P FMC HPC HA23 N FMC HPC HA23 P FMC HPC HBOO CC N FMC HPC HBOO CC P FMC HPC HBO1 N FMC HPC HBO1 P FMC HPC HBO2 N FMC HPC HBO2 P FMC HPC HBO3 N FMC HPC HBO3 P FMC_HPC_HB04_N FMC_HPC_HB04_P FMC_HPC_HB05_N FMC_HPC_HB05_P FMC_HPC_HB06_CC_N FMC_HPC_HB06_CC_P FMC_HPC_HB07_N FMC_HPC_HB07_P FMC_HPC_HB08_N FMC_HPC_HB08_P FMC_HPC_HB09_N FMC_HPC_HB09_P FMC_HPC_HB10_N FMC_HPC_HB10_P FMC_HPC_HB11_N FMC_HPC_HB11_P FMC_HPC_HB12_N FMC_HPC_HB12_P FMC_HPC_HB13_N FMC_HPC_HB13_P FMC_HPC_HB14_N FMC_HPC_HB14_P FMC_HPC_HB15_N FMC HPC HB15 P FMC HPC HB16 N FMC HPC HB16 P FMC HPC HB17 CC N FMC HPC HB17 CC P FMC HPC HB18 N FMC HPC HB18 P FMC HPC HB19 N FMC HPC HB19 P FMC HPC LAO0 CC N FMC HPC LAO0 CC P FMC HPC LAO1 CC N FMC HPC LAO1 CC P FMC HPC LAO2 Hu FMC HPC LAO2 P FMC HPC LAQ3 Hu FMC HPC LAQ3 P FMC HPC LAO4 N FMC HPC LAQA P FMC H
18. A A da oi 29 7 Clock Generation LL 30 Oscillator Differential ds eda copa ds E age iii a ead 30 Oscillator Socket Single Ended 2 5V sese 30 SMA Connectors Differential lesse ee 30 8 Multi Gigabit Transceivers GTX MCGTa e 31 9 PCI Express Endpoint Connectivity LL 32 10 SFP Module Connector 35 11 10 100 1000 Tri Speed Ethernet DIN 36 SGMII GTX Transceiver Clock Generation eee 37 12 USB to UART Bridge cerise ke ere ne read reese red e 40 13 USB Controller cere Re ncm a ERA E 41 14 DVI a ii 43 15 JIE Bus ii A y bee ANNA A falena 44 SKB NV Memory essee rinane deen ee e ate ree pert erp etd use st pus 46 16 Status LEDS 22 ke RM e a a 47 Ethernet PHY Status LEDs cee eee nee en 47 FPGA INIT and DONELEDs esee 3 hls 48 17 User ILO x rete REV pr u Gab ess 49 User LEIS 3 uet leali elia PRE 50 User Pushbutton Switches 51 User DIP Switch cesare eee RE ERR a YR EG a px darse 52 User SMA GPIO WEEN 53 LCD Display 16 Character x 2 Lines 54 ML605 Hardware User Guide www xilinx com UG534 v1 0 August 17 2009 XILINX 18 5WiItch Ss prete a ta 56 Power On Off Slide Switch GW 56 FPGA PROG B Pushbutton SW4 Active Low 0c cece eee eee eens 57 SYSACE RESET B Pushbutton SW3 hchve Lowi eee ee eens 57 System ACE CF CompactFlash Image Select DIP Switch SI Lee 58 MODE Boot EEPROM Select and CCLK Osc Enable DIP SW S2
19. Adapter PMBus pod and associated TI GUI References For more detailed information about this technology and the various power management controllers and regulator modules offered by Texas Instruments visit http www ti com ww en analog digital power index html 72 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description 22 System Monitor The System Monitor provides information regarding the FPGA on chip temperature and power supply conditions via JTAG and an internal FPGA interface The System Monitor can also be used to monitor external analog signals via 17 external analog input channels For more information regarding this functionality which is featured on every Virtex 6 family member see http www xilinx com systemmonitor This section provides a brief overview of the System Monitor related functionality that is supported on the ML605 Reference and Power Supply The System Monitor has dedicated analog power supply pins and supports the use of an external 1 25V reference IC U23 for the analog to digital conversion process An option using jumper J19 to select an on chip reference is also provided however the highest accuracy over a temperature range of 40 C to 125 C is obtained using an external reference Figure 1 45 illustrates the power supply and reference options on the ML605 For a more detailed discussion of these requirements see UG370 Xilinx UG370 Virtex 6 F
20. C17 d M18 H M17 H H18 d G18 H L16 A K16 E12 D12 H J12 H H12 A A14 A123 H20 H19 H C23 H B23 d A25 H B25 H 328 H27 A D30 H C30 A F18 E17 H L19 E18 H K18 K17 d D17 H B17 DR3 SDRAM Control Pins In addition see the Virtex 6 FPGA Memory Interface Solutions user guide at http www xilinx com support documentation ip_documentation ug406 pdf Also see the Virtex 6 FPGA Memory Resources User Guide at http www xilinx com support documentation user_guides ug363 pdf 22 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description 3 Platform Flash XL 128 Mbit 4 Linear FPGA U1 Bank 34 S2 SWITCH 6 ON U4 BPI Upper Half OFF U4 BPI Lower Half FLASH_A 2 FPGA U1 omnes Bank 24 VCC2V5 510 2 S2 6 7 8 A 128 Mb Xilinx XCF128X FTG64C Platform Flash XL device is used with an onboard 47 MHz oscillator to configure the FPGA in less than 100 ms from power valid as required by the PCI Express Card Electromechanical Specification This allows the PCle interface to be recognized and enumerated when plugged into a host PC To achieve the fastest configuration speed the FPGA mode pins are set to Slave SelectMAP and the onboard 47 MHz clock source external to the EPGA is used for configuration Configuration DIP switch S2 switch 1 controls the 4
21. LPC LA32 N M25 88 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX ML605 Master UCF Appendix D The UCF template is provided for designs that target the ML605 Net names provided in the constraints below correlate with net names on the ML605 rev C schematic On identifying the appropriate pins the net names below should be replaced with net names in the user RTL See the Constraints Guide for more information NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET CLK_33MHZ SYSACE CPU_RESET DDR3 CI DDR3 CI DDR3 CI DDR3_A0 DDR3_A1 DDR3 A2 DDR3 A3 DDR3 A4 DDR3 A5 DDR3 A6 DDR3 A7 DDR3 A8 DDR3 A9 DDR3 A10 DDR3 A11 DDR3 A12 DDR3 A13 DDR3 A14 DDR3 A15 DDR3_ BAO DDR3_BA1 DDR3 BA2 DDR3 CAS RB DDR3 CKEO DDR3_CKE1 DDR3_CLKO_N LEO P LKI N LKI P DDR3 DO DDR3_D1 DDR3_D2 DDR3_D3 DDR3 D4 DDR3 D5 DDR3 D6 DDR3 D7 DDR3_D8 DDR3_D9 DDR3_D10 LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC AE16 H10 L14 s A16 B16 El6 D16 s J17 H A15 x B15 hi G15 n F15 H M16 x M15 H
22. P FMC LPC LA15 Hu FMC LPC LA15 P FMC LPC LA16 N FMC LPC LA16 P FMC LPC LA17 CC N FMC LPC LA17 CC P FMC LPC LA18 CC N FMC LPC LA18 CC P FMC LPC LA19 N FMC LPC LA19 P FMC LPC LA20 N FMC LPC LA20 P FMC LPC LA21 N FMC LPC LA21 P FMC LPC LA22 N FMC LPC LA22 P FMC LPC LA23 N FMC LPC LA23 P FMC LPC LA24 N FMC LPC LA24 P LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC P33 D2 Tos DNs G4 Mes 33 n M5 nos M6 ns AF13 AG13 E27 K26 E31 E31 H30 G31 te J31 J29 K28 4331 H34 J34 WKS oles WH32 G32 K29 g30 L26 L25 G30 F30 D32 n D31 E33 E32 C34 D34 B34 Wer gms B321 tea i CC AS A33 N29 N28 L30 L29 N30 M30 R29 p29 T26 R26 p27 N27 MRO R28 p32 N32 96 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET
23. PMBus voltage and current monitoring via TI power controller System monitor Configuration methods Platform Flash XL BPI Linear Flash System ACE CF JTAG USB www xilinx com 9 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board XILINX Block Diagram Figure 1 1 shows a high level block diagram of the ML605 and its peripherals SYSTEM ACE CF S A CompactFlash S A 8 bit MPU I F JTAG USB MINI B USB JTAG CIRCUIT VITA 57 1 FMC HPC Connector VITA 57 1 FMC LPC Connector PLATFORM FLASH LINEAR FLASH BPI DVI CODEC VGA VIDEO DVI VIDEO CONN 10 100 1000 Ethernet PHY MII GMII RMII SODIMM Socket 204 pin DDR3 Decoupling Caps BANK32 BANK24 BANK34 BANK32 BANK33 BANK 25 35 BANK 26 36 BANK36 BANK24 34 BANK12 13 BANK15 16 BANK14 22 BANK34 116 BANK23 24 BANK112 113 BANKO BANK33 BANK34 Virtex 6 FPGA XC6VLX240T 1FFG1156 BANK116 BANK114 BANK116 BANK14 BANK24 SYSMON I F INIT DONE LEDs PROG PB MODE SW IIC BUS IIC EEPROM FMC HPC DDR3 SODIMM IIC FMC LPC SFP MODULE CONNECTOR SGMII PCle X8 EDGE CONN MGT SMA REF CLOCK MGT RX TX SMA PORT USER LED SW USER DIP SW 200MHZ LVDS CLOCK SMA CLOCK USER S E 2 5V CLOCK USB CONTROLLER HOSE TYPE A PERIP MINI B CONNECTORS CP2103 USB TO UART BRIDGE USB MINI B MEM Vterm Regulator UG534_01_081109 Figure 1 1 ML605 High Level Block Diagram Related Xilinx Documents
24. The red INIT LED DS31 comes on momentarily after the FPGA powers up and during its internal power on process The DONE LED DS13 comes on after the FPGA programming bitstream has been downloaded and the FPGA successfully configured VCC2V5 VCC2V5 FPGA INIT B FPGA_DONE NDS336P LED RED SMT OLED RED SMT o JJ A 27 4 1 1 16W UG534_06_072109 Figure 1 27 FPGA INIT and DONE LEDs Table 1 19 FPGA INIT and DONE LED Connections Controlled LED Schematic FPGA U1 Pin Netname DS31 INIT Red FPGA_INIT_B P8 DS13 DONE Green FPGA_DONE R8 NET FPGA INIT B LOC P8 NET FPGA DONE i LOC RE Figure 1 28 UCF Location Constraints for FPGA INIT B and FPGA_DONE 48 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX 17 User I O Detailed Description The ML605 provides the following user and general purpose I O capabilities User LEDs 8 with parallel wired GPIO male pin header User Pushbutton 5 switches with associated direction LEDs CPU Reset pushbutton switch User DIP switch 8 pole User SMA GPIO LCD Display 16 char x 2 lines Note All GPIO location constraints are collected in one partial UCF at the end of the section ML605 Hardware User Guide www xilinx com 49 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board XILINX User LEDs The ML605 provides two groups of active High LEDs as described in Figure 1 29
25. Xilinx Platform Flash XL data sheet for more information at http www xilinx com support documentation data sheets ds617 pdf In addition see the Xilinx Virtex 6 Configuration User Guide for more information at http www xilinx com support documentation user guides ug360 pdf 5 Xilinx System ACE CF and CompactFlash Connector The Xilinx System ACE CompactFlash CF configuration controller allows a Type I or Type II CompactFlash card to program the FPGA through the JTAG port Both hardware and software data can be downloaded through the JTAG port The System ACE CF controller supports up to eight configuration images on a single CompactFlash card The configuration address switches allow the user to choose which of the eight configuration images to use The CompactFlash CF card shipped with the board is correctly formatted to enable the System ACE CF controller to access the data stored in the card The System ACE CF controller requires a FAT16 file system with only one reserved sector permitted and a sector per cluster size of more than one UnitSize greater than 512 The FAT16 file system supports partitions of up to 2 GB If multiple partitions are used the System ACE CF directory structure must reside in the first partition on the CompactFlash with the xilinx sys file located in the root directory The xilinx sys file is used by the System ACE CF controller to define the project directory structure which consists of one mai
26. and Table 1 20 GPIO LED 0 GPIO LED 2 GPIO LED 3 GPIO LED 4 GPIO LED 5 GPIO LED 6 GPIO LED 7 00000000 LED GRN SMT LED GRN SMT LED GRN SMT LED GRN SMT LED GRN SMT o o o 9 R12 27 4 1 1 16W GPIO LED C GPIO LED W GPIO LED E GPIO LED S GPIO LED N This group of LEDs is mounted adjacent to their respective direction al M al push buttons as seen on the right side e co 2 n of the LCD on the board photo Figure Syxl amp 8 Bele amp x E ABE 1 2 A 1 XD FIG FIG AE H z z z z z tc tc e tc tc 9 9 9 9 9 a a a a a zi zs zu E RE g g g 8 a g g g g E Mrs 1 ria 1 Ris 1 Rie enz o o o o 27 4 27 4 27 4 27 4 27 4 1 1 1 1 1 2 1 16W 2 1 16W 2 1 16W 2 1 16W 2 1 16W UG534_07_081109 Figure 1 29 User LEDs and GPIO Connector Directional LEDs Note See User Pushbutton Switches page 51 for more details about the LEDs 50 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description Table 1 20 User LED Connections Controlled LED Schematic Netname GPIO J62 Pin FPGA U1 Pin DS12 GPIO LED 0 1 AC22 DS11 GPIO LED 1 2 AC24 DS9 GPIO LED 2 3 AE22 DS10 GPIO LED 3 4 AE23 DS15 GPIO LED 4 5 AB23 DS14 GPIO LED 5 6 AG23 DS22 GPIO LED 6 7 AE24 DS21 GPIO LED 7 8 AD24 DS16 GPIO LED C AP24 DS17 GPIO_LED_W AD21 DS19 GPIO LED E AE21 DS18 GPIO LED S AH28 DS20 GPIO LED N
27. block reset signal Notes PCIE TXn P N pairs are capacitively coupled to FPGA PCIE 100M MGTO P N pairs are capacitively coupled to FPGA PCIE 250M MGTI P N pairs are capacitively coupled to FPGA PCIE PERST B is level shifted by U32 For ML605 access is through MGT Banks 114 and 115 D vs WN r The PCIe interface obtains its power from the DC power supply provided with the ML605 or through the 12V ATX power supply connector The PCIe edge connector is not used for any power connections The board can be powered by one of two 12V sources J60 a 6 pin 2x3 molex type connector and J25 a 4 pin inline ATX disk drive type connector The 6 pin molex type connector provides 60W 12V 5A from the AC power adapter provided with the board while the 4 pin ATX disk drive connector is provided for users who want to power their board while it is installed inside a PC chassis For applications requiring additional power such as the use of expansion cards drawing significant power a larger AC adapter might be required If a different AC adapter is used its load regulation should be better than 10 ML605 power switch SW2 turns the board on and off by controlling the 12V supply to the board Caution Never apply power to the power brick connector J60 and the 4 pin ATX disk drive connector J25 at the same time as this will result in damage to the board See Figure 1 35 page 56 Never connect an auxiliary PCle 6 pin molex power c
28. the ML605 board is summarized in Table 1 3 Table 1 3 Voltage Rails U1 FPGA Bank HO Rail Voltage BANK 0 VCC2V5 FPGA 2 5V BANK 12 FMC VIO B M2C 2 5V BANK 13 VCC2V5 FPGA 2 5V BANK 14 VCC2V5 FPGA 2 5V BANK 15 VCC2V5 FPGA 2 5V BANK 16 VCC2V5 FPGA 2 5V BANK 22 VCC2V5 FPGA 2 5V BANK 23 VCC2V5 FPGA 2 5V BANK 24 VCC2V5 FPGA 2 5V BANK 25 VCC1V5_FPGA 1 5V 14 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description Table 1 3 Voltage Rails U1 FPGA Bank HO Rail Voltage BANK 26 VCC1V5_FPGA 1 5V BANK 32 VCC2V5 FPGA 2 5V BANK 33 VCC2V5 FPGA 2 5V BANK 34 VCC2V5 FPGA 2 5V BANK 35 VCC1V5_FPGA 1 5V BANK 36 VCC1V5_FPGA 1 5V References See the Xilinx Virtex 6 FPGA documentation for more information at http www xilinx com support documentation virtex 6 htm 2 512 MB DDR3 Memory SODIMM A 512MB DDR3 SODIMM is provided as a flexible and efficient form factor volatile memory for user applications The ML605 SODIMM socket is wired to support a maximum SODIMM size of 2 GB The ML605 DDR3 64 bit wide interface has been tested to 800 MT s The DDR3 interface is implemented in FPGA banks 25 26 35 and 36 DCI VRP N resistor connections are only implemented banks 26 and 36 DCI functionality in banks 25 and 35 is achieved in the UCF by cascading DCI between adjacent banks as follows CONFIG DCI CASCADE
29. 06_CC_P AF26 J28 FMC HPC HB07 N AH34 K29 FMC HPC HB06 CC N AE26 J30 FMC_HPC_HB11_P AJ29 K31 FMC_HPC_HB10_P AF28 J31 FMC_HPC_HB11_N AJ30 K32 FMC_HPC_HB10_N AF29 J33 FMC_HPC_HB15_P AE28 K34 FMC HPC HB14 P AE27 J34 FMC_HPC_HB15_N AE29 K35 FMC HPC HB14 N AD27 J36 FMC_HPC_HB18_P AD25 K37 FMC_HPC_HB17_CC_P AG27 J37 FMC_HPC_HB18_N AD26 K38 FMC_HPC_HB17_CC_N AG28 86 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Table C 2 VITA 57 1 FMC LPC Connections hh Schematic Netname a E M E Schematic Netname di du C2 FMC LPC DPO C2M P DI D4 FMC LPC GBTCLKO M2C P M6 C3 FMC_LPC_DP0_C2M_N D2 D5 FMC LPC GBTCLKO M2C N M5 C6 FMC LPC DPO M2C P F33 D8 FMC_LPC_LA01_CC_P F31 C7 FMC_LPC_DP0_M2C_N G33 D9 FMC_LPC_LA01_CC_N E31 C10 FMC_LPC_LA06_P K33 D11 FMC LPC LA05 P H34 C11 FMC LPC LAO06 N J34 D12 FMC_LPC_LA05_N H33 C14 FMC LPC LA10 P F30 D14 FMC_LPC_LA09_P L25 C15 FMC_LPC_LA10_N G30 D15 FMC_LPC_LA09_N L26 C18 FMC_LPC_LA14 P C33 D17 FMC LPC LA13 P D34 C19 FMC LPC LA14 N B34 D18 FMC LPC LA13 N C34 C22 FMC LPC LA18 CC P L29 D20 FMC LPC LA17 CC P N28 C23 FMC LPC LA18 CC N L30 D21 FMC LPC LA17 CC N N29 C26 FMC LPC LA27 P R31 D23 FMC LPC LA23 P R28 C27 FMC LPC LA27 N R32 D24 FMC LPC LA23 N R27 D26 FMC LPC LA26 P L33 D27
30. 137 A25 DDR3_DQS5_N 152 B25 DDR3_DQS5_P 154 G28 DDR3_DQS6_N 169 H27 DDR3_DQS6_P 171 D30 DDR3_DQS7_N 186 C30 DDR3_DQS7_P 188 F18 DDR3_ODTO 116 www xilinx com XILINX ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Table 1 4 DDR3 SODIMM Connections Conta U1 FPGA Pin Schematic Netname J1 SODIMM E17 DDR3_ODT1 120 E18 DDR3_RESET_B 30 K18 DDR3_S0_B 114 K17 DDR3_S1_B 121 D17 DDR3_TEMP_EVENT 198 B17 DDR3_WE_B 113 C17 DDR3_CAS_B 115 L19 DDR3_RAS_B 110 M18 DDR3 CKEO 73 M17 DDR3_CKE1 74 H18 DDR3 CLKO N 103 G18 DDR3 CLKO P 101 L16 DDR3 CLKI N 104 K16 DDR3_CLK1_P 102 Detailed Description The Memory Interface Generator MIG tool guidelines specify a set of Ul FPGA No Connect pins as follows H22 F21 B20 F19 C13 M12 L13 K14 F25 C29 C28 D24 These should be added to the UCF as CONFIG PROHIBIT pins CONFIG CONFIG CONFIG CONFIG W dm tg CONFIG CONFIG CONFIG CONFIG tg U tg tg CONFIG Wel ROHIBIT H22 ROHIBIT F21 ROHIBIT B20 ROHIBIT F19 ROHIBIT C13 ROHIBIT M12 ROHIBIT L13 ROHIBIT K14 ROHIBIT F25 CONFIG PROHIBIT C29 CONFIG PROHIBIT C28 ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 19 Chapter 1 ML605 Evaluation Board XILINX CONFIG PROHIBIT D24 Figure 1 3 provides the user constraints file
31. 25 AL24 AK23 AP29 AN29 AP26 AP27 AM26 AL26 AM30 AN30 AM28 AN28 AL25 AM25 AP31 AP30 AJ27 AK27 AK28 AL28 AK24 AJ24 AK29 AL29 AG26 AG25 TAH24 n 7 AH23 n E g275 AP25 B10 A10 G33 ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 95 Appendix D ML605 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET FMC LPC CLK1 M2C P FMC LPC DPO C2M N FMC LPC DPO C2M P FMC LPC DPO M2C N FMC LPC DPO M2C P FMC LPC GBTCLKO M2C N FMC LPC GBTCLKO M2C P FMC LPC IIC SCL LS FMC LPC IIC SDA LS FMC LPC LAO0 CC N FMC LPC LAO0 CC P FMC LPC LAO1 CC N FMC LPC LAO1 CC P FMC LPC LAO2 Hu FMC LPC LAO2 P FMC LPC LAQ3 Hu FMC LPC LAQ3 P FMC_LPC_LA04_N FMC_LPC_LA04_P FMC_LPC_LA05_N FMC_LPC_LA05_P FMC_LPC_LA06_N FMC_LPC_LA06_P FMC_LPC_LA07_N FMC_LPC_LA07_P FMC_LPC_LA08_N FMC_LPC_LA08_P FMC_LPC_LA09_N FMC_LPC_LA09_P FMC_LPC_LA10_N FMC LPC LA10 P FMC LPC LA11 N FMC LPC LA11 P FMC LPC LA12 N FMC LPC LA12 P FMC LPC LA13 N FMC LPC LA13 P FMC LPC LA14 N FMC LPC LA14
32. 28 P LOC N33 NET FMC LPC LA29 N LOC P34 NET FMC LPC LA29 P LOC N34 NET FMC LPC LA30 N LOC M27 NET FMC LPC LA30 P LOC M26 NET FMC LPC LA31 N LOC L31 NET FMC LPC LA31 P LOC M31 NET FMC LPC LA32 N LOC M25 NET FMC LPC LA32 P LOC N25 NET FMC LPC LA33 N LOC K31 NET FMC LPC LA33 P LOC K32 NET FMC LPC PRSNT M2C L LOC AD9 Figure 1 43 UCF Location Constraints for FMC LPC Connector J63 References Datasheets for the ROHS compliant FMC HPC Samtec SeaRay connector Carrier side socket ASP 134486 01 Module side plug ASP 134488 01 can be found on the Samtec web site at http www samtec com search vita57fmc aspx The high speed characterization report for this connector system can be found at http www samtec com ftppub testrpt HSC REPORT_SEAM SEAF 10MM_WEB pdf 21 Power Management AC Adapter and Input Power Jack Switch The ML605 is powered from a 12V source that is connected through a 6 pin 2X3 right angle Mini Fit type connector J60 The AC to DC power supply included in the kit has a mating 6 pin plug When the ML605 is installed into a table top or tower PC s PCIe slot the ML605 is typically powered from the PC ATX power supply One of the ATX hard disk type 4 pin power connectors is plugged into ML605 connector J25 The ML605 can be powered with the AC power adapter even when plugged into a PC PCIe motherboard slot however users are cautio
33. 2_M2C_N AF6 B17 FMC_HPC_DP6_M2C_N AM6 A10 FMC HPC DP3 M2C P AG3 B20 FMC_HPC_GBTCLK1_M2C_P AK6 All FMC_HPC_DP3_M2C_N AG4 B21 FMC_HPC_GBTCLK1_M2C_N AK5 A14 FMC HPC DP4 M2C P AJ3 B32 FMC_HPC_DP7_C2M_P API A15 FMC HPC DP4 M2C N AJ4 B33 FMC_HPC_DP7_C2M_N AP2 A18 FMC_HPC_DP5_M2C_P AL3 B36 FMC_HPC_DP6_C2M_P AN3 A19 FMC_HPC_DP5_M2C_N AL4 B37 FMC_HPC_DP6_C2M_N AN4 A22 FMC_HPC_DP1_C2M_P AD1 A23 FMC_HPC_DP1_C2M_N AD2 A26 FMC_HPC_DP2_C2M_P AF1 A27 FMC_HPC_DP2_C2M_N AF2 A30 FMC_HPC_DP3_C2M_P AH1 A31 FMC_HPC_DP3_C2M_N AH2 A34 FMC_HPC_DP4_C2M_P AK1 A35 FMC_HPC_DP4_C2M_N AK2 A38 FMC_HPC_DP5_C2M_P AM1 A39 FMC_HPC_DP5_C2M_N AM2 C2 FMC_HPC_DP0_C2M_P AB1 D4 FMC_HPC_GBTCLKO_M2C_P AD6 C3 FMC HPC DPO C2M N AB2 D5 FMC HPC GBTCLKO M2C N AD5 ML605 Hardware User Guide www xilinx com 83 UG534 v1 0 August 17 2009 Appendix C VITA 57 1 FMC Connections XILINX Table C 1 VITA 57 1 FMC HPC Connections Cont d Sri Schematic Netname wi n ECCE Schematic Netname et zen C6 FMC HPC DPO M2C P AC3 D8 FMC_HPC_LA01_CC_P AK19 C7 FMC_HPC_DP0_M2C_N ACA D9 FMC HPC LAO1 CC N AL19 C10 FMC HPC LA06 P AG20 D11 FMC_HPC_LA05_P AG22 C11 FMC_HPC_LA06_N AG21 D12 FMC_HPC_LA05_N AH22 C14 FMC_HPC_LA10_P AM20 D14 FMC_HPC_LA09_P AM18 C15 FMC_HPC_LA10_N AL20 D15 FMC_HPC_LA09_N AL18 C18 FMC_HPC
34. 7 LOC AK27 LOC AK28 LOC AL28 LOC AK24 LOC AJ24 LOC AK29 LOC AL29 LOC AG26 LOC AG25 LOC AH24 LOC AH23 FMC HPC PG M2C LS NET FMC HPC PRSNT M2C L Figure 1 41 LOC J27 LOC AP25 UCF Location Constraints for FMC HPC Connector J64 Table 1 27 Power Supply Voltages for HPC Connector Voltage Supply Eo reos No Pins Max Amps Tolerance Max E VADJ 0 3 3V 4 5 1000 uF VIO_B_M2C 0 VADJ 1 15 5 500 uF VREF_A_M2C 0 VADJ 1mA 2 10 uF VREF_B_M2C 0 VIO_B_M2C 1mA t 2 10 uF 3P3VAUX 3 3V 20mA 5 150 uF 3P3V 3 3V 3 5 1000 uF 12POV 12V 1 5 1000 uF 66 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description 20 VITA 57 1 FMC LPC Connector The ML605 implements both the High Pin Count HPC J64 and Low Pin Count LPC J63 connector options of VITA 57 1 1 FMC specification This section discusses the FMC LPC J63 connector The FMC standard calls for two connector densities a High Pin Count HPC and a Low Pin Count LPC implementation A common 10 x 40 position 400 pin locations connector form factor is used for both versions The HPC version is fully populated with 400 pins present and the LPC version is partially populated with 160 pins The 10 x 40 rows of a FMC LPC connector provides connectivity for e 68 singl
35. 7 MHz oscillator enable as outlined in 18 Switches page 56 See S2 switch setting details in Table 1 25 page 59 Also see the FPGA Design Considerations for the Configuration Flash page 27 for FPGA design recommendations Flash BPI P30 A Numonyx JS28F256P30 Linear Flash memory on the ML605 provides 32MB of non volatile storage that can be used for configuration as well as software storage The Linear Flash is connected to the FPGA configuration pins in parallel with the Platform Flash XL A DIP switch is provided to select configuration from either the Linear Flash or the Platform Flash XL See S2 switch setting details in Table 1 25 page 59 For an overview on configuring the FPGA see Configuration Options page 78 Figure 1 6 shows a block diagram for the Platform Flash and BPI Flash U27 PLATFORM FLASH FLASH_DI15 0 Esc Uy VCC2V5 Bank 24 PLATFLASH FCS B VCC2V5 919 3 ee S2 SWITCH 2 o ON U4 BOOT OFF U27 BOOT VCC2V5 FPGA FCS B FPGAUT1 Bank 24 FLASH CE B UG534 03 081209 Figure 1 6 Platform Flash and BPI Flash Block Diagram ML605 Hardware User Guide www xilinx com 23 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board 24 ML605 Flash Boot Options The ML605 has two parallel wired flash memory devices as shown in Figure 1 6 At ML605 power up before FPGA configuration DIP switch S2 switch 2 selects which flash device
36. AH27 User Pushbutton Switches The ML605 provides six active High pushbutton switches e SW5 SW6 SW7 SW8 and SW9 arranged in a diamond configuration to depict directional headings North South East West and Center respectively e SW10 CPU Reset pushbutton The six pushbuttons all have the same active High topology as the sample shown in Figure 1 30 The five directional pushbuttons are assigned as GPIO and the sixth is assigned as CPU_RESET Figure 1 30 and Table 1 21 describe the pushbutton switches VCC1V5 Pushbutton CPU RESET UG534 08 072109 Figure 1 30 User Pushbutton Switch Typical ML605 Hardware User Guide www xilinx com 51 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board XILINX Table 1 21 User Pushbutton Switch Connections poni Schematic Netname U1 FPGA Pin SW5 2 GPIO_SW_N A19 SW6 2 GPIO SW S A18 SW7 2 GPIO_SW_E G17 SW8 2 GPIO SW W H17 SW9 2 GPIO SW C G26 SW10 2 CPU RESET H10 User DIP Switch The ML605 includes an active High eight pole DIP switch as described in Figure 1 31 and Table 1 22 VCC1V5 GPIO DIP SW2 GPIO DIP SW3 GPIO DIP SW4 GPIO DIP SW5 GPIO DIP SW6 GPIO DIP SW7 GPIO DIP SW8 UG534_09_072109 Figure 1 31 User 8 pole DIP Switch Table 1 22 User DIP Switch Connections DIP Switch Pin Schematic Netname U1 FPGA Pin SW1 1 GPIO DIP SW1 D22
37. ASH A11 FLASH A12 FLASH A13 FLASH A14 FLASH A15 FLASH A16 FLASH A17 FLASH A18 FLASH A19 FLASH A20 FLASH A21 FLASH A22 FLASH A23 FLASH DO FLASH D1 FLASH D2 FLASH D3 FLASH D4 FLASH D5 FLASH D6 FLASH D7 FLASH D8 FLASH D9 FLASH D10 FLASH D11 FLASH D12 FLASH D13 FLASH D14 FLASH D15 FPGA FWE B FPGA FOE B FPGA CCLK FLASH WAIT PLATFLASH L B FPGA FCS B LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC ATIS H AK8 H ACI x AD10 C8 n i B8 n H9 n E8 n d A8 n n A9 d pg n ag i D10 H C10 F10 bon i AH8 x AG8 H apg i ANI H AF10 AF9 s ALI i AA23 AF24 AF25 W24 V24 H24 WH25 7 p24 R24 G23 H23 N24 N23 E23 os E24 L24 M23 J26 AF23 An24 n K8 n H AC23 Y24 Figure 1 7 UCF Location Constraints for Flash Memory Connections 26 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description FPGA Design Considerations for the Configuration Flash After FPGA configuration the FPGA design can disable the configuration flash or access the configuration flas
38. B specifications for more information at http www usb org developers docs The FPGA will require an implementation of a peripheral controller in order to communicate with the Cypress USB device See the Xilinx XPS External Peripheral Controller data sheet for more information at http www xilinx com support documentation ip_documentation xps_epc pdf 42 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description 14 DVI Codec The ML605 features a DVI connector P3 to support an external video monitor The DVI circuitry utilizes a Chrontel CH7301C U38 capable of 1600 X 1200 resolution with 24 bit color The video interface chip drives both the digital and analog signals to the DVI connector A DVI monitor can be connected to the board directly A VGA monitor can also be connected to the board using the supplied DVI to VGA adaptor The Chrontel CH7301C is controlled by way of the video IIC bus The DVI connector Table 1 16 supports the IIC protocol to allow the board to read the monitor s configuration parameters These parameters can be read by the FPGA using the DVI IIC bus see 15 IIC Bus page 44 Table 1 16 DVI Controller Connections U1 FPGA Pin Schematic Netname EE AJ19 DVI DO 63 AH19 DVI DI 62 AM17 DVI D2 61 AM16 DVI D3 60 AD17 DVI D4 59 AE17 DVI D5 58 AK18 DVI_D6 55 AK17 DVI
39. C LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC B2 G10 M11 CES A11 G11 E11 D14 C14 G12 G13 F14 H14 CLO G20 E19 E20 A20 A21 E22 E23 G21 B211 A23 A24 C20 D20 J20 G22 D26 E26 V B256 E26 C24 NDR pats C251 s ESTAS B28 D29 B27 5 G27 A28 E24 GEI F28 BL 12911 H28 B30 A30 E29 P29 E11 BEL E14 19 B22 A26 90 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET n n n DDR3 DM6 DDR3 DM7 DDR3_DOSO_N DDR3 DQSO P DDR3_DQS1_N DDR3_DQS1_P DDR3_DQS2_N DDR3 DQS2 P DDR3 DQS3 Nu DDR3 DQS3 P DDR3 DQS4 N DDR3 DQS4 P DDR3 DQS5 N DDR3 DQS5 P DDR3 DQS6 Nu DDR3 DQS6 P DDR3 DQS7 Nu DDR3 DQS7 P DDR3 ODTO DDR3_ODT1 DDR3 RAS RB DDR3 S0 B DDR3 S1 B DDR3 WE B DVI DO DVI D1 DVI D2 DVI D3 DVI D4 DVI D5 DVI D6 DVI D7 DVI D n DVI D9 DVI D10 DVI D11 DVI DE DDR3 RESET B DDR3 TEMP EVENT D
40. C connectors may be found in Appendix C VITA 57 1 FMC Connections in Table C 1 and Table C 2 respectively ML605 Hardware User Guide www xilinx com 61 UG534 v1 0 August 17 2009 XILINX Chapter 1 ML605 Evaluation Board QNO 0S3M QN QNO ES QNO N o INS INS a QNO QNO QNO QNO ONS INS ano ONO QNO QNO QNO QNO ano QNO ano Novi N9xv I Gb eee _ do QNO QNO QNO QNO ano Nemi ano sone dem GNO QNO _ 99 d Sivi ano QNO QNO 99 N ZW QNO QNO dw QNO QNO Nt QNO QNO drivi New QNO QNO dtivi oe QNO QNO ano ano Now New Guo dov dem oe ano GNO ano NS ano UN OWT desovi ono ano dom GNO QNO QNO 99 N IOVI QNO QNO 99 d LOVI QNO QNO QNO e A i NO QNO QNO QNO QNO QNO QNO QNO QNO QNO QNO ano 834 GNO NO g 2 3 a o CONI QNO QNO ano auo Nzew ano NEEN devi ano dem ano auo Novi ano Nun dom ano diem ano qu Nee ano Nemi adem qu dem ano aqu Nt ano Nsw dbm ano ase ano ano Nuvi ano metes apa quo dzvi ano quo New ano Novi dem ano dom ano ano Nswi ano Now asm INT Re TTM EMI ano Ntwi
41. D1 LS 93 T30 USB_D2_LS 92 T31 USB D3 LS 91 T29 USB_D4_LS 90 V28 USB_D5_LS 89 V27 USB_D6_LS 87 U25 USB_D7_LS 86 Y28 USB_D8_LS 66 W32 USB_D9_LS 65 W31 USB_D10_LS 61 Y29 USB_D11_LS 60 W29 USB D12 LS 59 Y34 USB D13 LS 58 Y33 USB D14 LS 57 Y31 USB_D15_LS 56 Y27 USB_INT_LS 46 W25 USB_RD_B_LS 47 T25 USB_RESET_B_LS 85 V25 USB_WR_B_LS 48 ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 41 Chapter 1 ML605 Evaluation Board NET USB AO LS LOC Y32 NET USB A1 LS LOC W26 NET USB CS B LS LOC W27 NET USB DO LS LOC R33 NET USB D1 LS LOC R34 NET USB D2 LS LOC T30 NET USB D3 LS LOC T31 NET USB D4 LS LOC T29 NET USB D5 LS LOC V28 NET USB D6 LS LOC V27 NET USB D7 LS LOC U25 NET USB D8 LS LOC Y28 NET USB D9 LS LOC W32 NET USB D10 LS LOC W31 NET USB D11 LS LOC Y29 NET USB D12 LS LOC W29 NET USB D13 LS LOC Y34 NET USB D14 LS LOC Y33 NET USB D15 LS LOC Y31 NET USB INT LS LOC Y27 NET USB RD B LS LOC W25 NET USB RESET B LS LOC T25 NET USB WR B LS LOC V25 Figure References The Cypress CY7C67300 data sheet can be found at XILINX 1 21 UCF Location Constraints for USB to UART http www cypress com products index jsp fid 10 amp rpn CY7C67300 In addition see the US
42. DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD R3 DO R3 D1 R3 D2 R3 D n R3 D4 R3 D5 R3 D6 R3 D7 R3 D8 R3 D n R3 D R3 D R3 D R3 D R3 D R3 D R3 D R3 D R3 D R3 D on 1 2 3 4 gu 6 7 g 9 R3 D20 R3 D21 R3 D22 R3 D23 R3 D24 R3 D25 R3 D26 R3 D27 R3 D28 R3 D29 R3 D30 R3 D31 R3 D32 R3 D33 R3 D34 R3 D35 R3 D36 R3 D37 R3 D38 R3 D39 R3 D40 R3 D41 R3 D42 R3 D43 R3 D44 R3 D45 R3 D46 R3 D47 R3 D48 R3 D49 R3 D50 R3 D51 R3 D52 R3 D53 R3 D54 R3 D55 R3 D56 R3 D57 R3 D58 R3 D59 R3 D60 R3 D61 R3 D62 R3 D63 R3 DMO R3_DM1 R3_DM2 R3_DM3 R3_DM4 R3 DM5 R3 DM6 R3 DM7 LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC gii E13 F13 K11 L11 K13 K12 D11 M13 Jia B13 B12 cio M11 C12 All cii F11 D14 cia ci2 G13 Plan H14 cio G20 E19 F20 A20 A21 E22 E23 G21 B21 A23 A24 C20 D20 J20 G22 D26 F26 B26 E26 C24 D25
43. Evaluation Board XILINX Configuration Options 78 The FPGA on the ML605 Evaluation Board can be configured by the following methods e 3 Platform Flash XL 128 Mbit page 23 e 4 Linear Flash BPI P30 page 23 e 5 Xilinx System ACE CF and CompactFlash Connector e 6 USBJTAG page 29 For more information see the Virtex 6 FPGA Configuration User Guide at http www xilinx com support documentation user_guides ug360 pdf Table 1 29 Mode Switch S2 Settings Mode Pins M2 M1 M0 Configuration Mode 110 Slave Select MAP 010 BPI Mode 101 JTAG With the mode set to JTAG 101 the ML605 will not attempt to boot or load a bitstream from either of the Flash devices If a CompactFlash CF card is installed in the CF socket U73 System ACE CF will attempt to load a bitstream from the CF card image address pointed to by the image select switch S1 With no CF card present the ML605 can be configured via the onboard JTAG controller and USB download cable as described above With the mode set to either Slave SelectMAP 110 or BPI Mode 010 the FPGA will attempt to configure itself from the selected Flash device as described in 3 Platform Flash XL 128 Mbit page 23 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Appendix A References The following documents are located at http www xilinx com support documentation virtex 6 htm ML605
44. FMC HPC DP2 C2M P FMC HPC DP2 M2C N FMC HPC DP2 M2C P FMC HPC DP3 C2M N FMC HPC DP3 C2M P FMC HPC DP3 M2C N FMC HPC DP3 M2C P FMC HPC DPA C2M N FMC HPC DPA C2M P FMC HPC DP4 M2C N FMC HPC DPA M2C P FMC HPC DP5 C2M N FMC HPC DP5 C2M P FMC HPC DP5 M2C N FMC HPC DP5 M2C P FMC HPC DP6 C2M N FMC HPC DP6 C2M P FMC HPC DP6 M2C N FMC HPC DP6 M2C P FMC HPC DP7 C2M N FMC HPC DP7 C2M P FMC HPC DP7 M2C N FMC HPC DP7 M2C P FMC HPC GBTCLKO M2C N FMC HPC GBTCLKO M2C P FMC HPC GBTCLK1 M2C N FMC HPC GBTCLK1 M2C P FMC HPC HAOO CC N FMC HPC HAOO CC P FMC HPC HAO1 CC N FMC HPC HA01 CC P FMC HPC HAO2 N FMC HPC HAO2 P FMC_HPC_HA03_N FMC_HPC_HA03_P FMC_HPC_HA04_N FMC_HPC_HA04_P FMC_HPC_HA05_N LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC WEA te K24 AP21 AP20 AC30 AD30 n H ARS H AB6 H AF34 AE34 AHS x AH6 AB2 ji ABI H AC4 H AC3 H AD2 i ADI H AEA gt AE3 AF2 H AFL hi AF6 hi AF5 AH2 H AHI H AGA H AG3 i AK2 H AK1 AJA s TAJ3 hi AM2 hi AMI Aa AL3 H AN4 x AN3 H AM6 i
45. FMC HPC LA31 P AL29 H32 FMC HPC LA28 N AJ27 ML605 Hardware User Guide www xilinx com 85 UG534 v1 0 August 17 2009 Appendix C VITA 57 1 FMC Connections XILINX Table C 1 VITA 57 1 FMC HPC Connections Cont d een Schematic Netname wi i NEE Schematic Netname et Tii G34 FMC_HPC_LA31_N AK29 H34 FMC_HPC_LA30_P AJ24 G36 FMC_HPC_LA33_P AH23 H35 FMC_HPC_LA30_N AK24 G37 FMC_HPC_LA33_N AH24 H37 FMC_HPC_LA32_P AG25 H38 FMC HPC LA32 N AG26 J2 FMC HPC CLK3 M2C IO P AE34 KA FMC HPC CLK2 M2C P U83 6 J3 FMC_HPC_CLK3_M2C_IO_N AF34 K5 FMC_HPC_CLK2_M2C_N U83 7 J6 FMC_HPC_HA03_P AA25 K7 FMC_HPC_HA02_P AB25 J7 FMC HPC HA03 N Y26 K8 FMC HPC HA02 N AC25 J9 FMC_HPC_HA07_P AA26 K10 FMC_HPC_HA06_P AA28 J10 FMC_HPC_HA07_N AB26 K11 FMC HPC HA0O6 N AA29 J12 FMC_HPC_HA11_P AG33 K13 FMC_HPC_HA10_P AD34 J13 FMC_HPC_HA11_N AG32 K14 FMC_HPC_HA10_N AC34 J15 FMC HPC HA14 P AA30 K16 FMC_HPC_HA17_CC_P V30 J16 FMC HPC HA14 N AA31 K17 FMC_HPC_HA17_CC_N W30 J18 FMC_HPC_HA18_P T33 K19 FMC_HPC_HA21_P U31 J19 FMC_HPC_HA18_N T34 K20 FMC HPC HA21 N U30 J21 FMC HPC HA22 P U28 K22 FMC HPC HA23 P U26 J22 FMC_HPC_HA22_N V29 K23 FMC_HPC_HA23_N U27 J24 FMC_HPC_HB01_P AN32 K25 FMC_HPC_HB00_CC_P AF30 J25 FMC_HPC_HB01_N AM32 K26 FMC_HPC_HB00_CC_N AG30 J27 FMC_HPC_HB07_P AJ34 K28 FMC_HPC_HB
46. FMC LPC LA26 N M32 G2 FMC LPC CLKI M2C P F33 H2 FMC_LPC_PRSNT_M2C_L AD9 G3 FMC_LPC_CLK1_M2C_N G33 H4 FMC_LPC_CLK0_M2C_P A10 G6 FMC_LPC_LA00_CC_P K26 H5 FMC_LPC_CLK0_M2C_N B10 G7 FMC_LPC_LA00_CC_N K27 H7 FMC_LPC_LA02_P G31 G9 FMC_LPC_LA03_P J31 H8 FMC_LPC_LA02_N H30 G10 FMC_LPC_LA03_N J32 H10 FMC_LPC_LA04_P K28 G12 FMC_LPC_LA08_P J30 H11 FMC_LPC_LA04_N J29 G13 FMC_LPC_LA08_N K29 H13 FMC_LPC_LA07_P G32 G15 FMC_LPC_LA12_P E32 H14 FMC_LPC_LA07_N H32 G16 FMC_LPC_LA12_N E33 H16 FMC LPC LA11 P D31 G18 FMC LPC LA16 P A33 H17 FMC LPC LA11 N D32 G19 FMC LPC LA16 N B33 H19 FMC LPC LA15 P C32 G21 FMC LPC LA20 P P29 H20 FMC_LPC_LA15_N B32 G22 FMC_LPC_LA20_N R29 H22 FMC LPC LA19 P M30 G24 FMC LPC LA22 P N27 H23 FMC LPC LA19 N N30 ML605 Hardware User Guide www xilinx com 87 UG534 v1 0 August 17 2009 Appendix C VITA 57 1 FMC Connections XILINX Table C 2 VITA 57 1 FMC LPC Connections Cont d uh Schematic Netname Ma E DE Schematic Netname M dics G25 FMC LPC LA22 N P27 H25 FMC LPC LA21 P R26 G27 FMC LPC LA25 P P31 H26 FMC_LPC_LA21_N T26 G28 FMC_LPC_LA25_N P30 H28 FMC_LPC_LA24 P N32 G30 FMC LPC LA29 P N34 H29 FMC LPC LA24 N P32 G31 FMC LPC LA29 N P34 H31 FMC_LPC_LA28_P N33 G33 FMC_LPC_LA31_P M31 H32 FMC_LPC_LA28_N M33 G34 FMC_LPC_LA31_N L31 H34 FMC_LPC_LA30_P N26 G36 FMC_LPC_LA33_P K32 H35 FMC_LPC_LA30_N M27 G37 FMC_LPC_LA33_N K31 H37 FMC LPC LA32 P N25 H38 FMC
47. FMC_HPC_HB04_P FMC_HPC_HB05_N FMC_HPC_HB05_P FMC_HPC_HB06_CC_N FMC_HPC_HB06_CC_P FMC_HPC_HB07_N FMC_HPC_HB07_P FMC_HPC_HB08_N FMC_HPC_HB08_P FMC_HPC_HB09_N FMC_HPC_HB09_P FMC_HPC_HB10_N FMC_HPC_HB10_P LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC AB27 TAA29 n i AA28 n AB26 AA26 n AF31 AG31 AB31 AB30 AC34 AD34 n 7 AG32 AG33 AE32 AD32 AD31 AE31 1431 n AA30 n E AC32 AB32 AB33 AC33 W30 V30 H T34 H T33 H U32 H U33 H V33 H V32 i U30 U31 x y29 H U28 U27 H U26 x AG30 AF30 M32 AN32 AP33 AP32 AM31 AL30 AL33 AM33 AN34 AN33 AE26 AF26 AH3A n E AJ34 AK32 AK33 AK34 AL34 AF29 AF28 64 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET
48. Guide www xilinx com 59 UG534 v1 0 August 17 2009 60 Chapter 1 ML605 Evaluation Board XILINX Table 1 26 Switch S2 Configuration Details Switch Configuration Mode Method Slave Switch Net Name JTAG SelectMAP Master BPI System ACE CF Platform Flash P30 Linear Flash XL 2 1 CCLK_EXTERNAL Off On Off 92 2 P30 CS SEL On Off On 52 3 FPGA_MO On Off Off 92 4 FPGA M1 Off On On 2 5 FPGA M2 On On Off S2 6 FLASH_A23 Off Don t Care Off 2 Notes 1 InJTAG mode 82 2 is shown as On for FPGA access to the P30 Linear Flash Alternatively set S2 2 to Off for FPGA access to the Platform Flash XL 2 In Master BPI mode 52 6 is shown as Off for selecting initial configuration from BPI address 0x000000 Alternativelv set S2 6 to On to select initial configuration from BPI address 0x800000 See 3 Platform Flash XL 128 Mbit page 23 and 4 Linear Flash BPI P30 page 23 for details 19 VITA 57 1 FMC HPC Connector The ML605 implements both the High Pin Count HPC J64 and Low Pin Count LPC J63 connector options of VITA 57 1 1 FMC specification This section discusses the FMC HPC J64 connector The FMC standard calls for two connector densities a High Pin Count HPC and a Low Pin Count LPC implementation A common 10 x 40 position 400 pin locations connector form factor is used for both versions The HPC version is fully populated with 400 pins present and the LPC versio
49. Hardware User Guide Virtex 6 Family Overview Virtex 6 FPGA Data Sheet DC and Switching Characteristics Virtex 6 Family Package Device Pinout Files ASCII Virtex 6 FPGA Packaging and Pinout Specifications Virtex 6 FPGA Configuration User Guide Virtex 6 FPGA SelectIO Resources User Guide Virtex 6 FPGA Clocking Resources User Guide Virtex 6 FPGA Memory Resources User Guide Virtex 6 FPGA Configurable Logic Block User Guide Virtex 6 FPGA GTX Transceivers User Guide Virtex 6 FPGA DSP48E1 Slice User Guide Virtex 6 FPGA Embedded Tri Mode Ethernet MAC User Guide Virtex 6 FPGA System Monitor User Guide www xilinx com 79 UG534 v1 0 August 17 2009 Appendix A References g XILINX 80 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Default Switch and Jumper Settings Appendix B Table B 1 Default Switch Settings REFDES Function Type Default SW2 Board power slide switch off User GPIO 8 pole DIP switch 8 off 7 off 6 off SW1 5 off 4 off 3 off 2 off 1 off System ACE CF configuration and image select 4 pole DIP switch 4 SysACE Mode 1 on pl 3 SysAce CFGAddr 2 0 off 2 SysAce CFGAddr 1 0 off 1 SysAce CFGAddr 0 0 off FPGA mode boot PROM select and FPGA CCLK select 6 pole DIP switch 6 FLASH A23 0 off 5 M2 0 off S2 4 M1 1 Bi M 2 0 010 Master BPI Up 3 MO 0 off 2 CS_SEL 1 boot f
50. Hardware User Guide www xilinx com 71 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board XILINX Table 1 28 Onboard Power System Devices Reference ili Power Rail Power Rail Schematic pevca Type Designator peecription Netname Voltage Page UCD9240PFC U24 PMBus Controller Core Addr 52 35 PTD08A020W U42 20A 0 6V 3 6V Adj Switching Regulator VCCINT_FPGA 1 00V 36 PTD08A020W U43 20A 0 6V 3 6V Adj Switching Regulator VCC2V5_FPGA 2 50V 37 PTD08A010W U44 10A 0 6V 3 6V Adj Switching Regulator VCCAUX 2 50V 38 UCD9240PFC U25 PMBus Controller Aux Addr 53 40 UCD7230RGWR U35 6A 0 6V 3 6V Adj Switching Regulator MGT AVCC 1 00V 41 UCD7230RGWR U36 6A 0 6V 3 6V Adj Switching Regulator MGT AVTT 1 00V 42 PTD08A010W U20 10A 0 6V 3 6V Adj Switching Regulator VCC_1V5 1 50V 43 PTD08A010W U21 10A 0 6V 3 6V Adj Switching Regulator VCC 3V3 3 30V 44 TPS79518DCOR U79 500mA Fixed Linear Regulator VCC 1V8 1 80V 45 TPS512300DRCT U17 3A DDR3 VTERM Tracking Linear VTTDDR 0 75V 45 Regulator TPS512300DRCT U17 10mA Tracking Reference output VTTVREF 0 75V 45 Voltage and current monitoring and control are available for selected power rails through Texas Instruments Fusion Digital Power graphical user interface GUI Both onboard TI power controllers are wired to the same PMBus The PMBus connector J3 is provided for use with the TI USB Interface
51. IE_PRSNT_B E PCIE PRSNT X4 El AS g PCIE PRSNT X8 Se Aerer H 2X3 Figure 1 17 PCle Lane Size Select Jumper J42 Table 1 7 shows the PCIe connector P1 that provides up to 8 lane access through the GTX transceivers to the Virtex 6 FPGA integrated Endpoint block for PCIe designs 32 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Table 1 7 PCle Edge Connector Connections Detailed Description U1 FPGA e P1 PCle Edge s as Package Pin Schematic Netname Connector Description Placement F1 PCIE TXO P A16 i Integrated Endpoint GTXEL X0Y15 F2 PCIE TXO N A17 block transmit pair H1 PCIE TX1 P A21 Integrated Endpoint GTXE1_X0Y14 H2 PCIE_TX1_N A22 block transmit pair K1 PCIE_TX2_P A25 Integrated Endpoint GTXE1_X0Y13 K2 PCIE_TX2_N A26 block transmit palr MI PCIE TX3 P A29 i Integrated Endpoint GTXE1_X0Y11 M2 PCIE_TX3_N A30 block transmit palr P1 PCIE_TX4_P A35 Integrated Endpoint GTXEL XOV10 P2 PCIE_TX4_N A36 block transmit palr Hn PCIE TX5 P A39 Integrated Endpoint GTXEL XOV9 T2 PCIE TX5 N A40 block transmit pair 7 VI PCIE_TX6_P A43 Integrated Endpoint i GTXE1_X0Y8 V2 PCIE_TX6_N A44 block transmit palr Y1 PCIE TX7 P A47 Integrated Endpoint GTXEL XOV7 Y2 PCIE TX7 N A48 block transmit palr J3 PCIE RXO P B14 Integrated Endpoint GTXE1_X0Y15 J4 PCIE RXO N B15 block rec
52. LOC LOC LOC LOC LOC LOC LOC APT AGI AH17 AGI AFL AK1 AJ1 AJ1 9 AL1 ALL Bills SAS Bulls Bill 4 Bill 4 I Bis 4 H9 A go I T24 T1235 J25 J24 y325 W26 W27 R33 e I R34 3 WEIL NT2QAMA V28 ADAM 25s y 284 W32 W31 WY 29 s W29 Y34 y33 e I VAI W 27g s W25 T2513 V25 U23 M22 L23 W34 V34 P26 P25 M28 28 100 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009
53. MC LPC LA20 P FMC LPC LA21 N FMC LPC LA21 P FMC LPC LA22 N FMC LPC LA22 P FMC LPC LA23 N LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC B10 A10 G33 R33 D2 nc pus G4 ne G3 Pa I I M5 n e M6 ne AF13 AGL I Bla WR s K26 E31 F31 I H30 G31 I J32 J31 I J29 K28 WHS 3 tes H34 J34 K33 WF G32 WK QAL J30 L26 L25 G30 E30 D32 pats E33 E32 C34 D34 B34 Wee CAE B32 NES ta WBS 3 lcs A33 N29 N28 39 L29 N30 M30 R29 s p29 EZIO R26 P27 N27 s VIRA ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 69 70 Chapter 1 ML605 Evaluation Board g XILINX NET FMC LPC LA23 P LOC R28 NET FMC LPC LA24 N LOC P32 NET FMC LPC LA24 P LOC N32 NET FMC LPC LA25 N LOC P30 NET FMC LPC LA25 P LOC P31 NET FMC LPC LA26 N LOC M32 NET FMC LPC LA26 P LOC L33 NET FMC LPC LA27 N LOC R32 NET FMC LPC LA27 P LOC R31 NET FMC LPC LA28 N LOC M33 NET FMC LPC LA
54. ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOSS OF DATA OR LO
55. N VP To Measure VCCINT Current Dedicated Analog Inputs Jumper on 9 11 10 12 Connect Vccint shunt to Vp Vn UG534 37 081209 Figure 1 46 System Monitor Header J35 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description ML605 Board Power Monitor In addition to monitoring the FPGA core supply power consumption two auxiliary analog input channels of the 16 that are available are used to implement a power monitor for the entire ML605 board The board power is monitored at the 12V power input connector Figure 1 47 shows how the power monitor is implemented and connected to the System Monitor auxiliary input channels 12 and 13 A simple resistor divider is used to monitor the 12V supply voltage and to provide a reference voltage to an instrumentation amplifier InAmp The voltage on the auxiliary channel 12 is equal to supply voltage divided by 24 0 5V The InAmp is used to amplify by a factor of 50 the voltage dropped across a 2 milliohm current sense shunt The voltage at the output of the InAmp is proportional to the current The voltage on auxiliary channel 13 Current amps x 0 002 x 50 e g 5A 0 5V 12V Supply Monitor 2M0 1 R1 R2 A si Ho IN IN OO O 11 5kQ 0 5 V INA213 74700 SC70 6 OUT 1kO RERT Package Y Q x VAUXP 13 4990 0 5 50V V 10nF 10nF Current Channel Q Pd VAUXN 13 1kQ 4700 10nF 1kQ DI VAUXP 12 O 10nF Volta
56. NET NET LCD DB4 LS LCD DB5 LS LCD DB6 LS LCD DB7 LS LCD RW LS LCD RS LS LCD E LS Figure 1 34 LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC AC22 AC24 AE22 AE23 AB23 AG23 AE24 AD24 AP24 AD21 AE21 AH28 AH27 G26 i G17 H A19 H A18 s H17 H H10 H D22 C22 L21 L20 KOTBA B18 K22 K21 1 W34 V34 AD14 AK11 AJ11 AE12 AC14 T28 AK12 UCF Location Constraints for User UO ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 55 Chapter 1 ML605 Evaluation Board 18 Switches XILINX The ML605 Evaluation board includes the following switches e Power On Off Slide Switch SW2 e FPGA PROG B SWA active Low e SYSACE RESET B SW3 active Low e System ACE CF CompactFlash Image Select DIP Switch S1 active High e MODE Boot EEPROM Select and CCLK Osc Enable DIP SW 82 active High Power On Off Slide Switch SW2 SW2 is the ML605 board main power on off switch Sliding the switch actuator from the off to on position applies 12V power from either J60 6 pin Mini Fit or J25 4 pin ATX power connector to the VCC12 P power plane via the 1m 1 3W series current sense resistor R346 See 22 System Monitor pa
57. NET NET NET NET NET NET NET NET NET FMC_HPC_HB11_N FMC HPC HB11 P FMC HPC HB12 N FMC HPC HB12 P FMC HPC HB13 N FMC HPC HB13 P FMC HPC HB14 N FMC HPC HB14 P FMC HPC HB15 N FMC HPC HB15 P FMC HPC HB16 N FMC HPC HB16 P FMC HPC HB17 CC N FMC HPC HB17 CC P FMC HPC HB18 N FMC HPC HB18 P FMC HPC HB19 N FMC HPC HB19 P FMC HPC LAO0 CC N FMC HPC LAO0 CC P FMC HPC LAO1 CC N FMC HPC LAO1 CC P FMC HPC LAO2 N FMC HPC LAO2 P FMC HPC LAQ3 Hu FMC HPC LAQ3 P FMC HPC LAO4 N FMC HPC LAO4 P FMC HPC LAOS Hu FMC HPC LAOS P FMC HPC LAO6 N FMC HPC LAO6 P FMC HPC LAO7 N FMC HPC LAO7 P FMC HPC LAO8 Hu FMC HPC LAOB8 P FMC HPC LAO9 N FMC HPC LAO9 P FMC HPC LA10 Hu FMC HPC LA10 P FMC HPC LA11 N FMC HPC LA11 P FMC HPC LA12 N FMC HPC LA12 P FMC HPC LA13 N FMC HPC LA13 P FMC HPC LA14 N FMC HPC LA14 P FMC HPC LA15 N FMC HPC LA15 P FMC HPC LA16 N FMC HPC LA16 P FMC HPC LA17 CC N FMC HPC LA17 CC P FMC HPC LA18 CC N FMC HPC LA18 CC P FMC HPC LA19 N FMC HPC LA19 P FMC HPC LA20 N LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC AJ30 AJ29 AJ32 AJ31
58. OC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC E10 H bon d AH8 H AG8 A apg i ANI i AF10 AF9 H ALI AA23 AF24 AF25 W24 V24 H24 ASS p24 R24 G23 H23 y N24 N23 R23 F24 L24 M23 J26 K23 K24 AP21 AP20 AC30 AD30 n A AB5 gt AB6 AF34 AE34 AHS Ma AH6 e AB2 s ABI AC4 ns AC3 AD2 G ADI AR4 Mes AE3 Ms AF2 UE AF1 AF6 AF5 AH2 KE AHI AG4 Nos AG3 us AK2 Be AKI KS AJA Gk AT K 92 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET FMC HPC DP5 C2M N FMC HPC DP5 C2M P FMC HPC DP5 M2C N FMC HPC DP5 M2C P FMC HPC DP6 C2M N FMC HPC DP6 C2M P FMC HPC DP6 M2C N FMC HPC DP6 M2C P FMC HPC DP7 C2M N FMC HPC DP7 C2M P FMC HPC DP7 M2C N FMC HPC DP7 M2C P FMC HPC GBTCLKO M2C N FMC HPC GBTCLKO M2C P FMC HPC GBTCLK1 M2C N FMC HPC GBTCLK1 M2C P FMC HPC HAOO CC N FMC HPC HAOO CC P FMC HPC HAO1 CC N FMC HPC HAO1 CC P FMC HPC HAO2 N FMC HPC HAO2 P FMC_HPC_HA03_N FMC_HPC
59. PC LAOS Hu FMC HPC LAOS P FMC HPC LAO6 Hu FMC HPC LAO6 P LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC WS Ns v29 1728 27 s U26 AG30 AF30 M32 AN32 AP33 AP32 AM31 AL30 AL33 AM33 AN34 AN33 AE26 AF26 AH34 AJ34 AK32 AK33 AK34 AL34 AF29 AF28 AJ30 AJ29 AJ32 AJ31 AH32 AH33 AD27 AE27 AE29 AE28 AH30 AH29 AG28 AG27 AD26 AD25 AK31 AL31 AF21 AF20 AL1 AK1 ERR SALES AD20 AC20 ADI ACTI AEl AF1 Qui gu 9 Gs AH22 n H AG22 AG21 AG20 94 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET FMC_HPC_LA07_N FMC_HPC_LA07_P FMC_HPC_LA08_N FMC_HPC_LA08_P FMC_HPC_LA09_N FMC_HPC_LA09_P FMC_HPC_LA10_N FMC_HPC_LA10_P FMC HPC LA11 N
60. PGA System Monitor User Guide VCC2V5 Analog Supply Filter SYSMON AVDD SYSMON VREFP C79 X5R 10v 0 1UF NY Ferrie Bead AGND Jumper on pins 1 2 Default Setting 1 2 Select External Reference 2 3 Select On Chip Reference NV AGND UG534 36 081209 Figure 1 45 System Monitor External Reference ML605 Hardware User Guide www xilinx com 73 UG534 v1 0 August 17 2009 74 Chapter 1 ML605 Evaluation Board XILINX System Monitor Header J35 Figure 1 46 shows the pinout for the System Monitor 12 pin header The header provides user access to the analog power supply Aygq and the 1 25V reference shown in Figure 1 45 page 73 Access to the FPGA thermal diode and dedicated analog input channel Vp Vn is also provided on this header The header can be used to connect user specific analog signals and sensors to the system monitor The kelvin points for a 5 milliohm current sensing shunt in the FPGA 1V V i core supply are also available on this header By connecting header pins 9 to 11 and 10 to 12 using jumpers the system monitor can be used to monitor the FPGA core current and power consumption This can be used to collect useful power information about a particular design or implementation FPGA System Monitor RIDI Header J35 cessa FPGA DX P FPGA DX N SYSMON AVDD 1 25V Reference Anti alias Filter ccint shunt P Vccint shunt N SYSMON VN SYSMO
61. PGA U1 Bank 13 SFP IIC interface SFP module connector P4 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description The ML605 IIC bus topology is shown in Figure 1 23 IC SDA MAIN LS BANK 34 IIC SDA SFP IC SCL SFP IIC SDA DVI BANK 34 IIC_SCL_DVI FMC_LPC_IIC_SDA_LS LEVEL LEVEL SHIFTER SHIFTER FMC LPC COLUMN C 2 Kb EEPROM on any FMC LPC FMC_LPC_IIC_SCL Mezzanine Card FMC_LPC_IIC_SDA Addr 0b1010001 BANK 13 LEVEL SHIFTER ST MICRO M24C08 WDWeTP FPGA IIC INTERFACE Addr 001010100 0b1010111 J64 FMC HPC COLUMN C j 2 Kb EEPROM on Mezzanine Card Addr 0b1010000 DDR3 SODIMM IIC_SCL_MAIN SOCKET Addr 0b1010011 IIC_SDA_MAIN 2 Kb EEPROM Addr 0b0011011 Temperature Sensor IIC_CLK_DVI_F IIC_SDA_DVI_F DVI CONN Addr 0b1010000 U38 DVI CODEC CHRONTEL SFP_MOD_DEF2 SFPMODULE SFP_MOD_DEF1_ CONNECTOR Addr 0b1010000 CH730C TF Addr 0b1110110 UG534_11_081209 Figure 1 23 IIC Bus Topology NET IIC SDA MAIN LS LOC AE9 NET IIC SCL MAIN LS LOC AK9 NET IIC SDA DVI LOC AP10 NET IIC SCL DVI LOC AN10 NET FMC LPC IIC SDA LS LOC AG13 NET FMC LPC IIC SCL LS LOC AF13 NET IIC SDA SFP LOC AA33 NET IIC SCL SFP LOC AA34 Figure 1 24 UCF Location Constraints for ML605 IIC buses ML605 Hardware User Guide www xilinx
62. ST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2009 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners PCI PCI Express PCle and PCI X are trademarks of PCI SIG Revision History The following table shows the revision history for this document Date Version Revision 8 17 2009 1 0 Initial Xilinx release ML605 Hardware User Guide www xilinx com UG534 v1 0 August 17 2009 Table of Contents Preface About This Guide Guide Contents ia g e a E a EE AE E ea a 5 Additional Support Resources 5 Conventions usse ee 5 Typographlical coire e r eb p e ttis e arce 5 Online Document 6 Chapter 1 ML605 Evaluation Board NS doi 7 Additional Information 7 HEET 8 Block Diagram uec bee pete p ep et peer aa 10 Related Xilinx Documents e 10 Detailed Eet kr de pride ri a P opi Rien ER aed 11 1 Virtex 6 XC6VLX240T 1FFG1156 2 ce I n 13 Configuration EE 13 I O Voltage Rails evocar ege ged Fut iper A CEDE RE pera e SE 14 2 512 MB DDR3 Memory SODIMM e n 15 3 Platform Flash XL 128 Mbit 23 4 Linear Flash BEI P30 cocos deer D E d RR ee 23 ML605 Flash Boot Options ENEE 24 5 Xilinx System ACE CF and CompactFlash Connector 27 6 USB JTAG reef A
63. SW1 2 GPIO_DIP_SW2 C22 SW1 3 GPIO DIP SW3 L21 SW1 4 GPIO_DIP_SW4 L20 SW1 5 GPIO_DIP_SW5 C18 SW1 6 GPIO DIP SW6 B18 52 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description Table 1 22 User DIP Switch Connections Cont d DIP Switch Pin Schematic Netname U1 FPGA Pin SW1 7 GPIO DIP SW7 K22 SW1 8 GPIO DIP SW8 K21 User SMA GPIO The ML605 includes an pair of SMA connectors for GPIO as described in Figure 1 32 and Table 1 23 J56 32K10K 400E3 USER SMA GPIO N USER SMA GPIO P UG534 10 072109 Figure 1 82 User SMA GPIO Table 1 23 User SMA Connections SMA Pin Schematic Netname U1 FPGA Pin J56 1 USER_SMA_GPIO_N W34 J57 1 USER_SMA_GPIO_P V34 ML605 Hardware User Guide www xilinx com UG534 v1 0 August 17 2009 53 Chapter 1 ML605 Evaluation Board g XILINX LCD Display 16 Character x 2 Lines The ML605 board has a 16 character x 2 line LCD Display Tech S162D BA BC installed onto J41 2x7 header on the board to display text information Potentiometer R270 adjusts the contrast of the LCD A ST2378E U33 2 5V to 5V level shifter is used to shift the voltage level between the FPGA and the LCD The data interface to the LCD is connected to the FPGA to support 4 bit mode only The LCD module has a connector that allows the LCD to be removed from the board to access to the components below it Caution Care should be taken
64. T NET NET NET NET NET NET NET NET NET NET FLASH A14 FLASH A15 FLASH A16 FLASH A17 FLASH A18 FLASH A19 FLASH A20 FLASH A21 FLASH A22 FLASH A23 FLASH DO FLASH D1 FLASH D2 FLASH D3 FLASH D4 FLASH D5 FLASH D6 FLASH D7 FLASH D8 FLASH D9 FLASH D10 FLASH D11 FLASH D12 FLASH D13 FLASH D14 FLASH D15 FLASH WAIT FMC HPC CLKO M2C N FMC HPC CLKO M2C P FMC HPC CLK1 M2C N FMC HPC CLK1 M2C P FMC HPC LK2 M2C IO N FMC HPC LK2 M2C IO FMC HPC LK2 M2C MGT C N FMC HPC LK2 M2C MGT C p FMC HPC LK3 M2C IO N FMC HPC LK3 M2C IO P FMC HPC LK3 M2C MGT C N ooooooooooo FMC HPC LK3 M2C MGT C P FMC HPC DPO C2M N FMC HPC DPO C2M P FMC HPC DPO M2C N FMC HPC DPO M2C P FMC HPC DP1 C2M N FMC HPC DP1 C2M P FMC HPC DP1 M2C N FMC HPC DP1 M2C P FMC HPC DP2 C2M N FMC HPC DP2 C2M P FMC HPC DP2 M2C N FMC HPC DP2 M2C P FMC HPC DP3 C2M N FMC HPC DP3 C2M P FMC HPC DP3 M2C N FMC HPC DP3 M2C P FMC HPC DPA C2M N FMC HPC DP4 C2M P FMC HPC DPA M2C N FMC HPC DPA M2C P LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC L
65. TX5 N PCIE TX5 P PCIE TX6 N PCIE TX6 P PCIE TX7 N PCIE TX7 P PCIE WAKE B LS PHY COL PHY CRS PHY INT PHY MDC PHY MDIO LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC A18 hi H17 i AN10 AK9 AA34 AP10 AE9 H AA33 n fi AD14 n ji AK11 AJ11 AE12 AK12 T28 AC14 AJ12 P5 n d PE n 3 y5 n V6 n a AE13 J4 J3 K6 KS IA I3 UNA N3 RA R3 UA U3 NWA W3 AAA AA3 F2 Fl H2 Hl K2 KI M2 M1 p2 pi T2 Tl V2 Vi y2 Yl AD22 AK13 AL13 AH14 n Hi AP14 AN14 n ji 98 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET PHY RESET PHY RXCLK PHY RXCTL RXDV PHY RXDO PHY RXDI PHY RXD2 PHY RXD3 PH
66. UA BPI or U27 Platform Flash provides the boot bitstream Typically S2 switch 2 will be open OFF to select the U27 Platform Flash Given that the mode switches 52 switch 3 MO switch 4 M1 and switch 5 M2 are set to Slave SelectM AP mode then U27 driven at 47 MHz can load a PCIe core bitstream before a host PC motherboard can scan its PCIe slots When S2 switch 2 is closed ON at power up the FPGA will be configured from the BPI flash device U4 Note that U4 address bit A23 is switched by S2 switch 6 which allows the lower or upper half of U4 to be chosen as a data source Table 1 5 shows the connections and pin numbers for the boot flash devices Table 1 5 Platform Flash and BPI Flash Connections XILINX U27 Platform U1 FPGA Pin Schematic Netname U4 BPI Flash Flash AL8 FLASH_A0 29 A1 AK8 FLASH_A1 25 B1 AC9 FLASH A2 24 C1 AD10 FLASH_A3 23 D1 C8 FLASH_A4 22 D2 B8 FLASH_A5 21 A2 E9 FLASH_A6 20 C2 E8 FLASH_A7 19 A3 A8 FLASH_A8 8 B3 A9 FLASH_A9 7 C3 D9 FLASH_A10 6 D3 C9 FLASH_A11 5 C4 D10 FLASH_A12 4 A5 C10 FLASH_A13 3 B5 F10 FLASH_A14 2 C5 F9 FLASH_A15 1 D7 AH8 FLASH_A16 55 D8 AGS8 FLASH A17 18 A7 AP9 FLASH_A18 17 B7 AN9 FLASH_A19 16 C7 AF10 FLASH A20 11 C8 AF9 FLASH_A21 10 A8 AL9 FLASH_A22 9 Gl AA23 FLASH_A23 26 NC www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Descriptio
67. UCF for the DDR3 SDRAM address pins Address NET DDR3 AO NET DDR3 A1 NET DDR3 A2 NET DDR3 A3 NET DDR3 A4 NET DDR3 Ab NET DDR3 A6 NET DDR3 A7 NET DDR3 A8 NET DDR3 A9 NET DDR3 A10 NET DDR3 A11 NET DDR3 A12 NET DDR3 A13 NET DDR3 A14 NET DDR3 A15 NET DDR3 BAO NET DDR3 BAI NET DDR3 BA2 Figure 1 3 UCF Location Constraints for D LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC D L14 H A16 B16 E16 x D16 J17 A15 H B15 G15 G F15 H M16 4 M15 H15 d 1715 H D15 C15 G K19 J19 x 215 R3 SDRAM Address Inputs 20 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description Data Figure 1 4 provides the UCF constraints for the DDR3 SDRAM data pins NEI NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD
68. VI GPIO1 FMC C2M PG LS DVI H DVI V DVI XCLK N DVI XCLK P FLASH AO FLASH A1 FLASH A2 FLASH A3 FLASH A4 FLASH A5 FLASH A6 FLASH A7 FLASH A8 FLASH A9 FLASH A10 FLASH A11 FLASH A12 FLASH A13 DVI RESET B LS LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC A29 H A31 E12 H D12 J12 s H12 H A14 H A13 H H20 H19 H C23 hi B23 H A25 H B25 i 328 A H27 s D30 C30 i E18 gt E17 L19 H E18 H K18 H R17 D17 B17 A AJ19 AH19 n H TAM17 n AM16 n A AD17 n 7 AE17 AK18 AK17 AE18 AF18 AL16 AK16 AD16 Kg n AN17 n H AP17 AD15 AC17 AC18 ATIS hi AK8 H ACI hi AD10 gms Bg RO HE A8 nos A9 pons Con D10 cod ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 91 Appendix D ML605 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NE
69. Y RXD4 PHY RXD5 PHY RXD6 PHY RXD7 PHY RXER PHY TXCLK PHY TXCTL TXEN PHY TXC GTXCLK PHY TXDO PHY TXD1 PHY TXD2 PHY TXD3 PHY TXD4 PHY TXD5 PHY TXD6 PHY TXD7 PHY TXER PLATFLASH L B PMBUS ALERT LS PMBUS CLK LS PMBUS CTRL LS PMBUS DATA LS SFP LOS SFP RX N SFP RX P SFP TX DISABLE FPGA SFP TX N SFP TX P SGMIICLK QO N SGMIICLK QO P SGMII RX N SGMII RX P SGMII TX N SGMII TX P SMA REFCLK N SMA REFCLK P SMA RX N SMA RX P SMA TX N SMA TX P SM FAN PWM SM FAN TACH SYSACE CFGTDI SYSACE DO SYSACE D1 SYSACE D2 SYSACE D3 SYSACE D4 SYSACE D5 SYSACE D6 SYSACE D7 SYSACE MPA00 LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC AH13 AP11 AM13 AN13 AF14 AE14 AN12 AMI2 AD11 AC12 AC13 AG12 AD12 AJ10 AH12 AM11 AL11 AG10 AG11 AL10 AM10 AE11 AF11 AH10 AC23 AH9 AC10 AJ9 Hi AB10 V23 EA n n E3 n i AP12 CA n i C3 n H H5 n i H6 n A B6 n S BS n d AA n A3 n n F5 n ji F6 n d D6 n d D5 n i B2 n 2 Bl i
70. _D7 54 AE18 DVI D8 53 AF18 DVI_D9 52 AL16 DVI_D10 51 AK16 DVI DI 50 AD16 DVI DE 2 AN17 DVI_H 4 AP17 DVI_RESET_B_LS 13 AD15 DVI V 5 AC17 DVI XCLK N 56 AC18 DVI_XCLK_P 57 NC DVI_GPIOO 8 NC DVI_GPIO1 7 ML605 Hardware User Guide www xilinx com 43 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board 15 IIC Bus NET DVI DO NET DVI DI NET DVI D2 NET DVI D3 NET DVI D4 NET DVI D5 NET DVI DE NET DVI D7 NET DVI D8 NET DVI D9 NET DVI D10 NET DVI D11 NET DVI DE NET DVI GPIO1 FMC C2M PG LS NET DVI H NET DVI RESET B LS NET DVI V NET DVI XCLK N NET DVI XCLK P Figure 1 22 UCF Location Constr LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC ai XILINX AJ19 AH19 AM17 AM16 AD17 AE17 AK18 AK17 AE18 AF18 AL16 AK16 AD16 K9 AN17 AP17 AD15 AC17 AC18 nts for DVI Codec The ML605 implements four IIC bus interfaces at the FPGA The MAIN IIC bus hosts four items FPGA U1 Bank 34 MAIN IIC interface 8Kb NV Memory U6 FMC HPC connector J64 DDR3 SODIMM Socket J1 The DVI IIC bus hosts two items FPGA U1 Bank 34 DVI IIC interface DVI codec U38 and DVI connector J63 The LPC IIC bus hosts two items FPGA U1 Bank 33 LPC IIC interface FMC LPC connector J63 The SFP IIC bus hosts two items 44 F
71. _HA03_P FMC_HPC_HA04_N FMC_HPC_HA04_P FMC_HPC_HA05_N FMC_HPC_HA05_P FMC_HPC_HA06_N FMC_HPC_HA06_P FMC_HPC_HA07_N FMC_HPC_HA07_P FMC_HPC_HA08_N FMC_HPC_HA08_P FMC_HPC_HA09_N FMC_HPC_HA09_P FMC_HPC_HA10_N FMC_HPC_HA10_P FMC_HPC_HA11_N FMC HPC HA11 P FMC HPC HA12 N FMC HPC HA12 P FMC HPC HA13 N FMC HPC HA13 P FMC HPC HA14 N FMC HPC HA14 P FMC HPC HA15 N FMC HPC HA15 P FMC HPC HA16 N FMC HPC HA16 P FMC HPC HA17 CC N FMC HPC HA17 CC P FMC HPC HA18 N FMC HPC HA18 P FMC HPC HA19 N FMC HPC HA19 P FMC_HPC_HA20_N FMC_HPC_HA20_P FMC_HPC_HA21_N LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC AM2 H AMI i ALZ4 H AL3 A ANA S AN3 i AME AM5 H AP2 APL H APE APS AD5 n ADE H AK5 H AK6 AF33 AE33 AC29 AD29 n ji AC25 AB25 WY 26 AA25 AC28 AB28 AC27 AB27 AA29 AA28 AB26 AA26 AF31 AG31 AB31 AB30 AC34 AD34 AG32 AG33 AE32 AD32 AD31 AE31 AA31 AA30 AC32 AB32 AB33 AC33 W30 V30 34 p33 5 1732 5 y33ts V33 V32
72. _LA14 P AN19 D17 FMC_HPC_LA13_P AP19 C19 FMC_HPC_LA14_N AN20 D18 FMC_HPC_LA13_N AN18 C22 FMC_HPC_LA18_CC_P AH25 D20 FMC_HPC_LA17_CC_P AN27 C23 FMC_HPC_LA18_CC_N AJ25 D21 FMC_HPC_LA17_CC_N AM27 C26 FMC HPC LA27 P AP30 D23 FMC HPC LA23 P AL26 C27 FMC HPC LA27 N AP31 D24 FMC_HPC_LA23_N AM26 C30 IIC SCL MAIN LS AK9 D26 FMC HPC LA26 P AM25 C31 IC SDA MAIN LS AE9 D27 FMC_HPC_LA26_N AL25 D29 FMC_HPC_TCK_BUF U88 15 D30 FMC_TDI_BUF J17 1 D31 FMC_HPC_TDO JA7 3 D33 FMC TMS BUF U88 17 E2 FMC_HPC_HA01_CC_P AD29 FI FMC HPC PG M2C LS J27 E3 FMC HPC HAO01 CC N AC29 F4 FMC HPC HAO00 CC P AE33 E6 FMC HPC HAO05 P AB27 F5 FMC HPC HA00 CC N AF33 E7 FMC HPC HAO5 N AC27 F7 FMC HPC HA04 P AB28 E9 FMC HPC HAO09 P AB30 F8 FMC HPC HAO04 N AC28 E10 FMC HPC HA09 N AB31 F10 FMC_HPC_HA08_P AG31 E12 FMC HPC HA13 P AE31 F11 FMC_HPC_HA08_N AF31 E13 FMC_HPC_HA13_N AD31 F13 FMC_HPC_HA12_P AD32 E15 FMC_HPC_HA16_P AC33 F14 FMC_HPC_HA12_N AE32 E16 FMC HPC HA16 N AB33 F16 FMC HPC HA15 P AB32 E18 FMC HPC HA20 P V32 F17 FMC HPC HA15 N AC32 E19 FMC HPC HA20 N V33 F19 FMC HPC HA19 P U33 E21 FMC HPC HB03 P AL30 F20 FMC HPC HA19 N U32 84 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Table C 1 VITA 57 1 FMC HPC Connections Cont d een Schematic Netname x
73. al ground Table 1 14 USB to UART Connections U1 FPGA Pin Schematic Netname U34 CP2103GM J24 USB 1 TX 25 J25 USB_1_RX 24 T23 USB_1_RTS 23 T24 USB_1_CTS 22 NET USB 1 CTS LOC T24 NET USB 1 RTS LOC T23 NET USB 1 RX LOC J25 NET USB 1 TX LOC J24 Figure 1 20 UCF Location Constraints for USB to UART References Technical information on the Silicon Labs CP2103GM and the VCP drivers can be found on their website at http www silabs com In addition see some of the Xilinx UART IP specifications at e http www xilinx com support documentation ip_documentation xps_uartlite pdf e http www xilinx com support documentation ip_documentation xps_uart16550 pdf www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX 13 USB Controller Detailed Description The ML605 provides USB support via a Cypress CY7C67300 EZ Host Programmable Embedded USB Host and Peripheral Controller U81 The host port is a USB Type A connector J5 A USB keyboard without an internal USB hub will be able to connect to this USB Host port to demonstrate functionality The peripheral port is a USB Type Mini B J20 Table 1 15 USB Controller Connections U1 FPGA Pin Schematic Netname U81 USB Controller Y32 USB A0 LS 52 W26 USB A1 LS 50 W27 USB CS B LS 49 R33 USB DO LS 94 R34 USB
74. block nameloci loc2 locn Online Document The following conventions are used in this document Convention Blue text Meaning or Use Cross reference link to a location in the current document Example See the section Additional Resources for details Refer to Title Formats in Chapter 1 for details Red text Cross reference link to a location in another document See Figure 2 5 in the Virtex 5 FPGA User Guide Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest speed files www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Chapter 1 ML605 Evaluation Board Overview The ML605 board enables hardware and software developers to create or evaluate designs targeting the Virtex 6 XC6VLX240T 1FFG1156 FPGA The ML605 provides board features common to many embedded processing systems Some commonly used features include a DDR3 SODIMM memory an 8 lane PCI Express interface a tri mode Ethernet PHY general purpose I O and a UART Additional user desired features can be added through daughter cards attached to the onboard high speed VITA 57 FPGA Mezzanine Connector FMC high pin count HPC expansion connector or the onboard VITA 57 FMC low pin count LPC connector A general listing of board features is provided in the Feature List section with further details in the Detailed Descrip
75. com 45 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board 8 Kb NV Memory XILINX The ML605 hosts an 8 Kb ST Microelectronics M24C08 WDWETP IIC parameter storage memory device U6 The IIC address of U7 is 0b1010100 and U6 is not write protected WP pin 7 is tied to GND The IIC memory is shown in Figure 1 25 VCC3V3 x VCC3V3 IIC SCL MAIN IIC SDA MAIN VCC3V3 1 C65 X5R 2 10V 0 1UF UG534 12 072109 Figure 1 25 IIC Memory U6 Table 1 17 IIC Memory Connections IIC Memory U6 FPGA U1 Pin Schematic Netname Pin Number Pin Name Not Applicable Tied to GND 1 AO Not Applicable Tied to GND 2 Al Not Applicable Pulled up 0 ohm to VCC3V3 3 A2 N10 IIC_SDA_MAIN 5 SDA P11 IIC SCL MAIN 6 SCL Not Applicable Tied to GND 7 WP References See the ST Micro M24C08 WDWOAOTP data sheet for more information at http www st com stonline products literature ds 5067 m24c08 w pdf In addition see the Xilinx XPS IIC Bus Interface Data Sheet at http www xilinx com support documentation ip documentation xps iic pdf 46 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX 16 Status LEDs Table 1 18 defines the status LEDs Table 1 18 Status LEDs Detailed Description Designator Signal Name Color Label Description DS1 SYSACE STAT LED GREEN Syste
76. e 1 38 System ACE CF CompactFlash Image Select DIP SW S1 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description MODE Boot EEPROM Select and CCLK Osc Enable DIP SW S2 DIP SW S2 is a multi purpose selector switch 52 switches 3 4 and 5 control the FPGA MODE as shown in Figure 1 39 page 59 and Table 1 25 page 59 DIP SW S2 switch 1 CCLK_EXTERNAL controls the enable pin of the 47 MHz oscillator SiT8102 X4 When S2 switch 1 is closed CCLK_EXTERNAL high X4 drives a 47 MHz clock onto signal FPGA_CCLK DIP SW S2 switch 2 is used to select the between the Xilinx Platform Flash or the Numonyx Linear Flash BPI for the FPGA boot memory device DIP SW S2 switch 6 is used to select the lower or upper half of flash memory U4 as the source of the FPGA bitstream image VCC2V5 510 5 CCLK EXTERNAL 1 P30_CS_SEL FPGA MO mu FPGA M1 FPGA M2 FLASH A23 R43 4 7K R50 o o o o o o 116w n 596 596 1 16W n 596 1 16W n 596 1 16W n 596 1 16W mw UG534 34 073109 Figure 1 39 FPGA MODE Boot EEPROM Select DIP SW S2 DIP SW 82 is a multi purpose selector switch S2 switches 3 4 and 5 control the FPGA MODE as shown in Table 1 25 Table 1 25 ML605 Configuration Modes Configuration Mode M 2 0 Bus Width CCLK Master BPI Up 010 8 16 Output JTAG 101 1 Input TCK Slave SelectMAP 110 8 16 32 Input ML605 Hardware User
77. e ended or 34 differential user defined signals e 1MGT e 1 MGT clock e 2 differential clocks e 61 ground 10 power connections Of the above signal and clock connectivity capability the ML605 implements the full set e 34 differential user defined pairs 34 LA pairs e 1MGT e 1 MGT clock e 2 differential clocks Signaling Speed Ratings e Single ended 9 GHz 18 Gb s e Differential Optimal Vertical 9 GHz 18 Gb s Optimal Horizontal 16 GHz 32 Gb s High Density Vertical 7 GHz 15 Gb s Mechanical specifications e Samtec SEAM SEAF Series e 1 27mm x 127mm 0 050 x 0 050 pitch The Samtec connector system is rated for signaling speeds up to 9 GHz 18 Gb s based on a 3 dB insertion loss point within a two level signaling environment Note The ML605 board VADJ voltage for the FMC HPC and LPC connectors J64 and J63 is fixed at 2 5V non adjustable The 2 5V rail cannot be turned off The ML605 VITA 57 1 FMC interfaces are compatible with 2 5V mezzanine cards capable of supporting 2 5V VADJ Pin outs and UCF location constraints for the FMC LPC connector are shown in Figure 1 42 and Figure 1 43 The FPGA connection tables for the FMC HPC and LPC connectors may be found in Appendix C VITA 57 1 FMC Connections in Table C 1 and Table C 2 respectively ML605 Hardware User Guide www xilinx com 67 UG534 v1 0 August 17 2009 XILINX Chapter 1 ML605 Evaluation Board UG534 072009 28 Figure 1 42 FMC LPC Co
78. ector P4 e One 1 MGT is used for an SGMII connection to the Ethernet PHY U80 ML605 Hardware User Guide www xilinx com 31 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board g XILINX References See the Virtex 6 FPGA GTX Transceivers User Guide for more information at http www xilinx com support documentation user_guides ug366 pdf 9 PCI Express Endpoint Connectivity The 8 lane PCIe edge connector performs data transfers at the rate of 2 5 GT s for a Gen1 application and 5 0 GT s for a Gen2 application The Virtex FPGA GTX MGTs are used for the multi gigabit per second serial interfaces The ML605 board trace impedance on all PCIe lanes supports both Gen1 and Gen applications The ML605 supports up to Gen1 x8 and Gen2 x4 as shipped with a 1 speed grade for the LX240T device Figure 1 16 page 32 shows the PCIe MGT bank 114 and 115 clocking diagram Note PCIe edge connector signal nomenclature is from perspective of the system mother board Pi Q1 PCIE 100M MGT1 P N CLK Qj PCIE 250M MGT 1 C P N IC5874001 ICS854104 Ui Ui Bank 115 Bank 114 MGTREFCLKOP N MGTREFCLKOP N PCIE 100M MGTO P N MGTTX MGTRX MGTTX MGTRX P N 3 0 P N 3 0 P N 7 4 P N 7 4 PCIE 250M MGT1 P N Figure 1 16 PCle MGT Banks 114 and 115 Clocking PCIe Lane width size is selected via jumper J42 as shown in Figure 1 17 page 32 J42 PCIE PRSNT X1 I2 PC
79. efault Interface Mode Jumper Settings Mode J22 J23 J24 GMII MII to copper i default Jumper over pins 1 2 Jumper over pins 1 2 No jumper SGMII to copper E no clock Jumper over pins 2 3 Jumper over pins 2 3 No jumper RGMII Jumper over pins 1 2 No jumper Jumper on On power up or on reset the PHY is configured to operate in GMII mode with PHY address 0b00111 using the settings shown in Table 1 11 These settings can be overwritten via software commands passed over the MDIO interface Table 1 11 Board Connections for PHY Configuration Pins Pin Connection on Bit 2 Bit 1 Bit 0 Board Definition and Value Definition and Value Definition and Value CFGO Vec 2 5V PHYADR 2 1 PHYADR 1 1 PHYADR 0 1 CFG1 Ground ENA_PAUSE 0 PHYADR 4 0 PHYADR 3 0 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description Table 1 11 Board Connections for PHY Configuration Pins Cont d Pin Connection on Bit 2 Bit 1 Bit 0 Board Definition and Value Definition and Value Definition and Value CFG2 Vec 2 5V ANEG 3 1 ANEG 2 1 ANEG 1 1 CFG3 Vec 2 5V ANEG 0 1 ENA XC 1 DIS 125 1 CFG4 Vec 2 5V HWCFG MD 2 1 HWCFG_MD 1 1 HWCFG_MD 0 1 CFG5 Vec 2 5V DIS_FC 1 DIS SLEEP 1 HWCFG MDJ 3 1 CFG6 PHY LED RX SEL BDT 0 INT POL 1 75 50 OHM 0 SGMII GTX Transceiver Clock Ge
80. eive pair K5 PCIE RX1 P B19 Integrated Endpoint GTXE1_X0Y14 K6 PCIE_RX1_N B20 block receive palr L3 PCIE_RX2_P B23 Integrated Endpoint GTXE1_X0Y13 L4 PCIE_RX2_N B24 block receive palr N3 PCIE RX3 P B27 Integrated Endpoint GTXEL XOYU N4 PCIE_RX3_N B28 block receive palr R3 PCIE_RX4_P B33 Integrated Endpoint GTXE1_X0Y10 R4 PCIE_RX4_N B34 block receive palr U3 PCIE_RX5_P B37 Integrated Endpoint GTXEL X0Y9 U4 PCIE_RX5_N B38 block receive pair W3 PCIE_RX6_P B41 i Integrated Endpoint GTXEL X0Y8 WA PCIE RX6 N B42 block receive pair AA3 PCIE RX7 P B45 i Integrated Endpoint GTXEL X0Y7 AA4 PCIE_RX7_N B46 block receive palr www xilinx com 33 ML605 Hardware User Guide UG534 v1 0 August 17 2009 34 Chapter 1 ML605 Evaluation Board g XILINX Table 1 7 PCle Edge Connector Connections Cont d ui FOGA Schematic Netname Br Ole Edge Description Package Pin Connector Placement P6 PCIE_100M_MGT0_P ado Por oe ICS854104 GIXE1_X0Y6 P5 PCIE_100M_MGTO_N U14 15 clock driver Sourced from U9 V6 PCIE_250M_MGT1_N U9 18 ICS874001 GTXE1_X0Y4 clock V5 PCIE_250M_MGT1_P U9 17 S E multiplier driver U14 6 PCIE CLK QO P A13 Integrated Endpoint block differential clock U14 7 PCIE_CLK_QO_N A14 pair from PCIe edge connector J42 2 4 6 PCIE PRSNT B AI ee jumper Integrated Endpoint block wake signal not AD22 PCIE WAKE B ER connected on ML605 board AE13 PCIE_PERST_B All Integrated Efidpojnt
81. ers J17 and J18 must be connected between pins 1 2 bypass to enable JTAG access to the FPGA on the basic ML605 board without FMC expansion modules installed as shown in Figure 1 9 and Figure 1 10 When either or both VITA 57 1 FMC expansion connectors are populated with an expansion module that has a JTAG chain the respective jumper s must be set to connect pins 2 3 in order to include the FMC expansion module s JTAG chain in the main ML605 JTAG chain J17 1 FMC_TDI_BUF Bypass FMC HPC J64 Jumper 1 2 2 FMC_LPC_TDI i Include FMC HPC J64 Jumper 2 3 FMC HPC TDO H 1x3 UG534 40 081309 Figure 1 9 VITA 57 1 FMC HPC J64 JTAG Bypass Jumper J17 J18 1 FMC LPC TDI Bypass FMC LPC J63 Jumper 1 2 2 SYSACE TDI i Include FMC LPC J63 Jumper 2 3 FMC_LPC_TDO H 1x3 UG534_41_081309 Figure 1 10 VITA 57 1 FMC LPC J63 JTAG Bypass Jumper J18 ML605 Hardware User Guide www xilinx com 29 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board XILINX The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software debug The JTAG connector USB Mini B J22 allows a host computer to download bitstreams to the FPGA using the Xilinx IMPACT software tool In addition the JTAG connector allows debug tools such as the ChipScope Pro Analyzer tool or a software debugger to access the FPGA The iMPACT software tool can also program the BPI flash via the USB J22 connection iMPACT can down
82. ge 73 for further details on 12V input current sensing Green LED DS25 will illuminate when the ML605 board power is on See section 21 Power Management page 70 for details on the onboard power system VCC12 P IN e VCC12 P DPDT R346 Power ATX Peripheral Cable Connector can plug into J25 when ML605 is in PC and the desk top AC adapter brick is not used J25 1 2 C280 E2 SE 0 5 0 001R 2 1 16W 16V Y14880R00100B09R n ELEC sw2 awe E 1201M2S3ABE2 3 Y 8 Ix Z o lo ES 3 CAUTION DO NOT plug a PC ATX power supply 6 pin connector into the J60 connector on the ML605 board The ATX 6 pin connector has a different pinout than J60 and will damage the ML605 board and void the board warranty DO NOT plug an auxilliary PCle 6 pin molex power connector into the J60 connector as this could damage the PCle motherboard and or the ML605 board J60 is marked with a NO PCIE POWER label to warn users of the poten tial hazard DO NOT apply power to J60 and the 4 pin ATX disk drive connector J25 at the same time as this will damage the ML605 board UG534_30 _081209 Figure 1 85 Power On Off Slide Switch SW2 56 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description FPGA PROG B Pushbutton SW4 Active Low This switch grounds the FPGA s PROG B pin when pressed This action clears the FPGA See the Virtex 6 FPGA data sheet fo
83. ge Channel gt I VAUXN 12 UG534 38 081209 1k Figure 1 47 ML605 12V Power Monitor ML605 Hardware User Guide www xilinx com 75 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board XILINX Fan Controller In highly demanding situations active thermal management in the form of a heatsink and fan may be required In order to support this drive circuitry for an external fan has been provided on the ML605 A fan with tach output can be connect at header J59 as shown in Figure 1 48 The fan PWM signal is generated by the FPGA and the tach input can be used to close the control loop and regulate the fan speed Alternatively the FPGA temperature as recorded by the System Monitor can be used to close the PWM control loop for the fan VCC12 P SM FAN TACH VCC2V5 1N4148 UG534 39 081209 Figure 1 48 ML605 Fan Driver 76 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description FPGA Power Supply Margining The PMBus IIC which provides access to the 2 x UDC9240 power controllers can also be accessed via FPGA I O in addition to a dedicated header J3 see Figure 1 49 A full description of the UDC9240 functionality is outside the scope of this user guide However this useful feature can be used for example to margin the FPGA and board power supplies when evaluating a design The System Monitor provides accurate measurements of the on chip supply vo
84. h to read write code or data When the FPGA design does not use the configuration flash the FPGA design must drive the FPGA FCS B pin High in order to disable the configuration flash and put the flash into a quiescent low power state Otherwise the Platform Flash XL in particular can continue to drive its array data onto the data bus causing unnecessary switching noise and power consumption For FPGA designs that access the flash for reading writing stored code or data connect the FPGA design or EDK embedded memory controller EMC peripheral to the flash through the pins defined in Table 1 5 page 24 or Figure 1 7 page 26 The Platform Flash XL defaults to a synchronous read mode Typically the Platform Flash XL requires an initialization procedure to put the Platform Flash XL into the common asynchronous read mode before accessing stored code or data To put the Platform Flash XL into asynchronous read mode apply the Set Configuration Register command sequence See DS617 Platform Flash XL High Density Configuration and Storage Device Data Sheet for details on the Set Configuration Register command References See the Numonyx Flash Memory specifications for more information at http www numonyx com Documents Datasheets 306666 P30 Discrete DS pdf In addition on the Xilinx Platform Flash product page at http www xilinx com products config mem pf htm click the Resources tab for more information Also see the
85. ilinx com 13 Chapter 1 ML605 Evaluation Board XILINX The ML605 supports Master BPI Up JTAG and Slave SelectMAP These are selected by setting M 2 0 options 010 101 and 110 shown in Table 1 2 Table 1 2 Virtex 6 FPGA Configuration Modes Configuration Mode M 2 0 Bus Width 1 CCLK Direction Master Serial 000 1 Output Master SPI 001 1 Output Master BPI Up 2 010 8 16 Output Master BPI Down 011 8 16 Output Master SelectMAP 2 100 8 16 Output JTAG 101 1 Input TCK Slave SelectMAP 110 8 16 32 Input Slave Serial 111 1 Input Notes 1 The parallel configuration modes bus is auto detected by the configuration logic 2 In Master configuration mode the CCLK pin is the clock source for the Virtex 6 FPGA internal ups da i logic The Virtex 6 FPGA CCLK output pin must be free from reflections to avoid double clocking the internal configuration logic See the Virtex 6 FPGA Configuration User Guide for more details 3 This is the default setting due to internal pull up termination on mode pins For an overview on configuring the FPGA see Configuration Options page 78 References See the Virtex 6 FPGA Configuration User Guide for detailed configuration information at http www xilinx com support documentation user guides ug360 pdf I O Voltage Rails There are 16 I O banks available on the Virtex 6 device The voltage applied to the FPGA I O banks used by
86. ing typographical conventions are used in this document Convention Meaning or Use Example Messages prompts and Courier font program files that the system speed grade 100 displays Literal commands that you enter Conr rar Dold in a syntactical statement ngdbuild design_name Commands that you select from File Open Helvetica bold mE Keyboard shortcuts Ctrl C ML605 Hardware User Guide www xilinx com 5 UG534 v1 0 August 17 2009 Preface About This Guide XILINX Convention Italic font Meaning or Use Variables in a syntax statement for which you must supply values Example ngdbuild design name References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild option name design name Braces A list of items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Vertical ellipsis Repetitive material that has been omitted IOB 1 IOB 2 Name Name QOUT CLKIN Horizontal ellipsis Repetitive material that has been omitted allow block
87. installed during operations utilizing the CompactFlash card Every time a CompactFlash card is inserted into the System ACE CF socket a configuration operation is initiated Pressing the System ACE CF reset button re programs the FPGA Note System ACE CF configuration is enabled by way of DIP switch S1 See 18 Switches page 56 for more details The System ACE CF MPU port is connected to the FPGA This connection allows the FPGA to use the System ACE CF controller to reconfigure the system or access the CompactFlash card as a generic FAT file system References See the System ACE CF product page for more information at http www xilinx com support documentation system ace solutions htm In addition see the System ACE CF data sheet at http www xilinx com support documentation data sheets ds080 pdf www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX m E m o 5 Detailed Description 6 USB JTAG JTAG configuration is provided through onboard USB to JTAG configuration logic where a computer host accesses the ML605 JTAG chain through a Type A computer host side to Type Mini B ML605 side USB cable The JTAG chain of the board is illustrated in Figure 1 8 JTAG configuration is allowable at any time under any mode pin setting JTAG initiated configuration takes priority over the mode pin settings UG534_02_081309 Figure 1 8 JTAG Chain Diagram FMC bypass jump
88. load a temporary design to the FPGA through the JTAG This provides a connection within the FPGA from the FPGA s JTAG port to the FPGA s BPI interface Through the connection made by the temporary design in the FPGA iMPACT can indirectly program the BPI flash or the Platform Flash XL from the JTAG USB J22 connector For an overview on configuring the FPGA see Configuration Options page 78 7 Clock Generation There are three FPGA fabric clock sources available on the ML605 Oscillator Differential The ML605 has one 2 5V LVDS differential 200 MHz oscillator U11 soldered onto the board and wired to an FPGA global clock input e Crystal oscillator Epson EG2121CA 200 0000M LHPA e PPM frequency jitter 50 ppm NET SYSCLK N LOC H9 NET SYSCLK P LOC J9 Figure 1 11 UCF Location Constraints for Oscillator Connections For more details see the Epson data sheet at http www epsontoyocom co jp english product OSC set04 eg2121ca index html Oscillator Socket Single Ended 2 5V One populated single ended clock socket X2 is provided for user applications The option of 3 3V or 2 5V power may be selected via a 0 ohm resistor selection The X2 socket is populated with a 66 MHz 2 5V single ended MMD Components MBH2100H 66 000 MHz oscillator NET USER CLOCK LOC U23 Figure 1 12 UCF Location Constraints for Oscillator Socket Connections For more details see the MMD Components data sheet at http www
89. ltages as the FPGA supplies are margined The PMBus and fan connections are shown in Figure 1 49 TI V3P3 UDC9240 PMBUS CLK 19 PMBUS CTRL 36 BANK 34 TEE 6v1x240tff1156 PMBUS CTRL LS PMBUS ALERT LS PMBUS DATA LS PMBUS CLK LS SM FAN TACH IO L11N SRCC 34 AJ9 IO L11P SRCC 34 AH9 IO L10N MRCC 34 AB10 IO L10P MRCC 34 AC10 IO L9N MRCC 34 M10 IO L9P MRCC 34 L10 UG534 35 081209 Figure 1 49 UDC9240 PMBus Access System Monitor ML605 Demonstration Design The various features described in this section are easily evaluated using a MicroBlaze based reference designed provided with the ML605 Evaluation Board This reference design supports a UART based interface using a terminal program such as Hyperterminal to provide information on the FPGA power supplies temperature and power consumption In addition the UART interface can be used to margin the FPGA supplies over the PMBus The System Monitor functionality can also be accessed at any time via JTAG using the ChipScope Pro Analyzer tool without design modifications or cores inserted into a user design The ChipScope Pro Analyzer tool automatically connects to the System Monitor via a JTAG cable after a connection is established References For more information on using the System Monitor and an overview of the tool support for this feature refer to UG370 ML605 Hardware User Guide www xilinx com 77 UG534 v1 0 August 17 2009 Chapter 1 ML605
90. m ACE CF System ACE CF Status Status LED DS2 TI PWRGOOD and GREEN POWER GOOD Both UCD9240 controllers MGT TI PWRGOOD report power good DS13 FPGA_DONE GREEN DONE FPGA configured successfully DS23 LED_GRN GREEN STATUS USB JTAG Connection Status Dual LED LED_RED RED DS25 12V GREEN 12V 12V Power On DS27 MGT_AVCC GREEN MGT AVCC Power On DS28 MGT_AVTT GREEN MGT_AVTT MGT AVTT Power On DS29 DDR3_VTTDDR_PWRGOOD GREEN DDR3 VTTDDR Power Good DS30 SYSACE_ERR_LED RED System ACE CF System ACE CF Error Error LED DS31 FPGA_INIT_B RED INIT FPGA Initialization in progress DS32 DVI_GPIO1_FMC_C2M_PG GREEN FMC PWR GD FMC Power Good Ethernet PHY Status LEDs The Ethernet PHY status LEDs are mounted to be visible when the ML605 board is installed into a PC motherboard They are mounted in right angle plastic housings and can be seen on the connector end of the board This cluster of six LEDs is installed adjacent to the RJ45 Ethernet jack P2 ML605 Hardware User Guide UG534 v1 0 August 17 2009 ALA DUP 10 Silkscreen TX 100 on board RX 1000 E Direction Link Rate P2 Indicator EE End view of ML605 Ethernet jack and status LEDs when installed vertically in a PC chassis Mbps Figure 1 26 Ethernet PHY Status LEDs www xilinx com 47 Chapter 1 ML605 Evaluation Board XILINX FPGA INIT and DONE LEDs The typical Xilinx FPGA power up and configuration status LEDs are present on the ML605
91. mmdcomp com pdf XO MBH111306L pdf SMA Connectors Differential A high precision clock signal can be provided to the FPGA using differential clock signals through the onboard 50 ohm SMA connectors J58 P J55 N NET USER SMA CLOCK N LOC NET USER SMA CLOCK P LOC Figure 1 13 UCF Location Constraints for SMA Connectors Connections M22 L23 30 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description GTX SMA Clock The ML605 includes a pair of SMA connectors for a GTX MGT Clock as described in Figure 1 14 and Table 1 6 J30 32K10K 400E3 T i SMA_REFCLK_C_N1 kel LL 013 DS SX B SMA REFCLK N E SMA_REFCLK_P Ja SMA REFCLK C P1 Sg SIG GND4 Sek oreet GND5 SFX GND6 GND7 UG534_12_081309 Figure 1 14 GTX SMA Clock Table 1 6 GTX SMA Clock Connections U1 FPGA Pin Schematic Netname SMA Pin F5 SMA_REFCLK_N J30 1 F6 SMA_REFCLK_P J31 1 NET SMA REFCLK N LOC F5 NET SMA REFCLK P LOC F6 Figure 1 15 UCF Location Constraints for GTX SMA Clock 8 Multi Gigabit Transceivers GTX MGTs The ML605 provides access to 20 MGTs e Eight 8 of the MGTs are wired to the PCIe x8 Endpoint P1 edge connector fingers e Eight 8 of the MGTs are wired to the FMC HPC connector J64 e One 1 MGT is wired to SMA connectors J26 J27 e One 1 MGTs is wired to the FMC LPC connector J63 e One 1 MGT is wired to the SFP Module conn
92. n Fixed 200 MHz oscillator differential Socket for a user populated 2 5V oscillator single ended SMA connectors differential SMA connectors for MGT clocking Multi Gigabit Transceivers GTX MGT e FMC HPC connector FMC LPC connector SMA PCIe SFP Module connector Ethernet PHY SGMII interface PCle Endpoint connectivity Genl8 lane x8 Gen2 4 lane x4 SFP module connector Gigabit Ethernet 10 100 1000 Mb s USB to UART bridge USB host and peripheral controller DVI codec and connector IIC buses 4 IIC EEPROM 1 KB e DDR3SODIMM socket DVI codec DVI connector FMC HPC connector e FMC LPC connector SFP module connector www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX ML605 Hardware User Guide Overview Status LEDs Ethernet status FPGA INIT FPGA DONE System ACE CF Status User I O USER LED Group 1 GPIO 8 USER LED Group 2 directional 5 User pushbuttons directional 5 CPU reset pushbutton User DIP switch GPIO 8 pole User SMA GPIO connectors 2 LCD character display 16 characters x 2 lines Switches Power on off slide switch System ACE CF reset pushbutton System ACE CF bitstream image select DIP switch Configuration MODE DIP switch Expansion ports FMC VITA 57 High Pin Count HPC FMC VITA 57 Low Pin Count LPC Power Management control and monitoring e
93. n Table 1 5 Platform Flash and BPI Flash Connections Cont d U27 Platform and control S2 switch 2 as shown in Figure 1 6 page 23 ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com U1 FPGA Pin Schematic Netname U4 BPI Flash Flash AF24 FLASH DO 34 F2 AF25 FLASH D1 36 E2 W24 FLASH DO 39 G3 V24 FLASH D3 41 E4 H24 FLASH D4 47 E5 H25 FLASH_D5 49 G5 P24 FLASH_D6 51 G6 R24 FLASH_D7 53 H7 G23 FLASH_D8 35 El H23 FLASH_D9 37 E3 N24 FLASH D10 40 F3 N23 FLASH D11 42 F4 F23 FLASH D12 48 F5 F24 FLASH D13 50 H5 L24 FLASH D14 52 G7 M23 FLASH D15 54 E7 J26 FLASH_WAIT 56 Not Applicable AF23 FPGA_FWE_B 14 G8 AA24 FPGA FOE B 32 F8 K8 FPGA CCLK NA F1 AC23 PLATFLASH L B NA H1 Y24 FPGA_FCS_B 1 30 B4 Notes 1 FPGA_FCS_B is routed to U4 BPI Flash pin 30 or U27 Platform Flash XL pin B4 via U10 25 Chapter 1 ML605 Evaluation Board XILINX Figure 1 7 provides the UCF constraints for the parallel wired Platform Flash and BPI Flash memories NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET FLASH AO FLASH AT FLASH A2 FLASH A3 FLASH A4 FLASH A5 FLASH A6 FLASH A7 FLASH A8 FLASH A9 FLASH A10 FL
94. n folder containing eight sub folders used to store the eight ACE files containing the configuration images Only one ACE file should exist within each sub folder All folder names must be compliant to the DOS 8 3 short file name format This means that the folder names can be up to eight characters long and cannot contain the following reserved characters lt gt This DOS 83 file name restriction does not apply to the actual ACE ML605 Hardware User Guide www xilinx com 27 UG534 v1 0 August 17 2009 28 Chapter 1 ML605 Evaluation Board XILINX file names Other folders and files may also coexist with the System ACE CF project within the FAT16 partition However the root directory must not contain more than a total of 16 folder and or file entries including deleted entries When ejecting or unplugging the CompactFlash device it is important to safely stop any read or write access to the CompactFlash device to avoid data corruption System ACE CF error and status LEDs indicate the operational state of the System ACE CF controller e A blinking red error LED indicates that no CompactFlash card is present e Asolid red error LED indicates an error condition during configuration e A blinking green status LED indicates a configuration operation is ongoing e A solid green status LED indicates a successful download Note Jumper J69 can be removed to disable the Red Error LED circuit It is recommended that this jumper is
95. n is partially populated with 160 pins The 10 x 40 rows of a FMC HPC connector provides connectivity for e 160 single ended or 80 differential user defined signals e 10MGTs e 2 MGT clocks e 4 differential clocks e 159 ground 15 power connections Of the above signal and clock connectivity capability the ML605 implements the following subset e 78 differential user defined pairs 34 LA pairs 12 HA pairs 10 HB pairs e 8 MGTs www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description e 2MGT clocks e 4 differential clocks Signaling Speed Ratings e Single ended 9 GHz 18 Gb s e Differential Optimal Vertical 9 GHz 18 Gb s Optimal Horizontal 16 GHz 32 Gb s High Density Vertical 7 GHz 15 Gb s Mechanical specifications e Samtec SEAM SEAF Series e 127mm x 1 27mm 0 050 x 0 050 pitch The Samtec connector system is rated for signaling speeds up to 9 GHz 18 Gb s based on a 3dB insertion loss point within a two level signaling environment Note The ML605 board VADJ voltage for the FMC HPC and LPC connectors J64 and J63 is fixed at 2 5V non adjustable The 2 5V rail cannot be turned off The ML605 VITA 57 1 FMC interfaces are compatible with 2 5V mezzanine cards capable of supporting 2 5V VADJ Pinouts and UCF location constraints for the FMC HPC connector is shown in Figure 1 40 and Figure 1 41 The FPGA connection tables for the FMC HPC and LP
96. n iti Schematic Netname ui us E22 FMC HPC HB03 N AM31 F22 FMC HPC HBO2 P AP32 E24 FMC_HPC_HB05_P AN33 F23 FMC_HPC_HB02_N AP33 E25 FMC_HPC_HB05_N AN34 F25 FMC_HPC_HB04_P AM33 E27 FMC_HPC_HB09_P AL34 F26 FMC_HPC_HB04_N AL33 E28 FMC_HPC_HB09_N AK34 F28 FMC_HPC_HB08_P AK33 E30 FMC_HPC_HB13_P AH33 F29 FMC HPC HB08 N AK32 E31 FMC HPC HB13 N AH32 F31 FMC HPC HPB12 P AJ31 E33 FMC HPC HB19 P AL31 F32 FMC HPC HB12 N AJ32 E34 FMC HPC HB19 N AK31 F34 FMC HPC HB16 P AH29 F35 FMC HPC HB16 N AH30 G2 FMC HPC CLKI M2C P AP20 H2 FMC HPC PRSNT M2C L AP25 G3 FMC_HPC_CLK1_M2C_N AP21 H4 FMC_HPC_CLK0_M2C_P K24 G6 FMC_HPC_LA00_CC_P AF20 H5 FMC_HPC_CLK0_M2C_N K23 G7 FMC_HPC_LA00_CC_N AF21 H7 FMC_HPC_LA02_P AC20 G9 FMC_HPC_LA03_P AC19 H8 FMC_HPC_LA02_N AD20 G10 FMC_HPC_LA03_N AD19 H10 FMC HPC LAQA P AF19 G12 FMC HPC LAO08 P AK22 H11 FMC HPC LA04 N AE19 G13 FMC HPC LAOS N AJ22 H13 FMC HPC LAO7 P AK21 G15 FMC HPC LA12 P AM21 H14 FMC_HPC_LA07_N AJ21 G16 FMC HPC LA12 N AL21 H16 FMC HPC LA11 P AM22 G18 FMC HPC LA16 P AP22 H17 FMC HPC LA11 N AN22 G19 FMC HPC LA16 N AN23 H19 FMC_HPC_LA15_P AM23 G21 FMC HPC LA20 P AK23 H20 FMC HPC LA15 N AL23 G22 FMC HPC LA20 N AL24 H22 FMC HPC LA19 P AN25 G24 FMC_HPC_LA22_P AP27 H23 FMC_HPC_LA19_N AN24 G25 FMC HPC LA22 N AP26 H25 FMC HPC LA21 P AN29 G27 FMC_HPC_LA25_P AN28 H26 FMC_HPC_LA21_N AP29 G28 FMC_HPC_LA25_N AM28 H28 FMC HPC LA24 P AN30 G30 FMC_HPC_LA29_P AL28 H29 FMC_HPC_LA24_ N AM30 G31 FMC HPC LA29 N AK28 H31 FMC HPC LA28 P AK27 G33
97. ned not to also connect an ATX 4 pin power connector to J25 See the caution notes below and in Figure 1 35 page 56 Caution DO NOT plug a PC ATX power supply 6 pin connector into ML605 connector J60 The ATX 6 pin connector has a different pinout than ML605 J60 and connecting the ATX 6 pin connector will damage the ML605 and void the board warranty Caution DO NOT apply power to J60 and the 4 pin ATX disk drive connector J25 at the same time as this will damage the ML605 board Refer to Figure 1 35 page 56 for details The ML605 power can be turned on or off through the board mounted slide switch SW2 When the switch is in the on position a green LED DS25 is illuminated www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description Onboard Power Regulation Figure 1 44 shows the ML605 onboard power supply architecture The ML605 uses power solutions from Texas Instruments Power Supply Power Controller 1 Linear Regulator 5 0V Q 1 5A max Switching Module VCCINT 920A max Switching Module FMC VADJ Q20A max Switching Module 2 5V 20A max Linear Regulator 1 8V 9 500mA max Power Controller 2 Switching Regulator MGT_VCC 6A max Switching Regulator MGT_VTT 6A max Switching Module 1 5V 920A max Switching Module 3 3V 9 20A max Sink Source DDR Regulator VTT VREF GA BA max UG534_13_072109 Figure 1 44 ML605 Onboard Power Regulators ML605
98. neration An Integrated Circuit Systems ICS844021I chip generates a high quality low jitter 125 MHz LVDS clock from an inexpensive 25 MHz crystal oscillator This clock is sent to the GTX driving the SGMII interface Series AC coupling capacitors are also present to allow the clock input of the FPGA to set the common mode voltage Table 1 12 shows the connections and pin numbers for the PHY Table 1 12 Ethernet PHYConnections U1 FPGA Pin Schematic Netname U80 M88E1111 AN14 PHY_MDIO 33 AP14 PHY_MDC 35 AH14 PHY_INT 32 AH13 PHY_RESET 36 AL13 PHY_CRS 115 AK13 PHY_COL 114 AP11 PHY_RXCLK 7 AG12 PHY_RXER 8 AM13 PHY_RXCTL_RXDV 4 AN13 PHY RXDO 3 AF14 PHY_RXD1 128 AE14 PHY_RXD2 126 AN12 PHY_RXD3 125 AM12 PHY_RXD4 124 AD11 PHY_RXD5 123 AC12 PHY_RXD6 121 AC13 PHY_RXD7 120 AH12 PHY_TXC_GTXCLK 14 AD12 PHY_TXCLK 10 AH10 PHY_TXER 13 ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 37 Chapter 1 ML605 Evaluation Board Table 1 12 Ethernet PHYConnections Cont d U1 FPGA Pin Schematic Netname U80 M88E1111 AJ10 PHY_TXCTL_TXEN 16 AM PHY TXDO 18 AL11 PHY TXD1 19 AG10 PHY_TXD2 20 AG11 PHY_TXD3 24 AL10 PHY_TXD4 25 AM10 PHY TXD5 26 AE11 PHY_TXD6 28 AF11 PHY_TXD7 29 A3 SGMII TX P 113 A4 SGMII TX N 112 B5 SGMII RX P 107 B6 SGMII RX N 105 XILINX 38 www xilin
99. nnector Pinout ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 68 XILINX Detailed Description NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET FMC LPC CLKO M2C N FMC LPC CLKO M2C P FMC LPC CLK1 M2C N FMC LPC CLK1 M2C P FMC LPC DPO C2M N FMC LPC DPO C2M P FMC LPC DPO M2C N FMC LPC DPO M2C P FMC LPC GBTCLKO M2C N FMC LPC GBTCLKO M2C P FMC LPC IIC SCL LS FMC LPC IIC SDA LS FMC LPC LAO0 CC N FMC LPC LAO0 CC P FMC LPC LAO1 CC N FMC LPC LAO1 CC P FMC LPC LAO2 Hu FMC LPC LAO2 P FMC LPC LAQ3 Hu FMC LPC LAQ3 P FMC LPC LAO4 N FMC LPC LAO4 P FMC LPC LAOS Hu FMC LPC LAOS P FMC LPC LAO6 Hu FMC LPC LAO6 P FMC LPC LAO7 Hu FMC LPC LAO7 P FMC LPC LAO8 Hu FMC LPC LAO8 P FMC LPC LAO9 N FMC LPC LAO9 P FMC LPC LA10 N FMC LPC LA10 P FMC LPC LA11 N FMC LPC LA11 P FMC LPC LA12 N FMC LPC LA12 P FMC LPC LA13 N FMC LPC LA13 P FMC LPC LA14 N FMC LPC LA14 P FMC LPC LA15 Hu FMC LPC LA15 P FMC LPC LA16 N FMC LPC LA16 P FMC LPC LA17 CC N FMC LPC LA17 CC P FMC LPC LA18 CC N FMC LPC LA18 CC P FMC LPC LA19 N FMC LPC LA19 P FMC LPC LA20 N F
100. not to scratch or damage the surface of the LCD window VCC5 VCC5 R158 J41 LCD DB7 1 2 LCD DB6 32 NI S LCD_DB5 3 E 03 LCD DB4 32 681K 1 NC 5 l6 NC n NC 7 ERE NG R270 LCD_E 9 LCD_RW 32 0 2K LCD_RS 11 o OT LCD_VEE 2 1 2W 13 LOO0 4 7 20 107 01 T silkscreen SE EE re LCD Contrast E UG534 28 073109 Figure 1 83 LCD Header J41 and Contrast Trimpot R270 Table 1 24 LCD Header Connections U1 FPGA Pin Schematic Netname J41 Pin AD14 LCD_DB4_LS 4 AK11 LCD_DB5_LS 3 AJ LCD_DB6_LS 2 AE12 LCD_DB7_LS 1 AC14 LCD_RW_LS 10 T28 LCD RS LS 11 AK12 LCD_E_LS 9 54 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description User LEDs and GPIO Connector NET NET NET NET NET NET NET NET NET NET NET NET NET GPIO LED 0 GPIO LED 1 GPIO LED 2 GPIO LED 3 GPIO LED 4 GPIO LED 5 GPIO LED 6 GPIO LED 7 GPIO LED C GPIO LED W GPIO LED E GPIO LED S GPIO LED N User Pushbutton Switches NET NET NET NET NET NET GPIO_SW_C GPIO_SW_E GPIO_SW_N GPIO_SW_S GPIO_SW_W CPU_RESET User DIP Switch NET NET NET NET NET NET NET NET GPIO DIP SWI GPIO DIP SW2 GPIO DIP SW3 GPIO DIP SWA GPIO DIP SWS GPIO DIP SWG GPIO DIP SW7 GPIO DIP SW8 User SMA GPIO Connections NET USER SMA GPIO N NET USER SMA GPIO P LCD Header Connections NET NET NET NET NET
101. nx com support documentation user_guides ug368 pdf ML605 Hardware User Guide UG534 v1 0 August 17 2009 www xilinx com 39 40 Chapter 1 ML605 Evaluation Board XILINX 12 USB to UART Bridge The ML605 contains a Silicon Labs CP2103GM USB to UART bridge device U34 which allows connection to a host computer with a USB cable The USB cable is supplied in this evaluation kit Type A end to host computer Type Mini B end to ML605 connector J21 Table 1 13 details the ML605 J21 pinout Xilinx UART IP is expected to be implemented in the FPGA fabric for instance Xilinx XPS UART Lite The FPGA supports the USB to UART bridge using four signal pins Transmit TX Receive RX Request to Send RTS and Clear to Send CTS Silicon Labs provides royalty free Virtual COM Port VCP drivers which permit the CP2103GM USB to UART bridge to appear as a COM port to host computer communications application software for example HyperTerm or TeraTerm The VCP device driver must be installed on the host PC prior to establishing communications with the ML605 Refer to the evaluation kit Getting Started Guide for driver installation instructions Table 1 13 USB Type B Pin Assignments and Signal Definitions USE E Signal Name Description 1 VBUS 5V from host system not used 2 USB DATA N Bidirectional differential serial data N side 3 USB DATA P Bidirectional differential serial data P side 4 GROUND Sign
102. onnector to J60 6 pin molex on the ML605 board as this could result in damage to the PCle motherboard and or ML605 board www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description The 6 pin molex connector is marked with a no PCle power label to warn users of the potential hazard References See the following websites for more Virtex 6 FPGA Integrated Endpoint Block for PCT Express information e http www ilinx com products ipcenter V6 PCI Express Block htm es http wwwxilinx com support documentation ipbusinterfacei o pci express v6pciexpressendpointblock htm In addition see the PCI Express specifications for more information at http www pcisig com specifications pciexpress 10 SFP Module Connector The board contains a small form factor pluggable SFP connector and cage assembly that accepts SFP modules The SFP interface is connected to MGT Bank 116 on the FPGA The SFP module serial ID interface is connected to the SFP IIC bus see 15 IIC Bus page 44 for more information The control and status signals for the SFP module are connected to jumpers and test points as described in Table 1 8 The SFP module connections are shown in Table 1 9 Table 1 8 SFP Module Control and Status SFP Control Status Board Connection Signal Test Point J52 GER TX FAULT High Fault Low Normal Operation Jumper J65 SFP TX DISABLE Off SFP Enabled
103. r more information on clearing the contents of the FPGA VCC2V5 FPGA PROG FPGA PROG B Silkscreen EE PROG UG534 31 073109 Figure 1 36 FPGA PROG B Pushbutton SW4 SYSACE RESET B Pushbutton SW3 Active Low When the System ACE CF configuration mode pin is high enabled by closing DIP SW S1 switch 4 the System ACE CF controller configures the FPGA from the CompactFlash card when a card is inserted or the SYSACE RESET button is pressed See 5 Xilinx System ACE CF and CompactFlash Connector page 27 for more details silkscreen SYSACE RESET B SYSACE RESET Pushbutton SW3 UG534_32_073109 Figure 1 37 System ACE CF RESET_B Pushbutton SW3 ML605 Hardware User Guide www xilinx com 57 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board XILINX 58 System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash CF image select DIP SW S1 switches 1 3 select which CF resident bitstream image will be downloaded to the FPGA S1 switches 1 3 offer eight binary addresses When on high the 1 switch 4 enables the System ACE CF controller to configure the FPGA from the CF card when a card is inserted or the SYSACE RESET button is pressed See 5 Xilinx System ACE CF and CompactFlash Connector page 27 for more details VCC2V5 510 5 SYSACE_CFGADDRO SYSACE_CFGADDRI SYSACE_CFGADDR2 SYSACE_CFGMODEPIN SDMX 4 X UG534_33_073109 Figur
104. rom BPI Flash on 1 EXT_CCLK 0 off ML605 Hardware User Guide www xilinx com 81 UG534 v1 0 August 17 2009 Appendix B Default Switch and Jumper Settings 82 Table B 2 Default Jumper Settings XILINX Jumper REFDES Function Default GMII J65 hektesch Jump 1 2 J67 Bins 28 SGM to Cu no ck Jump 1 2 J68 J66 pins 1 2 J68 ON RGMII modified MII in Cu no jumper FMC Bypass J18 exclude FMC LPC connector Jump 1 2 J17 exclude FMC LPC connector Jump1 2 System Monitor J19 Test_mon_vrefp sourced by U23 REF3012 Jump 1 2 J35 measure voltage on R kelvin on 12V rail ed i D 5 SFP Module J54 Full BW Jump 1 2 J65 SFP Enable Jump 1 2 PCIe Lane Size J42 1 lane Jump 1 2 www xilinx com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Appendix C VITA 57 1 FMC Connections Table C 1 shows VITA 57 1 FMC HPC Connections Table C 2 shows VITA 57 1 FMC LPC Connections Table C 1 VITA 57 1 FMC HPC Connections KE Schematic Netname Si ten aedes Schematic Netname E dco A2 FMC HPC DP1 M2C P AE3 B12 FMC HPC DP7 M2C P AP5 A3 FMC HPC DP1 M2C N AF4 B13 FMC_HPC_DP7_M2C_N AP6 A6 FMC_HPC_DP2_M2C_P AF5 B16 FMC_HPC_DP6_M2C_P AM5 A7 FMC_HPC_DP
105. tion sections Additional Information Additional information and support material is located at e http www xilinx com ml605 This information includes e Current version of this user guide in PDF format e Example design files for demonstration of Virtex 6 FPGA features and technology e Demonstration hardware and software configuration files for the System ACE CF controller Platform Flash configuration storage device and linear flash chip e Reference design files e Schematics in PDF and DxDesigner formats e Bill of materials BOM e Printed circuit board PCB layout in Allegro PCB format e Gerber files for the PCB Many free or shareware Gerber file viewers are available on the internet for viewing and printing these files e Additional documentation errata frequently asked questions and the latest news For information about the Virtex 6 family of FPGA devices including product highlights data sheets user guides and application notes see the Virtex 6 FPGA documentation page at http www xilinx com support documentation virtex 6 htm ML605 Hardware User Guide www xilinx com 7 UG534 v1 0 August 17 2009 Chapter 1 ML605 Evaluation Board g XILINX Features The ML605 provides the following features Virtex 6 XC6VLX240T 1CFFG1156 FPGA DDR3 Memory 512MB SODIMM Platform Flash XL 128 Mb Linear Flash 32 MB System ACE CF controller with 2 GB CompactFlash card JTAG configuration Clock generatio
106. x com ML605 Hardware User Guide UG534 v1 0 August 17 2009 XILINX Detailed Description NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET PHY COL PHY CRS PHY INT PHY MDC PHY MDIO PHY RESET PHY RXCLK PHY RXCTL RXDV PHY RXDO PHY RXD1 PHY RXD2 PHY RXD3 PHY RXD4 PHY RXD5 PHY RXD6 PHY RXD7 PHY RXER PHY TXCLK PHY TXCTL TXEN PHY TXC GTXCLK PHY TXDO PHY TXD1 PHY TXD2 PHY TXD3 PHY TXD4 PHY TXD5 PHY TXD6 PHY TXD7 PHY TXER NET SGMII TX P NET SGMII TX N NET SGMII RX P NET SGMII RX N References LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC AK13 AL13 AH14 n ji AP14 AN14 AH13 n 7 AP11 AM13 AN13 AF14 AE14 AN12 AM12 AD11 AC12 AC13 AG12 AD12 AJ10 AH12 AM11 AL11 AG10 AG11 AL10 AM10 AE11 AF11 AH10 A3 nes AA ns BET s B6 Figure 1 19 UCF Location Constraints for PHY See the Marvell Alaska Gigabit Ethernet Transceiver product page for more information at http www marvell com products transceivers alaska gigabit index jsp In addition see the Xilinx Tri Mode Ethernet MAC User Guide at http www xili

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