Renesas HD151TS207SS User's Manual
Contents
1. REFO 56 FS B REF1 55 VDD A VDD REF 54 VSS A XTAL IN 53 VSS IREF XTAL OUT 52 IREF VSS REF 51 FS A FS2 PCIF_0 50 TEST_CLK FS4 PCIF_1 49 PCI STOP PCIF 2 48 VDD 4 VDD_PCI 47 CPU S e lS le es kl l le feo llo l I0 I I VSS_PCI MODE PCI_0 PCI 1 PCI 2 PCI 3 VDD PCI VSS PCI SEL100 200 PCI 4 SEL33 25 PCI 5 46 JC ru Q CPU 1 gt 43 CPU_1 Q 42 VDD CPU G 41 CPU 0 ev 40 CPU 0s 39 VSS_SRC O 38 SRC PCI 6 e 37 SRC PWRDWNZ SAFE Fit 36 VDD SRC 3V66_0 RESE 35 VTT_PWRGD V66 1 23 34 VDD 48 C 66 24 33 VSS 48 3V66 25 32 FS3 DOT 48 3V66_2 26 31 SEL48 24 USB 48 3V66_3 27 30 SDATA SCLK 28 29 SEL66 48 3V66 4 VCH Top view PCI STOP Z PWRDWN 150 kQ Internal Pull up Rev 1 00 Apr 25 2003 page 3 of 38 tENESAS HD151TS207SS Pin Descriptions Pin name No Type Description VSS A 54 Ground Ground for PLL VSS CPU 45 Ground for outputs VSS IREF 53 Ground for current reference VSS SRC 39 Ground for outputs VSS 3V66 25 VSS PCI 11 17 VSS REF 6 VSS 48 33 i VDD A 55 Power 3 3 V Power Supply for PLL VDD_CPU 42 48 3 3 V Power Supply for outputs 9 VDD SRC 36 e VDD 3V66 24 O VDD_PCI 10 16 VDD REF 3 Q VD2. Item Symbol Min Typ Max Cycle to cycle jitter tccs 250 S Fig 1 Note1 3V66 Buffer 3V66 4 0 tasks 0 ps Rising edge Group Skew 91 5 V to 1 5 V Cs Fig 2 Slew rate m 1 0 x 4 0 Vins 0 4V to 2 4 V Clock Period O 998 ns Clock Duty Cycle 50 55 3V66 4 0 leads 3 5 ns 33 MHz PCI Note 1 Difference of cycle time between two adjoining cycles Ww e Rev 1 00 Apr 25 2003 page 31 of 38 RENESAS HD151TS207SS DC Electrical Characteristics PCI amp PCIF Clock CK409T Types Buffer Ta 0 C to 70 C VDD 3 3 V x1 Item Symbol Min Typ Max Unit Test Conditions Output Voltage Vou 3 1 V lou 2 1 mA VDD 2 3 3 V VoL 50 mV lo 1 mA VDD 3 3 V Output Current loH 33 mA Von 1 0 V lot 30 mA Vor 1 95 V Note 1 For conditions shown as Min or Max use the appropriate value specified under recommended operating conditions X AC Electrical Characteristics PCI amp PCIF Clock SS Ta 0 C to 70 C VDD 3 3 V C 30 pF O Item Symbol Min Typ Max Test Conditions Notes Cycle to cycle jitter tccs 250 S Fig 1 Note1 Rising edge PCI Group Skew tskS 0 Goo ps 1 5V to 1 5 V Fig 2 Clock Period aN ns gt 0 4 V to Slew rate tsi 1 0 4 0 V ns 24V Clock Duty Cycle 4 Q 50 55 96 Note 1 Difference of cycle time n two adjoining cycles Ww e Rev 1 00 Apr 25 2003 page 3
3. Tablel Clock Frequency Function Table Byte6 FS_A FS_B CPU SRC ine PCIF REFO USB Note Bit5 MHz MHz PCI REF1 DOT MHz MHz MHz 0 0 0 100 100 A do 33 14 318 48 0 0 1 200 66 33 14 318 48 0 1 0 133 200 66 33 14 318 48 0 1 1 16 RITE 66 33 14 318 48 1 0 0 IN 100 200 66 33 14 318 48 1 0 1 amp 100 200 66 33 14 318 48 1 1 V 266 100 200 66 33 14 318 48 1 1 333 100 200 66 33 14 318 48 Table2 Test Clock select table TEST CLK CPU SRC 3V66 PCIF REFO USB Note MHz MHz MHz PCI REF1 DOT MHz MHz MHz 41 REF REF REF4 REF REF REF SeeNofei 0 Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Tables Note 1 REF is aclock over driven on the XIN during test mode Rev 1 00 Apr 25 2003 page 7 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Table3 FS A and FS B pin Input level Logic Level Min Voltage Max Voltage 0 Low 0 35V 1 High 0 70V Bytel Control Register Bit Description Contents Type ult Note 7 Allow control of SCR with assertion 0 Free running RW See of PCI_LSTOP 1 Stopped with Table5 PCI STOP 6 SRC Output enable 0 Disabled tristate 1 1 Enabled O 5 Reserved lt RW 1 4 Reserved RW 1 3 Reserved RW 1 2 CPU2 Output enable 0 Disabled iris ate RW 1 1z ed 1 CPU1 Output enable 0 d tristate RW 1 1 bled 0 CPUO Output enable isabled tristate RW 1 Enabled Byte2 Control Register eV Bit Descrip
4. Bit Descri Type Default Note 7 PCI Stop cohtrol 0 Enabled all stoppable PCI RW 1 and SRC clocks are stopped 1 Disabled 6 PCI 6 Output enable 0 Disabled 1 Enabled RW 1 5 PCI_5 Output enable 0 Disabled 1 Enabled RW 1 4 PCI_4 Output enable 0 Disabled 1 Enabled RW 1 3 PCI 3 Output enable 0 Disabled 1 Enabled RW 1 2 PCI 2 Output enable 0 Disabled 1 Enabled RW 1 1 PCI_1 Output enable 0 Disabled 1 Enabled RW 1 0 PCI 0 Output enable 0 Disabled 1 Enabled RW 1 Rev 1 00 Apr 25 2003 page 9 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Byte4 Control Register Bit Description Contents Type Default Note 7 USB 48 2x output drive 0 2x Drive strength RW 0 1 Normal 6 USB 48MHz Output Enable 0 Disabled RW 1 1 Enabled 5 Allow control of PCIF_2 with 0 Free Running RW 0 assertion of PCI STOP 1 Stopped with PCI STOP 4 Allow control of PCIF 1 with 0 Free Running RW 0 assertion of PCI STOP 1 Stopped with PCI STOP 3 Allow control of PCIF 0 with 0 Free Running RW 0 assertion of PCI STOP 1 Stopped with PCI STOP 2 PCIF 2 Output enable 0 Disabled 1 Enabled RW X 1 PCIF 1 Output enable 0 Disabled 1 Enabled RW o 0 PCIF 0 Output enable 0 Disabled 1 Enabled RW Byte5 Control Register Bit Description Contents Default Note 7 DOT_48MHz Output Enable 0 Disabled 1 En RW 1 6 Reserved e RW
5. 3V66 O RESET4 22 OUTPUT 3V66 Watchdog RESET selectable out C Default is 3V66 output This signal is active low and selecte e latch input 3V66 1 3 23 26 OUTPUT 3V66 clock 3 3V outputs 27 SCLK 28 INPUT Clock input for IC logic O PULL UP SEL66 48 29 INPUT Latched select input for 3V66 VCH output 1 48 MHz 3V66 4 VCH OUTPUT 0 66 66 MHz 3V66 or VCH clock output SDATA 30 IN OUTPUT Data input fo ic PULL UP SELA8 24 31 INPUT Latch t input for 48 24 MHz output USB 48 OUTPUT 0 48 MHz 24 48 MHz clock 3 3 V output FS3 DOT_48 32 INPUT ncy select latch input pin OUTPUT Q 48 clock 3 3 V output VTT PWRGD 35 INPUT ualifying input that latches FS A and FS B PUL When asserted low FS A and FS B are latched SRC 37 TA T Complementary clock of Differential Serial Reference Clock SRC 38 O UT True clock of Differential Serial Reference Clock CPU_ 0 2 OUTPUT Complementary clock of differential CPU clock CPU 0 2 444 OUTPUT True clock of differential CPU clock 7 PCI STOP 49 INPUT PCI clocks stop pin Active Low input PULL UP When asserted low PCI 6 0 and SRC clocks are synchronously disabled in low state Usually this pin does not give to effect PCIF 2 0 clock outputs TEST_CLK 50 INPUT Test clock mode pin Active Low input PULL UP FS_ A B 51 52 INPUT CPU clocks frequency select latch input IREF 52 INPUT A precision resistor is attached to this pin
6. N Iref 2 Iref 2 or Float Float or Float Float Low Low Low Low Rev 1 00 Apr 25 2003 page 24 of 38 RENESAS HD151TS207SS Renesas clock generator C Serial Interface Operation 1 Write mode 1 1 Controller host sends a start bit 1 2 Controller host sends the write address D2 h 1 3 Renesas clock generator will acknowledge Renesas clock gen sends Low 1 4 Controller host sends a begin byte M 1 5 Renesas clock generator will acknowledge Renesas clock gen sends Low 1 6 Controller host sends a byte count N 1 7 Renesas clock generator will acknowledge Renesas clock gen sends Low 1 8 Controller host sends data from byte M to byte M N 1 1 9 Renesas clock generator will acknowledge each byte one at a time 1 10 Controller host sends a stop bit 1 bit 7 bits 1 bit 1 bit 8 bits 1 bi amp its 1bit 8 bits ck Byte Count N Ack Byte M Slave R W i address p Ack Begin Byte 2 h ibit 8bits 1 bit 8 bits ibit 1 bit Ack Byte M 1 0 eV Te Byte M N 1 Ack Stop bit Start bit Rev 1 00 Apr 25 2003 page 25 of 38 RENESAS HD151TS207SS Renesas clock generator VC Serial Interface Operation cont 2 Read mode 2 1 Controller host sends a start bit 2 2 Controller host sends the write address D2 h 2 3 Renesas clock generator will acknowledge Renesas clock gen sends Low 2 4 Controlle
7. 1 Late R W 0 3 PCI 3 Skew Select Bit 0 Normal 1 Late R W 0 2 PCI 2 Skew Select Bit 0 Normal 1 Late R W 1 PCI 1 Skew Select Bit 0 Normal 1 Late RW p 0 PCI 0 Skew Select Bit 0 Normal 1 Late F 0 Bit Description Conients Type Default Note 7 VCH Slew Rate Control Bit 00 Normal 10 R W 1 6 VCH Slew Rate Control Bito 0 7 RW 0 5 PCI Slew Rate Control Bit1 00 M R W 1 4 POlSlewRate Control Bito 0 RE RW 0 3 PCIF Slew Rate Control Bit 00 al 10 R W 1 2 PCIF Slew Rate Control Bito A a RW 0 1 3V66 Slew Rate Control iN Normal 10 RW 1 0 0 3V66 Slew Rate Contro Bi 017 s 11 77 5 Rev 1 00 Apr 25 2003 page 23 of 38 RENESAS HD151TS207SS Clock Stop Timing Diagram PCIl_STOP Assertion De assersion PCI_STOP PCI Low SRC Stoppable 6x Iref Controled by Byte2 6 SRC Stoppable Tristate Controled by Byte2 6 SRC Stoppable Tristate PCI_STOP Assertion De assertion Waveforms S PWRDWNVH Assertion De assersion Q lt lt 1 8 ms gt PWRDWN e nj 2x Iref Controled byfByte2 5 3 CPU Stoppable 6x Iref CPU Stoppable F Float Controled by Byte2 5 3 6x Iref DY o Float V Assertion De assertion Waveforms o e ONE PWRDWNZ U CPU SRC SRC 3V66 PCIF PCI USB DOT REF Normal Normal Normal Normal 66MHz 33MHz 48MHz 14 318MHz CPU Stoppable q
8. they do not convey any license under any intellectual property ri ny Other rights belonging to Renesas Technology Corporation or a third party 2 Renesas Technology Corporation assumes no responsibili lamage or infringement of any third party s rights originating in the use of any product data diagrams charts programs algorithms or circuit application examples coi hese materials 3 All information contained in these materials includin materials and are subject to change by Renesas Ti orporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Renesas Technology Corporation or an aul enesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein The information described here may c Renesas Technology Corporation assu Please also pay attention to inform np http www renesas com 4 When using any or all of the infi ontained in these materials including product data diagrams charts programs and algorithms please be sure to evaluate all information as a total system before ing decision on the applicability of the information and products Renesas Technology Corporation assumes no responsibility for any damage liability or other loss re 1 ormation contained herein 5 Renesas Technology ion semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which
9. 0 70 C Rev 1 00 Apr 25 2003 page 27 of 38 RENESAS HD151TS207SS DC Electrical Characteristics Serial Input Port Ta 0 C to 70 C VDD 3 3 V Item Symbol Min Typ Max Unit Test Conditions Input Low Voltage Vit 0 8 V Input High Voltage Vin 2 0 V Input Current li 50 50 yA VI 20 Vor 3 465 V VDD 3 465 V Input capacitance Ci 10 pF SDATA amp SCLK Note 1 For conditions shown as Min or Max use the appropriate value specified p operating conditions e Ta 0 C to 70 C VDD 3 3 V O AC Electrical Characteristics Serial Input port Item Symbol Min Typ Max Q Test Conditions Notes SCLK Frequency Fscik 100 Hz Normal Mode Start Hold Time bu 40 Dj us SCLK Low Time tLow 4 7 o us SCLK High Time tHiGH 4 0 ww us Data Setup Time tpsu 250 T gt ns Data Hold Time tpup 300 ns Stop Setup Time tstsu 0 us BUS Free Time between tspr uf us Stop amp Start Condition Ww e Rev 1 00 Apr 25 2003 page 28 of 38 RENESAS HD151TS207SS DC Electrical Characteristics CPU CPU Clock Ta 0 C to 70 C VDD 3 3 V Iref 475 Q x1 Item Symbol Min Typ Max Unit Test Conditions Output voltage Vo 1 20 V Rp 49 9 2 VDD 8 3 V Output Current lo nom mA VDD 3 3 V Output resistance 3000 Q Vo 1 2V Notes 1 For conditions shown as Min or Max use the
10. 3 3V Single Ended Clock Output Clock Outx 15V S Clock Outy 15V lt _tskS C Fig 2 Output Clock Skew 3 3V Si nded Clock Output o 4 Rs 3320 pr TS207 Ritet Rp Rp C 2pF C 2 pF 475Q 49 90 Fig 3 Load Circuit for CPU CPU Rev 1 00 Apr 25 2003 page 36 of 38 RENESAS HD151TS207SS Package Dimensions Unit mm C3 0 10 0 004 Rev 1 00 Apr 25 2003 page 37 of 38 RENESAS HD151TS207SS o RenesasTechnology Corp Sales Strategic Planning Div Nippon Bldg 2 6 2 Ohte machi Chiyoda ku Tokyo 100 0004 Japan Keep safety first in your circuit designs 1 Renesas Technology Corporation puts the maximum effort into making semigondu products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or prope e Remember to give due consideration to safety when making your circuii S With appropriate measures such as i placement of substitutive auxiliary circuits ii use of nonflammable material or iii prevention against any malfunction or mi Notes regarding these materials 1 These materials are intended as a reference to assist our cust rs e selection of the Renesas Technology Corporation product best suited to the customer s application
11. FS4 FS3 FS2 FSA FSB CPU SRC 3V66 PCI Be B94 B9 3 B Bory MHZ MHz MHz MHz 0 0 0 0 0 0 100 02 100 02 66 68 33 34 1 0 0 0 0 1 200 08 100 02 66 68 3334 2 0 0 0 1 0 133 06 100 02 66 68 33 34 3 0 0 0 1 1 166 69 100 00 66 68 33 34 4 0 0 1 0 0 200 08 100 02 6 33 34 5 0 0 1 0 1 400 07 100 02 66 33 34 6 0 0 1 1 0 266 71 100 NE 33 34 7 0 0 1 1 1 333 39 eS 66 68 33 34 8 0 1 0 0 0 138 69 109 02 66 68 33 34 9 0 1 0 0 1 1 100 02 66 68 33 34 10 0 1 0 1 0 d 100 02 66 68 33 34 11 0 1 0 1 1 Qus 100 02 66 68 33 34 12 0 1 1 0 0 Qj 52 91 100 02 66 68 33 34 13 0 1 1 0 Cy 15647 100 02 66 68 33 34 14 0 1 1 1 160 00 100 02 66 68 33 34 15 0 1 1 1 CX 163 58 100 02 66 68 33 34 16 1 0 0 O 0 167 14 100 02 6668 33 34 17 1 0 0 Qv 1 170 70 100 02 66 68 33 34 18 1 0 0 e 1 0 17425 100 00 66 68 33 34 19 1 0 1 1 17781 100 00 66 68 33 34 20 1 0 1 0 0 181 36 100 02 66 68 33 34 21 1 OY 1 0 1 184 92 100 02 66 68 33 34 22 1 1 1 0 186 70 100 02 66 68 33 34 23 1 1 1 1 189 36 100 02 66 68 33 34 24 1 1 0 0 0 192 03 100 02 66 68 33 34 25 1 1 0 0 1 194 70 100 02 66 68 33 34 26 1 1 0 1 0 19737 100 02 66 68 33 34 27 1 1 0 1 1 200 03 100 02 66 68 33 34 28 1 1 1 0 0 202 70 100 02 66 68 3334 29 1 1 1 0 1 205 37 100 02 66 68 33 34 30 1 1 1 1 0 208 03 100 02 66 68 33 34 31 1 1 1 1 1 210 70 100 02 66 68 3334 Rev 1 00 Apr 25 2003 page 13 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Byte10 Control Register Bit Description 7 SS
12. 00 0 00S ELL es ais O RW 0 Control Bit2 1001 0 4ns 0110 0 8 RN 1010 0 8ns 0101 2 1 PCIF PCI Clock Skew1 1011 1 2ns 0100 1 6ns R W 0 Control Bit1 1100 1 6ns 0011 2 0ns 0 PCIF PCI Clock Skew1 1101 2 0ns 0010 s 2 4ns RW 0 1111 2 8n Q9 2ns Note 1 Byte27 Control Register PCIF PCI Clock Skew is Skew1 2 N O Qin Bit Description Type Default Note 7 Reserved E R W 0 6 PCIF_2 Skew Select e 0 Normal 1 Late R W 0 See 5 PCIF_1 Ske it 0 Normal 1 Late R W 0 Note 4 PCIF_0Sk ct Bit 0 Normal 1 Late RW 0 1 3V66 ew Control Delay Ahead 3 RAN 1 Bit3 1000 0 0ns 0111 2 0 4ns 3V66 Clock Skew Control 1001 0 4ns 0110 0 8ns 2 Bit 1010 0 8ns 0101 1 2ns RW 0 1011 1 2ns 0100 1 6ns 1 3V66 Clock Skew Control 1100 1 6ns 0011 2 0ns RW o0 Bit 1101 2 0ns 0010 2 4ns 0 3V66 Clock Skew Control 1110 2 4ns 0001 2 8ns RN Bito 1111 2 8ns 0000 3 2ns Note 1 Normal Skew1 B26 3 0 Late Skew1 B26 3 0 Skew2 B26 7 4 Rev 1 00 Apr 25 2003 page 22 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Byte28 Control Register Bit Description Contents Type Default Note 7 Reserved 0 Normal 1 Late R W 0 6 PCI 6 Skew Select Bit 0 Normal 1 Late R W 0 See 5 PCI_5 Skew Select Bit 0 Normal 1 Late RW o0 UR 4 PCI 4 Skew Select Bit 0 Normal
13. 1 5 VCH Select 66MHz 48MHz 0 3V66 mo RW 0 1 VCH 4 mode 4 3V66 4 VCH Output Enable 0 ristate RW 1 12 ee A 3 3V66_3 Output Enable TES led 1 Enabled RW 1 2 3V66_2 Output Enable Disabled 1 Enabled RW 1 1 3V66_1 Output Enable 0 Disabled 1 Enabled RW 1 0 3V66_0 Output Enable 0 Disabled 1 Enabled RW 1 Byte6 Control Register w Bit Descriptio Contents Type Default Note 7 Test de 0 Disabled 1 Enabled RW 0 6 Reserved RW 0 5 FS A amp FS B Operation 0 Normal 1 Test mode RW 0 4 SRC Frequency Select 0 100MHz 1 200 MHz RW 0 3 Reserved RW 0 2 Spread Spectrum Mode 0 Spread OFF RW 0 See 1 Spread ON B9 7 6 1 REF1 Output Enable 0 Disabled 1 Enabled RW 1 0 REFO Output Enable 0 Disabled 1 Enabled RW 1 Rev 1 00 Apr 25 2003 page 10 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Byte7 Vendor Identification Register Bit Description Conients Type Default Note 7 Revision Code Bit3 Vendor Specific R 0 6 Revision Code Bit2 Vendor Specific R 0 5 Revision Code Bit1 Vendor Specific R 0 4 Revision Code BitO Vendor Specific R 1 3 Vendor ID Bit3 Vendor Specific R 1 2 Vendor ID Bit2 Vendor Specific R 1 Vendor ID Bit1 Vendor Specific R C 0 Vendor ID BitO Vendor Specific 1 Byte8 Read Back Byte Count Register O Bit Description Contents Type Default Note 7 Read back b
14. 2 of 38 RENESAS HD151TS207SS DC Electrical Characteristics USB amp VCH 48MHz Clock CK409T Type3A Buffer Ta 0 C to 70 C VDD 3 3 V x1 Item Symbol Min Typ Max Unit Test Conditions Output Voltage Vou 3 1 V lou 2 1 mA VDD 2 3 3 V VoL 50 mV lo 1 mA VDD 3 3 V Output Current lou 29 mA Vou 1 0 V lo 29 mA X Vo 1 95 V Note 1 For conditions shown as Min or Max use the appropriate value specified e commenced operating conditions o AC Electrical Characteristics USB amp VCH 48MHz Cloc Ta 0 C to 70 C VDD 3 3 V C 20 pF Q Item Symbol WMin Typ M nit Test Conditions Notes Cycle to cycle jitter tccs 350 ps Fig 1 Note1 Clock Period zm 20 831 Q ns Slew rate tsi 1 0 V ns 0 4 V to e m Clock Duty Cycle 45 55 96 Note 1 Difference of cycle time betwee adjoining cycles Rev 1 00 Apr 25 2003 page 33 of 38 RENESAS HD151TS207SS DC Electrical Characteristics DOT Clock CK409T Type3B Buffer Ta 0 C to 70 C VDD 3 3 V Item Symbol Min Typ 1 Max Unit Test Conditions Output Voltage Vou 3 1 V lou 2 1 mA VDD 2 3 3 V VoL 50 mV lo 1 mA VDD 3 3 V Output Current loH 29 mA Von 1 0 V loL 29 mA Vor 1 95 V Note 1 For conditions shown as Min or Max use the appropriate value specified under recommended operating conditions X AC Electrical Characteristics D
15. 44 NE SAS HD151TS207SS Mother Board Clock Generator for Intel P4 Chipset Springdale Description The HD151TS207SS is Intel CK409T type high performance low skew low generator It is specifically designed for Intel Pentium 4 chipset Features REJ03D0006 0100Z Preliminary Apr 25 2003 Q Ni motherboard clock O 3 differential pairs of current mode control CPU clocks Q 1 differential pair of Serial Reference Clock SRC sele abl 100 MHz 200 MHz 6 copies PCI clocks and 3 copies PCIF clocks 33V 633 MHz 1 copy PCI clock 3 3 V selectable 33 3 MHz 25 MHz 1 copy USB clock 3 3 V selectable 48 M abut 1 copy DOT clock 3 3 V 48 MHz NS 4 copies of 3V66 clocks 93 3 V 66 6 1 copy of 3V66 VCH clock 3 3 gt 66 6 MHz 48 MHz 2 copies of REF clocks 3 3 V4 1 8 MHz Power save and clock stop ion FC serial port programming Programmable rol Spread Spectrum Percentage Clock Output Skew Slew Rate Watchdog timer set output 56pin SSO ils Note FC is a trademark of Philips Corporation Pentium is registered trademark of Intel Corporation Rev 1 00 Apr 25 2003 page 1 of 38 RENESAS HD151TS207SS Key Specifications Supply Voltages VDD 3 3 V 5 CPU clock cycle to cycle jitter 125psl SSC Disabled CPU clock group Skew 100ps 3V66 clock group Skew 250psmax PCI clock group Skew 500psmax Rev 1 00 Apr 25 2003 page 2 of 38 tENESAS HD151TS207SS Pin Arrangement
16. C Spread Select Bit 2 0 6 5 Contents Type Default Note Bit 2 0 RW 0 000 0 500 100 0 250 RW 0 001 0 75095 101 0 375 010 1 000 110 40 5000 RW 0 011 1 500 111 0 750 4 Backup of latch Input FS_4 at Power ON 3 Backup of latch Input FS_3 at Power ON 2 Backup of latch Input FS_2 at Power ON 1 Backup of latch Input FS_A at Power ON 0 Backup of latch Input FS_B at When SAFE_F is Enable R X B15 5 1 PWRDWN SAFE_F pin to Low and if B23 1 0 frequency selection is changed to these setting and PWRDWN SAFE_F pin to High frequency selection Ke R X changed back to the lt C s UON R X Power ON Bytell Control Register Bit Description ce Co S Default Note 7 PCI STOP5 Enable Control Bit ble 1 Disable RW 0 6 CPU_STOP Enable Control Bi Enable 1 Disable RW 0 5 PWRDWN Enable Control Bi 0 Enable 1 Disable RW 0 4 Backup of B9 5 written When SAFE Ft is Enable R X dy B15 5 1 R X a BackUp Or BA Write PWRDWN SAFE_F pin to 2 Backup of B9 3 by IC Low and if B23 1 1 R X 1 Backup of ritten by IC frequency selection is changed to pR X f 2 these setting and 0 Backup o written by IC R X PWRDWN SAFE_F pin to High frequency selection is changed back to the last mode Rev 1 00 Apr 25 2003 page 14 of 38 RENESAS HD151TS207SS PC Co
17. D 48 34 o REFO 1 OUTPUT 33V 14 318 reference clock REF1 2 G XTAL_IN 4 INPUT 14 z XTAL input XTAL_OUT 5 OUTPUT MHz XTAL output n t connect when an external clock is applied at XTAL_IN FS2 PCIF 0 1 7 8 INPUT Gren select latch input pin OUT Free running PCI clock 3 3 V output PCIF_2 Free running PCI clock 3 3 V output MODE PCI 0 12 T Function select latch input pin for pin 22 UTPUT 1 Reset 0 clock output Q PCI clock 3 3 V output PCI 1 3 KA 14 OUTPUT PCI clock 3 3 V outputs 5 SEL100_200 18 INPUT Latched select input for SRC output PCI 4 OUTPUT 1 200 MHz 0 100 MHz PCI clock 3 3 V output SEL33 25 PCI 5 19 INPUT Latched select input for PCI5 output OUTPUT 1225 MHz 0 33 MHz PCI clock 3 3 V output PCI 6 Note 20 OUTPUT Those pins are 150 kQ internal pulled UP PCI clock 3 3 V outputs Those pins are 150 kQ internal pulled DOWN Rev 1 00 Apr 25 2003 page 4 of 38 RENESAS HD151TS207SS Pin Descriptions cont Pin name No Type Description PWRDWNZ 21 INPUT PWRDWNY SAFE_F selectable input SAFE Ff PULL UP Default is PWRDWNE input Byte15 5 1 SAFE Fs input PWRDWN is all clocks stop pin Asynchronous active Low input When asserted low all output clocks are disabled SAFE Fit is active Low input When SAFE Ft is Low frequency mode is changed to the predefined frequency mode
18. OT Clock N Ta 0 C to 70 C VDD 3 3 V C 10 pF O Item Symbol Min Typ Max 4 Test Conditions Notes Cycle to cycle jitter tccs 350 S Fig 1 Note1 Clock Period 20 881 ns Slew rate ts 2 0 V ns 0 4V to G 2 4V Clock Duty Cycle 45 55 Note 1 Difference of cycle time between two adjoining cycles Rev 1 00 Apr 25 2003 page 34 of 38 RENESAS HD151TS207SS DC Electrical Characteristics REF Clock CK409T Types Buffer Ta 0 C to 70 C VDD 3 3 V Item Symbol Min Typ 1 Max Unit Test Conditions Output Voltage Vou 3 1 V lou 2 1 mA VDD 2 3 3 V VoL 50 mV lo 1 mA VDD 3 3 V Output Current loH 33 mA Von 1 0 V lot 30 mA Vor 1 95 V Note 1 For conditions shown as Min or Max use the appropriate value specified under recommended operating conditions X AC Electrical Characteristics REF Clock N Ta 0 C to 70 C VDD 3 3 V Ci 30 pF O Item Symbol Min Typ Max Qi Test Conditions Notes Cycle to cycle jitter tccs 1000 n S Fig 1 Note1 Clock Period 69 841 S Slew rate tsi 1 0 ce V ns 0 4 V to 2 4 V Clock Duty Cycle 45 aN 55 Note 1 Difference of cycle time between two adjoining cycles Ww e Rev 1 00 Apr 25 2003 page 35 of 38 RENESAS HD151TS207SS Clock Out tcycle n tcycle n 1 tccs tcycle n tcycle n 1 Fig 1 Cycle to Cycle Jitter
19. Skew1 Confrol 1100 0 80ns 0011 1 00ns RW 0 Bitl 1101 1 00ns 0010 1 20ns 4 CPU Clock trol 1110 1 20ns 0001 1 40ns R W 0 Bito 1111 1 40ns 0000 1 60ns 3 CPU Skew2 Control Delay Ahead R W 1 See Bit3 1000 0 00ns 0111 2 0 15ns Note 1001 0 15ns 0110 0 30ns 1 2 eh Clock Skew2 Control 1010 0 30ns 0101 0 45ns R W 0 1011 0 45ns 0100 0 60ns 1 CPU Clock Skew2 Control 1100 0 60ns 0011 0 75ns R W 0 Bitl 1101 0 75ns 0010 0 90ns 0 CPU Clock Skew2 Control 1110 0 90ns 0001 1 05ns RW 0 Bito 1111 1 05ns 0000 1 20ns Note 1 Total CPU Clock Skew is Skew1 Skew2 Rev 1 00 Apr 25 2003 page 21 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Byte26 Control Register Bit Description Contents Type Default Note 7 PCIF PCI Clock Skew2 Skew2 is Late Skew that is Delay R W 0 See Control Bit3 Time from Normal Skew1 Note 6 PCIF PCI Clock Skew2 0000 0 0ns 1000 3 2ns RW o0 1 Control Bit 0001 0 4ns 1001 3 6ns 0010 0 8ns 1010 4 0ns 5 PCIF PCI Clock Skew2 0011 1 2ns 1011 4 4ns R W 0 Control Bit1 0100 1 6ns 1100 4 8ns 4 PCIF PCI Clock Skew2 0101 2 0ns 1101 5 2ns R W X Control Bito 0110 2 4ns 1110 5 6ns 0111 2 8ns 1111 6 0ns 3 PCIF PCI Clock Skew1 Skew1 is Normal Skew 1 See Control Bit3 Delay Ahead Note 2 PCIF PCI Clock Skew1 O
20. appropriate value specified under recommended operating conditional nom is output current loh shown in below 2 loh VDD 3Rr 3 3 3x475 2 32 mA loh x6 13 89 mA Voh Z 0 695 V 50 Q x loh x2 4 63 mA Voh Z 0 232 V 950 Q AC Electrical Characteristics CPU CPU Clock CPU at iming Ta 0 C to 70 C VDD 3 3 V Ci 2 pF Rs 332 Q Rp Sod Item Symbol Min Typ Unit Test Conditions Notes Cycle to cycle jitter tccs 125 ps Note1 CPU Group Skew tsks 1100 ps CPU clock out to CPU clock out 3 Rise time t 175 700 ps Vo 2 0 175 V 200MHz to 0 525 V Fall time t A m 700 ps Vo 0175V 200MHz eV to 0 525 V Clock Duty Cycle E 45 50 55 96 200MHz CPU clock period 10 ww Sen 9 99 m ns CPU clock perio X 7 49 ns CPU clock peri 6 5 99 ns CPU clock period 200 4 99 ns Cross point 0 7V voltage Vcross 0 25 0 55 V 200MHz Note 1 Difference of cycle time between two adjoining cycles Rev 1 00 Apr 25 2003 page 29 of 38 RENESAS HD151TS207SS DC Electrical Characteristics SRC SRC Clock Ta 0 C to 70 C VDD 3 3 V Iref 475 Q Item Symbol Min Typ 1 Max Unit Test Conditions Output voltage Vo 1 20 V Rp 49 9 Q VDD 3 3 V Output Current lo nom mA VDD 3 3 V Output resistance 3000 Q Vo 1 2V Notes 1 For conditions shown as Min or Max use the appropriate value specified under recommended
21. ay as shown at upper Byte19 Byte20 Read back of VCO2 actual frequency Byte21 Byte22 Read back of CPU actual frequency Rev 1 00 Apr 25 2003 page 18 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Byte19 Control Register Bit Description Contents Type Default Note 7 VCO2 Frequency Read Bit15 Calculation result of VCO2 R 0 frequency VCO2F R Bit14 R 0 6 CO2 Frequency Read Bit 100 MHz digit 5 VCO2 Frequency Read Bit13 0000 0 0001 1 1001 9 R 0 4 VCO2 Frequency Read Bit12 R 0 3 VCO2 Frequency Read Bit11 Calculation result of VCO2 R 0 frequency 1 R 2 VCO2 Frequency Read Bit10 10 MHz digit x 1 VCO2 Frequency Read Bit9 0000 0 0001 1 1001 9 R Cp 0 VCO2 Frequency Read Bit8 0 Byte20 Control Register O Bit Description Contents Type Default Note VCO2 Frequency Read Bit7 Calculation resul CO2 frequency VCO2F Read Bit6 CO2 Frequency Read Bi 1 MHz digi VCO2 Frequency Read Bit5 0000 0 060 1 1001 9 VCO2 Frequency Read Bit4 iN VCO2 Frequency Read Bit3 Cate on result of VCO2 VCO2 F Read Bit2 ney CO2 Frequency Read Bit MHz digit VCO2 Frequency Read Bit LS 0000 0 0001 1 1001 9 7 6 5 4 3 2 1 0 D D D D D d D Dd ojojoj o ojojojo VCO2 Frequency Read Bi Byte21 Control Rey Bit Descri Conients Type Default Note CPU Frequency Read Bit15 Calc
22. coming Alarm mode B23 0 1 3 Watchdog Timer Count Biti to cy ng RESET pin to Low R W 0 2 Watchdog Timer Count Bito is 586ms x8 4 7s at Power Rw o0 1 Backup Frequency Select Vo B10 4 0 1 B11 4 0 R W 0 When SAFE_F is Low frequency mode is changed to the predefined frequency mode decided by B10 4 0 or B11 4 0 0 Normal mode 1 Alarm mode R W 0 Rev 1 00 Apr 25 2003 page 20 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Byte24 Control Register Bit Description Contents Type Default Note 7 Reserved R W 0 6 PCI_STOP Stop PCI 6 0 Stoppable 1 Free running R W 0 Control Bit 5 PCI_STOP Stop PCI 5 0 Stoppable 1 Free running R W 0 Control Bit 4 PCI_STOP Stop PCI 4 0 Stoppable 1 Free running R W 0 Control Bit 3 PCI_STOP Stop PCI 3 0 Stoppable 1 Free running c Control Bit 2 PCI STOP Stop PCI 2 0 Stoppable 1 Free running 0 Control Bit 1 PCI_STOP Stop PCI 1 0 Stoppable 1 Free runnin R W 0 Control Bit 0 PCI_STOP Stop PCI 0 0 Stoppable 1 Free 2 R W 0 Control Bit o Byte25 Control Register Bit Description oras C Type Default Note 7 CPU Clock Skew1 Control lay Ahead R W 1 See Bit3 10 0 00ns 0111 0 20ns Note 1 40 20ns 0110 0 40ns 1 6 Ee Clock Skew1 Control 10 40 40ns 0101 0 60ns R W 0 1011 0 60ns 0100 0 80ns 5 CPU Clock
23. de FIequency Commer SI 50005500001 ise aa cft 1 VCO2 Frequency Control Bit9 R W 0 0 VCO2 Frequency Control Bit8 R W 0 Note 1 B17 3 0 and B18 7 0 must be written together at writing B18 in every case Rev 1 00 Apr 25 2003 page 17 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Byte18 Control Register Bit Description Contents Type Default Note 7 VCO2 Frequency Control Bit7 These bits are 10MHz digit of R W 0 See VCO2 frequency Note 6 VCO2F Control Bit6 R W 0 Baci Misia ani 0000 0 0001 1 1001 9 1 5 VCO2 Frequency Control Bit5 R W 0 4 VCO2 Frequency Control Bit4 R W 0 3 VCO2 Frequency Control Bit3 These bits are 1MHz digit of R W 0 VCO2 frequency 2 VCO2 F Bit2 R W e E 0000 0 0001 1 1001 9 1 VCO2 Frequency Control Bit1 Rw p 0 VCO2 Frequency Control BitO RW 0 How to set VCO2 frequency to 666 MHz Q Write Byte17 8 olololilolailailo 0 1 11l01 o0 1 11 0 Z c as m Ze ON gt 6 6 max 720 min 200 D How to read actual frequency ye and CPU clock Byte17 4 1 v Actual VCO2 freq r 4 Byte19 Byte20 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 0 Ne es cS T ae a 6 6 6 8 Note Case of VCO2 666 8 MHz Other clock frequency are able to read using the same w
24. ed RAN 0 6 PLL1 M1 Divider Control Bit6 M1 6 R W 0 5 PLL1 M1 Divider Control Bit5 M1 5 RAN 0 4 PLL1 M1 Divider Control Bit4 M1 4 R W 1 3 PLL1 M1 Divider Control Bit3 M1 3 R W 0 2 PLL1 M1 Divider Control Bit2 M1 2 R W x 1 PLL1 M1 Divider Control Bit1 M1 1 RW gi 0 PLL1 M1 Divider Control Bito M1 0 0 Note See Note 1 Note Bytel5 Control Register 1 B12 1 0 B13 7 0 and B14 6 0 must be written together at writin Bit Description Contents Type Default Note 7 PCI_5 Output Frequency Select 0 33 3 MH MHz R W 0 Bit 6 USB 48 Output Frequency 0 48 24 MHz R W 0 Select Bit 5 SAFE_F Input mode select Bit NEU input mode R W 0 AFE_F input mode fault is PWRDWNYZ5 input eV SAFE Fit is active Low input eV When SAFE F amp t is Low gt frequency mode is changed to the predefined frequency mode Predefined frequency mode is selected by B23 1 4 Clock Divid trol Bit 0 Normal mode R W 0 Clock dividers are changed by Table 5 selection decided B9 5 1 1 Over or Down clocking mode Clock dividers are changed by B15 3 0 and B16 7 0 B15 3 0 and B16 7 0 are able to be changed at B15 4 1 3 CPU Divider Control Bit3 0001 1 1 0111 1 7 R W X at 0010 1 2 1000 1 8 R W X 2 CPU Divider Control Bit2 0011 1 3 1001 1 9 1 CPU Divider Control Bit1 0100 1 4 1010 1 10 R W X 0 CPU Divider Control BitO 0101 1 5 1011 1 11 RW X 0110 1 6 Rev 1 00 A
25. ferred The data is loaded until a stop sequence is issued 7 At power on all registers are set to a default condition as shown Rev 1 00 Apr 25 2003 page 26 of 38 RENESAS HD151TS207SS Absolute Maximum Ratings Item Symbol Ratings Unit Conditions Supply voltage VDD 0 5 to 4 6 V Input voltage Vi 0 5 to 4 6 V Output voltage 1 Vo gp DW Input clamp current lik 50 mA Vi lt 0 Output clamp current lox 50 mA Vo 0 Continuous output current lo 50 mA Vo 0 to VDD Maximum power dissipation at Ta 55 C in still air of idi C Storage temperature Tstg 65 to 4150 Notes Stresses beyond those listed under absolute maximum ratings m use permanent damage to the device These are stress ratings only and functional operati f the device at these or any other conditions beyond those indicated under recomm perating conditions is not implied Exposure to absolute maximum rated conditio X reliability 1 The input and output negative voltage ratings may es ded if the input and output clamp ce Recommended Operating Conditions ev tended periods may affect device current ratings are observed Item Symbol Typ Max Unit Conditions Supply voltage VDD 135 3 3 3 465 V Supply voltage V x 3 135 3 8 3 465 V DC input signal voltage S 0 3 VDD 0O 3 V High level input voltage ev 2 0 VDD 0 3 V Low level input volta NV Vit 0 3 0 8 V Operating temperat Ta
26. human life is potentially atstake Please contac echnology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purp Such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use 6 The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials 7 If these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited 8 Please contact Renesas Technology Corporation for further details on these materials or the products contained therein ain technical inaccuracies or typographical errors 44 NE ESAS http www renesas com Copyright 2003 Renesas Technology Corporation All rights reserved Printed in Japan Colophon 0 0 Rev 1 00 Apr 25 2003 page 38 of 38 RENESAS
27. ntrolled Register Bit Map cont Byte12 Control Register Bit Description Contents Type Default Note 7 Reserved R W 0 6 Reserved R W 0 5 Reserved R W 0 4 Reserved R W 0 3 Reserved R W 0 2 PLL1 Output VCO1 Frequency 0 Normal mode ww See Control Bit PLL1 M1 6 0 and N1 9 0 are SP Note M1 N1 Divider Control Bit changed on Table 5 selection 1 PLL1 for SRC 3V66 PCI PLL decided by FS4 3 2 A B or B9 5 1 1 Over or Down clocking PLL1 M1 6 0 and N1 9 Ul ak changed by B12 1 b and B14 6 0 B12 1 0 obe cri Q 0 are able to be charge e B12 2 ze 1 PLL1 N1 Divider Control Bit9 N1 9 Cs R W 0 0 PLL1 N1 Divider Control Bit8 N1 8 R W 0 Note Byte13 Control Register S 1 B12 1 0 B13 7 0 and B14 6 0 must e Bit Description Contents Type Default Note PLL1 N1 Divider son ts N1 7 R W See 7 0 6 PLL1 N1 Divider Conte Bite N1 6 R W 1 5 PLL1 N1 ey Bit5 N1 5 RAN 0 4 PLL1 ivider Control Bit4 N1 4 RAN 0 3 PLL1 N1 Divider Control Bit3 N1 3 R W 1 2 PLL1 N1 Divider Control Bit2 N1 2 RAN 0 1 PLL1 N1 Divider Control Bit1 N1 1 R W 1 0 PLL1 N1 Divider Control BitO N1 0 R W 1 Note 1 B12 1 0 B13 7 0 and B14 6 0 must be written together at writing B14 in every case Rev 1 00 Apr 25 2003 page 15 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Byte14 Control Register Bit Description Contents Type Default 7 Reserv
28. operating conditions 2 l nom is output current loh shown in below loh VDD 3Rr 3 3 3x475 2 32 mA x loh x6 13 89 mA Voh Z 0 695V 950 Q loh x2 4 63 mA Voh Z 0 232V 850 Q Y AC Electrical Characteristics SRC SRC Clock SRC ary Timing Ta 0 C to 70 C VDD 3 3 V C 2 pF Rs 332 Q Rp 49 Item Symbol Min Typ M Unit Test Conditions Notes Cycle to cycle jitter tccs 125 ps Note1 Rise time t 175 00 ps Vo 0 175 V 100 MHz cA to 0 525 V Fall time ti 175 S 700 ps Vo 20 175 V 100 MHz Q to 0 525 V Clock Duty Cycle QN 50 55 96 100 MHz SRC clock period 100 c 9 99 ns SRC clock period 200 o 4 99 ns Cross point 0 7V voltage Vcros 0 25 0 55 V 100 MHz Note 1 Differenc ime between two adjoining cycles Rev 1 00 Apr 25 2003 page 30 of 38 RENESAS HD151TS207SS DC Electrical Characteristics 3V66 Buffer CK409T Type5 Buffer Ta 0 C to 70 C VDD 2 3 3 V Item Symbol Min Typ 1 Max Unit Test Conditions Output Voltage Vou 3 1 V lou 2 1 mA VDD 2 3 3 V VoL 50 mV lo 1 mA VDD 3 3 V Output Current loH 33 mA Von 1 0 V lot 30 mA Vor 1 95 V Note 1 For conditions shown as Min or Max use the appropriate value specified under recommended operating conditions X AC Electrical Characteristics 3V66 Buffer NS Ta 0 C to 70 C VDD 3 3 V Ci 30 pF Qi Test Conditions Notes
29. pr 25 2003 page 16 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Bytel6 Control Register Bit Description Contents Type Default Note 7 3V66 PCI PCIF Divider Control 3V66 divider ratio R W X Bit3 0010 1 2 0111 1 7 nez 0011 1 3 1000 1 8 V PCI PCIF Divider Control i R W X 6 un CI PC ivider Contro 0100 1 4 1001 1 9 0101 1 5 1010 1 10 0110 1 6 1011 1 11 5 3V66 PCI PCIF Divider Control PCI PCIF divider ratio 3v66 x R W Bit 1 2 C 4 3V66 PCI PCIF Divider Control R BitO 3 SRC Divider Control Bit3 0001 1 1 0111 1 7 X 0010 1 2 1000 1 O R W X 2 SRC Divider Control Bit2 0011 1 3 1001 re 1 SRC Divider Control Bit1 0100 1 4 10 R W X 0101 1 5 101 X 0 SRC Divider Control Bito 1 11 R W 0110 1 6 Byte17 Control Register Bit Description C Type Default Note 7 Reserved Q R W 0 6 Reserved c RW 0 5 Reserved A R W 0 4 PLL2 Output VCO2 ey cy 0 Normal mode RW OO See Control Bit VCO2 frequency is changed on Note M2 N2 Divid ontrol Bit Table 5 selection decided by 1 PLL2 for FS4 3 2 A B or B9 5 1 1 Over or Down clocking mode VCO2 frequency is changed by B17 3 0 and B18 7 0 with decimal B17 3 0 and B18 7 0 are able to be changed at B17 4 1 3 VCO2 Frequency Control Bit1 1 These bits are 100MHz digit of R W 0 VCO2 frequency 2 VCO2 F Bitl R W 1 E
30. r host sends a begin byte M 2 5 Renesas clock generator will acknowledge Renesas clock gen sends Low 2 6 Controller host sends a restart bit 2 7 Controller host sends the read address D3 h 2 8 Renesas clock generator will acknowledge Renesas clock gen sends Low X 2 9 Renesas clock generator will send the byte count N 2 10 Controller host will acknowledge M 2 11 Renesas clock generator will send data from byte M to byte M N 1 2 12 When Renesas clock generator sends the last byte controller ill not acknowledge 2 13 Controller host sends a stop bit Q 1 bit 7 bits 1bit 1 bit 8 bits A ibit 1 bit 7 bits 1 bit Start bit Slave R W Ack Begin Byte Ack Restart bit Slave address po h address mh T 1 bit 8 bits 1bit 8bits 1 8 bits 1 bit 8 bits 1 bit 1 bit Begin Count N e KA Byte M 1 Ack Byte M N 1 Not Ack Stop bit Notes 1 Renesas rator is a slave receiver IC component It can read back the data stored in the Or verification 2 a transfer rate supported by this clock generator is 100k bits sec or less standard b The input is operating at 3 3 V logic levels The data byte format is 8 bit bytes 5 To simplify the clock generator IC interface the protocol is set to use only block write from the controller 6 The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been trans
31. tion QY Contents Type Default Note 7 SRC_Pwrd de 0 Driven in power down RW 0 See 1 Tristate Table5 6 SRC rive mode 0 Driven when stopped RW 0 1 Tristate 5 CPU2_Pwrdwn drive mode 0 Driven in power down RW 0 See 1 Tristate Table4 4 CPU1_Pwrdwn drive mode 0 Driven in power down RW 0 1 Tristate 3 CPUO Pwrdwn drive mode 0 Driven in power down RW 0 1 Tristate 2 Reserved RW 0 1 Reserved RW 0 0 Reserved RW 0 Rev 1 00 Apr 25 2003 page 8 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Table4 CPU Clock Power Management Truth Table Signal Pin PWRDWN Non Stop Note PWRDWN Tristate Bit Outputs Byte2 5 3 Byte1 5 3 1 CPU 2 0 1 X Running CPU 2 0 0 0 Driven Iref x2 See Note1 CPU 2 0 0 1 Tristate Note 1 lref VDD 3Rr 3 3 3x475 2 32 mA Iref x2 4 6 mA Voh Z 0 23 V 950 Q X Table5 SRC Clock Power Management Truth Table SS t Signal Pin Pin PCI STOP amp PWRDWN Non sP oppable Note PWRDWN PCI_STOP Tristate Bit Tristate Bit Out Outputs Byte2 6 Byte2 7 er 21 Byte1 7 2 O SRC 1 1 X X R nning Running SRC 1 0 0 X Quin Driven See Note1 Iref x6 SRC 1 0 1 X Cs Running Tristate SRC 0 X X Driven Driven See Note1 lref x2 Iref x2 SRC 0 X X 1 Tristate Tristate Note 1 lref VDD 3Rr 3 3 3x4 2 mA Iref x6 13 9 mA Voh 550 Q Iref x2 4 6 mA Voh 0 23 V 950 Q Byte3 Control Registe w O Contents
32. ulation result of CPU frequency 7 R 0 i R 6 CPU Frequency Read Bit14 100 MHz digit 0 5 CPU Frequency Read Bit13 0000 0 0001 1 1001 9 R 0 4 CPU Frequency Read Bit12 R 0 3 CPU Frequency Read Bit11 Calculation result of CPU R 0 frequency R 2 CPU Frequency Read Bit10 10 MHz digit 0 1 CPU Frequency Read Bit9 0000 0 0001 1 1001 9 R 0 0 CPU Frequency Read Bit8 R 0 Rev 1 00 Apr 25 2003 page 19 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Byte22 Control Register Bit Description Contents Type Default Note 7 CPU Frequency Read Bit7 Calculation result of CPU frequency R 0 1 MHz digit PUF Read B R 0 6 CPUFrequency Read Bit6 0000 0 0001 1 1001 9 5 CPU Frequency Read Bit5 R 0 4 CPU Frequency Read Bit4 R 0 3 CPU Frequency Read Bit3 Calculation result of CPU frequency R 0 0 1 MHz digit 2 R 2 OPU Frequency Read Bit 50000 0001 1 1001 9 X 1 CPU Frequency Read Bit1 R Cp 0 CPU Frequency Read BitO 0 Byte23 Control Register Bit Description Conients Type Default Note 7 Watchdog Enable Control Bit 0 Disable Pin22 O output R W 0 1 Enable Pin2 ET output 6 RESET Reverse Control Bit 0 Normal 1 rse RAN 0 5 Watchdog Timer Count Bit3 These 4 bi Sponds to how RAN 1 4 Watch Ti Bip X anyw og timer will wait from R W 0 eoo Tue coun be
33. which is connected to internal current reference A resistor is connected between this pin and GNDIREF Note Those pins are 150 kQ internal pulled UP Those pins are 150 kQ internal pulled DOWN Rev 1 00 Apr 25 2003 page 5 of 38 3 NESAS HD151TS207SS Block Diagram 3 8VVDD 48 VSS_48 3 3VVDD_A VSS A 6x3 3VVDD 6xVSS VSS_IREF IREF REF 1 0 XTAL 14 318 MHz 14 318MHz CPU 2 0 CPU 2 0 PWRDWN SAFE_F PCI_STOP Q VTT_PWRGD C PCIF 2 0 C 3V66_0 RESET C 3V66 3 1 TEST_CLK C MODE Q SEL100 200 C 3V66 4 VCH SELe6 48 SEL48 240 USB 48 SEL33 25 Q FS 4 3 2A B CE SCLK SDATA D C DOT 48 NP Input pin Rev 1 00 Apr 25 2003 page 6 of 38 3 NESAS HD151TS207SS FC Controlled Register Bit Map ByteO Control Register Bit Description Contents Type Default Note 7 Reserved R 0 6 Reserved R 0 5 Reserved R 0 4 Reserved R 0 3 PCI Stop Reflects the current value 0 PCI STOP5 pin is Low R X of the external PCI STOP pin 1 PCI STOP pin is High 2 Reserved R 1 FS B Reflects the value of the 0 FS B Low at power up RO X See FS_B pin sampled on power up 1 FS_B High at power up A Table 0 FS_A Reflects the value of the 0 FS_A Low at power up X 1 FS_A pin sampled on power up 1 FS_A High at power O
34. yte count Bit7 Writing to this register will configure RW 0 6 Read back byte count Bit6 Saari ho ytes will RW 0 5 Read back byte count Bits Default is 1EheX 30 bytes RW 0 4 Read back byte count Bit4 RW 1 3 Read back byte count Bit3 gt RW 1 2 Read back byte count Bit2 RW 1 1 Read back byte count Bit1 e RW 1 0 Read back byte count Bit RW 0 Ww e Rev 1 00 Apr 25 2003 page 11 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Byte9 Control Register Bit Description Contents Type Default Note 7 SSC2 Enable Bit B6 2 0 or B9 7 1 SSC2 OFF RW 0 B6 2 1 amp B9 7 20 SSC2 ON 6 SSC1 Enable Bit B6 2 0 or B9 6 1 SSC1 OFF RW 0 B6 2 1 amp B9 6 0 SSC1 ON 5 Clock Frequency Control Latched input PCIF 1 at Power ON RW X See Bit4 Table 4 Clock Frequency Control Latched input DOT48 at Power ON RW X 6 Bit3 3 Clock Frequency Control Latched input PCIF 0 at Power ON TS Bit2 2 Clock Frequency Control Latched input FS_A at Power ON Cy X Bit1 1 Clock Frequency Control Latched input FS_B at Pow RW X Bito 0 Frequency Select Mode Bit 0 Freq is selected by latched input RW 0 FS Aand FS B 1 Freq is selecte B9 5 1 Rev 1 00 Apr 25 2003 page 12 of 38 RENESAS HD151TS207SS PC Controlled Register Bit Map cont Table6 Clock Frequency Function Table No
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