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National Instruments NI 6115/6120 User's Manual

1. Anti CHO 42 CHO Aliasing 12 Bit 54 gt Latch Data 16 Filter ADC 4 Anti CH1 43 ch AliasingK B gt 12 Bit 54 aton Data 16 Filter ADC Anti CH2 Aliasing 12 Bit 24 gt ia Data 16 r Filter ADC ae i ADC Bus Mini BG FIFO Data 32 gt interface MITE interface m Anti CH3 Mora Y aiasingl 12 bit 1222 Lie Data 16 m x CH3 Filter ADC Or P ao 5 ft 3 8 ral m Calibration Al Control m gt Mux y EEPROM 5 Anal IRQ O Trigger i 2 nad a Oo la iggi gt agon Levat Ly Trigger DMA O Circuitry y x f f z Analog Input 2 PFI Trigger X Trigger Timing Control PMAIRQ me E E DMA ES ee ee Input 1 Control Interface Control 1 Counter Bus RR eee Timing X Timing vo DAQ STC interface PAR FPGA pS nee Interface Er per 1 Analog Output RTSI Bus Analog DO 7770 71 STC Digital I O 8 X Digital O Timing Control Interface Output Control ne Digital VO 8 FPGA Digital 0 8 AO Control N Lg DACO Data 12 DAC Data 32 FIFO lt mses gt Calibration VvV NF Figure 3 1 NI 6115 Block Diagram National Instruments Corporation 3 1 NI 6115 6120 User Manual Chapter 3 Hardware Overview
2. PCI Bus Bus Interface MITE interface 1 KG gt Kisaa DMA Interface B Interface Analog Input DACs CHO gt pt Anti AI CHO nti CHO Ma te es p gt Aliasing 16 Bit 84 CHO pata 16 CHo ux Amplifier Filter ADC Latch P H gt CH1 D Aichi m gt Anti CH1 46 ch K Mx H Aliasing 16 Bit 4 Laton Data 16 CHi p Filter ADC CH2 a gt Anti CH2 AL CHE Pa Aliasing 16 Bit Sp CH2 Daa 16 Mux 5 Latch A CH2 Filter ADC gt Ha aoc H jeneric SHS pe m gt Anti CH3 __ ia me AI CH3 Amis 16 CH3 Data 16 m max H p gt Aliasing 16 Bit AP ich CH3 Filter TF s 7 5 it Calibration en Mux S EEPROM P P Analog T 2 O ke rigger p gt Trigger Level Trigger DACs 7 gt us Circuitry i i Q Tri x Analog Input i DMA IRQ gt PFI Trigger ngger Timing Control 1 Analog 1 EEPROM Ses a eet contol 1 Conti Counter Us an TE Timing 10 DAQ STC inertace ar PNR eee PP eT et Interface STC Digital I O 8 iy 1 Analog Output RTSI Bus Analog DIO bi Digital VO 1 Timing Control Interface Gowa Control Digital VO 8 Mux FPGA Digital 1 O 8 fi fi
3. Scatter gather DC Transfer Characteristics INL NUOVS vcs buts un due 0 35 LSB typ 1 LSB max NV6120 cine en 2 5 LSB max DNL NLOTIS Lune dee es aves 0 25 LSB typ 1 LSB max NYO 20 vice sieht eee 0 75 LSB typ no missing codes Offset gain error NDOT Sinnenas Refer to Table A 1 NTGI20 sh te Lt Refer to Table A 2 NI 6115 6120 User Manual A 2 ni com Appendix Table A 1 NI 6115 Analog Input DC Accuracy Information Specifications Absolute Accuracy Relative Accuracy Nominal Range Noise Vv of Reading Quantization mV Absolute Resolution mV Temp Accuracy at Full Offset Single Drift Full Scale Single Scale 24 Hours 1 Year mV Pt Averaged C mV Pt Averaged 50 0 346 0 348 33 42 3 6 0 0229 211 0 48 4 8 20 0 271 0 273 13 17 1 4 0 0229 69 4 19 1 9 10 0 026 0 028 6 7 8 3 0 72 0 0004 10 22 10 1 0 5 0 016 0 018 3 4 4 2 0 36 0 0004 4 61 4 8 0 48 2 0 036 0 038 1 3 1 8 0 16 0 0004 2 26 2 1 0 21 1 0 043 0 045 0 68 1 1 0 09 0 0004 1 23 1 2 0 12 0 5 0 058 0 060 0 35 0 69 0 061 0 0004 0 71 0 80 0 080 0 2 0 103 0 105 0 15 0 43 0 039 0 0004 0 39 0 51 0 051 Table A 2 NI 6120 Analog Input DC Accuracy Information Absolute Accuracy Relative Accuracy Nominal Range Noise Quantization Absolute V of Reading uV Accuracy Res
4. o P A ol OM N Lo ACHO ACHOGND ACH1 ACH2 ACH2GND ACH3 NC NC NC NC NC NC NC AOGND AOGND DGND DIOO DIO5 DGND DIO2 DIO7 DIO3 SCANCLK EXTSTROBE DGND PFI2 CONVERT PFI3 GPCTR1_SOURCE PFI4 GPCTR1_GATE GPCTR1_OUT DGND PFI7 STARTSCAN PFI8 GPCTRO_SOURCE DGND DGND NC No Connect Figure 4 1 1 0 Connector Pin Assignment for the NI 6115 6120 4 2 1 0 Connector Signal Descriptions Chapter 4 Connecting Signals Table 4 2 Signal Descriptions for 1 0 Connector Pins Signal Name Reference Direction Description ACH lt 0 3 gt GND Ground for Analog Input Channels 0 through 3 These pins are the bias current return point for pseudodifferential measurements ACH lt 0 3 gt ACH lt 0 3 gt GND Input Analog Input Channels 0 through 3 These pins are routed to the terminal of the respective channel amplifier and carry the input signal ACH lt 0 3 gt ACH lt 0 3 gt GND Input Analog Input Channels 0 through 3 These pins are routed to the terminal of the respective channel amplifier and are the DC reference for the input signal of that channel DACOOUT AOGND Output Analog Channel 0 Output This pin supplies the voltage output of AO channel 0 DACIOUT AOGND Output Analog Channel 1 Output This pin supplies the volta
5. 4 23 RTSI bus signal connections figure 3 13 timing connections 4 22 typical pretriggered acquisition figure 4 21 triggers analog trigger description 3 5 specifications A 16 digital trigger specifications A 17 questions about B 5 troubleshooting resources C 1 U UISOURCE signal 4 31 RTSI bus signal connections figure 3 13 unpacking NI 6115 6120 1 7 UPDATE signal See also PFIS UPDATE signal input timing figure 4 31 output timing figure 4 31 NI 6115 6120 User Manual I 10 RTSI bus signal connections figure 3 13 timing connections 4 30 using with UISOURCE signal 4 31 using with WFTRIG signal 4 29 V VCC signal table 4 6 voltage output specifications A 13 working voltage range 4 13 voltage controlled crystal oscillator VCXO 3 9 W waveform generation timing connections UISOURCE signal 4 31 UPDATE signal 4 30 WETRIG signal 4 29 waveform generation questions about B 4 Web professional services C 1 technical support C 1 WETRIG signal See also PFI6 WFTRIG signal input timing figure 4 30 output timing figure 4 30 RTSI bus signal connections figure 3 13 timing connections 4 29 wiring considerations 4 39 working voltage range 4 13 worldwide technical support C 2 ni com
6. Pseudodifferential signal connections increase common mode noise rejection They also allow input signals to float within the common mode limits of the PGIA 4 8 ni com Chapter 4 Connecting Signals Connections for Ground Referenced Signal Sources Figures 4 2 and 4 3 show how to connect a ground referenced signal source to a channel on the NI 6115 and NI 6120 respectively Common Mode AC Coupling ACHO Choke a Ground Z j Hoi r Referenced Liu Lt Instrumentation Amplifier Signal 100 pf Source Measured ACHO Voltage Common 10 nf Mode F Noise and en Ground Potential S77 x 6 10 kQ 40 pf for ranges gt 10 V ACHOGND 1 0 Connector ACHO Connections Shown Figure 4 2 Pseudodifferential Input Connections on the NI 6115 for Ground Referenced Signals National Instruments Corporation 4 9 NI 6115 6120 User Manual Chapter 4 Connecting Signals Ground Referenced Signal Source Common Mode Noise and Von Ground Potential 1 High Frequency CR H AC Coupling 100 pF Common Mode Choke ACHOGND 509 0 1 uF 7 N7 Instrumentation Amplifier Measured Voltage 10 kQ 40 pf for ranges gt 10 V NI 6115 6120 User Manual Figure 4 3 Pseudodifferential Input Connections on
7. Specifications This appendix lists the specifications of the NT 6115 6120 These specifications are typical at 25 C unless otherwise noted Analog Input Input Characteristics Number of channels ccceeseeseeeteees 4 pseudodifferential Type of ADC Resolution NI GUS asus 12 bits 1 in 4 096 NT G120 cece ste sites 16 bits 1 in 65 536 Pipeline NT GUS rentes 4 NT 6120 0 Sampling rate Maximum NE6115 haine rt 10 million S s NI 6120 800 kS s Minimum NEG ELS 3 5eme fa 20 kS s NT 6120 No minimum Input impedance ACH to ACH Range lt 10 Vow 1 MQ in parallel with 100 pF Range gt 10 Vow eee 10 kQ in parallel with 40 pF ACH to ACHGND NEGUS Sie prunes 10nF NIG 120 ceaee cake ateeetl 100 GQ National Instruments Corporation A 1 NI 6115 6120 User Manual Appendix Specifications ACH to ACHGND NL GLS scat tocieatvces sees cee 100 GQ NTG120 ssl sien 100 GQ Input bias current 300 pA Input offset current eee 200 pA Input coupling DC AC Max working voltage for all analog input channels Positive input ACH 11 V for ranges lt 10 V 42 V for ranges gt 10 V Negative input ACH 2 5 V Overvoltage protection ee 42 V Input current during overvoltage conditions 20 mA max Input FIFO size 16 or 32 MS Data transfer siccccsccccccdecsis nent ei DMA interrupts programmed I O DMA modes
8. lt gt gt STARTSCAN PFI lt 0 9 gt lt Scan Interval Counter TC gt GPCTRO_OUT LT Figure 3 11 STARTSCAN Signal Routing This figure shows that STARTSCAN can be generated from a number of sources including the external signals RTSI lt 0 6 gt and PFI lt 0 9 gt and the internal signals Scan Interval Counter TC and GPCTRO_OUT Many of these timing signals are also available as outputs on the RTSI pins as indicated in the RTS Triggers section later in this chapter and on the PFI pins as indicated in Chapter 4 Connecting Signals National Instruments Corporation 3 11 NI 6115 6120 User Manual Chapter 3 Hardware Overview Programmable Function Inputs The 10 PFIs are connected to the signal routing multiplexer for each timing signal and software can select one of the PFIs as the external source for a given timing signal It is important to note that any PFI can be used as an input by any timing signal and that multiple timing signals can simultaneously use the same PFI This flexible routing scheme reduces the need to change physical connections to the I O connector for different applications You also can individually enable each PFI pin to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector software can enable the output driver for the PFIS UPDATE pin Device and RTSI Clocks Many functions performed by the
9. resistance inch or inches integral nonlinearity a measurement in least significant bits of the worst case deviation from the ideal A D or D A transfer characteristic of the analog I O circuitry current output high current output low interrupt request kilohertz G 6 ni com L LabVIEW LED LSB master MAX MB Measurement Studio MHz MIO MITE MSB mux mV MXI National Instruments Corporation Glossary Laboratory Virtual Instrument Engineering Workbench a program development application based on the programming language G and used commonly for test and measurement purposes light emitting diode least significant bit a functional part of a MXT VME VXIbus device that initiates data transfers on the backplane a transfer can be either a read or a write Measurement and Automation Explorer megabytes of memory a set of test and measurement oriented software tools from National Instruments for C C and Visual Basic users megahertz multifunction I O MXI Interface to Everything most significant bit multiplexer a switching device with multiple inputs that sequentially connects each of its inputs to its output typically at high speeds in order to measure several signals with a single analog input channel millivolts a high performance communication link that interconnects devices using round flexible cables G 7 NI 6115 6120 User Manual Glossary NC NI NI DAQ
10. DAQ National Instruments Corporation Glossary Celsius calibration DAC centimeter complementary metal oxide semiconductor common mode rejection ratio a measure of an instrument to reject interference from a common mode signal usually expressed in decibels dB a Eurocard configuration of the PCI bus for industrial applications convert signal can clock digital I O on the same clock as analog I O a circuit that counts external pulses or clock pulses timing counter digital to analog digital to analog converter an electronic device that converts a digital number into a corresponding analog voltage or current analog channel 0 output signal analog channel output signal data acquisition 1 collecting and measuring electrical signals from sensors transducers and test probes or fixtures and inputting them to a computer for processing 2 collecting and measuring the same kinds of electrical signals with A D and or DIO devices plugged into a computer and possibly generating control signals with D A and or DIO devices in the same computer G 3 NI 6115 6120 User Manual Glossary DAQ STC dB DC DGND DI DIFF DIO DIP dithering DMA DNL DO E EEPROM ENOB NI 6115 6120 User Manual data acquisition system timing controller an application specific integrated circuit ASIC for the system timing requirements of a general A D and D A system such as a system containing the Natio
11. PFI6 WFTRIG PFI7 STARTSCAN PFI8 GPCTRO_SOURCE PFI9 GPCTRO_GATE PGIA PLL ppm pseudodifferential channels pu PWB PXI R range referenced signal sources National Instruments Corporation Glossary PFI2 convert PFI3 general purpose counter source PFI4 general purpose counter gate PFI5 update PFI6 waveform trigger PFI7 start of scan PFI8 general purpose counter 0 source PFI9 general purpose counter 0 gate programmable gain instrumentation amplifier phase locked loop parts per million pseudodifferential channels are all referred to a common ground but this ground is not directly connected to the computer ground Often this connection is made by a relatively low value resistor to give some isolation between the two grounds pull up printed wire board PCI eXtensions for Instrumentation an open specification that builds off the CompactPCI specification by adding instrumentation specific features the maximum and minimum parameters between which a sensor instrument or device operates with a specified set of characteristics signal sources with voltage signals that are referenced to a system ground such as the earth or a building ground also called grounded signal sources G 9 NI 6115 6120 User Manual Glossary rise time rms RTD RTSI bus RTSI_OSC S s S S s SCANCLK scatter gather signal conditioning SFDR SISOURCE SOURCE STARTSCAN STC system noise NI
12. Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 14 TRIG1 Input Signal Timing ty 25 50 ns Figure 4 15 TRIG1 Output Signal Timing The device also uses TRIG1 to initiate pretriggered DAQ operations In most pretriggered applications TRIG1 is generated by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIG1 and TRIG2 in a pretriggered DAQ operation TRIG2 Signal Any PFI pin can receive as an input the TRIG2 signal which is available as an output on the PFI1 TRIG2 pin Refer to Figure 4 13 for the relationship of TRIG2 to the DAQ sequence As an input TRIG2 is configured in the edge detection mode You can select any PFI pin as the source for TRIG2 and configure the polarity 4 22 ni com Chapter 4 Connecting Signals selection for either rising or falling edge The selected edge of TRIG2 initiates the posttriggered phase of a pretriggered DAQ sequence In pretriggered mode the TRIG1 signal initiates the acquisition The scan counter indicates the minimum number of scans before TRIG2 can be recognized After the scan counter decrements to zero it is loaded with the number of posttrigger scans to acquire while the acquisition continues The device ignores TRIG2 if it is asserted prior to the scan counter decrementing to zero After the selected edge of TRIG2 is received the device acquires a fixed number of sca
13. into the analog signals from transient digital signals Mating connectors and a backshell kit for making custom 68 pin cables are available from NI The parts in the following list are recommended for connectors that mate to the I O connector on the device e Honda 68 position solder cup female connector e Honda backshell Unpacking The NI 6115 6120 is shipped in an antistatic package to prevent electrostatic damage to the device Electrostatic discharge ESD can damage several components on the device A Caution Never touch the exposed pins of connectors To avoid such damage when handling the device take the following precautions e Ground yourself using a grounding strap or by holding a grounded object e Touch the antistatic package to a metal part of the computer chassis before removing the device from the package Remove the device from the package and inspect the device for loose components or any sign of damage Notify NI if the device appears damaged in any way Do not install a damaged device into the computer Store the NI 6115 6120 in the antistatic envelope when not in use National Instruments Corporation 1 7 NI 6115 6120 User Manual Chapter 1 Introduction Safety Information NI 6115 6120 User Manual The following section contains important safety information that you must follow when installing and using the product Do not operate the product in a manner not specified in this document
14. ni com Connecting Signals Table 4 1 1 0 Connector Details This chapter describes how to connect input and output signals to the NI 6115 6120 using the device I O connector Device with O Number Cable for Connecting Cable for Connecting Connector of Pins to 100 pin Accessories to 68 pin Accessories NI 6115 68 N A SH6868 Shielded Cable NI 6120 SH68 68 EP R6868 SH68 68R1 EP 1 0 Connector Figure 4 1 shows the pin assignments for the 68 pin I O connector on the NI 6115 6120 A signal description follows the connector pinouts A Caution Connections that exceed any of the maximum ratings of input or output signals on the NI 6115 6120 can damage the device and the computer NI is not liable for any damage resulting from such signal connections The Protection column of Tables 4 3 4 4 and 4 5 show the maximum input ratings for each signal National Instruments Corporation 4 1 NI 6115 6120 User Manual Chapter 4 NI 6115 6120 User Manual Connecting Signals ACHO ACH1 ACH1GND ACH2 ACH3 ACH3GND NC NC NC NC NC NC DACOOUT DAC1OUT NC DIO4 DGND DIO1 DIO6 DGND 5V OUTPUT DGND DGND PFIO TRIG1 PFI1 TRIG2 DGND 5V OUTPUT DGND PFI5 UPDATE PFI6 WFTRIG DGND PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
15. 0 Signal Summary for the NI 6115 Signal Impedance Protection Rise Type and Input Volts Source Sink Time Signal Name Direction Output On Off mA at V mA at V ns Bias ACH lt 0 3 gt AI 1 MQ in 42 V 300 pA parallel with 100 pF or 10 KQ in parallel with 40 pF ACH lt 0 3 gt AI 10nF to 42 V 300 pA ACH lt 0 3 gt GND DACOOUT AO 50Q Short circuit 5 at 10 5 at 10 to ground DACIOUT AO 50 Q Short circuit 5 at 10 5 at 10 to ground 1 Applies to range lt 10 V impedance refers to ACH lt 0 3 gt 2 Applies to range gt 10 V impedance refers to ACH lt 0 3 gt National Instruments Corporation 4 5 NI 6115 6120 User Manual Chapter 4 Connecting Signals Table 4 4 Analog 1 0 Summary for the NI 6120 Signal Impedance Protection Rise Type and Input Volts Source Sink Time Signal Name Direction Output On Off mA at V mA at V ns Bias ACH lt 0 3 gt Al 100 GQ 42 V to 300 pA to GND GND ACH lt 0 3 gt Al 100 GQ 42 V to 200 pA to GND GND Differential Pair AI 1 MQ in parallel 300 pA ACH lt 0 3 gt to with 100 pF or ACH lt 0 3 gt 10k in parallel with 40 pF DACOOUT AO 50 Q Short circuit 5 at 10 5 at 10 to ground DACIOUT AO 50Q Short circuit 5 at 10 5 at 10 to gro
16. 6 timing connections 4 28 self calibration 5 2 self resetting fuse 4 18 B 2 NI 6115 6120 User Manual signal connections analog input connections common mode signal rejection 4 12 floating signal sources 4 11 ground referenced signal sources 4 9 nonreferenced signal sources 4 11 analog output connections 4 14 data acquisition timing connections AIGATE signal 4 27 CONVERT signal 4 26 EXTSTROBE signal 4 29 SCANCLK signal 4 28 SISOURCE signal 4 27 STARTSCAN signal 4 24 TRIG1 signal 4 21 TRIG2 signal 4 22 typical posttriggered acquisition figure 4 21 typical pretriggered acquisition figure 4 21 digital I O connections 4 15 correlating 4 16 exceeding maximum input voltage ratings caution 4 18 field wiring considerations 4 39 general purpose timing signal connections FREQ _ OUT signal 4 38 GPCTRO_GATE signal 4 33 GPCTRO_OUT signal 4 34 GPCTRO_SOURCE signal 4 32 GPCTRO_UP_DOWN signal 4 35 GPCTR1_GATE signal 4 36 GPCTR1_OUT signal 4 36 GPCTR1_SOURCE signal 4 35 GPCTR1_UP_DOWN signal 4 37 T O connectors exceeding maximum ratings caution 4 1 NI 6115 6120 User Manual 1 8 overview 4 1 signal descriptions table 4 3 power connections 4 18 programmable function input connections 4 20 timing connections data acquisition timing connections 4 20 general purpose timing signal connections 4 32 waveform generation timing connections 4 29 types of signal sources floating 4 7
17. 6115 6120 If I m using one of the general purpose counter timers on the NI 6115 6120 but I do not see the counter timer output on the I O connector what am I doing wrong If you are using NI DAQ or LabWindows CVI you must configure the output line to output the signal to the I O connector Use the Select_Signal call in NI DAQ to configure the output line By default all timing I O lines except EXTSTROBE are high impedance What are the PFIs and how do I configure these lines PFIs are Programmable Function Inputs These lines serve as connections to virtually all internal timing signals If you are using NI DAQ or LabWindows CVI use the Select_Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI DAQ with LabVIEW and you want to connect external signal sources to the PFI lines you can use AI Clock Config AI Trigger Config AO Clock Config AO Trigger and Gate Config and Counter Set Attribute advanced level VIs to indicate which function the connected signal serves Use the Route Signal VI to enable the PFI lines to output internal signals Table B 1 Signal Name Equivalencies Hardware LabVIEW Signal Name Route Signal NI DAQ Select_Signal TRIG1 AI Start Trigger ND_IN_START_TRIGGER TRIG2 AI Stop Trigger ND_IN_STOP_TRIGGER STARTSCAN AI Scan Start ND_IN_SCAN_START SISOURCE ND
18. A HUMAN 2 IN ANY APPLICATION INCLUDING THE ABOVE RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY COMPUTER HARDWARE MALFUNCTIONS COMPUTER OPERATING SYSTEM SOFTWARE FITNESS FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION INSTALLATION ERRORS SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES TRANSIENT FAILURES OF ELECTRONIC SYSTEMS HARDWARE AND OR SOFTWARE UNANTICIPATED USES OR MISUSES OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY OR PERSONS INCLUDING THE RISK OF BODILY INJURY AND DEATH SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE TO AVOID DAMAGE INJURY OR DEATH THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES INCLUDING BUT NOT LIMITED TO BACK UP OR SHUT DOWN MECHANISMS BECAUSE EACH END USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS THE USER OR
19. AO Control DACO DAC Lg lt Data 16 FIFO Data 32 D Calibration Figure 3 2 NI 6120 Block Diagram PXI PCI Bus Input Mode B The following sections describe in detail each AT category The NI 6115 6120 supports only differential DIFF input mode For more information about DIFF input refer to the Connecting Analog Input Signals section of Chapter 4 Connecting Signals which contains diagrams showing the signal paths for DIFF input mode Note The inputs are differential only in the sense that the ground loops are broken The negative input is not intended to carry signals of interest rather it provides a DC reference point for the positive input which may be different than ground NI 6115 6120 User Manual 3 2 ni com Chapter 3 Hardware Overview Input Polarity and Input Range The NI 6115 6120 has bipolar inputs only Bipolar input means that the midpoint of the input voltage range is centered at zero volts You can independently configure each channel for a different input voltage range The software programmable gain on this device increases its overall flexibility by matching the input signal ranges to those that the ADC can accommodate It has ranges of 42 V 20 V 10 V 5 V 2 V 1 V 500 mV and 200 mV and is suited for a wide variety of signal levels By choosing the optimal gain setting you can maximize usage of the dynamic range of the ADC which effectively increases inpu
20. APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION INCLUDING WITHOUT LIMITATION THE APPROPRIATE DESIGN PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION Compliance FCC Canada Radio Frequency Interference Compliance Determining FCC Class The Federal Communications Commission FCC has rules to protect wireless communications from interference The FCC places digital electronics into two classes These classes are known as Class A for use in industrial commercial locations only or Class B for use in residential or commercial locations Depending on where it is operated this product could be subject to restrictions in the FCC rules In Canada the Department of Communications DOC of Industry Canada regulates wireless interference in much the same way Digital electronics emit weak signals during normal operation that can affect radio television or other wireless products By examining the product you purchased you can determine the FCC Class and therefore which of the two FCC DOC Warnings apply in the following sections Some products may not be labeled at all for FCC if so the reader should then assume these are Class A devices FCC Class A products only display a simple warning statement of one paragraph in length regarding interference and undesired operation M
21. Enr nan coeds ths Dont ren line inst 3 10 National Instruments Corporation vij NI 6115 6120 User Manual Contents Programmable Function Inputs ss 3 12 Device and RISE Clock ssrs ss n raa aaa Ea 3 12 RTSI Triggers asinine a AT E AERA duet ER EEA 3 12 Chapter 4 Connecting Signals VO Connector oneta e e a enter mire Men REE 4 1 T O Connector Signal Descriptions ss 4 3 Typ s of Signal Sources a e AU A e N a Pees 4 7 Bloating Siona SOUT ES y rend Mules TN EEE AE RE 4 7 Ground Referenced Signal Sources 4 8 Connecting Analog Input Signals ss 4 8 Connections for Ground Referenced Signal Sources 0 0 0 eee eeeeeereeeees 4 9 Connections for Nonreferenced or Floating Signal Sources 4 11 Common Mode Signal Rejection Considerations 4 12 Working Voltage Ran ge snoert stestevatevtves n on feed enr ds 4 13 Connecting Analog Output Signals 00 eee eseceecneceseseeeeseseeeseseeetsesseeeseeseee 4 14 Connecting Digital T O Sighals ess Mines tn 4 15 Correlating DIO Signal Connections 4 16 Power Connect Ons sent non Monnier edit en A RE te at et eee 4 18 Connecting Timing Signals ss 4 18 Programmable Function Input Connections 4 20 DAQ Timing Connections sise 4 20 TRIGE Sigma EE 5 se ren nn bi Gen A dE 4 21 TRIG Signals 58 a ai ein he eae nel 4 22 STARTSCAN Signal i air e rie tessa se re 4 24 CONV
22. Misuse of the product can result in a hazard You can compromise the safety protection built into the product if the product is damaged in any way If the product is damaged return it to National Instruments for repair Do not substitute parts or modify the product except as described in this document Use the product only with the chassis modules accessories and cables specified in the installation instructions You must have all covers and filler panels installed during operation of the product Do not operate the product in an explosive atmosphere or where there may be flammable gases or fumes If you must operate the product in such an environment it must be in a suitably rated enclosure If you need to clean the product use a soft nonmetallic brush The product must be completely dry and free from contaminants before you return it to service Operate the product only at or below Pollution Degree 2 Pollution is foreign matter in a solid liquid or gaseous state that can reduce dielectric strength or surface resistivity The following is a description of pollution degrees e Pollution Degree 1 means no pollution or only dry nonconductive pollution occurs The pollution has no influence e Pollution Degree 2 means that only nonconductive pollution occurs in most cases Occasionally however a temporary conductivity caused by condensation must be expected e Pollution Degree 3 means that conductive pollution occurs or dry no
23. National Instruments Corporation 1 1 NI 6115 6120 User Manual Chapter 1 Introduction you do not need the RTSI cable for system triggering and timing on the PXI In addition a phase locked loop PLL circuit accomplishes the synchronization of multiple NI PXI 6115 6120 devices or other PXI devices which support PLL synchronization by allowing these devices to all lock to the same reference clock present on the PXI backplane Refer to the Phase Locked Loop Circuit section of Chapter 3 Hardware Overview for more information Detailed specifications of the NI 6115 6120 are in Appendix A Specifications Using PXI with CompactPCI AN NI 6115 6120 User Manual The ability to use PXI compatible products with standard CompactPCI products is an important feature of PXI Specification Revision 2 0 If you use a PXI compatible plug in device in a standard CompactPCI chassis you are unable to use PXI specific functions but you can still use the basic plug in device functions For example the RTSI interface on the NI PXI 6115 6120 is available in a PXI chassis but not in a CompactPCI chassis The CompactPCI specification permits vendors to develop sub buses that coexist with the basic PCI interface on the CompactPCI bus Compatible operation is not guaranteed between CompactPCI devices with different sub buses nor between CompactPCI devices with sub buses and PXI devices The standard implementation for CompactPCI does not include thes
24. National Instruments Documentation ss xii Related Documentation estes farniente ee SEEE xiii Chapter 1 Introduction Abo tthe NL 6115 6120 232 Med terre tatin 1 1 Using PXI with CompactPCI nent ie eR E i 1 2 What You Need to Get Started dns nent i 1 3 Software Programming Choices ss 1 4 N DAQ ie ta ent E mener t a eet a EET 1 4 National Instruments ADE Software 1 5 Optional Equipment este een di ent aes ne SEEE 1 6 Custom Cabling ss nine EE i E EEA AN nd ee ets de tS 1 6 Unpacking sanaa o tn teint ri P SEE aR EE Ea ESTERS 1 7 Safety Information sssini nt wie Re A E ai a elas aan a 1 8 Chapter 2 Installing and Configuring the NI 6115 6120 Installing the SoftWare a R E nn iles nt 2 1 Installing the Hard Ware rarene isen teneri i EE E AEAEE 2 1 Configuring the DEVICE issues cease bd nn E EAEE 2 3 Chapter 3 Hardware Overview Analog INPUT asura E E EE E O dre E EE E E Mensuel 3 2 Input ModE a in Ae rE 3 2 Input Polarity and Input Range ss 3 3 Considerations for Selecting Input Ranges 0 0 eee eeeeeeeeeees 3 4 Input Coup lm gsc lt ne TA cuss Meee orig ent apie teens 3 4 Analog Output et edicts evi ies Headey ee eee hk cee ete ees aes 3 5 Analog TS SOL su semer nr tintin nt ne tue cents Re Sete tte 3 5 Antialiasing DL AE E mn denim mnt A E nt 3 8 Phase Locked oop CHCU nds Gun ee dates dat At ns eus 3 9 Correlated Digital VO amp 45 20 nn as arm nie teen 3 10 Timing Signal RON
25. This Manual bold CompactPCI italic monospace NI 6115 6120 PCI PXI Bold text denotes items that you must select or click in the software such as menu items and dialog box options Bold text also denotes parameter names and hardware labels CompactPCI refers to the core specification defined by the PCI Industrial Computer Manufacturer s Group PICMG Italic text denotes variables emphasis a cross reference or an introduction to a key concept This font also denotes text that is a placeholder for a word or value that you must supply Monospace text denotes text or characters that you should enter from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and code excerpts This phrase refers to any device in the NI 6115 6120 family Peripheral Component Interconnect PCT is a high performance expansion bus architecture originally developed by Intel to replace ISA and EISA A rugged open system for modular instrumentation based on CompactPCI with special mechanical electrical and software features The PXI bus standard was originally developed by National Instruments in 1997 and is now managed by the PXI bus Systems Alliance National Instruments Documentation NI 6115 6120 User Manual The NI
26. Trigger section of Chapter 3 Hardware Overview As an output this is the TRIG1 signal In posttrigger DAQ sequences a low to high transition indicates the initiation of the DAQ sequence In pretrigger applications a low to high transition indicates the initiation of the pretrigger conversions PFI1 TRIG2 DGND Input PFI1 Trigger 2 As an input this is a PFI As an Output output this is the TRIG2 signal In pretrigger applications a low to high transition indicates the initiation of the posttrigger conversions TRIG2 is not used in posttrigger applications PFI2 CONVERT DGND Input PFI2 Convert As an input this is a PFI As an output Output this is the CONVERT signal A high to low edge on CONVERT indicates that an A D conversion is occurring PFI3 GPCTR1_SOURCE DGND Input PFI3 Counter 1 Source As an input this is a PFI As Output an output this is the GPCTR1_SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 PFI4 GPCTR1_GATE DGND Input PFI4 Counter 1 Gate As an input this is a PFI As an Output output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 1 GPCTR1_OUT DGND Output Counter 1 Output This output is from the general purpose counter output PFIS UPDATE DGND Input PFI5 Update As an input this is a PFI As an output Output this is the UPDATE signal A high to low edge on UPDATE indicates that the AO
27. another PFI is externally generating the updates The output is an active low pulse with a pulse width of 50 to 75 ns This output is set to high impedance at startup 4 30 ni com Chapter 4 Connecting Signals Figures 4 27 and 4 28 show the timing requirements for UPDATE Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 27 UPDATE Input Signal Timing ty 50 75 ns Figure 4 28 UPDATE Output Signal Timing The DACs are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches The UI counter for the NI 6115 6120 normally generates UPDATE unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by software or the internal buffer counter BC D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate UISOURCE Signal Any PFI pin can receive as an input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses UISOURCE as a clock to time the generation of the UPDATE signal You must configure the PFI pin you select as the source for UISOURCE in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low Figure 4 29 shows the timing requirements for UISOUR
28. can be removed This signal has a 450 ns pulse width and is software enabled 3 Note When using NI DAQ SCANCLK polarity is low to high and cannot be changed programmatically Figure 4 23 shows the timing for SCANCLK CONVERT SCANCLK gt lt i gt L ta 50 to 100 ns tw 450 ns Figure 4 23 SCANCLK Signal Timing NI 6115 6120 User Manual 4 28 ni com Chapter 4 Connecting Signals EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external device can use this signal to latch signals or to trigger events In the single pulse mode software controls the level of EXTSTROBE A 10 us and a 1 2 us clock are available for generating a sequence of eight pulses in the hardware strobe mode Sy Note EXTSTROBE cannot be enabled through NI DAQ Figure 4 24 shows the timing for the hardware strobe mode EXTSTROBE signal ty 600 ns or 5 us Figure 4 24 EXTSTROBE Signal Timing Waveform Generation Timing Connections The AO group defined for the NI 6115 6120 is controlled by WFTRIG UPDATE and UISOURCE WFTRIG Signal Any PFI pin can receive as an input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input WFTRIG is configured in the edge detection mode You can select any PFI pin as the source for WFTRI
29. e Connect the equipment into an outlet on a circuit different from that to which the receiver is connected e Consult the dealer or an experienced radio TV technician for help Canadian Department of Communications This Class B digital apparatus meets all requirements of the Canadian Interference Causing Equipment Regulations Cet appareil num rique de la classe B respecte toutes les exigences du R glement sur le mat riel brouilleur du Canada Compliance to EU Directives Readers in the European Union EU must refer to the Manufacturer s Declaration of Conformity DoC for information pertaining to the CE Marking compliance scheme The Manufacturer includes a DoC for most every hardware product except for those bought for OEMs if also available from an original manufacturer that also markets in the EU or where compliance is not required as for electrically benign apparatus or cables To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Select the appropriate product family followed by your product and a link to the DoC appears in Adobe Acrobat format Click the Acrobat icon to download or read the DoC The CE Marking Declaration of Conformity will contain important supplementary information and instructions for the user or installer Contents About This Manual CONVENTIONS ES r Santa sut EE Lanes codes Ps Sates duets an beads inertie AE E xi
30. filter value Set paramID to ND_Digital_Filter Set ParamValue to ND_High for a filter value of 500 kHz on the NI 6115 or 100 kHz on the NI 6120 Use ND_Low for a filter value of 50 kHz on the NI 6115 Use ND_None to disable the filter The filter is disabled by default I have connected a differential input signal but my readings are random and drift rapidly What is wrong Check your ground reference connections The signal may be referenced to a level that is considered floating with reference to the device ground reference Even if you are in differential mode the signal must still be referenced to the same ground level as the device reference There are various methods of achieving this reference while maintaining a high common mode rejection ratio CMRR These methods are outlined in Chapter 4 Connecting Signals National Instruments Corporation B 3 NI 6115 6120 User Manual Appendix B NI 6115 6120 User Manual Common Questions I m using the DACs to generate a waveform but I discovered with a digital oscilloscope that there are glitches on the output signal Is this normal When the DAC switches from one voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of the D A code switches You can build a lowpass deglitching filter to remove some of these glitches depending on the frequency and nature of your output signal Can I synchronize
31. operations to the same clock Refer to the Correlating DIO Signal Connections section of Chapter 4 Connecting Signals for information on which signals you can use to clock DIO operation At system startup and reset the DIO ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals GPCTRO_UP_DOWN and GPCTR1_UP_DOWN are input only and do not affect the operation of the DIO lines Routing NI 6115 6120 User Manual The DAQ STC provides a flexible interface for connecting timing signals to other devices or external circuitry The NI 6115 6120 uses the RTSI bus to interconnect timing signals between devices and it uses the programmable function input PFD pins on the I O connector to connect the device to external circuitry These connections are designed to enable the NI 6115 6120 to both control and be controlled by other devices and circuits There are 13 timing signals internal to the DAQ STC that can be controlled by an external source These timing signals can also be controlled by signals generated by the DAQ STC and these selections are fully software 3 10 ni com Chapter 3 Hardware Overview configurable For example Figure 3 11 shows the signal routing multiplexer for controlling the STARTSCAN signal e RTSI Trigger lt 0 6 gt
32. or less than 42 V for ranges gt 10 V If any of these conditions are exceeded current limiters limit the input current to 20 mA maximum into any input until the fault condition is removed iy Note All inputs are protected at up to 42 V National Instruments Corporation 4 13 NI 6115 6120 User Manual Chapter 4 Connecting Signals Connecting Analog Output Signals The AO signals are DACOOUT DACIOUT and AOGND DACOOUT is the voltage output signal for AO channel 0 DACIOUT is the voltage output signal for AO channel 1 AOGND is the ground reference signal for the AO channels AOGND is a hard ground Figure 4 6 shows how to connect AO signals to the NI 6115 6120 Load e AOGND T tO DACOOUT lt Channel 0 Vv us O DAC1OUT lt Channel 1 Analog Output Channels NI 6115 6120 NI 6115 6120 User Manual Figure 4 6 Analog Output Connections 4 14 ni com Chapter 4 Connecting Signals Connecting Digital 1 0 Signals The DIO signals are DIO lt 0 7 gt and DGND DIO lt 0 7 gt are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program groups of individual lines to be inputs or outputs A Caution Exceeding the maximum input voltage ratings which are listed in Table 4 3 can damage the NI 6115 6120 and the computer NI is not liable for any damage resulting from such signal connecti
33. out memory buffer the first data stored is the first data sent to the acceptor often used on DAQ devices to temporarily store incoming or outgoing data until that data can be retrieved or output signal sources including batteries transformers or thermocouples with voltage signals that are not connected to an absolute reference or system ground also called nonreferenced signal sources field programmable gate array frequency output signal the factor by which a signal is amplified sometimes expressed in decibels gate signal general purpose counter signal general purpose counter 0 gate signal general purpose counter 0 output signal general purpose counter 0 clock source signal general purpose counter 0 up down signal general purpose counter gate signal general purpose counter output signal general purpose counter clock source signal G 5 NI 6115 6120 User Manual Glossary GPCTR1_UP_DOWN grounded signal sources T O impedance in INL kHz NI 6115 6120 User Manual general purpose counter 1 up down signal signal sources with voltage signals that are referenced to a system ground such as the earth or a building ground also called grounded signal sources hour hertz the number of scans read or updates written per second input output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces
34. selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to high impedance at startup Figure 4 32 shows the timing of GPCTRO_OUT 3 Note When using external clocking mode with correlated DIO this pin is used as an input for the external clock GPCTRO_SOURCE GPCTRO_OUT Pulse on TC GPCTRO_OUT Toggle output on TC i TC NI 6115 6120 User Manual Figure 4 32 GPCTRO_OUT Signal Timing 4 34 ni com Chapter 4 Connecting Signals GPCTRO_UP_DOWN Signal This signal can be received as an input on the DIO6 pin and is not available as an output on the I O connector The general purpose counter 0 counts down when this pin is at a logic low and count up when it is at a logic high You can disable this input so that software can control the up down functionality and leave the DIO6 pin free for general use GPCTR1_SOURCE Signal Any PFI pin can receive as an input the GPCTR1_SOURCE signal which is available as an output on the PFI3 GPCTR1_SOURCE pin As an input GPCTR1_SOURCE is configured in the edge detection mode You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge As an output GPCTR1_SOURCE monitors the actual clock connected to general purpose counter 1 even if another PFI is externally generating the source clock
35. table 4 3 input coupling 3 4 input polarity and range bipolar input 3 3 input range and measurement precision table 3 4 overvoltage hazard caution 3 3 selection considerations 3 4 inside region analog triggering mode 3 7 installation category 1 9 hardware installation 2 1 questions about B 2 software installation 2 1 unpacking NI 6115 6120 1 7 instrument drivers C 1 internal timebase device and RTSI clocks 3 12 K KnowledgeBase C 1 L loading calibration constants 5 1 low hysteresis analog triggering mode 3 8 lowValue 3 5 manual See documentation MITE bus interface chip 1 1 NI 6115 6120 User Manual Index National Instruments calibration certificate C 2 customer education C 1 Declaration of Conformity C 1 documentation xii professional services C 1 system integration services C 1 technical support C 1 worldwide offices C 2 NI 6115 6120 device See also hardware overview block diagrams NI 6115 block diagram 3 1 NI 6120 block diagram 3 2 configuration 2 3 custom cabling 1 6 optional equipment 1 6 overview 1 1 questions about analog input and output B 3 general information B 1 installation and configuration B 2 timing and digital I O B 5 requirements for getting started 1 3 safety information 1 8 unpacking 1 7 NI DAQ driver software questions about B 2 noise avoiding 4 39 nonreferenced signal connections 4 11 0 online technical support C 1 optional equ
36. the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks CVI DAQ STC LabVIEW Measurement Studio MITE MXI National Instruments NI ni com NI DAQ NI Developer Zone and RTSI are trademarks of National Instruments Corporation Product and company names mentioned herein are trademarks or trade names of their respective companies Patents For patents covering National Instruments products refer to the appropriate location Help Patents in your software the patents txt file on your CD or ni com patents WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS 1 NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO
37. with PXI 1 2 configuration description 2 3 questions about B 2 connectors See I O connectors contacting National Instruments C 2 conventions used in manual xi CONVERT signal See also PFI2 CONVERT signal input timing figure 4 26 output timing figure 4 26 RTSI bus signal connections figure 3 13 timing connections 4 26 typical posttriggered acquisition figure 4 21 typical pretriggered acquisition figure 4 21 correlated digital I O See digital I O counter timer applications B 5 custom cabling 1 6 customer education C 1 ni com professional services C 1 technical support C 1 D DACOOUT signal analog output signal connections 4 14 description table 4 3 signal summary table 4 5 DACIOUT signal analog output signal connections 4 14 description table 4 3 signal summary table 4 5 DAQ timing connections See data acquisition timing connections DAQ STC system timing controller overview 1 1 questions about B 1 timing signal routing 3 10 data acquisition timing connections AIGATE signal 4 20 4 27 CONVERT signal 4 20 4 26 EXTSTROBE signal 4 29 SCANCLK signal 4 20 4 28 SISOURCE signal 4 20 4 27 STARTSCAN signal 4 20 4 24 TRIGI signal 4 20 TRIG 2 signal 4 20 4 22 typical posttriggered acquisition figure 4 21 typical pretriggered acquisition figure 4 21 DC input coupling 3 4 Declaration of Conformity C 1 deglitching questions about B 4 device clocks 3 12 dev
38. 1 000 h ni com Appendix Specifications Digital 1 0 Number of channels 0 0 0 0 eee 8 input output Compatibility 000 eeeeeeeeeeeees TTL CMOS Table A 7 Digital logic levels Level Min Max Input low voltage 0 0 V 0 8 V Input high voltage 2 0 V 5 0 V Input low current Vin 0 V 320 UA Input high current V 5 V 10 uA Output low voltage Io 24 mA 0 4 V Output high voltage loy 13 mA 4 35 V Power on state Input high impedance Data transferSnsison anioien DMA interrupts programmed I O Input buffer session nios 2 000 bytes Output buffer 2 000 bytes Transfer rate 1 word 8 bits 10 Mwords s Timing 1 0 Number of channels 0 0 0 0 eee eee 2 up down counter timers 1 frequency scaler Resolution Counter timers cccccccceeseseseseeees 24 bits Frequency scaler esceeseeseeeeeees 4 bits Compatibility 2 0 eee eeeeeeneeseeeeeeenees TTL CMOS Base clocks available Counter timers cccccesscecceeeeeeees 20 MHz 100 kHz Frequency scaler eee eee 10 MHz 100 kHz National Instruments Corporation A 15 NI 6115 6120 User Manual Appendix Specifications Triggers NI 6115 6120 User Manual Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 0 0 0 10 ns edge detect mode Min gate pulse duration ee 10 ns edge detect mode Data transfers ccccccccccccccc
39. 115 6120 includes high density memory modules allowing for long waveform generations Analog Trigger In addition to supporting internal software triggering and external digital triggering to initiate a DAQ sequence these devices also support analog hardware triggering You can configure the analog trigger circuitry to accept either a direct analog input from the PFIO TRIG1 pin on the T O connector or a post gain signal from the output of the PGIA on any of the channels as shown in Figure 3 3 The trigger level range for the direct analog channel is 10 V with a resolution of 78 mV for the NI 6115 and 4 88 mV for the NI 6120 The input impedance for the direct analog channel is 10 kQ When this direct analog channel is configured for AC coupling the corner frequency is 159 Hz The range for the post PGIA trigger from a selected channel is the full scale range of the selected channel with a resolution of that range divided by 256 for the NI 6115 and 4 096 for the NI 6120 Two trigger reference signals lowValue and highValue can then be independently set to achieve advanced triggering modes Refer to Figures 3 3 through 3 8 for illustrations of these modes Sy Note The PFIO TRIGI pin is an analog input when configured as an analog trigger Therefore it is susceptible to crosstalk from adjacent pins which can result in false triggering when the pin is left unconnected To avoid false triggering make sure the PFI0 TRIG1 pin is connected
40. 1_OUT signal description table 4 4 general purpose counter timing summary figure 4 37 general purpose timing connections 4 36 signal summary table 4 7 GPCTR1_SOURCE signal See also PFI3 GPCTR1_SOURCE signal general purpose timing connections 4 35 general purpose counter timing summary figure 4 37 general purpose timing connections 4 35 GPCTR1_OUT signal timing figure 4 37 ni com GPCTR1_UP_DOWN signal digital I O lines 3 10 general purpose timing connections 4 37 ground referenced signal sources description 4 8 questions about B 3 signal connections 4 9 H hardware installation procedure 2 1 unpacking NI 6115 6120 1 8 hardware overview analog input input coupling 3 4 input mode 3 2 input polarity and range 3 3 selection considerations 3 4 analog output 3 5 analog trigger block diagram 3 6 overview 3 5 antialiasing filters 3 8 block diagrams NI 6115 block diagram 3 1 NI 6120 block diagram 3 2 correlated digital I O 3 10 phase locked loop circuit 3 9 timing signal routing clocks 3 12 overview 3 10 programmable function inputs 3 12 RTSI triggers 3 12 STARTSCAN signal routing figure 3 11 help professional services C 1 technical support C 1 high hysteresis analog triggering mode 3 7 highValue 3 5 National Instruments Corporation Index T O connectors exceeding maximum ratings caution 4 1 overview 4 1 pin assignments figure 4 2 signal descriptions
41. 21 CONVERT Output Signal Timing 4 26 ni com Chapter 4 Connecting Signals The ADC switches to hold mode within 20 ns of the selected edge This hold mode delay time is a function of temperature and does not vary from one conversion to the next The sample interval counter on the NI 6115 6120 device normally generates CONVERT unless you select some external source The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished It then reloads itself in preparation for the next STARTSCAN pulse A D conversions generated by either an internal or external CONVERT signal are inhibited unless they occur within a DAQ sequence Scans occurring Within a DAQ sequence may be gated by either the hardware signal AIGATE or the software command register gate AIGATE Signal Any PFI pin can receive as an input the AIGATE signal which is not available as an output on the I O connector The AIGATE signal can mask off scans in a DAQ sequence You can configure the PFI pin you select as the source for AIGATE in level detection mode You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur AIGATE can neither stop a scan in progress nor continue a previously gated off scan Once a scan has started AIGATE does not gate off conversions until the begin
42. 6115 6120 User Manual the difference in time between the 10 and 90 points of the step response of a system root mean square resistive temperature detector a metallic probe that measures temperature based upon its coefficient of resistivity real time system integration bus the National Instruments timing bus that connects DAQ devices directly by means of connectors on top of the devices for precise synchronization of functions RTSI Oscillator RTSI bus master clock seconds samples samples per second used to express the rate at which a DAQ device samples an analog signal scan clock signal a term that describes very high speed DMA burst mode transfers that are made only by the bus master the manipulation of signals to prepare them for digitizing spurious free dynamic range SI counter clock signal source signal start scan signal system timing controller a measure of the amount of noise present in an analog circuit or when the analog inputs are grounded G 10 ni com TC toh tgsu gw THD thermocouple tote out TRIG SP TTL U UI UISOURCE UPDATE National Instruments Corporation Glossary terminal count the ending value of a counter gate hold time gate setup time gate pulse width total harmonic distortion the ratio of the total rms signal due to harmonic distortion to the overall rms signal in decibel or a percentage a temperature sensor created by joining two d
43. 6115 6120 User Manual is one piece of the documentation set for the DAQ system You could have any of several types of documentation depending on the hardware and software in the system Use the documentation you have as follows e DAQ Quick Start Guide This guide describes how to install the DAQ software and hardware and confirm that the DAQ device is operating properly When using this guide refer to the pinout diagram for the NI 6110 6111 The pinouts for the NI 6110 6111 and the NI 6115 6120 are identical e DAQ hardware documentation This documentation has detailed information about the DAQ hardware that plugs into or is connected to the computer Use this documentation for hardware installation and xii ni com About This Manual configuration instructions specification information about the DAQ hardware and application hints Software documentation You may have both application software and NI DAQ documentation NI application software includes LabVIEW and Measurement Studio After you set up the hardware system use either your application software documentation or the NI DAQ documentation to help you write your application If you have a large complicated system it is worthwhile to look through the software documentation before you configure the hardware Accessory installation guides or manuals If you are using accessory products read the terminal block and cable assembly installation guides They explain how to ph
44. 68 pin male SCSI II type Operating temperature 0 to 50 C Storage temperature 20 to 70 C 1 RTSI Trigger lt 6 gt is configured as the PXI Star Trigger for the NI PXI 6115 6120 Refer to the RTSI Triggers section of Chapter 3 Hardware Overview for more information National Instruments Corporation A 17 NI 6115 6120 User Manual Appendix Specifications Relative humidity 10 to 90 noncondensing Pollution Degree indoor use only 2 Safety The NI 6115 6120 was evaluated using the criteria of EN 61010 1 a 2 1995 and meets the requirements of the following standards for safety and electrical equipment for measurement control and laboratory use e EN 61010 1 IEC 61010 1 e UL3111 1 e CAN CSA C22 2 No 1010 1 Maximum Working Voltage Maximum working voltage refers to the signal voltage plus the common mode voltage Channel to earth 0 eee eee eeeeeeeee 42 V Installation Category I Channel to channel eee eee 42 V Installation Category I Electromagnetic Compatibility EMC EM 2 ua CE C Tick and FCC Part 15 Class A Compliant MISSIONS sent Sods ete ins tnoit te scene EN 55011 Class A at 10 m FCC Part 15A above 1 GHz TM MUNICY nr sien lie de Evaluated to EN 61326 1998 Table 1 8 Note For full EMC and EMI compliance you must operate this device with shielded cabling In addition all covers and filler panels must be
45. Appendix Specifications Full Scale 0 3 dB Input Amplitude 74 38 T T T T T T T TT T T T T T T T T 0 1 1 0 10 0 Frequency MHz Figure A 1 NI 6115 Total Harmonic Distortion Plus Noise THD N NI 6115 6120 User Manual A 6 ni com Appendix Specifications Full Scale 0 3 dB Input Amplitude 85 e e o RS aS 83 g L x lt X X gt 81 x LS x 4 5V 2V 79 1V X 0 5 V 77 4 X 02V 0 10V x X X X x 75 T T T T T T T T T T T T T T T T X 1 10 100 Frequency kHz National Instruments Corporation Figure A 2 NI 6120 Total Harmonic Distortion Plus Noise THD N A 7 NI 6115 6120 User Manual Appendix Specifications High Voltage Ranges only 10 V Input Amplitude 74 68 O D THD N dBc O1 O 50 lt 50 V o 20 V 44 38 T T T T T T T T T T T T T T T T T 0 1 1 0 10 0 Frequency MHz Figure A 3 NI 6115 High Voltage THD N NI 6115 6120 User Manual A 8 ni com Appendix Specifications High Voltage Ranges only 10 V Input Amplitude 85 0 84 5 84 0 50 V 83 5 20 V 83 0 82 5 82 0 a
46. CE National Instruments Corporation 4 31 NI 6115 6120 User Manual Chapter 4 Connecting Signals tp 50 ns minimum ty 10 ns minimum Figure 4 29 UISOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase normally generates UISOURCE unless you select some external source General Purpose Timing Signal Connections The general purpose timing signals are GPCTRO_SOURCE GPCTRO_GATE GPCTRO_OUT GPCTRO_UP_DOWN GPCTR1_SOURCE GPCTR1_GATE GPCTR1_OUT GPCTR1_UP_DOWN and FREQ_OUT GPCTRO_SOURCE Signal Any PFI pin can receive as an input the GPCTRO_SOURCE signal which is available as an output on the PFI8 GPCTRO_SOURCE pin As an input GPCTRO_SOURCE is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO_SOURCE and configure the polarity selection for either rising or falling edge As an output GPCTRO_SOURCE reflects the actual clock connected to general purpose counter 0 even if another PFI is externally inputting the source clock This output is set to high impedance at startup NI 6115 6120 User Manual 4 32 ni com Chapter 4 Connecting Signals Figure 4 30 shows the timing requirements for GPCTRO_SOURCE t 50 ns minimum ty 10 ns minimum Figure 4 30 GPCTRO_SOURCE Signal Tim
47. DACs for output Each device features eight lines of TTL compatible correlated DIO and two 24 bit counter timers for TIO The NI 6115 6120 is a DAQ device for PXI or the PCI bus The device is software configured and calibrated and completely switchless and jumperless This feature is made possible by the NI MITE bus interface chip that connects the device to the PXI or PCI I O bus The MITE implements the PCI Local Bus Specification so that you can configure all the interrupts and base memory addresses with software The NI 6115 6120 uses the NI data acquisition system timing controller DAQ STC for time related functions The DAQ STC consists of three timing groups that control AI AO and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and a maximum timing resolution of 50 ns The DAQ STC makes possible such applications as buffered pulse generation and equivalent time sampling The NI 6115 6120 uses the Real Time System Integration RTSI bus to easily synchronize several measurement devices to a common trigger or timing event The RTSI bus allows synchronization of the measurements The RTSI bus consists of the RTSI bus interface and a ribbon cable to route timing and trigger signals between as many as five DAQ devices in the computer If you are using the NI PXI 6115 6120 in a PXI chassis RTSI lines known as the PXI trigger bus are part of the backplane Therefore
48. DAQ NI 6115 6120 User Manual Multifunction 1 0 Devices for PCI PXI CompactPCI Bus Computers NV NATIONAL November 2002 Edition gt INSTRUMENTS Part Number 322812C 01 Worldwide Technical Support and Product Information ni com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 Worldwide Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 55 11 3262 3599 Canada Calgary 403 274 9391 Canada Montreal 514 288 5722 Canada Ottawa 613 233 5949 Canada Qu bec 514 694 8521 Canada Toronto 905 785 0085 China 86 21 6555 7838 Czech Republic 02 2423 5774 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Greece 01 42 96 427 Hong Kong 2645 3186 India 91 80 4190000 Israel 03 6393737 Italy 02 413091 Japan 03 5472 2970 Korea 02 3451 3400 Malaysia 603 9596711 Mexico 001 800 010 0793 Netherlands 0348 433466 New Zealand 09 914 0488 Norway 32 27 73 00 Poland 22 3390 150 Portugal 210 311 210 Russia 095 238 7139 Singapore 65 6 226 5886 Slovenia 3 425 4200 South Africa 11 805 8197 Spain 91 640 0085 Sweden 08 587 895 00 Switzerland 056 200 51 51 Taiwan 02 2528 7227 United Kingdom 01635 523545 For further support information see the Technical Support and Professional Services appendix To comment on the documentation send email to techpubs ni com 2001 2002 National Instrumen
49. ERT Signal ses nn nine ten ts eee 4 26 AICATE Signal op tects Bret At oa tence RS ARE Re 4 27 SISOURCE Sipnalis cakiid tii eg ee Raa ae Bie 4 27 SCANCIK SIenal mres ER rm rs dire eds ne i 4 28 EXTSTROBE Signal dass sisted 4 29 Waveform Generation Timing Connections 0 eee eeceeseeeeeeeteeeeeeeees 4 29 WETRIG Signal Rae aie wisn ddl a nue nb in tr s 4 29 UPDA TEA Signal titine nl RERS 4 30 UISOURCE Signal dian in indie i ne te ete Den AE 4 31 General Purpose Timing Signal Connections 4 32 GPCTRO_SOURCE Signal ss 4 32 GPE TRO GATE Signal sd ts ere et nied res dre r s hed 4 33 GPCTRO OUT Signal ne tiie ten hs ten te 4 34 GPCFERO UP DOWN Si8tial jeccseet 5e ess 4 35 GPCTR1_SOURCE Signal insni orn a i a a a 4 35 GPCIRI GATE Signa eer nr EE 4 36 GPCIRI OUT Signal vise nnne A 4 36 NI 6115 6120 User Manual viii ni com Contents GPCTR1_UP DOWN Signaler EEA 4 37 FREQ OUT Signal 4 38 Field Wiring Considerations ss 4 39 Chapter 5 Calibration Loading Stored Calibration Constant ss 5 1 Self Cali bration kakr olde se AE eS Ba ie des ee ES 5 2 External Cahbration 5 E E E E be sais eR des 5 2 Appendix A Specifications Appendix B Common Questions Appendix C Technical Support and Professional Services Glossary Index National Instruments Corporation ix NI 6115 6120 User Manual About This Manual This manual describes the electrical and mechanical aspects of the NI 6115 6120 and contain
50. G and configure the polarity selection for either rising or falling edge The selected edge of WFTRIG starts the waveform generation for the DACs If you select internally generated UPDATE the UI counter starts As an output WFTRIG reflects the trigger that initiates waveform generation even if another PFI is externally triggering the waveform generation The output is an active high pulse with a pulse width of 25 to 50 ns This output is set to high impedance at startup National Instruments Corporation 4 29 NI 6115 6120 User Manual Chapter 4 Connecting Signals NI 6115 6120 User Manual Figures 4 25 and 4 26 show the timing requirements for WFTRIG t lt gt Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 25 WFTRIG Input Signal Timing ti lt gt ty 25 50 ns Figure 4 26 WFTRIG Output Signal Timing UPDATE Signal Any PFI pin can receive as an input the UPDATE signal which is available as an output on the PFIS UPDATE pin As an input UPDATE is configured in the edge detection mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of UPDATE updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output UPDATE reflects the actual update pulse that is connected to the DACs even if
51. I 6115 6120 RTSI lt 0 5 gt connects to PXI Trigger lt 0 5 gt respectively through the NI PXI 6115 6120 backplane In PXI RTSI lt 6 gt connects to the PXI Star Trigger line allowing the NI 6115 6120 to receive triggers from any Star Trigger controller plugged into slot 2 of the chassis For more information on the Star Trigger refer to the PXI Specification Revision 2 0 DAQ STC d lt _ _P TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTRO_SOURCE GPCTRO_GATE GPCTRO_OUT STARTSCAN AIGATE SISOURCE UISOURSE GPCTR1_SOURCE GPCTR1_GATE RTSI_OSC 20 MHz Trigger Ad 7 nr RTSI Bus Connector RTSI Switch Clock Switch lt ______ gt Figure 3 12 PCI RTSI Bus Signal Connection National Instruments Corporation NI 6115 6120 User Manual Chapter 3 Hardware Overview DAQ STC PXI Star 6 PXI Trigger 0 5 PXI Bus Connector 6 PXI Trigger 7 RTSI Switch lt lt _ _P A Switch lt _ _____ gt TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTRO_SOURCE GPCTRO_GATE GPCTRO_OUT STARTSCAN AIGATE SISOURCE UISOURSE GPCTR1_SOURCE GPCTR1_GATE RTSI_OSC 20 MHz WZ NI 6115 6120 User Manual Figure 3 13 PXI RTSI Bus Signal Connections Refer to the Connecting Timing Signals section of Chapter 4 Connecting Signals for a description of the signals shown in Figures 3 12 and 3 13 3 14
52. NI 6115 6120 The NI 6115 6120 is jumperless and switchless Which NI document should I read first to get started using DAQ software The DAQ Quick Start Guide and the NI DAQ or application software release notes documentation are good places to start What is the best way to test the NI 6115 6120 without programming the device Measurement amp Automation Explorer MAX has a Test Panel option that is available by selecting Devices and Interfaces and then selecting the device The test panels are excellent tools for performing simple functional tests of the device such as AI DIO and counter timer tests B 2 ni com Appendix B Common Questions Analog Input and Output Why is there a minimum sampling rate on the NI 6115 The NI 6115 makes use of a pipelined ADC in order to achieve high sampling rates Sampling at rates below 20 kS s can result in improper digitization which appear as noise in the acquired data How do I enable the programmable antialiasing filter on the NI 6115 6120 In LabVIEW select Data Acquisition Analog Input Advanced Analog Input AI Parameter vi from the function palette to set the filter values of 50 kHz and 500 kHz for the NI 6115 or to enable the 100 kHz filter for the NI 6120 on a per channel basis To disable the filter set the filter value to 0 Filter Setting Figure B 1 Setting Filter Values in LabVIEW In NI DAQ use the AI_Change_Parameter function to set the
53. NI 6115 6120 require a frequency timebase to generate the necessary timing signals for controlling A D conversions updates or general purpose signals at the I O connector The NI 6115 6120 can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the device to use the internal timebase you can also program the device to drive its internal timebase over the RTSI bus to another device that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is used directly by the device as the primary frequency source The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal This timebase is software selectable RTSI Triggers The seven RTSI trigger lines on the RTSI bus provide a very flexible interconnection scheme for any device sharing the RTSI bus These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals The RTSI trigger lines connect to other devices through the PXI bus on the PXI backplane or through a special ribbon cable that must be installed for PCI Figure 3 12 shows the PCI signal connection scheme and Figure 3 13 shows the PXI connection scheme NI 6115 6120 User Manual 3 12 ni com Chapter 3 Hardware Overview In PCI you can access all seven RTSI lines RTSI lt 0 6 gt through their RTSI cable With the NI PX
54. Pulse Width tsp 23 ns minimum Gate Setup Time tysu 10 ns minimum Gate Hold Time tgh 0 ns minimum Gate Pulse Width tow 10 ns minimum Output Delay Time tout 80 ns maximum Figure 4 36 GPCTR Timing Summary National Instruments Corporation 4 37 NI 6115 6120 User Manual Chapter 4 Connecting Signals The GATE and OUT signal transitions shown in Figure 4 36 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram but with the source signal inverted and referenced to the falling edge of the source signal would apply when the counter is programmed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on the NI 6115 6120 Figure 4 36 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by t and ten in Figure 4 36 The gate signal is not required to be held after the active edge of the source signal If you use an internal timebase clock the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty
55. RIG signal and is stopped by either software or the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware signal AIGATE or the software command register gate National Instruments Corporation 4 25 NI 6115 6120 User Manual Chapter 4 Connecting Signals CONVERT Signal Any PFI pin can receive as an input the CONVERT signal which is available as an output on the PFI2 CONVERT pin Refer to Figures 4 20 and 4 21 for the relationship of CONVERT to the DAQ sequence As an input CONVERT is configured in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or falling edge The selected edge of CONVERT initiates an A D conversion As an output CONVERT reflects the actual convert pulse that is connected to the ADC even if another PFI is externally generating the conversions The output is an active low pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup Figures 4 20 and 4 21 show the input and output timing requirements for CONVERT Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 20 CONVERT Input Signal Timing ty 50 100 ns NI 6115 6120 User Manual Figure 4
56. This output is set to high impedance at startup Figure 4 33 shows the timing requirements for GPCTR1_SOURCE tp 50 ns minimum ty 10 ns minimum Figure 4 33 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates GPCTR1_SOURCE unless you select some external source National Instruments Corporation 4 35 NI 6115 6120 User Manual Chapter 4 Connecting Signals NI 6115 6120 User Manual GPCTR1_GATE Signal Any PFI pin can receive as an input the GPCTR1_GATE signal which is available as an output on the PFI4 GPCTR1_GATE pin As an input GPCTR1_GATE is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of applications to perform actions such as starting and stopping the counter generating interrupts and saving the counter contents As an output GPCTR1_GATE monitors the actual gate signal connected to general purpose counter 1 even if another PFI externally generates the gate This output is set to high impedance at startup Figure 4 34 shows the timing requirements for the GPCTR1_GATE signal Rising Edge Polarity Falling Edge Polarity ty 10 ns
57. _IN_ SCAN _CLOCK_TIMEBASE CONVERT AI Convert ND_IN_CONVERT National Instruments Corporation B 5 NI 6115 6120 User Manual Appendix B Common Questions Table B 1 Signal Name Equivalencies Continued Hardware LabVIEW Signal Name Route Signal NI DAQ Select_Signal AIGATE ND_IN_ EXTERNAL _ GATE WETRIG AO Start Trigger ND_ OUT _ START _TRIGGER UPDATE AO Update ND_OUT_UPDATE UISOURCE ND_OUT UPDATE _CLOCK_TIMEBASE AOGATE ND_OUT EXTERNAL _ GATE A if you do you can damage the device the computer and the connected equipment NI 6115 6120 User Manual What are the power on states of the PFI and DIO lines on the T O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardware Hence the device circuitry is not actively driving the output either high or low However these lines may have pull up or pull down resistors connected to them as shown in Table 4 5 Digital 1 0 Signal Summary These resistors weakly pull the output to either a logic high or logic low state For example DIO O is in the high impedance state after power on and Table 4 5 shows that there is a 50 KQ pull up resistor This pull up resistor sets the DIO 0 pin to a logic high when the output is in a high impedance state B 6 Caution If you enable a PFI line for output do not connect any external signal source to it ni com Te
58. a one channel AI data acquisition with a one channel AO waveform generation on the NI 6115 6120 Yes One way to accomplish synchronization is to use the waveform generation timing pulses to control the AI data acquisition To do this follow steps 1 through 4 below in addition to the usual steps for data acquisition and waveform generation configuration 1 Enable the PFIS5 line for output as follows e Ifyou are using NI DAQ call Select_Signal deviceNumber ND_PFI_5 ND_OUT_UPDATE ND_HIGH_TO_LOW e If you are using LabVIEW select Data Acquisition Calibration and Configuration Route Signal vi from the function palette and set signal name to PFI5 and signal source to AO Update 2 Set up data acquisition timing so that the timing signal for A D conversion comes from PFIS5 as follows e Ifyou are using NI DAQ call Select_Signal deviceNumber ND_IN_SCAN_START ND_PFI_7 ND_HIGH_TO_LOW e Ifyou are using LabVIEW select Data Acquisition Analog Input Advanced Analog Input AI Clock Config vi with clock source code set to PFI pin high to low and clock source string set to 5 3 Initiate AI data acquisition which starts only when the AO waveform generation starts 4 Initiate AO waveform generation B 4 ni com Appendix B Common Questions Timing and Digital 1 0 What types of triggering can be hardware implemented on the NI 6115 6120 Hardware digital and analog triggering are both supported on the NI
59. al accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow
60. allation Category II is for measurements performed on circuits directly connected to the electrical distribution system This category refers to local level electrical distribution such as that provided by a standard wall outlet for example 115 V for U S or 230 V for Europe Examples of Installation Category II are measurements performed on household appliances portable tools and similar products e Installation Category III is for measurements performed in the building installation at the distribution level This category refers to measurements on hard wired equipment such as equipment in fixed installations distribution boards and circuit breakers Other examples are wiring including cables bus bars junction boxes switches socket outlets in the fixed installation and stationary motors with permanent connections to fixed installations e Installation Category IV is for measurements performed at the primary electrical supply installation lt 1 000 V Examples include electricity meters and measurements on primary overcurrent protection devices and on ripple control units Installation categories also referred to as measurement categories are defined in electrical safety standard IEC 61010 1 2 Working voltage is the highest rms value of an AC or DC voltage that can occur across any particular insulation 3 MAINS is defined as a hazardous live electrical supply system that powers equipment Suitably rated measuring circuits ma
61. alog input signal connections 4 8 description table 4 3 signal summary table 4 5 ACH lt 0 3 gt GND signal table 4 3 AIGATE signal gating DAQ sequences 4 25 4 27 overview 4 27 RTSI bus signal connections figure 3 13 analog input input coupling 3 4 input mode 3 2 input polarity and range 3 3 questions about B 3 selection considerations 3 4 analog input signal connections common mode signal rejection 4 12 floating signal sources 4 11 ground referenced signal sources 4 9 nonreferenced signal sources 4 11 pseudodifferential connections definition 4 8 ground referenced signals figure 4 9 National Instruments Corporation analog input specifications DC transfer characteristics A 2 dynamic characteristics A 4 input characteristics A 1 stability A 11 analog output overview 3 5 questions about B 3 signal connections 4 14 analog output specifications DC transfer characteristics A 12 dynamic characteristics A 14 output characteristics A 12 stability A 14 voltage output A 13 analog trigger above high level analog triggering mode figure 3 7 avoiding false triggering note 3 6 below low level analog triggering mode figure 3 6 block diagram 3 6 high hysteresis analog triggering mode figure 3 7 highValue 3 5 3 6 3 7 3 8 inside region analog triggering mode figure 3 7 low hysteresis analog triggering mode figure 3 8 lowValue 3 5 3 6 3 7 3 8 overview 3 5 specificati
62. alue stored in EEPROM Temperature coefficient 4 1 ppm C max Long term stability 00 ee 6 ppm 1 000 h Output Characteristics Number of channels 2 voltage Resolution NL OT Ste meme kines 12 bits 1 in 4 096 NT 6120 nie en en 16 bits 1 in 65 536 Max update rate L h nn l ss siennes 4 MS s system dependent 2 Channel sssiuecsiiscsstessissevcntevietess 2 5 MS s system dependent Output buffer size 16 or 32 MS Data transfers oeve cs33 ss terne DMA interrupts programmed I O DMA MOS 2 sis ccsseevtesreetonestenaseetiss Scatter gather DC Transfer Characteristics INL NI 61 15 Scie een une A 0 5 LSB typ 2 LSB max NIG 20 ii secdes sn a ne 0 35 LSB typ 1 LSB max DNL ND GIIS anean a ee eee ne 0 25 LSB typ 1 LSB max NE6120 iii ete nt des 0 2 LSB typ 1 LSB max Offset gain error NEOTSE ss hoes teins rs pense Refer to Table A 5 NL 6120 bec me ni nee at Refer to Table A 6 A 12 ni com Appendix Specifications Table A 5 NI 6115 Analog Output DC Accuracy Information Absolute Accuracy Relative Accuracy Power on output voltage before software loads calibration values NE GTS iii aly 400 mV NEGIZ O Keine aeee 80 mV Initial power up glitch Magnitude senson ninaka 2 V Duration nonnes 200 ms National Instruments Corporation A 13 Nominal Range at of Rea
63. antialaising Bessel filter On the NI 6115 you can program the filters to provide a third order 50 kHz lowpass filter a third order 500 kHz lowpass filter or a pass through mode with no filtering On the NI 6120 you can program the filters to provide a five pole 100 kHz low pass filter or pass through These Bessel filters are highly effective at reducing signal aliasing and are designed for use with software filters Existing software algorithms alone provide good roll off at the cut off frequency as shown in Figure 3 9 However aliasing can cause high frequency harmonics to make it through passbands in the filter By combining hardware and software filtering it is possible to obtain both steep roll off and clean filtering of high frequency aliases 3 8 ni com Chapter 3 Hardware Overview f 4f cutoff fuyquist cutoff 2 foutott Hess Response of Analog Hardware Filters Response of Software Filters Figure 3 9 Effects of Hardware and Software Filtering on Antialiasing Phase Locked Loop Circuit NIPXI 6115 6120 A phase locked loop PLL circuit accomplishes the synchronization of multiple NI PXI 6115 6120 devices or other PXI devices which support PLL synchronization by allowing these devices to all lock to the same reference clock present on the PXI backplane This circuit allows you to trigger input or output operations on different devices and ensures that samples occur at the same ti
64. ational Instruments Corporation 4 39 NI 6115 6120 User Manual Calibration This chapter discusses the calibration procedures for the NI 6115 6120 NI DAQ includes calibration functions for performing all of the steps in the calibration process Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments On the NI 6115 6120 these adjustments take the form of writing values to onboard calibration DACs CalDACs Some form of device calibration is required for most applications If you do not calibrate the device the signals and measurements could have very large offset gain and linearity errors Three levels of calibration are available to you and are described in this chapter The first level is the fastest easiest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Stored Calibration Constants The NI 6115 6120 is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do not retain calibration information when the device is unpowered Loading calibration constants refers to the process of loading the CalDACs with the values stored in t
65. ccceeeseseeeeeeees DMA interrupts programmed I O DMA mode inssi Scatter gather Analog Trigger NI 6115 6120 source Level Resolution NI 6115 NI 6120 Hysteresis Bandwidth External input PFIO TRIG1 Impedance Coupling Protection All analog input channels external trigger PFIO TRIG1 full scale internal 10 V external Positive or negative software selectable 8 bits 1 in 256 12 bits 1 in 4 096 Programmable 3 dB 5 MHz internal external 10 KQ AC DC 0 5 V to Vcc 0 5 V when configured as a digital signal 35 V when configured as an analog trigger signal or disabled 35 V powered off ni com RTSI Bus Interface Appendix Specifications Digital Trigger Compatibility 000 eeeeseeeeeeeee TTL Respons ekien Rising or falling edge Pulse Wide sesrehultnssiniine 10 ns min Trigger lines c cccccecececscseeseseeeeeeseseeees 7 Typic sacha oversee ts Master slave Power Requirement Physical Environmental 5 VDC 5 INT OLIS unes us 2 2 A NI G120 58 rue tin 3 0 A A DNS E A E A SEA 0 8 A Power available at I O connector 4 65 to 5 25 VDC at 1 A Dimensions not including connectors NI PCI 6115 6120 31 2 by 10 6 cm 12 3 by 4 2 in NI PXI 6115 6120 ee 16 by 10 cm 6 3 by 3 9 in T O connector eeeeeeeeeeeeees
66. chnical Support and Professional Services Visit the following sections of the NI Web site at ni com for technical support and professional services National Instruments Corporation Support Online technical support resources include the following Self Help Resources For immediate answers and solutions visit our extensive library of technical support resources available in English Japanese and Spanish at ni com support These resources are available for most products at no cost to registered users and include software drivers and updates a KnowledgeBase product manuals step by step troubleshooting wizards hardware schematics and conformity documentation example code tutorials and application notes instrument drivers discussion forums a measurement glossary and so on Assisted Support Options Contact NI engineers and other measurement and automation professionals by visiting ni com ask Our online system helps you define your question and connects you to the experts by phone discussion forum or email Training Visit ni com custed for self paced tutorials videos and interactive CDs You also can register for instructor led hands on courses at locations around the world System Integration If you have time constraints limited in house technical resources or other project challenges NI Alliance Program members can help To learn more call your local NI office or visit ni com alliance D
67. com National Instruments ADE Software LabVIEW features interactive graphics a state of the art interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of virtual instruments for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW LabWindows CVI is a complete ANSI C ADE that features an interactive user interface code generation tools and the LabWindows CVI Data Acquisition and Easy I O libraries Measurement Studio which includes tools for Visual C and tools for Visual Basic is a development suite that allows you to design test and measurement applications For Visual Basic developers Measurement Studio features a set of ActiveX controls for using National Instruments National Instruments Corporation 1 5 NI 6115 6120 User Manual Chapter 1 Introduction DAQ hardware These ActiveX controls provide a high level programming interface for building virtual instruments VIs For Visual C developers Measurement Studio offers a set of Visual C classes and tools to integrate those classes into Visual C applications The ActiveX controls and classes are available with Measurement Studio and the NI DAQ software VI Logger is an easy to use yet flexible tool specifically designed for data logging applications Using dialog windows you can configure data logging tasks to easily acquire log view and share your data VI Logger does not require any p
68. ding Temp Absolute Full Scale Offset Drift Acc at Full Theoretical Resolution V 24 Hrs 90 Days 1 Year mV C Scale mV mV 10 0 0437 0 0445 0 0454 8 9 0 0006 13 5 4 88 Table A 6 NI 6120 Analog Output DC Accuracy Information Absolute Accuracy Relative Accuracy Nominal Range at of Reading Temp Absolute Full Scale Offset Drift Acc at Full Theoretical Resolution V 24 Hrs 90 Days 1 Year mV C Scale mV uV 10 0 0512 0 0520 0 0529 1 9 0 0006 6 7 305 2 Voltage Output Ran BOS nenir a E E 10 V Output coupling DC Output impedance eects 50 Q 5 Current diye anemoon na 5 mA Output stability Any passive load Protection ss MN mnt ls Short circuit to ground NI 6115 6120 User Manual NI 6115 6120 User Manual Dynamic Characteristics Slew rate NI 6115 NI 6120 Nois NI 6115 NI 6120 e Glitch energy at midscale transition NTGITS nenn poea NL6120 i n a inleias Settling time NI 6115 NI 6120 Stability Offset temperature coefficient NIGIS s rie nntnes NT 6120 sen messe Gain temperature coefficient NT GS sense NEGI ZO siens Onboard calibration reference lt E E ne E Temperature coefficient Long term stability eee 600 UV ins DC to 5 MHz 100 HV ns DC to 1 MHz 30 mV for 1 us 10 mV for 1 us 300 ns to 0 01 4 us to 1 LSB 35 uV C 35 uV C 56 9 ppm C 6 5 ppm C 5 000 V 2 5 mV actual value stored in EEPROM 0 9 ppm C max 6 ppm
69. e or level detection depends upon the particular timing signal being controlled The detection requirements for each timing signal are listed within the section that discusses that individual signal In edge detection mode the minimum pulse width required is 10 ns This setting applies for both rising edge and falling edge polarity settings Edge detect mode does not have a maximum pulse width requirement In level detection mode the PFIs themselves do not impose a minimum or maximum pulse width requirement but the particular timing signal being controlled can impose limits These requirements are listed later in this chapter DAQ Timing Connections The DAQ timing signals are TRIG TRIG2 STARTSCAN CONVERT AIGATE SISOURCE SCANCLK and EXTSTROBE Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received A typical posttriggered DAQ sequence is shown in Figure 4 12 3 Note On the NI 6115 6120 each STARTSCAN pulse initiates one CONVERT pulse which simultaneously samples all channels NI 6115 6120 User Manual 4 20 ni com Chapter 4 Connecting Signals Se oe E E STARTSCAN __ CONVERT r m Scan Counter 4 3 2 1 Figure 4 12 Typical Posttriggered Acquisition Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after th
70. e sub buses The NI PXI 6115 6120 works in any standard CompactPCI chassis adhering to PICMG CompactPCI 2 0 R3 0 PXI specific features are implemented on the J2 connector of the CompactPCI bus Table 1 1 lists the J2 pins used by the NI PXI 61 15 6120 The PXI device is compatible with any CompactPCI chassis with a sub bus that does not drive these lines Even if the sub bus is capable of driving these lines the PXI device is still compatible as long as those pins on the sub bus are disabled by default and are never enabled Caution Damage can result if these lines are driven by the sub bus 1 2 ni com Chapter 1 Introduction Table 1 1 NI PXI 6115 6120 J2 Pin Assignment PXI J2 Pin NI PXI 6115 6120 Signal PXI Pin Name Number RTSI lt 0 5 gt PXI Trigger lt 0 5 gt B16 A16 A17 A18 B18 C18 RTSI 6 Star D17 RTSI Clock PXI Trigger 7 E16 Reserved LBL lt 0 12 gt C20 E20 A19 C19 Reserved LBR lt 0 12 gt A21 C21 D21 E21 A20 B20 E15 A3 C3 D3 E3 A2 B2 What You Need to Get Started To set up and use the NI 6115 6120 you need the following NI PCI 6115 NI PXI 6115 NI PCI 6120 NI PXI 6120 documentation LabVIEW Windows Measurement Studio Windows VI Logger Windows National Instruments Corporation Q At least one of the following devices Q NI 6115 6120 User Manual Q NI DAQ for PC compatibles Q A computer or a PXI CompactPCI chassis and controller h
71. e trigger Figure 4 13 shows a typical pretriggered DAQ sequence The description for each signal shown in these figures appears later in this chapter TRIG1 TRIG2 STARTSCAN CONVERT a ih en Scan Counter 3 12 11 i 0 12 12 12 1 10 Figure 4 13 Typical Pretriggered Acquisition TRIG1 Signal Any PFI pin can receive as an input the TRIG1 signal which is available as an output on the PFIO TRIGI pin Refer to Figures 4 12 and 4 13 for the relationship of TRIG1 to the DAQ sequence As an input TRIG1 is configured in the edge detection mode You can select any PFI pin as the source for TRIGI and configure the polarity selection for either rising or falling edge The selected edge of TRIGI starts the DAQ sequence for both posttriggered and pretriggered acquisitions The NI 6115 6120 supports analog triggering on the PFIO TRIGI pin National Instruments Corporation 4 21 NI 6115 6120 User Manual Chapter 4 Connecting Signals NI 6115 6120 User Manual Refer to Chapter 3 Hardware Overview for more information on analog triggering As an output TRIG1 reflects the action that initiates a DAQ sequence even if another PFI is externally triggering the acquisition The output is an active high pulse with a pulse width of 25 to 50 ns This output is set to high impedance at startup Figures 4 14 and 4 15 show the timing requirements for TRIG1
72. eclaration of Conformity DoC A DoC is our claim of compliance with various European Council Directives using the manufacturer s self declaration of conformance This system affords the user protection for electronic compatibility EMC and product safety You can obtain the DoC for your product by visiting ni com hardref nsf C 1 NI 6115 6120 User Manual Appendix C Technical Support and Professional Services e Calibration Certificate If your product supports calibration you can obtain the calibration certificate for your product at ni com calibration If you searched ni com and could not find the answers you need contact your local office or NI corporate headquarters Phone numbers for our worldwide offices are listed at the front of this manual You also can visit the Worldwide Offices section of ni com niglobal to access the branch office Web sites which provide up to date contact information support phone numbers email addresses and current events NI 6115 6120 User Manual C 2 ni com Glossary Prefix Meaning Value p pico 10 12 n nano 10 9 u micro 10 6 m milli 10 3 k kilo 103 M mega 106 Numbers Symbols degree IV IA I 5 V greater than greater than or equal to less than less than or equal to per percent plus or minus positive of or plus negative of or minus ohm square root of 5 VDC source signal National Instrumen
73. ections data acquisition timing connections AIGATE signal 4 27 CONVERT signal 4 26 National Instruments Corporation 1 9 Index EXTSTROBE signal 4 29 SCANCLK signal 4 28 SISOURCE signal 4 27 STARTSCAN signal 4 24 TRIGI signal 4 21 TRIG2 signal 4 22 typical posttriggered acquisition figure 4 21 typical pretriggered acquisition figure 4 21 general purpose timing signal connections FREQ _ OUT signal 4 38 GPCTRO_GATE signal 4 33 GPCTRO_OUT signal 4 34 GPCTRO_SOURCE signal 4 32 GPCTRO_UP_DOWN signal 4 35 GPCTR1_GATE signal 4 36 GPCTR1_OUT signal 4 36 GPCTR1_SOURCE signal 4 35 GPCTR1_UP_DOWN signal 4 37 programmable function input connections 4 20 questions about B 5 timing I O connections figure 4 19 waveform generation timing connections UISOURCE signal 4 31 UPDATE signal 4 30 WFTRIG signal 4 29 timing I O questions about B 5 specifications A 15 timing signal routing clocks 3 12 programmable function inputs 3 12 RTSI triggers 3 12 STARTSCAN signal routing figure 3 11 training customer C 1 NI 6115 6120 User Manual Index TRIGI signal See also PFIO TRIG1 signal input timing figure 4 22 output timing figure 4 22 RTSI bus signal connections figure 3 13 timing connections 4 21 typical posttriggered acquisition figure 4 21 typical pretriggered acquisition figure 4 21 TRIG signal See also PFIL TRIG2 signal input timing figure 4 23 output timing figure
74. el 5 pole Bessel 50 and 500 kHz software enabled 100 kHz software enabled 80 dB DC to 100 kHz ni com Appendix Table A 3 NI 6115 Analog Input Dynamic Characteristics Specifications Bandwidth SFDR Typ SFDR Max CMRR System Noise Input Range MHz dB dB dB LSB ms 4 50 V 5 5 78 70 34 0 35 20 V 4 4 78 70 40 0 45 10 V 7 2 81 75 46 0 35 5 V 4 8 81 75 52 0 35 2 V 4 8 85 75 60 0 45 1 V 4 4 85 75 66 0 60 500 mV 4 4 85 75 70 0 80 200 mV 4 1 81 70 72 1 3 1 3 dB frequency for input amplitude at 96 of the input range 0 3 dB 2 Measured at 100 kHz with twelfth order bandpass filter after signal source 3 DC to 60 Hz 4LSB ns including quantization Table A 4 NI 6120 Analog Input Dynamic Characteristics Bandwidth SFDR Typ SFDR Max CMRR System Noise Input Range MHz dB dB dB LSB s 50 V 1 0 95 90 60 1 2 20 V 1 0 96 90 68 1 2 10 V 1 0 95 90 76 1 2 5 V 1 0 95 90 82 1 5 2 V 1 0 96 90 90 1 7 1 V 1 0 94 90 95 2 0 500 mV 1 0 90 85 100 2 2 200 mV 1 0 85 80 105 2 8 1 3 dB frequency for input amplitude at 10 of the input range 20 dB 2 Measured at 100 kHz with twelfth order bandpass filter after signal source 3 100 production tested at 100 kHz 4 DC to 60 Hz 5 LSB ms not including quantization National Instruments Corporation NI 6115 6120 User Manual
75. elded twisted pair wires to connect AI signals to the device With this type of wire the signals attached to the ACH and ACH inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference e Route signals to the device carefully Keep cabling away from noise sources The most common noise source in a PCI DAQ system is the video monitor Separate the monitor from the analog signals as far as possible The following recommendations apply for all signal connections to the NI 6115 6120 e Separate the NI 6115 6120 signal lines from high current or high voltage lines These lines can induce currents in or voltages on the NI 6115 6120 signal lines if they run in parallel paths at a close distance To reduce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other e Do not run signal lines through conduits that also contain power lines e Protect signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running them through special metal conduits For more information refer to the NI Developer Zone tutorial Field Wiring and Noise Consideration for Analog Signals available at ni com zone N
76. ereafter referred to as the computer LY Optional One of the following software packages and NI 6115 6120 User Manual Chapter 1 Introduction Software Programming Choices When programming National Instruments DAQ hardware you can use an NI application development environment ADE or other ADEs In either case you use NI DAQ NI DAQ NI DAQ which shipped with the NI 6115 6120 has an extensive library of functions that you can call from the ADE These functions allow you to use all the features of the device NI DAQ carries out many of the complex interactions such as programming interrupts between the computer and the DAQ hardware NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to the code Whether you are using Lab VIEW LabWindows CVI Measurement Studio VI Logger or other ADEs your application uses NI DAQ as illustrated in Figure 1 1 NI 6115 6120 User Manual 1 4 ni com Chapter 1 Introduction LabVIEW Conventional LabWindows CVI Programming Environment Measurement Studio or VI Logger Driver Software ZN Personal NI DAQ o 4 p Computer or ardware Workstation Figure 1 1 The Relationship Among the Programming Environment NI DAQ and the Hardware To download a free copy of the most recent version of NI DAQ click Download Software at ni
77. ge output of AO channel 1 AOGND Analog Output Ground The AO voltages are referenced to this node DGND Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply DIO lt 0 7 gt DGND Input Output Digital I O Signals DIO6 and 7 can control the up down signal of general purpose counters 0 and 1 respectively 5V DGND Output 5 VDC Source These pins are fused for up to 1 A of 5 V supply The fuse is self resetting SCANCLK DGND Output Scan Clock This pin pulses once for each A D conversion when enabled The low to high edge indicates when the input signal can be removed from the input or switched to another signal EXTSTROBE DGND Output External Strobe This output can be toggled under software control to latch signals or trigger events on external devices National Instruments Corporation 4 3 NI 6115 6120 User Manual Chapter 4 Connecting Signals Table 4 2 Signal Descriptions for 1 0 Connector Pins Continued Signal Name Reference Direction Description PFIO TRIG1 DGND Input PFI0 Trigger 1 As an input this is either a PFI or the Output source for the hardware analog trigger PFI signals are explained in the Connecting Timing Signals section later in this chapter The hardware analog trigger is explained in the Analog
78. ground referenced 4 8 waveform generation timing connections UISOURCE signal 4 31 UPDATE signal 4 30 WFTRIG signal 4 29 working voltage range 4 13 SISOURCE signal 4 27 RTSI bus signal connections figure 3 13 software drivers C 1 software installation 2 1 software programmable gain input range and measurement precision table 3 4 overview 3 3 specifications analog input DC transfer characteristics A 2 dynamic characteristics A 4 input characteristics A 1 stability A 11 analog output DC transfer characteristics A 12 dynamic characteristics A 14 output characteristics A 12 stability A 14 voltage output A 13 ni com bus interface A 17 digital I O A 15 electromagnetic compatibility A 18 environmental A 17 physical A 17 power requirements A 17 RTSI trigger lines A 17 safety A 18 timing I O A 15 triggers analog trigger A 16 digital trigger A 17 stability specifications analog input A 11 analog output A 14 STARTSCAN signal See also PFI7 STARTSCAN signal input timing figure 4 24 output timing figure 4 25 RTSI bus signal connections figure 3 13 signal routing figure 3 11 timing connections 4 24 typical posttriggered acquisition figure 4 21 typical pretriggered acquisition figure 4 21 using the SISOURCE signal 4 27 support technical C 1 system integration services C 1 T technical support C 1 telephone technical support C 2 timebase clocks 3 12 timing conn
79. gure 4 5 Differential Input Connections on the NI 6120 for Nonreferenced Signals Figures 4 4 and 4 5 show a bias resistor connected between ACHO and the floating signal source ground This resistor provides a return path for the 200 pA bias current A value of 10 KQ to 100 KQ is usually sufficient If you do not use the resistor and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA and the PGIA saturates causing erroneous readings You must reference the source to the respective channel ground Common mode rejection might be improved by using another bias resistor from the ACHO input to ACHOGND This connection gives a slight measurement error due to the voltage divider formed with the output impedance of the floating source but it also gives a more balanced input for better common mode rejection Common Mode Signal Rejection Considerations NI 6115 6120 User Manual Figures 4 2 and 4 3 show connections for signal sources that are already referenced to some ground point with respect to the NI 6115 6120 In theory the PGIA can reject any voltage caused by ground potential differences between the signal source and the device In addition with pseudodifferential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the device 4 12 ni com Chapter 4 Connecting Signals Like any amplifier the common mode rejection rati
80. h the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense Canadian Department of Communications This Class A digital apparatus meets all requirements of the Canadian Interference Causing Equipment Regulations Cet appareil num rique de la classe A respecte toutes les exigences du R glement sur le mat riel brouilleur du Canada Class B Federal Communications Commission This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures e Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver
81. he EEPROM NI DAQ determines when this is necessary and does it automatically In the EEPROM there is a user modifiable calibration area in addition to the permanent factory calibration area Hence you can load the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed National Instruments Corporation 5 1 NI 6115 6120 User Manual Chapter 5 Calibration This method of calibration is not very accurate because it does not take into account the fact that the device measurement and output voltage errors can vary with time and temperature It is better to self calibrate when the device is installed in the environment in which it is used Self Calibration The NI 6115 6120 can measure and correct for almost all of its calibration related errors without any external signal connections NI DAQ software provides a self calibration method This self calibration process which generally takes two to five minutes is the preferred method of assuring accuracy in your application Initiate self calibration to minimize the effects of any offset and gain drifts particularly those caused by warming Immediately after self calibration the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference This error is addressed by external calibration which is discussed in the following section If you are interested prima
82. ice configuration See configuration DGND signal description table 4 3 digital I O signal connections 4 15 power connections 4 18 National Instruments Corporation 1 3 Index diagnostic resources C 1 digital I O See also DGND signal DIO lt 0 7 gt signal correlated clock signal driving DI and DO signals figure 4 17 description 3 10 falling edge RTSI clock signal driving DIO signal figure 4 18 rising edge AO update signal driving DIO signal figure 4 17 signals for clock source 4 16 questions about B 5 signal connections 4 15 specifications A 15 digital trigger overview 3 8 specifications A 17 DIO lt 0 7 gt signal description table 4 3 digital I O signal connections 4 15 signal summary table 4 6 documentation about this manual xi conventions used in manual xi National Instruments documentation xii online library C 1 related documentation xiii drivers instrument C 1 software C 1 E EEPROM storage of calibration constants 5 1 electromagnetic compatibility specifications A 18 environmental noise avoiding 4 39 environmental specifications A 17 equipment optional 1 6 example code C 1 NI 6115 6120 User Manual Index external calibration 5 2 EXTSTROBE signal description table 4 3 signal summary table 4 6 timing connections 4 29 F field wiring considerations 4 39 floating signal sources description 4 7 signal connections 4 11 FREQ_OUT signal descri
83. ing The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates GPCTRO_SOURCE unless you select some external source GPCTRO_GATE Signal Any PFI pin can receive as an input the GPCTRO_GATE signal which is available as an output on the PFI9 GPCTRO_GATE pin As an input GPCTRO_GATE is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of applications to perform actions such as starting and stopping the counter generating interrupts and saving the counter contents As an output GPCTRO_GATE reflects the actual gate signal connected to general purpose counter 0 even if another PFI is externally generating the gate This output is set to high impedance at startup National Instruments Corporation 4 33 NI 6115 6120 User Manual Chapter 4 Connecting Signals Figure 4 31 shows the timing requirements for GPCTRO_GATE Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 31 GPCTRO_GATE Signal Timing in Edge Detection Mode GPCTRO_OUT Signal This signal is available as an output on the GPCTRO_OUT pin The GPCTRO_OUT signal reflects the terminal count TC of general purpose counter 0 You have two software
84. installed Refer to the Declaration of Conformity DoC for this product for any additional regulatory compliance information To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Select the appropriate product family followed by the product and a link to the DoC in Adobe Acrobat format appears Click the Acrobat icon to download or read the DoC NI 6115 6120 User Manual A 18 ni com Common Questions This appendix contains a list of commonly asked questions and their answers relating to usage and special features of the NI 6115 6120 General Information What is the NI 6115 6120 The NI 6115 6120 is a switchless and jumperless enhanced MIO device that uses the DAQ STC for timing What is the DAQ STC The DAQ STC is the system timing control application specific integrated circuit ASIC designed by NI and is the backbone of the NI 6115 6120 device The DAQ STC contains seven 24 bit counters and three 16 bit counters The counters are divided into the following three groups e Al two 24 bit two 16 bit counters e AO three 24 bit one 16 bit counters e General purpose counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 us With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme i
85. ion includes setting the device base memory address and interrupt channel The NI PXI 6115 6120 is fully compatible with the industry standard PXT Specification Revision 2 0 This allows the PXI CompactPCI system to automatically perform all bus related configurations with no user interaction Bus related configuration includes setting the device base memory address and interrupt channel Data acquisition related configuration which you must perform includes such settings as analog input coupling and range and others You can modify these settings using NI DAQ or application level software such as LabVIEW and Measurement Studio To configure the device in Measurement amp Automation Explorer MAX refer to either the DAQ Quick Start Guide or to the NI DAQ User Manual for PC Compatibles at ni com manuals For operating system specific installation and troubleshooting instructions refer to ni com support daq National Instruments Corporation 2 3 NI 6115 6120 User Manual Hardware Overview This chapter presents an overview of the hardware functions on the NI 6115 6120 Figures 3 1 and 3 2 provide block diagrams for the NI 6115 and NI 6120 respectively
86. ipment 1 6 NI 6115 6120 User Manual P PFIO TRIGI signal See also TRIG1 signal analog triggering 3 5 description table 4 4 signal summary table 4 6 PFI1 TRIG2 signal See also TRIG2 signal description table 4 4 signal summary table 4 6 PFI2 CONVERT signal See also CONVERT signal description table 4 4 signal summary table 4 6 PFI3 GPCTR1_SOURCE signal See also GPCTR1_SOURCE signal description table 4 4 signal summary table 4 7 PFI4 GPCTR1_GATE signal See also GPCTR1_GATE signal description table 4 4 signal summary table 4 7 PFI5 UPDATE signal See also UPDATE signal description table 4 4 signal summary table 4 7 PFI6 WFTRIG signal See also WFTRIG signal description table 4 4 signal summary table 4 7 PFI7 STARTSCAN signal See also STARTSCAN signal description table 4 4 signal summary table 4 7 PFI8 GPCTRO_ SOURCE signal See also GPCTRO_SOURCE signal description table 4 5 signal summary table 4 7 ni com PFI9 GPCTRO_GATE signal See also GPCTRO_GATE signal description table 4 5 signal summary table 4 7 PFIs programmable function inputs questions about B 5 signal name equivalencies table B 5 signal routing 3 10 timing connections 4 20 phase locked loop circuit block diagram 3 10 description 3 9 phone technical support C 2 physical specifications A 17 pin assignments T O connector figure 4 2 PXI 6115 6120 J2 pi
87. issimilar metals whose junction produces a small voltage as a function of the temperature an offset delayed pulse the offset is tnanoseconds from the falling edge of the CONVERT signal output delay time period of a pulse train trigger signal source clock period source pulse width transistor transistor logic pulse width update interval update interval counter clock signal update signal G 11 NI 6115 6120 User Manual Glossary WFTRIG NI 6115 6120 User Manual volts collector common voltage power supply voltage common mode noise and ground potential voltage controlled crystal oscillator volts direct current virtual instrument 1 a combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a LabVIEW software module VI which consists of a front panel user interface and a block diagram program volts in measured voltage volts output high volts output low volts out volts root mean square ground referenced signal source waveform generation trigger signal G 12 ni com Index Numerics 5 V signal description table 4 3 incorrect connections caution 4 15 self resetting fuse 4 18 B 2 A above high level analog triggering mode 3 7 AC input coupling 3 4 ACH lt 0 3 gt signal analog input signal connections 4 8 description table 4 3 signal summary table 4 5 ACH lt 0 3 gt signal an
88. ld you connect these 5 V power pins directly to analog or digital ground or to any other voltage source on the NI 6115 6120 or any other device Doing so can damage the NI 6115 6120 and the computer NI is not liable for damage resulting from such connections Connecting Timing Signals A Caution Exceeding the maximum input voltage ratings which are listed in Table 4 3 can damage the NI 6115 6120 and the computer NI is not liable for any damage resulting from such signal connections NI 6115 6120 User Manual All external control over the timing of the NI 6115 6120 is routed through the 10 PFIs labeled PFIO through PFI9 These signals are explained in detail in the Programmable Function Input Connections section These PFIs are bidirectional as outputs they are not programmable and reflect the state of many DAQ waveform generation and general purpose timing signals There are five other dedicated outputs for the remainder of the timing signals As inputs the PFI signals are programmable and can control DAQ waveform generation and general purpose timing signals 4 18 ni com Chapter 4 Connecting Signals The DAQ signals are explained in the DAQ Timing Connections section later in this chapter The Waveform Generation Timing Connections section later in this chapter explains the waveform generation signals and the General Purpose Timing Signal Connections section later in this chapter explains the general purpose timing signals A
89. ll digital timing connections are referenced to DGND This reference is demonstrated in Figure 4 11 which shows how to connect an external TRIG1 source and an external STARTSCAN source to two PFI pins on the NI 6115 6120 PFIO TRIG1 PFI7 STARTSCAN TRIG1 STARTSCAN Source Source DGND 1 0 Connector NI 6115 6120 Figure 4 11 Timing 1 0 Connections National Instruments Corporation 4 19 NI 6115 6120 User Manual Chapter 4 Connecting Signals Programmable Function Input Connections You can externally control 13 internal timing signals from the PFI pins The source for each of these signals is software selectable from any PFI when you want external control This flexible routing scheme reduces the need to change the physical wiring to the device I O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the STARTSCAN signal as an output on the I O connector software can turn on the output driver for the PFI7 STARTSCAN pin Be careful not to drive a PFI signal externally when it is configured as an output As an input each PFI can be individually configured for edge or level detection and for polarity selection as well You can use the polarity selection for any of the timing signals but the edg
90. lt ee ee 81 5 THD N dBc 81 0 80 5 80 0 T T T T T T T TTT T T T T T T hat 1 10 100 Frequency kHz Figure A 4 NI 6120 High Voltage THD N National Instruments Corporation A 9 NI 6115 6120 User Manual Appendix Specifications With Filters Full Scale Input for Range of 1 V 71 6 70 4 69 2 O THD N dBc O O 65 6 64 4 63 2 62 T T T T T T T T T T T T T T T T T 10 100 1000 Frequency kHz Figure A 5 NI 6115 THD N with Filters A 10 ni com NI 6115 6120 User Manual Appendix Specifications 85 84 83 82 81 80 79 THD N dBc 78 77 76 75 With Filters Full Scale Input for Range of 1 V 10 100 Frequency kHz Figure A 6 NI 6120 THD N with Filters Stability Recommended warm up time 15 min Offset temperature coefficient Pregain NT GIS erased sun 12 uV C NIOLO rereongan 1 5 uV C Postgain NT GS eppes 64 uV C NT6120 ann eds 2 1 LSB C Gain temperature coefficient N GILS Essen en ets Asie 21 3 ppm C NEGIZ O iani erea 22 2 ppm C National Instruments Corporation A 11 NI 6115 6120 User Manual Appendix Specifications Analog Output NI 6115 6120 User Manual Onboard calibration reference Level ss sets nant 5 000 V 2 5 mV actual v
91. me The PLL circuitry consists of a voltage controlled crystal oscillator VCXO with a tuning range of 50 ppm The VCXO generates the 60 MHz master clock used onboard the NI PXI 6115 6120 The PLL locks to the 10 MHz oscillator line on the PXI backplane bus A phase comparator running at 1 MHz compares the PXI Bus and VCXO clock The loop filter then processes the error signal and outputs a control voltage for the VCXO Figure 3 10 illustrates the block diagram for the NI PXI 6115 6120 8 Note This feature is not available on the NI PCI 6115 6120 The PLL circuit is automatically enabled when the NI 6115 6120 is powered up No configuration steps are required in order to utilize PLL synchronization National Instruments Corporation 3 9 NI 6115 6120 User Manual Chapter 3 Hardware Overview 10 MHz Phase Comp 60 MHz out synched to 10 MHZ Div 10 Lod backplane clock Eme M gt VOXO gt ilter Div 60 t Figure 3 10 PLL Block Diagram Correlated Digital 1 0 Timing Signal The NI 6115 6120 contains eight lines of DIO for general purpose use You can software configure groups of individual lines for either input or output The NI 6115 6120 includes a FIFO for buffered operation This operation allows you to read write an array of data using either an internal or external clock source at a maximum rate of 10 MHz In addition you can correlate DIO and AI AO
92. minimum Figure 4 34 GPCTR1_GATE Signal Timing in Edge Detection Mode GPCTR1_OUT Signal This signal is available only as an output on the GPCTR1_OUT pin The GPCTR1_OUT signal monitors the TC device general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to high impedance at startup 4 36 ni com Chapter 4 Connecting Signals Figure 4 35 shows the timing requirements for GPCTR1_OUT TC GPCTR1_SOURCE GPCTR1_OUT Pulse on TC Toggle output on TC GPCTR1_OUT Figure 4 35 GPCTR1_OUT Signal Timing GPCTR1_UP_DOWN Signal This signal can be received as an input on the DIO7 pin and is not available as an output on the I O connector General purpose counter counts down when this pin is at a logic low and counts up at a logic high This input can be disabled so that software can control the up down functionality and leave the DIO7 pin free for general use Figure 4 36 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals lt j tsc lt tsp gt t tsp Vv i i i i SOURCE M NT Ce ae Vit y i tgu ME i tin GATE Vit lt tow gt tout gt V i OUT i VoL Source Clock Period tsc 50 ns minimum Source
93. n assignments table 1 3 PLL See phase locked loop circuit polarity See input polarity and range posttriggered data acquisition 4 20 power connections 5 V power pins 4 18 B 2 incorrect connections caution 4 18 power on states of PFI and DIO lines B 6 self resetting fuse 4 18 B 2 power requirement specifications A 17 power on states of PFI and DIO lines B 6 pretriggered data acquisition 4 21 professional services C 1 programmable function inputs PFIs See PFIs programmable function inputs programming examples C 1 pseudodifferential signal connections definition 4 8 ground referenced signals figure 4 9 PXI PXI 6115 6120 J2 pin assignments table 1 3 using with CompactPCI 1 2 National Instruments Corporation 1 7 Index Q questions and answers analog input and output B 3 general information B 1 installation and configuration B 2 timing and digital I O B 5 R Real Time System Integration See RTSI related documentation xiii requirements for getting started 1 3 RTSI bus signal connections figure 3 13 clocks correlating DIO signals 4 16 description 3 12 overview 1 1 triggers description 3 12 specifications A 17 S safety information 1 8 safety specifications A 18 sampling rate maximum B 1 minimum B 3 scan counter typical posttriggered acquisition figure 4 21 typical pretriggered acquisition 4 21 SCANCLK signal description table 4 3 signal summary table 4
94. nal Instruments E Series devices decibel the unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log10 V1 V2 for signals in volts direct current digital ground signal digital input differential mode an analog input mode consisting of two terminals both of which are isolated from computer ground whose difference is measured digital input output dual inline package the addition of Gaussian noise to an analog input signal for the purpose of increasing the resolution of a measurement when using averaging direct memory access a method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something else the fastest method of transferring data to from computer memory differential nonlinearity a measure in least significant bit of the worst case deviation of code widths from their ideal value of 1 LSB digital output electrically erasable programmable read only memory ROM that can be erased with an electrical signal and reprogrammed effective number of bits G 4 ni com ESD EXTSTROBE FIFO floating signal sources FPGA FREQ_OUT G gain GATE GPCTR GPCTRO_GATE GPCTRO_ OUT GPCTRO_SOURCE GPCTRO_UP_DOWN GPCTR1_GATE GPCTR1_OUT GPCTR1_SOURCE National Instruments Corporation Glossary electrostatic discharge external strobe signal farad a measurement unit of capacitance first in first
95. nconductive pollution occurs that becomes conductive due to condensation You must insulate signal connections for the maximum voltage for which the product is rated Do not exceed the maximum ratings for the product Do not install wiring while the product is live with electrical signals Do not remove or add connector blocks when power is connected to the system Avoid contact between your body and the connector block signal when hot swapping modules Remove power from signal lines before connecting them to or disconnecting them from the product 1 8 ni com Chapter 1 Introduction Operate the product at or below the installation category marked on the hardware label Measurement circuits are subjected to working voltages and transient stresses overvoltage from the circuit to which they are connected during measurement or test Installation categories establish standard impulse withstand voltage levels that commonly occur in electrical distribution systems The following is a description of installation categories e Installation Category I is for measurements performed on circuits not directly connected to the electrical distribution system referred to as MAINS voltage This category is for measurements of voltages from specially protected secondary circuits Such voltage measurements include signal levels special equipment limited energy parts of equipment circuits powered by regulated low voltage sources and electronics e Inst
96. ning of the next scan and conversely if conversions are being gated off AIGATE does not gate them back on until the beginning of the next scan SISOURCE Signal Any PFI pin can receive as an input the SISOURCE signal which is not available as an output on the I O connector The onboard scan interval counter SI uses SISOURCE as a clock to time the generation of the STARTSCAN signal You must configure the PFI pin you select as the source for SISOURCE in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation National Instruments Corporation 4 27 NI 6115 6120 User Manual Chapter 4 Connecting Signals Either the 20 MHz or 100 kHz internal timebase generates SISOURCE unless you select some external source Figure 4 22 shows the timing requirements for SISOURCE tp 50 ns minimum ty 23 ns minimum Figure 4 22 SISOURCE Signal Timing SCANCLK Signal SCANCLK is an output only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A D conversion begins The polarity of this output is software selectable but is typically configured so that a low to high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and
97. noise nonreferenced signal sources Nyquist frequency OUT PCI pd PFI PFIO TRIG1 PFI1 TRIG2 NI 6115 6120 User Manual not connected signal National Instruments National Instruments driver software for DAQ hardware an undesirable electrical signal from external sources such as the AC power line motors generators transformers fluorescent lights soldering irons CRT displays computers electrical storms welders radio transmitters and internal sources such as semiconductors resistors and capacitors noise corrupts signals you are trying to send or receive signal sources including batteries transformers or thermocouples with voltage signals that are not connected to an absolute reference or system ground also called nonreferenced signal sources the maximum signal frequency that a sampling system can accurately represent in frequency spectrum measurement which is half the sampling frequency output pin a counter output pin where the counter can generate various TTL pulse waveforms Peripheral Component Interconnect a high performance expansion bus architecture originally developed by Intel to replace ISA and EISA is achieving widespread acceptance as a standard for PCs and work stations and offers a theoretical maximum transfer rate of 132 Mbytes s pull down programmable function input PFIO0 trigger 1 PFIl trigger 2 G 8 ni com PFI2 CONVERT PFI3 GPCTR1_SOURCE PFI4 GPCTRI_GATE PFIS UPDATE
98. ns and the acquisition stops This mode acquires data both before and after receiving TRIG2 As an output TRIG reflects the posttrigger in a pretriggered DAQ sequence even if another PFI is externally triggering the acquisition TRIG is not used in posttriggered data acquisition The output is an active high pulse with a pulse width of 25 to 50 ns This output is set to high impedance at startup Figures 4 16 and 4 17 show the timing requirements for TRIG2 Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 16 TRIG2 Input Signal Timing i tw 25 50 ns i Figure 4 17 TRIG2 Output Signal Timing National Instruments Corporation 4 23 NI 6115 6120 User Manual Chapter 4 Connecting Signals NI 6115 6120 User Manual STARTSCAN Signal Any PFI pin can receive as an input the STARTSCAN signal which is available as an output on the PFI7 STARTSCAN pin Refer to Figures 4 18 and 4 19 for the relationship of STARTSCAN to the DAQ sequence As an input STARTSCAN is configured in the edge detection mode You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge The selected edge of STARTSCAN initiates a scan The sample interval counter starts if you select internally triggered CONVERT As an output STARTSCAN reflects the actual start pulse that initiates a scan even if another PFI is e
99. o CMRR of the PGIA is limited at high frequency This limitation has been compensated for in the design of the NI 6115 6120 by using a common mode choke on each channel NI6115 The purpose of the 10 nF capacitance on the ACH lt 0 3 gt connection of the NI 6115 is to provide an impedance for this choke to work against at high frequency thus improving the high frequency CMRR Depending on your application and the type of common noise at your source further common noise rejection might be gained by placing a 0 1 UF ceramic bypass capacitor between ACH and ACHOGND Working Voltage Range The PGIA operates normally by amplifying signals of interest while rejecting common mode signals as long as the following three conditions are met 1 The common mode voltage V m which is equivalent to subtracting ACH lt 0 3 gt GND from ACH lt 0 3 gt and which is shown in Figure 4 2 must be less than 2 5 V This V m is a constant for all range selections The signal voltage V which is equivalent to subtracting ACH lt 0 3 gt from ACH lt 0 3 gt and which is shown in Figure 4 2 must be less than or equal to the range selection of the given channel If V is greater than the range selected the signal clips and information is lost The total working voltage of the positive input which can be thought of as Vin V or simply as subtracting ACH lt 0 3 gt GND from ACH lt 0 3 gt must be less than 11 V for ranges lt 10 V
100. of one source clock period with respect to unsynchronized gating sources The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the NI 6115 6120 Figure 4 36 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal FREQ_OUT Signal This signal is available only as an output on the FREQ OUT pin The frequency generator for the NI 6115 6120 outputs the FREQ OUT pin The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The output polarity is software selectable This output is set to high impedance at startup NI 6115 6120 User Manual 4 38 ni com Chapter 4 Connecting Signals Field Wiring Considerations Environmental noise can seriously affect the measurement accuracy of the NI 6115 6120 if you do not take proper care when running signal wires between signal sources and the device The following recommendations apply mainly to AI signal routing although they also apply to signal routing in general Minimize noise pickup and maximize measurement accuracy by taking the following precautions e Use differential AI connections to reject common mode noise e Use individually shi
101. olution uV Temp at Full Full 24 Offset Single Drift Scale Single Scale Hours 1Year uV 23 Pt Averaged C mV Pt Averaged 50 0 157 0 159 7 799 2 5 621 9 503 5 0 0106 86 92 6 629 9 663 0 20 0 139 0 141 3 120 7 2 248 7 201 4 0 0106 31 11 2652 0 265 2 10 0 033 0 034 1 561 1 1 124 4 100 7 0 0006 4 94 1326 0 132 6 5 0 036 0 37 781 4 562 2 50 4 0 0006 2 61 663 0 66 3 2 0 039 0 041 344 0 224 9 20 1 0 0006 1 15 265 2 26 5 1 0 077 0 079 264 4 150 0 13 7 0 0006 1 05 180 8 18 1 0 5 0 100 0 102 178 8 144 3 13 7 0 0006 0 69 180 8 18 1 0 2 0 123 0 125 90 8 112 8 11 0 0 0006 0 35 144 7 14 5 Accuracies are valid for measurements following an internal calibration Averaged numbers assume dithering and averaging of 100 single channel readings Measurement accuracies are listed for operational temperatures within 1 C of internal calibration temperature and 10 C of external or factory calibration temperature 2 The offset might degrade by 3 LSB with filter enabled 3 The offset might degrade by 1 LSB when sampling above 500 kS s National Instruments Corporation A 3 NI 6115 6120 User Manual Appendix Specifications Dynamic Characteristics Interchannel skew cccceceseeeeeeeeeeees Analog filters Number Type NU GLIS Rss mnt atic NT 6120 rss NEGOTII Essen rte ts NDOO re fs anne Frequency Crosstalk NI 6115 6120 User Manual NV GLS tn NTOL20 Sete is A 4 3 pole Bess
102. ommon mode input range Ground Referenced Signal Sources A ground referenced signal source is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the NI 6115 6120 assuming that the computer is plugged into the same power system Non isolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improperly measured this difference may appear as an error in the measurement The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal Connecting Analog Input Signals NI 6115 6120 User Manual The NI 6115 6120 channels are configured as pseudodifferential inputs The input signal of each channel ACH lt 0 3 gt is tied to the positive input of its PGIA and each reference signal ACH lt 0 3 gt is tied to the negative input of its PGIA The inputs are differential only in the sense that ground loops are broken The reference signal ACH lt 0 3 gt is not intended to carry signals of interest but only to provide a DC reference point for ACH lt 0 3 gt that may be different from ground
103. ons Figure 4 7 shows signal connections for three typical DIO applications 5V Le LED 1x MW DIO lt 4 7 gt L pd i TTL Signal om DIO lt 0 3 gt 5V MW gt Switch Y DGND 1 0 Connector NI 6115 6120 Figure 4 7 Digital 1 0 Connections National Instruments Corporation 4 15 NI 6115 6120 User Manual Chapter 4 Connecting Signals Figure 4 7 shows DIO lt 0 3 gt configured for digital input and DIO lt 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the switch state shown in Figure 4 7 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 4 7 Correlating DIO Signal Connections You can correlate DIO and AI AO operations to the same clock on the NI 6115 6120 You can use any of the following signals as the clock source e AI Scan Start e AO Update e GPCTR e RTSI lt 0 5 gt e External Clock 3 Notes To use either of the GPCTR signals or the external clock to clock DIO operations you must use one RTSI lt 0 5 gt pin To use an external clock for correlated DIO the clock must have input on the Counter 0 output pin GPCTRO_OUT In this case be sure that this counter is not used in any other operation The following timing diagrams illustrate the use of these signals a
104. ons A 16 antialiasing filters description 3 8 effects of hardware and software filtering figure 3 9 enabling B 3 NI 6115 6120 User Manual Index AOGND signal analog output signal connections 4 14 description table 4 3 avoiding false triggering note 3 6 base address for NI 6115 6120 device B 2 below low level analog triggering mode 3 6 bipolar input 3 3 block diagrams bus NI 6115 6120 User Manual analog trigger 3 6 NI 6115 block diagram 3 1 NI 6120 block diagram 3 2 phase locked loop circuit figure 3 10 CompactPCI master device slot support note 2 2 using PXI with CompactPCI 1 2 interface specifications A 17 PCI overview 1 1 PCI Local Bus Specification 1 1 2 3 PXI 1 1 master device slot support note 2 2 NI PXI 6115 6120 J2 pin assignments table 1 3 PXI Specification Revision 2 0 1 2 2 3 RTSI device and RTSI clocks 3 12 overview 1 1 PCI RTSI Bus Signal Connection figure 3 13 RTSI triggers 3 12 timing signal routing 3 10 using PXI with CompactPCI 1 2 C cables See also I O connectors custom cabling 1 6 field wiring considerations 4 39 optional equipment 1 6 calibration external calibration 5 2 loading calibration constants 5 1 self calibration 5 2 calibration certificate C 2 clocks correlating DIO signals 4 16 device and RTSI clocks 3 12 commonly asked questions See questions and answers common mode signal rejection 4 12 CompactPCI using
105. ost of our products are FCC Class A The FCC rules have restrictions regarding the locations where FCC Class A products can be operated FCC Class B products display either a FCC ID code starting with the letters EXN Trade Name Model Number or the FCC Class B compliance mark that appears as shown here on the right FE Tested to Comply with FCC Standards Consult the FCC Web site at http www fcc gov for more information FCC DOC Warnings This equipment generates and uses radio frequency energy and if not installed and used in strict accordance with the instructions in this manual and the CE Marking Declaration of Conformity may cause interference to radio and television reception Classification requirements are the same for the Federal Communications Commission FCC and the Canadian Department of Communications DOC FOR HOME OR OFFICE USE Changes or modifications not expressly approved by National Instruments could void the user s authority to operate the equipment under the FCC Rules Class A Federal Communications Commission This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance wit
106. primary group is being updated PFI6 WFTRIG DGND Input PFI6 Waveform Trigger As an input this is a PFI Output As an output this is the WFTRIG signal In timed AO sequences a low to high transition indicates the initiation of the waveform generation PFI7 STARTSCAN DGND Input PFI7 Start of Scan As an input this is a PFI As an Output output this is the STARTSCAN signal This pin pulses once at the start of each AI scan in the interval scan A low to high transition indicates the start of the scan NI 6115 6120 User Manual 4 4 ni com Chapter 4 Connecting Signals Table 4 2 Signal Descriptions for I O Connector Pins Continued Signal Name Reference Direction Description PFI8 GPCTRO_SOURCE DGND Input PFI8 Counter 0 Source As an input this is a PFI As Output an output this is the GPCTRO_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 PFI9 GPCTRO_GATE DGND Input PFI9 Counter 0 Gate As an input this is a PFI As an Output output this is the GPCTRO_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 0 GPCTRO_OUT DGND Output Counter 0 Output This output is from the general purpose counter 0 output FREQ_OUT DGND Output Frequency Output This output is from the frequency generator output The GPCTRO_OUT acts as an input when using external clock mode with correlated DIO Table 4 3 Analog 1
107. ption table 4 5 general purpose timing connections 4 38 signal summary table 4 7 frequently asked questions See questions and answers fuse self resetting 4 18 B 2 G general purpose timing signal connections FREQ_OUT signal 4 38 GPCTRO_GATE signal 4 33 GPCTRO_OUT signal 4 34 GPCTRO_SOURCE signal 4 32 GPCTRO_UP_DOWN signal 4 35 GPCTR1_GATE signal 4 36 GPCTR1_OUT signal 4 36 GPCTR1_SOURCE signal 4 35 GPCTR1_UP_DOWN signal 4 37 questions about B 5 getting started equipment 1 3 glitches questions about B 4 GPCTRO_GATE signal See also PFI9 GPCTRO_GATE signal general purpose counter timing summary figure 4 37 general purpose timing connections 4 33 NI 6115 6120 User Manual l 4 RTSI bus signal connections figure 3 13 GPCTRO_OUT signal description table 4 5 general purpose counter timing summary figure 4 37 general purpose timing connections 4 34 RTSI bus signal connections figure 3 13 signal summary table 4 7 GPCTRO_SOURCE signal See also PFI8 GPCTRO_SOURCE signal general purpose counter timing summary figure 4 37 general purpose timing connections 4 32 GPCTRO_OUT signal timing figure 4 34 RTSI bus signal connections figure 3 13 GPCTRO_UP_DOWN signal digital I O lines 3 10 general purpose timing connections 4 35 GPCTR1_GATE signal See also PF1I4 GPCTR1_GATE signal general purpose counter timing summary figure 4 37 general purpose timing connections 4 36 GPCTR
108. r Manual Power off and unplug the computer Remove the cover Make sure there are no lighted LEDs on the motherboard If any are lit wait until they go out before continuing the installation Remove the expansion slot cover on the back panel of the computer Ground yourself using a grounding strap or by touching a grounded object Follow the ESD protection precautions described in the Unpacking section of Chapter 1 Introduction Insert the NI PCI 6115 6120 into a PCI system slot Gently rock the device to ease it into place It may be a tight fit but do not force the device into place Screw the mounting bracket of the device to the back panel rail of the computer 2 2 ni com Chapter 2 Installing and Configuring the NI 6115 6120 8 Replace the cover 9 Plug in and power on the computer The NI PCI 6115 6120 is now installed You are now ready to configure the hardware and software Configuring the Device Because of the NI standard architecture for data acquisition and the PCI bus specification the NI 6115 6120 is completely software configurable Two types of configuration are performed on the NI 6115 6120 bus related and data acquisition related configuration The NI PCI 6115 6120 is fully compatible with the industry standard PCI Local Bus Specification Revision 2 2 This compatibility allows the PCI system to automatically perform all bus related configurations with no user interaction Bus related configurat
109. rily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration NI 6115 6120 User Manual The NI 6115 6120 has an onboard calibration reference to ensure the accuracy of self calibration Its specifications are listed in Appendix A Specifications The reference voltage is measured at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applications but if you are using the device at an extreme temperature or if the onboard reference has not been measured for a year or more you may wish to externally calibrate the device An external calibration refers to calibrating the device with a known external reference rather than relying on the onboard reference Redetermining the value of the onboard reference is part of this process and the results can be saved in the EEPROM so you should not have to perform an external calibration very often You can externally calibrate the device by calling the NI DAQ calibration function 5 2 ni com Chapter 5 Calibration To externally calibrate your device be sure to use a very accurate external reference The reference should be several times more accurate than the device itself For a detailed calibration procedure for the NI 6115 6120 click Manual Calibration Procedures at ni com calibration National Instruments Corporation 5 3 NI 6115 6120 User Manual
110. rogramming it is a stand alone configuration based software program Using LabVIEW LabWindows CVI Measurement Studio or VI Logger greatly reduces the development time for your data acquisition and control application Optional Equipment NI offers a variety of products to use with the NI 6115 6120 including cables connector blocks and other accessories as follows e Shielded cables and cable assemblies e Connector blocks shielded 50 and 68 pin screw terminals e RTSI bus cables PCI only e Low channel count signal conditioning modules devices and accessories including conditioning for strain gauges resistance temperature detectors and relays For more specific information about these products refer to the NI catalog at ni com catalog Custom Cabling NI 6115 6120 User Manual NI offers cables and accessories to help you prototype your application or to use if you frequently change device interconnections If you want to develop your own cable however adhere to the following guidelines for best results e For AI signals use shielded twisted pair wires for each AI pair for differential inputs Tie the shield for each signal pair to the ground reference at the source 1 6 ni com Chapter 1 Introduction e Route the analog lines separately from the digital lines e When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise coupling
111. s clock sources You can software configure DIO operations for either rising or falling edge on whichever clock you choose as the source Figure 4 8 shows any clock signal in general driving two separate groups of lines configured for digital input DI and DO The DI operation is using the rising edge of the clock and the DO operation is using its falling edge NI 6115 6120 User Manual 4 16 ni com Chapter 4 Connecting Signals LALA DI lt 7 4 gt Y Figure 4 8 Clock Signal Driving DI and DO Signals Figure 4 9 shows a DIO operation driven by the AO Update signal on its rising edge AO Update 4 A A s CC Figure 4 9 Rising Edge AO Update Signal Driving a DIO Signal National Instruments Corporation 4 17 NI 6115 6120 User Manual Chapter 4 Connecting Signals Figure 4 10 shows a DIO operation driven by an RTSI clock signal on its falling edge RTSI Figure 4 10 Falling Edge RTSI Clock Signal Driving a DIO Signal Power Connections Two pins on the I O connector supply 5 V from the computer power supply using a self resetting fuse The fuse resets automatically within a few seconds after the overcurrent condition is removed These pins are referenced to DGND and can be used to power external digital circuitry The power rating is 4 65 to 5 25 VDC at 1 A A Caution Under no circumstances shou
112. s information concerning its operation and programming The NI 6115 6120 family includes the following devices e NIPCI 6115 e NIPXI 6115 e NIPCI 6120 e NIPXI 6120 The NI 6115 6120 is a high performance multifunction analog digital and timing I O data acquisition DAQ device for PXI and PCI bus computers Supported functions include analog input AI analog output AO digital I O DIO and timing I O TIO Conventions The following conventions appear in this manual lt gt Angle brackets that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example DIO lt 3 0 gt The symbol leads you through nested menu items and dialog box options to a final action The sequence File Page Setup Options directs you to pull down the File menu select the Page Setup item and select Options from the last dialog box The symbol indicates that the following text applies only to a specific product a specific operating system or a specific software version This icon denotes a note which alerts you to important information gt g This icon denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash When this symbol is marked on the product refer to the Safety Information section of Chapter 1 Introduction for precautions to take National Instruments Corporation xi NI 6115 6120 User Manual About
113. s quite flexible and completely software configurable New capabilities such as buffered pulse generation and equivalent time sampling are possible What does the maximum sampling rate mean to me Maximum sampling rate is the fastest you can acquire data on the device and still achieve accurate results The NI 6115 device has a maximum sampling rate of 10 MS s This sampling rate is at 10 MS s regardless if 1 or 4 channels are acquiring data The NI 6120 has a maximum sampling rate of 800 kS s National Instruments Corporation B 1 NI 6115 6120 User Manual Appendix B Common Questions What type of 5 V protection does the NI 6115 6120 have The NI 6115 6120 has 5 V lines equipped with a self resetting 1 A fuse How do I use the NI 6115 6120 with the NI DAQ C APT The NI DAQ User Manual for PC Compatibles describes the general programming flow when using the NI DAQ C API as well as contains example code For a list of functions that support the NI 6115 6120 you can refer to the NI DAQ Function Reference Help You can access this help file by clicking Start Programs National Instruments NI DAQ NI DAQ Help Installing and Configuring the Device NI 6115 6120 User Manual How do you set the base address for the NI 6115 6120 The base address of the NI 6115 6120 is assigned automatically through the PCI bus protocol This assignment is completely transparent to you What jumpers should I be aware of when configuring the
114. t signal resolution Table 3 1 shows the overall input range and precision according to the gain used A Caution The NI 6115 6120 is not designed for input voltages greater than 42 VDC Input voltages greater than 42 VDC can damage the NI 6115 6120 any device connected to it and the host computer Overvoltage can also cause an electric shock hazard for the operator NI is not liable for damage or injury resulting from such misuse National Instruments Corporation 3 3 NI 6115 6120 User Manual Chapter 3 Input Coupling NI 6115 6120 User Manual Hardware Overview Table 3 1 Input Range and Measurement Precision Precision Input Range 6115 12 Bit 6120 16 Bit 50 to 50 V 24 4 mV 1 53 mV 20 to 20 V 9 77 mV 610 uV 10 to 10 V 4 88 mV 305 uV 5 to 5 V 2 44 mV 153 uV 2 to 2 V 977 uV 61 0 uV 1 to 41V 488 LV 30 5 UV 500 to 500 mV 244 UV 15 3 uV 200 to 200 mV 97 7 UV 6 10 UV 1 The value of 1 least significant bit LSB of the ADC that is the voltage increment corresponding to a change of one count in the ADC count 2 Do not exceed 42 VDC maximum Note Refer to Appendix Specifications for absolute maximum ratings Considerations for Selecting Input Ranges The range you select depends on the expected range of the incoming signal A large input range can accommodate a large signal variation but reduces the voltage resolution Choosing a smaller input range improves
115. the NI 6120 for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the device ground shown as Vem in Figures 4 2 and 4 3 4 10 ni com Chapter 4 Connecting Signals Connections for Nonreferenced or Floating Signal Sources Figures 4 4 and 4 5 show how to connect a floating signal source to a channel on the NI 6115 and NI 6120 respectively Common Mode AC Coupling I TACHO Choke Instrumentation Amplifier Floating Signal Source Bias Current Return Paths Bias 7 Resistor see text Measured Voltage Vin 10 kKQ 40 pf for ranges gt 10 V ACHOGND 1 0 Connector ACHO Connections Shown Figure 4 4 Differential Input Connections on the NI 6115 for Nonreferenced Signals National Instruments Corporation 4 11 NI 6115 6120 User Manual Chapter 4 Connecting Signals L CE AC Coupling Instrumentation Floating Z TACHOF 7 i Amplifier Signal RU g i 1 100 pF 1M PGIA ai oe i g Measured Vin Voltage i ACHO A e kA a High Frequency Z Return Common Mode Choke Paths a A 10 kQ 40 pf for ranges gt 10 V esistor see text 50 Q 0 1 uF 1 0 Connector ACHOGND N7 L Fi
116. the voltage resolution but may result in the input signal going out of range For best results match the input range as closely as possible to the expected range of the input signal You can configure the NI 6115 6120 for either AC or DC input coupling on a per channel basis Use AC coupling when the AC signal contains a large DC component If you enable AC coupling you remove the large DC offset for the input amplifier and amplify only the AC component This configuration effectively uses the dynamic range of the ADC The input impedance for the programmable gain instrumentation amplifier PGIA channels is 1 MQ for ranges lt 10 V and 10 kQ for ranges gt 10 V This configuration provides an AC coupled corner frequency of 2 34 Hz for ranges lt 10 V and 234 Hz for ranges gt 10 V 3 4 ni com Chapter 3 Hardware Overview Analog Output The NI 6115 6120 supplies two channels of AO voltage at the I O connector The range is fixed at bipolar 10 V The AO channels on the NI 6115 contain 12 bit DACs that are capable of 4 MS s for one channel or 2 5 MS s for each of two channels The NI 6120 DACs are 16 bit and they have the same AO capabilities as the NI 6115 Refer to Appendix A Specifications for more detailed information about the AO capabilities of the NI 6115 6120 3 Note The AO channels do not have analog or digital filtering hardware and do produce images in the frequency domain related to the update rate The NI 6
117. to a low impedance signal source less than 1 KQ source impedance if you plan to enable this input using software National Instruments Corporation 3 5 NI 6115 6120 User Manual Chapter 3 Hardware Overview ADC gt Digital Data Analog Input PGIA CHO L highValue Trigger ADC DAC Analog 7 Input PGIA CH1 L ADC Analog T Analog Input PGIA Mux Trigger DAQ STC CH2 Z Circuit M ADC Analog zs Input PGIA CH3 AC Couple o He Trigger PFIO TRIG1 lin fe aaa BAC Figure 3 3 Analog Trigger Block Diagram for the NI 6115 6120 In below low level analog triggering mode the trigger is generated when the signal value is less than lowValue as shown in Figure 3 4 HighValue is unused lowValue Trigger Figure 3 4 Below Low Level Analog Triggering Mode In above high level analog triggering mode the trigger is generated when the signal value is greater than highValue as shown in Figure 3 5 LowValue is unused NI 6115 6120 User Manual ni com Chapter 3 Hardware Overview highValue Trigger Figure 3 5 Above High Level Analog Triggering Mode In inside region analog triggering mode the trigger is generated when the signal value is between the low Value and the high Val
118. ts Corporation All rights reserved Important Information Warranty The NI PCI 6115 NI PXI 6115 NI PCI 6120 and NI PXI 6120 devices are warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technic
119. ts Corporation G 1 NI 6115 6120 User Manual Glossary A A AID AC ACH ACHOGND ADC ADE Al AIGATE aliasing ANSI AO AOGND ASIC Bessel filter bipolar NI 6115 6120 User Manual amperes analog to digital alternating current analog input channel signal analog input channel ground signal analog to digital converter an electronic device often an integrated circuit that converts an analog voltage to a digital number application development environment such as LabVIEW LabWindows CVI Measurement Studio Visual Basic C and C analog input analog input gate signal the consequence of sampling that causes signals with frequencies higher than half the sampling frequency to appear as lower frequency components in a frequency spectrum American National Standards Institute analog output analog output ground signal application specific integrated circuit a proprietary semiconductor component designed and manufactured to perform a set of specific functions a filter with a maximally flat response in both magnitude and phase The phase response in the passband which is usually the region of interest is nearly linear Bessel filters reduce nonlinear phase distortion inherent in all IIR filters a signal range that includes both positive and negative values G 2 ni com CalDAC cm CMOS CMRR CompactPCI CONVERT correlated DIO counter timer CTR D D A DAC DACOOUT DACIOUT
120. u PFI7 STARTSCAN DIO Voc 0 5 3 5 at 5 at 0 4 1 5 50 kQ Vcc 0 4 pu PFI8 GPCTRO_SOURCE DIO Voc 0 5 3 5 at 5 at 0 4 1 5 50 kQ Vcc 0 4 pu PFI9 GPCTRO_GATE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ Vcc 0 4 pu GPCTRO_OUT DIO Voc 0 5 3 5 at 5 at 0 4 1 5 50 kQ Vcc 0 4 pu FREQ _OUT DO 3 5 at 5 at 0 4 1 5 50 kQ Vcc 0 4 pu pu pull up pd pull down DO Digital Output The tolerance on the 50 KQ pull up and pull down resistors is very large Actual value may range between 17 and 100 KQ Types of Signal Sources When making signal connections you must first determine whether the signal sources are floating or ground referenced The following sections describe these two types of signals Floating Signal Sources A floating signal source is not connected in any way to the building ground system but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolator outputs and isolation amplifiers An instrument or device that has an isolated output is a floating signal National Instruments Corporation 4 7 NI 6115 6120 User Manual Chapter 4 Connecting Signals source You must tie the ground reference of a floating signal to the NI 6115 6120 AI ground to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the c
121. ue as Figure 3 6 shows highValue lowValue Trigger l l j Figure 3 6 Inside Region Analog Triggering Mode In high hysteresis analog triggering mode the trigger is generated when the signal value is greater than highValue with the hysteresis specified by lowValue as Figure 3 7 shows highValue lowValue Trigger Figure 3 7 High Hysteresis Analog Triggering Mode National Instruments Corporation 3 7 NI 6115 6120 User Manual Chapter 3 Hardware Overview In low hysteresis analog triggering mode the trigger is generated when the signal value is less than low Value with the hysteresis specified by high Value as Figure 3 8 shows tiger Lot U Figure 3 8 Low Hysteresis Analog Triggering Mode The analog trigger circuit generates an internal digital trigger based on the AI signal and the user defined trigger levels This digital trigger can be used by any of the timing sections of the DAQ STC including the AI AO and general purpose counter timer sections For example the AI section can be configured to acquire n scans after the AI signal crosses a specific threshold As another example the AO section can be configured to update its outputs whenever the AI signal crosses a specific threshold Antialiasing Filters NI 6115 6120 User Manual Each AI channel on the NI 6115 6120 is equipped with a programmable
122. und 1 Applies to range lt 10 V impedance refers to ACH lt 0 3 gt 2 Applies to range gt 10 V impedance refers to ACH lt 0 3 gt Table 4 5 Digital 1 0 Signal Summary Signal Impedance Protection Rise Type and Input Volts Source Sink Time Signal Name Direction Output On Off mA at V mA at V ns Bias VCC DO 0 1 Q Short circuit 1A to ground DIO lt 0 7 gt DIO Vcc 0 5 13 at 24 at 0 4 1 1 50 KQ Vcc 0 4 pu SCANCLK DO 3 5 at 5 at 0 4 1 5 50 KQ Vcc 0 4 pu EXTSTROBE DO 3 5 at 5 at 0 4 1 5 50 KQ Vcc 0 4 pu PFIO TRIG1 Al 10 kQ 35 3 5 at 5 at 0 4 1 5 9 kQ DIO Voc 0 5 Vec 0 4 pu and 10 kQ pd PFI1 TRIG2 DIO Vcc 0 5 3 5 at 5 at 0 4 1 5 50 KQ Vcc 0 4 pu PFI2 CONVERT DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 KQ Vcc 0 4 pu NI 6115 6120 User Manual 4 6 ni com Chapter 4 Connecting Signals Table 4 5 Digital 1 0 Signal Summary Continued Signal Impedance Protection Rise Type and Input Volts Source Sink Time Signal Name Direction Output On Off mA at V mA at V ns Bias PFI3 GPCTR1_SOURCE DIO Voc 0 5 3 5 at 5 at 0 4 1 5 50 kQ Vcc 0 4 pu PFI4 GPCTR1_GATE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ Vcc 0 4 pu GPCTR1_OUT DO 3 5 at 5 at 0 4 1 5 50 kQ Vcc 0 4 pu PFIS UPDATE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ Voc 0 4 pu PFI6 WFTRIG DIO Voc 0 5 3 5 at 5 at 0 4 1 5 50 kQ Vcc 0 4 p
123. xternally triggering the starts You have two output options The first is an active high pulse with a pulse width of 25 to 50 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the last conversion in the scan which indicates a scan in progress STARTSCAN is deasserted t after the last conversion in the scan is initiated This output is set to high impedance at startup Figures 4 18 and 4 19 show the timing requirements for STARTSCAN Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 18 STARTSCAN Input Signal Timing 4 24 ni com Chapter 4 Connecting Signals tw 25 50ns a Start of Scan Start Pulse T 7 CONVERT STARTSCAN a l lt gt to 10 ns minimum L to b Scan in Progress Two Conversions per Scan Figure 4 19 STARTSCAN Output Signal Timing The CONVERT pulses are masked off until the device generates STARTSCAN If you are using internally generated conversions the first CONVERT appears when the onboard sample interval counter reaches zero If you select an external CONVERT the first external pulse after STARTSCAN generates a conversion STARTSCAN pulses should be separated by at least one scan period A counter on the NI 6115 6120 internally generates STARTSCAN unless you select some external source This counter is started by the T
124. y be connected to the MAINS for measuring purposes National Instruments Corporation 1 9 NI 6115 6120 User Manual Installing and Configuring the NI 6115 6120 This chapter explains how to install and configure the NI 6115 6120 Installing the Software Before you install the NI 6115 6120 complete the following steps to install the software 1 Install the ADE such as LabVIEW or Measurement Studio according to the instructions on the CD and the release notes 2 Install NI DAQ according to the instructions on the CD and the DAQ Quick Start Guide included with the device When using the DAQ Quick Start Guide refer to the pinout for the NI 6110 6111 which is identical to the pinout for the NI 6115 6120 My Note It is important to install NI DAQ before installing the NI 6115 6120 to ensure that the device is properly detected Installing the Hardware You can install the NI 6115 6120 in any available expansion slot in the computer However to achieve best noise performance leave as much room as possible between the NI 6115 6120 and other devices and hardware The following are general installation instructions so consult the computer user manual or technical reference manual for specific instructions and warnings NIPXI 6115 6120 1 Power off and unplug the computer 2 Choose an unused PXI slot in the system For maximum performance the NI PXI 6115 6120 has an onboard DMA controller that you can use onl
125. y if the device is installed in a slot that supports bus arbitration National Instruments Corporation 2 1 NI 6115 6120 User Manual Chapter 2 Installing and Configuring the NI 6115 6120 or bus master devices NI recommends installing the NI PXI 6115 6120 in such a slot 8 Note The PXI specification requires all slots to support bus master devices but the CompactPCI specification does not If you install in a CompactPCI non master slot you must disable the onboard DMA controller using software Make sure there are no lighted LEDs on the chassis If any are lit wait until they go out before continuing the installation Remove the filler panel for the slot you have chosen Ground yourself using a grounding strap or by touching a grounded object Follow the ESD protection precautions described in the Unpacking section of Chapter 1 Introduction Remove the rubber front panel screw protectors Insert the NI PXI 6115 6120 into a5 V PXI slot Use the injector ejector handle to fully insert the device into the chassis Screw the front panel of the NI PXI 6115 6120 to the front panel mounting rail of the system Visually verify the installation Make sure the device is not touching other devices or components and is fully inserted in the slot 10 Plug in and power on the computer The NI PXI 6115 6120 is now installed You are now ready to configure the hardware and software NIPCI 6115 6120 1 2 3 NI 6115 6120 Use
126. ysically connect the relevant pieces of the system Consult these guides when you are making the connections Related Documentation The following documents contain information you may find helpful National Instruments Corporation DAQ Quick Start Guide located at ni com manuals DAQ STC Technical Reference Manual located at ni com manuals NI Developer Zone tutorial Field Wiring and Noise Considerations for Analog Signals located at ni com zone NI DAQ User Manual for PC Compatibles located at ni com manuals NI DAQ Function Reference Help You can access this help file by clicking Start Programs National Instruments NI DAQ NI DAQ Help PCI Local Bus Specification Revision 2 2 PICMG 2 0 R3 0 CompactPCI Core Specification PXI Specification Revision 2 0 available from www pxisa org xiij NI 6115 6120 User Manual Introduction This chapter describes the NI 6115 6120 lists what you need to get started describes the optional software and optional equipment and explains how to unpack the device About the NI 6115 6120 Thank you for buying an NI 6115 6120 The NI 6115 6120 is a Plug and Play multifunction analog digital and timing I O device for PXI and PCI bus computers The NI 6115 features a 12 bit A D converter ADC per channel with four simultaneously sampling analog inputs and two 12 bit D A converters DACs with voltage outputs The NI 6120 features a 16 bit ADC per input channel and 16 bit

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