Cypress CY7C2561KV18 User's Manual
Contents
1. 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 144M A WPS BWS K NC 288M RPS A A CQ B NC Q9 D9 A NC K BWS A NC NC Q8 C NC NC D10 Vss A NC A Vas NC Q7 D8 D NC D11 Q10 Vss Vss Vss Vss Vss NC NC D7 E NC NC Q11 VDDQ Vss Vss Vss VDDQ NC D6 Q6 F NC Q12 D12 VDDQ Vpp Vss Msn Vppa NC NC Q5 G NC D13 Q13 VDDQ Vpp Vss Vpp Ven NC NC D5 H DOFF VREF VDDQ VDDQ VDD Vss VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ Von Vss VoD Vena NC Q4 D4 K NC NC O14 VDDQ Vpp Vss Vpp Vppa NC D3 Q3 L NC Q15 D15 Vino Vss Vss Vss VDDQ NC NC Q2 M NC NC D16 Vss Vss Vss Vis Vss NC Q1 D2 N NC D17 Q16 Vss A A A Vss NC NC D1 P NC NC Q17 A A QVLD A A NC DO QO R TDO TCK A A A ODT A A A TMS TDI CY7C2565KV18 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 288M A WPS BWS K BWS RPS A NC 144M CO B Q27 Q18 D18 A BWS3 K BWSy A D17 Q17 Q8 c D27 Q28 D19 Vss A NC A Vss D16 Q7 D8 D D28 D20 Q19 Vss Vss Vss Vss Vss Q16 D15 D7 E Q29 D29 Q20 VDDQ Vss Vss Vss Vppa Q15 D6 Q6 F Q30 Q21 D21 Vppa Vpp Vss VDD Vppa D14 Q14 Q5 G D30 D22 Q22 VDDQ Vpp Vss Vpp Vane Q13 D13 D5 H DOFF VREF VDDQ VDDQ VDD Vss VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ Vpp Vss Mise Von D12 Q4 D4 K Q32 D32 Q23 Vppa Vpp Vss Von Vppo Q12 D3 Q3 L Q33 Q24 D24 VDDQ Vss Vss Vss VDDQ D11 Q11 Q2 M D33 Q34 D25 Vss Vss Vss Vss Vss D10 Q1 D2 N D34 D26 Q25 Vss A A A Vss Q10 D9 D1 P Q35 D35 Q26 A2. P ME PRELIMINARY PERFORM Figure 2 TAP Controller State Diagram The state diagram for the TAP controller follows I1 1 TEST LOGIC RESET E 1 0 TEST LOGIC 1 SELECT SELECT py IDLE DR SCAN IR SCAN ETIN Mk NE 1 1 il CAPTURE DR a CAPTURE IR d Y SHIFT DR SHIFT IR 0 y ty 1 sa EXIT1 DR p EXIT1 IR d E PAUSE DR 0 PAUSE IR 0 1 Y 1 0 EXIT2 DR EXIT2 IR y v UPDATE DR UPDATE IR 1 1 0 0 Page 15 of 29 Note Document Number 001 15887 Rev E 13 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Feedback a PRELIVINARY CY7C2561KV18 CY7C2576KV18 S CYPRESS CY7C2563KV18 CY7C2565KV18 PERFORM Figure 3 TAP Controller Block Diagram m0 gt Bypass Register pe 2110 ms Selection i TDI TN Instruction Register Selection m TDO Circuitry Circuitry m 34 30129393 12 1 0 gt Identification Register 108 5 21 0 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range 14 15 16 Parameter Description Test Conditions Min Max Unit Vout Output HIGH Voltage lou 2 0 mA 1 4 V Vou2 Output HIGH Voltage lop 100 uA 1 6 V Voi4 Output LOW Voltage lo 2 0 mA 0 4 V VoL2 Output LOW Voltage lo 100 pA 0 2 V
3. r n ium _ 550 MHz 500 MHz 450 MHz 400 MHz Ben GA MAR BE Eon Min Max Min Max Min Max Min Max UI POWER Vpp Typical to the First Access 26 1 1 1 1 ms tcvc tKHKH K Clock Cycle Time 18184 2 0 84 22 8 4 25 8 4 ns KH tKHKL Input Clock K K HIGH 04 04 04 04 ns tk tk KH Input Clock K K LOW 04 04 04 04 ns tkHKH tkHKH K Clock Rise to K Clock Rise 077 085 0 94 1 06 ns rising edge to rising edge Setup Times tsA tAVKH Address Setup to K Clock Rise 023 025 0 275 04 ns tsc tivkH Control Setup to K Clock Rise RPS WPS 0 23 025 027 5 o4 ns tscppR tivKH Double Data Rate Control Setup to Clock K K 0 18 0 20 022 0 28 ns Rise BWSp BWS4 BWS BWS3 tsp tDVKH Dix Setup to Clock K K Rise 0 18 020 022 028 ns Hold Times tHA tKHAX Address Hold after K Clock Rise 0 23 0 25 0275 04 ns tuc tKHIX Control Hold after K Clock Rise RPS WPS 0 23 025 0 275 04 ns tHCDDR tkHIx Double Data Rate Control Hold after Clock K K 0 18 0 20 0 28 028 ns Rise BWSg BWS4 BWS BWS3 tub tkHDx Djx oj Hold after Clock K K Rise 0 18 020 0 28 028 ns Output Times tco tcHav K K Clock Rise to Data Valid 0 29 10331 037 045 ns tDOH tcHox Data Output Hold after Output K K Clock Rise 0 29
4. 0 33 0 37 045 ns Active to Active ccoo tcHcav K K Clock Rise to Echo Clock Valid 029 033 037 045 ns tcooH tcHcox Echo Clock Hold after K K Clock Rise 0 28 0 33 0 37 045 ns teap tcoHov Echo Clock High to Data Valid 0 15 0 15 0 15 0 20 ns tcoDoH tcoHox Echo Clock High to Data Invalid 0 15 0 15 0 15 020 ns tcoH tcoHcoL Output Clock CQ CQ HIGH 27 0 655 0 75 0 85 1 0 ns tcoucaH tcoHCOH CQ Clock Rise to CQ Clock Rise 0 655 0 75 085 10 ns rising edge to rising edge 27 tcHZ tcHoz Clock K K Rise to High Z 10 291 0 33 037 0 45 ns Active to High Z 28 21 telz tcHax1 Clock K K Rise to Low Z 28 29 0 29 0 33 0 37 045 ns tOVLD tcouovip Echo Clock High to QVLD Valid 30 0 15 0 15 0 15 0 15 0 15 0 15 0 20 0 20 ns PLL Timing tkc Var tkc Var Clock Phase Jitter 0 15 0 15 0 15 0 20 ns tke lock tkc lock PLL Lock Time K 20 20 20 20 US tkc Reset tkc Reset K Static to PLL Reset B1 30 30 30 30 ns Notes 25 When a part with a maximum frequency above 400 MHZ is operating at a lower clock frequency it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range 26 This part has a voltage regulator internally tbowER is the time that the power must be sup
5. Dyro EE GER Write Write Write Write Reg gt Reg gt Reg gt Reg Address Register Address Register ZS 21 A 20 0 Key 9 X WZ Key 9 X WZ Key 9 X WZ Control Kev 9 X WZ Read Add Decode Write Add Decode gt Read Data Reg Control Logic Block Diagram CY7C2576KV18 Piso las Ee Write Write Write Write gt Reg gt Reg gt Reg gt Reg Address A20 Register 20 0 Address Register N 21 A 20 0 Control Key 6 X NZ KeJv 6 X NZ Kew 6 X NZ KeJv 6 X NZ Write Add Decode Read Add Decode K DOFF Read Data Reg __ D ca VREF gt D gt cQ WPS gt Control Logic 9 B Qis 0 F oD Document Number 001 15887 Rev E Page 2 of 29 Feedback PERFORM CY7C2561KV18 CY7C2576KV18 PRELIMINARY CY7C2563KV18 CY7C2565KV18 Logic Block Diagram CY7C2563KV18 18 D 17 0 20 Address A99 Write Write Write Write Reg gt Reg Reg gt Reg Address A49 Register 19 0 Register CN l Control DOFF gt Keuv 84 X WL Keuv 84 X WL Keuv 84 X WL Keuv 84 X WL Write Add Decode Read Add Decode l gt Rea
6. M Table 2 Pin Definitions continued Pin Name IO Pin Description K Input Clock Positive Input Clock Input The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q 9 All accesses are initiated on the rising edge of K K Input Clock Negative Input Clock Input K is used to capture synchronous inputs being presented to the device and to drive out data through Og CQ Echo Clock Synchronous Echo Clock Outputs This is a free running clock and is synchronized to the input clock K of the QDR II The timings for the echo clocks are shown in the Switching Characteristics on page 24 ca Echo Clock Synchronous Echo Clock Outputs This is a free running clock and is synchronized to the input clock K of the QDR II The timings for the echo clocks are shown in the Switching Characteristics on page 24 ZA Input Output Impedance Matching Input This input is used to tune the device outputs to the system data bus impedance CQ CQ and Q x oj output impedance are set to 0 2 x RQ where RQ is a resistor connected between ZQ and ground Alternatively this pin can be connected directly to Vopa which enables the minimum impedance mode This pin cannot be connected directly to GND or left unconnected DOFF Input PLL Turn Off Active LOW Connecting this pin to ground turns off the PLL inside the device The timings in the PLL turned off o
7. 8 n A c E G G G H 8 J 8 oooooo6 ooooo K 00oooooooooo k L oooooopooooo t 8 M os ooooooooooo Im N oooooo ooooo P 00000000000 le R 00009000088 r A A 1 00 d 5 00 10 00 B 13001010 B 41 13001010 A 0 15 4X e 8 z NOTES 3 i 2 9 SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD NE i 5 PACKAGE WEIGHT 0 475g q JEDEC REFERENCE MO 216 DESIGN 4 6C t 1 PACKAGE CODE BBOAC M SEATING PLANE j o c o 8 E 51 85180 A 3 Document Number 001 15887 Rev E Page 28 of 29 Feedback Eia s CYPRESS PERFORM CY7C2561KV18 CY7C2576KV18 PRELIMINARY CY7C2563KV18 CY7C2565KV18 Uy Document History Page Document Title CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 72 Mbit QDR II SRAM 4 Word Burst Architecture 2 5 Cycle Read Latency with ODT Document Number 001 15887 Rev Ecn No EE s Description Of Change S 1120252 VKN See ECN New datasheet A 1246904 VKN AESA See ECN Added 550 and 500 MHz speed bins Removed 375 333 and 300 MHz speed bins Made ODT applicable only for DDR inputs Added footnote 2 B 1739343 VKN AESA SeeECN Converted from Advance Information to Preliminary C 2088787 VKN AESA SeeECN Changed PLL lock time from 2048 cycles to 20 us Added footnote 23 related to Ipp Corrected typo in the footnote 27 D 2612244 VKN AESA 11 25 08 Changed JTAG ID 31 29 from 001 to 000 Updated Power up seguence wa
8. Vin Input HIGH Voltage 0 65Vpp Vpp 0 3 V Vi Input LOW Voltage 0 3 0 35Vpp V Ix Input and Output Load Current GND lt Vj lt Vpp 5 5 uA Notes 14 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load levels are specified in the Electrical Characteristics Table 15 Overshoot Vin AC lt Vppa 0 35V Pulse width less than tcyc 2 Undershoot Vi AC gt 0 3V Pulse width less than tovc 2 16 All Voltage referenced to Ground Document Number 001 15887 Rev E Page 16 of 29 Feedback PERFORM TAP AC Switching Characteristics Over the Operating Range II 18 PRELIMINARY CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 Parameter Description Min Max Unit trcvc TCK Clock Cycle Time 50 ns trr TCK Clock Freguency 20 MHz tru TCK Clock HIGH 20 ns tn TCK Clock LOW 20 ns Setup Times tryss TMS Setup to TCK Clock Rise 5 ns trpis TDI Setup to TCK Clock Rise 5 ns tcs Capture Setup to TCK Rise ns Hold Times trMsH TMS Hold after TCK Clock Rise 5 ns trpiH TDI Hold after Clock Rise 5 ns tcH Capture Hold after Clock Rise 5 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns ttpox TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 4 shows the TAP timing and test conditions 18 Figure 4 TAP Timing and Test Conditions 0 9V ALL INPUT PULSES 500 1 8V 0 9V TDO OV Z 5
9. 7 Tek Dio on y mons Di3 X D30 D31 D32 D33 MMM tavLD 1 OVLD T I t DOH ie feb K NE _ capoH rc i i cap a gt ie Q01 oz aod a20 ENE s Read Latency 2 5 Cycles I EW to tccao CQOH l l CQ N x 3 ar l l lt 4 4 I tccao l l l tcaH CQHCQH tcdoH I l DON T CARE A UNDEFINED 32 Q00 refers to output from address AO Q01 refers to output from the next internal burst address following AO that is AO 1 33 Outputs are disabled High Z one clock cycle after a NOP 34 In this example if address A2 A1 then data Q20 D10 Q21 D11 Q22 D12 and Q23 D13 Write data is forwarded immediately as read results This note applies to the whole diagram Document Number 001 15887 Rev E Page 25 of 29 Feedback PERFORM Ordering Information PRELIMINARY CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 The following table lists all possible speed package and temperature range options supported for these devices Note that some options listed may not be available for order entry To verify the availability of a specific option visit the Cypress website at www cypress com and refer to the product summary page at http www cypress com products or contact your local sales representative for the status of availability of parts Cypress maintains a worldwide network of offices solution centers manu
10. VDDQ Vpp Vss Vpp Ven NC NC NC H DOFF VREF VDDQ VDDQ VDD Vss VDD VDDQ VDDQ VREF ZQ J NC NC NC Vee Von Vss VoD Vena NC Q1 D1 K NC NC NC VDDQ Vpp Vss Von Vppa NC NC NC L NC Q6 D6 Vino Vss Vss Vss VDDQ NC NC Qo M NC NC NC Vss Vss Vss Vss Vss NC NC DO N NC D7 NC Vss A A A Vss NC NC NC P NC NC Q7 A A QVLD A A NC NC NC R TDO TCK A A A ODT A A A TMS TDI CY7C2576KV18 8M x 9 1 2 3 4 5 6 7 8 9 10 11 A ca A A WPS NC K NC 144M RPS A A CQ B NC NC NC A NC 288M K BWS A NC NC Q4 e NC NC NC Vss A NC A Vss NC NC D4 D NC D5 NC Vss Vss Vss Vss Vss NC NC NC E NC NC Q5 VDDa Vss Vss Vss VDDQ NC D3 Q3 F NC NC NC Vppa Vas Vss VDD Vppa NC NC NC G NC D6 Q6 VDDQ Vpp Vss Vpp Vane NC NC NC H DOFF VREF VDDQ VDDQ VDD Vss VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ Vpp Vss Mise VDDQ NC Q2 D2 K NC NC NC Vppa Vpp Vss Von Vppa NC NC NC L NC Q7 D7 VDDQ Vss Vss Vss VDDQ NC NC Q1 M NC NC NC Vss Vss Vss Vss Vss NC NC D1 N NC D8 NC Vss A A A Vss NC NC NC P NC NC Q8 A A QVLD A A NC DO QO R TDO TCK A A A ODT A A A TMS TDI Note 2 NC 144M and NC 288M are not connected to the die and can be tied to any voltage level Document Number 001 15887 Rev E Page 4 of 29 Feedback LE y PRELIMINARY CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 PERFORM Pin Configuration The pin configuration for CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 and CY7C2565KV18 follow 4 continued 165 Ball FBGA 13 x 15 x 1 4 mm Pinout CY7C2563KV18 4M x 18
11. does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 15887 Rev E Revised April 24 2009 Page 29 of 29 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress IDT NEC Renesas and Samsung All product and company names mentioned in this document are the trademarks of their respective holders Feedback
12. loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between TDI and TDO pins This enables shifting of data through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM Several No Connect NC pins are also included in the scan register to reserve pins for higher density devices The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the input and output ring The Boundary Scan Order on page 19 shows the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of th
13. o is written into the device D g5 9j remains unaltered L H H H L H During the data portion of a write sequence only the lower byte Dra op is written into the device Dj35 9 remains unaltered H L H H L H During the data portion of a write sequence only the byte D 47 gj is written into the device Drg oj and Dj35 18j remains unaltered H L H H L H During the data portion of a write sequence only the byte Dr7 9j is written into the device Drg oj and D g5 4gj remains unaltered H H L H L H During the data portion of a write sequence only the byte D 26 1gj is written into the device Dr7 o and Dja5 27 remains unaltered H H L H L H During the data portion of a write sequence only the byte D 6 1gj is written into the device Dr47 oj and Dj35 7 remains unaltered H H H L L H During the data portion of a write sequence only the byte D 35 2 is written into the device Dj26 0 remains unaltered H H H L L H During the data portion of a write sequence only the byte D 35 2 is written into the device Dps oy remains unaltered L H No data is written into the device during this portion of a write operation L H No data is written into the device during this portion of a write operation Document Number 001 15887 Rev E Page 12 of 29 Feedback YPRESS PERFORM Mi Ew IEEE 1149 1 Serial Boundary Scan JTAG These SRAMs incorporate a serial boundary sca
14. up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB on any register Test Data Out TDO The TDO output pin is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine see Instruction Codes on page 18 The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register Performing a TAP Reset A Reset is performed by forcing TMS HIGH Vpp for five rising edges of TCK This Reset does not affect the operation of the SRAM and can be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a high Z state TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry Only one register can be selected at a time through the instruction registers Data is serially loaded into the TDI pin on the rising edge of TCK Data is output on the TDO pin on the falling edge of TCK Document Number 001 15887 Rev E PRELIMINARY CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 16 Upon power up the instruction register is
15. 0 where RO is the resistor tied to ZQ pin When left floating a high range termination value is selected by default For a detailed description on the ODT imple mentation refer to the application note On Die Termination for QDRII DDRII SRAMs PLL These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency During power up when the DOFF is tied HIGH the PLL is locked after 20 us of stable clock The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns However it is not necessary to reset the PLL to lock to the desired frequency The PLL automatically locks 20 us after a stable clock is presented The PLL may be disabled by applying ground to the DOFF pin When the PLL is turned off the device behaves in ODR I mode with one cycle latency and a longer access time For information refer to the application note PLL Considerations in QDRII DDRII QDRII DDRII Page 9 of 29 Feedback oS _ ER EE M Ef CYPRESS PERFORM Application Example Figure 1 shows two QDR II used in an application BUS MASTER CPU or ASIC DATA IN DATA OUT Address Vt PRELIMINARY CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 Figure 1 Application Example D SRAM 1 A RPS WPS BWS K K ZQ RQ 250ohms 70 RO 250 ohms ODT lt SR
16. 00 MR a GND trn tr ril lle i lw Test Clock Pw 4 N TCK o trcvc TMSH truss r28 T Test Mode Select TMS KEN KA ZA N tTDIS tTDIH Lats Ti HAKE EER TDI Test Data Out TDO E Men Notes X trpov trpox 17 tcs and tou refer to the setup and hold time requirements of latching data from the boundary scan register 18 Test conditions are specified using the load in TAP AC Test Conditions ta tr 1 ns Document Number 001 15887 Rev E Page 17 of 29 Feedback PERFORM CY7C2561KV18 CY7C2576KV18 PRELIMINARY CY7C2563KV18 CY7C2565KV18 Table 7 Identification Register Definitions Value Instruction Field Description CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 Revision Number 000 000 000 000 Version number 31 29 Cypress Device ID 11010010001000100 11010010001001100 11010010001010100 11010010001100100 Defines the type of 28 12 SRAM Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique 11 1 identification of SRAM vendor ID Register 1 1 1 1 Indicates the Presence 0 presence of an ID register Table 8 Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 109 Table 9 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output
17. 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C2561KV18 400BZXC 51 85180 CY7C2576KV18 400BZXC CY7C2563KV18 400BZXC CY7C2565KV18 400BZXC CY7C2561KV18 400BZI 51 85180 CY7C2576KV18 400BZI CY7C2563KV18 400BZI CY7C2565KV18 400BZI 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial Industrial CY7C2561KV18 400BZXI 51 85180 CY7C2576KV18 400BZXI CY7C2563KV18 400BZXI CY7C2565KV18 400BZXI 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Document Number 001 15887 Rev E Page 27 of 29 Feedback Lc PRELIMINARY CY7C2561KV18 CY7C2576KV18 Ef CYPRESS CY7C2563KV18 CY7C2565KV18 PERFORM Package Diagram Figure 7 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 BOTTOM VIEW PIN 1 CORNER TOP VIEW amp 9005MC f x PIN 1 CORNER 0 25M EA B 90 50 85x 0 14 1 2 3 4 5 6 Fi 8 9 10 11 11 10 9 8 7 6 amp 4 3 2 1 A e oooo ooood Ma B pT 1 9 0000000000 fs c 3 ooooo 060ooooo e a D z oooooo ooooo E ooooooooooo F o0ooooooooooo s 6 00000000000 s z
18. 4Vppo whichever is smaller 23 The operation current is calculated with 50 read cycle and 50 write cycle Document Number 001 15887 Rev E Page 21 of 29 Feedback PERFORM PRELIMINARY CY7C2561KV18 CY7C2576KV18 Electrical Characteristics continued DC Electrical Characteristics Over the Operating Range 16 CY7C2563KV18 CY7C2565KV18 Parameter Description Test Conditions Min Typ Max Unit la Automatic Power down Max VDD 550 MHz x8 380 mA Current Both Ports Deselected x9 380 Vin 2 Vin OF Vin lt Vi f fmax 1 tcvc mle a Inputs Static x36 380 500 MHz x8 360 mA x9 360 x18 360 x36 360 450 MHz x8 340 mA x9 340 x18 340 x36 340 400 MHz x8 320 mA x9 320 x18 320 x36 320 AC Electrical Characteristics Over the Operating Range 15 Parameter Description Test Conditions Min Typ Max Unit Vin Input HIGH Voltage Vner 0 2 Vppa 0 24 V ViL Input LOW Voltage 0 24 Vner 0 2 V Capacitance Tested initially and after any design or process change that may affect these parameters Parameter Description Test Conditions Max Unit CiN Input Capacitance TA 25 C f 1 MHZ Vpp 1 8V Vppo 1 5V 2 pF Co Output Capacitance 3 pF Thermal Resistance Tested initially and after any design or process change that may affect these param
19. 5 x 1 4 mm m Offered in both Pb free and non Pb free packages m JTAG 1149 1 compatible test access port m Phase Locked Loop PLL for accurate data placement Table 1 Selection Guide Configurations With Read Cycle Latency of 2 5 cycles CY7C2561KV18 8M x 8 CY7C2576KV18 8M x 9 CY7C2563KV18 4M x 18 CY7C2565KV18 2M x 36 Functional Description The CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 and CY7C2565KV18 are 1 8V Synchronous Pipelined SRAMs equipped with QDR II architecture Similar to ODR II archi tecture QDR II architecture consists of two separate ports the read port and the write port to access the memory array The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turn around the data bus that exists with common IO devices Each port is accessed through a common address bus Addresses for read and write addresses are latched on alternate rising edges of the input K clock Accesses to the QDR II read and write ports are completely independent of one another To maximize data throughput both read and write ports are equipped with DDR interfaces Each address location is associated with four 8 bit words CY7C2561KV18 9 bit words CY7C2576KV18 18 bit words CY7C2563KV18 or 36 bit words CY7C2565KV18 that burst sequentially
20. 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6c 79 1G 107 SR 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H Document Number 001 15887 Rev E Page 19 of 29 Feedback pd PRELIMINARY CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 PERFORM Power Up Sequence in QDR II SRAM PLL Constraints m PLL uses K clock as its synchronizing input The input must QDR II SRAMs must be powered up and initialized in a have low phase jitter which is specified as tke var predefined manner to prevent undefined operations m The PLL functions at frequencies down to 120 MHz m If the input clock is unstable and the PLL is enabled then the Power Up Sequence PLL may lock onto an incorrect frequency causing unstable m Apply power and drive DOFF either HIGH or LOW All other inputs can be HIGH or LOW SRAM behavior To avoid this provide 20 us of stable clock to a Apply Vpp before Vppo relock to the desired clock frequency a Apply Vppo before VREr or at the same time as VREF a Drive DOFF HIGH m Provide stable DOFF HIGH power and clo
21. A QVLD A A Q9 DO QO R TDO TCK A A A ODT A A A TMS TDI Document Number 001 15887 Rev E Page 5 of 29 Feedback PERFORM Table 2 Pin Definitions CY7C2561KV18 CY7C2576KV18 PRELIMINARY CY7C2563KV18 CY7C2565KV18 Pin Name IO Pin Description U x 0 Input Synchronous Data Input Signals Sampled on the rising edge of K and K clocks when valid write operations are active CY7C2561KV18 Drz oj CY7C2576KV18 D g 0 CY7C2563KV18 Di17 0 CY7C2565KV18 D 35 0 Input Synchronous Write Port Select Active LOW Sampled on the rising edge of the K clock When asserted active a write operation is initiated Deasserting deselects the write port Deselecting the write port ignores Dr Input Synchronous Nibble Write Select 0 1 Active LOW CY7C2561KV18 Only Sampled on the rising edge of the K and K clocks when write operations are active Used to select which nibble is written into the device during the current portion of the write operations NWSp controls D a 0j and NWS controls Drz 4j All the Nibble Write Selects are sampled on the same edge as the data Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device Input Synchronous Byte Write Select 0 1 2 and 3 Active LOW Sampled on the rising edge of the K and K clocks when write operations are active Used to select which byte is written into the d
22. AM 2 ODT lt CQ CQ CO CO Q D Q RPS WPS BWS K K A AA WPS BWS CLKIN1 CLKIN1 CLKIN2 CLKIN2 Source K fe Xd BB JJ 4 ANA MAAN Source K Table 3 Truth Table R 50ohms Vt Vppo 2 The truth table for CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 and CY7C2565KV18 follows 5 6 7 8 9 Operation K RPS WPS DQ DQ DQ DQ Write Cycle K rising edges Load address on the rising edge of K input write data on two consecutive K and L H IJ Lun D A at K t 1 D A 1 at Kt 1 D A 2 at K t 2 D A 3 at K t 2 Read Cycle 2 5 cycle Latency rising edges Load address on the rising edge of K wait two and half cycles read data on two consecutive K and K L H LIT X Q A at Kt 2 Q A 1 at Kit 3 T Q A 2 at K t 3 T Q A 3 at K t 4 NOP No Operation H D X Q High Z D X Q High Z D X Q High Z D X Q High Z Standby Clock Stopped Stopped X Previous State Previous State Previous State Previous State Notes X Don t Care H Logic HIGH L Logic LOW tT represents rising edge Device powers up deselected with the outputs in a tri state conditi
23. CY7C2561KV18 CY7C2576KV18 7i CYPRESS PRELIMINARY CY7C2563KV18 CY7C2565KV18 PERFORM 72 Mbit QDR II SRAM 4 Word Burst Architecture 2 5 Cycle Read Latency with ODT Features m Separate independent read and write data ports Supports concurrent transactions m 550 MHz clock for high bandwidth m 4 word burst for reducing address bus frequency m Double Data Rate DDR interfaces on both read and write ports data transferred at 1100 MHz at 550 MHz m Available in 2 5 clock cycle latency m Two input clocks K and K for precise DDR timing a SRAM uses rising edges only m Echo clocks CQ and CQ simplify data capture in high speed systems m Data valid pin QVLD to indicate valid data on the output m On Die Termination ODT feature _ a Supported for Dio BWSr oj and K K inputs m Single multiplexed address input bus latches address inputs for read and write ports m Separate port selects for depth expansion m Synchronous internally self timed writes m QDR II operates with 2 5 cycle read latency when DOFF is asserted HIGH m Operates similar to ODR I device with 1 cycle read latency when DOFF is asserted LOW m Available in x8 x9 x18 and x36 configurations m Full data coherency providing most current data m Core Vpp 1 8V 0 1V IO Vppg 1 4V to Vpp 1 Supports both 1 5V and 1 8V IO supply m HSTL inputs and variable drive HSTL output buffers m Available in 165 Ball FBGA package 13 x 1
24. CY7C2563KV 18 is organized internally as four arrays of 1M x 18 Accesses are completed in a burst of four sequential 18 bit data words Read operations are initiated by asserting RPS active at the rising edge of the positive input clock K The address presented to the address inputs is stored in the read address register Following the next two K clock rise the corre sponding lowest order 18 bit word of data is driven onto the Omz o using K as the output timing reference On the subse quent rising edge of K the next 18 bit data word is driven onto the Qr 7 9 This process continues until all four 18 bit data words have been driven out onto Qr47 9j The requested data is valid 0 45 ns from the rising edge of the input clock K or K To maintain the internal logic each read access must be allowed to complete Each read access consists of four 18 bit data words and takes two clock cycles to complete Therefore read accesses to the device can not be initiated on two consecutive K clock rises The internal logic of the device ignores the second read request Read accesses can be initiated on every other K Document Number 001 15887 Rev E PRELIMINARY CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 clock rise Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the input clocks K and K When the read port is deselected the CY7C2563KV18 first completes the pending read tr
25. I STATE IEEE Standard 1149 1 mandates that the TAP controller be able to put the output bus into a tri state mode The boundary scan register has a special bit located at bit 108 When this scan cell called the extest output bus tri state is latched into the preload register during the Update DR state in the TAP controller it directly controls the state of the output Q bus pins when the EXTEST is entered as the current instruction When HIGH it enables the output buffers to drive the output bus When LOW this bit places the output bus into a High Z condition This bit can be set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell latches into the preload register When the EXTEST instruction is entered this bit directly controls the output Q bus pins Note that this bit is preset HIGH to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Page 14 of 29 Feedback CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18
26. KV18 500BZI CY7C2576KV18 500BZI CY7C2563KV18 500BZI CY7C2565KV18 500BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C2561KV18 500BZXI CY7C2576KV18 500BZXI CY7C2563KV18 500BZXI CY7C2565KV18 500BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Document Number 001 15887 Rev E Page 26 of 29 Feedback PERFORM Table 11 Ordering Information continued CY7C2561KV18 CY7C2576KV18 PRELIMINARY CY7C2563KV18 CY7C2565KV18 CY7C2561KV18 450BZI CY7C2576KV18 450BZI CY7C2563KV18 450BZI CY7C2565KV18 450BZI CY7C2561KV18 450BZXI 51 85180 CY7C2576KV18 450BZXI CY7C2563KV18 450BZXI CY7C2565KV18 450BZXI 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Speed Package Operating MHz Ordering Code Diagram Package Type Range 450 CY7C2561KV18 450BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C2576KV18 450BZC CY7C2563KV18 450BZC CY7C2565KV18 450BZC CY7C2561KV18 450BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C2576KV18 450BZXC CY7C2563KV18 450BZXC CY7C2565KV18 450BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial 400 CY7C2561KV18 400BZC 51 85180 CY7C2576KV18 400BZC CY7C2563KV18 400BZC CY7C2565KV18 400BZC
27. ansactions Synchronous internal circuitry automatically tri states the outputs following the next rising edge of the negative input clock K This enables for a seamless transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock K On the following K clock rise the data presented to Dr7 o is latched and stored into the lower 18 bit write data register provided BWSp o are both asserted active On the subsequent rising edge of the negative input clock K the information presented to Dy4 9 is also stored into the write data register provided BWS 4 9 are both asserted active This process continues for one more cycle until four 18 bit words a total of 72 bits of data are stored in the SRAM The 72 bits of data are then written into the memory array atthe specified location Therefore write accesses to the device can not be initiated on two consecutive K clock rises The internal logic of the device ignores the second write request Write accesses can be initiated on every other rising edge of the positive input clock K Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks K and K When deselected the write port ignores all inputs after the pending write operations have been completed Byte Wri
28. cal components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress
29. captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins Document Number 001 15887 Rev E CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while the data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST The EXTEST instruction drives the preloaded data out through the system output pins This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift DR controller state EXTEST OUTPUT BUS TR
30. ck K K for 20 us to lock the PLL Figure 5 Power Up Waveforms Fw I II AO K K LJ i Xl us Xi del if XLI Y Unstable Clock gt 20us Stable clock gt Start Manta Operation Clock Start Clock Starts after Vpp Vpp Stable ca Fix HIGH or tie to Ypo DOFF Page 20 of 29 Document Number 001 15887 Rev E Feedback gp e PRELIMINARY CY7C2561KV18 CY7C2576KV18 Ef CYPRESS CY7C2563KV18 CY7C2565KV18 PERFORM Maximum Ratings Exceeding maximum ratings may impair the useful life of the Current into Outputs LOW eene 20 mA device These user guidelines are not tested Static Discharge Voltage MIL STD 883 M 3015 gt 2001V Storage Temperature ee 65 C to 150 C Latch up Current cc ccccsccccsescssescsnescenesceeneesenees 200 mA Ambient Temperature with Power Applied 55 C to 125 C Supply Voltage on Vpp Relative to GND 0 5V to 2 9V Operating Range Supply Voltage on Vopa Relative to GND 0 5V to Vpp Rande EE TA Vool Vppo DC Applied to Outputs in High Z 0 5V to Vppa 0 3V Commercial 0 C to 70 C 1 8 01V 1 4V to DC Input Voltage El ses aie 0 5V to Vpp 0 3V V Industrial 40 C to 85 C DD Electrical Characteristics DC Electrical Characteristics Over th
31. d Data Reg VREF WPS 9 BWS 1 0 72 W 017 0 F gt OVLD Logic Block Diagram CY7C2565KV18 36 D 35 0 GE Address 19 Ans0 Address Register Write Write Write Write Reg gt Reg gt Reg gt Reg A 18 0 Register N Control Write Add Decode Reu 9 X MZLIG Reu 9 X MZLG Reu 9 X MZLG Reu 9 X MZLG Read Add Decode I Read Data Reg Control Logic Document Number 001 15887 Rev E mo ca 36 r gt FP OVLD B O 35 0 Page 3 of 29 Feedback CY7C2561KV18 CY7C2576KV18 sz PRELIMINARY CY7C2563KV18 CY7C2565KV18 PERFORM Pin Configuration The pin configuration for CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 and CY7C2565KV18 follow 165 Ball FBGA 13 x 15 x 1 4 mm Pinout CY7C2561KV18 8M x 8 1 2 3 4 5 6 7 8 9 10 11 A cQ A A WPS NWS K NC 144M RPS A A cQ B NC NC NC A NC 288M K NWS A NC NC Q3 C NC NC NC Vss A NC A Vss NC NC D3 D NC D4 NC Vss Vss Vss Vss Vss NC NC NC E NC NC Q4 VDDQ Vss Vss Vss VDDQ NC D2 Q2 F NC NC NC VDDQ Vpp Vss Msn Vppa NC NC NC G NC D5 Q5
32. depends on the previous state of the SRAM If both ports are deselected the read port takes priority If a read was initiated on the previous cycle the write port takes priority as read operations can not be initiated on consecutive cycles If a write was initiated on the previous cycle the read port takes priority as write operations can not be initiated on consecutive cycles Therefore asserting both port selects active from a deselected state results in alter nating read or write operations being initiated with the first access being a read Depth Expansion The CY7C2563KV18 has a port select input for each port This enables for easy depth expansion Both port selects are sampled on the rising edge of the positive input clock only K Each port select input can deselect the specified port Deselecting a port does not affect the other port All pending transactions read and write are completed before the device is deselected Programmable Impedance An external resistor RQ must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output driver impedance The value of RQ must be 5X the value of the intended line impedance driven by the SRAM the allowable range of RQ to guarantee impedance matching with a tolerance of 415 is between 175O and 3500 with Vppo 1 5V The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature Echo Cloc
33. e Operating Range 16 Parameter Description Test Conditions Min Typ Max Unit Vpp Power Supply Voltage 1 7 1 8 1 9 V Vppa IO Supply Voltage 1 4 1 5 Vpp V Vou Output HIGH Voltage Note 20 Vppo 2 0 12 Vppo 2 0 12 V VoL Output LOW Voltage Note 21 Vppo 2 0 12 Vppo 2 0 12 V VoH Low Output HIGH Voltage lop 0 1 mA Nominal Impedance Vppo 0 2 VDDQ V VoL Low Output LOW Voltage lo 0 1 mA Nominal Impedance Vss 0 2 V Vin Input HIGH Voltage Vner 0 1 Vppa 0 15 V Vi Input LOW Voltage 0 15 Vner 0 1 V lx Input Leakage Current GND lt Vi lt Vppo 2 2 HA loz Output Leakage Current GND lt V lt Vppo Output Disabled 2 2 HA VREF Input Reference Voltage 22 Typical Value 0 75V 0 68 0 75 0 95 V IDD 23 Vpp Operating Supply Vpp Max 550 MHz x8 900 mA lour 0 mA x9 900 f fmax l tcvc x18 920 x36 1310 500 MHz x8 830 mA x9 830 x18 850 x36 1210 450 MHz x8 760 mA x9 760 x18 780 x36 1100 400 MHz x8 690 mA x9 690 x18 710 x36 1000 Notes 19 Power up Assumes a linear ramp from OV to Vpp min within 200 ms During this time Vi lt Vpp and Vppo lt Vpp 20 Output are impedance controlled loj Vppa 2 RQ 5 for values of 175 ohms lt RQ lt 350 ohms 21 Output are impedance controlled Io Vppo 2 RQ 5 for values of 175 ohms lt RQ lt 350 ohms 22 Vggr min 0 68V or 0 46Vppq whichever is larger VRer max 0 95V or 0 5
34. e register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in Identification Register Definitions on page 18 TAP Instruction Set Eight different instructions are possible with the three bit instruction register All combinations are listed in Instruction Codes on page 18 Three of these instructions are listed as RESERVED and must not be used The other five instructions are described in this section in detail Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO pins To execute the instruction after it is shifted in the TAP controller must be moved into the Update IR state Page 13 of 29 Feedback EE E PRELIMINARY PERFORM The IDCODE instruction loads a vendor specific 32 bit code into the instruction register It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift DR state The IDCODE ins
35. eters Parameter Description Test Conditions EES Unit OJA Thermal Resistance Test conditions follow standard test methods With Still Air 13 7 C W Junction to Ambient and procedures for measuring thermal 0m s impedance in accordance with EIA JESD51 With Air flow 12 56 1m s Ojc Thermal Resistance 3 73 C W Junction to Case Document Number 001 15887 Rev E Page 22 of 29 SS epELIMINAgy CYTC2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 PERFORM AC Test Loads and Waveforms VREF 0 75V Vggel e 0 75V OUTPUT VREF o 0 75V R 500 Pa ALL INPUT PULSES Device OUTPUT 1 25V Under 0 75V Test qud 5pF 0 25V _ Under p E Vper 0 75V Fast ZO T Slew Rate 2 V ns Bs RQ a 2500 a INCLUDING JIGAND b SCOPE Note pulse levels of 0 25V to 1 25V and output loading of the specified lo Iou and load capacitance shown in a of AC Test Loads and Waveforms Document Number 001 15887 Rev E 24 Unless otherwise noted test conditions are based on signal transition time of 2V ns timing reference levels of 0 75V Vref 0 75V RQ 2500 Vppg 1 5V input Page 23 of 29 Feedback CY7C2561KV18 CY7C2576KV18 PRELIMINARY Y7C2563KV18 CY7C2565KV18 PERFORM Switching Characteristics Over the Operating Range 2 251
36. evice during the current portion of the write operations Bytes not written remain unaltered CY7C2576KV18 BWSp controls Dig oy CY7C2563KV18 BWSj controls Ds oj and BWS controls Dr 7 9j CY7C2565KV18 BWSj controls Djs oj BWS controls Dr 7 9j BWS controls Drg 4sj and BWS3 controls D a5 27 All the Byte Write Selects are sampled on th same edge as the data Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device Input Synchronous Address Inputs Sampled on the rising edge ofthe K clock during active read and write operations These address inputs are multiplexed for both read and write operations Internally the device is organized as 8M x8 4 arrays each of 2M x 8 for CY7C2561KV18 8M x 9 4 arrays each of 2M x 9 for CY7C2576KV18 4M x 18 4 arrays each of 1M x 18 for CY7C2563KV18 and 2M x 36 4 arrays each of 512K x 36 for CY7C2565KV18 Therefore only 21 address inputs are needed to access the entire memory array of CY7C2561KV18 and CY7C2576KV18 20 address inputs for CY7C2563KV18 and 19 address inputs for CY7C2565KV18 These inputs are ignored when the appropriate port is deselected Qno Outputs Synchronous Data Output Signals These pins drive out the requested data when the read operation is active Valid data is driven out on the rising edge of the K and K clocks during read operations On deselecting the read port O are automatically tr
37. facturer s representatives and distributors To find the office closest to you visit us at http app cypress com portal server pt space CommunityPage amp control SetCommunity amp CommunityID 201 amp PageID 230 Table 11 Ordering Information Speed MHz Ordering Code Package Diagram Package Type Operating Range 550 CY7C2561KV18 550BZC CY7C2576KV18 550BZC CY7C2563KV18 550BZC CY7C2565KV18 550BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C2561KV18 550BZXC CY7C2576KV18 550BZXC CY7C2563KV18 550BZXC CY7C2565KV18 550BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Commercial CY7C2561KV18 550BZI CY7C2576KV18 550BZI CY7C2563KV18 550BZI CY7C2565KV18 550BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C2561KV18 550BZXI CY7C2576KV18 550BZXI CY7C2563KV18 550BZXI CY7C2565KV18 550BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 500 CY7C2561KV18 500BZC CY7C2576KV18 500BZC CY7C2563KV18 500BZC CY7C2565KV18 500BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C2561KV18 500BZXC CY7C2576KV18 500BZXC CY7C2563KV18 500BZXC CY7C2565KV18 500BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C2561
38. he number of address pins required By having separate read and write ports the QDR II completely eliminates the need to turn around the data bus and avoids any possible data contention thereby simplifying system design Each access consists of four 8 bit data transfers in the case of CY7C2561KV18 four 9 bit data transfers in the case of CY7C2576KV18 four 18 bit data transfers in the case of CY7C2563KV18 and four 36 bit data transfers in the case of CY7C2565KV 18 in two clock cycles These devices operate with a read latency of two and half cycles when DOFF pin is tied HIGH When DOFF pin is set LOW or connected to Vss then device behaves in ODR I mode with a read latency of one clock cycle Accesses for both ports are initiated on the positive input clock K All synchronous input and output timing are referenced from the rising edge of the input clocks K and K All synchronous data inputs D 0j pass through input registers controlled by the input clocks K and K All synchronous data outputs Or 0j outputs pass through output registers controlled by the rising odde of the input clocks K and K as well All synchronous control RPS WPS NWSp oj BWSLop inputs pass through input registers controlled by the rising edge of the input clocks K and K CY7C2563KV18 is described in the following sections The same basic descriptions apply to CY7C2561KV18 CY7C2576KV18 and CY7C2565KV18 Read Operations The
39. i stated CY7C2561KV18 Qrz g CY7C2576KV18 Qrg oj CY7C2563KV18 O 17 0 CY7C2565KV18 O g5 0 RPS Input Synchronous Read Port Select Active LOW Sampled on the rising edge of positive input clock K When active a read operation is initiated Deasserting deselects the read port When deselected the pending access is allowed to complete and the output drivers are automatically tri stated following the next rising edge of the K clock Each read access consists of a burst of four seguential transfers QVLD Valid output indicator Valid Output Indicator The Q Valid indicates valid output data QVLD is edge aligned with CQ and CQ opt Bl On Die Termination input pin On Die Termination Input This pin is used for On Die termination of the input signals ODT range selection is made during power up initialization A LOW on this pin selects a low range that follows RQ 3 33 for 1750 lt RO lt 3500 where RO is the resistor tied to ZO pin A HIGH on this pin selects a high range that follows RQ 1 66 for 1750 lt RO lt 2500 where RO is the resistor tied to ZO pin When left floating a high range termination value is selected by default Note 3 On Die Termination ODT feature is supported for Do BWS x 9 and K K inputs Document Number 001 15887 Rev E Page 6 of 29 Feedback PERFOR CY7C2561KV18 CY7C2576KV18 CYPRESS PRELIMINARY CY7C2563KV18 CY7C2565KV18
40. into or out of the device Because data is trans ferred into and out of the device on every rising edge of both input clocks K and K memory bandwidth is maximized while simpli fying system design by eliminating bus turn arounds These devices have an On Die Termination feature supported for Dio BWSpcg and K K inputs which helps eliminate external terminalon resistors reduce cost reduce board area and simplify board routing Depth expansion is accomplished with port selects which enables each port to operate independently All synchronous inputs pass through input registers controlled by the K or K input clocks All data outputs pass through output registers controlled by the K or K input clocks Writes are conducted with on chip synchronous self timed write circuitry Note Description 550 MHz 500 MHz 450 MHz 400 MHz Unit Maximum Operating Frequency 550 500 450 400 MHz Maximum Operating Current x8 900 830 760 690 mA x9 900 830 760 690 x18 920 850 780 710 x36 1310 1210 1100 1000 1 The Cypress QDR II devices surpass the QDR consortium specification and can support Vppq 1 4V to Vpp 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised April 24 2009 Cypress Semiconductor Corporation Document Number 001 15887 Rev E Feedback E PeELIMINAgv CY7C2561KV18 CY7C2576KV18 ss CY7C2563KV18 CY7C2565KV18 PERFORM Logic Block Diagram CY7C2561KV18
41. ks Echo clocks are provided on the QDR II to simplify data capture on high speed systems Two echo clocks are generated by the QDR II CQ is referenced with respect to K and CQ is refer enced with respect to K These are free running clocks and are synchronized to the input clock of the QDR II The timing for the echo clocks is shown in the Switching Characteristics on page 24 Document Number 001 15887 Rev E PRELIMINARY CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 Valid Data Indicator OVLD OVLD is provided on the QDR II to simplify data capture on high speed systems The OVLD is generated by the QDR II device along with data output This signal is also edge aligned with the echo clock and follows the timing of any data pin This signal is asserted half a cycle before valid data arrives On Die Termination ODT These devices have an On Die Termination feature for Data inputs Dio Byte Write Selects BWSr j and Input Clocks K and K The termination resistors are integrated within the chip The ODT range selection is enabled through ball R6 ODT pin The ODT termination tracks value of RQ where RQ is the resistor tied to the ZQ pin ODT range selection is made during power up initialization A LOW on this pin selects a low range that follows RQ 3 33 for 1750 lt RQ lt 3500 where RO is the resistor tied to ZQ pin A HIGH on this pin selects a high range that follows RQ 1 66 for 1750 lt RQ lt 250
42. n Test Access Port TAP in the FBGA package This part is fully compliant with IEEE Standard 1149 1 2001 The TAP operates using JEDEC standard 1 8V IO logic levels Disabling the JTAG Feature lt is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternatively be connected to Vpp through a pull up resistor TDO must be left unconnected Upon power up the device comes up in a reset state which does not interfere with the operation of the device Test Access Port Test Clock The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK This pin may be left unconnected if the TAP is not used The pin is pulled up inter nally resulting in a logic HIGH level Test Data In TDI The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information about loading the instruction register see the TAP Controller State Diagram on page 15 TDI is internally pulled
43. on t represents the cycle at which a read write operation is started t 1 t 2 andt 3 are the first second and third clock cycles respectively succeeding the t clock cycle 4 5 6 A represents address location latched by the devices when transaction was initiated A 1 A 2 and A 3 represents the address sequence in the burst 7 8 Data inputs are registered at K and K rising edges Data outputs are delivered on K and K rising edges as well 9 Ensure that when clock is stopped K K and C C HIGH This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically 10 If this signal was LOW to initiate the previous cycle this signal becomes a Don t Care for this operation 11 This signal was HIGH on previous K clock rise Initiating consecutive read or write operations on consecutive K clock rises is not permitted The device ignores the second read or write request Document Number 001 15887 Rev E Page 10 of 29 a PRELIVINARY CY7C2561KV18 CY7C2576KV18 S CYPRESS CY7C2563KV18 CY7C2565KV18 PERFORM Table 4 Write Cycle Descriptions The write cycle description table for CY7C2561KV18 and CY7C2563KV18 follows I 121 BWSy BWS K K Comments NWS NWS L L L H During the data portion of a write sequence CY7C2561KV18 both nibbles Dr 9j are written into the device CY7C2563KV18 both bytes Dana are wri
44. peration differs from those listed in this data sheet For normal operation this pin can be connected to a pull up through a 10 KO or less pull up resistor The device behaves in QDR I mode when the PLL is turned off In this mode the device can be operated at a frequency of up to 167 MHz with QDR I timing TDO Output TDO for JTAG TCK Input TCK Pin for JTAG TDI Input TDI Pin for JTAG TMS Input TMS Pin for JTAG NC N A Not Connected to the Die Can be tied to any voltage level NC 144M N A Not Connected to the Die Can be tied to any voltage level NC 288M N A Not Connected to the Die Can be tied to any voltage level VREF Input Reference Voltage Input Static input used to set the reference level for HSTL inputs outputs and AC Reference measurement points Vpp Power Supply Power Supply Inputs to the Core of the Device Vss Ground Ground for the Device Vppo Power Supply Power Supply Inputs for the Outputs of the Device Document Number 001 15887 Rev E Page 7 of 29 Feedback YPRESS PERFORM Mi Low Functional Overview The CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 are synchronous pipelined Burst SRAMs equipped with a read port and a write port The read port is dedicated to read operations and the write port is dedicated to write operations Data flows into the SRAM through the write port and flows out through the read port These devices multiplex the address inputs to minimize t
45. plied above Vpp minimum initially before a read or write operation can be initiated 27 These parameters are extrapolated from the input timing parameters tcyc 2 250 ps where 250 ps is the internal jitter These parameters are only guaranteed by design and are not tested in production 28 tcyz tci z are specified with a load capacitance of 5 pF as in b of AC Test Loads and Waveforms Transition is measured 100 mV from steady state voltage 29 At any given voltage and temperature tcuz is less than tc 7 and tcyz less than tco 30 toy p spec is applicable for both rising and falling edges of QVLD signal 31 Hold to Vi or Vj Document Number 001 15887 Rev E Page 24 of 29 Feedback _ EE m Ps EF CYPRESS PERFORM Switching Waveforms Read Write Deselect Sequence 2 33 34 Figure 6 Waveform for 2 5 Cycle Read Latency l RPS PRELIMINARY NOP READ WRITE 1 2 3 tkH tk tovc IkHRH READ 4 CY7C2561KV18 CY7C2576KV18 WRITE 5 NOP 6 7 8 CY7C2563KV18 CY7C2565KV18 ON NON ON poH rig rm MM A Y ll tsc ws UD TLL tsa QVLD Notes E A mt l tsc tHc A HA HD SEE EE EE EG af a _ A tup I SD l D 7 UM YY
46. ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the input and output ring contents Places the boundary scan register between TDI and TDO Does not affect the SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operation Document Number 001 15887 Rev E Page 18 of 29 Feedback CY7C2561KV18 CY7C2576KV18 CYPRESS PRELIMINARY CY7C2563KV18 CY7C2565KV18 PERFORM Table 10 Boundary Scan Order Bit Bump ID Bit Bump ID Bit Bump ID Bit Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 OF 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E
47. te Operations Byte write operations are supported by the CY7C2563KV18 A write operation is initiated as described in the Write Operations section The bytes that are written are determined by BWS and BWS which are sampled with each set of 18 bit data words Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered This feature can be used to simplify read modify or write operations to a byte write operation Concurrent Transactions The read and write ports on the CY7C2563KV18 operates completely independently of one another As each port latches the address inputs on different clock edges the user can read or write to any location regardless of the transaction on the other port If the ports access the same location when a read follows a write in successive clock cycles the SRAM delivers the most recent information associated with the specified address location This includes forwarding data from a write cycle that was initiated on the previous K clock rise Page 8 of 29 Feedback YPRESS PERFORM Mi Low Read access and write access must be scheduled such that one transaction is initiated on any clock cycle If both ports are selected on the same K clock rise the arbitration
48. truction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test Logic Reset state SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is supplied during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the input and output pins is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output undergoes a transition The TAP may then try to capture a signal while in transition metastable state This does not harm the device but there is no guarantee as to the value that is captured Repeatable results may not be possible To guarantee that the boundary scan register captures the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold times tcs and tcp The SRAM clock input might not be
49. tten into the device L L L H During the data portion of a write sequence CY7C2561KV18 both nibbles Dj7 9 are written into the device CY7C2563KV18 both bytes Dia are written into the device L H L H During the data portion of a write sequence CY7C2561KV18 only the lower nibble D g oj is written into the device Dr7 4 remains unaltered CY7C2563KV18 only the lower byte Djg o Is written into the device Dr47 9j remains unaltered L H L H During the data portion of a write sequence CY7C2561KV18 only the lower nibble Dr3 op is written into the device Dr7 4j remains unaltered CY7C2563KV18 only the lower byte Djg oj is written into the device Dr47 9j remains unaltered H L L H During the data portion of a write sequence CY7C2561KV18 only the upper nibble Drz 4j is written into the device Dag remains unaltered CY7C2563KV18 only the upper byte Dae is written into the device Djs oj remains unaltered H L L H During the data portion of a write sequence CY7C2561KV18 only the upper nibble Dr7 4j is written into the device Dj5 9j remains unaltered CY7C2563KV18 only the upper byte Dura is written into the device Djg o remains unaltered H H L H No data is written into the devices during this portion of a write operation H H L H No data is written into the devices during this portion of a write operation Table 5 Write C
50. veform and it s description Included Thermal Resistance values Changed the package size from 15 x 17 x1 4 mm to 13 x 15 x 1 4 mm E 2697841 04 24 2009 VKN Moved to external web Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com lcd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2007 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as criti
51. ycle Descriptions The write cycle description table for CY7C2576KV18 follows 121 BWS K K Comments L L H During the data portion of a write sequence the single byte Drs op is written into the device L L H During the data portion of a write sequence the single byte Dra oj is written into the device H L H No data is written into the device during this portion of a write operation H L H No data is written into the device during this portion of a write operation Note 12 Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table NWSg NWS4 BWSo BWS BWS and BWS can be altered on different portions of a write cycle as long as the setup and hold requirements are achieved Document Number 001 15887 Rev E Page 11 of 29 Feedback Table 6 Write Cycle Descriptions PERFORM PRELIMINARY CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 The write cycle description table for CY7C2565KV18 follows I 121 BWS BWS BWS2 BWS K K Comments L L L L L H During the data portion of a write sequence all four bytes Dras o are written into the device E L L L L H During the data portion of a write sequence all four bytes Dras o are written into the device L H H H L H During the data portion of a write sequence only the lower byte Djg
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