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Micron MT18KSF1G72PZ-1G6E1 memory module

1. ALERT_n Output Alert output Possesses functions such as CRC error flag and command and address parity error flag as output signal If a CRC error occurs ALERT_n goes LOW for the period time interval and returns HIGH If an error occurs during a command address parity check ALERT_n goes LOW un til the on going DRAM internal recovery transaction is complete During connectivity test mode this pin functions as an input Use of this signal is system dependent If not connected as signal ALERT_n pin must be connected to Vpp on DIMMs EVENT_n Output Temperature event The EVENT_n pin is asserted by the temperature sensor when critical tem perature thresholds have been exceeded This pin has no function NF on modules without temperature sensors PDF 09005aef84f8c349 asf36c2gx72pz pdf Rev F 2 15 EN 6 Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved Macron 16GB x72 ECC DR 288 Pin DDR4 RDIMM Pin Descriptions Table 5 Pin Descriptions Continued Symbol Type Description TDQS_t Output Termination data strobe When enabled via the mode register the DRAM device enables the TDQS_c same R7 termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c When the TDQS function is disabled via the mode register the DM TDQS_t pin provides the da x8 a
2. OV lt pA 5 Vin lt 1 1V li Input leakage current ZQ 3 pA 6 7 lyo DQ leakage OV lt Vin lt Vpp 4 4 pA 7 lozpa Output leakage current Voyt Vpp DQ is disabled 5 pA lozpu Output leakage current Voyt Vss DQ and ODT 50 pA are disabled ODT is disabled with ODT input HIGH Ivreeca Vrerca leakage Vererca Vpp 2 after DRAM is ini 2 2 yA 7 tialized Notes 1 Vppq balls on DRAM are tied to Vpp 2 Vpp must be greater than or equal to Vpp at all times 3 Vrerca Must not be greater than 0 6 x Vpp When Vpp is less than 500mV Vref may be less than or equal to 300mV 4 Vr termination voltages in excess of specification limit adversely affect command and address signals voltage margins and reduce timing margins 5 Command and address inputs are terminated to Vpp 2 in the registering clock driver In put current is dependent on termination resistance set in the registering clock driver 6 Tied to ground Not connected to edge connector 7 Multiply by number of DRAM die on module PDF 09005aef84f8c349 Micron Technology Inc reserves the right to change products or specifications without notice asf36c2gx72pz pdf Rev F 2 15 EN 2012 Micron Technology Inc All rights reserved 16 Macron 16GB x72 ECC DR 288 Pin DDR4 RDIMM Electrical Specifications Table 11 Thermal Characteristics Symbol Parameter Condition Value Uni
3. Parameter Symbol 2400 2133 Units One bank ACTIVATE PRECHARGE current Ippo 1728 1620 mA One bank ACTIVATE PRECHARGE word line boost lpp current Ippo 126 126 mA One bank ACTIVATE READ PRECHARGE current Ipp1 1800 1720 mA Precharge standby current Ipp2Nn2 1800 1656 mA Precharge standby ODT current Ipp2nt 1620 1512 mA Precharge power down current Ipp2p2 1152 1080 mA Precharge quite standby current Ipp207 1476 1404 mA Active standby current Ipp3n2 2412 2268 mA Active standby lpp current Ippan2 108 108 mA Active power down current Ipp3p2 1586 1584 mA Burst read current Ippar 3456 3240 mA Burst read Ippo current Ippaar 1296 1188 mA Burst write current Ippaw 3816 3420 mA Burst refresh current 1 x REF IppsB 4032 3960 mA Burst refresh lpp current 1 x REF Ippsp 450 450 mA Self refresh current Normal temperature range 0 85 C Ippen2 720 720 mA Self refresh current Extended temperature range 0 95 C IDD6E2 972 972 mA Self refresh current Reduced temperature range 0 45 C Ipper2 360 360 mA Auto self refresh current 25 C Ipp6az 324 324 mA Auto self refresh current 45 C Ipp6az 360 360 mA Auto self refresh current 75 C Ipp6a2 576 576 mA Bank interleave read current Ipp7 4356 3870 mA Bank interleave read lpp current Ipp7 306 270 mA Maximum power down current Ipps 648 648 mA Notes 1 One module rank in the active Ipp pp the other rank in Ipp2p pp3n 2 All ranks in this Ipppp condition PDF 09005aef84f8c349
4. are used in the x4 and x8 configura tions x16 based SDRAM only has BGO CO C1 C2 RDIMM LRDIMM on ly Input Chip ID These inputs are used only when devices are stacked that is 2H 4H and 8H stacks for x4 and x8 configurations using through silicon vias TSVs These pins are not used in the x16 configuration Some DDR4 modules support a traditional DDP package which uses CS1_n CKE1 and ODT1 to control the second die All other stack configurations such as a 4H or 8H are assumed to be single load master slave type configurations where CO C1 and C2 are used as chip ID selects in conjunction with a single CS_n CKE and ODT Chip ID is considered part of the command code CKx_t CKx_c Input Clock Differential clock inputs All address command and control input signals are sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c CKEx Input Clock enable CKE HIGH activates and CKE LOW deactivates the internal clock signals device input buffers and output drivers Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operations all banks idle or active power down row active in any bank CKE is asynchronous for self refresh exit After Vrerca has become stable during the power on and ini tialization sequence it must be maintained during all operations including SELF REFRESH CKE must be maintained HIGH throughout read and write accesses Input buffers excluding
5. asf36c2gx72pz pdf Rev F 2 15 EN 19 Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved Macron Registering Clock Driver Specifications 16GB x72 ECC DR 288 Pin DDR4 RDIMM Registering Clock Driver Specifications Table 14 Registering Clock Driver Electrical Characteristics DDR4 RCD01 devices or equivalent Parameter Symbol Pins Min Nom Max Units DC supply voltage Vpop 1 14 1 2 1 26 V DC reference voltage VREF VREFCA 0 49 x Vopp 0 5 x Vopp 0 51 x VDD V DC termination Vor VREF 40mV VREF Vrer 40mV V voltage High level input Vin CMOS DRST_n 0 65 x VDD VDD V voltage Low level input ViL cmos 0 0 35 x Vpp V voltage DRST_n pulse width tIN 1 0 us IT_Pow er_stable AC high level output Vonago All outputs except Vit 0 15 x Vpp V voltage ALERT_n AC low level output VoL ao Virt 0 1 5x Vpp V voltage AC differential out Vonaift ag Yn_t Yn_c BCK_t 0 3 x Vpp mV put high measure BCK_c ment level for out put slew rate AC differential out Vorditf ao 0 3 x Vpp mV put low measure ment level for out put slew rate Note 1 Timing and switching specifications for the register listed are critical for proper opera tion of DDR4 SDRAM RDIMMs These are meant to be a subset of the parameters for the specifi
6. module may not be available in all listed speed grades Module Speed Grade Component Speed Grade 2G6 075 2G4 083E 2G3 083 2G1 093E 1G9 107E Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully de signed terminations controlled board impedances routing topologies trace length matching and decoupling However good signal integrity starts at the system level Mi cron encourages designers to simulate the signal characteristics of the system s memo ry bus to ensure adequate signal integrity of the entire memory system Power Operating voltages are specified at the edge connector of the module not at the DRAM Designers must account for any system voltage drops at anticipated power levels to en sure the required supply voltage is maintained PDF 09005aef84f8c349 1 8 Micron Technology Inc reserves the right to change products or specifications without notice asf36c2gx72pz pdf Rev F 2 15 EN 2012 Micron Technology Inc All rights reserved Macron lbp Specifications 16GB x72 ECC DR 288 Pin DDR4 RDIMM lbp Specifications Table 13 DDR4 lpp Specifications and Conditions 16GB Die Revision A Values are for the MT40A1G4 DDR4 SDRAM only and are computed from values specified in the 4Gb 1 Gig x 4 compo nent data sheet
7. DQ U18 DQ U32 DQ42 WDQ DQ DQ46 W DQ DQ DQ43 jrDQ DQ DQ47 Wr DQ DQ Vss H zi zR Vss WW ZQ zQ g DQS6_t W Vss DQS15_t Vss DQS6_c DQS15_c_W CS_n DQS t DQS _ cS_n DQS t DQS cS_n DQS t DQS c CS_n DQS t DQS c DQ48 WDQ DQ DQ52 yw DQ DQ DQa49 WDQ__ U19 DQ U31 DQ53 WDQ_ U9 DQ U22 DQ50 W DQ DQ DQ54 y DQ DQ DQ51 M DQ DQ DQ55 y DQ DQ Vss WWWZQ ZQ p Vss M ZQ zQ R DQs7_t Ms DQS16_t Vis DQS7_c M 2 DQS16_c Wr CS n DQS t DQS_c CS n DQS t DQS_c CS_n DQS t DQS_ CS_n DQS t DQS_c DQ56 WDQ DQ DQ60 yH DQ DQ DQ57 W DQ_ U20 DQ U30 DQ61 MH DQ U10 DQ U21 DQ58 WDQ DQ DQ62 yWW DQ DQ DQ59 jDQ DQ DQ63 y DQ DQ Vss WW1ZQ 203 Vss WW ZQ ZQ p Vss Vss Note Functional Block Diagram U16 A BCSO_n Rank 0 gt A BCS1_n Rank 1 gt A BBA 1 0 DDR4 SDRAM A BBG 1 0 DDR4 SDRAM gt A BACT_n DDR4 SDRAM A BA 17 13 0 DDR4 SDRAM gt A B RAS_n A16 DDR4 SDRAM gt A B CAS_n A15 DDR4 SDRAM CSO_n Np CS1_n N BA 1 0 N BG 1 0 W ACT n w A 17 13 0 RAS_n A16 gt CAS_n A15 N Om Bw WE_n A14 W AB WE_n A14 DDR4 SDRAM CKEO yy A BCKEO Rank 0 CKE1 y T ABCKE1 Rank 1 oDTO W gt gt A BODTO Rank 0 opri wW E awoDT Rank 1 PARIN W p A BPAR DDR4 SDRAM 2 0 yw 2 0 DDR4 SDRAM ALER
8. either the DRAM address and control bus or the I C bus interface The RCD I C bus interface resides on the same I C bus interface as the module temperature sensor and EEPROM Parity Operations The RCD includes a parity checking function that can be enabled or disabled in control word RCOE The RCD receives a parity bit at the DPAR input from the memory control ler and compares it with the data received on the qualified command and address in puts it indicates on its open drain ALERT_n pin whether a parity error has occurred If parity checking is enabled the RCD forwards commands to the SDRAM when no parity error has occurred If the parity error function is disabled the RCD forwards sampled commands to the SDRAM regardless of whether a parity error has occurred Parity is al so checked during control word WRITE operations unless parity checking is disabled Rank Addressing The chip select pins CS_n on Micron s modules are used to select a specific rank of DRAM The RDIMM is capable of selecting ranks in one of three different operating modes dependant on setting DA 1 0 bits in the DIMM configuration control word lo cated within the RCD Direct DualCS mode is utilized for single or dual rank modules For quad rank modules either direct or encoded QuadCS mode is used PDF 09005aef84f8c349 1 4 Micron Technology Inc reserves the right to change products or specifications without notice asf36c2gx72pz pdf Rev F 2 15 EN 2012 M
9. mode register setting MR 4 A 4 HIGH training times change when enabled DM_n DBI_n TDQS_t DMU_n DBIU_n DML_n DBII_n 1 0 Input data mask and data bus inversion DM_n is an input mask signal for write data Input data is masked when DM_n is sampled LOW coincident with that input data during a write ac cess DM_n is sampled on both edges of DQS DM is multiplexed with the DBI function by the mode register A10 A11 and A12 settings in MR5 For a x8 device the function of DM or TDQS is enabled by the mode register A11 setting in MR1 DBI_n is an input output identifying whether to store output the true or inverted data If DBI_n is LOW the data will be stored output after inversion inside the DDR4 device and not inverted if DBI_n is HIGH TDQS is only supported in x8 SDRAM configurations TDQS is not valid for UDIMMs SDA VO Serial Data Bidirectional signal used to transfer data in or out of the EEPROM or EEPROM TS combo device DQS_t DQS_c DQSU_t DQSU_c DQSL_t DQSL_c VO Data strobe Output with read data input with write data Edge aligned with read data cen tered aligned with write data For x16 configurations DQSL corresponds to the data on DQ 7 0 and DQSU corresponds to the data on DQ 15 8 For the x4 and x8 configurations DQS corresponds to the data on DQ 3 0 and DQ 7 0 respectively DDR4 SDRAM supports a differen tial data strobe only and does not support a single ended data strobe
10. 2 Vs 218 CK1t 254 Vss TDQS14_t 3 DQ4 39 Vss 75 CKO_c 111 DQS14_c 147 Vss 183 DQ25 219 CKi_c 255 DQS5 _c TDQS14_ 4 Vss 40 DQS12_t 76 Vpp 112 Vss 148 DQ5 184 Vs 220 Vpp 256 DQS5_t TDQS12_t 5 DQO 41 DQS12_c 77 Vit 113 DQ46 149 Vss 185 DQS3_c 221 Vit 257 Vss TDQS12_c Vss 42 Vss 78 EVENT_n 114 Vss 150 DQ1 186 DQS3_t 222 PARITY 258 DQ47 pas9_t 43 DQ30 79 A0 115 DQ42 151 Vss 187 Ves 223 Vpp 1259 Vss TDQS9_t 8 DQSO9_c 44 Vss 80 Vpop 116 Vss 152 DQSO_c 188 DQ31 224 BA1 260 DQ43 TDQS9_c 9 Vss 45 DQ26 81 BAO 117 DQ52 153 DQSO_t 189 Vss 225 A10 261 Vss AP 10 DQ6 46 Vss 82 RAS_n 118 Vss 154 Vss 190 DQ27 226 Vpp 262 DQ53 A16 11 Vss 47 CB4 83 Voo 119 DQ48 155 DQ7 l191 Vss 227 NC 263 Vss 12 DQ2 48 Vss 84 CSO_n 120 Vss 156 Vss 192 CB5 228 WE_n 264 DQ49 A14 13 Vss 49 CBO 85 Voo 121 DQS15_t 157 DQ3 193 Vs 229 Vpp 265 Veg TDQS15_t 14 DQ12 50 Vss 86 CAS_n 122 DQS15_c 158 Vss 194 CB1 230 NC 266 DQS6_c A15 TDQS15_c 15 Vss 51 DQS17_t 87 ODTO 123 Vss 159 DQ13 195 Vss 231 Vop 267 DQS6_t TDQS17_t 16 DQ8 52 DQS17_c 88 Vpop 124 DQ54 160 Vss 196 DQS8_c 232 A13 268 Vss TDQS17_c 17 Vss 53 Vss 89 CSt_n 125 Vss 161 DQ9 197 DQS8t 233 Vpp 269 DQ55 NC 18 DQS10_t 54 CB6 90 Voo 126 DQ50 162 Vss 198 Vss 234 A17 270 Vss TDQS10_t 19 DQS10_c 55 Vss 91 ODT1 127 Vss 163 DQS1_c 199 CB7 235 NC 271 DQ51 TDQS10_
11. 2_c 210 A11 246 Vss 282 DQ59 TDQS11_c 31 Vss 67 Vbo 103 Vos 139 SAO 175 DQS2_t 211 A7 247 DQ39 283 Vss 32 DQ22 68 A8 104 DQ34 140 sat 176 Vss 212 Vpp 1248 Vss 284 Vppspp 33 Vss 69 A6 105 Vss 141 SCL 177 DQ23 213 A5 249 DQ35 285 SDA 34 DQ18 70 Vbo 106 DQ44 142 Vpp 178 Vss 214 A4 250 Vss 286 Vpp 35 Vss 71 A3 107 Vss 143 Vpp 179 DQ19 215 Vbo 251 DQ45 287 Vpp 36 DQ28 72 A1 108 DQ40 144 NC 180 Vss 216 A2 252 Vss 288 Vpp PDF 09005aef84f8c349 asf36c2gx72pz pdf Rev F 2 15 EN Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved Macron Pin Descriptions 16GB x72 ECC DR 288 Pin DDR4 RDIMM Pin Descriptions The pin description table below is a comprehensive list of all possible pins for DDR4 modules All pins listed may not be supported on this module See Functional Block Di agram for pins specific to this module Table 5 Pin Descriptions Symbol Type Description Ax Input Address inputs Provide the row address for ACTIVATE commands and the column address for READ WRITE commands in order to select one location out of the memory array in the respec tive bank A10 AP A12 BC_n WE_n A14 CAS_n A15 and RAS_n A16 have additional functions see individual entries in this table The address inputs also provide the op code during the MODE REGISTER SET comman
12. A6 A5 A7 A7 A8 A8 A8 A7 A9 A9 A9 A10 A10 A10 A11 A11 A13 A13 A13 A11 A12 A12 A12 A14 A14 A14 A15 A15 A15 A16 A16 A16 A17 A17 A17 BAO BAO BA1 BA1 BA1 BAO BGO BGO BG1 BG1 BG1 BGO Registering Clock Driver Operation Registered DDR4 SDRAM modules use a registering clock driver device consisting of a register and a phase lock loop PLL The device complies with the JEDEC DDR4 RCDO1 Specification PDF 09005aef84f8c349 1 3 Micron Technology Inc reserves the right to change products or specifications without notice asf36c2gx72pz pdf Rev F 2 15 EN 2012 Micron Technology Inc All rights reserved IA icron 16GB x72 ECC DR 288 Pin DDR4 RDIMM Registering Clock Driver Operation To reduce the electrical load on the host memory controller s command address and control bus Micron s RDIMMs utilize a DDR4 registering clock driver RCD The RCD presents a single load to the controller while redriving signals to the DDR4 SDRAM de vices which helps enable higher densities and increase signal integrity The RCD also provides a low jitter low skew PLL that redistributes a differential clock pair to multiple differential pairs of clock outputs Control Words The RCD device s used on DDR4 RDIMMs and LRDIMMs contain configuration regis ters known as control words which the host uses to configure the RCD based on criteria determined by the module design Control words can be set by the host controller through
13. CK_t CK_c ODT RESET_n and CKE are disabled during power down Input buffers excluding CKE and RESET are disabled during self refresh CSx_n Input Chip select All commands are masked when CS_n is registered HIGH CS_n provides external rank selection on systems with multiple ranks CS_n is considered part of the command code CS2_n and CS3_n are not used on UDIMMs PDF 09005aef84f8c349 asf36c2gx72pz pdf Rev F 2 15 EN 5 Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved Macron 16GB x72 ECC DR 288 Pin DDR4 RDIMM Pin Descriptions Table 5 Pin Descriptions Continued Symbol Type Description ODTx PARITY Input Input On die termination ODT registered HIGH enables termination resistance internal to the DDR4 SDRAM When enabled ODT Rr is applied only to each DQ DQS_t DQS_c DM_n DBI_n TDQS_t and TDQS_c signal for x4 and x8 configurations when the TDQS function is ena bled via the mode register For the x16 configuration Rrr is applied to each DQ DQSU _t DQSU_c DQSL_t DQSL_c UDM_n and LDM_n signal The ODT pin will be ignored if the mode registers are programmed to disable Rrr Parity for command and address This function can be enabled or disabled via the mode register When enabled in MR5 the DRAM calculates parity with ACT_n RAS_n A16 CAS_n A15 WE_
14. IA icron 16GB x72 ECC DR 288 Pin DDR4 BEINN DDR4 SDRAM RDIMM MTA36ASF2G72PZ 16GB Features Figure 1 288 Pin RDIMM MO 309 R C B Module height 31 25mm 1 23in DDR4 functionality and operations supported as defined in the component data sheet a i e 288 pin registered dual in line memory module g a a RDIMM p Fast data transfer rates PC4 2400 or PC4 2133 OVUNUARORORONOONAUBUBUBURUROOOAONONONONENOVORONONQOQONONONONONOONOOONONIOY mmnm ANUARORORORORORRORONONARN e 16GB 2 Gig x 72 i Vpp 1 20V NOM ee Marking e Operating temperature S Vee eey INOM onada OC lt Toper lt 95 C None Vppspp 2 5V NOM e Package e Supports ECC error detection and correction 288 pin DIMM halogen free Z e Nominal and dynamic on die termination ODT for e Frequency CAS latency data strobe and mask signals 0 83ns CL 17 DDR4 2400 2G3 e Low power auto self refresh LPASR 0 93ns CL 15 DDR4 2133 2G1 e On die Vgerpo generation and calibration e Dual rank e On board I C temperature sensor with integrated serial presence detect SPD EEPROM e 16 internal banks 4 groups of 4 banks each e Fixed burst chop BC of 4 and burst length BL of 8 via the mode register set MRS e Selectable BC4 or BL8 on the fly OTF e Gold edge contacts e Halogen
15. Q U28 DQ10 WDQ DQ DQ14 WW DQ DQ DQ11 WDQ DQ DQ15 y DQ DQ Vss WZ zQ p Vss WW ZQ ZQ gs DQS2_t M Vss DQS11_t Vss DQS2_c_W DQS11_ c wr cS_n DQS t DQS _ CS n DQS t DQS_c CS_n DQS t DQS_c CS_n DQS t DQS_c DQ16 WDQ DQ DQ20 ww DQ DQ DQI7 WDQ__ U13 DQ U36 DQ21 mvHDQ u3 DQ U27 DQ18 WDQ DQ DQ22 WW DQ DQ DQ19 MDQ DQ DQ23 M DQ DQ Vss WW ZQ zQ g Vss WW ZQ zQ g DQS3_t M vis DQS12_t Vis DQS3_c DQS12_c M CS_n DQS t DQS_c CS_n DQS t DQS_c CS n DQS t DQS_c CS_n DQS t DQS_c DQ24 M DQ DQ DQ28 yr DQ DQ DQ25 WDQ_ U14 DQ U35 DQ29 MDQ U4 DQ U26 DQ26 W4DQ DQ DQ30 M DQ DQ DQ27 WWW DQ DQ DQ31 yr DQ DQ Vss WW zam Vss VH ZQ za DQS8_t r vis DQS17_t Ww vs DQs8_c W es DQS17_c Wn CS n DQS t DQS_c CS n DQS t DQS c CS n DQS t DQS_c CS_n DQS t DQS_c CBO DQ DQ CB4 y H DQ DQ BID U5 DQ U25 ces W DQ_ u15 DQ U34 CB2 M DQ DQ CB6 WW DQ DQ CB3 _WDQ DQ cB7 WW DQ DQ Vss WZ ZQ p Vss WW ZQ ZQ p DQS4_t M Vis DQS13_t WW Vis DQs4_c W DQS13_c M CS n DQS t DQS_c cS n DQS t DQS_c CS_n DQS t DQS_ CS_n DQS t DQS_c DQ32 WW DQ DQ DQ36 w DQ DQ DQ33 W4DQ_ U17 DQ U33 DQ37 M DQ U7 DQ U24 DQ34 WDQ DQ DQ38 W DQ DQ DQ35 W DQ DQ DQ39 MH DQ DQ Vss N Z zay Vss WW ZQ zo DQS5_t W Vis DQS14_t Vis DQS5_c W DQS14_c M A CS n DQS t DQS_c CS n DQS t DQS_c CS_n DQS t DQS_c CS_n DQS t DQS_c DQ40 WDQ DQ DQ44 pw DQ DQ DQ41 WDQ_ U8 DQ U23 DQ45 MH
16. T_CONN j_ amp ALERT_DRAM DDR4 SDRAM SAO gt _ P SA1 SA2 L SCL SDA L ick CK 1 0 _t lt DDR4 SDRAM CK_c CK 1 0 _ RESET_CONN RESET_DRAM DDR4 SDRAM Zor Vss Rank 0 U1 U5 U7 U15 U17 U20 Rank 1 U21 38 Command control address and clock line terminations DDR4 A BCS_n 1 0 A BBA 1 0 A BBG 1 0 SDRAM A BACT_n A BAI17 13 0 A B RAS_n A16 AIB CAS_n A15 A B WE_n A14 Vir AJBCKE 1 0 A BODT 1 0 TI SDRAM CK 3 0 _t ji Evi CK 3 0 c ji rt a U6 SPD EEPROM scL_ gt Temperature SDA sensor EVT A0 Al A2 TTT SAO SA1 SA2 EVENT SPD EEPROM Temp Sensor Vooso ____4 _ ale Register Voo T DDR4 SDRAM Register Vr T E Control command and address termination VREFCA gt DDR4 SDRAM Register Vee t DDR4 SDRAM vs l T DDR4SDRAM Register 1 The ZQ ball on each DDR4 component is connected to an external 2400 1 resistor that is tied to ground It is used for the calibration of the component s ODT and output driver PDF 09005aef84f8c349 asf36c2gx72pz pdf Rev F 2 15 EN 11 Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved Macron 16GB x72 ECC DR 288 Pin DDR4 RDIMM General Description General Description Fly By Topology H
17. age current SCL SDA Vin Vppspp Or Vssspp lu 5 yA Output leakage current Vout Vppspp Or Vssspp SDA in High Z lLo 5 yA Table 16 Temperature Sensor and EEPROM Serial Interface Timing Parameter Condition Symbol Min Max Units Clock frequency SCL 10 1000 kHz Clock pulse width HIGH time tHIGH 260 ns Clock pulse width LOW time tLOW 500 ns Detect clock LOW timeout tTIMEOUT 25 35 ms SDA rise time tR 120 ns SDA fall time tF 120 ns Data in setup time tsU DAT 50 ns Data in hold time tHD DI 0 ns Data out hold time tHD DAT 0 350 ns Start condition setup time tSU STA 260 ns Start condition hold time tHD STA 260 ns Stop condition setup time tsU STO 260 ns Time the bus must be free before a new transi tBUF 500 ns tion can start Write time tw 5 ms Warm power cycle time off tPOFF 1 ms Time from power on to first command tINIT 10 ms PDF 09005aef84f8c349 21 Micron Technology Inc reserves the right to change products or specifications without notice asf36c2gx72pz pdf Rev F 2 15 EN 2012 Micron Technology Inc All rights reserved In icron 16GB x72 ECC DR 288 Pin DDR4 RDIMM Module Dimensions Module Dimensions Figure 3 288 Pin DDR4 RDIMM Front view 3 9 0153 133 48 5 255 A T 133 22 5 244 ell Thee i a U6 u1 u2 u3 U4 U5 Cd U7 u8 u9 u10 z z le
18. c NC C2 20 Vss 56 CB2 92 Voo 128 DQ60o 164 DQSIt 200 Vs 1236 Vpp 1272 Vss 21 DQ14 57 Vss 93 CS2_n 129 Vss 165 Vss 201 CB3 237 CS3_n 273 DQ61 co C1 NC 22 Vss 58 RESET_n 94 Vss 130 pase 166 DQ15 202 vs 238 sa2 274 Vss 23 DQ10 59 Vpp 95 DQ36 131 Vss 167 Vss 203 CKE1 239 Vss 275 DQ57 NC 24 Vss 60 CKEO 96 Vss 132 DQs16_t 168 DQ11 204 Vpp 240 DQ37 276 Vss TDQS16_t PDF 09005aef84f8c349 asf36c2gx72pz pdf Rev F 2 15 EN Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved Macron Table 4 Pin Assignments Continued 16GB x72 ECC DR 288 Pin DDR4 RDIMM Pin Assignments 288 Pin DDR4 RDIMM Front 288 Pin DDR4 RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 25 DQ20 61 Vpp 97 DQ32 133 DQS16_c 169 Vss 205 NC 241 Vss 277 DQS7_c TDQS16_c 26 Vss 62 ACT_n 98 Vss 134 Vss 170 DQ21 206 Vpp 242 DQ33 278 DQS7_t 27 DQ16 63 BGO 99 DQS13_t 135 DQ62 171 Vss 207 BG1 243 Vss 279 Vss TDQ13_t 28 Vss 64 VDpp 100 DQS13_c 136 Vss 172 DQ17 208 ALERT_n 244 DQS4_c 280 DQ63 TDQS13_c 29 DQS11_t 65 A12 BC_n 101 Vss 137 DQ58 173 Vss 209 VDD 245 DQS4_t 281 Vss TDQS11_t 30 DQS11_c 66 A9 102 DQ38 138 Vss 174 DQS
19. c device used on the module See the JEDEC RCD01 specification for complete op erating electrical characteristics Registering clock driver parametric values are specified for device default control word settings unless otherwise stated The RCOA control word setting does not affect parametric values PDF 09005aef84f8c349 asf36c2gx72pz pdf Rev F 2 15 EN 20 Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved Macron Temperature Sensor With SPD EEPROM 16GB x72 ECC DR 288 Pin DDR4 RDIMM Temperature Sensor With SPD EEPROM The temperature sensor continuously monitors the module s temperature and can be read back at any time over the I C bus shared with the serial presence detect SPD EE PROM Refer to JEDEC JC 42 4 EE1004 and TSE2004 device specifications for complete details SPD Data For the latest SPD data refer to Micron s SPD page micron com SPD Table 15 Temperature Sensor With SPD EEPROM Operating Conditions Parameter Condition Symbol Min Nom Max Units Supply voltage Vppspp 2 5 V Input low voltage logic 0 all inputs Vi 0 5 Vppspp x 0 3 V Input high voltage logic 1 all inputs Vin Vppspp 0 7 Vppspp 0 5 V Output low voltage 3mA sink current Vppspp gt 2V VoL 0 4 V Input leak
20. c2gx72pz pdf Rev F 2 15 EN 1 0 Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved Macron Functional Block Diagram Figure 2 Functional Block Diagram 16GB x72 ECC DR 288 Pin DDR4 RDIMM A BCSO_n AIBCS1_n DQS0_t W DQs9_t W DQS0_c WW DQs9_c r CS_n DQS t DQS_c CS_n DQS_t DQS_c CS n DQS t DQS_c cs_n DQS t DQS_c DQ0 W4 DQ DQ DQ4 W DQ DQ DQi W4DQ_ U1 DQ U29 DQ5 WDQ_ u11 DQ U38 DQ2 M DQ DQ DQ6 W DQ DQ DQ3 WDQ DQ DQ7 M DQ DQ Vss V Zi ZQ p Vss WZQ ZQ p DQS1_t W V s DQS10_t Vis DQS1_c DQS10_c M ms CS_n DQS t DQS_c CS_n DQS t DQS_c CS n DQS t DQS_c CS_n DQS t DQS_c DQ8 WDQ DQ DQ12 yH DQ DQ DQ9 MHDQ U12 DQ U37 DQ13 wDQ U2 D
21. ce MT40A1G4 4Gb DDR4 SDRAM Module Module Memory Clock Clock Cycles Part Number Density Configuration Bandwidth Data Rate CL RCD RP MTA36ASF2G72PZ 2G3__ 16GB 2 Gig x 72 19 2 GB s 0 83ns 2400 MT s 17 17 17 MTA36ASF2G72PZ 2G1__ 16GB 2 Gig x 72 17 0 GB s 0 93ns 2133 MT s 15 15 15 Notes 1 The data sheet for the base device can be found on micron com 2 All part numbers end with a two place code not shown that designates component and PCB revisions Consult factory for current revision codes Example MTA36ASF2G72PZ 2G3A1 PDF 09005aef84f8c349 asf36c2gx72pz pdf Rev F 2 15 EN Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved Macron Pin Assignments Table 4 Pin Assignments 16GB x72 ECC DR 288 Pin DDR4 RDIMM Pin Assignments The pin assignment table below is a comprehensive list of all possible pin assignments for DDR4 RDIMM modules See Functional Block Diagram for pins specific to this mod ule 288 Pin DDR4 RDIMM Front 288 Pin DDR4 RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 NC 37 Vss 73 Vpp 109 Veg 145 NC 181 DQ29 217 Vpp 253 DQM 2 Vss 38 DQ24 74 cKot 110 DQS14_t 146 Vperca 18
22. d A17 is only defined for x4 SDRAM A10 AP Input Auto precharge A10 is sampled during READ and WRITE commands to determine whether an auto precharge should be performed on the accessed bank after a READ or WRITE operation HIGH auto precharge LOW no auto precharge A10 is sampled during a PRECHARGE com mand to determine whether the precharge applies to one bank A10 LOW or all banks A10 HIGH If only one bank is to be precharged the bank is selected by the bank group and bank addresses A12 BC_n Input Burst chop A12 BC_n is sampled during READ and WRITE commands to determine if burst chop on the fly will be performed HIGH no burst chop LOW burst chopped See Com mand Truth Table in the DDR4 component data sheet ACT_n Input Command input ACT_n defines the ACTIVATE command being entered along with CS_n The input into RAS_n A16 CAS_n A15 and WE_n A14 are considered as row address A16 A15 and A14 See Command Truth Table BAx BGx Input Input Bank address inputs Define the bank with a bank group to which an ACTIVATE READ WRITE or PRECHARGE command is being applied Also determine which mode register is to be accessed during a MODE REGISTER SET command Bank group address inputs Define the bank group to which a REFRESH ACTIVATE READ WRITE or PRECHARGE command is being applied Also determine which mode register is to be accessed during a MODE REGISTER SET command BG 1 0
23. deral Way P O Box 6 Boise ID 83707 0006 Tel 208 368 4000 www micron com products support Sales inquiries 800 932 4992 Micron and the Micron logo are trademarks of Micron Technology Inc All other trademarks are the property of their respective owners This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein Although considered final these specifications are subject to change as further product development and data characterization some times occur PDF 09005aef84f8c349 22 Micron Technology Inc reserves the right to change products or specifications without notice asf36c2gx72pz pdf Rev F 2 15 EN 2012 Micron Technology Inc All rights reserved
24. e ta mask DM function and the TDQS_c pin is not used The TDQS function must be disabled in RDIMM only the mode register for both the x4 and x16 configurations The DM function is supported only in x8 and x16 configurations DM DBI and TDQS are a shared pin and are enabled disabled by mode register settings For more information about TDQS see the DDR4 DRAM component da ta sheet TDQS_t and TDQS_c are not valid for UDIMMs Vpp Supply Module power supply 1 2V TYP Vpp Supply DRAM activating power supply 2 5V 0 125V 0 250V VREFCA Supply Reference voltage for control command and address pins Vss Supply Ground Vit Supply Power supply for termination of address command and control Vpp 2 Vppspp Supply Power supply used to power the 2C bus for SPD RFU Reserved for future use NC No connect No internal electrical connection is present NF No function May have internal connection present but has no function PDF 09005aef84f8c349 asf36c2gx72pz pdf Rev F 2 15 EN 7 Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved Macron 16GB x72 ECC DR 288 Pin DDR4 RDIMM DQ Map DQ Map Table 6 Component to Module DQ Map Front Component Component Reference Component Module Pin Reference Component Module Pin Numbe
25. ee structure where the termination is off the module near the connector Inherent to fly by topology the timing skew between the clock and DQS sig nals can be easily accounted for by using the write leveling feature of DDR4 PDF 09005aef84f8c349 asf36c2gx72pz pdf Rev F 2 15 EN 1 2 Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved In icron 16GB x72 ECC DR 288 Pin DDR4 RDIMM Address Mapping to DRAM Address Mapping to DRAM Address Mirroring To achieve optimum routing of the address bus on DDR4 multi rank modules the ad dress bus will be wired as shown in the table below or mirrored For quad rank mod ules ranks 1 and 3 are mirrored and ranks 0 and 2 are non mirrored Highlighted ad dress pins have no secondary functions allowing for normal operation when cross wired Data is still read from the same address it was written However Load Mode op erations require a specific address This requires the controller to accommodate for a rank that is mirrored Systems may reference DDR4 SPD to determine if the module has mirroring implemented or not See the JEDEC DDR4 SPD specification for more de tails Table 8 Address Mirroring Edge Connector Pin DRAM Pin Non mirrored DRAM Pin Mirrored AO AO AO Al Al Al A2 A2 A2 A3 A3 A4 A4 A4 A3 A5 A5 A6 A6
26. free e Fly by topology Terminated control command and address bus Table 1 Key Timing Parameters Data Rate MT s CL Industry 20 Speed Nomen CL CL CL CL CL CL CL CL CL CL tRCD tRP tRC Grade clature 19 18 17 16 15 14 13 12 11 10 CL 9 ns ns ns 2G6 PC4 2666 2666 2666 2400 2133 2133 1866 1866 1600 1333 14 16 14 16 46 16 2G4 PC4 2400 2400 2400 2400 2133 1866 1866 1600 1600 1333 13 32 13 32 45 32 2G3 PC4 2400 2400 2400 2133 2133 1866 1866 1600 1600 1333 14 16 14 16 46 16 2G1 PC4 2133 2133 2133 1866 1866 1600 1600 1333 13 5 13 5 46 5 PDF 09005aef84f8c349 1 Micron Technology Inc reserves the right to change products or specifications without notice asf36c2gx72pz pdf Rev F 2 15 EN 2012 Micron Technology Inc All rights reserved Products and specifications discussed herein are subject to change by Micron without notice Macron 16GB x72 ECC DR 288 Pin DDR4 RDIMM Features Table 2 Addressing Parameter 16GB Row address 64K A 15 0 Column address 1K A 9 0 Device bank group address 4 BG 1 0 Device bank address per group 4 BA 1 0 Device configuration 4Gb 1 Gig x 4 16 banks Module rank address 2 CS_n 1 0 Table 3 Part Numbers and Timing Parameters 16GB Modules Base devi
27. g 0 75 oik u16 gt 7 amp 31 40 1 230 u11 U13 u15 U17 u19 10 1 224 2 50 0 098 D U12 U14 U18 u20 E 50 0 A 2X e gt P A p 16 1 0 63 9 5 0 374 TYP TYP 4 8 0 789 TYP umuNnnNNNNNONON RAUNA ENON N ONANAN ONNA O NONANO DOODO O NOONA AART ci oneal t E Pin 1 0 75 0 030 R 15 0 059 2 20 0 087 TYP 0 85 0 033 0 60 0 0236 Pin 144 i TYP TYP i 3 35 0 132 TYP D a 72 25 2 84 a TYP 126 65 4 99 TYP Back view 1 25 0 049 x 45 2X X k Z U21 U22 U23 U24 U25 U26 U27 U28 U29 z z _t D 2 z C 3 0 0 118 4x TYP i u31 u U33 u34 U36 U7 U38 4 14605 _____ A a le A 7 2 P C TYP 8 0 0 315 tp Y I fl TTT TTT ET i 0 5 0 0197 TYP i 5 0 3 15 0 124 Pin 288 Se Nain 145 TYP 10 2 0 4 5 95 0 234 TYP 10 2 0 4 22 95 0 90 Typ 22 95 0 9 25 5 1 0 Typ 28 9 1 14 gt TYP TYP TYP TYP 56 10 2 21 64 6 2 54 TYP TYP Notes 1 All dimensions are in millimeters inches MAX MIN or typical TYP where noted 2 The dimensional diagram is for reference only 8000 S Fe
28. icron Technology Inc All rights reserved Macron 16GB x72 ECC DR 288 Pin DDR4 RDIMM Temperature Sensor With SPD EEPROM Operation Temperature Sensor With SPD EEPROM Operation Thermal Sensor Operations EVENT_n Pin The integrated thermal sensor continuously monitors the temperature of the module PCB directly below the device and updates the temperature data register Temperature data may be read from the bus host at any time which provides the host real time feed back of the module s temperature Multiple programmable and read only temperature registers can be used to create a custom temperature sensing solution based on system requirements and JEDEC JC 42 2 The temperature sensor also adds the EVENT_n pin open drain which requires a pull up to Vppspp EVENT_n is a temperature sensor output used to flag critical events that can be set up in the sensor s configuration registers EVENT_n is not used by the serial presence detect SPD EEPROM EVENT_n has three defined modes of operation interrupt comparator and TCRIT In interrupt mode the EVENT_n pin remains asserted until it is released by writing a 1 to the clear event bit in the status register In comparator mode the EVENT_n pin clears itself when the error condition is removed Comparator mode is always used when the temperature is compared against the TCRIT limit In TCRIT only mode the EVENT_n pin is only asserted if the measured temperature exceeds the TCRIT li
29. igh speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal memory bank groups DDR4 SDRAM modules utilizing 4 and 8 bit wide DDR4 SDRAM devices have four internal bank groups consisting of four memory banks each provid ing a total of 16 banks 16 bit wide DDR4 SDRAM devices have two internal bank groups consisting of four memory banks each providing a total of eight banks DDR4 SDRAM modules benefit from DDR4 SDRAM s use of an 8n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I O pins A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n bit wide four clock data transfer at the internal DRAM core and eight corresponding n bit wide one half clock cycle data transfers at the I O pins DDR4 modules use two sets of differential signals DQS_t and DQS_c to capture data and CK_t and CK_c to capture commands addresses and control signals Differential clocks and data strobes ensure exceptional noise immunity for these signals and pro vide precise crossing points to capture input signals DDR4 modules use faster clock speeds than earlier DDR technologies making signal quality more important than ever For improved signal quality the clock control com mand and address buses have been routed in a fly by topology where each clock con trol command and address pin on each DRAM is connected to a single trace and ter minated rather than a tr
30. mit it then re mains asserted until the temperature drops below the TCRIT limit minus the TCRIT hysteresis SPD EEPROM Operation DDR4 SDRAM modules incorporate SPD The SPD data is stored in a 512 byte JEDEC JC 42 4 compliant EEPROM that is segregated into four 128 byte write protectable blocks The SPD content is aligned with these blocks as shown in the table below Block Range Description 0 0 127 000h 07Fh Configuration and DRAM parameters 1 128 255 080h OFFh Module parameters 2 256 319 100h 13Fh Reserved all bytes coded as 00h 320 383 140h 17Fh Manufacturing information 3 384 511 180h 1FFh End user programmable The first 384 bytes are programmed by Micron to comply with JEDEC standard JC 45 Appendix X Serial Presence Detect SPD for DDR4 SDRAM Modules The remaining 128 bytes of storage are available for use by the customer The EEPROM resides on a two wire C serial interface and is not integrated with the memory bus in any manner It operates as a slave device in the IC bus protocol with all operations synchronized by the serial clock Transfer rates of up to 1 MHz are achieva ble at 2 5V NOM Micron implements reversible software write protection on DDR4 SDRAM based mod ules This prevents the lower 384 bytes bytes 0 to 383 from being inadvertently pro grammed or corrupted The upper 128 bytes remain available for customer use and are unprotected PDF 09005aef84f8c349 asf36c2gx72
31. n A14 BG 1 0 BA 1 0 A 16 0 Input parity should be maintained at the rising edge of the clock and at the same time as command and address with CS_n LOW RAS_n A16 CAS_n A15 WE_n A14 Input Command inputs RAS_n A16 CAS_n A15 and WE_n A14 along with CS_n define the com mand and or address being entered and have multiple functions For example for activation with ACT_n LOW these are addresses like A16 A15 and A14 but for a non activation com mand with ACT_n HIGH these are command pins for READ WRITE and other commands de fined in Command Truth Table RESET_n CMOS Input Active LOW asynchronous reset Reset is active when RESET_n is LOW and inactive when RE SET_n is HIGH RESET_n must be HIGH during normal operation SAx Input Serial address inputs Used to configure the temperature sensor SPD EEPROM address range on the I2C bus SCL Input Serial clock for temperature sensor SPD EEPROM Used to synchronize communication to and from the temperature sensor SPD EEPROM on the I2C bus DQx CBx VO Data input output and check bit input output Bidirectional data bus DQ represents DQ 3 0 DQ 7 0 and DQ 15 0 for the x4 x8 and x16 configurations respectively If cyclic re dundancy checksum CRC is enabled via the mode register the CRC code is added at the end of the data burst Any one or all of DQ0 DQ1 DQ2 or DQ3 may be used for monitoring of inter nal Vper level during test via
32. nt Reference Component Module Pin Reference Component Module Pin Number DQ Module DQ Number Number DQ Module DQ Number U21 0 60 128 U22 0 52 117 1 62 135 1 55 269 2 61 273 2 53 262 3 63 280 3 54 124 U23 0 41 253 U24 0 37 240 1 43 260 1 38 102 2 40 108 2 36 95 3 42 115 3 39 247 U25 0 CBO 49 U26 0 28 36 1 CB3 201 1 30 43 2 CB1 194 2 29 181 3 CB2 56 3 31 188 U27 0 21 170 U28 0 13 159 1 22 32 1 14 21 2 20 25 2 12 14 3 23 177 3 15 166 U29 0 5 U30 0 56 130 1 157 1 58 137 2 150 2 57 275 3 2 12 3 59 282 U31 0 48 119 U32 0 45 251 1 51 271 1 46 113 2 49 264 2 44 106 3 50 126 3 47 258 PDF 09005aef84f8c349 asf36c2gx72pz pdf Rev F 2 15 EN Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved Macron 16GB x72 ECC DR 288 Pin DDR4 RDIMM DQ Map Table 7 Component to Module DQ Map Back Continued Component Component Reference Component Module Pin Reference Component Module Pin Number DQ Module DQ Number Number DQ Module DQ Number U33 0 34 104 U34 0 CB6 54 1 32 97 1 CB5 192 2 35 249 2 CB7 199 3 33 242 3 CB4 47 U35 0 25 183 U36 0 18 34 1 27 190 1 17 172 2 24 38 2 19 179 3 26 45 3 16 27 U37 0 9 161 U38 0 5 148 1 11 168 1 6 10 2 16 2 4 3 3 10 23 3 7 155 PDF 09005aef84f8c349 asf36
33. pz pdf Rev F 2 15 EN 1 5 Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved 16GB x72 ECC DR 288 Pin DDR4 RDIMM Electrical Specifications Macron Electrical Specifications Stresses greater than those listed may cause permanent damage to the module This is a stress rating only and functional operation of the module at these or any other condi tions outside those indicated in each device s data sheet is not implied Exposure to ab solute maximum rating conditions for extended periods may adversely affect reliability Table 9 Absolute Maximum Ratings Symbol Parameter Min Max Units Notes Vpp Vpp supply voltage relative to Vss 0 4 1 5 V 1 Vppa Vppq supply voltage relative to Vss 0 4 1 5 V 1 Vpp Voltage on Vpp pin relative to Vss 0 4 3 0 V 2 Vin Vout Voltage on any pin relative to Vss 0 4 1 5 V Table 10 Operating Conditions Symbol Parameter Min Nom Max Units Notes Vpp Vpp supply voltage 1 14 1 20 1 26 V 1 Vpp DRAM activating power supply 2 375 2 5 2 75 V 2 Vrerca pc Input reference voltage 0 49 x Vpp 0 5 x Vpp 0 51 x Vpp V 3 command address bus lyvTr Termination reference current from Vr 750 750 mA Vit Termination reference voltage DC 0 49 x Vpp 0 5 x Vpp 0 51 x Vpp V 4 command address bus 20mV 20mV li Input leakage current any input excluding ZQ
34. r DQ Module DQ Number Number DQ Module DQ Number U1 0 3 157 U2 0 14 21 1 0 5 1 13 159 2 2 12 2 15 166 3 1 150 3 12 14 U3 0 22 32 U4 0 30 43 1 21 170 1 28 36 2 23 177 2 31 188 3 20 25 3 29 181 U5 0 CB3 201 U7 0 38 102 1 CBO 49 1 37 240 2 CB2 56 2 39 247 3 CB1 194 3 36 95 U8 0 43 260 U9 0 55 269 1 41 253 1 52 117 2 42 115 2 54 124 3 40 108 3 53 262 U10 0 62 135 U11 0 6 10 1 60 128 1 5 148 2 63 280 2 7 155 3 61 273 3 4 3 U12 0 11 168 U13 0 17 172 1 9 161 1 18 34 2 10 23 2 16 27 3 8 16 3 19 179 U14 0 27 190 U15 0 CB5 192 1 25 183 1 CB6 54 2 26 45 2 CB4 47 3 24 38 3 CB7 199 U17 0 32 97 U18 0 46 113 1 34 104 1 45 251 2 33 242 2 47 258 3 35 249 3 44 106 PDF 09005aef84f8c349 asf36c2gx72pz pdf Rev F 2 15 EN Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved 16GB x72 ECC DR 288 Pin DDR4 RDIMM Macron DQ Map Table 6 Component to Module DQ Map Front Continued Component Component Reference Component Module Pin Reference Component Module Pin Number DQ Module DQ Number Number DQ Module DQ Number U19 0 51 271 U20 0 58 137 1 48 119 1 56 130 2 50 126 2 59 282 3 49 264 3 57 275 Table 7 Component to Module DQ Map Back Component Compone
35. ts Notes Te Commercial operating case temperature 0 to 85 C 1 2 3 gt 85 to 95 C 1 2 3 4 TOPER Normal operating temperature range 0 to 85 C 5 6 Extended temperature operating range optional gt 85 to 95 C 5 6 Notes 1 Maximum operating case temperature Tc is measured in the center of the package A thermal solution must be designed to ensure the DRAM device does not exceed the maximum Tc during operation Device functionality is not guaranteed if the DRAM device exceeds the maximum Tc dur ing operation If Tc exceeds 85 C the DRAM device must be refreshed externally at 2X refresh a 3 9us interval refresh rate The refresh rate must double when 85 C lt Toper lt 95 C available at micron com For additional information refer to technical note TN 00 08 Thermal Applications PDF 09005aef84f8c349 asf36c2gx72pz pdf Rev F 2 15 EN 1 7 Micron Technology Inc reserves the right to change products or specifications without notice 2012 Micron Technology Inc All rights reserved IA icron 16GB x72 ECC DR 288 Pin DDR4 RDIMM DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR4 component data sheets Component specifications are available at micron com Module speed grades correlate with component speed grades as shown below Table 12 Module and Component Speed Grades DDR4 components may exceed the listed module speed grades

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