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Silicon Power SP002GBLTU133V01 memory module

1. SP002GBLTU160V01 2 PC3 12800 DDR3 1600 11 11 11 SP004GBLTU133V01 2 PC3 8500 DDR3 1066 SP004GBLTU133V01 2 ASB TENS BC3 10600 DDR3 1333 999 256Mx8 2Ranks SP004GBLTU160V01 2 PC3 12800 DDR3 1600 11 11 11 SP004GBLTU133N01 2 4GB 512Mx64 PC3 10600 DDR3 1333 99 9 SP004GBLTU160N01 2 512Mx8 1Rank PC3 12800 DDR3 1600 iti SP008GBLTU133N01 2 8GB 1Gx64 PC3 10600 DDR3 1333 9 9 9 SPOO8GBLTU160N01 2 512Mx8 2Ranks PC3 12800 DDR3 1600 11 11 11 Note 1 This document supports all LTU Series DDR3 240Pin UDIMM products 2 Some item was being EOL in this list Please contact with our sales Dep 3 All part numbers end with a double digit code is for customize use only Example SP001GBLTU133S02 XX 2 Rev 1 5 May 2012 a pee DDR3 UDIMM w o ECC i a L Product Specification Module Specification Kit Package Module Density amp Timing Part Number Bandwidth Data Rate nnec I Bandwidth Data Rate i CAIR SP002GBLTU106S21 2 PC3 8500 DDR3 1066 1GB x 2 Kit Package SP002GBLTU133S21 2 PC3 10600 DDR3 1333 99 9 SP003GBLTU106S31 2 PC3 8500 DDR3 1066 1GB x 3 Kit Package SP003GBLTU133S31 2 PC3 10600 DDR3 1333 99 9 SP004GBLTU106S21 2 PC3 8500 DDR3 1066 SP004GBLTU133S21 2 2GB x 2 Kit Package PC3 10600 DDR3 1333 99 9 SP004GBLTU160S21 2 PC3 12800 DDR3 1600 99 9 SP004GBLTU106V21 2 PC3 8500 DDR3 1066 SP004GBLTU133V21 2 2GB x 2 Kit Package PC3 10600 DDR3 1333 99
2. 9 SP004GBLTU160V21 2 PC3 12800 DDR3 1600 11 11 11 SPOO6GBLTU106S31 2 PC3 8500 DDR3 1066 SP006GBLTU133S31 2 2GB x 3 Kit Package PC3 10600 DDR3 1333 99 9 SPOO6GBLTU160S31 2 PC3 12800 DDR3 1600 99 9 SPOO06GBLTU106V31 2 PC3 8500 DDR3 1066 SPOO6GBLTU133V31 2 2GB x 3 Kit Package PC3 10600 DDR3 1333 99 9 SPO06GBLTU160V31 2 PC3 12800 DDR3 1600 11 11 11 SP008GBLTU106V21 2 PC3 8500 DDR3 1066 SP008GBLTU133V21 2 4GB x 2 Kit Package PC3 10600 DDR3 1333 999 SP008GBLTU133V21 2 PC3 12800 DDR3 1600 11 11 11 SP012GBLTU106V31 2 PC3 8500 DDR3 1066 4GB x 3 Kit Package SP012GBLTU133V31 2 PC3 10600 DDR3 1333 99 9 SP016GBLTU133N21 2 PC3 10600 DDR3 1333 999 8GB x 2 Kit Package SP016GBLTU160N21 2 PC3 12800 DDR3 1600 11 11 11 Note 1 This document supports all LTU Series DDR3 240Pin UDIMM products 2 Some item was being EOL in this list Please contact with our sales Dep 3 All part numbers end with a double digit code is for customize use only Example SPO001GBLTU133S02 XX 3 Rev 1 5 May 2012 a pee DDR3 UDIMM w o ECC i a L Product Specification Pin Assignments 240 Pin UDIMM Front rin ama Tan L Symbol Pin Symbol Pin Symbol_ rs poo 33 pass 63 cki Tas nasar e Daso 6 Dazs 66 von Tas Dasz e vss se vss se nc os vss o Da Taa nc leo voo 99 pase ra pa as nc 73 wes 103 Dase 2 vss so ckeo so vss mo vss 2 vs
3. Drawing x8 2Ranks Front view 133 50 5 256 133 20 5 244 4 0 0 157 MAX 0 75 0 03 R 8x U1 U2 u3 UA US U6 u7 30 5 1 2 29 85 1 175 2 5 0 098 D 2x wa 17 3 0 68 D 2x D A 2 3 0 091 TYP HELL LLLLLII i 760008 1 37 0 054 2 2 0 087 TYP 1 0 0 039 0 8 0 031 9 5 0 374 1 17 0 046 TYP TYP TYP 1 45 0 057 TYP Pin 120 54 68 2 15 TYP 123 0 4 84 TYP Back view 3 0 0 118 4x TYP K aa 5 0 0 197 TYP Pin 121 71 0 2 79 a 61189 TYP ihe Note 1 All dimensions are in millimeters inches MAX MIN or typical TYP where noted Note 2 The dimensional diagram is for reference only 3 05 0 12 Typ TU X Pin 240 T Rev 1 5 May 2012
4. K and CK Clock enable CKE registered HIGH activates and CKE registered LOW deactivates GRES clocking circuitry on the DDR3 SDRAM Data input mask DM is an input mask signal for write data Input data is masked when DM DMO DM7 nol issampled HIGH along with that input data during a write access DM is sampled on both p edges of DQS Although DM pins are input only the DM loading is designed to match that of DQ and DQS7pins ODTO On die termination ODT registered HIGH enables termination resistance internal to the ODT1 Input DDR3 SDRAM When enabled ODT is only applied to the following pins DQ DQS DQS and DM The ODT input will be ignored if disabled via the LOAD MODE command RAS CAS input Command inputs RAS CAS and WE along with S define the command being WE p entered mou Reset RESET is an active LOW CMOS input referenced to Vss The RESET input RESET p receiver is a CMOS input defined as a rail to rail signal with DC HIGH 2 0 8 xVpp and DC LVCMOS LOW lt 0 2 xV a SO S1 reece S enables registered LOW and disables registered HIGH the command SAI2 0 net Presence detect address inputs These pins are used to configure the SPD EEPROM 2 0 nes address range Serial clock for presence detect SCL is used to synchronize the presence detect data transfer to and from the module Data strobe Output with read data input with write data for source synchronous operation DQS0 DQS 7 Edge aligned wit
5. a pee DDR3 UDIMM w o ECC iff ai Product Specification Features e DDR3 functionality and operations supported as defined in the component data sheet e 240pin unbuffered dual in line memory module UDIMM e Fast data transfer rates PC3 8500 PC3 10600 PC3 12800 e Single or Dual rank e 1GB 128 Meg x 64 2GB 256 Meg x 64 4GB 512Meg x 64 8GB 1Giga x 64 e Voo Vppa 1 5V 0 075V e Vppspp 3 0V to 3 6V e Reset pin for improved system stability e Nominal and dynamic on die termination ODT for data strobe and mask signals e Fixed burst chop BC of 4 and burst length BL of 8 via the mode register set MRS e Fly by topology e Terminated control command and address bus e Adjustable data output drive strength e Serial presence detect SPD EEPROM e Gold edge contacts e Pb free 1 Rev 1 5 May 2012 a pee DDR3 UDIMM w o ECC i a L Product Specification Module Specification Single DIMM Package Module Density amp Timing Part Number Bandwidth Data Rate Configuration Bandwidth Data Rate tCL tRCD tRP SP001GBLTU106S01 2 1GB 128Mx64 PC3 8500 DDR3 1066 SP001GBLTU133S01 2 128Mx8 1Rank PC3 10600 DDR3 1333 9 99 SP002GBLTU106S01 2 PC3 8500 DDR3 1066 SP002GBLTU133S01 2 2GB Z36Mx64 T PC3 10600 DDR3 1333 999 128Mx8 2Ranks SP002GBLTU160S01 2 PC3 12800 DDR3 1600 99 9 SP002GBLTU106V01 2 PC3 8500 DDR3 1066 SP002GBLTU133V01 2 PNE 6910900 DDR3 1333 999 2 256Mx8 1Rank
6. h read data center aligned with write data Serial presence detect data SDA is a bidirectional pin used to transfer addresses and data into and out of the SPD EEPROM on the module Supply ma supply 1 5V 0 075V The component Vpp and Vona are connected to the module Temperature sensor SPD EEPROM power supply 3 0V to 3 6V NC No connect These pins are not connected on the module NU Not used These pins are not used in specific module configuration operations Input 7 Rev 1 5 May 2012 a pee DDR3 UDIMM w o ECC K ai i Product Specification Simplified Mechanical Drawing x8 1Rank Front view 2 7 0 106 133 50 5 256 _ MAX 133 20 5 244 me 30 5 1 2 29 85 1 175 17 3 0 68 TYP 2 3 0 091 TYP _ ii ui il HEE U Pin 1 0 76 0 030 R Pe 1 37 0 054 2 2 0 087 TYP 1 0 0 029 0 8 0 031 1 17 0 046 bh Mre 9 5 0 374 2 5 0 098 D 2x TYP a c 54 68 2 15 Pin 120 TYP 123 0 4 84 TYP Back view No Components This Side of Module 3 0 0 118 4x TYP 3 05 0 12 TyP__ Pin 240 kto S 5 0 0 197 TYP Pin 121 TYP TYP Note 1 All dimensions are in millimeters inches MAX MIN or typical TYP where noted Note 2 The dimensional diagram is for reference only 6 Rev 1 5 May 2012 a pee DDR3 UDIMM w o ECC K ai i Product Specification Simplified Mechanical
7. s s ar lse vss me vss a vss s m eo vss mo saz rao Daz eo voo eo Daso i20 vrr 240 Pin UDIMM Back Pin Symbol Pin Symbol Ta Symbol Pin ama 128 Das ise nc fres ao 218 Dasz 210 4 Rev 1 5 May 2012 a pee DDR3 UDIMM w o ECC i a L Product Specification Pin Description Description Address inputs Provide the row address for ACTIVE commands and the column address and auto precharge bit for READ WRITE commands to select one location out of the memory array in the respective bank A10 is sampled during a PRECHARGE command to A0 A14 moui determine whether the PRECHARGE applies to one bank A10 LOW or all banks A10 p HIGH If only one bank is to be precharged the bank is selected by BA A12 is sampled during READ and WRITE commands to determine if burst chop on the fly will be performed The address inputs also provide the opcode during mode register command set 8M A0 A13 Bank address inputs BAO BA1 define to which device bank an ACTIVE READ WRITE BA0 BA2 Input orPRECHARGE command is being applied BAO BA1 define which mode register including MR EMR EMR 2 and EMR 3 is loaded during the LOAD MODE command CKO CKO input Fark CK and CK are differential clock inputs All address and control input signals are CK1 CK1 j Input sampled on the crossing of the positive edge of CK and negative edge of CK Output data DOS and DQS DQS is referenced to the crossings of C

Silicon Power SP002GBLTU133V01 memory module

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