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Intel Core T5470

1. 80 Datasheet Package Mechanical Specifications and Pin Information em D Figure 19 Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Right Side 2 a B lt c m 8 B 6 7 17 18 21 22 8 8 Datasheet 81 m e n tel Package Mechanical Specifications and Pin Information Figure 20 Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Left Side V Dep 58 VSS Deep Das DP 2614 Dep D 63 DIR Dep Dam zl Jg 9 3 5 82 Datasheet Package Mechanical Specifications and Pin Information Figure 21 Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Right Side D 29 1114 DINV O 7 D 12 DIR Dap D 20 D 10 D 13 DO D 18 Dap DINV 1 Die D 22 DA D 15 Datasheet 83 intel Package Mechanical Specifications and Pin Information Table 18 Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name 84
2. Signal Ball Signal Name Ball Signal Ball Name Number Number Name Number A 3 P2 BCLK 0 AN5 D 20 R41 A 4 v4 BCLK 1 A35 D 21 w41 A 5 WI BNR C35 D 22 N43 A 6 T4 4 15 D 23 U41 A 7 AAI BPM 1 AY8 D 24 AA41 A 8 AB4 BPM 2 BA7 D 25 AB40 A 9 T2 BPM 3 5 26 4 AD40 A 10 AC5 BPRI AY2 D 27 AC41 A 11 AD2 BRO L5 D 28 AA43 A 12 AD4 BSEL 0 M2 D 29 Y40 A 13 AAS BSEL 1 A37 D 30 Y44 1414 5 BSEL 2 C37 D 31 T44 A 15 AB2 COMP 0 B38 D 32 AP44 A 16 AC1 COMP 1 AE43 D 33 AR43 A 17 AN1 COMP 2 AD44 D 34 AH40 A 18 AK4 COMP 3 AE1 D 35 AF40 A 19 AG1 D 0 AF2 D 36 AJ43 A 20 AT4 D 1 F40 D 37 AG41 A 21 AK2 D 2 G43 D 38 AF44 A 22 AT2 D 3 E43 D 39 AH44 A 23 AH2 D 4 143 40 4 AM44 A 24 AF4 D 5 H40 D 41 AN43 25 4 AJ5 D 6 H44 D 42 AM40 A 26 AHA D 7 G39 D 43 AK40 A 27 AM4 D 8 E41 D 44 AG43 A 28 AP4 D 9 L41 D 45 AP40 A 29 ARS D 10 K44 D 46 AN41 A 30 AJ1 D 11 N41 D 47 AL41 A 31 AL1 D 12 T40 D 48 AV38 A 32 AM2 D 13 M40 D 49 AT44 A 33 AUS D 14 M44 D 50 AV40 A 34 AP2 D 15 L43 D 51 AU41 A 35 AR1 D 16 P44 D 52 AW41 ADS C7 D 17 40 D 53 AR41 ADSTB 0 M4 D 18 V44 D 54 BA37 ADSTB 1 Y4 D 19 AB44 D 55 BB38 Datasheet Package Mechanical Specifications and Pin Information intel Table 18 Intel Core 2 Duo M
3. Table 17 Pin Listing Table 17 Pin Listing Pin Pin Name Signal Buffer Directi Pin 4 Pin Name Signal Buffer Directi Type on Type on F2 VSS Power Other G25 D 5 Source Synch iid F3 RS 0 Common Clock Input utpu F4 RS 1 Common Clock Input G26 VSS Power Other F5 VSS Power Other H1 ADS Common Clock Su ue F6 RSVD Reserved Input F7 Power Other H2 REQ 1 Source Synch Output F8 VSS Power Other H3 VSS Power Other F9 VCC Power Other E Wee p url H4 LOCK Common Clock Input F10 VCC Power Other Output F11 VSS Power Other H5 DEFER Common Clock Input F12 VCC Power Other H6 VSS Power Other F13 VSS Power Other H21 VSS Power Other F14 VCC Power Other H22 D 12 Source Synch Bue F15 vcc Power Other 7 Input F16 VSS Power Other H23 D 15 Source Synch Output TET vec Power Other H24 VSS Power Other F18 VCC Power Other Input F19 VSS Power Other H25 DINV O Source Synch Output F20 VCC Power Other H26 DSTBP 0 Source Synch Input Input Output F21 DRDY Common Clock Output Input P 11 A 9 Source Synch s t F22 VSS Power Other urpu J2 VSS Power Other F23 D 4 Source Synch bid TY urpu 33 REQ 3 Source Synch p Input Output F24 D 1 Source Synch Output Input P J4 A 3 Source Synch e F25 VSS Power Other F26 D 13 f Source Synch PU ae Ee y Output J6 VCCP Power Other G1 VSS Power Other J21 VCCP Power Other G2 TRDY Common
4. Signal Ball Signal Name Ball Signal Ball Name Number Number Name Number VCCP AG13 VCCP B12 VCCP M14 VCCP AG35 VCCP B14 VCCP N7 VCCP AG37 VCCP B32 VCCP N9 VCCP AH14 VCCP C13 VCCP N11 VCCP AJ7 VCCP C33 VCCP N13 VCCP AJ9 VCCP D12 VCCP N35 VCCP AJ11 VCCP D14 VCCP N37 VCCP AJ13 VCCP D32 VCCP P10 VCCP AJ35 VCCP E11 VCCP P12 VCCP AJ37 VCCP E13 VCCP P14 VCCP AK10 VCCP E33 VCCP P36 VCCP AK12 VCCP E35 VCCP P38 VCCP AK14 VCCP F12 VCCP R7 VCCP AK36 VCCP F14 VCCP R9 VCCP AK38 VCCP F34 VCCP R11 VCCP AL7 VCCP F36 VCCP R13 VCCP AL9 VCCP G11 VCCP R35 VCCP AL11 VCCP G13 VCCP R37 VCCP AL13 VCCP G35 VCCP T14 VCCP AL35 VCCP H12 VCCP U7 VCCP AL37 VCCP H14 VCCP U9 VCCP AN7 VCCP H36 VCCP U11 VCCP AN9 VCCP 111 VCCP U13 VCCP AN11 VCCP J13 VCCP U35 VCCP AN13 VCCP J35 VCCP U37 VCCP AN35 VCCP 137 VCCP V10 VCCP AN37 VCCP K10 VCCP V12 VCCP AP10 VCCP K12 VCCP V14 VCCP AP12 VCCP K14 VCCP V36 VCCP AP36 VCCP K36 VCCP V38 VCCP AP38 VCCP K38 VCCP W7 VCCP AR7 VCCP L7 VCCP WO VCCP AR9 VCCP L9 VCCP Wii VCCP AR11 VCCP L11 VCCP W13 VCCP AR13 VCCP L13 VCCP W35 VCCP AU11 VCCP L35 VCCP W37 VCCP AU13 VCCP L37 VCCP Y14 Datasheet Package Mechanical Specifications and Pin Information intel Table 18 Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Datasheet Signal Ba
5. Table 16 Pin Name Listing Table 16 Pin Names Dieting Signal Signal e Pin Name Pin Buffer Direction PiniName Pins Burer Direction Type Type Source Input Source Input A 24 R4 A 3 J4 Synch Output Synch Output Source Input Source Input A 25 T5 A 4 L5 Synch Output Synch Output Source Input Source Input A 26 T3 A 5 L4 Synch Output Synch Output Source Input Source Input A 27 W2 A 6 K5 Synch Output Synch Output Source Input Source Input A 28 w5 A 7 M3 Synch Output Synch Output Source Input Source Input A 29 Y4 A 8 N2 Synch Output Synch Output Source Input Source Input A 30 U2 A 9 11 Synch Output Synch Output Source Input Source Input A 31 V4 A 10 N3 Synch Output Synch Output Source Input Source Input A 32 W3 A 11 P5 Synch Output Synch Output Source Input Source Input A 33 AA4 A 12 P2 Synch Output Synch Output Source Input Source Input A 34 AB2 A 13 L2 Synch Output Synch Output Source Input Source Input A 35 AA3 A 14 P4 Synch Output Synch Output Source Input A20M A6 CMOS Input A 15 P1 Synch Output Common Input ADS HI Clock Output Source Input A 16 RI Synch Output Source Input y H ADSTB O M1 P Synch Output Source Input A 17 Y2 Synch Output Source Input ADSTB 1 V1 Synch Output A 18 U5 Source Input Synch Output BCLK 0 A22 Bus Clock Input A 19 4 R3 Source Input BCLK 1 A21 Bus Clock Input Sy
6. sc 00000000000000000000000000 00000000000000000000000000 0000000000000000000000000 ee f S869 Je 16 MAIA JAIS COO O00 XXEOXXXOX3XOO0O0O0O0ooOdgug MAIA dOL Xt 3NOZ Xb INOZ 1 433 YINYOD 1 d334 3533 00 Xt Nm 002 Xr Datasheet 56 intel Package Mechanical Specifications and Pin Information 59088 10 65 98 CD og EE DVO aisvascvo amp omvasrvo t aisva recor tH Deg PEZ OT M SISVE 89v 07 Ze omvassvoz zeen soen 54 ert j 9260 vl t SLNIWWOD 998 15 soz setz g TOSWAS SYSLIWITIIW Intel Core 2 Duo Mobile Processor POP and LV Die Micro FCBGA Processor Package Drawing Figure 14 b tv Ob BEDE PEZE OE BZ IZ HZ OC BT ST HT ZT OL 8 9 v Z 53 956 v58 SL 32S a TIvlad Buiuedo 1siseu 1epios zu gege 00 ejeureiq PPN 009900 MIIA WOLLOG T H gt ES O 0 0 0 0 0 0 0 0 0 EE SC EG my 1009005050590 000 0 s Ce Ev Ty LE SE EE TE GZ Z SZ ELIZ GT LT STETTTG LS E T Y lt f z Sb 31905 Yy 110130 g viaa aas
7. DPSLP when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state To return to the Sleep State DPSLP must be deasserted DPSLP is driven by the ICH9M DPSLP Input DPWR is a control signal used by the chipset to reduce power on the processor data bus input buffers The processor drives this pin during dynamic FSB frequency switching Input DPWR Output DRDY Data Ready is asserted by the data driver on each data Input transfer indicating valid data on the data bus In a multi common Output clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of both FSB agents DRDY Data strobe used to latch in D 63 0 Signals Associated Strobe DSTBN 3 0 D 15 0 DINV O DSTBN 0 D 31 16 DINV 1 DSTBN 1 D 47 32 DINV 2 DSTBN 2 D 63 48 DINV 3 DSTBN 3 Datasheet 95 intel Package Mechanical Specifications and Pin Information Table 19 Signal Description Sheet 4 of 8 Name Type Description DSTBP 3 0 Input Output Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DINV 0 Z DSTBP 0 D 31 16 DINV 1 DSTBP 1 D 47 32 DINV 2 DSTBP 2 D 63 48 DINV 3 DSTBP 3 FERR PBE Output FERR Floating point Error PBE
8. 0 0 0 0 000 OO 0 EES z2 z25o0uo ES HY py 000 0 0 0 0 0 0 0 1090505004000 0 000 S w xS e SEENEN ay NY RRS RRR RM Di 0 Av 050 0 O OT aa COO 28 Th S an aqeasqns 9682284 iapun Axod3 aa 3 335 MAIA 4 La di iannnanaaaanana F d MIIA dOL Fa gt ke J M3IA JAIS gt 39vXoVd gt lt 0 v T Oo 57 Datasheet Package Mechanical Specifications and Pin Information Intel Core 2 Duo Mobile Processor ULV SC and ULV DC Die Micro FCBGA Processor Package Drawing intel Figure 15 3 10 8598 Sy 31V2S V uviaa E EE EE GJ a t 2ISva 94 ISV 94 DISV8 tu vlt toog T alavi rroal 2Isvevezor H d DIsVa 89v 0z SM 956 e Ee z v58 sjensqns 9681284 9 SZ NYS jlysepun Axod3 sse o soz o Sy guia Buiuedo 15 56 opgoe Loot j 2z0 0 6 00 A al 9260 S ue 2 M3IA 898 00000
9. 6 9 A i Ipca Icc Intel Enhanced Deeper Sleep State 5 9 A IppwpN Icc Deep Power Down Technology State C6 Ss 3 5 A i Vcc Power Supply Current Slew Rate at Processor dIcc or Package Pin 600 mA us 7 9 IccA Icc for Veca Supply 130 mA I Icc for Vccp Supply before Vec Stable u 4 5 10 CER Icc for VecpSupply after Vcc Stable 2 5 A 11 NOTES 1 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note Datasheet 37 SEU Ie 10 11 12 i n tel Electrical Specifications that this differs from the VID employed by the processor during a power management event Intel Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Enhanced Halt State The voltage specifications are assumed to be measured across Vcc sense and Vss sense pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe Specified at 105 C T Specified at the nominal Vcc Measured at the bulk capacitors on the motherboard Vcc Boor tolerance shown in Figure 7 and Figure 8 Based on simulations an
10. REQ RSP par ALLEL imb 0006000 uel 7 pE E i 7 BCLK 133 MHz NOTES 1 All common clock signals will be active for two BCLKs instead of one e g ADS HIT 2 The double pumped signal strobes will have only one transition per BCLK when active instead of two 3 The quad pumped signal strobes will have only two transitions per BCLK when active instead of four 4 Same setup and hold times apply but relative to every second rising BCLK 5 Following a RESET the bus will be in the legacy full frequency mode 6 There will not be a down shift right after RESET deassertion 7 There is no backing out of a transition into or out of half frequency mode Once the sequence starts it must be completed Enhanced Intel amp Dynamic Acceleration Technology The processor supports Intel Dynamic Acceleration Technology mode The Intel Dynamic Acceleration Technology feature allows one core of the processor to operate at a higher frequency point when the other core is inactive and the operating system requests increased performance This higher frequency is called the opportunistic frequency and the maximum rated operating frequency is the ensured frequency The processor includes a hysteresis mechanism that improves overall Intel Dynamic Acceleration Technology performance by decreasing unnecessary transitions of the cores in and out of Intel Dynamic Acceler
11. 1 7 W 2 8 Poca Intel Enhanced Deeper Sleep state Power 1 3 Ww 2 8 Intel Deep Power Down Power 0 3 Ww 8 Tj Junction Temperature 0 105 S 3 4 NOTES 1 The TDP specification should be used to design the processor thermal solution The TDP is not the maximum theoretical power the processor can generate 2 Not 100 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum has been reached 4 The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 5 Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser than TDP in HFM 6 At Tj of 105 C 7 At Tj of 50 C 8 At Tj of 35 C Datasheet e Thermal Specifications and Design Considerations n tel Table 22 Power Specifications for the Dual Core Low Power Standard Voltage Processors 25W in Standard Package Processor Thermal Design R Symbol M mbar Core Frequency amp Voltage Power Unit Notes P9700 2 8 GHZ amp VCCHFM 25 P9600 2 667 GHZ amp VCCHFM 25 P8800 2 667 GHZ amp VCCHFM 25 P9500 2 53 GHz amp VccHFM 25 14 TDP P8700 2 53 GHz amp Vcc
12. cong mer Of 36 A has to be sustained for short time wer of 35 us Average current will be less than maximum specified Iccpgs VR OCP threshold should be high enough to support current levels described herein Datasheet 39 intel Electrical Specifications Table 11 Voltage and Current Specifications for the Dual Core Ultra Low Voltage SFF Processor Symbol Parameter Min Typ Max Unit Notes Vcc in Enhanced Intel Dynamic Acceleration E VCCDAM Technology Mode 0 8 1 1625 V 1 2 VCcCHFM Vcc at Highest Frequency Mode HFM 0 775 1 1 1 VccLFM Vcc at Lowest Frequency Mode LFM 0 8 0 975 V 1 VccsLFM Vcc at Super Low Frequency Mode Super LFM 0 725 0 925 V 1 Vcc BOOT Default Vcc Voltage for Initial Power Up 1 20 V 2 6 8 Vccp AGTL Termination Voltage 1 00 1 05 1 10 V VCCA PLL Supply Voltage 1 425 1 5 1 575 V Vcc at Deeper Sleep 0 65 0 8 V 1 Vbpc4 Vcc at Intel Enhanced Deeper Sleep State 0 6 em 0 8 V 1 VccpPPwpN Vcc at Deep Power Down Technology State C6 0 35 0 6 V 1 Iccpes Icc for Processors Recommended Design Target 18 A 5 Processor Number Core Frequency Voltage SU9600 1 6 GHz Vccurew 18 Icc SU9400 1 4 GHz Vccurw 18 SU9300 1 2 GHz amp VCcCHFM 18 A 3 4 12 1 2 GHz amp VCCLFM 18 0 8 GHz amp VCcCSLFM 13 I Icc Auto Halt amp Stop Grant me HFM 6 3 A 3 4 12 SGNT SuperLFM 4 4
13. 11 5mV 3mV 0 5000V lt Vcc cone lt 0 7500V Total tolerance window including ripple is 35mV for C6 0 3000V lt Vcc cone lt 0 5000V NOTE Deeper Sleep mode tolerance depends on VID value Datasheet 44 Electrical Specifications n tel Figure 6 Datasheet Deeper Sleep Vcc and Icc Loadline for Low Power Standard Voltage Processors Vcc cone V Slope 4 0 mV A at package VccSense VssSense pins Differential Remote Sense required Vcc cone max HFM LFM Voc core pc max HFM LF Vcc cone nom HFM LFM Voccog pc in Le HFMILFM Vcc cone Tolerance V min EECH VR St Pt Error 1 Icc coRE A 0 Icc cone Max HFM LFM Note 1 Vcc cone Set Point Error Tolerance is per below Tolerance VID Voltage Range VID 1 5 3mV Vcc cone gt 0 7500V 11 5mV 3mV 0 5000V lt Vcc cone lt 0 7500V Total tolerance window including ripple is 35mV for C6 0 3000V lt Vcc cone lt 0 5000V NOTES 1 Applies to low power standard voltage 22 mm dual core processors 2 Deeper Sleep mode tolerance depends on VID value 45 Electrical Specifications Active VCC and ICC Loadline for Low Voltage Ultra Low Voltage and Power Figure 7 Optimized Performance Processor Vcc coRE V Slope 4 0 mV A at package VccSense VssSense pins Differential Remote Sense required Vcc core max HFM LFM Voc core
14. at VccurM 0 7 W 2 5 8 at Vccsi EM 0 6 PppnsiP Deeper Sleep Power 0 4 W 2 8 Poca Intel Enhanced Deeper Sleep state Power 0 3 WwW 2 8 Pce Intel Deep Power Down Power 0 2 W 2 8 Tj Junction Temperature 0 100 C 3 4 NOTES 1 The TDP specification should be used to design the processor thermal solution The TDP is not the maximum theoretical power the processor can generate 2 Not 100 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum T has been reached 4 The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 5 Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser than TDP in HFM 6 At Tj of 100 C 7 At Tj of 50 C 8 At Tj of 35 C Datasheet 107 m n tel Thermal Specifications and Design Considerations 5 1 5 1 1 Table 27 108 Monitoring Die Temperature The processor incorporates three methods of monitoring die temperature Thermal Diode Intel Thermal Monitor Digital Thermal Sensor Thermal Diode Intel s processors utilize an SMBus thermal sensor to read back the voltage current characteristics of a sub
15. intel Package Mechanical Specifications and Pin Information Table 16 Pin Name Listing Table 16 Pin Name Listing Signal Signal Pin Name Pin Buffer Direction Pin Name Pin Buffer Direction Type Type vss AA2 e vss AC14 pod vss AA5 E vss AC16 pud vss AAS pesi vss AC19 posa vss AA11 GE vss AC21 jussi vss AA14 vss AC24 n vss AA16 vss AD2 uL vss AA19 pee vss ADS vss AA22 For vss AD8 Ee vss AA25 bid vss AD11 vss AB1 dee vss AD13 Ee vss AB4 ud vss AD16 pos vss AB8 d vss AD19 pata vss AB11 SE vss AD22 Pond vss AB13 Ge vss AD25 ra vss AB16 vss AE1 Pod vss AB19 vss AE4 Pied vss AB23 cae vss AE8 pd vss AB26 Ge vss AE11 SS vss AC3 pod vss AE14 bud vss AC6 poids vss AE16 bends vss AC8 SE vss AE19 eis vss AC11 podus vss AE23 psi Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Table 16 Pin Name Listing Table 16 Pin Name Listing Signal Signal Pin Name Pin Buffer Direction Pin Name Pin Buffer Direction Type Type vss AE26 pod vss C14 vss AF2 Pad vss C16 Geer vss AF6 vss C19 pid vss AF8 ad vss C22 vss AF11 pud vss C25 c vss AF13 ond vss D1 c vss AF16 biel vss D4 pod vss AF19 E vss D8 Pd vss AF21 EL vss D11 pat vss AF25 Ge vss D13 e vss B6 vss D16 pad vss B8 vss
16. vec vss vcc vec vss vec DRDY VSS D 4 amp 114 VSS 1313 F e VCCP Dep VSS D 9 4 D 5 vss G H vss D 12 f D 15 vss DINV O DAR l H J VCCP vss D 11 D 10 vss E J K VCCP D 14 VSS D 8 4 D 17 vss L vss D 22 D 20 vss DI29 ra L M VCCP vss D 23 D 21 vss EI M N VCCP D 16 VSS DINV 1 D 31 vss N P VSS D 26 amp D 25 vss D 24 18 4 P R VCCP vss D 19 D 28 vss R T VCCP D 37 VSS D 27 D 30 vss U vss DINV 2 D 39 vss DI38 COMPL U VCCP VSS D 36 D 34 VSS D 35 amp V w VCCP D 41 4 VSS D 43 D 44 vss w Y vss D 32 D 42 vss D 40 DE Y aa vss vss vec vss vcc D 50 vss D 45 D 46 vss ud A AB vcc vss vec vec vss vcc 5211 D 51 vss D 33 amp D 47 4 vss AC vss vcc vss vec vec vss DINY 3 vss D 60 D 63 vss 5714 5314 A vec vec vss vec vss 5413 5914 vss p e1 amp D 49 vss GTLREF vss vss vec vec vss vcc D 58 D 55 vss p 48 amp PSTBN 3 vss A vcc vcc vss vec vec vss vec vss 62 4 ppsepe vss TESTA 14 15 16 17 18 19 20 21 22 23 24 25 26 60 Datasheet Package Mechanical Specifications and Pin Information Datasheet intel
17. 1 1 V 1 2 Vcc at Super Low Frequency Mode Super LFM 0 75 0 95 V 1 Vcc Boor Default Vcc Voltage for Initial Power Up 1 2 V 2 Vccp AGTL Termination Voltage 1 0 1 05 1 1 V VccA PLL Supply Voltage 1 425 1 5 1 575 V VccpPnsiP Vcc at Deeper Sleep 0 65 0 85 1 2 Vpc4 Vcc at Intel Enhanced Deeper Sleep State 0 6 0 85 V 1 2 VccpPPwbN Vcc at Deep Power Down Technology State C6 0 35 0 7 V 1 2 Iccpgs Icc for Processors Recommended Design Target 47 A 12 Icc for Processors Processor Number Core Frequency Voltage T9900 3 06 GHZ amp VccHFM 47 Icc T9800 2 93 GHz amp VCccHFM 47 T9600 2 80 GHz amp VccHFM 47 T9550 2 66 GHz Vecuem 47 A 3 4 10 T9400 2 53 GHz amp VccHFM 47 1 6 GHz amp VccLFM 31 4 0 8 GHz amp VCcCSLFM 22 4 I Icc Auto Halt amp Stop Grant Sh HFM 25 4 A 3 4 10 SCNT SuperLFM 13 7 Icc Sleep Isi p HFM 24 7 A 3 4 10 SuperLFM 13 5 Icc Deep Sleep Ipsip HFM 22 9 A 3 4 10 SuperLFM 13 0 Ippgsip Icc Deeper Sleep C4 11 7 A Ipca Icc Intel Enhanced Deeper Sleep 10 5 A j Ippwon Icc Deep Power Down Technology State C6 5 7 A 1 Vcc Power Supply Current Slew Rate at Processor _ _ dIcc pr Package Pin 600 mA us 5 7 Icc for VCCA Supply 130 mA I Iccc for Vccp Supply before Vcc Stable 4 5 A 8 CER Icc for Vccp Supply after Vcc Stable 2 5 A 9 NOTES See next page 34 Datasheet
18. CC3 CC4 CC6 VID x provides the ability for the processor to request core voltage level reductions greater than one VID tick The amount of VID tick reduction is fixed and only occurs while the processor is in Intel Dynamic Acceleration Technology mode This improved voltage regulator efficiency during periods of reduced power consumption allows for leakage current reduction which results in platform power savings and extended battery life When in Intel Dynamic Acceleration Technology mode it is possible for both cores to be active under certain internal conditions In such a scenario the processor may draw a Instantaneous current cong 1 for a short duration of tryst however the average Icc current will be lesser than or equal to Iccpgs current specification Please refer to the Processor DC Specifications section for more details Processor Power Status Indicator PSI 2 Signal The processor incorporates the PSI signal that is asserted when the processor is in a reduced power consumption state PSI can be used to improve intermediate and light load efficiency of the voltage regulator resulting in platform power savings and extended battery life The algorithm that the processor uses for determining when to assert PSI is different from the algorithm used in previous mobile processors PSI 2 functionality is expanded further to support three processor states e Both cores are in idle state Only one core active state e B
19. INTR NMI PREQ RESET SMI or APIC interrupt core state break halt break OR Monitor event AND STPCLK high not asserted t STPCLK assertion and de assertion have no effect if a core is in C2 C3 or C4 Core C4 state supports the package level Deep C4 sub state P LVL5 P LVL6 read is issued once the L2 cache is reduced to zero 12 Datasheet Low Power Features Figure 2 Table 1 2 1 1 2 1 1 1 2 1 1 2 Datasheet intel Package Low Power States ge 4009 STPCLK asserted A S a Stop Deep Deeper Sleep Normal SLP asserted E DPSLP asete cm DPRSTP asserted SC e Grant Sleep n J Sleep A uu STPCLK deasserted S so SLP deasserted K Grape deasserte J DPRSTPS deasserted __ e Snoop Snoop serviced occurs Lt S Stop Grant Snoop Wu o Deeper Sleep includes the Deeper Sleep state Deep C4 sub state and C6 Coordination of Core Low Power States at the Package Level Package State Core1 State C4 Deep Power Down CoreO State co cit c2 c3 Technology State Code Named C6 State CO Normal Normal Normal Normal Normal cii Normal Normal Normal Normal Normal C2 Normal Normal Stop Grant Stop Grant Stop Grant C3 Normal Normal Stop Grant Deep Sleep Deep Sleep Deeper Sleep Intel te Deep Power Normal Normal Stop
20. Pending Break Event is a multiplexed signal and its meaning is qualified with STPCLK When STPCLK is not asserted FERR PBE indicates a floating point when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using Microsoft MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state When FERR PBE is asserted indicating a break event it will remain asserted until STPCLK is deasserted Assertion of PREQ when STPCLK is active will also cause an FERR break event For additional information on the pending break event functionality including identification of support of the feature and enable disable information refer to Volumes 3A and 3B of the Inte 64 and IA 32 Architectures Software Developer s Manuals and the Inte Processor Identification and CPUID Instruction application note GTLREF Input GTLREF determines the signal reference level for AGTL input pins GTLREF should be set at 2 3 GTLREF is used by the AGTL receivers to determine if a signal is a logical 0 or logical 1 HIT HITM Input Output Input Output HIT Snoop Hit and HITM Hit Modified convey transacti
21. Table 19 100 Package Mechanical Specifications and Pin Information Signal Description Sheet 8 of 8 Name Type Description VCCSENSE Output VCCSENSE together with VSSSENSE are voltage feedback signals that control the 2 1 mQ loadline at the processor die It should be used to sense voltage near the silicon with little noise VID 6 0 Output VID 6 0 Voltage ID pins are used to support automatic selection of power supply voltages Vcc Unlike some previous generations of processors these are CMOS signals that are driven by the processor The voltage supply for these pins must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID pins becomes valid The VID pins are needed to support the processor voltage specification variations See Table 2 for definitions of these pins The VR must supply the voltage that is requested by the pins or disable itself VSSSENSE Output VSSSENSE together with VCCSENSE are voltage feedback signals that control the 2 1 mQ loadline at the processor die It should be used to sense ground near the silicon with little noise 8 Datasheet m e Thermal Specifications and Design Considerations n tel 5 Caution Table 20 Datasheet Thermal Specifications and Design Considerations A complete thermal solution includes both component and system level thermal ma
22. amp Vecsirm 24 32 Datasheet Electrical Specifications i n tel Table 6 Voltage and Current Specifications for the Dual Core Extreme Edition Processors Sheet 2 of 2 Symbol Parameter Min Typ Max Unit Notes I Icc Auto Halt amp Stop Grant rid HFM 29 7 A 3 4 10 dd SuperLFM 16 7 Icc Sleep Isip HFM 28 8 A 3 4 10 SuperLFM 16 5 Icc Deep Sleep Ipsip HFM 26 8 A 3 4 10 SuperLFM 16 0 IDPRSLP Icc Deeper Sleep C4 z 12 2 A 3 4 Ipc4 Icc Intel Enhanced Deeper Sleep State 11 7 A 3 4 Ippwon Icc Deep Power Down Technology State C6 11 0 A 3 4 Vcc Power Supply Current Slew Rate at zZ dIccyor Processor Package Pin and MADS Zeg IccA Icc for VCCA Supply mE 130 mA I Icc for Vccp Supply before Vcc Stable u 4 5 A 8 Icc for Vccp Supply after Vec Stable 2 5 A 9 NOTES 1 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Intel Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Enhanced Halt State 2 The voltage specifications are assumed to be measured across Vcc_sense and sense pin
23. at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum T has been reached 4 The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 5 Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser than TDP in HFM 6 At Tj of 105 C 7 At Tj of 50 C 8 At Tj of 35 C Datasheet 105 n tel Thermal Specifications and Design Considerations Table 25 Power Specifications for the Dual Core Ultra Low Voltage ULV Processors Symbol ol Core Frequency amp Voltage Unit Notes SU9600 1 4 GHz amp HFM Vcc 10 SU9400 1 4 GHz amp HFM Vcc 10 TDP SU9300 1 2GHz amp HFM Vcc 10 w fh e gt 1 2 GHz Super LFM Vcc 10 0 8 GHz Super LFM Vcc 8 Symbol Parameter Min Typ Max Unit Notes Pau Auto Halt Stop Grant Power PSGNT at VCCHFM mE 2 9 Ww 2 5 7 at Vccsi EM 1 6 Sleep Power 2 5 Psip at VccurM 8 1 W 2 5 7 at Vccsi EM Deep Sleep Power Ppsip at VCcCHFM 1 3 Ww 2 5 8 at Vccsi EM 0 9 PppnsiP Deeper Sleep Power 0 6 W 2 8 Poca Intel Enhanced Deeper Sleep state Power 0 4 WwW 2 8 Intel Deep Power Down Power 0 25 Ww 2 8 Tj Junction Temperature 0 105 SC 3 4 NOTES 1 The TDP spe
24. is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 Vu and Voy may experience excursions above Vccp However input signal drivers must comply with the signal quality specifications 5 This is the pulldown driver resistance Measured at 0 31 Vccp Ron min 0 418 Rz Ron typ 0 455 Ron max 527 Rrr typical value of 55 Q is used for Roy typ min max calculations 6 GTLREF should be generated from Vccp with a 1 tolerance resistor divider The Vccp referred to in these specifications is the instantaneous Vccp 7 Rrr is the on die termination resistance measured at Vo of the AGTL output driver Measured at 0 31 Vccp Rrr is connected to Vccp on die Refer to processor I O buffer models for I V characteristics 8 Specified with on die Ry and Roy turned off Vin between 0 and Vccp 9 Cpad includes die capacitance only No package parasitics are included 10 This is the external resistor on the comp pins 11 On die termination resistance measured at 0 33 Vccp 12 Applies to Signals A 35 3 13 Applies to Signals D 63 0 14 Applies to Signals BPRIZ DEFER PREQ PREST RS 2 0 TRDY ADS BNR BPM 3 0 BRO 48 DBSY DRDY HIT HITM LOCK PRDY DPWR DSTB 1 0 DSTBP 3 0 and DSTBN 3 0 Datasheet Electrical Specifications Table 14 C
25. register block mapped in the processor s I O address space The P_LVLx I O reads are converted to equivalent MWAIT C state requests inside the processor and do not directly result in I O reads on the processor FSB The P_LVLx I O Monitor address does not need to be set up before using the P_LVLx I O read interface The sub state hints used for each P_LVLx read can be configured through the IA32_MISC_ENABLES model specific register MSR If a core encounters a GMCH break event while STPCLK is asserted it asserts the PBE output signal Assertion of PBE when STPCLK is asserted indicates to system logic that individual cores should return to the CO state and the processor should return to the Normal state Figure 1 shows the core low power states and Figure 2 shows the package low power states for the processor Table 1 maps the core low power states to package low power states 11 Low Power Features intel Figure 1 Core Low Power States Grant STPCLK 8 STPCLK asserted deasserted STPCLK STPCLK deasserted STPCLK asserted n Spt deasserted TPCLK caymwart asserted Se Core state utr inst SS break instruction MWAIT C1 Halt break 1 co IA P_LVL2 or MWAIT C2 u Core State SES A Core state P LVLA or break P LVL5 P LVL6 LVL3 or MWAIT C4 C6 Core MWAIT C3 state ca C6 break A y c3 halt break A20M transition INIT
26. 0 0 0 0 1 0 0 6750 1 0 0 0 0 1 1 0 6625 1 0 0 0 1 0 0 0 6500 1 0 0 0 1 0 1 0 6375 1 0 0 0 1 1 0 0 6250 1 0 0 0 1 1 1 0 6125 1 0 0 1 0 0 0 0 6000 1 0 0 1 0 0 1 0 5875 1 0 0 1 0 1 0 0 5750 1 0 0 1 0 1 1 0 5625 1 0 0 1 1 0 0 0 5500 1 0 0 1 1 0 1 0 5375 1 0 0 1 1 1 0 0 5250 1 0 0 1 1 1 1 0 5125 1 0 1 0 0 0 0 0 5000 1 0 1 0 0 0 1 0 4875 1 0 1 0 0 1 0 0 4750 1 0 1 0 0 1 1 0 4625 1 0 1 0 1 0 0 0 4500 1 0 1 0 1 0 1 0 4375 1 0 1 0 1 1 0 0 4250 ntel 27 intel Table 2 28 Voltage Identification Definition Sheet 3 of 3 Electrical Specifications VID6 VID5 VID4 VID3 VID2 VID1 VIDO Vcc V 1 0 1 0 1 1 1 0 4125 1 0 1 1 0 0 0 0 4000 1 0 1 1 0 0 1 0 3875 1 0 1 1 0 1 0 0 3750 1 0 1 1 0 1 1 0 3625 1 0 1 1 1 0 0 0 3500 1 0 1 1 1 0 1 0 3375 1 0 1 1 1 1 0 0 3250 1 0 1 1 1 1 1 0 3125 1 1 0 0 0 0 0 0 3000 1 1 0 0 0 0 1 0 2875 1 1 0 0 0 1 0 0 2750 1 1 0 0 0 1 1 0 2625 1 1 0 0 1 0 0 0 2500 1 1 0 0 1 0 1 0 2375 1 1 0 0 1 1 0 0 2250 1 1 0 0 1 1 1 0 2125 1 1 0 1 0 0 0 0 2000 1 1 0 1 0 0 1 0 1875 1 1 0 1 0 1 0 0 1750 1 1 0 1 0 1 1 0 1625 1 1 0 1 1 0 0 0 1500 1 1 0 1 1 0 1 0 1375 1 1 0 1 1 1 0 0 1250 1 1 0 1 1 1 1 0 1125 1 1 1 0 0 0 0 0 1000 1 1 1 0 0 0 1 0 0875 1 1 1 0 0 1 0 0 0750 1 1 1 0 0 1 1 0 0625 1 1 1 0 1 0 0 0 0500 1 1 1 0 1 0 1 0 0375 1
27. 1 0 0 1 3500 0 0 0 1 1 0 1 1 3375 0 0 0 1 1 1 0 1 3250 0 0 0 1 1 1 1 1 3125 0 0 1 0 0 0 0 1 3000 0 0 1 0 0 0 1 1 2875 0 0 1 0 0 1 0 1 2750 0 0 1 0 0 1 1 1 2625 0 0 1 0 1 0 0 1 2500 0 0 1 0 1 0 1 1 2375 0 0 1 0 1 1 0 1 2250 0 0 1 0 1 1 1 1 2125 0 0 1 1 0 0 0 1 2000 0 0 1 1 0 0 1 1 1875 0 0 1 1 0 1 0 1 1750 0 0 1 1 0 1 1 1 1625 0 0 1 1 1 0 0 1 1500 0 0 1 1 1 0 1 1 1375 0 0 1 1 1 1 0 1 1250 0 0 1 1 1 1 1 1 1125 0 1 0 0 0 0 0 1 1000 0 1 0 0 0 0 1 1 0875 0 1 0 0 0 1 0 1 0750 0 1 0 0 0 1 1 1 0625 0 1 0 0 1 0 0 1 0500 0 1 0 0 1 0 1 1 0375 0 1 0 0 1 1 0 1 0250 0 1 0 0 1 1 1 1 0125 Datasheet Electrical Specifications Table 2 Datasheet Voltage Identification Definition Sheet 2 of 3 VID6 VID5 VID4 VID3 VID2 VID1 VIDO Vcc V 0 1 0 1 0 0 0 1 0000 0 1 0 1 0 0 1 0 9875 0 1 0 1 0 1 0 0 9750 0 1 0 1 0 1 1 0 9625 0 1 0 1 1 0 0 0 9500 0 1 0 1 1 0 1 0 9375 0 1 0 1 1 1 0 0 9250 0 1 0 1 1 1 1 0 9125 0 1 1 0 0 0 0 0 9000 0 1 1 0 0 0 1 0 8875 0 1 1 0 0 1 0 0 8750 0 1 1 0 0 1 1 0 8625 0 1 1 0 1 0 0 0 8500 0 1 1 0 1 0 1 0 8375 0 1 1 0 1 1 0 0 8250 0 1 1 0 1 1 1 0 8125 0 1 1 1 0 0 0 0 8000 0 1 1 1 0 0 1 0 7875 0 1 1 1 0 1 0 0 7750 0 1 1 1 0 1 1 0 7625 0 1 1 1 1 0 0 0 7500 0 1 1 1 1 0 1 0 7375 0 1 1 1 1 1 0 0 7250 0 1 1 1 1 1 1 0 7125 1 0 0 0 0 0 0 0 7000 1 0 0 0 0 0 1 0 6875 1
28. 1 2 5 Stop Grarit SNOOP EE 16 2 1 2 4 Sleep State exse kde pex ge RC a 16 2 1 2 5 Deep Sleep State iiir che teme rne tke Pl ERAT E Ru ER Seen 16 2 1 2 6 Deeper Sleep St tte s tanen nane nun ENER KK 17 2 2 Enhanced Intel SpeedStep Technology 19 2 3 Extended Low Power States sisse RE NENNEN ENNER NENNEN NENNEN sese kai nad 20 2 4 FSB Low Power NK hayan hase hu NENNEN nad dn 21 2 4 1 Dynamic FSB Frequency Switching esses nemen 21 2 4 2 Enhanced Intel Dynamic Acceleration Technology eese 22 PEE DCN 23 2 6 Processor Power Status Indicator PSI 2 5 8 23 3 Electrical Specifications ceruice ette ENNER ENNER SEENEN dE EEN REENEN ENKEN MAR 25 3 1 JPowerand Ground PINS sagte neen HE BE E Qux 25 3 2 Decoupling Guidelines cei iiir eut axo SE Fa ba Res aaa n 25 3 2 1 VCC Decoupling iot bo e i EEN xu aan aV Ek deen duer 25 3 2 2 FSB AGTE F Decoupling gege these ue SNE SNE as
29. 1 t 0 1 1 0 0 0250 1 1 1 0 1 1 1 0 0125 1 1 1 1 0 0 0 0 0000 1 1 1 1 0 0 1 0 0000 1 1 1 d 0 1 0 0 0000 1 1 1 1 0 1 1 0 0000 1 1 1 1 1 0 0 0 0000 1 1 1 1 1 0 1 0 0000 1 1 1 1 1 1 0 0 0000 1 1 1 1 1 1 1 0 0000 Datasheet Electrical Specifications i n tel 3 4 3 5 3 6 Table 3 Datasheet Catastrophic Thermal Protection The processor supports the THERMTRIP signal for catastrophic thermal protection An external thermal sensor should also be used to protect the processor and the system against excessive temperatures Even with the activation of THERMTRIP which halts all processor internal clocks and activity leakage current can be high enough that the processor cannot be protected in all conditions without the removal of power to the processor If the external thermal sensor detects a catastrophic processor temperature of approximately 125 C maximum or if the THERMTRIP signal is asserted the Vcc supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor THERMTRIP functionality is not ensured if the PWRGOOD signal is not asserted and during Deep Power Down Technology State C6 Reserved and Unused Pins All RESERVED RSVD pins must remain unconnected Connection of these pins to Vcc Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Section 4 2 for a pi
30. AL25 VSS AR31 VSS AW15 VSS AL27 VSS AR35 VSS AW17 VSS AL29 VSS AR37 VSS AW19 VSS AL31 VSS AR39 VSS AW21 VSS AL39 VSS AT6 VSS AW23 VSS AM6 VSS AT8 VSS AW25 VSS AM8 VSS AT10 VSS AW27 VSS AM10 VSS AT12 VSS AW29 VSS AM12 VSS AT36 VSS AW31 VSS AM34 VSS AT38 VSS AW33 VSS AM36 VSS AT42 VSS AW35 VSS AM38 VSS AU3 VSS AW37 VSS AM42 VSS AU7 VSS AW39 VSS AN3 VSS AU9 VSS AY6 VSS AN15 VSS AU15 VSS AY12 VSS AN17 VSS AU17 VSS AY34 VSS AN19 VSS AU19 VSS AY42 VSS AN21 VSS AU21 VSS AY44 VSS AN23 VSS AU23 VSS B4 VSS AN25 VSS AU25 VSS B6 VSS AN27 VSS AU27 VSS B36 VSS AN29 VSS AU29 VSS B42 VSS AN31 VSS AU31 VSS BA1 VSS AN39 VSS AU35 VSS BA3 VSS AP6 VSS AU37 VSS BA9 VSS AP8 VSS AU39 VSS BA11 VSS AP34 VSS AV6 VSS BA13 VSS 42 VSS AV12 VSS BA15 VSS AR3 VSS AV34 VSS BA17 VSS ARIS VSS AV36 VSS BA19 VSS AR17 VSS AV42 VSS BA21 VSS AR19 VSS AV44 VSS BA23 VSS AR21 VSS AW1 VSS BA25 VSS AR23 VSS AW3 VSS BA27 VSS AR25 VSS AW9 VSS BA29 VSS AR27 VSS AW11 VSS BA31 Datasheet Package Mechanical Specifications and Pin Information intel Table 18 Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Datasheet Signal Ball Signal Name Ball Signal Ball Name Number Number Name Number VSS BA33 VSS C31 VSS H10 VSS BA39 VSS C39 VSS H34 55 BA43 VSS D2 VSS H38 VSS BB2 VSS D6 VSS H42 VSS BB6 VSS D36 VSS 1
31. Clock Input 122 VSS Power Other G3 RS 2 Common Clock Input 323 D 11 Source Synch Phe G4 VSS Power Other EN G5 BPRI Common Clock Input 124 D 10 Source Synch DA Input G6 HIT Common Clock 125 VSS Power Other G21 VCCP Power Other 6 PSTBNIQ Source synch Input 7 Output nput G22 D 3 Source Synch Output K1 VSS Power Other Input G23 VSS Power Othe wer r K2 REQ 2 Source Synch Output nput G24 D 9 Source Synch Output Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Table 17 Pin Listing Table 17 Pin Listing Pin Pin Name Signal Buffer Directi Pin Pin Name Signal Buffer Directi Type on Type on K3 REQ O 4 Source Synch ate M22 dd Fawer orner Input K4 VSS Power Other M23 D 23 Source Synch Output Input Input K5 A 6 Source Synch Output M24 D 21 Source Synch Output K6 VCCP Power Other M25 VSS Power Other K21 VCCP Power Other M26 Lm d Source Synch i K22 D 14 Source Synch IPPut ETE y Output N1 VSS Power Other K23 VSS Power Other N2 814 Source Synch Se Input utpu K24 D 8 Source Synch Output Input P N3 A 10 Source Synch Gre P K25 D 17 Source Synch S Output N4 VSS Power Other K26 VSS Power Other N5 RSVD Res
32. Open Drain UO Asynchronous PROCHOT CMOS Output Asynchronous PSI VID 6 0 BSEL 2 0 CMOS Input Synchronous to TCK TCK TDI TMS TRST Open Drain Output Synchronous to TCK TDO FSB Clock Clock BCLK 1 0 COMP 3 0 DBR 2 GTLREF RSVD TEST2 TEST1 Power Other THERMDA THERMDC Vcc VCCA Vccp Vcc SENSE Vss VsS_SENSE NOTES See next page Datasheet Electrical Specifications i n tel 3 8 3 9 Caution Table 5 Datasheet HB Refer to Chapter 4 for signal descriptions and termination requirements 2 In processor systems where there is no debug port implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects 3 BPM 2 1 and PRDY are AGTL output only signals 4 PROCHOT signal type is open drain output and CMOS input 5 On die termination differs from other AGTL signals CMOS Signals CMOS input signals are shown in Table 4 Legacy output FERR IERR and other non AGTL signals THERMTRIP and PROCHOT use Open Drain output buffers These signals do not have setup or hold time specifications in relation to BCLK 1 0 However all of the CMOS signals are required to be asserted for more than four BCLKs for the processor to recognize them See Section 3 10 for the DC specifications for the CMOS signal groups Maximum Ratings Table 5 specifies abso
33. Termination Voltage 1 00 1 05 1 10 V VccA PLL Supply Voltage 1 425 1 5 1 575 V Vccpprstp Vcc at Deeper Sleep 0 65 0 8 V 1 2 Vpca4 at Intel Enhanced Deeper Sleep State 0 6 0 8 V 1 2 VccpPPwbN Vcc at Deep Power Down Technology State C6 0 35 0 6 V 1 2 Iccpes Icc for Processors Recommended Design Target 9 A 5 Processor Number Core Frequency Voltage Icc SU3500 1 4 GHz amp VCcCHFM 9 SU3300 1 2 GHz amp VCcCHFM _ 9 3 4 12 1 2 GHz amp VccLFM 9 et 0 8 GHz amp VCcCSLFM 7 I Icc Auto Halt amp Stop Grant one HFM 4 4 A 3 4 12 SGNT SuperLFM 3 7 Icc Sleep Isi p HFM 4 1 A 3 4 12 SuperLFM 3 5 Datasheet 41 i n tel Electrical Specifications Table 12 Voltage and Current Specifications for the Ultra Low Voltage Single Core 5 5 W SFF Processor Symbol Parameter Min Typ Max Unit Notes Icc Deep Sleep Ipsip HFM 3 3 A 3 4 12 SuperLFM 3 0 IDPRSLP Icc Deeper Sleep 2 1 A 3 4 Ipc4 Icc Intel Enhanced Deeper Sleep State 1 9 A 3 4 IppwpN Icc Deep Power Down Technology State C6 1 7 A 3 4 Vcc Power Supply Current Slew Rate at Processor E dIcc pr Package Pin 600 mA us 7 9 Icc for Veca Supply ee 130 mA I Icc for Vccp Supply before Vcc Stable A 4 5 10 GCP Icc for VccpSupply after Vcc Stable 2 5 A 11 NOTES 1 Each processor is programmed with a maximum valid voltage identification value VID wh
34. Von is determined by value of the external pull up resistor to Vecp 4 For Vin between 0 V and Von 5 Cpad includes die capacitance only No package parasitics are included 8 Datasheet 49 50 Electrical Specifications Datasheet m 8 Package Mechanical Specifications and Pin Information n tel 4 4 1 Caution Datasheet Package Mechanical Specifications and Pin Information Package Mechanical Specifications The processor XE and SV is available in 478 pin Micro FCPGA packages as well as 479 ball Micro FCBGA packages The package mechanical dimensions are shown in Figure 9 through Figure 13 The processor POP LV ULV DC and ULV SC is available 956 ball Micro FCBGA packages The package mechanical dimensions are shown in Figure 14 and Figure 15 The maximum outgoing co planarity is 0 2 mm 8 mils for SFF processors The mechanical package pressure specifications are in a direction normal to the surface of the processor This protects the processor die from fracture risk due to uneven die pressure distribution under tilt stack up tolerances and other similar conditions These specifications assume that a mechanical attach is designed specifically to load one type of processor A 15 Ibf load limit should not be exceeded on BGA packages so as to not impact solder joint reliability after reflow This load limit ensures that impact to the package solder joints due to transient bend shock or tensile loading is
35. Y24 Geer vss Ti VSSSENSE AE7 Pod Output vss T4 vss T23 pud vss T26 ae vss U3 a vss U6 ae vss U21 Gei vss U24 Ge vss v2 a vss V5 vss v22 fed vss v25 Enel vss wi eL vss w4 Ge vss w23 pe vss w26 pia vss Y3 pond vss Y6 pad 71 m 8 tel Package Mechanical Specifications and Pin Information Table 17 Pin Listing Table 17 Pind Listing Pin Pin Name Signal Buffer Directi Pin Pin Name aco did iin Type on A2 vss Power Other AA13 VCC Power Other A3 SMIZ CMOS Input AA14 VSS Power Other Aa vss Power Other AA15 VCC Power Other A5 FERR Open Drain Output ARTS VSS Power Other A6 A20M CMOS Input AA17 VCC Power Other A7 VCC Power Other AA18 VCC Power Other A8 vss Power Other AA19 VSS Power Other A9 VCC Power Other AA20 VCC Power Other A10 Power Other AA21 D 50 Source Synch tie Alt e EE AA22 VSS Power Other A12 VCC Power Other Input A13 VCC Power Other AA23 D 45 Source Synch Output din yee Power oter AA24 D 46 amp Source Synch I Pu A15 VCC Power Other Output A16 VSS Power Other AA25 VSS Power Other A17 VCC Power Other AA26 ed Source Synch d A18 VCC Power Other AB1 VSS Power Other A19 VSS Power Other A20 VCC Power Other AB2 A 34 So
36. agent responsible for driving data on the FSB to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on both FSB agents Datasheet m 8 Package Mechanical Specifications and Pin Information n tel Table 19 Signal Description Sheet 3 of 8 Name Type Description DEFER is asserted by an agent to indicate that a transaction cannot be ensured in order completion Assertion of DEFER is DEFER Input normally the responsibility of the addressed memory or input output agent This signal must connect the appropriate pins of both FSB agents DINV 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DINV 3 0 signals are activated when the data on the data bus is inverted The bus agent will invert the data bus signals if more than half the bits within the covered group would change level in the next cycle DINV 3 0 Assignment To Data Bus Input Bus Si l Data Bus Si l Greg us Signa ata Bus Signals DINV 3 0 DINV 3 D 63 48 DINV 2 D 47 32 DINV 1 D 31 16 DINV 0 D 15 0 DPRSTP when asserted on the platform causes the processor to transition from the Deep Sleep State to the Deeper Sleep state or DPRSTP Input Deep Power Down Technology C6 state To return to the Deep Sleep State DPRSTP must be deasserted DPRSTP is driven by the ICH9M
37. another agent on the FSB or the interrupt has been latched The processor returns to the Stop Grant state once the snoop has been serviced or the interrupt has been latched Sleep State The Sleep state is a low power state in which the processor maintains its context maintains the phase locked loop PLL and stops all internal clocks The Sleep state is entered through assertion of the SLP signal while in the Stop Grant state The SLP pin should only be asserted when the processor is in the Stop Grant state SLP assertions while the processor is not in the Stop Grant state is out of specification and may result in unapproved operation In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP DPSLP or RESET are allowed on the FSB while the processor is in Sleep state Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior Any transition on an input signal before the processor has returned to the Stop Grant state will result in unpredictable behavior If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through the Stop Grant state If RESET is driven active while the processor is in the Sleep state the
38. are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 3 0 should connect the appropriate pins of all processor FSB agents This includes debug or performance monitoring tools 93 intel Package Mechanical Specifications and Pin Information Table 19 Signal Description Sheet 2 of 8 Name Type Description BPRI Input BPRI Bus Priority Request is used to arbitrate for ownership of the FSB It must connect the appropriate pins of both FSB agents Observing BPRI active as asserted by the priority agent causes the other agent to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BRO Input Output BRO is used by the processor to request the bus The arbitration is done between the processor Symmetric Agent and GMCH High Priority Agent BSEL 2 0 Output BSEL 2 0 Bus Select are used to select the processor input clock frequency Table 3 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency COMP 3 0 Analog COMP 3 0 must be terminated on the system
39. board using precision 1 tolerance resistors D 63 0 Input Output D 63 0 Data are the data signals These signals provide a 64 bit data path between the FSB agents and must connect the appropriate pins on both agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DINV Quad Pumped Signal Groups DSTBN DSTBP Data Group D 15 0 0 D 31 16 1 D 47 32 4 2 D 63 48 4 3 w NI 19 Furthermore the DINV pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DINV signal When the DINV signal is active the corresponding data group is inverted and therefore sampled active high DBR Output DBR Data Bus Reset is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect in the system DBR is not a processor signal DBSY 94 Input Output DBSY Data Bus Busy is asserted by the
40. including Enhanced Intel SpeedStep Technology and dynamic FSB frequency switching Datasheet n tel Introduction Digital thermal sensor DTS Intel 64 architecture e Supports enhanced Intel Virtualization Technology e Enhanced Intel Dynamic Acceleration Technology and Enhanced Multi Threaded Thermal Management EMTTM e Supports PSI2 functionality e SV processor offered in Micro FCPGA and Micro FCBGA packaging technologies e Processor in POP LV and ULV are offered in Micro FCBGA packaging technologies only e Execute Disable Bit support for enhanced security Intel Deep Power Down low power state with P_LVL6 I O support e Support for Intel Trusted Execution Technology e Half ratio support N 2 for core to bus ratio 1 1 Terminology Term Definition A symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the T name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level Front Side Bus Refers to the interface between th
41. lt 0 5000V NOTES 1 Applies to Low Voltage Ultra Low Voltage and Power Optimised Performance processors in 22 mmx22 mm package 2 Deeper Sleep mode tolerance depends on VID value 47 intel Electrical Specifications Table 13 AGTL Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes Vccp I O Voltage 1 00 1 05 1 10 V GTLREF Reference Voltage 0 65 0 70 0 72 V 6 Rcomp Compensation Resistor 27 23 27 5 27 78 Q 10 Ropr A Termination Resistor Address 49 55 63 Q 11 12 Ropr p Termination Resistor Data 49 55 63 Q 11 13 Termination Resistor Control 49 55 63 Q 11 14 Vin Input High Voltage 0 82 1 05 1 20 V 3 6 Vit Input Low Voltage 0 10 0 0 55 V 2 4 VoH Output High Voltage 0 90 Vccp 1 10 V 6 Termination Resistance Address 50 55 61 Q 7 12 Rrr p Termination Resistance Data 50 55 61 Q 7 13 Termination Resistance Control 50 55 61 Q 7 14 RoN A Buffer On Resistance Address 23 25 29 Q 5 12 Ron p Buffer On Resistance Data 23 25 29 Q 5 13 Ron cntri_ Buffer On Resistance Control 23 25 29 Q 5 14 Ij Input Leakage Current 100 HA Cpad Pad Capacitance 1 80 2 30 2 75 pF 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3
42. method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Thermal Monitor The DTS is only valid while the processor is in the normal operating state the Normal package level low power state Unlike traditional thermal devices the DTS outputs a temperature relative to the maximum supported operating temperature of the processor T max It is the responsibility of software to convert the relative temperature to an absolute temperature The temperature returned by the DTS will always be at or below Tj max Catastrophic temperature conditions are detectable via an Out Of Specification status bit This bit is also part of the DTS MSR When this bit is set the processor is operating out of specification and immediate shutdown of the system should occur The processor operation and code execution is not ensured once the activation of the Out of Specification status bit is set The DTS relative temperature readout corresponds to the Thermal Monitor TM1 TM2 trigger point When the DTS indicates maximum processor core temperature has been reached the TM1 or TM2 hardware thermal control mechanism will activate The DTS and TM1 TM2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradi
43. minimized The 15 Ibf metric should be used in parallel with the 689 kPa 100 psi pressure limit as long as neither limits are exceeded In some cases designing to 15 Ibf will exceed the pressure specification of 689 kPa 100 psi and therefore should be reduced to ensure both limits are maintained Moreover the processor package substrate should not be used as a mechanical reference or load bearing surface for the thermal or mechanical solution The Micro FCBGA package incorporates land side capacitors The land side capacitors are electrically conductive so care should be taken to avoid contacting the capacitors with other electrically conductive materials on the motherboard Doing so may short the capacitors and possibly damage the device or render it inactive 51 intel Figure 9 52 Package Mechanical Specifications and Pin Information 6 MB and 3 MB on 6 MB Die Micro FCPGA Package Drawing Sheet 1 of 2 B6887 01 D76563 1 C A B d G e o GIS ojo BE ggg 22900200050 00009000906 E 33 5 2 8 000000000000000000000900 900000000000090000000900000 ik S SIS S RIR E 96000000000000000000000006 4 4 als E 6000000000000 9000000000006 2 9600000000000 0000000000000 3 000000 9996 d 000000 4 e 00000 8 6090 000000 t 000
44. sensor vendors to ensure they have a part capable of reading the thermal diode in BJT model Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor s Automatic mode activation of the thermal control circuit This temperature offset must be considered when using the processor thermal diode to implement power management events This offset is different than the diode Toffset value programmed into the processor Model Specific Register MSR Table 27 and Table 28 provide the diode interface and transistor model specifications Thermal Diode Interface Signal Name Pin Ball Number Signal Description THERMDA A24 Thermal diode anode THERMDC A25 Thermal diode cathode Datasheet m Thermal Specifications and Design Considerations n tel Table 28 5 1 2 Datasheet Thermal Diode Parameters Using Transistor Model Symbol Parameter Min Typ Max Unit Notes Igw Forward Bias Current 5 ge 200 uA 1 Ig Emitter Current 5 200 ng Transistor Ideality 0 997 1 001 1 008 2 3 4 Beta 0 1 0 4 0 5 2 3 Ry Series Resistance 3 0 4 5 7 0 Q NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Characterized across a temperature range of 50 105 C 3 Not 100 tested Specified by design characterization 4 The ideality factor nQ represents the de
45. support current levels described herein Datasheet Electrical Specifications intel Table 9 Voltage and Current Specifications for the Dual Core Power Optimized Performance 25 W SFF Processors Symbol Parameter Min Typ Max Unit Notes Vcc in Enhanced Intel Dynamic Acceleration _ VCCDAM Technology Mode 0 9 1 275 V 1 2 VccHFM Vcc at Highest Frequency Mode HFM 0 9 1 2125 V 1 2 VcciEM Vcc at Lowest Frequency Mode LFM 0 85 1 025 V 1 2 VccsiFM at Super Low Frequency Mode Super LFM 0 75 0 95 V 1 2 Vcc Boor Default Vcc Voltage for Initial Power Up 1 20 V 2 6 8 Vccp AGTL Termination Voltage 1 00 1 05 1 10 V VccA PLL Supply Voltage 1 425 1 5 1 575 V Vccpprstp Vcc at Deeper Sleep 0 65 0 85 V 1 2 Vpc4 Vcc at Intel Enhanced Deeper Sleep State 0 6 0 85 V 1 2 VccpPPwbN Vcc at Deep Power Down Technology State C6 0 35 0 7 V 1 2 IccpEs Icc for Processors Recommended Design Target 37 A 5 Processor Number Core Frequency Voltage SP9600 2 53 GHz Vecuem 37 Icc SP9400 2 4 GHZ Vecuem 37 SP9300 2 26 GHz Vecuem 37 A 3 4 12 1 2 GHz amp VccLFM 28 0 8 GHz amp VccsLFM 17 I Icc Auto Halt amp Stop Grant 14 8 Pil HFM 8 8 A 3 4 12 SENI SuperLFM i Icc Sleep Isip HFM 14 2 A 3 4 12 SuperLFM 8 6 Icc Deep Sleep Ipsip HFM 12 5 A 3 4 12 SuperLFM 8 1 Ippnsip Icc Deeper Sleep
46. to maintain the processor junction temperature within the maximum specification the system must initiate an orderly shutdown to prevent damage If the processor enters one of the above low power states with PROCHOT already asserted PROCHOT will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point However PROCHOT will de assert for the duration of Deep Power Down Technology state C6 residency If Thermal Monitor automatic mode is disabled the processor will be operating out of specification Regardless of enabling the automatic or on demand modes in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature of approximately 125 C At this point the THERMTRIP signal will go active THERMTRIP activation is independent of processor activity and does not generate any bus cycles When THERMTRIP is asserted the processor core voltage must be shut down within the time specified in Chapter 3 In all cases the Intel Thermal Monitor feature must be enabled for the processor to remain within specification Digital Thermal Sensor The processor also contains an on die Digital Thermal Sensor DTS that can be read via an MSR 1 0 interface Each core of the processor will have a unique digital thermal sensor whose temperature is accessible via the processor MSRs The DTS is the preferred
47. will be lesser than or equal to 300 mV 42 Datasheet Electrical Specifications Figure 4 Datasheet Active Vcc and Icc Loadline for Standard Voltage Low Power SV 25 W and Dual Core Extreme Edition Processors Vcc cone V Slope 2 1 mV A at package VccSense VssSense pins Differential Remote Sense required Vec core max HFM LFM Vcc core pc max HFM LFM Vec core nom HFM LFM Vcc core pc Min HFM LFM Vec core min HFM LFM Vcc core Tolerance VR St Pt Error 1 Icc conE 0 Icc core max A HFM LFM Note 1 Vcc cone Set Point Error Tolerance is per below Tolerance Vcc cone VID Voltage Range 1 5 Voc core gt 0 7500V 11 5mV 0 5000V lt core lt 0 75000V intel 43 n tel Electrical Specifications Deeper Sleep Vcc and Icc Loadline for Standard Voltage Low Power SV Figure 5 25 W and Dual Core Extreme Edition Processors Vcc cone V Slope 2 1 mV A at package VccSense VssSense pins Differential Remote Sense required Vec core max HFM LFM Voc core pc max HFM LFM Vcc coge nom HFM LFM Vec core pc min HFM LFM Vec core min HFM LFM Vcc core Tolerance VR St Pt Error 1 Icc coRE 0 lcc coge max A HEM LFM Note 1 Vcc core Set Point Error Tolerance is per below Tolerance Vcc cone VID Voltage Range VID 1 5 3mV Vec core gt 0 7500V
48. 000 000000 L 66000 600090 E Seege i 0000 gt 1 LESSER 5 o 000000 d 996090 E 000000 000000 000000 i 600090 000000 _ 999999 8 T 000000 960600 000000 000 90600000000000000000009000 00000000000000000000000000 ng 000000000000 00000000000069 ot 000000000000000000000 S 5 kb E 5 8 8 P L 478 PINS Die DETAIL SCALE 20 LAHEL SIDE VIEW Package Substrate 037 MAX 0 65 MAX f riir FRONT VIEW TOP VIEW Datasheet intel 3 MB die Micro FCPGA Processor Package Drawing Sheet 1 of 2 Package Mechanical Specifications and Pin Information Figure 10 T p9soza 10 6 98 Sud Buda oz 3nvos yuvaa 31598 ao 5900 31598 L I 3508 S 8 ST 28 alv DIN 9s 00 MAIA 4 V xi sso E Z j Ly 9 Em 1 9 ayeqsqns 9 81284 DISV8 SL8 ST DISV8 SL TE DISV8 SL TE kO 5 ald 5331 3 MIIA 401 fo 2 ke MAIA WOLLOS MAI
49. 00000 1 000000 000000 000000 Q90000____ rye 9090900 GO0000 600000 000000 000000 000000 000000 000000 000000 000000 000000 000000 o 000000 000000 000000 600000000000000000000000060 0000000000000 0000000000000 00000000000000000000000000 90000000000000000000000000 0000000000000000000000000 6000000000000000000000000 19 5 XVII NIW SY3LIWINIW M3IA 3GIS STIV8 64t g viaa 33S 7208WAS 05 3 8 uviaa V lvisd 335 MAIA 1NO 3H S MIIA dOL 19 55 Datasheet Package Mechanical Specifications and Pin Information intel 3 MB Die Micro FCBGA Processor Package Drawing Sheet 2 of 2 Figure 13 1H9BH LNINOdWOD 6 I0 zv 98 M3IA WOLLOG 318VMOTIV XVW 550 00000000000000000004d00000 0000000000000 0000000000000 00000000000000000000000000 00000000000000000900000000 000000 000000 4 4 9 e 000000 000000 000000 000000 000000 869 000000 000000 000000 1 9000000 000000 OO00000 000000 000000 000000 000000 000000 000000 000000 000000 i 000000 1 e Et 000000 000000 00000000000000000000000000 0000000000000 0000000000000
50. 00000000000 00000000000000000000000000 9660006 0000000000 99999969 s wr 5869 JO a v gt 90705 L6 EL SCO SOE00 MAIA 3415 AUAA UA KATAA AAAA M3IA dOL Xb INOZ 1 433 U3NHOD Xb INOZ E 1 0 4331 3503 DIS Xv 7 Ge Datasheet 54 intel Package Mechanical Specifications and Pin Information 3 MB Die Micro FCBGA Processor Package Drawing Sheet 1 of 2 Figure 12 1 c0z 6a 10 1598 oz WOS y viaa eyensqns 9682284 MAIA WOLLOG SH T eooocooooocodoooooooo0006 Ri n 59 80 90 M N 690 190 D DISV8 Z T JISV8 Ls Ch 12009 alv O eozoo 91958 SZ8 ST DISV8 SZ8 ST JISV8 SL TE DISV8 SZ TE LOZ Z Eet 88 0 P Du TH 19 4 D 2 L8 D SO SE Ser ta S0 St Ser Ta oO 000000 000000 000000 5 000000 000000 i 000000 000000 000000 0
51. 17 VCC Power Other E2 BNR Common Clock Input C18 VCC Power Other Output C19 VSS Power Other E3 VSS Power Other C20 DBR CMOS Output E4 HITM Common Clock DH tput C231 BSEL 2 CMOS Output EE E DPRSTP CMOS Input C22 VSS Power Other 2 2 npu E6 VSS Power Other C23 TEST1 Test C24 TEST3 Test E7 VCC Power Other E VSS P th C25 VSS Power Other S SE E9 VCC Power Other C26 VCCA Power Other EL VCC P th Di VSS Power Other a SA D2 RSVD Reserved E11 VSS Power Other E12 VCC Power Other D3 RSVD Reserved E1 VCC P th D4 VSS Power Other 3 E14 VSS P th D5 STPCLK CMOS Input pen One E15 vcc Power Other D6 PWRGOOD CMOS Input EL VSS P th D7 SLP CMOS Input da dba E17 VCC P th D8 VSS Power Other ower other E18 VCC Power Other D9 VCC Power Other EL VSS P th D10 VCC Power Other 3 ower other E2 VCC P th VSS Power Other d Get E21 VSS Power Other D12 Power Other Input D13 VSS Power Other E22 D 0 Source Synch Output D14 VCC Power Other Ge Dive ELE Input D15 Power Other Output D16 VSS Power Other E24 VSS Power Other D17 Power Other E25 614 Source Synch ate D18 VCC Power Other HEpu D19 VSS Power Other E26 D 2 amp Source Synch Ge D20 IERR Open Drain Output Input F1 BRO Common Clock Output 75 m n tel Package Mechanical Specifications and Pin Information
52. 19 VSS R17 VSS W21 VSS R19 VSS W23 VSS R21 VSS W25 VSS R23 VSS W27 VSS R25 VSS W29 VSS R27 VSS w31 VSS R29 VSS w39 VSS R31 VSS Y6 VSS R39 VSS Y8 VSS T6 VSS Y10 VSS T8 VSS Y12 VSS T10 VSS Y34 VSS T12 VSS Y36 VSS T34 VSS Y38 VSS T36 VSS Y42 VSS T38 VSSSENSE BC13 VSS T42 VSS U3 VSS U5 Datasheet e Package Mechanical Specifications and Pin Information n tel 4 3 Table 19 Datasheet Alphabetical Signals Reference Signal Description Sheet 1 of 8 Name Type Description A 35 3 Input Output A 35 3 Address define a 235 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of both agents on the processor FSB A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 Address signals are used as straps which are sampled before RESET is deasserted A20M Input If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure r
53. 3 n tel Thermal Specifications and Design Considerations Table 23 Power Specifications for the Dual Core Power Optimized Performance 25 W SFF Processors Symbol Core Frequency amp Voltage mu cn Unit Notes SP9600 2 53 GHz amp HFM Vec 25 SP9400 2 4 GHz amp HFM Vec 25 TDP SP9300 2 26 GHz amp HFM Vcc 25 Wo be 1 6 GHz Super LFM Vcc 20 0 8 GHz amp Super LFM 11 Symbol Parameter Min Typ Max Unit Notes Auto Halt Stop Grant Power pne at VccurM 8 3 W 2 5 7 at Vccsi EM 3 3 Sleep Power Psi p at VCccHFM md 7 5 W 2 5 7 at Vccsi EM 3 1 Deep Sleep Power Ppsi p at VccuEM 2 9 W 2 5 8 at Vccsi EM 1 8 PpprsLp Deeper Sleep Power 1 0 Ww 2 8 Poca Intel Enhanced Deeper Sleep State Power 0 9 Ww 2 8 Pce Intel Deep Power Down Power 0 3 WwW 2 8 Tj Junction Temperature 0 105 C 3 4 NOTES 1 The TDP specification should be used to design the processor thermal solution The TDP is not the maximum theoretical power the processor can generate 2 Not 100 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum has been reached The Intel Thermal Monitor automat
54. 3 VSS BB12 VSS D42 VSS J15 VSS BB36 VSS D44 VSS 117 VSS BB42 VSS E1 VSS J19 VSS BC3 VSS E3 VSS J21 VSS BC9 VSS E9 VSS J23 VSS BC11 VSS E15 VSS J25 VSS BC15 VSS E17 VSS 127 55 BC17 VSS E19 VSS 129 VSS BC19 VSS E21 VSS J31 55 21 55 23 55 139 55 23 55 25 55 K6 VSS BC25 VSS E27 VSS K8 VSS BC27 VSS E29 VSS K34 VSS BC29 VSS E31 VSS K42 VSS BC31 VSS E39 VSS L3 VSS BC33 VSS F6 VSS L15 VSS BC41 VSS F42 VSS L17 VSS BD4 VSS F44 VSS L19 VSS BD6 VSS G1 VSS L21 VSS BD36 VSS G3 VSS L23 VSS BD38 VSS G9 VSS L25 VSS BD40 VSS G15 VSS L27 VSS C3 VSS G17 VSS L29 55 C11 VSS G19 VSS L31 VSS C15 VSS G21 VSS L39 VSS C17 VSS G23 VSS M6 VSS C19 VSS G25 VSS M8 VSS C21 VSS G27 VSS M10 VSS C23 VSS G29 VSS M12 VSS C25 VSS G31 VSS M34 VSS C27 VSS G37 VSS M36 VSS C29 VSS H6 VSS M38 91 intel Package Mechanical Specifications and Pin Information Table 18 Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name 92 Signal Ball Signal Name Ball Signal Ball Name Number Number Name Number VSS M42 VSS U15 VSS N3 VSS U17 VSS N15 VSS U19 VSS N17 VSS U21 VSS N19 VSS U23 VSS N21 VSS U25 VSS N23 VSS U27 VSS N25 VSS U29 VSS N27 VSS U31 VSS N29 VSS U39 VSS N31 VSS V6 VSS N39 VSS V VSS P6 VSS V34 VSS P8 VSS V42 VSS P34 VSS W3 VSS P42 VSS 15 VSS R3 VSS W17 VSS R15 VSS W
55. 7 VCC Power Other AF VCCBEN Power Other B18 VCC Power Other AF8 VSS Power Other AF9 VCC Power Other TE doi pad AF10 VCC Power Other Bei NE Bee AF11 VSS Power Other Bee ee Output AF12 VCC Power Other B23 Gos AF13 VSS Power Other ues T ee B25 THRMDC Power Other AFI5 VCC Power Other B26 VOCA AFI6 vss Power Other C1 RESET Common Clock Input AF17 VCC Power Other iai eund AF18 Power Other c3 TEST7 Tesi AF19 VSS Power Other EE mies Input AF20 VCC Power Other c gt vss Power otmen AF21 VSS Power Other 5 FINT cmos me C7 mS Open Drain Output 74 Package Mechanical Specifications and Pin Information Datasheet intel Table 17 Pin Listing Table 17 Pin Listing Pin Pin Name Signal Buffer Directi Pin Pin Name Signal Buffer Directi Type on Type on C8 VSS Power Other D21 ae ad Open Drain Deeg C9 VCC Power Other utpu C10 VCC Power Other D22 RSVD Reserved C11 VSS Power Other D23 VSS Power Other C12 VCC Power Other D24 DPWR Common Clock Und Ci VCC P th 3 owen other D25 TEST2 Test C14 VSS P th owerOtner D26 VSS Power Other C15 VCC Power Other InBUU C16 VSS Power Other DBSY Common Clock Output C
56. A 3415 v M m 3 unen nr EI frs p Deeg T aj N o 000000 000000 00000000000000000000000000 00000000000000000000000000 00000000000000000000000000 00000000000000000000000000 00000000000000000000000000 1 00000000000000000000000000 1 SNId 8v Je T Tg wel 59 56 586 r a R i 56 556 53 Datasheet Package Mechanical Specifications and Pin Information 3 MB Die Micro FCPGA Processor Package Drawing Sheet 2 of 2 intel Figure 11 c vos9 q 0 0 498 MAIA WOLLOd 1H9I3H LNINOdWOD 3I8VMOTIV XVW ST 0000000000000000000 00000 000000000000000 0000000000 00000000000000000090000000 999 000000 000000 000000 000000 000000 000000 000000 000000 000000 060066 i 960066 000000 000000 000000 000000 000000 000000 000000 000000 000000 o 000000 000000 000000 060000000000000000000000000 99 9 000000000000000
57. AIT C1 instruction Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor core to return to the CO state See the Inte 64 and IA 32 Architectures Software Developer s Manuals Volume 2A Instruction Set Reference A M and Volume 2B Instruction Set Reference N Z for more information Core C2 State Individual cores of the dual core processor can enter the C2 state by initiating a P LVL2 I O read to the P BLK or an MWAIT C2 instruction but the processor will not issue a Stop Grant Acknowledge special bus cycle unless the STPCLK pin is also asserted While in the C2 state the dual core processor will process bus snoops and snoops from the other core The processor core will enter a snoopable sub state not shown in Figure 1 to process the snoop and then return to the C2 state Core C3 State Individual cores of the dual core processor can enter the C3 state by initiating a P LVL3 I O read to the P BLK or an MWAIT C3 instruction Before entering C3 the processor core flushes the contents of its L1 caches into the processor s L2 cache Except for the caches the processor core maintains all its architectural states in the C3 state The Monitor remains armed if it is configured All of the clocks in the processor core are stopped in the C3 state Because the core s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on th
58. D19 pod vss B11 a vss D23 pod vss B13 E vss D26 Ge vss B16 po vss E3 pone vss B19 Ge vss E6 vss B21 EE vss E8 P vss B24 pia vss E11 p vss C2 pond vss E14 Per vss C5 pad vss E16 pie vss c8 Pd vss E19 ud vss Cii vss E21 jid 69 70 intel Package Mechanical Specifications and Pin Information Table 16 Pin Name Listing Table 16 Pin Name Listing Signal Signal Pin Name Pin Buffer Direction Pin Name Pin Buffer Direction Type Type vss E24 Prei vss ki posui vss F2 vss K4 a vss F5 SE vss K23 posui vss F8 GE vss K26 EE vss F11 pori vss L3 n vss F13 p vss L6 Ge vss F16 pd vss L21 piel vss F19 Pes vss L24 Ee vss F22 ec vss M2 pia vss F25 dee vss M5 ud vss G1 ud vss M22 pos vss G4 d vss M25 ein vss G23 ee vss N1 pond vss G26 Ge vss N4 aer vss H3 Ee vss N23 Pod vss H6 Ge vss N26 Poe vss H21 ed vss P3 vss H24 pd vss P6 Pd vss 12 vss P21 pud vss TA od vss p g owe vss J22 SE vss R2 a vss J25 pos vss R5 posi Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Table 16 Pin Name Listing Table 16 Pin Name Listing Signal Signal Pin Name Pin Buffer Direction Pin Name Pin Buffer Direction Type Type vss R22 pud vss Y21 Pod vss R25 pad vss
59. Direction Pin Name Pin Buffer Direction Type Type vcc A9 pod vcc AB15 ee A10 pad vcc AB17 Pound VCC 12 vcc AB18 pud 13 vcc AB20 A15 a vcc AC7 pied A17 bia vcc ACO SE A18 psal vcc AC10 Ge 20 vcc AC12 Geier VCC AAT EL vcc AC13 Pd vcc AA9 eg vcc AC15 pa vcc AA10 vcc AC17 pois VCC AA12 bal vcc AC18 jd vcc AA13 fed vcc AD7 pond AA15 pad vcc AD9 pod VCC AA17 pte vcc AD10 posu vcc AA18 Ge vcc AD12 SE vcc AA20 poa vcc AD14 P VCC AB7 pisa vcc AD15 e VCC ABO pies vcc AD17 po vcc AB10 pad vcc AD18 pr VCC AB12 Pd vcc AE9 Pd VCC AB14 vcc AE10 Pid 65 66 intel Package Mechanical Specifications and Pin Information Table 16 Pin Name Listing Table 16 Pin Name Listing Signal Signal Pin Name Pin Buffer Direction Pin Name Pin Buffer Direction Type Type AE12 e vcc B20 pus vcc AE13 C9 Ped vcc AE15 vcc C10 AE17 rid C12 pod vcc AE18 vcc C13 vcc AE20 uid vcc C15 AF9 pd VCC C17 atar vcc AF10 pesi vcc C18 E AF12 pedi D9 posui VCC AF14 jud vcc D10 odd vcc AF15 jud vcc D12 DL AF17 pd D14 Ge vcc AF18 ee vcc D15 pora vcc AF20 a vcc D17 pid B7 SE vcc D18 vcc B9 Ge vcc E7 pod vcc B10 ed vcc E9 Ger B12 ed vcc E10 Ger B14 posu E12 vcc B15
60. Electrical Specifications i n tel 1 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Intel Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Enhanced Halt State 2 The voltage specifications are assumed to be measured across Vcc_sense and Vss_sense pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 3 Specified at 105 C T 4 Specified at the nominal Vcc 5 Measured at the bulk capacitors on the motherboard 6 Vcc Boor tolerance shown in Figure 7 and Figure 8 7 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested 8 This is a power up peak current specification that is applicable when Vccp is high and Vcc cong is low 9 This is a steady state Icccurrent specification that is applicable when both Vccp and cone
61. Grant Deep Sleep Enhanced Deeper Sleep Down Technology Intel Deep Power Down NOTE 1 AutoHALT or MWAIT C1 Core Low Power State Descriptions Core CO State This is the normal operating state for cores in the processor Core C1 AutoHALT Powerdown State C1 AutoHALT is a low power state entered when a core executes the HALT instruction The processor core will transition to the CO state upon occurrence of SMI INIT LINT 1 0 NMI INTR or FSB interrupt messages RESET will cause the processor to immediately initialize itself A System Management Interrupt SMI handler will return execution to either Normal state or the AutoHALT Powerdown state See the Inte 64 and IA 32 Architectures Software Developer s Manuals Volume 3A 3B System Programmer s Guide for more information 13 m 8 n tel Low Power Features 2 1 1 3 2 1 1 4 2 1 1 5 2 1 1 6 14 The system can generate a STPCLK while the processor is in the AutoHALT Powerdown state When the system deasserts the STPCLK interrupt the processor will return execution to the HALT state While in AutoHALT Powerdown state the dual core processor will process bus snoops and snoops from the other core The processor core will enter a snoopable sub state not shown in Figure 1 to process the snoop and then return to the AutoHALT Powerdown state Core C1 MWAIT Powerdown State C1 MWAIT is a low power state entered when the processor core executes the MW
62. HFM 25 WwW 5 6 P8600 2 4 GHz VccureM 25 S P8400 2 267 GHz amp VCCHFM 25 1 6 GHz amp VCCLFM 20 0 8 GHz amp VCcCSLFM 11 Symbol Parameter Min Typ Max Unit Notes P Auto Halt Stop Grant Power a at VCCHFM mE 8 1 Ww 2 5 7 SGNT at VCccsLFM 3 7 Sleep Power Psi p at VccHFM 7 3 WwW 2 5 7 at Vccsi FM 3 5 Deep Sleep Power Ppsip at VccurM 2 9 Ww 2 5 8 at Vccsi EM 2 1 Ppprstp Deeper Sleep Power 1 0 Ww 2 8 Poca Intel Enhanced Deeper Sleep State Power 0 9 WwW 2 8 Pce Intel Deep Power Down Power 0 3 2 8 Tj Junction Temperature 0 105 C 3 4 NOTES 1 The TDP specification should be used to design the processor thermal solution The TDP is not the maximum theoretical power the processor can generate 2 Not 100 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum has been reached Refer to Section 6 1 for more details 4 The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 5 Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser than TDP in HFM 6 At Tj of 105 C 7 At Tj of 50 C 8 At Tj of 35 C Datasheet 10
63. Icc Sleep Isi p HFM 5 9 A 3 4 12 SuperLFM 4 2 Icc Deep Sleep Ipsip HFM 5 0 A 3 4 12 SuperLFM 3 7 IDPRSLP Icc Deeper Sleep 3 2 A Ipc4 Icc Intel Enhanced Deeper Sleep State 2 8 A 7 IppwpN Icc Deep Power Down Technology State C6 x 2 4 A j Vcc Power Supply Current Slew Rate at Processor dccus Rn Pp 600 mA us 7 9 Icc for Veca Supply E ES 130 mA I Icc for Vccp Supply before Vcc Stable E 4 5 10 SS Icc for VccpSupply after Vcc Stable 2 5 A 11 NOTES See next page 40 Datasheet Electrical Specifications i n tel NOURW 10 11 12 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Intel Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Enhanced Halt State The voltage specifications are assumed to be measured across Vcc sense and Vss sense pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe Specif
64. MOS Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes Vccp I O Voltage 1 00 1 05 1 10 V ViL Input Low Voltage CMOS 0 10 0 00 0 3 Vccp V 2 Vin Input High Voltage 0 7 Vccp Vccp Vccp t 0 1 V 2 VoL Output Low Voltage 0 10 0 0 1 Vccp V 2 Vou Output High Voltage 0 9 Vccp Vccp Vccp t 0 1 V 2 Io Output Low Current 1 5 4 1 mA 3 Ion Output High Current 1 5 4 1 mA 4 Input Leakage Current 100 HA 5 Cpadi Pad Capacitance 1 80 2 30 2 75 pF 6 Cpad2 Pad Capacitance for CMOS Input 0 95 1 2 1 45 pF 7 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The Vccp referred to in these specifications refers to instantaneous Vccp 3 Measured at 0 1 Vccp 4 Measured at 0 9 Vccp 5 For Vin between 0 V and Vccp Measured when the driver is tristated 6 Cpad1 includes die capacitance only for DPRSTP DPSLP PWRGOOD No package parasitics are included 7 Cpad2 includes die capacitance for all other CMOS input signals No package parasitics are included Table 15 Open Drain Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes VoH Output High Voltage Vccp 596 Vecp Vecp 5 V 3 VoL Output Low Voltage 0 0 20 V Io Output Low Current 16 50 mA ILo Output Leakage Current 200 HA 4 Cpad Pad Capacitance 1 80 2 30 2 75 pF NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Measured at 0 2 V 3
65. Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enters System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If an SMI is asserted during the deassertion of RESET then the processor will tristate its outputs 98 Datasheet Package Mechanical Specifications and Pin Information Table 19 Datasheet intel Signal Description Sheet 7 of 8 Name Type Description STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units STPCLK Input The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK Input TCK Test Clock provides the clock input for the processor Test Bus P also known as the Test Access Port TDI Input TDI Test Data In transfers serial test data into the processor TDI P provides the serial input needed for JTAG specification support TDO Test Da
66. NEN di RA 109 Datasheet 3 5 1 3 Digital Thermal Sensor E E RR 111 2 Out of Specification Detecton eene nemen emen enne 112 3 PROCHOT Sigmal aerea denied SEENEN Ey Ee 112 dien Core Low Power States EE 12 3 Package LoWw POWer States iet esit x SEENEN dave aE 13 3 Dynamic FSB Frequency Switching Protocol nennen 22 4 Active VCC and ICC Loadline for Standard Voltage Low Power SV 25 W and Dual Core Extreme Edition PrOCGSSOMS 5 ons egage Seed areas dE notae alae c aatia teat e e e tud Cum alin 43 5 Deeper Sleep VCC and ICC Loadline for Standard Voltage Low Power SV 25 W and Dual Core Extreme Edition Processors ENEE 44 6 Deeper Sleep VCC and ICC Loadline for Low Power Standard Voltage Processors 45 7 Active VCC and ICC Loadline for Low Voltage Ultra Low Voltage and Power Optimized Performance PEOCeSSOTr see gege dE setae quia dena EDI EENS SES at OUI ENNER tees 46 8 Deeper Sleep VCC and ICC Loadline for Low Voltage Ultra Low Voltage and Power RD Performance e EE 9 6 MB and 3 MB on 6 MB Die Micro FCPGA Package Drawing Sheet 1 of 2 SS 10 3 MB die Micro FCPGA Processor Package Drawing Sheet 1 2 53 11 3 MB Die Micro FCPGA Processor Package Drawing Sheet 2 of 21 54 12 3 MB Die Micro FCBGA Processor Package Drawing Sheet 1 of 2 55 13 3 MB Die Micro FCBGA Processor
67. Package Drawing Sheet 2 2 56 14 Intel Core 2 Duo Mobile Processor POP and LV Die Micro FCBGA Processor Package RICH e 57 15 Intel Core 2 Duo Mobile Processor ULV SC and ULV DC Die Micro FCBGA Processor Package 58 16 Processor Pinout Top Package View Left Side ssssssessssseseenmem nme 59 17 Processor Pinout Top Package View Right 5 8 60 18 Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Left Side 80 19 Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Right Side 81 20 Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Left Side 82 21 Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Right Side 83 Tables 1 Coordination of Core Low Power States at the Package Level 13 2 Voltage Identification Definition ie NEEN NEEN EEEENNEEENE NES nhan haa ka SEENEN ERR EN A 26 3 BSEL 2 0 Encoding for BCLK FreqUency siessese enne nen enu na KEE EESK ER NEEN ERKENNEN RER seas 29 4 FSB PIN Groups fc MR NEITA 30 5 Processor Absolute Maximum Ratings Nini aa iaa EEE eee 31 6 Voltage and Curren
68. Package Mechanical Specifications and Pin Information Table 18 Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name 86 Signal Ball Signal Name Ball Signal Ball Name Number Number Name Number VCC AH22 VCC AP32 VCC B22 VCC AH24 VCC AR33 VCC B24 VCC AH26 VCC AT14 VCC B26 VCC AH28 VCC AT16 VCC B28 VCC AH30 VCC AT18 VCC B30 VCC AH32 VCC AT20 VCC BB14 VCC AJ33 VCC AT22 VCC BB16 VCC AK16 VCC AT24 VCC BB18 VCC AK18 VCC AT26 VCC BB20 VCC AK20 VCC AT28 VCC BB22 VCC AK22 VCC AT30 VCC BB24 VCC AK24 VCC AT32 VCC BB26 VCC AK26 VCC AT34 VCC BB28 VCC AK28 VCC AU33 VCC BB30 VCC AK30 VCC AV14 VCC BB32 VCC AK32 VCC AV16 VCC BD14 VCC AL33 VCC AV18 VCC BD16 VCC AM14 VCC AV20 VCC BD18 VCC AM16 VCC AV22 VCC BD20 VCC AM18 VCC AV24 VCC BD22 VCC AM20 VCC AV26 VCC BD24 VCC AM22 VCC AV28 VCC BD26 VCC AM24 VCC AV30 VCC BD28 VCC AM26 VCC AV32 VCC BD30 VCC AM28 VCC AY14 VCC BD32 VCC AM30 VCC AY16 VCC D16 VCC AM32 VCC AY18 VCC D18 VCC AN33 VCC AY20 VCC D20 VCC AP14 VCC AY22 VCC D22 VCC AP16 VCC AY24 VCC D24 VCC AP18 VCC AY26 VCC D26 VCC AP20 VCC AY28 VCC D28 VCC AP22 VCC AY30 VCC D30 VCC AP24 VCC AY32 VCC F16 VCC AP26 VCC B16 VCC F18 VCC AP28 VCC B18 VCC F20 VCC AP30 VCC B20 VCC F22 Datasheet Package Mechanical Specifications and Pin Information intel Table 18 Intel Core 2 Duo Mobile Proce
69. SLP and STPCLK signals should be deasserted immediately after RESET is asserted to ensure the processor correctly executes the Reset sequence While in the Sleep state the processor is capable of entering an even lower power state the Deep Sleep state by asserting the DPSLP pin See Section 2 1 2 5 While the processor is in the Sleep state the SLP pin must be deasserted if another asynchronous FSB event needs to occur Deep Sleep State The Deep Sleep state is entered through assertion of the DPSLP pin while in the Sleep state BCLK may be stopped during the Deep Sleep state for additional platform level power savings BCLK stop restart timings on appropriate GMCH based platforms with the CK505 clock chip are as follows Deep Sleep entry the system clock chip may stop tristate BCLK within 2 BCLKs of DPSLP assertion It is permissible to leave BCLK running during Deep Sleep Deep Sleep exit the system clock chip must drive BCLK to differential DC levels within 2 3 ns of DPSLP deassertion and start toggling BCLK within 10 BCLK periods To re enter the Sleep state the DPSLP pin must be deasserted BCLK can be re started after DPSLP deassertion as described above A period of 15 microseconds to allow for PLL stabilization must occur before the processor can be considered to be in the Sleep state Once in the Sleep state the SLP pin must be deasserted to re enter the Stop Grant state While in Deep Sleep state the
70. SVD D3 Reserved Other RSVD D22 Reserved HIT G6 Common Input Clock Output RSVD F6 Reserved HITM 4 RSVD M4 Reserved P RSVD N5 Reserved IERR D20 GC Output RSVD T2 Reserved IGNNE C4 CMOS Input BOND v3 Reserved INIT B3 CMOS Input SEPT D7 j Mes Input LINTO C6 CMOS Input vM Boe Input LINTI B4 CMOS Input STPCLK D5 CMOS Input em m Common Input TCK AC5 CMOS Input Clock Output TDI AA6 CMOS Input Common Open PRDY AC2 Clock Output TDO AB3 Drain Output PREQ ACL pd Input TEST1 C23 Test TEST2 D25 Test PROCHOT p21 OPen Input TEST3 C24 Test Drain Output PSI 6 CMOS Output TESTA AFee Test PWRGOOD D6 CMOS Input TESTS JE Test TEST6 A26 Test REQ 0 K3 Source Input Synch Output TEST7 C3 Test Source Input THERMTRIP Open REQ 1 ES Synch Output C7 Drain Output Source Input Power REQ 2 K2 Synch Output THRMDA A24 Other Source Input Power REQ 3 J3 Synch Output THRMDC B25 Other Source Input TMS AB5 CMOS Input REQ 4 LI Synch Output Common Common TRDY G2 Clock Input RESET Ci Clock Input TRST AB6 CMOS Input Common RS 0 F3 Clock Input vcc A7 Power Other Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Table 16 Pin Name Listing Table 16 Pin Name Listing Signal Signal Pin Name Pin Buffer
71. U22 Source Input Synch Output D 47 AB25 Synch Output Source Input DINV 3 AC20 p Source Input Synch Output D 48 AE24 Synch Output y P DPRSTP E5 CMOS Input Source Input D 49 AD24 Synch Output DPSLP B5 CMOS Input Common Input Source Input DPWR D24 D 50 AA21 Synch Output Clock Output Common Input Source Input DRDY F21 D 51 AB22 Synch Output Clock Output Source Input Source Input DSTBN 0 J26 D 52 AB21 Synch Output Synch Output Source Input Source Input DSTBN 1 L26 D 53 AC26 Synch Output Synch Output Source Input Source Input DSTBN 2 Y26 D 54 AD20 Synch Output Synch Output Source Input Source Input DSTBN 3 AE25 D 55 AE22 Synch Output Synch Output Source Input Source Input DSTBP 0 H26 D 56 AF23 Synch Output Synch Output Source Input Source Input DSTBP 1 M26 D 57 AC25 Synch Output Synch Output 63 m 8 n tel Package Mechanical Specifications and Pin Information Table 16 Pin Name Listing Table 16 Pin Name Listing Signal Signal Pin Name Pin Buffer Direction Pin Name Pin Buffer Direction Type Type Source Input Common DSTBP 2 AA26 Synch Output RS 1 F4 Clock Input Source Input Common DSTBP 3 AF24 Synch Output RS 2 G3 Clock Input FERR AS E Output RSVD B2 Reserved RSVD D2 Reserved GrLREF ap26 POE Input R
72. active RESET both FSB agents will deassert their outputs within two clocks All processor straps must be valid within the specified setup time before RESET is deasserted There is a 55 O nominal on die pull up resistor on this signal RS 2 0 Input RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of both FSB agents RSVD Reserved No Connect These pins are RESERVED and must be left unconnected on the board However it is recommended that routing channels to these pins on the board be kept open for possible future use SLP Input SLP Sleep when asserted in Stop Grant state causes the processor to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertion of the RESET signal deassertion of SLP and removal of the BCLK input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units If DPSLP is asserted while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state SMI Input SMI System
73. an pru udi D 30 amp T25 Cnt Ge D 9 fen EEN SE D 31 amp N25 SE BU x MEL Sch CN D 32 amp 22 SEN D j J23 San SCC D 33 amp AB24 SEN GE D 12 H22 EEN SC D 34 amp v24 S SC DET3J F26 pod SEN D 35 v26 p nA 62 Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Table 16 Pin Name Listing Table 16 Pin Name Listing Signal Signal Pin Name Pin Buffer Direction Pin Name Pin Buffer Direction Type Type Source Input Source Input Hals v23 Synch Output D 58 AE Synch Output Source Input Source Input PISTE T22 Synch Output D 59 GES Synch Output Source Input Source Input SS ves Synch Output D 60 AC22 Synch Output Source Input Source Input D 39 U23 Synch Output D 61 AD23 Synch Output Source Input Source Input Synch Output D 62 Are Synch Output Source Input Source Input Ss Wee Synch Output D 63 ees Synch Output 4214 Y23 Source Input DBR C20 CMOS Output Synch Output Common Input DBSY Source Input Clock Output D 43 W24 Synch Output Common DEFER H5 Input Source Input Clock D 44 W25 Synch Output Source Input DINV 0 H25 Source Input Synch Output D 45 AA23 Synch Output Source Input DINV 1 N24 Source Input Synch Output D 46 AA24 Synch Output Source Input DINV 2
74. are enabled The processor implements two software interfaces for requesting enhanced package low power states MWAIT instruction extensions with sub state hints and via BIOS by configuring IA32 MISC ENABLES MSR bits to automatically promote package low power states to enhanced package low power states Extended Stop Grant and Enhanced Deeper Sleep must be enabled via the BIOS for the processor to remain within specification As processor technology changes enabling the extended low power states becomes increasingly crucial when building computer systems Maintaining the proper BIOS configuration is key to reliable long term system operation Not complying to this guideline may affect the long term reliability of the processor Enhanced Intel SpeedStep Technology transitions are multistep processes that require clocked control These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low power states since processor clocks are not active in these states Extended Deeper Sleep is an exception to this rule when the Hard CAE configuration is enabled in the IA32 MISC ENABLES MSR This Extended Deeper Sleep state configuration will lower core voltage to the Deeper Sleep level while in Deeper Sleep and upon exit will automatically transition to the lowest operating voltage and frequency to reduce snoop service latency The transition to the lowest operating point or back to the original software requested point may not b
75. are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Intel Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Enhanced Halt State 2 The voltage specifications are assumed to be measured across Vcc_sense and sense pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 3 Specified at 105 C Tj 4 Specified at the nominal Vcc 5 Measured at the bulk capacitors on the motherboard 6 Vcc Boor tolerance shown in Figure 7 and Figure 8 7 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested 8 This is a power up peak current specification that is applicable when Vccp is high and Vcc _ core is low 9 This is a steady state current specification that is applicable when both Vccp and coge are high 10 Processor Icc requirements in Intel Dynamic Acceleration Technology mode are lesser than Icc in HFM 11 The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV 12 Instantaneous current
76. are high 10 Processor Icc requirements in Intel Dynamic Acceleration Technology mode are lesser than Icc in HFM 11 The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV 12 Instantaneous current Icc cong wer Of 57 A has to be sustained for short time of 35 us Average current will be less than maximum specified Iccpgs VR OCP threshold should be high enough to support current levels described herein Table 8 Voltage and Current Specifications for the Dual Core Low Power Standard Voltage Processors 25 W in Standard Package Symbol Parameter Min Typ Max Unit Notes Vec in Enhanced Intel Dynamic Acceleration VCCDAM Technology Mode a ez i Ss VccurM Vcc at Highest Frequency Mode HFM 0 9 1 25 V 1 VcciFM Vcc at Lowest Frequency Mode LFM 0 85 1 025 V 1 VccsLFM Vcc at Super Low Frequency Mode Super LFM 0 75 0 95 V 1 Vcc BooT Default Vcc Voltage for Initial Power Up 1 2 V 2 6 Vccp AGTL Termination Voltage 1 0 1 05 1 1 V VCCA PLL Supply Voltage 1 425 1 5 1 575 V VccpPnsiP Vcc at Deeper Sleep 0 65 0 85 V 1 2 Vpc4 Vcc at Intel Enhanced Deeper Sleep State 0 6 0 85 V 1 2 VccpPPwbN Vcc at Deep Power Down Technology State C6 0 35 0 7 V 1 2 IccpEs Icc for Processors Recommended Design Target 38 A 12 Icc for Processors Processor Number Core Frequency Voltage P9700 2 8 GHz amp VccHFM 38 P9600 2 667 GHz am
77. ation Technology mode Normally the processor would exit Intel Dynamic Acceleration Technology as soon as two cores are active This can become an issue if the idle core is frequently awakened for a short periods i e high timer tick rates The hysteresis mechanism allows two cores to be active for a limited time before it transitions out of Intel Dynamic Acceleration Technology mode Intel Dynamic Acceleration Technology mode enabling requires Exposure via BIOS of the opportunistic frequency as the highest ACPI P state e Enhanced Multi Threaded Thermal Management EMTTM Intel Dynamic Acceleration Technology mode and EMTTM MSR configuration via BIOS Datasheet m 8 Low Power Features n tel j 2 5 2 6 Datasheet When in Intel Dynamic Acceleration Technology mode it is possible for both cores to be active under certain internal conditions In such a scenario the processor may draw a Instantaneous current Icc cong iwsr for a short duration of tryst however the average Icc current will be lesser than or equal to Iccpgs current specification Please refer to the Processor DC Specifications section for more details VID x The processor implements the VID x feature for improved control of core voltage levels when the processor enters a reduced power consumption state VID x applies only when the processor is in the Intel Dynamic Acceleration Technology performance state and one or more cores are in low power state i e
78. casion through an MWAIT C4 sub state field If shrink prevention is enabled the processor does not enter Intel Enhanced Deeper Sleep state or Intel Deep Power Down state since the L2 cache remains valid and in full size Datasheet m e Low Power Features n tel j 2 2 Enhanced Intel SpeedStep Technology The processor features Enhanced Intel SpeedStep Technology Following are the key features of Enhanced Intel SpeedStep Technology e Multiple voltage and frequency operating points provide optimal performance at the lowest power e Voltage and frequency selection is software controlled by writing to processor MSRs If the target frequency is higher than the current frequency Vcc is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency If the target frequency is lower than the current frequency the PLL locks to the new frequency and the Vcc is changed through the VID pin mechanism Software transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition completes e The processor controls voltage ramp rates internally to ensure glitch free transitions e Low transition latency and large number of transitions possible per second Processor core including L2 cache is unavailable for up to 10 us during the frequency transition The bus protocol BNR mechanism is used to block sn
79. ch Input i Output AE10 VCC Power Other AD1 BPM 2 Common Clock Output AE11 VSS Power Other AD2 VSS Power Other AE12 VCC Power Other Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Table 17 Pin Listing Table 17 Pin Listing Pin Pin Name eme SCH Pin Pin Name u AE13 Power Other AF22 D 62 4 Source Synch S AE14 55 Power Other utput AE15 VCC Power Other AF23 D 56 Source Synch Se AE16 VSS Power Other DSTBP 3 Input AE17 VCC Power Other AF24 Source Synch Output AE18 Power Other AF25 VSS Power Other AE19 VSS Power Other AF26 TESTA Test AE20 VCC Power Other B2 RSVD Reserved AE21 D 58 Source Synch B3 CMOS Input B4 LINTI CMOS Input AE22 D 55 Source Synch SEN B5 DPSLP CMOS Input AE23 vss Power Other B6 VSS Power other Input B7 VCC Power Other AE24 D 48 Source Synch Output B8 VSS Power Other AE25 Source Synch SC B9 vcc Power Other put B10 VCC Power Other AE26 VSS Power Other B11 VSS Power Other TESTS Test B12 VCC Power Other AF2 VSS Power Other B13 VSS Power Other AF3 VID S5 CMOS Output Bid ee ee AF4 VID 3 CMOS Output BE JEG sewer OEE AF5 VID i CMOS Output Bi Jes Rowe SE AF6 VSS Power Other B1
80. cification should be used to design the processor thermal solution The TDP is not the maximum theoretical power the processor can generate 2 Not 100 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum T has been reached The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser than TDP in HFM At Tj of 105 C At Tj of 50 C At Tj of 35 C s EO 106 Datasheet m e Thermal Specifications and Design Considerations n tel Table 26 Power Specifications for the Single Core Ultra Low Voltage 5 5 W SFF Processors Processor Thermal Design F Symbol Number Core Frequency amp Voltage Power Unit Notes SU3500 1 4 GHz amp HFM 5 5 S 1 2 GH HFM V TDP U3300 GHz amp cc 5 5 W 1 4 5 1 2 GHz amp Super LFM Vcc 5 5 6 0 8 GHz amp Super LFM Vcc 5 Symbol Parameter Min Typ Max Unit Notes P Auto Halt Stop Grant Power AH at VccurM 2 1 W 2 5 7 PsGNT at VccsirM 1 4 Sleep Power Psi p at VCcCHFM 1 8 W 2 5 7 at Vccsi rM 1 2 Deep Sleep Power
81. d averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested This is a power up peak current specification that is applicable when Vccp is high and Vcc cong is low This is a steady state Icc current specification that is applicable when both Vccp and Vcc core are high Processor Icc requirements in Intel Dynamic Acceleration Technology mode are lesser than Icc in HFM The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV Instantaneous current Icc core inst Of 44 A has to be sustained for short time over of 35 us Average current will be less than maximum specified Iccpgs VR OCP threshold should be high enough to support current levels described herein Table 10 Voltage and Current Specifications for the Dual Core Low Voltage SFF Processor Symbol Parameter Min Typ Max Unit Notes Vcc in Enhanced Intel Dynamic Acceleration z Vccpam Technology Mode 0 3 Tras M 1 2 VccHFM Vec at Highest Frequency Mode HFM 0 9 1 175 V 1 VCccLFM Vcc at Lowest Frequency Mode LFM 0 85 1 025 V 1 VccsLrFM at Super Low Frequency Mode Super LFM 0 75 0 95 V 1 Vcc BOOT Default Vcc Voltage for Initial Power Up 1 20 V 2 6 8 Vccp AGTL Termination Voltage 1 00 1 05 1 10 V VCCA PLL Supply Voltage 1 425 1 5 1 575 V VccpPnsiP Vcc at Deeper Sl
82. die SRAM that resides in the Vccp domain At this point the core Vcc will be dropped to the lowest core voltage closer to O V The processor is now in an extremely low power state In Intel Deep Power Down Technology state the processor does not need to be snooped as all the caches are flushed before entering this state 17 m e n tel Low Power Features 2 1 2 6 3 18 Dynamic Cache Sizing Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions The second core is already in C4 and Intel Enhanced Deeper Sleep state or Deep Power Down Technology state C6 is enabled as specified in Section 2 1 1 6 The CO timer that tracks continuous residency in the Normal package state has not expired This timer is cleared during the first entry into Deeper Sleep to allow consecutive Deeper Sleep entries to shrink the L2 cache as needed The FSB speed to processor core speed ratio is below the predefined L2 shrink threshold The number of L2 cache ways disabled upon each Deeper Sleep entry is configured in the BBL_CR_CTL3 MSR The CO timer is referenced through the CLOCK_CORE_CST_CONTROL_STT MSR The shrink threshold under which the L2 cache size is reduced is configured in the PMG_CST_CONFIG_CONTROL MSR If the FSB speed to processor core speed ratio is above the predefined L2 shrink threshold then L2 cache expansion will b
83. e instantaneous Furthermore upon very frequent transitions between active and idle states the transitions may lag behind the idle state entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases Datasheet m e Low Power Features n tel j 2 4 2 4 1 Datasheet FSB Low Power Enhancements The processor incorporates FSB low power enhancements Dynamic FSB Power Down BPRI control for address and control input buffers Dynamic Bus Parking Dynamic On Die Termination disabling Low Vccp I O termination voltage e Dynamic FSB frequency switching The processor incorporates the DPWR signal that controls the data bus input buffers on the processor The DPWR signal disables the buffers when not used and activates them only when data bus activity occurs resulting in significant power savings with no performance impact BPRI control also allows the processor address and control input buffers to be turned off when the BPRI signal is inactive Dynamic Bus Parking allows a reciprocal power reduction in GMCH address and control input buffers when the processor deasserts its BRO pin The On Die Termination on the processor FSB buffers is disabled when the signals are driven low resul
84. e FSB or when the other core of the dual core processor accesses cacheable memory The processor core will transition to the CO state upon occurrence of a Monitor event SMI INIT LINT 1 0 NMI INTR or FSB interrupt message RESET will cause the processor core to immediately initialize itself Core C4 State Individual cores of the dual core processor can enter the C4 state by initiating a P_LVL4 or P LVL5 I O read to the P BLK or an MWAIT C4 instruction The processor core behavior in the C4 state is nearly identical to the behavior in the C3 state The only difference is that if both processor cores are in C4 the central power management logic will request that the entire processor enter the Deeper Sleep package low power state see Section 2 1 2 6 To enable the package level Intel Enhanced Deeper Sleep state Dynamic Cache Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the PMG CST CONFIG CONTROL MSR Refer to Section 2 1 2 6 for further details on Intel Enhanced Deeper Sleep state Datasheet m e Low Power Features n tel j 2 1 1 7 2 1 2 2 1 2 1 2 1 2 2 Datasheet Core Deep Power Down Technology Code Name C6 State Deep Power Down Technology state is a new power saving state which is being implemented on the processor In Deep Power Down Technology the processor saves its entire architectural state onto an on die SRAM hence allowing it to lower its main core voltage to any value ev
85. e Synch p Input Output u2 AL30 Source Synch Output w21 VCCP Power Other Power Other w22 D 41 Source Synch aa Input Wi A 21 Source Synch Output W23 VSS Power Other Datasheet Package Mechanical Specifications and Pin Information Table 17 Pin Listing Pin Pin Name Signal Buffer Directi Type on Input W24 D 43 Source Synch Output w25 D 44 Source Synch DH y Output W26 VSS Power Other Input Y1 COMP 3 Power Other Output Y2 A 17 amp Source Synch I Put Output Y3 VSS Power Other Input 4 29 4 Source Synch Output Y5 A 22 amp Source Synch I Put y Output Y6 VSS Power Other Y21 VSS Power Other Input Y22 D 32 Source Synch Output Y23 D 42 amp Source Synch I Put Output Y24 VSS Power Other Input Y25 D 40 Source Synch Output DSTBN 2 Input Y26 Source Synch Output Datasheet intel Figure 18 Package Mechanical Specifications and Pin Information Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Left Side AER A 17 E 31 4 Heu 19 4 BPM 3 Al22 A 34 Al32 AIR 29 ARE VID 4 VID 1 VID S VID 3 VID 2 2 D BPM 1 D VID 6 BPM 0 De Al20 AIDS ADR 18 4 Al25 26 AAR ADAp An 2
86. e processor and system core logic also FSB known as the chipset components AGTL Advanced Gunning Transceiver Logic Used to refer to Assisted GTL signaling technology on some Intel processors Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not Storage be connected to any supply voltages have any I Os biased or receive any Conditions clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Enhanced Intel SpeedStep Technology that provides power management capabilities to laptops Technology Processor core die with integrated L1 and L2 cache All AC timing and signal Processor Core integrity specifications are at the pads of the processor core 8 Datasheet Introduction 1 2 Datasheet intel Term Definition Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vu
87. e requested If the ratio is zero then the ratio will not be taken into account for Dynamic Cache Sizing decisions Upon STPCLK deassertion the first core exiting Intel Enhanced Deeper Sleep state or Deep Power Down Technology state will expand the L2 cache to two ways and invalidate previously disabled cache ways If the L2 cache reduction conditions stated above still exist when the last core returns to C4 and the package enters Intel Enhanced Deeper Sleep state or Deep Power Down Technology state C6 then the L2 will be shrunk to zero again If a core requests a processor performance state resulting in a higher ratio than the predefined L2 shrink threshold the CO timer expires or the second core not the one currently entering the interrupt routine requests the C1 C2 or C3 states then the whole L2 will be expanded upon the next interrupt event In addition the processor supports Full Shrink on L2 cache When the MWAIT Deep Power Down Technology state instruction is executed with a 2 in ECX 3 0 the micro code will shrink all the active ways of the L2 cache in one step This ensures that the package enters Deep Power Down Technology immediately when both cores are in CC6 instead of iterating till the cache is reduced to zero The operating system OS is expected to use this hint when it wants to enter the lowest power state and can tolerate the longer entry latency L2 cache shrink prevention may be enabled as needed on oc
88. ecognition of this signal following an input output write instruction it must be valid along with the TRDY assertion of the corresponding input output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 Input Output Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTB O A 35 17 ADSTB 1 BCLK 1 0 Input The differential pair BCLK Bus Clock determines the FSB frequency All FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss BNR Input Output BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions BPM 2 1 BPM 3 0 Output Input Output BPM 3 0 Breakpoint Monitor are breakpoint and performance monitor signals They
89. ectively referred to as Adaptive Thermal Monitoring features TM1 and TM2 can co exist within the processor If both TM1 and TM2 bits are enabled in the auto throttle MSR TM2 takes precedence over TM1 However if Force TM1 over TM2 is enabled in MSRs via BIOS and TM2 is not sufficient to cool the processor below the maximum operating temperature then TM1 will also activate to help cool down the processor If a processor load based Enhanced Intel SpeedStep Technology transition through MSR write is initiated when a TM2 period is active there are two possible results 1 If the processor load based Enhanced Intel SpeedStep Technology transition target frequency is higher than the TM2 transition based target frequency the processor load based transition will be deferred until the TM2 event has been completed 2 If the processor load based Enhanced Intel SpeedStep Technology transition target frequency is lower than the TM2 transition based target frequency the processor will transition to the processor load based Enhanced Intel SpeedStep Technology target frequency point The TCC may also be activated via on demand mode If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1 the TCC will be activated immediately independent of the processor temperature When using on demand mode to activate the TCC the duty cycle of the clock modulation is programmable via bits 3 1 of the same ACPI Intel Thermal Monitor control regi
90. ed These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum has been reached 4 The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 5 Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser than TDP in HFM 6 At Tj of 105 C 7 At Tj of 50 C 8 At Tj of 35 C 101 intel Table 21 102 Thermal Specifications and Design Considerations Power Specifications for the Dual Core Standard Voltage Processor Processor Thermal Design P Symbol N mber Core Frequency amp Voltage Power Unit Notes T9900 3 06 GHz Vecuem 35 T9800 2 93 GHZ amp VCcCHFM 35 T9600 2 80 GHz amp VCcCHFM 35 joa TDP T9550 2 66 GHz amp VCcCHFM 35 Ww 5 6 T9400 2 53 GHz amp VCcCHFM 35 t 1 6 GHz amp VccLFM 22 0 8 GHz amp Vecsiem 12 Symbol Parameter Min Typ Max Unit Notes P Auto Halt Stop Grant Power Ge at VccurM 13 9 Ww 2 5 7 SCNT at VCCSLFM 5 0 Sleep Power Psi p at VccHFM 13 1 Ww 2 5 7 at VCCSLFM 4 8 Deep Sleep Power at VccurM 5 5 Ww 2 5 8 at VCCSLFM 2 2 Deeper Sleep Power
91. eep 0 65 0 85 V 1 Vpca Vcc at Intel Enhanced Deeper Sleep State 0 6 0 85 1 VccpPPwpN Vcc at Deep Power Down Technology State C6 0 35 0 7 V 1 Iccpes Icc for Processors Recommended Design Target 27 A 5 Processor Number Core Frequency Voltage SL9600 2 13 GHz amp VCcCHFM 27 Icc SL9400 1 86 GHz amp Vccurw 27 SL9300 1 6 GHz Vccurew 27 A 3 4 12 1 6 GHz amp VCCLFM 25 5 0 8 GHz amp VCcCSLFM 15 I Icc Auto Halt amp Stop Grant E HFM 12 3 A 3 4 12 SGNT SuperLFM 8 2 Icc Sleep Isi p HFM 11 8 A 3 4 12 SuperLFM 8 0 38 Datasheet Electrical Specifications i n tel Table 10 Voltage and Current Specifications for the Dual Core Low Voltage SFF Processor Symbol Parameter Min Typ Max Unit Notes Icc Deep Sleep Ipsip HFM 10 5 A 3 4 12 SuperLFM 7 5 IDPRSLP Icc Deeper Sleep 6 5 A 3 4 Ipca Icc Intel Enhanced Deeper Sleep 5 6 A 3 4 IppwpN Icc Deep Power Down Technology State C6 3 2 A 3 4 Power Supply Current Slew Rate at Processor _ dIcc or Package Pin 600 mA us 7 9 Icc for VccA Supply E 130 mA I Icc for Vccp Supply before Vcc Stable u 4 5 A 10 Icc for Vccp Supply after Vcc Stable 2 5 A 11 NOTES 1 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values
92. en as low as 0 V When the core enters Deep Power Down Technology state it saves the processor state that is relevant to the processor context in an on die SRAM that resides on a separate power plane Vccp I O power supply This allows the main core Vcc to be lowered to any arbitrary voltage including 0 V The on die storage for saving the processor state is implemented as a per core SRAM Package Low power State Descriptions Normal State This is the normal operating state for the processor The processor remains in the Normal state when at least one of its cores is in the CO C1 AutoHALT or C1 MWAIT state Stop Grant State When the STPCLK pin is asserted each core of the dual core processor enters the Stop Grant state within 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Processor cores that are already in the C2 C3 or C4 state remain in their current low power state When the STPCLK pin is deasserted each core returns to its previous core low power state Since the AGTL signal pins receive power from the FSB these pins should not be driven allowing the level to return to Vccp for minimum power drawn by the termination resistors in this state In addition all other input pins on the FSB should be driven to the inactive state RESET causes the processor to immediately initialize itself but the processor will stay in Stop Grant state When RESET is asserted by the s
93. encies and voltages as the resolved request and transition to that frequency and voltage The processor also supports Dynamic FSB Frequency Switching and Intel Dynamic Acceleration Technology mode on select SKUs The operating system can take advantage of these features and request a lower operating point called SuperLFM due to Dynamic FSB Frequency Switching and a higher operating point Intel Dynamic Acceleration Technology mode Datasheet 19 m 8 n tel Low Power Features 2 3 Note Caution Caution 20 Extended Low Power States Extended low power states CXE optimize for power by forcibly reducing the performance state of the processor when it enters a package low power state Instead of directly transitioning into the package low power state the enhanced package low power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point Upon receiving a break event from the package low power state control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs The advantage of this feature is that it significantly reduces leakage while in the Stop Grant and Deeper Sleep states Deep Power Down Technology is always enabled in the extended low power state as described above Long term reliability cannot be assured unless all the Extended Low Power States
94. ent between the individual core DTS Additionally the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power mechanical and thermal attach and software application The system designer is required to use the DTS to ensure proper operation of the processor within its temperature operating specifications m n tel Thermal Specifications and Design Considerations 5 3 112 Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs These thresholds have the capability of generating interrupts via the core s local APIC Refer to the Inte 64 and IA 32 Architectures Software Developer s Manuals for specific register and programming details Out of Specification Detection Overheat detection is performed by monitoring the processor temperature and temperature gradient This feature is intended for graceful shutdown before the THERMTRIP is activated If the processor s TM1 or TM2 are triggered and the temperature remains high an Out Of Spec status and sticky bit are latched in the status MSR register and generates a thermal interrupt PROCHOT Signal Pin An external signal PROCHOT processor hot is asserted when the processor die temperature has reached its maximum operating temperature If TM1 or TM2 is enabled then the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertio
95. er urpu AD6 VID 0 CMOS Output AB25 D 47 Source Synch E AD7 VCC Power Other AD VSS P th AB26 vss Power Other i EE AD9 VCC P th AC1 PREQ Common Clock Input 5 po s AD1 V P t AC2 PRDY Common Clock Output ES din i AD11 V P t AC3 VSS Power Other EE AD12 VCC Power Other AC4 BPM 3 Common Clock Output AD13 vss Power Other AC5 TCK CMOS Input AD14 Power Other AC6 VSS Power Other AD15 VCC Power Other AC7 VCC Power Other AD16 VSS Power Other AC8 VSS Power Other AD17 VCC Power Other AC9 VCC Power Other AD18 Power Other AC10 VCC Power Other AD19 VSS Power Other AC11 VSS Power Other AD20 D 54 Source Synch Gen AC12 VCC Power Other p Input AC13 VCC Power Other AD21 D 59 Source Synch Car ACTA VSS Power Other AD22 VSS Power Other AC15 VCC Power Other Input AC16 55 Power Other ADS Plot Source SYNE oi itout AC17 vcc Power Other AD24 D 49 Source Synch at AC18 VCC Power Other SEN AC19 VSS Power Other AD25 VSS Power Other Input AD26 GTLREF Power Other Input AC20 DINV 3 Source Synch Output VSS Power Other AC21 VSS Power Other AE2 VID 6 CMOS Output D 60 amp Source Synch E AE3 VID 4 CMOS Output utpu AE4 VSS Power Other AC23 D 63 f Source Synch See AES VID 2 CMOS Output AE PSI CMOS tput AC24 VSS Power Other i B PUER Input AE7 VSSSENSE Power Other Output AC25 D 57 Source Synch Output AE8 VSS Power Other AE9 VCC Power Other AC26 D 53 amp Source Syn
96. erved Li REQ 4 Source Synch Pd N6 VCCP Power Other utpu N21 VCCP Power Other L2 A 13 Source Synch Input Input Output N22 D 16 Source Synch Output L3 VSS Power Other N23 VSS Power Other Input L4 A S Source Synch oou N24 DINV 1 Source Synch UE Input L5 A 4 Source Synch oou N25 D 31 Source Synch Ser L6 VSS Power Other N26 VSS Power Other L21 VSS Power Other CET P1 A 15 Source Synch SE L22 D 22 Source Synch p Output Input Input P2 A 12 Source Synch Output L23 D 20 amp Source Synch a p utpu P3 vss Power Other L24 VSS Power Other PTT P4 A 14 amp Source Synch SE L25 D 29 Source Synch p Output Input DSTBN 1 Input P5 A 11 Source Synch Output L26 Source Synch Output pica P6 VSS Power Other Mi ADSTBIO Source synch DON P21 VSS Power Other Output z 7 nput M2 VSS Power Other P22 D 26 Source Synch Output Input M3 A 7 Source Synch Output P23 D 25 4 Source Synch Ge utput M4 RSVD Reserved P24 vss Power Other M5 VSS Power Other Input M6 VCCP Power Other p25 D 24 Source Synch Output M21 VCCP Power Other 77 m n tel Package Mechanical Specifications and Pin Information Table 17 Pin Listing Table 17 Pin Listing Pin Pin Name Signal Buffer Directi Pin 4 Pin Name Signal Buffer Directi Type on Type o
97. formation here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel E 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information Enhanced Intel SpeedStep Technology for specified units of this processor are available See the Processor Spec Finder at http processorfinder intel com or contact your Intel representative for more information Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain platform software enabled for it Functionality performance or other benefits
98. ic mode must be enabled for the processor to operate within specifications Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser than TDP in HFM At Tj of 105 C At Tj of 50 C At Tj of 35 C ON Du 104 Datasheet Thermal Specifications and Design Considerations ntel Table 24 Power Specifications fro the Dual Core Low Voltage LV SFF Processors Processor Thermal Design Symbol Number Core Frequency amp Voltage Power Unit Notes SL9600 2 13 GHz amp HFM Vcc 17 SL9400 1 86 GHz amp HFM Vcc 17 1 6 GHz amp HFM Vcc 1 4 5 TDP SL9300 1 6 GHz amp Super LFM Vcc 17 W 6 0 8 GHz amp Super LFM Vcc 16 7 10 Symbol Parameter Min Typ Max Unit Notes p Auto Halt Stop Grant Power ee at VccurM 6 3 W 2 5 7 SGNT at Vccsi FM 3 0 Sleep Power Psip at VccurM 5 7 W 2 5 7 at Vccsi FM 2 8 Deep Sleep Power at VccurM 2 6 W 2 5 8 at Vccsi EM 1 3 P Deeper Sleep Power 0 9 Ww 1 Poca Intel Enhanced Deeper Sleep State Power 0 8 Ww 1 Intel amp Deep Power Down Power 0 3 Ww 1 Tj Junction Temperature 0 105 C 14 NOTES 1 The TDP specification should be used to design the processor thermal solution The TDP is not the maximum theoretical power the processor can generate 2 Not 100 tested These power specifications are determined by characterization of the processor currents
99. ich is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Intel Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Enhanced Halt State 2 The voltage specifications are assumed to be measured across Vcc sense and Vss sense pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 3 Specified at 100 C T 4 Specified at the nominal Vcc 5 Measured at the bulk capacitors on the motherboard 6 Vcc Boor tolerance shown in Figure 4 and Figure 5 7 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested 8 This is a power up peak current specification that is applicable when Vccp is high and Vcc core is low 9 This is a steady state Icc current specification that is applicable when both Vccp and Vec core are high 10 Processor Icc requirements in Intel Dynamic Acceleration Technology mode are lesser than Icc in HFM 11 The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor
100. ied at 105 C T Specified at the nominal Vcc Measured at the bulk capacitors on the motherboard Vcc Boor tolerance shown in Figure 7 and Figure 8 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested This is a power up peak current specification that is applicable when Vccp is high and Vcc core is low This is a steady state Icc current specification that is applicable when both Vccp and Vcc core are high Processor Icc requirements in Intel Dynamic Acceleration Technology mode are lesser than Icc in HFM The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV Instantaneous current Icc core inst Of 24 A has to be sustained for short time wer of 35 5 Average current will be less than maximum specified Iccpgs VR OCP threshold should be high enough to support current levels described herein Table 12 Voltage and Current Specifications for the Ultra Low Voltage Single Core 5 5 W SFF Processor Symbol Parameter Min Typ Max Unit Notes VccHFM at Highest Frequency Mode HFM 0 775 1 1 V 1 2 Vcci EM Vcc at Lowest Frequency Mode LFM 0 8 0 975 V 1 2 VccsiFM at Super Low Frequency Mode Super LEM 0 725 0 925 V 1 2 Vcc Boor Default Vcc Voltage for Initial Power Up 1 20 V 2 6 8 Vccp AGTL
101. in name Added Table 18 Added Table 23 Added Table 24 Added Table 25 320120 002 August 2008 e Added information for Intel Core 2 Duo T9800 T9550 P9600 320120 003 P8700 January 2009 e Added information for Intel Core 2 Duo processor skus below Updated Table 7 and 21 with T9900 Updated Table 9 and 23 with SP9600 Updated Table 10 and 24 with SL9600 Updataed Table 11 and 25 with SU9600 Updated Table 12 and 26 with SU3500 320120 004 March 2009 8 6 Datasheet Introduction j n tel 9 1 Introduction The Intel Core 2 Duo mobile processor Intel Core 2 Duo mobile processor low voltage LV ultra low voltage ULV in small form factor SFF package and Intel Core 2 Extreme mobile are high performance low power mobile processor based on the Intel Core microarchitecture for Intel Centrino 2 processor technology This document contains electrical mechanical and thermal specifications for the following processors e The Intel Core 2 Duo processors and Intel Core 2 Extreme processors support the Mobile Intel 4 Series Express Chipset and Intel ICH9M I O controller Dual core extreme edition DC XE Standard voltage SV 25 W processor in standard package Power Optimized Performance POP e The Intel Core 2 Duo processor in SFF package supports the Mobile Intel GS45 Express Chipset and Intel ICH9M SFF I O controller This document co
102. intel Intel Core 2 Duo Mobile Processor Intel Core 2 Solo Mobile Processor and Intel Core 2 Extreme Mobile Processor on 45 nm Process Datasheet For platforms based on Mobile Intel 4 Series Express Chipset Family March 2009 Document Number 320120 004 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The in
103. inuously The Intel Thermal Monitor controls the processor temperature by modulating starting and stopping the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature The Intel Thermal Monitor uses two modes to activate the TCC automatic mode and on demand mode If both modes are activated automatic mode takes precedence There are two automatic modes called Intel Thermal Monitor 1 TM1 and Intel Thermal Monitor 2 TM2 These modes are selected by writing values to the MSRs of the processor After automatic mode is enabled the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation When TM1 is enabled and a high temperature situation exists the clocks will be modulated by alternately turning the clocks off and on at a 50 duty cycle Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase Once the temperature has returned to a non critical level modulation ceases and TCC goes inactive A small amount of hysteresis has been included to prevent rapid 109 110 n tel Thermal Specifications and Design Considerations active inactive transitions of the TCC when the processor temperature is near the trip point The duty cycle is factory configured and cannot be modified Also automatic mode does not require any additional hardwa
104. ll Signal Name Ball Signal Ball Name Number Number Name Number VCCSENSE BD12 VSS AB42 VSS AG17 VID 0 BD8 VSS AC3 VSS AG19 VID 1 BC7 VSS AC15 VSS AG21 VID 2 BB10 VSS AC17 VSS AG23 VID 3 BB8 VSS AC19 VSS AG25 VID 4 BC5 vss AC21 vss AG27 VID 5 BB4 VSS AC23 VSS AG29 VID 6 AY4 vss AC25 vss AG31 VSS A5 VSS AC27 VSS AG39 VSS A7 VSS AC29 VSS AH6 VSS A9 VSS AC31 VSS AH8 VSS A11 VSS AC39 VSS AH10 VSS A15 VSS AD6 VSS AH12 VSS A17 VSS ADS VSS AH34 VSS A19 VSS AD10 VSS AH36 VSS A21 VSS AD12 VSS AH38 VSS A23 VSS AD34 VSS AH42 VSS A25 VSS AD36 VSS AJ3 VSS A27 VSS AD38 VSS AJ15 VSS A29 VSS AD42 VSS AJ17 VSS A31 VSS AE3 VSS AJ19 VSS A39 VSS AE15 VSS AJ21 VSS A41 VSS AE17 VSS AJ23 VSS AA3 VSS AE19 VSS AJ25 VSS AA15 VSS AE21 VSS AJ27 VSS AA17 VSS AE23 VSS AJ29 VSS AA19 VSS AE25 VSS AJ31 VSS AA21 VSS AE27 VSS AJ39 VSS AA23 VSS AE29 VSS AK6 VSS AA25 VSS AE31 VSS AK8 VSS AA27 VSS AE39 VSS AK34 VSS AA29 VSS AF6 VSS AK42 VSS AA31 VSS AF8 VSS AL3 VSS AA39 VSS AF34 VSS AL15 VSS AB6 VSS AF42 VSS AL17 VSS AB8 VSS AG3 VSS AL19 VSS AB34 VSS AG15 VSS AL21 89 intel Package Mechanical Specifications and Pin Information Table 18 Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name 90 Signal Ball Signal Name Ball Signal Ball Name Number Number Name Number VSS AL23 VSS AR29 VSS AW13 VSS
105. lnerabilities and can thus help improve the overall security of the system See the Inte 64 and IA 32 Architectures Software Developer s Manuals for more detailed information Intel 64 64 bit memory extensions to the IA 32 architecture Technology Intel Processor virtualization that when used in conjunction with Virtual Machine Virtualization Monitor software enables multiple robust independent software Technology environments inside a single platform Half ratio support N 2 for Core to Intel Core 2 Duo processors and Intel Core 2 Extreme processors support the N 2 feature that allows having fractional core to bus ratios This feature Bus ratio provides the flexibility of having more frequency options and being able to have products with smaller frequency steps TDP Thermal Design Power Vcc The processor core power supply Vss The processor ground LV Low voltage ULV Ultra Low Voltage DC XE Dual core Extreme Edition References Material and concepts available in the following documents may be beneficial when reading this document Document d Number Intel Core 2 Duo Mobile Processor Intel Core 2 Solo Mobile Processor Intel Core 2 Extreme Processor on 45 nm Technology 320121 Specification Update Mobile Intel 4 Series Express Chipset Family Datasheet 320122 Mobile Intel 4 Series Express Chipset Family Specification Update 320123 In
106. lute maximum and minimum ratings only which lie outside the functional limits of the processor Only within specified operation limits can functionality and long term reliability be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes 2 TsrORAGE Processor Storage Temperature 40 85 3 4 5 TsroRAGE Processor Storage Temperature 25 6 Any Processo
107. mployed by the processor during a power management event Intel Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Enhanced Halt State 2 The voltage specifications are assumed to be measured across sgyse and Vss_sense pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 3 Specified at 105 C T 4 Specified at the nominal Vcc 5 Measured at the bulk capacitors on the motherboard 6 Vcc Boor tolerance shown in Figure 4 and Figure 5 7 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested 8 This is a power up peak current specification that is applicable when Vccp is high and Vcc core is low 9 This is a steady state Icccurrent specification that is applicable when both Vccp and Vcc cone are high 10 Processor Icc requirements in Intel Dynamic Acceleration Technology mode are lesser than Icc in HFM 11 The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV 12 Instantaneous current coge wer Of 49 A has to be sustained for short time wer of 35 us Average 36 current will be less than maximum specified Iccpgs VR OCP threshold should be high enough to
108. n Input Input P26 D 18 Source Synch Output U5 A 18 Source Synch Output R1 A 16 4 Source Synch cn U6 VSS Power Other U21 55 Power Other R2 VSS Power Other Input Input U22 DINV 2 Source Synch Output R3 A 19 Source Synch Output Input Input U23 D 39 Source Synch Output R4 A 24 Source Synch 5 S P ER U24 VSS Power Other i E a U25 D 38 Source Synch I Put R6 VCCP Power Other y Output R21 VCCP Power Other U26 COMPI 1 Power Other usd R22 VSS Power Other utpu ot ADSTB 1 Input Input Vi Source Synch R23 D 19 Source Synch Output Output Input V2 VSS Power Other R24 D 28 Source Synch Output v3 RSVD Reserved R29 Nee newer Omer v4 A 31 Source Synch Uu Input R26 COMP 0 Power Other Output V5 VSS Power Other T1 VSS Power Other V6 VCCP Power Other T2 RSVD Reserved V21 VCCP Power Other 13 A 26 Source Synch beer WSs Powe Ome Input T4 VSS Power Other v23 D 36 Source Synch Output Input Input T5 A 25 Source Synch Output V24 D 34 Source Synch Output T6 VCCP Power Other V25 VSS Power Other Tel Ke Bees v26 D 35 Source Synch SE Input T22 D 37 Source Wi VSS Power Other T23 Powel Omer W2 2714 Source Synch putt T24 p 27 Source Synch odd nee w3 A 32 Source Synch pu Input Output T25 D 30 Source Synch ergoe w4 VSS Power Other 1 Fower orner ws A 28 f Source Synch Ui A 23 Source Synch Gen Sep P w6 A 20 Sourc
109. n listing of the processor and the location of all RSVD pins For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level Unused active low AGTL inputs may be left as no connects if AGTL termination is provided on the processor silicon Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected The TEST1 TEST2 TEST3 TESTA TEST5 TEST6 TEST7 pins are used for test purposes internally and can be left as No Connects FSB Frequency Select Signals BSEL 2 0 The BSEL 2 0 signals are used to select the frequency of the processor input clock BCLK 1 0 These signals should be connected to the clock chip and the appropriate chipset on the platform The BSEL encoding for BCLK 1 0 is shown in Table 3 BSEL 2 0 Encoding for BCLK Frequency BSEL 2 BSEL 1 BSEL O BCLK Frequency L L L 266 MHz L L H RESERVED L H H RESERVED L H L 200 MHz H H L RESERVED H H H RESERVED H L H RESERVED H L L RESERVED 29 Table 4 30 FSB Signal Groups Electrical Specifications The FSB signals have been combined into groups by buffer type in the following sections In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving Wi
110. n or deassertion of PROCHOT Refer to the an interrupt upon the assertion or deassertion of PROCHOT Refer to the Intel 64 and IA 32 Architectures Software Developer s Manuals for specific register and programming details The processor implements a bi directional PROCHOT capability to allow system designs to protect various components from overheating situations The PROCHOT signal is bi directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components Only a single PROCHOT pin exists at a package level of the processor When either core s thermal sensor trips PROCHOT signal will be driven by the processor package If only TM1 is enabled PROCHOT will be asserted regardless of which core is above its TCC temperature trip point and both cores will have their core clocks modulated If TM2 is enabled then regardless of which core s are above the TCC temperature trip point both cores will enter the lowest programmed TM2 performance state It is important to note that Intel recommends both TM1 and TM2 to be enabled When PROCHOT is driven by an external agent if only TM1 is enabled on both cores then both processor cores will have their core clocks modulated If TM2 is enabled on both cores then both processor cores will enter the lo
111. nagement features To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed so the processor remains within the minimum and maximum junction temperature Tj specifications at the corresponding thermal design power TDP value listed in the tables below Operating the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system Power Specifications for the Dual Core Extreme Edition Processor Processor Thermal Design gt Symbol Number Core Frequency amp Voltage Power Unit Notes 3 06 GHz amp VccHFM 44 14 TDP X9100 1 6 GHz amp VCCLFM 29 W 5 6 0 8 GHz amp VCCSLFM 20 Symbol Parameter Min Typ Max Unit Notes P Auto Halt Stop Grant Power GC at VccurM 18 8 Ww 2 5 7 SGNT at Vccsi FM 6 7 Sleep Power Psi p at VccHFM 17 8 2 5 7 at VccsirM 6 4 Deep Sleep Power at VccHFM 82 w 2 5 8 at Vccsi FM 3 8 Ppprstp Deeper Sleep Power 1 9 WwW 2 8 Poca Intel Enhanced Deeper Sleep state Power 1 7 W 2 8 Pce Intel Deep Power Down Power 1 3 W 2 8 Tj Junction Temperature 0 105 C 3 4 NOTES 1 The TDP specification should be used to design the processor thermal solution The TDP is not the maximum theoretical power the processor can generate 2 Not 100 test
112. nch Output Common Input BNR E2 Source Input Clock Output A 20 W Synch Output Common Input BPM 0 AD4 Source Input Clock Output A 21 U4 Synch Output Cumman BPM 1 AD3 Output Source Input Clock A 22 Y5 Synch Output Common Source Input BPM 2 ADI Clock Output A 23 U1 Synch Output Common Input BPM 3 AC4 Glock Output 61 intel Package Mechanical Specifications and Pin Information Table 16 Pin Name Listing Table 16 Pin Name Listing Signal Signal Pin Name Pin Buffer Direction Pin Name Pin Buffer Direction Type Type BPRI G5 SE Input D 14 22 pti Ce mas Temm ER enne Set imi BSEL 0 B22 CMOS Output D 16 N22 ean Input BSEL 1 B23 CMOS Output ynch EE BSEL 2 C21 CMOS Output D 17 K25 nd oU COMPLOJ REG 181 P26 pen odie COMP 1 U26 pre D 19 amp R23 p COMP 2 AAT Ge M D 20 amp 123 ind min SSES Y1 pod Su D 21 amp M24 ind Geer D 0 E22 EEN SC 2211 122 win D 1 SE Sec Ce D 23 amp M23 SEN GER D 2 SCH Sec Su D 24 amp P25 pon eut D 3 ae Eds TA D 25 amp P23 SEN D 4 F23 pode GC D 26 amp P22 pou D 5 Se SE D 27 amp T24 pow Ge D 6 E25 pod D 28 amp R24 Sch D 7 E23 poni e D 29 amp 125 ndi der D 8 K
113. nii epe ava EE bo ER 25 3 2 3 FSB Clock BCLK 1 0 and Processor Clocking eee 25 3 3 Voltage Identification and Power Sequencing eceeeee eee e eee ee eens ee mmn 26 3 4 Catastrophic Thermal Protection SE NENNEN ENEE RENE NEEN EES REENEN ENN 29 3 5 Reserved and Unused PINS 2 eost eee resa NEEN SE pa ga ENEE SEENEN ENN EEN d Rea 29 3 6 FSB Frequency Select Signals BSEL 2 0 esses 29 3 2 FSB Signal GroupS EMT 30 BiB SOMOS Le AIS ccc E 31 3 9 Maximum E ele Le CEET 31 3 10 Processor DC Specifications iiaia nass a nnn 32 4 Package Mechanical Specifications and Pin Information 51 4 1 Package Mechanical 51 4 2 Processor Pinout and Pin List 3 iiec een SENN sex rrt Ea ANAE 59 4 3 Alphabetical Signals Reference eene meses een 93 5 Thermal Specifications and Design Considerations teens 101 5 1 Monitoring Di Temperature siseses ete spe suadeo utu cetur de diede QUA RE nee QUE D e E ER TEE TEQUE ES 108 5 1 1 Thermal Diode iiiter extremen oxi RRE dE dE 108 5 1 2 Intel Thermal MOhitOr 220 DEE retta EES DRE RD Rin SEE
114. normal state HFM to LFM and in lower power states Deep Sleep and Deeper Sleep 97 intel Package Mechanical Specifications and Pin Information Table 19 Signal Description Sheet 6 of 8 Name Type Description PWRGOOD Input PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal remains low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 Input Output REQ 4 0 Request Command must connect the appropriate pins of both FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 0 RESET Input Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least two milliseconds after Vcc and BCLK have reached their proper specifications On observing
115. ntains electrical mechanical and thermal specifications for Power Optimized Performance POP in SFF package Low voltage LV Processor in SFF package Ultra low voltage ULV dual core DC and single core SC Processors in SFF package Notes In this document 1 Intel Core 2 Duo processor and the Intel Core 2 Extreme processor are referred to as the processor 2 Intel Core 2 Duo LV ULV POP processors are referred to as SFF processor 3 Mobile Intel 4 Series Express Chipset is referred as the GMCH Key features include Dual core processor for mobile with enhanced performance e Supports Intel architecture with Intel Wide Dynamic Execution e Supports L1 cache to cache C2C transfer On die primary 32 KB instruction cache and 32 KB write back data cache in each core e The processor in DC XE standard voltage SV and LV have an on die up to 6 MB second level shared cache with Advanced Transfer Cache architecture e The processor in ULV single core and dual core have an on die up to 3 MB second level shared cache with Advanced Transfer Cache architecture e Streaming SIMD extensions 2 SSE2 streaming SIMD extensions 3 SSE3 supplemental streaming SIMD extensions 3 SSSE3 and SSE4 1 instruction sets e The processor in DC XE SV and LV are offered at 1066 MHz source synchronous front side bus FSB e The processor in ULV are offered at 800 MHz source synchronous FSB e Advanced power management features
116. obile Processor in SFF Package Listing by Ball Name Datasheet Signal Ball Signal Name Ball Signal Ball Name Number Number Name Number D 56 AY36 PRDY AV10 TMS AW5 D 57 AT40 PREQ AV2 TRDY L1 D 58 BC35 PROCHOT D38 TRST AV8 D 59 BC39 PSI BD10 VCC AA33 D 60 BA41 PWRGOOD E7 VCC AB16 D 61 BB40 REQ O R1 VCC AB18 D 62 BA35 REQ 1 R5 VCC AB20 D 63 AU43 REQ 2 U1 VCC AB22 DBR 17 REQ 3 P4 VCC AB24 DBSY Ji REQ 4 WE VCC AB26 DEFER N5 RESET G5 VCC AB28 DINV 0O P40 RS 0 K2 VCC AB30 DINV 1 R43 RS 1 H4 VCC AB32 DINV 2 AJ41 RS 2 K4 VCC AC33 DINV 3 BC37 RSVDO1 V2 VCC AD16 DPRSTP G7 RSVDO2 Y2 VCC AD18 DPSLP B8 RSVDO3 AG5 VCC AD20 DPWR C41 RSVD04 AL5 VCC AD22 DRDY F38 RSVDO5 J9 VCC AD24 DSTBN 0 K40 RSVDO6 F4 VCC AD26 DSTBN 1 U43 RSVDO7 H8 VCC AD28 DSTBN 2 AK44 SLP D10 VCC AD30 DSTBN 3 AY40 SMI E5 VCC AD32 DSTBP 0 J41 STPCLK F8 VCC AE33 DSTBP 1 W43 TCK AV4 VCC AF16 DSTBP 2 AL43 TDI AW7 VCC AF18 DSTBP 3 AY38 TDO AU1 VCC AF20 FERR D4 TEST1 E37 VCC AF22 GTLREF AW43 TEST2 D40 VCC AF24 HIT H2 TEST3 C43 VCC AF26 HITM F2 TEST4 AE41 VCC AF28 IERR B40 TEST5 AY10 VCC AF30 IGNNE F10 TEST6 AC43 VCC AF32 INIT D8 THERMTRIP B10 VCC AG33 LINTO C9 THRMDA BB34 VCC AH16 LINT1 C5 THRMDC BD34 VCC AH18 LOCK N1 THERMTRIP B10 VCC AH20 85 intel
117. ocessor cesses 101 Power Specifications for the Dual Core Standard Voltage 5 102 Power Specifications for the Dual Core Low Power Standard Voltage Processors 25 W in Standard Package TEES 103 Power Specifications for the Dual Core Power Optimized Performance 25 W SFF PFOCESSOMS T AEN EA SEENEN E EAR 104 Power Specifications fro the Dual Core Low Voltage LV SFF Processors 105 Power Specifications for the Dual Core Ultra Low Voltage ULV Processors 106 Power Specifications for the Single Core Ultra Low Voltage 5 5 W SFF Processors 107 Thermal Diode Interface oie coit te terea EE EE 108 Thermal Diode Parameters Using Transistor Model 109 Datasheet 5 intel Revision History Document Revision Number Number Description Date 320120 001 Initial Release July 2008 Chapter Update Chapter 1 Added introduction to the Intel Core 2 Duo Processor in SFF Package Section 4 1 Added the package coplanarity information for the processors in SFF Package e Figure Update Added Figure 7 Added Figure 8 Added Figure 14 Added Figure 15 Added Figure 18 through Figure 21 e Table Update Added Table 9 Added Table 10 Added Table 11 Added Table 12 Updated Table 16 Added Intel Core 2 Duo SFF Package Processor Ball listing by P
118. on snoop operation results Either FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall that can be continued by reasserting HIT and HITM together IERR Output IERR Internal Error is asserted by the processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET BINIT or INIT IGNNE Input IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute non control floating point instructions If IGNNE is deasserted the processor generates an exception on a non control floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an input output write instruction it must be valid along with the TRDY assertion of the corresponding input output Write bus transaction 96 Datasheet m 8 Package Mechanical Specifications and Pin Information n tel Table 19 Datasheet Signal Description Sheet 5 of 8 Name Type Description INIT Input INIT Initialization when as
119. onment may cause a noticeable performance loss 8 Datasheet 113
120. ooping Improved Intel Thermal Monitor mode When the on die thermal sensor indicates that the die temperature is too high the processor can automatically perform a transition to a lower frequency and voltage specified in a software programmable MSR The processor waits for a fixed time period If the die temperature is down to acceptable levels an up transition to the previous frequency and voltage point occurs An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management e Enhanced thermal management features Digital Thermal Sensor and Out of Specification detection Intel Thermal Monitor 1 TM1 in addition to Intel Thermal Monitor 2 TM2 in case of unsuccessful TM2 transition Dual core thermal management synchronization Each core in the dual core processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology but both cores must operate at the same frequency and voltage The processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole If both cores request the same frequency and voltage then the processor will transition to the requested common frequency and voltage If the two cores have different frequency and voltage requests then the processor will take the highest of the two frequ
121. oth cores are in active state PSI 2 functionality improves overall voltage regulator efficiency over a wide power range based on the C state and P state of the two cores The combined C state and P state of both cores are used to dynamically predict processor power The real time power prediction is compared against a set of predefined and configured values of CHH and CHL CHH is indicative of the active C state of both the cores and CHL is indicative that only one core is in active C state and the other core is in low power core state PSI 2 output is asserted upon crossing these thresholds indicating that the processor requires lower power The voltage regulator will adapt its power output accordingly Additionally the voltage regulator may switch to a single phase and or asynchronous mode when the processor is idle and fused leakage limit is less than or equal to the BIOS threshold value 23 24 Low Power Features Datasheet m Electrical Specifications 3 Electrical Specifications 3 1 Power and Ground Pins For clean on chip power distribution the processor will have a large number of power and Vss ground inputs All power pins must be connected to Vcc power ntel planes while all Vss pins must be connected to system ground planes Use of multiple power and ground planes is recommended to reduce I R drop The processor Vcc pins must be supplied the voltage determined by the VID Voltage ID pins 3 2 Decou
122. p VCcCHFM 38 Icc P8800 2 667 GHz amp VccHFM 38 P9500 2 53 GHz amp VccHFM 38 P8700 2 53 GHz VecHem 38 A 3 4 10 P8600 2 4 GHz amp VccHFM 38 P8400 2 267 GHz VecHem 38 1 6 GHz amp VCCLFM 27 7 0 8 GHz amp VccsiFM 17 5 Datasheet 35 i n tel Electrical Specifications Table 8 Voltage and Current Specifications for the Dual Core Low Power Standard Voltage Processors 25 W in Standard Package Symbol Parameter Min Typ Max Unit Notes I Icc Auto Halt amp Stop Grant Eis HFM 15 3 A 3 4 10 nid SuperLFM 10 5 Icc Sleep Isip HFM 14 6 A 3 4 10 SuperLFM 10 3 Icc Deep Sleep Ipsip HFM 12 9 A 3 4 10 SuperLFM 9 8 IDPRSLP Icc Deeper Sleep 7 3 A 3 4 Ipca Icc Intel Enhanced Deeper Sleep 6 7 A 3 4 Ippwon Icc Deep Power Down Technology State C6 4 3 A 3 4 Vcc Power Supply Current Slew Rate at Processor dIcc pr Package Pin 600 mA us 5 7 Icca Icc for VCCA Supply 130 mA I Iccc for Vecp Supply before Vec Stable u u 4 5 A 8 SES Icc for Vccp Supply after Vcc Stable 2 5 A 9 NOTES 1 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID e
123. p state is initiated by DPRSTP deassertion when either core requests a core state other than C4 or either core requests a processor performance state other than the lowest operating point Intel Enhanced Deeper Sleep State Intel Enhanced Deeper Sleep state is a sub state of Deeper Sleep that extends power saving capabilities by allowing the processor to further reduce core voltage once the L2 cache has been reduced to zero ways and completely shut down The following events occur when the processor enters Intel Enhanced Deeper Sleep state The last core entering C4 issues a P_LVL4 or P LVL5 I O read or an MWAIT C4 instruction and then progressively reduces the L2 cache to zero Once the L2 cache has been reduced to zero the processor triggers a special chipset sequence to notify the chipset to redirect all FSB traffic except APIC messages to memory The snoops are replied as misses by the chipset and are directed to main memory instead of the L2 cache This allows for higher residency of the processor s Intel Enhanced Deeper Sleep state e The processor drives the VID code corresponding to the Intel Enhanced Deeper Sleep state core voltage on the VID 6 0 pins Deep Power Down State Technology Code Named C6 State When both cores have entered the CC6 state and the L2 cache has been shrunk down to zero ways the processor will enter the Deep Power Down Technology state To do so both cores save their architectural states in the on
124. pc max HFM LFM Vcc coge nom HFM LFM Voc cone pc min HEMILFM 44 c Vec core min HFM LFM VR St Pt Error 1 Icc coRE 0 lcc cone max A Note 1 Vcc cone Set Point Error Tolerance is per below HFM LFM Tolerance Vcc cone VID Voltage Range 1 5 gt 0 7500V 11 5mV 0 5000V lt Vcc core lt 0 7500V 25mV 0 3000V lt Vcc cone lt 0 5000V NOTES 1 Applies to Low Voltage Ultra Low Voltage and Power Optimised Performance processors in 22 mmx22 mm package 2 Active mode tolerance depends on VID value 46 Datasheet Electrical Specifications i n tel Figure 8 Datasheet Deeper Sleep VCC and ICC Loadline for Low Voltage Ultra Low Voltage and Power Optimized Performance Processor Vcc cone V Slope 4 0 mV A at package VccSense VssSense pins Differential Remote Sense required Vcc cone max HFM LFM Voc core pc max Voc cong nom HFMILFM Vcc cone pc min HFM LFM Vocem Tolerance 000007707 V min HEM LFM iil VR St Pt Error 1 l CC CORE 0 Icc core max A HFM LFM Note 1 Vcc core Set Point Error Tolerance is per below Tolerance Vcc cone VID Voltage Range VID 1 5 3mV Vcc core gt 0 7500V 11 5mV 3mV 0 5000V lt Vcc cone lt 0 7500V Total tolerance window including ripple is 35mV for C6 0 3000V lt Vcc cone
125. pling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage such as electrolytic capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in the tables in Section 3 10 Failure to do so can result in timing violations or reduced lifetime of the component 3 2 1 Vcc Decoupling Vcc regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR and keep a low interconnect resistance from the regulator to the socket Bulk decoupling for the large current swings when the part is powering on or entering exiting low power states should be provided by the voltage regulator solution depending on the specific system design 3 2 2 FSB AGTL Decoupling The processors integrate signal termination on the die as well as incorporate high frequency decoupling capacitance on the processor package Decoupling must also be provided by the sy
126. poids vcc E13 ps B17 SE vcc E15 vcc B18 pod vcc E17 scald Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Table 16 Pin Name Listing Table 16 Pin Name Listing Signal Signal Pin Name Pin Buffer Direction Pin Name Pin Buffer Direction Type Type Power Power VCC E18 Other VCCP R6 Other Power Power VCC E20 Other VCCP R21 Other Power Power VCC F7 Other VCCP T6 Other Power Power VCC F9 Other VCCP T21 Other Power Power VCC F10 Other VCCP V6 Other Power Power VCC F12 Other VCCP V21 Other Power Power VCC F14 Other VCCP W21 Other Power Power VCC F15 Other VCCSENSE AF7 Other VCC F17 pee VID 0 AD6 CMOS Output VID 1 AF5 CMOS Output Power VCC F18 Other VID 2 AE5 CMOS Output ee EM Pawer VID 3 AF4 CMOS Output Other VID 4 AE3 CMOS Output VCCA B26 er VID 5 AF3 CMOS Output VID 6 AE2 CMOS Output Power VCCA C26 Other 2 Power Other Power VCCP G21 Other vss A4 Power Other Power VCCP J6 Other vss A8 Power Other Power VCCP J21 Other vss All Power Other Power VCCP K6 Power Other VSS A14 Other Power VCCP K21 Other vss A16 Power Other Power VCCP M6 Other vss A19 Power Other Power VCCP M21 Other vss 23 Power Other Power VCCP N6 Other vss A25 Power Other Power VCCP N21 Other 67 68
127. processor is incapable of responding to snoop transactions or latching interrupt signals No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state When the processor is in Deep Sleep Datasheet m e Low Power Features n tel j 2 1 2 6 2 1 2 6 1 2 1 2 6 2 Datasheet state it will not respond to interrupts or snoop transactions Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior Deeper Sleep State The Deeper Sleep state is similar to the Deep Sleep state but further reduces core voltage levels One of the potential lower core voltage levels is achieved by entering the base Deeper Sleep state The Deeper Sleep state is entered through assertion of the DPRSTP pin while in the Deep Sleep state The following lower core voltage level is achieved by entering the Intel Enhanced Deeper Sleep state which is a sub state of Deeper Sleep state Intel Enhanced Deeper Sleep state is entered through assertion of the DPRSTP pin while in the Deep Sleep only when the L2 cache has been completely shut down Refer to Section 2 1 2 6 1 and Section 2 1 2 6 3 for further details on reducing the L2 cache and entering Intel Enhanced Deeper Sleep state In response to entering Deeper Sleep the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID 6 0 pins Exit from Deeper Sleep or Intel Enhanced Deeper Slee
128. processor package Table 18 lists the SFF processor ballout alphabetically by signal name For signal descriptions refer to Section 4 3 Figure 16 Processor Pinout Top Package View Left Side 1 2 3 4 5 6 7 8 9 10 11 12 13 vss smi vss FERR A2oMe vcc vss VCC VCC vss VCC vec A Bi rsvp INIT4 um 5 4 vss vcc vss vcc vcc vss VCC vss C RESET vss 7 vss Linto THERM vss vcc vcc vss vcc vcc c D vss RsvD rsvp vss STPCLK PWRGO sip vss vcc vcc vss vcc vss D E DBSY BNR vss HiTm PPRSTP vcc vss vcc vcc vss vcc vec E BRO vss rspoj Rst1j vss Rsvb vcc vss VCC VCC vss VCC vss F G vss TRDY RS 2 vss BPRI HIT G H aps REQI1 vss Lock DEFER vss H J 9 4 vss REQDI ais vss VCCP J K vss REQ 2 REQIO vss 6 4 VCCP K L 413 A13 vss atsie 414 vss L M ADSTBIO vss apz RSVD vss VCCP M N vss A 8 A 10 amp vss Rsvp vccP N P A5 lan vss anaje Anis vss P R A 16 4 vss 1911 A24 vss VCCP R T vss rsvp A 26 4 vss 2514 vccP T u AP3 amp A 30 vss atije 1811 vss U v DSIBHI vss rsvp 3113 vss VCCP w vss A 27 amp A 32 vss 28 20 4 w y comers A17 vss 2914 A21
129. r Supply Voltage with Vcc Respect to Vss hs De M Ue etx Input Voltage with 0 1 1 45 V VinAsynch CMOS Ros Input Voltage with 0 1 1 45 V NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 31 n tel Electrical Specifications 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 4 This rating applies to the processor and does not include any tray or packaging 5 Failure to adhere to this specification can affect the long term reliability of the processor 6 For Intel Core 2 Duo mobile processors in 22x22 mm package 3 10 Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless noted otherwise The tables list the DC specifications for the processor and are valid only while meeting specifications for junction temperature clock frequency and input voltages The Highest Frequenc
130. re software drivers or interrupt handling routines Processor performance will be decreased by the same amount as the duty cycle when the TCC is active When 2 is enabled and a high temperature situation exists the processor will perform an Enhanced Intel SpeedStep Technology transition to the LFM When the processor temperature drops below the critical level the processor will make an Enhanced Intel SpeedStep Technology transition to the last requested operating point The processor also supports Enhanced Multi Threaded Thermal Monitoring EMTTM EMTTM is a processor feature that enhances TM2 with a processor throttling algorithm known as Adaptive TM2 Adaptive TM2 transitions to intermediate operating points rather than directly to the LFM once the processor has reached its thermal limit and subsequently searches for the highest possible operating point Please ensure this feature is enabled and supported in the BIOS Also with EMTTM enabled the operating system can request the processor to throttling to any point between Intel Dynamic Acceleration Technology frequency and SuperLFM frequency as long as these features are enabled in the BIOS and supported by the processor The Intel Thermal Monitor automatic mode and Enhanced Multi Threaded Thermal Monitoring must be enabled through BIOS for the processor to be operating within specifications Intel recommends TM1 and TM2 be enabled on the processors TM1 TM2 and EMTTM features are coll
131. s at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 3 Specified at 105 C Tj 4 Specified at the nominal Vcc 5 Measured at the bulk capacitors on the motherboard 6 Vcc Boor tolerance shown in Figure 4 and Figure 5 7 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested 8 This is a power up peak current specification which is applicable when Vccp is high and cogg is low 9 This is a steady state current specification which is applicable when both Vccp and Vcc cone are high 10 The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV 11 The Iccpes max specification of 60 A is for Intel Core 2 Extreme processors only Datasheet 33 intel Electrical Specifications Table 7 Voltage and Current Specifications for the Dual Core Standard Voltage Processors Symbol Parameter Min Typ Max Unit Notes Vcc in Enhanced Intel Dynamic Acceleration Technology Mode 19 s Y 1 2 VccHFM Vcc at Highest Frequency Mode HFM 1 0 1 25 V 1 2 VcciFM Vcc at Lowest Frequency Mode LFM 0 85
132. serted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal However to ensure recognition of this signal following an input output write instruction it must be valid along with the TRDY assertion of the corresponding input output write bus transaction INIT must connect the appropriate pins of both FSB agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST LINT 1 0 Input LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK Input Output LOCK indicates to the system that a transaction must occur atomicall
133. soz sez ayeweig BN T 7 Soz Sec v0 0 9v 00 v G SINAWWOD NU was S alAWITHW MIIA dOL M3IA WOLLO T Co gt be c gt e 2 8 Myd 335 M3IA 3415 3 3900Vd ke EEGEN A Le S T LR RRE E A 9 ees 74 a 3 oOo9o9o95 oC e 4 ti ooo o o o o o oco RR RR ON NOM d 5 DEE De GOSS w 7 E d N 0 0002020202020505050 050505050 000 00 000 w 0 0 0 0 O OO O0 O O O D O O O O O O O 0 O O D 0 0 0 0 0 0 RR RR RR RR n Dee poo 0 0 O 0 020 000 GEET D Li 0 0 0 0 0 00 0000 O0 0 O0 O0 O O OO O A Deen vv e Kiel e EE EE 1 ZE a am 0 0 0 0 OO 0 OO 0 O D O O0 O O OC 0000 uv SEET X pag Zen AY wy E AN 0 0 0 O 0 0 OO O 0 0 0 OO OO OO O ee ee O 0 0 0 0 0 0 000505 AY 9o ooo 0 o oC o o o NY dco coco o 079 0 av Y E ER 0 aa Y o o Le Ty lt 1 gt 7 Le Tp 3 4 18 gt Datasheet 58 m 8 Package Mechanical Specifications and Pin Information n tel 4 2 Processor Pinout and Pin List Figure 16 and Figure 17 show the processor SV and XE pinout as viewed from the top of the package Table 16 provides the pin list arranged numerically by pin number Figure 16 through Figure 18 show the top view of the LV and ULV
134. ssor in SFF Package Listing by Ball Name Datasheet Signal Ball Signal Name Ball Signal Ball Name Number Number Name Number VCC F24 VCC P18 VCC Y32 VCC F26 VCC P20 VCCA B34 VCC F28 VCC P22 VCCA D34 VCC F30 VCC P24 VCCP A13 VCC F32 VCC P26 VCCP A33 VCC G33 VCC P28 VCCP AA7 VCC H16 VCC P30 VCCP AA9 VCC H18 VCC P32 VCCP AA11 VCC H20 VCC R33 VCCP AA13 VCC H22 VCC T16 VCCP AA35 VCC H24 VCC T18 VCCP AA37 VCC H26 VCC T20 VCCP AB10 VCC H28 VCC T22 VCCP AB12 VCC H30 VCC T24 VCCP AB14 VCC H32 VCC T26 VCCP AB36 VCC J33 VCC T28 VCCP AB38 VCC K16 VCC T30 VCCP AC7 VCC K18 VCC T32 VCCP AC9 VCC K20 VCC U33 VCCP AC11 VCC K22 VCC V16 VCCP AC13 VCC K24 VCC V18 VCCP AC35 VCC K26 VCC V20 VCCP AC37 VCC K28 VCC V22 VCCP AD14 VCC K30 VCC V24 VCCP AE7 VCC K32 VCC V26 VCCP AE9 VCC L33 VCC V28 VCCP AE11 VCC M16 VCC V30 VCCP AE13 VCC M18 VCC V32 VCCP AE35 VCC M20 VCC W33 VCCP AE37 VCC M22 VCC Y16 VCCP AF10 VCC M24 VCC Y18 VCCP AF12 VCC M26 VCC Y20 VCCP AF14 VCC M28 VCC Y22 VCCP AF36 VCC M30 VCC Y24 VCCP AF38 VCC M32 VCC Y26 VCCP AG7 VCC N33 VCC Y28 VCCP AG9 VCC P16 VCC Y30 VCCP AG11 87 intel Package Mechanical Specifications and Pin Information Table 18 Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name 88
135. stem motherboard for proper AGTL bus operation 3 2 3 FSB Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous generation processors the processor core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier will be set at its default ratio at manufacturing The processor uses a differential clocking implementation Datasheet 25 intel 3 3 Table 2 26 Voltage Identification and Power Sequencing Electrical Specifications The processor uses seven voltage identification pins VID 6 0 to support automatic selection of power supply voltages The VID pins for the processor are CMOS outputs driven by the processor VID circuitry Table 2 specifies the voltage level corresponding to the state of VID 6 0 A 1 in the table refers to a high voltage level and a 0 refers to a low voltage level Voltage Identification Definition Sheet 1 of 3 VID6 VID5 VID4 VID3 VID2 VID1 VIDO Vcc V 0 0 0 0 0 0 0 1 5000 0 0 0 0 0 0 1 1 4875 0 0 0 0 0 1 0 1 4750 0 0 0 0 0 1 1 1 4625 0 0 0 0 1 0 0 1 4500 0 0 0 0 1 0 1 1 4375 0 0 0 0 1 1 0 1 4250 0 0 0 0 1 1 1 1 4125 0 0 0 1 0 0 0 1 4000 0 0 0 1 0 0 1 1 3875 0 0 0 1 0 1 0 1 3750 0 0 0 1 0 1 1 1 3625 0 0 0 1
136. ster In automatic mode the duty cycle is fixed at 50 on 50 off however in on demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On demand mode may be used at the same time automatic mode is enabled however if the system tries to enable the TCC via on demand mode at the same time automatic mode is enabled and a high temperature condition exists automatic mode will take precedence An external signal PROCHOT processor hot is asserted when the processor detects that its temperature is above the thermal trip point Bus snooping and interrupt latching are also active while the TCC is active Datasheet m Thermal Specifications and Design Considerations n tel 5 1 3 Datasheet Besides the thermal sensor and thermal control circuit the Intel Thermal Monitor also includes one ACPI register one performance counter register three MSR and one I O pin PROCHOT All are available to monitor and control the state of the Intel Thermal Monitor feature The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT PROCHOT will not be asserted when the processor is in the Stop Grant Sleep Deep Sleep and Deeper Sleep low power states hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification If the platform thermal solution is not able
137. strate PNP transistor Since these characteristics are a function of temperature these parameters can be used to calculate silicon temperature values For older silicon process technologies it is possible to simplify the voltage current and temperature relationships by treating the substrate transistor as though it were a simple diffusion diode In this case the assumption is that the beta of the transistor does not impact the calculated temperature values The resultant diode model essentially predicts a quasi linear relationship between the base emitter voltage differential of the PNP transistor and the applied temperature one of the proportionality constants in this relationship is processor specific and is known as the diode ideality factor Realization of this relationship is accomplished with the SMBus thermal sensor that is connected to the transistor The processor however is built on Intel s advanced 45 nm processor technology Due to this new processor technology it is no longer possible to model the substrate transistor as a simple diode To accurately calculate silicon temperature use a full bi polar junction transistor type model In this model the voltage current and temperature characteristics include an additional process dependant parameter which is known as the transistor beta System designers should be aware that the current thermal sensors may not be configured to account for beta and should work with their SMB thermal
138. t Specifications for the Dual Core Extreme Edition Processors 32 7 Voltage and Current Specifications for the Dual Core Standard Voltage Processors 34 8 Voltage and Current Specifications for the Dual Core Low Power Standard Voltage Processors 25 W In Standard Package EE 35 9 Voltage and Current Specifications for the Dual Core Power Optimized Performance 25 W SFE ele EE 37 10 Voltage and Current Specifications for the Dual Core Low Voltage SFF Processor 38 11 Voltage and Current Specifications for the Dual Core Ultra Low Voltage SFF Processor 40 12 Voltage and Current Specifications for the Ultra Low Voltage Single Core 5 5 W SEF Die 41 13 AGTL Signal Group DC Specifications cece cere ee eee eee eee eee eee nennen 48 14 CMOS Signal Group DC Gpecfications cece eee ee eee eee eee teense teens nennen 49 15 Open Drain Signal Group DC Specifications ccc cece eee eee eee eee eee menm 49 Datasheet 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name LISING RD AP RIXA EE DERE FU 61 dE BC elle 72 Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball 8 84 Se le gl Le e t 93 Power Specifications for the Dual Core Extreme Edition Pr
139. ta Out transfers serial test data out of the processor TDO Output TDO provides the serial output needed for JTAG specification support TEST1 TEST2 TEST3 Refer to the appropriate platform design guide for further TEST1 TEST4 Input TEST2 TEST3 TEST4 TEST5 TEST6 and TEST7 termination TESTS requirements and implementation details TEST6 TEST7 THRMDA Other Thermal Diode Anode THRMDC Other Thermal Diode Cathode The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false Output trips The processor will stop all execution when the junction temperature exceeds approximately 125 C This is signalled to the system by the THERMTRIP Thermal Trip pin TMS Input TMS Test Mode Select is a JTAG specification support signal used by debug tools TRDY Target Ready is asserted by the target to indicate that it is TRDY Input ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of both FSB agents TRST Test Reset resets the Test Access Port TAP logic TRST TRST Input must be driven low during power on Reset VCC Input Processor core power supply VSS Input Processor core ground node VCCA Input VCCA provides isolated power for the internal processor core PLLS VCCP Input Processor I O Power Supply 99 intel
140. tel I O Controller Hub 9 ICH9 I O Controller Hub 9M ICH9M 316972 Datasheet Intel I O Controller Hub 9 ICH9 I O Controller Hub 9M ICH9M AM 316973 Specification Update Intel 64 and IA 32 Architectures Software Developer s Manuals Volume 1 Basic Architecture 253665 Volume 2A Instruction Set Reference A M 253666 10 Introduction Document Document Number Volume 2B Instruction Set Reference N Z 253667 Volume 3A System Programming Guide 253668 Volume 3B System Programming Guide 253669 NOTE Contact your Intel representative for the latest revision of this document 8 Datasheet m e Low Power Features n tel j 2 2 1 Datasheet Low Power Features Clock Control and Low Power States The processor supports low power states both at the individual core level and the package level for optimal power management A core may independently enter the C1 AutoHALT C1 MWAIT C2 C3 C4 Intel Enhanced Deeper Sleep and Intel Deep Power Down Technology low power states When both cores coincide in a common core low power state the central power management logic ensures the entire processor enters the respective package low power state by initiating a P_LVLx P_LVL2 P_LVL3 P_LVL4 P_LVL5 P_LVL6 I O read to the GMCH The processor implements two software interfaces for requesting low power states MWAIT instruction extensions with sub state hints and P_LVLx reads to the ACPI P BLK
141. th the implementation of a source synchronous data bus two sets of timing parameters are specified One set is for common clock signals which are dependent upon the rising edge of BCLKO ADS HIT HITMZ etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as the rising edge of BCLKO Asychronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 4 identifies which signals are common clock source synchronous and asynchronous FSB Pin Groups Signal Group Type Signals AGTL Common Synchronous to 5 Clock Input BCLK 1 0 BPRI DEFER PREQ RESET RS 2 0 TRDY AGTL Common Synchronous to ADS BNR BPM 3 0 43 BRO DBSY DRDY Clock I O BCLK 1 0 HIT HITM LOCK PRDY 2 DPWR AGTL Source Synchronous I O Synchronous to assoc strobe Signals Associated Strobe REQ 4 0 A 16 3 ADSTB 0 A 35 17 ADSTB 1 D 15 0 DINVO DSTBPO DSTBNO D 31 16 DINV1 D 47 32 DINV2 DSTBP1 DSTBN1 DSTBP2 DSTBN2 D 63 48 DINV3 DSTBP3 DSTBN3 AGTL Strobes Synchronous to ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 BCLK 1 0 eias nsus INN A20M DPRSTP DPSLP IGNNE INIT LINTO H y INTR LINT1 NMI PWRGOOD SMI SLP STPCLK Open Drain Asynchronous FERR IERR THERMTRIP Output
142. ting in additional power savings The low I O termination voltage is on a dedicated voltage plane independent of the core voltage enabling low I O switching power at all times Dynamic FSB Frequency Switching Dynamic FSB frequency switching effectively reduces the internal bus clock frequency in half to further decrease the minimum processor operating frequency from the Enhanced Intel SpeedStep Technology performance states and achieve the Super Low Frequency Mode Super LFM This feature is supported at FSB frequencies of 1066 MHz 800 MHz and 667 MHz and does not entail a change in the external bus signal BCLK frequency Instead both the processor and GMCH internally lower their BCLK reference frequency to 50 of the externally visible frequency Both the processor and GMCH maintain a virtual BCLK signal VBCLK that is aligned to the external BCLK but at half the frequency After a downward shift it would appear externally as if the bus is running with a 133 MHz base clock in all aspects except that the actual external BCLK remains at 266 MHz See Figure 3 for details The transition into Super LFM a down shift is done following a handshake between the processor and GMCH A similar handshake is used to indicate an up shift a change back to normal operating mode Please ensure this feature is enabled and supported in the BIOS 21 ntel Figure 3 2 4 2 22 Low Power Features Dynamic FSB Frequency Switching Protocol
143. urce Synch Bute A21 BCLK 1 Bus Clock Input AB3 TDO Open Drain Output A22 BCLK 0 Bus Clock Input ABA VSS Power Other A23 VSS Power Other AB5 TMS CMOS Input A24 THRMDA Power Other AB6 TRST CMOS Input A25 VSS Power Other AB7 vcc Power Other A26 TEST6 Test 8 VSS Power Other AA COMP 2 Power Other See ABS VCC Power Other AB10 VCC Power Other AA2 VSS Power Other AB11 VSS Power Other AA3 A 35 Source Synch uU 2 VCC Power Other Input AB13 VSS Power Other AA4 A 33 Source Synch Output ABI4 VEG Power Other AAS VSS Power Other AB15 VCC Power Other AA6 TDI CMOS Input AB16 VSS Power Other AA7 VCC Power Other AB17 VCC Power Other AA8 VSS Power other AB18 VCC Power Other AA9 VCC Power Other AB19 VSS Power Other AA10 VCC Power Other AB20 VCC Power Other AAT VSS TOWEN OLNE AB21 D 52 Source Synch PH AA12 VCC Power Other Output Datasheet 73 ntel Package Mechanical Specifications and Pin Information Table 17 Pin Listing Table 17 Pin Listing Pin Pin Name Signal Buffer Directi Pin 4 Pin Name Signal Buffer Directi Type on Type on AB22 D 51 Source Synch A AD3 BPM 1 Common Clock Output Input DER VSS Power Other ADS BEER Common ee AB24 3314 Source Synch GE AD5 VSS Power Oth
144. viation from ideal transistor model behavior as exemplified by the equation for the collector current lc ls e geen 1 where Is saturation current electronic charge Ver voltage across the transistor base emitter junction same nodes as VD k Boltzmann Constant and T absolute temperature Kelvin Intel amp Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC Thermal Control Circuit when the processor silicon reaches its maximum operating temperature The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active With a properly designed and characterized thermal solution the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active cont
145. vss Y AA COMP 2 vss A 35 A 33 vss TDI vcc vss vcc vcc vss vcc vcc vss A 34 TDO vss ts TRST vss vcc vcc vss vcc vss AC PREQ amp proy vss BPMIS vss vcc vss vcc vcc vss vcc vcc 2 AD 21 vss BPMIO VID 0 vec vss vcc vcc vss vec vss AE vss vib 6 vip 4 vss VID 2 psi vss vcc vcc vss vcc vcc L AF TESTS vss VID 5 VID 3 VID 1 vss s ee vss vcc vcc vss vcc vss 1 2 3 4 5 6 7 8 9 10 11 12 13 NOTES 1 Keying option for Micro FCPGA A1 and B1 are de populated 2 Keying option for Micro FCBGA A1 is de populated and B1 is VSS Datasheet 59 intel Package Mechanical Specifications and Pin Information Figure 17 Processor Pinout Top Package View Right Side 14 15 16 17 18 19 20 21 22 23 24 25 26 a vss vcc vss vec vec vss vcc VSS THRMDA VSS Teste A B vec vss vec vec vss vec VSS BSEL 0 BSEL 1 VSS THRMDC VCCA B c vss vec vss vec vec vss pene 5 2 VSS TESTI TEST3 VSS vccA c D vec vcc vss vec vec vss pe PROCHOT Rsvp vss DPWR TEST2 vss D vcc vss vcc vec vss vcc VSS D 0 4 D 7 amp VSS D 6 D 2 E vec
146. west programmed TM2 performance state It should be noted that Force TM1 on TM2 enabled via BIOS does not have any effect on external PROCHOT If PROCHOT is driven by an external agent when TM1 TM2 and Force TM1 on TM2 are all enabled then the processor will still apply only TM2 PROCHOT may be used for thermal protection of voltage regulators VR System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached By asserting PROCHOT pulled low and activating the TCC the VR will cool down as a result of reduced processor power consumption Bi directional PROCHOT can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on bi directional PROCHOT only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP With a properly designed and characterized thermal solution it is anticipated that bi directional PROCHOT would only be asserted for very short periods Datasheet m 8 Thermal Specifications and Design Considerations n tel of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient envir
147. will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Pentium Centrino Intel Core Duo Intel SpeedStep MMX and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2008 2009 Intel Corporation All rights reserved 2 Datasheet Contents 1 EME FOU CULO I E 7 PEE Zeus ale Let ATL 8 1 2 ie EE 9 2 Low Power Features ee NEEN cee KEREN KAREN EEERKN EN KR 11 2 1 Clock Control and Low Power 9 8 65 nee 11 2 1 1 Core Low Power State Descriptions ena 13 2 1 1 1 COPECO State EE 13 2 1 1 2 Core C1 AutoHALT Powerdown Gtate cesses 13 2 1 1 3 Core C1 MWAIT Powerdown Gtate nennen 14 1 4 Core c E shee 14 2 1 1 5 Core C3 Sbabe eege dng geed REENEN de ENEE EE ER esa rA DE Ure virga Rd ets 14 21 1 6 Core C4 EE 14 2 1 1 7 Core Deep Power Down Technology Code Name C6 State 15 2 1 2 Package Low power State Descriptions nme 15 Ke Den EI 15 2 12 2 Ee ee Lu 15 2
148. y This signal must connect the appropriate pins of both FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the FSB it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock PRDY Output Probe Ready signal used by debug tools to determine processor debug readiness PREQ Input Probe Request signal used by debug tools to request debug operation of the processor PROCHOT Input Output As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled The TCC will remain active until the system deasserts PROCHOT By default PROCHOT is configured as an output The processor must be enabled via the BIOS for PROCHOT to be configured as bidirectional This signal may require voltage translation on the motherboard PSI Output Processor Power Status Indicator signal This signal is asserted when the processor is both in the
149. y Mode HFM and Lowest Frequency Mode LFM refer to the highest and lowest core operating frequencies supported on the processor Active mode load line specifications apply in all states except in the Deep Sleep and Deeper Sleep states Vcc Boor is the default voltage driven by the voltage regulator at power up in order to set the VID values Unless specified otherwise all specifications for the processor are at T 105 C Read all notes associated with each parameter Table 6 Voltage and Current Specifications for the Dual Core Extreme Edition Processors Sheet 1 of 2 Symbol Parameter Min Typ Max Unit Notes Vcc in Enhanced Intel Dynamic Acceleration VCCDAM Technology Mode d Tom d 1 2 VccHFM Vcc at Highest Frequency Mode HFM 1 0 ES 1 275 V VccLFM Vcc at Lowest Frequency Mode LEM 0 85 1 1 V 1 2 Vcc at Super Low Frequency Mode VCCSLFM S per LFM 0 8 1 0 V 1 2 Vcc Boor Default Vcc Voltage for Initial Power Up 1 20 V 2 6 Vecp AGTL Termination Voltage 1 00 1 05 1 10 V VCCA PLL Supply Voltage 1 425 1 5 1 575 V VCcCDPRSLP Vcc at Deeper Sleep 0 65 0 85 V 1 2 Vpca4 Vcc at Intel Enhanced Deeper Sleep State 0 6 0 85 V 1 2 Vcc at Deep Power Down Technology State VccpePWDN 66 P gy 0 35 0 7 V Icc for Processors Recommended Design Iccpes Target 3 60 A 12 Icc for Processors Processor Number Core Frequency Voltage X9100 3 06 GHz amp VCcCHFM 59 1 6 GHz amp VcciFM 34 A 3 4 10 0 8 GHz
150. ystem the STPCLK SLP DPSLP and DPRSTP pins must be deasserted prior to RESET deassertion as per AC Specification T45 When re entering the Stop Grant state from the Sleep state STPCLK should be deasserted after the deassertion of SLP as per AC Specification T75 While in Stop Grant state the processor will service snoops and latch interrupts delivered on the FSB The processor will latch SMI INIT and LINT 1 0 interrupts and will service only one of each upon return to the Normal state The PBE signal may be driven when the processor is in Stop Grant state PBE will be asserted if there is any pending interrupt or Monitor event latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still cause assertion of PBE Assertion of PBE indicates to system logic that the entire processor should return to the Normal state A transition to the Stop Grant Snoop state occurs when the processor detects a snoop on the FSB see Section 2 1 2 3 A transition to the Sleep state see Section 2 1 2 4 occurs with the assertion of the SLP signal 15 Bm e n tel Low Power Features 2 1 2 3 2 1 2 4 2 1 2 5 16 Stop Grant Snoop State The processor responds to snoop or interrupt transactions on the FSB while in Stop Grant state by entering the Stop Grant Snoop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or

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