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Intel Xeon LF80550KF0604M processor

1. Pin No Pin Name Sue yee Direction Pin No Pin Name e ae Direction P7 Vss Power Other T24 Vcc Power Other P8 Vec Power Other T25 Vss Power Other P9 Vss Power Other T26 Vcc Power Other P23 Vss Power Other T27 Vss Power Other P24 Vec Power Other T28 Vcc Power Other P25 Vss Power Other T29 Vss Power Other P26 Vcc Power Other T30 Vcc Power Other P27 Vss Power Other T31 Vss Power Other P28 Vec Power Other Ui VCACHE Power Other P29 Vss Power Other U2 Vss Power Other P30 Vec Power Other U3 VCACHE Power Other P31 Vss Power Other U4 Vss Power Other R1 VCACHE Power Other U5 VCACHE Power Other R2 Vss Power Other U6 Vss Power Other R3 VCACHE Power Other U7 VCACHE Power Other R4 Vss Power Other U8 Vss Power Other R5 VCACHE Power Other U9 VCACHE Power Other R6 Vss Power Other U23 Vcc Power Other R7 VCACHE Power Other U24 Vss Power Other R8 Vss Power Other U25 Vec Power Other R9 VCACHE Power Other U26 Vss Power Other R23 Vec Power Other U27 Vec Power Other R24 Vss Power Other U28 Vss Power Other R25 Vec Power Other U29 Vec Power Other R26 Vss Power Other U30 Vss Power Other R27 Vec Power Other U31 Vec Power Other R28 Vss Power Other V1 Vss Power Other R29 Vec Power Other V2 Vec Power Other R30 Vss Power Other v3 Vss Power Other R31 Vec Power Other V4 Vec Power Other T1 Vss Power Other V5 Vss Power Other T2 Vec Power Other
2. i ui a o ES lt L m N E ris E g E 3 zi et o Sz E Oe e m s kra E OI g ET g Se ei EJ S miim BE E E lel ie Se EL Sg i B E SE iu T 40060059200966000050096 fs t i 333333 i 333352 9009 9 99099994080 el S Bile je je E E i DAC 2 e g 3 m e J 2 2 2 E HH Jalala Slslsi Ges BRR BBR 8 z l g 3 Hu Hid 8 HE 22 3 e ale lle lll lll J l o t e Jl SEE EN E Jt Al a E DE SS 2 zs gl S RN e m N Pa e MAUL ZS nl E a TS 2u e B a x ER ES TT lo H E Les 3 amp 3 S E H ee E RES os gs 4 N ME T n E o S wi d 5 EE j zz i E 3 j os LL ES a a 5 E M j ke S j 1 n 1 n o m A a E co co iy m ES o ES lt Dual Core Intel Xeon Processor 7100 Series Datasheet Mechanical Specifications intel Processor Package Drawing Sheet 2 of 2 Figure 3 3 DEER mamm nos ma y m 68587 DEEN U6 328 NAIA WOLLOS Ip 1N3NOdHO2 318VM0TW XY E KEE 099090990900090000 0900090090900000000 000000000000000 9 9 9 9 9 9 9 9 4 99 1 GOOHEOQOHOHOOQOOO 9909000000000000000000000009006 99900000000000090009000000
3. Pin Name Pin No Re Uie Direction A3 A22 Source Sync Input Output A4 A20 Source Sync Input Output A5 B18 Source Sync Input Output A63 C18 Source Sync Input Output A73 A19 Source Sync Input Output A8 C17 Source Sync Input Output A9 D17 Source Sync Input Output A103 A13 Source Sync Input Output A114 B16 Source Sync Input Output A125 B14 Source Sync Input Output A133 B13 Source Sync Input Output A143 A12 Source Sync Input Output A15 C15 Source Sync Input Output A163 C14 Source Sync Input Output A17 D16 Source Sync Input Output A18 D15 Source Sync Input Output A193 F15 Source Sync Input Output A203 A10 Source Sync Input Output A213 B10 Source Sync Input Output A223 B11 Source Sync Input Output A234 C12 Source Sync Input Output A243 E14 Source Sync Input Output A254 D13 Source Sync Input Output A263 A9 Source Sync Input Output A273 B8 Source Sync Input Output A285 E13 Source Sync Input Output A293 D12 Source Sync Input Output Dual Core Intel Xeon Processor 7100 Series Datasheet Pin Name Pin No Type Direction A303 Cii Source Sync Input Output A31 B7 Source Sync Input Output A32 A6 Source Sync Input Output A33 A7 Source Sync Input Output A34 C9 Source Sync Input Output A354 C8 Source Sync Source Sync A363 F16 Source Sync Source Sync A375 F22 Source Sync
4. VID5 VID4 VID3 VID2 VID1 VIDO VID V VID5 VID4 VID3 VID2 VID1 VIDO VID V 0 0 1 0 1 0 0 8375 0 1 1 0 1 0 1 2125 1 0 1 0 0 1 0 8500 1 1 1 0 0 1 1 2250 0 0 1 0 0 1 0 8625 0 1 1 0 0 1 1 2375 1 0 1 0 0 0 0 8750 1 1 1 0 0 0 1 2500 0 0 1 0 0 0 0 8875 0 i 1 0 0 0 1 2625 1 0 0 1 1 1 0 9000 1 1 0 1 1 1 1 2750 0 0 0 L 1 1 0 9125 0 1 0 1 1 1 1 2875 1 0 0 1 1 0 0 9250 1 1 0 1 1 0 1 3000 0 0 0 1 1 0 0 9375 0 1 0 1 1 0 1 3125 1 0 0 1 0 1 0 9500 1 1 0 1 0 1 1 3250 0 0 0 1 0 1 0 9625 0 3 0 1 0 1 1 3375 1 0 0 1 0 0 0 9750 1 1 0 1 0 0 1 3500 0 0 0 1 0 0 0 9875 0 i 0 1 0 0 1 3625 1 0 0 0 1 1 1 0000 1 1 0 0 1 1 1 3750 0 0 0 0 di 1 1 0125 0 1 0 0 1 1 1 3875 1 0 0 0 1 0 1 0250 1 i 0 0 1 0 1 4000 0 0 0 0 1 0 1 0375 0 1 0 0 1 0 1 4125 1 0 0 0 0 1 1 0500 1 1 0 0 0 1 1 4250 0 0 0 0 0 1 1 0625 0 d 0 0 0 1 1 4375 1 0 0 0 0 0 1 0750 1 1 0 0 0 0 1 4500 0 0 0 0 0 0 1 0875 0 Ji 0 0 0 0 1 4625 1 1 1 1 1 1 VRM off 1 0 1 1 1 1 1 4750 0 1 1 1 1 1 VRM off 0 0 1 1 1 1 1 4875 1 a 1 1 1 0 1 1000 1 0 1 1 1 0 1 5000 0 1 1 1 1 0 1 1125 0 0 1 1 1 0 1 5125 1 1 1 1 0 1 1 1250 1 0 1 1 0 1 1 5250 0 1 1 1 0 1 1 1375 0 0 1 1 0 1 1 5375 1 1 1 1 0 0 1 1500 1 0 1 1 0 0 1 5500 0 d 1 1 0 0 1 1625 0 0 1 1 0 0 1 5625 1 1 1 0 1 1 1 1750 1 0 1 0 1 1 1 5750 0 1 1 0 1 1 1 1875 0 0 1 0 1 1 1 5875 1 I 1 0 1 0 1 2000 1 0 1 0 1 0 1 6000 2 3 Cache Voltage Identification CVID The
5. 64 Dual Core Intel Xeon Processor 7100 Series Datasheet Signal Definitions 5 Signal Definitions 5 1 Signal Definitions Table 5 1 Signal Definitions Sheet 1 of 8 Name Type Description A 39 3 A20M I O A 39 3 4 Address define a 240 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of all agents on the Dual Core Intel Xeon processor 7100 series front side bus A 39 3 are protected by parity signals AP 1 0 A 39 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processors sample a subset of the A 39 3 pins to determine their power on configuration See Section 7 1 If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A202 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 Mbyte boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid 6 clks before the I O write s response ADS I O ADS
6. Register Command R W Lock Reset State RESERVED 00h N A N A RESERVED Ch 1 Temp Value 01h R N 0000 0000 Status Register 1 02h Undefined Configuration Register 1 03h R 0000 0000 Conversion Rate Register 04h 0000 0111 RESERVED 05h 06h N A N A RESERVED Ch 1 Temp High Limiti 07h 0101 0101 Ch 1 Temp Low Limit 4 08h R 0000 0000 Configuration Register 09h Ww 0000 0000 Conversion Rate Register OAh Ww 0000 0111 RESERVED OBh OCh N A N A RESERVED Ch 1 Temp High Limitt4 ODh Ww Y 0101 0101 Ch 1 Temp Low Limit 4 OEh w Y 0000 0000 One shot OFh VW N A N A RESERVED 10h N A N A RESERVED Ch 1 Temp Offset 11h R W Y 0000 0000 RESERVED2 12h 22h N A N A RESERVED Status Register 2 23h R N 0000 0000 RESERVED 24h 29h N A N A RESERVED Ch 2 Temp Value 30h R 0000 0000 Ch 2 Temp High Limit 31h R W 0101 0101 Ch 2 Temp Low Limit 32h R W 0000 0000 RESERVED 33h R N A 0000 0000 Ch 2 Temp Offset 34h R W Y 0000 0000 RESERVED 35h FDh N A N A RESERVED Manufacturer ID FEh R N A 0100 0001 Die Revision Code FFh R N A 1001xxxx Notes di 2 Bit 3 of Configuration register 1 must be set to 0 default value is 0 Writing to RESERVED bits may cause unexpected results RESERVED bits that must be correctly programmed are identified in the register definitions in the following section Reading from RESERVED bits will return unknown values 3 The 4 least significant bits of the thermal sensor d
7. Dual Core Intel Xeon Processor 7100 Series Datasheet Electrical Specifications Table 2 16 Front Side Bus Differential BCLK Specifications Sheet 2 of 2 Symbol Parameter Min Typ Max Unit Notes VUS Undershoot 0 300 N A N A V 4 VRBM Ringback Margin 0 200 N A N A V 5 VTM Threshold Margin Vcnoss 0 100 Vcrosst 0 100 V 6 Notes 1 Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLKO is equal to the falling edge of BCLK1 que qe and the maximum Falling Edge Ringback Si receiver switches It includes input threshold hysteresis oN Vhavg iS the statistical average of the Vu measured by the oscilloscope Overshoot is defined as the absolute value of the maximum voltage Undershoot is defined as the absolute value of the minimum voltage Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback Table 2 17 BSEL 1 0 VID 5 0 and CVID 3 0 DC Specifications The crossing point must meet the absolute and relative crossing point specifications simultaneously VHavg Can be measured directly using Vtop on Agilent scopes and High on Tektronix scopes Threshold Region is defined as a region entered around the crossing point voltage in which the differential Symbol Parameter Typ Max Unit Notes Ron Buffer On Resistance 80 Q 1 Rpull_up Pull up resistor
8. Bit Description 15 0 RESERVED 0000h FFFFh Reserved HCKS Header Checksum This location provides the checksum of the Header Section Writes to this register have no effect Offset ODh Bit Description 7 0 Header Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Processor Data This section contains two pieces of data e The S spec QDF of the part in ASCII format e 1 2 bit field to declare if the part is a pre production sample or a production unit SQNUM S Spec QDF Number This location provides the S SPec or QDF number of the processor The S spec QDF field is six ASCII characters wide and is programmed with the same S spec QDF value as marked on the processor If the value is less than six characters in length leading spaces 20h are programmed in this field Writes to this register have no effect Example A processor with a QDF mark of QEU5 contains the following in field OE 13h 20 20 51 45 55 35h This data consists of two blanks at OEh and OFh followed by the ASCII codes for QEUBS in locations 10 13h Dual Core Intel Xeon Processor 7100 Series Datasheet Features Offset OEh 13h Bit Description 47 40 Character 6 S SPEC or QDF character or 20h OOh OFFh ASCII character 39 32 Character 5 S SPEC or QDF character or 20h OOh OFFh ASCII character 31 24 Charac
9. Pin Listing Table 4 2 Pin Listing by Pin Number Sheet 5 of 16 intel Table 4 2 Pin Listing by Pin Number Sheet 6 of 16 Pin No Pin Name Sue yee Direction Pin No Pin Name Bone d Direction F4 Vcc Power Other G26 Vcc Power Other F5 BPM3 Common Clk Input Output G27 Vss Power Other F6 BPMO Common Clk Input Output G28 Vcc Power Other F7 Vss Power Other G29 Vss Power Other F8 BPM1 Common Clk Input Output G30 Vec Power Other F9 GTLREF3 Power Other Input G31 Vss Power Other F10 Vr Power Other H1 VCACHE Power Other F11 BINIT Common CIk Input Output H2 Vss Power Other F12 BR1 Common CIk Input H3 VCACHE Power Other F13 Vss Power Other H4 Vss Power Other F14 ADSTB1 Source Sync Input Output H5 VCACHE Power Other F15 A19 Source Sync Input Output H6 Vss Power Other F16 A36 Source Sync Input Output H7 VCACHE Power Other F17 ADSTBO Source Sync Input Output H8 Vss Power Other F18 DBSY Common CIk Input Output H9 VCACHE Power Other F19 Vss Power Other H23 Vec Power Other F20 BNR Common Clk Input Output H24 Vss Power Other F21 RS2 Common CIk Input H25 Vcc Power Other F22 A37 Source Sync Input Output H26 Vss Power Other F23 GTLREF2 Power Other Input H27 Vcc Power Other F24 TRST TAP Input H28 Vss Power Other F25 Vss Power Other H29 Vec Power Other F26 THERMTRIP Async GTL O
10. Bit Description 7 0 Tcase Maximum 00h FFh Maximum Case Temperature of the processor PCDCKS Processor Core Data Checksum This location provides the checksum of the Processor Core Data Section Writes to this register have no effect Offset 24h Bit Description 7 0 Processor Core Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Cache Data This section contains cache related data RES3 Reserved 3 These locations are reserved Writes to this register have no effect Offset 25h 26h Bit Description 15 0 RESERVED 3 0000h FFFFh Reserved Dual Core Intel Xeon Processor 7100 Series Datasheet 101 intel a 7 4 3 4 2 7 4 3 4 3 7 4 3 4 4 102 L2SIZE L2 Cache Size This location contains the size of the level two cache in kilobytes Writes to this register have no effect Example The Dual Core Intel Xeon processor 7100 series has a 2 MB 2048 KB L2 cache total 1 MB L2 cache per core Thus offset 27 28h will contain 0800h Offset 27h 28h Bit Description 15 0 L2 Cache Size 0000h 07FFh Reserved 0800h 2 MB 0801h FFFFh Reserved L3SIZE L3 Cache Size This location contains the size of the level three cache in kilobytes Writes to this register have no effect Example The Dual Core Intel Xeon processor 7100 series has either a 4 MB 4096 KB
11. E 25 gi PER S S 2 m tn ES Bes Die BIE FEE a gs a n T amp p E E E x o n 235 E uA ZS e g 32 E PELLIS E 2 2 ea 3 j EN 3 lt 8 SE S z E S 8 d z e o hev 5 a Law SX Ki m zx me SN oO a3 ke Dual Core Intel Xeon Processor 7100 Series Datasheet 123 Boxed Processor Specifications 3 D Figure 8 7 Recommended Processor Layout and Pitch MIN 82 6MM 3 25 e e e e o e e e AIRFLOW 1 I I 124 Dual Core Intel Xeon Processor 7100 Series Datasheet m Boxed Processor Specifications n te 8 2 2 8 2 3 8 3 8 3 1 Boxed Processor Heatsink Weight The boxed processor heatsink weight is approximately 530 grams See Section 3 of this document for details on the processor weight and the Dual Core Intel Xeon Processor 7100 Series Thermal Mechanical Design Guidelines for the enabled heatsink requirements Boxed Processor Retention Mechanism and Heatsink Supports Baseboards and chassis s designed for use by system integrators should include holes that are in proper alignment with each other to support the boxed processor See Figure 8 7 for example of processor pitch and layout Figure 8 1 illustrates the retention solution This is designed to extend air cooling capability through the use of larger heatsinks with minimal airflow blockage and minimal bypass These retention mechanisms can allow the u
12. 8 MB 8192 KB or 16 MB 16384 KB L3 cache Thus offset 29 2Ah will contain 1000h for 4 MB 2000h for 8 MB or 4000h for 16 MB Offset 29h 2Ah Bit Description 15 0 L3 Cache Size 0000h OFFFh Reserved 1000h 4MB 1001h 1FFFh Reserved 2000h 8MB 2001h 3FFFh Reserved 4000h 16MB 4001h FFFFh Reserved MAXCVID Maximum Cache VID This location contains the maximum Cache VID Voltage Identification voltage that may be requested via the CVID pins This field rounded to the next thousandth is in mV and is reflected in hex Writes to this register have no effect Example From Table 2 10 the maximum CVID is 1 3500 V maximum voltage Offset 2B 2Ch would contain 0546h 1350 decimal Offset 2Bh 2Ch Bit Description 15 0 Maximum Cache VID 0000h 0545h Reserved 0546h 1 35 V 0548h FFFFh Reserved Dual Core Intel Xeon Processor 7100 Series Datasheet Features 7 4 3 4 5 Note 7 4 3 4 6 7 4 3 4 7 7 4 3 5 7 4 3 5 1 intel This location contains the minimum Cache voltage This field rounded to the next thousandth is in mV and is reflected in hex The minimum VcAcgg reflected in this field is the minimum allowable voltage assuming the FMB maximum current draw for two processors Writes to this register have no effect MINCV Minimum Cache Voltage The minimum core voltage value in offset 2D 2Eh is a single value that assumes the FMB maximum curre
13. The processor continues to execute instructions during the voltage transition Operation at the lower voltage reduces the power consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operating frequency and voltage transition back to the normal system operating point Transition of the VID code will occur first in order to ensure proper operation once the processor reaches its normal operating frequency Refer to Figure 6 4 for an illustration of this ordering Dual Core Intel Xeon Processor 7100 Series Datasheet n Thermal Specifications n tel Figure 6 4 Thermal Monitor 2 Frequency and Voltage Ordering Note 6 2 3 Tun Temperature Frequency Vcc ch Time a T hysteresis gt The PROCHOT signal is asserted when a high temperature situation is detected regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled If a processor has its Thermal Control Circuit activated via a Thermal Monitor 2 event and an Enhanced Intel SpeedStep Technology transition to a higher target frequency through the applicable MSR write is attempted this frequency transition will be delayed until the TCC is deactiv
14. y k 9 E 8 3 39 2 13385 ONI mvaa 31v3 10N OU Boxed Processor Specifications Top Side Board Keep Out Zones Part 2 e6c61V s SE G3KOTTY S 1N3NOdHMO9 QNYORN3HION ON LNOdI3N YIONI4 GUYOG 9N114S X3 o NOILDIYLS3Y 1HDI3H IN3NOdNOD CHNOGUJHION XYM HHP lee O Q3NOTTY 1N3H3OV1d LN3NOdMOO GUVOBYSHLON ON C2 v 310H NYHL SNI1NDON u0553208d NO 112141838 1H913H LN3NOdMOO XVM NM 92 8 EE V3UV AT8N355V510 YNISLYIH E 100 7000 2004 20E Lued 20 0 NOILOIYLS3Y 1H91IH LN3NOJNOD XYN WH 92 8 EE V3uv XNISLV3H 149 01D XP 0 0 NOI12INIS3U 1H91IH 1N3NOdNOO XYN HNIS E OSI M EE HUT N3931 96 09 one 21 GEN WIRT Ob EH H EICH Les O WI DEE p 3839998989899989988939989o 3339399999923990999999299 3899999999999999999999999 32N383438 04 NMOHS QUVOB 163l 1810711 EE NAH EE Dobe ji 383009000000 0000000980000 O GEESS 338686 L a EEEH 333233 d 239388 988838 EEERH 389898 333329 339999 100971 393333 SES vgl 333333 339333 ES 339889 i 333339 339839
15. 5 RESERVED RESERVED Reserved for future use 4 R2HIGH 0 If set indicates the processor core 2 thermal diode high temperature alarm has activated 3 R2LOW 0 If set indicates the processor core 2 thermal diode low temperature alarm has activated 2 R2OPEN 0 If set indicates an open fault in the connection to the processor core 2 diode 1 RESERVED RESERVED Reserved for future use 0 LSB ALERT 0 If set indicates the ALERT pin has been asserted low This bit gets reset when the ALERT output gets reset Configuration Register The Configuration Register controls several functions of the temperature sensor such as ALERT masking stand by mode and others Table 7 17 and Table 7 18 shows the bit definitions of the Configuration Registers Table 7 17 SMBus Thermal Sensor Configuration Register Sheet 1 of 2 114 Bit Name Reset State Function 7 MSB MASK 0 Mask SM_ALERT bit Clear the bit to allow interrupts via SM ALERTE and allow the thermal sensor to respond to the ARA command when an alarm is active Set the bit to disable interrupt mode The bit is not used to clear the state of the SM ALERT output An ARA command may not be recognized if the mask is enabled RUN STOP Stand by mode control bit If set the device immediately stops converting and enters stand by mode It will perform new temperature measurements when a one shot is performed If cleared the device automatically update
16. Address Strobe is asserted to indicate the validity of the transaction address on the A 39 3 and transaction request type on REQ 4 0 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must connect the appropriate pins on all Dual Core Intel Xeon processor 7100 series processor front side bus agents ADSTB 1 0 I O Address strobes are used to latch A 39 3 and REQ 4 0 on their rising and falling edge AP 1 0 I O AP 1 0 Address Parity are driven by the requestor one common clock after ADS A 39 3 REQ 4 0 are driven A correct parity signal is electrically high if an even number of covered signals are electrically low and electrically low if an odd number of covered signals are electrically low This allows parity to be electrically high when all the covered signals are electrically high AP 1 0 should connect the appropriate pins of all Dual Core Intel Xeon processor 7100 series front side bus agents The following table defines the coverage for these signals Request Signals Subphase 1 Subphase 2 A 39 24 APO AP1 A 23 3 AP1 APO REQ 4 0 4 AP1 APO BCLK 1 0 The differential bus clock pair BCLK 1 0 determines the bus frequency All processor front side bus agents must receive these signals to drive
17. D4 Async GTL Input VCACHE R9 Power Other TCK E24 TAP Input VCACHE U1 Power Other TDI C24 TAP Input VCACHE U3 Power Other TDO E25 TAP Output VCACHE U5 Power Other TEST BUS A16 Power Other Input VCACHE U7 Power Other TESTHIO W6 Power Other Input VCACHE U9 Power Other TESTHI1 W7 Power Other Input Vcc A8 Power Other TESTHI2 w8 Power Other Input Vcc A14 Power Other TESTHI3 Y6 Power Other Input Vcc A18 Power Other TESTHI4 AA7 Power Other Input Vcc A24 Power Other TESTHI5 AD5 Power Other Input Vec B20 Power Other TESTHI6 AER Power Other Input Vcc C4 Power Other THERMTRIP F26 Async GTL Output Vec C22 Power Other TMS A25 TAP Input Vec C30 Power Other TRDY E19 Common Clk Input Vec D8 Power Other TRST F24 TAP Input Vcc D14 Power Other VCACHE H1 Power Other Vcc D18 Power Other VCACHE H3 Power Other Vec D24 Power Other VCACHE H5 Power Other Vec D31 Power Other VCACHE H7 Power Other Vec E6 Power Other VCACHE H9 Power Other Vcc E20 Power Other VCACHE K1 Power Other Vcc E26 Power Other VCACHE K3 Power Other Vcc E28 Power Other VCACHE K5 Power Other Vec E30 Power Other VCACHE K7 Power Other Vcc F1 Power Other VCACHE K9 Power Other Vec F4 Power Other VCACHE M1 Power Other Vec F29 Power Other VCACHE M3 Power Other Vcc F31 Power Other VCACHE M5 Power Other Vcc G2 Power Other VCACHE M7 Power Other Vec G4 Power Other VCACHE M9 Power Other Vcc G6 Power Other VCACHE N1 Power Other Vcc G8 Power Other 52 Dual Core Intel Xeo
18. HN 9278 S287 Y3NY NISLV3H O NOILOIYLSAY j 1H913H ISS NOLL2INIS3N 1H9 3H 1N3NOdHOO gn MMI TE OSI M I 77 T 0N3931 g s 8 NOI1218193U N 1H913H SZE M A CH INIILNO JNISIV3H E 001 H C L 9L5 BM CH i E Il 00571 KS H 19 WR K 3108 AW HLIM INIT NI H ET e 3NI1100 A1083 5v 10 CH 00 E 2860 CIL 2 H 2 H S310H fH oO ONILNNOW YOSS4IOUd 2 IO an L 77 LI a 4 8 2010 4 H 9 91 01 XY J sv cost 1 1 Nid 130208 r ZS ken _l2 2 a o 00g Cl T te JNI1LNO XNISLV3H 688 4 1N3AQ200 31VuVd3S o PETS NO NMOHS 38 111M 1004339 NOI1V1093U JOVLIOA Q31V3931NI o 30N343434 404 NMOHS QuvO8 1S3l 1004V1 AVM Z ONY v09 132208 NO Q3SYG SNOISN3WIG v o IECH G3HONI NI Q31VIS SNOISN3NIQ o 9666 031392v88 Su3l3WI TTIW NI Q31V1S SNOISN3WIQ AYYNIYd E E q Y6GI G PIA ISNV Ydd S39NV43101 ANY NOISN3HIQ T1V E q 27111 03114408 YJAO 30N30303 4_3 VL ONIMYNO SIHL NO 5 Wl SJONVYFIOL ONY SNOISN3WIQ T1V 3714 3SV8V1VQ0 Q a 03114408 HLIM NOII1V13HNOD NI Q3S 38 OL ONIMVYG SIHL N Wd JOIS AYYNIYd ssion p 7m EE NEE NO11V804409 T31N1 40 LNISNOJ N3LLIYM 20104 JHL LDOHLIM 031410014 YO C34V14S Q 0300004438 038019810 38 LON AVW 9 TEVLE SE SIN31N09 SLI NY 39N3014N02 NI G3S079S10 SI LI U WIIN3Q14NO2 NOIYNOdHOO 131N1 SNIVINOO ONIAYHO SIHL Ee SI all ye EEES am g f 9 L g c o o Ee o i c Ki o n o Oo ale re 3 Q
19. Processor 7100 Series Datasheet 35 intel Electrical Specifications Figure 2 8 Vcacne Overshoot Example Waveform 2 10 4 2 10 5 Vcache Overshoot Example Waveform Vcache_max after unloading transient VOS cache Vcache 10 mV per division N Vcache_max prior to unloading transient Time 10 ps per division Notes 1 Vos cacHE is measured overshoot voltage 2 Tos cacueis measured time duration above Vcache max Die Voltage Validation Overshoot events from application testing on the processor must meet the specifications in Table 2 14 when measured across the Vecsense and Vsssense pins and Table 2 15 when measured across the Vcc CACHE SENSE and Vss CACHE SENSE pins Overshoot events that are 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope Clock Miscellaneous and AGTL Specifications Table 2 16 Front Side Bus Differential BCLK Specifications Sheet 1 of 2 36 Symbol Parameter Min Typ Max Unit Notes VL Input Low Voltage 0 150 0 000 N A V VH Input High Voltage 0 660 0 700 0 850 V VcROSS abs Absolute Crossing 0 250 N A 0 550 V 1 7 Point VCROSS rel Relative Crossing 0 250 0 5 N A 0 550 0 5 V 2 7 8 Point Vuayg 0 700 VHavg 0 700 A VCROSS Range of Crossing N A N A 0 140 V Point VOV Overshoot N A N A 0 300 V 3
20. Processor 7100 Series Thermal Mechanical Design Guidelines for system and environmental implementation details 2 The TcowrnoL orrser for 95W TDP parts is greater than or equal to 16 C Table 6 3 95W Dual Core Intel Xeon Processor 7100 Series Thermal Profile teen Tcase max C Tease mal C GE Note The TcoNTROL orrser for 95W TDP parts is greater than or equal to 16 C 76 Dual Core Intel Xeon Processor 7100 Series Datasheet n Thermal Specifications n tel 6 1 2 Figure 6 3 6 2 6 2 1 Thermal Metrology The maximum and minimum case temperatures Tcase specified in Table 6 1 are measured at the geometric top center of the processor integrated heat spreader IHS Figure 6 3 illustrates the location where TcAsg temperature measurements should be made For detailed guidelines on temperature measurement methodology refer to the Dual Core Intel Xeon Processor 7100 Series Thermal Mechanical Design Guidelines Case Temperature TcAsg Measurement Location Measure from edge of IHS 19 2 mm 0 756 in Measure T ep at this point geometric center of IHS 19 2 mm 0 756 in 53 34 mm FC mPGA4 Package Thermal grease should cover entire area of IHS Processor Thermal Features Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the Thermal Control Circuit TCC when the processor silicon reaches its maximum operating t
21. the thermal profile see Figure 6 1 or Figure 6 2 If the diode temperature is less than Tcontrol then the case temperature is permitted to exceed the thermal profile but the diode temperature must remain at or below Tcontrol Systems that implement fan speed control must be designed to take these conditions into account Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications The Dual Core Intel Xeon processor 7100 series thermal profile ensures adherence to Intel reliability requirements The thermal profile is representative of a industry enabled 2U heat sink In this scenario it is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Refer to the Dual Core Intel Xeon Processor 7100 Series Thermal Mechanical Design Guidelines for details on system thermal solution design thermal profiles and environmental considerations Dual Core Intel Xeon Processor 7100 Series Datasheet 73 Table 6 1 74 intel Thermal Specifications The upper point of the thermal profile consists of the Thermal Design Power TDP defined in Table 6 1and the associated Tcase value The lower point of the thermal profile consists of x PCONTROL BASE and y TCASE MAX PCONTROL BASE Pcontrol is defined as the processor power at which TcAsg calculated from the thermal profile correspo
22. transmitted by the thermal sensor and the bits that aren t shaded are transmitted by the SMBus host controller Write Byte SMBus Packet S Slave Address Write Ack Command Code Ack Data Ack P 1 7 bits 0 1 8 bits 1 8 bits 1 1 Read Byte SMBus Packet Slave Command Slave S Address Write Ack Code Ack S Address Read Ack Data f P 1 7 bits 0 i 8 bits 1 1 7 bits 1 1 8 1 1 bits Send Byte SMBus Packet S Slave Address Write Ack Command Code Ack P 1 7 bits 0 1 8 bits 1 1 Receive Byte SMBus Packet S Slave Address Read Ack Data P 1 7 bits 1 1 8 bits 1 1 ARA SMBus Packet S ARA Read Ack Address P 1 0001 100 1 1 Device Address 1 1 Note 1 This is an 8 bit field The device which sent the alert will respond to the ARA Packet with its address in the seven most significant bits The least significant bit is undefined and may return as a 1 or 0 See Section 7 4 1 for details on the Thermal Sensor Device addressing 2 The shaded bits are transmitted by the thermal sensor and the bits that aren t shaded are transmitted by the SMBus host controller Dual Core Intel Xeon Processor 7100 Series Datasheet 111 intel Table 7 13 SMBus Thermal Sensor Command Byte Bit Assignments Features
23. 0 110 CVID 0 023 CVID 0 068 CVID 0 114 CVID 0 014 CVID 0 058 CVID 0 102 Notes 1 Icacne refers to the current drawn by a single Dual Core Intel Xeon processor 7100 series cache The VcacHE MIN loadline assumes two Dual Core Intel Xeon processor 7100 series caches are powered off one VRM and that the second cache is drawing IcAcug max 40A 2 VynM max and Vygu MIN are VRM voltage regulation requirements measured at the power plane reference point the VRM remote sense point is on the system board not at the socket Figure 2 6 Vcacne Static and Transient Tolerance at the Board Icache A 0 5 10 15 20 25 30 35 40 CVID 0 000 4 CVID 0 020 4 SC Vcache CVID 0 040 4 Maximum CVID 0 060 4 fo Vcache Typical Vcache V Vcache CVID 0 080 4 Minimum CVID 0 100 4 CVID 0 120 2 10 2 Vcc Overshoot Specification The Dual Core Intel Xeon processor 7100 series can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the Vecsense and Vsssense pins 34 Dual Core Intel Xeon Processor 7100 Series Datasheet Electrical Specifications Table 2 14 Vcc Overshoot Specification Symbol Par
24. 2 4 5 Torque 8 N m 70 Ibf in 3 4 5 Notes 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 A tensile load is defined as a pulling load applied to the IHS in the direction normal to the IHS surface 3 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 4 These guidelines are based on limited testing for design characterization and incidental applications one time only 5 Handling guidelines are for the package only and do not include the limits of the processor socket 3 5 Package Insertion Specifications The Dual Core Intel Xeon processor 7100 series can be inserted into and removed from a mPGA604 socket 15 times The socket should meet the mPGA604 requirements detailed in the mPGA604 Socket Design Guidelines 3 6 Processor Mass Specifications The typical mass of the Dual Core Intel Xeon processor 7100 series is 34 g 1 20 oz This mass weight includes all the components that are included in the package 3 7 Processor Materials Table 3 3 lists some of the package components and associated materials Table 3 3 Processor Materials Component Material Integrated Heat Spreader IHS Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Pins Gold Plated Copper 3 8 Processor Markings Figure 3 4 shows the topside markings and Figure 3 5 shows the bottom s
25. 26 Processor Absolute Maximum Ratings kaka kk kk kk ak k nns 27 Voltage and Current SpecificatiONS ss ss akla lak sika s ka k kb a ha kak a k e a ka aa EENS ba 28 VCC Static and Transient Tolerance s k s k dini xi EENS NEES a ake pega kla EE KEE EE ENER nace 31 VCACHE Static and Transient Tolerance at the Die Sense Location 33 VCACHE Static and Transient Tolerance at the Board 34 VCC Overshoot Specification eei tenes kalak nek nite xa cages Sa a DR RIA NATA Sa b k b na k 35 VCACHE Overshoot Specifica ti M s six xez sadir sik RENE nasa nana dan ann ke aa acu ede Ra E RYE Rau a 35 Front Side Bus Differential BCLK Specifications ene 36 BSEL 1 0 VID 5 0 and CVID 3 0 DC Specifications hh kk kk kk kk 37 VIDPWRGD DC Specifications cic irnn sta setenta na RER SN DENGER de h ka RR e ban na saw ipe RR Eau Rina 37 AGTL Signal Group DC Specifications sssr u asas mala anad eee eee nemen 38 PWRGOOD and TAP Signal Group DC Specifications kk kk kk 38 GTL Asynchronous and AGTL Asynchronous Signal Group Klee eet ue Le 39 SMBus Signal Group DC Specifications k khk khWkL h lkkkkkkk kk kk kk kk nemen 39 AGTL Bus Voltage Definitions ic sk kikan kak dek e ENEE Sed d a hand nada hak hak a SA k 40 Processor Loading SpecificatiOns sissies is sulu sanika al k nak j yab naza ana kira cx ya sakal Fai NEE aa Ee 45 Package Handling Guidelines
26. 3 4 3 33 3 2 3 16 3 0 2 6 or 2 5 GHz 65 nm process technology Binary compatible with application running on previous members of Intel s IA 32 microprocessor line Intel 64 architecture Intel NetBurst microarchitecture Hyper Threading Technology Hardware support for multithreaded applications Rapid Execution Engine Arithmetic Logic Units ALUS run at twice the processor core frequency Hyper Pipelined Technology intel Machine Check Architecture MCA Includes 16 KB Level 1 L1 data cache 2 MB Advanced Transfer Cache On die full speed Level 2 L2 Cache with 8 way associativity and Error Correcting Code ECC Up to 16MB Level 3 L3 Cache with 16 way associativity and Error Correcting Code ECC Intel Cache Safe Technology Fast 667 or 800 MHz system bus with Error Correcting Code ECC Enables system support of up to 64 GB of physical memory Demand Based Switching DBS with Enhanced Intel SpeedStep Technology Enhanced thermal and power management capabilities W Advanced Dynamic Execution Thermal Monitor TM1 W Very deep out of order execution Thermal Monitor 2 TM2 W Enhanced branch prediction W 144 Streaming SIMD Extensions 2 SSE2 instructions W Intel Virtualization Technology W 13 Streaming SIMD Extensions 3 SSE3 W Execute Disable Bit instructions m Enhanced floating point and multimedia unit for enhanced video audio encryption and 3D performance W
27. 30 2 4 VCC Static and Transient Tolerance sis sa xalaka teirinn ae tetas seb a s AR ERRARE kalan 32 2 5 VCACHE Static and Transient Tolerance at the Die Sense Location 33 2 6 VCACHE Static and Transient Tolerance at the Board 34 2 7 VCC Overshoot Example Waveform a 3 sa aan adil anln nal ka ak aa kanek aia a a daa eee aa ene 35 2 8 VCACHE Overshoot Example Waveform hL L kkkklk kk kk kk eaten kk eens eases kk ak kk kaka 36 3 1 Processor Package Assembly Sketch iani nin nia ka n n Pn kae a geg 41 3 2 Processor Package Drawing Sheet 1 of ii 43 3 3 Processor Package Drawing Sheet 2 of 21 44 3 4 Processor Topside IMarkingSiniis kiyan helise naka RRD dee biban dnd walan de dE de la Dee RERBA RE HE 47 3 5 Processor Bottom Side Markinges ss ca REENEN ene enu na kan ka nana sa aa a a aba dalal asla da Ela 47 3 6 Processor Pin Out Coordinates Top View 48 6 1 150W Dual Core Intel Xeon Processor 7100 Series Thermal Profile 75 4 Dual Core Intel Xeon Processor 7100 Series Datasheet 8 2 8 3 8 4 8 5 8 6 8 7 Tables 1 1 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 2 21 100 d NI WN N oou kk NJ E C IN RR IN E C N RIN N 95W Dual Core Intel Xeon Processor 7100 Series Thermal Profile 76 Case Temperature TCASE Measurement Location 77 Thermal Monitor 2 Frequen
28. 4 Die Voltage Validation isis icin cerise kanala nen l nan b d sa saa x pack P e e b a 36 2 10 5 Clock Miscellaneous and AGTL Gpecflcations tees eee eeeeeeees 36 2 11 AGTL Front Side Bus Specifications emen 40 3 Mechanical Specifications ee esee sa exea ce isa NEEN REENEN kk kaka kak kak kak aka Rr dU 41 3 1 Package Mechanical Drawing c y a sh n Ai nil sene e detienen balad hana d k Waw aa kak EE EE DA ERE 42 3 2 Processor Component Keep Out Zones 45 3 3 Package Loading Specifications dk dE KEES sk lala sikand sa ca lala bala dee da k Wana 45 3 4 Package Handling Guidelines ls kk kasa a khak NENNEN NENNEN nenne nannte nasa ka kd a 46 3 5 Package Insertion Gpechfications kk kk kk eee kk k kk kkkkkkkkkkkakkkkkkkkk kkka kak nee 46 3 6 Processor Mass Specifications Sek SKNKNRNK ka sk n kira a aw k naka kak krea kk ka kin kay ARRA 46 3 7 Processor Materials iced rnnt eo neon ee fepe e qnn kak kelka k ENEE Neie EN k we r e 46 3 8 Processor ManrkingSiisinssiiatesns kan xaza n did da z h klan W a RENE k We W EE n E ANM 46 3 9 Processor Pin Out Coordinates lt s sikak skukxakaxalkk sikk anek aka we a k ma sae ala w ke ae a ea ee d a ade 48 4 x aELIDMETS rrr enge 49 4 1 Dual Core Intel Xeon Processor 7100 Series Pin Assignments ssssss 49 4 1 1 Pin Listing by Pin Name 49 4 1 2 Pin Li
29. 5 2 7 4 3 5 3 7 4 3 6 104 Example The A 0 and A 1 steppings of the Dual Core Intel Xeon processor 7100 series utilizes the first revision package FC mPGA4 Thus at offset 32 35h the data is a space followed by 1 0 In hex this would be 20 31 2E 30 The B 0 stepping of the Dual Core Intel Xeon processor 7100 series utilizes the second revision package FC mPGA6 Thus at offset 32 35h the data is a space followed by 2 0 In hex this would be 20 32 2E 30 Offset 32h 35h Bit Description 31 24 Character 4 ASCII character or 20h 00h 0FFh ASCII character 23 16 Character 3 ASCII character OOh OFFh ASCII character 15 8 Character 2 ASCII character OOh OFFh ASCII character 7 0 Character 1 ASCII character OOh OFFh ASCII character RES5 Reserved 5 This location is reserved Writes to this register have no effect Offset 36h Bit Description 7 0 RESERVED 5 00h FFh Reserved PKDCKS Package Data Checksum This location provides the checksum of the Package Data Section Writes to this register have no effect Offset 37h Bit Description 7 0 Package Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Part Number Data This section provides traceability There are 208 available bytes in this section for future use Dual Core Intel Xeon Proce
30. CVID 3 0 pins supply the encodings that determine the voltage to be supplied by the Vcacue the L3 cache voltage for the Dual Core Intel Xeon processor 7100 series voltage regulator The CVID specification for the Dual Core Intel Xeon processor 7100 22 Dual Core Intel Xeon Processor 7100 Series Datasheet m Electrical Specifications n tel Table 2 5 2 4 series is defined by the VRM 9 1 DC DC Converter Design Guidelines The voltage set by the CVID pins is the maximum VcAcgge Voltage allowed by the processor A minimum Vcacue Voltage is provided in Table 2 10 Dual Core Intel Xeon processor 7100 series with the same front side bus frequency internal cache sizes and stepping will have consistent CVID values The Dual Core Intel Xeon processor 7100 series uses four voltage identification pins CVID 3 0 to support automatic selection of power supply voltages Table 2 5 specifies the voltage level corresponding to the state of CVID 3 0 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty in a single processor per regulator design or if both processor Sockets are empty in a two processors per regulator design or the voltage regulation circuit cannot supply the voltage that is requested the processor s voltage regulator must disable itself See the VRM 9 1 DC DC Converter Design Guidelines for more details Cache Voltage Identification CVID Defini
31. Common Clock Input Synchronous to BCLK 1 0 BPRI BR 3 1 DEFER ID 7 0 IDS OOD RESET RS 2 0 RSP TRDY AGTL Common Clock I O Synchronous to BCLK 1 0 ADS AP 1 0 BINIT BNR BPM 5 0 BRO DBSY DP 3 0 DRDY HIT HITM LOCK MCERR AGTL Source Synchronous I O AGTL Strobe Input Output Synchronous to associated strobe Synchronous to BCLK 1 0 Signals Associated Strobe REQ 4 0 ADSTBO A 37 36 16 3 A 39 38 35 17 ADSTB1 D 15 0 DSTBPO DEP 1 0 DBIO DSTBNO D 31 16 DSTBP1 DEP 3 2 DBI1 DSTBN1 D 47 32 DSTBP2 DEP 5 4 DBI2 DSTBN2 D 63 48 DSTBP3 DEP 7 6 DBI3 DSTBN3 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 AGTL Asynchronous Output Asynchronous FERR PBE IERR PROCHOT GTL Asynchronous Input Asynchronous A20M FORCEPR IGNNE INIT LINTO INTR LINT1 NMI SMI STPCLK GTL Asynchronous Output Asynchronous THERMTRIP TAP Input Synchronous to TCK TCK TDI TMS TAP Input Asynchronous TRST TAP Output Synchronous to TCK TDO Front Side Bus Clock Input Clock BCLK 1 0 SMBus Synchronous to SM_CLK SM_ALERT SM_CLK SM_DAT SM_EP_A 2 0 SM_TS_A 1 0 SM_WP Power Other Power Other BOOT_SELECT BSEL 1 0 COMPO CVID 3 0 GTLREF 3 0 ODTEN PWRGOOD RESERVED SKTOCC SM_VCC TEST_BUS TESTHI 6 0 VcacHE Vcc Vecar Vcc CACHE SENSE VcciopLL VCCPLL VCCSENS
32. DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor front side bus agents DSTBN 3 0 amp DSTBP 3 0 I O I O Data strobe used to latch in D 63 0 DEP 7 0 and DBI 3 0 Data strobe used to latch in D 63 0 DEP 7 0 and DBI 3 0 FERR PBE FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to Vol 3 of the Inte Architecture Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction ap
33. Direction Pin Name Pin No ux nu Direction Vss H4 Power Other Vss M26 Power Other Vss H6 Power Other Vss M28 Power Other Vss H8 Power Other Vss M30 Power Other Vss H24 Power Other Vss N2 Power Other Vss H26 Power Other Vss N4 Power Other Vss H28 Power Other Vss N6 Power Other Vss H30 Power Other Vss N8 Power Other Vss J1 Power Other Vss N24 Power Other Vss J3 Power Other Vss N26 Power Other Vss J5 Power Other Vss N28 Power Other Vss J7 Power Other Vss N30 Power Other Vss J9 Power Other Vss P1 Power Other Vss J23 Power Other Vss P3 Power Other Vss J25 Power Other Vss P5 Power Other Vss J27 Power Other Vss P7 Power Other Vss J29 Power Other Vss P9 Power Other Vss J31 Power Other Vss P23 Power Other Vss K2 Power Other Vss P25 Power Other Vss K4 Power Other Vss P27 Power Other Vss K6 Power Other Vss P29 Power Other Vss K8 Power Other Vss P31 Power Other Vss K24 Power Other Vss R2 Power Other Vss K26 Power Other Vss R4 Power Other Vss K28 Power Other Vss R6 Power Other Vss K30 Power Other Vss R8 Power Other Vss L1 Power Other Vss R24 Power Other Vss L3 Power Other Vss R26 Power Other Vss L5 Power Other Vss R28 Power Other Vss L7 Power Other Vss R30 Power Other Vss L9 Power Other Vss T1 Power Other Vss L23 Power Other Vss T3 Power Other Vss L25 Power Other Vss T5 Power Other Vss L27 Power Other Vss T7 Power Other Vss L29 Power Other Vss T9 Power Other Vss L31 Power Other Vss T23 Power Other Vss M2 Power Other Vss T25 Power Other Vss M4 Power
34. Other Vss T27 Power Other Vss M6 Power Other Vss T29 Power Other Vss M8 Power Other Vss T31 Power Other Vss M24 Power Other Vss U2 Power Other Dual Core Intel Xeon Processor 7100 Series Datasheet 55 intel Pin Listing Table 4 1 Pin Listing by Pin Name Table 4 1 Pin Listing by Pin Name Sheet 15 of 16 Sheet 16 of 16 Pin Name Pin No Exc Direction Pin Name Pin No E a Direction Vss U4 Power Other Vss AA23 Power Other Vss U6 Power Other Vss AA30 Power Other Vss U8 Power Other Vss AB1 Power Other Vss U24 Power Other Vss AB5 Power Other Vss U26 Power Other Vss AB11 Power Other Vss U28 Power Other Vss AB21 Power Other Vss U30 Power Other Vss AB27 Power Other Vss Vi Power Other Vss AB31 Power Other Vss V3 Power Other Vss AC2 Power Other Vss V5 Power Other Vss AC7 Power Other Vss V7 Power Other Vss AC13 Power Other Vss ve Power Other Vss AC19 Power Other Vss V23 Power Other Vss AC25 Power Other Vss V25 Power Other Vss AD3 Power Other Vss V27 Power Other Vss AD9 Power Other Vss V29 Power Other Vss AD15 Power Other Vss V31 Power Other Vss AD17 Power Other Vss w2 Power Other Vss AD23 Power Other Vss WA Power Other Vss AE6 Power Other Vss W24 Power Other Vss AE11 Power Other Vss W26 Power Other Vss AE21 Power Other Vss w28 Power Other Vss AE27 Power Other Vss W30 Power Other Vssa AAS Power Other Input Vss Yi Power Other Vss CACHE SENSE C31 Po
35. Power Other Vcc L30 Power Other Vec V Power Other Vcc M23 Power Other Vcc V24 Power Other Vec M25 Power Other Vec V26 Power Other Vcc M27 Power Other Vec V28 Power Other Vec M29 Power Other Vec v30 Power Other Vcc M31 Power Other Vcc wi Power Other Vcc N23 Power Other Vcc W25 Power Other Vcc N25 Power Other Vcc W27 Power Other Vec N27 Power Other Vcc w29 Power Other Vcc N29 Power Other Vcc W31 Power Other Vcc N31 Power Other Vcc Y2 Power Other Dual Core Intel Xeon Processor 7100 Series Datasheet 53 intel Table 4 1 Pin Listing by Pin Name Table 4 1 Pin Listing by Pin Name Sheet 11 of 16 Sheet 12 of 16 Pin Name Pin No e Direction Pin Name Pin No ee Direction Vcc Y16 Power Other Vss A29 Power Other Vcc Y22 Power Other Vss B2 Power Other Vcc Y30 Power Other Vss B9 Power Other Vcc AA1 Power Other Vss B15 Power Other Vcc AA6 Power Other Vss B17 Power Other Vcc AA20 Power Other Vss B23 Power Other Vcc AA26 Power Other Vss B28 Power Other Vcc AA31 Power Other Vss C7 Power Other Vcc AB2 Power Other Vss C13 Power Other Vcc AB8 Power Other Vss C19 Power Other Vcc AB14 Power Other Vss C25 Power Other Vcc AB18 Power Other Vss C29 Power Other Vec AB24 Power Other Vss D2 Power Other Vcc AB30 Power Other Vss D5 Power Other Vcc AC3 Power Other Vss D11 Power Other Vcc AC16 Power Other Vss D21 Po
36. Programmable Read Only Memory Amemory device located on the processor and addressable via the SMBus which can be used by the OEM to store information useful for system management e SMBus System Management Bus A two wire interface through which simple system and power management related devices can communicate with the rest of the system It is based on the principals of the operation of the I2C two wire serial bus from Phillips Semiconductor Dual Core Intel Xeon Processor 7100 Series Datasheet 13 intel Note I2C is a two wire communications bus protocol developed by Philips SMBus is a subset of the I C bus protocol and was developed by Intel Implementations of the IC bus protocol or the SMBus bus protocol may require licenses from various entities including Philips Electronics N V and North American Philips Corporation e Storage Conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor pins should not be connected to any supply voltages have any I Os biased or receive any clocks e Symmetric Agent A symmetric agent is a processor which shares the same I O subsystem and memory array and runs the same operating system as another processor in a system Systems using symmetric agents are known as Symmetric MultiProcessing SMP systems Dual Core Intel Xeon pro
37. Sensor Alert Interrupt The SMBus thermal sensor located on the processor includes the ability to interrupt the SMBus when a fault condition exists The fault conditions consist of 1 a processor thermal diode value measurement that exceeds a user defined high or low threshold programmed into the Command Register or 2 disconnection of the processor thermal diode from the thermal sensor The interrupt can be enabled and disabled via the thermal sensor Configuration Register and is delivered to the system board via the SM_ALERT open drain output Once latched the SM_ALERT should only be cleared by reading the Alert Response byte from the Alert Response Address of the thermal sensor The Alert Response Address is a special slave address shown in Table 7 12 The SM_ALERT will be cleared once the SMBus master device reads the slave ARA unless the fault condition persists Reading the Status Register or setting the mask bit within the Configuration Register does not clear the interrupt 8 Dual Core Intel Xeon Processor 7100 Series Datasheet E e Boxed Processor Specifications n te 8 8 1 Boxed Processor Specifications Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels Future revisions may have solutions that differ from those discussed here The thermal solution for the boxed Dual Core Intel Xeon processor 7100 series f
38. Signal Direction Pin No Pin Name Signal Direction Buffer Type Buffer Type apis Vs PoweyOter AE8 DEP4A Source Sync Input Output AD16 COMPO Power Other Input AE9 D44 Source Sync Input Output AD17 Vss Power Other AE10 D42 Source Sync Input Output AD18 D36 Source Sync Input Output AE11 Vss Power Other AD19 D30 Source Sync Input Output AE12 DBI2 Source Sync Input Output AD20 Vcc Power Other AE13 D35 Source Sync Input Output AD21 D29 Source Sync Input Output AE14 Vcc Power Other AD22 DBI1 Source Sync Input Output AE15 DEP3 Source Sync Input Output AD23 Vss Power Other AE16 DEP2 Source Sync Input Output AD24 D2i Source Sync Input Output AE17 DP3 Common Clk Input Output AD25 D18 Source Sync Input Output AE18 Vec Power Other AD26 Vcc Power Other AE19 DP1 Common Clk Input Output AD27 D4 SourceSync Input Output AE20 D28 Source Sync Input Output AD28 SM ALERTX SMBus Output AE21 Vss Power Other AD29 SM WP SMBus Input AE22 D27 Source Sync Input Output AD30 DEP1 Source Sync Input Output AE23 D22 Source Sync Input Output AD31 DEPO Source Sync Input Output AE24 Vec Power Other AE2 Don t Care AE25 D19 Source Sync Input Output AE3 Don t Care AE26 D16 Source Sync Input Output AE4 Var AE27 Vss Power Other AE5 TESTHI6 Power Other Input AE28 SM_VCC Power Other AE6 Vss Power Other AE29 SM_VCC Power Other AE7 D58 Source Sync Input Output AE30 Reserved
39. Source Sync A385 B6 Source Sync Source Sync A393 C16 Source Sync Source Sync A20M F27 Async GTL Input ADS D19 Common Clk Input Output ADSTBO F17 Source Sync Input Output ADSTB1 F14 Source Sync Input Output APO E10 Common Clk Input Output AP1 D9 Common Clk Input Output BCLKO Y4 FSB CIk Input BCLK1 w5 FSB Clk Input BINIT F11 Common CIk Input Output BNR F20 Common Clk Input Output BOOT_SELECT G7 Power Other Input BPMO F6 Common Clk Input Output BPM1 F8 Common Clk Input Output BPM2 E7 Common Clk Input Output BPM3 F5 Common Clk Input Output BPM4 E8 Common Clk Input Output BPM5 E4 Common Clk Input Output 49 intel Pin Listing Table 4 1 Pin Listing by Pin Name Table 4 1 Pin Listing by Pin Name Sheet 3 of 16 Sheet 4 of 16 Pin Name Pin No Direction Pin Name Pin No nm s Direction BPRI D23 Common Clk Input D28 AE20 Source Sync Input Output BRO D20 Common CIk Input Output D29 AD21 Source Sync Input Output BR1 F12 Common CIk Input D30 AD19 Source Sync Input Output BR2 E11 Common CIk Input D31 AB17 Source Sync Input Output BR3 D10 Common CIk Input D32 AB16 Source Sync Input Output BSELO AA3 Power Other Output D33 AA16 Source Sync Input Output BSEL1 AB3 Power Other Output D34 AC17 Source Sync Input Output COMPO AD16 Power Other Input D35
40. Sync Input Output D56 AC8 Source Sync Input Output D17 AC26 Source Sync Input Output D57 AD7 Source Sync Input Output D18 AD25 Source Sync Input Output D58 AE7 Source Sync Input Output D19 AE25 Source Sync Input Output D59 AC6 Source Sync Input Output D20 AC24 Source Sync Input Output D60 AC5 Source Sync Input Output D21 AD24 Source Sync Input Output D61 AA Source Sync Input Output D22 AE23 Source Sync Input Output D62 Y9 Source Sync Input Output D23 AC23 Source Sync Input Output D63 AB6 Source Sync Input Output D24 AA18 Source Sync Input Output DBIO AC27 Source Sync Input Output D25 AC20 Source Sync Input Output DBI1 AD22 Source Sync Input Output D26 AC21 Source Sync Input Output DBI2 AE12 Source Sync Input Output D27 AE22 Source Sync Input Output DBI3 AB9 Source Sync Input Output 50 Dual Core Intel Xeon Processor 7100 Series Datasheet Pin Listing Table 4 1 Pin Listing by Pin Name Sheet 5 of 16 intel Table 4 1 Pin Listing by Pin Name Sheet 6 of 16 Signal Buffer Signal Buffer Pin Name Pin No Type Direction Pin Name Pin No Type Direction DBSY F18 Common CIk Input Output ID1 B26 Common Clk Input DEFER C23 Common Clk Input ID2 D25 Common Clk Input DEPO AD31 Source Sync Input
41. Thermal Monitor 2 provide efficient and effective cooling in high temperature situations Enhanced Intel SpeedStep technology allows trade offs to be made between performance and power consumption This may lower average power consumption in conjunction with OS support The Dual Core Intel Xeon processor 7100 series supports Hyper Threading Technology This feature allows a single physical processor to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers control registers to provide increased system responsiveness in multitasking environments and headroom for next generation multi threaded applications More information on Hyper Threading Technology can be found at http www intel com technology hyperthread Support for Intel s Execute Disable Bit functionality has been added which can prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system Execute Disable Bit allows the processor to classify areas in memory by where application code can execute and where it cannot When a malicious worm attempts to insert code in the buffer the processor disables code execution preventing damage or worm propagation Other features within the Intel NetBurst microarchitecture include Advanced Dynamic Execution Advanced Transfer Cach
42. V VoL Output Low Voltage 0 0 400 V To Output Low Current N A 3 0 mA Ij Input Leakage Current N A 10 HA ILo Output Leakage Current N A 10 HA Coup SMBus Pin Capacitance 15 0 pF 3 Notes 1 These parameters are based on design characterization and are not tested 2 All DC specifications for the SMBus signal group are measured at the processor pins 3 Platform designers may need this value to calculate the maximum loading of the SMBus and to determine maximum rise and fall times for SMBus signals Dual Core Intel Xeon Processor 7100 Series Datasheet 39 Table 2 23 40 Electrical Specifications AGTL Front Side Bus Specifications Routing topology recommendations are in the appropriate platform design guide Termination resistors are not required for most AGTL signals because they are integrated into the processor silicon Valid high and low levels are determined by the input buffers which compare a signal s voltage with a reference voltage called GTLREF Table 2 23 lists the GTLREF specifications GTLREF should be generated on the system board using high precision voltage divider circuits For more details on platform design see the appropriate platform design guide AGTL Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes GTLREF Bus Reference 0 98 0 63 0 63 Vr 1 02 0 63 V 1 2 6 Voltage Vr Vr Rot Termination 45 50 55 Q 3 Resistance pull u
43. a signal name refers to an active low signal indicating that a signal is in the asserted state when driven to a low level For example when RESET is low i e when RESET is asserted a reset has been requested Conversely when NMI is high i e when NMI is asserted a nonmaskable interrupt request has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level Front side bus refers to the interface between the processor system core logic i e the chipset components and other bus agents The front side bus supports multiprocessing and cache coherency For this document front side bus is used as the generic term for the Dual Core Intel Xeon processor 7100 series system bus Commonly used terms are explained here for clarification e Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology is the next generation implementation of the Geyserville technology which extends power management capabilities of servers e FC mPGAG The Dual Core Intel Xeon processor 7100 series is available in a Flip Chip Micro Pin Grid Array 6 package consisting of a processor core mounted on a pinned substrate with an integrated heat spreader IHS Thi
44. a single Dual Core Intel Xeon Processor 7100 Series cache The VcacHE min loadline assumes two Dual Core Intel Xeon Processor 7100 Series caches are powered off one VRM and that the second cache is drawing IcAcug max 40A 2 vam max and Vypm MIN are VRM voltage regulation requirements measured across the Vcc cacHe sense and Vss_CACHE_SENSE pins at the socket ji H Figure 2 5 Vcacne Static and Transient Tolerance at the Die Sense Location Icache A 0 5 10 15 20 25 30 35 40 CVID 0 000 4 Vcache CVID 0 050 4 Maximum CVID 0 100 4 CVID 0 150 4 Vcache V CVID 0 200 4 Vesa Typical CVID 0 250 Vcache Minimum CVID 0 300 Notes 1 Icacue refers to the current drawn by a single Dual Core Intel Xeon processor 7100 series cache The VcacHE MIN loadline assumes two Dual Core Intel Xeon processor 7100 series caches are powered off one VRM and that the second cache is drawing IcAcug max 40A 2 ynM MAX ahd Vynu MIN are VRM voltage regulation requirements measured across the Vcc cache SENSE and Vss CACHE SENSE pins at the socket 8 u Dual Core Intel Xeon Processor 7100 Series Datasheet 33 e n tel Electrical Specifications Table 2 13 Veacne Static and Transient Tolerance at the Board icacse TAL Venus Vormer VI VeswemeiV Notes 0 cwb 0 000 Vb o94 cvid o082 12 5 CVID 0 017 CVID 0 061 CVID 0 106 CVID 0 020 CVID 0 065 CVID
45. appropriate platform design guide for complete implementation details VccpLL The on die PLL filter solution will not be implemented on this platform The Vcce input should be left unconnected VcCSENSE VSSSENSE Vecsense and Vsssense provide isolated low impedance connections to the processor core voltage Vcc and ground Vss These signals must be connected to the voltage regulator feedback signals which ensure the output voltage i e processor voltage remains within specification Please see the applicable platform design guide for implementation details VID 5 0 VID 5 0 Voltage ID pins are used to support automatic selection of Vcc These are open drain signals that are driven by the processor and must be pulled to no more than 3 3 V 5 tolerance with a resistor Conversely the Vcc VR output must be disabled prior to the voltage supply for these pins becoming invalid The VID pins are needed to support processor voltage specification variations See Table 2 4 for definitions of these pins The Vcc VR must supply the voltage that is requested by these pins or disable itself VIDPWRGD The processor requires this input to determine that the supply voltage for BSEL 1 0 VID 5 0 and CVID 3 0 is stable and within specification Vss is the ground plane for the Dual Core Intel Xeon processor 7100 series Vssa provides an isolated internal ground for internal PLL s Do not connect directly to gr
46. are bussed together thus all processors are affected in unison The Hyper Threading Technology feature adds the conditions that all logical processors share the same STPCLK signal internally When the STPCLK signal is asserted the processor enters the Stop Grant state issuing a Stop Grant Special Bus Cycle SBC for each processor or logical processor The chipset needs to account for a variable number of processors asserting the Stop Grant SBC on Dual Core Intel Xeon Processor 7100 Series Datasheet 83 intel aya 7 2 2 7 2 2 1 7 2 2 2 84 the bus before allowing the processor to be transitioned into one of the lower processor power states Refer to the applicable chipset specification and the Cedar Mill Processor Family BIOS Writer s Guide for more information Normal State This is the normal operating state for the processor HALT or Enhanced Power Down State The Enhanced HALT power down state is configured and enabled via the BIOS Refer to the Cedar Mill Processor Family BIOS Writer s Guide for Enhanced HALT state configuration information If the Enhanced HALT state is not enabled the default power down state entered will be HALT Refer to the section below for details on HALT and Enhanced HALT states HALT Power Down State HALT is a low power state entered when all logical processors have executed the HALT or MWAIT instruction When one of the logical processors executes the HALT or MWAIT instruction that log
47. bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wire OR signal which must connect the appropriate pins of all processor system bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges BOOT SELECT The BOOT_SELECT input informs the processor whether the platform supports the Dual Core Intel Xeon processor 7100 series Incompatible platform designs will have this input connected to Vss Thus this pin is essentially an electrical key to prevent the Dual Core Intel Xeon processor 7100 series from running in a system that is not designed for it For platforms that are designed to support the Dual Core Intel Xeon processor 7100 series this pin should be changed to a no connect BPM 5 0 I O BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins of all Dual Core Intel Xeon processor 7100 series front side bus agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provi
48. cannot be adjusted based on experimental measurements of TcAsg PROCHOT or Tdiode on random processor samples FORCEPR Signal Pin The FORCEPR force power reduction input can be used by the platform to force the Dual Core Intel Xeon processor 7100 series to activate the TCC If the Thermal Monitor is enabled the TCC will be activated upon the assertion of the FORCEPR signal The TCC will remain active until the system deasserts FORCEPR FORCEPR is an asynchronous input FORCEPR can be used to thermally protect other system components To use the voltage regulator VR as an example when the FORCEPR pin is asserted the TCC in the processor will activate reducing the current consumption of the processor and the corresponding temperature of the VR It should be noted that assertion of FORCEPR does not automatically assert PROCHOT As mentioned previously the PROCHOT signal is asserted when a high temperature situation is detected A minimum pulse width of 500 microseconds is recommended when FORCEPR is asserted by the system Sustained activation of the FORCEPR pin may cause noticeable platform performance degradation Refer to the appropriate platform design guide for details on implementing the FORCEPR signal feature THERMTRIP Signal Pin Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon
49. duty cycle of the TCC will override the duty cycle selected by the On Demand mode Dual Core Intel Xeon Processor 7100 Series Datasheet 79 e n tel Thermal Specifications 6 2 5 6 2 6 6 2 7 80 PROCHOT Signal Pin An external signal PROCHOT processor hot is asserted when the processor die temperature has reached its factory configured trip point If the Thermal Monitor is enabled note that the Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Refer to the JA 32 Intel Architecture Software Developer s Manual and the Cedar Mill Processor Family BIOS Writer s Guide for specific register and programming details PROCHOT is designed to assert at or a few degrees higher than maximum Tease as specified by the thermal profile when dissipating TDP power and cannot be interpreted as an indication of processor case temperature This temperature delta accounts for processor package lifetime and manufacturing variations and attempts to ensure the Thermal Control Circuit is not activated below maximum TcAse when dissipating TDP power There is no defined or fixed correlation between the PROCHOT trip temperature the case temperature or the thermal diode temperature Thermal solutions must be designed to the processor specifications and
50. execution from the SMM handler On the Dual Core Intel Xeon processor 7100 series it is required that SMI assertion be observed 8 BCLKs before the Response Status RS 2 0 is observed by the processor If SMI is asserted during the deassertion of RESET the processor will tri state its outputs STPCLK STPCLK Stop Clock when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the front side bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK TDI TCK Test Clock provides the clock input for the processor Test Access Port TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TEST_BUS Must be connected to all other processor TEST_BUS signals in the system See the appropriate platform design guideline for termination details TESTHI 6 0 TESTHI 6 0 must be connecte
51. has reached an elevated temperature refer to the THERMTRIP definition in Table 5 1 At this point the system bus signal THERMTRIP will go active and stay active as described in Table 5 1 THERMTRIP activation is independent of processor activity and does not generate any bus cycles Intel also recommends removal of Vr TcoNrTROoL and Fan Speed Reduction TcoNTROL S a temperature specification based on a temperature reading from the thermal diode The value for TcowrRoL orrser Will be calibrated in manufacturing and configured for each processor The TcoNTRo temperature for a given processor can be Dual Core Intel Xeon Processor 7100 Series Datasheet n Thermal Specifications n tel 6 2 8 obtained by reading the IA32 TEMPERATURE TARGET MSR in the processor The TcoNrROL OFFSET Value that is read from the IA32 TEMPERATURE TARGET MSR 1A2H must be converted from Hexadecimal to Decimal and added to a TcoNTROL BASE Value of 50 C for 150W TDP parts and added to a TcoNTROL BASE Value of 40 C for 95W TDP parts The Platform Id Bits located in the IA32 PLATFORM ID MSR 17H Bits 52 50 may be used by the BIOS to determine the TDP of the processor A 150W TDP part has a Platform ID of 001 Processor Flag 1 and a 95W TDP part has a Platform ID of 101 Processor Flag 5 Refer to the Cedar Mill Processor Family BIOS Writers Guide for specific register details The value of TcowrRoL orrser May vary from 0x00h to Ox1Eh Refer
52. iiie ode rex n Waa dal kra kek waa sd Mey aA nies 46 Processor Materials iso d nina nnn se kan xalat an bak aa danka nan k SEH Kan y k a bk a ka k D Raa h j ka 46 Pii Listing bY PIN oorr 49 Pin Listing by Pin Number solasan n sina ka aa naya SEN d aa EE ba kak an nak Ka ake XR ra we DEE ERR FER 57 Signal Definitions ere E se a aeg aea DUE cea VA PR du van T Ead REDEEM R AD N 65 Dual Core Intel Xeon Processor 7100 Series Thermal Specifications 74 150W Dual Core Intel Xeon Processor 7100 Series Thermal Profile 75 95W Dual Core Intel Xeon Processor 7100 Series Thermal Profile 76 Power On Configuration Option Pins 83 Thermal Sensor SMBus Addressing 4 iil s k eect tees ee eee eee kalak kala la a ala ak aa ak ala aa al kl kala a i a 89 Dual Core Intel Xeon Processor 7100 Series Datasheet 5 ntel 7 3 7 5 7 6 7 7 7 8 7 9 7 10 7 11 7 12 7 13 7 14 7 15 7 16 7 17 7 18 Memory Device SMBus Addressing i ici kucknak kla a ek lak ka ae aa e kenala kile eli aa a ka e e a a eene 89 Read Byte SMBUS Packet aza alin kan kam e qx en ani baki na ER saa ae kk aa k r ak k d EK deg geed 90 Write Byte SMBUS Packet ecce pee err k W k k h s kk betes Nn ka anan Fe wan kh R ben ka kad 90 Processor Information ROM Data Gectlons kk kk kk kk kk kk mene 91 128 Byte ROM Checksum Va
53. is no larger than 1 kO The processor includes a 10 kQ pull down resistor to Vss for each of these signals For more information on the usage of these pins see Section 7 4 1 SM TS A 1 0 The SM TS A Thermal Sensor Select Address pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple processors The device s addressing as implemented includes a Hi Z state for both address pins The use of the Hi Z state is achieved by leaving the input floating unconnected For more information on the usage of these pins see Section 7 4 1 SM VCC SM VCC provides power to the SMBus components on the Dual Core Intel Xeon processor 7100 series package SM WP WP Write Protect can be used to write protect the Scratch EEPROM The Scratch EEPROM is write protected when this input is pulled high to SM VCC The processor includes a 10 KQ pull down resistor to Vss for this signal Dual Core Intel Xeon Processor 7100 Series Datasheet Signal Definitions Table 5 1 intel Signal Definitions Sheet 7 of 8 Name SMI Type I Description SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program
54. must supply the voltage that is requested by these pins or disable itself D 63 0 I O D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor front side bus agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to strobes and DBI Furthermore the DBI pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 I O DBI 3 0 are source synchronous and indicate the polarity of the D 63 0 and DEP 7 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within an 18 bit group including ECC bits would have been asserted electrically low the bus agent may invert the data bus and corresponding ECC signals for that particular sub phase for that 18 bit group DBSY DEFER I O DBSY Data Bus Busy is asserted by the agent responsible for driv
55. not include the limits of the processor socket This specification applies for thermal retention solutions that allow baseboard deflection This specification applies either for thermal retention solutions that prevent baseboard deflection or for the Intel enabled reference solution CEK 6 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement 7 Experimentally validated test condition used a heatsink mass of 1 Ibm 0 45 kg with 100 G acceleration measured at heatsink mass The dynamic portion of this specification in the product application can have flexibility in specific values but the ultimate product of mass times acceleration should not exceed this validated dynamic load 1 Ibm x 100 G 100 Ib 8 Transient loading is defined as a 2 second duration peak load superimposed on the static load requirement representative of loads experienced by the package during heatsink installation SL Dual Core Intel Xeon Processor 7100 Series Datasheet 45 e n tel Mechanical Specifications 3 4 Package Handling Guidelines Table 3 2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Table 3 2 Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N 80 Ibf 1 4 5 Tensile 156 N 35 Ibf
56. processor front side bus agents MCERR assertion conditions are configurable at a system level Assertion options are defined as follows e Enabled or disabled Asserted if configured for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the JA 32 Intel Software Developer s Manual Volume 3 System Programming Guide or the BIOS Writer s Guide which includes the Dual Core Intel Xeon Processor 7100 Series processor Since multiple agents may drive this signal at the same time MCERR is a wired OR signal which must connect the appropriate pins of all processor front side bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers MCERR is activated on specific clock edges and sampled on specific clock edges ODTEN ODTEN On die termination enable should be connected to Vy through a resistor to enable on die termination for end bus agents For middle bus agents pull this signal down via a resistor to ground to disable on die termination Whenever ODTEN is high on die termination will be active regardless of other states of the bus OOD OOD allows data delivery to occur subsequent to IDS assertion during the Deferred Phase PRO
57. refer to the eXtended Debug Port Debug Port Design Guide for MP Platforms and the appropriate platform design guide for more detailed information regarding debug tools specifications Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging Dual Core Intel Xeon Processor 7100 Series processor systems Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of Dual Core Intel Xeon Processor 7100 Series processor based multiprocessor systems the LAI is critical in providing the ability to probe and capture front side bus signals There are two sets of considerations to keep in mind when designing a Dual Core Intel Xeon Processor 7100 Series processor based system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI pins plug into the socket while the processor pins plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained f
58. tage 9999991 388686 V KC 900090000000000050099900 9999090 00999000900090089 EE EE EE 9399999499993999909999999 000 Gd 90999099999999000909999000 3 0 EE h CIT 8 oN eat 908 1009 Vai Z 008 1 al 00671 bet qd ne Beene ao PATAS me a nh 2 n no hen n SS ae Be Sx Gs 88 of os 59 pens mal SES Wo daa ee e ee EE MO L4Y 04809 12111 40 Amen NALLIWA 0184 3M InOHLUM 138019510 3G ION AYN SININOS SLI NY EE BE MEET DATE EE 3 STOOD ATAVER SINL SI agal Cusl 26261V on onal P T 8 9 L g intel Figure 8 3 Dual Core Intel Xeon Processor 7100 Series Datasheet 120 intel Boxed Processor Specifications Bottom Side Board Keep Out Zones Figure 8 4 Y Y S 9 1 g M CODE SWHOdIVld NI YO4 NId33y LHO 3H LN3NOdNOO XYW WW PS 2 00l SNYOSIVId JAOGY NY NZ N03 NI d13 LHOIIH IN3NOdWOD XYW WW 80 6 002 Q3H011Y LN3W32V1d 1N3NOdHO2 QUYOGU3HLON ON 31V1d 9NIUdS e 00L 96 6 000 21 kK 800 _ INN T ARA 008 2 JE 000 2 8 06 000 0 i 05271 G 9 059 Y Ia SWYOALV 1d JAQAY QNV NZ 303 NId33 1912 LNINOdWOD XVN WW 80 S 1I NOISU3A CISS NOIL1V2I3I23dS AWG S21NO812313 NIHIL JHL NO Q3SYG 3UV SNOISN3HIQ JS3HL SWYOSLV Id NI uOJ LHOI3H IN3NOdWOO XVN WW vS 2 00I 002 205 AHVQONOO3S 32N38333U 404 NMOHS QUVOS IS3
59. tas cher re da na daah GE E aa kaka Wae xa ha Seha Wana n bA G an ER w wana Ta Dee W 117 8 2 Mechanical Specifications SSES N ENNER EN AR ka heka kak a kla ayak Wk kk kala l k aka e ka ar NENNEN 118 8 2 1 Boxed Processor Heatsink Dimensions Lh khk kkkkk kk kk kk kk kkkkkkkkkkkkkkkkkkk 118 8 2 2 Boxed Processor Heatsink Weight sess meme 125 8 2 3 Boxed Processor Retention Mechanism and Heatsink Supports 125 8 3 Thermal Specifications says yan sadsala can n edu ss ka naa ge REES aac xa aa d ded re dua adus 125 8 3 1 Boxed Processor Cooling Reouirements eee eeeeeeaeeeeeeeee 125 8 3 2 Boxed Processor Contebnte see euer ANS EEN NEE RENE SE a kaka naa aba ka ER AGREE Ee 126 9 Debug Tools Specifications ege ENER SES REESEN ERR ceux sa ap na saan RR EE ENEE ENER KSE NARRA 127 9 1 logic Analyzer Interface LAL s asn s y aye ni sman nus nanan na nad rane sira da la sinan aa a ge e degen 127 9 1 1 Mechanical Considerations cesses KSE bana ke kalak REESEN abad ka nak ak n k 127 9 1 2 Electrical Considerations s iax s eei a dana aa kann b ka ak nenale aa k ENEE die 127 Figures 2 1 On Die Front Side Bus Termination a cek nas ala anaka kas halk dana akan akai na ka ana dana aya aE 18 2 2 Phase Lock Loop PLL Filter Reguiremente kk kk kk mmm 20 2 3 Dual Core Intel Xeon Processor 7100 Series Load Current vs Time
60. the lower bus ratio and VID operating point of the Enhanced HALT state While in the Enhanced HALT Snoop state snoops and interrupt transactions are handled the same way as in the HALT Snoop state After the snoop is serviced or the interrupt is latched the processor returns to the Enhanced HALT state Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology enables the processor to switch between frequency and voltage points which may result in platform power savings In order to support this technology the system must support dynamic VID transitions Switching between voltage frequency states is software controlled For more configuration details also refer to the Cedar Mill Processor Family BIOS Writer s Guide Not all processors are capable of supporting Enhanced Intel SpeedStep Technology More details on which processor frequencies will support this feature will be provided in future releases of the NDA Specification Update Enhanced Intel SpeedStep Technology is a technology that creates processor performance states P states P states are power consumption and capability states within the Normal state Enhanced Intel SpeedStep technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the Dual Core Int
61. their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing the falling edge of BCLK1 Dual Core Intel Xeon Processor 7100 Series Datasheet 65 Table 5 1 66 intel Signal Definitions Signal Definitions Sheet 2 of 8 Name BINIT Type I O Description BINIT Bus Initialization may be observed and driven by all processor front side bus agents If used BINIT must connect the appropriate pins of all such agents If the BINIT driver is enabled BINIT is asserted to signal any bus condition that prevents reliable future operation If BINIT observation is enabled during power on configuration see Section 7 1 and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their I O Queue IOQ and transaction tracking state machines upon observation of BINIT assertion Once the BINIT assertion has been observed the bus agents will re arbitrate for the front side bus and attempt completion of their bus queue and IOQ entries If BINIT observation is enabled during power on configuration a central agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system BNR I O BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a
62. to 3 3V 1000 Q 2 Igi Max Pin Current 8 mA Io Output Leakage Current 200 HA 3 VroL Voltage Tolerance 3 3 1 05 V 4 Notes 1 These parameters are not tested and are based on design simulations 2 Pull up each line to 3 3 V using 1 KO 5 resistor Refer to 64 bit Intel Xeon Processor MP Platform Design Guide 3 Leakage to Vss with pin held at 2 5 V 4 Represents the maximum allowable termination voltage Table 2 18 VIDPWRGD DC Specifications Symbol Parameter Min Max Unit Notes Vu Input Low Voltage 0 0 0 30 V Vin Input High Voltage 0 90 Vr V Dual Core Intel Xeon Processor 7100 Series Datasheet 37 intel Table 2 19 AGTL Signal Group DC Specifications Electrical Specifications Symbol Parameter Min Max Unit Notes VIL Input Low Voltage 0 0 GTLREF 0 10 Ver V 1 3 VIH Input High Voltage GTLREF 0 10 Mr Vir V 2 3 VOH Output High Voltage 0 90 Vir Vit V 3 IOL Output Low Current N A Vrr mA 5 0 50 Rtt min RON min Ri ILI Input Leakage Current N A 200 HA 4 ILO Output Leakage Current N A 200 HA 6 RON Buffer On Resistance 8 12 Q Notes 1 Vj is defined as the voltage level at a receiving agent that will be interpreted as a logical low value 2 Vy is defined as the voltage level at a receiving agent that will be interpreted as a logical high value 3 The V4 referred to in these specifications refers to the instantaneou
63. to the Cedar Mill Processor Family BIOS Writers Guide for specific register details When Tdiode is above Tconrno then Tcase must be at or below Tcase max as defined by the thermal profile see Figure 6 1 and Table 6 2 or Figure 6 2 and Table 6 3 Otherwise the processor temperature can be maintained at TcoNTROL Thermal Diode The processor incorporates two on die thermal diodes A thermal sensor located on the processor package monitors the die temperature of the processor for thermal management long term die temperature change purposes The thermal diodes are separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor 8 Dual Core Intel Xeon Processor 7100 Series Datasheet 81 82 Thermal Specifications Dual Core Intel Xeon Processor 7100 Series Datasheet Features 7 7 1 Table 7 1 7 2 intel Features Power On Configuration Options Several configuration options can be set by hardware The Dual Core Intel Xeon processor 7100 series samples its hardware configuration at reset on the active to inactive transition of RESET Z For specifications on these options refer to Table 7 1 The sampled information configures the processor for subsequent operation These configuration options can only be changed by another reset All resets configure the processor For reset purposes the processor does not distinguish between a warm reset and a pow
64. 0 signals are used to select the frequency of the processor input clock BCLK 1 0 Table 2 3 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All processors must operate at the same front side bus frequency The Dual Core Intel Xeon processor 7100 series operates at a 667 MTS or 800 MTS front side bus frequency selected by a 166 MHz or 200 MHz BCLK 1 0 frequency Individual processors operate at the front side bus frequency specified by BSEL 1 0 For more information about these pins refer to Section 5 1 and the appropriate platform design guide Dual Core Intel Xeon Processor 7100 Series Datasheet 19 1 0 Tabl 1 0 BSEL1 BSELO Function RESERVED RESERVED 1 1 166 MHz 2 1 3 Phase Lock Loop PLL Power and Filter CCIOP d Vcca_CACHE are power so i Diagram not to scale 2 No specification for frequencies beyond f ore core frequency Dual Core Intel Xeon Processor 7100 Series Datasheet Electrical Specifications n tel 2 2 3 fpeak if existent should be less than 0 05 MHz fcore represents the maximum core frequency supported by the platform Voltage Identification VID The VID 5 0 pins supply the encodings that determine the voltage to be supplied by the Vcc the core voltage for the Dual Core Intel Xeon processor 710
65. 0 series voltage regulator The VID specification for the Dual Core Intel Xeon processor 7100 series is defined by the Vcc Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 2 Design Guidelines The voltage set by the VID signals is the maximum Vcc voltage allowed by the processor VID signals are open drain outputs which must be pulled up to Vr Please refer to Table 2 17 for the DC specifications for these signals A minimum Vcc voltage is provided in Table 2 10 and changes with frequency This allows processors running at a higher frequency to have a relaxed minimum Vcc voltage specification The specifications have been set such that one voltage regulator can work with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings Furthermore any Dual Core Intel Xeon Processor 7100 Series processor even those on the same processor front side bus can drive different VID settings during normal operation The Dual Core Intel Xeon processor 7100 series uses six voltage identification pins VID 5 0 to support automatic selection of power supply voltages Table 2 4 specifies the voltage level corresponding to the state of VID 5 0 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty i e VID 5 0 x11111 or the voltage reg
66. 00006 0000 000000000 seee o 000000000 000000000 eeeeeceoe 000000000 000000000 000000000 000000000 000000000 00000000S 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 aseeeeee 000000000 000000000 000000000 090000 0000000060 tz P sevova Eg 3128 MIN d01 LED 03H21VHSS08 4004334 1N3N0dNO2 189138 1N3N0dH0 3189VM011V ER M3IA 3018 Y 1 E 7 o P 3ov 0Y4 LALALALLLLLALALLL L LLLL LlI Fix II NOILVYOdHOD TILNI JO LN3SNOO NILLIYM J014 JHL INOHLIM 0314100N HO 031Y14810 0300008438 038019810 38 LON AVW SIN31NO SLI ONY 22201 M07 NI 038012810 SI LI NOILVWSOJNI TVILN3014NO9 NOI1VHOdHO 131NI SNIVINOO ONIMVHG STHL Z sys 68580 9 L 8 Dual Core Intel Xeon Processor 7100 Series Datasheet 44 n Mechanical Specifications n tel 3 2 3 3 Table 3 1 Processor Component Keep Out Zones The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep out zones Decoupling capacitors are typically mount
67. 010 0 0 1 X A4h A5h 1010 0 1 0 X A6h A7h 1010 0 1 1 X A8h A9h 1010 1 0 0 X AAh ABh 1010 1 0 1 X ACh ADh 1010 1 1 0 X AEh AFh 1010 1 1 1 X Note 1 This addressing scheme will support up to 8 processors on a single SMBus Dual Core Intel Xeon Processor 7100 Series Datasheet 89 intel T Table 7 4 Table 7 5 7 4 3 90 PIROM and Scratch EEPROM Supported SMBus Transactions The Processor Information ROM PIROM responds to two SMBus packet types Read Byte and Write Byte However since the PIROM is write protected it will acknowledge a Write Byte command but ignore the data The Scratch EEPROM responds to Read Byte and Write Byte commands Table 7 4 diagrams the Read Byte command Table 7 5 diagrams the Write Byte command Following a write cycle to the scratch ROM software must allow a minimum of 10 ms before accessing either ROM of the processor In the tables S represents the SMBus start bit P represents a stop bit R represents a read bit W represents a write bit A represents an acknowledge ACK and represents a negative acknowledge NACK The shaded bits are transmitted by the Processor Information ROM or Scratch EEPROM and the bits that aren t shaded are transmitted by the SMBus host controller In the tables the data addresses indicate 8 bits The SMBus host controller should transmit 8 bits with the most significant bit indicating which section of the EEPROM is
68. 1 CPUID CPUID This location contains the CPUID Processor Type Family Model and Stepping The CPUID field is a copy of the results in EAX 13 0 from Function 1 of the CPUID instruction The MSB is at location 16h the LSB is at location 17h Writes to this register have no effect Example If the CPUID of a processor is OF68h then the value programmed into offset 16 17h of the PIROM is 3DAOh Note The field is not aligned on a byte boundary since the first two bits of the offset are reserved Thus the data must be shifted right by two in order to obtain the same results Note The first two bits of the PIROM are reserved as highlighted in the example below CPUID instruction results 0000 1111 0110 1000 OF68h PIROM content 0011 1101 1010 0000 3DA0h Offset 16h 17h Bit Description 15 14 Processor Type 00b 11b Processor Type 13 10 Processor Family OOh OFh Processor Family 9 6 Processor Model OOh OFh Processor Model 5 2 Processor Stepping 00h OFh Processor Stepping 1 0 Reserved 00b 11b Reserved 98 Dual Core Intel Xeon Processor 7100 Series Datasheet Features 7 4 3 3 2 7 4 3 3 3 7 4 3 3 4 intel RES2 Reserved 2 These locations are reserved Writes to this register have no effect Offset 18h 19h Bit Description 15 0 RESERVED 2 0000h FFFFh Reserved FSB Front Side Bus Speed This location contains the fr
69. 39h FFh Reserved 7 4 3 1 8 TRDA Thermal Reference Data Address This location provides the offset to the Thermal Reference Data Section Writes to this register have no effect Offset 08h Bit Description 7 0 Thermal Reference Data Address Byte pointer to the Thermal Reference Data section 00h Thermal Reference Data section not present 01h 6Fh Reserved 70h Thermal Reference Data section pointer value 71h FFh Reserved 7 4 3 1 9 FDA Feature Data Address This location provides the offset to the Feature Data Section Writes to this register have no effect Offset 09h Bit Description 7 0 Feature Data Address Byte pointer to the Feature Data section 00h Feature Data section not present Oih 73h Reserved 74h Feature Data section pointer value 75h FFh Reserved Dual Core Intel Xeon Processor 7100 Series Datasheet 95 intel TN 7 4 3 1 10 7 4 3 1 11 7 4 3 1 12 7 4 3 2 7 4 3 2 1 96 ODA Other Data Address This location provides the offset to the Other Data Section Writes to this register have no effect Offset OAh Bit Description 7 0 Other Data Address Byte pointer to the Other Data section 00h Other Data section not present Oih 7Dh Reserved 7Eh Other Data section pointer value 7Fh FFh Reserved RES1 Reserved 1 This locations are reserved Writes to this register have no effect Offset OBh OCh
70. 6 D32 Source Sync Input Output AC25 Vss Power Other AB17 D31 Source Sync Input Output AC26 D17 Source Sync Input Output AB18 Vec Power Other AC27 DBIO Source Sync Input Output AB19 D14 Source Sync Input Output AC28 SM_CLK SMBus Input AB20 D12 Source Sync Input Output AC29 SM_DAT SMBus Output AB21 Vss Power Other AC30 Don t Care AB22 D13 Source Sync Input Output AC31 Vec Power Other AB23 D9 Source Sync Input Output AD1 VccPLL Power Other Input AB24 Vcc Power Other AD2 Vcc Power Other AB25 D8 Source Sync Input Output AD3 Vss Power Other AB26 D7 Source Sync Input Output AD4 VccioPLL Power Other Input AB27 Vss Power Other AD5 TESTHI5 Power Other Input AB28 SM_EP_A2 SMBus Input AD6 DEP5 Source Sync Input Output AB29 SM EP A1 SMBus Input AD7 D57 Source Sync Input Output AB30 Vec Power Other AD8 D46 Source Sync Input Output AB31 Vss Power Other AD9 Vss Power Other AC1 Don t Care AD10 D45 Source Sync Input Output AC2 Vss Power Other AD11 D40 Source Sync Input Output AC3 Vcc Power Other AD12 Vir Power Other ACA DEP6 Source Sync Input Output AD13 D38 Source Sync Input Output AC5 D60 Source Sync Input Output AD14 D39 Source Sync Input Output Dual Core Intel Xeon Processor 7100 Series Datasheet 63 intel Table 4 2 Pin Listing by Pin Number Table 4 2 Pin Listing by Pin Number Sheet 15 of 16 Sheet 16 of 16 Pin No Pin Name
71. 667 or 800 MTS FSB Dual Core Intel Xeon processor 7100 series will be available with 4 MB 8 MB or 16 MB of on die level 3 L3 cache All versions of the Dual Core Intel Xeon processor 7100 series will include manageability features Components of the manageability features include an OEM EEPROM and Processor Information ROM which are accessed through an SMBus interface and contain information relevant to the particular processor and system in which it is installed Features of the Dual Core Intel Xeon Processor 7100 Series of Supported L2 Advanced Integrated L3 FSB Symmetric Agents Per FSB Transfer Cache Cache Frequency Dual Core Intel 1 2 2 MB total 4 MB 8 MB or 667 or Xeon Processor 1 MB per core 16 MB 800 MTS 7100 Series Notes 1 Total accessible size of L2 caches may vary by one cache line pair 128 bytes per core depending on usage and operating environment 2 Total accessible size of the L3 cache may vary by up to thirty two 32 cache lines 64 bytes per line depending on usage and operating environment The Dual Core Intel Xeon processor 7100 series is packaged in a 604 pin Flip Chip Micro Pin Grid Array FC mPGA6 package and utilizes a surface mount Zero Insertion Force ZIF mPGA604 socket The Dual Core Intel Xeon processor 7100 series supports 40 bit addressing data bus ECC protection single bit error correction with double bit error detection and the bus protocol addition of t
72. AE13 Source Sync Input Output CVIDO E2 Power Other Output D36 AD18 Source Sync Input Output CVID1 D1 Power Other Output D37 AB15 Source Sync Input Output CVID2 C2 Power Other Output D38 AD13 Source Sync Input Output CVID3 A2 Power Other Output D39 AD14 Source Sync Input Output DO Y26 Source Sync Input Output D40 AD11 Source Sync Input Output Di AA27 Source Sync Input Output D41 AC12 Source Sync Input Output D2 Y24 Source Sync Input Output D42 AE10 Source Sync Input Output D3 AA25 Source Sync Input Output D43 AC11 Source Sync Input Output D4 AD27 Source Sync Input Output D44 AE9 Source Sync Input Output D5 Y23 Source Sync Input Output D45 AD10 Source Sync Input Output D6 AA24 Source Sync Input Output D46 AD8 Source Sync Input Output D7 AB26 Source Sync Input Output D47 AC9 Source Sync Input Output D8 AB25 Source Sync Input Output D48 AA13 Source Sync Input Output D9 AB23 Source Sync Input Output D49 AA14 Source Sync Input Output D10 AA22 Source Sync Input Output D50 AC14 Source Sync Input Output D11 AA21 Source Sync Input Output D51 AB12 Source Sync Input Output D124 AB20 Source Sync Input Output D52 AB13 Source Sync Input Output D134 AB22 Source Sync Input Output D53 AA11 Source Sync Input Output D14 AB19 Source Sync Input Output D54 AA10 Source Sync Input Output D15 AA19 Source Sync Input Output D55 AB10 Source Sync Input Output D16 AE26 Source
73. AP 1 0 BOOT SELECT PWRGOOD TCK1 TDI TMS BINIT BNR BPM 5 0 BPRI BR 3 0 TRST 1 VIDPWRGD D 63 0 DBI 3 0 DBSY DEFER DEP 7 0 DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FORCEPR HIT HITM ID 7 0 IDS IGNNE INIT LINTO INTR LINT1 NMI LOCK MCERR ODTEN OOD REQ 4 0 RESET RS 2 0 RSP SMI STPCLK TRDY Notes 1 These signals also have hysteresis added to the reference voltage See Table 2 20 for more information GTL Asynchronous and AGTL Asynchronous Signals The Dual Core Intel Xeon Processor 7100 Series processor does not utilize CMOS voltage levels on any signals that connect to the processor silicon As a result inputs signals such as A20M FORCEPR IGNNE INIT LINTO INTR LINT1 NMI SMI and STPCLK utilize GTL buffers Legacy output THERMTRIP utilizes a GTL output buffer All of these asynchronous signals follow the same DC requirements as GTL signals however the outputs are not driven high during the logical 0 to 1 transition by the processor FERR PBE IERR and PROCHOT have now been defined as AGTL asynchronous signals as they include an active pMOS device GTL asynchronous and AGTL asynchronous signals do not have setup or hold time specifications in relation to BCLK 1 0 However all of the GTL asynchronous and AGTL asynchronous signals are required to be asserted deasserted for at least six BCLKs in order for the processor to r
74. Bus thermal sensor may be used to read the thermal diode mentioned in Section 6 2 8 These devices and their features are described below The SMBus thermal sensor and its associated thermal diode are not related to and are completely independent of the precision on die temperature sensor and thermal control circuit TCC of the Thermal Monitor or Thermal Monitor 2 features discussed in Section 6 2 1 The processor SMBus implementation uses the clock and data signals of the System Management Bus SMBus Specification It does not implement the SMBSUS signal Layout and routing guidelines are available in the appropriate platform design guide document For platforms which do not implement any of the SMBus features found on the processor all of the SMBus connections except SM VCC to the socket pins may be left unconnected SM ALERT SM CLK SM DAT SM EP A 2 0 SM TS A 1 0 SM WP Dual Core Intel Xeon Processor 7100 Series Datasheet 87 intel T Figure 7 2 7 4 1 88 Logical Schematic of SMBus Circuitry SM VCC SM TS A0 SM TS Al vec SM EP AQ A0 Processor A0 SM EP A Information Al SMEPA Thermal Sensor suwe al ALERT VSS SM CLK SM DAT SM_ALERT Note Actual implementation may vary This figure is provided to offer a general understanding of the architecture All SMBus pull up and pull down resistors are 10 kQ and located on the processor SMBus Device Addressing Of the addr
75. CHOT The assertion of PROCHOT processor hot indicates that the processor die temperature has reached its thermal limit See Section 6 2 4 for more details PWRGOOD PWRGOOD Power Good is an input The processor requires this signal to be a clean indication that all Dual Core Intel Xeon processor 7100 series clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor This signal is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation Dual Core Intel Xeon Processor 7100 Series Datasheet 69 intel Table 5 1 70 Signal Definitions Signal Definitions Sheet 6 of 8 Name REQ 4 0 Type I O Description REQ 4 0 Request Command must connect the appropriate pins of all processor front side bus agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 1 0 Refer to the AP 1 0 signal d
76. Core 7 4 Reserved Information 3 2 Number of cores 1 0 Number of threads per core 7Ah 8 Additional Processor Feature 7 Reserved Flags 6 Intel Cache Safe Technology 5 C1E State 4 Intel Virtualization Technology 3 Execute Disable 2 Intel 64 1 Thermal Monitor TM2 0 Enhanced Intel SpeedStep Technology 7B 7Ch 16 Thermal Adjustment Factors 15 8 Measurement Correction Factor Pending 7 0 Temperature Target 7D 7Eh 16 Reserved Reserved 7Fh 8 Checksum 1 byte checksum Details on each of these sections are described below Reserved fields or bits SHOULD be programmed to zeros However OEMs should not rely on this model Dual Core Intel Xeon Processor 7100 Series Datasheet Features 7 4 3 1 7 4 3 1 1 7 4 3 1 2 7 4 3 1 3 intel Header To maintain backward compatibility the Header defines the starting address for each subsequent section of the PIROM Software should check for the offset before reading data from a particular section of the ROM Example Code looking for the cache data of a processor would read offset O5h to find a value of 25h 25h is the first address within the Cache Data section of the PIROM DFR Data Format Revision This location identifies the data format revision of the PIROM data structure Writes to this register have no effect Offset 00h Bit Description 7 0 Data Format Revision The data format revision i
77. Dual Core Intel Xeon Processor 7100 Series Datasheet September 2006 Reference Number 314553 Revision 002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Dual Core Intel Xeon Processor 7100 Series Processor 7110 7120 7130 7140 and 7150 processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request I C
78. E VID 5 0 VIDPWRGD Vse Vesa Vss_CACHE_SENSE VssseNse Vry VITEN Dual Core Intel Xeon Processor 7100 Series Datasheet 25 e n tel Electrical Specifications Table 2 7 Table 2 8 2 7 26 Notes 1 Refer to Section 5 1 for signal descriptions Signal Description Table Signals with R A 39 3 ADS ADSTB 1 0 AP 1 0 BINIT BNR BOOT SELECT BPRI D 63 0 DBI 3 0 DBSY DEFER DEP 7 0 DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 HIT HITM ID 7 0 IDS LOCK MCERR OOD REQ 4 0 RS 2 0 RSP TRDY Signals with R BINIT BNR HIT HITM MCERR Notes 1 Signals not included in the Signals with R r list require termination on the baseboard Please refer to Table 2 6 for the signal type and Table 2 17 to Table 2 22 for the corresponding DC specifications 2 The BOOT_SELECT pin is not terminated to Ry It has a 500 5000 Q internal pullup The ODTEN signals enables or disables Ry Those signals affected by ODTEN still present Ry termination to the signal s pin when the processor is placed in tri state mode Furthermore the following signals are not affected when the processor is placed in tri state mode BSEL 1 0 CVID 3 0 SKTOCC SM_ALERT SM_CLK SM_DAT SM_EP_A 2 0 SM_TS_A 1 0 SM_WP TEST_BUS TESTHI 6 0 VID 5 0 and VTTEN Signal Reference Voltages GTLREF Vor 2 A20M A 39 3 ADS ADSTB 1 0
79. Offset 04h Bit Description 7 0 Processor Core Data Address Byte pointer to the Processor Data section 00h Processor Core Data section not present Oih 15h Reserved 16h Processor Core Data section pointer value 17h FFh Reserved L3CDA L3 Cache Data Address This location provides the offset to the L3 Cache Data Section Writes to this register have no effect Offset 05h Bit Description 7 0 L3 Cache Data Address Byte pointer to the L3 Cache Data section 00h L3 Cache Data section not present Oth 24h Reserved 25h L3 Cache Data section pointer value 26h FFh Reserved PKDA Package Data Address This location provides the offset to the Package Data Section Writes to this register have no effect Offset 06h Bit Description 7 0 Package Data Address Byte pointer to the Package Data section 00h Package Data section not present Oth 31h Reserved 32h Package Data section pointer value 33h FFh Reserved Dual Core Intel Xeon Processor 7100 Series Datasheet intel 7 4 3 1 7 PNDA Part Number Data Address This location provides the offset to the Part Number Data Section Writes to this register have no effect Offset 07h Bit Description 7 0 Part Number Data Address Byte pointer to the Part Number Data section 00h Part Number Data section not present Oih 37h Reserved 38h Part Number Data section pointer value
80. Output ID3 D27 Common Clk Input DEP1 AD30 Source Sync Input Output ID4 C28 Common Clk Input DEP2 AE16 Source Sync Input Output ID5 B29 Common Clk Input DEP3 AE15 Source Sync Input Output ID6 B30 Common Clk Input DEP4 AE8 Source Sync Input Output ID7 A30 Common CIk Input DEP5 AD6 Source Sync Input Output IDS A28 Common Clk Input DEP6 AC4 Source Sync Input Output IERR E5 Async GTL Output DEP7 AAA Source Sync Input Output IGNNE C26 Async GTL Input DPO AC18 Common Clk Input Output INIT D6 Async GTL Input DP1 AE19 Common Clk Input Output LINTO INTR B24 Async GTL Input DP2 AC15 Common Clk Input Output LINT1 NMI G23 Async GTL Input DP3 AE17 Common Clk Input Output LOCK A17 Common Clk Input Output DRDY E18 Common Clk Input Output MCERR D7 Common Clk Input Output DSTBNO Y21 Source Sync Input Output ODTEN B5 Power Other Input DSTBN1 Y18 Source Sync Input Output OOD D29 Common Clk Input DSTBN2 Y15 Source Sync Input Output PROCHOT B25 Async GTL Output DSTBN3 Y12 Source Sync Input Output PWRGOOD AB7 Async GTL Input DSTBPO Y20 Source Sync Input Output REQO B19 Source Sync Input Output DSTBP1i Y17 Source Sync Input Output REQ1 B21 Source Sync Input Output DSTBP2 Y14 Source Sync Input Output REQ2 C21 Source Sync Input Output DSTBP3 Y11 Source Sync Input Output REQ3 C20 Source Sync Input Output Don t Care B4 REQ4 B22 Source Sync Input Output Don t Care A4 Reserve
81. Power Other Output C3 VID3 Power Other Output C4 Vcc Power Other C5 Don t Care C6 RSP Common Clk Input C7 Vss Power Other C8 A35 Source Sync Input Output C9 A34 Source Sync Input Output C10 Vit Power Other C11 A30 Source Sync Input Output C12 A235 Source Sync Input Output C13 Vss Power Other C14 A163 Source Sync Input Output C15 A155 Source Sync Input Output C16 A39 Source Sync Input Output 57 intel Table 4 2 Pin Listing by Pin Number Sheet 3 of 16 Pin Listing Table 4 2 Pin Listing by Pin Number Sheet 4 of 16 Pin No Pin Name R cara Direction Pin No Pin Name UNE IN Direction C17 A8 Source Sync Input Output D26 VsssENSE Power Other Output C18 A63 Source Sync Input Output D27 ID3 Common Clk Input C19 Vss Power Other D28 Vss Power Other C20 REQ3 Common Clk Input Output D29 OOD Common Clk Input C21 REQ2 Common Clk Input Output D30 Vss Power Other C22 Vece Power Other D31 Vcc Power Other C23 DEFER Common Clk Input Ei VTTEN Power Other Output C24 TDI TAP Input E2 CVIDO Power Other Output C25 Vss Power Other Input E3 VID1 Power Other Output C26 IGNNE Async GTL Input E4 BPM5 Common Clk Input Output C27 SMI Async GTL Input E5 IERR Common Clk Output C28 ID4 Common Clk Input E6 Vcc Power Other C29 Vss Power Other E7 BPM2 Common Clk Inpu
82. System Management mode The Dual Core Intel Xeon processor 7100 series is designed for high performance multi processor server applications for mid tier enterprise serving and server consolidation Based on the Intel NetBurst microarchitecture and the new Hyper Threading Technology it is binary compatible with pervious Intel Architecture IA 32 processors The addition of Intel amp 64 architecture provides 64 bit computing and 40 bit addressing provides up to 1 Terabyte of direct memory addressability The Dual Core Intel Xeon processor 7100 series is scalable to four processors and beyond in a multiprocessor system providing exceptional performance for applications running on advanced operating systems such as Microsoft Windows 2003 server and Linux operating systems The Dual Core Intel Xeon processor 7100 series delivers compute power at unparalleled value and flexibility for internet infrastructure and departmental server applications including application servers databases and business intelligence The Intel NetBurst microarchitecture with Hyper Threading Technology and Intel 64 architecture delivers outstanding performance and headroom from peak internet server workloads resulting in faster response times support for more users and improved scalability 8 Dual Core Intel Xeon Processor 7100 Series Datasheet 9 10 Dual Core Intel Xeon Processor 7100 Series Datasheet Introduction 1 intel Introduction Th
83. TESTHI pins should be tied to Vr using a matched resistor where a matched resistor has a resistance value within 20 of the impedance of the board transmission line traces For example if the trace impedance is 50 Q then a value between 40 Q and 60 Q is required The TESTHI pins may use individual pull up resistors or be grouped together as detailed below Please note that utilization of boundary scan test will not be functional if pins are connected together A matched resistor should be used for each group TESTHI 3 0 TESTHI 6 5 e TESTHIA cannot be grouped with other TESTHI signals Mixing Processors Intel supports and validates multi processor configurations in which all processors operate with the same front side bus frequency core frequency and internal cache sizes Mixing processors operating at different internal clock frequencies is not supported and will not be validated by Intel Intel does not support or validate operation of processors with different cache sizes Mixing different processor steppings but the same model as per the CPUID instruction is supported Details on CPUID are provided in the Cedar Mill Processor Family BIOS Writer s Guide document and the Intel Processor Identification and the CPUID Instruction application note The Dual Core Intel Xeon processor 7100 series does not support mixing of the 7110 7120 7130 or 7140 Processor Numbers The Dual Core Intel Xeon processor 7100 series does support mi
84. V6 Vec Power Other T3 Vss Power Other V7 Vss Power Other T4 Vec Power Other V Vec Power Other T5 Vss Power Other v9 Vss Power Other T6 Vec Power Other V23 Vss Power Other T7 Vss Power Other V24 Vcc Power Other T8 Vec Power Other V25 Vss Power Other T9 Vss Power Other V26 Vcc Power Other T23 Vss Power Other V27 Vss Power Other Dual Core Intel Xeon Processor 7100 Series Datasheet 61 intel Table 4 2 Pin Listing by Pin Number Sheet 11 of 16 Pin Listing Table 4 2 Pin Listing by Pin Number Sheet 12 of 16 Signal Signal Pin No Pin Name Buffer Type Direction Pin No Pin Name Buffer Type Direction V28 Vcc Power Other Y19 Vss Power Other V29 Vss Power Other Y20 DSTBPO Source Sync Input Output v30 Vcc Power Other Y21 DSTBNO Source Sync Input Output V31 Vss Power Other Y22 Vec Power Other WI Vcc Power Other Y23 D5 Source Sync Input Output w2 Vss Power Other Y24 D2 Source Sync Input Output w3 Reserved Y25 Vss Power Other WA Vss Power Other Y26 DO Source Sync Input Output w5 BCLK1 FSB CIk Input Y27 Reserved We TESTHIO Power Other Input Y28 Reserved W7 TESTHI1 Power Other Input Y29 SM TS1 A1 SMBus Input w8 TESTHI2 Power Other Input Y30 Vcc Power Other w9 GTLREF1 Power Other Input Y31 Vss Power Other W23 GTLREFO Power Other Input AAT Vcc Power Other W24 Vss Power Other AA2 Vss Powe
85. al 314555 4 Design Guidelines Dual Core Intel Xeon Processor 7100 Series Thermal Test Vehicle 4 and Cooling Solution Thermal Models 64 bit Intel amp Xeon amp Processor MP with up to 8MB L3 Cache Cooling 1 Solution Mechanical Models 64 bit Intel Xeon Processor MP with up to 8MB L3 Cache Mechanical 2 Models Cedar Mill Processor Family BIOS Writer s Guide BWG 3 eXtended Debug Port Debug Port Design Guide for MP Platforms 3 mPGA604 Socket Design Guidelines 254239 4 14 Dual Core Intel Xeon Processor 7100 Series Datasheet Introduction Document Intel Order Number Notes Vcc Voltage Regulator Module VRM and Enterprise Voltage Regulator 306760 4 Down EVRD 10 2 Design Guidelines VRM 9 1 DC DC Converter Design Guidelines 306826 4 ATX ATX12V Power Supply Design Guidelines MPS Power Supply A Server System Infrastructure SSI Specification 6 For Midrange Chassis Power Supplies System Management Bus SMBus Specification 7 Notes 1 The Dual Core Intel Xeon Processor 7100 Series utilizes the 64 bit Intel Xeon Processor MP with up n Ogu to 8MB L3 Cache Cooling Solution Mechanical Models in ProE and IGES format which are available electronically The Dual Core Intel Xeon Processor 7100 Series utilizes the 64 bit Intel Xeon Processor MP with up to 8MB L3 Cache Mechanical Models in ProE and IGES formats which are available electronically Contact your Intel representative to r
86. ameter Min Max Units Figure Notes Magnitude of Vcc E Vos Max overshoot above VID 0 023 M a Time duration of Vcc E Tos MAx overshoot above VID B us rz Figure 2 7 Vcc Overshoot Example Waveform Voltage Time Overshoot Waveform VID Reference Vos Peak maximum overshoot identified during validation Tos OS time above VID Time from initial VID crossing to final crossing of VID 2 10 3 Veacne Overshoot Specification The Dual Core Intel Xeon processor 7100 series can tolerate short transient overshoot events where Vcacue exceeds the VcAcug maximum loadline voltage when transitioning from a high to low current load condition This overshoot cannot exceed VcAcHE max VOS cache MAX VOS cache MAX is the maximum allowable overshoot above VcacHE max at the low current load These specifications apply to the processor cache voltage as measured across the Vcc CACHE sENsE 8nd Vss CACHE aver PINS Table 2 15 Veacne Overshoot Specification Symbol Parameter Min Max Units Figure Notes Magnitude of VcAcuE Vos_CACHE_MAX overshoot above VCACHE MAX 0 025 2 8 Tos CACHE MAX overshoot above VCACHE MAX Time duration of VcAcHE 50 us 2 8 Note 1 VcacHE Max is defined in Table 2 12 and Table 2 13 where Icacue is the low ending current of the high to low current load condition Dual Core Intel Xeon
87. ated and the TM2 event is complete Not all processors are capable of supporting Thermal Monitor 2 More details on which processor frequencies will support this feature will be provided in future releases of the NDA Specification Update On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor and Thermal Monitor 2 features On Demand mode is intended as a means to reduce system level power consumption Systems utilizing the Dual Core Intel Xeon processor 7100 series processor must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the IA 32 CLOCK MODULATION MSR is written to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the same IA 32 CLOCK MODULATION MSR In On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On Demand mode may be used in conjunction with the Thermal Monitor or Thermal Monitor 2 If Thermal Monitor is enabled and the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured
88. but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes Vcc Processor core supply voltage with 0 3 1 55 V respect to VSS VCACHE Processor L3 cache voltage with 0 3 1 55 V respect to VSS Vit Front side bus termination voltage 0 3 1 55 V with respect to VSS TCASE Processor case temperature See Section 6 See Section 6 SC TsTORAGE Processor storage temperature 40 85 3 4 Notes 1 Forfunctional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Overshoot and undershoot voltage guidelines for input output and I O signals are outlined in Section 3 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Stora
89. ce Sync Input Output A20 A4 Source Sync Input Output A21 Vss Power Other A22 A3 Source Sync Input Output A23 HITM Common CIk Input Output A24 Vec Power Other A25 TMS TAP Input A26 IDO Common CIk Input A27 Vss Power Other A28 IDS Common CIk Input A29 Vss Power Other A30 ID7 Common Clk Input A31 Reserved B1 VIDPWRGD Power Other Input B2 Vss Power Other B3 VID4 Power Other Output B4 Don t Care Power Other B5 ODTEN Power Other Input B6 A38 Source Sync Input Output B7 A31 Source Sync Input Output B8 A27 Source Sync Input Output Dual Core Intel Xeon Processor 7100 Series Datasheet Pin No Pin Name homie Direction B9 Vss Power Other B10 A21 Source Sync Input Output B11 A22 Source Sync Input Output B12 Vir Power Other B13 A135 Source Sync Input Output B14 A125 Source Sync Input Output B15 Vss Power Other B16 A11 Source Sync Input Output B17 Vss Power Other B18 A5 Source Sync Input Output B19 REQO Common Clk Input Output B20 Vec Power Other B21 REQ1 Common CIk Input Output B22 REQ4 Common CIk Input Output B23 Vss Power Other B24 LINTO INTR Async GTL Input B25 PROCHOT Power Other Output B26 ID1 Common Clk Input B27 VccsENSE Power Other Output B28 Vss Power Other B29 ID5 Common CIk Input B30 ID6 Common CIk Input B31 Vcc_cAcHE_SENSE Power Other C1 Don t Care C2 CVID2
90. cessor 7100 series processors should only be used in SMP systems which have two or fewer symmetric agents per front side bus e Dual Core Intel Xeon processor 7100 series The entire product including processor core substrate and integrated heat spreader IHS 1 2 References Material and concepts available in the following documents may be beneficial when reading this document Document Intel Order Number Notes AP 485 Intel Processor Identification and the CPUID Instruction 241618 4 IA 32 Intel Architecture Software Developer s Manual Volume 1 Basic Architecture 253665 e Volume 2A Instruction Set Reference A M 253666 e Volume 2B Instruction Set Reference N Z 253667 e Volume 3A System Programming Guide 253668 e Volume 3B System Programming Guide 253669 IA 32 Intel Architecture Software Developer s Manual Documentation 252046 4 Changes IA 32 Intel Architecture Optimization Reference Manual 248966 4 Intel Extended Memory 64 Technology Software Developer s Manual e Volume 1 300834 e Volume 2 300835 IA 32 Intel Architecture and Intel Extended Memory 64 Technology 252046 4 Software Developer s Manual Documentation Changes Dual Core Intel Xeon Processor 7100 Series Specification Update 314554 4 Dual Core Intel Xeon Processor 7100 Series Boundary Scan 4 Descriptive Language BSDL Files Dual Core Intel Xeon Processor 7100 Series Thermal Mechanic
91. cle For the Dual Core Intel Xeon processor 7100 series both logical processors must be in the Stop Grant state before the deassertion of STPCLK Since the AGTL signal pins receive power from the front side bus these pins should not be driven allowing the level to return to Var for minimum power drawn by the termination resistors in this state In addition all other input pins on the front side bus should be driven to the inactive state BINIT is not serviced while the processor is in Stop Grant state The event is latched and can be serviced by software upon exit from the Stop Grant state RESET causes the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state occurs with the deassertion of the STPCLK signal A transition to the Grant Snoop state occurs when the processor detects a snoop on the front side bus see Section 7 2 4 While in the Stop Grant state SMI INIT BINIT and LINT 1 0 are latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event is recognized upon return to the Normal state Dual Core Intel Xeon Processor 7100 Series Datasheet 85 intel TR 7 2 4 7 2 4 1 7 2 4 2 7 3 Note 86 While in Stop Grant state the processor processes snoops on the front side bus and latches interrupts delivered on the front side bus The PBE signal can be driven wh
92. ctronic Signature This location contains a 64 bit identification number The value in this field is either a serial signature or an electronic signature Bits 5 amp 6 of the Processor Feature Flags Offset 78h indicates which signature is present Intel does not guarantee that each processor will have a unique value in this field Writes to this register have no effect Offset 4Dh 54h Bit Description 63 0 Processor Serial Electronic Signature 00000000h FFFFFFFFh Electronic Signature 7 4 3 6 4 RES7 Reserved 7 This location is reserved Writes to this register have no effect Offset 55h 6Eh Bit Description 207 0 RESERVED 7 7 4 3 6 5 PNDCKS Part Number Data Checksum This location provides the checksum of the Part Number Data Section Writes to this register have no effect Offset 6F Bit Description 7 0 Part Number Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value 7 4 3 7 Thermal Reference Data This section is reserved for future use 7 4 3 7 1 RESS Reserved 8 This location is reserved Writes to this register have no effect Offset 70h Bit Description 7 0 RESERVED 8 106 Dual Core Intel Xeon Processor 7100 Series Datasheet Features 7 4 3 7 2 7 4 3 7 3 7 4 3 8 7 4 3 8 1 7 4 3 8 2 Note RES9 Reserved 9 This location
93. cy and Voltage Ordering tees estes eeeeeeeeeeeees 79 Stop Clock State Machine gedu eegene anit vn SAAR ENEE SEN EEN EE a R yad Mec ER UTE E 85 Logical Schematic of SMBUS Circuitry s ssssssssssnsenensensnunonsenaasnnannnassnnnnnsssanennannano 88 Passive Dual Core Intel Xeon Processor 7100 Series Thermal Solution 3U and larger ccceceee cece eee kabak kl bak kalak nemen 118 Top Side Board Keep Out Zones Part 1 119 Top Side Board Keep Out Zones Part 21 120 Bottom Side Board Keep Out Zones 121 Board Mounting Hole Keep Out Zones 122 Thermal Solution Volumetric lk lakllkkleklkkk dka kak lk sklk aa kak kiw k ak kalak enemies nnns 123 Recommended Processor Layout and Bitch 124 Features of the Dual Core Intel Xeon Processor 7100 Gelee 12 166 MHz Core Frequency to Front Side Bus Multiplier Configuration 18 200 MHz Core Frequency to Front Side Bus Multiplier Configuration es 19 BSEL 1 0 Frequency Table for BCLK 1 0 eeseeeen mmm 19 Voltage Identification VID Definition esssssssssssesne nmm 22 Cache Voltage Identification CVID Definition mmn 23 Front Side BUS Pin Gro ps iiis b yi binay n helka eta sc dene eara ki y k k a bek ead RE AER RE RAE LA Ra REA 25 Signal Description Table eterne mika ennt ch p rex RENE dam n we oia Ka wana oes VERE MEE NEEN 26 Signal Reference Voltages iiis aT NEEN DATE cu duda ra exa eO drea ax Es
94. d Dual Core Intel Xeon Processor 7100 Series Datasheet 99 intel T 7 4 3 3 5 7 4 3 3 6 7 4 3 3 7 Note 100 MCF Maximum Core Frequency This location contains the maximum core frequency for the processor The frequency should equate to the markings on the processor and or the QDF S spec speed even if the parts are not limited or locked to the intended speed Format of this field is in MHz rounded to a whole number and encoded in hex format Writes to this register have no effect Example A 3 40 GHz processor will have a value of OD48h which equates to 3400 decimal Therefore offset 1D 1Eh has a value of 0D48 Offset 1Dh 1Eh Bit Description 15 0 Maximum Core Frequency 0000h 09C3 Reserved 09C4h 2 5 Ghz 09C5h 0A27h Reserved 0A28h 2 6 GHz 0A29h 0BB7h Reserved OBB8h 3 0 GHz OBB9h OCSEh Reserved OC5Fh 3 167 GHz OC60h 0C7Fh Reserved OC80h 3 2 GHz OC81h OD5Eh Reserved ODO5h 3 333 GHz ODO6h 0D47h Reserved OD48h 3 4 GHz OD49h FFFFh Reserved MAXVID Maximum Core VID This location contains the maximum Core VID Voltage Identification voltage that may be requested via the VID pins This field rounded to the next thousandth is in mV and is reflected in hex Writes to this register have no effect Example From Table 2 10 the maximum VID is 1 3500 V maximum voltage Offset 1F 20h would contain 0546h 1350 decimal Offset 1Fh 20h Bit Descripti
95. d A31 Don t Care C1 Reserved E16 Don t Care C5 Reserved w3 Don t Care AC1 Reserved Y27 Don t Care AC30 Reserved Y28 Don t Care AE2 Reserved AE30 Don t Care AE3 RESET Y8 Common Clk Input FERR PBE E27 Async GTL Output RSO E21 Common Clk Input FORCEPR A15 Power Other Input RS1 D22 Common CIk Input GTLREFO w23 Power Other Input RS2 F21 Common Clk Input GTLREF1 WO Power Other Input RSP C6 Common CIk Input GTLREF2 F23 Power Other Input SKTOCC A3 Power Other Output GTLREF3 F9 Power Other Input SM_ALERT AD28 SMBus Output HIT E22 Common CIk Input Output SM CLK AC28 SMBus Input HITM A23 Common CIk Input Output SM DAT AC29 SMBus Input Output IDO A26 Common CIk Input SM EP AO AA29 SMBus Input Dual Core Intel Xeon Processor 7100 Series Datasheet 51 intel Pin Listing Table 4 1 Pin Listing by Pin Name Table 4 1 Pin Listing by Pin Name Sheet 7 of 16 Sheet 8 of 16 Pin Name Pin No Edd Direction Pin Name Pin No Ee Direction SM EP A1 AB29 SMBus Input VCACHE N3 Power Other SM EP A2 AB28 SMBus Input VCACHE N5 Power Other SM TS1 AO AA28 SMBus Input VCACHE N7 Power Other SM TS1 A1 Y29 SMBus Input VCACHE N9 Power Other SM VCC AE28 Power Other VCACHE R1 Power Other SM_VCC AE29 Power Other VCACHE R3 Power Other SM WP AD29 SMBus Input VCACHE R5 Power Other SMI C27 Async GTL Input VCACHE R7 Power Other STPCLK
96. d flow impedance is 29 cfm at 0 14 H20 In addition the processor pitch should be 3 25 inches or slightly more when placed in side by side orientation Figure 8 7 illustrates the side by side orientation and pitch Note that the heatsinks are interleaved to reduce air bypass It is also recommended that the ambient air temperature outside of the chassis be kept at or below 35 C The air passing directly over the processor heatsink should not be preheated by other system components such as another processor and should be kept at or below 40 C Again meeting the processor s temperature specification is the responsibility of the system integrator Dual Core Intel Xeon Processor 7100 Series Datasheet 125 e n tel Boxed Processor Specifications 8 3 2 Boxed Processor Contents The boxed processor will include the following items e Dual Core Intel Xeon processor 7100 series e Unattached Passive Heatsink with captive screws e Thermal Interface Material pre attached e Warranty Installation manual with Intel Inside logo The other items listed in Figure 8 1 required with this thermal solution should be shipped with either the chassis or the mainboard They include e CEK Spring typically included with mainboard Chassis Standoffs e System fans 126 Dual Core Intel Xeon Processor 7100 Series Datasheet n Debug Tools Specifications n tel 9 9 1 9 1 1 9 1 2 Debug Tools Specifications Please
97. d to a Vr power source through a resistor for proper processor operation See Section 2 4 for more details THERMTRIP Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur THERMTRIP Thermal Trip will activate at a temperature that is approximately 15 C above the maximum case temperature TC Measurement of the temperature is accomplished through an internal thermal sensor Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage VCC must be removed following the assertion of THERMTRIP Driving of the THERMTRIP signals is enabled within 10 us of the assertion of PWRGOOD and is disabled on de assertion of PWRGOOD Once activated THERMTRIP remains latched until PWRGOOD is de asserted While the deassertion of the PWRGOOD signal will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 us of the assertion of PWRGOOD Thermtrip should not be sampled until 10 us after PWRGOOD assertion at the processor TMS TMS Test Mode Select is a JTAG specification support signal used by debug tools TRDY TRDY Target Ready is asserted by the target chipset to indicate that it is ready t
98. der IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting For more information on designing a component level thermal solution refer to the Dual Core Intel Xeon Processor 7100 Series Thermal Mechanical Design Guidelines The boxed processor will ship with a component thermal solution Refer to Section 8 for details on the boxed processor Thermal Specifications To allow the optimal operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature Tcase specifications as defined by the applicable thermal profile see Table 6 1 and Figure 6 10r Figure 6 2 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the appropriate processor thermal mechanical design guidelines The Dual Core Intel Xeon processor 7100 series uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and assure processor reliability Selection of the appropriate fan speed will be based on the temperature reported by the processor s Thermal Diode If the diode temperature is greater than or equal to Tcontrol see Section 6 2 7 then the processor case temperature must remain at or below the temperature as specified by
99. des PREQ Probe Request functionality for the TAP port PREQ is a processor input and is used by debug tools to request debug operation of the processors BPM 5 4 must be bussed to all bus agents Please refer to the appropriate platform design guide for more detailed information BPRI BPRI Bus Priority Request is used to arbitrate for ownership of the processor front side bus It must connect the appropriate pins of all processor front side bus agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until its requests are issued then releases the bus by deasserting BPRI Dual Core Intel Xeon Processor 7100 Series Datasheet Signal Definitions intel Table 5 1 Signal Definitions Sheet 3 of 8 BRO Name BR 3 1 Type I O I Description BR 3 0 Bus Request drive the BREQ 3 0 signals in the system The BREQ 3 0 signals are interconnected in a rotating manner to individual processor pins The tables below give the rotating interconnect between the processor and bus signals for 3 load configurations BR 3 0 Signals Rotating Interconnect 3 Load Configuration Agent 0 Agent 1 Bus Signal Pins Pins BREQO BRO BR1 BREQ1 BR1 BRO BREQ2 BR2 BR3 BREQ3 BR3 BR2 During powe
100. e enhanced floating point and multi media unit and Streaming SIMD Extensions 2 SSE2 The Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor The Advanced Transfer Cache is a 2 MB total on die level 2 L2 cache organized as 1 MB dedicated per core The floating point and multi media units include 128 bit wide registers and a separate register for data movement SSE2 instructions provide highly efficient double precision floating point SIMD integer and memory management operations In addition Streaming SIMD Extensions 3 SSE3 instructions have been added to further extend the capabilities of Intel processor technology Other processor enhancements include core frequency improvements and microarchitectural improvements Dual Core Intel Xeon Processor 7100 Series Datasheet 11 intel The Dual Core Intel Xeon processor 7100 series processor supports Intel 64 as an enhancement to Intel s IA 32 architecture This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Further details can be found in the 64 bit Extension Technology Software Developer s Guide at http developer intel com technology 64bitextensions Table 1 1 12 Introduction Dual Core Intel Xeon processor 7100 series are intended for high performance multi processor server systems with support for up to two processors on a
101. e Dual Core Intel Xeon Processor 7100 Series Processor Number 7150 7140 7130 7120 and 7110 is a dual core product for multi processor servers The Dual Core Intel Xeon processor 7100 series is a 64 bit server processor utilizing two physical Intel NetBurst microarchitecture cores in one package It maintains the tradition of compatibility with IA 32 software and includes features found in the Intel Xeon processor such as Hyper Pipelined Technology a Rapid Execution Engine and an Execution Trace Cache Hyper Pipelined Technology includes a multi stage pipeline allowing the processor to reach much higher core frequencies The 667 MTS Mega Transfer per Seconds front side bus is a quad pumped bus running off a 166 MHz system clock making 5 3 GB per second data transfer rates possible The 800 MTS front side bus FSB is a quad pumped bus running off a 200 MHz system clock making 6 4 GB per second data transfer rates possible The Execution Trace Cache is a level 1 L1 cache that stores decoded micro operations which removes the decoder from the main execution path thereby increasing performance In addition the Dual Core Intel Xeon processor 7100 series includes the Intel Extended Memory 64 Technology providing additional address capability In addition enhanced thermal and power management capabilities are implemented including Thermal Monitor Thermal Monitor 2 TM2 and Enhanced Intel SpeedStep technology Thermal Monitor and
102. e proper noise margin and signal integrity Ru is not configurable and is always enabled for these signals See Table 2 7 for a list of these signals Figure 2 1 illustrates the active on die termination Dual Core Intel Xeon Processor 7100 Series Datasheet 17 e n tel Electrical Specifications Figure 2 1 Note 2 1 1 Table 2 1 18 On Die Front Side Bus Termination End Agent Middle Agent Ko Ra z Signal Signal R R On die termination resistors for AGTL signals R Additional on die resistance implemented for proper noise margin and signal integrity wired OR signals only Some AGTL signals do not include on die termination R and must be terminated on the motherboard See Table 2 7 for details regarding these signals Front Side Bus Clock and Processor Clocking BCLK 1 0 directly controls the front side bus interface speed as well as the core frequency of the processor The Dual Core Intel Xeon Processor 7100 Series processor core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier will be set at its default ratio during manufacturing The default setting generates the maximum speed for the processor It is possible to override this setting using software Refer to the Cedar Mill Processor Family BIOS Writer s Guide for details This will permit operation at a speed lower than the processor s tested frequency The processor core freq
103. eaving the pins floating to achieve the Hi Z state If the system designer wants to drive the SM_TS_A 1 0 pins with logic the designer must still ensure that the pins are at valid input levels prior to or while the SM_VCC supply ramps up The system designer must also ensure that their particular implementation does not add excessive capacitance to the address inputs Excess capacitance at the address inputs may cause address recognition problems Refer to the appropriate platform design guide document Figure 7 2 shows a logical diagram of the pin connections Table 7 2 and Table 7 3 describe the address pin connections and how they affect the addressing of the devices Thermal Sensor SMBus Addressing Eoo Peces Device Select 8 bit Address Word on Serial Bus SM TS A1 SM TS AO b 7 0 3Xh 0011 0 0 0011000Xb 0 z2 0011001Xb 0 1 0011010Xb 5Xh 0101 z2 0 0101001Xb z2 z2 0101010Xb z2 1 0101011Xb 9Xh 1001 1 0 1001100Xb 1 z2 1001101Xb 1 1 1001110Xb Notes 1 Upper address bits are decoded in conjunction with the device select pins 2 Atri state or Z state on this pin is achieved by leaving this pin unconnected System management software must be aware of the processor dependent addresses for the thermal sensor Memory Device SMBus Addressing UN ex Paie Device Select R W SM EP A2 SM EP A1 SM EP AO bits 7 4 bit 3 bit 2 bit 1 bit 0 AOh Ath 1010 0 0 0 X A2h A3h 1
104. eceive the latest revisions of these documents This collateral is available publicly at http developer intel com This document is available at http www formfactors org This document is available at http www ssiforum org This document is available at http www smbus org 1 3 State of Data The data contained within this document is subject to change It is the most accurate information available by the publication date of this document For processor stepping info refer to the Dual Core Intel Xeon Processor 7100 Series Specification Update 8 Dual Core Intel Xeon Processor 7100 Series Datasheet 15 16 Introduction Dual Core Intel Xeon Processor 7100 Series Datasheet n Electrical Specifications n tel 2 2 1 Electrical Specifications Front Side Bus and GTLREF Most Dual Core Intel Xeon Processor 7100 Series processor front side bus FSB signals use Assisted Gunning Transceiver Logic AGTL signaling technology This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates AGTL buffers are open drain and require pull up resistors to provide the high logic level and termination AGTL output buffers differ from GTL buffers with the addition of an active pMOS pull up transistor to assist the pull up resistors during the first clock of a low to high voltage transition Platforms implement a termination voltage level for AGTL signa
105. ecognize the proper signal state except during power on configuration See Table 2 21 for the DC specifications for the GTL asynchronous and AGTL asynchronous signal groups Dual Core Intel Xeon Processor 7100 Series Datasheet n Electrical Specifications n tel 2 8 2 9 Table 2 9 Test Access Port TAP Connection Due to the voltage levels supported by other components in the TAP logic Intel recommends that the Dual Core Intel Xeon Processor 7100 Series processor s be first in the TAP chain followed by any other components within the system Use of a translation buffer to connect to the rest of the chain is recommended unless one of the other components is capable of accepting an input of the appropriate voltage Similar considerations must be made for TCK TMS TRST TDI and TDO Two copies of each signal may be required each driving a different voltage level Maximum Ratings Table 2 9 specifies absolute maximum and minimum ratings Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional
106. ed to either the topside or pin side of the package substrate See Figure 3 2 and Figure 3 3 for keepout zones Package Loading Specifications Table 3 1 provides dynamic and static load specifications for the processor package These mechanical load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal and mechanical solutions The minimum loading specification must be maintained by any thermal and mechanical solution Processor Loading Specifications Parameter Minimum Maximum Unit Notes Static Compressive 44 222 N 1 2 3 4 Load 10 50 bf 44 288 N 1 2 3 5 10 65 bf Dynamic 222 N 0 45 kg 100 G N 1 3 4 6 7 Compressive Load 50 Ibf static 1 Ibm 100 G bf 288 N 0 45 kg 100 G N 1 3 5 6 7 65 Ibf static 1 Ibm 100 G bf Transient 445 N 1 3 8 100 bf Notes 1 These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface 3 These parameters are based on limited testing for design characterization Loading limits are for the package only and do
107. el Xeon Processor 7100 Series Datasheet Features 7 4 intel performance and power requirements of the processor and system Note that the front side bus is not altered only the internal core frequency is changed In order to run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep technology e Voltage frequency selection is software controlled by writing to processor MSR s Model Specific Registers thus eliminating chipset dependency If the target frequency is higher than the current frequency Vcc is incremented in steps 12 5 mV by placing a new value on the VID signals and the processor shifts to the new frequency Note that the top frequency for the processor can not be exceeded If the target frequency is lower than the current frequency the processor shifts to the new frequency and Vcc is then decremented in steps 12 5 mV by changing the target VID through the VID signals Refer to the Cedar Mill Processor Family BIOS Writer s Guide for specific information to enable and configure Enhanced Intel SpeedStep technology in BIOS System Management Bus SMBus Interface The Dual Core Intel Xeon processor 7100 series package includes an SMBus interface which allows access to a memory component with two sections referred to as the Processor Information ROM and the Scratch EEPROM and a thermal sensor on the substrate The SM
108. emperature The TCC reduces processor power consumption as needed by modulating starting and stopping the internal processor core clocks The Thermal Monitor or Thermal Monitor 2 must be enabled for the processor to be operating within specifications The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 50 Clocks will not be off for more than 3 microseconds when the TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases Dual Core Intel Xeon Processor 7100 Series Datasheet 77 e n tel Thermal Specifications 6 2 2 78 With a thermal solution designed to meet the thermal profile it i
109. en the processor is in Stop Grant state PBE is asserted if there is any pending interrupt latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear still cause assertion of PBE Assertion of PBE indicates to system logic that it should return the processor to the Normal state Enhanced HALT Snoop State or HALT Snoop State Stop Grant Snoop State The Enhanced HALT Snoop state is used in conjunction with the Enhanced HALT state If Enhanced HALT state is not enabled in the BIOS the default Snoop state entered will be the HALT Snoop state Refer to the sections below for details on HALT Snoop state Grant Snoop state and Enhanced HALT Snoop state HALT Snoop State Stop Grant Snoop State The processor responds to snoop or interrupt transactions on the front side bus while in Stop Grant state or in HALT Power Down state During a snoop or interrupt transaction the processor enters the HALT Grant Snoop state The processor stays in this state until the snoop on the front side bus has been serviced whether by the processor or another agent on the front side bus or the interrupt has been latched After the snoop is serviced or the interrupt is latched the processor will return to the Stop Grant state or HALT Power Down state as appropriate Enhanced HALT Snoop State The Enhanced HALT Snoop state is the default Snoop state when the Enhanced HALT state is enabled via the BIOS The processor remains in
110. er on reset Power On Configuration Option Pins Configuration Option Pint Output tri state SMI or A 39 for Arb ID 3 middle agent A 36 for Arb ID 0 end agent Execute BIST Built In Self Test INIT or A 3 In Order Queue de pipelining set IOQ depth to 1 A 7 Disable MCERR observation A 9 Disable BINIT observation A 10 APIC cluster ID A 12 11 Disable bus parking A 15 Core Frequency to Front Side Bus Multiplier A 21 16 Symmetric agent arbitration ID BR 1 0 Disable Hyper Threading Technology HT Technology A 31 Note 1 Asserting this signal during RESET selects the corresponding option 2 Address pins not identified in this table as configuration options should not be asserted during RESET Clock Control and Low Power States The processor allows the use of HALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 7 1 for a visual representation of the processor low power states The Dual Core Intel Xeon processor 7100 series adds support for Enhanced HALT power down state Refer to Figure 7 1 and the following sections For more configuration details also refer to the Cedar Mill Processor Family BIOS Writer s Guide The Stop Grant state requires chipset and BIOS support on multiprocessor systems In a multiprocessor system all the STPCLK signals
111. ere the sign is always positive sign 0 and is shown in Table 7 14 The values shown are also used to program the Thermal Limit Registers The values of these registers should be treated as saturating values Values above 127 are represented at 127 decimal and values of zero and below may be represented as 0 to 127 decimal If the device returns a value where the sign bit is set 1 and the data is 000 0000 through 111 1110 the temperature should be interpreted as 0 Celsius Thermal Value Register Encoding Temperature Register Value C binary 127 0111 1111 126 0 111 1110 100 0 110 0100 50 0 011 0010 25 0 001 1001 1 0 000 0001 0 0 000 0000 Thermal Limit Registers The SMBus thermal sensor has high and low Thermal Limit Registers for each channel These registers allow the user to define high and low limits for the processor core thermal diode readings The encoding for these registers is the same as for the thermal reference registers shown in Table 7 14 If either processor thermal diode reading equals or exceeds one of these limits then the alarm bit RIHIGH R1LOW R2HIGH or R2LOW in the Thermal Sensor Status Register is triggered Status Registers The Status Registers shown in Table 7 15 and Table 7 16 indicates which if any thermal value thresholds for the processor core thermal diode have been exceeded It also indicates whether a conversion is in progress or an open circu
112. esa Va WE EEUU UE nda RUIN EE 15 2 Electrical Specificatioris oie isse kk ge ARR RR ER kk SEA EENEG AER 17 24 Front Side Bus and GTLREE e eeises su axe eoru gg kann maya b ra dy nes ark daka a ale A ra dad EES 17 2 1 1 Front Side Bus Clock and Processor Clocking esee 18 2 1 2 Front Side Bus Clock Select BGL OI 19 2 1 3 Phase Lock Loop PLL Power and Filter 20 2 2 Voltage Identification VID sa css n sus ala cl terne cu sese xama ene zara kak pa raices na kan as WEKA 21 2 3 Cache Voltage Identification CID 22 2 4 Reserved Unused and TESTHI Pins 23 2 5 rel Wl Le TEE 24 2 6 Front Side BuS Sigial GOUDS iiec eset tik kan ian d n SEN W n REESEN n es H n taa ur ern Ne 24 2 7 GTL Asynchronous and AGTL Asynchronous SGionals esee 26 2 8 Test Access Port TAP Connection acis dken ka nine NENNEN NENNEN SR nk b ka aa n Wa ba ka Wan RA nad 27 2 9 Maximum Rang ene egegegegeege gegen Eh ENEE NR SAS dE e a ia aya ENER ENER SANS na ay n GIR EA e AN 27 2 10 Processor DC Specifications 2 testes kalil kya b n nakan hak k na a OASE nan a EE DAS n sa d aa ek a 28 2 10 1 Flexible Motherboard FMB Guidelines kk kk kk kk kk kk kk kk ka 28 2 10 2 VCC Overshoot Specification eissis a kas ya ki kh lle kla kan ba A san cak wada alay k i 34 2 10 3 VCACHE Overshoot Specification s5 si asc sarslaskalenn kl kak eee eee si nennen 35 2 10
113. escription for details on parity checking of these signals RESET RS 2 0 RSP Asserting the RESET signal resets all processors to known states and invalidates their internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least 1 ms after Vcc and BCLK have reached their specified levels On observing active RESET all front side bus agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10 ms A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in Section 7 1 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect to the appropriate pins of all processor front side bus agents RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins of all processor front side bus agents A correct parity signal is electrically high if an even number of covered signals are electrically low and electrically low if an odd number of covered signals are electrically low If RS 2 0 are all electrically high RSP is also electrically high since this indicates it is not being dr
114. esses broadcast across the SMBus the memory component claims those of the form 1010XXXZb The XXX bits are defined by pull up and pull down resistors on the system baseboard These address pins are pulled down weakly 10 kQ on the processor substrate to ensure that the memory components are in a known state in systems which do not support the SMBus or only support a partial implementation The Z bit is the read write bit for the serial bus transaction The thermal sensor internally decodes one of three upper address patterns from the bus of the form 0011XXXZb 1001XXXZb or 0101XXXZb The device s addressing as implemented uses the SM TS A 1 0 pins in either the HI LO or Hi Z state Therefore the thermal sensor supports nine unique addresses To set either pin for the Hi Z state the pin must be left floating As before the Z bit is the read write bit for the serial transaction Note that addresses of the form 0000XXXXb are Reserved and should not be generated by an SMBus master The thermal sensor samples and latches the SM TS A 1 0 signals at power up System designers should ensure that these signals are at valid Vu Vr or floating input levels prior to or while the thermal sensor s SM VCC supply powers up This should be done by pulling the pins to SM VCC or Vss Dual Core Intel Xeon Processor 7100 Series Datasheet Features Table 7 2 Note Table 7 3 intel via a 1 kQ or smaller resistor or l
115. fication refers to a single processor with Rrr disabled 17 The voltage specification requirements are measured across the Vec cacHe SENSE and Vss cache sense Pins at the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the scope probe 18 This specification represents the Vcc reduction due to each VID transition See Section 2 2 19 This specification refers to the total reduction of the load line due to VID transitions below the specified VID 20 Icc tpc is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion Please see the applicable design guidelines for further details The processor is capable of drawing Icc tpc indefinitely Refer to Figure 2 3 for further details on the average processor current draw over various time durations This parameter is based on design characterization and is not tested 21 Icacug toc is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature assessment The voltage regulator is respon
116. ge temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no pins can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 4 This rating applies to the processor and does not include any packaging or trays Dual Core Intel Xeon Processor 7100 Series Datasheet 27 e n tel Electrical Specifications 2 10 Processor DC Specifications The following notes apply e The processor DC specifications in this section are defined at the processor core silicon and not at the package pins unless noted otherwise e The notes associated with each parameter are part of the specification for that parameter e Unless otherwise noted all specifications in the tables apply to all frequencies and cache sizes e Unless otherwise noted all the specifications in the tables are based on estimates and simulations These specifications will be updated with characterized data from silicon measurements at a later date See Section 5 for the pin signal definitions Most of the signals on the processor front side bus are in the AGTL signal group The DC specifications for these signals are listed in Table 2 19 Table 2 10 through Table 2 22 list the DC specifications for t
117. he Data 3ih Package Data 37h Part Number Data 6Fh Thermal Ref Data 73h Feature Data 7Fh Dual Core Intel Xeon Processor 7100 Series Datasheet 109 intel TN 7 4 5 7 4 6 110 Checksums are automatically calculated and programmed by Intel The first step in calculating the checksum is to add each byte from the field to the next subsequent byte This result is then negated to provide the checksum Example For a byte string of AA445Ch the resulting checksum will be B6h AA 10101010 44 01000100 5C 0101100 AA 44 5C 01001010 Negate the sum 10110101 1 101101 B6h Scratch EEPROM Also available in the memory component on the processor SMBus is an EEPROM which may be used for other data at the system or processor vendor s discretion The data in this EEPROM once programmed can be write protected by asserting the active high SM WP signal This signal has a weak pull down 10 k9 to allow the EEPROM to be programmed in systems with no implementation of this signal The Scratch EEPROM resides in the upper half of the memory component addresses 80 FFh The lower half comprises the Processor Information ROM addresses 00 7Fh which is permanently write protected by Intel SMBus Thermal Sensor The processor s SMBus thermal sensor provides a means of acquiring thermal data from the processor s two thermal diodes The thermal sensor is composed of control logic SMBus interface logic a precision ana
118. he Deferred Phase The Dual Core Intel Xeon processor 7100 series uses a scalable system bus protocol referred to as the front side bus in this document The front side bus utilizes a split transaction deferred reply and Deferred Phase protocol The front side bus uses Source Synchronous Transfer SST of address and data to improve performance The processor transfers data four times per bus clock 4X data transfer rate Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked double pumped or the 2X address bus In addition the Request Phase completes in one clock cycle Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 5 3 GB 667 MTS or 6 4 GB 800 MTS per second Finally the front side bus is also used to deliver interrupts The Dual Core Intel Xeon processor 7100 series supports a threshold based mechanism for enhanced cache error reporting IA32_MCG_CAP 11 1 Intel recommends that fault prediction handlers rely on this mechanism to assess processor cache health Please refer to the IA 32 Intel Architecture Software Developer s Manual Volume 3A for more detailed information Please note that the Dual Core Intel Xeon processor 7100 series does not support the newly added overwrite rules Dual Core Intel Xeon Processor 7100 Series Datasheet Introduction 1 1 intel Terminology A symbol after
119. he Dual Core Intel Xeon Processor 7100 Series processor and are valid only while meeting specifications for case temperature clock frequency and input voltages 2 10 1 Flexible Motherboard FMB Guidelines The FMB guidelines are estimates of the maximum values that the Dual Core Intel Xeon processor 7100 series processor will have over certain time periods The values are only estimates as actual specifications for future processors may differ The Dual Core Intel Xeon processor 7100 series may or may not have specifications equal to the FMB value in the foreseeable future System designers should meet the FMB values to ensure that their systems will be compatible with future releases of the Dual Core Intel Xeon processor 7100 series Table 2 10 Voltage and Current Specifications Sheet 1 of 2 Core Symbol Parameter Freq Min Typ Max VID Unit Notes VID Range Vcc for processor core All freq Refer to Table 2 11 1 1000 V 1 2 3 1 3500 4 5 7 VID Transition VID step size during All freq t12 5 mV 18 transition Total allowable DC load line All freq 450 mV 19 shift from VID steps CVID Range Vcc for processor L3 cache All freq Refer to Table 2 12 or Table 2 13 1 1000 V 17 1 3500 Vir FSB termination voltage All freq 1 176 1 20 1 224 V 11 12 DC specification 13 Vr FSB termination voltage All freq 1 140 1 20 1 260 V 11 12 AC specification 13 14 SM VCC SMBus supply voltage All freq 3 135 3 300 3 465 V 13 Icc Icc for processor core Al
120. ical processor is halted however the other processor continues normal operation The processor transitions to the Normal state upon the occurrence of SMI BINIT INIT LINT 1 0 NMI INTR or an interrupt delivered over the front side bus RESET causes the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state See the JA 32 Intel Architecture Software Developer s Manual Volume III System Programming Guide for more information The system can generate a STPCLK while the processor is in the HALT Power Down state When the system deasserts the STPCLK interrupt the processor returns execution to the HALT state While in HALT Power Down state the processor processes bus snoops and interrupts Enhanced HALT Power Down State Enhanced HALT state is a low power state entered when all logical processors have executed the HALT or MWAIT instructions and Enhanced HALT state has been enabled via the BIOS When one of the logical processors executes the HALT instruction that logical processor is halted however the other processor continues normal operation The Enhanced HALT state is generally a lower power state than the Stop Grant state The processor automatically transitions to a lower core frequency and voltage operating point before entering the Enhanced HALT state Note that the processor FSB frequency is not altered only the i
121. ide markings on the processor These diagrams are to aid in the identification of the Dual Core Intel Xeon processor 7100 series 46 Dual Core Intel Xeon Processor 7100 Series Datasheet Mechanical Specifications Figure 3 4 Processor Topside Markings 2D Matrix Processor Name is Pin 1 Indicator Includes ATPO and Serial s Number front end mark i m 05 Notes 1 All characters will be in upper case 2 Drawing is not to scale Figure 3 5 Processor Bottom Side Markings Pin 1 Indicator Processor Speed Cache Bus Number Pin Field 7140M 3400 16M 800 FPO Serial d 13 Characters SL9HA COSTA RICA A S Spec C0096109 0021 Country of Assy Dual Core Intel Xeon Processor 7100 Series Datasheet 47 n tel Mechanical Specifications 3 9 Processor Pin Out Coordinates Figure 3 6 shows the top view of the processor pin coordinates The coordinates are referred to throughout the document to identify processor pins Figure 3 6 Processor Pin Out Coordinates Top View COMMON ADDRESS COMMON Async CLOCK CLOCK JTAG 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 81 Alo e O OO0e609001A Bo e Q O O0 O O O OJ B clo 9 e eoooeo9o c Dlo O O O O O O e D Ele O O O O e o e E Fle e o e O O e o _ e O O OF Ge e e e oe O 0 e e e e G He e e e ee 6 e o e o e o e OH n Jeoeo eo e e e e e e lJ gt Keeee ee 6 e
122. ie revision code may change and should not be used for identification All of the commands in Table 7 13 are for reading or writing registers in the SMBus thermal sensor except the one shot register OFh The one shot command forces the immediate start of a new conversion cycle If a conversion is in progress when the one shot command is received then the command is ignored If the thermal sensor is in stand by mode when the one shot command is received a conversion is performed and the sensor returns to stand by mode The one shot command is not supported when the thermal sensor is in auto convert mode Note Writing to a read command register or reading from a write command register will produce invalid results 112 Dual Core Intel Xeon Processor 7100 Series Datasheet Features 7 4 8 7 4 8 1 Table 7 14 7 4 8 2 7 4 8 3 intel The default command after reset is to a reserved value 00h After reset Receive Byte SMBus packets will return invalid data until another command is sent to the thermal sensor SMBus Thermal Sensor Registers Thermal Value Registers Once the SMBus thermal sensor reads a processor thermal diode it performs an analog to digital conversion and stores the data in a temperature value register The supported range is 127 to 0 decimal and is expressed as an eight bit number representing temperature in degrees Celsius This eight bit value consists of seven bits of data and a sign bit MSB wh
123. ing data on the processor front side bus to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor front side bus agents DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or I O agent This signal must connect the appropriate pins of all processor front side bus agents Dual Core Intel Xeon Processor 7100 Series Datasheet 67 intel Signal Definitions Table 5 1 Signal Definitions Sheet 4 of 8 Name DEP 7 0 Type I O Description The DEP 7 0 data bus ECC protection signals provide optional ECC protection for the data bus They are driven by the agent responsible for driving D 63 0 and if ECC is implemented must connect the appropriate pins of all bus agents which use them Furthermore the DBI pins determine the polarity of the ECC signals Each pair of 2 ECC signals corresponds to one DBI signal When the DBI signal is active the corresponding ECC pair is inverted and therefore sampled active high DP 3 0 I O DP 3 0 Data Parity provide optional parity protection for the data bus They are driven by the agent responsible for driving D 63 0 and if parity is implemented must connect the appropriate pins of all bus agents which use them DRDY I O
124. ircuits must be taken from processor Vcc and Vss pins Refer to the Vcc Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 2 Design Guidelines for socket load line guidelines and VR implementation Dual Core Intel Xeon Processor 7100 Series Datasheet 31 intel Electrical Specifications Figure 2 4 Vcc Static and Transient Tolerance 32 lcc A 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 VID 0 000 Voc Maximum VID 0 050 VID 0 100 9 o gt VID 0 150 Voc Typical VID 0 200 Voc Mnimum VID 0 250 Notes 1 The Vcc min and Vcc max load lines represent static and transient limits 2 Refer to Table 2 10 for processor VID information for Vcc 3 The load lines specify voltage limits at the die measured at the Vccsense and Vsssense pins Voltage regulation feedback for voltage regulator circuits must be taken from processor Vcc and Vss pins Refer to the Vcc Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 2 Design Guidelines for socket load line guidelines and VR implementation Dual Core Intel Xeon Processor 7100 Series Datasheet n Electrical Specifications n tel Table 2 12 VcAcge Static and Transient Tolerance at the Die Sense Location rone A Vormm VI Vorner lV Tess asf Notes 0 cw 0 000 cvi o0a1 cvi o082 12 Notes 1 Icacne refers to the current drawn by
125. is a two wire communications bus protocol developed by Philips SMBus is a subset of the IC bus protocol and was developed by Intel Implementations of the I2C bus protocol may require licenses from various entities including Philips Electronics N V and North American Philips Corporation Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Processors will not operate including 32 bit operation without an Intel amp 64 architecture enabled BIOS Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information Intel Pentium Intel Xeon Intel NetBurst Enhanced Intel SpeedStep Technology Intel 64 and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2006 Intel Corporation 2 Dual Core Intel Xeon Processor 7100 Series Datasheet Contents 1 ZtrodO les b mm 11 1 1 Terminology EE 13 1 2 AREPERENCES 4 gg e dece bend EE de guai quta dades Dee ran pne dela RN EORR Den 14 1 3 State of Data sk sami Kinn eege he iki bah xs dinda nana b n de arde Xa r
126. is reserved Writes to this register have no effect Offset 71h 72h Bit Description 15 0 RESERVED 9 TRDCKS Thermal Reference Data Checksum This location provides the checksum of the Thermal Reference Data Section Writes to this register have no effect Offset 73h Bit Description 7 0 Thermal Reference Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Feature Data This section provides information on key features that the platform may need to understand without powering on the processor PCFF Processor Core Feature Flags This location contains a copy of results in EDX 31 0 from Function 1 of the CPUID instruction These details provide instruction and feature support by product family A decode of these bits is found in the Cedar Mill Processor Family BIOS Writers Guide or the AP 485 Intel Processor Identification and CPUID Instruction application note Writes to this register have no effect Offset 74h 77h Bit Description 31 0 Processor Core Feature Flags 0000h FFFFF Feature Flags PFF Processor Feature Flags This location contains additional feature information from the processor Writes to this register have no effect Bit 5 and Bit 6 are mutually exclusive only one bit will be set Offset 78h Bit Description 7 Multi Core set if the process
127. it has been detected in either processor core thermal diode connection Once set alarm bits stay set until they are cleared by a Status Register read A successful read to the Status Register will clear any alarm bits that may have been set unless the alarm condition persists If the SM ALERTZ signal is enabled via the Thermal Sensor Configuration Register and a thermal diode threshold is exceeded an alert will be sent to the platform via the SM ALERT signal Dual Core Intel Xeon Processor 7100 Series Datasheet 113 intel Features Table 7 15 SMBus Thermal Sensor Status Register 1 Bit Name Reset State Function 7 MSB BUSY N A If set indicates that the device s analog to digital converter is busy 6 RESERVED RESERVED Reserved for future use 5 RESERVED RESERVED Reserved for future use 4 R1HIGH 0 If set indicates the processor core 1 thermal diode high temperature alarm has activated 3 RiLOW 0 If set indicates the processor core 1 thermal diode low temperature alarm has activated 2 R1OPEN 0 If set indicates an open fault in the connection to the processor core 1 diode 1 RESERVED RESERVED Reserved for future use 0 LSB RESERVED RESERVED Reserved for future use Table 7 16 SMBus Thermal Sensor Status Register 2 7 4 8 4 Bit Name Reset State Function 7 MSB RESERVED RESERVED Reserved for future use 6 RESERVED RESERVED Reserved for future use
128. iven by any agent guaranteeing correct parity SKTOCC SKTOCC Socket occupied will be pulled to ground by the processor to indicate that the processor is present There is no connection to the processor silicon for this signal SM_ALERT SM_ALERT SMBus Alert is an asynchronous interrupt line associated with the SMBus Thermal Sensor device It is an open drain output and the processor includes a 10kQ pull up resistor to SM VCC for this signal For more information on the usage of the SM ALERT pin see Section 7 4 9 SM CLK I O The SM CLK SMBus Clock signal is an input clock to the system management logic which is required for operation of the system management features of the Dual Core Intel Xeon processor 7100 series This clock is driven by the SMBus controller and is asynchronous to other clocks in the processor The processor includes a 10 kQ pull up resistor to SM VCC for this signal SM DAT I O The SM DAT SMBus Data signal is the data signal for the SMBus This signal provides the single bit mechanism for transferring data between SMBus devices The processor includes a 10 kQ pull up resistor to SM VCC for this signal SM EP A 2 0 The SM EP A EEPROM Select Address pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple processors To set an SM EP A line high a pull up resistor should be used that
129. l NOIIVHOdNO2 131N 4O IN3SNOD N3LLIUM YOIMd JHL LRONLIM C35010 10 38 LON AVW SIN31NO2 SLI ANY 30301302 NI 035019510 1 11 NOLLYHYOIN nne NOIlYMOZHOD 131N SNIVINOO ONIAVHG SIMI Eug 26281V on onal 9 L E c 121 Dual Core Intel Xeon Processor 7100 Series Datasheet 3 30 Y 13i Boxed Processor Specifications v3uv SIHI NI 4JOQNVIS SISSVHO YO S310H ONILNNOW Quvog ON 30N343434 YO4 NMOHS S310H ONILNNOW YOSS3I0Ud AINO 39038343 04 NMOHS 3NI110O QUVON araf ION 402 ENN Nu3llVd 3 10H 40 Y3LN39 WOUi Nu3llVd 310H 402 00 21 0617 S 9 y 90 6 NOILYYOdYOD TILNI dO 1N3 N09 NILLIYM NOlNUd FHL LMOHLIM 13 3 Q0M NO 31V14S10 0390004438 3S010810 38 LON AVN SIN3INO2 SLI ONY 39N3014N09 NI 38019810 SI LI NOLLYMYOIN 1V11N30 JNO NOIlVHOdHOD 131N1 SNIVINOD 9NIAYHO STHL ST al se ETT ES n y E 9 L 9 Board Mounting Hole Keep Out Zones intel Figure 8 5 Dual Core Intel Xeon Processor 7100 Series Datasheet 122 Boxed Processor Specifications n tel Figure 8 6 Thermal Solution Volumetric cea e mm cel nee vu be 2 z F E S i EI m m 3 E g N 2 SS E ER Br 8 ERZ
130. l Monitor 2 O N AJ OY Oa N Enhanced Intel Speed Step Technology Bits are set when a feature is present and cleared when they are not 108 Dual Core Intel Xeon Processor 7100 Series Datasheet Features 7 4 3 8 5 7 4 3 9 7 4 3 9 1 7 4 3 9 2 7 4 4 Table 7 7 intel TAF Thermal Adjustment Factors This location contains information on thermal adjustment factors for the processor This field and it s details are pending and will be updated in a future revision Writes to this register have no effect Offset 7Bh 7Ch Bit Description 15 8 Measurement Correction Factor 7 0 Temperature Target Other Data RES10 Reserved 10 These locations are reserved Writes to this register have no effect Offset 7Dh 7Eh Bit Description 15 0 RESERVED FDCKS Feature Data Checksum This location provides the checksum of the Feature Data Section Writes to this register have no effect Offset 7Fh Bit Description 7 0 Feature Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Checksums The PIROM includes multiple checksums Table 7 7 includes the checksum values for each section defined in the 128 byte ROM 128 Byte ROM Checksum Values Section Checksum Address Header ODh Processor Data 15h Processor Core Data 24h Cac
131. l freq 135 A 7 10 Icc TDC Core Thermal Design All freq 115 A 20 H Current TDC IcACHE Icc for processor L3 cache All freq 40 A 28 Dual Core Intel Xeon Processor 7100 Series Datasheet Electrical Specifications n tel Table 2 10 Voltage and Current Specifications Sheet 2 of 2 Symbol Parameter pude Min Typ Max VID Unit Notes IcAcHE TDC Cache Thermal Design All freq 35 A H Current TDC Ir FSB termination current All freq 4 A 11 15 In FSB mid agent current All freq 1 3 A 11 16 Ism_vec Icc for SMBus supply All freq 100 122 5 mA 11 IsGnt_CORE Icc Stop Grant Core All freq 70 A 6 9 IsGnt CACHE Icc Stop Grant Cache All freq 35 A 6 9 Itcc Icc TCC active All freq Icc A 8 Icc VCCA Icc for PLL pin All freq 60 mA Icc vccioPLL Icc for I O PLL pin All freq 60 mA Icc VCCA_CACHE Icc for L3 cache PLL pin All freq 60 mA Icc cri REF Icc per GTLREF pin All freq 200 HA Notes 1 These voltages and frequencies are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 2 and Table 2 4 for more information 2 The voltage specification requirements are measured across the Vccsense and Vsssense pins using an oscilloscope set to a 100 MHz bandwidth and probes that are 1 5 pF maximum capacitance and 1 MQ minimum impedance at the processor socket The maximum length of ground wire on the probe should be less tha
132. log to digital converter and a single bank of precision current sources The A D converter and the current source are muxed between the two sensor channels The sensor drives a small current through the p n junction for the thermal diodes located on the processor core The forward bias voltage generated across each thermal diode is sensed and the precision A D converter derives a byte of thermal reference data or a thermal byte reading The resolution of the least significant bit of a thermal byte is 1 Celsius The processor incorporates the SMBus thermal sensor onto the processor package Upper and lower thermal reference thresholds can be individually programmed for each channel of the SMBus thermal sensor Comparator circuits sample the register where the single byte of thermal data thermal byte reading is stored These circuits compare the single byte result against programmable threshold bytes If enabled the alert signal on the processor SMBus SM ALERT Z will be asserted when the sensor detects that either the high or low threshold is reached or crossed for each channel Analysis of SMBus thermal sensor data may be useful in detecting changes in the system environment that may require attention The processor SMBus thermal sensor may be used to monitor long term temperature trends but can not be used to manage the short term temperature of the processor or predict the activation of the thermal control circuit As mentioned earlier the
133. ls defined as Ver Because platforms implement separate power planes for each processor separate Vcc and Mr supplies are necessary This configuration allows for improved noise tolerance as processor frequency increases Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families Design guidelines for the processor front side bus are detailed in the appropriate platform design guides refer to Section 1 2 The AGTL inputs require a reference voltage GTLREF which is used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF must be generated on the motherboard see Table 2 23 for GTLREF specifications Please refer to the appropriate platform design guidelines for details Termination resistors Rrr for AGTL signals are provided on the processor silicon and are terminated to V7 The on die termination resistors are a selectable feature and can be enabled or disabled via the ODTEN signal For end bus agents on die termination resistors are enabled to control reflections on the transmission line For the middle bus agent on die termination Ry resistors must be disabled Intel chipsets will also provide on termination thus eliminating the need to terminate the bus on the motherboard for most AGTL signals Processor wired OR signals may also include additional on die resistors R to further ensur
134. lues 4i assis a sk lase a kaka kaka eee nena aa kk wa ajala kaca ae ad a a k 109 Write Byte SMBUS Packet issa nlkyimi ae lk kak kk kk ask ka lak k m kad ke aja kalak ae wa kan dk a kal ka ail a 111 Read Byte SMBUS Racket sis sana xain ki vb geed n bak n a an k n xeya EEN Ge coins 111 Send Byte SMBUS PaGKe ld x ssr dak asma nda ke lak naa kl kl b ka ke be diba ke b ra neku READER ERA KEES een 111 Receive Byte SMBUS P Ck t 4 xa H ld nan ni cake seen sna NEEN n a hak naa nanus pia RR aa da k n EN Na tel 111 ARA SMBUS PACK E 111 SMBus Thermal Sensor Command Byte Bit Assignments hk kK k kWK WkKk lkk kk kk kk 112 Thermal Value Register Encoding l kk kk kk kake nemen enemies 113 SMBus Thermal Sensor Status Register 1 sss 114 SMBus Thermal Sensor Status Register 2 114 SMBus Thermal Sensor Configuration Register 114 SMBus Thermal Sensor Conversion Rate Register 115 Dual Core Intel Xeon Processor 7100 Series Datasheet Revision History Document Number Revision Number Description Release Date 314553 001 e Initial Release August 2006 314553 002 e Added 3 5GHz at 667 ratio e Updated Processor Mixing September 2006 8 Dual Core Intel Xeon Processor 7100 Series Datasheet Dual Core Intel Xeon Processor 7100 Series Datasheet Features Available at
135. minal V of 1 2 V Dual Core Intel Xeon Processor 7100 Series Datasheet Electrical Specifications n tel Table 2 21 GTL Asynchronous and AGTL Asynchronous Signal Group DC Specifications Symbol Parameter Min Max Unit Notes VIL Input Low Voltage 0 GTLREF 10 Vr V 2 VIH Input High Voltage GTLREF 1096 Vr Vr V 3 4 VIL A20M SMI IGNNE 0 0 4 Vr V 2 Input Low Voltage VIH A20M SMI IGNNE 0 6 V5 Vit V 3 4 Input High Voltage VOH Output High Voltage Vit V 1 4 IoL Output Low Current 50 mA 5 ILI Input Leakage Current N A 200 HA 6 ILO Output Leakage Current 200 HA 7 Ron Buffer On Resistance 8 12 Q Notes 1 All outputs are open drain 2 Vy is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 3 Viu is defined as the voltage range at a receiving agent that will be interpreted as a logical high value 4 The Vy referred to in these specifications refers to instantaneous Ver Bi The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load Leakage to Vss with pin held at Var Leakage to Var with pin held at 300 mV DO Table 2 22 SMBus Signal Group DC Specifications Symbol Parameter Min Max Unit Notes 1 2 VIL Input Low Voltage 0 30 0 30 SM_VCC V Vin Input High Voltage 0 70 SM_VCC 3 465
136. n Processor 7100 Series Datasheet Pin Listing l n tel Table 4 1 Pin Listing by Pin Name Table 4 1 Pin Listing by Pin Name Sheet 9 of 16 Sheet 10 of 16 Pin Name Pin No MN Direction Pin Name Pin No uc WU Direction Vcc G24 Power Other Vcc P2 Power Other Vcc G26 Power Other Vcc P4 Power Other Vcc G28 Power Other Vec P6 Power Other Vcc G30 Power Other Vec P8 Power Other Vcc H23 Power Other Vcc P24 Power Other Vcc H25 Power Other Vcc P26 Power Other Vcc H27 Power Other Vcc P28 Power Other Vec H29 Power Other Vec P30 Power Other Vcc H31 Power Other Vcc R23 Power Other Vec J2 Power Other Vcc R25 Power Other Vcc J4 Power Other Vcc R27 Power Other Vcc J6 Power Other Vcc R29 Power Other Vec J8 Power Other Vec R31 Power Other Vcc J24 Power Other Vcc T2 Power Other Vcc J26 Power Other Vcc T4 Power Other Vec J28 Power Other Vcc T6 Power Other Vcc J30 Power Other Vcc T8 Power Other Vcc K23 Power Other Vcc T24 Power Other Vec K25 Power Other Vec T26 Power Other Vcc K27 Power Other Vcc T28 Power Other Vcc K29 Power Other Vcc T30 Power Other Vec K31 Power Other Vec U23 Power Other Vcc L2 Power Other Vcc U25 Power Other Vcc L4 Power Other Vcc U27 Power Other Vcc L6 Power Other Vcc U29 Power Other Vec L8 Power Other Vec U31 Power Other Vcc L24 Power Other Vcc V2 Power Other Vcc L26 Power Other Vcc V4 Power Other Vec L28 Power Other Vec V6
137. n 5 mm Ensure external noise from the system is not coupled into the scope probe 3 Refer to Table 2 11 for the minimum typical and maximum Vcc allowed for a given current The processor should not be subjected to any Vcc and Icc combination wherein Vec exceeds Vcc max for a given current 4 Moreover Vcc should never exceed the VID voltage Failure to adhere to this specification can shorten the processor lifetime 5 Vcc MIN and Vcc max are defined at the frequency s associated Icc max on the Vcc load line 6 The current specified is also for the HALT State 8 7 FMB is the Flexible Motherboard guideline These guidelines are for estimation purposes only See Section 2 10 1 for further details on FMB guidelines 8 The maximum instantaneous current the processor will draw while the thermal control circuit TCC is active as indicated by the assertion of PROCHOT is the same as the maximum Icc for the processor 9 The core and cache portions of Stop Grant current is specified at Vcc and VcAcugmax 10 Icc Max specification is based on Vcc Maximum loadline Refer to Figure 2 4 for details 11 These parameters are based on design characterization and are not tested 12 Ver must be provided via a separate voltage source and must not be connected to Vcc 13 These specifications are measured at the package pin 14 Baseboard bandwidth is limited to 20 MHz 15 This specification refers to a single processor with Ry enabled 16 This speci
138. nally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET IGNNE IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid a 6 clks before the I O write s response 68 Dual Core Intel Xeon Processor 7100 Series Datasheet Signal Definitions intel Table 5 1 Signal Definitions Sheet 5 of 8 Name INIT Type I Description INIT Initialization when asserted resets integer registers inside all processors without affecting their internal caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor front side bus agents If INIT is sampled active on the active to inactive transition of RESET then the processo
139. nation of reduced frequency and VID results in a decrease to the processor power consumption A processor enabled for Thermal Monitor 2 includes two operating points each consisting of a specific operating frequency and voltage The first operating point represents the normal operating condition for the processor Under this condition the core frequency to system bus multiplier utilized by the processor is that contained in the IA32 FLEX BRVID SEL MSR and the VID is that specified in Table 2 10 These parameters represent normal system operation The second point consists of both a lower operating frequency and voltage When the TCC is activated the processor automatically transitions to the new frequency This transition occurs very rapidly on the order of 5 microseconds During the frequency transition the processor is unable to service any bus requests and consequently all bus traffic is blocked Edge triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator The voltage regulator must support dynamic VID steps in order to support Thermal Monitor 2 During the voltage change it will be necessary to transition through multiple VID codes to reach the target operating voltage Each step will be one VID table entry see Table 2 10
140. nds to the lowest possible value of Tcontrol This point is associated with the Tcontrol value see Section 6 2 7 However because Tcontrol represents a diode temperature it is necessary to define the associated case temperature This is TcasE Max PcowrRoL BASE Please see Section 6 2 7 and the Dual Core Intel Xeon Processor 7100 Series Thermal Mechanical Design Guidelines for proper usage of the Tcontrol specification The case temperature is defined at the geometric top center of the processor IHS Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the TDP indicated in Table 6 1 The Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more details on this feature refer to Section 6 2 To ensure maximum flexibility for future requirements systems should be designed to the Flexible Motherboard FMB guidelines even if a processor with a lower thermal dissipation is currently planned Thermal Monitor or Thermal Monitor 2 feature must be enabled for the processor to remain within specification Dual Core Intel Xeon Processor 7100 Series Thermal Specifications Thermal Minimum Maximum QDF S Spec Design Power TCASE TCASE Notes Frequency W C C Grea
141. nes for complete details on the mPGA604 socket The package components shown in Figure 3 1 include the following 1 Integrated Heat Spreader IHS 2 Processor die 3 FC mPGA6 package 4 Pin side capacitors 5 Package pin Processor Package Assembly Sketch B 4 5 This drawing is not to scale and is for reference only The mPGA604 socket is not shown Dual Core Intel Xeon Processor 7100 Series Datasheet 41 intel Package Mechanical Drawing The package mechanical drawings are shown in Figure 3 2 and Figure 3 3 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include 42 1 2 3 4 5 Mechanical Specifications Package reference with tolerances total height length width etc IHS parallelism and tilt Pin dimensions Top side and back side component keep out dimensions Reference datums All drawing dimensions are in millimeters Dual Core Intel Xeon Processor 7100 Series Datasheet Mechanical Specifications n tel Figure 3 2 Processor Package Drawing Sheet 1 of 2
142. nt draw for two processors Refer to Table 2 10 and Table 2 12 for the minimum cache voltage specifications based on actual real time current draw Example For a Dual Core Intel Xeon processor 7100 series the minimum voltage is 0 802 V 1 100 V Min CVID 0 298 V Voltage Offset at maximum current Offset 2D 2Eh would contain 0322h 0802 decimal Offset 2Dh 2bh Bit Description 15 0 Minimum Cache Voltage 0000h 0321h Reserved 0322 0 802 V 0323h FFFFh Reserved RES4 Reserved 4 These locations are reserved Writes to this register have no effect Offset 2Fh 30h Bit Description 15 0 RESERVED 4 0000h FFFFh Reserved CDCKS Cache Data Checksum This location provides the checksum of the Cache Data Section Writes to this register have no effect Offset 31h Bit Description 7 0 Cache Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Package Data This section provides package revision information PREV Package Revision This location tracks the highest level package revision It is provided in ASCII format of four characters 8 bits x 4 characters 32 bits The package is documented as 1 0 2 0 etc If this only consumes three ASCII characters a leading space is provided in the data field Dual Core Intel Xeon Processor 7100 Series Datasheet 103 intel TN 7 4 3
143. nternal core frequency is changed When entering the low power state the processor first switches to the lower bus ratio and then transitions to the lower VID While in the Enhanced HALT state the processor processes bus snoops The processor exits the Enhanced HALT state when a break event occurs When the processor exits the Enhanced HALT state it first transitions the VID to the original value and then changes the bus ratio back to the original value Dual Core Intel Xeon Processor 7100 Series Datasheet Features Figure 7 1 7 2 3 intel Stop Clock State Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated Normal State gt Enhanced HALT or HALT State Normal i INIT BINIT INTR NMI SMI BCLK running rma execution __RESET FSB interrupts Snoops and interrupts allowed A Snoop Snoop STPCLK STPCLK Puert Event Asserted De asserted Occurs Serviced Y Enhanced HALT Snoop or HALT Snoop State BCLK running Service snoops to caches Y Y Stop Grant State Snoop Even Oats Stop Grant Snoop State BCLK running i BCLK running Snoops and interrupts allowed Snoop Event Serviced Service snoops to caches Stop Grant State When the STPCLK pin is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cy
144. o e o e o e OK 9 Leoeo eo e e e e e L s Q Mie eo e ee Processor EEEE E o6 M o 9 Ne e e e ee 0 0e 0 6e 0 6 O N ZS 5 Pleeee eo e o e o e o e o ejpP o o Reese ee Top View e o e o e o e o n gt le e ese eo e e e e e e e el ule e e e ee e e e e By vje e e e eo e e e e e e e e Oly wio e o e O O O e e e w Yle e e o eo O e OO eO ole O e ely AA e O O O O O e o o e olo o e o AA AB e e o O oe O O 0 e o o elo e AB ACloeoeo eo O 9 O O O OO O 9 AC AD lo e e O one O e o o OjO OO O AD AE ooo O O O O O O O 0 O AE 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 CLOCKS DATA O Signal VTT 9 VCC Reserved No Connect Ground VCache 8 48 Dual Core Intel Xeon Processor 7100 Series Datasheet Pin Listing 4 4 1 4 1 1 Pin Listing Dual Core Intel Xeon Processor 7100 Series Pin Assignments Section 2 6 contains the front side bus signal groups for the Dual Core Intel Xeon processor 7100 series see Table 2 6 This section provides a sorted pin list in Table 4 1 and Table 4 2 Table 4 1 is a listing of all processor pins ordered alphabetically by pin name Table 4 2 is a listing of all processor pins ordered by pin number Pin Listing by Pin Name Table 4 1 Pin Listing by Pin Name Sheet 1 of 16 Sheet 2 of 16 Table 4 1 Pin Listing by Pin Name Signal Buffer
145. o receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all front side bus agents TRST TRST Test Reset resets the Test Access Port TAP logic TRST must be driven electrically low during power on Reset Please refer to the eXtended Debug Port Debug Port Design Guide for Twin Castle Chipset Platforms or the eXtended Debug Port Debug Port Design Guide for MP Platforms for details VACHE Vcacue Provides power to the L3 cache on the Dual Core Intel Xeon processor 7100 series Vcc Vcc provides power to the core logic of the Dual Core Intel Xeon processor 7100 series Vcca Vcca provides isolated power for the analog portion of the internal PLL s Use a discrete RLC filter to provide clean power Refer to the appropriate platform design guide for complete implementation details Dual Core Intel Xeon Processor 7100 Series Datasheet 71 Table 5 1 72 intel Signal Definitions Signal Definitions Sheet 8 of 8 Name Vcc CACHE SENSE Vss CACHE SENSE Type O Description Vcc CACHE SENSE and Vss CACHE SENSE provide isolated low impedance connections to the processor cache voltage VcAcug and ground Vss They can be used to sense or measure voltage or ground near the silicon with little noise VccioPLL Vcc opkL Provides isolated power for digital portion of the internal PLL s Follow the guidelines for VccA and refer to the
146. on 15 0 Maximum Core VID 0000h 0545h Reserved 0546h 1 35 V 0548h FFFFh Reserved MINV Minimum Core Voltage This location contains the minimum Processor Core voltage This field rounded to the next thousandth is in mV and is reflected in hex The minimum Vcc reflected in this field is the minimum allowable voltage assuming the FMB maximum current draw Writes to this register have no effect The minimum core voltage value in offset 21 22h is a single value that assumes the FMB maximum current draw Refer to Table 2 10 and Table 2 11 for the minimum core voltage specifications based on actual real time current draw Dual Core Intel Xeon Processor 7100 Series Datasheet Features 7 4 3 3 8 7 4 3 3 9 7 4 3 4 7 4 3 4 1 intel Example For a Dual Core Intel Xeon processor 7100 series the minimum voltage is 0 991 V 1 100 V Min VID 0 209 V Voltage Offset at maximum current Offset 21 22h would contain O3DFh 0991 decimal Offset 21h 22h Bit Description 15 0 Minimum Core Voltage 0000h 03DEh Reserved O3DF 0 991 V 03EOh FFFFh Reserved TCASE Tcase Maximum This location provides the maximum Tcase for the processor The field reflects temperature in degrees Celsius in hex format This data can be found in the Table 6 1 The thermal specifications are specified at the case Integrated Heat Spreader IHS Writes to this register have no effect Offset 23h
147. on See Table 2 7 for details on AGTL signals that do not include on die termination Unused active high inputs should be connected through a resistor to ground Vss Unused outputs may be left unconnected However this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability For unused AGTL input or I O signals use pull up resistors of the same value as the on die termination resistors R77 See Table 2 15 Most TAP signals GTL asynchronous inputs and GTL asynchronous outputs do not include on die termination see Table 2 7 for those signals which do not have on die termination Inputs and used outputs must be terminated on the system board Unused outputs may be terminated on the system board or left connected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in the appropriate platform design guide and the appropriate debug port design guide Don t Care pins are pins on the processor package that are not connected to the processor die These pins can be connected on the motherboard in any way necessary for compatible motherboard designs to support other processor versions The
148. ont side bus frequency information Systems may need to read this offset to decide if all installed processors support the same front side bus speed Because the Intel NetBurst microarchitecture bus is described as a 4X data bus the frequency given in this field is currently 667 MHz or 800 MHz The data provided is the speed rounded to a whole number and reflected in hex Writes to this register have no effect Example The Dual Core Intel Xeon processor 7100 series supports a 667 or 800 MHz front side bus Therefore offset 1A 1Bh has a value of 029Bh or 0320h Offset 1Ah 1Bh Bit Description 15 0 Front Side Bus Speed 0000h 029Ah Reserved 029Bh 667 MHz 029Ch 031Fh Reserved 0320h 800 Mhz 0321h FFFFh Reserved MPSUP Multiprocessor Support This location contains 2 bits for representing the supported number of physical processors on the bus These two bits are MSB aligned where 00b equates to single processor operation 01b is a dual processor operation and 11b represents multi processor operation The Dual Core Intel Xeon processor 7100 series is an MP processor The remaining six bits in this field are reserved for the future use Writes to this register have no effect Example An MP processor will use COh at offset 1Ch Offset 1Ch Bit Description 7 6 Multiprocessor Support UP DP or MP indictor 00b UP 01b DP 10b Reserved 11b MP 5 0 RESERVED 000000b 111111b Reserve
149. operate only at or below the frequency marked on the package 2 Listed frequencies are not necessarily committed production frequencies 3 For valid core frequencies of the processor refer to the Dual Core Intel Xeon Processor 7100 Series Specification Update 4 As described in Section 1 1 H refers to a high logic level i e signal asserted and L refers to a low logic level i e signal deasserted 200 MHz Core Frequency to Front Side Bus Multiplier Configuration Core Frequency to Front Side Bus SNR T A214 A203 A19 A18 A17 A16 Multiplier 1 13 2 6 GHz H H L L H L 1 15 3 GHz H H L L L 1 16 3 20 GHz H L H H H H 1 17 3 40 GHz H L H H H L Notes 1 Individual processors operate only at or below the frequency marked on the package 2 Listed frequencies are not necessarily committed production frequencies 3 For valid core frequencies of the processor refer to the Dual Core Intel Xeon Processor 7100 Series Specification Update 4 As described in Section 1 1 H refers to a high logic level i e signal asserted and L refers to a low logic level i e signal deasserted The Dual Core Intel Xeon processor 7100 series uses a differential clocking implementation For more information on the Dual Core Intel Xeon processor 7100 series clocking refer to the appropriate clock driver design guidelines Front Side Bus Clock Select BSEL 1 0 The BSEL 1
150. or each processor frequency includes an unattached passive heatsink This solution is targeted at chassis which are 3U and above in height This section documents baseboard and platform requirements for the thermal solution supplied with the boxed Dual Core Intel Xeon processor 7100 series This section is particularly important to companies that design and manufacture baseboards chassis and complete systems Figure 8 1 shows the conceptual drawing of the boxed processor thermal solution Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designer s responsibility to consider their proprietary cooling solution when designing to the required keep out zone on their system platform and chassis Dual Core Intel Xeon Processor 7100 Series Datasheet 117 n n tel Boxed Processor Specifications Figure 8 1 8 2 8 2 1 118 Passive Dual Core Intel Xeon Processor 7100 Series Thermal Solution 3U and larger 4X HEAT SINK SCREW HEAT SINK 4X HEAT SINK SCREW SPRING T MAIN BOARD AND SOCKET CEK SPRING Note 1 The heatsink in this image is for reference only 2 This drawing shows the retention scheme for the boxed processor Mechanical Specifications This section documents the mechanical specifications of the boxed processor passive hea
151. or is a dual core processor 6 Serial signature set if there is a serial signature at offset 4D 54h 5 Electronic signature present set if there is a electronic signature at 4D 54h 4 Thermal Sense Device present set if an SMBus thermal sensor on package Dual Core Intel Xeon Processor 7100 Series Datasheet 107 intel Offset 78h Bit Description 3 Reserved 2 OEM EEPROM present set if there is a scratch ROM at offset 80 FFh 1 Core VID present set if there is a VID provided by the processor 0 L3 Cache present set if there is a level 3 cache on the processor 7 4 3 8 3 PTCI Processor Thread and Core Information This location contains information regarding the number of cores and threads on the processor Writes to this register have no effect Example The Dual Core Intel Xeon processor 7100 series has two cores and two threads per core Therefore this register will have a value of 0Ah Offset 79h Bit Description 7 4 Reserved 3 2 Number of cores 1 0 Number of threads per core 7 4 3 8 4 APFF Additional Processor Feature Flags This location contains additional feature information for the processor This field is defined as follows Writes to this register have no effect Offset 7Ah Bit Description Reserved Intel Cache Safe Technology CIE State Intel virtualization Technology Execute Disable Intel 64 Therma
152. ound This pin is to be connected to Vcca and Vecjop_ through a discrete filter circuit Var is the front side bus termination voltage VTTEN can be used as an output enable for the Vr regulator VTTEN is used as an electrical key to prevent processors with mechanically equivalent pinouts from accidentally booting in a Dual Core Intel Xeon processor 7100 series platform Since VTTEN is an open circuit on the processor package VITEN must be pulled up on the motherboard Refer to the appropriate platform design guide for implementation details 8 Dual Core Intel Xeon Processor 7100 Series Datasheet n Thermal Specifications n tel 6 6 1 Note 6 1 1 Thermal Specifications Package Thermal Specifications The Dual Core Intel Xeon processor 7100 series requires a thermal solution to maintain temperatures within operating limits Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Sprea
153. p RL Termination 360 450 540 Q 4 Resistance pull down COMPO COMP Resistance 49 4 49 9 50 4 Q 5 Notes 1 The tolerances for this specification have been stated generically to enable system designers to calculate the minimum values across the range of Vr GTLREF is generated from V on the baseboard by a voltage divider of 1 resistors Ry is the on die termination resistance measured at V7 2 of the AGTL output driver R is the on die termination resistance for improved noise margin and signal integrity The COMPO resistor is provided by the baseboard with 1 resistors See the appropriate platform design guide for implementation details The Vy referred to in these specifications refers to instantaneous Vr 8 Ov MIRO Dual Core Intel Xeon Processor 7100 Series Datasheet n Mechanical Specifications n tel 3 Figure 3 1 Note Mechanical Specifications The Dual Core Intel Xeon processor 7100 series is packaged in a Flip Chip Micro Pin Grid Array 6 FC mPGA6 package that interfaces with the motherboard via a mPGA604 socket The package consists of a processor core mounted on a substrate pin carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together Refer to the mPGA604 Socket Design Guideli
154. plication note FORCEPR This input can be used to force activation of the Thermal Control Circuit GTLREF 3 0 GTLREF determines the signal reference level for AGTL input pins GTLREF is used by the AGTL receivers to determine if a signal is an electrical 0 or an electrical 1 Please refer to Table 2 23 for further details HIT HITM I O I O HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any front side bus agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together every other common clock Since multiple agents may deliver snoop results at the same time HIT and HITM are wire OR signals which must connect the appropriate pins of all processor front side bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers HIT and HITM are activated on specific clock edges and sampled on specific clock edges ID 7 0 ID 7 0 are the Transaction ID signals They are driven during the Deferred Phase by the deferring agent IDS IDS is the ID Strobe signal It is asserted to begin the Deferred Phase IERR IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor front side bus This transaction may optio
155. processor s high thermal ramp rates make this infeasible Refer to the thermal design guidelines listed in Section 1 2 for more details The SMBus thermal sensor feature in the processor cannot be used to measure Tease The Tease specification in Section 6 must be met regardless of the reading of the processor s thermal sensor in order to ensure adequate cooling for the entire processor The SMBus thermal sensor feature is only available while Vec and SM VCC are at valid levels and the processor is not in a low power state Dual Core Intel Xeon Processor 7100 Series Datasheet Features 7 4 7 Table 7 8 Table 7 9 Table 7 10 Table 7 11 Table 7 12 intel Thermal Sensor Supported SMBus Transactions The thermal sensor responds to five of the SMBus packet types Write Byte Read Byte Send Byte Receive Byte and Alert Response Address ARA The Send Byte packet can be used for sending one shot commands The Receive Byte packet accesses the register commanded by the last Read Byte packet and can be used to continuously read from a register If a Receive Byte packet was preceded by a Write Byte or send Byte packet more recently than a Read Byte packet then the behavior is undefined Table 7 8 through Table 7 12 diagram the five packet types In these figures S represents the SMBus start bit P represents a stop bit Ack represents an acknowledge and represents a negative acknowledge NACK The shaded bits are
156. r Other W25 Vec Power Other AA3 BSELO Power Other Output W26 Vss Power Other AA4 DEP7 Source Sync Input Output W27 Vec Power Other AA5 VssA Power Other Input W28 Vss Power Other AA6 Vec Power Other w29 Vec Power Other AA7 TESTHI4 Power Other Input W30 Vss Power Other AA D61 Source Sync Input Output W31 Vcc Power Other AA9 Vss Power Other Y1 Vss Power Other AA10 D54 Source Sync Input Output Y2 Vcc Power Other AA11 D53 Source Sync Input Output Y3 Vss Power Other AA12 Vit Power Other Y4 BCLKO FSB CIk Input AA13 D48 Source Sync Input Output Y5 Vss Power Other AA14 D49 Source Sync Input Output Y6 TESTHI3 Power Other Input AA15 Vss Power Other X7 Vss Power Other AA16 D33 Source Sync Input Output Y8 RESET Common Clk Input AA17 Vss Power Other Y9 D62 Source Sync Input Output AA18 D24 Source Sync Input Output Y10 Vr Power Other AA19 D15 Source Sync Input Output Yii DSTBP3 Source Sync Input Output AA20 Vcc Power Other Y12 DSTBN3 Source Sync Input Output AA21 D11 Source Sync Input Output Y13 Vss Power Other AA22 D10 Source Sync Input Output Y14 DSTBP2 Source Sync Input Output AA23 Vss Power Other Y15 DSTBN2 Source Sync Input Output AA24 D6 Source Sync Input Output Y16 Vcc Power Other AA25 D3 Source Sync Input Output Y17 DSTBP1 Source Sync Input Output AA26 Vcc Power Other Y18 DSTBN1 Source Sync Input Output AA27 D1 Source Sync Input Output 62 Dual Core Intel Xeon Processor 7100 Series Data
157. r executes its Built in Self Test BIST LINTO INTR LINT1 NMI LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all front side bus agents When the APIC functionality is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous These signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK I O LOCK indicates to the system that a set of transactions must occur atomically This signal must connect the appropriate pins of all processor front side bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor front side bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor front side bus throughout the bus locked operation and ensure the atomicity of lock MCERR I O MCERR Machine Check Error is asserted to indicate an unrecoverable error or a bus protocol violation It may be driven by all
158. r on configuration the central agent must assert the BRO bus signal All symmetric agents sample their BR 3 0 pins on the active to inactive transition of RESET The pin which the agent samples asserted determines its agent ID BSEL 1 0 These output signals are used to select the front side bus frequency The frequency is determined by the processor s chipset and frequency synthesizer capabilities All front side bus agents must operate at the same frequency Individual processors will only operate at their specified front side bus frequency See the appropriate platform design guide for implementation examples See Table 2 3 for output values Refer to the appropriate platform design guide for termination recommendations COMPO COMPO must be terminated to Vss on the baseboard using precision resistors This input configures the AGTL drivers of the processor Refer to the appropriate platform design guide and Table 2 23 for implementation details CVID 3 0 CVID 3 0 Cache Voltage ID pins are used to support automatic selection of VcacHe These are open drain signals that are driven by the processor and must be pulled to no more than 3 3 V 5 tolerance with a resistor Conversely the VcAcug VR output must be disabled prior to the voltage supply for these pins becoming invalid The CVID pins are needed to support processor voltage specification variations See Table 2 5 for definitions of these pins The VcAcuE VR
159. rocessor Core Data Byte pointer OOh if not present Address 05h 8 L3 Cache Data Address Byte pointer 00h if not present 06h 8 Package Data Address Byte pointer OOh if not present 07h 8 Part Number Data Address Byte pointer OOh if not present 08h 8 Thermal Reference Data Byte pointer OOh if not present Address 09h 8 Feature Data Address Byte pointer 00h if not present OAh 8 Other Data Address Byte pointer 00h if not present OB OCh 16 Reserved Reserved ODh 8 Checksum 1 byte checksum Processor Data OE 13h 48 S spec QDF Number Six 8 bit ASCII characters 14h 6 Reserved Reserved most significant bits 2 Sample Production 00b Sample 01b Production 15h 8 Checksum 1 byte checksum Processor Core Data 16 17h 2 Processor Core Type From CPUID 4 Processor Core Family From CPUID 4 Processor Core Model From CPUID 4 Processor Core Stepping From CPUID 2 Reserved Reserved for future use 18 19h 16 Reserved Reserved for future use 1A 1Bh 16 Front Side Bus Speed 16 bit binary number in MHz 1Ch 2 Multiprocessor Support 00b UP 01b DP 10b RSVD 11b MP 6 Reserved Reserved 1D 1Eh 16 Maximum Core Frequency 16 bit binary number in MHz 1F 20h 16 Maximum Core VID Maximum Vcc Ge by VID outputs in m 21 22h 16 Minimum Core Voltage Minimum processor DC Vcc in mV 23h 8 Tcase Maximum Maximum case temperature spec in C 24h 8 Checksum 1 byte checksum Cache Data 25 26h 16 Reserved Reserved for future use 27 28h 16 L2 Cache Size 16 bi
160. rom the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the Dual Core Intel Xeon Processor 7100 Series processor heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical performance of the front side bus therefore it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide 8 Dual Core Intel Xeon Processor 7100 Series Datasheet 127 128 Debug Tools Specifications Dual Core Intel Xeon Processor 7100 Series Datasheet
161. s Var 4 Leakage to Vss with pin held at Vmr 5 The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load 9 Leakage to Vr with pin held at 300 mV Table 2 20 PWRGOOD and TAP Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Vuys Input Hysteresis 120 396 mV 5 PWRGOOD Input Low to 0 5 Vr VHYS_MIN s 0 5 Vir Vuvs MAX V 3 6 V High Threshold Voltage 0 24 0 24 Tw TAP Input Low to High 0 5 Vir Vuys MIN 0 5 Vr Vuys max V 3 Threshold Voltage H H PWRGOOD Input High to V 3 T Low Threshold Voltage 0 4 Vir 0 6 Vir T TAP Input High to Low 0 5 Vr B Vuvs MAX 0 5 Vr Vuys MIN V 3 Threshold Voltage Vou Output High Voltage N A Vit V 2 3 Igi Output Low Current 45 mA 4 Ir Input Leakage Current 200 HA Iro Output Leakage Current 200 HA Ron Buffer On Resistance 8 12 Q Ron TDO Buffer On 7 12 Q Resistance Notes 1 All outputs are open drain 2 TAP signal group must meet system signal quality specification in Chapter 3 3 The Vy referred to in these specifications refers to instantaneous Vyr 4 The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load Du 38 Vuys represents the amount of hysteresis nominally centered about 0 5 V for all TAP inputs 0 24 V is defined at 20 of no
162. s anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable A thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the Dual Core Intel Xeon Processor 7100 Series Thermal Mechanical Design Guidelines for information on designing a thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines Thermal Monitor 2 The Dual Core Intel Xeon processor 7100 series also supports an additional power reduction capability known as Thermal Monitor 2 TM2 This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor The Thermal Monitor or Thermal Monitor 2 feature must be enabled for the processor to be operating within specifications When Thermal Monitor 2 is enabled and a high temperature situation is detected the Thermal Control Circuit TCC will be activated The TCC causes the processor to adjust its operating frequency via the bus multiplier and input voltage via the VID signals This combi
163. s on a timed basis AL TH This bit selects the function of pin 13 Default 0 ALERT Always set this bit to O Dual Core Intel Xeon Processor 7100 Series Datasheet intel Table 7 17 SMBus Thermal Sensor Configuration Register Sheet 2 of 2 Bit Name Reset State Function 4 RESERVED RESERVED Reserved for future use 3 Remote 1 2 0 Setting this bit to 1 enables the user to read the processor core 2 values from the processor core 1 registers Default 0 means Read processor core 1 values from the processor core 1 registers Always set this bit to 0 2 Temp Range 0 Setting this bit to 1 enables the extended temperature measurement range 50 C to 150 C Default 0 0 C to 127 C Always set this bit to 0 1 Mask R1 0 Setting this bit to 1 masks ALERTS due to the processor core 1 temperature exceeding a programmed limit Default 0 Always set this bit to 0 0 Mask R2 0 Setting this bit to 1 masks ALERTS due to the processor core 2 temperature exceeding a programmed limit Default 0 Always set this bit to 0 7 4 8 5 Conversion Rate Register The contents of the Conversion Rate Registers determine the nominal rate at which analog to digital conversions happen when the SMBus thermal sensor is in auto convert mode There are two Conversion Rate Registers address 04h for reading the conversion rate value and address OAh for writing the value Table 7 18 show
164. s packaging technology employs a 1 27 mm 0 05 in pitch for the substrate pins Front Side Bus FSB The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied e Integrated Heat Spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface e mPGAG604 The Dual Core Intel Xeon processor 7100 series processor mates with the system board through this surface mount 604 pin zero insertion force ZIF socket e OEM Original Equipment Manufacturer e Processor core The processor s execution engine All AC timing and signal integrity specifications are to the pads of the processor core e Processor Information ROM PIROM A memory device located on the processor and accessible via the System Management Bus SMBus which contains information regarding the processor s features This device is shared with the Scratch EEPROM is programmed during manufacturing and is write protected e Scratch EEPROM Electrically Erasable
165. s the mapping between Conversion Rate Register values and the conversion rate As indicated in Table 7 13 the Conversion Rate Register is set to its default state of 1000b 16 Hz nominally when the thermal sensor is powered up There is a 30 error tolerance between the conversion rate indicated in the conversion rate register and the actual conversion rate Table 7 18 SMBus Thermal Sensor Conversion Rate Register Bit Name Reset State Function 7 MSB Averaging 0 Setting this bit to 1 disables averaging of the temperature measurements at the slower conversion rates Default 0 Averaging enabled Dual Core Intel Xeon Processor 7100 Series Datasheet 115 intel Table 7 18 SMBus Thermal Sensor Conversion Rate Register 7 4 9 116 Bit Name Reset State Function 6 RESERVED RESERVED Reserved for future use 5 4 Channel Selector 00 These bits are used to select the temperature measurement channels 00 Round robin 01 Local Temperature 10 Processor Core 1 Temperature 11 Processor Core 2 Temperature Default 00 Always set these bits to 00 3 0 Conversion Rates 1000 These bits determine how often the temperature sensor measures each temperature channel Bit encoding Conversions sec 0000 0 0625 0001 0 125 0010 0 25 0011 0 5 0100 1 0101 22 0110 24 0111 28 1000 16 default 1001 32 1010 Continuous Measurements SMBus Thermal
166. s used whenever fields within the PIROM are redefined The initial definition will begin at a value of 1 If a field or bit assignment within a field is changed such that software needs to discern between the old and new definition then the data format revision field will be incremented 00h Reserved Oth Initial definition 02h Second revision 03h Third revision Defined by this EMTS 04h FFh Reserved PISIZE PIROM Size This location identifies the PIROM size Writes to this register have no effect Offset 01h 02h Bit Description 15 0 PIROM Size The PIROM size provides the size of the device in hex bytes The MSB is at location 01h the LSB is at location 02h 0000h 007Fh Reserved 0080h 128 byte PIROM size 0081 FFFFh Reserved PDA Processor Data Address This location provides the offset to the Processor Data Section Writes to this register have no effect Offset 03h Bit Description 7 0 Processor Data Address Byte pointer to the Processor Data section 00h Processor Data section not present Oih ODh Reserved OEh Processor Data section pointer value OFh FFh Reserved Dual Core Intel Xeon Processor 7100 Series Datasheet 93 intel 7 4 3 1 4 7 4 3 1 5 7 4 3 1 6 94 PCDA Processor Core Data Address Features This location provides the offset to the Processor Core Data Section Writes to this register have no effect
167. se of much heavier heatsink masses compared to legacy solution limitations by using a load path attached to the chassis pan The CEK spring on the under side of the baseboard provides the necessary compressive load for the thermal interface material The baseboard is intended to be isolated such that the dynamic loads from the heatsink are transferred to the chassis pan via the heatsink screws and heatsink standoffs This reduces the risk of package pullout and solder joint failures in a shock and vibe situation The assembly requires larger diameter holes to compensate for the CEK spring embosses See Figure 8 2 and Figure 8 3 for processor mounting thru holes For further details on the solution refer to the Dual Core Intel Xeon Processor 7100 Series Thermal Mechanical Design Guidelines Thermal Specifications This section describes the cooling requirements of the heatsink solution utilized by the boxed processor Boxed Processor Cooling Requirements The boxed processor will be cooled by forcing ducted chassis fan airflow through the passive heat sink solution Meeting the processor s temperature specifications is a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is found in Section 6 of this document For the boxed processor passive heatsink to operate properly chassis air movement devices are required Necessary airflow and associate
168. sheet Pin Listing Table 4 2 Pin Listing by Pin Number Sheet 13 of 16 intel Table 4 2 Pin Listing by Pin Number Sheet 14 of 16 Pin No Pin Name une Direction Pin No Pin Name gine ce Direction AA28 SM TS1 AO SMBus Input AC6 D59 Source Sync Input Output AA29 SM EP AO SMBus Input AC7 Vss Power Other AA30 Vss Power Other AC8 D56 Source Sync Input Output AA31 Vec Power Other AC9 D47 Source Sync Input Output AB1 Vss Power Other AC10 Vr Power Other AB2 Vcc Power Other AC11 D43 Source Sync Input Output AB3 BSEL1 Power Other Output AC12 D41 Source Sync Input Output AB4 VccA Power Other Input AC13 Vss Power Other AB5 Vss Power Other AC14 D50 Source Sync Input Output AB6 D63 Source Sync Input Output AC15 DP2 Common Clk Input Output AB7 PWRGOOD Async GTL Input AC16 Vec Power Other AB8 Vcc Power Other AC17 D34 Source Sync Input Output AB9 DBI3 Source Sync Input Output AC18 DPO Common Clk Input Output AB10 D55 Source Sync Input Output AC19 Vss Power Other AB11 Vss Power Other AC20 D25 Source Sync Input Output AB12 D51 Source Sync Input Output AC21 D26 Source Sync Input Output AB13 D52 Source Sync Input Output AC22 Vec Power Other AB14 Vec Power Other AC23 D23 Source Sync Input Output AB15 D37 Source Sync Input Output AC24 D20 Source Sync Input Output AB1
169. sible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion Please see the applicable design guidelines for further details The processor is capable of drawing IcAcug rpc indefinitely This parameter is based on design characterization and is not tested g Dual Core Intel Xeon Processor 7100 Series Datasheet 29 n n tel Electrical Specifications Figure 2 3 Dual Core Intel Xeon Processor 7100 Series Load Current vs Time lt t 23 o kl EI E J o 23 o 0 01 0 1 1 10 100 1000 Tim e Duration s Notes 1 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than lcc roc 2 Not 100 tested Specified by design characterization 30 Dual Core Intel Xeon Processor 7100 Series Datasheet m Electrical Specifications n tel Table 2 11 Vcc Static and Transient Tolerance Le TAT T Yez Vere M Vem Nores 0 vo ooo vo ooo Vib 00 0 123 eo vi oors vio oos _vio o115 123 so vi 010 Vib 0120 Vib 0140 123 eo vb o18 _vio o133 _vio o153 123 Notes 1 The Vcc M N and Vcc max load lines represent static and transient limits 2 This table is intended to aid in reading discrete points on Figure 2 4 3 The load lines specify voltage limits at the die measured at the Vccsense and Vsssense pins Voltage regulation feedback for voltage regulator c
170. ssor 7100 Series Datasheet Features 7 4 3 6 1 PREV Package Revision intel This location contains seven ASCII characters reflecting the Intel part number for the processor This information is typically marked on the outside of the processor If the part number is less than 7 characters a leading space is inserted into the value The part number should match the information found in the marking specification found in Section 3 Writes to this register have no effect Example A processor with a part number of 80546KF will have data found at offset 38 3Eh is 38 30 35 34 36 4B 46 Offset 38h 3Eh Bit Description 4F 48 Character 7 ASCII character or 20h OOh OFFh ASCII character 47 40 Character 6 ASCII character or 20h OOh OFFh ASCII character 39 32 Character 5 ASCII character or 20h OOh OFFh ASCII character 31 24 Character 4 ASCII character OOh OFFh ASCII character 23 16 Character 3 ASCII character OOh OFFh ASCII character Character 2 ASCII character OOh OFFh ASCII character 7 0 Character 1 ASCII character OOh OFFh ASCII character 7 4 3 6 2 RES6 Reserved 6 This location is reserved Writes to this register have no effect Offset 3Fh 4Ch Bit Description 111 0 RESERVED 6 Dual Core Intel Xeon Processor 7100 Series Datasheet 105 intel 7 4 3 6 3 PSERSIG Processor Serial Ele
171. sting by Pin Number 57 5 Signal Definitions iiie er dran eas ceed kaka anan a capes ENEE ENEE a ya ala e EA Qara RARE REA 65 5 1 Signal Definitions EE 65 6 Thermal Specifications E e eretecse sexe kaka kk 3 Pa gs EXTR kak kaka aka kak 73 6 1 Package Thermal Specifications s 4 s 2 2 s ni sal n NEES ENEE NEE ER bad a nha hax a E waa ER Dayka SEN EH 73 6 1 1 Thermal Specifications iere ete tien nene d k aa nin astutia d EE EE ba DAD a a 73 6 1 2 Thermal Metrology 2229 s3 yioyla y Han la V l da te reet Rena AER EENS geed eA a 77 6 2 Processor Thermal Features gess geweit n Eeer g a b ya dine saa ln enne chau nan daa gau a E Rd eX XS RR ege ka 77 6 221 Thermal Monito St ier BEE e b da ed d wan enr DEED SOME ed ook 77 6 2 2 Thermal Monitor dengen eeng ege eege yox ae Rito Qe N NEE gk uM e OR a Diana 78 6 2 3 On Demand D TEE 79 6 2 4 PROCHOTZ Signal PIN si Hc neee ninan ka nan k Zar DA wa RUE BEA bk Wa D h 80 6 2 5 FORCEPR Signal Pil ai sya sk deman Wada dank ka SEENEN kara kb ad ebd k 80 Dual Core Intel Xeon Processor 7100 Series Datasheet 3 intel 6 2 5 THERMTRIP Signal Pil i ENER kik nak d ka b na n RR ERRARE EE DEES ka Wa unis DER RR k 80 6 2 7 TCONTROL and Fan Speed Reduction sssssssssseseseemmeenee 80 6 2 8 Thermal Diode i esteso Genee te nex tim Ee RN Ge kad ya WR NA WI b ya wis kar kar e W an kak 81 7 j x g
172. t Output C30 Vec Power Other E8 BPM4 Common CIk Input Output C31 Vss CACHE SENSE Power Other E9 Vss Power Other D1 CVID1 Power Other Output E10 APO Common Clk Input Output D2 Vss Power Other E11 BR2 Common CIk Input D3 VID2 Power Other Output E12 Vit Power Other D4 STPCLK Async GTL Input E13 A28 Source Sync Input Output DS Vss Power Other E14 A24 Source Sync Input Output D6 INIT Async GTL Input E15 Vss Power Other D7 MCERR Common CIk Input Output E16 Reserved D8 Vcc Power Other E17 Vss Power Other D9 AP1 Common Clk Input Output E18 DRDY Common Clk Input Output D10 BR3 Common CIk Input E19 TRDY Common CIk Input D11 Vss Power Other E20 Vcc Power Other D12 A293 Source Sync Input Output E21 RSO Common CIk Input D13 A25 Source Sync Input Output E22 HIT Common CIk Input Output D14 Vcc Power Other E23 Vss Power Other D15 A18 Source Sync Input Output E24 TCK TAP Input D16 A173 Source Sync Input Output E25 TDO TAP Output D17 A9 Source Sync Input Output E26 Vcc Power Other D18 Vcc Power Other E27 FERR PBE Async GTL Output D19 ADS Common Clk Input Output E28 Vec Power Other D20 BRO Common Clk Input Output E29 Vss Power Other D21 Vss Power Other E30 Vcc Power Other D22 RS1 Common Clk Input E31 Vss Power Other D23 BPRI Common Clk Input F1 Vcc Power Other D24 Vcc Power Other F2 Vss Power Other D25 ID2 Common Clk Input F3 VIDO Power Other Output 58 Dual Core Intel Xeon Processor 7100 Series Datasheet
173. t binary number in KB 29 2Ah 16 L3 Cache Size 16 bit binary number in KB 2B 2Ch 16 Maximum Cache CVID Maximum VcacHE requested by CVID outputs in mV Dual Core Intel Xeon Processor 7100 Series Datasheet 91 intel Table 7 6 Note 92 Features Processor Information ROM Data Sections Sheet 2 of 2 Offset Section TT Function Notes Bits 2D 2Eh 16 Minimum Cache Voltage Minimum processor DC VcAcue in mV 2F 30h 16 Reserved Reserved 31h 8 Checksum 1 byte checksum Package Data 32 35h 32 Package Revision Four 8 bit ASCII characters 36h 8 Reserved Reserved for future use 37h 8 Checksum 1 byte checksum Part Number Data 38 3Eh 56 Processor Part Number Seven 8 bit ASCII characters 3F 4Ch 112 Reserved Reserved 4D 54h 64 Processor Electronic 64 bit identification number Signature 55 6Eh 208 Reserved Reserved 6Fh 8 Checksum 1 byte checksum Thermal Ref Data 70h 8 Reserved Reserved 71 72h 16 Reserved Reserved 73h 8 Checksum 1 byte checksum Feature Data 74 77h 32 Processor Core Feature From CPUID function 1 EDX contents Flags 78h 8 Processor Feature Flags 7 Multi Core 6 Serial Signature 5 Electronic Signature Present 4 Thermal Sense Device Present 3 Reserved 2 OEM EEPROM Present 1 Core VID Present 0 L3 Cache Present 79h 8 Processor Thread and
174. t wo o epea a p o gt o gt op p gt gt p gt p gt nn 5jw awvwarbmgmm Dn 83 7 1 Power On Configuration Options kk kka dka akla ka aska a elek a ajak aa a a ek nemen ak kala 83 7 2 Clock Control and Low Power States 83 7 2 1 Normal State s xey sar yan Dima e uge MORA wc q n S n Seege dew kar w an kak 84 7 2 2 HALT or Enhanced Power Down State 84 7 2 3 StOp Grant Zenter SE i n b n S ye k KEMERA Ee EES SE 85 7 2 4 Enhanced HALT Snoop State or HALT Snoop State Stop Grant SNOOP Stats sreski tennen SEA dee amies mM AE w d w ADEM mind 86 7 3 Enhanced Intel SpeedStep Technology 86 7 4 System Management Bus SMBus Interface ssssssssssssseee eene 87 4 4 1 SMBus Device Addressing seriais ENNEN NEE n nur na na a XY Pan Mena Pa a EAM ERRARE 88 7 4 2 PIROM and Scratch EEPROM Supported SMBus Transactions ccecce 90 7 4 3 Processor Information ROM PIROM kk kk kk mmm 90 TAGE Ee cur cT 109 7 4 5 Scratch EEPROM s 56 14a0y x a eoa Ebak A adab C REA ERE b Q lee d ban ka kek 110 7 4 5 SMBUS Thermal SensOr ccs neide tases ken ae dini e dara SEAN kalak dra b wali a di 110 7 4 7 Thermal Sensor Supported SMBus Transactions khk khk kK kkklkkkk tees eset kk 111 7 4 8 SMBus Thermal Sensor Registers eene 113 7 4 9 SMBus Thermal Sensor Alert Interrupt sess 116 8 Boxed Processor Spechfications eee eee kk kk kk kaka kk kk kaka 117 8 1 Introduction as
175. ter 4 S SPEC or QDF character OOh OFFh ASCII character 23 16 Character 3 S SPEC or QDF character OOh OFFh ASCII character Character 2 S SPEC or QDF character OOh OFFh ASCII character 7 0 Character 1 S SPEC or QDF character OOh OFFh ASCII character 7 4 3 2 2 SAMPROD Sample Production This location contains the sample production field which is a two bit field and is LSB aligned All Q spec material will use a value of 00b All S spec material will use a value of 01b All other values are reserved Writes to this register have no effect Example A processor with a Qxxx mark engineering sample will have offset 14h set to 00h A processor with an Sxxxx mark production unit will use 01h at offset 14h Offset 14h Bit Description 7 2 RESERVED 000000b 111111b Reserved 1 0 Sample Production Sample or Production indictor 00b Sample 01b Production 10b 11b Reserved Dual Core Intel Xeon Processor 7100 Series Datasheet 97 intel TN 7 4 3 2 3 PDCKS Processor Data Checksum This location provides the checksum of the Processor Data Section Writes to this register have no effect Offset 15h Bit Description 7 0 Processor Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value 7 4 3 3 Processor Core Data This section contains core silicon related data 7 4 3 3
176. ter than 3 0 GHz 150 5 See Figure 6 1 1 2 and Table 6 2 Less than or equal to 95 5 See Figure 6 2 1 2 3 0 GHz and Table 6 3 Note 1 Thermal Design Power TDP should be used for processor thermal solution design targets The TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 2 FMB or Flexible Motherboard guidelines provide a design target for meeting future thermal requirements See Section 2 10 1 for further information on FMB Dual Core Intel Xeon Processor 7100 Series Datasheet m Thermal Specifications n tel Figure 6 1 150W Dual Core Intel Xeon Processor 7100 Series Thermal Profile 70 C 8 TCASE_MAX g 20 40 60 80 100 120 140 160 Power WM y 0 158 x 45 Note Refer to the Dual Core Intel Xeon Processor 7100 Series Thermal Mechanical Design Guidelines for system and environmental implementation details Table 6 2 150W Dual Core Intel Xeon Processor 7100 Series Thermal Profile Power W Teaser max C Dual Core Intel Xeon Processor 7100 Series Datasheet 75 e n tel Thermal Specifications Figure 6 2 95W Dual Core Intel Xeon Processor 7100 Series Thermal Profile 65 60 55 Tcase max C ol e 35 35 25 15 5 5 15 25 35 45 55 65 75 85 95 Power W y 0 158 x 45 Notes 1 Refer to the Dual Core Intel Xeon
177. tion CVID3 CVID2 CVID1 CVIDO CVID V 1 1 1 1 Off 1 1 1 0 1 100 1 1 0 1 1 125 1 1 0 0 1 150 1 0 1 1 1 175 1 0 1 0 1 200 1 0 0 1 1 225 1 0 0 0 1 250 0 1 1 1 1 275 0 1 1 0 1 300 0 1 0 1 1 325 0 1 0 0 1 350 0 0 1 1 1 375 0 0 1 0 1 400 0 0 0 1 1 425 0 0 0 0 1 450 Note The voltage regulator will have a fifth VID input and for VRM 10 2 compliant regulators a sixth VID input as well The extra input s should be tied to a high voltage on the motherboard for correct operation Refer to the appropriate platform design guide for further implementation details Reserved Unused and TESTHI Pins All RESERVED pins must be left unconnected Connection of these pins to Vcc Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Section 5 for a pin listing for the processor and the location of all RESERVED pins For reliable operation always terminate unused inputs or bidirectional signals to their respective deasserted states On die termination has been included on the Dual Core Intel Xeon processor 7100 series to allow signals to be terminated within the processor Dual Core Intel Xeon Processor 7100 Series Datasheet 23 e n tel Electrical Specifications 2 5 2 6 24 silicon Most unused AGTL inputs may be left as no connects since AGTL termination is provided on the processor silic
178. to be addressed the Processor Information ROM MSB 0 or the Scratch EEPROM MSB 1 Read Byte SMBus Packet Slave Comman Slave S dig Write A d Code AJS Address Read A Data P 1 7 bits L 1 8 bits 1 1 7 bits 1 1 8 bits 1 1 Write Byte SMBus Packet S Slave Address Write A Command Code A Data A P 1 7 bits 1 1 8 bits 1 8 bits 1 1 Processor Information ROM PIROM The lower half 128 bytes of the SMBus memory component is an electrically programmed read only memory with information about the processor This information is permanently write protected Table 7 6 shows the data fields and Section 7 4 3 provides the formats of the data fields included in the Processor Information ROM PIROM The PIROM consists of the following sections e Header e Processor Data e Processor Core Data e Cache Data e Package Data e Part Number Data e Thermal Reference Data Feature Data e Other Data Dual Core Intel Xeon Processor 7100 Series Datasheet Features Table 7 6 Processor Information ROM Data Sections Sheet 1 of 2 Offset Section e Function Notes Header 00h 8 Data Format Revision Two 4 bit hex digits 01 02h 16 PIROM Size Size in bytes MSB first 03h Processor Data Address Byte pointer 00h if not present 04h 8 P
179. tsink Boxed Processor Heatsink Dimensions The boxed processor is shipped with an unattached passive heatsink Clearance is required around the heatsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor and assembled heatsink are shown in the following figures Dual Core Intel Xeon Processor 7100 Series Datasheet intel Boxed Processor Specifications Top Side Board Keep Out Zones Part 1 Figure 8 2 119 d Y 4 S 9 L 8 3 30 i IS3NS 9 UATRT 3T2S 10K Qi NOW 31635 Y H c62S1V X q 7 Q34011V SLNINOdHOD QNVOBNHION ON LNOd33N Y39NIA GUYOE 9NIHdS W39 E Wi Laun ox vao 3002 sevo hir s Gs Wielt EE ANGE eva 20720701 EENS NOLL2INIS3N 1HO13H LN3NOdNOO QUVOGUHIOH XYN WAPI IGG Q 3ivo e gen HII GARE m RE P N am eme distin di ET mea ERE PER Q3MOTIY 1N3N3OV T4 LN3NOdHOD QHYOBH3HION ON Q Y 2i NO 119181838 1H013H lN3NOdHOO In WN 928 SET V3UV A 18N388V810 JNISIV3H amp e E EEN NO 119141834 1H913H ININOJNOJ XVH
180. uency is configured during reset by using values stored internally during manufacturing The stored values set the highest bus fraction at which the particular processor can operate If lower speeds are desired the appropriate bus ratio multiplier can be configured by driving the A 21 16 pins at reset For details of operation at core frequencies lower than the maximum rated processor speed refer to the Cedar Mill Processor Family BIOS Writer s Guide The bus ratio multipliers supported are shown in Table 2 1 and Table 2 2 Other combinations will not be validated or supported by Intel For a given processor only the ratios which result in a core frequency equal to or less than the frequency marked on the processor are supported 166 MHz Core Frequency to Front Side Bus Multiplier Configuration Sheet 1 of 2 Core Frequency to Front Side Bus Core Frequency A213 A20 A19 A18 A17 A16 Multiplier 166 MHz 1 15 2 5 GHz H 1 18 3 GHz H L H F 1 Dual Core Intel Xeon Processor 7100 Series Datasheet intel Table 2 1 Table 2 2 2 1 2 Electrical Specifications 166 MHz Core Frequency to Front Side Bus Multiplier Configuration Sheet 2 of 2 Core Frequency to Front Side Bus Mo rd A213 A203 A193 A183 A174 A163 Multiplier 1 19 3 16 GHz H L H H L 1 20 3 33 GHz H L H L H H 1 21 3 50 GHz H L H L H Notes 1 Individual processors
181. ulation circuit cannot supply the voltage that is requested the processor s voltage regulator must disable itself See the Vcc Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 2 Design Guidelines for more details The Dual Core Intel Xeon processor 7100 series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 2 10 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 2 11 and Figure 2 4 The VRM or VRD utilized must be capable of regulating its output to the value defined by the new VID DC specifications for VID transitions are included in Table 2 10 and Table 2 11 Please refer to the Vcc Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 2 Design Guidelines for further details Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable Dual Core Intel Xeon Processor 7100 Series Datasheet 21 n tel Electrical Specifications Table 2 4 Voltage Identification VID Definition
182. utput H30 Vss Power Other F27 A20M Async GTL Input H31 Vec Power Other F28 Vss Power Other J1 Vss Power Other F29 Vec Power Other J2 Vec Power Other F30 Vss Power Other J3 Vss Power Other F31 Vcc Power Other J4 Vcc Power Other G1 Vss Power Other J5 Vss Power Other G2 Vec Power Other J6 Vcc Power Other G3 Vss Power Other J7 Vss Power Other G4 Vcc Power Other J8 Vcc Power Other G5 Vss Power Other J9 Vss Power Other G6 Vec Power Other J23 Vss Power Other G7 BOOT SELECT Power Other Input J24 Vec Power Other G8 Vec Power Other J25 Vss Power Other G9 Vss Power Other J26 Vcc Power Other G23 LINT1 NMI Async GTL Input J27 Vss Power Other G24 Vcc Power Other J28 Vcc Power Other G25 Vss Power Other J29 Vss Power Other Dual Core Intel Xeon Processor 7100 Series Datasheet 59 intel Table 4 2 Pin Listing by Pin Number Sheet 7 of 16 Pin Listing Table 4 2 Pin Listing by Pin Number Sheet 8 of 16 Pin No Pin Name GE Direction Pin No Pin Name en Direction J30 Vcc Power Other M3 VCACHE Power Other J31 Vss Power Other M4 Vss Power Other K1 VCACHE Power Other M5 VCACHE Power Other K2 Vss Power Other M6 Vss Power Other K3 VCACHE Power Other M7 VCACHE Power Other K4 Vss Power Other M8 Vss Power Other K5 VCACHE Power Other M9 VCACHE Power Other K6 Vss Power Other M23 Vec Power Other K7 VCACHE Po
183. wer Other Vcc AC22 Power Other Vss D28 Power Other Vcc AC31 Power Other Vss D30 Power Other Vcc AD2 Power Other Vss E9 Power Other Vcc AD20 Power Other Vss E15 Power Other Vcc AD26 Power Other Vss E17 Power Other Vcc AE14 Power Other Vss E23 Power Other Vec AE18 Power Other Vss E29 Power Other Vcc AE24 Power Other Vss E31 Power Other VccA AB4 Power Other Input Vss F2 Power Other Vcc CACHE SENSE B31 Power Other Output Vss F7 Power Other VccioPLL AD4 Power Other Input Vss F13 Power Other VecPLL AD1 Power Other Input Vss F19 Power Other VccsENSE B27 Power Other Output Vss F25 Power Other VIDO F3 Power Other Output Vss F28 Power Other VID1 E3 Power Other Output Vss F30 Power Other VID2 D3 Power Other Output Vss G1 Power Other VID3 C3 Power Other Output Vss G3 Power Other VID4 B3 Power Other Output Vss G5 Power Other VIDE A1 Power Other Output Vss G9 Power Other VIDPWRGD B1 Power Other Input Vss G25 Power Other Vss A5 Power Other Vss G27 Power Other Vss A11 Power Other Vss G29 Power Other Vss A21 Power Other Vss G31 Power Other Vss A27 Power Other Vss H2 Power Other 54 Dual Core Intel Xeon Processor 7100 Series Datasheet Pin Listing Table 4 1 Pin Listing by Pin Name Sheet 13 of 16 Table 4 1 Pin Listing by Pin Name intel Sheet 14 of 16 Pin Name Pin No eos
184. wer Other 24 Vss Power Other K8 Vss Power Other 25 Vec Power Other K9 VCACHE Power Other 26 Vss Power Other K23 Vcc Power Other M27 Vcc Power Other K24 Vss Power Other M28 Vss Power Other K25 Vec Power Other M29 Vec Power Other K26 Vss Power Other 30 Vss Power Other K27 Vec Power Other 31 Vec Power Other K28 Vss Power Other N1 VCACHE Power Other K29 Vcc Power Other N2 Vss Power Other K30 Vss Power Other N3 VCACHE Power Other K31 Vec Power Other N4 Vss Power Other L1 Vss Power Other N5 VCACHE Power Other L2 Vcc Power Other N6 Vss Power Other L3 Vss Power Other N7 VCACHE Power Other L4 Vcc Power Other N8 Vss Power Other L5 Vss Power Other N9 VCACHE Power Other L6 Vcc Power Other N23 Vec Power Other L7 Vss Power Other N24 Vss Power Other L8 Vcc Power Other N25 Vcc Power Other L9 Vss Power Other N26 Vss Power Other L23 Vss Power Other N27 Vcc Power Other L24 Vcc Power Other N28 Vss Power Other L25 Vss Power Other N29 Vec Power Other L26 Vcc Power Other N30 Vss Power Other L27 Vss Power Other N31 Vec Power Other L28 Vec Power Other P1 Vss Power Other L29 Vss Power Other P2 Vcc Power Other L30 Vcc Power Other P3 Vss Power Other L31 Vss Power Other P4 Vec Power Other Mi VCACHE Power Other P5 Vss Power Other M2 Vss Power Other P6 Vec Power Other 60 Dual Core Intel Xeon Processor 7100 Series Datasheet Pin Listing Table 4 2 Pin Listing by Pin Number Sheet 9 of 16 intel Table 4 2 Pin Listing by Pin Number Sheet 10 of 16
185. wer Other Output Vss Y3 Power Other VsssENSE D26 Power Other Output Vss Y5 Power Other Vit B12 Power Other Vss Y7 Power Other Vr C10 Power Other Vss Y13 Power Other Vit E12 Power Other Vss Y19 Power Other Vit F10 Power Other Vss Y25 Power Other Vit Y10 Power Other Vss Y31 Power Other Vit AA12 Power Other Vss AA2 Power Other Vr AC10 Power Other Vss AA9 Power Other Vr AD12 Power Other Vss AA15 Power Other Vit AE4 Power Other Vss AA17 Power Other VTTEN E1 Power Other Output 56 Dual Core Intel Xeon Processor 7100 Series Datasheet Pin Listing 4 1 2 Pin Listing by Pin Number Table 4 2 Pin Listing by Pin Number Sheet 1 of 16 intel Table 4 2 Pin Listing by Pin Number Sheet 2 of 16 Pin No Pin Name mco oi Direction A1 VID5 Power Other Output A2 CVID3 Power Other Output A3 SKTOCC Power Other Output A4 Don t Care A5 Vss Power Other A6 A32 Source Sync Input Output A7 A33 Source Sync Input Output A8 Vcc Power Other A9 A26 Source Sync Input Output A10 A20 Source Sync Input Output A11 Vss Power Other A12 A14 Source Sync Input Output A13 A10 Source Sync Input Output A14 Vec Power Other A15 FORCEPR Power Other Input A16 TEST_BUS Power Other Input A17 LOCK Common Clk Input Output A18 Vec Power Other A19 A7 Sour
186. xing of the 7150 and 7140 Processor Numbers Front Side Bus Signal Groups The front side bus signals are grouped by buffer type as listed in Table 2 6 The buffer type indicates which AC and DC specifications apply to the signals AGTL input signals have differential input buffers that use GTLREF as a reference level In this document Dual Core Intel Xeon Processor 7100 Series Datasheet Electrical Specifications intel the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving AGTL asynchronous outputs can become active anytime and include an active pMOS pull up transistor to assist during the first clock of a low to high voltage transition Implementing a source synchronous data bus requires specifying two sets of timing parameters One set is for common clock signals which are dependent upon the rising edge of BCLKO ADS HIT HITM etc The second set is for the source synchronous signals that are relative to their respective strobe lines data and address as well as the rising edge of BCLKO Asynchronous signals are present A20M IGNNE etc and can become active at any time during the clock cycle Table 2 6 identifies signals as common clock source synchronous and asynchronous Table 2 6 Front Side Bus Pin Groups Signal Group Type Signals AGTL

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