Elixir 1GB Unbuffered DDR2 SDRAM DIMM
Contents
1. CS1 CSO DQS0 M DAQS 4 M paso WV Das 4 DM0 M DM 4 M DM CS DAQS DQS DM CS Das DAS DM CS DAQS DQS DM CS DQS DQS DQ0 4 1 00 1 00 DQ32 1 00 00 DQ1 1 01 101 DQ33 1 01 01 DQ2 N 1 02 02 DQ34 N 1 02 m 02 DQ3 N 1 03 DO 103 D8 DQ35 1 03 D4 m 103 D12 DQ4 N 1 04 H 1 04 DQ36 N 1 04 1 04 DQ5 4 1 05 105 DQ37 1 05 105 DQ6 1 06 1 06 DQ38 M 1 06 1 06 DQ7 107 07 DQ39 4 107 07 DQS1 M DQS5 DQS1 DAS 5 M DM1 M DM5 M DM CS DAQS DAS DM CS DQS DQS DM CS DQS DAS DM CS DQS DQS DQ8 1 00 o0 DA40 1 00 1 00 Dag N 101 OR DQ41 M 1 01 0 1 DAa1I0 W_ 02 02 pa42 1 02 02 DQ11 M 03 D1 B 03 D9 DQ43 M 1 03 D5 103 D13 DQ12 M 104 04 DQ44 NM 1 04 1 0 4 DQ13 M 1 05 105 DQ45 M 1 05 1 05 DQ14 M 1 06 06 DQ46 M 1 06 1 0 6 DQ15 M 107 07 DQ47 M 107 VO7 DQS2 Das6 DAS 2 DAS 6 DM2 DM6 M DM CS Das DAS2. PC2 5300 PC2 6400 Unit Symbol Parameter f f Min Max Min Max Tck Clock Cycle Time Average 3000 8000 2500 8000 ps Tch CK high level width Average 0 48 0 52 0 48 0 52 Tck Tel CK low level width Average 0 48 0 52 0 48 0 52 Tck WL Write command to DQS associated clock edge RL 1 RL 1 Nck Tdqss Write command to 1 DQS latching transition 0 25 0 25 0 25 0 25 Tck Tdss DQS falling edge to CK setup time write cycle 0 2 0 2 Tck Tash e edge hold time from CK write 0 2 7 0 2 Tek Tdgsl H DQS input low high pulse width write cycle 0 35 0 35 Tck Twpre Write preamble 0 35 0 35 Teck Twpst Write postamble 0 4 0 6 0 4 0 6 Tck Tis Address and control input setup time 200 175 ps Tih Address and control input hold time 275 250 ps Tipw Input pulse width 0 6 0 6 Tck Tus no a DM input setup time differential data 100 50 ps Toh S DM input hold time differential data 175 i 125 7 ps Tdipw DQ and DM input pulse width each input 0 35 0 35 Tck Tac DQ output access time from CK CK 450 450 400 400 ps Tdgsck DQS output access time from CK CK 400 400 350 350 ps Thz Data out high impedance time from CK CK tac max 7 tACmax ps Tiz DQs DQS low impedance time from CK CK tac min tac max tACmin tACmax ps Tiz DQ DQ low impedance time from CK CK 2tac min tac max 2tac min tac max ps Tdqsq DQS DQ skew DQS amp associated DQ signals 240 200
3. Txard Txards Taond Taon Taonpd Taofd Taof Taofpd Tanpd Taxpd Tmrd Tmod Toit tDelay Tric Trefi Parameter Exit active power down to read command Exit active power down to read command ODT turn on delay ODT turn on ODT turn on Power down mode ODT turn off delay ODT turn off ODT turn off Power down mode ODT to power down entry latency ODT power down exit latency Mode register set command cycle time MRS command to ODT update delay OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops Low Refresh to active Refresh command time Average Periodic Refresh Interval 85 C lt Tcase lt 95 C Average Periodic Refresh Interval 0 C lt Tease lt 85 C Speed Grade Definition PC2 5300 Symbol Parameter 1 Min Max Tras Row Active Time 45 70 000 Tre Row Cycle Time 60 g Tred RAS to CAS delay 15 Trp Row Precharge Time 15 7 REV 1 2 10 2008 PC2 5300 Min Max 2 a 7 AL 2 2 Tac min Tac max 0 7 2Tck Tachina Taema ti 2 5 2 5 Tac min n x 2 5Tck Tagine Tac max 1 3 8 2 c 0 12 0 12 Tis Tck Tih 127 5 3 9 7 8 PC2 6400 Unit Min Max 45 70 000 ns 57 5 ns 12 5 z ns 12 5 7 ns 15 NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice PC2 6400 Unit Min Max 2 Neck 8 AL Neck 2 2 Neck Tac min Tac max 0 7 ns A 2Tck Tac min 2 Tasia 4 ns 2 5 2 5 Nck Tac mi
4. Operating Current one bank Burst 2 reads continuous burst address and control inputs changing once per clock cycle DQ and DQS outputs changing twice per clock cycle CL 2 5 Tck Tck MIN IOUT OMa Auto Refresh Current Tre Trfc MIN Self Refresh Current CKE lt 0 2V Operating Current four bank four bank interleaving with BL 4 address and control inputs randomly changing 50 of data changing at every transfer Trc Trc min IOUT OMa PC2 5300 1408 1320 176 1144 880 493 194 1056 1452 1584 1936 194 2156 PC2 6400 1628 1540 176 1320 968 528 194 1232 1672 1804 2156 194 2420 Note Module IDD was calculated from component IDD It may differ from the actual measurement REV 1 2 13 10 2008 elixir Unit Ma Ma Ma Ma Ma Ma Ma Ma Ma Ma Ma Ma Ma NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module Tcase 0 C 85 C Vona 1 8V 0 1V Voo 1 8V 0 1V See AC Characteristics Part 1 of 2 elixir
5. REV 1 2 8 10 2008 PC2 5300 PC2 6400 3C AC 06 36 3C 39 7F 80 18 14 22 1E 00 00 13 17 FD 7F7F7F0B00000000 f NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect Part 1 of 2 2GB 256Mx64 2 RANKs UNBUFFERED DDR2 SDRAM DIMM based on 128Mx8 8Banks 8K Refresh 1 8V DDR2 SDRAMs with SPD elixir o SPD Entry Value bo a ty Note Byte Description PC2 5300 PC2 6400 PC2 5300 PC2 6400 3C AC 3C AC 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type DDR2 08 3 Number of Row Addresses on Assembly 14 OE 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Ranks 2 ranks Height 30mm 61 6 Data Width of Assembly X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1 8V 05 9 DDR2 SDRAM Device Cycle Time at CL X 3ns 2 5ns 30 25 10 DDR2 SDRAM Device Access Time from Clock at CL X 0 45ns 0 4ns 45 40 11 DIMM Configuration Type Non parity ECC 00 12 Refresh
6. reserves the right to change Products and Specifications without notice M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect Part 2 of 2 2GB elixir 256Mx64 2 RANKs UNBUFFERED DDR2 SDRAM DIMM based on 128Mx8 8Banks 8K Refresh 1 8V DDR2 SDRAMs with SPD Serial PD Data Entry Hexadecimal SPD Entry Value Byte Description PC2 5300 PC2 6400 3C AC The number below a decimal 40 Extension of Byte 41 tRC and Byte 42 tRFC point of tRC and tRFC are 0 tRFC is less than 256ns 41 Minimum Core Cycle Time tRC 60 0ns 57 5ns 42 Min Auto Refresh Command Cycle Time tRFC 127 5ns 43 Maximum Clock Cycle Time tCK 8 0ns 44 Max DQS DQ Skew Factor tQHS 0 24ns 0 20ns 45 Read Data Hold Skew Factor tQHS 0 34ns 0 30ns 46 PLL Relock Time Undefined 46 61 Reserved Undefined 62 SPD Revision 1 3 63 Checksum for bytes 0 62 Checksum Data 64 71 Manufacture s JEDEC ID Code NANYA 72 Module Manufacturing Location Manufacturing Code 73 91 Module Part number Module Part Number in ASCII 92 255 Reserved Undefined Note 1 M2Y2G64TU8HDOB 3C gt 4D325932473634545538484430422D33432020 M2Y2G64TU8HDOB AC 4D325932473634545538484430422D4 1432020 M2Y2G64TU8HD4B 3C gt 4D325932473634545538484434422D33432020 M2Y2G64TU8HD4B AC gt 4D325932473634545538484434422D41 432020
7. 114 DQS7 153 DQ29 193 CSO 234 Vss 34 DQ25 74 CAS 115 Vss 154 Vss 194 Vopa 235 DQ62 35 Vss 75 Vppa 116 DQ58 155 DM3 195 ODTO 236 DQ63 36 DQs3 76 NC CST 117 DQ59 156 NC 196 A13 237 Vss 37 DQS3 77 NC ODT1 118 Vss 157 Vss 197 Voo 238 Vopspp 38 Vss 78 Vppa 119 SDA 158 DQ30 198 Vss 239 SAO 39 DQ26 79 Vss 120 SCL 159 DQ31 199 DQ36 240 SA1 40 DQ27 80 DQ32 160 Vss 200 DQ37 41 Vss 81 DQ33 161 NC 201 Vss Note 1 NC No Connect 2 CS1 ODT1 and CKE1 Pins 76 77 and 171 are only support in 2GB module type REV 1 2 3 10 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B Celixi r M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM Input Output Functional Description Symbol CKO CK1 CK2 KO CK1 C Ol CKEO CKE1 VDDQ ODTO ODT1 BAO BA2 AO AQ A10 AP A11 A13 DQO DQ63 VDD VSS DQSO0 DQS8 DQSO DQS8 DMO DM8 SAO SA2 SDA SCL V DDSPD REV 1 2 10 2008 Type SSTL SSTL SSTL SSTL SSTL Supply Supply Input SSTL SSTL SSTL Supply SSTL Input Supply Polarity Positive Edge Negative Edge Active High Active Low Active Low Active High Active High Negative and Positive E
8. DIMM Mechanical Characteristics x lt 4 10 mm 01 20 DDR2 SDRAM DIMM Type Information UDIMM 133 35mm 02 21 DDR2 SDRAM Module Attributes Normal DIMM 00 22 DDR2 SDRAM Device Attributes General e ack 07 23 Minimum Clock Cycle at CL X 1 3 75ns 3D 24 Maximum Data Access Time from Clock at CL X 1 0 5ns 50 25 Minimum Clock Cycle Time at CL X 2 5 0ns 50 26 Maximum Data Access Time from Clock at CL X 2 0 6ns 60 27 Minimum Row Precharge Time trp 15ns 12 5ns 3C 32 28 Minimum Row Active to Row Active delay trap 7 5ns 1E 29 Minimum RAS to CAS delay trcp 15ns 12 5ns 3C 32 30 Minimum RAS Pulse Width tras 45ns 2D 31 Module Bank Density 1GB 01 32 Address and Command Setup Time Before Clock tis 0 20ns 0 17ns 20 17 33 Address and Command Hold Time After Clock tix 0 27ns 0 25ns 27 25 34 Data Input Setup Time Before Clock tps 0 10ns 0 05ns 10 05 35 Data Input Hold Time After Clock ton 0 17ns 0 12ns 17 12 36 Write Recovery Time twa 15 0ns 3C 37 Internal Write to Read Command delay twtr 7 5ns 1E 38 Internal Read to Precharge delay tare 7 5ns 1E 39 Reserved Undefined 00 REV 1 2 7 10 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Det
9. Note TCAsE Operating Temperature Ambient 0 to 95 C 1 2 3 TsTG Storage Temperature Plastic 55 to 100 C IL Short Circuit Output Current 5 to5 Ma Note 1 Case temperature is measured at top and center side of any DRAMs 2 tcase gt 85 C gt trer 3 9 us 3 All DRAM specification only support 0 C lt tcase lt 85 C DC Electrical Characteristics and Operating Conditions Tcase 0 C 85 C Vona 1 8V 0 1V Voo 1 8V 0 1V See AC Characteristics Symbol Parameter Min Max Units Notes VDD Supply Voltage 1 7 1 9 V 1 VDDQ Supply Voltage for Output 1 7 1 9 V 1 3 VDDL Supply Voltage for VDDQL 1 7 1 9 V VREF Input Reference Voltage 0 49VDDQ 0 51VDDQ Mv VTT Termination Voltage VREF 0 04 VREF 0 04 V 4 VIH DC Input High Logic1 Voltage VREF 0 125 VDDQ 0 3 V VIL DC Input Low Logic0 Voltage 0 3 VREF 0 125 V Note 1 Inputs are not recognized as valid until VREF stabilizes 2 VREF is expected to be equal to 0 5 V DDQ of the transmitting device and to track variations in the DC level of the same Peak to peak noise on VREF may not exceed 2 of the DC value 3 VDDQ tracks with VDD VDDL tracks with VDD 4 VTT of transmitting device track VREF of receiving device Environmental Parameters Symbol Parameter Rating Units Note Topr Module Operating Temperature Range ambient 0 to 55 C 3 Hopr Operating Humidity relative 10 to 90 TsTG Storage Temperature Plastic 55 to 100 C 1 Hs
10. 3 D2 DQ51 M 1 03 D6 DQ20 NM 1 04 DQ52 M 704 DQ21 P 1 05 DQ53 NM 1 05 DQ22 p 1 06 DQ54 N 1 06 DQ23 NMN O7 DQ55 M NO7 DQS3 M DQS7 M Das 3M pas7 V DM3 _ DM 7 p _ DM CS DOQS DQS DM CS DOS DQS DQ24 100 DQ56 NMN 1 00 DQ25 p 1 01 DQ57 1 01 DQ26 MV 1 02 DQ58 1 02 DQ27 NMN 1 03 D3 Da59 1 03 D7 DQ28 p 1 04 Da60 1 0 4 DQ29 W 1 05 DQ61 N 1 05 DQ30 WV 1 06 DQ62 W 1 06 DQ31 p _ O7 DQ63 N O7 Serial PD SCL gt wp ao A1 Met SDA do su d BAO BA2 M gt BAO BA2 SDRAMs D0 D7 AO0 A13 V A0 A13 SDRAMs D0 D7 RAS MN gt RAS SDRAMs D0 D7 CAS M gt CAS SDRAMs DO D7 VDDSPD SPR WE N gt WE SDRAMs DO D7 VDD VDDQ DO D7 CKEO _ CKE SDRAMs D0 D7 ODTo gt ODT SDRAMs D0 D7 V REF aa DO D7 vss F DO D7 REV 1 2 5 10 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram 2GB 2 Ranks 128Mx8 DDR2 SDRAMs Cel IXIr
11. 64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM elixir Serial Presence Detect Part 1 of 2 1GB 128Mx64 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 128Mx8 8Banks 8K Refresh 1 8V DDR2 SDRAMs with SPD E SPD Entry Value go pirat ty Note Byte Description PC2 5300 PC2 6400 PC2 5300 PC2 6400 3C AC 3C AC 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type DDR2 08 3 Number of Row Addresses on Assembly 14 OE 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Ranks 1 rank Height 30mm 60 6 Data Width of Assembly X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1 8V 05 9 DDR2 SDRAM Device Cycle Time at CL X 3ns 2 5ns 30 25 10 DDR2 SDRAM Device Access Time from Clock at CL X 0 45ns 0 4ns 45 40 11 DIMM Configuration Type Non parity ECC 00 12 Refresh Rate Type 7 8us 82 13 Primary DDR2 SDRAM Width X8 08 14 Error Checking DDR2 SDRAM Device Width Undefined 00 15 Reserved Undefined 00 16 DDR2 SDRAM Device Attributes Burst Length Supported 4 8 0c 17 DDR2 SDRAM Device Attributes Number of Device Banks 8 08 18 ae vera Device Attributes CAS Latencies 3 4 5 38 19
12. AMs FRONT 13335 5 250 13135 gt r S i 12895 lt 5 077 D id Q E N DAMOANNAONANNANA ANDORA NANANA CEDEN CANA Detail A _ Detail B 25 0 098 BACK 63 00 56 00 2 480 gt i k 2 165 gt SIDE O MEANAANANAAACANTANNANTENNAEATAETARNENEEA TEANN EENN J PE O C C Detail B 1 27 0 10 i 0 050 4 0 004 0 8 0 5 ee 0 031 4 0 02 gt il OGO000 1 00Pitch 0 039 0 059 0 004 Note All dimensions are typical with tolerances of 0 15 0 006 unless otherwise stated Units Millimeters Inches REV 1 2 17 10 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B Celixi r M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM Revision Log Rev Date 0 1 03 2008 1 0 04 2008 1 1 07 2008 1 2 10 2008 REV 1 2 10 2008 Preliminary Edition Official Release Revision update Add new part number Modification 18 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without noti
13. DM CS DAQS DAS DM CS DAQS DAS DM CS DAQS DAS DQ16 1 00 1 00 DQ48 M 1 00 700 DQ17 1 01 1 01 Da4g W 101 01 DQ18 N 1 02 1 02 DQ50 M 1 02 1 02 DQ19 1 03 D2 1 03 D10 DQ51 M 103 D6 03 D14 DQ20 M 1 04 1 0 4 DQ52 4 1 04 1 04 DQ21 NM 1 05 1 05 DQ53 M 1 05 1 05 DQ22 M 1 06 1 06 DQ54 M 1 06 06 DQ23 107 VO7 pas5s 1 07 VO7 Das3 DQS7 M DAS3 M DAS7Z M DM3 M DM7 M DM CS DAS DAS DM CS Das DQS DM CS Das DAS DM CS DAQS DAS Da2z4 1 00 00 DQ56 M 00 00 DQ25 M 1 01 01 DQ57 M 1 01 01 pa2z6 4 1 02 1 02 DQ58 M 1 02 1 02 DQ27 M 1 03 D3 03 D11 DQ59 M 1 03 D7 1 03 D15 DQ28 M 1 04 VO 4 DQ60 N 1 04 1 0 4 DQ29 M 1 05 1 05 DQ61 NM 1 05 1 05 DQ30 M 1 06 1 06 DQ62 M 1 06 1 0 6 DQ31 107 VO7 DQ63 NM VO7 07 BA0 BA2 M gt BAO BA2 SDRAMs D0 D15 A0 A13 W gt A0 A13 SDRAMs D0 D15 Serial PD RAS RAS SDRAMs D0 D15 scL VDDSPD SPD CAS M gt CAS SDRAMs D0 D15 l4 SDA WE WV gt gt WE SDRAMs D0 D15 WP al VDD VDDQ J DO D15 CKE0 gt CKE SDRAMs D0 D7 g CKE1 gt CKE SDRAMs D8 D15 SA0 SAI SPR y REF fe ey ODT0 gt ODT SDRAMs D0 D7 Vss _ _ _ D0 D15 ODT1 gt ODT SDRAMs D8 D15 REV 1 2 6 10 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G
14. M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B Celixi r M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE Based on 128Mx8 DDR2 SDRAM D die Features Performance PC2 5300 PC2 6400 Speed Sort 3C AC Unit DIMM CAS Latency 5 5 fck Clock Frequency 333 400 MHz tck Clock Cycle 3 2 5 ns f DQ DQ Burst Frequency 667 800 Mbps e JEDEC Standard 240 pin Dual In Line Memory Module e 128Mx64 and 256Mx64 DDR2 Unbuffered DIMM based on Elixir 128Mx8 DDR2 SDRAM D die component e Double Data Rate architecture two data transfer per clock cycle Differential bi directional data strobe DQS amp DQS e DQS is edge aligned with data for reads and is center aligned with data for writes e Differential clock inputs CK amp CK Intended for 333MHz 400MHz applications e Inputs and outputs are SSTL 18 compatible e Voo Vong 1 8V 0 1V e 7 8 us Max Average Periodic Refresh Interval Description Programmable Operation Device CAS Latency 3 4 5 Burst Length 4 8 e Auto Refresh CBR and Self Refresh Modes Automatic and controlled precharge commands e 14 10 1 Addressing row column rank 1GB e 14 10 2 Addressing row column rank 2GB e Serial Presence Detect e On Die Termination ODT OCD impedance adjustment e Gold contacts e SDRAMs in 60 ball BGA Package e RoHs Compl
15. M2Y2G64TU8HD5B 3C gt 4D325932473634545538484435422D33432020 M2Y2G64TU8HD5B AC gt 4D325932473634545538484435422D41 432020 M2Y2G64TU8HD6B 3C gt 4D325932473634545538484436422D33432020 M2Y2G64TU8HD6B AC 4D325932473634545538484436422D41 432020 REV 1 2 10 10 2008 pc2 s300 pce 6400 3C AC 06 36 3C 39 7F 80 18 14 22 1E 00 00 13 18 FE 7F7F7F0B00000000 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice IXIr M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B Cel Absolute Maximum Ratings Symbol Parameter Rating Units Vin Vout Voltage on any pin relative to Vss 0 5 to 2 3 V VDDQ Voltage on Vppq supply relative to Vss 0 5 to 2 3 V VDDaL Voltage on VppaL supply relative to Vss 0 5 to 2 3 V VDD Voltage on VDD supply relative to Vss 1 0 to 2 3 V Note Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability DC Operating Conditions Symbol Parameter Rating Units
16. Rate Type 7 8uS 82 13 Primary DDR2 SDRAM Width X8 08 14 Error Checking DDR2 SDRAM Device Width Undefined 00 15 Reserved Undefined 00 16 DDR2 SDRAM Device Attributes Burst Length Supported 4 8 oC 17 DDR2 SDRAM Device Attributes Number of Device Banks 8 08 18 eee coe Device Attributes CAS Latencies 3 4 5 38 19 DIMM Mechanical Characteristics x lt 4 10 mm 01 20 DDR2 SDRAM DIMM Type Information UDIMM 133 35mm 02 21 DDR2 SDRAM Module Attributes Normal DIMM 00 22 DDR2 SDRAM Device Attributes General E ee 07 23 Minimum Clock Cycle at CL X 1 3 75ns 3D 24 Maximum Data Access Time from Clock at CL X 1 0 5ns 50 25 Minimum Clock Cycle Time at CL X 2 5 0ns 50 26 Maximum Data Access Time from Clock at CL X 2 0 6ns 60 27 Minimum Row Precharge Time tpp 15ns 12 5ns 3C 32 28 Minimum Row Active to Row Active delay trrp 7 5ns 1E 29 Minimum RAS to CAS delay taco 15ns 12 5ns 3C 32 30 Minimum RAS Pulse Width tras 45ns 2D 31 Module Bank Density 1GB 01 32 Address and Command Setup Time Before Clock tis 0 20ns 0 17ns 20 17 33 Address and Command Hold Time After Clock ti 0 27ns 0 25ns 27 25 34 Data Input Setup Time Before Clock tps 0 10ns 0 05ns 10 05 35 Data Input Hold Time After Clock ton 0 17ns 0 12ns 17 12 36 Write Recovery Time twr 15 0ns 3C 37 Internal Write to Read Command delay twtr 7 5ns 1E 38 Internal Read to Precharge delay trate 7 5ns 1E 39 Reserved Undefined 00 REV 1 2 9 10 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP
17. ce
18. dge Active High Function The positive line of the differential pair of system clock inputs which drives the input to the on DIMM PLL All the DDR2 SDRAM address and control inputs are sampled on the rising edge of their associated clocks The negative line of the differential pair of system clock inputs which drives the input to the on DIMM PLL Activates the SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode CKE1 apply on 2GB UDIMM only Enables the associated SDRAM command decoder when low and disables the command decoder when high When the command decoder is disabled new commands are ignored but previous operations continue CS1 apply on 2GB UDIMM only When sampled at the positive rising edge of the clock RAS CAS WE define the operation to be executed by the SDRAM Reference voltage for SSTL 18 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity On Die Termination control signals ODT1 apply on 2GB UDIMM only Selects which SDRAM bank is to be active During a Bank Activate command cycle AO A13 defines the row address RAO RA13 when sampled at the rising clock edge During a Read or Write command cycle AO A9 defines the column address CA0 CA9 when sampled at the rising clock edge In addition to the column address AP is used to invoke Autoprecharge operat
19. ect Part 2 of 2 1GB elixir 128Mx64 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 128Mx8 8Banks 8K Refresh 1 8V DDR2 SDRAMs with SPD Serial PD Data Entry Hexadecimal SPD Entry Value Byte Description PC2 5300 PC2 6400 3C AC The number below a A decimal point of tRC and 40 Extension of Byte 41 trc and Byte 42 trec tRFC are 0 tRFC is less than 256ns 41 Minimum Core Cycle Time trc 60 0ns 57 5ns 42 Min Auto Refresh Command Cycle Time tarc 127 5ns 43 Maximum Clock Cycle Time tck 8 0ns 44 Max DQS DQ Skew Factor toas 0 24ns 0 20ns 45 Read Data Hold Skew Factor tons 0 34ns 0 30ns 46 PLL Relock Time Undefined 46 61 Reserved Undefined 62 SPD Revision 1 3 63 Checksum for bytes 0 62 Checksum Data 64 71 Manufacture s JEDEC ID Code NANYA 72 Module Manufacturing Location Manufacturing Code Module Part Number in 73 91 Module Part number ASCII 92 255 Reserved Undefined Note 1 M2Y1G64TU88D0B 3C gt 4D325931473634545538384430422D33432020 M2Y1G64TU88D0B AC gt 4D325931473634545538384430422D41 432020 M2Y1G64TU88D4B 3C gt 4D325931473634545538384434422D33432020 M2Y1G64TU88D4B AC gt 4D325931473634545538384434422D41 432020 M2Y1G64TU88D5B 3C 4D325931473634545538384435422D33432020 M2Y1G64TU88D5B AC gt 4D325931473634545538384435422D41 432020 M2Y1G64TU88D6B 3C gt 4D325931473634545538384436422D33432020 M2Y1G64TU88D6B AC gt 4D325931473634545538384436422D4 1432020 M2Y1G64TU88D7B AC 4D325931473634545538384437422D4 1432020
20. eens Differential Clock Inputs DQ0 DA63 CKEO CKE1 Clock Enable DQS0 DQS8 RAS Row Address Strobe DM0 DM8 CAS Column Address Strobe DAS0 DQS8 WE Write Enable VDD CS0 CS1 Chip Selects VREF A0 A9 A0 A13 Address Inputs VDDSPD A10 AP Column Address Input Auto precharge VSS BAO BA2 SDRAM Bank Address Inputs SCL RESET Reset pin SDA ODTO ODT1 On die termination control lines SAO SA2 NC No Connect Note ODT1 CKE1 and CS1 are only support in 2GB module type REV 1 2 10 2008 2 IXIr Organization Leads Power Note 128Mx64 GOLD 1 8V 256Mx64 Data input output Bidirectional data strobes Input Data Mask Differential data strobes Power 1 8V Ref Voltage for SSTL_18 inputs Serial EEPROM positive power supply Ground Serial Presence Detect Clock Input Serial Presence Detect Data input output Serial Presence Detect Address Inputs NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B Celi Pinout Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 VREF 42 NC 82 V
21. hanging once per clock cycle Operating Current one bank active read precharge Burst 2 Trc Tre MIN CL 2 5 Tck Tck MIN IOUT OMa address and control inputs changing once per clock cycle Precharge Power Down Standby Current all banks idle power down mode CKE lt VIL MAX Tck Tck MIN Idle Standby Current CS gt VIH MIN all banks idle CKE gt VIH MIN Tck Tck MIN address and control inputs changing once per clock cycle Precharge Quiet Standby Current All banks idle CS is HIGH CKE is HIGH tcx tck miny Other control and address inputs are stable Data bus inputs are floating Active Power Down Current All banks open Tck Tck MIN CKE is LOW Other control and address inputs are STABLE Data bus inputs are floating MRS A12 bit is set to low Fast Power down Exit Active Power Down Current All banks open Tck Tck MIN CKE is LOW Other control and address inputs are STABLE Data bus inputs are floating MRS A12 bit is set to high Slow Power down Exit Active Standby Current one bank active precharge CS gt VIH MIN CKE gt VIH MIN Trc Tras MAX Tck Tck MIN DQ DM and DQS inputs changing twice per clock cycle address and control inputs changing once per clock cycle Operating Current one bank Burst 2 writes continuous burst address and control inputs changing once per clock cycle DQ and DQS inputs changing twice per clock cycle CL 2 5 Tck Tck MIN
22. iance M2Y1G64TU88D0B M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B and M2Y1G64TU88D7B are 240 Pin Double Data Rate 2 DDR2 Synchronous DRAM Unbuffered Dual In Line Memory Module UDIMM organized as one rank 128Mx64 and two ranks 256Mx64 high speed memory array M2Y1G64TU88DOB M2Y1G64TU88D4B M2Y1G64TU88D5B M2Y1G64TU88D6B and M2Y1G64TU88D7B use eight 128Mx8 DDR2 SDRAMs and M2Y2G64TU8HDOB M2Y2G64TU8HD4B M2Y2G64TU8HD5B and M2Y2G64TU8HD6EB use sixteen 128Mx8 DDR2 SDRAMs in BGA packages These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR2 SDRAM DIMMs provide a high performance flexible 8 byte interface in a 5 25 long space saving footprint The DIMM is intended for use in applications operating up to 333MHz or 400MHz clock speeds and achieves high speed data transfer rates of up to 667Mbps or 800Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs A0 A13 and I O inputs BAO BA1 and BA2 using the mode register set cycle The DIMM uses serial presence detect implemented via a serial 2 048 bit EEPROM using a standard IIC protocol The first 128 bytes of serial PD data are programmed and locked during module assembly The remaining 128 bytes a
23. ion at the end of the Burst Read or Write cycle If AP is high Autoprecharge s selected and BAO BA1 defines the bank to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BAO BA1 to control which bank s to precharge If AP is high all 4 banks will be precharged regardless of the state of BAO BA1 If AP is low then BAO BA1 are used to define which bank to pre charge Data and Check Bit Input Output pins Power and ground for the DDR2 SDRAM input buffers and core logic Data strobe for input and output data The data write masks associated with one data byte In Write mode DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no effect DM8 is associated with check bits CBO CB7 and is not used on x64 modules Address inputs Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address This bi directional pin is used to transfer data into or out of the SPD EEPROM A resistor must be connected from the SDA bus line to V DD to act as a pull up This signal is used to clock data into and out of the SPD EEPROM A resistor may be connected from the SCL bus time to V DD to act as a pull up Serial EEPROM positive power supply 4 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifica
24. k MIN IOUT OMa address and control inputs changing once per clock cycle Precharge Power Down Standby Current all banks idle power down mode CKE lt VIL MAX Tck Tck MIN Idle Standby Current CS gt VIH MIN all banks idle CKE gt VIH MIN Tck Tck MIN address and control inputs changing once per clock cycle Precharge Quiet Standby Current All banks idle CS is HIGH CKE is HIGH tex tex mn Other control and address inputs are stable Data bus inputs are floating Active Power Down Current All banks open Tck Tck MIN CKE is LOW Other control and address inputs are STABLE Data bus inputs are floating MRS A12 bit is set to low Fast Power down Exit Active Power Down Current All banks open Tck Tck MIN CKE is LOW Other control and address inputs are STABLE Data bus inputs are floating MRS A12 bit is set to high Slow Power down Exit Active Standby Current one bank active precharge CS gt VIH MIN CKE gt VIH MIN Tre Tras MAX Tck Tck MIN DQ DM and DQS inputs changing twice per clock cycle address and control inputs changing once per clock cycle Operating Current one bank Burst 2 writes continuous burst address and control inputs changing once per clock cycle DQ and DQS inputs changing twice per clock cycle CL 2 5 Tck Tck MIN Operating Current one bank Burst 2 reads continuous burst address and control inputs changing once per clock cycle DQ a
25. n n ns j 2 5Tck Tac min 2 Tacan tl ns 3 Nck 8 Nck 2 Nck 0 12 ns 0 12 ns Tis Tck Tih ns 127 5 ns 3 9 us 7 8 us NANYA TECHNOLOGY CORP IXIr M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B Celi Package Dimensions 1GB 1 Rank 128Mx8 DDR2 SDRAMs FRONT 13335 i 5 250 13135 f D S 12895 lt 5 077 Y i N pmm S E Detail A Detail B 025 0 098 BACK 63 00 55 00 2 480 2 165 SIDE C 3 18 Max 0 125 Detail B 1 27440 10 l 0 050 0 004 0 8 4 0 5 a BECO gt 40083114 0 02 OMMO000 1 00 Pitch 0 039 0 059 0 004 Note All dimensions are typical with tolerances of 0 15 0 006 unless otherwise stated Units Millimeters Inches REV 1 2 16 10 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B Celi Package Dimensions 2GB 2 Ranks 128Mx8 DDR2 SDR
26. nd DQS outputs changing twice per clock cycle CL 2 5 Tck Tck MIN IOUT OMa Auto Refresh Current Tre Trfc MIN Self Refresh Current CKE lt 0 2V Operating Current four bank four bank interleaving with BL 4 address and control inputs randomly changing 50 of data changing at every transfer Trc Trc min IOUT OMa PC2 5300 880 792 88 572 440 246 97 528 924 1056 1408 97 1628 PC2 6400 1012 924 88 660 484 264 97 616 1056 1188 1540 97 1804 Note Module IDD was calculated from component IDD It may differ from the actual measurement REV 1 2 12 10 2008 elixir Unit NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM Operating Standby and Refresh Currents Tcase 0 C 85 C Vooo Von 1 8V 0 1V 2GB 2 Ranks 128Mx8 DDR2 SDRAMs Symbol DDO DD1 DD2P DD2N DD2Q DD3PF DD3PS DD3N DD4W DD4R DDS DD6 DD7 Parameter Condition Operating Current one bank active precharge Tre Tre MIN Tck Tck MIN DQ DM and DQS inputs changing twice per clock cycle address and control inputs c
27. ps Tip Minimum half clk period for any given cycle Min Tch abs _ Min Tch abs ps defined by clk high Tch or clk low Tcl time Tcl abs Tcl abs Tqhs Data hold Skew Factor 340 300 ps Tah Data output hold time from DQS tup tqus z Thp Tqhs ps Trpre Read preamble 0 9 1 1 0 9 1 1 Tck Trpst Read postamble 0 4 0 6 0 4 0 6 Tck Trrd Active bank A to Active bank B command 7 5 7 5 ns Taw Te Window for 1KB page size 37 5 35 i ns Teed CAS to CAS 2 2 Nck Twr Write recovery time without Auto Precharge 15 15 ns Tdal Auto precharge write recovery precharge time WR tnRP WR tnRP Nck Twir Internal write to read command delay 7 5 7 5 ns Trip Internal read to precharge command delay 7 5 7 5 ns Tcke CKE minimum pulse width 3 3 Neck Txsnr Exit self refresh to a Non read command Trfc 10 Trfc 10 ns Txsrd Exit self refresh to a Read command 200 200 Neck T aul ee power down to any Non read 2 7 2 Nek REV 1 2 14 10 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B Cel M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module Tcase 0 C 85 C Vona 1 8V 0 1V Voo 1 8V 0 1V See AC Characteristics Part 2 of 2 Symbol
28. re available for use by the customer REV 1 2 1 10 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B Celi M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM Ordering Information Part Number Speed M2Y1G64TU88D0B 3C 333MHz 3 00ns CL 5 DDR2 667 PC2 5300 M2Y1G64TU88D0B AC 400MHz 2 50ns CL 5 DDR2 800 PC2 6400 M2Y1G64TU88D4B 3C 333MHz 3 00ns CL 5 DDR2 667 PC2 5300 M2Y1G64TU88D4B AC 400MHz 2 50ns CL 5 DDR2 800 PC2 6400 M2Y1G64TU88D5B 3C 333MHz 3 00ns CL 5 DDR2 667 PC2 5300 M2Y1G64TU88D5B AC 400MHz 2 50ns CL 5 DDR2 800 PC2 6400 M2Y1G64TU88D6B 3C 333MHz 3 00ns CL 5 DDR2 667 PC2 5300 M2Y1G64TU88D6B AC 400MHz 2 50ns CL 5 DDR2 800 PC2 6400 M2Y1G64TU88D7B AC 400MHz 2 50ns CL 5 DDR2 800 PC2 6400 M2Y2G64TU8HDOB 3C 333MHz 3 00ns CL 5 DDR2 667 PC2 5300 M2Y2G64TU8HDOB AC 400MHz 2 50ns CL 5 DDR2 800 PC2 6400 M2Y2G64TU8HD4B 3C 333MHz 3 00ns CL 5 DDR2 667 PC2 5300 M2Y2G64TU8HD4B AC 400MHz 2 50ns CL 5 DDR2 800 PC2 6400 M2Y2G64TU8HD5B 3C 333MHz 3 00ns CL 5 DDR2 667 PC2 5300 M2Y2G64TU8HD5B AC 400MHz 2 50ns CL 5 DDR2 800 PC2 6400 M2Y2G64TU8HD6B 3C 333MHz 3 00ns CL 5 DDR2 667 PC2 5300 M2Y2G64TU8HD6B AC 400MHz 2 50ns CL 5 DDR2 800 PC2 6400 Pin Description
29. ss 121 Vss 162 NC 202 DM4 2 Vss 43 NC 83 Das4 122 DQ4 163 Vss 203 NC 3 DQO 44 Vss 84 DQS4 123 DQ5 164 NC 204 Vss 4 DQ1 45 NC 85 Vss 124 Vss 165 NC 205 DQ38 5 Vss 46 NC 86 DQ34 125 DMO 166 Vss 206 DQ39 6 DASO 47 Vss 87 DQ35 126 NC 167 NC 207 Vss 7 DQSO 48 NC 88 Vss 127 Vss 168 NC 208 DQ44 8 Vss 49 NC 89 DQ40 128 DQ6 169 Vss 209 DQ45 9 DQ2 50 Vss 90 DQ41 129 DQ7 170 Vopa 210 Vss 10 DQ3 51 Vppa 91 Vss 130 Vss 171 NC CKE1 211 DM5 11 Vss 52 CKEO 92 DQs5 131 DQ12 172 Voo 212 NC 12 DQ8 53 Vop 93 DQS5 132 DQ13 173 NC 213 Vss 13 DQ9 54 BA2 94 Vss 133 Vss 174 NC 214 DQ46 14 Vss 55 NC 95 DQ42 134 DM1 175 Vopa 215 DQ47 15 Das1 56 Vopa 96 DQ43 135 NC 176 A12 216 Vss 16 DQS1 57 A11 97 Vss 136 Vss 177 A9 217 DQ52 17 Vss 58 A7 98 DQ48 137 CK1 178 Voo 218 DQ53 18 NC 59 Vop 99 DQ49 138 CKT 179 A8 219 Vss 19 NC 60 A5 100 Vss 139 Vss 180 A6 220 CK2 20 Vss 61 A4 101 SA2 140 DQ14 181 Vopa 221 CK2 21 DQ10 62 Vppa 102 NC 141 DQ15 182 A3 222 Vss 22 DQ11 63 A2 103 Vss 142 Vss 183 A1 223 DM6 23 Vss 64 Vop 104 DQs6 143 DQ20 184 Voo 224 NC 24 DQ16 KEY 105 DQS6 144 DQ21 KEY 225 Vss 25 DQ17 65 Vss 106 Vss 145 Vss 185 CKO 226 DQ54 26 Vss 66 Vss 107 DQ50 146 DM2 186 CKO 227 DQ55 27 DQs2 67 VDD 108 DQ51 147 NC 187 VDD 228 Vss 28 DQS2 68 NC 109 Vss 148 Vss 188 AO 229 DQ60 29 Vss 69 VDD 110 DQ56 149 DQ22 189 Voo 230 DQ61 30 DQ18 70 A10 AP 111 DQ57 150 DQ23 190 BA1 231 Vss 31 DQ19 71 BAO 112 Vss 151 Vss 191 Vopa 232 DM7 32 Vss 72 VDDQ 113 DQs7 152 DQ28 192 RAS 233 NC 33 DQ24 73 WE
30. tg Storage Humidity without condensation 5 to 95 1 PBAR Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stresses greater than those listed may cause permanent damage to the device This is a tress rating only and device functional operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Up to 9850 ft 3 The component maximum case temperature shall not exceed the value specified in the component spec REV 1 2 11 10 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM Operating Standby and Refresh Currents Tcase 0 C 85 C Vooo Voo 1 8V 0 1V 1GB 1 Rank 128Mx8 DDR2 SDRAMs Symbol DDO DD1 DD2P DD2N DD2Q DD3PF DD3PS DD3N DD4w DD4R DDS DD6 DD7 Parameter Condition Operating Current one bank active precharge Tre Tre MIN Tck Tck MIN DQ DM and DQS inputs changing twice per clock cycle address and control inputs changing once per clock cycle Operating Current one bank active read precharge Burst 2 Trc Tre MIN CL 2 5 Tck Tc
31. tions without notice M2Y1G64TU88DOB M2Y2G64TU8HDOB M2Y1G64TU88D4B M2Y2G64TU8HD4B M2Y1G64TU88D5B M2Y2G64TU8HD5B M2Y1G64TU88D6B M2Y2G64TU8HD6B M2Y1G64TU88D7B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram 1GB 1 Rank 128Mx8 DDR2 SDRAMs elixir CSO DQS 0 M DQS4 M DQS0 M DQS4M DM 0 N DM 4 N DM CS DQS DQS DM CS DQS DAS DQ0 VW 1 00 DQ32 W 1 00 DQ1 101 DQ33 M 1 0 1 DQ2 N4 1 02 DQ34 W 0 2 Da3s 4 v0 3 DO DQ35 W 1 03 D4 DQ4 N4_ 1 04 DQ36 N 1 0 4 DQ5 NWH 1 05 DQ37 V VO 5 DQ6 V 1 06 DQ38 M 1 06 DQ7 N O7 DQ39 NM O7 DQS1 M DQS5 M DQS1 M DQS5 M DM1i DM5 p _ DM CS DQS DAS DM CS DQS DQS DQ8 V 1 00 DQ40 M 0 0 DQ9 M 101 DQ41 N 1 01 DQI10 M 102 DQ42 NM 102 DQ11 M 103 D1 DQ43 NMN 103 D5 pai2z r 1 04 DQ 44 1 04 pai3s VW 1 05 DQ45 N V0 5 pa14 rv 1 06 DQ46 M V0 6 pa1i5 V O7 DQ47 N O7 DQS2 M DQS6 M DQS2 M DQS6 M DM 2 N DM 6 p _ B CS DEE BES DM CS DQS DQS DQ16 M 1 00 DQ48 N 1 00 DQ17Z M 1 01 DQ49 N 01 DQ18 WM 1 02 DQ50 M 1 02 DQ19 M 1 0
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