Transcend 256MB SDRAM PC133 Unbuffer Non-ECC Memory
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1. ICS2 CLKO CLK2 A0 A12 x a i BAO BA1 DQ0 DQ7 DQ0 DQ7 RAS CAS SDRAM INE Serial EEPROM SCL SCL SDA SDA AO A1 A2 SA0 SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 4 TS32MLS64V6F 168PIN PC133 Unbuffered DIMM 256MB With 32M X 8 CL3 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 8 W Short circuit current los 50 mA Operating Temperature TA 0 70 C Note Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VI2. Output data hold time CAS latency 2 toH 2 7 ns 2 CLK high pulse width tCH 2 5 ns 3 CLK low pulse width tCL 2 5 ns 3 Input setup time tss 1 5 ns 3 Input hold time tSH 0 8 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output in Hi Z CAS latency 2 tSHZ 5 4 ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8 168PIN PC133 Unbuffered DIMM TS32M LS64V6F 256MB With 32M X 8 CL3 SIMPLIFIED TRUTH TABLE COMMAND CKEn 1 CKEn CS RAS CAS WE DQM BAo 1 A1o AP A11 A12 Ao A9 Note Register Mode Register Set H x L L L L x OP CODE 12 Refresh Auto Refresh H 3 Self Entry H L L L E fiH Xx A 3 Refresh Exit L H H H 3 L l H X X X y x 3 Bank Active amp Row Addr H x L L H H x v Row Address Read amp Auto Precharge Disable L Column 4 Column H X L H L H x V Address Address Auto Precharge Enable H Ao As 4 5 Write amp Auto Precharge Disable L Column 4 Column Muto Piech Enabi H X L H L L x V Address Address uto Precharge Enable H Ao As 4 5 Burst Stop H
3. Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time Raatin 2 ns 1 tRAS max 100 us Row cycle time tRc min 65 ns 1 Last data in to new col Address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to Active delay tDAL 2CLK tRP 7 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccD min 1 CLK 3 Number of valid output data CAS latency 2 1 aA 4 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 168PIN PC133 Unbuffered DIMM TS32M LS64V6F 256MB With 32M X 8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Min Max Unit Note CLK cycle time CAS latency 2 tcc 3 1000 I 1 CLK to valid output delay CAS latency 2 tSAC 5 4 ns 1 2
4. be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc 9 TS32MLS64V6F Serial Presence Detect Specification 168PIN PC133 Unbuffered DIMM 256MB With 32M X 8 CL3 Serial Presence Detect Byte No Function Described Standard Vendor Part Specification 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly 13 OD 4 of Column Addresses on this Assembly 10 OA 5 of Module Banks on this Assembly 1 bank 01 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 15 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC None 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width 64bit 00 15 Min Clock Delay Back to Back Random Address 1
5. 132 A13 07 DQ4 49 Vcc 91 DQ36 133 Vcc 08 DQ5 50 NC 92 DQ37 134 NC 09 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 Vss 54 Vss 96 Vss 138 Vss 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 Vcc 101 DQ45 143 Vcc 18 Vcc 60 DQ20 102 Vcc 144 DQ52 19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 Vref 104 DQ47 146 Vref 21 CBO 63 CKE1 105 CB4 147 REGE 22 CB1 64 Vss 106 CB5 148 Vss 23 Vss 65 DQ21 107 Vss 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 Vcc 68 Vss 110 Vcc 152 Vss 27 WE 69 DQ24 111 CAS 153 DQ56 28 DQMO 70 DQ25 112 DQM4 154 DQ57 29 DQM1 71 DQ26 113 DQM5 155 DQ58 30 CSO 72 DQ27 114 CS1 156 DQ59 31 NC 73 Vcc 115 RAS 157 Vcc 32 Vss 74 DQ28 116 Vss 158 DQ60 33 AO 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 AG 78 Vss 120 A7 162 Vss 37 A8 79 CLK2 121 AQ 163 CLK3 38 A10 AP 80 NC 122 BAO 164 NC 39 BA1 81 NC 123 A11 165 SAO 40 Vcc 82 SDA 124 Vcc 166 SA1 41 Vcc 83 SCL 125 CLK1 167 SA2 42 CLKO 84 Vcc 126 A12 168 Vcc Please refer Block Diagram Transcend information Inc 3 168PIN PC133 Unbuffered DIMM TS32M LS64V6F 256MB With 32M X 8 CL3 Block Diagram A0 A12 A0 A12 A0 A12 BAO BA1 a BAO BA1 BAO BA1 BAO BA1 DQ0 DQ63 DQ0 DQ7 DQ0 DQ7 DQO0 DQ7 RAS A ne RAS ICAS ICAS SDRAM ICAS SDRAM IWE
6. H 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4 V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current Iu 10 10 uA 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs CAPACITANCE Vpp 3 3V Ta 23 C f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Unit Input capacitance Ao A12 BAo BA1 CIN1 30 40 pF Input capacitance RAS CAS WE CIN2 30 40 pF Input capacitance CKEO CIN3 30 40 pF Input capacitance CLKO CLK2 CIN4 25 30 pF Input capacitance CSO CS2 CIN5 16 25 pF Input capacitance DQM0 DQM 7 CIN6 8 10 pF Data input output capacitance DQ0 DQ63 COUT1 6 8 pF DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition CAS Latency Value Typ Unit Note Transcend information Inc 168PIN PC133 Unbuffered DIMM TS32M LS64V6F 256MB With 32M X 8 CL3 Operating Current Burst Length 1 em A cc1 i m One Bank Active TBE Ren loL OmA Precharge Standby Current ICc2P CKEsViL max tcc 10ns 16 mA in power down mode Icc2PS CKE a
7. N TOCOCOCOOUCUCO COONAN m COONAN TOCOCOCCOUCUCOo COONAN OMR R Raa MRR a a a R aa a a ag DODANAONAOATONONANNNOONNNNN TO PCB 09 7312 gt TS32MLS64V6F 168PIN PC133 Unbuffered DIMM 256MB With 32M X 8 CL3 Pin Identification Symbol Function AO A12 BAO BA1 Address input Dimensions Side Millimeters Inches A 133 35 0 40 5 250 0 016 B 65 67 2 585 C 23 49 0 925 D 8 89 0 350 E 3 00 0 118 F 29 21 0 20 1 150 0 008 G 19 80 0 788 H 15 80 0 622 1 27 0 10 0 050 0 004 Refer Placement Transcend information Inc DQO0 DQ63 Data Input Output CLKO CLK2 Clock Input CKEO Clock Enable Input CSO CS2 Chip Select Input RAS Row Address Strobe ICAS Column Address Strobe IWE Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Volt Power Supply Vss Ground NC No Connection 168PIN PC133 Unbuffered DIMM TS32M LS64V6F 256MB With 32M X 8 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 Vss 43 Vss 85 Vss 127 Vss 02 DQO 44 NC 86 DQ32 128 CKEO 03 DQ1 45 ICS2 87 DQ33 129 CS3 04 DQ2 46 DQM2 88 DQ34 130 DQM6 05 DQ3 47 DQM3 89 DQ35 131 DQM7 06 Vcc 48 NC 90 Vcc
8. TS32MLS64V6F Description The TS32MLS64V6F is a 32M x 64bits Synchronous Dynamic RAM high density for PC 133 The TS32MLS64V6F consists of 8pcs CMOS 32Mx8 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS32MLS64V6F is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e RoHS compliant products e Performance Range PC 133 e Conformed to JEDEC Standard Spec e Burst Mode Operation e Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e Allinputs are sampled at the positive going edge of the system clock Transcend information Inc 168PIN PC133 Unbuffered DIMM 256MB With 32M X 8 CL3 Placement COONAN TOCOCOCCOUCCO COON OCCA ACACIA OMR RROA MRR a R aa a a ag DODANAONAONTONONANONTOONNN
9. X L H H L X X 6 Precharge Bank Selection V L Both Banks 9 X L i a L x X H X Clock Suspend or Entry Active Power Down H L H x Xx x X L V V V x Exit L H x x x x X Precharge Power Entry H x x x Down Mode H L x L H H H X Ext H x x x L H X L V V V DQM H X 7 No Operation C d peration Comman x H x x x x L H H H V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A12 BAo BA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BA1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BA are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA1 are ignored and both banks are selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can
10. clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Prec All Auto Prec OE R W Burst 23 SDRAM Cycle Time 2 highest CL 10ns AO 24 SDRAM Access from Clock 2 highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 16ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 256MB 40 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 62 SPD Data Revision Code JEDEC2 02 63 Checksum for Bytes 0 62 C2 C2 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location T 54 73 90 Manufacturers Part Number TS32MLS64V6F 54 53 33 32 4D 4C 53 36 34 56 36 46 Transcend information Inc 10 168PIN PC133 Unbuffered DIMM TS32M LS64V6F 256MB With 32M X 8 CL3 20 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufactory Variable 95 98 _ Assembly Serial Number By Manufactory Variable 99 125 Manu
11. facturer Specific Data 0 126 Intel Specification Frequency 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 3 Clock 0 3 F6 128 Unused Storage Locations Open FF Transcend information Inc 11
12. mp CLK lt ViL max tcc 16 Sea pch Sonate re ehenged one dene diting SOK 160 Precharge Standby Current mA in non power down mode IccoNS CKE2VIH min CLK lt VIL max tcc lt 80 Input signals are stable Active Standby Current Icc3P CKE lt ViL max tcc 10ns 48 HR in power down mode Icc3PS_ ICKE amp CLK lt ViL max tcc 48 Active Standby Current Icc3N CKE2VIH min CS2ViH min tcc 10ns 240 Input signals are changed one time during 30ns in non power down mode Sk Bank Acti ON Ral AGING Icc3NS CKE gt ViH min CLK lt ViL max tec 200 Input signals are stable loL omA Operating Current Icc4 Page Burst 3 880 mA 1 CURO teco 2CLKs Refresh Current ICC5 tRC2tRC min 1600 mA 2 C 24 Self Refresh Current ICC6 CKE lt 0 2V mA L 12 Note 1 Measured with outputs open 2 Refresh period is 64ms 3 Unless otherwise noticed input swing level is CMOS VIH VIL VDDOQ VSSQ Transcend information Inc 6 TS32MLS64V6F 168PIN PC133 Unbuffered DIMM 256MB With 32M X 8 CL3 AC OPERATING TEST CONDITIONS voo 3 3V 0 3V TA 0 to 70 C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 O 3 3V Vit 1 4V Output Vos eae love ama Output Q _Z0 50 Ohm e
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