Transcend 256MB SDRAM PC100 Unbuffer Non-ECC Memory
Contents
1. PCB 09 7309 TS32MLS64V8D 168PIN PC100 Unbuffered DIMM 256MB With 16M X 8 CL3 Pin Identification Symbol Function A0 A11 BAO BA1 Address input Dimensions Side Millimeters Inches A 133 35 0 40 5 250 0 016 B 65 67 2 585 C 23 49 0 925 D 8 89 0 350 E 3 00 0 118 F 29 21 0 20 1 150 0 008 G 19 80 0 788 H 15 80 0 622 1 27 0 10 0 050 0 004 Refer Placement Transcend information Inc DQ0 DQ63 Data Input Output CLKO CLK3 Clock Input CKEO CKE1 Clock Enable Input CS0 CS3 Chip Select Input RAS Row Address Strobe ICAS Column Address Strobe IWE Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection 168PIN PC100 Unbuffered DIMM T2. buffers with Tri State outputs 4 Dout is disabled OV lt VOUT lt VDDQ CAPACITANCE TA 25 C f 1MHz Parameter Symbol Min Max Unit Input capacitance Ao A11 BAo 1 CIN1 60 90 pF Input capacitance RAS CAS WE CIN2 60 90 pF Input capacitance CKEO CKE1 CIN3 35 55 pF Input capacitance CLKO CLK3 CIN4 25 35 pF Input capacitance CSO CS3 CIN5 25 35 pF Input capacitance DQM0 DQM 7 CIN6 15 25 pF Data input output capacitance DQ0 DQ63 Cour 10 20 pF Transcend information Inc 5 168PIN PC100 Unbuffered DIMM TS32MLS64V8D 256MB With 16M X 8 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition CAS Latency Value Unit Note Operating Current Icc1 Burst Length 1 1120 mA 1 One Bank Active tRC gt tRCc min loL OmA Precharge Standby Current jIcc2P CKE lt ViL max tcc 15ns 16 mA iA power down mode Icc2PS CKE amp CLK lt VIL max tcc 16 Precharge Standby Current ICcC2N CKE ViH min CS ViH min tcc 15ns 240 mA in non power down mode Input signals are changed one time during 30ns Icc2NS_ gt CLKxViL max tcc lt 112 Input signals are stable Active Standby Current Icc3P CKEsViIL max tcc 15ns 80 mA in Power dowm mode CKE amp CLKsViL max tcc 80 CKE ViH min CS ViH min tcc 15ns 480 mA Input signal
3. h d time during 30 Active Standby Current nput signals are Changed one time during ns 55d in non power down mode _ One Bank Active IccaNS CKE2VIH min CLK lt VIL max tcc Input signals are stable Operating Current Icc4 loL 0 mA 3 1 240 mA 1 Bust Mode Page Burst tccp 2CLKs 2 1 160 Refresh Current Icc5 tRC2tRC min 3 200 mA 2 Self Refresh Current cce CKE lt 0 2V 24 mA Note 1 Measured with outputs open 2 Refresh period is 64ms Transcend information Inc 6 168PIN PC100 Unbuffered DIMM TS32MLS64V8D 256MB With 16M X 8 CL3 AC OPERATING TEST CONDITIONS voo 3 3V 0 3V 0 to 70 C Parameter vau t AC Input levels VIH VIL 2 4 0 4 Input timing measurement reference level Input rise and fall time tr tf 1 1 Output timing measurement reference level Output load condition See Fig 2 3 3V Vit 1 4V 1200 Ohm 50 2 4 2 Output 4 Z0 50 Ohm Q9 Vo DC 0 4V lo 2mA 80pF LL 870 Ohm Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 20 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time tRAS min 50 ns 1 tRAS max 100 us Row cycle time tRC min 70
4. 26 A12 168 Vcc Please refer Block Diagram Transcend information Inc 3 168PIN PC100 Unbuffered DIMM TS32MLS64V8D 256MB With 16M X 8 CL3 Block Diagram 11 A0 A11 A0 A11 BAO BA1 BAO BA1 290 2063 mE DQ0 DQ7 um DQ0 DQ7 IRAS a mee ICAS 16Mx8 icas _16 8 E eas 16Mx8 p an SDRAM UE SDRAM mai WE SDRAM CSO EET ES IS xg us SY CKEO mi CKE Q gd E 8 g DOM2 DQM3 i ICS2 ie A0 A11 A0 A11 mE ann Ho anne ICAS SDRAM yeas SDRAM aioe SDRAM cs o Hes as g CKE 5 CKE 9 d A0 A11 BAO BA1 BAO BA1 BAO BA1 BAO BA1 A EH DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 a i IRAS IRAS IRAS IRAS icas SDRAM B s SORAN CAS SDRAM CAS an L ANE zB 3 SHE J CKE1 E A0 A11 BAO BA1 DQ0 DQ7 RAS 11 AO A11 1 11 BAO BA1 DQ0 DQ7 silt asane Heas a ANE E ICS DQM6 DQM7 CLK2 CLK3 Serial EEPROM SCL SCL SDA SDA 1 2 SAO SA1S 2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend informa
5. S32MLS64V8D 256MB With 16M X 8 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 Vss 43 Vss 85 Vss 127 Vss 02 DQO 44 NC 86 DQ32 128 03 DQ1 45 ICS2 87 DQ33 129 CS3 04 DQ2 46 DQM2 88 DQ34 130 DQM6 05 DQ3 47 DQM3 89 DQ35 131 DQM7 06 Vcc 48 NC 90 Vcc 132 A13 07 DQ4 49 Vcc 91 DQ36 133 Vcc 08 DQ5 50 NC 92 DQ37 134 NC 09 DQ6 51 NC 93 DQ38 135 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 Vss 54 Vss 96 Vss 138 Vss 13 DQ9 55 DQ16 97 DQ41 139 0048 14 DQ10 56 DQ17 98 DQ42 140 0049 15 0011 57 0018 99 0043 141 00950 16 0012 58 0019 100 0044 142 0051 17 0013 59 Vcc 101 DQ45 143 Vcc 18 Vcc 60 DQ20 102 Vcc 144 DQ52 19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 Vref 104 DQ47 146 Vref 21 CBO 63 CKE1 105 CB4 147 REGE 22 CB1 64 Vss 106 CB5 148 Vss 23 Vss 65 DQ21 107 Vss 149 DQ53 24 NC 66 DQ22 108 NC 150 0054 25 67 0023 109 NC 151 0055 26 Vcc 68 Vss 110 Vcc 152 Vss 27 ANE 69 DQ24 111 CAS 153 DQ56 28 DQMO 70 DQ25 112 DQM4 154 DQ57 29 DQM1 71 DQ26 113 DQM5 155 DQ58 30 CSO 72 DQ27 114 CS1 156 0959 31 73 Vcc 115 RAS 157 Vcc 32 Vss 74 DQ28 116 Vss 158 DQ60 33 AO 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 160 0062 35 4 77 0031 119 161 00963 36 78 Vss 120 A7 162 Vss 37 A8 79 CLK2 121 AQ 163 CLK3 38 A10 AP 80 NC 122 164 NC 39 BA1 81 NC 123 11 165 40 Vcc 82 SDA 124 Vcc 166 SA1 41 Vcc 83 SCL 125 CLK1 167 SA2 42 CLKO 84 Vcc 1
6. TS32MLS64V8D 168PIN PC100 Unbuffered DIMM 256MB With 16M X 8 CL3 1Description The TS32MLS64V8D is a 32M bit x 64 Synchronous Dynamic RAM high density for PC 100 The TS32MLS64V8D consists of 16pcs CMOS 16Mx8 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS32MLS64V8D is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e RoHS compliant products e Performance Range PC 100 e Conformed to JEDEC Standard 4 clocks e 33 554 432 words x 64 bits organization e Burst Mode Operation e Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e All inputs are sampled at the positive going edge of the system clock Transcend information Inc Placement
7. alid X Don t Care H Logic High L Logic Low OP Code Operand Code Ao A11 BAo BA1 Program keys MRS MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state BAo BA1 Bank select address If both BAo and BA are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank is selected If both BAo is High and BA is Low at read write row active and precharge bank C is selected If both BAo and BAt1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA is ignored and both banks are selected During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Trans
8. ccess from Clock 2 highest CL 7ns 70 25 SDRAM Cycle Time 3 highest CL 0 00 26 SDRAM Access from Clock 3 highest CL 0 00 27 Minimum Row Precharge Time 20 14 28 Minimum Row Active to Row Activate 20 14 29 Minimum RAS to CAS Delay 20 14 30 Minimum RAS Pulse Width 50 32 31 Density of Each Bank on Module 128MB 20 32 Command Address Setup Time 2ns 20 33 Command Address Hold Time 1ns 10 34 Data Signal Setup Time 2ns 20 35 Data Signal Hold Time 1ns 10 36 61 Superset Information 00 62 SPD Data Revision Code Version 1 2 12 63 Checksum for Bytes 0 62 47 64 71 Manufacturers ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location T 54 54 53 33 32 4D 4C 73 90 Manufacturers Part Number TS32MLS64V8D 53 36 34 56 38 44 20 20 20 20 20 20 Transcend information Inc 10 168PIN PC100 Unbuffered DIMM TS32MLS64V8D 256MB With 16M X 8 CL3 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 100MHz 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 3 Clock 0 3 F6 128 Unused Storage Locations Open FF Transcend information Inc 11
9. cend information Inc 9 TS32MLS64V8D Serial Presence Detect Specification 168PIN PC100 Unbuffered DIMM 256MB With 16M X 8 CL3 Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly A0 A11 0C 4 of Column Addresses on this Assembly A0 A9 0A 5 of Module Banks on this Assembly 2 bank 02 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 10ns AO 10 SDRAM Access from Clock highest CL 6ns 60 11 DIMM configuration type non parity ECC None 00 12 Refresh Rate Type 15 625us Self Refresh 80 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 3 2 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 Prec All Auto Prec 22 SDRAM Device Attributes General R W Burst OE 23 SDRAM Cycle Time a highest CL 12ns CO 24 SDRAM A
10. k rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8 TS32MLS64V8D 168PIN PC100 Unbuffered DIMM 256MB With 16M X 8 CL3 SIMPLIFIED TRUTH TABLE COMMAND CKEn 1 CKEn CS RAS CAS WE DQM BAo 1 A10 AP Note Register Mode Register Set H X L L L L X OP CODE 1 2 Auto Refresh H H L L L H x 3 Entry L 3 Refresh Self L H H 3 Refresh i efres Exit L H H X X X X X 3 Bank Active amp Row Addr H X L L H H X V Row Address Read amp Auto Precharge Disable L Column 4 H X L H L H X V Address Column Address Auto Precharge Enable H VASA 4 5 i Auto Precharge Disable L Column 4 Write amp H X L H L L X V Address Column Address Auto Precharge Enable H 45 Burst Stop H L H H L x 6 Bank Selection V L L X Precharge Both Banks H L L H X H Clock Suspend or Entry H L x 5 X Active Power L V V V X Down Exit L H X X X X X H X X X Entry H L x Precharge Power L H X Down Mode Exit H X X X L H X L V V V DQM H X V X 7 H X X X No Operation Command H X X X L H H H Note 1 V V
11. ns 1 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 1 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccD min 1 CLK 3 Number of valid CAS latency 3 2 ea 4 output data CAS latency 2 1 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 7 168PIN PC100 Unbuffered DIMM TS32MLS64V8D 256MB With 16M X 8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Unit Note Min Max CLK cycle time CAS latency 3 tcc 10 1000 ns 1 CAS latency 2 12 CLK to valid CAS latency 3 tSAC 6 ns 1 2 output delay CAS latency 2 Output data CAS latency 3 tOH 3 ns 2 hold time CAS latency 2 3 CLK high pulse width tCH 3 ns 3 CLK low pulse width tCL 3 ns 3 Input setup time tss 2 ns 3 Input hold time tSH 1 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output CAS latency 3 tSHZ 6 ns in Hi Z CAS latency 2 Note 1 Parameters depend on programmed CAS latency 2 If cloc
12. tion Inc 4 TS32MLS64V8D ABSOLUTE MAXIMUM RATINGS 168PIN PC100 Unbuffered DIMM 256MB With 16M X 8 CL3 Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 16 Short circuit current los 50 mA Operating Temperature TA 0 70 C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VbD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 24 V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current Inputs 16 16 uA 3 Input leakage current I O pins 3 3 uA 4 Note 1 max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional
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