VAASAN AMMATTIKORKEAKOULU
Contents
1. IrDA transceiver Two 40 pins Expansion headers with diode protection Also with the above hardware the board is also equipped with software examples The board requires its users to be familiar with Quartus II software before the FPGA chip can be programmed and in some case the requirement is not only the Quartus II software but also the NIOS II software The figure below shows the block diagram of the DE2 board 50 Mhz 27 Mhz I Extin USB 2 0 Host Device 16 bit Audio CODEC 10 100 Ethernet Phy MAC VGA 10 bit Video DAC SD Card TV Decoder Cyclone II FPGA 2035 IrDA Transceiver User Green LEDs 8 Flash 1 Mbyte User Red LEDs 18 SDRAM 8 Mbytes 16x 2 LCD Module SRAM 512 Kbytes PS2 amp RS 232 Ports T Segment Display 8 Toggle Switches 18 Expansion Headers 2 Pushbutton Switches 4 EPCS16 Config Device USB Blaster Figure 2 Block diagram of the DE2 board x1 3 DEVELOPMENT SOFTWARE In this section of the report the software used for the implementation of the project will be described in short detail 31 QUARTUS II SOFTWARE The software was developed by Altera technology for programming FPGA device using HDL programming Block diagram schematic files or others design entry formats it has an easy to use graphical user interface and a modular complier which includes the following lists below 1 Analysis and synthesis 2 Fitter place and route 3 Assembler generates th2. 23 X IMPEEMENTATION atitatott et nette ute pisk 25 Fd SDCONIROLLEER 02 ete S FUN eR UR NUR DEUS 28 AUDIO CONTROLLER i 000040 40000 31 33 VOICONTROLBEBR sioe ter qo IERI bc D OE t 34 5 4 peo setate eoo nee E oho rack draps A 45 5 5 WAVE LIBRARY ied ione Pe tiui adiu 48 5 6 55 ten Ur eina sto dein said Fed eod deno e a epa es Ope 50 25 SER 51 5 8 FUNCTIONAL DIAGRAM eitis HER PU PARURE e sis 52 5 9 PROBLEM FACED eir uM e ud 53 SO FUTURE WORK 54 6 CONCLUSION 5 tecti qiti lestis iue A REFERENCE ABBREVIATIONS FGPA DC FAT SD SOPC RIFF JTAG UART HDL VHDL VHSIC DAC Field gate programmable array Inter integrated circuit Fat allocation table Secure digital System on programmable chip Resources interchange file format Joint test action group Universal asynchronous receiver transmitter Hardware description language VHSIC Hardware description language Very high speed integrated circuit Digital to analog converter 1 INTRODUCTION The aim of this thesis is to build an FPGA based music player Firstly the word FPGA is an acronym for Field programmable gate array which is an integrated circuit designed to b
3. HSYNC 69 and Hcount lt 77 HBACK PORCH HSYNC and Vcount gt 40 VSYNC VBACK PORCH and Vcount lt 48 VSYNC VBACK PORCH then htmpi Hcount HSYNC HBACK PORCH 69 vtmpl Vcount VSYNC VBACK PORCH 41 ctmpl others gt 0 ctmpl crange conv integer vtmpl if ctmpl conv integer htmpi player 3 1 8 1 then sc player 1 1 lt elsif ctmpil conv integer htmp1 player 3 1 8 then sc player 1 1 lt 0 end if else sc player 1 1 0 end if end if end process Figure 24 Bit update process 43 44 This process was performed for every information title of the song sample rate time and volume displayed on the VGA monitor Each of the character and symbol displayed on the VGA monitor were given an address to make it accessible to the Nios processor for update The screenshot below gives an insight how it was implemented in the VHDL code process clk begin if rising_edge clk then Make sure every logic on rising edge of clock if reset 1 then To synchronise it if chipselect 1 then if write 1 then if address 00000 then player 1 lt conv integer writedata downto 0 elsif address 00001 then player 1 1 lt conv_integer writedata 9 downto 0 elsif address 00010 then player 1 2 lt conv_integer writedata 9 downto 0 elsif address 00011 then player 1 3 lt conv_integer writedata 9 downto
4. The function set the data register for the mode of operation which I2C was preffered to other mode of operation for the project and enable the master clocking mode BCLK wms731 ADCLRC CODEC DACLRC oe ENCODER ADCDAT DECORDER DACDAT Figure 16 Master mode connection BCLK Output ADCLRC DACLRC pP e 1 tDDA NEN ADCDAT DACDAT Figure 17 Digital Audio Data Timing Master Mode In the SOPC builder two PIO pins were connected to the I2C bus This bus protocol was implemented in the software module to configure the audio chip with 16 bits per channel In this mode the MSB is available on the second rising edge of the BCLK following the transition in the DACLRC or ADCLRC Figure 19 below gives an insight The audio data fetched from the SD card is always 512 bytes and will be written to the DAC FIFO of the audio controller Before the writing it checks if the FIFO buffer is not full gt i LEFT CHANNEL RIGHT CHANNEL DACLRC ADCLRC lt gt 1 BCLK gt 4 BCLK pact TERME ites Aa ADCDAT 11213 n 2 n 1 11213 n2 ni n MSB LSB MSB LSB Figure 18 S mode of operation The I2C bus consists of two wires and a ground connection The two wires are I2C_SCLK which has a data width of port direction is set to output and port SDIN Wow ACK ET 54 ACK Zn 5 POS An r p dt START STOP Figure 19 Two wire C mode direction reset value of
5. Table 5 Color combination voltage level of the signal to achieve 2 different color combinations 37 The VGA timing requirement is an important parameter that was considered when implementing the VGA controller circuit The timing parameters for the display are 640 x 480 resolutions a 25 175 MHz clock 31 469 KHz Line Frequency and 59 94 Hz Field Frequency Pixels Role 8 Front porch 96 Horizontal Sync 40 Back Porch 8 Left border 640 Active 8 Right border 800 total line Lines Role 2 Front porch 2 Vertical Sync 25 Back porch 8 Top Border 38 480 Active 8 Bottom border 525 total field Table 6 and 7 Horizontal and vertical sync signals The values in table 5 and 6 were used for the horizontal and vertical scanning of the screen at a refreshing rate of 60 Hz The horizontal and vertical scanning uses a counter for its implementation which can be seen in the screenshot below The total horizontal is 800 and that of the vertical is 525 HCounter process clk25 begin if rising edge clk25 then if reset 1 then Hcount lt others gt 0 elsif EndOfLine 1 then Hcount lt others gt 0 else Hcount lt Hcount 1 end if end if end process HCounter EndOfLine lt 1 when Hcount HTOTAL 1 else 0 VCounter process clk25 begin if rising edge clk25 then if reset 1 then Vcount lt others gt 0 elsif EndOfLine 1 then if EndOfField 1 then Vco
6. The Nios EDS automatically creates a board support package BSP for Nios II processor based system thus saving time required for manually creating it BSP The BSP created provide C C runtime environment insulating engineers from the hardware in the embedded system design It has an easy to use graphical interface which creates and manages makefile generated based on the system file ptf create with the SOPC builder 12 13 4 BACKGROUND ABOUT THE SYSTEM REQUIREMENT The following heading gives an insight about the major entity of the system 41 WAV FORMAT The Wav file format is part of the numerous formats defined in the Microsoft RIFF specification for storing media files It can be identified by the extension in its filename wav The type of data samples stored is the raw data without any form of compression making it relatively large compared to other media format like the MPEG It consists of three chunks of information namely 1 RIFF Resource interchange file format 2 Format 3 Data The RIFF is a tagged file structure developed for multimedia resources files Its structure is very similar to the Electronic Art IFF though not a file format in its own natural existence but contains Interchange file format related to its origin As a chunk it identifies the file as a Wav file making it suitable for 1 playing back multimedia data 2 recording multimedia data 3 Exchanging multimedia data between applicati
7. The buttons perform the different functions the rightmost button is used to reset the program on the DE2 board two middle buttons were used to increase and decrease the audio volume leftmost for increasing and the rightmost for decreasing The last leftmost button was used to play next track song on the SD card Each of the switches used for this project performs two different functions since it can go back and forth The first switch SW 0 is used to either continuously repeat the current playing song from the SD card or leave it as a free playing music player i e plays all the song stored in the SD card and go back to the first track The second switch SW 1 was used to either play or pause the music in the card 5 8 FUNCTIONAL DIAGRAM The use case diagram below shows the benefits the user of the music player will derived from application 52 53 User I E lt gt just volume Figure 33 Use case diagram After the FPGA chip have been configured the user will be able to perform the functions in the use case diagram with the music player 5 9 PROBLEM FACED The problem faced at first was understanding the HDL language Secondly making the display interface most of the time used in the project because I have no good background or prior experience Firstly I was using the 100 MHz clock for the clock input instead of the 50 MHz which was processed in the VHDL implementation of the displa
8. a time The following functions implement the FAT library used in this project 1 FatClusterType This function identifies the cluster type in the FAT system A cluster is a group of sectors on memory devices that have at lease a piece of information in it The table below describe the FAT cluster type and their value or range as used in the implementation FAT value 0000h Description Unused cluster 46 0002h FFEFh Used Next cluster in file FFF0h FFF6h Reserved cluster FFF7h Bad cluster FFF8h FFFF Used Last cluster in file Table 9 Cluster Types 9 The screenshot below shows how the FAT cluster type was implemented if Fat gt 0 amp amp Fat lt OxFFFO Type CLUSTER NEXT INFILE else if Fat gt OxFFF8 amp amp Fat lt un Type CLUSTER LAST INFILE else if Fat unsigned short 0x00 Type CLUSTER UNUSED else if Fat gt OxFFFO amp amp Fat lt OxFFF6 Type CLUSTER RESERVED else if Fat OxFFF7 Type CLUSTER_BAD return Type Figure 27 Cluster type 2 Fat_Dump This function checks the directory created by the FAT system and fetch out information like name of the file in the directory date created attributes of the file e g hidden file read only system file volume of the file and so on 47 3 Fat_ComposeFilename This function was used to fetch the name and the extension type of the file in the directory of the FAT system The FAT system support
9. if Processor Additions tH Processors Video and Image Processing m Target Device Famy o tt Memories and Memory Controler Use Connecti Module Name cpu C 4 instruction master 4 dela master FT je debug ote V E onchip mem Ho I timer i S V timer stamp al E pio green led a y E pio red led s 7 8 pio switeh v jtag uart k T Description Nios I Processor Avalon Memory Mapped Master Avalon Memory Mapped Master Avalon Memory Mapped Slave On Chip Memory RAM or ROM Avalon Memory Mapped Slave Interval Timer Avalon Memory Mapped Slave Interval Timer Avalon Memory Mapped Slave PIO Parallel V0 Avalon Memory Mapped Slave PIO Paralel VO Avalon Memory Mapped Slave PIO Parallel 0 JTAG UART Clock pll 00 system pll c system pll c system pll cd system pll c0 system pli 00 system pl c system Figure 13 SOPC Builder connection 5 1 SD CONTROLLER 190 0 02204800 0x02202000 0 022050 0 0x022050e0 0202202120 0502205130 0102205150 0x02204fff F Ox02203fff 1 0x022050df 00220802 08022051 0 02205136 00220515 In the software stack diagram SD Card was used to store the music file which was read by the Nios II processor The main operation of the SD Card was implemented in the software phase
10. 0 elsif address 00100 then player 1 4 lt conv_integer writedata 9 downto 0 elsif address 00101 then player 1 5 lt conv_integer writedata 9 downto 0 elsif address lt 00111 then player 2 lt conv_integer writedata 9 downto 0 elsif address lt 01000 then Player 2 1 lt conv_integer writedata 9 downto 0 elsif address lt 01001 then player 2 2 lt conv_integer writedata 9 downto 0 Figure 25 Bit addressing Note Using to_integer gives a compilation error on Quartus V10 try to avoid it The address uses 5 bits which accommodate up to 32 addresses The Nios uses this addresses to update the information on the VGA monitor An example is shown in the screenshot below for updating the sample rate of the wav song sample 6 sample 5 sample 4 sample 3 sample 2 sample 1 45 sample 10 sample 100 10 sample rate 1000 100 sample 10000 1000 sample 100000 10000 sample 1000000 100000 IOWR VGA 0 BASE 12 sample 6 VGA 0 BASE 11 sample 5 VGA 0 BASE 10 sample 4 VGA 0 5 9 1 3 IOWR VGA 0 BASE 8 sample 2 IOWR VGA 0 BASE 7 sample 1 Figure 26 Nios screen updating 5 4 FAT FILE LIBRARY The FAT file library implement the FAT16 file system for reading wave file stored in the SD Card The FAT library support 8 characters long file name and only reads 512 bytes of data at
11. 0 0 and the SDAT which has a bi direction port data width of 1 and port direction reset value of 0 0 5 3 VGA CONTROLLER The standard VGA format of a monitor contains 640 columns by 480 rows of picture elements These elements are referred to as pixels performing the function of displaying images on the screen of the monitor by turning ON and OFF of individual pixel The VGA monitor uses five control signals RED GREEN BLUE HSYNC and VSYNC The first three control signals are commonly referred to as RGB signal controlling the colour formation of a pixel at any location on the screen of the monitor These signals are carried by the VGA connector to the VGA port of the host The signals are analog signal with voltage level ranging from 0 7 to 1V 34 35 Figure 14 and Table 3 show a typical VGA connector and pin numbering of the connector 00000 00000 00000 Figure 20 VGA Connector Pin 1 RED pin 2 GREEN pin 3 BLUE pin 4 ID2 pin 5 GND pin 6 RGND pin 7 GGND pin 8 BGND pin 9 5V pin 10 GND 36 pin 11 IDO pin 12 ID1 pin 13 HSYNC pin 14 VSYNC pin 15 ID3 Table 4 Pin numbering of VGA Connector To achieve different colour combinations the RGB signal voltage have to be varied The text color on the VGA display for this project is white as can be seen in Figure 15 below This shows that the RGB signals are high Table 4 show the VGA RED VGA GREEN VGA_BLUE Resulting Color Blue
12. PX VAASAN AMMATTIKORKEAKOULU 069 VASA YRKESHOGSKOLA 9 UNIVERSITY OF APPLIED SCIENCES MOSES ADELERE AN FPGA MUSIC PLAYER TECHNOLOGY AND COMMUNICATION 2011 VAASAN AMMATTIKORKEAKOULU UNIVERSITY OF APPLIED SCIENCES Information Technology Degree Programme ABSTRACT Author Moses Adelere Title An FPGA Based Music Player Year 2011 Language English Pages 55 Name of Supervisor Yang Liu As the demand for portable electronics devices increase so is the need for an improved technology Electronics manufacturers around the world are looking for ways to make profit at a reasonable cost of production The objective of this thesis is to replace microcontroller based electronic devices with an FPGA which eliminates the cost of acquiring new peripheral when new functionality is to be added to existing devices The design is in two phases mainly consisting the hardware and software The hardware modules use an Intellectual properties from Terasic Technology excepts the VGA display The software module communicates with the Nios processor Keywords FPGA Microcontroller Intellectual properties ACKNOWLEDGEMENT First and foremost to Almight God for his guidance and wisdom all through the years I have lived To my mother for giving me life To the rest of my family for their support To all my friends who support and advise me all through my study To my supervisor Liu Yang for his advise and support To Jarmo Makela who
13. SYSTEM all channels Contains the letters data 0x61746164 little endian form This is the number of bytes in the data sample The actual sound data The FAT is an abbreviation of File Allocation Table designed by Microsoft giving operating systems the possibility to track the location and determine the order of succession of each pieces of a file Since the inception of the common removable flash memory the FAT system has become a format widely used file format in digital device computers The FAT file system provides a way of tracking and monitoring when a file is created or updated and identifying the size of the file It also provides mechanism for storing other characteristics of a file such as read only whether a hidden in a directory display making it an ideal file format for removable memory devices The table below provides information about the structure of the FAT file system 16 Byte Offset 0x00 0x03 0x0B 0x0D 0x0E 0x10 0x11 0x13 0x15 0x16 0x18 Ox1A 0x1C Length Bytes 17 Description jump instruction to boot code indicates what system formatted the volume number of bytes per sector number of sector per cluster number of reserved sector number of allocated tables maximum number of root directory entries total number of sector media descriptor sectors per FAT sectors per track Numbers of h
14. ader 2 JP2 Altera USB Blaster Controller Chipset Expansion Header 1 JP1 Altera EPCS16 Configuration Device Altera Cyclone II FPGA RUNIPROG Switch for JTAG AS Modes 16x2 LCD Module SD Card Slot 7 Segment Displays Per G 8 Green LEDs 18 Red LEDs gt E IITians IrDA Transceiver 1 T IEEE veal SMA External Clock 18 Toggle Switches 1 WWE 4 Debounced Pushbutton Switches 50 MHz Oscillator 8 MB SDRAM 512 SRAM 4 MB Flash Memory Figure 1 DE2 Educational Board 5 The board has many features allowing end user to implement a wide range of embedded application ranging from the simple to sophisticated circuits The board is equipped with the following hardware Altera cyclone II 2C35 FPGA device Altera serial configuration device EPCS16 USB Blaster for programming and user API control both JTAG and Active serial programming modes are supported 512 Kbytes SRAM 8 MByte flash memory SD Card socket Four user push button switches 18 Toggle switches 18 Red user LEDs 9 Green user LEDs 50 MHz and 27 MHz Oscillator for clock sources 24 bit CD quality audio CODEC with line in line out and microphone in jacks VGA DAC 10 bits high speed triple DACs with VGA out connector TV decoder NTSC PAL and TV in connector 10 100 Ethernet controller with a connector USB Host Slave controller with USB type A and B connector PS 2 mouse keyboard connector
15. available to the rest of the audio system on CLKOUT In Digital audio interface it can be operated in any of the 4 mode offer These are 1 PC 2 DSP 3 Right justified 4 Left justified The entire modes have a common characteristic of MSB first and operate with data 16 to 32 bit also the DACLRC and ADCLRC must always change on the falling edge of the BCLK Only the Right justified does not supports 32 bits data 12 ADDRESS READ IS 0x34 2 ADDRESS WRITE IS 0x35 26 SDAT MCN lt gt m ocu 9 9 all q 202 1 g a th Ra v 20 lt i en G RO AGND Acca AGND yd OA I 1000P AGND ABND WM8731 QFN28 045 A NCC33 A VCC33 o TC2 100U 0 3V 1210 BCI BC2 BC3 BC4 OW OW OW 0 10 R12 0 21 Figure 8 Schematic diagram of Audio CODEC 44 SD CARD The SD Card known as the secure digital card was design to cater for the need for reliable data storage on consumer mobile and portable electronics such as digital camera mobile phones etc it was design by the SD Card association All SD Card supports Microsoft FAT16 file system The SD Card can be accessed via a dedicated serial interface for fast data transmission The interfacing buses are 1 SPI 2 SD 1 bit mode 3 SD 4 bit mode DAT2 L CD DAT3 CID I27 0 lox E SCR 63 0 Memory core interface reset I
16. ayed on the VGA screen is done both in the hardware and software In the software I used the function IOWR VGA 0 BASE ADDRESS PARAMETER and for the hardware update bit mapping method was employed The process involves creating a tile memory example an 8 x 80 rom for numerical values shown below and each ascii bit on the VGA display gets its bit from the memory 001111000001100000111100001111000000011001111110001111000111111000 11110000111100 011001100001100001100110011001100000111001100000011001100110011001 10011001100110 01101110001 11000000001 10000001 100001 111001 1 1110001 10000000001 10001 10011001100110 011101100001 100000001 1000001 1 10001 1001 10000001 1001 1 1 1 1000001 100000 11110000111110 42 011001100001 1000001 10000000001 1001 111111000001 10011001 100001 100001 100110000001 10 011001100001 100001 10000001 100110000001 100110011001 1001 100001100001 10011001100110 00111100011111100111111000111100000001 1000111100001 111000001 100000 11110000111100 000000000000000000000000000000000000000000000000000000000000000000 00000000000000 The screenshot below shows the implementation of a single bit update for the VGA PLAYER1 score 1 process 1 25 variable htmpi std logic vector 9 downto 0 variable vtmpl std logic vector 9 downto 0 variable ctmpl std logic vector 0 to 311 begin if rising edge clk25 then if reset 1 then sc player 1 1 0 elsif Hcount gt HBACK PORCH
17. e configured by the designer after being manufactured The configuration of an FPGA can be done using HDL and C programming language provided it has a custom program inbuilt processor like in Altera FPGA used for the implementation of this project Altera defines FPGA ha a semiconductor device that can be programmed after manufacturing and allow you to program products features and functions adapt to new standards and reconfigure hardware for specific applications even after the product has been installed on the FPGA 5 1 1 BRIEF INTRODUCTION ABOUT FPGA The manifestation of the FPGA industry began from PROM programmable read only memory and PLD programmable logic device Both of which can be programed in batches from the factory In 1984 the first FPGA device was invented by Ross Freeman also the co founder of the Xilinx technology The first design was XC2064 chip is a computer chip full of open gates that engineers can reprogram as much as the need arises to add a new functionality to custom device and the adaptation to changing specification 1 2 BENEFIT OF USING FPGA IN DESIGN The following benefits can be derived from using FPGA chips in electronics designs 1 Good performance considering the advantage derived from hardware parallelism FPGA exceeds the computing power of digital signal processing 10 2 Customization This option provides the designer of electronics system the flexibility to ch
18. e programming file 4 Timing Analysis 5 EDA Netlist Writer The following procedure describe how to create a new project on the Quartus II graphical interface 1 Launch the software from your computer 2 Create a new project select File New project wizard 3 Choose the device family for this project cyclone 4 Using the Text editor create a new HDL file Verilog VHDL or Block editor to create clock diagram with symbols representing the design 5 Use the MegaWizard Plug in manager to generate custom variations of megafunctions and IP functions to instantiate the design Optional 6 Use SOPC builder or DSP builder to create a system level design For this project SOPC builder was deployed 7 Use the Analysis and synthesis to synthesize the design 8 Perform place and route on the design using the fitter 9 Perform the timing analysis on the design using the timer analyser 10 Create the programming file using the Assembler 11 Program the FPGA device using the sof or pof file created by the Assembler from the programmer roe Nager ex e TI n Y Quartus Il Software w11 LA 4 Bx der C wn V Sup D Herio ong A F SYN A SYN Tetke gx l ZI MES QUARTUS II QUARTUS Hagar Jemma Leen sgrarme f 4 I d Documentation L
19. eads for interrupt 0x13 count of hidden sectors preceding the partition 0x20 4 This field is the new 32 bit total count of sectors on the volume Table 2 Common offset among versions of FAT file system 1 4 21 STRUCTURE OF THE FAT16 FILE SYSTEM The FAT system disk is organised into sectors with each sector storing 512 bytes of data The sector is the smallest unit used when writing or reading data from disk formatted with the FAT system Unlike the sector the cluster is used by the operating system as the smallest unit when allocating storage space on disk with FAT partition having a variying size depending on size of the partition and varies from drive to drive The FAT identifies each cluster in a partition as 1 Cluster in use by a file 2 Bad cluster 3 Unused cluster 4 Last cluster in a file FAT16 file system uses 16 bits cluster addressing system and its volume is divided into four as shown in Figure 6 below The boot sector is the first sector of the volume defining the volume and also contains the code to enter the file system The FAT is a series of addresses for checking the next cluster in the system and accessed as a lookup table The FAT is an important data structure such 18 19 that it has two copies one as the primary and the other as a backup when there is a fault in the system The root folder directory has a fixed location and length 512 bytes always located at the
20. ith a counter size of 32 bits with enabled writable period readable snapshot and start stop control bit The SDRAM controller provides the memory for the Nios system The SDRAM has a data width of 16 bits address width with a row of 12 bits and column of 8 bits The Flash memory interface is also an important SOPC component It has a data width of 16 bits and address width of 22 bits It was used in the SOPC builder system to provide memory for the system The SRAM module used in the SOPC builder is a user defined component also providing an altaernative memory for the processor It has an address width of 18 bits and a data width of 16 bits The CPU module provides the arithmetic logic unit for the system It uses the 32 bit RISC architetcture and runs at 100MHz clock speed which was provided using the Altera PLL generator The Phase lock loop PLL module was used to set the required clocking for the system It takes an input clock of 50 MHz to generate a clock of 100 MHz for the CPU and other components with the exception of the Audio controller which runs at a clock of 18 432 MHz The JTAG UART module provides the communication interface between the host PC and the SOPC builder system It eliminate the need for a separate RS 232 connection 5 7 USER CONTROL User control is provided with four key buttons and two switches The key buttons and the switches were connected using the PIOs in the SOPC builder 51
21. made mathematics so simple also not to forget Dr Gao Chao a teacher of high pedigree and to the rest of the teacher in VAMK To Altera and Terasic for giving the right to edit source code and other intellectual propery of the company CONTENTS ABSTRACT ACKNOWLEDGE MEIN 2 ABBREVIATIONS ena Ina 3 I INTRODUCE s diac datei tita ae Une eeu HM oum uit tates 4 11 BRIEF INTRODUCTION ABOUT FPGA eene 4 1 2 BENEFIT OF USING FPGA IN DESIGN eee 4 2 JDE2 EDUCATIONALTE BOARD onere eo ret eaaet ne naso ee apu 5 2 1 STRUCTURE OF THE BOARD unten netto deo detecte 6 3 DEVELOPMENT SOFTWARE leas att 9 3d 9 3 2 SOPE BUILDER eleg gute dt ester d 11 3 3 NIOS I EMBEDDED DEVELOPMENT 12 4 BACKGROUND ABOUT THE SYSTEM 13 AA WAV FORMAT Mi ue aids 13 Z2 FAT FILES YSTEM asada doses iran rg psa ei cepi a 16 4 2 1 STRUCTURE OF THE FATI6 FILE 18 43 WMS7SI AUDIO ARA 19 AA SDCARD S ASS 22 Z5 ADV7123 VGA CODEC dius tie una E
22. nterface driver 1 1111 CL DATO DAT v Card interface controller reset Power on detection RS cue LN ESL a a a Ee du qo SE SLE a co 4 FR ue a o3 4 22 23 Figure 9 SD Card Architetcture 8 4 5 ADV7123 VGA CODEC The ADV7123 is triple high speed digital to analog converter on a single monolithic chip 4 It has three 10 bit input ports 5V 3 3V power supply and requires clock input for full functionality Also include in the ADV7123 is an additional control signals composite SYNC and BLANK Its applications can be seen in the following 1 Video signal reconstruction Instrumentation Digital radio modulation Image processing High resolution colour graphic Digital video systems The figure below show the schematic diagram of the ADV7123 video DAC connected to the VGA port 24 Q BC106 BC107 0 1U 010 R962 R972 R98 75 575 9 75 Figure 10 Schematic of Video DAC The table below shows the electrical signal and description of the video DAC Signal name Description VGA R 9 0 10 bit red level VGA_G 9 0 10 bit green level VGA B 9 0 10 bit blue level VGA CLK VGA clock VGA BLANK VGA BLANK VGA HS VGA HSYNC 25 VGA VS VGA VSYNC VGA SYNC VGA SYNC Table 3 Signal assignment of ADV7123 5 IMPLEMENTATION The implementation for the system requirement
23. of this project is divided into two parts 1 Hardware 2 Software which the SOPC builder uses the Avalon switch fabric as the connecting bridge between the hardware and the software Avalon switch fabric is a collection of signals and logics that connects master and slave of the SOPC builder and other custom components in a Nios II system development The block diagrams below hardware and software stack for the project 26 Figure 11 Software stack System Requirement 100 MHZ Phase 65 deg Audio Socket MIC In Line In Line Out Seg 7 Seg 7 Controller Device Controller Figure 12 Hardware stack In the hardware development I used the SOPC builder components and other custom or user defined components to configure and generate the Nios system For the software development the Nios embedded design suite was used to communicate with the processor The figure below shows the hardware connection in the SOPC builder for the implementation of the project 27 71 Aera SPC Builder system CU File Edt Module System View Tools Nios Help System Contents System Generation Component Library Project i H New component 900 8 062 sram_controller Terasic Technologies i Terasie Technologies nc VGA Library Avalon Verification Suite Bridges and Adapters 8 Interface Protocols Legacy Components Peripherals PLL
24. ons The format chunk identifies parameters such as numbers of channel sample rates etc while the Data chunk contains the actual data sample of the media file The figure below show a Wav file format block 14 File offset Field Size 3 field name andian bytes bytes big d 4 The RIFF chunk descriptor 4 little 4 The Format of concern here is big 4 WAVE which requires two 12 sub chunks fmt and data 16 20 22 The fmt sub chunk litle describes the format of 28 the sound information in m 4 the data sub chunk 34 little BitsPerSample 2 36 gt 40 The data sub chunk EDEN 4 i v Indicates the size of the little a sound information and t contains the raw sound data 2 Figure 5 A Canonical Wav file format 4 The table below gives an insight about the wav file format Offset Name Size Bytes Description 0 ChunkID 4 Contains the letters RIFF in ASCII format 0x46464952 little endian form 4 ChunkSize 4 4 8 subchuklSize 8 SubChunk2Size 12 Subchunk1ID 4 Contains the letter fmt 0x20746d66 little endian form 20 AudioFormat 2 PCM 1 other values indicate a form of compression in the data 24 SampleRate 4 8000 44100 etc 32 BlockAlign 2 The number of bytes for one sample including 15 36 Subchunk2ID 4 40 Subchunk2Size 4 44 Data no specific size Table 1 Wave Data information 4 4 2 FAT FILE
25. oose the desire components controllers and peripherals to be used in designs 3 Component and cost reduction With the vast capability of FPGA previous system designs that required additional components to improve its functionality can be replaced with a single FPGA chip The reduction in the number of components in a design can reduce the robust size of the board and inventory management thus reduce the time expended and also cut down the cost of production 4 Obsolescence mitigation FPGA soft processor provides an excellent solution that arises when considering the lifespan of electronics designs Since the source of HDL for the soft processor can be purchased from it owner to combat the issue of component obsolescence mitigation 2 DE2 EDUCATIONAL BOARD The information about the DE2 educational board is an extract from the user manual provided by Altera on the board 21 STRUCTURE OF THE DE2 BOARD The figure below shows a labelled diagram of the DE2 educational board illustrating its layout and indicating the component constituting the board USB USB USB Ethernet Blaster Device Host Mic Line Line Video VGA Video 10 100M Pot Pot Pot in in Ou In Port Pot RS 232 Port ww ud m UU 27 MHz Oscillator j 24 bit Audio Codec AN M d Power ON OFF Switch gt 5 2 Keyboard Mouse Port VGA 10 bit DAC USB Host Slave Controller TV Decoder NTSCIPAL Ethernet 10 100M Controller Expansion He
26. ow unsigned int nCount 0 FAT BROWSE HANDLE hBrowse FAT DIRECTORY Dir if Fat FileBrowseBegin amp hBrowse while Fat FileBrowseNext amp hBrowse amp Dir nCount return nCount Figure 29 File counting in the FAT system 5 5 WAVE LIBRARY The WAVE library implements the decoding and retrieving of audio signal from the wave file The code implementation will be seen in the Appendices 49 The following function implements the wave format used in the project 1 Wave_IsWaveFile This function check the format of the file stored in the SD card The algorithm used is shown with the screenshot below WAVE IsWaveFile char szWave const int nSize bool bYes FALSE if nSize gt sizeof WAVE HEADER WAVE HEADER pHeader WAVE HEADER szWave if pHeader gt ChunkID TAG RIFF amp amp pHeader gt Format TAG WAVE int nOffset waveGetChunkOffset sziave nSize CHUNK FORMAT if nOffset PCM FORMAT CHUNK pPcmChunk PCM FORMAT CHUNK szWave nOffset if pPcmChunk gt Size 16 amp amp pPcmChunk gt AudioFormat 1 uncompress PCM bYes TRUE return bYes Figure 30 Wave IsWaveFile 2 Wave GetSampleRate The function returns the sample rate of the music file Ths screenshot below shows the algorithm int nOffset waveGetChunkOffset szWave nSize CHUNK FORMAT if nOffset PCM FORMAT CHUNK pPcmChunk PCM FORMAT CHUNK szWave nOffset nNum
27. pPcmChunk gt SampleRate return nNum Figure 31 GetSampleRate 3 waveGetChunkOffset This function is returns the offset value of the wav format The offset value contains the necessary information of the wav format that is why this function is important to other functional implementation of the wav format as can be seen in the code above The implementation can be seen below if nSize gt sizeof WAVE HEADER int nOffset sizeof WAVE HEADER CHUNK pChunk CHUNK szWave nOffset gt while pChunk gt ID ChunkID amp amp nOffset lt nSize int nSkip sizeof CHUNK pChunk gt Size pChunk CHUNK alt u8 pChunk nSkip nOffset nSkip if pChunk gt ID ChunkID nNum nOffset return nNum Figure 32 waveGetChunkOffset 5 6 OTHER PERIPHERALS The DE2 board provides a 2 x 16 LCD module which display the name of the music currently playing and the volume of the player The LCD module is an SOPC builder component which was included into the project The LEDs display the strength of the audio signal which I called an equaliser The LEDs module was included into the SOPC builder as a PIO component which includes 9 PIOs for the green LEDs and 18 PIOs for the red LEDs both having an output direction port The timer is another SOPC component used in the project The project includes two interval timer components from the SOPC library The timers have 1 milliseconds period w
28. r T Figure 3 Quartus II Graphical user interface Note The Quartus II software includes solutions for all phases of FPGA and CPLD designs user manual 10 11 3 2 SOPC BUILDER The SOPC builder is one among the system level design flow supported by the Quartus II software It is included in the Quartus II software and allows engineers to rapidly design and evaluates system on chip architecture as well as design at a higher level of abstraction The SOPC builder is an automated system development tools that dramatically simply the task of creating a high performance SOPC designs user manual it provides engineers the opportunity to design a custom component use SOPC system component in design architectures as well as generate and verifying the system before final integration of the system It composed of components such as CPU memory timer standard and user define peripheral UART JTAG Avalon tri state bridge etc and also provide an interface to user defined logics There are four techniques for using SOPC builder system with user defined logic 1 Simple PIO connection 2 Bus interface to external logic 3 Publishing a local SOPC builder component and 4 instantiation inside the system module For each project created with the SOPC builder contains a system descriptive file The file which has a ptf extension contains all the options setting and parameter included in the SOPC builder Each componen
29. s 8 3 filename system i e 8 bits for the file name and 3 bit for its extension type The figure below shows how it was implemented in the Nios C code while i lt 8 amp amp pDir Name i 0 amp amp pDir Name i szFilename nPos pDir gt Name i SzFilename nPos i 0 while i lt amp amp pDir gt Extension i 0 amp amp pDir Extension i szFilename nPos pDir gt Extension i 2 1 nPos 0 Figure 28 File name compose 4 Fat_FileSize This function returns the size volume of the file in the directory 5 FatNextCluster This fuction check the status of thr next clusters of the data The pseudo code below describes the flow of the implementation 1 if status is readonly 2 Nextcluster unsigned short gVolumelnfo szFatTable ThisCluster lt lt 1 3 ClusterType fatClusterType NextCluster 4 check if type is not next in file and not last in file NextCluster 0 48 5 else nFatEntryPerSector gVolumelnfo BPB_BytsPerSec nFatEntrySize 7 sector gVolumeinfor FatEntrySector ThisCluster nFatEntrySize g VolumeInfo BPB_BytsPerSec 8 read data block from SD Card 9 NextCluster unsigned short szBlock ThisCluster nFatEntryPerSec nFatEntrySize 10 go to 4 11 exit 6 Fat_FileCount This function was used to count the number of files in the FAT directory The implementation is shown bel
30. start of the volume The other folders and all files occupy the rest of the volume and are divided into clusters Figure 6 Structure of the FAT16 volume Note FAT16 can not be used on volume greater than 2GB 43 WM8731 AUDIO CODEC The CODEC is a low power stereo codec integrated with a headphone driver specifically designed for portable audio device such MP3 player PDAs smartphone recorders etc The CODEC is equipped with stereo line and microphone level audio inputs alongside with a mute function programmable line level volume control and a bias voltage output suitable for an electret type microphone It has a sampling rate ranging between 8 KHz to 96 KHz and can be controlled using serial I2C bus interface The controlling interface uses 2 or 3 wire serial interface which provides the access characteristic like volume control power management mute and de emphasis Digital filter de emphasis is provided at 32 KHz 44 1 KHz and 48 KHz can be applied to the digital data under software control The figure below shows the block and schematic of the Audio CODEC respectively muswolfson WM8731 610 73dB 1dB Steps DIGTAL AUDIO INTERFACE Figure 7 Block diagram of WM8731 Audio CODEC 20 The CODEC includes a crystal oscillator circuit which allows audio system reference clock to be generated on device The oscillator is designed for low EMI and radiation type In buffered form it is
31. t included in the SOPC design has a corresponding PTF file and this file is used in generating the source code software component and simulation files for the system The design flow of a typical SOPC builder is shown below Y Add memory component 1 Y Add memory component 2 Simulation 1 I I I 1 I I I 1 1 1 I 1 I 1 I I 1 I 1 i I i 1 i 1 Y Connect Starta ate x d m Connect SOPC Assign FPGA Connect Quartus Il gt Sore 4 5 gt gt Builder system Pins amp compile FPGA pins project H gt H generate module to Quartus II to memory system Add memory Quartus project project chips uilder component N system i i i 1 1 i I i 1 Add other 1 components 1 1 1 1 1 1 I 1 i i 1 i 1 dE 1 NET rw shi n V va lt 2 wv Component Level prensa Quartus II Project Board Level D Design EE Level Design EDGE T Figure 4 Design flow of SOPC builder 3 3 II EMBEDDED DEVELOPMENT IDE The Nios II IDE is based on the Eclipse IDE platform and the Eclipse CDT plug in It has a user friendly development environment that works for all Nios II processor based system With the Altera FPGA connected to the host machine running Nios IDE engineers can write program for and communicate with Nios II processor via the Altera JT AG usually the USB Blaster
32. the response related to the command issued 3 send_cmd 30 This function sends command to the SD card 4 SD card init This function function initialises and detects the card It persistently sends command to the card and waits until the response is a success An example of the response is the CRC The command sent in this function is in the following sequence cmd55 cmd4l cmd2 emd3 emd9 emdl10 cmd7 cmd16 The hardware peripheral as used in the SOPC builder for the wiring the SD card uses four parallel input output PIO peripheral The PIOs are SD_CLK SD_DAT SD_DAT3 SD_CMD The SD_CLK has data width of 1 directional port is set to output and the port direction reset value is 0x0 SD DAT SD CMD and the SD DAT3 has a data width of 1 direactional port is set to bidirectional tristate and the port direction reset value is 0 0 5 2 AUDIO CONTROLLER The Audio controller used is a user defined SOPC component from Terasic technology It needs an input clock of 18 432 MHz which was generated using PLL and the resulting clock fed to the Audio controller was 18 51 MHz The audio configuration demands that the controller operates in the master mode so that the serial bit BCK and the left right channel clock were provided by the audio chip The master mode was enabled in the software with the function below Bool audio init void Bsuccess audio regwrite 7 0x0042 32
33. unt lt others gt 0 else Vcount lt Vcount 1 end if end if end if end process VCounter Figure 21 Horizontal and vertical counter The VGA timing table shown in Table 7 is derived from 640 x 480 resolutions using the clock of 25 175 MHz 39 40 Vertical Horizontal Syne Symbol Table 8 VGA Timing Since the clock required for the resolution 640 x 480 need 25 MHZ and the board provides a 50 MHz clock I generate the 25 MHz using the VHDL code in the screenshot below process clk begin if rising edge clk then Clk25 not clk25 end if end process Figure 22 25 MHz clock generation The display raster was implemented using an 8 x 8 rom An example of the rom created for letter V is shown below 01100110 01100110 01100110 01100110 01100110 00111100 00011000 00000000 Figure 23 VGA Display The method used for the text displayed on the VGA is called tile mapping The texts are in predesigned patterns An example for a pattern TIME is shown below 41 0111111000111100011000110111111000000000 000110000001 100001 11011101 10000000000000 000110000001 100001 11111101 1000000001 1000 000110000001 100001 1010110111 100000000000 000110000001 100001 10001 101 10000000000000 000110000001 100001 10001 1011000000001 1000 0001100000111100011000110111111000000000 0000000000000000000000000000000000000000 The update of the data displ
34. using the SD 1 bit mode of operation in the hardware phase four PIO pins were connected to the SD Card socket Figure 14 below shows the hardwire connection between the SD card in SD 1 bit mode and the host device 28 Figure 14 SD Card 1 bit Mode 7 The SD 1 bit mode is a synchronous serial protocol with one line for data used for bulk data transfer one clock line for data synchronisation and one command line for sending command frames It support bus sharing and can be simply be describe as a command data protocol The data signal line has three purposes 1 To signal interrupts from the signal to the host 2 To indicate successful reception of data blocks on write operations 3 implement wait states from the device to the host 29 In the software implementation the following function prototype were used to configure the card 1 bit mode This means that it will only read a block of data at a time i e 512 byte 1 SD read block This function read a single block of data at a time whose size is 512 byte It sent the cmd17 to read the data on the SD card then synchronise the data with the clock Figure 15 shows the reading operation 8 154 socks 8 multiple 8 multiple 3 8 d o z gt e DATA OUT OCh CMD17 is i Start Byte 2 Sytes e Figure 15 Read operation 6 2 response_R This function return
35. y to generate a 25 MHz used for the 640 x 480 resolution display of the VGA When the project was first ran I found that the audio out was too fast resulting in a humming output This was caused by the crystal clock not been connected in the HDL used for the custom component 5 10 FUTURE WORK After the completion of the project I planned to make a video game with the DE2 educational board preferable a soccer game and a chat application 6 CONCLUSION In this project I have create a music player on an FPGA chip The target of the project in the beginning was achieved The Altera DE2 Education board is a good starting point to learn how to program an FPGA Altera already provides software tool like Quartus II SOPC builder and Nios EDS as the programming IDE for the FPGA 54 55 REFERENCE 1 Dave Dittrich http staff washingtom edu dittrich 2 Microsoft http www microsoft com about 3 Mcgill http www mmsp ece mcgill ca 4 Analog Device http www analog com 5 Altera http www altera com 6 Terasic http www terasic com 7 http downloads amilda org MODs SDCard SD pdf 8 http alumni cs ucr edu amitra sdcard ProductManualS DCardv1 9 pd f 9 http home teleport com binary fat16 htm 10 National instrument http zone ni com devzone cda tut 1d 6984 11 Wolfson microelectronics http www wolfsonmicro com
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