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DE2 Development and Education Board User Manual

1. 23 Chapter 4 DE 2 7 R Video BIriiis M HT 25 4 1 GO SI crise r ct 25 AER C E 26 4 3 bU EN UU Ue 27 4 4 Overall Structure of the DE2 70 Video Utility eese 28 Chapter 5 Usine the DE2 70 811 30 5 1 the Cyclone H RG E 20 the LEDSand 32 5 3 Usine the PSC e miert Display acon encase 26 5 4 IY TE UU 38 5 5 PE e 40 50 Using th Expansion SII NR 4 5 7 iU 10 E E 4 5 8 A M Audio 48 s UNE t 40 ST EM PA re E NER 40 S11 FastEthernet Network Controlle ineo orani tene Run ou 50 Altera DE2 70 Board A MON OC te pene sacs cece Tem 22 415 Impen ntng ay V Encode essene EEE Eaa 54 ae US ESD Hor na 1 o E E E TE E RUE 55 XS U D e E EE E 56 5 16 Using 57 Chapter 6 Examples of Advanced Demonstrations eescsssssssececcccsssssececocosssssccecooc
2. IO A2 Cer e IO A3 A4 o o 18 BAT54S 548 d 0 A7 7 OOS CE Lo o lais A9 GPIO DO R51 47 Ae I 16 IG Am GPIO Di RNA OM oA o oma 10 A13 eee SOV IO CLKOUTnO4g c 20 IO A14 CLKOUTp024 A15 A16 La 14 lO A17 iO A18 I E A19 1 A20 Q protection registors and diodes 283 2 8 3 lO A22 o o 1 lO A23 A24 34 A25 not shown for other ports 104 of ast 365425 lO A28 5 38 lO A29 IO A30 9 o o 1 40 IO A31 BOX Header 2X20M VCCIO5 VCCIO5 GPIO 1 J5 IO CLKINn1 ee 0 lO CLKINp1 IO B1 Ene IO B2 Drar OBS lO B4 lO B5 IO B6 9 10 IO B7 GPIO D32 A 47 10 BO D Pa des EP lO B9 GPIO D33 OBI IO B10 o o Io lO B12 LE ET IO B13 CLKOUTn1 i 20 lO B14 lO CLKOUTpi 1 o o 221 lO B15 f lO B16 Loa 54 IO B17 protection registors and diodes Co o zal 10 Bs OO VCC33 9 30 not shown for other ports 0 D Ez 99 3 ow lO B24 54 IO B25 lO B26 le 156 lO B27 IO B28 P8 B29 IO B30 Lo aao lO B31 BOX Header 2X20M Figure 5 11 Schematic diagram of the expansion headers IO A 0 PIN C30 GPIO Connection 0 IO 0 A 1 PIN C29 GPIO Connection 0 1 A 2 PIN E28 GPIO Connection 0 2 DE2 70 User Manual A 3 PIN D29 GPIO Connection 0 IO 3 43 D
3. Learning through Innovation 2 User Development and Education Board Manual FT nag UNIVERSAL SERIAL BUS Altera DE2 70 Board Chapter 1 DE2 7 0 Package sisca 1 1 1 PAC CONE ae E AE TOES l t2 Board SSD 2 1 3 ruis 3 Chapter 2 ANCEa DB2 70 DOSOEU ice none HS ERE Ea one 4 24 Lavourtaud etd Io cI NER IINE US EDO OE 4 2 2 Block Diasram ofthe DE2 70 DOSE EE 5 2 9 Power op The DE2 7 0 DOO aeo a Padre HEU dues TEE EEEa SEEE 9 Chapter 3 Db2 0 REL vi 1 SN GTB OL 0 E 11 2 2 Controlling the LEDs 7 Segment Displays and LCD 13 3 3 Switches E E ecu ERR S MuR 15 3 4 SDRAM SSRAM Flash Controller and Programmer essere 16 3 5 CSE E E EE E 15 S OMM 19 3 7 oD ou E 20 3 8 Ade PVA a an 6 21 3 9 Overall Structure of the DE2 70 Control
4. NBIS8 SYN DE2 70 User Manual Press KEY3 on the DE2 70 board can play the next music file stored in the SD card e Press KEY2 and KEYI will increase and decrease the output music volume respectively Figure 6 16 illustrates the setup for this demonstration dini m 1 iL T uar 1 f T 6 BRHRERWES WEFSES 3 DEZI e with music fils wav Figure 6 16 The setup for the SD music player demonstration 6 9 Music Synthesizer Demonstration This demonstration shows how to implement a Multi tone Electronic Keyboard using DE2 70 board with a PS 2 Keyboard and a speaker PS 2 Keyboard is used as the piano keyboard for input The Cyclone II FPGA on the DE2 70 board serves as the Music Synthesizer SOC to generate music and tones The VGA connected to the DE2 70 board is used to show which key is pressed during the playing of the music 83 DE2 70 User Manual Figure 6 15 shows the block diagram of the design of the Music Synthesizer There are four major blocks in the circuit DEMO SOUND PS2 KEYBOARD STAFF and TONE GENERATOR The DEMO SOUND block stores a demo sound for user to play PS2 KEYBOARD handles the users input from PS 2 keyboard The STAFF block draws the corresponding keyboard diagram on VGA monitor when key s are pressed The TONE GENERATOR 1s the core of music synthesizer SOC User can switch the music source either from 52 or the DEMO SOUND block using SW9 To repeat t
5. 91161 PIUUO0III JUJ WAS Figure 4 4 Video Capture Block Diagram The control flow for video displaying is described below 1 Host computer downloads the raw image data to SDRAM U2 2 Host issues a display command to Nios II processor 3 Nios II processor interprets the command received and moves the raw image data from the SDRAM to SSRAM through the Multi Port SSRAM controller 4 VGA Controller continuously reads the raw image data from the SSRAM and sends them to the VGA port The control flow for video capturing is described below 1 Host computer issues a capture command to Nios II processor 2 Nios II processor interprets the command and controls Video In controller to capture the raw image data into the SSRAM After capturing is done Nios II processor copies the raw image data from the SSRAM to SDRAM U2 3 Host computer reads the raw image data from the SDRAM U2 Host computer converts the raw image data to RGB color space and displays it 29 NBTE m DE2 70 User Manual Chapter 5 Using the DE2 70 Board This chapter gives instructions for using the DE2 70 board and describes each of its I O devices 5 1 Configuring the Cyclone II FPGA The procedure for downloading a circuit from a host computer to the DE2 70 board is described in the tutorial Quartus II Introduction This tutorial 1s found in the DE2 70 tutorials folder on the DE2 70 System CD ROM The user is encouraged to read the tutorial first and
6. Figure 6 10 The setup for the Karaoke Machine 6 7 Ethernet Packet Sending Receiving In this demonstration we will show how to send and receive Ethernet packets using the Fast Ethernet controller on DE2 70 board As illustrated in Figure 6 11 we use the Nios II processor to send and receive Ethernet packets using the DM9000A Ethernet PHY MAC Controller The demonstration can be set up to use either a loop back connection from one board to itself or two DE2 70 boards connected together On the transmitting side the Nios II processor sends 64 byte packets every 0 5 seconds to the After receiving the packet the DM9000A appends a four byte checksum to the packet and sends it to the Ethernet port On the receiving side the DM9000A checks every packet received to see if the destination MAC 78 NDE DA DE2 70 User Manual Jia address in the packet is identical to the MAC address of the DE2 70 board If the packet received does have the same MAC address or is a broadcast packet the DM9000A will accept the packet and send an interrupt to the Nios II processor The processor will then display the packet contents in the Nios II IDE console window 64 Bytes Data Dm 64 Bytes Data 4 Bytes Checksum 64 Bytes Data 4 Bytes Checksum Nios II Interrupt Davicom CPU 4 DM9000A Read Data Ethernet 64 Bytes Data 4 Bytes Checksum a Figure 6 11 Packet sending and receiving
7. Table 6 2 Usage of the switches pushbuttons KEYs SW O OFF BRASS ON STRING PS 2 Keyboard DE2 70 User Manual Table 6 3 Usage of the PS 2 Keyboard s keys Keyboard Input tita e UCET MAT us Y 54 441 TI 4 Lae Figure 6 16 The Setup of the Music Synthesizer Demonstration 86 DE2 70 User Manual 6 10 Audio Recording and Playing This demonstration shows how to implement an audio recorder and player using the DE2 70 board with the built in Audio CODEC chip This demonstration is developed based on SOPC Builder and NIOS IDE Figure 6 18 shows the man machine interface of this demonstration Two push buttons and six toggle switches are used for users to configure this audio system SWO is used to specify recording source to be Line in or MIC In SWI is to enable disable MIC Boost when the recoding source is MIC In SW2 is used to enable disable Zero Cross Detection for audio playing SW3 SW4 and SW5 are used to specify recording sample rate as 96K 48K 44 1 K 32K or SK The 16x2 LCD is used to indicate the Recording Playing status The seg7 is used to display Recording Playing duration with time unit in 1 100 second The LED 15 used to indicate the audio signal strength Table 6 4 summarizes the usage of toggle switches for configuring the audio recorder and player iir E bal m H E HI EZE A c Recor
8. to SDRAM SRAM MN te un 5 p 5 e e 55 c EZ e SEG7 SEG7 Controller AUDIO dmm AUDIO Controller Figure 6 19 Block diagram of the audio recorder and player Demonstration Setup File Locations and Instructions e Hardware Project directory DE2 70 AUDIO e Bit stream used DE2P_TOP sof e Software Project directory DE2 70 AUDIONsoftwareNproject audio e Software Execution File DE2 70 AUDIONsoftwareNproject auidovaudioMlebug audio elf e Connect an Audio Source to the LINE IN port of the DE2 70 board e Connect a Microphone to MIC IN port on the DE2 70 board e Connect a speaker or headset to LINE OUT port on the DE2 70 board e Load the bit stream into FPGA note 1 88 N DTE 8Y DE2 70 User Manual e Load the Software Execution File into FPGA note 1 e Configure audio with the toggle switches e Press KEY3 on the DE2 70 board to start stop audio recoding note 2 e Press KEY2 on the DE2 70 board to start stop audio playing note 3 Note 1 Execute DE2_70_AUDIO demo batch audio bat will download sof and elf files 2 Recording process will stop if audio buffer is full 3 Playing process will stop if audio data is played completely Audio is from MIC Audio is from LINE IN Disable MIC Boost Enable MIC Boost Disable Zero cross Detection Enable Zero cross Detection Unlisted combination Table 6 4 Toggle switch setting for audio recorder and p
9. B VBUS Do CP CAP2 4 Eon etu CP_CAP1 A CS V V WR Gr 39 RI20 A A 530 7 4 OU VCC33 ONGC RD 60 R121 10K LEDB m INT2 TEST2 R122 10K 59 INT1 TESTI SN RESET Le R123 100K U VCC33 D87 D88 lt OTG DREQ THES s BAT54S BAT54S OTG DACK n 29 DACKO e J14 OTG DREQO 24 OTG FSPEED R124 1 5K 3 n 28 D D 4 xo 44 e lt OTG_LSPEED__R128 V 7 5K 23 Lit BEAD VCCS ul 9 052 058 Y Y USBETYPE 47p 47p 068 01 Figure 5 20 USB ISP1362 host and device schematic 55 V Bo DE2 70 User Manual S RYA OTG_D 4 PIN J12 ISP1362 Data 4 Table 5 17 USB 19581362 pin assignments 5 15 Using IrDA The DE2 70 board provides a simple wireless communication media using the Agilent HSDL 3201 low power infrared transceiver The datasheet for this device is provided in the DatasheetNrDA folder on the DE2 70 System CD ROM Note that the highest transmission rate supported is 115 2 Kbit s and both the TX and RX sides have to use the same transmission rate Figure 5 21 shows the schematic of the IrDA communication link Please refer to the following website for detailed information on how to send and receive data using the IrDA link http techtrain microchip com webseminars documents IrDA_BW pdf 56 V Bo DE2 7
10. and the Nios II processor to implement a USB mouse movement detector We also implemented a video frame buffer with a VGA controller to perform the real time image storage and display Figure 6 5 shows the block diagram of the circuit which allows the user to draw lines on the VGA display screen using the USB mouse The VGA Controller block is integrated into the Altera Avalon bus so that it can be controlled by the Nios II processor Once the program running on the Nios II processor 15 started it will detect the existence of the USB mouse connected to DE2 70 board Once the mouse is moved the Nios II processor is able to keep track of the movement and record it in a frame buffer memory The VGA Controller will overlap the data stored in the frame buffer with a default image pattern and display the overlapped image on the VGA display 72 DE2 70 User Manual AVU S n VA Philips ISP1362 USB i Host Mouse Port Altera Niosll 4 gt System CPU Interconnect Fabric VGA Controller 4 gt ADV7123 Frame Buffer Figure 6 5 Block diagram of the USB paintbrush demonstration Demonstration Setup File Locations and Instructions Project directory DE2_70_NIOS_HOST_MOUSE_VGA Bit stream used DE2_70_NIOS_HOST_MOUSE_VGA sof Nios II Workspace DE2_70_NIOS_HOST_MOUSE_VGA Software e Connect a USB Mouse to the USB Host Connector ty
11. in which the music files are stored in an SD card and the board can play the music files via its CD quality audio DAC circuits We use the Nios II processor to read the music data stored in the SD Card and use the Wolfson WM 8731 audio CODEC to play the music 80 V Bo DE2 70 User Manual S RYA Figure 6 13 shows the hardware block diagram of this demonstration The system requires a 50 MHZ clock provided from the board The PLL generates a 100 MHZ clock for NIOS II processor and the other controllers except for the audio controller The audio chip is controlled by the Audio Controller which is a user defined SOPC component This audio controller needs an input clock running at 18 432 MHZ In this design the clock is provided by the PLL block The audio controller requires the audio chip working in master mode so the serial bit BCK and the left right channel clock LRCK are provided by the audio chip The 7 segment display 15 controlled by the Seg 7 Controller which also 15 a user defined SOPC component Two PIO pins are connected to the I2C bus The I2C protocol is implemented by software Four PIO pins are connected to the SD CARD socket SD 1 Bit Mode is used to access the SD card and is implemented by software All of the other SOPC components in the block diagram are SOPC Builder built in components 100 MHZ Phase 65 deg M SSRAM u Controller V Chip SDRAM B SDRAM i Controller Chip Chip Audio Socket
12. o Ts Figure 5 23 ps FLASH DI0 14 FLASH A 0 21 FLASH AO FLASH A1 FLASH A2 FLASH A3 FLASH A4 FLASH A5 FLASH A6 FLASH A7 FLASH A8 FLASH A9 FLASH A10 FLASH A11 FLASH A12 FLASH A13 FLASH A14 FLASH A15 FLASH A16 FLASH A17 FLASH A18 FLASH A19 FLASH A20 FLASH A21 FLASH WE n FLASH RESET n FLASH WP n FLASH OE n FLASH BYTE n F VCC33 R32 4 K FLASH RY R33 4 7K FLASH Figure 5 24 SR_VCC33 O O v db GG Do KO e A FLASH_RY FLASH_CE_n SR_VCC33 SRAM SRAM 6 SRAM SRAM 8 SRAM 9 SRAM 6 SRAM 68 SRAM 69 SRAM SRAM SRAM 4 SRAM SRAM SRAM SRAM SSRAM 512Kx36 SRAM 6 SRAM IS61LPS51236A 200TQLI SRAM 8 SRAM 5 SRAM SRAM 8 SRAM 9 SRAM SRAM SRAM SRAM 8 SRAM 9 SRAM 0 C C C C O SI Oo O SSRAM schematic F VCC33 FLASH DO FLASH D1 o FLASH D2 FLASH D3 FLASH D4 FLASH D5 FLASH D6 FLASH D7 FLASH D8 FLASH D9 FLASH D10 FLASH D11 FLASH D12 DQ12 FLASH D13 DQ13 FLASH D14 DQ14 rie FLASH D15 A i S IN EB N DQ10 DQ11 E IS I D FLASH 8Mx8 Flash schematic 59 data0 data1 data2 data3 data4 data5 data6 6 SRAM data7 SRAM dataparO data8 data9 data10 data1 1 data12 data13 data14 SRAM data15 0 SRAM_datapar1 data16 data17 data18 data19 data20 data21 SRAM_data22 data23 SRAM datapar2 data24 data25 data26 data27 4 SRAM data28 data29 data30 data31 SRAM dat
13. the like You can also connect a microphone to the Microphone in connector on the DE2 70 board your voice will be mixed with the music played from the audio player Figure 2 3 The default VGA output pattern 10 NDE o DE2 70 User Manual Jionv4 Chapter 3 DE2 70 Control Panel The DE2 70 board comes with a Control Panel facility that allows users to access various components on the board from a host computer The host computer communicates with the board through an USB connection The facility can be used to verify the functionality of components on the board or be used as a debug tool while developing RTL code This chapter first presents some basic functions of the Control Panel then describes its structure in block diagram form and finally describes its capabilities 3 1 Control Panel Setup The Control Panel Software Utility is located in the DE2_70_control_pane SW folder in the DE2 70 System CD ROM To install it just copy the whole folder to your host computer Launch the control panel by executing the DE2 70 Control Panel exe Specific control codes should be downloaded to your FPGA board before the control panel can request it to perform required tasks The control codes include one sof file and one e f file To download the codes just click the Download Code button on the program The program will call Quartus II and Nios II tools to download the control codes to the FPGA board through USB Blaster
14. to treat the information below as a short reference The DE2 70 board contains a serial EEPROM chip that stores configuration data for the Cyclone II FPGA This configuration data is automatically loaded from the EEPROM chip into the FPGA each time power is applied to the board Using the Quartus II software it 15 possible to reprogram the FPGA at any time and it is also possible to change the non volatile data that 15 stored in the serial EEPROM chip Both types of programming methods are described below 1 JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream 15 downloaded directly into the Cyclone II FPGA The FPGA will retain this configuration as long as power 15 applied to the board the configuration 15 lost when the power 15 turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the Altera EPCSIO serial EEPROM chip It provides non volatile storage of the bit stream so that the information is retained even when the power supply to the DE2 70 board 15 turned off When the board s power 15 turned on the configuration data in the EPCS16 device is automatically loaded into the Cyclone II FPGA The sections below describe the steps used to perform both JTAG and AS programming For both methods the DE2 70 board is connected to a host computer via a USB cable Using this connection the boar
15. using the Nios II processor Demonstration Setup File Locations and Instructions e Project directory DE2 70 NET e Bit stream used DE2 70 NET sof e Nios II Workspace DE2 70 NETNSoftware e Plug aCAT5 loop back cable into the Ethernet connector of DE2 70 Load the bit stream into the FPGA e Run the Nios II IDE under the workspace DE2 70 NET e Click on the Compile and Run button e You should now be able to observe the contents of the packets received 64 byte packets sent 68 byte packets received because of the extra checksum bytes Figure 6 12 illustrates the setup for this demonstration 79 DE2 70 User Manual 10 100Mbps CAT 5 Cable Loopback Device z EE z VEU C E ee C EE P E 1 tt ee LO uno mt Mn e PER H t 200 peaz mi wur Em ES EE m 1 nma ca mm Ethernet Driver Figure 6 12 The setup for the Ethernet demonstration 6 5 SD Card Music Player Many commercial media audio players use a large external storage device such as an SD card or CF card to store music or video files Such players may also include high quality DAC devices so that good audio quality can be produced The DE2 70 board provides the hardware and software needed for SD card access and professional audio performance so that it 1s possible to design advanced multimedia products using the DE2 70 board In this demonstration we show how to implement an SD Card Music Player on the DE2 70 board
16. when in the DOWN closest to the edge of the DE2 70 board position and logic 1 when in the UP position Clock inputs 50 MHz oscillator 28 63 MHz oscillator e SMA external clock input V Bodh DE2 70 User Manual O S RYA Audio CODEC e Wolfson WM8731 24 bit sigma delta audio CODEC Line level input line level output and microphone input jacks e Sampling frequency 8 to 96 KHz e Applications for MP3 players and recorders PDAs smart phones voice recorders etc VGA output e Uses the ADV7123 140 MHz triple 10 bit high speed video DAC e With 15 pin high density D sub connector e Supports up to 1600 x 1200 at 100 Hz refresh rate e Can be used with the Cyclone II FPGA to implement a high performance TV Encoder NTSC PAL SECAM TV decoder circuit Uses two ADV7180 Multi format SDTV Video Decoders Supports worldwide NTSC PAL SECAM color demodulation e One 10 bit ADC 4X over sampling for CVBS e Supports Composite Video CVBS RCA jack input e Supports digital output formats 8 bit ITU R BT 656 YCrCb 4 2 2 output HS VS and FIELD e Applications DVD recorders LCD TV Set top boxes Digital TV Portable video devices and PIP picture in picture display 10 100 Ethernet controller e Integrated MAC and PHY with a general processor interface e Supports 100Base T and IOBase T applications e Supports full duplex operation at 10 Mb s and 100 Mb s with auto MDIX e Fully compliant with the IEEE 802 3u Specif
17. 0 User Manual S RYA Figure 5 21 IrDA schematic IRDA TXD PIN W 1 IRDA Transmitter IRDA RXD PIN W22 IRDA Receiver Table 5 18 IrDA pin assignments 5 16 Using SDRAM SRAM Flash The DE2 70 board provides a 2 Mbyte SSRAM 8 Mbyte Flash memory and two 32 Mbyte SDRAM chips Figures 5 22 5 23 and 5 24 show the schematics of the memory chips The pin assignments for each device are listed in Tables 5 19 5 20 and 5 21 The datasheets for the memory chips are provided in the Datasheet Memory folder on the DE2 70 System CD ROM 57 T DRAM_DJ0 34 DRAMO A 0 12 DRAMI AJ 0 12 DRAMO AO DRAMO DRAMO A2 DRAMO A3 DRAMO A4 DRAMO A5 DRAMO A6 DRAMO A7 DRAMO A8 DRAMO DRAMO A10 DRAMO AT1 DRAMO A12 26 DRAMO CLK L 3 CKE DRAMO LDQMO DRAMO UDOMI ag DRAMO WE n 4e gt DRAMO CAS n gt DRAMO RAS n 1a Z DRAMO CS n 8 S CS DRAMO BAO 27 DRAMO BA DR_VCC33 DE2 70 User Manual DR_VCC33 DRAM DO DRAM1_ AO DRAM D1 DRAMI Al P DRAM D2 DRAMI A2 DRAM D3 DRAMI A3 2 DRAM D4 DRAMI A4 z DRAM D5 DRAMI A5 A DRAM D6 DRAM1_AG DRAM D7 DRAM1_A7 DRAM D8 DRAM1_A8 DRAM D9 DRAMI A9 7 DRAM D10 DRAMI A10 DRAM D11 DRAMI A11 SDRAM 16Mx1 i AR DRAM D12 DRAMI A12 n SDRAM 16Mx1877 1 DRAMI CLK D13 UL HE ES 5 D13 DRAM D14 DRAMI CKE D14 9 D14 DRAM D15 DRAMI LDQMO T l
18. 2 2 component video data compatible with the 8 bit ITU R BT 656 interface standard The ADV7180 is compatible with a broad range of video devices including DVD players tape based sources broadcast sources and security surveillance cameras The registers in both of the TV decoders can be programmed by a serial I2C bus which 1s connected to the Cyclone II FPGA as indicated in Figure 5 18 Note that the I2C address of the TV decoder 1 U11 and TV decoder 2 U12 are 0x40 and 0x42 respectively The pin assignments are listed in Table 5 16 Detailed information on the ADV7180 is available on the manufacturer s web site or in the Datasheet TV Decoder folder on the DE2 70 System CD ROM 52 V VCC33 VGND D83 BAT54S 0 1u L TD1 RESET VGND C27 0 1u 6 C28 29 O 1ul 0 1u 28MHZ I2C ADDRESS IS 0x40 V_VCC330 lac SCLK 4 Be SPAT 34 z lt 120 SDAT V VCC33 VGND D84 BAT54S RCA JACK TD2 RESET n C33 0 1u 6 C34 0 11 0 11 28MHZ 26 ADDRESS IS 0x42 y vccaao p l2C SCLK 34 20 SDAT Figure 5 18 V VCC33 O V_VCC18 AV1_VCC18 O O Si O QE U11 AIN1 AIN2 AIN3 RESET VREFN VREFP ADV7180 XTAL XTAL1 ALSB PWRDWN V VCC33 V_VCC18 AV2_VCC18 O U12 G AIN1 AIN2 AIN3 RESET VREFN VREFP ADV7180 XTAL 1 58 PWRDWN VS FIELD HS DE2 70 User Manual cI TD1 DIO 7 PV1 VCC18 Q 31 0 1u C30 R91 10n 1 74K
19. 8 2 R109 NZ 2K 2K N W 20 SDAT lt 126 SCLK SCLK R103 330 age 20 ADDRESS READ IS 0x34 ON oid C40 5 l2C ADDRESS WRITE IS 0x35 U13 PHONE JACK P u R104 680 L l C42 R105 8 Vege AGND OA_VCC33 jn 47K J12 LINE OUT al AGND AGND EXPOSED DACDAT DACLRCK ADCDAT ADCLRCK HPVDD LHPOUT RHPOUT AUD_ADCLRCK dm z O A VCC33 Ww N AGND AGND Figure 5 14 Audio CODEC schematic Table 5 12 Audio CODEC pin assignments 48 NBre o DE2 70 User Manual JionVv4 5 9 RS 232 Serial Port The DE2 70 board uses the ADM3202 transceiver chip and a 9 pin D SUB connector for RS 232 communications For detailed information on how to use the transceiver refer to the datasheet which is available on the manufacturer s web site or in the Datasheet RS232 folder on the DE2 70 System CD ROM Figure 5 15 shows the related schematics and Table 5 13 lists the Cyclone II FPGA pin assignments RXD LEDR R44 330 AX UART RXD VCC33 TXD LEDG R45 330 AX UART TXD Table 5 13 RS 232 pin assignments 5 10 PS 2 Serial Port The DE2 70 board includes a standard PS 2 interface and a connector for a PS 2 keyboard or mouse In addition users can use the PS 2 keyboard and mouse on the DE2 70 board simultaneously by an plug an extension PS 2 Y Cable Figure 5 16 shows the schematic of the PS 2 circuit Instructions for using a PS 2 mouse or keyboard can be found by performing an appropriate sear
20. 90 MHZ Audio Audio MIC In Controller Chip Line In Line Out LCD Module Seg 7 Device LCD Controller Seg 7 Controller ME 1 1081051811 uo E Ay PIO Controller Figure 6 13 Block diagram of the SD music player demonstration Figure 6 14 shows the software stack of this demonstration SD 1 Bit Mod block implements the SD 1 bit mode protocol for reading raw data from the SD card The FAT16 block implements FATI6 file system for reading wave files that stored in the SD card In this block only read function is implemented The WAVE Lib block implements WAVE file decoding function for receiving audio signal from wave files The I2C block implements I2C protocol for configuring audio chip The SEG7 block implements displaying function for display elapsed playing time The Audio block implements audio FIFO checking function and audio signal sending receiving function 81 NBre o DE2 70 User Manual Jionv4 FAT 16 SD 1 Bit Mode NIOS HAL Figure 6 14 Software Stack of the SD music player demonstration The audio chip should be configured before sending audio signal to the audio chip The main program uses I2C protocol to configure the audio chip working in master mode the audio interface as 12 with 16 bits per channel and sampling rate according to the wave file content In audio playing loop the main program reads 512 byte audio data from the SD card and then writes the data to DAC FIFO
21. A port of the board 2 Click Load button and specify an image file for displaying It can be a bitmap or jpeg file The selected image file will be displayed on the display window of the Video Utility 3 Select the desired Image Positioning method to fit the image to the VGA 640x480 display dimension Click Display button to start downloading the image to the DE2 70 board 5 After finish downloading you will see the desired image shown on the screen of the VGA monitor 26 INDIE SYAN DE2 70 User Manual Video Utility V1 0 0 Display Capture Image Position STRETCH Dimension 640 x 480 Pixels Load Display Download Code Disconnect Exit Connected display success 6 4 sec Figure 4 2 Displaying selected image file on VGA Monitor 4 3 Video Capture Choosing the Capture tab leads to the window in Figure 4 3 The function is designed to capture an image from the video sources and sent the image from the FPGA board to the host computer The input video source can be PAL or NTSC signals Please follow the steps below to capture an image from a video source 1 Connect a video source such as a VCD DVD player or NTSC PAL camera to VIDEO IN 1 or VIDEO IN 2 port on the board Specify Video Source as VIDEO IN 1 or VIDEO IN 2 3 Click Capture button to start capturing process Then you will see the captured image shown in the display window of the Video Utility The image dimension of the captured image is also d
22. A programming and control DE2 70 System CD containing the DE2 70 documentation and supporting materials including the User Manual the Control Panel utility reference designs and demonstrations device datasheets tutorials and a set of laboratory exercises CD ROMs containing Altera s Quartus II Web Edition and the Nios II Embedded Design Suit Evaluation Edition software Bag of six rubber silicon covers for the DE2 70 board stands The bag also contains some extender pins which can be used to facilitate easier probing with testing equipment of the board s I O expansion headers Clear plastic cover for the board 12V DC wall mount power supply The DE2 70 Board Assembly To assemble the included stands for the DE2 70 board Assemble a rubber silicon cover as shown in Figure 1 2 for each of the six copper stands on the DE2 70 board The clear plastic cover provides extra protection and 15 mounted over the top of the board by using additional stands and screws F Figure 1 2 The feet for the DE2 70 board 1 3 Here are the addresses where you can get help if you encounter problems Getting Help Altera Corporation 101 Innovation Drive San Jose California 95134 USA Email university altera com Terasic Technologies No 356 Sec 1 Fusing E Rd Jhubei City HsinChu County Taiwan 302 Email support terasic com Web DE2 70 terasic com DE2 70 User Manual DE2 70 User Manual Chapter 2 Altera D
23. B Config Blaster Dev Figure 2 2 Block diagram of the DE2 70 board Following is more detailed information about the blocks in Figure 2 2 Cyclone II 2C70 FPGA 68 416 LEs 250 M4K RAM blocks 1 152 000 total RAM bits 150 embedded multipliers 4 PLLs 622 user I O pins FineLine BGA 896 pin package Serial Configuration device and USB Blaster circuit Altera s EPCS16 Serial Configuration device On board USB Blaster for programming and user API control JTAG and AS programming modes are supported BoM DE2 70 User Manual ADER SSRAM 2 Mbyte standard synchronous SRAM e Organized as 512K x 36 bits e Accessible as memory for the Nios II processor and by the DE2 70 Control Panel SDRAM e Two 32 Mbyte Single Data Rate Synchronous Dynamic RAM memory chips e Organized as 4M x 16 bits x 4 banks e Accessible as memory for the Nios II processor and by the DE2 70 Control Panel Flash memory 8 Mbyte NOR Flash memory e Support both byte and word mode access e Accessible as memory for the Nios II processor and by the DE2 70 Control Panel SD card socket Provides SPI and 1 bit SD mode for SD Card access e Accessible as memory for the Nios II processor with the DE2 70 SD Card Driver Pushbutton switches e 4 pushbutton switches Debounced by a Schmitt trigger circuit e Normally high generates one active low pulse when the switch is pressed Toggle switches e 18 toggle switches for user inputs e A switch causes logic 0
24. Bus Specification Rev 2 0 supporting data transfer at full speed 12 Mbit s and low speed 1 5 Mbit s Figure 5 20 shows the schematic diagram of the USB circuitry the pin assignments for the associated interface are listed in Table 5 17 Detailed information for using the ISP1362 device is available in its datasheet and programming guide both documents can be found on the manufacturer s web site or in the Datasheet USB folder on the DE2 70 System CD ROM The most challenging part of a USB application is in the design of the software driver needed Two complete examples of USB drivers for both host and device applications can be found in Sections 6 4 and 6 5 These demonstrations provide examples of software drivers for the Nios II processor H VCC5 H VCC5 VCC33 E i E D 0 15 oO D85 D86 T ei AY OOJOO U VCC5 BAT54S BAT54S OOO OOO J13 gt gt gt gt gt gt FR RA H SUSPEND H SUSWKUP 33 A 5 A0 H SUSPEND D SUSWKUP 34 OTG D15 18 ic C48 C49 ENSE D15 VDD 99 oU VCC5 gt 11 USB A TYPE 4 47p 47p n al H OC2 118 R112 A22 Bo 10 14 FLDMS f 37 R113 22 H DP2 AV 42 HOCI Q H_PSW1 R116 22 R114 R115 OTG_DM1 6 Ord pei 50 R117 22 15K 15K D4 ISP1362 48 R118 4 7K E he D3 ID BOY ga oU _VCC33 E D2 OTGMODE as Rig An
25. DATA O ENET DATA 1 ENET_DATA 2 ENET DATA 3 DATA 4 DATA 5 DATA 6 ENET_DATAI7 ENET DATA 9 ENET 10 ENET 11 ENET DATA 12 ENET DATA 13 ENET DATA 14 ENET DATA 15 PIN B23 PIN D27 PIN B27 ENET CLK ENET CMD N VCC250 Anm 0 1u DE2 70 User Manual N VCC33 O R72 NGND BC36 BC37 N veo L2 BEAD RX RX TG Tu a ee L TX DM9000A 8 16bt TX DM9000AE ENET D9 ENET D10 ENET D11 ENET D12 ENET D13 wo Qa D 9 uw x Ed z t a D e aa S ENET D14 ENET D15 ENET DO ENET D1 ENET D2 ENET D3 ENET D4 ENET D5 ENET D6 ENET D7 Fast Ethernet schematic DM9000A DATA 15 DM9000A Clock 25 MHz DM9000A Command Data Select 0 Command 1 Data 51 ENET RESET e ENET CS n ENET lOw 35 ENET IOR n INT L ENET CMD lt ON_VCC33 ON_VCC33 NDE o DE2 70 User Manual JionVv4 ENET CS N PIN C28 DM9000A Chip Select ENET INT PIN C27 DM9000A Interrupt ENET_IOR_N PIN A28 DM9000A Read IOW N PIN B28 DM9000A Write ENET RESET N PIN B29 DM9000A Reset Table 5 15 Fast Ethernet pin assignments 5 12 TV Decoder The DE2 70 board is equipped with two Analog Devices ADV7180 TV decoder chips The ADV7180 is an integrated video decoder that automatically detects and converts a standard analog baseband television signal NTSC PAL and SECAM into 4
26. E2 70 Board This chapter presents the features and design characteristics of the DE2 70 board 2 1 Layout and Components A photograph of the DE2 70 board is shown in Figure 2 1 It depicts the layout of the board and indicates the location of the connectors and key components Ethernet 10 100M Port USB Device Port Micin Line In Line Out VGA Out RS 232 Port USB Blaster Port USB Host Port Video In 1 Ms In 2 i U T E TV Decoder NTSC PAL X2 12V DC Power Supply lt gt PS2 Port Connector i sem E 7 i d EEUU dm p P 4 e VGA 10 bit DAC Power ON OFF Switch m oe d al Ethernet 10 100M Controller USB Host Slave 5 Controller 3 Audio CODEC T gt ja TR Altera USB Blaster 50Mhz Oscillator Controller chipset WANI 2S cH E Expansion Header 2 um ccce Altera EPCS16 Configuration Device le o 7 eel bbl LLL 3 Expansion Header 1 RT T5 E AMRERERMEREREREMEMESANAEAESRAME E RUN PROG Switch for dnm JTAG AS Modes M LES 1 G E CS 1 ter CELLS SD Card Slot www teros m SD Card Not Included S Hiit m im p mm ve Altera Cyclone 16x2 LCD Module 5 EH gine Se See hte kee bee amen di FPGA with 70K LEs S ALORS OBERE RR BR NL AL USE P Ge d IrDA Transceiver 7 Seg
27. E2 70 User Manual B 4 PIN H28 GPIO Connection 1 IO 4 Table 5 8 Pin assignments for the expansion headers DE2 70 User Manual 5 7 Using VGA The DE2 70 board includes a 16 pin D SUB connector for VGA output The VGA synchronization signals are provided directly from the Cyclone II FPGA and the Analog Devices ADV7123 triple 10 bit high speed video DAC 15 used to produce the analog data signals red green and blue The associated schematic 1s given in Figure 5 12 and can support resolutions of up to 1600 x 1200 pixels at 100 MHz VGA_VCC33 em E Wo a O 3 15 515151 5 515 RBO 7K gt gt gt gt gt gt gt gt gt gt R81 560 RSET BC47 BC48 VGA R 0 9 D 0 1u 0 1u VGA 0 9 uio VGA B O 9 VGA GO VGA Gi VGA G2 VGA R VGA G SS VOACB VGA G4 IOR 25 VGA B VGA G5 6 VGA G6 ADV7123 IOG Fan VGA G7 5 SANI og R82 R83 R84 VGA G8 28 VGA G9 IOB 5 7557575 VGA BLANK n G9 BUE og L S SYNC n 12 los 1 VGA HS R85 4 Z wWvGA VS R86 4 VGA B3 VGA B8 x Q O E 5 gt VGA_BO VGA_B1 VGA_B2 VGA_B4 VGA_B5 VGA_B6 VGA_B7 VGA_B9 O VGA_VCC33 Figure 5 12 VGA circuit schematic The timing specification for VGA synchronization and RGB red green blue data can be found on various educational web sites for example search for VGA signal timing Fig
28. Headers with diode protection In addition to these hardware features the DE2 70 board has software support for standard I O interfaces and a control panel facility for accessing various components Also software is provided for a number of demonstrations that illustrate the advanced capabilities of the DE2 70 board In order to use the DE2 70 board the user has to be familiar with the Quartus II software The necessary knowledge can be acquired by reading the tutorials Getting Started with Altera s DE2 70 Board and Quartus II Introduction which exists 1n three versions based on the design entry method used namely Verilog VHDL or schematic entry These tutorials are provided in the directory DE2_70_tutorials on the DE2 70 System CD ROM that accompanies the DE2 70 board and can also be found on Altera s DE2 70 web pages 2 2 Block Diagram of the DE2 70 Board Figure 2 2 gives the block diagram of the DE2 70 board To provide maximum flexibility for the user all connections are made through the Cyclone II FPGA device Thus the user can configure the FPGA to implement any system design DE2 70 User Manual 50Mhz 28Mhz Ext In USB 2 0 Host Device 24 bit Audio CODEC 10 100 Ethernet PHY MAC XSGA 10 bit Video DAC SD Card TV Decoder 2 Cyclone FPGA 2010 IrDA Transceiver User Green LEDs 9 Flash 8 Mbyte User Red LEDs 18 SDRAM 64 Mbyte SRAM 2 Mbyte 7 SEG Display 8 Expansion Headers 2 EPCS16 US
29. RN44 47 L 16 DO ie A 15 TOT Di ET manam Py 4 TD1 D2 Po 4 L 13 TLDS FR sh A 1 TOL D4 z 11 TDt D5 Eo Al 15 Aja UR R92 120 TD1 VS 9 R93 120 TDI H3 lt 1 TDi CLK27 TD2 DIO 7 PV2 VCC18 Q 37 0 1u C36 R96 1 74K 47 TD2 DO TD2 D1 MAL 14 TB2 De TD2 D3 TD2 D4 TD2 D5 TD2 D6 ID2 D7 120 TD2 VS 120 TD2 H lt TD2 CLK27 TV Decoder schematic e DE2 70 User Manual Jianv4 TD1 CLK27 PIN G15 TV Decoder 1 Clock Input Table 5 16 TV Decoder pin assignments 5 13 Implementing a TV Encoder Although the DE2 70 board does not include a TV encoder chip the ADV7123 10 bit high speed triple ADCs can be used to implement a professional quality TV encoder with the digital processing part implemented in the Cyclone II FPGA Figure 5 19 shows a block diagram of a TV encoder implemented in this manner TV Encoder Block Cyclone 2070 O Composite 5 ir Y U cos V sin Clock Calculate or Y S Video Timing Composite or RCA Y C U cos V sin SIN or RCA Pb cos Tables Figure 5 19 ATV Encoder that uses the Cyclone II FPGA and the ADV7123 54 BoM DE2 70 User Manual ADER 5 14 Using USB Host and Device The DE2 70 board provides both USB host and device interfaces using the Philips ISP1362 single chip USB controller The host and device controllers are compliant with the Universal Serial
30. USB 0 connection The sof file is downloaded to FPGA The e f file is downloaded to either SDRAM U2 or SSRAM according to the user option To activate the Control Panel perform the following steps 1 Make sure Quartus II and NIOS II are installed successfully on your PC 2 Connect the supplied USB cable to the USB Blaster port connect the 12V power supply and turn the power switch ON Set the RUN PROG switch to the RUN position Start the executable DE2 70 control panel exe on the host computer The Control Panel user interface shown in Figure 3 1 will appear 5 Select the target memory SDRAM U2 or SSRAM on the control panel Note The e f file will be downloaded to the target memory and the memory will be read only in later memory access operation 6 Click Download Code button Note the Control Panel will occupy the USB port until you 11 DE2 70 User Manual close that port you cannot use Quartus II to download a configuration file into the FPGA until you close the USB port 7 The Control Panel is now ready for use experiment by setting the value of some LEDs display and observing the result on the DE2 70 board Control Panel V1 0 0 JLEDGO LEDREB ILEDG1 LEDR _JLEDG2 JJLEDRB _ILEDGS3 LEDR8 ILEDG4 LEDR1U LEDGES LEDR11 LEDIGB LEDR12 JLEDR13 _ILEDG8 LEDR14 ETIN EE LEDRD LEDR15 Product Mame ILEDR1 LEDR16 DE 70 ILEDR 2 LEDR17 JLEDR3 ILEDR4 JILEDRS http www altera com Light All Un
31. a Memory Product Name DE 2 70 sequential Fead Address ngnnon Length 000000 M Entire Memory Load Merory Content to a File hitp www altera com ter asic Target Memory WWW DET BAIG EO About SDRAM U2 Download Code Disconnect Exit Connected ISDRAM LIT Random Write Success Figure 3 7 Accessing the SDRAM UI A 16 bit word can be written into the SDRAM by entering the address of the desired location specifying the data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 3 7 depicts the result of writing the hexadecimal value 6 into location 200 followed by reading the same location The Sequential Write function of the Control Panel 15 used to write the contents of a file into the SDRAM as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be written in the Length box If the entire file is to be loaded then a checkmark may be placed in the File Length box instead of giving the number of bytes 3 initiate the writing of data click on the Write a File to Memory button When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Control Panel also supports loading files with a hex extension Files with a hex extension are ASCII text files that specify memory values using ASCII cha
32. a high logic level 3 3 volts when it 15 not pressed and provides a low logic level 0 volts when depressed Since the pushbutton switches are debounced they are appropriate for use as clock or reset inputs in a circuit Pushbutton depressed Pushbutton released Before Debouncing Schmitt Trigger Debounced e a Figure 5 3 Switch debouncing 32 DE2 70 User Manual There are also 18 toggle switches sliders on the DE2 70 board These switches are not debounced and are intended for use as level sensitive data inputs to a circuit Each switch is connected directly to a pin on the Cyclone II FPGA When a switch is in the DOWN position closest to the edge of the board it provides a low logic level 0 volts to the FPGA and when the switch is in the UP position it provides a high logic level 3 3 volts To use SW 7 you need to first change nCEO to Use as regular I O under Assignments Device Device amp Pin Options Dual Purpose Pins tab There are 27 user controllable LEDs on the DE2 70 board Eighteen red LEDs are situated above the 18 toggle switches and eight green LEDs are found above the pushbutton switches the 9 green LED is in the middle of the 7 segment displays Each LED is driven directly by a pin on the Cyclone II FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off A schematic diagram that shows the pushbu
33. an be found in the DE2_70_demonstrations folder from the DE2 70 System CD ROM For each of demonstrations described in the following sections we give the name of the project directory for its files which are subdirectories of the DE2 70_demonstrations folder Installing the Demonstrations To install the demonstrations on your computer perform the following 1 Copy the directory DE2_70_demonstrations into a local directory of your choice It is important to ensure that the path to your local directory contains no spaces otherwise the Nios II software will not work 6 1 DE2 70 Factory Configuration The DE2 70 board is shipped from the factory with a default configuration that demonstrates some of the basic features of the board The setup required for this demonstration and the locations of its files are shown below Demonstration Setup File Locations and Instructions e Project directory DE2_70_Default e Bit stream used DE2_70_Default sof or DE2_70_Default pof e Power on the DE2 70 board with the USB cable connected to the USB Blaster port If necessary that is if the default factory configuration of the DE2 70 board is not currently stored in EPCS16 device download the bit stream to the board by using either JTAG or AS programming e You should now be able to observe that the 7 segment displays are displaying a sequence of characters and the red and green LEDs are flashing Also Welcome to the Altera DE2 70 is Shown o
34. and also provides DC VCC5 DC 3 3V VCC33 and two GND pins Among these 36 I O pins 4 pins are connected to the PLL clock input and output pins of the FPGA allowing the expansion daughter cards to access the PLL blocks in the FPGA The voltage level of the I O pins on the expansion headers can be adjusted to 3 3V 2 5V or 1 8V using JP1 Because the expansion I Os are connected to the BANK 5 of the FPGA and the VCCIO voltage VCCIOS of this bank is controlled by the header JP1 users can use a jumper to select the input voltage of VCCIOS to 3 3V 2 5V and 1 8V to control the voltage level of the I O pins Table 5 7 lists the jumper settings of the The pin outs of the appear in the Figure 5 10 Finally Figure 5 11 shows the related schematics Each pin on the expansion headers is connected to two diodes and a resistor that provide protection from high and low voltages The figure shows the protection circuitry for only two of the pins on each header but this circuitry is included for all 72 data pins Table 5 8 gives the pin assignments Short Pins 1 and 2 Short Pins 5 and 6 Short Pins 3 and 4 Table 5 7 Voltage level setting of the expansion headers using JP1 41 DE2 70 User Manual 1 8V 2 5V 3 3V 2 4 6 ji 9 9 9 ee 1 3 5 Figure 5 10 pin settings VCCIO5 VCCIOS GPIO 0 J4 IO CLKINnO is A0 IO CLKINpO Io T IO
35. apar3 LA DE2 70 User Manual DE2 70 User Manual 60 DE2 70 User Manual DRAMO CKE PIN AA8 SDRAM 1 Clock Enable 61 DE2 70 User Manual DRAM1_RAS_N 9 SDRAM 2 Row Address Strobe DRAM1 CAS N PIN N8 SDRAM 2 Column Address Strobe DRAM1 CKE PIN L10 SDRAM 2 Clock Enable DRAM1 CLK PIN G5 SDRAM 2 Clock DRAM1 WE N PIN M9 SDRAM 2 Write Enable DRAM1 CS N PIN P9 SDRAM 2 Chip Select Table 5 19 SDRAM pin assignments 62 DE2 70 User Manual 8 PIN AK17 SRAM Data 8 63 DE2 70 User Manual SRAM_DPA2 PIN AK20 SRAM Parity Data 2 SRAM_DPA3 PIN AJ9 SRAM Parity Data 3 SRAM GW N PIN AG18 SRAM Global Write Enable SRAM OE N PIN AD18 SRAM Output Enable SRAM WE N PIN AF18 SRAM Write Enable Table 5 20 SSRAM pin assignments 64 DE2 70 User Manual FLASH DQ 5 PIN AB29 FLASH Data 5 FLASH WP N FLASH Write Protect Programming Acceleration Table 5 21 Flash pin assignments 65 NBTE m DE2 70 User Manual Chapter 6 Examples of Advanced Demonstrations This chapter provides a number of examples of advanced circuits implemented on the DE2 70 board These circuits provide demonstrations of the major features on the board such as its audio and video capabilities and USB and Ethernet connectivity For each demonstration the Cyclone II FPGA or EPCS16 serial EEPROM configuration file 15 provided as well as the full source code in Verilog HDL code All of the associated files c
36. asheet which can be found on the manufacturer s web site and from the Datasheet LCD folder on the DE2 70 System CD ROM A schematic diagram of the LCD module showing connections to the Cyclone II FPGA is given in Figure 5 9 The associated pin assignments appear in Table 5 6 Q1 8050 Q2 8550 VCC430 680 LCD ON R35 680 Q3 gt m VCC43 Q4 8550 VCC430 R38 1K LCD DIO 7 R36 680 oholelcolaul lolzizlnbolo R39 m mi or LCD BLON R37 680 Q5 Q aiaameaaaaaa 47 Ls 8050 Sees e a O aZ DIS1 2 X 16 DIGIT LCD LCD 2x16 Figure 5 9 Schematic diagram of the LCD module LCD DATA O PIN LCD Data O0 LCD PIN E3 LCD Data 1 LCD DATA PIN D2 LCD Data 2 LCD 3 PIN D3 LCD Data 3 LCD DATAI 4 PIN C1 LCD Data 4 40 mo DE2 70 User Manual JN OS RYA LCD PIN C2 LCD Data 5 LCD RW LCD Read Write Select 0 Write 1 Read LCD EN LCD Enable LCD RS PIN F2 LCD Command Data Select 0 Command 1 Data LCD ON PIN F1 LCD Power ON OFF LCD BLON PIN G3 LCD Back Light ON OFF Table 5 6 Pin assignments for the LCD module Note that the current LCD modules used on DE2 DE2 70 boards do not have backlight Therefore the LCD BLON signal should not be used in users design projects 5 6 Using the Expansion Header The DE2 70 Board provides two 40 pin expansion headers Each header connects directly to 36 pins of the Cyclone II FPGA
37. ch on various educational web sites The pin assignments for the associated interface are shown in Table 5 14 49 PS2 KBDAT n PS2 MSCLK D9 BAT54S VCC33 PS2 KBCLK PS2 MSDAT Lo oo R49 w R SS O Aa OE DE2 70 User Manual VCC5 VCC5 Q Q Q R46 R47 R172 R173 2K 2K R48 120 D10 D95 D96 BAT54S BAT54S BAT54S TUM I O UN VCC33 VCC33 VCC33 Figure 5 16 PS 2 schematic PIN F24 PS 2 Clock PIN E24 PS 2 Data PIN D26 PS 2 Clock reserved for second PS 2 device PIN D25 PS 2 Data reserved for second PS 2 device Table 5 14 PS 2 pin assignments 5 11 Fast Ethernet Network Controller The DE2 70 board provides Ethernet support via the Davicom DM90004A Fast Ethernet controller chip The DM9000A includes a general processor interface 16 Kbytes SRAM a media access control MAC unit and a 10 100M PHY transceiver Figure 5 17 shows the schematic for the Fast Ethernet interface and the associated pin assignments are listed in Table 5 15 For detailed information on how to use the DM9000A refer to its datasheet and application note which are available on the manufacturer s web site or in the Datasheet Ethernet folder on the DE2 70 System CD ROM 50 ae ENET Df0 15 N VCC33O N VCC33O RJ45INTLED E xa CHSGND 0 1u NGND NGND 120 SPEED R78 120 ACT Figure 5 17
38. d the data input from the line in port 15 then mixed with the microphone in port and the result is sent to the line out port For this demonstration the sample rate is set to 48 kHz Pressing the pushbutton KEYO reconfigures the gain of the audio CODEC via the I2C bus cycling through one of the ten predefined gains volume levels provided by the device 76 DE2 70 User Manual AVU n VA I2C Audio Line out Configuration Audio line Push Button CODEC Ine in Mic in ADC to DAC Figure 6 9 Block diagram of the Karaoke Machine demonstration Demonstration Setup File Locations and Instructions e Project directory DE2 70 i2sound e Bit stream used DE2 70_i2sound sof or DE2 70 i2sound pof e Connect a microphone to the microphone in port pink color on the DE2 70 board e Connect the audio output of a music player such as an MP3 player or computer to the line in port blue color on the DE2 70 board e Connect a headset speaker to the line out port green color on the DE2 70 board e Load the bit stream into the FPGA e You should be able to hear a mixture of the microphone sound and the sound from the music player e Press KEYO to adjust the volume it cycles between volume levels 0 to 9 Figure 6 10 illustrates the setup for this demonstration T7 DE2 70 User Manual vs or 1533 22 E AE ma ioi pi m 3 IT H Er i DE270 h BEER mee mee m ere aes T 3 rT l
39. d Play Status E T Un Ss lm E ax Record Play Duration Signal Strength Play Sample rate Record Audio Source MIC Boost Zero Cross Detect Figure 6 18 Man Machine Interface of Audio Recorder and Player Figure 6 19 shows the block diagram of the design of the Audio Recorder and Player There are hardware part and software part in the block diagram The software part means the Nios II program that stored in SSRAM The software part is built by Nios II IDE in C programming language The 87 DE2 70 User Manual AVU S RYA hardware part 1s built by SOPC Builder under Quartus II The hardware part includes all the other blocks The AUDIO Controller is a user defined SOPC component It is designed to send audio data to the audio chip or receive audio data from the audio chip The audio chip is programmed through I2C protocol which 15 implemented in C code The I2C pin from audio chip 1s connected to SOPC System Interconnect Fabric through PIO controllers In this example the audio chip is configured in Master Mode The audio interface 15 configured as I2S and 16 bit mode A 18 432MHz clock generated by the PLL is connected to the XTI MCLK pin of the audio chip through the AUDIO Controller 50M Hz Store SDRAM Audio RESE N SDRAM Data SRAM dumm SRAM Nios II JIAG Controller Program UART PIO 1 LED KEY SW D2C LCD Controller LCD uw ats
40. d through USB Blaseter US B 0 connection The sof file 15 downloaded to FPGA The e f file is downloaded to SDRAM UI To activate the Video Utility perform the following steps 1 Make sure Quartus II and Nios II are installed successfully on your PC 2 Connect the supplied USB cable to the USB Blaster port connect the 12V power supply and turn the power switch ON Set the RUN PROG switch to the RUN position Start the executable DE2 70 VIDEO exe on the host computer The Video Utility user interface shown in Figure 4 1 will appear 5 Click the Download Code button The Control Panel will occupy the USB port until you close that port you cannot use Quartus II to download a configuration file into the FPGA until you close the USB port 6 The Video Utility 15 now ready for use 25 DE2 70 User Manual Video Utility 0 0 Display Capture Image Position CENTER Dimension 640 x 480 Pixels Load Display Download Code Disconnect Exit Connected Download code success Figure 4 1 The DE2 70 Video Utility window 4 VGA Display Choosing the Display tab in the DE2 70 Video Utility leads to the window shown in Figure 4 2 The function is designed to download an image from the host computer to the FPGA board and output the image through the VGA interface with resolution 640x480 Please follow the steps below to exercise the Video Utility 1 Connect a VGA monitor to the VG
41. d will be identified by the host computer as an Altera USB Blaster device The process for installing on the host computer the necessary software device driver that communicates with the USB Blaster is described in the tutorial Getting Started with Altera s DE2 70 Board This tutorial is available on the DE2 70 System CD ROM 30 DE2 70 User Manual Configuring the FPGA in JTAG Mode Figure 5 1 illustrates the JTAG configuration setup To download a configuration bit stream into the Cyclone II FPGA perform the following steps Ensure that power 15 applied to the DE2 70 board Connect the supplied USB cable to the USB Blaster port on the DE2 70 board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch on the left side of the board to the RUN position The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof filename extension USB Blaster Circuit PROG RUN Quartus JTAG Confi RUN ps SAR JTAG Config Port Power on Config EPCS16 Serial Configuration Device Figure 5 1 The JTAG configuration scheme Configuring the EPCS16 in AS Mode Figure 5 2 illustrates the AS configuration set up To download a configuration bit stream into the EPCS 16 serial EEPROM device perform the following steps Ensure that power is applied to the DE2 70 board Connect the supplied USB cable to the USB Blas
42. ector which can be used to connect an external clock source to the board In addition all these clock inputs are connected to the phase lock loops PLL clock input pin of the FPGA allowed users can use these clocks as a source clock for the PLL circuit The clock distribution on the DE2 70 board is shown in Figure 5 8 The associated pin assignments for clock inputs to FPGA I O pins are listed in Table 5 5 38 DE2 70 User Manual GPIO_0 GPIO 1 2 2 SD Card 2 SMA Connector AUDIO CODEC 50 MHz 4 _ ___f __y Oscillator PS 2 Cyclone II FPGA 28 MHz TV Oscillator decoder 1 Ethernet TV decoder 2 ye DAC ES ppc SSRAM FLASH Figure 5 8 Block diagram of the clock distribution CLK 28 PIN E16 28 MHz clock input PIN AD15 50 MHz clock input CLK 50 CLK 50 2 PIN D16 50 MHz clock input PIN R28 50 MHz clock input PIN R3 50 MHz clock input CLK 50 3 CLK 50 4 EXT CLOCK External SMA clock input PIN R29 Table 5 5 Pin assignments for the clock inputs 39 E oy DE2 70 User Manual ADER 5 5 Using the LCD Module The LCD module has built in fonts and can be used to display text by sending appropriate commands to the display controller which is called HD44780 Detailed information for using the display is available in its dat
43. g tool 1 Choosing the USB tab leads to the window in Figure 3 8 2 Plug an USB mouse to the USB HOST port on the DE2 70 board 3 Press the Start button to start the USB mouse monitoring process and button caption 15 changed from Start to Stop In the monitoring process the status of the USB mouse 15 updated and shown in the Control Panel s GUI window in real time Press Stop to terminate the monitoring process 18 DE2 70 User Manual M Praduct Mame DE 70 http www altera com X298 Y 21b5 L1 R0 Stop ter WoW CEP com Connected usb mouse status checking Figure 3 8 USB Mouse Monitoring Tool 3 6 PS2 Device The Control Panel provides users a tool to receive the inputs from a PS2 keyboard in real time The received scan codes are translated to ASCII code and displayed in the control window Only visible ASCII codes are displayed For control key only Carriage Return ENTER key is implemented This function can be used to verify the functionality of the PS2 Interface Please follow the steps below to exercise the PS2 device Choosing the PS2 tab leads to the window in Figure 3 9 Plug a PS2 Keyboard to the FPGA board Then 3 Press the Start button to start PS2Keyboard input receiving process Button caption 15 changed from Start to Stop 4 In the receiving process users can start to press the attached keyboard The input data will be displayed in the control window in real ti
44. he demo sound users can press KEY 1 The TONE GENERATOR has two tones 1 String 2 Brass which can be controlled by SWO The audio codec used on the DE2 70 board has two channels which can be turned ON OFF using SW1 and SW2 Figure 6 17 illustrates the setup for this demonstration CYCLONE Il 2C70 VGA HS VGA VS DEMO1 CODE ICT OUND Demo CODE VGAR DAC VGAG VGAB SOUND1_CODE MUX STAFF SOUND2_CODE SOUND1 KEY1_CODE SOUND2 KEY2 CODE SOUND SENERATOR CODEC SOUND2 OFF SW 9 SWI 0 SW 2 1 Figure 6 17 Block diagram of the Music Synthesizer design Demonstration Setup File Locations and Instructions e Project directory DE2 70 Synthesizer 84 mo DE2 70 User Manual JN OS RYA e Bit stream used DE2 70 Synthesizer sof or DE2 70_Synthesizer pof e Connect a PS 2 Keyboard to the DE2 70 board e Connect the VGA output of the DE2 70 board to a VGA monitor both LCD and CRT type of monitors should work e Connect the Lineout of the DE2 70 board to a speaker e Load the bit stream into FPGA e Make sure all the switches SW 9 0 are set to 0 Down Position e Press KEYI on the DE2 70 board to start the music demo e Press KEYO on the DE2 70 board to reset the circuit Table 6 2 and 6 3 illustrate the usage of the switches pushbuttons KEYs PS 2 Keyboard e Switches and Pushbuttons KEY 1 Repeat the Demo Music SW 9 OFF DEMO ON PS2 KEYBOARD SW 1 Channel 1 ON OFF SWI2 Channel 2 ON OFF
45. ication e Supports IP TCP UDP checksum generation and checking e Supports back pressure mode for half duplex mode flow control USB Host Slave controller Complies fully with Universal Serial Bus Specification Rev 2 0 e Supports data transfer at full speed and low speed e Supports both USB host and device e Two USB ports one type A for a host and one type B for a device e Provides a high speed parallel interface to most available processors supports Nios II with a Terasic driver e Supports Programmed I O PIO and Direct Memory Access DMA 8 NDE o DE2 70 User Manual JionVv4 Serial ports One RS 232 port e One PS 2 port DB 9 serial connector for the RS 232 port e PS 2 connector for connecting a PS2 mouse or keyboard to the DE2 70 board IrDA transceiver e Contains a 115 2 kb s infrared transceiver e 32mALED drive current e Integrated EMI shield EC825 1 Class 1 eye safe e Edge detection input Two 40 pin expansion headers 72 Cyclone II I O pins as well as 8 power and ground lines are brought out to two 40 pin expansion connectors e 40 pin header is designed to accept a standard 40 pin ribbon cable used for IDE hard drives e Diode and resistor protection is provided 2 3 Power up the DE2 70 Board The DE2 70 board comes with a preloaded configuration bit stream to demonstrate some features of the board This bit stream also allows users to see quickly if the board is working properly To power up the board
46. ice in its USB device list and ask for the associated driver the device will be identified as a Philips PDIUSBDI2 SMART Evaluation Board After completion of the driver installation on the host computer the next step is to run a software program on the host computer called JSP1362DcUsb exe this program communicates with the DE2 70 board In the JSP1362DcUsb program clicking on the Add button in the window panel of the software causes the host computer to send a particular USB packet to the DE2 70 board the packet will be received by the Nios II processor and will increment the value of a hardware counter The value of the counter is displayed on one of the board s 7 segment displays and also on the green LEDs If 74 DE2 70 User Manual the user clicks on the Clear button in the window panel of the software driver the host computer sends a different USB packet to the board which causes the Nios II processor to clear the hardware counter to zero Link to Host PC Setup Package Pee Philips Enumeration ISP1362 Information Device Port Communication Figure 6 7 Block diagram of the USB device demonstration Demonstration Setup File Locations and Instructions e Project directory DE2 70 NIOS DEVICE LEDNIW e Bit stream used DE2 70 NIOS DEVICE LED sof e Nios Il Workspace DE2 70 NIOS DEVICE LEDNHWASoftware e Borland BC Software Driver DE2 70 NIOS DEVICE LEDNSW e Connect the USB Device connect
47. in the Audio Controller Before writing the data to the FIFO the program have to make sure the FIFO is not full The design also mixes the audio signal from the microphone in and line in for the Karaoke style effects by enabling the BYPASS and SITETONE functions in the audio chip Finally users can obtain the status of the SD music player from the 2x16 LCD module the 7 segment display and the LEDs The top and bottom row of the LCD module will display the file name of the music that 1s playing on the DE2 70 board and the value of music volume respectively The 7 segments display will show how long the music file has been played The LED will indicate the audio signal strength Demonstration Setup File Locations and Instructions e Project directory DE2 70 SD Card Audio Player e Bit stream used DE2 70 SD Card Audio Player sof e Nios II Workspace DE2 70 SD Card Audio PlayerNSoftware e Format your SD card into FAT 6 format e Put the played wave files to the root directory of the SD card The provided wave files must have a sample rate of either 96K 48K 44 1K 32K or 8K Besides the wave files must be stereo and 16 bits per channel Also the file name must be short filename Load the bitstream into the FPGA on the DE2 70 board Run the Nios II IDE under the workspace DE2_70_SD_Card_Audio_Playe Software e Connect a headset or speaker to the DE2 70 board and you should be able to hear the music played from the SD Card 82
48. ios II c Avalon MM SSRAM I Tri state Bridge Controller am 911181 JDVUUOIAIJUT 154 Figure 3 13 The block diagram of the DE2 70 control panel 24 V Bodh DE2 70 User Manual O S RYA Chapter 4 DE2 70 Video Utility The DE2 70 board comes with a video utility that allows users to access video components on the board from a host computer The host computer communicates with the board through the USB Blaster link The facility can be used to verify the functionality of video components on the board capture the video sent from the video in ports or display desired pattern on the VGA port This chapter first presents some basic functions of the Video Utility control panel then describes its structure in block diagram form and finally describes its capabilities 4 1 Video Utility Setup The Video Utility is located in the DE2_70_video utility SW folder in the DE2 70 System CD ROM To install it just copy the whole folder to your host computer Launch the Video Utility by executing the DE2 70 VIDEO exe Specific configuration files should be downloaded to your FPGA board before the Control Panel can request it to perform required tasks The configuration files include one sof file and one e f file To download the codes simply click the Download Code button on the program The program will call Quartus II and Nios II tools to download the control codes to the FPGA boar
49. isplayed 4 Users can click Save button to save the captured image as a bitmap or jpeg file 27 DE2 70 User Manual Video Utility V100 Display Capture Video Source VIDEO IN 1 Dimension 720x576 Save Capture Download Code Disconnect Exit Connected Video Capture success Dim 720x576 7 7 sec Figure 4 3 Video Capturing Tool 4 4 Overall Structure of the DE2 70 Video Utility The DE2 70 Video Utility is based on a NIOS II system running in the Cyclone II FPGA with the SDRAM U2 or SSRAM The software part is implemented in C code the hardware part 15 implemented in Verilog code with SOPC builder which makes it possible for a knowledgeable user to change the functionality of the Video Utility The code is located inside the DE2 70 demonstrations directory on the DE2 70 System CD ROM Figure 4 4 depicts the block diagram of the Video Utility Each input output device 15 controlled by the NIOS II Processor instantiated The communication between the DE2 70 board and the host PC is via the USB Blaster link The NIOS II processor interprets the commands sent from the PC and performs the appropriate actions 28 DE2 70 User Manual NIOS II Program S SDRAM NIOS II Controller SDRAM UI oy SDRAM Cc SDRAM U2 Controller VGA JTAG Blaster Hardware Controller Multi Port Key SSRAM SSRAM lt Controller Avalon MM Slave VIDEO In K N VIDEO IN Controller
50. layer 89 DE2 70 User Manual Chapter 7 Appendix 7 1 Revision History Version Change Log V1 0 Initial Version Preliminary V1 01 1 Add appendix chapter 2 Modify Chapter 2 3 4 5 6 V1 03 Modify clock frequency of the VGA DAC V1 02 Modify Figure 6 8 V1 04 Modify Section 5 4 7 3 Copyright Statement Copyright 2008 Terasic Technologies All rights reserved 90
51. light AlL ter asic Target Memory WWW DET BAIG EO SDRAM U2 Download Code Disconnect Exit Connected Download Code success Figure 3 1 The DE2 70 Control Panel If you get a Fail to connect FPGA board error message on starting the Control Panel program you can manually download the DE2_70_Control_Panel sof file using the Quartus Programmer and then run NiosDownloadBatch bat The concept of the DE2 70 Control Panel is illustrated in Figure 3 2 The Control Codes that performs the control functions is implemented in the FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical interface is used to issue commands to the control codes It handles all requests and performs data transfers between the computer and the DE2 70 board 12 DE2 70 User Manual 7 SEG Display alejas LCD USB Blaster Contro ontro PS 2 Codes Ps USB Device SD Card Soket LEDs Figure 3 2 The DE2 70 Control Panel concept The DE2 70 Control Panel can be used to light up LEDs change the values displayed on 7 segment and LCD displays monitor buttons switches status read write the SDRAM SSRAM and Flash Memory monitor the status of an USB mouse read data from a PS 2 keyboard and read SD CARD specification information The feature of reading writing a word or an entire file from to the Flash Memory allows the user to devel
52. me Press Stop to terminate the monitoring process 19 NBIS8 SYN DE2 70 User Manual Control Panel V1 0 0 LED 7 SEG LCD Button Memory USB PS2 SD CARD Audio PS2 Keyboard s Product Mame DE 70 http www altera com ter asic Target Memory AAA LET BAIC COM About SDRAM U2 Download Code Disconnect Exit Connected Figure 3 9 Reading the PS2 Keyboard 3 7 SDCARD The function is designed to read the identification and specification of the SD card The 1 bit SD MODE is used to access the SD card This function can be used to verify the functionality of SD CARD Interface Follow the steps below to exercise the SD card 1 Choosing the SD CARD tab leads to the window in Figure 3 10 First 2 Insert a SD card to the DE2 70 board then press the Read button to read the SD card The SD card s identification and specification will be displayed in the control window 20 DE2 70 User Manual LED 7 SEG LCD Button Memory USB PS2 SD CARD Audio ab CARD SD CARD Identification Manufacturer ID 3bEh OEM Applicatian ID 2D48h Praduct Name Product Revisian Dh Serlal No 00800595 Date Code 0075h SO CARD Specification CSD Version Mo 1 0 Read Access Time 20 ms Product Name Fead Access Time NSAC 1 x100 cycle DE 70 Max Data Transfer Rate 25 Mbits s Max Read Data Block Length 512 Byte NER Memory Capacity 122MB ti http www altera c
53. ment Displays hs 8Mbyte Flash Memory m3 T uses i 18 Red LEDs a d HE EL 8 Green LEDs n PN m no 18 Toggle Switches m FT ul a r1 alala hd Bed had 154 1S lt SMA Extemal Clock 32Mbyte SDRAMx2 28Mhz Oscillator 2Mbyte SSRAM 4 Push button Switches Figure 2 1 The DE2 70 board The DE2 70 board has many features that allow the user to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the DE2 70 board e Altera Cyclone II 2C70 FPGA device Altera Serial Configuration device EPCS16 e USB Blaster on board for programming and user API control both JTAG and Active Serial 4 NDE o DE2 70 User Manual JionVv4 AS programming modes are supported 2 Mbyte SSRAM e Two 32 Mbyte SDRAM 8 Mbyte Flash memory e SD Card socket 4 pushbutton switches e 18 toggle switches 18 red user LEDs 9 green user LEDs 50 MHz oscillator and 28 63 MHz oscillator for clock sources e 24 bit CD quality audio CODEC with line in line out and microphone in jacks e VGA DAC 10 bit high speed triple DACs with VGA out connector e 2 TV Decoder NTSC PAL SECAM and TV in connector e 10 100 Ethernet Controller with a connector e USB Host Slave Controller with USB type A and type B connectors e RS 232 transceiver and 9 pin connector e PS 2 mouse keyboard connector IrDA transceiver e SMA connector e Two 40 pin Expansion
54. n Ei gt Delay gt Timer DLY2 ee oe T Controller VGA HS DAC Decoder VGA Y VGA VS 7123 7180 TD HS edel To Control the ea e eye G TD_VS Initiation ce Detector Sequence m I I2C SCLK YUV 4 2 2 uve YCbCr E DC AV To Eze ue oe conte YUV 4 4 4 RGB Figure 6 1 Block diagram of the TV box demonstration Demonstration Setup File Locations and Instructions Project directory DE2_70_TV Bit stream used DE2_70_TV sof or DE2_70_TV pof Connect a DVD player s composite video output yellow plug to the Video IN 1 RCA jack J8 of the DE2 70 board The DVD player has to be configured to provide NTSC output o 60 Hz refresh rate 4 3 aspect ratio o Non progressive video Connect the VGA output of the DE2 70 board to a VGA monitor both LCD and CRT type of monitors should work Connect the audio output of the DVD player to the line in port of the DE2 70 board and connect a speaker to the line out port If the audio output jacks from the DVD player are of RCA type then an adaptor will be needed to convert to the mini stereo plug supported on the DE2 70 board this 1s the same type of plug supported on most computers Load the bit stream into FPGA Press KEYO on the DE2 70 board to reset the circuit Figure 6 2 illustrates the setup f
55. n the LCD display 66 V Bodh DE2 70 User Manual O S RYA Optionally connect a VGA display to the VGA D SUB connector When connected the VGA display should show a pattern of colors Optionally connect a powered speaker to the stereo audio out jack e Place toggle switch SW17 in the UP position to hear a 1 kHz humming sound from the audio out port Alternatively if switch SW17 1s DOWN the microphone in port can be connected to a microphone to hear voice sounds or the line in port can be used to play audio from an appropriate sound source The Verilog source code for this demonstration 1s provided in the DE2_70_Default folder which also includes the necessary files for the corresponding Quartus II project The top level Verilog file called DE2_70_Default v can be used as a template for other projects because it defines ports that correspond to all of the user accessible pins on the Cyclone II FPGA 6 2 TV Box Demonstration This demonstration plays video and audio input from a DVD player using the VGA output audio CODEC and one TV decoder U11 on the DE2 70 board Figure 6 1 shows the block diagram of the design There are two major blocks in the circuit called 26 AV Config and TV to VGA The TV to VGA block consists of the ITU R 656 Decoder SDRAM Frame Buffer YUV422 to YUV444 YCrCb to RGB and VGA Controller The figure also shows the TV Decoder ADV7180 and the VGA DAC ADV7123 chips used As soon as the bi
56. of code that drives a VGA display is described in Sections 6 2 6 3 and 6 4 Back porch b Front porch d Display interval HSYNC Sync a Figure 5 13 VGA horizontal timing specification DATA wwe os 19 ase 9 s 00 sense mem wr wel oo meme owe mem e es nme Dee omm pupa er er n mn owe wem oa 22 fos os e coo Table 5 9 VGA horizontal timing specification wow mem om 1 www mem 5 m www wem s wm xw meme s m mm 5 xem meme s m mm 3 Table 5 10 WGA vertical timing specification 46 DE2 70 User Manual Table 5 11 ADV7123 pin assignments 47 NDE DA DE2 70 User Manual WionVvA 5 8 Using the 24 bit Audio CODEC The DE2 70 board provides high quality 24 bit audio via the Wolfson WM8731 audio CODEC enCOder DECoder This chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz The WM8731 is controlled by a serial I2C bus interface which is connected to pins on the Cyclone II FPGA A schematic diagram of the audio circuitry 15 shown in Figure 5 14 and the FPGA pin assignments are listed in Table 5 12 Detailed information for using the WM8731 codec is available in its datasheet which can be found on the manufacturer s web site or in the Datasheet Audio CODEC folder on the DE2 70 System CD ROM J11 LINE IN VCC33 VCC33 R10
57. om Read ter asic Target Memory Www LET BAIC COM SDRAM U2 Download Code Disconnect Exit Connected SD CARD read success Figure 3 10 Reading the SD card Identification and Specification 3 8 Audio Playing and Recording This interesting audio tool is designed to control the audio chip on the DE2 70 board for audio playing and recording It can play audio stored in a given WAVE file record audio and save the audio signal as a wave file The WAVE file must be uncompressed stereo 2 channels per sample and 16 bits per channel Its sample rate must be either 96K 48K 44 1K 32K or 8K Follow the steps below to exercise this tool D oe tS Choosing the Audio tab leads to the window in Figure 3 11 To play audio plug a headset or speaker to the LINE OUT port on the board Select the Play Audio item in the com box as shown in Figure 3 11 Click Open Wave to select a WAVE file The waveform of the specified wave file will be displayed in the waveform window The sampling rate of the wave file also 15 displayed in the Sample Rate Combo Box You can drag the scrollbar to browse the waveform In the waveform window the blue line represents left channel signal and green line represents right channel signal Click Start Play to start audio play The program will download the waveform to SDRAM UI configure the audio chip for audio playing and then start the audio playing process You will hear the audio s
58. op multimedia applications Flash Audio Player Flash Picture Viewer without worrying about how to build a Memory Programmer 3 2 Controlling the LEDs 7 Segment Displays and LCD Display A simple function of the Control Panel is to allow setting the values displayed on LEDs 7 segment displays and the LCD character display Choosing the LED tab leads to the window in Figure 3 3 Here you can directly turn the individual LEDs on or off by selecting them or click Light All or Unlight AIP 13 LED Product Name DE 70 hittp www altera com ter asic Target Memory About SDRAM U2 WoW cerasir com MILEDGO MILEDG1 MILEDG MILEDGS MILEDG4 MILEDGS wILEDGB wILEDG wiLEDGB wILEDR v LEDR1 MILEDR2 wi LEDR3 MILEDR4 MILEDRS vi LEDRE LEDR i LEDRG MILEDRID vw LEDR11 v LEDRT12 v LEDR13 wILEDR14 v LEDR15 MILEDR16 MILEDR17 Light All Unlight AlL Connected Set Led Success Figure 3 3 Controlling LEDs Choosing the 7 SEG tab leads to the window in Figure 3 4 In the tab sheet directly use the Up Down control and Dot Check box to specified desired patterns the 7 SEG patterns on the board will be updated immediately Control Panel V1 0 0 Download Code Disconnect Exit DE2 70 User Manual SEG 12345678 dot dot dot dot dot dot dot dot Product Name E Em Em Er Em SIT EE E DE 70 http www altera com
59. or both LCD and CRT type of monitors should work e Connect the one audio output of the DVD player to the line in port of the DE2 70 board and connect a speaker to the line out port If the audio output jacks from the DVD player are of 70 DE2 70 User Manual RCA type then an adaptor will be needed to convert to the mini stereo plug supported on the DE2 70 board this is the same type of plug supported on most computers Load the bit stream into FPGA e The detailed configuration for switching video source of main and sub window are listed in Table 6 1 Figure 6 4 illustrates the setup for this demonstration DETTY VGA Out Figure 6 4 The setup for the TV box PIP demonstration SW 17 OFF Signal display mode T1 NDE o DE2 70 User Manual JionVv4 SW 16 OFF SW 17 OFF Signal display mode Video in 1 SW 16 ON SW 17 ON Main window Video in 2 PIP display mode SW 16 OFF Sub window Video in 1 SW 17 ON Main window Video in 1 PIP display mode SW 16 ON Sub window Video in 2 Table 6 1 The setup for the TV box PIP demonstration 6 4 USB Paintbrush USB is a popular communication method used in many multimedia products The DE2 70 board provides a complete USB solution for both host and device applications In this demonstration we implement a Paintbrush application by using a USB mouse as the input device This demonstration uses the device port of the Philips ISP1362 chip
60. or of the DE2 70 board to the host computer using a USB cable type A gt B e Load the bit stream into FPGA e Run Nios IL IDE with HW as the workspace Click on Compile and Run e A new USB hardware device will be detected Specify the location of the driver as DE2_70_NIOS_DEVICE_LED D12test inf Philips PDIUSBDI2 SMART Evaluation Board Ignore any warning messages produced during installation e The host computer should report that a Philips PDIUSBDI2 SMART Evaluation Board is now installed e Execute the software DE2 70 NIOS DEVICE LED SW ISP1362DcUsb exe on the host computer Then experiment with the software by clicking on the ADD and Clear buttons Figure 6 8 illustrates the setup for this demonstration 75 aN OT DE2 70 User Manual Memo 111 1213 33 33 33351335 D22222222222222222222 222222222222222222322 Ree RRR RRR ee USB Driver Figure 6 8 The setup for the USB device demonstration 6 6 A Karaoke Machine This demonstration uses the microphone in line in and line out ports on the DE2 70 board to create a Karaoke Machine application The Wolfson WM8731 audio CODEC is configured in the master mode where the audio CODEC generates AD DA serial bit clock BCK and the left right channel clock LRCK automatically As indicated in Figure 6 9 the 126 interface is used to configure the Audio CODEC The sample rate and gain of the CODEC are set in this manner an
61. or this demonstration 68 aN OT DE2 70 User Manual Line Out Line In CVBS S Video YPbPr Output VGA Out Audio Output Figure 6 2 The setup for the TV box demonstration 6 3 TV Box Picture in Picture PIP Demonstration The DE2 70 board has two TV decoders and RCA jacks that allow users to process two video sources simultaneously using the 2C70 FPGA This demonstration will multiplex two different video source signals from the TV decoders and display both video signals on the LCD CRT monitor using picture in picture mode PIP mode One picture is displayed on the full screen and the other picture is displayed in a small sub window Also users can select which video is displayed in main sub window via a toggle switch Figure 6 3 shows the basic block diagram of this demonstration There are three major blocks in the circuit called Composite_to_VGA PIP_Position_Controller and VGA_Multiplexer The Composite_to_VGA block consists all of the function blocks in the TV box demonstration project 69 DE2 70 User Manual described in the section 6 2 The Composite_to_VGA block takes the video signals from the TV decoders as input and generate VGA interfaced signals as output The circuit in the FPGA is equipped with two Composite_to_VGA blocks converting the video signals from the TV decoder 1 and TV decoder 2 respectively To display two video signals in PIP mode on the LCD CRT monitor the output VGA da
62. ound from the headset or speaker To stop the audio playing simply click Stop Play 21 DE2 70 User Manual LED 7 SEG LCD Button Memory USB PS2 SD CARD Audio Audio Play gt Product Name DE 70 http www altera com Sample Rate 441 7 Open Wave Start Play ter asic aye Memory WWW LET BAIC COMI SDRAM 2 2 Download Code Disconnect Exit Connected SD CARD read success Figure 3 11 Playing audio from a selected wave file To record sound using a microphone please follow the steps below 1 Plug a microphone to the MIC port on the board 2 Select the Record MIC item in the com box and select desired sampling rate as shown in Figure 3 12 3 Click Start Record to start the record process The program will configure the audio chip for MIC recording retrieve audio signal from the MIC port and then save the audio signal into SDRAM UI 4 To stop recording click Stop Record Finally audio signal saved in SDRAM UI will be uploaded to the host computer and displayed on the waveform window Click Save Wave to save the waveform into a WAV file 22 DE2 70 User Manual LED 7 SEG LOD Button Memory USB PS2 SD CARD Audio Audio Mic Record bd Product Mame DE 70 http www altera com Sample Rate 44 1K Gias c Target Memory _ wWWW LeFBSIC COM About SDRAM U2 Download Code Disconnect Exit Connected Auiod record successf
63. pe A of the DE2 70 board e Connect the VGA output of the DE2 70 board to a VGA monitor both LCD and CRT type of monitors should work Load the bit stream into FPGA Run the Nios II and choose DE2_70_NIOS_HOST_MOUSE_VGA as the workspace Click on the Compile and Run button e You should now be able to observe a blue background with an Altera logo on the VGA display e Move the USB mouse and observe the corresponding movements of the cursor on the screen Left click mouse to draw white dots lines and right click the mouse to draw blue dots lines on the screen Figure 6 6 illustrates the setup for this demonstration 73 DE2 70 User Manual ATER DE2 Board E m USB Driver Figure 6 6 The setup for the USB paintbrush demonstration 6 5 USB Device Most USB applications and products operate as USB devices rather than USB hosts In this demonstration we show how the DE2 70 board can operate as a USB device that can be connected to a host computer As indicated in the block diagram in Figure 6 7 the Nios II processor is used to communicate with the host computer via the host port on the DE2 70 board s Philips ISP1362 device After connecting the DE2 70 board to a USB port on the host computer a software program has to be executed on the Nios II processor to initialize the Philips ISP1362 chip Once the software program is successfully executed the host computer will identify the new dev
64. perform the following steps 1 Connect the provided USB cable from the host computer to the USB Blaster connector on the DE2 70 board For communication between the host and the DE2 70 board it is necessary to install the Altera USB Blaster driver software If this driver is not already installed on the host computer it can be installed as explained in the tutorial Getting Started with Altera s DE2 70 Board This tutorial is available in the directory DE2_70_tutorials on the DE2 70 System CD ROM Connect the 12V adapter to the DE2 70 board Connect a VGA monitor to the VGA port on the DE2 70 board Connect your headset to the Line out audio port on the DE2 70 board Turn the RUN PROG switch on the left edge of the DE2 70 board to RUN position the PROG position is used only for the AS Mode programming 6 Turn the power on by pressing the ON OFF switch on the DE2 70 board b oS DE2 70 User Manual At this point you should observe the following All user LEDs are flashing All 7 segment displays are cycling through the numbers 0 to F The LCD display shows Welcome to the Altera DE2 70 The VGA monitor displays the image shown in Figure 2 3 Set the toggle switch SW17 to the DOWN position you should hear a 1 kHz sound Set the toggle switch SW17 to the UP position and connect the output of an audio player to the Line in connector on the DE2 70 board on your headset you should hear the music played from the audio player MP3 PC iPod or
65. racters to represent hexadecimal values For example a file containing the line 0123456789ABCDEF defines four 8 bit values 01 23 45 67 89 AB CD EF These values will be loaded consecutively 17 NDE o DE2 70 User Manual JionVv4 into the memory The Sequential Read function is used to read the contents of the SDRAM UI and place them into a file as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be copied into the file in the Length box If the entire contents of the SDRAM UI are to be copied which involves all 32 Mbytes then place a checkmark in the Entire Memory box 3 Press Load Memory Content to a File button 4 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner Users can use the similar way to access the SSRAM and Flash Please note that users need to erase the flash before writing data to it 3 5 USB Monitoring The Control Panel provides users a USB monitoring tool which monitors the real time status of a USB mouse connected to the DE2 70 board The movement of the mouse and the status of the three buttons will be shown 11 the graphical and text interface The mouse movement 15 translated as a position x y with range from 0 0 1023 767 This function can be used to verify the functionality of the USB Host Follow the steps below to exercise the USB Mouse Monitorin
66. real time Press Stop to end the monitoring process 15 DE2 70 User Manual LED 7 SEG LCD Button Memory USB PS2 SD CARD Audio Buttoni Switch Buttan m m m Switch mu cop hitp www altera com ter asic Target Memory WwWW LEFBSIE COM About SDRAM U2 Download Code Disconnect Exit Connected Figure 3 0 Monitoring switches and buttons The ability to check the status of button and switch is not needed in typical design activities However it provides users a simple mechanism for verifying if the buttons and switches are functioning correctly Thus it can be used for troubleshooting purposes 34 SDRAM SSRAM Flash Controller and Programmer The Control Panel can be used to write read data to from the SDRAM SSRAM and FLASH chips on the DE2 70 board We will describe how the SDRAM U1 may be accessed the same approach is used to access the SDRAM U2 SRAM and FLASH Click on the Memory tab and select SDRAM UI to reach the window in Figure 3 7 Please note the target memory chosen for storing elf file 1s read only Also please erase the flash before writing data to it 16 DE2 70 User Manual LED 7 SEG LCD Button Memory USB PS2 SD CARD Audio SDRAM U1 1000000h WORDS gt Fandom Access Address wDATA DECA rDATA Doon Write Read Sequential Write Address Length 000000 File Length ce Write a File t
67. s As indicated in the schematic in Figure 5 6 the seven segments are connected to pins on the Cyclone II FPGA Applying a low logic level to a segment causes it to light up and applying a high logic level turns it off Each segment in a display is identified by an index from 0 to 6 with the positions given in Figure 5 7 In addition the decimal point is identified as DP Table 5 4 shows the assignments of FPGA pins to the 7 segment displays HEXO 6 RN17 1K HEXO DO A0 Q HEXO Di ALL 89 HEX0 D2 a Wr a C0 8 HEXO D3 4 ww EE RN18 1K D4 Q EO HEXO D5 HEXO D6 Dod 6 7Segment Display HEXO DP A ww Figure 5 6 Schematic diagram of the 7 segment displays Figure 5 7 Position and index of each segment in a 7 segment display HEXO D 0 PIN AE8 Seven Segment Digit O O HEXO D 1 PIN AF9 Seven Segment Digit O 1 HEXO D 2 PIN AH9 Seven Segment Digit O 2 36 DE2 70 User Manual HEXO D S PIN AD10 Seven Segment Digit 3 37 NBTE m DE2 70 User Manual HEX5 D 0 PIN M3 Seven Segment Digit 5 0 Table 5 4 Pin assignments for the 7 segment displays 5 4 Clock Circuitry The DE2 70 board includes two oscillators that produce 28 86 MHz and 50 MHz clock signals Both two clock signals are connected to the FPGA that are used for clocking the user logic Also the 28 86 MHz oscillator is used to drive the two TV decoders The board also includes an SMA conn
68. sssssecececosssssseee 66 6 1 DE2 70 Factory 66 6 2 Ty Ox TC 1 E 67 6 3 TV Box Picture in Picture PIP Demonstration eee enne 69 56 4 a a E eee ee ene eer 72 6 5 CSB Gy CG au 74 Pa NAIR oc UE 76 6 7 IRC CCI E EU UE 78 6 8 a VTS i MITT 60 6 9 5 26 83 6 10 Audio Recording and PlA ba SN ae anenai 87 90 7 1 90 7 2 90 DE2 70 User Manual Chapter 1 DE2 70 Package The DE2 70 package contains all components needed to use the DE2 70 board in conjunction with a computer that runs the Microsoft Windows software 1 1 Package Contents Figure 1 1 shows a photograph of the DE2 70 package Figure 1 1 The DE2 70 package contents 1 DE2 70 User Manual The DE2 70 package includes 1 2 The DE2 70 board USB Cable for FPG
69. t DRAMI _UDOMI 39 PIS gt DRAM1 WE n 4e gt DRAMI CAS n DRAMI RAS n 4e _ gt DRAMI CS n 4o _ gt DRAMI BAO gt DRAMI 2 SDRAMO on veces SDRAM1 R1 4 7K DRAMO WE n R7 47K DRAM1 WE n R2 4 7K DRAMO CAS n R8 4 7K DRAM1 CAS n R3 4 7K DRAMO RAS n R9 47K DRAM1 RAS n R4 4 7K DRAMO CS n R1 4 7K DRAM1 CS n R 4 7K DRAMO CKE R1 4 7K DRAM1 CKE Figure 5 22 SDRAM schematic 58 FE LES OLA P LS DRAM D16 DRAM D17 DRAM D18 DRAM D19 DRAM D20 DRAM D 1 DRAM D22 DRAM D23 DRAM D24 DRAM D25 DRAM_D26 DRAM D27 DRAM_D28 DRAM D29 DRAM D30 DRAM D31 a SRAM DQJ0 31 E SRAM DPAJO 3 m SRAM 0 18 SRAM BE n 0 3 SRAM addro SRAM addri 0 SRAM addr2 a SRAM _ addr3 SRAM _addr4 A3 SRAM addr5 A4 SRAM_addr6 A4 AS SRAM addr7 An A6 SRAM addr8 ac SRAM addr9 47 8 SRAM addr10 Ag A9 SRAM addri1 A10 SRAM addr12 o A11 SRAM addii3 g1 A12 SRAM addri4 go 13 SRAM addri5 99 14 SRAM addri6 100 19 SRAM addri7 4 ae SRAM addr18 TR AH 2 NC A19 8 NC A20 SRAM MODE SRAM ZZ 4 MODE SRAM outen n ZZ SRAM clock CLK GW n BWE n ADV n ADSC n ADSP n CE1 n CE2 CE3 n SRAM globalw n SRAM writeen n SRAM advance n SRAM adsoonttroler SRAM adsprocessor SRAM chipen1 n SRAM chipen2 SRAM chipen3 n SRAM byteen nO SRAM byteen ni BWA n SRAM byteen n2 BWB n BWC n SRAM byteen n3 BWD n rs O KO KO CO XO CO CO OO CO oo Do Oo OO COO
70. t stream is downloaded into the FPGA the register values of the TV Decoder chip are used to configure the TV decoder via the 26 AV Config block which uses the I2C protocol to communicate with the TV Decoder chip Following the power on sequence the TV Decoder chip will be unstable for a time period the Lock Detector 1s responsible for detecting this instability The ITU R 656 Decoder block extracts YCrCb 4 2 2 YUV 4 2 2 video signals from the ITU R 656 data stream sent from the TV Decoder It also generates a data valid control signal indicating the valid period of data output Because the video signal from the TV Decoder 15 interlaced we need to perform de interlacing on the data source We used the SDRAM Frame Buffer and a field selection multiplexer MU X which is controled by the VGA controller to perform the de interlacing operation Internally the VGA Controller generates data request and odd even selected signals to the SDRAM Frame Buffer and filed selection multiplexerr MU X The YUV422 to YUV444 block converts the selected YCrCb 4 2 2 YUV 4 2 2 video data to the YCrCb 4 4 4 YUV 4 4 4 video data format Finally the YCrCb RGB block converts the YCrCb data into RGB output The VGA Controller block generates standard VGA sync signals HS and VGA_VS to enable the display on a VGA 67 DE2 70 User Manual monitor spram TD_DATA Frame ecoder Data Valid Puffer Request Initiatio
71. ta rate of the Composite_to_VGA block for the sub window must be two times as fast as the rate of the Composite_to_VGA block for the main window In addition the output timing of the VGA interface signal from the Composite_to_VGA block 1s controlled by the pip_position_controller block that determines the stating poison of the sub window Finally both of the two VGA interfaced signals will be multiplexed and sent to the LCD CRT monitor via the VGA_multiplexer block Video in 1 a D TD data VGA data Composite_to TV decoder we aan PiP position Sub window TD clock controller Sub window Control signal TD clock andae VGA DAC PLL VGA data Sub Video in 2 TD clock or Video in 1 eee VGA TV decoder j Composite_to_ data Main VGA multiplexer Main window TD data VGA Main window Figure 6 3 Block diagram of the TV PIP demonstration Demonstration Setup File Locations and Instructions e Project directory DE2 70 TV PIP e Bit stream used DE2 70 TV PIP sof or DE2 70 TV PIP pof e Connect composite video output yellow plug of DVD player 1 and DVD player2 to the Video in 1 and Video in 2 RCA jack J8 and J9 of the DE2 70 board respectively Both DVD players must be configured to provide o 60 Hz refresh rate 4 3 aspect ratio o Non progressive video e Connect the VGA output of the DE2 70 board to a VGA monit
72. ter asic Target Memory www Lerasic com About SDRAM L2 Download Code Connected Set Led Success Disconnect Exit Figure 3 4 Controlling 7 SEG display 14 DE2 70 User Manual Choosing the LCD tab leads to the window in Figure 3 5 Text can be written to the LCD display by typing it in the LCD box and pressing the Set button m Panel Y1 0 0 rECD ALTERA TERASIC Praduct Mame DE 70 http www altera com ter asic Target Memory www Derasic com SDRAM L2 Downoad Code Disconnect Exit Connected Set LCD Success Figure 3 5 Controlling LEDs and the LCD display The ability to set arbitrary values into simple display devices is not needed in typical design activities However it gives the user a simple mechanism for verifying that these devices are functioning correctly in case a malfunction is suspected Thus it can be used for troubleshooting purposes 3 3 Switches and Buttons Choosing the Button tab leads to the window in Figure 3 6 The function is designed to monitor the status of switches and buttons in real time and show the status in a graphical user interface It can be used to verify the functionality of the switches and buttons Press the Start button to start button switch status monitoring process and button caption is changed from Start to Stop In the monitoring process the status of buttons and switches on the board is shown in the GUI window and updated in
73. ter port on the DE2 70 board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch on the left side of the board to the PROG position The EPCS16 chip can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the pof filename extension Once the programming operation is finished set the RUN PROG switch back to the RUN 31 VES DE2 70 User Manual ANU c n position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCS16 device to be loaded into the FPGA chip USB Blaster Circuit PROG RUN Quartus Il AS Mode Programmer Config m AS Mode PROG Auto onfig Por Power on Contig EPCS16 Serial Configuration Device Figure 5 2 The AS configuration scheme In addition to its use for JTAG and AS programming the USB Blaster port on the DE2 70 board can also be used to control some of the board s features remotely from a host computer Details that describe this method of using the USB Blaster port are given in Chapter 3 5 2 Using the LEDs and Switches The DE2 70 board provides four pushbutton switches Each of these switches is debounced using a Schmitt Trigger circuit as indicated in Figure 5 3 The four outputs called KEYO KEYI KEY2 and KEY3 of the Schmitt Trigger devices are connected directly to the Cyclone II FPGA Each switch provides
74. tton and toggle switches is given in Figure 5 4 A schematic diagram that shows the LED circuitry appears in Figure 5 5 A list of the pin names on the Cyclone IJ FPGA that are connected to the toggle switches 15 given in Table 5 1 Similarly the pins used to connect to the pushbutton switches and LEDs are displayed in Tables 5 2 and 5 3 respectively 2 SW6 3 GND 5 GND 2 SW7 3 GND 5 GND SLIDE SW SLIDE SW 2 SW12 2 120 SW13 3 GND 3 GND 5 GND 5 GND SLIDE SW SLIDE SW 3 SW O 17 5 GND 5 GND GND ND SLIDE SW D A D Figure 5 4 Schematic diagram of the pushbutton and toggle switches 33 DE2 70 User Manual LEDR10 7A LEDR 330 8 LEDR11 LEDR 5 LEDR12 p LEDR LEDR13 7A LEDR 330 8 LEDR15 77 LEDR ZA LEDR LEDR16 LEDR17 ZA LEDR Figure 5 5 Schematic diagram of the LEDs 34 DE2 70 User Manual SW 16 PIN L7 Toggle Switch 16 SW 17 PIN L8 Toggle Switch 17 Table 5 1 Pin assignments for the toggle switches Table 5 2 Pin assignments for the pushbutton switches 35 mu DE2 70 User Manual ule A LEDG 7 PIN AA24 LED Green 7 LEDG 8 PIN AC14 LED Green 8 Table 5 3 Pin assignments for the LEDs 5 3 Using the 7 segment Displays The DE2 70 Board has eight 7 segment displays These displays are arranged into two pairs and a group of four with the intent of displaying numbers of various size
75. ully Figure 3 12 Audio Recording and Saving as a WAV file To record audio sound from LINE IN port please connect an audio source to the LINE IN port on the board The operation is as same as recording audio from MIC 3 9 Overall Structure of the DE2 70 Control Panel The DE2 70 Control Panel is based on a NIOS II system running in the Cyclone II FPGA with the SDRAM U2 or SSRAM The software part is implemented in C code the hardware part is implemented in Verilog code with SOPC builder which makes it possible for a knowledgeable user to change the functionality of the Control Panel The code is located inside the DE2 70 demonstrations directory on the DE2 System CD ROM To run the Control Panel users must first configure it as explained in Section 3 1 Figure 3 13 depicts the structure of the Control Panel Each input output device is controlled by the NIOS II Processor instantiated in the FPGA chip The communication with the PC is done via the USB Blaster link The NIOS II interprets the commands sent from the PC and performs the corresponding actions 23 DE2 70 User Manual SEG7 Controller cS T SEG Display SDRAM Controller UE SDRAM U1 Nios II LCD Controller R LCD USB Controller a USB Mouse PS2 Controller oT PS2 Keyboard PIO Controller Cs LED Button FPGA SOPC JTAG Blaster Hardware Pee a Switch Seg7 SD Card Avalon MM Flash C A Tristate Bridge gt Controller K Flash N
76. ure 5 13 illustrates the basic timing requirements for each row horizontal that is displayed on a VGA monitor An active low pulse of specific duration time a in the figure is applied to the horizontal synchronization Async input of the monitor which signifies the end of one row of data and the start of the next The data RGB inputs on the monitor must be off driven to 0 V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there 15 a time period called the front porch d where the RGB signals must again be off before the next sync pulse can occur The timing of the vertical synchronization vsync is the same as shown in Figure 5 13 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Table 5 9 and 5 10 show for different resolutions the durations of time periods a b c and d for both horizontal and vertical timing Detailed information for using the ADV7123 video DAC is available in its datasheet which can be 45 mo DE2 70 User Manual JN OS RYA found on the manufacturer s web site or in the Datasheet VGA DAC folder on the DE2 70 System CD ROM The pin assignments between the Cyclone II FPGA and the ADV7123 are listed in Table 5 11 An example

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