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1. SMARTMEDIA CARD PowerPC 405 un PROCESSOR BLOCK 1 J iNENIBAND 96 1 8 88 BB E 88888855588 PROCESSOR BLOCK2 4 8 E 33343333343 us sma ATmegai28L 4 USER CLOCK 55 PPC FPGA STATUS LED S Us SMA DEBUG RS232 CONNECTORS L sma i 2 gt 85232 2 CY62256 xt ADDRESS ur para VOLTAGE INDICATORS 1 POWER HEADER CONTROL 252 4083 P12 SMARTMEDIA CONFIGURATION prp k uie XILINX VIRTEXII 4995 5 7 j ADDRESS FLASH E para amb x16 DDR VIT p xoavPrartoo 125 CONTROL 28784083 125 SWITCHING CONFIG DDR gt 014 E REGULATOR JUMPERS a FF1704 U24 CLOCK SOURCE 5 ECLK1 ADDRESS ADDRESS DDR SDRAM DDR SWITCHING JUMPER GRID 2 6 DATA DATA amp MbXi6 MODULE Jes RoBOcLock 9 4 lt CONTROL CONTROL DDR u28 PLL1 hi gt hd gt u20 8 ps Dessen 5 DDRESS ADDRESS DDR SDRAM DDR PLL4
2. M 167 25 read 168 2 5 1 Description 168 2 5 2 Arguments 168 2 5 3 Values eet 168 2 5 4 Notes 168 169 2 6 1 Description 169 2 6 2 X 169 2 6 3 seht inet te 169 2 6 4 Notes 2 7 buffer allocates 170 271 170 2 7 2 Arguments 170 2 7 3 170 274 170 171 171 2 8 1 Description 2 8 2 Arguments 171 2 8 3 SY AICS a 171 2 8 4 NOLES E 171 2 9 write dword 172 2 9 1 172 2 9 2 E E 172 2 9 3 Return Values 2 9 4 Notes 172 172 2 10 read dword 173 2 10 1 pcs RR 173 2 10 2 AT OUMENLS 173 2 10 3 Return Values 173 2 10 4 bor
3. 45V 12V 45V PCI 3H 12v 12V HA GND TMS HA Be TDO TDI 45V B6 6 POL NTAN PCI INTAn Be NIE INTC Hag X PRSNT1 NID T Bio RSVD 1 PRSNT2 VIO Ati PRSNT2 rsvp 43 3V Keyway TPS XBH 33VAUX TATE PCL PCI 816 GND RST A16 voz C PCLOLK Bt7 CLK 7 PCI GNTn PCI REQn Brg GNT ATS PoLGNTa TPS PCI REOn Big REQ 9 0 8 PMEn PCI AD31 820 PME 20 PCI AD28 B21 031 030 2 VS S AD29 33 AS PCI AD28 PCI AD27 GND AD28 A23 PCI_AD26 PCI_AD25 B24 027 AD26 V8 6 825 4025 GND 25 AD24 PCI B26 223V AD24 226 PCI IDSEL IDSEL Haso PCLIDSEL Bog AD23 Tagg PCI AD21 29 GND 529 PCI 020 19 B30 4021 020 5 019 END PCI AD18 PCI_AD17 832 133 AD18 PCI_ADI6 CBEn2 833 ADIT 018 Wea e FRAME 832 PCI FRAMEN gt gt POLIRBYR Waa Bae ROY aD a36 PCI TRDYn PCI aay 43 8 TRDY C POI TRDYn PCLDEVSELn
4. Met ee e MCN 121 7 1 Gigabit Ethernet Fiber 7 1 1 Stratos Lightwave Quad Fiber Transceiver 73 ee ettet eee tatnen hee ehe reete ella eben 122 7 1 2 FPGA 123 7 2 Infiniband HSSCD2 7 2 1 FPGA to InfiniBand HSSDC2 124 7 3 SOG ATA 125 7 3 1 FPGA to Serial ATA Connector 125 7 4 SMA Connectors 7 4 1 FPGA to SMA Connector 8 CPU DEBUG AND CPU TRACE 8 1 E 127 8 1 1 CPU Debug Connector 128 8 1 2 Debus P 128 8 1 3 Traces 129 8 1 4 CPU Trace Connector eene tente 129 8 1 5 Combined CPU Trace Debug Connection to FPGA 130 9 GPIO EEBDY S rite roo eren eet 130 9 1 Status Indicators 130 92 AE PGAGPIO TED iis Re ede e EE ete e e eet ee Ree o e 131 10 PCI INTERFACE 10 1 to th 133 10 1 1 PCI VECO 133 10 1 2 PCI Edge Connector 133 10 1 3 Connection between the PCI connector and the 134 10 2
5. SRAM3_A6 U15 AJ3 SRAM3_A7 U15 AB4 SRAM3_A8 U15 AC4 SRAM3_A9 U15 AD4 SRAM3_A10 U15 AJ2 SRAM3 A11 U15 AB3 SRAM3 A12 U15 AC3 SRAM3 A13 U15 AD3 SRAM3 A14 U15 AF3 SRAM3 A15 U15 AG3 SRAM3 A16 U15 AH3 SRAM3 A17 U15 AH2 SRAM3_A18 U15 AG2 SRAM3_A19 U15 AF2 SRAM3_A20 U15 AE2 SRAM3_ADSCn U15 AG4 SRAM3_ADSPn U15 AF4 SRAM3_ADVn U15 AE4 SRAM3_BWAn U15 AE5 SRAM3_BWBn U15 AH12 SRAM3_BWCn U15 AF5 SRAM3_BWDn ET6000K10S User Guide U15 AG5 www emulation com GG Gale ea BOARD HARDWARE Signal Name FPGA Pin SRAM3 BWEn U15 AH5 SRAM3 CEN U15 AB6 SRAM3 DQAO U15 AH6 SRAM3_DQA1 015 6 SRAM3_DQA2 15 7 SRAM3_DQA3 15 AC7 SRAM3_DQA4 SRAM3_DQA5 15 AE7 SRAM3_DQA6 SRAM3 DQAT U U U15 AD7 U U15 AF7 U15 AG7 SRAM3 DQBO U15 AJ7 SRAM3 SRAM3_DQB2 U15 AD8 U15 AE8 c SRAM3_DQB3 U15 AF8 SRAM3_DQB4 SRAM3_DQB5 U15 AG8 U15 AH8 SRAM3_DQB6 U15 AJ8 SRAM3_DQB7 SRAM3 DQCO U15 AB9 U15 AC9 G SRAM3_DQC1 U15 AD9
6. L 3 4 Gig E Infiniband User CLK 212 EG212CA DDR PLO SMA 25 25V PECL mS FLASH DCLK3A FLASH whera x16 FPGA GCLKOUT RoboClock It ose 2 CYB944V rere PLL2BN DDR CLKOp Ost gt DDR SDRAM 64Mx16 liis BANK 1 30V BANK O 30V DDR gt DDR SDRAM DDR 64M x 16 FPGA _ 008 Pup XILINX BANK6 25V pe CLOCK CPLD gt BUFFER CLK2p piieveas7 DDR SDRAM DDR Cum GAM x 16 BANK 4 3 0V BANKS 3 0V AL DDR_CLK3p gt DDR SDRAM DDR osc PLLIB p E x M16 PLLIBN peep RoboClock I feru CYBO44V A wove DDR PLLFBpin EG SSRAM uP 2M x38 1281 j al DCLKO ECC SSRAM 2M System 2 FPGA i j SRAM 10092 gt Test ECLKS Header ECLK4 SSRAM 2M x36 Figure 33 Clocking Block Diagram The clocking structures for the ET6000K108S include the following features Two user selectable socketed oscillators X4 X5 One 48 MHz oscillator Tw
7. Daughter Card ET6000K10S IO Connections Connections Test Signal Name Connector Test Signal Name FPGA Pin Header Header J1 154 P3N40 16 15 11 154 TST_HDRA118 U15 P38 1 155 P3N37 16 17 P11 155 TST_HDRA119 U15 P37 J1 156 P3N36 16 19 P11 156 TST HDRA120 U15 R34 1 157 P3N33 16 21 P11 157 TST_HDRA121 U15 R33 1 158 P3N32 J6 23 11 158 TST HDRA122 U15 R38 1 159 P3N31 J2 44 11 159 TST_HDRA123 U15 R37 J1 160 P3N30 J2 45 11 160 TST_HDRA124 U15 R32 J1 161 P3N25 J6 25 P11 161 TST 125 U15 R31 11 162 No Connect P11 162 GND J1 163 P3N24 J6 27 P11 163 TST_HDRA126 U15 T35 J1 164 P3N21 J6 29 P11 164 TST_HDRA127 U15 R35 1 165 P3N20 16 31 P11 165 TST_HDRA128 U15 T40 J1 166 P3N17 J6 33 11 166 TST_HDRA129 U15 T33 J1 167 P3N16 16 35 P11 167 TST_HDRA130 U15 T32 J1 168 P3N13 J6 37 P11 168 TST_HDRA131 015 035 J1 169 P3N12 16 39 P11 169 TST_HDRA132 U15 AK38 J1 170 P3N11 J2 47 11 170 TST_HDRA133 U15 AK37 1 171 P3N10 J2 48 P11 171 TST HDRA134 U15 W36 11 172 P3N5 J6 41 P11 172 TST_HDRA135 U15 W35 11 173 No Connect P11 173 GND J1 174 P3N4 16 43 P11 174 TST_HDRA136 U15 AK34 J1 175 P3N1 16 45 11 175 TST_HDRA137 U15 AK33 J1 176 16 47 P11 176 TST_HDRA138 U15 AA36 J1 177 P4N25 17 P11 177 TST_HDRA139 U15 AA31 J1 178 P4N24 17 3 11 178 TST_HDRA140 U15 AB31 J1 179 P4N23 J7 5 P11 179 TST HDRA141 U15 AA40
8. ET6000K10S User Guide www emulation com 96 BOARD HARDWARE Signal Name FPGA Pin FLASH1_ADDR17 U15 H10 FLASH1_ADDR18 U15 K11 FLASH1_ADDR19 U15 F12 FLASH1_ADDR20 015 612 FLASH1_ADDR21 U15J10 FLASH1 DATAO U15 E15 FLASH1 DATA1 U15 G13 FLASH1 DATA2 U15J16 FLASH1 DATA3 015 13 FLASH1_DATA4 U15 K13 FLASH1 DATAS U15 K16 FLASH1 DATAG 015146 FLASH1_DATA7 U15 F17 FLASH1 DATAS U15 F13 FLASH1_DATA9 U15 H13 FLASH1 DATA10 U15 F15 FLASH1_DATA11 015 15 FLASH1_DATA12 U15 D16 FLASH1_DATA13 U15 E17 FLASH1_DATA14 U15 M16 FLASH1_DATA15 U15 M13 FLASH1_CEn U15 F10 FLASH1 OEn U15 G16 FLASH1_WEn 015 017 FLASH1_WPn 15 12 e 6 2 Synchronous SRAM The Synchronous SRAM U8 U9 010 011 memory components on the ET6000K108 can accommodate up to 2 x 36 devices refer to Figure 47 ET6000K10S User Guide ww w emulation com 97 BOARD HARDWARE SRAM1 A0 327 52 DQa0 1 36 53 _ DQal SRAMI 2 35 81 end 56 SRAMI DQa2 _ SRAM1 94 B 57 SRAM1_DQa3 SRAM1_A4 33 Qa3 58 5 32 M Doat 59 SRAM1_DQa5 A6 100 5 0255 62 ___ 1_ SRAM1_A7 99 6 63 SRAMI 7 8 82 a poe 68 SRAM1_DQb0 SRAM1_AQ 81
9. Figure 63 M66EN and PCIXCAP Jumper ET6000K10S User Guide ww w emulation com 138 BOARD HARDWARE If the card s maximum frequency is 133 MHz it leaves this pin unconnected except for a decoupling capacitor If the card s maximum frequency is 66 MHz it connects PCIXCAP to ground through a resistor and decoupling capacitor Conventional cards connect this pin to ground An add in card indicates its capability with one of the combinations of the M66EN and PCIXCAP pins listed in Table 36 Table 36 M66EN and Encoding PCIXCAP Conventional PCI X Device Device Frequency Frequency Capability Capabilit Ground Ground 33 MHz connected Pull down 33 MHz PCI X 66 MHz connected connected connected connected The ET6000K108 is factory configured to operate in PCI mode 33MHz JP2 5 6 and JP2 9 10 jumpers installed 10 2 3 Further Information on PCI PCI X Signals The following signals have pull up resistors 1M on the ET6000K108S This is technically a violation of the PCI specification but there are systems that have these signals floating PCI LOCKn PCI 4 PCI ACK64n Note The function of LOCKn pin was deleted in version 2 3 of the PCI Specification The PCI JTAG signals TDI TRSTn are not used TDI are connected together per the PCI Specification to maintain JTAG chain integrity on the motherboard The signals TMS
10. 144 TST_HDRAGS 83 183 TST HDRA145 5 HDRA66 84 4 GND TST HDRA67 85 7 185 TST 46 TST_HDRAGS 86 186 TST 147 HDRA6S 87 187 HDHA148 GND 88 188 TST HDRAT49 HDRA7O 89 189 TST_HDRAT50 TST_HDRA7T 90 190 5 TST_HDRA72 91 791 TST HDRA152 TST_HDRA73 9217 192 5 5 15 93 193 _ 54 5 ADRA __ 94 194 __157_ 55 _ ST_HDRA7S 9517 195 96 196 ST_HDRATSS ST 77 9717 197 ST_HDRATST ST 78 9817 198 TST 158 GND 99 199 TST HDRA159 12V 100 7 200 TST HDRAT6O ws 203 _____ 201 204 202 85 _ 205 4 P con200 Figure 66 Test Header ET6000K10S User Guide ww w emulation com 143 BOARD HARDWARE 12 1 1 Test Header Connector Micropax connector 200 pin is used as a standard interface to all Emulation Technology logic emulation boards This connector has a specified current rating of 0 5 amps per contact See datasheet for more information P N 91294 003 12 1 2 Test Header Pin Numbering Figure 67 indicates the pin numbering scheme used on the test headers pt Mounting Holes Figure 67 Test Header Pin Numbering ET6000K10S User Guide www emulation com 144 BOARD HARDWARE 12 2 ET3000K 10SD Daughter Em
11. Bag DEVSEL GND 1 PCI STOPn 3 3V Bae STOP Y33 C STOPn B40 LOCK 3 3 Tago R123 5 1K PCI PERRn EE 40 SMBCLK HM iol PCI_SERRn B42 2 3 E PCI SERRn eu SERR GND M3 f POL PAR PCI B44 123V PAR PCI 5 POLPAR PCI 14 B45 015 A45 2 46 014 3 3 Tage PCI AD13 PCI AD12 T POL ADI PCI_AD10 1012 ADI Aas PCI_M66EN AD10 GND PCI 9 B51 A51 PCI EA GND Hu PCI PCI_AD 858 008 CIBEO A53 Ve Vs B54 007 PCI ADS PCI ADS 855 19 3V 006 A55 PCI_AD4 PCI_AD3 856 005 004 556 857 2003 GND PCI_AD2 9 57 GND 002 PCI B58 A58 Vio 3 59 001 000 59 Vio 3 PCI ACK64n PCI ACKGAn 550 160 PCI REQ64n t 862 5V 35V A62 1 45V 25V 64 bit Keyway RSVD PCI CBEn7 PCI 6 GND _ UBER PCLCBEnS PCI OBEN PARGA PCI CI64M EDGE PCI AD 0 63 Note The B side ofthe connector must be on the components side of the PCB Figure 62 PCI Edge Connector 10 1 3 Connection
12. FLASHO WE ne 9 e FPGA DONE 12 27 WPi GND oe 14 GND 4 28F640B3 TSOP48 Figure 46 FLASH Connection The Intel Advanced Boot Block Flash Memory C3 device supports read array mode operations at various IO voltages 1 8V and erase and program operations at or 12V VPP On the ET6000K10SC VPP is 3 3 The ET6000K10SC interfaces to the FLASH at 2 5V levels This family of devices is capable of fast programming at 12V not utilized on the 6000 105 The device features the following e Enhanced blocking for easy segmentation of code and data or additional design flexibility e Program Suspend to Read command VCCQ input of 1 65V 2 5V or 2 7V 3 6V on all I Os e Maximum program and erase time specification for improved data storage For more information on this part please refer to the Intel P N TE28F640C3TC80 datasheet 6 1 1 FLASH Connection to the FPGA The FLASH memory components are connected to the FPGA on Bank 0 and Bank 1 as listed in Table 21 The VCCO of the IO banks are connected to 2 5V Table 21 Connection between FPGA and FLASH Signal Name FPGA Pin FLASHO ADDRO U15 G26 ET6000K10S User Guide ww w emulation com 94 BOARD HARDWARE Signal Name FPGA Pin FLASHO_ADDR1 U15 E27 FLASHO_ADDR2 U15 K27 FLASHO_ADDR3 U15 E30 FLASHO_ADDR4 U15 F30 FLASHO_ADDRS5 U15 H26 FLASHO_ADDR6 015127 FLASHO
13. MSEL 0 3 LED Indicators Signals CPLD_LEDn 0 3 GPIO to FPGA Signals 0 7 3 2 1 CPLD Programming Connector A programming cable for the XC95288XV is shipped with the ET6000K10S The CPLD programming header P7 as shown in Figure 30 is used to download the files to the CPLD using the XILINX JTAG cable 43 3V Q R110 1K JTAG CPLD TCK JTAG CPLD TDO JTAG CPLD TMS co gt JTAG_CPLD_TDI R114 1K Figure 30 CPLD Programming Header 3 2 2 Design Notes the CPLD Oscillator X1 is a 48 MHz oscillator used to clock the CPLD This part is soldered down to the PWB and is not intended to be user configurable The 48 MHz is divided down to 8 MHz in the CPLD to provide the clock for the micro controller U4 The clock signal is labeled MPU_CLK on the schematic The 48 MHz is used directly for the state machines in the CPLD for controlling the interface to the SmartMedia card The frequency of 48 MHz is interesting because it is the closest frequency to 50 MHz that can be divided by an integer to get 8 MHz The ET6000K10S User Guide www emulation com 72 BOARD HARDWARE frequency 50 MHz is the fastest that the Virtex II Pro parts can be configured with SelectMap without wait states So FPGA configuration using SelectMap occurs at very nearly the fastest theoretical speed Serial and JTAG configuration of the Virtex II Pro FPGA
14. Memory Fill Memory Urite BAR Memory Display memory test on SSRAM 1 memory test on SSRAM 2 memory test on SSRAM 3 memory test on SSRAM 4 memory test on DDR full memory test Cincluding blockram gt memory test on FPGA block memory bar memory range test bar memory address data bitwise test Main Menu 9 gt Quit PCI BASE ADDRESS bbaie888 1 1 2 96000000 68800006 66000000 5 86000000 Please select option 6 The 000 105 features DDR SDRAM SRAM and Flash memory devices The ET6000K108S specific memory tests are designed to exercise and verify the functionality of those features Select one of the memoty devices to be tested Mrite Read Duord Same Address Memory Fill BAR Memory Urite BAR Memory Display memory test on SSRAM 1 memory test on SSRAM 2 memory test on SSRAM 3 memory test on SSRAM 4 memory test on DDR full memory test including blockram gt memory test FPGA block memory bar memory range test bar memory address data bitwise test Main Menu 9 gt Quit BASE ADDRESS bbaie O 1 2 00000000 5 Please select option word count 80x188 top if an error occurs or isplay any errors that occur or 7 The AETEST Test utility will now test the selected memory device using the memory controllers available in the PCI reference design
15. 69 5 1 SRAMI A10 44 0901 72 SRAMI 2 5 45 10 0962 73 SHAMI DQb3 5 A12 46 3 74 SRAM1_DQb4 5 A13 47 E 75 SRAM1_DQb5 5 48 3 B 78 5 1 0066 5 15 49 14 Qb6 79 SRAMI A16 50 2 5 DQcO SRAM1_A17 43 5 73 SRAM1_DQct 18 6 SRAM1 DQc2 A19 39 7 SRAM1_DQc3 SRAMI A20 38 9 g SRAMI DQc4 20 9 5 DQc5 SRAM1_ADVn 83 c5 12 SRAM1_DQc6 SRAMI 5 84 AS ied 13 SRAM1_DQc7 5 5 85 rd 18 SRAM1_Dado VEG MEN B 19 SRAMI 0091 SRAMi BWAn 93 hae 22 SRAM1_DQd2 SRAMI BWBn 94 wee 0005 23 SHAMI Dada BWCn 95 WEB 0003 24 0004 SRAM1_BWDn 96 094 725 0095 53 SBATH DOS 28 SRAM1_DQd6 SRAMi BWEn 87 0096 55 SRAM1_DQd7 SRAM1_GWn 88 AWE 0997 51 SRAMI LBon 31 one TRG 80_ SHAMI DQPb 89 SRAM1_DQPc 730 5 1 SRAM1_CEn 98 SRAM1_CE2 97 14 eee 37 __ 1_ 92 5 OEn 86 SRAM1_ZZ 64 EE 74 15 3 3V VDD Fa vss VDD vss VDD vss VDD VSS 4 42 5V vss VDDQ vss VDDQ vss VDDQ vss VDDQ
16. 173 2 11 2 11 1 Description 2 11 2 M 174 2 11 3 ReturnValues 174 2 11 4 Notes 175 2 12 1 Description 176 2 12 2 M 176 2 12 3 SAEI SEa 176 2 12 4 2 12 5 Derived Functions n no 178 List of Figures Figute T E T6000K10S LOGIC Bimulation Boat 7 Figure 2 Default Jumper Setup Figure 3 6000 105 Board Recognition Figure 4 ET6000K10S Not Found Figure 5 Main Menu Figure 6 PCI Menu Figure 7 Memory Menu Figure 8 Memory Write DWORD Figure 9 Memory Read DWORD Figure 10 Memory Write Read DWORD Figure 11 BAR Memory Fill Figure 12 Bar Memory Write Figure 13 Bar Memory Display Figure 14 Bar Memory Range Test Figure 15 Bar Memory Address Data Bitwise Test Figure 16 Flash Menu Figure 17 Daughter Board Menu Figure 18 New Project Screen Shot Figure 19 Input File Figure 20 New Project Dialog Box Figure 21 Project Navigator Figure 22 Main Menu Figure 23 Interactive Configuration Option Menu Figure 24 6000 105 Block Diagram Figure 25 Bankout Diagram Figure 26 MCU General Purpose IO Con
17. 9 a xc vp20 51204 Creete New Source Design Entry User Constraints implement Design Generate Programming File Figure 21 Project Navigator In the Process for Source window a process is signified by the icon In the Process for Source window the user must right click on the Generate Programming File process and select properties The default settings are correct The user should verify a couple important options right click and selecting properties options e Configuration Options Tab Configuration Pin Powerdown Pull Up ET6000K10S User Guide www emulation com 54 PROGRAMMING CONFIGURING THE HARDWARE Process Properties Default 4 Default 5 Default 6 Default NoWait Default Noait Readback Options Tab Security Enable Readback and Reconfiguration www emulation com 55 ET6000K10S User Guide PROGRAMMING CONFIGURING THE HARDWARE Process Properties x General Options Configuration Options Startup Options Readback Options Encryption Options Property Name Value Security Ena ble Readback and E gt Create ReadBack Data Files Allow Pins to Persist N A Create Logic Allocation File Create Mask File The user can now generate the bit file In the Process for Source window u
18. also used for direction select and output enable on U2 and U3 respectively 12 2 1 Daughter Card LED s The LED s act as visual indicators representing the presence of active power sources D1 LED indicating 3 3 V present e D2 LED indicating 5 0 V present D3 LED indicating 12 V present ET6000K10S User Guide www emulation com 147 BOARD HARDWARE Under normal operating conditions all LED s should be ON 12 2 2 Power Supply A linear power supply U4 is present to provide level shift translation functions when the board is populated with passive bus switches Resistors R10 and R11 can be used to select alternate voltage sources 5V or 3 3V respectively When used U4 must be removed in order to prevent contention The power supplies is rated as follows e 5 V power supply is rated for 1 A 3 3 V power supply is rated for 1 A 1 5 V power supply is rated for 1 A e 12 V power supply is rated for 0 5 A e 12V power supply is rated for 0 5 A NOTE Never populate R10 R11 simultaneously this will result in a shorting the 3 3V and 5V power supplies Header J8 allows external connection to the Power Sources refer to Table 38 for connection details Table 38 External Power Connections Function i Function GND GND 5V 1 5V GND GND 5V 12V GND GND 3 3V 12V GND GND 35 V 12V GND GND 1 5V 12V ET6000K10S User Guide www emulation com
19. 12 5 TST_HDRAT 13 7113 TST HDRAB1 TST 14 7 114 5 HDRA82 TST HDRA3 15 7 115 TST HDRA83 TST_HDRA4 16 116 5 HDRAB4 TST 5 117 TST 85 TST_HDRAG 18 118 GND _ 7 19 119 TST_HDRA86 5 ADRAS 201 120 TST_HDRAST TST HDRAS 21 121 GND 22 122 HDHA89 ST 23 gt 123 ST 9 TST ADRA __24 7124 __ 5 _ 5 2 25 1125 ST 92 ST HDHAT3 26 126 ST HDHA9S TST_HDRATS 27 127 ST_HDRAS 128 TST HDRA95 3 129 GND 7130 TST HDRA96 5 aol 31 131 TST_HDRAST a 32 7 132 HDHAO8 GND 33 7 133 HDHAOS 20 3417 a34 TST HDHA T 35 1835 ST HDRAZ2 36 136 TST HDHA102 TST HDRA23 37 137 5 103 ST HDRA24 38 138 TST HDRA104 TST 25 39 7 139 TST HDHA105 TST HDRA26 40 GND TST ADRA y 7141 5 106 ADRAS 42 m42 7 5 43 43 TST HDRATOS ______441 144 TST HDRATOS TST HDRA30 45 7 145 TST 110 46 7146 TST TST HDRA32 47 7147 TST HDRA112 TST HDRA33
20. 153 15 D20 JP5 32 TRG 154 15 D19 JP5 34 PPC_TRC_TS5 15 20 JP5 36 PPC_TRC_TS6 1519 JP5 38 U U U U U U 9 GPIO LED s 9 1 Status Indicators The 6000 105 uses 051 and 1052 to visually indicate the status of the board 051 is controller by the MCU U4 and the CPLD U5 controls DS2 ET6000K10S User Guide www emulation com 130 BOARD HARDWARE Table 32 lists the function of the GPIO LED s The is number from left to right LEDO to LED7 Table 32 GPIO LED s Signal Name Description LEDO0n Indicates SmartMedia configuration passed MCU_LED1n Indicates invalid SmartMedia card MCU_LED2n Indicates configuration error MCU_LED3n Indicates data transfer in progress from SmartMedia to the FPGA CPLD LEDOn Indicates FPGA is not configured CPLD LEDin Indicates board reset CPLD_LED2n Indicates RoboClock PLL 1 U25 is in lock CPLD_LED3n Indicates RoboClock PLL 2 026 is in lock 9 2 FPGA GPIO LED s The ET6000K10S provides 10 GPIO LED s directly connected to the FPGA IO pins Table 33 lists the FPGA on the ET6000K10S and is available to the user The signals are acttve LOW Table 33 FPGA GPIO LED s ET6000K10S User Guide www emulation com 131 BOARD HARDWARE FPGA U15 AT30 U15 AN30 U15 AP30 U15 AL30 U15 AM30 U15 AT31
21. SRAM3_DQC2 SRAM3_DQC3 U15 AF9 U15 AH9 SRAM3_DQC4 015 9 SRAM3_DQC5 15 AB10 SRAM3_DQC6 15 AC10 SRAM3_DQC7 SRAM3_DQD0 15 AE10 SRAM3_DQD1 U U U15 AD10 U U 15 AF10 SRAM3_DQD2 ET6000K10S User Guide U15 AG10 www emulation com BOARD HARDWARE Signal Name FPGA Pin SRAM3_DQD3 U15 AH10 SRAM3 DQD4 U15 AJ10 SRAM3_DQD5 U15 ACI1 SRAM3 DQD6 U15 AD11 SRAM3 DQD7 U15 AE11 SRAM3_DQPA 015 11 SRAM3_DQPB U15 AG11 SRAM3_DQPC U15 AH11 SRAM3_DQPD 015 11 SRAM3_GWn U15 A 5 SRAM3 LBOn U15 AD1 SRAM3 015 U15 AG6 U15 AW1 U15 AV1 U15 AU1 015 015 1 015 U15 AL3 U15 AM3 U15 AN3 U15 AR3 U15 AP2 U15 AR2 U15 AT2 U15 AU2 U15 AV2 U15 AW2 6000 105 User Guide www emulation com 109 BOARD HARDWARE Signal Name FPGA Pin SRAM4_A16 U15 AK3 c A17 U15 AN2 A18 U15 AM2 SRAMA A19 U15 AL2 SRAM4_A20 U15 AK2 SRAM4_ADSCn U15 AV3 SRAM4_ADSPn U15 AU3 SRAM4_ADVn U15 AT3 SRAM4_BWAn SRAM4_BWBn U15 AW3 U15 AK4 SRAM4_BWCn U15 AL4 SRAM4 BWDn SRAM4
22. VIRTEX II AAND ISE Up to four IBM PowerPC RISC processor blocks Based on Virtex IT FPGA technology Flexible logic resources up to 125 136 Logic Cells SRAM based in system configuration Active Interconnect technology SelectRAM memory hierarchy Up to 556 Dedicated 18 bit x 18 bit multiplier blocks High performance clock management circuitry SelectlO Ultra technology o Digitally Controlled Impedance DCI I O 1 2 PowerPC 405 Core Embedded 300 MHz Harvard architecture core Low power consumption 0 9 mW MHz Five stage data path pipeline Hardware multiply divide unit Thirty two 32 bit general purpose registers 16 KB two way set associative instruction cache 16 KB two way set associative data cache Memory Management Unit MMU 64 entry unified Translation Look aside Buffers TLB Variable page sizes 1 KB to 16 MB Dedicated on chip memory OCM interface Supports IBM CoreConnect bus architecture Debug and trace support Timer facilities 1 3 RocketlO 3 125 Gbps Transceivers Full duplex serial transceiver SERDES capable of baud rates from 622 Mb s to 3 125 Gb s please reference the Xilinx datasheet for speed grade limitations 80 Gb s duplex data rate 16 channels ET6000K10S User Guide www emulation com 17 INTRODUCTION VIRTEX II AAND ISE e Monolithic clock synthesis and clock recovery CDR Fibre Channel Gigabit Ethernet 10 Gb Atta
23. 4 4 Common Clock Source Selections The following configuration is the most common Configuration 1 CLOCKA gt PLL1A CLOCKB gt PLL2BN RoboClock 1 025 is driven from oscillator X4 RoboClock 2 U26 is driven from oscillator X5 RoboClock 2 can also be driven from RoboClock 1 output DCLK3 it required 45 RoboClock PLL Clock Buffers The CY7B994V U25 U26 High Speed Multi Phase PLL Clock Buffers offer user selectable control over system clock functions ET6000K10S User Guide www emulation com 79 BOARD HARDWARE Eighteen configurable outputs each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews at LVTTL levels refer to Figure 36 The outputs are arranged in five banks Banks 1 to 4 of four outputs allow a divide function of 1 to 12 while simultaneously allowing phase adjustments in 625 ps 1300 ps increments up to 10 4 ns One of the output banks also includes an independent clock invert function The feedback bank consists of two outputs which allows divide by functionality from 1 to 12 and limited phase adjustments Any one of these eighteen outputs can be connected to the feedback input as well as driving other inputs Selectable reference input is a fault tolerance feature which allows smooth change over to secondary clock source when the primary clock source is not in operation The reference inputs and feedback inputs are configurable to acc
24. Ci Ci ci c Ci c c Ci Ci Ci c Ci Ci 00 105 User Guide www emulation com 120 BOARD HARDWARE Signal Name FPGA Pin DDR SDRAM DDR_7B_DATA7 U15 Y34 U21 13 DDR_7B_DATA8 U15 W33 21 54 DDR_7B_DATA9 U15 W34 21 56 DDR_7B_DATA10 15 V31 21 57 DDR_7B_DATA11 15 U32 21 59 DDR_7B_DATA13 15 V33 21 62 U U DDR_7B_DATA12 U15 V32 21 60 U U DDR_7B_DATA14 15 031 21 63 DDR_7B_DATA15 UTS Tl 21 65 DDR FPGA 7B UDOQS 21 51 DDR_FPGA_7B_LDQS 21 16 DDR_FPGA_7B_UDM 21 47 DDR_FPGA_7B_LDM 21 20 DDR FPGA 7B BAO 21 26 DDR FPGA 7B 2127 DDR_FPGA_7B_CASn 21 22 DDR_FPGA_7B_CKE 21 44 DDR_FPGA_7B_CSn 21 24 DDR_FPGA_7B_RASn 21 23 U U U U U U U U U U U U U U U U U U U DDR_FPGA_7B_WEn 2121 7 0 Transceivers RocketIO transceivers are an exciting new feature of the Virtex II Pro family These multigigabit transceivers can transmit data at speeds from 622 Mb s up to 3 125 Gb s determined be the speed grade of the part please refer to the Xilinx datasheet capable of various high speed serial standards such as Gigabit Ethernet
25. Double Data Rate DDR SDRAM represents an enhancement to the traditional SDRAM Instead of data and control signals operating at the same frequency data ET6000K10S User Guide ww w emulation com 111 BOARD HARDWARE operates at twice the clock frequency while address and control operate at the base clock frequency In other words the data is written or read from the part on every clock transition or twice per clock cycle This effectively doubles the throughput of the memory device The trade off for such an improvement in throughput is increased complexity in interface logic to the DDR memory as well as increased complexity in routing the DDR signals on the printed circuit board Additionally this memory has the same latencies as standatd SDRAM so that while the data transfers are twice as fast the latencies associated with DDR SDRAM are on par with standard SDRAM 6 3 1 Basics of DDR Operation DDR SDRAM provides data captute at a tate of twice the clock frequency Therefore DDR SDRAM with a clock frequency of 100 MHz has a peak data transfer rate of 200 MHz or 6 4 Gigabits per second for a 16 bit interface In order to maintain high speed signal integrity and stringent timing goals a bi directional data strobe is used in conjunction with 5511 2 signaling standard as well as differential clocks DDR SDRAM operates as source synchronous system in which data is captured twice clock cycle using a bi directional data st
26. ET6000K10S User Guide ww w emulation com 156 BOARD HARDWARE Daughter Card Connections ET6000K10S IO Connections Test Header Signal Name P4N22 Connector Test Header P11 180 Signal Name TST_HDRA142 FPGA Pin 115 559 11 181 TST_HDRA143 U15 A 35 P4N16 P11 182 TST_HDRA144 015 36 P4N15 P11 183 TST_HDRA145 U15 AJ33 GND P11 184 GND P4N14 P11 185 TST_HDRA146 15 11 186 TST_HDRA147 15 37 P4N8 P11 187 HDRA148 15 38 P4N5 P11 188 TST_HDRA149 15 AJ41 P4N4 P11 189 TST_HDRA150 15 42 P4N1 P11 190 TST_HDRA151 15 A 31 211 191 TST_HDRA152 15 AJ32 P4NX13 P11 192 TST_HDRA153 U15 AH33 P4NX12 211 193 TST_HDRA154 U15 AH37 P4NX9 P11 194 TST_HDRA155 U15 AH38 No Connect P11 195 GND P4NX8 P11 196 TST_HDRA156 U15 AH31 P4NX3 P11 197 HDRA157 U15 AH32 PANX2 P11 198 HDRA158 U15 A 40 P4NX1 211 199 TST_HDRA159 U15 AH40 13 Two bus bars MP2 and MP3 are installed to prevent flexing of PWB They connected to the ground plane and can be used to ground test equipment Be careful not to short any power rails or signals to these metal bars they can carry a lo
27. Hardware Selup i eoo tti er la D E AERE KEIN TOP Re REIR MEER eeu 138 10 2 1 Present Signals 138 10 2 2 M66EN and PCIXCAP Encoding 138 10 2 3 Further Information on PCI PCI X Signals 139 11 POWER SYSTEM 140 11 1 FI IWIISH LTSILI MM 140 11 2 Stand Alone Operation 140 11 2 1 External Power Connector M 141 11 2 2 CT 142 11 2 3 Power Indicators 142 12 TEST HEADER amp DAUGHTER CARD CONNECTIONS 142 12 1 Test een 142 12 1 1 Test Header Conectores ORC AXI 144 12 1 2 Test Header Pin Numberilig eee e ERR QUOD E TER ORO ERR ED ERI entia eased 144 12 2 ET3000K10SD Daughter Card 145 12 2 1 Daughter Card EBD S 147 12 2 2 Iun dn S 12 2 3 Unbuffered 12 2 4 12 2 5 12 2 6 Connection between FPGA and the Daughter Card Headers 13 MECHANICA V
28. 009 DDR FPGA 6A ADDIO 28 9 57 DDR DA DDR FPGA ADDii 41 10 DQ10 59 DDR DDR FPGA 6A ADDi2 42 11 60 DDR 6A 0012 DDR FPGA 6A ADDi3 17 12 0912 62 DDR 6A DQi3 A13 DQ13 63 DDH 6A 0014 DDR FPGA BAO _ 26 DQ14 6 DDR DOTS DDR FPGA GA BAT 27 BAO 0015 BAI 47 _ DDR PLL1 45 UDM 20 DDR_PLLin 46 upos DDR_6A_UDQS DDR FPGA CKE _ 44 ibas 16 6A DDR 6A RAS 55 NC DDR_FPGA_6A_WEn 21 CAS NC X DDR FPGA GA 5 24 WE NC 53 CS NC DNU 49 DOR VREF DNU 2 5V vssa VSSQ VDDQ 15 VSSQ VDDQ 55 VSSQ VDDQ 57 VSSQ VDDQ vss VDD Hs 55 VDD 733 VSS VDD IT46V64M16 TSOP66 Figure 54 DDR SDRAM Connection 6 3 3 DDR SDRAM Clocking Refer to the DDR Clocking Section 6 3 4 DDR SDRAM Termination DDR SDRAM is based on the SSTL2 JEDEC Standard Stub Series Terminated Logic 2 5V signaling standard The SSTL2 termination model used for DDR SDRAM has two types of termination e Class 1 Also called 55112 O Used for unidirectional signaling Control signals e Class 2 Also called SSTL2_II O Used for bi directional signaling Data signals Both Class 1 and Class 2 are based on a 50Q controlled impedance environment and termination to 1 25V power su
29. 2 3 3 Return Values successful function call will return zero 2 3 4 Notes The source code for bar write dword is portable to each of the operating systems intended for AETEST usage ET6000K10S User Guide www emulation com 166 APPENDIX 2 4 bar_read byte bar read byte is a high level function C function which is recommended for development by users of the ET6000K10S 2 4 1 Description bar read byte allows users of the ET6000K10S to read a byte of data from any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 4 2 Arguments The arguments for byte are shown in Table 43 They are listed order Table 43 bar read byte Arguments Argument Description Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 unsigned long byte offset Address Number of bytes to 0 0 bytes in mem space offset data byte data Pointer to a byte of data for the 0x00 Oxff read operation 8 bits Itypedef unsigned char byte 2 4 3 Return Values successful function call will return zero The byte of data read duting the access is placed in the variable location pointed to by data 244 Notes The source code for bar read byte is portable to each of the operating systems intended for usage ET6000K10S User Guide www
30. C2 VCC 102 abr 3221 o Figure 29 MCU Serial Port There are two signals attached to the MCU e Transmit Data e Receive Data TXD and RXD provide bi directional transmission of transmit and receive data No hardware handshaking is supported 3 2 CPLD The Xilinx XC95288XV U5 CPLD is needed to handle the counters and state machines associated with the high speed interface to the SmartMedia card Approximately 90 of the resources of this device are utilized so 10 are available to the user The Verilog source code for the CPLD CPLD V is provided the CD ROM The CPLD performs the following functions e Interface to the Micro Controller Data UPAD O 7 Control Signals UP RDn WRn UP ALE Clock MCU CLK e Interface to the SmartMedia Data Bus SM D 0 7 Control Signals SM REn SM WEn SM ALE CLE SM CEn SM RDYBUSYn FPGA Configuration Serial SelectMap Data Bus FPGA DJO 7 ET6000K10S User Guide ww w emulation com 71 BOARD HARDWARE Control Signals _ FPGA_RD WRn FPGA_CSn FPGA_DONE FPGA_INITn FPGA_PROGn Clock FPGA DCLK FPGA Configuration JTAG JTAG Signals _ TDI FPGA DONE TDO FPGA TMS SRAM Chip Select Generation Signal SRAM_CSn FPGA Configuration MODE Select DipSwitch Signals
31. Tti Figure 58 Recommended connections for the R14K ST11 Table 3 details the connection between the FPGA and the R14K ST11 Gigabit Ethernet Transceiver showing the pins used on the FPGA and the R14K ST11 Table 25 Connections between FPGA and R14K ST11 Gig E Fiber Signal Name FPGA Pin R14 ST11 Pin GIGEO TxP U15 A16 ET6000K10S User Guide www emulation com 123 BOARD HARDWARE Signal Name FPGA Pin R14 ST11 Pin GIGEO U15 A15 87 GIGEO RxN U15 A14 3 9 GIGE1_TxP U15 A12 GIGE1_TxN 15 A13 3 13 GIGE1_RxP 15 A11 1317 GIGE1_RxN 15 A10 1849 GIGE2_TxP 15 A8 3 21 GIGE2_TxN 15 49 15 25 GIGE2 RxP 15 7 3 27 GIGE3_TxP GIGE3_TxN U U U GIGE2_RxN U U U GIGE3_RxP U GIGE3_RxN U 7 2 Infiniband HSSCD2 The InfiniBand Architecture is a high speed point to point serial connection standard These links can operate three levels of link performance 2 5 Gbps 10 Gbps and 30 Gbps The 2 5 Gbps connection it within the range of operation of the Virtex II Pro RocketIO For more information about InfiniBand see http www infinibandta ore home 7 2 1 to InfiniBand HSSDC2 Connector The connection between the FPGA and the InfiniBand HSSDC2 connector is fairly simple involving only four wires per connector as well as a few discrete components to provide for AC coupling of th
32. Goto Return to the original address specified at the beginning press 0 Quit Return to Memory Menu press MINNTSystem32 cmd exe aetest_wdm exe 8 4 8 18 14 18 55555555 55555555 55555555 55555555 45 55555555 55555555 55555555 55555555 55555555 55555555 55555555 55555555 55555555 55555555 55555555 928 91 d42d278a 3104312 1 04 2 fe2e4768 27e38fba 67558ae3 483338 2 Sicaifde 553 17 7 54446448 44 716e3a8f 87b5b75d 11461656 19323 0 4 4 744569 561fef79 2e 7fb5id d73dd5b7 80 92529 e93efcUfF 94450 21 4478 733 81629970 2 05 1 36712 c6falech 1 650 O946f6df 902 9 ei9eb 77e BPadbbce 72c27ac3 a4955dad 14 e4f84318 888c51f8 751ec641 20721874 2565 9733e8b4 34 8 58 579775 914 5020 48897729 749 4 2 77 447 4 48264418 ceibc8b3 40 69913 28 189e294d 51 49475 55060441 8485 11c 48 b2c4b69c 824 9 fifa352f 87 27 f848e715 4546 48dbaff2 789dc349 c8Ubb815 6 383 b27eb736 e4f3f500 54259244 dib2b6802 f f89ebb c2242543 6261fb 76 176 8 Sh7FFO84 250 1568 27373264 35f135bB8 dei3d
33. for Windows 98 ME using VxD driver ET6000K10S User Guide www emulation com 12 GETTING STARTED AETEST_WDM EXE for Windows 2000 XP 3 The AETEST utility should now recognize the ET6000K10S with the DEVICE ID of 0 1600 and its VENDOR ID of Ox17DF AWINNTSystem32 cmd exe aetest_wdm exe icrosoft Windows 2000 Version 5 00 21951 lt C gt Copyright 1985 2000 Microsoft Corp gt 4 aetest aetest Daetest_wdm exe ymbolic link is pcillven 17df amp deu 1608 amp subsyus 9 56788 4713 amp 4a7580b58 amp 08 amp 38 81 f Bbi1da27 6ac7 4d1f 9eb8 1daf10 57e71315 ound device 174 41600 name DN68808K18S UirtexII Pro Single FPGA board ompiled on Sep 15 2083 at 11 19 42 ress any key 4 Follow the on screen instructions until the Main Menu 15 displayed AWINNTSystem32 cmd exe aetest wdm exe ASIC Emulator PCI Controller Driver 49 1 PCI Menu 2 Memory Menu 3 Flash Menu 5 Daughter Board Menu Q gt Quit PCI BASE ADDRESS bbaie888 1 b3aie 88808 4 66800000 Please select option m 5 From the Main Menu choose Memory Menu The memory menu will now appear 6000 105 User Guide www emulation com 13 GETTING STARTED t WINNT System32 cmd exe aetest_wdm exe ASIC Emulator PCI Controller Driver 049 Write Dword Same Address 22 Read Duord Same Address Write Read Duord Same Address
34. 10 1 Connection to the FPGA The FPGA connections to the PCI bus consist of 91 signals spread across two banks Bank 4 and Bank 5 A description of these signals can be found are in the following sections Note The PCI interface is not 5V tolerant Do not modify the PCI edge connector to fit in the host PC 10 1 1 PCI VCCO on the FPGA A Linear Technology LTC1763 regulator refer to Figure 61 is used to ensure electrical compatibility to PCI and to protect the Virtex II Pro from over voltage conditions It is used for the VCCO of the banks connected to the PCI interface For more information see XAPP653 Virtex II Pro PCI Reference Design at http www xilinx com xapp xapp653 pdf 5V TP7 3 0V U12 SHON 4 85 ict 6278 ND 5 015 10uF 2202 6281 10V is 1 7 OND RE E T 16 0 1uF 20 R115 20 STANT LT1763 808 26 1 TANT Figure 61 VirtexII Pro PCI VCCO Regulator 10 1 2 PCI Edge Connector Figure 62 shows P4 the PCI 3 3V 64 Bit edge connector used to interface with the host PC ET6000K10S User Guide ww w emulation com 133 BOARD HARDWARE
35. CLKFB 0 CLK270 RS CLKDV CLK2X LOCKED DCM WCLK PHASE SHIFT X253 04 070500 Figure 38 DDR DCM Implementation 4 6 2 Connections between FPGA and DDR PLL Clock Buffer The connection between the FPGA and the DDR PLL Clock Driver U27 consists of SSTL_2 differential DDR PLLO can be used as a feedback reference clock input The connections shown in Table 16 Table 16 Connection between FPGA and DDR PLL Clock Driver Signal Name FPGA Pin DDR PLL Clock Driver U27 DDR_CLK U15 P41 U27 13 ET6000K10S User Guide www emulation com 87 BOARD HARDWARE DDR_CLKn U15 P42 DDR_PLLO 01522 DDR_PLLOn U15 K22 4 7 Power PC PPC Clock A 3 3 V half can oscillator X6 and the signal SYS_CLK provide an external clock source for the PPC The oscillator is socketed and the 6000 10 is shipped with a 100MHz oscillator refer to Figure 39 43 3V R48 2 2R C142 0 047uF R41 YS CLK SY LK 3 RS 5 33 Figure 39 PPC External Clock 4 7 1 Clocking Methodology Refer to the Xilinx application notes for more information on this subject 4 7 2 Connections between FPGA and DDR PLL Clock Buffer The connection between the FPGA and the external oscillator are shown in Table 17 Table 17 Connection between FPGA and External PPC Oscillator Signal Name FPGA Pin DDR PLL Clock Driver U27 SYS_CLK U15 AN22 X6 3 4 8 Rocket IO Clock
36. E s 1 1 Summary of Virtex II Pro Features 1 2 PowerPCM JOS 13 RocketlO 3 125 Gbps Transceiv rs ote 17 1 4 Virtex II FPGA Fabric 2 FOUNDATION ISE 6 11 2 1 Foundation Features 5 2 1 1 IDIS UE 2 1 2 2 1 3 Implementation and Configuration 2 1 4 Integr tion e ee ted PER EGRE UR ORE REDI 3 PRO DEVELOPERS INTRODUCTION TO THE SOFTWARE 5 24 1 EXPLORING THE SOFTWARE TOOLS eas 1 1 7 1 1 1 Getting Started with 5 1 12 M ETUR 1 1 3 Io eM uim 1 1 4 Memory Menu m 1 1 5 MEMOS o ONERE EE RE A E 1 1 6 Daughter Bo rd Menus nano sna A ETAREN OE A RTA OAA me AENEA ERETI 1 2 GNU 2 GETTING MORE INFORMATION 2 1 Printed Documentation 2 2 ue oe R 2 3 Online PROGRAMMING CONFIGURING THE HARDWARE cccscssssssssssssscssssssssessssssssssessssssesssssessssesessso
37. SDRAM termination voltage VTT must track 50 of VDDQ over voltage temperature and noise The ML6554 024 is used as a voltage source for DDR termination Connecting the pin to the 2 5V supply allows the regulator to track the VDDQ supply refer to Figure 57 A dedicated VREF output supplies the VREF pins the as well as on the DDR SDRAM devices and maintains a less that 40mV offset from 43 3V R36 100 C120 Bape 100 100uF 100uF 42 5V 16 10 1 10 109 d 10 8 1 25V L1 rr ee C464 3 3uH 21 1500 150uF 0 1uF 3 3 192 A 10K 12 1 25V SHDN VL1 VL2 s 4 20 E PGND1 0 001uF PEND VREF OUT TANT TANT E AGND DDR VREF ae 8 _ PKGGND DDR VREF P97 13 14 15 16 ML6554 PSOP16 1K 5 Figure 57 DDR VTT Termination Regulator 6 3 6 DDR SDRAM Connection to the FPGA The DDR SDRAM memory components are connected to the FPGA on Bank 6 and Bank 7 As mentioned the connections between the FPGA and the DDR SDRAM are not homogeneous as control and address are handled differently from the data and differently from the clocks However all of these signals are controlled impedance and are SSTL2 terminated The termination of these signals is covered in
38. U15 AP31 U15 AR31 U15 AM31 10 Interface Peripheral Component Interconnect PCI Local Bus is a bus standard that is a mainstay of many different computer systems PCI is a high performance bus with multiplexed address and data lines Defined for both 32 bit and 64 bit wide data buses PCI is intended for use as an interconnect mechanism between highly integrated peripheral controller components peripheral add in boards and processor memory systems The ET6000K10S can be hosted a 32 bit or 64 bit PCI PCI X slot and includes two main components FPGA as the PCI bus Master e PCI Edge Connector Pro parts does not tolerate 5V signaling so the 6000 105 must be plugged into a 3 3V PCI slot PCI X by definition is 3 3V signaling The PWB is keyed so that it is not possible to mistakenly plug the board into a 5V PCI slot Do NOT out the key in the PCI host slot and do NOT modify the ET6000K10S to get it to fit into the slot If you need 3 3V PCI slot the ETPCIEXT S3 Extender can perform this function Please refer to Emulation Technology website extender also has the capability to slow the clock frequency of the PCI bus by a factor of two function that is very useful when prototyping ASIC s The 3 3V power on the PCI connector is not used Instead 3 3V is generated from the 5V supply ET6000K10S User Guide ww w emulation com 132 BOARD HARDWARE
39. Use Current Simulatar Emulator FLASH Memory Karl F data workarea dn3000K10 uP DN 11 After programming the processor close all AVR Studio windows and open the HyperTerminal Window Press ENTER to display the first initialization instruction 12 Enter number of FPGAS on board 1 6 1 13 Please select the first FPGA on the board F A E B or 14 Please enter selection 1 6 for F 9 15 The initialization process will then be completed and present the user with the FPGA configuration main menu The FPGA is now ready to be configured see Configuring the FPGA using SelectMap ET6000K10S User Guide www emulation com 50 PROGRAMMING CONFIGURING THE HARDWARE 3 Configuring HyperTerminal A terminal emulator is required to monitor MCU transactions Emulation Technology suggests using the Windows based program HyperTerminal Hypertrm exe The configuration file for HyperTerminal ET6000K10S ht is supplied on the CD ROM can be downloaded from Emulation Technology website The RS232 port is configured with the following parameters Bits per second 9600 Data bits 8 e Parity None e Stop Bits 1 Flow control None e Terminal Emulation VT100 A cable that converts the 5 2 header to is shipped with the ET6000K10S Insert the 5 x 2 header into the MCU RS232 header P5 P5 is not keyed ensure cotrect pin orientation Note MCU RS232 Header P5 is not ke
40. vss VDDQ vss VDDQ vss VDDQ vss VDDQ CY7CT481V33 TOFP 100 Figure 47 SSRAM Connection The SSRAM s can be stuffed with the following options Pipelined Flow through Pipelined with NoBL Flow through with NoBL e Pipelined ZBT Flow trough ZBT Syncburst Flow through Figure 48 is the most straightforward type of SSRAM Write data may be accepted on the same clock cycle as the activation signal and address and read data is returned one clock cycle after it is requested Syncburst is designed to allow ET6000K10S User Guide www emulation com 98 BOARD HARDWARE two controllers to access the same SSRAM using two activation signals ADSC and ADSP5 an activation with ADSP requires data and byte enables one clock cycle after the address and activation Syncburst Pipelined Figure 49 1s identical except for registered outputs which delay read data an additional clock cycle but may be necessary for high speed designs 18 2 Address Burst Control 1 0 Memory Block Control Logic Figure 48 SSRAM Flow trough Write Control 18 2 Burst a Control 1 0 Figure 49 SSRAM Pipeline Zero Bus Turnaround ZBT SSRAM s are designed to eliminate wait states between reads and writes by synchronizing data Figure 50 accept and return data one clock cycle after the address phase and ZBT Pipeline SSRAMs Figur
41. 1Gb 1Mb x 36 7 gt 4 81 5 81 4 43 gt 16M x 16 X4 100 VO PCI VO PCI TSOP66 BB 5 1 User 10 5 996 PCI PCI X I O 91 Rocket 5 180 9 pins Differential Pairs 492 Figure 25 Bankout Diagram 3 FPGA Configuration Emulation Technology developed the SmartMedia Configuration Environment to address the need for a space efficient pre engineered high density configuration solution for systems with single or multiple FPGA s The technology is a groundbreaking in system programmable configuration solution that provides substantial savings in development effort and cost per bit over traditional PROM and embedded solutions for high capacity FPGA systems Virtex II Pro devices are configured by loading application specific configuration data into internal memory Configuration is carried out using a subset of the device pins some of which ate dedicated while others can be reused as general purpose inputs and outputs after configuration is complete SmartMedia is the primary means of configuring the FPGA on the ET6000K10S board Configuration of FPGA is accomplished using either Serial SelectMAP or the JTAG interface The remainder of this section describes the functional blocks that entail the FPGA configuration envitonment 3 1 Micro Controller Unit MCU The Atmel ATmega128L U4 micro controller is used to control the configuration process The ATmega128L provides the
42. 48 148 TST HDRATi3 TST HDRA34 49 1 7 7149 __157_ 114 TST_HDRA3S 5017 150 5 TST 51 6 1151 CND 5 7 52 152 TST_HDRATIO TST 8 53 7 153 TST HDRA3S 54 154 TST_HDRATIO GND 55 7155 HDHATIO TST HDRA4O 56 7 156 HDHA120 5 57 7157 TST HDRAT21 TST HDRA4Z 58 158 22 ST HDRA43 5917 159 ST HDRAT23 ST 44 60 160 ST 24 ST 45 ST HDHAT25 ST 45 62 17 162 GN ST HDRA47 63 163 TST 126 TST HDRA48 64 164 TST_HDRAT27 TST HDRA49 65 165 5 _ 28 GND 66 166 TST HDRA128 TST_HDRASO 67 7167 TST ADRAT30 68 168 TST HDRA52 69 169 TST 2 TST HDRA53 70 770 TST HDRA133 ST 54 7 579 4 TST 55 72 172 TST HDRA135 5 HDHA56 73 173 TST HDRA57 74 174 HDRAT36 75 175 7 ST 59 76 176 ST GND 77 DENT ST HDHAT3S ST 6 781 178 ST 40 ST_HDRAGT 7917 179 ST_HDRATAT ST_HDRAGZ 80 ST 42 TST HDRA63 81 181 TST HDRA143 5 4 82 182
43. BWEn U15 AM4 U15 AP4 SRAM4_CEn U15 AT4 SRAM4 DQAO SRAM4_DQA1 U15 AN5 U15 AP5 SRAM4 DQA2 U15 AR5 SRAM4_DQA3 SRAM4_DQA4 U15 AT5 U15 AY5 SRAM4_DQA5 15 AK6 SRAM4_DQA6 SRAM4_DQA7 15 AM6 15 AN6 SRAM4_DQBO 15 SRAM4_DQB1 SRAM4_DQB2 15 AT6 SRAM4_DQB3 15 AY6 SRAM4_DQB4 15 7 SRAM4 DOB5 U U U U U15 AR6 U U U U 15 AL7 SRAM4 DOBG ET6000K10S User Guide U15 AM7 ww w emulation com ea a e 110 BOARD HARDWARE Signal Name FPGA Pin SRAM4_DQB7 U15 AN7 SRAM4 DQCO ULT APT SRAM4 U15 AR7 SRAM4 DQC2 U15 AU7 SRAM4 DQC3 U15 AV7 SRAM4_DQC4 U15 AW7 SRAM4_ DQC5 U15 AK8 SRAM4 DQC6 U15 AL8 SRAM4_DQC7 SRAM4_DQD0 U15 AM8 U15 AN8 SRAM4_DQD1 U15 AP8 SRAM4_DQD2 SRAM4_DQD3 U15 AT8 U15 AU8 SRAM4_DQD4 U15 AK9 SRAM4_DQD5 SRAM4 DQD6 U15 AL9 U15 AM9 SRAM4 DQD7 U15 AN9 SRAM4_DQPA SRAM4_DQPB U15 AK10 U15 AL10 SRAM4_DQPC U15 AM10 SRAM4_DQPD SRAM4_GWn L15 AL11 U15 AR4 LBOn U15 AM1 5 4 OEn U15 AL5 SRAMA ZZ U15 AM5 SRAM 6 3 DDR SDRAM U7 20
44. Board Level Integration Xilinx understands the critical issues such as complex board layout signal integrity high speed bus interface high performance I O bandwidth and electromagnetic interference for system level designers To ease the system level designers challenge ISE provides support to all Xilinx leading FPGA technologies System IO XCITE e Digital clock management for system timing control management for electromagnetic interference To really help you ensure your programmable logic design works in context of your entire system Xilinx provides complete pin configurations packaging information tips on signal integration and various simulation models for your board level verification including e IBIS models HSPICE models e STAMP models 3 Pro Developers Kit V2PDK is the Virtex II Pro Developer s Kit and is included to provide an existing framework of hardware and software code to explore the capabilities of the Virtex II Pro as well as a basis to build new systems wide variety of software and hardware tools are used to build a Virtex II ProTM design V2PDK The design flow is a tool chain methodology that exists to simplify the entire design process by providing integration between the tools and automating tasks The main focus of the design flow is integrating the programs with each other to accomplish the system design The system design process can be loosely divided i
45. CON10X3 CON10X3 REFSEL1 CON10X3 CON10X3 CON10X3 Figure 37 RoboClock Configuration Jumpers 4 5 3 Useful Notes and Hints The RoboClock consistently outputs 32 5MHz signals in cases of improper settings or unacceptable clock inputs This was observed when the CY7B994V part was operating at a nominal frequency of 36 4MHz with FS set LOW Identical clocks were sent to PLL2B and PLL2BN For the CY7B994V part the operating frequency can reach up to 200 MHz However the maximum output frequency is 185MHz This means when 185 MHz lt lt 200MHz the output divider must be set to at least 2 Otherwise the RoboClocks will output garbage 4 5 4 Customizing the Oscillators The user can customize the frequency of the clock networks by stuffing different oscillators in X4 and X5 The 6000 105 is shipped with 14 318MHz oscillator in location X4 and 33 333MHz oscillator in X5 The RoboClocks are not 5V tolerant so 3 3V oscillators are necessary ET6000K10S User Guide www emulation com 85 BOARD HARDWARE Emulation Technology suggests Digi Key http www digikey com as a possible source for the oscillators Of note is the Epson line of oscillators called the SG 8002 Programmable Oscillators Any frequency between 1 00MHz 106 25MHz can procured in the normal Digi Key shipping time of 24 hours A half can 3 3 VCMOS version is needed with a tolerance of 50ppm The part number for an acceptable
46. DDR SDRAM Termination The Data signals DQ the Data Strobe DQS and the Data Mask DM signals are point to point signals going from the FPGA to the DDR SDRAM components As mentioned above these signals are controlled impedance and terminated according to the DDR SDRAM specification This termination is covered below in DDR SDRAM Termination The connection of the Data the Data Strobe and the Data Mask signals between the FPGA and the DDR SDRAM components in covered in Table 23 The data data strobe and data mask signals all serve different purposes The data signals are self evident carrying the raw data between the chips and are bi directional The data strobe signals are responsible for actual clocking in the data on rising and falling edges of the clock Finally the data mask signals can be used to enable or disable the reading and writing of some of the bytes in a 16 bit word transaction ET6000K10S User Guide www emulation com 115 BOARD HARDWARE Table 23 Connection between FPGA and DDR SDRAM Signal Name FPGA Pin DDR_6A_ADDO 15 42 DDR_6A_ADD1 15 AF39 DDR_6A_ADD2 15 AF36 DDR_6A_ADD3 15 AF34 DDR_6A_ADD4 15 AF33 DDR 6A ADD5 15 AF35 DDR 6A ADD6 15 AF37 DDR_6A_ADD7 15 40 DDR_6A_ADD8 15 AE35 DDR_6A_ADD9 15 41 DDR_6A_ADD10 15 AE36 DDR 6A ADD11 15 41 DDR_6A_ADD12 15 AD42 DDR 6A ADD13 15 AE38 DDR_6A_DATAO 15 AE31 DDR 6A DATA1 U15 AF32 DDR_6A_DATA2 15 AE32 DDR DATA3 15 AE33 DDR DAT
47. FPGA and DDR PLL Clock Buffer 47 Power PPG Clock sete eee e E ERE LAS EXTR WP Eee EX VE PERF ee Pere eese 4 7 1 Clocking Methodology diii ee rra rre eet die eie e HE RE CHR Pate ee 4 7 2 Connections between FPGA and DDR PLL Clock Buffer 4 8 Rocket IO ClO CK 4 8 1 Clocking Methodology 4 8 2 Connections between FPGA and DDR PLL Clock Buffer 4 8 3 Reference 64 5 4 9 External User Clock SMA 4 9 1 FPGA to SMA Connector RESET TOPOLOGY 2 105 Reset 5 2 PPC Reset MEMOR Yrer neeaae 6 1 FLASH 6 1 1 FLASH Connection the FPGA 6 2 Synchronous 6 2 1 SSRAM Configuration 6 2 2 6 2 3 SRAM Termination 6 2 4 SSRAM Connection to the FPGA 6 3_ DDR SDRAM sreci t t 111 6 3 1 Basics o DDR Operations 112 6 3 2 DDR SDRAM Configuration 112 6 3 3 DDR SDRAM Clocking 113 6 3 4 DDR SDRAM Termination 113 6 3 5 DDR SDRAM Power Supply 115 6 3 6 DDR SDRAM Connection to the FPGA ER 115 7 ROGKETLIO TRANSCEIVERS
48. FPGA and DDR PLL Clock Driver e 17 Connection between FPGA and External PPC Oscillator 18 Connections between FPGA and Rocket IO Oscillators e 19 Connections between FPGA and SMA Connector CLK e 20 PPC Reset e 21 Connection between FPGA and FLASH 22 Connection between FPGA and SRAM s e 23 Connection between FPGA and DDR SDRAM e 24 Pinout of R14K ST11 Gigabit Fiber Transceiver e 25 Connections between FPGA and R14K ST11 Gig E Fiber e 26 Connections between FPGA and Infniband HSSDC2 e 27 Connections between FPGA and SATA e 28 Connections between FPGA and SMA Connectors e 29 RocketIO Performance e 30 CPU Debug connection to FPG e 31 Combined CPU Trace Debug connection to FPGA e 32 GPIO LED s e 33 FPGA GPIO LED s e 34 PCI to FPGA Connections e 35 Present Signal Definition e 36 M66EN and PCIXCAP Encoding 37 Voltage Indicators e 38 External Power Connections e 39 Connection between FPGA and the Daughter Card Headers e 40 bar write byte Arguments e 41 bar write word Arguments 2 write dword Arguments e 43 bar read byte Arguments 4 5 4 44 bar read word Arguments 45 bar read dword Arguments e 46 dma buffer allocate Arguments e 47 buffer free Arguments e 48 dma write dword Arguments e 49 dma re
49. PCI_PERRn 15 17 PCI REQ64n U15 AR23 PCI ACK64n U15 AY23 PCI REQn U15 AW10 PCI RSTn U15 AP20 PCI_SERRn ET6000K10S User Guide www emulation com U15 AV18 137 BOARD HARDWARE Signal Name Connector FPGA Pin PCI STOPn P4 A38 U15 AU16 PCI TRDYn P4 A36 U15 AT16 10 2 PCI PCI X Hardware Setup The following section describes the PCI PCI X hardware setup More information is available from the PCI PCI X Specifications available from PCI SIG http www pcisig com home 10 2 1 Present Signals The Present signals indicate to the system board whether an add in card is physically present in the slot and if one is present the total power requirements of the add in card refer to Table 35 Table 35 Present Signal Definition PRSNT1 PRSNT2 Add in Card Configuration Add in card present 25 W maximum Add in card present 15 W maximum Add in card present 7 5 W maximum The 6000 105 is factory configured for 25W power setting 1 1 2 and JP1 3 4 jumpers installed 10 2 2 M66EN and PCIXCAP Encoding The 66MHZ ENABLE pin indicates to a device whether the bus segment is operating at 66 or 33 MHz Add in cards indicate whether they support PCI X and if so which frequency by the way they connect one pin called PCIXCAP refer to Figure 63 PCI X 133 CAP PCI X 66 CAP RES GND R90 228 10 0 01uF C241 0 01uF
50. Press any key to exit the selected memory device test The test should complete successfully as indicated by the dots ET6000K10S User Guide www emulation com 14 GETTING STARTED cmd exe aetest_wdm exe Duord Same fiddress BAR Memory Fill BAR Memory Write BAR Memory Display memory test on SSRAM 1 memory test on SSRAM 2 memory test on SSRAM 3 memory test on SSRAM 4 memory test on DDR full memory test Cincluding blockram gt memory test on FPGA block memory bar memory range test bar memory address data bitwise test Main Menu Q gt Quit BASE ADDRESS 1 1 2 988880008 5 68800008 Please select option word count 100 top if an error occurs or isplay any errors that occur 8 Congratulations You have now programmed the ET6000K10S and successfully executed our AETEST utility to exercise various features of the ET6000K108 ET6000K10S User Guide www emulation com 15 INTRODUCTION VIRTEX II AAND ISE Chapter Introduction to Virtex l Pro and ISE 1 Virtex4l Pro The Virtex II Pro FPGA solution is the most technically sophisticated silicon and softwate product development in the history of the programmable logic industry The goal was to revolutionize system architecture from the ground up To achieve that objective the best circuit engineers and system architects from IBM Mindspeed and Xili
51. ROM 30 PCI_CS_INTERRUPT_LINE PCI_CS_INTERRUPT_PIN x3d PCI CS MIN GNT PCI MAX LAT Ox3f Input config offset hex Ox00 Oxff wotd to write in hex Loop indefinitely n If looping was selected pressing any key will stop the loop 7 Read Config DWORD Allows the user to read from configuration space This function has the option to single read loop read with display and loop read without display 8 Display Config registers Reads and displays all of the configuration registers 0x0 0 0 OxFC for device OxFC for the active device and function number Use function 1 0 options S and F to change the active device and function numbers respectively ET6000K10S User Guide www emulation com 30 INTRODUCTION THE SOFTWARE TOOLS Function Name Description Configure BARs from a file Reloads the PCI configuration of the active device from a file It writes to the command register and writes the 6 BARs with the values from the file This function is useful for hot swapping devices power switch still required on extender or reinitializing a device when its configuration has been altered WARNING Since the PCI BIOS is not assigning the BARs for this device a memory conflict may be induced by using this option This option is for advanced user only Save BAR configuration to Writes PCI Device ID Vendor ID and the BARs into a a file
52. allows users of the 6000 105 to read dword of data from any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 6 2 Arguments The arguments for read d word are shown in Table 45 They are listed in order Table 45 read dword Arguments Argument Description Possible Values unsigned long barnum BAR number to be accessed 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 unsigned long byte offset Address Number of bytes to 0 0 bytes in mem space offset data dword data Pointer to a dword of data for the 0 00000000 read operation 32 bits typedef unsigned char dword 2 6 3 Return Values A successful function call will return zero The dword of data read during the access is placed in the variable location pointed to by dara 2 6 4 Notes The source code for bar read dword is portable to each of the operating systems intended for AETEST usage ET6000K10S User Guide www emulation com 169 APPENDIX 2 7 dma_buffer_allocate dma_buffer_allocate is a high level function C function which is recommended for development by users of the ET6000K10S 2 7 1 Description buffer allocate allows users of the ET6000K10S to allocate DMA buffer 2 7 2 Arguments The arguments for dma buffer allocate are shown in Table 46 They are listed in order T
53. and function number without displaying them This function is useful when the user is debugging configuration accesses Loops on device number 0 reading the Vendor ID and Device ID The function moves onto the next device number 1 when the user presses a key The function moves all the way through device number 0 to device number Ox7F in case there are any bridges on your PCI bus Display all PCI information for PCI device function 7 0 Reads and displays all of the configuration space for the active device and function number Use options 5 and to change the active device and function numbers respectively Then use this option to view the entire configuration space ET6000K10S User Guide www emulation com 29 INTRODUCTION THE SOFTWARE TOOLS Option Function Name Description 6 Write Config DWORD Allows the user to write to configuration space following text will appear to remind the user what is in configuration space for a PCI device PCI_CS_VENDOR_ID 00 PCI_CS_DEVICE_ID 0x02 PCI COMMAND x04 PCI_CS_STATUS Ox06 PCI_CS_REVISION_ID x08 PCI CS CLASS CODE 0x09 PCI CS CACHE LINE SIZE PCI_CS_MASTER_LATENCY xOd PCI_CS_HEADER_TYPE PCI_CS_BIST OxOf PCI CS BASE ADDRESS 0 0x10 PCI_CS_BASE_ADDRESS_1 x14 PCI_CS_BASE_ADDRESS_2 0x18 PCI_CS_BASE_ADDRESS_3 PCI_CS_BASE_ADDRESS_4 0x20 PCI_CS_BASE_ADDRESS_5 0x24 PCI CS EXPANSION
54. assert PWRRSTn The CPLD inverts the PWRRSTn signal to PWRRST that is used to disable the transmitter in the RS232 interface U6 during programming of the MCU U4 This is done to avoid contention on the BRXD signal ET6000K10S User Guide www emulation com 92 BOARD HARDWARE Depressing the reset push button S1 causes the following sequence of events 1 Reset of the CPLD and MCU 2 Reset of FPGA through FPGA_GRSTn signal 3 FPGA configuration is cleared 4 If the dip switch is set for SelectMAP configuration option and there is a valid SmartMedia card inserted into the socket then the FPGA will be configured A SmartMedia card is valid if it complies with the SSFDC specification and contains a file named main txt in the root directory If the card is invalid or there is no card present then the FPGA will not be configured 5 Main Menu will appear in the Terminal Window Note The identical sequence of events occurs at power up 5 2 PPC Reset The ET6000K10S also contains another RESET push button 53 used to reset the PPC This signal is pulled up on the ET6000K10S The user is responsible for debouncing the reset signal in the FPGA Table 20 shows the connection between the reset push button and the FPGA Table 20 PPC Reset Signal Name FPGA Pin Push Button Switch PPC RESETn U15 F24 53 4 6 The ET6000K10S provides three different memory technologies to the user FLASH Syn
55. between the PCI connector and the FPGA Table 34 shows the connection between the PCI Edge Connector and the FPGA The VCCO of the banks are connected to 3 0 Table 34 PCI to FPGA Connections Connector FPGA Pin P4 A58 U15 AU20 ET6000K10S User Guide ww w emulation com 134 BOARD HARDWARE Connector FPGA Pin 4 58 U15 AW23 4 57 15 20 P4 B56 15 AV23 P4 A55 P4 B55 15 AY20 P4 A54 U U U15 AU19 U U 152XT19 P4 B53 U15 AW20 P4 B52 U15 AV20 PCI AD10 P4 A49 U15 AT18 U15 AY19 PCI AD11 U15 AR18 PCI AD12 PCI AD13 U15 AW19 15 AU17 PCI AD14 15 AV19 PCI AD15 PCI AD16 15 ATI 15 AU15 PCI AD17 15 15 PCI_AD18 PCI_AD19 15 AU15 15 AV15 PCI AD20 15 13 PCI AD21 PCI AD22 15 AY14 15 AR13 PCI AD23 15 AY13 PCI AD24 15 AU12 PCI AD25 15 AV13 PCI AD26 U U U U U U U U U U U U U U 15 AT I2 PCI AD27 U15 AW12 PCI AD28 U15 AV11 PCI AD29 ET6000K10S User Guide ww w emulation com U15 AY11 BOARD HARDWARE Signal Name Connector FPGA Pin PCI_AD30 P4 A20 15 AU11 PCI_AD31 P4 B20 15 AY 10 PCI AD32 P4 A91 PCI AD33 P4 B90 15 AY33 PCI AD34 P4 A89 U U U15 AV33 U U 15 AU33 PCI AD35 P4 B89 U15 AW33 PCI_AD36 P
56. configured e Level 2 All messages that Level 1 displays Options that are found in main txt file names for each FPGA as entered main txt Maker ID device ID and size of Smart Media card All files found on Smart Media card If sanity check is chosen the bit file attributes will be displayed part package date and time of the bit file During configuration a will be printed out after each block 16 KB has successfully been transferred from the Smart Media to the current FPGA 4 2 2 Sanity Check The Sanity Check if enabled verifies that the bit file was created for the right part the right version of Xilinx was used and the bitgen options were set correctly If any of the settings found in the bit file are not compatible with the FPGA a message will appear from the serial port and the user will be asked whether or not they want to continue with the bit file Please see the section Bit File Generation for SelectMAP Configuration for details on which bitgen options need to be changed from the default settings A PC version of the sanity check can be run on your bit files before copying them onto the Smart Media card see section PC Bit File Sanity Check for more details 4 2 3 Format of main txt format of the main txt file is as follows 1 The first nonempty uncommented line in main txt should be Verbose level X where can be 0 1 or 2 If this line is missing
57. data stored into the buffer pointed to by IpOutBuffer LPOVERLAPPED IpOverlapped Pointer to an OVERLAPPED structure 2 12 3 Return Values A successful DeviceloControl operation will return zero non zero value is returned if a failure occurs ET6000K10S User Guide www emulation com 176 APPENDIX 2 12 4 Notes hDevice The CreateFile function should be used to retrieve a handle dwloControlCode See include qlentlcodes h which is included with the AETEST source code for example control codes IpInBuffer This parameter can be set to NULL if no input data is required for the operation nInBuffetSize N A IpOutBuffer This parameter can be set to NULL if operation does not produce any output data NOutBufferSize N A IpBytesReturned If the output buffer is too small the call function fails and the returned byte count is zero If the output buffer is full prior to operation completion the call will fail However DeviceIoControl will return all of the data in the output buffer and returned byte count will correspond to the amount of data returned IpOverlapped If hDevice was opened with the FILE FLAG OVERLAPPED flag IpOverlapped must point to a valid OVERLAPPED structure Under these conditions the operation is asynchronous i e overlapped operation IpOverlapped is NULL under these conditions the function will fail If the FILE FLAG OVERLAPPED was not used to open hDevice Ip
58. emulation com 167 APPENDIX 2 5 bar read word read word is a high level function function which is recommended for development by users of the 00 105 2 5 1 Description bar read word allows users of the ET6000K10S to read word of data from location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 5 2 Arguments The arguments for read word are shown in Table 44 They are listed in order Table 44 read word Arguments Argument Description Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 unsigned long byte offset Address Number of bytes to 0 0 bytes in mem space offset data wotd data Pointer to a word of data for the 0 0000 Oxffff read operation 16 bits typedef unsigned char word 253 Return Values A successful function call will return zero The word of data read during the access is placed in the variable location pointed to by data 2 5 4 Notes The source code for bar_read_word is portable to each of the operating systems intended for AETEST usage ET6000K10S User Guide www emulation com 168 APPENDIX 2 6 bar read dword bar read dword is a high level function C function which is recommended for development by users of the ET6000K10S 2 6 1 Description bar read dword
59. following features 128K bytes of In System ET6000K10S User Guide www emulation com 68 BOARD HARDWARE Programmable Flash with Read While Write capabilities 4K bytes EEPROM 4K bytes SRAM 53 general purpose I O lines 32 general purpose working registers Real Time Counter RTC four flexible Timer Counters with compare modes and PWM 2 USARTs byte oriented Two wire Serial Interface 8 channel 10 bit ADC with optional differential input stage with programmable gain programmable Watchdog Timer with Internal Oscillator an SPI serial port IEEE std 1149 1 compliant JTAG test interface also used for accessing the On chip Debug system and programming and six software selectable power saving modes The micto controller interfaces to the CPLD U5 via an 8 bit bus and the SmartMedia interfaces to the CPLD via an 8 bit bus The FPGA interfaces to the CPLD via the JTAG interface and an 8 bit bus used during Serial and SelectMap programming of the FPGA The amount of internal SRAM 4 Kbytes is not large enough to hold the FAT needed for SmartMedia so an external 32K x 8 SRAM U7 was added The micro controller is programmed in system via the serial programming interface SPT The micro controller has the following responsibilities e Reading the SmartMedia card Configuring the Virtex II Pro FPGA Executing ET6000K10S self tests Other than FPGA configuration the micro controller has no other function Less than half of th
60. or Use Example font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets not connected An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild design_name Braces A list of items from which you must choose one ot more lowpwr on off Vertical bar Vertical ellipsis Separates items in a list of choices Repetitive material that has been omitted lowpwr off IOB 1 Name IOB 2 Name CLKIN Horizontal ellipsis Repetitive material that has been omitted allow block block_name loc 1002 locn Prefix or suffix th Indicates hexadecimal notation Read from address 0x00110373 returned 4552494h Letter H or Signal is active low 3 2 Online Document The following conventions are used in this document INT is active low fpga inta nis active low Convention Meaning Use Example ET6000K10S User Guide www emulation com ABOUT THIS MANUAL Blue Text Cross reference link to a See the section Additional location in t
61. oscillator from this family would be SG 8002DC PCB ND e Package SG 8002DC Halfcan Output Enable 33V CMOS 50 If the order is placed via the web page the requested frequency to two decimal places is placed in the Web Order Notes datasheet is on the CD ROM for this oscillator Any polarity of output enabled for each oscillator on pin 1 is acceptable Ensure the proper jumper settings for JP7 B9 JP7 B10 See Table 15 for a description 4 6 DDR Clocking The DDR Clock is generated in the FPGA by using the Digital Clock Managers DCM Clocking for DDR SDRAM requires the transmission of two clocks the positive clock and the negative clock 5511 2 differential These two clocks are 180 out of phase from each other and their phase alignment must be tightly controlled In order to prevent signal integrity problems and timing differences from becoming an issue it is preferable for each device whether memory or register to have its own clock While it is possible for each device to have a positive and negative clock generated by the FPGA this unnecessarily consumes pins that could be used elsewhere To save these pins an externally DDR SDRAM clock driver is used The clock is routed to the DDR PLL Clock Driver 027 that distributes the individual clocks to the separate DDR devices U20 U21 022 and 023 4 6 1 Clocking Methodology This section describes the DDR clocking methodology implemented in the refe
62. read the DWORD stored at the specified address repeatedly ET6000K10S User Guide www emulation com 32 INTRODUCTION THE SOFTWARE TOOLS Options 2 and 3 are useful for debugging read transactions Command Prompt aetest_wdm exe Bar Number 5 gt 8 Address Chex 81280808808 1 Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely lease select 1 esult abcdef45 it a key to continue Figure 9 Memory Read DWORD Figure 9 shows a read of the DWORD from address 0x200000 of SSRAM 4 This read retrieves the data xabcdef45 written in the Write DWORD section See Figure 8 Write Read DWORD Opt 3 Write Read DWORD allows the user to write DWORD to any location in the Base Address Registers BAR Then the function read back the data stored from the same address Akin to the previous DWORD operation all 4 gigabytes of PCI memory can be accessed Figure 10 shows a typical memory write read operation The user will be prompted once the option is chosen for the BAR to be accessed Then the memory location in hex is required AETEST will prompt the user for the number of DWORDs to write in decimal Each DWORD must be individually entered Finally the user must choose a display option 1 Following the write AETEST will read the DWORD stored at the specified address and display it 2 Same as option 1 however the transaction is repe
63. reuse it in other designs ISE s Architecture Wizards allow easy access to device features like the Digital Clock Manager and Multi Gigabit I O technology ISE also includes a tool called PACE Pinout Area Constraint Editor which includes a front end pin assignment editor a ET6000K10S User Guide www emulation com 20 INTRODUCTION VIRTEX II ISE design hierarchy browser and an area constraint editor By using PACE designers are able to observe and describe information regarding the connectivity and resource requirements of a design resource layout of a target FPGA and the mapping of the design onto the FPGA via location atea This rich mixture of design entry capabilities provides the easiest to use design environment available today for your logic design 2 1 2 Synthesis Synthesis is one of the most essential steps in your design methodology It takes your conceptual Hardware Description Language HDL design definition and generates the logical or physical representation for the targeted silicon device A state of the art synthesis engine is required to produce highly optimized results with a fast compile and turnaround time To meet this requirement the synthesis engine needs to be tightly integrated with the physical implementation tool and have the ability to proactively meet the design timing requirements by driving the placement in the physical device In addition cross probing between the physical desig
64. s are back off positions only The 48 MHz clock can be divided down in the CPLD and used as a clock source to the PWB clock network CPLD_CLKOUT The signals GPIO 0 7 are general purpose IO connections between the CPLD and the FPGA ROBO_LOCK 1 2 Indicates that the RoboClock U25 U26 PLU s are locked FPGA_MSEL 0 3 selects the configuration mode of FPGA refer to Table 9 Table 9 FPGA Configuration Modes Configuration Mode CLK Direction Master Serial Out Slave Serial In Master Select MAP Slave SelectMAP Boundary Scan Note Grayed options not supported by this design 3 3 SmartMedia The configuration bit file for the FPGA is copied to a SmartMedia card using the SmartDisk FlashPath Floppy Disk Adapter The approximate file size for each possible FPGA option is shown below in Table 10 Note that several BIT files can be put on a 32MB card ET6000K10S is shipped with two 32 megabyte 3 3V SmartMedia cards The 6000 105 support card densities up to 128MB Note Do NOT format the SmartMedia card using the default Windows file format program Smart Media cards come pre formatted from the factory and files can be deleted from the card when they no longer needed If the SmartMedia card requires formatting format the media with the program supplied by the FlashPath SmartMedia floppy adapter software Table 10 FPGA configuration file sizes Virtex II
65. state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFF mode When in MID the device will enter factory test mode JP8 A9 B9 ROBOCLOCK 2 Output Divider Function Select Controls the divider function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 4 in the datasheet JP8 A10 B10 ROBOCLOCK Z2 Output Divider Function Select Conttols the divider function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 4 in the datasheet 3 3 Powering ON the ET6000K 10S This section describes what is necessary to power up the ET6000K10S 1 Install the 6000 105 in the test PC ET6000K10S User Guide www emulation com 11 GETTING STARTED Note The PCI interface is keyed so that it is not possible to mistakenly plug the board into a 5V PCI slot Do NOT grind out the key in the PCI host slot and do NOT modify the ET6000K108 to get it to fit into the slot Emulation Technology offers a PCI Extender P N ETPCIEXT S3 that can be used to interface the 6000 105 to the PC in case no 3 3 slots are available Please refer to Emulation Technology website for more information 2 Install the SmartMedia card containing the PCI reference design into the ET6000K10S 3 Power ON the test PC and allow booting in DOS mode Note The FPGA programming will commence as soon as the ET6000K108 15 poweted on if
66. the SmartMedia card contains the necessary configuration file and bit files In general the FPGA will be programmed prior to the PCI devices being configured However some computers have a FastBoot or QuickBoot feature which speeds up the booting process of the PC These features ate incompatible with the FPGA programming sequence of the ET6000K108 as the FPGA may not be configured prior to PCI bus activity As a result 6000 105 will not be recognized by the computer Workaround the computer has FastBoot or QuickBoot or similar feature it should be disabled Otherwise a soft reset should be performed by simultaneously pressing the CTRL ALT DELETE keys after the computer has completed the Power On Self Test POST This will allow the ET6000K10S enough time to configure the FPGA so that the computer will recognize the ET6000K108 device 4 Playing with your ET6000K 10S At this point the ET6000K10S should be powered on with the PC booted in DOS mode The FPGA should also be programmed with the PCI reference design supplied by Emulation Technology The ASIC Emulator Test Utility AETEST can now be used in DOS to verify the functionality of the 6000 105 1 Ifthe AETEST utility is not yet installed refer to Appendix A for installation instructions 2 AETEST utility appropriate for the Operating System AETESTDJ EXE for Windows 95 98 ME using DPMI AETEST98 EXE
67. this option to configure the FPGA in SelectMAP mode 45 Bitstream Encryption Pro devices have an on chip decryptor using one or two sets of three keys for triple key Data Encryption Standard DES operation Xilinx software tools offer an optional encryption of the configuration data bitstream with a triple key DES ET6000K10S User Guide www emulation com 63 PROGRAMMING CONFIGURING THE HARDWARE determined by the designer The keys stored in the FPGA by JTAG instruction and retained by a battery connected to the VBATT pin when the device is not powered Pro devices can be configured with the corresponding encrypted bitstream using any of the configuration modes described previously A detailed description of how to use bitstream encryption is provided in the Lzrex II Pro Platform FPGA User Guide ET6000K10S User Guide www emulation com 64 BOARD HARDWARE Chapter Board Hardware 1 Introduction to the Board ET6000K108 Logic Emulation board provides for a comprehensive collection of peripherals to use in creating a system around the Pro FPGA Figure 24 is a block diagram of the ET6000K10S Logic Emulation board DN6000K10S BLOCK DIAGRAM ROCKET IO INTERFACES HSSDC2 HSSDC2 46 TEST HEADER 200PIN
68. to the ET6000K108 please refer to datasheet for more information The 5V rated for 25W PCI Specification 12V and 12 is obtained from the PCI fingers 11 2 Stand Alone Operation The ET6000K10S can be used standalone meaning it doesn t have to be plugged into a PCI slot An external ATX power supply is used to supply power to the ET6000K10S in this configuration refer to Figure 64 The external power supply connects to header P12 a Tyco disk drive type of connector Duting standalone operation the ET6000K10S has the following power supplies ET6000K10S User Guide ww w emulation com 140 BOARD HARDWARE 1 5V 25V 3 3V 12 The 1 5V 2 5V and 3 3V power supplies are generated from the 5V supply using the External ATX power supply Figure 64 ATX Power Supply Any ATX type power supply is adequate Emulation Technology recommends a power supply rated for 250W Note The switching regulators in the Power Supply may require and external load to operate within specifications 6000 105 may not meet the minimum load requirements Emulation Technology recommends attaching an old disk drive to one of the spate connectors 11 2 1 External Power Connector Figure 65 indicates the connections to the external power connector This header is fully polarized to prevent reverse connection and is rated for 250VAC at 13A 6000 105 User Guide www emulation com 141 BOAR
69. 00 Version 5 00 21951 lt C gt Copyright 1985 2000 Microsoft Corp gt aetest aetest Daetest_wdm exe ymbolic link is pcifftven_17df dev_166G amp subs ys_9 ab56 78 amp revu_47 38 4a750b580838 8 lt fGbida2 6ac7 4d1f 9ebB 1daf 1b7e7131 gt ound device vi df 41688 name DNGBBBK1B8S UirtexII Pro Single FPGA board i Sep 15 2003 at 11 19 42 Figure 3 ET6000K10S Board Recognition Upon recognition AETEST will notify the user which device was found In certain implementations the entire configuration space and the configuration of the BARs is sent to the screen immediate following the board recognition notification If AETEST does not recognize the 6000 105 AETEST will alert the user See Figure 4 ET6000K10S User Guide www emulation com 26 INTRODUCTION THE SOFTWARE TOOLS 32 aetest_wdm exe icrosoft Windows 2000 Version 5 00 21951 lt C gt Copyright 1985 2088 Microsoft Corp gt aetest Naetest aetest wdm exe o SP INTERFACE DEUICE available for this GUID instance ould not find open DnDeu device Figure 4 ET6000K10S Not Found AETEST will still however several ET6000K10S specific options will not be available 1 1 2 Main Menu Upon powering up and after board recognition the user must merely press a key to enter the Main Menu shown in Figure 5 AWINNT System32 cmd exe aetest wdm exe ASIC
70. 00K10S User Guide www emulation com 34 INTRODUCTION THE SOFTWARE TOOLS Command Prompt aetest_wdm exe Input bar number 98 52 Input starting address Chex and 32 bit aligned 81200808 Input number of bytes Chex and divisible by 45 88 Fill vith 8 address data 0 55555555 data address Figure 11 BAR Memory Fill As in previous function descriptions Figure 11 shows an access of SSRAM 4 Address 0x200000 is used as the starting address and 0x80 bytes are filled Data pattern option 3 is used See option Bar Memory Display for a view of the results of this transaction Bar Memory Write Opt 5 Memory Write enables to user to write DWORD s to PCI memory space All 4 gigabytes of memory space is accessible Figure 12 shows a sample transaction Once the option is chosen the user must input the BAR Number followed by the address within the specified BAR Then the user needs to input the number of DWORDs to be written in decimal The data to be written must be entered for each DWORD ET6000K10S User Guide www emulation com 35 INTRODUCTION THE SOFTWARE TOOLS 5 Command Prompt aetest_wdm exe AR ffset Dword aligned gt 0 01200020 umber of Dwords nter Dword Data xabcdef45_ Figure 12 Bar Memory Write The transaction shown in Figure 12 writes the DWORD Oxabcdef45 to address 0x200020 of SSRAM 4 See optio
71. 0K10S enables designers to implement embedded processor based applications with extreme flexibility using IP cores and ET6000K10S User Guide www emulation com 6 GETTING STARTED customized modules The Pro FPGA with its integrated PowerPC processor and powerful Rocket I O Multi Gigabit Transceivers MGT make it possible to develop highly flexible and high speed serial transceiver applications The 000 105 in its standard configuration includes 64 bit PCI PCI X interface 512K x 36 SRAM 4 16M x 16 DDR SDRAM 4 4M x 16 FLASH 2 an RS232 port for monitor and a SmartMedia interface for configuration There are 9 low skew clock sources that are distributed to the FPGA and the test header A 200 pin test header allows for connection to individual FPGA s IO banks using a custom daughter card Figure 1 shows the ET6000K10S Logic Emulation Board Figure 1 ET6000K10S LOGIC Emulation Board The 6000 105 LOGIC Emulation Kit includes the following ET6000K10S development board 2VP70 or 2VP100 in FF1704 package Note Specific speed grade parts required for various RocketIO Power operating speeds refer to Xilinx datasheet 32MB SmartMedia Card with reference design and main txt 32MB SmartMedia Card for customer use blank FlashPath Adapter to copy bit files to the SmartMedia Card s N 5 RS232 Serial cable female female 6ft ET6000K10S User Guide www emulation com 7
72. 1 11 GND J1 012 BP2N2 P2N2 3 3 1112 TST HDRAO U15 M25 11 013 P2N1 J2 8 P11 13 TST 1 U15 K26 J1 014 PZNO 2 9 11 14 TST_HDRA2 U15 AH42 1 015 BP2NX7 P2NX7 135 11 15 TST_HDRA3 U15 D26 1 016 BP2NX6 P2NX6 J3 7 P11 16 TST_HDRA4 U15 AH35 1 017 BP2NX5 P2NX5 15 9 P11 17 TST HDRA 5 U15 M24 J1 018 BP2NX4 P2NX4 J3 11 P11 18 TST_HDRAG U15 AG35 J1 019 P2NX1 J2 10 P11 19 TST HDRA7 U15 AG36 J1 020 2 2 11 11 20 TST HDRAS U15 AG38 11 021 P3NX9 J2 40 11 21 TST HDRA9 U15 AG39 11 022 No Connect P11 22 GND J1 023 P3NX8 J241 P11 23 TST HDRA10 015 634 ET6000K10S User Guide ww w emulation com 150 BOARD HARDWARE Daughter Card ET6000K10S IO Connections Connections Test Signal Name Connector Test Signal Name FPGA Pin Header Header J1 024 BP3NX5 P3NX5 15 13 P11 24 TST HDRA11 U15 C34 J1 025 BP3NX4 P3NX4 19 19 11 25 TST HDRA12 015 033 J1 026 BP3N89 P3N89 J3 17 P11 26 TST HDRA13 U15 H32 1 027 BP3N88 P3N88 3 19 P11 27 TST HDRA14 U15 32 J1 028 BP3N87 P3N87 19 21 11 28 TST HDRA15 U15 C33 1 029 BP3N86 P3N86 18 23 P11 29 TST 16 U15 C22 J1 030 BP3N83 P3N83 J3 25 P11 30 TST HDRA17 015 731 J1 031 BP3N82 P3N82 19 27 11 31 TST HDRA18 U15 G31 1 032 BP3N77 P3N77 19 29 P11 32 TST HDRA19 U15 H30 1 033 No Connect 11 33 GND J1 034 BP3N76 P3N76 3 31 P11 34 TST HDRA20 U1
73. 148 BOARD HARDWARE 12 2 3 Unbuffered The ET3000k10SD Daughter Card provides 66 unbuffered 1 0 signals including 5 single ended clock signals available on headers J5 J6 and J7 The function of these signals is position dependent 12 2 4 Buffered The ET3000k10SD Daughter Card provides 48 buffered I O signals available on headers J3 and J4 The function of these signals is position dependent U1 U2 and U3 allow for different populating options and devices can be active or passive Active The LCV162245A is used for asynchronous communication between data buses It allows data transmission from the A to the B or from the B to the A bus depending on the logic level at the direction control DIR input The output enable input be used to disable the device so that the busses are effectively isolated Passive The FST163245 bus switches are used to connect or isolate two ports without providing any current sink or source capabilities Thus they generate little or no noise of their own while providing a low resistance path for an external driver The output enable OE input can be used to disable the device so that the busses are effectively isolated 12 2 5 LVDS IO Low voltage differential signaling LVDS is a signaling method used for high speed transmission of binary data over copper It is well recognized that the benefits of balanced data transmission begin to outweigh the costs over single ended techni
74. 2 bit or a 64 bit transaction respectively Finally the parameter verify is set to TRUE when the access is to be verified If verification is not desired verify is set to FALSE ET6000K10S User Guide www emulation com 175 APPENDIX 2 12 DeviceloControl DeviceloControl is low level function Users of the ET6000K10S are advised to use higher level functions such as bat wtite dword and bar_read_dword for development 2 12 1 Description DevicelIoControl is used to send commands and receive messages from a specified device on the PCI bus in a Windows environment The QL library is based upon this function A successful DeviceloControl operation will return zero non zero value is returned if a failure occurs 2 12 2 Arguments The arguments for the DeviceIoControl method is listed in Table 51 They are listed in order Table 51 DeviceIoControl Arguments Argument Description HANDLE hDevice Handle to the device for operation DWORD dwloControlCode Control code for the operation LPVOID IpInBuffer Pointer to a buffer containing data necessary for operation DWORD nInBufferSize Specifies the size in bytes of the buffer pointed to by IpInBuffer LPVOID IpOutBuffer Pointer to a buffer that receives the operation s output data DWORD nOutBufferSize Specifies the size in bytes of the buffer pointed to by IpOutBuffer LPDWORD IpBytesReturned Pointer to a variable that receives the size in bytes of the
75. 38 P3N38 P11 56 TST 40 U15 M19 J1 057 BP3N35 P3N35 J4 13 P11 57 IST HDRA41 U15 L19 J1 058 BP3N34 P3N34 4 15 P11 58 TST 42 U15 C17 1 059 BP3N29 P3N29 4 17 P11 59 TST HDRA43 U15 C18 11 060 BP3N28 P3N28 14 19 P11 60 TST HDRA44 U15 E18 J1 061 BP3N27 P3N27 J4 21 P11 61 TST HDRA45 U15 AM33 1 062 BP3N26 P3N26 4 23 P11 62 TST_HDRA46 015 618 11 063 P3N23 10 21 P11 63 TST HDRA47 015118 1 064 P3N22 2 22 P11 64 TST HDRA48 U15 K18 1 065 BP3N19 P3N19 4 25 P11 65 TST 49 015 617 11 066 No Connect P11 66 GND 1 067 BP3N18 P3N18 4 27 P11 67 TST_HDRASO U15 AN34 11 068 BP3N15 P3N15 4 29 P11 68 TST 51 U15 AF41 11 069 BP3N14 P3N14 J4 31 P11 69 TST_HDRA52 0715147 11 070 P3N9 2 23 P11 70 TST HDRA53 U15 M17 1 071 P3N8 2 24 P11 71 TST HDRA54 915 18 1 072 BP3N7 P3N7 4 33 1172 TST HDRA55 U15 F16 11 073 BP3N6 P3N6 4 35 P11 73 TST HDRA56 015 616 1 074 BP3N3 P3N3 4 37 1174 TST HDRA57 U15 H16 1 075 BP3N2 P3N2 4 39 P11 75 TST 58 U15 C15 ET6000K10S User Guide www emulation com 152 BOARD HARDWARE Daughter Card ET6000K10S IO Connections Connections Test Signal Name Connector Test Signal Name FPGA Pin He
76. 4 A88 U15 AV32 PCI_AD37 P4 B87 15 2 PCI_AD38 PCI_AD39 P4 A86 U15 AU32 U15 AW31 PCI_AD40 15 AV31 PCI_AD41 PCI_AD42 15 AY30 15 AU31 PCI AD43 15 30 PCI_AD44 PCI_AD45 15 AV30 15 AY29 PCI AD46 15 AU30 PCI AD47 PCI AD48 15 AY28 15 AV28 PCI AD49 PCI AD50 PCI AD51 15 AU28 15 AV27 PCI AD52 15 AU27 PCI AD53 15 AY26 PCI AD54 15 27 PCI AD55 15 26 PCI_AD56 15 AU26 PCI_AD57 15 AV26 PCI_AD58 ET6000K10S User Guide www emulation com U U U U U U U U U U15 AW27 U U U U U U U U U 15 26 BOARD HARDWARE Signal Name Connector FPGA Pin PCI_AD59 P4 B71 15 AY25 PCI AD60 P4 A70 15 25 PCI AD61 P4 B69 15 AV25 PCI AD62 P4 A68 15 AU24 PCI AD63 P4 B68 15 AY24 PCI CBENO P4 A52 15 AR19 PCI CBEN1 P4 B44 15 AY18 PCI CBEN2 P4 B33 C Exp Ce eL Ee 15 AV16 PCI CBEN3 PCI 4 P4 B26 U15 AW13 U15 AW24 PCI CBEN5 U15 AR24 PCI CBENG PCI CBEN 7 15 AV24 15 AU23 PCI CLK 15 AU21 PCI DEVSELn PCI FRAMEn 15 AV17 U15 AR16 PCI GNTn 15 AV10 PCI IDSEL PCI INTAn 15 AV12 15 AU10 PCI IRDYn U15 AW16 PCI LOCKn PCI PAR U15 AW17 15 AT24 PCI_PAR64 15 AR17
77. 4 U15J6 SRAMI U15 K6 SRAM1_DQAG U15 L6 SRAM1_DQA7 U15 N6 SRAM1_DQBO 015 07 SRAM1_DQB1 U15 E7 SRAM1_DQB2 U15 F7 SRAM1_DQB3 U15 H7 SRAM1_DQB4 U15 7 SRAM1_DQB5 U15 K7 SRAM1_DQB6 01517 SRAM1_DQB7 U15 M7 SRAM1_DQCO 0157 SRAM1_DQC1 0158 SRAM1_DQC2 U15 K8 SRAM1_DQC3 01518 SRAM1_DQC4 U15 M8 SRAM1_DQC5 0158 G c c c 6000 105 User Guide www emulation com 103 BOARD HARDWARE Signal Name FPGA Pin SRAMI DQC6 U15 K9 SRAM1_DQC7 U15 L9 SRAMI DQDO U15 M9 SRAMI DQD1 U15 N9 SRAMI DQD2 U15 L10 SRAMI DQD3 U15 M10 SRAMI DQD4 U15 N10 SRAMI DQD5 U15 P10 SRAMI DQD6 U15 M11 SRAMI DQD7 U15 N11 SRAMI DQPA SRAM1_DQPB U15 R11 SRAM1_DQPC SRAM1_DQPD U15 M12 SRAM1_GWn SRAM1_LBON SRAM1_OEn SRAM1_ZZ 6000 105 User Guide www emulation com 104 BOARD HARDWARE FPGA Pin U15 W2 U15 N3 U15 P3 U15 R3 U15 T3 U15 U3 U15 U2 U15 T2 U15 R2 U U U U U U 15 P2 15 V4 15 04 15 14 15 4 15 4 U15 AA4 U15 N
78. 45PA BOTTOM OF PWB U1 U2 U3 BUFFERS OR LEVEL TRANSLATORS Figure 68 ET3000K10SD Daughter Card Block Diagram ET6000K10S User Guide www emulation com 145 BOARD HARDWARE The ET3000K10SD Daughter Card provides 16 differential pairs 48 buffered passive active I O and 66 unbuffered I O signals The ET3000K10SD Daughter Card is pictured in Figure 69 gt He fe ns 72 LE 97 9 5 9 9 AAAA 2 pte obo teh e e e ie 5 gt gt es es ee f t g s PRONG N d ie gt V 00 lt Figure 69 ET3000K10S Daughter Card ET6000K10S User Guide www emulation com 146 BOARD HARDWARE Figure 70 show the assembly drawing of the ET3000K10SD Daughter Card IDT74FST163245 devices U1 U2 U3 are used as bus switches in the passive mode and the IDT74LVC16245A U1 U2 U3 devices are used as bus transceivers in the active mode The ET3000K10SD has separate enable direction signals for each driver i i TE 8272178 Pae 5 eC wN is _ corso ars tza man CICC eT LFLiLj D 1200 WMA CORSE Figure 70 Assembly drawing for the ET3000K10SD NOTE Signals P4NX7 and P4NX6
79. 5 U15 P5 U15 T5 U15 R6 U15 T6 U15 U6 U15 W6 U15 Y6 U15 AA6 U15 P7 015 17 015 07 U15 V7 Gic gocce ccu aeu ET6000K10S User Guide www emulation com 105 BOARD HARDWARE Signal Name FPGA Pin SSRAM SRAM2_DQB2 U15 W7 09 72 SRAM2 DQB3 U15 Y7 U9 73 SRAM2_DQB4 U15 AA7 U9 74 SRAM2_DQB5 U15 P8 19 75 SRAM2 DQB6 U15 R8 U9 78 SRAM2_DQB7 U15 T8 U9 79 SRAM2 DQCO U15 U8 U92 SRAM2_DQC1 U15 V8 109 3 SRAM2_DQC2 U15 W8 U9 6 SRAM2_DQC3 U15 P9 U9 7 SRAM2 DQC4 U15 R9 1198 SRAM2_DQC5 U15 U9 09 9 SRAM2 DQC6 U15 W9 U9 12 SRAM2 DQC7 U15 Y9 U9 13 SRAM2 DQDO U15 AA9 U9 18 SRAM2 DQD1 U15 R10 19 19 SRAM2_DQD2 U15 T10 19 22 SRAM2_DQD3 U15 U10 U9 23 SRAM2 DQD4 U15 V10 U9 24 SRAM2 DQD5 U15 W10 09 25 SRAM2_DQD6 U15 V5 U9 28 SRAM2_DQD7 U15 AA10 09 29 SRAM2_DQPA U15 U11 U9 51 SRAM2_DQPB U15 V11 09 80 SRAM2_DQPC U15 W11 094 SRAM2 DQPD U15 Y11 U9 30 SRAM2_GWn U15 R5 U9 88 SRAM2_LBOn U15 N1 09 31 SRAM2_OEn U15 W5 U9 86 ET6000K10S User Guide www emulation com 106 BOARD HARDWARE Signal Name FPGA Pin SRAM2 ZZ U15 P6 SRAM3 0 U15 AD2 SRAM3 1 U15 AK1 SRAM3 A2 U15 AJ1 SRAM3 U15 AH1 SRAM3 A4 U15 AF1 SRAM3 5 U15 AE1
80. 5 C30 J1 035 BP3N75 P3N75 13 33 P11 35 21 U15 C28 J1 036 BP3N74 P3N74 3 35 11 36 TST HDRA22 U15 C29 11 037 P3N69 1242 11 37 TST HDRA23 U15 M14 1 038 P3N68 2 43 P11 38 TST HDRA24 U15 C13 J1 039 BP3N67 P3N67 3 37 P11 39 TST HDRA25 015113 J1 040 BP3N66 P3N66 13 39 P11 40 TST 015112 U U J1 041 BP3N63 P3N63 J3 41 P11 41 TST HDRA27 15 C11 J1 042 BP3N62 P3N62 J3 43 P11 42 TST_HDRA28 15 C10 J1 043 BP3N57 P3N57 J3 45 P11 43 TST HDRA29 U15 C9 11 044 11 44 GND J1 045 BP3N56 P3N56 J3 47 11 45 TST HDRA30 U15 AG32 J1 046 No Connect P11 46 TST_HDRA31 U15 AG33 J1 047 No Connect P11 47 TST HDRA32 U15 L20 J1 048 BP3N49 P3N49 j4 1 P11 48 TST HDRA33 U15 K20 J1 049 BP3N48 P3N48 4 3 P11 49 TST_HDRA34 U15 M20 ET6000K10S User Guide www emulation com 151 BOARD HARDWARE Daughter Card ET6000K10S IO Connections Connections Test Signal Name Connector Test Signal Name FPGA Pin Header Header J1 050 P3N47 12 19 11 50 TST HDRA35 U15 M21 1 051 P3N46 12 20 P11 51 TST HDRA236 U15 AK35 1 052 BP3N43 P3N43 14 5 P11 52 TST_HDRA37 U15 G19 11 053 BP3N42 P3N42 J4 7 P11 53 TST_HDRA38 U15 AK36 J1 054 BP3N39 P3N39 4 9 P11 54 TST_HDRA39 15 19 11055 No Connect P11 55 GND J1 056 BP3N
81. A fpgaF bit the line above configures FPGA with the bit file fpgaF bit end of main txt Given the above example file Verbose level is set to 2 a sanity check on the bit files will be performed and FPGA will be configured with file fpgaF bit NOTE All configuration file names have a maximum length of eight 8 characters with an additional three for the extension Do not name your configuration bit files with long file names In addition all file names should be located in the root directory of the Smart Media card no subdirectories or folders are allowed Since the main txt file controls which bit file is used to configure the FPGA the Smart Media card can contain other bit files ET6000K10S User Guide www emulation com 58 PROGRAMMING CONFIGURING THE HARDWARE 4 3 Starting SelectMAP Configuration If using the reference design SmartMedia card that came with the 6000 105 then no files need to be copied to the card Otherwise copy your bit file and main txt to the root directory of the SmartMedia card using the FlashPath floppy adapter or some other means Make sure the dipswitch 52 is set for SelectMAP as shown in Table 5 Table 5 S2 Dipswitch Configuration Settings Signal Name Pins Status MSELO Pins 1 amp 8 Closed FPGA_MSEL1 Pins 2 amp 7 Open FPGA_MSEL2 Pins amp 6 DIP_SW3 Pins 4 amp 5 Set up the serial port connection as described above in Configuring Hy
82. A4 15 3157 DDR 6A DATAS5 15 AD38 DDR DATAG 111051 DDR_6A_DATA7 15 AD32 DDR DATAS 15 AD355 DDR DATA9 15 AD34 DDR 6A DATA10 15 AC36 DDR 6A DATA11 15 4037 DDR_6A_DATA12 15 AC31 DDR_6A_DATA13 15 AC32 Ci Ci c c Ci Ci c Ci Ci G Ci ET6000K10S User Guide www emulation com 116 BOARD HARDWARE Signal Name FPGA Pin DDR_6A_DATA14 U15 AB33 DDR_6A_DATA15 U15 AB34 DDR_FPGA_6A_UDQS 15 AC34 DDR FPGA 6A 1005 15 AD36 DDR FPGA 6A UDM DDR 6A LDM 15 AG31 DDR FPGA 6A U U U15 AD39 U U 15 AD41 DDR_FPGA_6A_BA1 U15 AE42 DDR_FPGA_6A_CASn DDR_FPGA_6A_CKE U15 AB40 U15 AB36 DDR_FPGA_6A_CSn U15 AC39 DDR FPGA 6A RASn DDR FPGA 6A WEn U15 AB37 U15 AB39 DDR 6B ADDO U15 AT40 DDR 6B ADDI1 U15 AV42 DDR 6B ADD2 U15 AV40 DDR_6B_ADD3 U15 AWA1 DDR 6B ADD4 U15 AW40 DDR_6B_ADD5 U15 AW42 DDR_6B_ADD6 U15 AV41 DDR_6B_ADD7 U15 AU39 DDR_6B_ADD8 U15 AU41 DDR_6B_ADD9 U15 AU42 DDR_6B_ADD10 U15 AT39 DDR_6B_ADD11 U15 AT42 DDR_6B_ADD12 U15 AN42 DDR_6B
83. BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 unsigned long byte offset Address Number of bytes to 0 0 bytes in mem space offset data word data wotd of data for the write 0 0000 operation 16 bits typedef unsigned char word 2 2 3 Return Values A successful function call will return zero 2 2 4 Notes The source code for bar write word is portable to each of the operating systems intended for AE TEST usage ET6000K10S User Guide www emulation com 165 APPENDIX 2 3 bar write dword bar write dword is a high level function C function which is recommended for development by users of the ET6000K10S 2 3 1 Description bar write dword allows users of the ET6000K10S to write a dwotd of data to any location in the Base Address Registers BARs of PCI memory 4 gigabytes of PCI memory is available for access 2 3 2 Arguments The arguments for write dword are shown in Table 42 They are listed in order Table 42 write dword Arguments Argument Description Possible Values unsigned long barnum BAR number to be accessed BARO 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 BAR5 5 unsigned long byte offset Address Number of bytes to 0 0 bytes in mem space offset data dword data dword of data for the write 0x00000000 Oxffffffff operation 32 bits typedef unsigned char dword
84. Combined Trace Debug Connector Pinout Figure 61 VirtexII Pro PCI VCCO Regulator Figure 62 PCI Edge Connector Figure 63 M66EN and Jumper Figure 64 ATX Power Supply Figure 65 External Power Connection Figure 66 Test Header Figure 67 Test Header Pin Numbering Figure 68 ET3000K10SD Daughter Card Block Diagram Figure 69 000 105 Daughter Figure 70 Assembly drawing for the ET3000K10SD 46 List of Tables Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Ta Ta Ta Ta Ta Ta Ta Ta Ta Ta Ta Ta e 1 Jumper Description 2 Menu Options e 3 PCI Menu Options e 4 Daughter Board Options 5 52 Dipswitch Configuration Setting 6 HyperTerminal Main Menu Options 7 HyperTerminal Interactive Configuration Menu Options 8 Sanity Check Command Line Options 9 FPGA Configuration Modes e 10 FPGA configuration file sizes 11 Connection between CPLD MCU 12 FPGA JTAG connection to CPLD e 13 Clocking inputs to the FPGA 14 Clock Source e 15 RoboClock Configuration Signals e 16 Connection between
85. D JP5 A3 CLOCKA Clock signal from oscillator X4 JP5 A1 CLOCKB Clock signal from oscillator X5 JP5 A5 PLL1B Secondary clock input to RoboClock JP5 B4 differential pair with PLLIBN PLLIBN Secondary clock input to RoboClock JP5 B5 differential pair with PLL1B PLL2B Secondary clock input to RoboClock JP5 B1 differential pair with PLL2BN PLL2BN Secondary clock input to RoboClock JP5 B2 ET6000K10S User Guide www emulation com 78 BOARD HARDWARE Description Connector differential pair with PLL2BN Provides a ground reference for signals in the ribbon cable 4 2 1 Clock Source J umper Header Figure 35 shows JP5 the clock source header connector used to select between different clock soutces CLOCKA CLOCKB Clock Source Jumpers Figure 35 Clock Source Jumper 4 3 External Clocks The clock source jumper allows the user a simple means to attach external clocks to the clock grid The user can attach 10 pin ribbon cable to JP5B C which allows for connection the differential pair inputs of both RoboClocks JP5C ground pins for signal integrity These signals are described in Table 14 Both differential pairs provide some flexibility The user can bring a single 3 3V TTL input It can be attached to either input However the other input must be left open The user can provide a differential clock input to the pair to the RoboClocks
86. D HARDWARE Figure 65 External Power Connection Note Header P12 is not hot plug able Do not attach power while power supply is ON 11 2 2 Power Monitors Two triple supply monitors 01 U2 are used to monitor the 1 5V 2 5V and 3 3V supplies for more information on these devices please refer to the datasheet for the LT1326 from Linear Technology These power supply monitors also provide a push button reset input that is utilized to reset the various sub circuits of the ET6000K108 After power up PWRRSTn remains asserted for approximately 200ms 11 2 3 Power Indicators There are six LED s on ET6000K10S used to indicates the presence of the following voltage sources refer to Table 37 Table 37 Voltage Indicators Voltage Source 2 5V 3 0V used for PCI only 3 3V 5V 12V 12V 12 Test Header amp Daughter Card Connections 12 1 Test Header The ET6000K10S offers 200 pin test header P11 that allows the user connection to discrete FPGA pins refer to Figure 66 6000 105 User Guide www emulation com 142 BOARD HARDWARE P11 412V 1 101 GND 2 102 GND 2 5V 103 1 5V 41 104 GND 2 5V 5 L105 3 3V 6 106 _ 7 107 GND GND 8 108 GND 3 3V 91 109 GND 5 10 10 GND GND ml 5 79 TST ADRAD 12
87. EMULATION TECHNOLOGY LOGIC Emulation Source User Guide ET6000K10S LOGIC EMULATION SOURCE ET6000K 10S User Manual Version 1 1 Emulation Technology EMULATION TECHNOLOGY INC Worldwide Headquarters 2344 Walsh Avenue Building Santa Clara CA 95051 1301 U S A Tel 408 982 0660 or 1 800 ADAPTER 1 800 232 7837 Fax 408 982 0664 support emulation com Table of Contents ABOUT THIS MANUAL 1 1 MANUAL CONTENTS 4 2 ADDITIONAL RESOURCES 41 2 CONVENTIONS 55 3 1 M n 22 Online Document 4 RELEVANT INFORMATION RH 4 GETTING STARTED He 6 1 PRECAUTION DC 6 2 THEET6000KI0S LOGIC EMULATION KIT arora eea E ee e POR E ETE 6 3 INSTALLATION INSTRUCTIONS RUN RA YE 8 3 1 Jumper Setup 27 Jumper Description enn rii RH EIFE e 9 3 94 Powering ON the ETO000KIOS Ce 11 4 PLAYING WITH YOUR ETO000K10S EE V EAT EFE 12 INTRODUCTION TO VIRTEX II PRO AND IS Evsccsccscaciosenssccvuessssctsnstescsevesdiesenssccsuevessctsucsecttesctsesensvecsuevss econssdevensesyssdoacesydcouevess T 16 1
88. Emulator PCI Controller Driver 49 1 PCI Menu 2 Memory Menu 32 Flash Menu 5 Daughter Board Menu Quit BASE ADDRESS 1 b3aie 2 B 69000008 88800008 5 Please select option m Figure 5 Main Menu The possible Main Menu options and a description can be found in Table 2 ET6000K10S User Guide www emulation com 27 INTRODUCTION THE SOFTWARE TOOLS Function Name Table 2 Main Menu Options Description Read FPGA F Revision Displays the revision of the reference design in FPGA F PCI Menu Takes User to PCI Menu Memory Menu Takes User to Memory Menu Daughter Board Menu 1 1 3 Menu Upon entering PCI Menu from the Menu AETEST will output a screen similar to the one shown in Figure 6 Take User to Daughter Board Menu S ICNWINNTSystem32cmd exe aetest_wdm exe ASIC Emulator PCI Controller Driver v4 1 gt Display Vendor and Device ID M gt Main Menu 9 gt Quit PCI bbaie888 3 66980000 Please select option BASE ADDRESS Figure 6 PCI Menu The possible PCI Menu options and a description can be found in Table 3 Table 3 PCI Menu Options Option Function Name Description Set PCI Device Number Sets a PCI device number of your choice as the active device hex input Available device numbers is listed to help t
89. FiberChannel InfiniBand and XAUI In addition the channel bonding feature ageregates multiple channels allowing for even higher data transfer rates For additional information on RocketIO transceivers see RocketlO Transceiver User Guide at http www xilinx com publications products v2pro userguide ug024 pdf The ET6000K10S board has 10 RocketIO transceivers available on the top side of the FPGA These 10 transceivers implement three different MGT interfaces on boatd ET6000K10S User Guide ww w emulation com 121 BOARD HARDWARE including four Gigabit Ethernet Fiber channels two InfiniBand channels and two Serial channels one configured as a Serial ATA Host the other configured as a Serial ATA Device peripheral and two SMA interfaces 71 Gigabit Ethernet Fiber Gigabit Ethernet fiber represents a marked evolution over copper Gigabit Ethernet allowing signals to be transmitted 500 meters multimode or as much as 10km singlemode In addition it provides for high tolerance of EMI and in turn produces little EMI 711 Stratos Lightwave Quad Fiber Transceiver J 3 While the Virtex II Pro can deliver the speeds required by Gigabit Ethernet it is not capable of transmitting or receiving optical signals directly This capability is added by the inclusion of Stratos Lightwave R14K ST11 Quad Gigabit Ethernet Transceivers The 14 5 11 is a 4 port multimode transceiver capable of transmitting approximately 550 me
90. Flexible frequency synthesis High resolution phase shifting o 16 global clock multiplexer buffers in all parts e Active Interconnect technology Fourth generation segmented routing structure Fast predictable routing delay independent of fanout o Deep sub micron noise immunity benefits Select I O Ultra technology Upto 852 user I Os Twenty two single ended standards and five differential standards o Programmable LVITL and LVCMOS sink source current 2 mA to 24 mA per o Digitally Controlled Impedance DCI I O on chip termination resistors for single ended I O standards PCI support 1 Differential signaling 840 Mb s Low Voltage Differential Signaling I O LVDS with current mode drivers Bus LVDS I O HypetTransport LDT I O with current driver buffers Built in DDR input and output registers Proprietary high performance technology for communications between Xilinx devices High bandwidth data path Double Data Rate DDR link Web based HDL generation methodology SRAM based in system configuration Fast SelectMAP configuration ET6000K10S User Guide www emulation com 19 INTRODUCTION VIRTEX II AAND ISE o Triple Data Encryption Standard DES security option bitstream encryption IEEEI1522 support Partial reconfiguration Unlimited reprogrammability o Readback capability Supported by Xilinx Foundation M and Alliance
91. Full Memory Test tests each of the four SSRAMs and the PRO BlockRAM on the 6000 105 Memory Tests On FPGA Block Memory Opt n Tests entire FPGA BlockRAM Bar Memory Range Test Opt p Memory Range test is a generic memory test It verifies the functionality of a user selectable range of PCI memory First it prompts the user for a BAR number a starting address offset a DWORD count and the number of iterations The user is also prompted if the program should stop if error occurs or if the program should display any errors that occur This allows for maximum flexibility when debugging a design with an oscilloscope or debugging any memories or memory locations on your PCI bus The memory test is very complete performing a write then a read to every location a read from every location and then a read wtite read test to every location All other memory test options listed in the memory menu are based on this generic memory test function WINNT System32 cmd exe aetest_wdm exe M gt Main Menu Q gt Quit PCI BASE ADDRESS 8 1 1 b3aie 00 2 68880008 3 68000008 4 66660000 5 66000000 Please select option p lemory test of a range within bar ar 68 5578 tarting address offset byte addr 8x8012080008 word count 8x28 lumber of Iterations for endless gt 1 top if an error occurs Cy or isplay any errors that occur or 2 oing write read all re
92. GA_SYNTH rev_1 50001 06 edf Es Copy Input Design to the Project directory r Selectthe Constraint File for the Project Constraint File Budice Jack DiniGroup 50001 06 Source fpgac Copy Constraint file to the Project directory Figure 19 Input File Select the device and the design flow for the project The user must specify a project name and location The correct property values must be selected refer to Figure 20 SI j x Select the Device and Design Flow for the Project Property Name Value Device Family Virtex2P Device 2 0 Package 1704 Speed Grade 5 Top Level Module Synthesis Tool Simulator Other Generated Simulation Lanquage lt Back Help Figure 20 New Project Dialog Box The Project Navigator will create a new project with the required files Emulation Technology prefers to use Synplicity s Synplify for synthesis which is recommended for the user also Consequently edif files are used in the design flow described here ET6000K10S User Guide www emulation com 53 PROGRAMMING CONFIGURING THE HARDWARE Selecting the edif file in the Module View window the user s Project Navigator box should resemble Figure 21 oject Navigator ON5000106 DN5000106 npt Edt Wew Project Source Erocess Window ear
93. GETTING STARTED IDC 10 pin to DB 9 pin adaptor cable Jumpers 0 1 x10 Documentation Reference CD Optional items that support development efforts not provided Xilinx ISE software JTAG cable Coax loop back cables Daughter Card ATAVRISP kit for MCU reprogramming 3 Installation Instructions 3 1 Jumper Setup Figure 2 indicates the factory jumper configuration of the ET6000K10S ET6000K10S User Guide www emulation com GETTING STARTED 1 Ct En sanas sesse N o 9 o e 9 gt Nee ee 6 AS N A N 5 FBFO1 FBDS01 e FBF02 502 80512 OSCA BZAA Osce 1 C1 Fst ZZA 7944 ZZA RBCFO RBCF1 50 CDS1 lt RBDF1 0050 0051 N SSNS f ii 2 Figure 2 Default Jumper Setup 3 2 J umper Description Table 1 describes the functionality of the installed jumpers on the ET6000K10S Table 1 Jumper Description Jumper Signal Description Installed Name JP1 1 2 PRSNT1 Configured for 25W power setting JP2 1 2 PCI interface configured fo
94. Itypedef int buffer handle 2 8 3 Return Values A successful function call will return zero If 2 is returned the DPMI implementation of AETEST is not being used See Notes 2 8 4 Notes The dma buffer free code is wtitten for use in the DPMI DOS implementation of AETEST ET6000K10S User Guide www emulation com 171 APPENDIX 2 9 dma_write_dword dma_write_dword is a high level function C function which is recommended for development by users of the ET6000K10S 2 9 1 Description dma_write_dword allows users of ET6000K10S to write dword of data to any byte aligned location in a DMA buffer 2 9 2 Arguments The arguments for dma write dword are shown in Table 48 They are listed in order Table 48 write dword Arguments Argument Desctiption dma buffer handle hndl Handle for buffer int offset Offset in bytes of the write location in the DMA buffer dword data dword 32 bit of data for the write operation Itypedef int buffer handle typedef unsigned char dword 2 9 3 Return Values successful function call will return zero If 2 is returned the DPMI implementation of AETEST 15 not being used See Notes 2 9 4 Notes The dma write dword code is wtitten for use in the DPMI DOS implementation of AETEST ET6000K10S User Guide www emulation com 172 APPENDIX 2 10 dma read dword read dword is a high level function C function w
95. L33 signals and the SSRAMs are LVCMOS25 The CLK interface is level translated by the flowing circuit in Figure 53 3 3 Figure 53 Clock Level Translation ET6000K10S User Guide www emulation com 101 BOARD HARDWARE 6 2 3 SRAM Termination No termination is necessary but the option to use DCI is available on all signals 6 2 4 SSRAM Connection to the FPGA The SSRAM memory components are connected to the FPGA on Bank 2 and Bank 3 as listed in Table 22 VCCO of the IO banks are connected to 2 5V Table 22 Connection between FPGA and SRAM s Signal Name FPGA Pin SRAM1_A0 01514 1 U15 K1 SRAMI A2 0151 SRAM1_A3 015 61 SRAMI A4 U15 F1 SRAMI A5 U15 E1 SRAM1_A6 U15 F3 SRAMI A7 U15 G3 SRAMI U15 H3 SRAMI A9 U15 K3 SRAMI A10 U15 H2 SRAMI A11 U15J2 SRAMI A12 U15 K2 SRAMI A13 U15 L2 SRAMI A14 U15 M2 SRAMI A15 015 03 SRAMI A16 U15 E3 SRAMI A17 U15 G2 SRAMI A18 U15 F2 SRAMI A19 U15 E2 SRAMI A20 U15 D2 SRAM1_ADSCn U15 F4 SRAM1_ADSPn U15 M3 Co 2 GL GP GC ET6000K10S User Guide www emulation com 102 BOARD HARDWARE Signal Name FPGA Pin SRAM1_ADVn 01513 SRAM1_BWAn U15 G4 SRAM1_BWBn U15 H4 SRAM1_BWCn 0154 SRAM1_BWDn 01514 SRAM1_BWEn U15 M4 SRAM1_CEn U15 H5 SRAMI DQAO U15 D6 SRAM1_DQA1 U15 E6 SRAM1_DQA2 U15 G6 SRAM1_DQA3 U15 H6 SRAM1_DQA
96. N O E ENA N 160 1 APPENDIX AETEST INSTALLATION INSTRUCTIONS 160 1 1 DOS and Windows 95 98 ME using 160 1 2 Wirndows 9S ME usins a VXD driver ertet ie e ig Ae p rn e aep TR ears 160 L3 Windows 2000 161 1 4 Windows 162 1 5 Linux 1 6 Solaris 2 APPENDIX B BASIC EUNCTIONS 164 2 1 write byte 2 1 1 p 164 2 6 read dword 2 8 buffer free 2 12 DeviceloControl 2 1 2 164 2 13 Return 164 2 14 lr T 164 2 2 bar write word 165 2 2 1 Description 165 2 2 2 Arguments 165 2 2 3 Return H T 165 2 2 4 Eh 165 2 3 write 2 31 borne 2 3 2 EE 2 3 3 Return Values 2 3 4 DS ORES 166 2 4 0271 E 167 2 4 1 Description 2 4 2 Arguments 167 2 4 3 Return Values 167 2 4 4 Ur t
97. Overlapped is ignored The operation must complete before DeviceloControl will return ET6000K10S User Guide www emulation com 177 APPENDIX 2 12 5 Derived Functions The following functions ate based on DeviceloControl ConfigRead ControlRead rite Read BAR Writ OL MapBufferAddr QL UnMapBufferAddr GetBufferSize Red OL Writ BAR BAR ResetDevice ET6000K10S User Guide www emulation com 178 179
98. PMA brefclk brefclk2 91024 35 091802 Figure 40 REFCLK BREFCI K Selection Logic 4 8 2 Connections between FPGA and DDR PLL Clock Buffer The connection between the FPGA and the external oscillators ate shown in Table 18 Table 18 Connections between FPGA and Rocket IO Oscillators Signal Name FPGA Pin OSCILLATOR ET6000K10S User Guide www emulation com 89 BOARD HARDWARE 4 8 3 Reference Clocks A high degree of accuracy is required from the reference clocks X2 X3 For this reason it is required that one of the oscillators listed in this section be used The ET6000K10S is shipped with the Pletronics parts Note the PCB footprint was designed to take either Epson EG 2121CA 2 5V LVPECL Outputs See the Epson Electronics America website for detailed information The circuit shown in Figure 41 must be used to interface the oscillator s LVPECL outputs to the LVDS inputs of the transceiver reference clock Alternatively the LVDS_25_DCI input buffer may be used to terminate the signals with on chip termination as shown in Figure 42 EG2121CA 2 5V PECL 1000 105024 025a 121102 Figure 41 LVPECL Reference Clock Oscillator Interface EG2121CA 2 5V PECL 1000 103024 0250 112202 Figure 42 LVPECL Reference Clock Oscillator Interface DCI Pletronics LV1145B LVDS Outputs See the Pletronics website for detailed information The circuit shown in Figure 43 must be used to interface the o
99. Pro ET6000K10S User Guide ww w emulation com 73 BOARD HARDWARE Device Length bits XC2VP70 25 604 096 XC2VP100 33 645 312 SmartMedia Cards are available from www computers4sure com 3 3 1 SmartMedia Connector Figure 31 shows J1 the SmartMedia connector used to download the configuration files to the FPGA gt SmartMedia Figure 31 SmartMedia Connector Note Do not press down on the top of the SmartMedia connector J1 if a SmartMedia card is not installed The metal case shorts 3 3V to GND 3 3 2 SmartMedia connection to CPLD MCU Table 11 shows the connection between the SmartMedia connector and the CPLD MCU Table 11 Connection between CPLD MCU CPLD MPU Connector U5 26 11 6 5 27 5 28 1 8 5 31 119 5 33 71 13 5 34 114 U U U U U U 1 15 ET6000K10S User Guide www emulation com 74 BOARD HARDWARE Signal Name CPLD MPU Connector SM_D7 05 39 J1 16 SM_CLE 5 20 1 2 SM_ALE 521 11 3 SM_WEn 5 22 1 4 SM_RDYBUSYn 5 40 14 19 SM_WPn 5 23 11 5 SM_CEn 5 24 1121 SM_REn 5 25 11 20 SM_CDn 048 iz 3 4 Boundary Scan J TAG IEEE 1532 Mode boundaty scan mode dedicated pins are used for configuring the Virtex II Pro device The configuration is done entirely through the IEEE 1149 1 Test Access Port The FPGA JTAG interfaces to IO on the CPLD This al
100. TDI o Figure 27 MCU JTAG Connector 3 1 3 MCU Programming Connector programming cable for the ATmegal128L is shipped with the ET6000K10S and mates to the MCU programming header P1 as shown in Figure 28 The programming header is used to download the files to the MCU using the AVR In System Programming Cable BRXD 1 3 PWRRSTn 5 SCK 7 9 BTXD Figure 28 MCU Programming Connector 3 1 4 RS232 Interface An RS232 serial port P5 is provided for low speed communication with the MCU The RS 232 standard specifies output voltage levels between 5 to 15 Volts for logical 1 and 5 to 15 Volts for logical 0 Input must be compatible with voltages in the range of 3V to 15V for logical 1 and 3V to 15V for logical 0 This ensures data bits are read correctly even at maximum cable lengths between DTE and DCE specified as 50 feet The RS 232 standatd has two primary modes of operation Data Terminal Equipment D TE and Data Communication Equipment DCE These can be thought of as host or PC for and as peripheral for DCE The ET6000K108 operates in the DCE mode only Figure 29 shows the implementation of the serial port on the 00 105 ET6000K10S User Guide ww w emulation com 70 BOARD HARDWARE BTXD 3 3V 43 3V UG P5 TXD 1 2 RXD 4 5 75 10K PWRRST EN FORCEOFF INVALID C2 0 1uF Fc V C1
101. U15 G38 DDR 7A ADDI1 U15 F40 DDR ADD12 U15 E42 DDR 7A ADD13 U15 F36 DDR 7A DATAO U15 N35 DDR U15 N36 DDR 7A DATA2 U15 M38 DDR DATA U15 M39 DDR DATA4 U15 M33 DDR DATA5 U15 M34 U U c Ci Ci c Ci DDR 7A DATAG 15 M31 DDR 7A 15 M32 DDR 7A DATAS U15 L34 DDR 7A DATA9 U15 L35 DDR 7A DATA10 U15 K36 DDR 7A DATA11 U15 K35 DDR_7A_DATA12 U15 K38 DDR_7A_DATA13 U15 K37 DDR_7A_DATA14 115 59 DDR 7A DATA15 11538 DDR_FPGA_7A_UDQS U15 K34 DDR_FPGA_7A_LDQS U15 M41 DDR_FPGA_7A_UDM U15 H36 Gye ea eum ET6000K10S User Guide www emulation com 119 BOARD HARDWARE Signal Name FPGA Pin DDR_FPGA_7A_LDM U15 L42 DDR FPGA 7A BAO 1715 239 DDR_FPGA_7A_BA1 U15 F41 DDR_FPGA_7A_CASn 15 D41 DDR_FPGA_7A_CKE 15 E40 DDR_FPGA_7A_CSn 15 41 DDR_FPGA_7A_RASn 15 D42 DDR_FPGA_7A_WEn 15 D40 DDR 7B ADDO 15 V39 DDR 7B 1 15 V41 DDR 7B ADD2 15 W37 DDR 7B ADD3 15 W41 DDR 7B ADD4 15 W40 DDR 7B ADD5 15 W39 DDR_7B_ADD6 15 W38 DDR_7B_ADD7 15 V38 DDR_7B_ADD8 15041 DDR_7B_ADD9 15 040 DDR_7B_ADD10 15 039 DDR_7B_ADD11 15 038 DDR_7B_ADD12 15 T38 DDR_7B_ADD13 15 R40 DDR_7B_DATAO U15 AA33 DDR 7B DATA1 U15 AA34 DDR 7B DATA2 15 Y31 DDR 7B DATA3 15 332 DDR 7B DATA4 15 156 DDR_7B_DATA5 1557 DDR 7B 1 29 c
102. _ADD13 U15 AM37 hE es eu se EIE re Gn ea DDR_6B_DATAO U15 AR37 DDR 6B DATA1 ET6000K10S User Guide U15 A138 ww w emulation com 117 BOARD HARDWARE Signal Name FPGA Pin DDR_6B_DATA2 U15 AP36 DDR 6B DATA3 U15 AP37 DDR 6B DATA4 U15 AP35 DDR 6B DATAS 15 AR36 DDR 6B DATAG 15 AN35 DDR 6B 15 AN36 DDR 6B DATAS 15 34 DDR_6B_DATA9 15 AM35 DDR 6B DATA10 15 AL33 DDR 68 DATA11 15 AL34 DDR_6B_DATA12 15 AL38 DDR_6B_DATA13 15 AL39 DDR_6B_DATA14 15 AL31 DDR 6B DATA15 15 AL32 DDR 68 12005 15 AL36 DDR 68 1005 15 AP39 DDR 68 UDM 15 ALA0 DDR FPGA 6B LDM 15 AN37 DDR_FPGA_6B_BAO 15 41 DDR FPGA 6B BA1 015 1 DDR_FPGA_6B_CASn U15 AM41 DDR_FPGA_6B_CKE U15 AM39 DDR_FPGA_6B_CSn U15 AM38 DDR_FPGA_6B_RASn U15 AN40 DDR FPGA 6B WEn 015 2 DDR 7A ADDO 015 641 DDR_7A_ADD1 U15 H38 DDR_7A_ADD2 U15 H40 DDR 7A ADD3 U15J41 U U U U U U U U U U U U U U U U CX ec se ue 6000 105 User Guide www emulation com 118 BOARD HARDWARE Signal Name FPGA Pin DDR_7A_ADD4 01542 DDR_7A_ADD5 U15 H41 DDR_7A_ADD6 U15 H39 DDR_7A_ADD7 U15 G42 DDR 7A ADDS U15 G39 DDR 7A ADD9 U15 F42 DDR 7A ADD10
103. _ADDR7 015 26 FLASHO_ADDR8 U15 F27 FLASHO_ADDR9 U15 M27 FLASHO_ADDR10 U15 G30 FLASHO_ADDR11 U15 E28 FLASHO_ADDR12 015126 FLASHO_ADDR13 U15 H27 FLASHO_ADDR14 U15 F28 FLASHO ADDR15 U15 30 FLASHO ADDR16 U15 K30 FLASHO ADDR17 U15 M26 FLASHO ADDR18 U15 27 FLASHO ADDR19 U15 M29 FLASHO ADDR20 U15 D30 FLASHO ADDR21 U15 D27 U U FLASHO DATAO 15 K31 FLASHO DATA1 15 M30 FLASHO DATA2 U15 E33 FLASHO DATA3 U15 E51 FLASHO DATA4 U15 F31 FLASHO DATA5 U15 F33 FLASHO DATAG 015 633 FLASHO DATA7 U15 E34 Cre eue m ET6000K10S User Guide ww w emulation com 95 BOARD HARDWARE Signal Name FPGA Pin FLASHO DATAS U15 L30 FLASHO DATA9 15 D31 15 L51 U FLASHO DATA10 U FLASHO DATA11 U15 B32 FLASHO DATA12 U15 F32 FLASHO DATA13 U15 D34 U U U U FLASHO DATA14 15 H33 FLASHO DATA15 15 H31 FLASHO CEn 15 G27 FLASHO OEn 15 amp 52 FLASHO WEn U15 33 FLASHO WPn U15 M28 FLASH1 ADDRO U15 D9 FLASH1 ADDR1 U15 D10 FLASH1 ADDR2 U15 E11 FLASH1 ADDR3 015 512 FLASH1 ADDR4 1715 12 FLASH1 ADDR5 U15 E9 FLASH1 ADDR6 UT5 FT FLASH1 ADDRT7 U15 F9 FLASH1_ADDR8 U15 E10 FLASH1_ADDR9 U15 H11 FLASH1_ADDR10 U15 K12 FLASH1_ADDR11 U15 J11 FLASH1_ADDR12 U15 J17 FLASH1_ADDR13 U15 G10 FLASH1_ADDR14 U15 D12 FLASH1_ADDR15 U15 D13 FLASH1_ADDR16 U15 E13
104. able 46 dma buffer allocate Arguments Argument Desctiption buffer handle hndl Pointer to a handle int for the allocated DMA buffer int nbytes Number of bytes of memory to allocate int phy addr Pointer to an int specifying the physical address of the DMA buffer Itypedef int buffer handle 2 7 3 Return Values successful function call will return zero An error will return a non zero value If 1 is returned the allocation failed If 2 15 returned the DPMI implementation of AETEST is not being used See Notes An integer indicating the handle for DMA buffer is placed in the variable location pointed to by An integer indicating the physical address of the DMA buffer is placed in the variable location pointed to by phy_adar 2 7 4 Notes The dma buffer allocate code is written for use in the DPMI DOS implementation of AETEST ET6000K10S User Guide www emulation com 170 APPENDIX 2 8 dma_buffer free dma_buffer_free is a high level function C function which is recommended for development by users of the 00 105 2 8 1 Description dma_buffer_free allows users of the ET6000K10S to free memory associated with a previously allocated DMA buffer 2 8 2 Arguments The argument s for dma buffer free are shown in Table 47 They are listed in order Table 47 buffer free Arguments Argument Desctiption dma buffer handle hndl Handle for a DMA buffer
105. ace supports the attachment of external debug tools such as the ChipScope Integrated Logic Analyzer a powerful tool providing logic analyzer capabilities for signals inside an FPGA without the need for expensive external instrumentation Using the JTAG test access port a debug tool can single step the processor and examine the internal processor state to facilitate software debugging This capability complies with the IEEE 1149 1 specification for vendor specific extensions and is therefore compatible with standard JTAG hardware for boundary scan system testing 8 1 CPU Debug External debug mode can be used to alter normal program execution It provides the ability to debug system hardware as well as software The mode supports multiple functions starting and stopping the processor single stepping instruction execution setting breakpoints as well as monitoring processor status Access to processor resources is provided through the CPU Debug port The PPC405 JTAG Joint Test Action Group Debug port complies with IEEE standard 1149 1 1990 IEEE Standard Test Access Port and Boundary Scan ET6000K10S User Guide ww w emulation com 127 BOARD HARDWARE Architecture This standard describes a method for accessing internal chip resources using a four signal or five signal interface The PPC405 JTAG Debug port supports scan based board testing and is further enhanced to support the attachment of debug tools These enhancements comply wit
106. ad all data cpu_addr gt oing read write read all data cpu_addr gt done with memory test ress key Cpossibly twice Figure 14 Bar Memory Range Test Bar Memory Address Data Bitwise Test Opt k Same as BAR Memory Range Test except this tests the data bits one at a time ET6000K10S User Guide www emulation com 38 INTRODUCTION THE SOFTWARE TOOLS C WINNT System32 cmd exe aetest_wdm exe full memory test Cincluding blockram gt memory test on FPGA block memory bar memory range test bar memory address data bitwise test Main Menu 9 gt Quit PCI BASE ADDRESS 1 1 1 2 5 12717171477 68800008 4 66688000 6860008 3 Please select option k emory test of a range address data within a bar ar lt 0 5 0 tarting address offset byte addr 6x61260000 word count of memory range Bx28 umber of Iterations for endless gt 1 top if an error occurs Cy or isplay any errors that occur or one with memory test ress a key Cpossibly twice Figure 15 Bar Memory Address Data Bitwise Test 1 1 5 Flash Menu Upon entering the Flash Menu from the Main Menu AETEST will output a screen similar to the one shown in Figure 16 WINNT System32 cmd exe aetest_wdm exe ASIC Emulator Flash Programming 949 Flashi Display Flash2 Display Flashi Erase amp Program Test tests xi bytes Flash2 Era
107. ad dword Arguments 50 pci rdwr Arguments e 51 DeviceloControl Arguments ABOUT THIS MANUAL Chapter About This Manual This User Guide accompanies the ET6000K10S LOGIC Emulation Board For specific information regarding the Virtex II Pro parts please reference the datasheet 1 Manual Contents This manual contains the following chapters Chapter 1 Getting Started contains information on the contents of the LOGIC Emulation Kit Chapter 2 Introduction to the Virtex II and ISE an overview of the Vitex II platform and the software features Chapter 3 Introduction to the Software Tools information regarding test software Chapter 4 Programming Configuring the Hardware step by step information on programming and configuring the hardware Chapter 5 Board Hardware detailed description of board hardware 2 Additional Resources For additional information go to http www emulation com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Description URL User Manual This is the main source of technical information The manual should contain most of the answers to your questions ET6000K10S User Guide www emulation com 1 ABOUT THIS MANUAL Resource Description URL Web Site The web page will contain the latest manual application n
108. ader Header J1 076 BP4N27 P4N27 J4 41 P11 76 TST HDRA59 U15 C14 J1 077 No Connect P11 77 GND 1 078 BP4N26 P4N26 4 43 P11 78 TST_HDRAGO U15 P12 J1 079 BP4N21 P4N21 4 45 P11 79 TST 61 915 812 1 080 BP4N20 P4N20 4 47 P11 80 TST 2 015 05 1 081 No Connect P11 81 TST 63 U15 T12 1 082 No Connect P11 82 TST_HDRA64 015 012 J1 083 No Connect P11 83 HDRA65 U15 V12 1 084 No Connect P11 84 TST HDRA66 U15 W12 11 085 No Connect P11 85 TST HDRAG7 U15 Y12 11 086 No Connect P11 86 TST HDRAG8 U15 AA12 11 087 No Connect P11 87 TST HDRAO9 U15 AB12 1 088 No Connect P11 88 GND J1 089 No Connect P11 89 TST HDRA70 U15 N12 J1 090 No Connect P11 90 TST HDRAT71 U15 K5 1 091 No Connect P11 91 TST_HDRA72 U15J5 11 092 No Connect 11 92 TST HDRA73 U15 AK11 J1 093 No Connect P11 93 1 5V J1 094 No Connect P11 94 TST HDRA74 U15 AK12 J1 095 P4NX7 J7 45 P11 95 TST_HDRA75 U15 AK5 J1 096 P4NX6 J7 47 P11 96 TST HDRA76 U15 AL12 J1 097 No Connect P11 97 TST HDRAT7 U15 AU4 11 098 No Connect P11 98 ISE 78 U15 A 12 J1 099 No Connect P11 99 GND J1 100 No Connect P11 100 12V J1 101 No Connect P11 101 GND ET6000K10S User Guide www emulation com 153 BOARD HARDWARE Daughter Card ET6000K10S IO Connections Connections Test Signal Name Connec
109. ain txt to get the name place of main txt of the bit file to be used for configuration as well as options for the configuration process However a user can put several files that follow the format for main txt on the SmartMedia card that contain different options for the configuration process By selecting the main menu option 4 the user can select a file from a list of files that should be used in place of main txt After selecting a new file to use in place of main txt the user should select Main Menu option 1 to configure the FPGA s according to this new file If the power is turned off or the reset button S1 is pressed the configuration file is changed back to the default main txt List files on This option prints out a list of all the files found on the SmartMedia SmartMedia card Select FPGA to This option allows the user to select an FPGA to configure via program via JTAG JTAG Display Contents ofa This option allows the use to list the contents of any text file on TXT File the Smart Media card Selecting Option 2 results in the following menu to be displayed refer to Figure 23 DN5000106 HyperTerminal lol x File Edit View Call Transfer ENTER SELECTION 2 INTERACTIVE CONFIGURATION MENU 1 Select bit files to configure FPGA s 2 Set verbose level current level 2 3 Disable sanity check for bit files Main menu ENTER SELECTION C
110. al port on the PC 2 Download the latest programming file for the CPLD from Emulation Technology website filename http www emulation com 3 RuniMPACT From the Windows START menu choose PROGRAMS Xilinx ISE 6 Accessories iMPACT 4 Select the Configure Devices option and proceed by clicking the NEXT button ET6000K10S User Guide www emulation com 42 PROGRAMMING CONFIGURING THE HARDWARE Operation Mode Selection x What do you wantto do first Prepare Configuration Files Load Configuration File cdf 5 Select Boundary Scan Mode option and proceed by clicking the NEXT button Configure Devices wantto configure device via Slave Serial Mode SelectMAP Desktop Configuration Mode 6 Select the Automatically connect to cable and identify Boundary Scan chain option and proceed by clicking the NEXT button ET6000K10S User Guide www emulation com 43 PROGRAMMING CONFIGURING THE HARDWARE Boundary Scan Mode Selection 7 Ifthe process was successful the following window will appear Boundary Scan Chain Contents Summary o a 8 Click OK button 9 Enter the location of the CPLD JED file in the window prompting the file name and click OK The following window would be displayed ET6000K10S User Guide www emulation com 44 PROGRAMMING CONFIGURING THE HARDWARE untitled Configuration M
111. amp DDR FLASH Test Daughter Card Test with or without cables BAR Range Tests AETEST also provides the user with the following abilities Recognize the 6000 105 Read FPGA F Revision Display Vendor and Device ID Set PCI Device and Function Number Display all configured PCI devices Various loops for PCI device function and ID numbers Write and Read Configuration DWORD Write DWORD Read DWORD and Write Read DWORD Same Address BAR Memory Fill Write and Display Configure Save BAR s from to a file of AETEST s tests and functionality are based upon simple C functions Descriptions of variety of functions may found ET6000K10S User Guide www emulation com 25 INTRODUCTION THE SOFTWARE TOOLS Appendix B AETEST Basic C Functions NOTE of the screen captures are taken from the aetest_wdm exe implementation of the AETEST utility program unless otherwise noted Certain functions may be missing from the figures However all functions will be discussed in their proper context 111 Getting Started with AETEST Once AETEST is installed and the ET6000K108 board is powered on the user can execute his her incarnation of AETEST The ET6000K10S is defined by its DEVICE ID of 0 1600 and its VENDOR ID of 0x17df AETEST should immediately recognize the ET6000K10S Logic Emulation board shown in Figure 3 IC WINNTSystem32cmd exe aetest wdm exe E 5 icrosoft Windows 20
112. and TRSTn left unconnected The following signals are not connected on the ET6000K108 3 3VAUX INTBn INTCn INTDn ET6000K10S User Guide ww w emulation com 139 BOARD HARDWARE 11 Power System The 06000 105 supports a wide range of technologies from legacy devices like serial ports to DDR SDRAM and RocketIO multi gigabit transceivers This wide range of technologies requires a wide range of power supplies These are provided on ET6000K10S using a combination of switching and linear power regulators The ET6000K10S can be hosted in 3 3V PCI PCI X slot or it can be used a standalone configuration During in system operation the primary supply to the ET6000K10S8 secondary supplies is derived from the PCI 5V fingers while in standalone operation the primary power to the 6000 105 is derived from an external ATX type power supply 11 1 In System Operation Power is supplied to all the secondary supplies on the ET6000K10S from the PCI 5V fingers The PCI 3 3V is not used and the user should not connect this supply to the power grid During in system operation ET6000K10S has the following power supplies 15 25 4 3 3V 5V 12V 12 The 1 5V 2 5V and 3 3V power supplies are generated from the 5V supply using the DATEL power modules U28 U29 U30 These modules are non isolated 300kHz switching regulators rated for 10A and provide clean power
113. ated indefinitely 3 AETEST will repeatedly write then read DWORD stored at the specified address ET6000K10S User Guide www emulation com 33 INTRODUCTION THE SOFTWARE TOOLS Command Prompt aetest_wdm exe Bar Number 5 gt 8 Address Chex 81280808808 umbers of long words to write Cin decimal 1 long word to write hex 54fedcha 1 Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely lease select S4fedcha 54fedcha it a key to continue Figure 10 Memory Write Read DWORD Figure 10 shows a write tead of the DWORD 0x54fedcba from address 0x200000 of SSRAM 4 Bar Memory Fill Opt 4 Memory enables to user to fill a region of PCI memory space with a data selectable pattern All 4 gigabytes of memory space is accessible Figure 11 shows a sample transaction Using Bar Memory Fill the user must first enter the BAR Number to be accessed Then the starting address must be entered in hex and the number of bytes the user wishes to fill in hex and divisible by 4 Finally the user must choose from a selection data patterns 1 Fill with 0 fill all the locations with 0x00000000 clear the memory 2 Data Address fill each DWORD with its address 3 Alternating 0x55555555 and Oxaaaaaaaa 4 Oxfffffttf fill all of the memory bits 5 Data Address fill each DWORD with its address inverted ET60
114. bits per second from the MGTs 25 Gbps transmit and 25 Gbps receive The SelectIO are capable of supporting multiple high speed I O standards from LVDS to SSTL2 to PCI The DCMs ate capable of 24 MHz to 420 MHz operation and provide for clock deskew frequency synthesis and fine phase shifting 2 2 FPGA Bankout Diagram The FPGA is connected directly or indirectly to all other devices on the board Figure 25 shows the connections to the FPGA on a per bank basis ET6000K10S User Guide www emulation com 67 BOARD HARDWARE 10GBit Ethernet HSSDC_2 HSSDC_2 SATA SATA SMA SMA 1 b 2 E v di FLASH 64Mb e 5 FLASH 64Mb viet x16 S 2 S ANS TSOP48 5 Et 9 4 TSOP48 X X ge A SDR SRAM 72Mb 1 87 0 87 DDR SDRAM 1Gb 1Mb x 36 2 5V 2 5V 4 43 gt 16 16 4 100 TSOP66 SDR SRAM 72Mb B2 154 B7 141 DDR SDRAM 1Gb 1Mb x 36 M 71 gt SSTL2 43 16M x16 X4 TQFP100 2 5V XILINX VIRTEX2P TSOP66 XC2VP 00 125 SDR SRAM 72Mb B3 154 F170 6 141 DDR SDRAM 166 1Mb x 36 4 71 M 43 16M x16 X4 TQFP100 2 5V 55112 TSOP66 SDR SRAM 72Mb DDR SDRAM
115. chment Unit Interface and Infiniband compliant transceivers 8 16 or 32 bit selectable internal FPGA interface 10 encoder and decoder 50 75 on chip selectable transmit and receive terminations e Programmable comma detection e Channel bonding support two to sixteen channels Rate matching via insertion deletion characters e Four levels of selectable pre emphasis Five levels of output differential voltage Per channel internal loopback modes 2 5V transceiver supply voltage 14 Virtex ll FPGA Fabric Description of the Virtex II Family fabric follows SeleccRAM memory hierarchy o Up to 10 Mb of True Dual Port RAM in 18 Kb block SelectRAM resources o Upto 1 7 Mb of distributed SelectRAM resources o High performance interfaces to external memory e Arithmetic functions Dedicated 18 bit x 18 bit multiplier blocks Fast look ahead carry logic chains Flexible logic resources o Up to 111 232 internal registers latches with Clock Enable o Up to 111 232 look up tables LUTs or cascadable variable 1 to 16 bits shift registers Wide multiplexers and wide input function support o Horizontal cascade chain and Sum of Products support ET6000K10S User Guide www emulation com 18 INTRODUCTION VIRTEX II ISE Internal 3 state busing e High performance clock management circuitry Up to eight Digital Clock Manager DCM modules Precise clock de skew
116. chronous SRAM and DDR SDRAM in various densities 6 1 FLASH The FLASH 014 016 memory components on the 6000 105 can accommodate up to 4M x 16 devices refer to Figure 46 In addition to programming the FPGA and storing bitstreams the FLASH may be used for non volatile storage ET6000K10S User Guide ww w emulation com 93 BOARD HARDWARE 016 FLASHO_ADDRO 25 2 FLASHO DATAO FEASHRcADDR 24 40 31 PASHO DATAT m 33 FLASHO_DATA2 FLASHO_ADDRS 22 A2 8 3 FEASH DATAS FLASHO_ADDR4 21 8 S I8 FEASH DATAR FLASHO ADDRS o 40 DATAS 5 10 Fe bos 8 pee _____18 BN ata 187 16 096 44 FLASHO_DATA7 8 30 FLASHO0 DATAS _ FLASH0 ADDRS 7 35 FLASHO DATAS FLASHO ADDRIO 6 9 009 34 FERSHO DATATO ADDRii 5 10 9 0010 33 FLASHO DATATT ADDRi2 4 AM i uH 39 FLASHU DATATZ 41 FLASHO_DATATS FLASHO ADDRi4 3 A18 0013 35 FLASHO_ADDR15 1 14 0914 6 FLASHO_ADDR16 48 15 E 9 FLASHO ADDRI7 17 16 a FLASHO_ADDRI8 16 217 FLASHO_ADDR19 15 18 m FLASHO_ADDR20 10 19 i ADDH2 g 20 9 180 3 3V 21 ypp T FLASHO_CEn 26 m 37 3 3V FLASHO_OEn 28
117. ct This input must be set according to the nominal frequency Refer to Table 1 in the datasheet ROBOCLOCK 1 Feedback Output Phase Function Select This input determines the phase function of the Feedback Bank s 0 1 outputs Refer to Table 3 in the datasheet FBDS01 ROBOCLOCK 1 Feedback Divider Function Select These inputs determine the function of the QFAO QFA1 outputs Refer to Table 4 in the datasheet FBDS11 ET6000K10S User Guide ROBOCLOCK 1 Feedback Divider Function Select These inputs determine the function of the QFAO and QFA1 outputs Refer to Table 4 in the www emulation com 82 BOARD HARDWARE Description Connector datasheet ROBOCLOCK 2 Frequency Select This input must be set according to the nominal frequency Refer to Table 1 in the datasheet JP7 B5 ROBOCLOCK 2 Feedback Output Phase Function Select This input determines the phase function of the Feedback Bank s 0 1 outputs Refer to Table 3 in the datasheet JP7 B6 FBDS02 ROBOCLOCK 2 Feedback Divider Function Select These inputs determine the function of the QFAO QFA1 outputs Refer to Table 4 in the datasheet FBDS12 OSCA ROBOCLOCK 2 Feedback Divider Function Select These inputs determine the function of the QFAO and QFA1 outputs Refer to Table 4 in the datasheet Enable for Oscillator A X4 JP7 B9 OSCB Enable
118. e GW Asynchronous inputs include the Output Enable OE and burst mode control DQa b c d and DPa b c d a b c d each are 8 bits wide the case of DQ and 1 bit wide in the case of DP Addresses and chip enables are registered with either Address Status Processor ADSP or Address Status Controller ADSC input pins Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin ADV Address data inputs and write controls are registered on chip to initiate self timed WRITE cycle WRITE cycles can be one to four bytes wide as controlled by the write control inputs Individual byte write allows individual byte to be written Bwa controls DQa DPa BWb controls and DPb BWe controls DQc BWd controls DQd and DPd BWa BWb BWc and BWd can be active only with BWE being LOW GW being LOW causes all bytes to be written WRITE pass through capability allows written data available at the output for the immediately next READ cycle This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance All inputs and outputs of the CY7C1380B and is JEDEC standard JESD8 5 compatible Note CE2 and CE2n are hard wired on PWB to there respective active states Use SRAM_CExn signal to select the individual devices 6 2 2 SSRAM Clocking The SSRAMs are clocked directly by RoboClock 2 U26 ECLK1 ECLK2 ECLK3 ECLK4 are LVTT
119. e 128KB of FLASH is used for FPGA configuration and utilities so the user is welcome to utilize the rest of the resources of the micro controller for their own applications Instructions for customizing the micro controller are contained in the file Atmegal128L datasheet please reference CD ROM or contact Atmel 3 1 1 MCU General Purpose IO GPIO Header P2 as shown in Figure 26 allows for connection to the unused MCU IO pins The user can utilize this IO as required e g external interrupts external IO expansion etc Note The interface is LVTTL33 and the device is not 5V tolerant Figure 26 MCU General Purpose IO Connector 3 1 2 MCU J TAG Interface The ATMega128L micro controller has JTAG interface that can be used for on chip debugging real time emulation and programming of FLASH EEPROM fuses and Lock Bits In order to take advantage of the JTAG interface you must have the Atmel ET6000K10S User Guide ww w emulation com 69 BOARD HARDWARE AVR JTAG ICE kit part number ATAVRJTAGICE and AVR studio software that Atmel provides free at www atmel com The JT AG interface for the ATmega128L be accessed through four pins TMS TDO and TDI on header P3 Header P3 as shown in Figure 27 allows for connection to the MCU JTAG pins 43 3V 3 3V o R70 2 0 JTAG MCU 1 JTAG TMS 5 7 9 PWRRSTn coo gt x JTAG MCU
120. e 51 accept and return data two clock cycles after the address phase This allows the user to begin a write burst ET6000K10S User Guide www emulation com 99 BOARD HARDWARE immediately after the last word of a read burst because read data will be returned before the first write data is required The timing is illustrated in Figure 52 Write Control amp p Data Coherency Figure 50 SSRAM ZBT Flow trough Write Control amp m Data Coherency E a 5 eze Figure 51 SSRAM Pipeline Address 4 i Phase i i Syncburst 1 Phase 95 1 1 Flowth Pipelined Phase X Figure 52 Syncburst ZBT SSRAM Timing 6000 105 User Guide www emulation com 100 BOARD HARDWARE 6 2 1 SSRAM Configuration The ET6000K10S is factory stuffed with the Cypress P N CY7C1380B 133AC SSRAM devices please refer to datasheet for more information There are 524 288 x 36 SSRAM cells with advanced synchronous peripheral circuitry and a 2 bit counter for internal burst operation All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input ECLK 1 4 The synchronous inputs include all addresses all data inputs address pipelining Chip Enable CE burst control inputs ADSC ADSP and ADV write enables BWa BWb BWd and BWE and Global Writ
121. e note the RocketIO Tranceiver performance in Table 29 Table 29 RocketIO Performance Speed Grade RocketIO Tranceiver FF 2 5 2 5 2 0 PowerPC Processor Block 350 ET6000K10S User Guide www emulation com 126 BOARD HARDWARE 8 CPU Debug and CPU Trace The 06000 105 board includes two CPU debugging interfaces the CPU Debug JP3 is a vertical header and the Combined CPU Trace and Debug J5 is a vertical mictor connector These connectors can be used in conjunction with third party tools in some cases the Xilinx Parallel Cable IV to debug software as it runs on the processor The PowerPC 405 CPU core includes dedicated debug resources that support a variety of debug modes for debugging during hardware and software development These debug resources include e Internal debug mode for use by ROM monitors and software debuggers External debug mode for use by JTAG debuggers e Debug wait mode which allows the servicing of interrupts while the processor appeats to be stopped e Real time trace mode which supports event triggering for real time tracing Debug modes and events are controlled using debug registers in the processor The debug registers are accessed either through software running on the processor or through the JTAG port The debug modes events controls and interfaces provide a powerful combination of debug resources for hardware and software development tools The JTAG port interf
122. e signals These connections are shown in Table 26 Table 26 Connections between FPGA and Infniband HSSDC2 FPGA Pin Connector U15 A20 14 6 015 421 14 5 015 419 142 ET6000K10S User Guide www emulation com 124 BOARD HARDWARE FPGA Pin Connector U15 A18 14 3 15 24 76 6 15 25 16 5 15 423 16 2 U U U U 15 422 16 3 The InfiniBand connectors have different connections to FPGA for transmit and receive differential pairs The receive differential pair between the FPGA and the InfiniBand HSSDC2 connector is connected by way of a 0 01 uF capacitor This capacitor AC couples the incoming signal to the FPGA The transmit differential pair between the FPGA and the InfiniBand HSSDC2 connector is connected by way of a 0 resistor The resistor is used as a placeholder to allow for AC coupling if desired at a future date 7 3 Serial ATA Serial is the next generation of the ATA family of interfaces Providing a higher throughput through a simpler and less expensive cable Serial ATA maintains software compatibility with older ATA implementations 7 3 1 FPGA to Serial ATA Connector The ET6000K10S board provides for operation as a Serial ATA host or device The connection between the FPGA and the Serial ATA connector is fairly simple involving only four wires per connector as well as a few capacitors and resistors to AC couple the signals These connections are also s
123. ed with programming MCU 2 Programming the MCU Code updates will be posted on Emulation Technology website The is required to purchase the IAR Compiler if in house development is required The compiler is available from http www iar com The number 15 EWA90PCUBLV150 In order to program the MCU install AVR Studio 407 from Atmel http www atmel com This program is freeware and 15 also included on the CD ROM The CPLD must be programmed before the MCU can be programmed see Programming the CPLD This section lists detailed instructions for programming the MCU using the AVR tools Note This user guide will not be updated for every revision of the Atmel AVR tools so please be aware of minor differences 1 The ET6000K10S must be powered with the Atmel AVR cable connected to MCU ISP header P1 and the other end to a serial port on the PC ET6000K10S User Guide www emulation com 47 PROGRAMMING CONFIGURING THE HARDWARE 2 The MCU 5232 serial port is required to complete the initialization phase after the MCU has been programmed See Configuring HyperTerminal 3 Download and unzip the latest programming file for MCU from Emulation Technology website Processor and CPLD update http www emulation com 4 Run AVR Studio From the Windows START menu choose PROGRAMS Atmel AVR Studio 4 5 Cancel the Welcome to AVR Studio 4 window by clicking cancel button 6 S
124. elect TOOLS STK500 AVRISP JTAG ICE and a new window should appear 7 In the Device list select the Atmega128 and in Flash window point to the location of the MCU programming file ET6000K10S A90 Fuses LockBits Advanced Board Auto Device Erase Device r Programming mode ISP Erase Device Before Parallel High Voltage Sena Verify Device After Programming Flash Use Curent Simulator Emulator FLASH Memory Input HEX File data workarea dn3000K1 O uP DN 2 Program Verify Read EEPROM Use Current Simulator Emulator EEPROM Memory nput HEX File e Program Verify Read Getting revisions Hw 0x01 SW Major 01 S w Minor Getting oscillator parameters 0 01 0 00 50 0 01 OK 8 Select the Advanced tab and read the device signature by selecting the Read Signature button ET6000K10S User Guide www emulation com 48 PROGRAMMING CONFIGURING THE HARDWARE Select frequency ha Head Byte C Flash Eeprom ta Memory 9 Select the Program tab and program the device by selecting the Program button in the Flash window 10 The device is now programmed and the status window should report the following ET6000K10S User Guide www emulation com 49 PROGRAMMING CONFIGURING THE HARDWARE t
125. enu Check configuration status Select file to use for configuration List files on Smart Media Select FPGA to program via JTAG Display Contents of a TXT file ENTER SELECTION Connected 1 06 47 Auto detect 9600841 ScROLL caes Num Capture Print echo Figure 22 Main Menu The HyperTerminal interface gives the user an easy method for handling and monitoring the ET6000K10S FPGA configuration 4 3 1 Description of Main Menu Options Table 6 describes the Main Menu options found on the HyperTerminal interface Table 6 HyperTerminal Main Menu Options Function Description Configure FPGA s The FPGA will configure in mode You can also Using main txt as press the reset button 51 to reconfigure the FPGA in Select the Configuration File MAP mode Interactive FPGA This option takes you to a menu titled Interactive configuration menu Configuration Menu and allows the FPGA to be configured through a set of menu options instead of using the main txt file The menu options are described in 3 Check Configuration This option checks the status of the DONE pin and prints out Status whether or not have been configured along with the file name that was used for configuration ET6000K10S User Guide www emulation com 60 PROGRAMMING CONFIGURING THE HARDWARE Function Description Select file to use in By default the processor uses the file m
126. fbe 110162 2add2375 6444084 8fbe69ba Gfb3ab81 4018763a 96405003 5b3753e8 42 25 07 902 98 456 61 4 6465 7e9e2432 fc3eUUf8 e67e24a8 8 243 0 706869 6 e4119088 319729 b57a6c 7 8c2daaeb 849dc19 76cc87ab 2dBe9db8 329b689c 44490031 d615ca47 8237146c 5a68da9b 80741510 47ba2ec2 b71e55di 77c953af 2 74 879 43 37 37 6 1 4816 33eeb69d 26fe9 cc 4d231e67 35980763 954 275 251b64e8 444 4 4 9 7bfdb934 lt j ump 4060402 Cq gt uit Figure 13 Bar Memory Display The sample view shown in Figure 13 displays 160 DWORDS of SSRAM 4 data starting at address 0x200000 The data displays the results of the transactions shown in Figure 11 and Figure 12 For Figure 11 alternating DWORDs of Oxaaaaaaaa and 0x55555555 were written starting at address 0x200000 total of 0x80 128 decimal bytes of data were written Then for Figure 12 the DWORD Oxabcdef45 was written to the address 0x200020 It is clear to see the results of the Bar Memory and Memory Write transactions with the Memory Display function SSRAM Memoty Test Opt c f SSRAM Memory Test allows the user to test one of the four SSRAMs on the 6000 105 DDR SDRAM Memory Test Opt h DDR SDRAM Memory Test allows the user to test all of the DDR SDRAMs on the ET6000K108 Full Memory Test Opt 1 ET6000K10S User Guide www emulation com 37 INTRODUCTION THE SOFTWARE TOOLS
127. file from the active device This option is for advanced users only 1 1 4 Memory Menu Upon entering the Memory Menu from the Main Menu AETEST will output a screen similar to the one shown in Figure 7 S 32 aetest_wdm exe ASIC Emulator PCI Controller Driver v4 Write Dword Same Address 2 gt Read Dword Same Address Weite Read Dword Same Address BAR Memory Fill BAR Memory Write BAR Memory Display memory test on SSRAM 1 memory test on SSRAM 2 memory test on SSRAM 3 memory test on SSRAM 4 memory test on DDR full memory test including blockram gt memory test on FPGA block memory bar memory range test bar memory address data bitwise test Main Menu Q gt Quit PCI BASE ADDRESS 1 1 b3ai ieBBB 2 68000000 86000008 4 5 668600000 Please select option Figure 7 Memory Menu The possible Memory Menu options and their descriptions are listed below In each description an example transaction will be shown The accesses will focus on SSRAM 4 at the AETEST address location of 0x200000 NOTE The AETEST address is offset by 2 to the left when compared to the actual SSRAM address For example AETEST address 0x200000 is equivalent to the SSRAM address 0x80000 ET6000K10S User Guide www emulation com 31 INTRODUCTION THE SOFTWARE TOOLS Write DWORD Opt 1 Write DWORD allows t
128. finiband HSSDC_2 Interfaces Two SATA Interfaces Two Multi Gigabit Ttransceiver channels SMA e One User Clock SMA Interface differential e 200 Pin Test Header e CPU Debug and Trace Interfaces in Berg and Mictor connectors NOTE RocketIO interface speed is directly affected by the speed grade of the part Please refer to the Xilinx datasheet 2 Virtex4l Pro FPGA The Virtex II Pro FPGA is situated on the topside of the board For a detailed description of the capabilities of the Virtex II Pro FPGA refer to the datasheet on the Xilinx website 2 1 FPGA 2VP70 Facts The Virtex II Pro Platform FPGA on board the ET6000K108 is FPGA in the FF1704 package The capabilities of the 2VP70 base model include 2PowerPC M 405 processor 16 or 20 Multi Gigabit Transceivers ET6000K10S User Guide www emulation com 66 BOARD HARDWARE 996 SelectI O e 8 Digital Clock Managers DCMs 33000 logic slices 5900 of block SelectRAM BRAM 328 18 x 18 bit multiplier blocks The FF1704 package for the FPGA that is used on the 6000 105 is a 1 0mm 42 5 x 42 5mm fully populated with four corner balls removed flip chip BGA The PowerPC 405 is capable of operation at 300 MHz and is capable of 420 Dhrystone MIPs dependend on the speed grade of the part Each of capable of 3 125 Gigabits per second in both directions for an aggregate bandwidth of 50 Giga
129. for Oscillator B X5 JP7 B10 REFSEL1 ROBOCLOCK 1 Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair PLL1A as the reference input When HIGH it will use the REFB pair PLL1BC as the reference input This input has an internal pull down JP8 B1 REFSEL2 ROBOCLOCK 2 Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair DCLK3 or CLKOUT as the reference input When HIGH it will use the REFB pair PLL2BC or PLL2BNC as the reference input This input has an internal pull down ET6000K10S User Guide ROBOCLOCK 1 Output Mode This pin determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFF mode When in MID the device will enter ww w emulation com 83 BOARD HARDWARE Description Connector factory test mode ROBOCLOCK 2 Output Mode This pin determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD mode When in MID the device will enter factory test mode JP8 B4 FBDIS1 ROBOCLOCK 1 Feedback Disable This input co
130. h the IEEE 1149 1 specifications for vendor specific extensions and are compatible with standard JTAG hardware for boundary scan system testing The PPC405 JTAG debug port supports the four required JTAG signals TMS TDI and TDO It also implements the optional TRST signal The frequency of the JTAG clock signal can range from 0 MHz DC to one half of the processor clock frequency The debug port logic is reset at the same time the system is reset using TRST When TRST is asserted the JTAG TAP controller returns to the test logic reset state Refer to the PPC405 Processor Block Manual for mote information on the debug port signals Information on is found in the IEEE standard 1149 1 1990 8 1 1 CPU Debug Connector Figure 59 shows JP3 the vertical header used to debug the operation of software in the CPU This is done using debug tools such as Parallel Cable IV or third party tools This connector cannot be used when the Mictor connector is in use PPC_JTAG_TDO A D PPC_JTAG_TRSTn R9 WA 1K PPC_JTAG_TCK G 2 5V HEADER 8X2 Figure 59 CPU Debug Connector 8 1 2 CPU Debug Connection to FPGA The connection between the CPU debug connector and the FPGA are shown in Table 30 These signals are attached to the PowerPC 405 JTAG debug resources using normal FPGA routing resources The JTAG debug resources are not hard wired to particular pins and are available for a
131. he current file or in Resoutces for details another file in the current Refer to Title Formats in document Chapter 1 for details Red Text Cross reference link to a See Figure 2 5 in the location in another document Virtex I Handbook Blue underlined text Hyperlink to website URL Go to http www xilinx com for the latest datasheets 4 Relevant Information Information about PCI can be obtained from the following sources Reference the PCI Special Interest Group for the latest in PCI PCI X Specifications PCI Special Interest Group http www pcisig com 2575 NE Kathryn St 17 Hillsboro OR 97124 FAX 503 693 8344 Other recommended specifications include PCI Industrial Computer Manufacturers Group PICMG http picmg org 401 Edgewater Place Suite 500 Wakefield MA 01880 USA TEL 781 224 1100 FAX 781 224 1239 Suggested reference books available from Amazon Tom Shanley Don Anderson PCI System Architecture 4 Edition Mindshare Tom Shanley Karen Gettman PCI X System Architecture With CD Edition Inc Mindshare Samir Palnitkar Verilog HDL A Guide to Digital Design and Synthesis ISBN 0 13 451675 3 ET6000K10S User Guide www emulation com ABOUT THIS MANUAL Sundar Rajan Essential VHDL RTL Synthesis Done Right Edwin Breecher The 10 Booster Improve Your IO Performance Dramatically ET6000K10S User Guide www emulation com GETTING STARTED Cha
132. he user match up the Device ID and Vendor ID with the desired device number ET6000K10S User Guide www emulation com 28 Function Name INTRODUCTION TO THE SOFTWARE TOOLS Description Set PCI Function Number Sets a PCI function number of your choice as the active function of a multi function device hex input The Device ID and Vendor ID of each function within the active device number to help the user choose the desired function Display all configured PCI devices Displays the PCI device numbers and corresponding Device ID and Vendor ID of all devices seen on the bus This function will not display device numbers with a Device ID and Vendor ID of all one OxFFFF Display Vendor and Device ID Displays the Vendor ID and the Device ID for the ET6000K10S which should be Ox17df and 0x1600 respectively Display Vendor and Device ID for PCI device function Displays the Vendor ID and Device ID of the active device and function number Loop on PCI device function 7 and display Vendor and Device ID Reads and displays the Vendor ID and Device ID of the active device number and function number Repeats until the user presses a key to stop it Loop on PCI device function 7F 0 and without displaying Vendor Device ID Progressive loop on all PCI device numbers with display Vendor and Device ID Reads the Vendor ID and Device ID of the active device number
133. he user to write to any location in the Base Address Registers BAR All 4 gigabytes of PCI memory can be accessed A minimum of 1 to a maximum of 1024 DWORDs can be written in sequential order to the same address Figure 8 shows a typical memory write Once the option is chosen the user must input the BAR Number followed by the address within the specified BAR Then the user needs to input the number of DWORDs to be written in decimal The data to be written must be entered for each DWORD Finally the user must choose to repeat the write access indefinitely or not Pressing any key will stop a looping write Command Prompt aetest_wdm exe Bar Number 8 55 8 Address Chex gt 8120808808 umbers of long words to write decimal 1 long word to write Cin hex abcdef45 oop indefinitely or n gt it a key to continue Figure 8 Memory Write DWORD The transaction shown in Figure 8 writes the DWORD Oxabcdef45 to address 0x200000 of SSRAM 4 Read DWORD Opt 2 Read DWORD allows the user to read DWORD from any location in the Base Address Registers BAR Figure 9 shows a typical memory read Once the option is chosen the user must input the Bar Number followed by the address location Then the user is given three options 1 AETEST will read the DWORD stored at the specified address and display it 2 Same as option 1 however the transaction is repeated indefinitely 3 AETEST will
134. hich is recommended for development by users of the ET6000K10S 2 10 1 Description read dwotd allows users of the ET6000K10S to read a dword of data from any byte aligned location in a DMA buffer 2 10 2 Arguments The arguments for read dword are shown in Table 49 They are listed in order Table 49 read dword Arguments Argument Desctiption dma buffer handle hndl Handle for a DMA buffer int offset Offset in bytes of the write location in the DMA buffer dword data Pointer to a dword 32 bit of data for the read operation typedef int dma_buffer_handle typedef unsigned char dword 2 10 3 Return Values successful function call will return zero If 2 is returned the DPMI implementation of AETEST 15 not being used See Notes 2 10 4 Notes The dma read dwotrd code is written for use in the DPMI DOS implementation of AETEST ET6000K10S User Guide www emulation com 173 APPENDIX 2 11 pci_rdwr rdwr is a function used in older revisions of AETEST Users of the ET6000K10S are advised to use current functions such as bar_write_dword and bar read dword for development 2 11 1 Description pci rdwr is the primary function for reading and writing to the Base Address Registers BARs 2 11 2 Arguments The arguments for pei_tdwr are shown in Table 50 They are listed in order Argument Table 50 pci rdwr Arguments Desctiption Possible Values long batn
135. hown in Table 27 Table 27 Connections between FPGA and SATA Signal Name FPGA Pin Connector SAO0 TxP U15 A28 J7 6 TxN 15 429 17 5 SA0 RxP 15 A27 17 2 __ 15 426 7 3 SA1__TxP 15 432 J8 6 SA1__TxN 13 493 15 5 1 RxP 15 A31 18 2 SA1__RxN 15 A30 15 3 6000 105 User Guide www emulation com 125 BOARD HARDWARE The Serial ATA connectors have different connections to the FPGA for transmit and receive differential pairs The receive differential pair is connected by way of a 0 01uF capacitor to AC couple the incoming signal to the FPGA The transmit differential pair between the FPGA and the Serial ATA connector is connected by way of a 0 resistor The resistor is a placeholder to allow for AC coupling if required at a future date The ML300 provides for operation as a Serial host or device 7 4 SMA Connectors The SMA connectors allow for direct connection the FPGA MGT interfaces 7 4 1 FPGA to SMA Connector The ET6000K10S board provides two discrete MGT channels The connection between the FPGA and the SMA connectors is fairly simple involving only one wire per connector as well as a few capacitors and resistors to AC couple the signals These connections are also shown in Table 28 Table 28 Connections between FPGA and SMA Connectors Signal Name Connector SMA1__TxP 110 SMA1__TxN 112 SMA1__RxP Jo Pleas
136. ion 1 Place the files install exe and QLDriver sys into the same directory on your PC machine 2 install 3 After the driver is installed start the driver by selecting Control Panel Devices find QLDriver click Start 4 Run aetestnt exe Note Although this driver will work under Windows 2000 we recommend using the WDM driver instead If you must use it see the README txt file in the ntdriver docs directory on the CD ROM 1 5 Linux This version of AETEST has been tested on Red Hat Linux 7 2 kernel version 2 4 x The driver file dndev o and its source code included the ET6000K10S CD ROM The scripts load and dndev unload which are also included the CD ROM are used to load and unload the driver Follow the procedures listed below for installation 1 Login as toot to statt the driver and run the program 2 Load the driver type sh dndev load 3 Unload the driver type sh dndev unload 4 After the driver is loaded run the utility aetest linux 5 user may need to run chmod on aetest linux to make it executable type chmod aetest linux ET6000K10S User Guide www emulation com 162 APPENDIX NOTE All text files including scripts are DOS text format with an extra carriage return character after every new line they must be converted 1 6 Solaris The utility and driver tested on Solaris 7 0 Spare with the 32 bit kernel F
137. l frequency f NOM Refer to Table 1 in the datasheet JP7 A7 B7 FBDS02 ROBOCLOCK 2 Feedback Divider Function Select These inputs determine the function of the QFAO and QFA1 outputs Refer to Table 4 in the datasheet JP7 A9 B9 JP7 A10 B10 OSCA OSCB Enable for Oscillator A X4 Enable for Oscillator B X5 JP8 A1 B1 REFSEL1 ET6000K10S User Guide ROBOCLOCK 1 Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair PLL1A as the reference input When HIGH it will use the REFB pair PLL1BC PLLIBNC as the reference input This input has an internal pull down www emulation com 10 GETTING STARTED Jumper Installed Description JP8 A2 B2 ROBOCLOCK 2 Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair DCLK3 FPGA_CLKOUT as the reference input When HIGH it will use the REFB pair PLL2BC or PLL2BNC as the reference input This input has an internal pull down ROBOCLOCK 1 Output Mode This pin determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFF mode When in MID the device will enter factory test mode ROBOCLOCK Z2 Output Mode This pin determines the clock outputs disable
138. l is available in the RISCWatch Debugger User s Guide 8 1 4 CPU Trace Connector Agilent Windriver has defined a Trace Port Analyzer IPA port for the PowerPC 4xx line of CPU cores that combines the CPU Trace and the CPU Debug interfaces onto a single 38 pin Mictor connector This provides for high speed controlled impedance signaling x4 2 x 5 6 TRC PPC_DBG_HALTn 7 8 PPC_JTAG_TDO 12 VSENSE 14 PPC_JTAG_TCK 13 14 6 X JTAG 5 15 15 Hex JTAG TDT 17 18 25 X 22 24 ppc 1510 Figure 60 Combined Trace Debug Connector Pinout ET6000K10S User Guide www emulation com 129 BOARD HARDWARE 8 1 5 Combined CPU Trace Debug Connection to FPGA Table 31 shows the connection between the Combined CPU Trace and Debug Port 15 The connections to the FPGA are shared with the CPU Trace and CPU Debug interfaces discussed in previous sections Table 31 Combined CPU Trace Debug connection to FPGA Signal Name FPGA Pin Connector PPC_TRC_TCK U15 E24 JP5 6 DBG HALTIn U15 E23 JP5 7 PPC_TRC_VSENSE N A JP5 12 PPC_JTAG_TDO U15 D24 JP5 11 PPC_JTAG_TCK U15 D23 JP5 15 PPC_JTAG_TMS U15 C24 5 17 PPC_JTAG_TDI U15 C23 JP5 19 PPC_JTAG_TRSTn U5 79 JP5 21 1510 15 220 JP5 24 TRC 1540 U15 F19 JP5 26 PPC_TRC_TS1E 15 E20 JP5 28 IRC 52 15 19 JP5 30 PPC
139. lows manipulation of the data as required by the application and allows the JTAG chain to become an address on the existing bus The processor can then read from or write to the address representing the JTAG chain 3 4 1 FPGA J TAG Connector Figure 32 shows P6 the JTAG connector used to download the configuration files to the FPGA 43 3V 2 R103 lt gt R107 lt R109 1K 1K 1K 3 3 FPGA CCLK TCK L FPGA_DONE TDO FPGA_PROGn TMS FPGA_INITn FPGA DIN TDI o gt co Ix 2 R113 1K Figure 32 FPGA Connector 3 4 2 FPGA J TAG connection to CPLD Table 12 shows the connection between the FPGA JTAG connector and the CPLD ET6000K10S User Guide www emulation com 75 BOARD HARDWARE Table 12 FPGA JTAG connection CPLD Signal Name Connector DCLK TCK 1 DONE TDO P6 3 INITn TMS P6 5 DATAO TDI P6 9 4 Clock Generation 4 1 Clock Methodology The ET6000K10S Logic Emulation board has a flexible and configurable clocking scheme Figure 33 is a block diagram showing the clocking resources and connections CLOCK DISTRIBUTION ASIC EMULATION BOARD DN5000106
140. n Bar Memory Display for view of the results of this transaction Bar Memory Display Opt 8 Memory Display enables to user to view 160 DWORDs of PCI memory space All 4 gigabytes of memory space is accessible Figure 13 shows a sample view The user will be prompted to choose a starting address upon selecting the Bar Memory Display function Input starting address hex and 32 bit aligned The address must be in hexadecimal and 32 bit aligned A screen similar to the one shown in Figure 13 will be outputted to the screen after entering the starting address The screen will contain 20 lines of which each line lists 8 DWORDS of data Combining the very first line and the first column on the screen specifies the corresponding address of each DWORD For example the DWORD of data 0x1663669b in column 5 row 6 is associated with 0x200080 column 1 row 1 Consequently the address is 0 20008 Some viewing options are listed in the final line of the screen To select an option the uset needs to press the key corresponding to the letter number contained in the parentheses The options are e Forward View the next 160 DWORDs of data press f ET6000K10S User Guide www emulation com 36 INTRODUCTION THE SOFTWARE TOOLS Back View the previous 160 DWORDs of data press b e Jump View a newly specified location press The user will be prompted for the new address in hex
141. n report and the HDL design code will further enhance the turnaround time Xilinx ISE provides the seamless integration with the leading synthesis engines from Mentor Graphics Synopsys and Synplicity You can use the synthesis engine of our choice In addition ISE includes Xilinx proprietary synthesis technology XST You have options to use multiple synthesis engines to obtain the best optimized result of yout programmable logic design 2 1 3 Implementation and Configuration Programmable logic design implementation assigns the logic created during design entry and synthesis into specific physical resources of the target device The term place and route has historically been used to describe the implementation process for FPGA devices and fitting has been used for CPLDs Implementation is followed by device configuration where a bitstream is generated from the physical place and route information and downloaded into the target programmable logic device To ensure designers get their product to market quickly Xilinx ISE software provides several key technologies required for design implementation Ultra fast runtimes enable multiple turns per day ProActive Timing Closure drives high performance results Timing driven place and route combined with push button ease e Incremental Design ET6000K10S User Guide www emulation com 21 INTRODUCTION VIRTEX II AAND ISE e Macro Builder 2 1 4
142. nal Name Connector Test Signal Name FPGA Pin Header Header 1 128 P3N85 J5 35 P11 128 TST HDRA95 U15 N34 11 129 No Connect 11 129 GND J1 130 P3N84 J5 37 P11 130 TST HDRA96 U15 N37 1 131 P3N81 J5 39 P11 131 TST_HDRA97 U15 M35 J1 132 P3N80 5 41 11 132 TST_HDRA98 U15 AK39 J1 133 P3N79 2 3 11 133 TST_HDRA99 U15 AK40 J1 134 P3N78 J24 P11 134 TST_HDRA100 U15 L39 J1 135 P3N73 J2 6 P11 135 TST 101 U15 L38 J1 136 P3N72 J2 7 P11 136 TST HDRA102 U15 L40 J1 137 P3N71 J2 33 P11 137 TST_HDRA103 U15 K40 J1 138 P3N70 J2 34 P11 138 TST_HDRA104 015 136 11159 P3N65 J5 43 P11 139 TST_HDRA105 015 137 J1 140 No Connect P11 140 GND 11141 P3N64 J5 45 P11 141 TST HDRA106 U15 K42 1 142 P3N61 J5 47 P11 142 TST_HDRA107 U15J36 J1 143 P3N60 J5 49 P11 143 TST_HDRA108 U15 AK31 11 144 P3N59 161 P11 144 TST HDRA109 U15 AK32 11 145 P3N58 6 3 P11 145 TST_HDRA110 U15 H37 J1 146 P3N53 16 5 11 146 HDRA111 915 037 1 147 P3N52 16 7 P11 147 TST_HDRA112 U15 E37 J1 148 P3N51 J2 17 P11 148 TST HDRA113 015 036 1 149 P3N50 J2 18 P11 149 TST HDRA114 U15 E36 1 150 P3N45 16 9 11 150 TST_HDRA115 U15 P35 J1 151 No Connect 11 151 1 152 P3N44 J6 11 11 152 TST HDRA116 U15 P32 1 153 P3N41 16 13 211153 117 015 231 6000 105 User Guide www emulation com 155 BOARD HARDWARE
143. nector Figure 27 MCU JTAG Connector Figure 28 MCU Programming Connector Figure 29 MCU Serial Figure 30 CPLD Programming Header Figure 31 SmartMedia Connector Figure 32 FPGA JTAG Connector Figure 33 Clocking Block Diagram Figure 34 LVPECL Clock Input and Termination Figure 35 Clock Source Jumper Figure 36 RoboClock Functional Block Diagram Figure 37 RoboClock Configuration Jumpers Figure 38 DDR DCM Implementation Figure 39 PPC External Clock Figure 40 REFCLK BREFCLK Selection Logic Figure 41 LVPECL Reference Clock Oscillator Interface Figure 42 LVPECL Reference Clock Oscillator Interface DCT Figure 43 LVDS Reference Clock Oscillator Interface Figure 44 LVDS Reference Clock Oscillator Interface DCI Figure 45 Reset Topology Block Diagram Figure 46 FLASH Connection Figure 47 SSRAM Connection Figure 48 SSRAM Flow trough Figure 49 SSRAM Pipeline Figure 50 SSRAM ZBT Flow trough Figure 51 SSRAM Pipeline Figure 52 Syncburst and ZBT SSRAM Timing Figure 53 Clock Level Translation sse Figute54 DORS DRAM CONEGU Figure 55 SSTL2 Class 1 Figure 56 SSTL2 Class 2 Termination Figure 57 DDR VTT Termination Regulator Figure 58 Recommended connections for the R14K ST11 Figure 59 CPU Debug Connector Figure 60
144. nterface 3 2 2571 3 2 1 CPLD Programin ne OELEK 72 3 22 Design Notes on the rir 72 3 3 SmartMedia 3 3 1 SmartMedia Connector 3 3 2 SmartMedia connection to CPED MCVU ertt eerte rae eret din ee cie eer been eee ee pecie 74 3 4 Boundary Scan JTAG IEEE 1532 Mode 79 3 4 1 FPGA JTAG 575 3 4 2 FPGA JTAG connection to CPLD weld CLOCK GENERATION Senet ads 4 1 Clock Methodology 5 e ta Ut EE REPE UR 4 2 Clock Source Jumpers 4 2 1 Glock Source Jumper etii reete ee e bee e ER 79 4 3 79 4 4 Common Clock Source Selections 45 RoboClock PLL Clock eie PER He ORE Eee 79 4 5 1 Robo Glock CornfiguratomTUmbpets trece ch eee 81 4 5 2 Clock Source Jumper Header 4 5 3 Useful Notes and Hints 4 5 4 Customizing the Oscillators AiO DDR Clocking iieri nee e RR 4 6 1 Clocking Methodology oc 4 6 2 Connections between
145. nto the following tasks Builds the software application ET6000K10S User Guide www emulation com 22 INTRODUCTION VIRTEX II ISE e Simulates the hardware description e Simulates the hardware with the software application e Simulates the hardware into the FPGA using the software application in on chip memory e Runs timing simulation Configures the bitstream for the FPGA ET6000K10S User Guide www emulation com 23 INTRODUCTION THE SOFTWARE TOOLS Chapter Introduction to the Software Tools This chapter introduces the software tools as well as references to more information 1 Exploring the Software Tools 11 5 AETEST utility program is used primarily to test and verify the functionality of the ET6000K108 Logic Emulation board All AETEST source code is included on the CD ROM shipped with your ET6000K108 Logic Emulation kit AETEST can be installed on a variety of operating systems including DOS and Windows 95 98 ME using DPMI DOS Protected Mode Interface Windows 98 ME using a VxD driver Windows 2000 XP Windows WDM Windows NT Linux e Solaris Detailed installation instructions each version may be found in Appendix Appendix A AETEST Installation Instructions ET6000K10S User Guide www emulation com 24 INTRODUCTION THE SOFTWARE TOOLS The AETEST utility program contains the following tests PCI Test Memory Tests SRAM
146. ntrols the state of QPA 0 1 When HIGH the QFA 0 1 is disabled to the HOLD OFF HI Z state the disable state is determined by OUTPUT MODE When LOW the QFA 0 1 is enabled Refer to Table 5 in the datasheet This input has an internal pull down FBDIS2 ROBOCLOCK 7H Feedback Disable This input controls the state of QPA 0 1 When HIGH the 04 is disabled to the HOLD OFF or HI Z state the disable state is determined by OUTPUT MODE When LOW the 0 1 is enabled Refer to Table 5 in the datasheet This input has an internal pull down ROBOCLOCK 2 Output Phase Function Select Controls the phase function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 3 in the datasheet ROBOCLOCK Z2 Output Phase Function Select Controls the phase function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 3 in the datasheet ROBOCLOCK Z2 Output Divider Function Select Controls the divider function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 4 in the datasheet ET6000K10S User Guide ROBOCLOCK 2 Output Divider Function Select Controls the divider function of bank 1 2 3 amp 4 ECLK of outputs Refer to Table 4 in the datasheet ww w emulation com JP8 B10 84 BOARD HARDWARE 4 5 2 Clock Source J umper Header Figure 37 shows JP6 JP7 and the RoboClock configuration jumpers
147. nx co developed the world s most advanced FPGA silicon product Leading teams from top embedded systems companies worked together with Xilinx software teams to develop the systems software and IP solutions that enabled new system architecture paradigm The result is the first solution capable of implementing high performance system on a chip designs previously the exclusive domain of custom ASICs yet with the flexibility and low development cost of programmable logic The Virtex II Pro family marks the first paradigm change from programmable logic to programmable systems with profound implications for leading edge system architectures in networking applications deeply embedded systems and digital signal processing systems It allows custom user defined system architectures to be synthesized next generation connectivity standards to be seamlessly bridged and complex hardware and softwate systems to be co developed rapidly with in system debug at system speeds Together these capabilities usher in the next programmable logic revolution 1 1 Summary of Virtex l Pro Features The Virtex II Pro has an impressive collection of both programmable logic and hard IP that has historically been the domain of the ASICs High performance FPGA solution including o Up to twenty four RocketIO embedded multi gigabit transceiver blocks based on Mindspeed s SkyRail technology ET6000K10S User Guide www emulation com 16 INTRODUCTION
148. o RoboclocklI M CY7B994V Multi Phase PLL Clock Buffers ET6000K10S User Guide www emulation com 76 BOARD HARDWARE The clock source selection grid formed by JP5 distributes clock signals to two Roboclock PLL clock buffers U25 U26 The clock outputs from the buffers are dispersed throughout the board Two 3 3 V half can oscillator sockets X4 X5 and the signal CPDL_CLKOUT from the CPLD provide on board input clock solutions The ET6000K10S is shipped with both a 14 318 MHz X4 and 33 33 MHz X5 oscillator Neither X4 nor X5 are used by the configuration circuitry so the user is free to stuff any standard 3 3 V half can oscillators in the X4 and X5 positions The Clock Grid can also accept a 5X2 ribbon cable This cable can provide input clocks to the Roboclocks The two Roboclocks offer functional control of clock frequency and skew among other things The two Roboclocks PLL clock buffers 025 and 1026 are configured via header arrays JP6 JP7 JP8 The ET6000K10S is factory stuffed with CYB994V which can operate at frequencies from 24 MHz to 200 MHz respectively Each chip has 16 output clocks along with two feedback output clocks Two sets of eight output clocks are jumper selectable for each chip The feedback clocks are controlled separately The PLL clock buffers can accept either LVTTL33 or Differential LVPECL reference inputs refer to Figure 34 The devices can operate at up to 12x the input frequency while the outp
149. o test connections 2 DN3888K18SD without cables to test for shorts Main Menu Please select option Figure 17 Daughter Board Menu The possible Daughter Board Menu options and a description can be found in Table 4 Table 4 Daughter Board Options Function Name Description ET3000K10SD w cables The FPGA outputs a signal to the Daughter Board where it is sent driven back to the FPGA The data is compared for correctness This is repeated for all test header signals ET6000K10S User Guide www emulation com 40 INTRODUCTION THE SOFTWARE TOOLS Function Name Description ET3000K10SD w o cables All IO signals on the 6000 10 are driven to ground Then the option performs a walking 1s test for all of the test header signals test checks for shorts on the ET6000K10S 1 2 GNU Tools GNU software is used to develop software for the Virtex II Pro family of FPGAs This includes the GNU C compiler GCC the GNU binary utilities binutils the GNU debugger GDB and the GNU make program From the GNU Project website http www gnu otg The GNU Project was launched in 1984 to develop a complete Unix like operating system which is free software the GNU system GNU is a recursive acronym for GNU s Not Unix it is pronounced guh NEW Variants of the GNU operating system that use the Linux kernel are now widely used though these systems are often referred to as Linux they a
150. ode iMPACT File Edit View Mode Operations Output Help D si He S 25 86 2 22 alo x 85288 cpld jed For Help press F1 Configuration Mode Boundary Scan Parallel 1 2 Note The device selected should be XC95288XV 10 Select the device right click and select Program option 11 Select the Erase before programming and the Erase option before clicking the OK button ET6000K10S User Guide www emulation com 45 PROGRAMMING CONFIGURING THE HARDWARE Program Options 2 On The Fly Program Load FRGA 7 Secure Mode Parallel Mode Program Key Use D4 for 7 PROM CaclRunner Usercode 8 Hex Digits XPLA UES Enter up to characters 12 The device will be programmed with the file selected If programming was successful the following window will appear ET6000K10S User Guide www emulation com 46 PROGRAMMING CONFIGURING THE HARDWARE 8 untitled Configuration Mode iMPACT loj x File Edit View Mode Operations Output Help eis seo gv Boundary Scan Slave Serial SelectMAP Desktop Configuration 85288 cpld jed TDO Programming Succeeded PROGRESS END End Operation Elapsedtime 5 4 For Help press F1 Configuration Mode _ 5 Parallel 13 The CPLD is now programmed proce
151. ollow the procedures listed below for installation 1 Login as root to install and run AETEST 2 Go to the driver directory make sure the driver file dndev is in the sparc sub directory 3 install the driver run sh dndev install sh 4 To uninstall the driver run sh dndev uninstall sh 5 Run aetest_solaris 6 user may need to run chmod on aetest_solaris to make it executable type chmod aetest solaris The driver is compiled with the gcc compiler aetest_solaris is compiled with gmake You can download it from the GNU website The make from the Solaris installation does not work with our makefile format NOTE All text files including scripts are DOS text format with an extra carriage return character after every new line they must be converted ET6000K10S User Guide www emulation com 163 APPENDIX 2 Appendix B AETEST Basic C Functions The AETEST utility program is built on a core of basic C functions These functions perform a variety of PCI accesses e g configuration reads writes memory read writes and test functions e g memory tests This appendix will describe a handful of these functions 2 1 bar_write_byte bar_write_byte is a high level function C function which is recommended for development by users of the ET6000K10S 2 1 1 Description bar write byte allows users of the 6000 105 to write byte of data to any location in the Base Addre
152. ommodate either LVTTL or Differential LVPECL inputs The completely integrated PLL reduces jitter Please refer to the datasheet for more detailed information ET6000K10S User Guide ww w emulation com 80 BOARD HARDWARE LOCK FBKB Phase Control Logic FBSEL Freq Divide and Phase REFA Detector Gee REFA REFB rs fp REFB OUTPUT MODE Pr REFSEL FBFO m OFAC gt Phase 4 Feedback Bank gt nans 0 FBDS1 gt FBDIS Matrix AER 4QA0 pivideand 401 Bank 4 4F 1 gt phase 4050 gt Select 4080 Ans b 4051 Matrix 4081 0154 3F0 E Divide anc 30A1 3 3 gt Prase 5 Set rkp Sue Matrix S 0153 gt 20 0 2F0 gt Divide and p 2o b Lo 20 1 2 24 2m Phase 2050 Select rhe 2051 Matrix 2081 0152 P 0 10 0 gt and 1F1 gt Le 10 1 Phase Bank 1 1080 select 1080 k Matrix R Figure 36 RoboClock Functional Block Diagram 4 5 1 RoboClock Configuration J umpers Header JP6 JP7 and JP8 enable the user to configure the RoboClocks as required These ate 3 way headers and allow the signal to float MID or be pulled to GND LOW or 3 3V HIGH A brief de
153. on that is used to reset the ET6000K10S Figure 45 shows the distribution of the reset signal PWRRSTn In addition to controlling the reset the power supplies rails 1 5V 2 5V 3 3V and 5V are monitored for under voltage conditions that will cause the assertion of PWRRSTn signal Momentarily depressing the RESET push button S1 causes a narrow 100us soft reset pulse on the signal PWRRSTn If the reset push button is depressed for more than 2s and held PWRRSTn will be asserted continuously LED DS2 2 when lit means that reset is asserted refer the section describing the GPIO LED s PCI PCI X Interface PCI 3 3V 5 0 1 5V Reset Circuit LTC1326 3 3V 2 5V le 10K ANN PWRRSTn Reset Circuit LTC1326 Push Button ISP Interface Header MCU JTAG Header MCU ATmega128L PPC JTAG DEBUG Header Figure 45 Reset Topology Block Diagram JTAG 5 CPLD XC95288XV FPGA_GRSTn PWRRST RS232 IcL3221 Note RS232 Tranceiver must be disabled during MCU programming phase in order to avoid contention on the BTXD signal pin PPC_JTAG_TRSTOUTn FPGA XC2VP70 100 125 2 5V lt gt FPGA_DONE FLASH 28264083 FLASH 28264083 Note The Serial Programming Cable SPI when connected to P1 will
154. onnected 1 13 25 Auto detect 6008 1 ScRoLL caps Capture Print echo Figure 23 Interactive Configuration Option Menu ET6000K10S User Guide www emulation com 61 PROGRAMMING CONFIGURING THE HARDWARE Table 7 describes the Interactive Configuration Menu options Table 7 HyperTerminal Interactive Configuration Menu Options Function Description Select a bit file to The user is able to select a bit file from a list of bit files found on configure 5 the SmartMedia card for configuring the FPGA Set verbose level The user can change the verbose level from the current setting current level 2 NOTE If the user goes back to the main menu and configures the FPGA s using main txt the verbose level will be set to whatever setting is specified in main txt Disable Enable The user can disable or enable the sanity check depending on what sanity check for bit the current setting is files NOTE If the user goes back to the main menu and configures the FPGA s using main txt the sanity check will be set to whatever setting is specified in main txt Main menu Returns the user to the Main Menu 4 4 PC Bit File Sanity Check A version of the sanity check has been compiled for use on a PC the executable is sanityCheck exe which can be found on the CD shipped with the ET6000K10S This allows you to run the sanity check on bit files before copying them onto the Smart Media card Thi
155. or X is an invalid level then the default verbose level will be 2 2 second nonempty uncommented line main txt tells whether or not to perform a sanity check on the bit files before configuring an FPGA Sanity check y ET6000K10S User Guide www emulation com 57 PROGRAMMING CONFIGURING THE HARDWARE cc 22 where stands for yes n for no If the line is missing or the character after the 7 is not or n then the sanity check will be enabled 3 each FPGA that the user wants to configure there should be exactly one entry in the main txt file with the following format FPGA example bit In the above format the following FPGA is to signal that this entry is for FPGA F and FPGA F would then be configured with the bit file example bit The ET6000K10S only has one FPGA which is FPGA There can be any number of spaces between the and the configuration file name but they need to be on the same line 4 Comments are allowed with the following rules All comments must start at the beginning of the line All comments must begin with Ifa comment spans multiple lines then each line should start with Commented lines will be ignored during configuration and are only for the uset s purpose 5 he file main txt is NOT case sensitive Example of main txt statt of file Verbose level 2 Sanity check y FPG
156. otes FAQ articles and any device errata and manual addenda Please visit and bookmark http www emulation com Data Book Pages from The Programmable Logic Data Book which contains device specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging http support xilinx com partinfo databook htm You may direct questions and feedback to Emulation Technology using this e mail address support emulation com Phone Support Call us at 408 982 0660 during the hours of 8 00am to 5 00pm Pacific Time FAQ The download section of the web page contains a document called ET6000K10S Frequently Asked Questions FAQ This document is periodically updated with information that may not be in the User s Manual 3 Conventions This document uses the following conventions An example illustrates each convention 3 1 Typographical The following typographical conventions used in this document Convention Meaning or Use Example Courier font Messages prompts and speed grade program files that the system 100 displays Courier bold Literal commands that you ngdbuild enter in a syntactical statement design name Garamond bold ET6000K10S User Guide Commands that you select File gt Open from a menu Keyboard shortcuts Ctrl C www emulation com 2 ABOUT THIS MANUAL Convention Meaning
157. p 2Mb X 36 gt DATA 16 148 1 DDR PLLan ROBOCLOCK SWITCHING 3 3 10A PLL ECLK O 5 lt MODULE ADDRESS ADDRESS SDRAM DDR PLLip 129 026 2Mb X 36 DATA DATA 64Mb X 16 ad DDR PLLin E Lock CONTROL 46 64 16 4 PWRRSTn MONITOR CONFIG d ADDRESS ADDRESS DDR SDRAM DDR PLL2p LTC1326 JUMPERS 2Mb X36 L Ee 7 1481 33 6 4 16 DDR_PLL2n PROGRAMMABLE CLOCK SOURCE Uti CONTROL fe CONTROL 023 VOLTAGE SOURCES SWITCH E 4 Primary 32 64 Bit 33 66MHz Bus 133MHz PCI X Bus 2 Mi Eia ey Figure 24 ET6000K10S Block Diagram 11 105 Functionality The components and interfaces featured on the 6000 105 includes 2VP70 5 6 7 or 2VP100 5 6 Virtex II Pro FPGA Options ET6000K10S User Guide www emulation com 4 65 BOARD HARDWARE e Flexible and Configurable Clocking Scheme e SmartMedia Configuration DDRSDRAM 16M x 16 e Synchronous SRAM 512K x 32 36 e FLASH 4M x 16 Primary 32 64 Bit 33 66MHz PCI Bus 133MHz PCI X Bus 10Gbit Ethernet Fiber Interface optional e Two In
158. perTerminal Next place the SmartMedia card in the SmartMedia socket on the 6000 105 and turn on the power NOTE the can only go in one way The SmartMedia is hotswappable and can be taken out or put into the socket even when the power is on Once the power has been turned on the configuration process will begin as long as there is a valid SmartMedia card inserted properly in the socket If there is not a valid SmartMedia card the socket then 051 will be lit see Table 32 for GPIO LED s and the Main Menu will appear from the serial port A SmartMedia card is determined to be invalid if either the format of the card does not follow the SSFDC specifications or if it does not contain a file named main txt in the root directory If the configuration was successful a message stating so will appear and the Main Menu will come up Otherwise an error message will appear The LEDs on 051 DS2 give feedback during and after the configuration process see Table 32 for GPIO LED s for further details After the FPGA has been configured the following Main Menu will appear via the port refer to Figure 22 ET6000K10S User Guide www emulation com 59 PROGRAMMING CONFIGURING THE HARDWARE DN5000106 HyperTerminal lol x File Edit View Call Transfer Help MAIN MENU Aug 20 2003 12 33 48 Config_LIB Revision 1 39 Configure FPGA s using MAIN TXT Interactive FPGA configuration m
159. pply ET6000K10S User Guide www emulation com 113 BOARD HARDWARE SSTL2 Class 1 termination is used for unidirectional signaling such as control signals It is based on a 50Q controlled impedance driver a 50Q controlled impedance transmission line and 50Q parallel termination to at the receiver Figure 55 shows a basic SSTL2 Class 1 circuit The driver is brought to 50Q by the addition of a 250 series resistor immediately adjacent to the driver implemented using DCI thus no need for an external component Vir 0 5 x Figure 55 SSTL2 Class 1 Termination SSTL2 Class 2 termination is used for bi directional signaling such as data signals It is based on 500 controlled impedance driver and 500 parallel termination to for the receiver at both ends connected through 500 controlled impedance transmission line Figure 56 shows a basic SSTL2 Class 2 circuit The driver is brought to 50Q by the addition of a 25Q series resistor immediately adjacent to the driver Veer 0 5 X VSS Figure 56 SSTL2 Class 2 Termination Note DCI termination must be implemented in the DDR SDRAM controller design ET6000K10S User Guide www emulation com 114 BOARD HARDWARE 6 3 5 DDR SDRAM Power Supply The DATEL 2 5V module U30 is used to supply power to the 2 5V plane that supplies the VDDQ pins of the DDR SDRAM devices According to the JEDEC Specification Double Data Rate DDR
160. pter Getting Started Congratulations on your purchase of the 6000 105 LOGIC Emulation Board You can begin by installing the software or by powering on your 6000 105 If you wish to begin installation please follow the installation instructions The remainder of this chapter describes the contents of the box and how to start using the ET6000K10S LOGIC Emulation Board 1 Precaution The ET6000K10S is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar with FPGA s and circuit boards so a lecture in ESD really isn t appropriate and wouldn t be read anyway However the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda org basics part1 ctm The ET6000K10S has been factory tested and pre programmed to ensure correct operation You do not need to alter any jumpers or program anything to see the board wotk reference design is included on the enclosed CD Please verify that the board is in working order by following the steps below 2 The ET6000K 10S LOGIC Emwulation Kit The ET6000K10S LOGIC Emulation Kit provides a complete development platform for designing and verifying applications based on the Xilinx Virtex II Pro FPGA family The ET6000K10S can be hosted in a 32 64 bit PCI PCI X slot or can be used in a stand alone application This ET600
161. ques when the signal transmission times approach 10 ns This represents signaling rates of about 30 Mbps or clock rates of 60 MHz in single edge clocking systems and above LVDS is defined in the TIA EIA 644 standards Connector 2 is a Mini D Ribbon MDR connector 50 pin manufactured by 3M used specifically for high speed LVDS signaling The connector mates with a standard off the shelf 3M cable assembly P N 14150 EZBB XXX 0LC where XXX is 050 05 m 150 1 5m 300 3 0 m 500 5 0 m Please contact for further details http www 3m com ET6000K10S User Guide www emulation com 149 BOARD HARDWARE 12 2 6 Connection between FPGA and the Daughter Card Headers Table 39 shows the IO connections between the ET3000K10SD headers and the FPGA IO pins The VCCO of the IO banks are connected to 2 5V Table 39 Connection between FPGA and the Daughter Card Headers Daughter Card Connections ET6000K10S IO Connections Test Signal Name Header Connector Test Signal Name FPGA Pin Header j1 001 No Connect P11 1 12V J1 002 No Connect P11 2 GND J1 003 154 11 3 2 5 11 004 No Connect P11 4 5V J1 005 BCLK1 5 3 P11 5 2 5V J1 006 No Connect P11 6 5V J1 007 CCLK1 5 5 P11 7 CCLK1 J1 008 No Connect P11 8 GND J1 009 No Connect P11 9 3 3V J1 010 BP2N3 P2N3 J3 1 P11 10 ECLK5 J1 011 No Connect 1
162. r conventional PCI at JP2 7 8 PCL ET6000K10S User Guide www emulation com 9 GETTING STARTED Jumper Installed Signal Name Description JP5 A1 B1 JP5 A1 B1 CLOCKA CLOCKB Oscillator X4 connected to RoboClock 2 026 Oscillator X5 connected to RoboClock 1 025 JP6 A3 B3 CDS0 ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 3 amp 4 CCLK of outputs Refer to Table 4 in the datasheet JP6 A4 B4 JP6 A7 B7 CDS1 DDSO ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 3 amp 4 CCLK of outputs Refer to Table 4 in the datasheet ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 1 amp 1 DCLK of outputs Refer to Table 4 in the datasheet JP6 A7 B8 DDS1 ROBOCLOCK 1 Output Divider Function Select Conttols the divider function of bank 1 amp 1 DCLK of outputs Refer to Table 4 in the datasheet JP7 A1 B1 FS1 ROBOCLOCK 1 Frequency Select This input must be set according to the nominal frequency f NOM Refer to Table 1 in the datasheet JP7 A4 B4 FBDS11 ROBOCLOCK 1 Feedback Divider Function Select These inputs determine the function of the QFAO and 1 outputs Refer to Table 4 in the datasheet JP7 B5 C5 FS2 ROBOCLOCK 2 Frequency Select This input must be set according to the nomina
163. ration It is INOT necessary to have the serial port connection in order to configure the FPGA in SeleccMAP mode However if an error occurs during the configuration the user would be able to identify possible problems by viewing the configuration status messages See Configuring HyperTerminal on how to setup the serial port 41 Bit File Generation for SelectMAP Configuration Configuring ET6000K10S Virtex II PRO FPGA requires the generation of bit files by the Xilinx ISE tools NOTE This user guide will not be updated for every revision of the Xilinx tools so please be aware of minor differences The Xilinx ISE 6 11 revision is used here The CPLD and MCU must be programmed before executing the following instructions First a project must be created Open the Xilinx ISE Project Navigator software package Go to the File menu and select New Project A New Project dialog box will pop up shown in Figure 20 New Project x r Enter Name and Location for the Project Project Name Project Location DN5000106 CADNs0001 06 Select the type of Top Level module for the Project Top Level Module Type EDIF 5 Figure 18 New Project Screen Shot Select the input files for the project refer to Figure 19 ET6000K10S User Guide www emulation com 52 PROGRAMMING CONFIGURING THE HARDWARE New Project gt Select the Input File for the Project Input Design rce fpgacode FP
164. re more accurately called GNU Linux systems As a prerequisite for the development of the GNU system many different software packages compilers assemblers linkers debuggers libraries and other tools had to be programmed 2 Getting More Information 2 1 Printed Documentation The printed documentation as mentioned previously takes the form of a Virtex II Pro datasheet and an ET6000K 105 User Guide 2 2 Electronic Documentation Multiple documents and datasheets have been included on the CD 2 3 Online Documentation There is a public access site that can be found on Emulation Technology web site at http www emulation com ET6000K10S User Guide www emulation com 41 PROGRAMMING CONFIGURING THE HARDWARE Chapter Programming Configuring the Hardware This chapter details the programming and configuration instructions for the ET6000K10S 1 Programming the CPLD Code updates will be posted on Emulation Technology website The is required to purchase the Xilinx Development Tools if in house development is required The tools ate available from Xilinx http www xilinx com This section lists detailed instructions for programming the CPLD using the Xilinx ISE 6 1i tools Note This user guide will not be updated for every revision of the Xilinx tools so please be aware of minor differences 1 The ET6000K10S must be powered with the Xilinx JTAG cable connected to header P7 and the other end to a seri
165. rence design refer to Figure 38 The first DCM generates and CLK90 CLKO directly follows the user supplied input clock one of the clock sources PCI CLK etc This DCM also supplies the CLKDV output which is the input clock divided by 16 used for the AUTO REFRESH counter The second DCM in the controller block DCM2_RECAPTURE generates a phase shifted version of the user input clock It is used to recapture data from the DOS clock domain during a memory Read Data ET6000K10S User Guide ww w emulation com 86 BOARD HARDWARE recaptured in the rclk domain is then transferred to the system clock domain The phase shift value is specific to the system and must be programmed accordingly When adequate DCM resources ate available a third DCM can be used for better timing margins This DCM is used to generate WCLK a phase shifted version of the system clock WCLK is used to clock data at the DDR registers during a Write BUFG CLKO gt clk IBUFG SSTL2 1 ida user clk _CLKS0 ake LIPAD gt gt CLK 180 CLKFB user rst RST BUFG CLKDV gt gt ddr CLK2X SSTL2 LOCKED ddr OBUF SSTL2 DCM CLK 5 DCM2_RECAPTURE FDDH BUFG clkdv 16 CLKO gt CLKIN CLK90 CLKFB CLK180 CLK270 EST CLKDV CLK2X LOCKED locked RCLK PHASE_SHIFT DCMS optional BUFG welk CLKIN CLK90
166. robe to clock the data The DDR SDRAM control bus consists of a clock enable chip select row and column addresses bank address and a write enable Commands are entered on the positive edges of the clock and data occuts for both positive and negative edges of the clock The double data rate memory utilizes a differential pair for the system clock and therefore has both a true clock and complementary clock CK signal 6 3 2 DDR SDRAM Configuration The DDR SDRAM memory components on the ET6000K10S are arranged as 16 bit mode refer to Figure 54 Made up of four discrete parts 020 021 022 023 the components used ate 64 Mb x 16 parts organized as 16 million deep by 16 bits wide and 4 banks This provides for a total capacity of 128 Mbytes for the system for more information refer to Micron s datasheet PN MT46V64M106 ET6000K10S User Guide ww w emulation com 112 BOARD HARDWARE DDR FPGA GA ADDO 29 DDR_6A_DQO ADD1 208 FPGA SA ADD DO DDR FPGA 6A 003 32 2 002 7 503 DDR FPGA 6A_ADD4 35 8 ___ _ _504 DDR FPGA 6A_ADD5 36 4 DQ4 i0 6 5 __ DDR FPGA ADD6 37 5 005 714 006 __ FPGA ADD7 38 006 13 DDR 6A DG7 DDR FPGA GA ADD8 39 7 54 DDR 6A DQ8 DDR FPGA 6A ADDI 40 8 008 56 DDR
167. rsion of AETEST Follow the procedures listed below for installation 1 Place the files aetestdj exe and cwsdpmi exe The DOS Extender into the same directory on your PC machine 2 Bootinto DOS mode if you have not already done so 3 A DOS Boot disk must be used the Windows machine 4 Runaetestdj exe 1 2 Windows 98 ME using a VxD driver Instead of running AETEST directly from DOS the user can run AETEST with a VxD device driver The driver file PCICFG VXD and the executable aetest98 exe ate included on the ET6000K10S CD ROM The drivet s source code and its makefile ate also included Follow the procedures listed below for installation 1 Place PCICFG VXD and aetest98 exe into the same directory 2 When Windows first starts with the device plugged in it should ask for a device driver Select Specify the location of the driver ET6000K10S User Guide ww w emulation com 13 160 APPENDIX 3 Select Display a list of the drivers in a specific location 4 Select Other devices 5 Under the Manufacturers tab select unknown device 6 Under Models select unsupported device 7 Run aetest98 exe NOTE re compile the driver file PCICFG VXD the user must download the VtoolsD compiler from http www numega com 1 3 Windows 2000 The precompiled executable aetest_wdm exe and its source code included in the ET6000K10S CD ROM The driver file DnDev sy
168. s The 06000 105 provides two oscillators one for Gigibit Ethernet X2 and the other for Infiniband X3 There are eight clock inputs into each RocketIO transceiver instantiation REFCLK and BREFCLK are reference clocks generated from an external sources and presented to the FPGA as differential inputs The reference clocks connect to REFCLK BREFCLK ports of the RocketlO multi gigabit transcetver MGT While only one of these reference clocks is needed to drive the MGT BREFCLK or BREFCLK2 must be used or serial speeds of 2 5 Gbps or greater The reference clock also locks a Digital Clock Manager DCM or a BUFG to ET6000K10S User Guide www emulation com 88 BOARD HARDWARE generate all of the other clocks for the GT Never run a reference dock through a DCM since unwanted jitter will be introduced 4 8 1 Clocking Methodology At speeds of 2 5 Gbps or greater REFCLK configuration introduces more than the maximum allowable jitter to the RocketIO transceiver For these higher speeds BREFCLK configuration is required The BREFCLK configuration uses dedicated routing resources that reduce jitter BREFCLK must enter the FPGA through dedicated clock I O BREFCLK can connect to the BREFCLK inputs of the transceiver and the CLKIN input of the DCM for creation of USRCLKs For more information refer to the Rocket IO User Guide available from the Xilinx website REF_CLK_V_SEL refclk2 REFCLKSEL refclk_out to PCS and
169. s PC bit file sanity check verifies that the right version of Xilinx tools was used and the bitgen options have been set correctly To run the sanity check from the command line V osanityCheck f fpga bit d s See Table 8 for command line options Table 8 Sanity Check Command Line Options Command Line Required or Optional Desctiption Option f Required This option must be followed by the name of the bit file to perform the sanity check on d Optional This option prints out a description of the different bitgen options and their ET6000K10S User Guide www emulation com 62 PROGRAMMING CONFIGURING THE HARDWARE Command Line Required or Optional Description Option different values 5 Optional This option prints out the current bitgen settings found in the file specified with the f option If the bit file passes the sanity check you should see something similar to sanityCheck f fpga_sm bit Performing Sanity Check on File fpga_sm bit DATE 2003 07 16 TIME 10 47 01 PART 2vp70ff1704 FILE SIZE 3262448 bytes ALL BITGEN OPTIONS ARE SET CORRECTLY If the bit file does not pass then a message stating why it didn t pass will print out For example sanityCheck f fpga_sm bit Performing Sanity Check on File fpga_sm bit DATE 2003 17 03 TIME 10 47 01 PART 2vp70ff1704 FILE SIZE 3262448 bytes ERROR PowerDown status is enabled you must disable
170. s and its corresponding inf file are also included in the CD ROM Follow the procedures listed below for installation 1 If the old version of AETEST s NT driver is installed on the machine it must be uninstalled 2 Start the PC with the ET6000K10S plugged Windows should recognize the board and ask for a driver 3 When the Found New Hardware Wizard box pops up click Next 4 Select Display a list of the known drivers for this device so that I can choose a specific driver 5 Select Other device 6 Select Have Disk 7 to the directory where Dndev inf is located and select it 8 Locate the driver file DnDev sys 9 Click on one of the devices and select Next 10 Run aetest_wdm exe NOTE To compile aetest_wdm exe the user must use Visual C 6 0 setupapi lib in version 5 0 does not contain all of the necessary functions ET6000K10S User Guide www emulation com 161 APPENDIX 1 4 Windows NT Precompiled executables aetestnt exe and install exe are included in the CD ROM which is shipped with your ET6000K10S Logic Emulation board The driver files QLDriver sys QLDriver 16MB sys also included in the CD ROM The two driver files are identical except QLDriver_16MB sys only allocates a maximum of 16MB per BAR It is useful for systems with insufficient RAM To use it rename it to QLDriver sys and re install Follow the procedures listed below for installat
171. scillator s LVDS outputs to the LVDS inputs of the transceiver reference clock Alternatively the LVDS_25_DCI input buffer may be used to terminate the signals with on chip termination as shown in Figure 44 ET6000K10S User Guide www emulation com 90 BOARD HARDWARE LV1145B 2 5V LVDS UGae4 aesb oso102 Figure 43 LVDS Reference Clock Oscillator Interface LV1145B 2 5V LVDS UGae4 254 112202 Figure 44 LVDS Reference Clock Oscillator Interface DCI Note Depending on weather or not the LVPECL or the LVDS patts is selected the user must appropriately terminate the differential signals with R126 R127 R128 R140 R141 and R142 to maintain optimum signal integrity 4 9 External User Clock SMA The SMA connectors J13 JJ16 allow for direct connection of an external differential clock to the FPGA 4 9 1 FPGA to SMA Connector The connection between the FPGA and the SMA connectors is fairly simple involving only one wire per connector as well as a few resistors to AC couple and terminate the signals The connections are also shown in Table 19 Table 19 Connections between FPGA and SMA Connector CLK Signal Name FPGA Pin Connector CLK_USERp U15 K21 J16 CLK_USERn 01521 15 6000 105 User Guide www emulation com 91 BOARD HARDWARE 5 Reset Topology 51 ET6000K10S Reset The voltage monitor devices from Linear Technology P N LTC1326 U1 U2 allow a push button reset functi
172. scription of each pin is given in Table 15 Table 15 RoboClock Configuration Signals Description Connector Output Phase Function Select Controls the phase JP6 B1 function of bank 3 amp 4 of outputs refer to Table 3 in the datasheet Output Phase Function Select Controls the phase JP6 B2 function of bank 3 amp 4 of outputs refer to Table 3 in the datasheet ET6000K10S User Guide www emulation com 81 BOARD HARDWARE Description Connector ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 3 amp 4 CCLK of outputs Refer to Table 4 in the datasheet JP6 B3 ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 3 amp 4 CCLK of outputs Refer to Table 4 in the datasheet ROBOCLOCK 7H Output Phase Function Select Controls the phase function of bank 1 amp 2 DCLK of outputs Refer to Table 3 in the datasheet ROBOCLOCK 1 Output Phase Function Select Controls the phase function of bank 1 amp 2 DCLK of outputs Refer to Table 3 in the datasheet ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 1 amp 1 DCLK of outputs Refer to Table 4 in the datasheet ROBOCLOCK 1 Output Divider Function Select Controls the divider function of bank 1 amp 1 DCLK of outputs Refer to Table 4 in the datasheet ROBOCLOCK 1 Frequency Sele
173. se amp Program Test tests Ux1880880 bytes Flashi Erase amp Program Test tests entire flash thootblock gt Flash2 Erase amp Program Test tests entire flash thootblock gt Flashi Erase lt 0 10000 bytes Flash2 Erase lt 0 10000 bytes Debug Opti n G gt Clear Status Flashi gt gt Clear Status Flash2 gt M gt Main Menu Q gt Quit PCI BASE ADDRESS 8 bbaie 1 b3ale800 Please select option m Figure 16 Flash Menu The possible Flash Menu options and their descriptions are listed below Flash Display Opt 1 2 Displays Flash Memory content Flash Erase amp Program Test tests 0x10000 bytes Opt 3 4 Erase and Test the first 0x10000 bytes of the flash ET6000K10S User Guide www emulation com 39 INTRODUCTION THE SOFTWARE TOOLS Flash Erase amp Program Test tests entire flash bootblock Opt 5 6 Erase and Test the entire flash including boot block this test takes approximately 5 minutes Flash Erase 0x10000 bytes Opt 7 8 Erase the first 0x10000 bytes of the flash Clear Status Opt G H Clear error status bits in case any errors occurred 1 1 6 Daughter Board Menu Upon entering the Daughter Board Menu from the Main Menu AETEST will output a screen similar to the one shown in Figure 17 Command Prompt aetest_wdm exe loj x Daughter Board Menu 1 DN3888K18SD with cables t
174. ser must right click on the Generate Programming File process and select Run The bit file will be generated and may be found in the project directory 4 2 Creating Configuration File main txt To control which bit file on the Smart Media card is used to configure the FPGA in SelectMAP mode a file named main txt must be created and copied to the root directory of the Smart Media card The configuration process cannot be performed without this file Below is a description of the options that can be set in the file a description of the format this file needs to follow and an example of a main txt file 4 2 1 Verbose Level Duting the configuration process there are three different verbose levels that can be selected for the serial port messages Level 0 Fatal error messages Bit file errors e g bit file was created for the wrong part bit file was created with wrong version of Xilinx tools or bitgen options are set incorrectly Initializing message will appear before configuration single message will appear once the FPGA is configured e Level 1 All messages that Level 0 displays Displays configuration type should be Select ET6000K10S User Guide www emulation com 56 PROGRAMMING CONFIGURING THE HARDWARE Displays current FPGA being configured if the configuration type is set to SelectMAP Displays a message at the completion of configuration for each FPGA
175. series development systems Integrated VHDL and Verilog design flows o ChipScope M Pro Integrated Logic Analyzer 0 13 um nine layer copper process with 90 nm high speed transistors 1 5V VCCINT core power supply dedicated 2 5 VCCAUX auxiliary and VCCO power supplies IEEE 1149 1 compatible boundary scan logic support Hip Chip and Wire Bond Ball Grid Array BGA packages in standard 1 00 mm pitch Each device 100 factory tested 2 Foundation ISE 6 1i ISE Foundation is the industrys most complete programmable logic design environment ISE Foundation includes the industry s most advanced timing driven implementation tools available for programmable logic design along with design entry synthesis and verification capabilities With its ultra fast runtimes ProActive Timing Closure technologies and seamless integration with the industry s most advanced verification products ISE Foundation offers a great design environment for anyone looking for a complete programmable logic design solution 2 1 Foundation Features 2 1 1 Design Entry ISE greatly improves your Time to Market productivity and design quality with robust design entry features ISE provides support for today s most popular methods for design capture including HDL and schematic entry integration of IP cores as well as robust support for reuse of your own IP ISE even includes technology called IP Builder which allows you to capture your own IP and
176. ss Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 1 2 Arguments The arguments for bar write byte are shown in Table 40 They are listed in order Table 40 write byte Arguments Argument Description Possible Values unsigned long barnum BAR number to be accessed 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 or BAR5 5 unsigned long byte offset Address Number of bytes to 0 0 bytes in BAR s mem space offset data byte data A byte of data for the write 0x00 Oxff operation 8 bits typedef unsigned char byte 2 1 3 Return Values successful function call will return zero 2 1 4 Notes The source code for bar write byte is portable to each of the operating systems intended for AETEST usage ET6000K10S User Guide www emulation com 164 APPENDIX 2 2 bar write word bat write word is a high level function function which is recommended for development by users of the 00 105 2 2 1 Description bar write word allows users of the ET6000K10S to write a word of data to any location in the Base Address Registers BARs of PCI memory All 4 gigabytes of PCI memory is available for access 2 2 2 Arguments The arguments for write word are shown in Table 41 They are listed in order Table 41 write word Arguments Argument Description Possible Values unsigned long barnum BAR number to be accessed
177. sssessssssosessesesssssesssessesasesssesesessasesssossssesesesesesessess 42 1 PROGRAMMING THE CPDED BR AER A ER ERE EE I OU MERE Ne UR REESE UE 42 2 PROGRAMMING THE MCU 47 3 CONFIGURING 51 4 CONFIGURING THE FPGA USING 5 51 4 1 Bit foriSelectMAP citi oa tr 52 42 Creating Configuration File e tese PER C ime tea e pete 56 4 2 1 Verbose Level 4 2 2 Sanity Check 4 2 3 Format of main txt 4 3 Starting Select MAP Configuration 4 3 1 Description of Main Menu Options te t RUPEE 60 44 PC File Sanity Check 4 5 Bitstream Encryption BOARD HARDWARE 1 INTRODUCTION TO THE BOARD 65 Tdj SETG000KTOS FuticHOnality siete NEST ANE REATO BORA TENE REA U TRADE EROR TAPER UO TERMINER EAD TEN 65 2 VIRTEX II PRO FPGA 2 1 FPGA 2VP70 Facts 22 FPGA Bankout Diagram EPGA CONEIGURATION ptit ses i ite e E EHE ER 3 1 Micro Controller Unit MCU 3 1 1 General Purpose TO GPIO enetan RYE RE RESERVE SNP RESUME 69 3 12 MCU STAG Tite rta DR 69 3 1 3 MCU Programming Connector 3 1 4 RS232 I
178. t of ET6000K10S User Guide P11 200 www emulation com TST_HDRA160 U15 AH41 157 BOARD HARDWARE current The PCI bracket MP1 is also connected to the ground plane at each of the screw mounts Mounting holes are provided for standalone operation The ET6000K10S conforms to the following dimensions ET6000K10S User Guide www emulation com 158 BOARD HARDWARE I d nup BE E 4 HEHE HEHE HH HH dup Tee eee S H x x D D CHAMFER B mm TYP 44 a unupg ss h d a XtKX X tt x x a m b AX AEX AHX 152 0mm ET6000K10S User Guide ww w emulation com 159 APPENDIX Chapter Appendix 1 Appendix A AETEST Installation Instructions 1 1 DOS and Windows 95 98 ME using DPMI Precompiled executables aetestdj exe and cwsdpmi exe are included in the CD ROM which is shipped with your ET6000K10S Logic Emulation board If the user is running DOS on a Windows 95 98 ME machine the PC must be booted using a DOS boot disk A DOS boot disk is packaged with the ET6000K10S The user only needs to follow the steps listed below to run the DPMI ve
179. ters about 1 3 of a mile The R14K ST11 pinout is shown in Table 24 Table 24 Pinout of R14K ST11 Gigabit Fiber Transceiver Pin Number Description GP Grounding Posts Connect to signal ground 1 11 21 31 Transmitter DATA In 2 12 22 32 Transmitter Signal Ground 3 13 23 33 Transmitter DATA In 4 14 24 34 Transmitter Power Supply 5 15 25 35 Signal Detect Satisfactory Optical Input Logic 1 Output Fault Condition Logic 0 Output 6 16 26 36 Transmit Disable 7 17 27 37 Receiver DATA Out 8 18 28 38 Receiver Power Supply 9 19 29 39 Receiver DATA Out 10 20 30 40 Receiver Signal Ground ET6000K10S User Guide ww w emulation com 122 BOARD HARDWARE 7 1 2 FPGA to Transceiver The connections between the transceiver made using AC coupling capacitors on the receive paths In addition there are 180 ohm pull downs on the receive side to convert from the LVPECL signaling standards used by the fiber transceivers The Stratos Lightwave recommended connectivity for the T14K ST11 Gigabit Ethernet Transceiver is shown in Table 25 The connections from the FPGA to the Gigabit Ethernet Fiber transceiver ate based on this figure The AC coupling capacitor value of 0 1 uF provides for less than 4 ps of pattern dependent jitter PDJ for run lengths of 72 or less TRANSCEIVER SerDes or PHY GP 2 12 22 32 VCC 3 3
180. tor Test Signal Name FPGA Pin Header Header 1 102 12 27 11 102 HDRA U15 AP22 11 193 No Connect P11 103 1 5V J1 104 MBCKO J2 28 P11 104 GND J1 105 No Connect P11 105 3 3V J1 106 MBCK6 15 9 P11 106 DCLK1 1 107 No Connect P11 107 GND J1 108 ECLK1 J5 7 P11 108 GND 1 109 No Connect P11 109 GND 11 119 No Connect P11 110 GND J1 111 P2N5 J5 15 11 111 TST_HDRA79 U15 AF12 11112 P2N4 J5 17 11 112 TST_HDRA80 U15 AG12 J1 113 P2NX11 2 2 11 113 TST HDRAS81 U15 AE12 1 114 P2NX10 11 114 TST_HDRA82 U15 AD6 11 115 P2NX9 15 19 11 115 TST HDRAS3 U15 AD12 11 116 P2NX8 J5 21 P11 116 TST_HDRA84 U15 AC6 J1 117 P2NX3 J5 23 P11 117 TST HDRASB5 U15 AC12 1 118 No Connect P11 118 GND J1 119 P2NX2 15 25 11 119 TST HDR S6 U15 P33 J1 120 P3NX11 2 29 11 120 TST_HDRA87 U15 P34 J1 121 P3NX10 12 30 11 121 TST_HDRA88 U15 N31 11 122 P3NX7 J2 31 11 122 TST_HDRA89 U15 N32 11 123 P3NX6 2 32 11 123 TST_HDRA90 U15 N41 J1 124 P3NX3 5 27 11 124 TST_HDRA91 U15 N42 J1 125 P3NX2 J5 29 P11 125 TST_HDRA92 U15 N39 J1 126 P3NX1 J5 31 P11 126 TST_HDRA93 U15 N40 1 127 J5 33 11 127 TST_HDRA94 015 333 ET6000K10S User Guide www emulation com 154 BOARD HARDWARE Daughter Card ET6000K10S IO Connections Connections Test Sig
181. ttachment in the FPGA fabric making it is possible to route these signals to whichever FPGA pins the user would prefer to use Table 30 CPU Debug connection to FPGA Signal Name FPGA Pin Connector PPC_JTAG_TDO U15 D24 JP34 TDI U15 C23 JP3 3 PPC_JTAG_TRSTn U5 79 PPC_JTAG_TCK 015 023 ET6000K10S User Guide www emulation com 128 BOARD HARDWARE Signal Name FPGA Pin Connector PPC_JTAG_TMS U15 C24 JP3 7 PPC_DBG_HALTn U15 E23 JP3 7 8 1 3 CPU Trace The CPU Trace port accesses the real time trace debug capabilities built into the PowerPC 405 CPU core Real time trace debug mode supports real time tracing of the instruction stream executed by the processor In this mode debug events are used to cause external trigger events external trace tool uses the trigger events to control the collection of trace information The broadcast of trace information occurs independently of external trigger events trace information is always supplied by the processor Real time trace debug does not affect processor performance Real time trace debug mode is always enabled However the trigger events occur only when both internal debug mode and external debug mode disabled Most trigger events blocked when either of those two debug modes is enabled Information on the trace debug capabilities how trace debug works and how to connect an external trace too
182. ulation Technology manufactures a daughter ET3000K10SD card that allows the user connection to the FPGA IO pins The daughter card has the following features Buffered I O Passive and Active Bus Drivers e Unbuffered I O Differential LVDS pairs Note Not available on ET6000K10S Logic Emulation board e Headers for Test Points The daughter card contains headers that may be useful with certain types of oscilloscope probes or when wiring pins to prototype areas Figure 68 is block diagram of the daughter card DIFFERENTIAL BCLK1 js 6 MBCK6 _ DIFF CLOCK J3 J4 J5 J6 J7 50 PIN IDC HEADER UNBUFFERED 1 0 0 17 Y DIFF PAIR A0 A15 46 UNBUFFERED 0 23 oo 50 PIN MINI D RIBBON CABLE N CONNECTOR J7 UNBUFFERED l O 0 23 LINEAR REGULATOR 12VDC TO 3 3V 3 9VDC NT POWER INDICATORS ry Kx A N N BUFFERED I O 0 15 Ut UNBUFFERED 0 0 15 Y N 3 3 45 0V 12 0V J3 BUFFERED I O 0 7 A N N POWER U2 UNBUFFERED 0 15 HEADER BUFFERED I O 0 7 3 3 5 0V gt 4 12 0 96 BUFFERED 1 0 0 15 U3 UNBUFFERED I O 0 15 12 0V gt Y N GND 20 PIN IDC 74LVC16245APA 200 PIN MICROPAX HEADER 74FST1632
183. um BAR number to be accessed 0 BARI 1 BAR2 2 BAR3 3 BAR4 4 ot BAR5 5 long byte_offset Address Number of bytes to offset data 0 0 bytes in mem space long upper_data The upper 32 bits of data for a 64 bit access 0 00000000 long lower_data Data the lower 32 bits of a 64 bit access 0 00000000 int command PCI command MEM_READ 0x6 MEM WRITE 0x7 int be Byte Enables 0x00 DWORD BYTE EN 0x08 int dwordcount Number of DWORDs 10r2 int verify Verify TRUE do not verify access FALSE 2 11 3 ReturnValues Ox0 Ox1 When pci rdwr is called with READ as its command argument the returned DWORD is placed into the variable access_memory_dword_read The declaration for access memory dword read is Extern unsigned long access memory dwotd ET6000K10S User Guide 174 www emulation com APPENDIX 2 11 4 Notes In a typical transaction the byte_offset value will be a multiple of 4 resulting in a DWORD aligned read or write The PCI command will either be a Memory Read or a Memory Write where MEM_READ and MEM_WRITE are define definitions used in AETEST BARx where x 0 5 are also define definitions in AETEST The byte enable be is often set to DWORD_BYTE_EN for 32 bit transactions dwordcount is either 1 or 2 indicating a 3
184. ut clocks can be divided up to 12x the operating frequency 33 3 3 3 3 3 3V 9 o o R243 R244 R241 R242 130 130 130 130 PLL2B a C519 0 1 PLL2BN 1 C520 0 1uF PLL1B C515 PLL1BN C516 0 1 R248 lt R249 R246 5 R247 2 82 5 oe 82 5 Figure 34 LVPECL Clock Input and Termination Note The schematic shows capacitors in locations C519 C520 C515 C516 These are actually populated with 0 ohm resistors for direct connection to the RoboClock reference inputs The terminating resistors to GDN and 3 3V are not stuffed When using LVPECL make the required hardware changes The connections between the and various clocking resources are documented in Table 13 covering the clocking inputs and outputs respectively Table 13 Clocking inputs to the FPGA ET6000K10S User Guide www emulation com 77 BOARD HARDWARE Signal Name FPGA Pin Clock Refdes and Pin CLK_USERn J13 CLK_USERp Gig E_OSCp Gig E_OSCn Infin_OSCp Infin OSCn DDR_PLLO DDR_PLLOn CCLKO DCLKO ECLKO PCI_CLK SYS CLK GCLKOUT 4 2 Clock Source J umpers The clock source grid JP5 gives the user the ability to customize the clock scheme on the ET6000K108 A brief description of each pin is given in Table 14 Table 14 Clock Source Signals Signal Name Description Connector CPLD CLKOUT Clock signal from the CPL
185. yed Ensure correct pin orientation Pin 1 is indicated with a letter 1 on the board silkscreen as well as dot Pin 1 on the 5 X 2 cable header is indicated with a triangular shape printed on the connector female to female RS232 cable is provided with the ET6000K10S This cable will attach directly to the RS232 port of a PC Emulation Technology suggests Jameco as a possible supplier http www jameco com The part number is 132345 Male to female extension cables ate part number 25700 4 Configuring the FPGA using SelectMAP The simplest mode of configuration for the ETT6000K10S Virtex II PRO FPGA involves the SelectMAP configuration method using a SmartMedia card The ET6000K10S8 ships with two 32 MB SmartMedia cards One of these SmartMedia cards contains a reference design bit file produced for configuration and a file named main txt that sets the configuration options see Creating Configuration File main txt The SmartMedia card containing the reference design has been write ET6000K10S User Guide www emulation com 5 PROGRAMMING CONFIGURING THE HARDWARE protected by the application of the silver write protect sticker on the card The other SmartMedia card is empty and available for user applications To configure the FPGA with the reference design please skip to Starting Select MAP Configuration Status messages are reported by the MCU via the RS232 serial port during FPGA configu

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