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Analog Devices ADV7180BSTZ Datasheet

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1. Interrupt and VDP Map Default State Address Register Bit Description 71615 4132 10 Comments Notes 0x64 VDP LINE OOE VBI DATA P318 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 318 PAL NTSC N A Reserved LINE 0 Decode default standards on the lines indicated in Table 69 1 Manually program the VBI standard If set to 1 all VBILDATA_ to be decoded on each line see Table 70 Px_Ny bits can be set as desired 0x65 VDP_LINE_OOF VBI_DATA_P319_N286 3 0 0 0 0 0 Sets VBI standard to be decoded from MAN_LINE_PGM must Line 319 PAL Line 286 NTSC be set to 1 for these bits VBI DATA P6 N23 3 0 0 0 0 0 Sets VBI standard to be decoded from to be effective Line 6 PAL Line 23 NTSC 0x66 VDP LINE 010 VBI DATA P320 N287 3 0 0 0 01 0 Sets VBI standard to decoded from MAN LINE PGM must Line 320 PAL Line 287 NTSC be set to 1 for these bits DATA P7 N24 3 0 o o o o Sets VBI standard to be decoded from 19 be effective Line 7 PAL Line 24 NTSC 0x67 VDP LINE 011 VBI DATA P321 N288 3 0 0 0 0 0 Sets VBI standard to be decoded from MAN_LINE_PGM must Line 321 PAL Line 288 NTSC be set to 1 for these bits VBI_DATA_P8_N25 3 0 o o o o Sets VBI standard to be decoded from to be effect
2. Bit Shading Indicates Interrupt and VDP Map Default State Address Register Bit Description 7 6 5 41 312 1 0 Comments Notes Ox4A Interrupt Status 3 SD CHNG SD 60 Hz 50 Hz 0 No change in SD signal standard These bits can be cleared read only frame rate at output detected at the output and masked by 1 A change in SD signal standard is Register 0x4Band detected at the output Register 0x4C respectively SD_V_LOCK_CHNG_Q 0 change in SD VSYNC lock status 1 SD VSYNC lock status has changed SD H LOCK CHNG Q 0 No change in HSYNC lock status 1 SD HSYNC lock status has changed SD AD CHNG SD autodetect 0 No change in AD RESULT 2 0 bits in changed Status 1 register 1 AD_RESULT 2 0 bits in Status 1 register have changed SCM LOCK CHNG SECAM lock 0 No change in SECAM lock status 1 SECAM lock status has changed PAL SW LK CHNG 0 No change in PAL swinging burst ock status 1 PAL swinging burst lock status has changed Reserved x x Not used 0x4B Interrupt Clear 3 SD_OP_CHNG_CLR 0 Do not clear write only 1 Clears SD_OP_CHNG_Q bit SD_V_LOCK_CHNG_CLR 0 Do not clear 1 Clears SD_V_LOCK_CHNG_Q bit SD_H_LOCK_CHNG_CLR 0 Do not clear 1 Clears SD_H_LOCK_CHNG_Q bit SD_AD_CHNG_CLR 0 Do not clear 1 Clears SD_AD_CHNG_Q bit SCM_LOCK_CHNG_CLR 0 Do not clear 1 Clears SCM_LOCK_CHNG_Q bit PAL_SW_LK_CHNG_CLR 0 Do
3. Address Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Reset Value Hex 64 40 Interrupt RW INTRO INTRO DUR MV INTRO _ MV INTRO _ MPU _ INTRO INTRO SEL 0 0001x000 10 Configuration 1 SEL 1 SEL 0 SEL 1 SEL 0 INTRQ SEL 1 66 42 Interrupt Status 1 MV PS CS Q SD FR CHNG Q SD UNLOCK Q SD LOCK Q 67 43 Interrupt Clear 1 Ww MV PS CS CLR 50 FR CHNG _ SD UNLOCK SD LOCK CLR 0000000 00 CLR CLR 68 44 Interrupt Mask 1 RW MV PS CS SD FR CHNG _ SD UNLOCK SD LOCK MSKB x0000000 00 MSKB MSKB MSKB 69 45 Raw Status 1 R MPU STIM _ EVEN FIELD CCAPD INTRO 70 46 Interrupt Status2 R MPU_STIM_ SD_FIELD_ GEMD_Q CCAPD_Q INTRO Q CHNGD Q 71 47 Interrupt Clear 2 Ww MPU STIM SD FIELD _ GEMD CLR CCAPD CLR 0 00000 00 INTRO CLR CHNGD CLR 72 48 Interrupt Mask 2 RW MPU STIM _ SD FIELD _ GEMD MSKB CCAPD MSKB 0xx00000 00 INTRO MSKB CHNGD MSKB 73 49 Raw Status 2 R SCM LOCK SD H LOCK SD V LOCK SD OP 50Hz 74 4A Interrupt Status3 R PAL SW LK SCM LOCK _ SD AD CHNG 50 H LOCK SD V LOCK SD OP CHNG CHNG CHNG CHNG CHNG Q 75 4B Interrupt Clear 3 Ww PAL SW LK SCM LOCK SD AD CHNG 50 H LOCK SD V LOCK SD OP CHNG xx000000 00 CHNG CLR CHNG CLR CLR CHNG CLR CHNG CLR CLR 76 4C Interrupt Mask 3 RW PAL SW LK SCM LOCK SD AD CHNG 50 H LOCK SD V LOCK SD OP CHNG xx000000 00 CHNG MSKB CHNG MSKB MSKB CHNG MSKB CHNG MSKB MS
4. Rev J Page 88 of 114 ADV7180 Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 0x18 Shaping Filter WYSFMIA 0 wideband Y Reserved do not use Control 2 shaping filter mode allows 0lolo o 1 Reserved donot use the user to select which Y shaping filter is used for 0 5050 T 0 SVHS the Y component of Y C 0 0 0 1 1 SVHS2 YPrPb B W input signals 0 0 11010 SVHS3 it is also used when good quality input CVBS Ge DAG at signal is detected for all 10 1 SVHS5 other inputs the Y 0 10 1 1 1 SVHS6 shaping filter chosen is lolo svHs7 controlled by YSFM 4 0 SVHS8 0 SVHS9 0 1 0 1 SVHS10 0 SVHS11 1 SVHS12 0 1 1 1 0 SVHS 13 0 1 1 1 1 SVHS 14 1 0 0 0 SVHS15 1 0 0 0 1 SVHS 16 1 0 0 0 SVHS 17 110 0 1 1 SVHS 18 CCIR 601 1 011 010 Reserved do not use 1 1 1 1 1 Reserved do not use Reserved do not use Reserved Set to default WYSFMOVR enables 0 Autoselection of best filter use of the automatic 1 Manual select filter using WYSFM 4 0 WYSFM filter 0x19 Comb filter PSFSEL 1 0 controls
5. Figure 50 CCAP Waveform and Decoded Data Correlation Table 82 CCAP Readback Registers Signal Name Register Location Address User Sub Map CCAP BYTE 1 7 0 VDP CCAP DATA 0 7 0 121 0x79 CCAP BYTE 2 7 0 VDP CCAP DATA 1 7 0 122 Ox7A These registers are readback registers default value does not apply Rev J Page 65 of 114 ADV7180 VITC VITC CLEAR VITC Clear Address 0x78 6 VITC has a sequence of 10 syncs between each data byte The User Sub Map Write Only Self Clearing VDP strips these syncs from the data stream to output only the Setting VITC CLEAR to 1 reinitializes the VITC readback data bytes The VITC results are available in Register VDP_VITC_ registers DATA 0 Register VDP VITC DATA 8 Register 0x92 to Register 039A user subran VITC_AVL VITC Available Address 0x78 6 User Sub Map Read Only The VITC has a CRC byte at the end the syncs in between each data byte are also used in this CRC calculation Because the syncs When is 0y VITG data istot detected in between each data byte are not output the CRC is calculated When VITC_AVL is 1 VITC data is detected internally The calculated CRC is available for the user in the VITC Readback Registers VDP VITC CALC CRC register Resister Ox9B user sub map When the VDP completes decoding the VITC line the VITC DATA xand VITC CRC registers are updated and the VITC AVI bit is set See Figure 51 for
6. 54 VBI Data Decode ninna 54 PC Readback Registers eerte 63 Pixel Port Configuration eerte 76 GPO Control eee ei e teneam 77 MPU Port Description 78 Register Accessu EIER EIE 79 Register Programming eese 79 TE Cir 79 FC Register Maps ete ed oU RR 80 PCB Layout Recommendations 107 Analog Interface Inputs sese 107 Power Supply Decoupling sse 107 M 107 VREEN and VRE RP 5er ER dei 107 Digital Outputs Both Data and Clocks 107 Digital Inputs 82e RR UR 107 Typical Circuit Connection eese 108 Outline Dimensions eene 112 Ordering Guide ien nee ETE 114 Automotive Products sssseeeeeeeeetteteettenns 114 Rev J Page 2 of 114 ADV7180 REVISION HISTORY 1 15 Rev I to Rev J Changesto 3 ete 8 Changes to Table 16 Table 17 and Table 18 24 Changes to Table 107 eene eee eit 99 Updated Outline Dimensions seen 112 Changes to Ordering Guide eee 114 2 14 Rev H to Rev I Changes to Figure 3 Caption and Figure 4 Caption 6 Changes to Figure 7 ees
7. Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes OxE9 PAL V bit end PVEND 4 0 number of 1 UI ET 0 O PAL default ITU R BT 656 lines after rollover to set V low PVENDSIGN 0 Set to low when manual programming 1 Not suitable for user programming PVENDDELE delay V bit 0 No delay going low by one line 1 Additional delay by one line relative to PVEND even field PVENDDELO delay V bit 0 No delay going low by one line 1 Additional delay by one line relative to PVEND odd field OxEA PALF bit toggle 4 0 number of 0 0 01 1 PAL default ITU R BT 656 lines after rollover to toggle F signal PFTOGSIGN 0 Set to low when manual programming 1 Not suitable for user programming PFTOGDELE delay 0 No delay F transition by one line 1 Additional delay by one line relative to PFTOG even field PFTOGDELO delay 0 No delay F transition by one line 1 Additional delay by one line relative to PFTOG odd field OxEB Vblank Control 1 PVBIELCM 1 0 PAL VBI 0 0 VBlends one line earlier Line 335 Controls position of even field line control 0 1 ITU R BT 470 compliant Line 336 first active comb 1 0 VBlend linel Line 337 filtered line after VBI ends one line later Line 337 on even field in PAL 1 1 VBI ends two lines later Line 338 PVBIOLCM 1 0 PAL VBI 0 ends one line earlier Line 22 Controls position of
8. 31 Changes to Table 39 and LAGT 1 0 Luma Automatic Gain Timing Address Ox2F 7 6 Section ss 36 Changed Calculation of the Luma Calibration Factor Section Heading to Calculation of the Chroma Calibration Factor 38 Changes to Range Range Selection Address 0x04 0 Section 45 Changes to PHS Polarity HS Address 0x37 7 Section 46 Changes to 0x0D Ox1D 0x2C 0x37 and 0x41 Table 107 85 Changes to Power Supply Decoupling Section 110 Deleted Figure 55 Renumbered Sequentially 110 Changes to Figure 55 eite rettet 111 Changes t tertie apetece dtes 112 Changes to Figure57 x sepe pe pe RUD En 113 Changes to Figure 58 cuis ieneeen oreet 114 Changes to Ordering Guide ee 117 7 10 Rev E to Rev F Added 48 Lead LQFP Changes to Features Section Charges to Table 2 75 toii E Rhe HERR 4 Added Figure 5 Renumbered Sequentially 6 Added Input Current SDA SCLK Parameter and Input Current PWRDWN Parameter Table 3 ee 7 Added Figure 11 and Table 12 Renumbered Sequentially 16 Changes to MAN MUX EN Manual Input Muxing Enable Address 0xCA 7 Section 19 Added GDE SEL OLD ADF Bit Description Table 107 92 Moved 32 Lead LFCSP Section
9. 0 2 0 09 ig 5 27 005 SEATING aas PLANE TAN 818 8 BSC d LEAD PITCH 0 17 VIEWA ROTATED 90 CCW 051706 A COMPLIANT TO JEDEC STANDARDS MS 026 BCD Figure 63 64 Lead Low Profile Quad Flat Package LOFP 10 mm x 10 mm Body ST 64 2 Dimensions shown in millimeters ms i 7 20 TOP VIEW 7 00 SQ 20 5 DOWN 6 80 5 TN ox SEATING SN PLANE 98 PLANARITY VIEWA ROTATED 90 CCW 051706 A COMPLIANT TO JEDEC STANDARDS MS 026 BBC Figure 64 48 Lead Low Profile Quad Flat Package LOFP 7mm x 7 mm Body ST 48 Dimensions shown in millimeters Rev J Page 113 of 114 ADV7180 ORDERING GUIDE Model Temperature Range Package Description Package Option ADV7180KCP32Z 10 C to 70 C 32 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 32 12 ADV7180KCP32Z RL 10 C to 70 C 32 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 32 12 ADV7180BCPZ 409 to 85 C 40 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 40 9 ADV7180BCPZ REEL 40 C to 85 C 40 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 40 9 ADV7180BSTZ 40 C to 85 C 64 Lead Low Profile Quad Flat Package LOFP ST 64 2 ADV7180BSTZ REEL 40 C to 85 C 64 Lead Low Profile Quad Flat Package LOFP ST 64 2 ADV7180WBCP32Z 40 C to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 32 12 ADV7180WBCP32Z RL 409 to 85 C 32 Lead Lead Frame Chip Sca
10. VDP GS VPS PDC UTC 0 7 0 VDP GS VPS PDC UTC 1 7 0 VDP GS VPS PDC UTC 2 7 0 VDP GS VPS PDC UTC 3 7 0 VDP VPS PDC UTC 4 7 0 VDP VPS PDC UTC 5 7 0 VDP VPS PDC UTC 6 7 0 VDP VPS PDC UTC 7 7 0 VDP VPS PDC UTC 8 7 0 VDP VPS PDC UTC 9 7 0 VDP VPS PDC UTC 10 7 0 VDP VPS PDC UTC 11 7 0 VDP VPS PDC UTC 12 7 0 Dec Address User Sub Map Hex Address User Sub Map 132 0x84 133 0x85 134 0x86 135 0x87 136 0x88 137 0x89 138 Ox8A 139 0x8B 140 0x8C 141 0x8D 142 Ox8E 143 Ox8F 144 0x90 1 The default value does not apply to readback registers VBI System 2 The user has an option of using a different data slicer called VBI System 2 This data slicer is used to decode Gemstar and closed caption VBI signals only Using this system the Gemstar data is available only in the ancillary data stream A special mode enables one line of data to be read back through Gemstar Data Recovery The Gemstar compatible data recovery block GSCD supports 1x and 2x data transmissions In addition it can serve as a closed caption decoder Gemstar compatible data transmissions can occur only in NTSC Closed caption data can be decoded in both PAL and NTSC The block can be configured via as follows e GDECEL 15 0 allows data recovery on selected video lines on even fields to be enabled or disabled e GDECOL 15 0 enables the data recovery on selected lines for odd fields e GDECAD O0 con
11. STR Function Table 17 DR STR C Function DR STR C 1 0 Description 00 Low drive strength 1x 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive strength 4x 1 Not recommended for the optimal performance of the ADV7180 Drive Strength Selection Sync DR STR S 1 0 Address 0xF4 1 0 The DR STR S 1 0 bits allow the user to select the strength of the synchronization signals with which HS VS and FIELD are driven For more information see the Drive Strength Selection Data section Table 18 STR S Function DR STR S 1 0 Description 00 Low drive strength 1x 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive strength 4x DR STR 1 0 Description 00 01 default 10 Low drive strength 1x Medium low drive strength 2x Medium high drive strength 3x 11 High drive strength 4x Not recommended for the optimal performance of the ADV7180 Drive Strength Selection Clock DR STR 1 0 Address 0xF4 3 2 The DR STR 1 0 bits be used to select the strength of the clock signal output driver LLC pin For more information see the Drive Strength Selection Sync and the Drive Strength Selection Data sections 1 Not recommended for the optimal performance of the ADV7180 Enable Subcarrier Frequency Lock Pin SFL PIN Address 0x04 1 The EN SFL PIN bit
12. Setting AD PALM EN to 0 default disables the autodetection of PAL M Setting AD PALM EN to 1 enables the detection of PAL M AD NTSC EN Enable Autodetection of NTSC Address 0x07 1 Setting AD NTSC EN to 0 default disables the detection of standard NTSC Setting AD NTSC EN to 1 enables the detection of standard NTSC SELECT THE RAW LOCK SIGNAL SRLS TIME WIN FREE RUN fsc LOCK 72 TAKE LOCK INTO ACCOUNT FSCLE COUNTER INTO LOCK COUNTER OUT OF LOCK AD PAL EN Enable Autodetection of PAL B D I G H Address 0x07 0 Setting AD PAL EN to 0 default disables the detection of standard PAL Setting AD PAL EN to 1 enables the detection of standard PAL SFL INV Subcarrier Frequency Lock Inversion This bit controls the behavior of the PAL switch bit in the SFL genlock telegram data stream It was implemented to solve some compatibility issues with video encoders It solves two problems First the PAL switch bit is only meaningful in PAL Some encoders including Analog Devices encoders also look at the state of this bit in NTSC Second there was a design change in Analog Devices encoders from ADV717x to ADV719x The older versions used the SFL genlock telegram bit directly whereas the newer ones invert the bit prior to using it The reason for this is that the inversion compensated for the one line delay of an SFL genlock telegram transmission As a result for the ADV717x and ADV73xx encoder
13. ses 108 Added Figure 58 Updated Outline Dimensions Changes to Ordering 2 10 Rev D to Rev E Added 32 Lead LFCSP tette Throughout es ee SRI scares 1 Changes to Figure Vi sires setae p ERU ERE RU BUNC ESSERE 1 Changes to Introduction sees 4 Added Figure 4 Renumbered Sequentially 8 Added Figure 9 and Table 11 sse 14 Changes to Figure 11 seen 15 Changes to Table 12 and Table 13 sss 16 Changes to Power On Reset Section Analog Input Muxing Section and e ita eR ERRARE 17 Changes to PDBP Section and TOD 19 Changes to Identification Section sss 21 Changes to VS and FIELD Configuration Section and SQPE SOCOM p 44 Changes to Table 99 and Table 100 sss 72 Changes to GPO Control Section 73 Changes to Table 104 nanona eie eb 76 Changes to Table 106 eroi eee ipn rete e 80 Added PRESE EUM EN 108 Added Fig re 59 te eto etie 110 Changes to Ordering 110 6 09 Rev C to Rev D Change to General Description sse 1 Deleted Comparison with the ADV7181B Section 5 Deleted Figure 2 Renumbered Sequentially aub Changes to Power Requirements Parameter
14. 625 50 PAL 525 60 NTSC 0000 0001 0010 0011 0100 0101 0110 0111 1000 to 1111 Disable VDP Teletext system identified by VDP TTXT VPS ETSI EN 300 231 V 1 3 1 VITC WSS ITU R BT 1119 1 ETSI EN 300294 Reserved Reserved CCAP Reserved Disable VDP Teletext system identified by VDP TTXT TYPE Reserved VITC CGMS EIA J CPR 1204 IEC 61880 Gemstar 1 Gemstar_2x CCAP 608 Reserved Rev J Page 55 of 114 ADV7180 Table 71 VBI Data Standards to be Decoded on Line Px PAL or Line Ny NTSC Signal Name Register Location Dec Address Hex Address VBI DATA P6 N23 VDP_LINE_OOF 7 4 101 0x65 VBI_DATA_P7_N24 VDP_LINE_010 7 4 102 0x66 VBI_DATA_P8_N25 VDP_LINE_011 7 4 103 0x67 VBI_DATA_P9 VDP_LINE_012 7 4 104 0x68 VBI_DATA_P10 VDP_LINE_013 7 4 105 0x69 VBI_DATA_P11 VDP_LINE_014 7 4 106 Ox6A VBI_DATA_P12_N10 VDP_LINE_015 7 4 107 0 6 VBI DATA P13 N11 VDP LINE 016 7 4 108 0 6 VBI DATA P14 N12 VDP LINE 017 7 4 109 0x6D VBI_DATA_P15_N13 VDP_LINE_018 7 4 110 Ox6E VBI DATA P16 N14 VDP LINE 019 7 4 111 Ox6F VBI DATA P17 N15 VDP LINE 01A 7 4 112 0x70 VBI DATA P18 N16 VDP LINE 01B 7 4 113 0x71 VBI_DATA_P19_N17 VDP_LINE_01C 7 4 114 0x72 VBI_DATA_P20_N18 VDP_LINE_01D 7 4 115 0x73 VBI_DATA_P21_N19 VDP_LINE_01E 7 4 116 0x74 VBI_DATA_P22_N20 VDP_LINE_01F 7 4 117 0x75 VBI_DATA_P23_N21 VDP_LINE_020 7 4 118 0x76 VBI_DATA_P24_N22 VDP_LINE_021 7 4 119 0x77 VBI DATA
15. GS_VPS_PDC_UTC_CB_CHANGE Enable Content Based Updating for Gemstar VPS PDC UTC Address 0x9C 5 User Sub Map Setting GS_VPS_PDC_UTC_CB_CHANGE to 0 disables content based updating Setting GS_VPS_PDC_UTC_CB_CHANGE to 1 default enables content based updating WSS_CGMS_CB_CHANGE Enable Content Based Updating for WSS CGMS Address 0x9C 4 User Sub Map Setting WSS CGMS CB CHANGE to 0 disables content based updating Setting WSS CGMS CB CHANGE to 1 default enables content based updating VDP Interrupt Based Reading of VDP PC Registers Some VDP status bits are also linked to the interrupt request controller so that the user does not have to poll the available status bit The user can configure the video decoder to trigger an interrupt request on the INTRQ pin in response to the valid data available in the registers This function is available for the following data types e CGMS or WSS The user can select either triggering an interrupt request each time sliced data is available or triggering an interrupt request only when the sliced data has changed Selection is made via the WSS_CGMS_CB_ CHANGE bit e Gemstar PDC VPS or UTC The user can select to trigger an interrupt request each time sliced data is available or to trigger an interrupt request only when the sliced data has changed Selection is made via the GS_VPS_PDC_UTC CB_CHANGE bit Rev J Page 61 of 114 ADV7180 The sequence for t
16. 274 275 1276 283 255 TT Ut ao i VIDEO NVBEG 4 0 0x05 NVEND 4 0 0x04 1BT 656 4 1 0 04 7 1 NFTOG 4 0 0x03 1APPLIES IF NEWAVMODE 0 MUST BE MANUALLY SHIFTED IF NEWAVMODE 1 Figure 38 NTSC Default ITU R 656 the Polarity of H V and F is Embedded in the Data 05700 029 DM FIELD 1 EET 15251 1 1 2 314 15 161718191 tol 1 12 13 14 18 l OUTPUT 4 VIDEO Ee am ME OUTPUT t H 1 vs 4 4 OUTPUT 2 FIELD NVBEG 4 0 0x01 NVEND 4 0 0x04 77 d OUTPUT 4 NFTOG 4 0 0x06 FIELD 2 sU 126211 12631 264 2651 266 267 268 269 270 2711 2721 273 274 275 276 1277 2851 em PO Unde ooo dg VIDEO 1 OUTPUT ee OUTPUT NVBEG 4 0 0x01 NVEND 4 0 0x04 FIELD OUTPUT 4 NFTOG 4 0 0x06 Figure 39 NTSC Typical VSYNC FIELD Positions Using the Register Writes in Table 65 05700 030 Rev J Page 49 of 114 ADV7180 ADVANCE BEGIN OF VSYNC BY NVBEG 4 0 DELAY BEGIN OF VSYNC BY NVBEG 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO NVBEGDELO 0 0 1 1 0 0 1 ADVANCE BY ADVANCE BY 0 5 LINE 0 5 LINE VSYNC BEGIN Figure 40 NTSC VSYNC Begin NVBEGDELO NTSC VSYNC Begin Delay on Odd Field Address OxE5 7 When NVBEGDELO is 0 default there is no delay Setting NVBEGDELO to 1 delays VSYNC goin
17. 38 ALSB This pin selects the address for the ADV7180 For ALSB set to Logic 0 the address selected for a write is Address 0x40 for ALSB set to Logic 1 the address selected is Address 0x42 39 SDATA 1 0 Port Serial Data Input Output Pin 40 SCLK Port Serial Clock Input The maximum clock rate is 400 kHz 45 VS FIELD Vertical Synchronization Output Signal Field Synchronization Output Signal 46 INTRO Interrupt Request Output Interrupt occurs when certain signals are detected the input video see Table 108 47 HS Horizontal Synchronization Output Signal Rev J Page 17 of 114 ADV7180 POWER SUPPLY SEQUENCING POWER UP SEQUENCE The power up sequence for the ADV7180 is to power up all power supplies simultaneously If this is not possible the 3 3 V supply Dvppio must be established first When the 3 3 V supply is stable power up the 1 8 V supplies Dvpp and as quickly as possible Until the 1 8 V supplies are fully established all digital pins are in an undefined state During power up all supplies must adhere to the specifications listed in the Absolute Maximum Ratings section Take care to ensure that a lower rated supply does not go above a higher rated supply For example the 3 3 V Dvppio supply must never drop below a 1 8 V supply such as the Dvpp or To power up the ADV7180 follow these steps Assert the PWRDWN pin and the RESET
18. 5 The DNR EN bit enables the DNR block or bypasses it Table 49 DNR EN Function PEAKING GAIN 7 0 Luma Peaking Gain Address OxFB 7 0 This filter can be manually enabled The user can select to boost or to attenuate the mid region of the Y spectrum around 3 MHz The peaking filter can visually improve the picture by showing more definition on the picture details that contain frequency components around 3 MHz The default value on this register passes through the luma data unaltered A lower value attenuates the signal and a higher value gains the luma signal A plot of the responses of the filter is shown in Figure 33 Table 51 GAIN 7 0 Function Setting Description 0x40 Default O dB response Setting Description 0 Bypasses DNR disable 1 default Enables digital noise reduction on the luma data DNR TH 7 0 DNR Noise Threshold Address 0x50 7 0 The DNRI block is positioned before the luma peaking block The DNR TH 7 0 value is an unsigned 8 bit number used to determine the maximum edge that is interpreted as noise and therefore blanked from the luma data Programming a large value into DNR TH 7 0 causes the DNR block to interpret even large transients as noise and remove them As a result the effect on the video data is more visible Programming a small value causes only small transients to be seen as noise and to be removed Table 50 DNR TH 7 0 Function
19. FUNCTIONAL BLOCK DIAGRAM CLOCK PROCESSING BLOCK XTAL1Q XTALO as ANALOG y 8 BIT 16 BIT2 VIDEO DIGITAL PIXEL DATA INPUT PROCESSING c BLOCK P15 TO PO 2 iN 2D COMB x O vs Ans 9 VBI SLICER 3 5 a E 2 o COLOR Aw6 DEMOD ADV7180 F SCLK SDATA ALSB RESET PWRDWN4 1ONLY AVAILABLE ON 64 LEAD PACKAGE AND 48 LEAD PACKAGES 216 ONLY AVAILABLE 64 LEAD PACKAGE 348 LEAD 40 LEAD AND 32 LEAD PACKAGE USES ONE LEAD FOR VS FIELD 4NOT AVAILABLE ON 32 LEAD PACKAGE 5ONLY AVAILABLE ON 48 LEAD AND 64 LEAD PACKAGES Figure 1 05700 001 video performance for consumer applications with true 8 bit data resolution Three analog video input channels accept standard composite S Video or component video signals supporting a wide range of consumer video sources AGC and clamp restore circuitry allow an input video signal peak to peak range to 1 0 V Alternatively these can be bypassed for manual settings The line locked clock output allows the output data rate timing signals and output clock signals to be synchronous asynchronous or line locked even with 5 line length variation Output control signals allow glueless interface connections in many applications The ADV7180 is programmed via a 2 wire serial bidirectional port PC compatible and is fabricated in a 1 8 V CMOS process Its monolithic CMOS construction ensures greater functionality with low
20. Rev J Page 29 of 114 Gain on Cr channel 0 dB Gain on Cr channel 42 dB Gain on Cr channel 6 dB ADV7180 SD OFF Cb 7 0 SD Offset Cb Channel Address 0 1 7 0 This register allows the user to select an offset for the Cb channel only and to adjust the hue of the picture There is a functional overlap with the HUE 7 0 register Table 30 SD OFF Cb Function SD OFF Cb 7 0 Description 0x80 default 0 mV offset applied to the Cb channel 0x00 312 mV offset applied to the Cb channel OxFF 312 mV offset applied to the Cb channel SD OFF Cr 7 0 SD Offset Cr Channel Address 0xE2 7 0 This register allows the user to select an offset for the Cr channel only and to adjust the hue of the picture There is a functional overlap with the HUE 7 0 register Table 31 SD OFF Cr Function SD OFF Cr 7 0 Description 0x80 default 0 mV offset applied to the Cr channel 0x00 312 mV offset applied to the Cr channel OxFF 312 mV offset applied to the Cr channel BRI 7 0 Brightness Adjust Address 0x0A 7 0 This register controls the brightness of the video signal It allows the user to adjust the brightness of the picture Table 32 BRI Function BRI 7 0 Description 0x00 default Offset of the luma channel 0 IRE Ox7F Offset of the luma channel 30 IRE 0x80 Offset of the luma channel 30 IRE HUE 7 0 Hue Adjust Address 0x0B 7 0 This register contains the val
21. Sharp blending maximizes the effect of CTI on the picture but may also increase the visual impact of small amplitude high frequency chroma noise Table 48 CTI AB Function AB 1 0 Description 00 Sharpest mixing between sharpened and original chroma signal 01 Sharp mixing 10 Smooth mixing 11 default Smoothest alpha blend function CTI C TH 7 0 CTI Chroma Threshold Address 0x4E 7 0 The CTI C TH 7 0 value is an unsigned 8 bit number specifying how big the amplitude step in a chroma transition must be to be steepened by the CTI block Programming a small value into this register causes even smaller edges to be steepened by the CTI block Making TH 7 0 a large value causes the block to improve large transitions only The default value for CTI C TH 7 0 is 0x08 indicating the threshold for the chroma edges prior to CTI Rev J Page 40 of 114 ADV7180 DIGITAL NOISE REDUCTION DNR AND LUMA PEAKING FILTER Digital noise reduction is based on the assumption that high frequency signals with low amplitude are probably noise and that therefore their removal improves picture quality The following are the two DNR blocks in the ADV7180 the DNR1 block before the luma peaking filter and the DNR2 block after the luma peaking filter as shown in Figure 32 LUMA LUMA PEAKING FILTER OUTPUT Figure 32 DNR and Peaking Block Diagram EN Digital Noise Reduction Enable Address 0 4
22. UTC BYTE 3 3 UTC BYTE 3 2 UTC BYTE 3 1 UTC BYTE 3 0 136 88 VDP VPS R vPS PDC _ vPS PDC UTC VPS PDC UTC vPS PDC UTC vPs UrC vPS PDC UTC VPS PDC UTC vPS PDC UTC PDC UIC 4 BYTE 4 7 BYTE 416 BYTE 4 5 BYTE 4 4 BYTE 4 3 BYTE BYTE 4 1 BYTE 410 137 89 VDP_VPS_ R VPS PDC UTC VPS PDC UTC VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ PDC_UTC_5 BYTE 517 BYTE 516 BYTE 5 5 BYTE 5 4 BYTE 5 3 BYTE 512 BYTE 5 1 BYTE 510 138 8A VDP VPS R VPS PDC UTC VPS PDC UTC VPS PDC UIC VPS PDC UTC VPS PDC VPS PDC UTC 5 PDC UTC VPS PDC PDC UIC 6 BYTE 6 7 BYTE 6 6 BYTE 6 5 BYTE 6 4 BYTE 6 3 BYTE 6 2 BYTE 6 1 BYTE 6 0 139 8B VDP VPS PDC R VPS PDC UIC VPS PDC UTC VPS PDC UIC VPS PDC UTC VPS PDC UIC VPS PDC UTC 5 PDC UTC VPS PDC UTC UTC 7 BYTE 717 BYTE 7 6 BYTE 7 5 BYTE 7 4 BYTE 7 3 BYTE 7 2 BYTE 7 1 BYTE 710 140 8C VDP_VPS_PDC_ R VPS_PDC_UTC_ VPS PDC UTC VPS_PDC_UTC_ VPS PDC UTC VPS VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ UTC 8 BYTE 817 BYTE 8 6 BYTE 8 5 BYTE 8 4 BYTE 8 3 BYTE 8 2 BYTE 8 1 BYTE 8 0 141 8D VDP VPS PDC R VPS PDC UIC VPS PDC UTC 5 PDC UIC VPS PDC UTC VPS PDC UIC VPS PDC UTC 5 PDC UTC VPS PDC UTC 9 BYTE 9 7 BYTE 9 6 BYTE 9 5 BYTE 9 4 BYTE 9 3 BYTE BYTE 9 1 BYTE 9 0 142 8E VDP_VPS_PDC_ R VPS_PDC_UTC_ VPS PDC UTC VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ UTC_10 BYTE_10 7 BY
23. luma auto 010 Slow 2 sec Only has an effect matic gain timing allows Medium TC 1 sec if LAGC 1 0 is set adjustment of the luma to autogain 001 AGC tracking speed 12 0 Fast TC 0 2 sec 010 011 or 100 111 Adaptive 0x30 Luma Gain LMG 7 0 LG 7 0 luma XE exc EC LMG 11 0 see the LMG section Min value 1024d Control 2 Luma manual gain lower eight LMG 11 0 see the LMG section Max value 4095d Gain2 LG bits see LMG 11 8 LG 11 8 for description 0x31 VS FIELD Reserved 0 1 O Set to default Control 1 HVSTIM selects where 0 Start of line relative to HSE HSE HSYNC end within a line of video the 1 Start of line relative to HSB HSB HSYNC begin VS signal is asserted NEWAVMODE sets the 0 EAV SAV codes generated to suit EAV SAV mode Analog Devices encoders 1 Manual VS FIELD position controlled by Register 0x32 Register 0x33 and Register OxE5 to Register OXEA Reserved 1 Set to default 0x32 VS FIELD Reserved Set to default NEWAVMODE bit Control 2 VSBHE 0 VS goes high in the middle of the must be set high line even field 1 VS changes state at the start of the line even field VSBHO 0 VS goes high in the middle of the line odd field 1 VS changes state at the start of the line odd field 0x33 VS FIELD Reserved 0 0 0 1 0 0 Setto default Control 3 VSEHE 0 VS goes low in the middle of the NEWAVMODE bit line even field must be set high 1 VS changes sta
24. that were decoded by the VDP in the transmission order The WORD 5 Byte 2 7 0 position of bits in bytes is in the inverse transmission order The number of VBI WORDS for each VBI data standard and For example closed captioning has two user data bytes as the total number of UDWs in the ancillary data stream is shown shown in Table 82 in Table 78 Table 77 Framing Code Sequence for Different VBI Standards Error Free Framing Code Bits Error Free Framing Code Reported by VBI Standard Length in Bits in Order of Transmission VDP in Reverse Order of Transmission TTXT SYSTEM A PAL 8 11100111 11100111 TTXT SYSTEM B PAL 8 11100100 00100111 TTXT SYSTEM B NTSC 8 11100100 00100111 SYSTEM C PAL and NTSC 8 11100111 11100111 SYSTEM D PALandNTSC 8 11100101 10100111 VPS PAL 16 1000101010001 1001 1001100101010001 VITC NTSC and PAL 1 0 0 WSS PAL 24 000111100011110000011111 111110000011110001111000 GEMSTAR 1x NTSC 3 001 100 GEMSTAR 2x NTSC 11 1001 1011 101 101 1101 1001 CCAP NTSC and PAL 3 001 100 CGMS NTSC 1 0 0 Table 78 Total User Data Words for Different VBI Standards VBI Standard ADF Mode Framing Code UDWs Data Words No of Padding Words Total UDWs TTXT SYSTEM A PAL 00 nibble mode 6 74 0 84 01 10 byte mode 3 37 0 44 TTXT SYSTEM B PAL 00 nibble mode 6 84 2 96 01 10 byte mode 3 42 3 52 SYSTEM B NTSC 00 nibble mode 6 68 2
25. the horizontal blanking period in two ways e Insert all data straight into the data stream even the reserved values of 0x00 and OxFE if they occur This may violate output data format specification ITU R BT 1364 e 5 data into nibbles and insert the half bytes over double the number of cycles in a 4 bit format When GDECAD is 0 default the data is split into half bytes and inserted When GDECAD is 1 the data is output straight into the data stream in 8 bit format Table 97 PAL Line Enable Bits and Line Numbering Line Number GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address 0x4B 7 0 The 16 bits of GDECOL 15 0 form a collection of 16 individual line decode enable signals See Table 96 and Table 97 To retrieve closed caption data services on NTSC Line 21 GDECOL 11 must be set To retrieve closed caption data services on PAL Line 22 GDECOL 14 must be set The default value of GDECOL 15 0 is 0x0000 This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the odd field Enable Gemstar slicing only on lines where VBI data is expected Line 3 0 ITU R BT 470 Enable Bit Comment 12 8 GDECOL O Not valid 13 9 GDECOL 1 Not valid 14 10 GDECOL 2 Not valid 15 11 GDECOL 3 Not valid 0 12 GDECOL 4 Not valid 1 13 GDECOL 5 Not valid 2 14 GDECOL 6 Not valid 3 15 GDECOL 7 Not valid 4 16 GDECOL 8 Not valid 5 17 GDECOL 9
26. 0 Reserved 1 141 Freeze gain Reserved 1 Setto 1 0x2D Chroma Gain CMG 11 8 CG 1 1 8 in 0 1 CAGC 1 0 settings Control 1 manual mode the chroma decide in which Chroma Gain1 gain control can be used to mode CMG 11 0 CG program a desired manual operates chroma gain in auto mode it can be used to read back the current gain value Reserved 1 1 Setto 1 CAGT 1 0 chroma auto 01 0 Slow 2 sec Has an effect only matic gain timing allows 1 Medium TC 1 sec if CAGC 1 0 is set adjustment of the chroma 1 0 R d to autogain 10 AGC tracking speed eels Adaptive Rev J Page 90 of 114 ADV7180 Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 0 2 Chroma Gain CMG 7 0 CG 7 0 chroma 90 0 0 0 0 0 0 0 CMG 11 0 see the CMG section Min value Od Control 2 manual gain lower eight CMG 11 0 see the CMG section Max value 4095d Chroma Gain2 bits see CMG 11 8 CG CG 11 8 for description Ox2F Luma Gain LMG 11 8 LG 1 1 8 in x x xe lx LAGC 1 0 settings decide in which Control 1 Luma manual mode luma gain mode LMG 11 0 operates Gain1 LG control can be used to program a desired manual luma gain in auto mode it can be used to read back the actual gain value used Reserved 1 1 Setto 1 LAGT 1 0
27. 1 1110 1 1 1 0 When 0 is set to 0 Logic 0 is output from the GPOO pin 1 1111 1 1 1 1 When GPO 0 is set to 1 Logic 1 is output from the GPOO pin When is set to 0 Logic 0 is output from the GPOI pin X indicates any value When is set to 1 Logic 1 is output from the GPO pin GPO 2 When GPO 2 is set to 0 Logic is output from the 2 pin When GPO 2 is set to 1 Logic 1 is output from the 2 pin GPO 3 When GPO 3 is set to 0 Logic 0 is output from the GPO3 pin When GPO 3 is set to 1 Logic 1 is output from the GPO3 pin Rev J Page 77 of 114 ADV7180 MPU PORT DESCRIPTION The ADV7180 supports a 2 wire T C compatible serial interface Two inputs serial data SDATA and serial clock SCLK carry information between the ADV7180 and the system master controller Each slave device is recognized by a unique address The ADV7180 port allows the user to set up and configure the decoder and to read back the captured VBI data The ADV7180 has four possible slave addresses for both read and write operations depending on the logic level of the ALSB pin The four unique addresses are shown in Table 104 The ADV7180 ALSB pin controls Bit 1 of the slave address By altering the ALSB it is possible to control two ADV7180 devices in an application without the conflict of using the same slave address The LSB Bit 0 sets either a read or write operation Logic 1 corres
28. 1 8 V to 3 3 V 2 SFL Subcarrier Frequency Lock This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder 3 15 35 40 DGND G Ground for Digital Supply 5 to 10 16 17 P7 to P2 P1 PO Video Pixel Output Port 11 LLC Line Locked Output Clock for the Output Pixel Data Nominally 27 MHz but varies up or down according to video line length 12 XTAL1 This pin should be connected to the 28 6363 MHz crystal or not connected if an external 1 8 V 28 6363 MHz clock oscillator source is used to clock the ADV7180 In crystal mode the crystal must be a fundamental crystal 13 XTAL Input Pin for the 28 6363 MHz Crystal This pin can be overdriven by an external 1 8 V 28 6363 MHz clock oscillator source In crystal mode the crystal must be a fundamental crystal 14 36 DVDD P Digital Supply Voltage 1 8 V 18 PWRDWN A logic low this pin places the ADV7180 into power down mode 19 ELPF The recommended external loop filter must be connected to this ELPF as shown Figure 57 20 PVDD P PLL Supply Voltage 1 8 V 21 24 28 AGND G Ground for Analog Supply 22 TEST 0 This pin must be tied to DGND 23 29 30 1 to Ain3 Analog Video Input Channels 25 VREFP Internal Voltage Reference Output See Figure 57 for recommended output circuitry 26 VREFN Internal Voltage Reference Output See Figure 57 fo
29. 2 PDN override 00010000 10 61 3D Manual window control RW CKILLTHR 2 CKILLTHR 1 CKILLTHRIO 01110010 B2 65 41 Resample control RW SFL_INV 00000001 01 72 48 Gemstar Control 1 RW GDECEL 15 GDECEL 14 GDECEL 13 GDECEL 12 GDECEL 11 GDECEL 10 GDECELI9 GDECEL 8 00000000 00 73 49 Gemstar Control 2 RW GDECEL 7 GDECELI6 GDECEL 5 GDECELIA GDECEL 3 GDECEL 2 GDECEL 1 GDECEL 0 00000000 00 74 4A Gemstar Control 3 RW GDECOL 15 GDECOL 14 GDECOL 13 GDECOL 12 GDECOL 11 GDECOL 10 GDECOL 9 GDECOL 8 00000000 00 75 48 Gemstar Control 4 RW GDECOL 7 GDECOLI6 GDECOLI5 GDECOLIA GDECOLI3 GDECOL 2 GDECOL 1 GDECOLIO 00000000 00 76 4 Gemstar Control 5 RW GDE SEL OLD ADF GDECAD xxxx0000 00 77 4D CTIDNR Control 1 RW DNR EN AB 1 ABIO AB EN CTI EN 11101111 78 4E CTIDNR Control 2 RW CTI C THI7 CTI C THI6 CT C TH 5 CTI C THIA CTI CTI 21 C TH 1 CTI C THIO 00001000 08 80 50 CTIDNR Control 4 RW DNR_TH 7 DNR_TH 6 DNR THI5 DNR THIA DNR 21 DNR TH 1 DNR 01 00001000 08 81 51 Lockcount RW FSCLE SRLS COL 2 COL 1 COL O CIL 2 CIL 1 CIL O 00100100 24 82 52 CVBS TRIM RW CVBS IBIAS 3 CVBS IBIAS 2 CVBS IBIAS 1 CVBS IBIAS O 00001011 0 88 58 VS FIELD pin control RW ADC sampling control VS FIELD 00000000 00 89 59 General purpose outputs RW GPO ENABLE GPO 3 GPO 2 1 GPOIO 00000000 00 1
30. 63 235 Vblank Control 1 RW NVBIOLCM 1 NVBIOLCM O NVBIELCM 1 NVBIELCM O PVBIOLCM 1 PVBIOLCMIO PVBIELCM 1 PVBIELCMIO 01010101 55 236 EC Vblank Control 2 RW NVBIOCCM 1 NVBIECCM 1 PVBIOCCM 1 PVBIOCCMIO PVBIECCM 1 PVBIECCM 0 01010101 55 243 AFE CONTROL 1 RW AA FILT AA FILT EN 2 AA FILT EN 1 AA FILT 00000000 00 MAN OVR 244 F4 Drive strength RW DR STR 1 DR STR O DR STR C 1 DR STR 0 DR STR S 1 DR STR SI O 010101 15 248 F8 IF comp control RW FFILTSEL 2 IFFILTSEL 1 FFILTSEL O 00000000 00 249 F9 VS mode control RW VS COAST VS COAST EXTEND VS _ EXTEND VS _ 00000011 03 1 MODEIO MIN FREQ MAX FREQ 251 control RW PEAKING_ PEAKING PEAKING PEAKING PEAKING _ PEAKING PEAKING PEAKING 01000000 40 GAIN 7 GAIN 6 GAIN 5 41 GAIN 3 GAIN 2 GAIN 1 GAIN O 252 Coring threshold RW DNR_TH2 7 DNR_TH2 6 DNR TH2 5 2 4 DNR_TH2 3 DNR_TH2 2 DNR_TH2 1 DNR_TH2 0 00000100 04 1 This feature applies to the 48 lead 40 lead and 32 lead LFCSP only because VS or FIELD is shared on a single pin This feature applies to the 64 lead and 48 lead LOFP only Rev J Page 81 of 114 ADV7180 Table 106 Interrupt and VDP System Register Map Details User Sub Map
31. CCAP Gemstar CGMS GEMD_CLR 0 Do not clear and WSS data uses the 1 Clears GEMD_Q bit Mode 1 data slicer Reserved ojo SD_FIELD_CHNGD_CLR 0 Do not clear 1 Clears SD FIELD CHNGD Reserved Not used MPU STIM INTRQ CLR 0 Do not clear 1 Clears MPU STIM INTRQ Q bit 0x48 Interrupt Mask 2 CCAPD MSK 0 Masks CCAPD Q bit VBI System 2 Note that interrupt in read write 1 Unmasks CCAPD_Q bit VBI System 2 Register 0x46 for the CCAP Gemstar CGMS GEMD_MSK 0 Masks GEMD_Q bit VBI System 2 and WSS data uses the 1 Unmasks GEMD_Q bit VBI System 2 Mode 1 data slicer Reserved ojo Not used SD_FIELD_CHNGD_MSK 0 Masks SD FIELD CHNGD 1 Unmasks SD FIELD CHNGD bit Reserved 0 0 Not used MPU STIM INTRO MSK 0 Masks MPU_STIM_INTRQ_Q bit 1 Unmasks MPU_STIM_INTRQ_Q bit 0x49 Raw Status 3 SD OP 50Hz SD 60 Hz 50 Hz 0 SD 60 Hz signal output These bits are status read only frame rate at output 1 SD 50 Hz signal output bits only they cannot be cleared or masked SD V LOCK 0 SD vertical sync lock not established Register Ox4A is used for 1 SD vertical sync lock established this purpose SD H LOCK 0 SD horizontal sync lock not established 1 SD horizontal sync lock established Reserved x Not used SCM LOCK 0 SECAM lock not established 1 SECAM lock established Reserved x x x Not used Rev J Page 101 of 114 ADV7180
32. Composite LOFP and LFCSP Composite LOFP reserved LFCSP S Video LOFP and LFCSP S Video LOFP reserved LFCSP S Video LOFP reserved LFCSP YPrPb LOFP and LFCSP YPrPb LOFP reserved LFCSP Reserved LOFP and LFCSP Reserved LOFP and LFCSP Reserved LOFP and LFCSP Reserved LOFP and LFCSP 2 2 2 2 2 2 2 o o o o ojojo ojw 2 2 2 2 o o o o l 2 25 2 5 olo ojo o o 2 o 2 oj2 o 2 o 2 o 2 o o Reserved LOFP and LFCSP VID SEL 3 0 the VID SEL bits allow the user to select the input video standard Autodetect PAL B G H I D NTSC J no pedestal SECAM Autodetect PAL B G H I D NTSC M pedestal SECAM Autodetect PAL N pedestal NTSC J no pedestal SECAM Autodetect PAL N pedestal NTSC M pedestal SECAM NTSC J NTSCM PAL 60 NTSC 4 43 PAL B G H I D PAL N PAL B G H I D with pedestal PAL M without pedestal PALM PAL Combination N PAL Combination N with pedestal SECAM 2 2 2 2 2 2 1 2 olololo 2 2 2 2 ololo oi2 2 2 2 2 2 olo 2 2 oloi2 oi lo 2 o 2 o 2 o 2 o 2 o 23 o SECAM with pedestal Mandatory write required for Y C S Video mode Reg 0x58 0x04 see Reg 0x58 for bit description 0x01 Video selection Reserved Set to default SOPE Disable square pix
33. MAN ENABLE bit must be set to 1 For teletext system identification VDP assumes that if teletext is present in a video channel all the teletext lines comply with a single standard system Therefore the line programming using the VBI DATA Px Ny and VBI DATA Px registers identifies Rev J Page 56 of 114 ADV7180 VDP TTXT TYPE MAN ENABLE Enable Manual Selection of Teletext Type Address 0x60 2 User Sub Map Setting MAN ENABLE to 0 default the manual programming of the teletext type is disabled Setting VDP TTXT TYPE MAN ENABLE to 1 the manual programming of the teletext type is enabled VDP TTXT TYPE 1 0 Specify the Teletext Type Address 0x60 1 0 User Sub Map These bits specify the teletext type to be decoded These bits are functional only if VDP TTXT TYPE MAN ENABLE is set to 1 Table 72 TTXT TYPE MAN Function VDP TTXT TYPE MAN 1 0 625 50 PAL 525 60 NTSC 00 default Teletext ITU BT 653 Reserved 625 50 A 01 Teletext ITU BT 653 Teletext ITU BT 653 625 50 B WST 525 60 B 10 Teletext ITU BT 653 Teletext ITU BT 653 625 50 C 525 60 C or EIA516 NABTS 11 Teletext ITU BT 653 Teletext ITU BT 653 625 50 D 525 60 D VDP Ancillary Data Output Reading the data back via PC may not be feasible for VBI data standards with high data rates for example teletext An alternative is to place the sliced data in a packet i
34. NVBIECCM 1 0 NTSC VBI 0 0 Color output beginning Line 282 Controls the position even field color control 1 ITU R BT 470 compliant color output of first line that beginning Line 283 Cae Ru ane 1 0 VBI ends one line later Line 284 See 1 1 Color output beginning Line 285 NVBIOCCM 1 0 NTSC VBI 0 Color output beginning Line 20 Controls the position odd field color control o 1 ITU R BT 470 compliant color output of first line that beginning Line 21 outputs color after VBl on odd field in 1 0 Color output beginning Line 22 NTSC 1 1 Color output beginning Line 23 Rev J Page 98 of 114 ADV7180 Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes OxF3 AFE CONTROL 1 AA FILT _ 2 0 0 Antialiasing Filter 1 disabled AA FILT MAN OVR antialiasing filter enable must be enabled to change settings defined by INSEL 3 0 1 Antialiasing Filter 1 enabled 0 Antialiasing Filter 2 disabled 1 Antialiasing Filter 2 enabled 0 Antialiasing Filter 3 disabled 1 Antialiasing Filter 3 enabled AA FILT MAN OVR 0 Override disabled antialiasing filter override 1 Override enabled Reserved 4 Drive strength DR STR S 1 0 selects 010 Low drive strength 1x The low drive the dr
35. Not valid 6 18 GDECOL 10 Not valid 7 19 GDECOL 11 Not valid 8 20 GDECOL 12 Not valid 9 21 GDECOL 13 Not valid 10 22 GDECOL 14 Closed caption 11 23 GDECOL 15 Not valid 12 321 8 GDECEL 0 Not valid 13 322 9 GDECEL 1 Not valid 14 323 10 GDECEL 2 Not valid 15 324 11 GDECEL 3 Not valid 0 325 12 GDECEL 4 Not valid 1 326 13 GDECEL 5 Not valid 2 327 14 GDECEL 6 Not valid 3 328 15 GDECEL 7 Not valid 4 329 16 GDECEL 8 Not valid 5 330 17 GDECEL 9 Not valid 6 331 18 GDECEL 10 Not valid 7 332 19 GDECEL 11 Not valid 8 333 20 GDECEL 12 Not valid 9 334 21 GDECEL 13 Not valid 10 335 22 GDECEL 14 Closed caption 11 336 23 GDECEL 15 Not valid Rev J Page 74 of 114 ADV7180 Letterbox Detection Incoming video signals may conform to different aspect ratios 16 9 wide screen or 4 3 standard For certain transmissions in the wide screen format a digital sequence WSS is transmitted with the video signal If a WSS sequence is provided the aspect ratio of the video can be derived from the digitally decoded bits that WSS contains In the absence of a WSS sequence letterbox detection can be used to find wide screen signals The detection algorithm examines the active video content of lines at the start and end of a field If black lines are detected this may indicate that the currently shown picture is in wide screen format The active video content luminance magnitude over a line
36. Table 2 4 6 Chenges to Table 29 oec ien needs 25 Ghani ges to Figure 33 eee pte X ivi RE 44 Changes to Subaddress 0x0A Notes Table 104 81 Changes to Ordering Guide sss 110 Rev J Page 3 of 114 ADV7180 4 09 Rev B to Rev C Changes to Features Section sse Changes to Absolute Maximum Ratings Table 7 Changes to Figure 7 and Table 8 EPAD Addition Added Power On RESET Section sse Changes to MAN MUX EN Manual Input Muxing Enable Address 0xC4 7 Section and Table 12 17 Changes to Identification Section 21 Added Table 16 Renumbered Sequentially 21 Changes to Table 2 Red 23 Changes to CIL 2 0 Count Into Lock Address 0x51 2 0 Section and COL 2 0 Count Out of Lock Address 0x51 5 3 Section cce DRIED TERRE NS 25 Changes to Table 32 and Table 33 2 30 Changes to Table 34 2 32 Changes to Table 42 3235 Changes to Table 52 5 a tenete en biete 38 Changes to Table 53 and Table 56 sss 39 Changes to Table 61 and Figure 32 sss 43 Added SQPE Square Pixel Mode Address 0x01 2 Section 44 Changes to NEWAVMODE New AV Mode Address 0x31 4 J 44 Changes to Figure 45 Changes to NFTOG 4 0 NTSC Field Toggle Address OxE7 4 0 Secti
37. The NTSC and PAL configuration registers allow the user to customize the comb filter operation depending on which video standard is detected by autodetection or selected by manual programming The NSFSEL 1 0 control selects how much of the overall signal bandwidth is fed to the combs A narrow split filter selection results in better performance on diagonal lines but more dot crawl in the final output image The opposite is true for selecting a wide bandwidth split filter Table 53 NSFSEL Function NSFSEL 1 0 Description 00 default Narrow 01 Medium 10 Medium 11 Wide CTAPSN 1 0 Chroma Comb Taps NTSC Address 0x38 7 6 Table 54 CTAPSN Function CTAPSN 1 0 Description 00 Do not use 01 NTSC chroma comb adapts three lines three taps to two lines two taps 10 default NTSC chroma comb adapts five lines five taps to three lines three taps 11 NTSC chroma comb adapts five lines five taps to four lines four taps CCMN 2 0 Chroma Comb Mode NTSC Address 0x38 5 3 Table 55 CCMN Function CCMN 2 0 Description Configuration 000 default Adaptive comb mode Adaptive three line chroma comb for CTAPSN 01 Adaptive four line chroma comb for CTAPSN 10 Adaptive five line chroma comb for CTAPSN 11 100 Disable chroma comb 101 Fixed chroma comb top lines of line memory Fixed two line chroma comb for CTAPSN 01 Fixed three line chroma comb for CTAPSN 10 Fixed four
38. The VSBHO and VSBHE bits select the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high or low When VSBHO is 0 default the VS pin goes high in the middle of a line of video odd field When VSBHO is 1 the VS pin changes state at the start of a line odd field VSBHE VS Begin Horizontal Position Even Address 0x32 6 The VSBHO and VSBHE bits select the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to only change state when HS is high or low When VSBHE is 0 default the VS pin goes high in the middle of a line of video even field When VSBHE is 1 the VS pin changes state at the start ofa line even field VSEHO VS End Horizontal Position Odd Address 0x33 7 The VSEHO and VSEHE bits select the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high or low When VSEHO is 0 default the VS pin goes low inactive in the middle of a line of video odd field When VSEHO is 1 the VS pin changes state at the start ofa line odd field VSEHE VS End Horizontal Position Even Address 0x33 6 The VSEHO and VSEHE bits select the position within a line at which the VS pin not the bit in the AV code becomes activ
39. When SWPC is 0 default no swapping is allowed When SWPC is 1 the Cr and Cb values can be swapped PAD SEL 2 0 LLC Output Selection Address 0x8F 6 4 The following PC write allows the user to select between LLC nominally at 27 MHz and LLC nominally at 13 5 MHz The LLC signal is useful for LLC compatible wide bus 16 bit output modes See the OF SEL 3 0 Output Format Selection Address 0 03 5 2 section for additional information The LLC signal and data on the data bus are synchronized By default the rising edge of LLC LLC is aligned with the Y data the falling edge occurs when the data bus holds C data The polarity of the clock and therefore the Y C assignments to the clock edges can be altered by using the polarity LLC pin When LLC SEL is 000 the output is nominally 27 MHz LLC on the LLC pin default When LLC PAD SEL is 101 the output is nominally 13 5 MHz LLC on the LLC pin Data Port Pins P 15 0 Format and Mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Video Out 8 Bit 4 2 2 YCrCb 7 0 OUT Video Out 16 Bit 4 2 2 Y 7 0 OUT CrCb 7 0 OUT Table 101 48 Lead 40 Lead and 32 Lead Devices P7 to PO Output Input Pin Mapping Data Port Pins P 7 0 Format and Mode 7 6 5 4 3 2 1 0 Video Out 8 Bit 4 2 2 YCrCb 7 0 OUT Table 102 ADV7180 Standard Definition Pixel Port Modes 64 Lead LQF
40. and SFL VBI EN allows VBI data 0 All lines filtered and scaled Line 1 to Line 21 to be 1 Only active video region filtered passed through with only a minimum amount of filtering performed 0x04 Extended Range allows the user 0 16 lt Y lt 235 16 x C P lt 240 ITU R BT 656 output control to select the range of output values can be 1 1 lt Y lt 254 1 lt C P lt 254 Extended range ITU R BT 656 compliant or can fill the whole accessible number range EN_SFL_PIN 0 SFL output is disabled SFL output 1 SFL information output on the SFL pin enables encoder and decoder to be connected directly BL_C_VBI blank chroma 0 Decode and output color During VBI during VBI if set it enables 1 Blank Cr and Cb data in the region to be passed through the decoder undistorted TIM OE timing signals 0 HS VS FIELD three stated Controlled by TOD output enable 1 HS VS FIELD forced active Reserved x x Reserved 1 BT 656 4 allows the 0 ITU R BT 656 3 compatible user to select an output 1 ITU R BT 656 4 compatible mode compatible with ITU R BT 656 3 4 Rev J 85 of 114 ADV7180 Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 0x07 Autodetect AD PAL EN PAL B D I G H 0 Disable enable
41. current and in turn causing more internal digital noise Shorter traces reduce the possibility of reflections Adding a 30 to 50 O series resistor can suppress reflections reduce EMI and reduce the current spikes inside the ADV7180 If series resistors are used place them as close as possible to the ADV7180 pins However try not to add vias or extra length to the output trace to place the resistors closer If possible limit the capacitance that each of the digital outputs drives to less than 15 pF This can easily be accomplished by keeping traces short and by connecting the outputs to only one device Loading the outputs with excessive capacitance increases the current transients inside the ADV7180 creating more digital noise on its power supplies The 40 lead and 32 lead LFCSP have an exposed metal paddle on the bottom of the package This paddle must be soldered to PCB ground for proper heat dissipation and for noise and mechanical strength benefits DIGITAL INPUTS The digital inputs on the ADV7180 are designed to work with 1 8 V to 3 3 V signals and are not tolerant of 5 V signals Extra components are needed if 5 V logic signals are required to be applied to the decoder Rev J Page 107 of 114 ADV7180 TYPICAL CIRCUIT CONNECTION Examples of how to connect the 40 lead LFCSP 64 lead LQFP 48 lead LQFP and 32 lead LFCSP video decoders are shown in Figure 57 Figure 58 Figure 59 and Figure 60 For a detailed schemat
42. output by the ADV7180 in 8 bit format SECONDARY DATA IDENTIFICATION USER DATA 4 OR 8 WORDS Figure 52 Gemstar and CCAP Embedded Data Packet Generic 05700 043 Table 86 Generic Data Output Packet Byte DI9 DI8 DI7 DI6 D 5 D 4 D 2 D 1 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 2X Line 3 0 0 0 SDID 5 EP EP 0 0 0 0 DC 1 DC 0 0 0 Data count DC 6 EP EP 0 0 Word1 7 4 0 0 User data words 7 EP EP 0 0 Word 1 3 0 0 0 User data words 8 EP EP 0 0 Word2 7 4 0 0 User data words 9 EP EP 0 0 Word2 3 0 0 0 User data words 10 EP EP 0 0 Word3 7 4 0 0 User data words 11 EP EP 0 0 Word3 3 0 0 0 User data words 12 EP EP 0 0 Word4 7 4 0 0 User data words 13 EP EP 0 0 Word4 3 0 0 0 User data words 14 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 0 0 Checksum Table 87 Data Byte Allocation User Data Words 2x Raw Information Bytes Retrieved from the Video Line GDECAD Including Padding Padding Bytes DC 1 0 1 4 0 8 0 10 1 4 1 4 0 01 0 2 0 4 0 01 0 2 1 4 2 01 Rev J Page 69 of 114 ADV7180 Gemstar Bit Names The following are the Gemstar bit names e DID The data identification value is 0x140 10 bit value Care is taken so that in 8 bit systems the two LSBs do not car
43. 0 The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV Code FF 00 00 XY see Figure 37 HSE is set to 00000000000b which is 0 LLC clock cycles from count 0 The default value of HSE 10 0 is 00 indicating that the HS pulse ends 0 pixels after the falling edge of HS For example e To shift the HS toward active video by 20 LLCs add 20 LLCs to both HSB and HSE that is HSB 10 0 00000010110 HSE 10 0 00000010100 e To shift the HS away from active video by 20 LLCs add 1696 LLCs to both HSB and HSE for NTSC that is HSB 10 0 11010100010 HSE 10 0 11010100000 Therefore 1696 is derived from the NTSC total number of pixels 1716 e move 20 LLCs away from active video subtract 20 from 1716 and add the result in binary to both HSB 10 0 and HSE 10 0 PHS Polarity HS Address 0x37 7 The polarity of the HS pin can be inverted using the PHS bit When PHS is 0 default HS is active low When PHS is 1 HS is active high Characteristic HS to Active Video HS Begin Adjust HS End Adjust LLC Clock Cycles C Active Video Samples Total LLC Clock Standard HSB 10 0 Default HSE 10 0 Default in Figure 37 Default Line Din Figure 37 Cycles E in Figure 37 NTSC 00000000010b 00000000000b 272 720Y 720C 1440 1716 PAL 00000000010b 00000000000b 284 720Y 720C 1440 1728
44. 010 Narrow control the signal bandwidth O0 1 Medium that is fed to the comb 0 Wid filters PAL 1 ide 1 1 Widest NSFSEL 1 0 controls 010 Narrow the signal bandwidth Medium that is fed to the comb 0 filters NTSC 1 edium 1 1 Wide Reserved 1 1 1 1 Set as default 0x1D ADI Control 2 Reserved 0 0 x Set to default EN28XTAL 0 Reserved do not use 1 Use 28 MHz crystal TRI LLC 0 LLC pin active 1 LLC pin three stated Rev J Page 89 of 114 ADV7180 Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 0x27 Pixel delay LTA 1 0 luma timing 0 0 Nodelay CVBS mode control adjust allows the user to 0 1 Luma one clock 37 ns late LTA 1 0 00b specify a timing difference S Video mode between chroma and 1 O Luma two clocks 74 ns early LTA 1 0 016 luma samples 1 1 Luma one clock 37 ns early YPrPb mode LTA 1 0 01b Reserved 0 Setto 0 CTA 2 0 chroma 1 Not a valid setting CVBS mode timing adjust allows olola Chroma two pixels early CTA 2 0 011b a specified timing ol1lo Ch ixel S Video mode difference between roma one pixel early CTA 2 0 101b the luma and chroma 9 p p No delay YPrPb mode samples 1 01 0 Chroma one pixel late CTA 2 0 110b 1 0 1 Chroma
45. 101 Kill at 1596 Kill at 1696 110 Kill at 3296 Kill at 3296 111 Reserved for Analog Devices internal use only do not select Rev J Page 39 of 114 ADV7180 CHROMA TRANSIENT IMPROVEMENT CTI The signal bandwidth allocated for chroma is typically much smaller than that for luminance In the past this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance The uneven bandwidth however may lead to visual artifacts in sharp color transitions At the border of two bars of color both components luma and chroma change at the same time see Figure 31 Due to the higher bandwidth the signal transition of the luma component is usually much sharper than that of the chroma component The color edge is not sharp and can be blurred in the worst case over several pixels LUMA SIGNAL WITH A TRANSITION ACCOMPANIED LUMA SIGNAL BY A CHROMA TRANSITION ORIGINAL SLOW CHROMA Pr parri TRANSITION PRIOR TO CTI SHARPENED CHROMA 8 TRANSITION AT THE 8 OUTPUT OF CTI Figure 31 CTI Luma Chroma Transition The chroma transient improvement block examines the input video data It detects transitions of chroma and can be programmed to create steeper chroma edges in an attempt to artificially restore lost color bandwidth The CTI block however operates only on edges above a certain threshold to ensure that noise is not em
46. 11 0 LMG 11 0 Read Write Description LAGT 1 0 Description 00 Slow TC 2 sec 01 Medium TC 1 sec 10 Fast TC 0 2 sec 11 default Adaptive LMG 11 0 x Write Manual gain for luma path LG 11 0 x Read Actual used gain LMG 11 0 Luma 1 LumaCalibrationFactor where LMG 11 0 is a decimal value between 1024 and 4095 Calculation of the Luma Calibration Factor 1 Using a video source set content to a grey field and apply as a standard CVBS signal to the CVBS input of the board 2 Using an oscilloscope measure the signal at CVBS input to ensure that its sync depth color burst and luma are at the standard levels 3 Connect the output parallel pixel bus of the ADV7180 to a backend system that has unity gain and monitor output voltage 4 Measure the luma level correctly from the black level Turn off the Luma AGC and manually change the value of the luma gain control register LMG 11 0 until the output luma level matches the input measured in Step 2 This value in decimal is the luma calibration factor Rev J Page 37 of 114 ADV7180 BETACAM Enable Betacam Levels Address 0x01 5 If YPrPb data is routed through the ADV7180 the automatic gain control modes can target different video input levels as outlined in Table 44 The BETACAM bit is valid only if the input mode is YPrPb component The BETACAM bit sets the target value for AGC operation A revi
47. 140008 22 sl 24 i OUTPUT 005 VIDEO 0 PVBEG 4 0 0x05 PVEND 4 0 0x04 PFTOG 4 0 0x03 QU uuum FIELD 2 13101 311 312 313 314 315 316 317 318 319 320 3211322 335 OUTPUT P775 VIDEO 1 i IL TL n p m mi URL eg Te PVBEG 4 0 0x05 PVEND 4 0 0x04 2 PFTOG 4 0 0x03 Figure 43 PAL Default ITU R BT 656 the Polarity of H V and F Is Embedded in the Data 05700 034 Rev J Page 51 of 114 ADV7180 OUTPUT e s VIDEO H E ps 162211 16231 624 625 FIELD 1 11213 lais i617 i8 dos 1 iml Bil 2 i DS OUTPUT vs OUTPUT FIELD OUTPUT output 077 VIDEO HS OUTPUT vs OUTPUT FIELD OUTPUT FIELD 2 j 0 PVBEG 4 0 0x01 PVEND 4 0 0x04 7 2 0000 PFTOG 4 0 0x06 1310 311 312 313 314 315 316 317 318 319 320 321 322 1323 i a rr PVBEG 4 0 0x01 PVEND A 0 0x04 lavi 05700 035 PFTOG 4 0 0x06 Figure 44 PAL Typical VS FIELD Positions Using the Register Writes Shown in Table 66 Table 66 User Settings for PAL See Figure 44 4 0 PAL VSYNC Begin Address 0 8 4 0 The default value of PVBE
48. 4 0 0 User data words 9 EP EP 0 0 CCAP Word2 3 0 0 0 User data words 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 95 PAL CCAP Data Full Byte Mode Byte D 9 D 8 D 7 DI6 D 5 D 4 D 3 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EF 0 1 0 1 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 CCAP Word1 7 0 0 0 User data words 7 CCAP Word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum NTSC CCAP Data See the GDECEL 15 0 Gemstar Decoding Even Lines Half byte output mode is selected by setting GDECAD to 0 and Address 0x48 7 0 Address 0x49 7 0 section andthe the full byte mode is enabled by setting GDECAD to 1 See the GDECOL 15 0 Gemstar Decoding Odd Lines GDECAD Gemstar Decode Ancillary Data Format Address Address Address section 0x4C 0 section The data packet formats are shown in Table 92 GDECEL 15 0 Gemstar Decoding Even Lines and Table 93 Only closed caption data can be embedded in the Address 0x48 7 0 Address 0x49 7 0 output data stream The 16 bits of GDECEL 15 0 are interpreted as a collection of NTSC closed caption data is sliced on Line 21 of even and odd 16 individual line decode enable signals
49. 75 e EP Even parity for Bit B8 to Bit B2 The EP of the parity bit is set so that an even number of 1s are in Bit B8 to Bit B2 including the parity bit D8 CS Checksum word The CS word is used to increase confidence of the integrity of the ancillary data packet from the DID SDID and DC through user data words It consists of 10 bits that include the following a 9 bit calculated value and B9 as the inverse of B8 The checksum value B8 to BO is equal to the nine LSBs of the EP The MSB B9 is the inverse of EP This ensures that restricted Code 0x00 and Code OxFF do not occur LINE NUMBER 9 0 The line number of the line that immediately precedes the ancillary data packet The line number is from the numbering system in ITU R BT 470 The line number runs from 1 to 625 in a 625 line system and from 1 to 263 in a 525 line system Note that due to the vertical delay through the comb filters the line number on which the packet is output differs from the line number on which the VBI data was sliced Data count The data count specifies the number of UDWs in the ancillary stream for the standard The total number of user data words is four times the data count Padding words can be introduced to make the total number of UDWs divisible by 4 sum of the nine LSBs of the DID SDID and DC and all UDWs in the packet Prior to the start of the
50. 8 223 DF ST Noise Readback 2 R ST NOISE 7 ST NOISE 6 ST NOISE 5 5 NOISE A ST NOISE 3 ST NOISE 2 ST NOISE 1 ST NOISE O 224 0 Reserved 225 SDOffset Cb RW SD OFF Cb 7 SD OFF SD OFF 51 50 OFF 50 OFF 3 SD OFF 21 SD OFF Cb 1 SD OFF CbI0 10000000 80 226 2 SD Offset Cr RW SD OFF Cr 7 SD OFF Cr 6 SD OFF Cr 5 SD OFF Cr 4 50 OFF Cr 3 SD OFF Cr 2 SD OFF Cr 1 SD OFF Cr 0 10000000 80 227 SDSaturation Cb RW SD SAT Cb 7 SD SAT Cb 6 SD SAT Cb 5 50 SAT 50 SAT CbI3 SD SAT 21 SD SAT CbI1 SD SAT 10000000 80 228 4 50 Saturation Cr RW SD SAT Cr 7 SD SAT Cr 6 SD SAT 5 SD SAT Cr 4 50 SAT Ci 3 SD SAT 112 SD SAT Ci 1 SD SAT Cr 0 10000000 80 229 5 NTSCV bit begin RW NVBEGDELO NVBEGDELE NVBEGSIGN NVBEG 4 NVBEGI3 NVBEG 2 NVBEG 1 NVBEG O 00100101 25 230 E6 NTSCV bit end RW NVENDDELO NVENDDELE NVENDSIGN NVEND 4 NVENDI3 NVEND 2 NVEND 1 NVEND 0 00000100 04 231 E7 NTSCF bit toggle RW NFTOGDELO NFTOGDELE NFTOGSIGN NFTOG 4 NFTOG 3 NFTOG 2 NFTOG 1 0 01100011 63 232 E8 PALV bit begin RW PVBEGDELO PVBEGDELE PVBEGSIGN PVBEG 4 PVBEG 3 PVBEG 2 PVBEG 1 PVBEGI O 01100101 65 233 9 PALV bit end RW PVENDDELO PVENDDELE PVENDSIGN PVEND 4 PVEND 3 PVEND 2 PVEND 1 PVEND 0 00010100 14 234 EA PALF bit toggle RW PFTOGDELO PFTOGDELE PFTOGSIGN PFTOG 4 PFTOG 3 PFTOG 2 PFTOG 1 PFTOG O 01100011
51. AV codes can be inserted as per ITU R BT 656 Rev J Page 26 of 114 Chroma digital fine clamp This block uses a high precision algorithm to clamp the video signal Chroma demodulation This block employs a color subcarrier fsc recovery unit to regenerate the color subcarrier for any modulated chroma scheme The demodulation block then performs an AM demodulation for PAL and NTSC and an FM demodulation for SECAM Chroma filter This block contains a chroma decimation filter CAA with a fixed response and some shaping filters CSH that have selectable responses Chroma gain control AGC can operate on several different modes including gain based on the color subcarrier amplitude gain based on the depth of the horizontal sync pulse on the luma channel or fixed manual gain Chroma resample The chroma data is digitally resampled to keep it perfectly aligned with the luma data The resampling is done to correct for static and dynamic line length errors of the incoming video signal Chroma 2D comb The 2D five line superadaptive comb filter provides high quality Y C separation in case the input signal is CVBS AV code insertion At this point the demodulated chroma Cr and Cb signal is merged with the retrieved luma values AV codes be inserted as per ITU R 656 ADV7180 SYNC PROCESSING The ADV7180 extracts syncs embedded in the analog input video signal There is currently no support for external HS VS in
52. EP 0 0 CCAP Word 1 3 0 0 0 User data words 8 EP EP 0 0 CCAP Word2 7 4 0 0 User data words 9 0 0 CCAP Word2 3 0 0 0 User data words 10 CSI8 Cs8 csi7 csie 451 fcs 2 csm csio Checksum Table 93 NTSC CCAP Data Full Byte Mode Byte DI9 D 8 D 7 DI6 D 5 D 4 D 3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 1 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 CCAP Word1 7 0 0 0 User data words 7 CCAP Word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Rev J 72 of 114 ADV7180 Table 94 PAL CCAP Data Half Byte Mode Byte DI9 DI8 DI7 DI6 D 5 D 4 D 3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 0 1 0 1 0 0 0 SDID 5 0 0 0 0 0 1 0 0 Data count 6 EP EP 0 0 CCAP Word1 7 4 0 0 User data words 7 EP EP 0 0 CCAP Word1 3 0 0 0 User data words 8 0 0 CCAP Word2 7
53. Each bit refers to a line fields The corresponding enable bit must be set high See the of video in an even field Setting the bit enables the decoder block GDECAD Gemstar Decode Ancillary Data Format Address trying to find Gemstar or closed caption compatible data on 0x4C 0 section and the GDECOL 15 0 Gemstar Decoding that particular line Setting the bit to 0 prevents the decoder Odd Lines Address 0x4A 7 0 Address 0x4B 7 0 section from trying to retrieve data See Table 96 and Table 97 PAL CCAP Data To retrieve closed caption data services on NTSC Line 284 Half byte output mode is selected by setting GDECAD to 0 and GDECEL 11 must be set full byte output mode is selected by setting GDECAD to 1 See To retrieve closed caption data services on PAL Line 335 the GDECAD Gemstar Decode Ancillary Data Format GDECEL 14 must be set Address 0x4C 0 section Table 94 and Table 95 list the The default value of GDECEL 15 0 is 0x0000 This setting bytes of the data packet instructs the decoder not to attempt to decode Gemstar or Only closed caption data be embedded in the output data CCAP data from any line in the even field Enable Gemstar stream PAL closed caption data is sliced from Line 22 and slicing only on lines where VBI data is expected Line 335 The corresponding enable bits must be set Rev J Page 73 of 114 ADV7180 Table 96 NTSC Line Enable Bits and Corresponding Line Numbering Line Number
54. ITU R BT 656 lines after Icounr rollover to set V low VENDSIGN 0 Set to low when manual programming 1 Not suitable for user programming VENDDELE delay V bit 0 No delay going low by one line 1 Additional delay by one line relative to NVEND even field VENDDELO delay V bit 0 No delay going low by one line 1 Additional delay by one line relative to NVEND odd field OxE7 NTSC F bit FTOG 4 0 number of 1 1 NTSC default toggle ines after lcouwr rollover to toggle F signal FTOGSIGN 0 Set to low when manual programming 1 Not suitable for user programming FTOGDELE delay 0 No delay F transition by one line 1 Additional delay by one line relative to NFTOG even field FTOGDELO delay 0 No delay F transition by one line 1 Additional delay by one line relative to NFTOG odd field OxE8 PALV bit begin PVBEG 4 0 number of 0 0 1 O 1 PAL default ITU R BT 656 lines after Icount rollover to set V high PVBEGSIGN 0 Set to low when manual programming 1 Not suitable for user programming PVBEGDELE delay V bit 0 No delay going high by one line 1 Additional delay by one line relative to PVBEG even field PVBEGDELO delay V bit 0 No delay going high by one line 1 Additional delay by one line relative to PVBEG odd field Rev J Page 97 of 114 ADV7180
55. Interval Time Codes VITC Not applicable Wide Screen Signaling WSS ITU R BT 1119 1 ETSI EN 300294 Closed Captioning CCAP Not applicable The VBI data standard that the VDP decodes on a particular line of incoming video has been set by default as described in Table 69 This can be overridden manually and any VBI data can be decoded on any line The details of manual programming are described in Table 70 VDP Default Configuration The VDP can decode different VBI data standards on a line to line basis The various standards supported by default on different lines of VBI are explained in Table 69 VDP Manual Configuration MAN LINE PGM Enable Manual Line Programming of VBI Standards Address 0x64 7 User Sub Map The user can configure the VDP to decode different standards on a line to line basis through manual line programming For this the user must set the LINE PGM bit The user must write into all the line programming registers DATA Px Ny and VBI DATA Px see Register 0x64 to Register 0x77 in Table 108 When MAN LINE PGM to 0 default is set the VDP decodes default standards on lines as shown in Table 69 When MAN LINE PGM to 1 is set the VBI standards to be decoded are manually programmed VBI DATA Px Ny 3 0 VBI DATA Px 3 0 VBI Standard to be Decoded on Line X for PAL Line Y for NTSC Address 0x64 to Address 0x77 User Sub Map These are related 4 bit clusters in Register 0x64 to R
56. Line 3 0 ITU R BT 470 Enable Bit Comment 0 10 GDECOL 0 Gemstar 1 11 GDECOL 1 Gemstar 2 12 GDECOL 2 Gemstar 3 13 GDECOL 3 Gemstar 4 14 GDECOL 4 Gemstar 5 15 GDECOL 5 Gemstar 6 16 GDECOL 6 Gemstar 7 17 GDECOL 7 Gemstar 8 18 GDECOL 8 Gemstar 9 19 GDECOL 9 Gemstar 10 20 GDECOL 10 Gemstar 11 21 GDECOL 11 Gemstar or closed caption 12 22 GDECOL 12 Gemstar 13 23 GDECOL 13 Gemstar 14 24 GDECOL 14 Gemstar 15 25 GDECOL 15 Gemstar 0 273 10 GDECEL 0 Gemstar 1 274 11 GDECEL 1 Gemstar 2 275 12 GDECEL 2 Gemstar 3 276 13 GDECEL 3 Gemstar 4 277 14 GDECEL 4 Gemstar 5 278 15 GDECEL 5 Gemstar 6 279 16 GDECEL 6 Gemstar 7 280 17 GDECEL 7 Gemstar 8 281 18 GDECEL 8 Gemstar 9 282 19 GDECEL 9 Gemstar 10 283 20 GDECEL 10 Gemstar 11 284 21 GDECEL 1 1 Gemstar or closed caption 12 285 22 GDECEL 12 Gemstar 13 286 23 GDECEL 13 Gemstar 14 287 24 GDECEL 14 Gemstar 15 288 25 GDECEL 15 Gemstar GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 The decoded data from Gemstar compatible transmissions or closed caption compatible transmissions is inserted into the horizontal blanking period of the respective line of video A potential problem can arise if the retrieved data bytes have a value of 0x00 or OxFE In an ITU R BT 656 compatible data stream these values are reserved and used only to form a fixed preamble The GDECAD bit allows the data to be inserted into
57. MVCS T3 Macrovision color striping protection conforms to Type 3 if high Type 2 if low 2 MV PS DET Detected Macrovision pseudo sync pulses 3 MV AGCDET Detected Macrovision AGC pulses 4 LL NSTD Line length is nonstandard 5 FSC NSTD fsc frequency is nonstandard 6 Reserved 7 Reserved STATUS 3 Status 3 7 0 Address 0x13 7 0 Table 23 Status 3 Function AD RESULT 2 0 Description 000 NTSC M J 001 NTSC 4 43 010 PALM 011 PAL 60 100 PAL B G H I D 101 SECAM 110 PAL Combination N 111 SECAM 525 Status 3 7 0 Bit Name Description 0 INST HLOCK Horizontal lock indicator instantaneous 1 GEMD Gemstar detect 2 SD OP 50Hz Flags whether 50 Hz or 60 Hz is present at output 3 Reserved Reserved for future use 4 FREE RUN ACT ADV7180 outputs a blue screen see the DEF VAL EN Default Value Enable Address OxOC O section 5 STD FLD LEN Field length is correct for currently selected video standard 6 Interlaced Interlaced video detected field sequence found 7 PAL SW LOCK Reliable sequence of swinging bursts detected Rev J Page 25 of 114 ADV7180 VIDEO PROCESSOR STANDARD DEFINITION PROCESSOR MACROVISION VBI DATA STANDARD DETECTION RECOVERY AUTODETECTION DIGITIZED CVBS DIGITIZED Y YC LUMA FILTER SYNC EXTRACT DIGITIZED CVBS DIGITIZED C YC DIGITAL RECOVERY CONTROL PREDICTOR LUMA GAIN LINE LENGTH SLLC CONTROL LUMA LUMA RESAMPLE
58. PROCESSING BLOCK XTAL1 XTAL QO 8 BIT DIGITAL PIXEL DATA PROCESSING ADC BLOCK u P7 TO PO 2 5 2D COMB ANALOG VIDEO 4 w a Q Hs INPUTS 4 VSEIELD 5 05700 060 SCLK SDATA ALSB RESET PWRDWN Figure 5 48 Lead LQFP Functional Block Diagram Rev J Page 7 of 114 ADV7180 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Avpp 1 71 V to 1 89 V Dvpp 1 65 V to 2 0 V Dvppio 1 62 V to 3 6 V 1 65 V to 2 0 V specified at operating temperature range unless otherwise noted Table 3 Parameter Symbol Test Conditions Comments Min Typ Max Unit STATIC PERFORMANCE Resolution Each ADC N 10 Bits Integral Nonlinearity INL BSL in CVBS mode 2 LSB Differential Nonlinearity DNL CVBS mode 0 6 0 6 LSB DIGITAL INPUTS Input High Voltage DVDDIO 3 3 V Vin 2 V Input High Voltage DVDDIO 1 8 V 1 2 V Input Low Voltage DVDDIO 3 3 V 0 8 V Input Low Voltage DVDDIO 1 8 V 0 4 V Crystal Inputs Vin 12 V Vit 0 4 V Input Current 10 10 uA Input Current SDA SCLK 10 15 uA Input Current PWRDWN 10 48 uA Input Capacitance 10 pF DIGITAL OUTPUTS Output High Voltage DVDDIO 3 3 V Vou Isour 0 4 mA 24 V Output High Voltage DVDDIO 1 8 V Von Isource 0 4 mA 1 4 V Output Low Voltage DVDDIO 3 3 V Vo Isink 3 2 mA 0 4 V Output Low Voltage DVDDIO 1 8 V Vo Isink 1 6 mA 0 2 V High Impedance Leakage Current 10 uA Output C
59. Port Serial Clock Input The maximum clock rate is 400 kHz 63 FIELD Field Synchronization Output Signal 64 VS Vertical Synchronization Output Signal Rev J Page 16 of 114 48 LEAD LQFP ADV7180 a al ow BG oaj o 2 0 amp amp o dau z ITIS gt 48 47 461 45 44 43 42 41 401 39 38137 DGND 1 36 peus DVDDIO 2 25 Am5 SFL 3 34 Ajn4 DVDDIO 4 Ain pula i ADV7180 32 AGND GPOD 6 31 AVDD 7 TOP VIEW 39 VFEFN N Pe Not to Scale VREFP P5 9 28 AGND 10 27 2 1 26 2 2 25 PVDD amp NC NO CONNECT 13 14 151 16 17 18 19 20 21 221 23 24 5 2 232 g Exag a gt lt c 4 z Figure 11 48 Lead LQFP Pin Configuration Table 12 48 Lead LQFP Pin Function Descriptions Pin No Mnemonic Type Description 1 13 19 43 DGND G Digital Ground 2 4 DVDDIO P Digital I O Supply Voltage 1 8 V to 3 3 V 3 SFL Subcarrier Frequency Lock This pin contains a serial output stream that be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder 5 6 41 42 GPOO GPO3 General Purpose Outputs These pins can be configured via C to allow control of external devices 7 to 12 20 22 P7 to P2 P1 PO Video Pixel Output Port
60. Rev J Page 108 of 114 KEEP CLOSE TO THE ADV7180 AND ON THE SAME SIDE OF PCB AS THE ADV7180 05700 048 ADV7180 ANALOG INPUT 1 THE SUGGESTED INPUT ARRANGEMENT Y ODE IS AS SEEN ON THE EVAL BOARD AND IS 1 a 4 DIRECTLY SUPPORTED BY INSEL lt IN 360 390 Dypp_1 8V Dypp_1 8V ANALOG INPUT 2 CVBS 0 1uF L e 360 0 1 10 0 1 10nF 390 ANALOG INPUT 3 Dyppio 3 3V L Avpp 1 8V YC Y 0 1uF T z L Ans 360 0 1 0 1 390 Dyppio 3 3V Pypp 1 8V 10nF 10nF ANALOG INPUT Cr 0 1 10nF 0 1 l lt 1 0 1uF 10nF 360 i 390 P 0 7 ANALOG INPUT 5 5 0 1pF 8 BIT 16 BIT lt Ans Awi gt PO DATA BUS OUTPUT MODE OUTPUT MODE 360 P 0 7 NIA CbCr ae Aw gt 8 P2 P 8 15 656 601 YCbCr Y ANALOG INPUT 6 S18 P3 T Aw gt YC C 0 1uF d P 8 15 I e 215 Ps 360 e AwS gt ADV7180BSTZ gt LQFP 64 4 KEEP VREFN AND VREFP CAPACITOR AS CLOSE AS J61 POSSIBLE TO THE ADV7180 AND ON THE SAME SIDE OF THE AS THE ADV7180 250 Psd 0 1pF INT GPO3 GPO2 GPO1 GPOO FIELD lt lt us amp sr Pypp_1 8V ae 27 28 33 28 33 EXTERNAL __ 2 O41 22 44 COOP FILTER 47pF 1 28 63636MHz CI 47pF POWER DOWN gt Dyppio 3 3V 4kQ 1 1 69kQ TIE ADDRESS 42 TIE LOW PC ADDRESS 40 KEEP CLOSE TO THE ADV7180 AND ON THE SAME SIDE OF PCB AS THE ADV
61. The ADV7180 can configure itself to support PAL B D I G H PAL M PAL N PAL Combination NTSC M NTSC J SECAM 50 Hz 60 Hz NTSC 4 43 and PAL 60 GENERAL SETUP Video Standard Selection The VID SEL 3 0 bits Address 0x00 7 4 allow the user to force the digital core into a specific video standard Under normal circumstances this is not necessary The VID SEL 3 0 bits default to an autodetection mode that supports PAL NTSC SECAM and variants thereof Autodetection of SD Modes To guide the autodetect system of the ADV7180 individual enable bits are provided for each of the supported video standards Setting the relevant bit to 0 inhibits the standard from being detected automatically Instead the system chooses the closest of the remaining enabled standards The results of the autodetection block can be read back via the status registers see the Global Status Register section for more information VID SEL 3 0 Address 0x00 7 4 Table 24 VID SEL Function VID SEL 3 0 Description 0000 default Autodetect PAL B G H I D NTSC J no pedestal SECAM 0001 Autodetect PAL B G H I D NTSC M pedestal SECAM 0010 Autodetect PAL N pedestal NTSC J no pedestal SECAM 0011 Autodetect PAL N pedestal NTSC M pedestal SECAM 0100 NTSC J 0101 NTSC 0110 PAL 60 0111 NTSC 4 43 1000 PAL B G H I D 1001 PAL N PAL B G H I D with pedestal 1010 PAL M without pedestal 1011 PAL M 1100 PAL
62. and the part returns to the idle condition 9 1 7 8 9 05700 044 Figure 53 Bus Data Transfer WRITE S QUENCE S SLAVE ADDR 5 SUB ADDR A S A S TP LSB 0 S START BIT P STOP A S ACKNOWLEDGE BY SLAVE A M ACKNOWLEDGE BY MASTER A S NO ACKNOWLEDGE BY SLAVE A M NO ACKNOWLEDGE BY MASTER 5 RTP LSB 1 Om oma 05700 045 Figure 54 Read Write Sequence Rev J 78 of 114 5 55 MPU can write to or read from all ofthe ADV7180 registers except the subaddress register which is write only The subaddress register determines which register the next read or write operation accesses All communications with the part through the bus start with an access to the subaddress register A read write operation is then performed from or to the target address which increments to the next address until a stop command on the bus is performed REGISTER PROGRAMMING The following sections describe the configuration for each register The communication register is an 8 bit write only register After the part is accessed over the bus and a read write operation is selected the subaddress is set up The subaddress register determines to or from which register the operation takes place Table 105 lists the various operations under the control of the subaddress register for the co
63. be decoded from MAN_LINE_PGM must Line 327 PAL Line 275 NTSC be set to 1 for these bits VBI_DATA_P14_N12 3 0 0 0 0 0 Sets VBI standard to be decoded from to be effective Line 14 PAL Line 12 NTSC Ox6E VDP LINE 018 VBI DATA P328 N276 3 0 0 0 0 0 Sets VBI standard to be decoded from MAN LINE PGM must Line 328 PAL Line 276 NTSC be set to 1 for these bits DATA P15 NI13 3 0 0 0 0 0 Sets VBI standard to be decoded from 19 be effective Line 15 PAL Line 13 NTSC Ox6F VDP_LINE_019 VBI DATA P329 N277 3 0 0 0 0 0 Sets VBI standard to be decoded from MAN_LINE_PGM must Line 329 PAL Line 277 NTSC be set to 1 for these bits DATA P16 NI14 3 0 0 0 0 0 Sets VBI standard to decoded from 19 be effective Line 16 PAL Line 14 NTSC 0x70 VDP_LINE_01A VBI DATA P330 N278 3 0 0000 Sets VBI standard to be decoded from MAN LINE PGM must Line 330 PAL Line 278 NTSC be set to 1 for these bits VBI DATA P17 N15 3 0 0 0 0 0 Sets VBI standard to be decoded from to be effective Line 17 PAL Line 15 NTSC 0x71 VDP_LINE_01B VBI_DATA_P331_N279 3 0 0 0 01 0 Sets VBI standard to decoded from MAN LINE PGM must Line 331 PAL Line 279 NTSC be set to 1 for these bits VBI DATA 18 N16 3 0 Sets VBI standard to be decoded from to be effective Line 18 PAL Line 16 NTSC 0x72 VDP LINE 01C VBI DATA P332 N280 3 0 0 0 0 0 Sets VBI standard to be decoded from MAN_LINE_PGM must Line 332 PAL Line 280 NTSC be set to 1
64. chroma only for Y C or U V interleaved for YPrPb input formats e Chromaantialias filter CAA The ADV7180 oversamples the CVBS by a factor of 4 and the chroma YPrPb by a factor 2 A decimating filter CAA is used to preserve the active video band and to remove any out of band components The CAA filter has a fixed response COMBINED Y ANTIALIAS S CCIR MODE SHAPING FILTER 8 AMPLITUDE dB 8 100 05700 020 120 2 4 6 8 10 12 FREQUENCY MHz Figure 25 Combined Y Antialias CCIR Mode Shaping Filter COMBINED Y ANTIALIAS PAL NOTCH FILTERS Y RESAMPLE ns 0 2 4 f 12 ene ai Figure 26 Combined Y Antialias PAL Notch Filters 8 AMPLITUDE dB k h 60 05700 021 Rev 35 of 114 ADV7180 Chroma shaping filters CSH The shaping filter block 5 can be programmed to perform a variety of low pass responses It can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression Digital resampling filter This block allows dynamic resampling of the video signal to alter parameters such as the time base of a line of video Fundamentally the resampler is a set of low pass filters The actual response is chosen by the system without user intervention Figure 28 shows the overall response of all filters together COMBINED Y dil 1 7 E NOTCH FILTER
65. enables the output of subcarrier lock information also known as genlock from the ADV7180 core to an encoder in a decoder encoder back to back arrangement When EN SFL PIN is 0 default the subcarrier frequency lock output is disabled When EN SFL PIN is 1 the subcarrier frequency lock information is presented on the SFL pin Polarity LLC Pin PCLK Address 0x37 0 The polarity of the clock that leaves the ADV7180 via the LLC pin can be inverted using the PCLK bit Changing the polarity of the LLC clock output may be necessary to meet the setup and hold time expectations of follow on chips When PCLK is 0 the LLC output polarity is inverted When PCLK is 1 default the LLC output polarity is normal see the Timing Specifications section Rev J Page 24 of 114 GLOBAL STATUS REGISTER Four registers provide summary information about the video decoder The IDENT register allows the user to identify the revision code of the ADV7180 The other three registers Address 0x10 Address 0x12 and Address 0x13 contain status bits from the ADV7180 IDENTIFICATION IDENT 7 0 Address 0x11 7 0 This is the register identification of the ADV7180 revision Table 19 describes the various versions of the ADV7180 Table 19 IDENT CODE Table 21 Status 1 Function ADV7180 IDENT 7 0 Description 0x1B Initial release silicon 0x1C Improved ESD and PDC fix Ox1E 48 lead and 32 lead devices only 1
66. for these bits VBI_DATA_P19_N17 3 0 0 0 0 0 Sets VBI standard to be decoded from to be effective Line 19 PAL Line 17 NTSC 0x73 VDP LINE 01D VBI DATA P333 N281 3 0 0 0 0 0 Sets VBI standard to be decoded from MAN LINE PGM must Line 333 PAL Line 281 NTSC be set to 1 for these bits VBI DATA 20 1813 0 o ojo o Sets VBI standard to be decoded from 19 be effective Line 20 PAL Line 18 NTSC Rev J Page 104 of 114 ADV7180 Bit Shading Indicates Interrupt and VDP Map Default State Address Register Bit Description 7 6 5 41 31 2 1 0 Comments Notes 0x74 VDP LINE O1E VBI DATA P334 N282 3 0 0 0 0 0 Sets VBI standard to be decoded from MAN_LINE_PGM must Line 334 PAL Line 282 NTSC be set to 1 for these bits VBI_DATA_P21_N19 3 0 0 0 00 Sets VBI standard to be decoded from to be effective Line 21 PAL Line 19 NTSC 0x75 VDP LINE 01 VBI DATA P335 N283 3 0 0 0 0 0 Sets VBI standard to be decoded from MAN_LINE_PGM must be Line 335 PAL Line 283 NTSC set to 1 for these bits to VBI_DATA_P22_N20 3 0 0 0 0 0 Sets VBI standard to be decoded from be effective Line 22 PAL Line 20 NTSC 0x76 VDP LINE 020 VBI DATA P336 N284 3 0 0 0 01 0 Sets VBI standard to decoded from LINE PGM must Line 336 PAL Lin
67. it may be necessary to duplicate the AV codes from the luma path into the chroma path In an 8 bit wide output interface Cb Y Cr Y interleaved data the AV codes are defined as FF 00 00 AV with AV being the transmitted word that contains information about H V F SD DUP 1 16 BIT INTERFACE Dr ym X m o Y 16 BIT INTERFACE Gan ATS Cb Y Cr Y In this output interface mode the following assignment takes place Cb FF Y 00 Cr 00 and Y AV In a 16 bit output interface 64 lead LQFP only where Y and Cr Cb are delivered via separate data buses the AV code is spread over the whole 16 bits The SD DUP AV bit allows the user to replicate the AV codes on both buses therefore the full AV sequence can be found on the Y bus as well as on the Cr Cb bus see Figure 36 When SD DUP AV is 0 default the AV codes are in single fashion to suit 8 bit interleaved data output When SD is 1 the AV codes are duplicated for 16 bit interfaces VBI EN Vertical Blanking Interval Data Enable Address 0x03 7 The VBI enable bit allows data such as intercast and closed caption data to be passed through the luma channel of the decoder with a minimal amount of filtering All data for Line 1 to Line 21 is passed through and available at the output port The ADV7180 does not blank the luma data and automatically switches all filters along the luma data path into their widest bandwidth For active video
68. locked status 1 01 0 100 lines of video 1 0 1 500 lines of video 15 110 1000 lines of video 1 1 1 100 000 lines of video SRLS select raw lock signal 0 Over field with vertical info selects the determination 1 Line to line evaluation of the lock status FSCLE fsc lock enable 0 Lock status set only by horizontal lock 1 Lock status set by horizontal lock and subcarrier lock 0x52 CVBS TRIM CVBS IBIAS 3 0 sets the 1 1 Default AFE bias current setting bias current for the analog 1 1 0 1 Recommended AFE bias current for front end for CVBS inputs CVBS inputs Reserved Rev J 94 of 114 ADV7180 Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 0x58 VS FIELD VS FIELD VSYNC or FIELD 0 FIELD Pin 37 on 40 lead pin control output 40 lead and 1 VSYNC LFCSP Pin 31 on 32 lead LFCSP only 32 lead LFCSP Reserved 0 Set to default ADC sampling control 0 ADC sampling control 1 Y C mode only Mandatory write Reserved 0 Set to default 0x59 General GPO 3 0 LQFP only 0 Outputs 0 to GPOO GPO ENABLE purpose 1 Outputs 1 to GPOO must be set to 1 outputs Cis GPO for these bits to 0 utputs 0 to 1 take effect 1 Outputs 1 to GPO1 0 Outputs 0 to GPO2 1 Outputs 1 to G
69. must be a fundamental crystal 22 XTAL This is the input pin for the 28 6363 MHz crystal or this pin can overdriven an external 1 8 V 28 6363 MHz clock oscillator source In crystal mode the crystal must be a fundamental crystal 23 58 DVDD P Digital Supply Voltage 1 8 V 27 28 33 41 42 NC No Connect These pins are not connected internally 44 45 50 29 PWRDWN A logic low on this pin places the ADV7180 in power down mode 30 ELPF recommended external loop filter must be connected to the ELPF pin as shown Figure 58 31 PVDD P PLL Supply Voltage 1 8 V 32 37 43 AGND G Analog Ground 34 TEST O This pin must be tied to DGND 35 36 46 to 49 Am1 to Analog Video Input Channels 38 VREFP Internal Voltage Reference Output See Figure 58 for recommended output circuitry Rev J Page 15 of 114 ADV7180 Pin No Mnemonic Type Description 39 VREFN Internal Voltage Reference Output See Figure 58 for recommended output circuitry 40 AVDD P Analog Supply Voltage 1 8 V 51 RESET System Reset Input Active low A minimum low reset pulse width of 5 ms is required to reset the ADV7180 circuitry 52 ALSB This pin selects the address for the ADV7180 For ALSB set to Logic 0 the address selected for a write is Address 0x40 for ALSB set to Logic 1 the address selected is Address 0x42 53 SDATA 1 0 Port Serial Data Input Output Pin 54 SCLK 2
70. not clear 1 Clears PAL SW LK CHNG Reserved Not used 0x4C Interrupt Mask 3 SD OP CHNG MSK 0 Masks SD OP CHNG Q bit read write 1 Unmasks SD_OP_CHNG_Q bit SD V LOCK CHNG MSK 0 Masks 50 V LOCK CHNG Q bit 1 Unmasks SD V LOCK CHNG bit SD H LOCK CHNG 5 0 Masks SD LOCK CHNG Qbit 1 Unmasks SD LOCK CHNG bit SD AD CHNG MSK 0 Masks 50 AD CHNG Q bit 1 Unmasks SD AD CHNG SCM LOCK CHNG MSK 0 Masks SCM LOCK CHNG Q bit 1 Unmasks SCM LOCK CHNG bit PAL SW LK CHNG 0 Masks PAL SW LK CHNG Qbit 1 Unmasks PAL SW LK CHNG bit Reserved Not used Ox4E Interrupt Status 4 read only CCAPD 0 Closed captioning not detected These bits can be cleared 1 Closed captioning detected and masked by Register Reserved x Ox4F and Register 0x50 respectively note that an VDP CGMS WSS CHNGD OQ see 0 CGMS WSS data is not changed interrupt in Register Ox4E Ox9C Bit 4 of user sub map to determine not available for the CCAP Gemstar whether interrupt is issued for a 1 CGMS WSS data is changed available CGMS WSS VPS PDC change in detected data or for when UTC and VITC data uses data is detected regardless of content the VDP data slicer Reserved x VDP GS VPS PDC UTC CHNG 0 Gemstar PDC VPS UTC data is not see 0 9 Bit 5 of User Sub Map to deter changed not available mine whether interrupt is issued for a 1 Gemstar PDC VPS UTC data is change in detected data or for when changed available data is detecte
71. or more writes for the sequence For example for HSB 10 0 write to Address 0x34 first immediately followed by Address 0x35 and so on Rev J Page 79 of 114 ADV7180 REGISTER MAPS Table 105 Main Register Map Details User Map Address Reset Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Value Hex 0 00 Input control RW VID SEL 3 VID SEL 2 VID SEL 1 VID SEL O INSEL 3 INSEL 2 INSEL 1 INSEL 0 00000000 00 1 01 Video selection RW ENHSPLL BETACAM ENVSPROC SQPE 11001000 8 3 03 Output control RW VBI EN TOD OF SELI 3 OF SEL 2 OF SEL 1 SEL O SD DUP AV 00001100 0 4 04 Extended output control RW BT 656 4 TIM OE BL C VBI EN SFL PIN Range 01 0101 45 5 05 Reserved 6 06 Reserved 7 07 Autodetect enable RW 5 525 SECAM AD 443 EN AD P60 AD PALN EN AD PALM EN AD NTSC EN AD PAL EN 01111111 7F 8 08 Contrast RW CON 7 CONI6 CONI5 CONIA CONI3 CON 2 CONI 1 CONIO 10000000 80 9 09 Reserved 10 0 Brightness RW BRI 7 BRI 6 BRI 5 BRI 4 BRI 3 BRI 2 BRI 1 BRI O 00000000 00 11 08 RW HUE 7 HUE 6 HUE 5 HUE 4 HUE 3 HUE 2 HUE 1 HUE 0 00000000 00 12 0
72. readback register by writing a high to the clear bit This resets the state of the available bit to low and indicates that the data in the associated readback registers is not valid After the VDP decodes the next line of the corresponding VBI data the decoded data is placed into the readback register and the available bit is set to high to indicate that valid data is now available Though the VDP decodes this VBI data in subsequent lines if present the decoded data is not updated to the readback registers until the clear bit is set high again However this data is available through the 656 ancillary data packets The clear and available bits are in the STATUS CLEAR Address 0x78 user sub map write only and VDP STATUS Address 0x78 user sub map read only registers respectively Example Readback Procedure The following tasks must be performed to read one packet line of PDC data from the decoder 1 Write 10 to GS VPS PDC UTCT 1 0 Address 0x9C user sub map to specify that PDC data must be updated to registers 2 Write high to the GS PDC VPS UTC CLEAR bit Address 0x78 user sub map to enable I C register updating 3 Poll the GS PDC VPS UTC AVL bit Address 0x78 user sub map going high to check the availability of the PDC packets 4 Read the data bytes from the PDC registers Repeat Step 1 to Step 3 to read another line or packet of data To read a packet of CCAP CGMS or WS
73. state if the PWRDWN bit is set to 0 via or if the ADV7180 is reset using the RESET pin PDBP must be set to 1 for the PWRDWN bit to power down the ADV7180 When PWRDWN is 0 default the chip is operational When PWRDWN is 1 the ADV7180 is in a chip wide power down mode RESET CONTROL Reset Chip Reset Address 0x0F 7 Setting this bit which is equivalent to controlling the RESET pin on the ADV7180 issues a full chip reset All registers are reset to their default power up values Note that some register bits do not have a reset value specified They keep their last written value Those bits are marked as having a reset value of x in the register tables see Table 107 and Table 108 After the reset sequence the part immediately starts to acquire the incoming video signal 1 For 32 lead is the only power down option For 64 lead 48 lead and 40 lead only After setting the reset bit or initiating a reset via the RESET pin the part returns to the default for its primary mode of operation All PC bits are loaded with their default values making this bit self clearing Executing a software reset takes approximately 2 ms However it is recommended to wait 5 ms before any further writes are performed The master controller receives a no acknowledge condition on the ninth clock cycle when chip reset is implemented see the MPU Port Description section When the reset bit is 0 default operatio
74. switched on or off For QAM based video standards PAL and NTSC as well as FM based systems SECAM the threshold for the color kill decision is selectable via the CKILLTHR 2 0 bits If color kill is enabled and the color carrier of the incoming video signal is less than the threshold for 128 consecutive video lines color processing is switched off black and white output To switch the color processing back on another 128 consecutive lines with a color burst greater than the threshold are required The color kill option works only for input signals with a modulated chroma part For component input YPrPb there is no color kill Setting CKE to 0 disables color kill Setting CKE to 1 default enables color kill CKILLTHR 2 0 Color Kill Threshold Address 0x3D 6 4 The CKILLTHR 2 0 bits allow the user to select a threshold for the color kill function The threshold applies only to QAM based NTSC and PAL or FM modulated SECAM video standards To enable the color kill function the CKE bit must be set For Setting 000 Setting 001 Setting 010 and Setting 011 chroma demodulation inside the ADV7180 may not work satisfactorily for poor input video signals Table 47 CKILLTHR Function Description CKILLTHR 2 0 SECAM NTSC PAL 000 No color kill Kill at 0 596 001 Kill at 596 Kill at 1 596 010 Kill at 796 Kill at 2 596 011 default Kill at 896 Kill at 496 100 Kill at 9 596 Kill at 8 596
75. the bit Setting it high forces the output drivers for HS VS and FIELD into the active state that is driving state even if the TOD bit is set If OE is set to low the HS VS and FIELD pins are three stated depending on the TOD bit This functionality is beneficial if the decoder is only used as a timing generator This may be the case if only the timing signals are extracted from an incoming signal or if the part is in free run mode where a separate chip can output a company logo for example For more information on three state control see the Three State Output Drivers section and the Three State LLC Driver section Individual drive strength controls are provided via the DR STR xbits When OE is 0 default HS VS and FIELD are three stated according to the TOD bit When OE is 1 HS VS and FIELD are forced active all the time Drive Strength Selection Data DR STR 1 0 Address 0xF4 5 4 For EMC and crosstalk reasons it may be desirable to strengthen or weaken the drive strength of the output drivers The DR STR 1 0 bits affect the P 15 0 for the 64 lead device or P 7 0 for the 48 lead 40 lead and 32 lead devices output drivers Note that DR STR 1 0 also affects the drive strength of the INTRQ interrupt pin on all ADV7180 models For more information on three state control see the Drive Strength Selection Clock and the Drive Strength Selection Sync sections Table 16
76. the C to VITC bit mapping BITO BIT 1 Se DHT p gt 88 89 VITC WAVEFORM 05700 042 Figure 51 VITC Waveform and Decoded Data Correlation Table 83 VITC Readback Registers Signal Name Register Location Address User Sub Map VITC DATA 0 7 0 VDP VITC DATA 0 7 0 VITC Bits 9 2 146 0x92 VITC DATA 1 7 0 VDP VITC DATA 1 7 0 VITC Bits 19 12 147 0x93 VITC DATA 2 7 0 VDP VITC DATA 2 7 0 VITC Bits 29 22 148 0x94 VITC DATA 3 7 0 VDP VITC DATA 3 7 0 VITC Bits 39 32 149 0x95 VITC DATA 4 7 0 VDP VITC DATA 4 7 0 VITC Bits 49 42 150 0x96 VITC DATA 5 7 0 VDP VITC DATA 5 7 0 VITC Bits 59 52 151 0x97 VITC DATA 6 7 0 VDP VITC DATA 6 7 0 VITC Bits 69 62 152 0x98 VITC DATA 7 7 0 VDP VITC DATA 7 7 0 VITC Bits 79 72 153 0x99 VITC DATA 8 7 0 VDP VITC DATA 8 7 0 VITC Bits 89 82 154 Ox9A CRC 7 0 VDP VITC CALC CRC 7 0 155 Ox9B These registers are readback registers default value does not apply Rev J Page 66 of 114 ADV7180 VPS PDC UTC GEMSTAR The readback registers for VPS PDC and UTC are shared Gemstar is a high data rate standard and is available only through the ancillary stream However for evaluation purposes any one line of Gemstar is available through the registers sharing the same register space as PDC UTC and VPS Therefore only VPS PDC UTC or Gemstar be read through the at one time To identify the
77. the filter settings for YSH and YPK are restored See the BL C VBI Blank Chroma During VBI Address 0x04 2 section for information on the chroma path When is 0 default all video lines are filtered scaled When VBI EN is 1 only the active video region is filtered scaled SD DUP AV 0 8 BIT INTERFACE GoOOgGO INTERLEAVED LE CB CB CR gS AV CODE SECTION 2 AV CODE SECTION AV CODE SECTION 05700 027 Figure 36 AV Code Duplication Control 64 Lead LOFP Only Rev J Page 45 of 114 ADV7180 BL C VBI Blank Chroma During VBI Address 0x04 2 Setting BL VBIhigh blanks the Cr and Cb values of all VBI lines This is done so any data that may arrive during VBI is not decoded as color and is output through Cr and Cb As a result it is possible to send VBI lines into the decoder and then output them through an encoder again undistorted Without this blanking any color that is incorrectly decoded is encoded by the video encoder thus distorting the VBI lines Setting BL VBIto 0 decodes and outputs color during VBI Setting C VBI to 1 default blanks Cr and Cb values during VBI Range Range Selection Address 0x04 0 AV codes as per ITU R BT 656 formerly known as CCIR 656 consist of a fixed header made up of OxFF and 0x00 values These two values are reserved and therefore are not to be used for active video Additionally the ITU specifies that the nomin
78. two pixels late 15 110 Chroma three pixels late 1 1 1 Not a valid setting AUTO PDC EN 0 Use values in LTA 1 0 and CTA 2 0 automatically programs for delaying luma chroma the LTA CTA values so that luma and chroma are aligned at the output for 1 LTA and CTA values determined all modes of operation automatically SWPC allows the Cr and 0 No swapping Cb samples to be swapped 1 Swap the Cr and Cb output samples 0 2 PW UPD peak white 0 Update once per video line Peak white must control update determines the 1 Update once per field be enabled see rate of gain LAGC 2 0 Reserved 1 Set to default CKE color kill enable 0 Color kill disabled For SECAM color allows the color kill 1 Color kill enabled kill the threshold function to be switched is set at 896 see on and off CKILLTHR 2 0 Reserved 1 Set to default 0 2 CAGC 1 0 chroma auto 0 0 Manual fixed gain Use CMG 11 0 control matic gain control selects 1 Use luma gain for chroma the basic mode of ilo A Based orb operation for the AGC in utomatic gain ased on color burst the chroma path 1 1 Freeze chroma gain Reserved 1 1 Set to 1 LAGC 2 0 luma auto Manual fixed gain Use LMG 11 0 matic gain control selects olola Peak white algorithm off Blank level to the mode of operation for sync tip 2 Peak white algorithm on Blank level to synctip 0 1 1 Reserved Reserved 10 1 Reserved 1 1
79. 0 0 0 For DEF Y 5 0 0x0D blue is the default value for Y Register 0 0 has a default value of 0x36 DEF C 7 0 Default Value C Address 0x0D 7 0 The DEF C 7 0 register complements the DEF Y 5 0 value It defines the four MSBs of Cr and Cb values to be output if e TheDEF VAL AUTO EN bit is set to high and the ADV7180 cannot lock to the input video automatic mode DEF VAL EN bit is set to high forced output The data that is finally output from the ADV7180 for the chroma side is Cr 3 0 DEF C 7 4 0 0 0 0 and Cb 3 0 DEF C 3 0 0 0 0 0 For DEF_C 7 0 0x7C blue is the default value for Cr and Cb DEF VAL EN Default Value Enable Address 0x0C 0 This bit forces the use of the default values for Y Cr and Cb See the descriptions in the DEF Y 5 0 Default Value Y Address 0x0C 7 2 and DEF C 7 0 Default Value C Address 0x0D 7 0 sections for additional information In this mode the decoder also outputs a stable 27 MHz clock HS and VS Setting DEF VAL EN to 0 default outputs a colored screen determined by user programmable Y Cr and Cb values when the decoder free runs Free run mode is turned on and off by the DEF VAL AUTO EN bit Setting DEF VAL EN to 1 forces a colored screen output determined by user programmable Y Cr and Cb values This overrides picture data even if the decoder is locked Rev J Page30 of 114 DEF VAL AUTO EN Default Value Automatic Enable Ad
80. 0 0 Gemstar Word2 7 4 0 0 User data words 9 0 0 Gemstar Word2 3 0 0 0 User data words 10 0 0 Gemstar Word3 7 4 0 0 User data words 11 0 0 Gemstar Word3 3 0 0 0 User data words 12 EP EP 0 0 Gemstar Word4 7 4 0 0 User data words 13 EP EP 0 0 Gemstar Word4 3 0 0 0 User data words 14 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Rev J Page 70 of 114 Table 89 Gemstar 2x Data Full Byte Mode ADV7180 Byte DI9 DI8 DI7 DI6 D 5 D 4 D 2 D 1 0 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 1 Line 3 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 Gemstar Word 7 0 0 0 User data words 7 Gemstar Word2 7 0 0 0 User data words 8 Gemstar Word3 7 0 0 0 User data words 9 Gemstar Word4 7 0 0 0 User data words 10 CSI8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 90 Gemstar 1x Data Half Byte Mode Byte D 9 DI8 DI7 DI6 D 5 D 4 D 2 D 1 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF
81. 0 Hz coast mode requency 1 1 Reserved Reserved OxFB Peaking control PEAKING GAIN 7 0 0 1 0 0 0 0 0 O Increases decreases the gain for high frequency portions of the video signal OxFC Coring DNR TH2 7 0 1 0 0 Specifies the maximum edge that is threshold interpreted as noise and therefore blanked Shading indicates default values x indicates a bit that keeps the last written value Rev J Page 99 of 114 ADV7180 To read to and write from the registers in Table 108 the SUB USR EN bit Address OxOE 5 must be set to Logic 1 Table 108 Register Map Descriptions User Sub Map Bit Shading Indicates Interrupt and VDP Map Default State Address Register Bit Description 71615 4132 10 Comments Notes 0x40 Interrupt Configuration 1 INTRQ_OP_SEL 1 0 interrupt 0 0 Open drain drive level select 0 1 Drive low when active 1 0 Drive high when active 1 1 Reserved MPU_STIM_INTRQ manual 0 Manual interrupt mode disabled interrupt set mode 1 Manual interrupt mode enabled Reserved x Not used MV_INTRQ_SEL 1 0 0 0 Reserved Macrovision interrupt select 011 Pseudo sync only 1 0 Color stripe only 1 1 Pseudo sync or color stripe INTRQ DUR SEL 1 0 0 0 Three XTAL periods interrupt duration select 0 1 15 XTAL periods 1 0 63 XTAL
82. 0 Line 3 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 EP EP 0 0 Gemstar Word1 7 4 0 0 User data words 7 EP EP 0 0 Gemstar Word1 3 0 0 0 User data words 8 EP EP 0 0 Gemstar Word2 7 4 0 0 User data words 9 EP EP 0 0 Gemstar Word2 3 0 0 0 User data words 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 91 Gemstar 1x Data Full Byte Mode Byte DI9 DI8 DI7 DI6 D 5 D 4 D 2 D 1 0 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 Line 3 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 Gemstar Word1 7 0 0 0 User data words 7 Gemstar Word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 518 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Rev J Page 71 of 114 ADV7180 Table 92 NTSC CCAP Data Half Byte Mode Byte DI9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 1 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 EP EP 0 0 CCAP Word1 7 4 0 0 User data words 7 EP
83. 01110 45 20 Gain Control 1 W CAGT 1 CAGTIOI CMG 11 CMG 10 CMGI9 CMGI8 11110100 F4 45 2D Chroma Gain 1 R CG 11 CG 10 CGI9 CGI8 46 2E ChromaGainControl2 W CMGI7 CMGI6 CMGI5 CMGIA CMGI3 CMG 2 CMG 1 CMGIO 00000000 00 46 2E Gain 2 R CGI7 CG 5 4 CG 3 CG 2 cai CG O 47 2F Luma Gain Control 1 W LAGT O LMG 11 LMG 10 LMG 9 LMG 8 1111 FO 47 2F Luma Gain 1 R LG 11 LG 10 LG 9 LG 8 48 30 Luma Gain Control 2 W LMGI7 LMG 6 LMG 5 LMG 4 LMG 3 LMG 2 LMG 1 LMG O 00 48 30 LumaGain2 R LG 6 LG 5 16141 LG 3 LG 2 LG 1 LG 0 49 31 VS FIELD Control 1 RW NEWAVMODE HVSTIM 00010010 12 50 32 VS FIELD Control 2 RW VSBHO VSBHE 01000001 41 51 33 VS FIELD Control 3 RW VSEHO VSEHE 10000100 84 52 34 HS Position Control 1 RW HSB 10 HSB 9 HSB 8 HSE 10 HSE 9 HSE 8 00000000 00 53 35 HS Position Control 2 RW HSB 7 HSB 6 HSBI 5 HSB 4 HSB 3 HSB 2 HSB 1 HSB O 00000010 02 54 36 HSPosition Control 3 RW HSE 7 HSE 6 HSE 5 HSE 4 HSE 3 HSE 2 1 0 00000000 00 55 37 Polarity RW 5 PVS PF PCLK 00000001 01 56 38 NTSC comb control RW CTAPSN 1 CTAPSNIO CCMNI 2 CCMN 1 CCMNIO YCMNI2 YCMNI1 YCMNIO 10000000 80 57 39 PALcomb control RW CTAPSP 1 0 CCMPI 2 CCMP 1 CCMPIO YCMP 2 YCMP 1 YCMP 0 11000000 CO 58 3A ADCcontrol RW PWRDWN MUX 0 PWRDWN 1 PWRDWN
84. 1 1 0 O Cr 3 0 DEF C 7 4 O 0 0 0 Default Cb Cr is C the Cr and Cb default Cb 3 0 DEF C 3 0 0 0 0 0 value output in values are defined in this free run mode register default values give blue screen output OxOE ADI Control 1 Reserved 0 0 0 0 0 Setas default SUB USR EN enables 0 Access main register space See Figure 55 user to access the interrupt 1 Access interrupt VDP register space VDP register map Reserved 010 Set as default Rev J Page 86 of 114 ADV7180 Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes OxOF Power Reserved 0 0 Setto default management PDBP power down bit 0 Chip power down controlled by pin Not applicable for priority selects between 32 lead LFCSP PWRDWN bit or pin control 1 Bit has priority pin disregarded Reserved 0 0 Set to default PWRDWN power down 0 System functional places the decoder into a 1 Powered down See PDBP full power down mode OxOF Bit 2 Reserved 0 Set to default Reset chip reset loads 0 Normal operation all PC bits with default values 1 Start reset sequence Executing reset takes approxi mately 2 ms this bit is self clearing 0x10 Status 1 IN_LOCK x 1 in lock now Provides info read only LOST_LOCK x 1 lost lock since last read about ru tat t FSC LO
85. 1 P15 N13 O P328 N276 3 P328 N276 2 P328 N276 1 P328 276 0 111 6F VDP LINE 019 RW VBI DATA VBI DATA _ VBI DATA VBI DATA VBI DATA VBI DATA VBI DATA VBI DATA _ 00000000 00 P16 N14 3 P16 N14 2 P16 N14 1 P16 140 P329 27713 P329 N277 2 P329 N277 1 P329 277 0 112 70 VDP LINE 01A RW VBI DATA VBI_DATA_ VBI_DATA_ VBI DATA _ VBI DATA VBI DATA _ VBI DATA VBI DATA 00000000 00 P17 N15 3 17 N15 2 P17 N15 1 17 1510 P330 N278 3 P330 N278 2 P330 N278 1 P330 278 0 113 71 VDP LINE 01 RW VBI DATA VBI DATA _ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI DATA _ VBI DATA VBI DATA 00000000 00 18 N16 3 P18 16 2 P18 N16 1 P18 N16 O P331 N279 3 P331 N279 2 P331 N279 1 P331 2790 114 72 VDP LINE 01 RW VBI DATA VBI DATA _ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI DATA _ VBI DATA VBI DATA _ 00000000 00 P19 N17 3 P19 N17 2 P19 N17 1 P19 1710 P332 N280 3 P332 N280 2 P332 N280 1 P332 N280 0 115 73 VDP LINE 01D RW VBI DATA VBI DATA _ VBI DATA _ VBI DATA VBI DATA _ VBI DATA VBI DATA VBI DATA _ 00000000 00 20 N18 3 20 N18 2 P20 N18 1 20 N18 O N281 3 N281 2 281 2810 116 74 VDP LINE O1E RW VBI DATA VBI DATA _ VBI DATA _ VBI DATA VBI DATA VBI DATA _ VBI DATA _ VBI DATA 00000000 00 P21 N19 3 P21 N19 2 P21 N19 1 P21 N19 O P334 28213 P334 N282 2 P334 N282 1 P334 2820 117 75 VDP LINE 01 RW VBI DATA VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI DATA _ VBI DATA _ VBI _ VBI 00000000 00 22
86. 10 100 default 100 101 500 110 1000 111 100 000 COLOR CONTROLS These registers allow the user to control picture appearance including control of the active data in the event of video being lost These controls are independent of any other controls For instance brightness control is independent of picture clamping although both controls affect the dc level of the signal CON 7 0 Contrast Adjust Address 0x08 7 0 This register allows the user to control contrast adjustment of the picture Table 27 CON Function CON 7 0 Description 0x80 default Gain on luma channel 1 0x00 Gain on luma channel 0 OxFF Gain on luma channel 2 CIL 2 0 Number of Video Lines 000 1 001 2 010 5 011 10 100 default 100 101 500 110 1000 111 100 000 SD SAT Cb 7 0 SD Saturation Cb Channel Address 0xE3 7 0 This register allows the user to control the gain of the Cb channel only which in turn adjusts the saturation of the picture Table 28 SD SAT Cb Function SD SAT Cb 7 0 Description 0x80 default Gain on Cb channel 0 dB 0x00 Gain on Cb channel 42 dB OxFF Gain on Cb channel 6 dB SD SAT Cr 7 0 SD Saturation Cr Channel Address 0xE4 7 0 This register allows the user to control the gain of the Cr channel only which in turn adjusts the saturation of the picture Table 29 SD SAT Cr Function SD SAT Cr 7 0 Description 0x80 default 0x00 OxFF
87. 2D COMB RESAMPLE CONTROL CHROMA CHROMA RESAMPLE 2D COMB VIDEO DATA OUTPUT AV CODE INSERTION p MEASUREMENT BLOCK 2 I2C VIDEO DATA PROCESSING BLOCK 05700 015 Figure 20 Block Diagram of the Video Processor Figure 20 shows a block diagram of the ADV7180 video processor The ADV7180 can handle standard definition video in CVBS SD CHROMA PATH The input signal is processed by the following blocks Y C and YPrPb formats It can be divided into a luminance and chrominance path If the input video is of a composite type CVBS both processing paths are fed with the CVBS input SD LUMA PATH The input signal is processed by the following blocks e Luma digital fine clamp This block uses a high precision algorithm to clamp the video signal e Luma filter This block contains a luma decimation filter YAA with a fixed response and some shaping filters YSH that have selectable responses e Luma gain control The automatic gain control AGC can operate on a variety of different modes including gain based on the depth of the horizontal sync pulse peak white mode and fixed manual gain Luma resample To correct for line length errors as well as dynamic line length changes the data is digitally resampled e Luma 2D comb The 2D comb filter provides Y C separation e code insertion At this point the decoded luma Y signal is merged with the retrieved chroma values
88. 3 DATA 3 7 0 Decoded VITC data read only 0x96 VDP VITC DATA 4 DATA 417 0 Decoded VITC data read only 0x97 VDP VITC DATA 5 DATA 5 7 0 Decoded VITC data read only 0x98 VDP VITC DATA 6 VITC DATA 6 7 0 X X X X X X X X Decoded VITC data read only 0x99 VDP VITC DATA 7 DATA 7 7 0 Decoded VITC data read only Ox9A VDP VITC DATA 8 DATA 8 7 0 Decoded VITC data read only Ox9B VDP CALC CRC 7 0 Decoded data read only 0 9 VDP OUTPUT SEL Reserved WSS CGMS CHANGE 0 Disable content based updating of The available bit shows CGMS and WSS data the availability of data 1 Enable content based updating of only when its content CGMS and WSS data has changed GS_VPS_PDC_UTC_CB_CHANGE Disable content based updating of Gemstar VPS PDC and UTC data Enable content based updating of Gemstar VPS PDC and UTC data PC GS VPS PDC UTC 1 0 0 0 Gemstar 1x Gemstar 2x 0 1 VPS 1 0 PDC 1 1 UTC Standard expected to be decoded Shading indicates default values x indicates a bit that keeps the last written value Rev J Page 106 of 114 ADV7180 PCB LAYOUT RECOMMENDATIONS The ADV7180 is a high prec
89. 33 NC 17 18 19 20 21 22 23 24 25 26 27 28 29 f30 31 32 45489 995 589 J2E amp gEkzao0 amaze 4 gt 05700 008 Figure 10 64 Lead LQFP Pin Configuration Table 11 64 Lead LQFP Pin Function Description Pin No Mnemonic Type Description 1 INTRO Interrupt Request Output Interrupt occurs when certain signals detected on the input video see Table 108 2 HS Horizontal Synchronization Output Signal 3 10 24 57 DGND G Digital Ground 4 11 DVDDIO P Digital I O Supply Voltage 1 8 V to 3 3 V 5 to 8 14 to 19 P11 to P8 Video Pixel Output Port See Table 100 for output configuration for 8 bit and 16 bit modes 25 26 59 to 62 P7 to P2 P1 PO P15 to P12 9 SFL Subcarrier Frequency Lock This pin contains a serial output stream that be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder 12 13 55 56 GPOO GPO3 O General Purpose Outputs These pins can be configured via to allow control of external devices 20 LLC This is a line locked output clock for the pixel data output by the ADV7180 It is nominally 27 MHz but varies up or down according to video line length 21 XTAL1 This pin should be connected to the 28 6363 MHz crystal or left as a no connect if an external 1 8 V 28 6363 MHz clock oscillator source is used to clock the ADV7180 In crystal mode the crystal
90. 363 MHz Frequency Stability 50 ppm PC PORT SCLK Frequency 400 kHz SCLK Minimum Pulse Width High ti 0 6 us SCLK Minimum Pulse Width Low t 1 3 us Hold Time Start Condition ts 0 6 us Setup Time Start Condition ta 0 6 us SDA Setup Time ts 100 ns SCLK and SDA Rise Times te 300 ns SCLK and SDA Fall Times 300 ns Setup Time for Stop Condition ts 0 6 us RESET FEATURE Reset Pulse Width 5 ms CLOCK OUTPUTS LLC Mark Space Ratio 45 55 55 45 96 cycle DATA AND CONTROL OUTPUTS Data Output Transitional Time tu Negative clock edge to start of valid data 3 6 ns tserue tio t11 Data Output Transitional Time t End of valid data to negative clock edge 24 ns to t12 Timing Diagrams SDATA SCLK 05700 005 tg OUTPUT LLC OUTPUTS 0 TO P7 HS VS FIELD SFL 05700 006 Figure 7 Pixel Port and Control Output Timing Rev J Page 10 of 114 ADV7180 ANALOG SPECIFICATIONS Guaranteed by characterization Avpp 1 71 V to 1 89 V Dvpp 1 65 V to 2 0 V Dvppio 1 62 V to 3 6 V 1 65 V to 2 0 V specified at operating temperature range unless otherwise noted Table 6 Parameter Test Conditions Min Max Unit CLAMP CIRCUITRY External Clamp Capacitor 0 1 uF Input Impedance Clamps switched off 10 MO Large Clamp Source Current 0 4 mA Large Clamp Sink Current 0 4 mA Fine Clamp Source Current 10 uA Fine Clamp Sink Current 10 uA THERMAL SPECIFICATIONS Tabl
91. 4 Structure of VBI Words in the Ancillary Data Stream Each VBI data standard has been split into a clock run in CRI a framing code FC and a number of data bytes n The data packet in the ancillary stream includes only the FC and data bytes Table 76 shows the format of VBI WORD x in the ancillary data stream Table 76 Structure of VBI Data Words in the Ancillary Stream Ancillary Data Byte No ByteType Description VBI WORD 1 FCO Framing Code 23 16 VBI WORD 2 Framing Code 15 8 VBI WORD 3 FC2 Framing Code 7 0 VBI WORD 4 DB1 First data byte VBI WORD N43 DBn Last n data byte VDP Framing Code The length of the actual framing code depends on the VBI data standard For uniformity the length of the framing code reported in the ancillary data stream is always 24 bits For standards with a smaller framing code length the extra LSB bits are set to 0 The valid length of the framing code can be decoded from the VBI DATA STD bits available in IDO UDW 1 The framing code is always reported in the inverse transmission order Byte B9 B8 B7 B6 B5 B4 B3 B2 B1 BO Description 0 0 0 0 0 0 0 0 0 0 0 Ancillary data preamble 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 3 EP EP 0 PC DID6 2 4 0 0 0 DID 4 EP EP PC SDID7 2 5 0 0 0 SDID 5 EP EP 0 DC 4 0 0 0 Data count 6 EP EP Padding 1 0 VBI_DATA_STD 3 0 0 0 IDO User Data Word 1 7 EP EP 0 LINE NUMBER 9 5 0 0 ID1 User Data Word 2 8 EP EP EVEN FI
92. 40 lead LFCSP ADV7180WBCPZ Automotive 40 lead LFCSP ADV7180BSTZ 64 lead LOFP ADV7180WBSTZ Automotive 64 lead LOFP ADV7180WBST48Z Automotive 48 lead LOFP QOO AWWW WW Digital Outputs Temperature Grade 8 bit 10 C to 70 C 8 bit 40 C to 85 C 8 bit 40 C to 85 C 8 bit 40 C to 125 C 8 bit 16 bit 40 C to 85 C 8 bit 16 bit 40 C to 125 C 8 bit 40 C to 85 C 1 W Automotive qualification completed Rev J 5 of 114 ADV7180 FUNCTIONAL BLOCK DIAGRAMS CLOCK PROCESSING BLOCK ADLLT PROCESSING 8 BIT DIGITAL PIXEL DATA PROCESSING u P7 TO PO BLOCK gt x o x ANALOG 5 Q HS VIDEO z 9 INPUTS x m 2 LE 2 2 o 05700 055 SCLK SDATA ALSB RESET Figure 2 32 Lead LFCSP Functional Diagram CLOCK PROCESSING BLOCK 16 BIT DIGITAL PIXEL DATA PROCESSING BLOCK P15 TO PO 2D COMB hs ANALOG 9 5 VIDEO INPUTS x VBI SLICER Q ys 5 FIELD GPO0 GPO3 O SFL O iNTRQ SCLK SDATA ALSB RESET PWRDWN 8 Figure 3 64 Lead LQFP Functional Block Diagram CLOCK PROCESSING BLOCK XTAL1 XTALO ADLLT PROCESSING Otte DIGITAL PIXEL DATA PROCESSING BLOCK P7 TO Aint 5 2D COMB x ANALOG 5 Hs VIDEO 2 INPUTS 1 x VBI SLICER 5 VSIFIELD 3 gt m ja 2 a E 2 o 05700 004 SCLK SDATA ALSB RESET PWRDWN Figure 4 40 Lead LFCSP Functional Block Diagram Rev J Page 6 of 114 ADV7180 CLOCK
93. 43 8 Free RunLineLength1 W LLC PAD SEL 2 PAD _ LLC PAD _ 00000000 00 SEL 1 SEL 0 153 99 CCAP 1 R 1 CCAP1 6 CCAP 1 5 CCAP 1 4 CCAP1 3 CCAP1 2 CCAP 1 1 CCAP1 0 Rev J Page 80 of 114 ADV7180 Address Reset Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Value Hex 154 9A CCAP2 R CCAP2 7 2 6 CCAP2 5 CCAP2 4 CCAP2 3 CCAP2 2 CCAP2 1 2 0 155 98 Letterbox 1 R LCTI 7 LB LCT 6 LB LCT 5 LB_LCT 4 LB_LCT 3 LB_LCT 2 LB_LCT 1 LB_LCT 0 156 9 Letterbox 2 R LB LCM 7 LB LCM 6 LB LCMI5 LB LCMIA LB LCM 3 LB_LCM 2 LB_LCM 1 LB LCM O 157 90 Letterbox 3 R LCB 7 LB LCBI6 LB LCBI 5 LB 41 LB LCBI 3 LB LCB 2 LB LCBI 1 LB LCBI O 178 B2 CRCenable Ww CRC ENABLE 00011100 1C 195 C3 ADCSwitch 1 RW Reserved MUX1 2 MUX1 1 MUX1 0 Reserved MUXO 2 MUXO 1 MUXO O 00 196 4 ADCSwitch 2 RW MUX Reserved MUX2 2 MUX2 1 MUX2 0 00 220 DC Letterbox Control 1 RW LB THIA LB THI 3 LB TH 2 LB TH 1 LB TH O 10101100 AC 221 DD Letterbox Control 2 RW LB SL 3 LB SL 2 LB SL 1 LB 510 LB EL 3 LB EL 2 LB EL 1 LB EL O 01001100 4 222 DE ST Noise Readback 1 R ST NOISE VLD ST NOISE 10 ST NOISE 9 ST NOISE
94. 5 LINE ADVANCE BY 0 5 LINE VSYNC BEGIN Figure 45 PAL VSYNC Begin 05700 036 ADV7180 PFTOGDELO PAL Field Toggle Delay on Odd Field Address OxEA 7 When PFTOGDELO is 0 default there is no delay Setting PFTOGDELO to 1 delays the F toggle transition on an 74 odd field by a line relative to PFTOG NOT VALID FOR USER PROGRAMMING PFTOGDELE PAL Field Toggle Delay on Even Field Address OxEA 6 YES NO i n When PFTOGDELE is 0 there is no delay Setting PFTOGDELE to 1 default delays the F toggle transition FVENDDEEO on an even field by a line relative to PFTOG 2 PFTOGSIGN PAL Field Toggle Sign Address OXEA 5 Setting PFTOGSIGN to 0 delays the field transition Set for user ADDITIONAL ADDITIONAL manual programming DELAY BY DELAY BY ADVANCE END OF DELAY END OF VSYNC VSYNC BY PVEND 4 0 BY PVEND 4 0 LENE TINE Setting PFTOGSIGN to 1 default advances the field transition not recommended for user programming PFTOG PAL Field Toggle Address OXEA 4 0 The default value of PFTOG is 00011 indicating the PAL field toggle position 1 1 0 0 For all NTSC PAL field timing controls the F bit in the AV code and the field signal on the FIELD pin are modified VSYNC END 05700 037 A o Figure 46 PAL VSYNC End PVENDDELO PAL VSYNC End Delay on Odd Field Address OxE9 7 NOTIOR USER When PVENDDELO is 0 default there is no delay Setting PVENDDELO to 1 delays VSYN
95. 64 lead and 40 lead models only STATUS 1 Status 1 7 0 Address 0x10 7 0 This read only register provides information about the internal status of the ADV7180 See the CIL 2 0 Count Into Lock Address 0x51 2 0 section and the COL 2 0 Count Out of Lock Address 0x51 5 3 section for details on timing Depending on the setting of the FSCLE bit the Status Register 0 and Status Register 1 are based solely on horizontal timing infor mation or on the horizontal timing and lock status of the color subcarrier See the FSCLE fSC Lock Enable Address 0x51 7 section AUTODETECTION RESULT AD RESULT 2 0 Address 0x10 6 4 The AD_RESULT 2 0 bits report back on the findings from the ADV7180 autodetection block See the General Setup section for more information on enabling the autodetection block and the Autodetection of SD Modes section for more information on how to configure it Table 20 AD RESULT Function Status 1 7 0 Bit Name Description 0 IN LOCK In lock now 1 LOST LOCK Lost lock since last read of this register 2 FSC LOCK fsc locked now 3 FOLLOW PW AGC follows peak white algorithm 4 AD RESULT O Result of autodetection 5 AD RESULT 1 Result of autodetection 6 AD RESULT 2 Result of autodetection 7 COL KILL Color kill active STATUS 2 Status 2 7 0 Address 0x12 7 0 Table 22 Status 2 Function Status 2 7 0 Bit Name Description 0 MVCS DET Detected Macrovision color striping 1
96. 7180 lt LL 330 5 gt sDA gt 330 05700 049 NC NO CONNECT l Figure 58 64 Lead LQFP Typical Connection Diagram Rev J Page 109 of 114 ADV7180 ANALOG INPUT 1 THE SUGGESTED INPUT ARRANGEMENT Y 0 1uF IS AS SEEN ON THE EVAL BOARD AND IS an4 DIRECTLY SUPPORTED BY INSEL lt 360 390 Dypp 1 8V Dypp 1 8V ANALOG INPUT 2 CVBS 0 1uF lt 1 2 0 1uF 10nF 0 1 10nF 360 390 D 3 3V Aypp_1 8V ANALOG INPUT 3 VDDIO Ll VDD YOY 0 1pF lt 1 0 1 0 1 360 Dvppio 3 3V Pypp 1 8V 10nF l 390 10nF VDDIO VDD ANALOG INPUT 4 1 10nF 0 1 Cr 0 1yF 0 1 10nF 360 C Ans 390 x SL S3 5 8 0 7 WE O O O OO ANALOG INPUT 5 Cb 0 1yF 26 S gt Aint a A 360 Ans x 27 amp amp i 2 61 A Aw2 _ gt O Ain2 P24 911 631 ANALOG INPUT 6 Aw gt 6910 P4 A YC C 34 Sa P5 1 5 TJ gt Di IN HE P6 I 360 ud Aw5 gt O Ain5 P7 Si Pry L Aw6 gt 360 Ain6 ADV7180WBST48Z LQFP 48 KEEP VREFN AND VREFP CAPACITOR AS CLOSE AS POSSIBLE TO THE ADV7180 AND ON THE SAME 30 SIDE OF THE PCB AS THE ADV7180 Q VREFN 0 1uF INTRQ 04 INT VREFP GP03 41 GPO3 2 542 GPO2 GPO1 Q GPO1 GPO0 GPO0 170 xTAL x L 4TpF VSIFIELD VS FIELD 28 63636MHz C 47 p 47pF 498 L 3 SFLO amp sr Pypp_1 8V R
97. 80 01 10 byte mode 3 34 3 44 TTXT SYSTEM PAL and NTSC 00 nibble mode 6 66 0 76 01 10 byte mode 3 33 2 42 TTXT SYSTEM D PAL and 00 nibble mode 6 68 2 80 NTSC 01 10 byte mode 3 34 3 44 VPS PAL 00 nibble mode 6 26 0 36 01 10 byte mode 3 13 0 20 VITC NTSC and PAL 00 nibble mode 6 18 0 28 01 10 byte mode 3 9 0 16 WSS PAL 00 nibble mode 6 4 2 16 01 10 byte mode 3 2 3 12 GEMSTAR 1x NTSC 00 nibble mode 6 4 2 16 01 10 byte mode 3 2 3 12 GEMSTAR 2x NTSC 00 nibble mode 6 8 2 20 01 10 byte mode 3 4 1 12 CCAP NTSC and PAL 00 nibble mode 6 4 2 16 01 10 byte mode 3 2 3 12 CGMS NTSC 00 nibble mode 6 6 0 16 01 10 byte mode 3 343 2 12 The first four UDWs are always the ID Rev J Page 60 of 114 ADV7180 PC Interface Dedicated readback registers are available for CCAP CGMS WSS Gemstar VPS PDC UTC and VITC Because teletext is a high data rate standard data extraction is supported only through the ancillary data packet User Interface for Readback Registers The VDP decodes all enabled VBI data standards in real time Because the access speed is much lower than the decoded rate when the registers are accessed they may be updated with data from the next line To avoid this VDP has a self clearing clear bit and an available AVL status bit accompanying all readback registers The user must clear the
98. A 0 122 7A VDP_CCAP_ R CCAP_BYTE_2 7 BYTE 2 6 BYTE 2 5 CCAP BYTE 2 41 CCAP_BYTE_2 3 BYTE 2 21 CCAP BYTE 2 11 2 0 DATA 1 125 70 VDP_CGMS_ R CGMS CRC 5 CGMS_CRC 4 5 3 CGMS 2 WSS DATA 0 126 7E VDP CGMS _ R CGMS CRC 1 CGMS CRC O CGMS WSS 13 CGMS WSS 12 CGMS WSS 11 CGMS WSS 10 CGMS WSS 9 CGMS WSSI 8 WSS DATA 1 127 7F VDP CGMS _ R CGMS WSSI 7 CGMS_WSS 6 CGMS WSS 5 CGMS WSSI 4 CGMS WSSI 3 CGMS 1 55 21 CGMS WSS 1 CGMS WSSI O WSS DATA 2 132 84 VDP GS VPS R GS VPS PDC 65 VPS PDC GS VPS PDC GS VPS PDC GS 5 PDC 65 VPS PDC GS VPS PDC GS VPS PDC PDC UTC 0 UTC BYTE O 7 0 BYTE O 6 UTC BYTE O 5 BYTE 0 41 UTC BYTE O 3 UTC BYTE O 2 UTC BYTE UTC BYTE O O 133 85 VDP GS VPS GS VPS PDC 65 VPS PDC 65 ves PDC GS VPS PDC 65 ves PDC 65 VPS PDC 65 VPS PDC 65 VPS PDC PDC UIC 1 UTC BYTE 1 7 UTC BYTE 1 6 UTC BYTE 1 5 UTC BYTE 1 41 UTC BYTE 1 3 UTC BYTE 1 2 UTC BYTE 1 1 UTC BYTE 1 0 134 86 VDP GS VPS R GS VPS PDC 65 VPS PDC 65 ves PDC GS VPS 65 ves PDC 65 VPS PDC 65 VPS PDC 05 VPS PDC PDC UIC 2 UTC BYTE 2 7 UTC BYTE 2 6 UTC BYTE 2 5 UTC BYTE 241 UTC BYTE 2 3 UTC BYTE 2 2 UTC BYTE 211 UTC BYTE 2 0 135 87 VDP GS VPS R GS VPS PDC 65 VPS PDC 65 5 PDC GS VPS PDC 65 ves PDC 65 VPS PDC 65 VPS 65 VPS PDC PDC UIC 3 UTC BYTE 3 7 UTC BYTE 3 6 UTC BYTE 3 5 UTC BYTE 3 4
99. ADC Connected To ADC Connected To ADC Connected To 64 LFCSP 400r LQFP 64 or LFCSP 40 or LQFP 64 or LFCSP 400r MUXO 2 0 LQFP 48 LFCSP 32 MUX1 2 0 LQFP 48 LFCSP 32 MUX2 2 0 LQFP 48 LFCSP 32 000 No connect No connect 000 No connect No connect 000 No connect No connect 001 1 1 001 No connect No connect 001 No connect No connect 010 2 No connect 010 No connect No connect 010 2 No connect 011 A3 No connect 011 A3 No connect 011 No connect No connect 100 Ain2 100 Ain4 2 100 connect No connect 101 5 3 101 5 101 5 3 110 Am6 No connect 110 Am6 No connect 110 Ain6 No connect 111 No connect No connect 111 No connect No connect 111 No connect No connect Note the following e can only be processed by MUXO e can only be processed by MUX0 and MUXI YPrPb can only be processed by MUX0 and MUX2 Rev J Page 21 of 114 ADV7180 ANTIALIASING FILTERS The ADV7180 has optional on chip antialiasing AA filters on each of the three channels that are multiplexed to the ADC see Figure 17 The filters are designed for standard definition video up to 10 MHz bandwidth Figure 18 and Figure 19 show the filter magnitude and phase characteristics The antialiasing filters are enabled by default and the selection of INSEL 3 0 determines which filters are powered up at any given time For example if CVBS mode is selected the filter circuits for the remainin
100. ANALOG DEVICES 10 Bit 4x Oversampling SDTV Video Decoder ADV7180 FEATURES Qualified for automotive applications Worldwide NTSC PAL SECAM color demodulation support One 10 bit ADC 4x oversampling for CVBS 2x oversampling for Y C mode and 2x oversampling for YPrPb per channel 3 video input channels with on chip antialiasing filter CVBS composite Y C S Video and YPrPb component video input support 5 line adaptive comb filters and CTI DNR video enhancement Mini TBC functionality provided by adaptive digital line length tracking ADLLT signal processing and enhanced FIFO management Integrated AGC with adaptive peak white mode Macrovision copy protection detection NTSC PAL SECAM autodetection 8 bit ITU R BT 656 YCrCb 4 2 2 output and HS VS and FIELD 1 0 V analog input signal range Full featured VBI data slicer with teletext support WST Power down mode and ultralow sleep mode current 2 wire serial MPU interface IC compatible Single 1 8 V supply possible 1 8 V analog 1 8 V PLL 1 8 V digital 1 8 V to 3 3 V I O supply 10 to 70 C commercial temperature grade 40 C to 85 C industrial automotive qualified temperature grade 40 to 125 C temperature grade for automotive qualified 4 package types 64 lead 10 mm x 10 mm RoHS compliant LOFP 48 Lead 7 mm x 7 mm RoHS compliant LOFP 40 lead 6 mm x 6 mm RoHS compliant LFCSP 32 lead 5 mm x 5 mm RoHS compliant LFCSP GENERAL DESCRIPTION The ADV7180 auto
101. ATA 6 VITC DATA 6 7 DATA 6 6 DATA 6 5 VITC DATA 6 41 VITC DATA 6 3 VITC DATA 6 2 VITC DATA 6 1 VITC DATA 610 153 99 VDP VITC DATA 7 R DATA 7 7 VITC DATA 7 6 DATA 7 5 VITC DATA 7 4 VITC DATA 7 3 VITC DATA 7 2 VITC DATA 7 1 VITC DATA 70 154 9A VDP VITC DATA 8 DATA 8 7 VITC DATA 8 6 DATA 8 5 VITC DATA 8 41 VITC DATA 8 3 VITC DATA 8 2 VITC DATA 8 1 VITC DATA 810 155 9B VDP_VITC_CALC_ R VITC CRC 7 VITC_CRC 6 VITC CRC 5 VITC_CRC 4 VITC_CRC 3 VITC_CRC 2 VITC_CRC 1 VITC_CRC 0 CRC 156 9 VDP OUTPUT SEL RW GS 5 _ GS 5_ GS 5 _ WSS_CGMS_ 00110000 30 PDC_UTC 1 PDC UTCIO PDC CB CHANGE CB CHANGE 1 To access the registers listed in Table 106 SUB USR EN in Register Address OxOE must be programmed to 1 x in a reset value indicates do not care Rev J Page 83 of 114 ADV7180 Table 107 Main Register Map Descriptions User Main Map Subaddress Register Bit Description Bits Shading Indicates Default State 7 6 5 4 2 1 Comments Notes 0x00 Input control INSEL 3 0 the INSEL bits allow the user to select an input channel and the input format refer to Table 13 and Table 14 for full routing details Composite LOFP and LFCSP Composite LOFP reserved LFCSP Composite LOFP and LFCSP Composite LOFP reserved LFCSP
102. A_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 00000000 00 P8 N25 3 P8 N25 2 P8 N25 1 P8 25 0 P321 N288 3 P321 N288 2 P321 N288 1 P321 N288 0 104 68 VDP LINE 012 RW VBI DATA VBI DATA VBI DATA VBI DATA VBI DATA VBI DATA _ VBI DATA VBI DATA 00000000 00 P9 3 P9 2 P9 1 P322 3 P322 2 P322 1 P322 0 105 69 VDP_LINE_013 RW VBI DATA VBI DATA VBI DATA VBI DATA VBI DATA _ VBI DATA VBI DATA VBI DATA 00000000 00 P10 3 P10 2 P10 1 P10 0 P323 3 P323 2 P323 1 P323 0 106 6A VDP LINE 014 RW VBI DATA VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 00000000 00 P11 3 P11 2 P11 1 P11 0 P324_N272 3 P324_N272 2 P324_N272 1 P324 N272 0 107 6B VDP LINE 015 RW VBI DATA VBI DATA _ VBI DATA _ VBI DATA VBI DATA VBI DATA _ VBI DATA VBI_DATA_ 00000000 00 P12_N10 3 P12_N10 2 P12_N10 1 P12_N10 0 P325 N273 3 P325 N273 2 P325 N273 1 P325 N273 0 108 6 VDP LINE 016 RW VBI DATA VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 00000000 00 P13_N11 3 P13_N11 2 P13_N11 1 P13 1110 P326 27413 P326 N274 2 P326 N274 1 P326 N274 0 109 6D VDP LINE 017 RW VBI DATA VBI DATA _ VBI DATA VBI DATA VBI DATA VBI DATA VBI DATA VBI DATA 00000000 00 P14_N12 3 P14 N12 2 P14_N12 1 P14 1210 P327 N275 3 P327 N275 2 P327 N275 1 P327 N275 0 110 6E VDP LINE 018 RW VBI DATA VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 00000000 00 P15_N13 3 P15_N13 2 15 N13
103. Ain4 0100 Composite CVBS input on Ain5 0101 Composite CVBS input on 0110 Y C S Video Y input on 1 C input on Ain4 0111 Y C S Video Y input Ain2 C input on 5 1000 Y C S Video Y input on Ain3 C input on 1001 YPrPb Y input on A1 Pb input on Ain4 Pr input on Ain5 1010 YPrPb Y input on 2 Pr input on Pb input on Ain3 1011 to 1111 Reserved Reserved Table 14 40 Lead and 32 Lead LFCSP INSEL 3 0 INSEL 3 0 Video Format Analog Input 0000 Composite CVBS input on 1 0001 to 0010 Reserved Reserved 0011 Composite CVBS input on Ain2 0100 Composite CVBS input on Ain3 0101 Reserved Reserved 0110 Y C S Video Y input on 1 C input on 2 0111 to 1000 Reserved Reserved 1001 YPrPb Y input on 1 Pr input on Ain3 Pb input on 2 1010 to 1111 Reserved Reserved Rev J 20 of 114 ANALOG INPUT MUXING The ADV7180 has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder Figure 14 and Figure 15 outline the overall structure of the input muxing provided in the ADV7180 A maximum of six CVBS inputs can be connected to and decoded by the 64 lead and 48 lead devices and a maximum of three CVBS inputs can be connected to and decoded by the 40 lead and 32 lead LFCSP devices As shown in the Pin Configurations and Function Descriptions section these analog input pins lie in close proximity to one anoth
104. Bottom lines of memory CCMP 2 0 chroma comb mode PAL Three line adaptive for CTAPSN 01 Four line adaptive for CTAPSN 10 Five line adaptive for CTAPSN 11 Disable chroma comb Fixed two line for CTAPSN 01 Fixed three line for CTAPSN 10 Fixed four line for CTAPSN 11 Top lines of memory Fixed three line for CTAPSN 01 Fixed four line for CTAPSN 10 Fixed five line for CTAPSN 11 All lines of memory Fixed two line for CTAPSN 01 Fixed three line for CTAPSN 10 Fixed four line for CTAPSN 11 Bottom lines of memory CTAPSP 1 0 chroma comb taps PAL Not used Adapts five lines to three lines two taps Adapts five lines to three lines three taps Adapts five lines to four lines four taps Rev J Page92 of 114 ADV7180 Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes Ox3A ADC control MUX PDN override mux 0 No control over power down override power down for muxes and associ ated channel circuit 1 Allows power down of MUX0 MUX1 MUX2 associated channel circuit When INSEL 3 0 is used unused channels are automatically powered down PWRDWN MUX 2 0 MUX2 and associat
105. C going low on an odd i i field by a line relative to PVEND PVENDDELE PAL VSYNC End Delay on Even Field foni Address 0 9 6 1 0 0 1 When PVENDDELE is 0 default there is no delay i i Setting PVENDDELE to 1 delays VSYNC going low on an even ADDITIONAL ADDITIONAL field by a line relative to PVEND TUINE TLINE PVENDSIGN PAL VSYNC End Sign Address 0xE9 5 Setting PVENDSIGN to 0 default delays the end of VSYNC FIELD 5 set for user manual programming 5 Setting PVENDSIGN to 1 advances the end of VSYNC not Figure 47 PAL F Toggle recommended for user programming PVEND 4 0 PAL VSYNC End Address OxE9 4 0 The default value of PVEND is 10100 indicating the PAL VSYNC end position For all NTSC PAL VSYNC timing controls both the V bit in the AV code and the VSYNC signal on the VS pin are modified Rev J Page 53 of 114 ADV7180 SYNC PROCESSING The ADV7180 has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video If desired the blocks can be disabled via the following two bits ENHSPLL and ENVSPROC ENHSPLL Enable HSYNC Processor Address 0x01 6 The HSYNC processor is designed to filter incoming HSYNCS that have been corrupted by noise providing improved performance for video signals with stable time bases but poor SNR Setting ENHSPLL to 0 disables the HSYNC processor Setting ENHSPLL to 1 default enables the HS
106. CHNG is 0 default Gemstar PDC UTC or VPS data is not detected When VDP GS VPS PDC UTC CHNG Q is 1 Gemstar PDC UTC or VPS data is detected VDP VITC Address 0x4E 6 User Sub Map Read Only When VDP_VITC_Q is 0 default VITC data is not detected When VITC Q is 1 VITC data is detected Interrupt Status Clear Register Details It is not necessary to write 0 to these write only bits because they automatically reset after they are set to 1 self clearing VDP CCAPD Address Ox4F 0 User Sub Map Setting VDP CCAPD to 1 clears the CCAP bit VDP CGMS WSS CHNGD Address Ox4F 2 User Sub Map Setting VDP CGMS WSS CHNGD to 1 clears the VDP CGMS WSS CHNGD Q bit VDP GS VPS PDC UTC CHNG CIR Address 0x4F 4 User Sub Map Setting VDP GS VPS PDC UTC CHNG CLR to 1 clears the VDP GS VPS PDC UTC CHNG Q bit VDP VITC CLR Address 0x4F 6 User Sub Map Setting VITC CLR to 1 clears the VDP_VITC_Q bit Rev J 62 of 114 lC READBACK REGISTERS Teletext Because teletext is a high data rate standard the decoded bytes are available only as ancillary data However a AVL bit is provided in so that the user can check whether the VDP detects teletext Note that the TTXT AVL bit is a plain status bit and does not use the protocol identified in the Interface section TTXT AVL Teletext Detected Status Address 0x78 7
107. CK x 1 fsc lock now FOLLOW PW x 1 peak white AGC mode active AD RESULT 2 0 auto NTSC M J Detected detection result reports olol1 NTSC 4 43 standard the standard of the input video 0 10 0 1 1 PAL 60 PAL B G H I D 1 01 SECAM 1 11 0 PAL Combination 1 1 1 SECAM 525 COL_KILL x 1 color kill is active Color kill Ox11 IDENT IDENT 7 0 provides 1 1 1 0 0 identification on the value Ox1C revision of the part 0x12 Status 2 MVCS DET x MV color striping detected 1 detected read only MVCS T3 x MV color striping type 0 Type 2 1 3 MV PS DET x MV pseudosync detected 1 detected MV AGC DET x MV AGC pulses detected 1 detected LL NSTD x Nonstandard line length 1 detected FSC NSTD x fsc frequency nonstandard 1 detected Reserved x x 0x13 Status 3 INST_HLOCK x 1 horizontal lock achieved Unfiltered read only GEMD x 1 Gemstar data detected SD OP 50Hz 0 SD 60 Hz detected SD field rate detect 1 SD 50 Hz detected Reserved x FREE RUN ACT x 1 free run mode active Blue screen output STD FLD LEN x 1 field length standard Correct field length found Interlaced x 1 interlaced video detected Field sequence found PAL SW LOCK x 1 2 swinging burst detected Reliable swinging burst sequence 0x14 Analog Reserved 0 0 1 O Setto default clamp control CCLEN current clamp 0 Current sources switched off enable allows the user 1 Current source
108. CLEAR 0 Does not reinitialize the GS PDC VPS This is a self clearing bit UTC readback registers 1 Refreshes the GS PDC VPS UTC readback registers Reserved 0 VITC CLEAR 0 Does not reinitialize the VITC readback This is a self clearing bit registers 1 Reinitializes the VITC readback registers Reserved 0 0x79 VDP DATA 0 CCAP BYTE 1 7 0 Decoded Byte 1 of CCAP read only Ox7A VDP CCAP DATA 1 CCAP BYTE 2 7 0 Decoded Byte 2 of CCAP read only 0x7D VDP CGMS WSS DATA 0 CGMS_CRC 5 2 Decoded sequence for CGMS read only Reserved 010 040 Ox7E VDP CGMS WSS DATA 1 CGMS WSS 13 8 x X X Decoded CGMS WSS data read only CGMS CRC 1 0 x x Decoded CRC sequence for CGMS Ox7F VDP CGMS WSS DATA 2 CGMS WSS 7 0 X X X X X X x Decoded CGMS WSS data read only 0x84 VDP GS VPS PDC UTC 0 GS VPS PDC UTC BYTE 0 7 0 Decoded Gemstar VPS PDC UTC data read only 0x85 VDP GS VPS PDC UTC 1 GS VPS PDC UTC BYTE 1 7 0 X X X X X X X X Decoded Gemstar VPS PDC UTC data read only Rev J Page 105 of 114 ADV7180 Bit Shading Indicates Interrupt and VDP Map Default State Address Register Bit Description 7165 4132 10 Comments Notes 0x86 VDP GS VPS PDC UTC 2 GS VPS PDC UTC BYTE 2 7 0 X X X X X X X X Decoded Gemstar V
109. Combination N 1101 PAL Combination N with pedestal 1110 SECAM 1111 SECAM with pedestal AD_SEC525_EN Enable Autodetection of SECAM 525 Line Video Address 0x07 7 Setting AD_SEC525_EN to 0 default disables the autodetection of a 525 line system with a SECAM style FM modulated color component Setting AD_SEC525_EN to 1 enables the detection of aSECAM style FM modulated color component Rev J Page 27 of 114 ADV7180 AD SECAM EN Enable Autodetection of SECAM Address 0x07 6 Setting AD SECAM EN to 0 default disables the autodetection of SECAM Setting AD SECAM EN to 1 enables the detection of SECAM AD NA443 EN Enable Autodetection of NTSC 4 43 Address 0x07 5 Setting AD N443 EN to 0 disables the autodetection of NTSC style systems with a 4 43 MHz color subcarrier Setting N443 EN to 1 default enables the detection of NTSC style systems with a 4 43 MHz color subcarrier AD P60 EN Enable Autodetection of PAL 60 Address 0x07 4 Setting AD P60 EN to 0 disables the autodetection of PAL systems with a 60 Hz field rate Setting AD P60 EN to 1 default enables the detection of PAL systems with a 60 Hz field rate AD PALN EN Enable Autodetection of PAL N Address 0x07 3 Setting PALN EN to 0 default disables the detection of the PAL N standard Setting PALN EN to 1 enables the detection of the PAL standard AD PALM EN Enable Autodetection of PAL M Address 0x07 2
110. Default Value Y RW DEF_Y 5 DEF Y 4 DEF Y 3 DEF Y 2 DEF Y 1 DEF Y 0 DEF VAL DEF VAL EN 00110110 36 AUTO EN 13 00 Default Value RW DEF_C 7 DEF_C 6 DEF_C 5 DEF_C 4 DEF C 3 DEF 21 DEF C 1 DEF C 0 01111100 7C 14 0 ADI Control 1 RW SUB USR EN 00000000 00 15 OF Power management RW Reset PWRDWN PDBP 00000000 00 16 10 Status 1 R COL AD RESULT 2 AD RESULT 1 AD_RESULT O FOLLOW PW FSC LOCK LOST LOCK LOCK 17 11 IDENT IDENT 7 IDENT 6 IDENT 5 IDENT 4 DENTI 3 IDENT 2 IDENT 1 DENTI O 00011100 1C 18 12 Status 2 R FSC NSTD LLNSTD MV AGC DET MV PS DET MVCS MVCS DET 19 13 Status3 R PAL SW LOCK Interlaced STDFLDLEN FREE RUN ACT Reserved SD OP 50Hz GEMD INST HLOCK 20 14 Analog clamp control RW VCLEN CCLEN 00010010 12 21 15 Digital Clamp Control 1 RW DCIT1 DCTIO DCFE 0000xxxx 00 22 16 Reserved 23 17 Shaping Filter Control 1 RW CSFM 2 CSFM 1 CSFMIO 5 41 YSFMI3 YSFM 2 YSFM 1 YSFMIO 00000001 01 24 18 Shaping Filter Control2 RW WYSFMOVR WYSFMIA WYSFMI3 WYSFMI2 WYSFM 1 WYSFMIO 10010011 93 25 19 Comb filter control RW NSFSEL 1 NSFSEL O PSFSEL 1 PSFSEL O 11110001 F1 29 10 ADI Control 2 RW TRI LLC EN28XTAL 01000xxx 40 39 27 Pixel delay control RW SWPC AUTO PDC EN CTA 2 1 0 LTA 1 LTA O 01011000 58 43 2B Misc gain control RW CKE PW UPD 11100001 E1 44 2C AGC mode control RW LAGC 2 LAGC 1 0 CAGC 1 0 101
111. ELD LINE NUMBER 4 0 0 0 ID2 User Data Word 3 9 EP EP 0 0 0 0 VDP TYPE 1 0 0 0 ID3 User Data Word 4 10 VBI WORD 1 7 0 0 0 104 User Data Word 5 11 VBI WORD 2 7 0 0 0 ID5 User Data Word 6 12 VBI WORD 3 7 0 0 0 ID6 User Data Word 7 13 VBI WORD 4 7 0 0 0 ID7 User Data Word 8 14 VBI WORD 5 7 0 0 0 ID8 User Data Word 9 Pad 0x200 these padding words may be present depending on ancillary data type user data word 3 1 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 1 B8 Checksum 0 0 CS checksum word Table 77 shows the framing code and its valid length for VBI data standards supported by VDP Example For teletext B WST the framing code byte is 11100100 0xE4 with bits shown in the order of transmission WORD 1 0x27 WORD 2 0x00 WORD 3 0x00 translated into in the ancillary data stream for nibble mode are as follows UDW5 5 2 0010 UDW6 5 2 0111 UDWT7 5 2 0000 undefined bits set to 0 UDWS 5 2 0000 undefined bits set to 0 UDW 5 2 0000 undefined bits set to 0 UDW10 5 2 0000 undefined bits set to 0 For byte mode UDW5 9 2 0010_0111 UDW6 9 2 0000 0000 undefined bits set to 0 UDWT7 9 2 0000 0000 undefined bits set to 0 Rev J Page 59 of 114 ADV7180 Data Bytes The data bytes in the ancillary data stream are as follows WORD 4 to WORD N 3 contain the data words VBI WORD 4 Byte 1 7 0
112. ES 1 THE EXPOSED PAD MUST BE CONNECTED TO GND Figure 8 32 Lead LFCSP Pin Configuration 05700 057 Table 9 32 Lead LFCSP Pin Function Descriptions Pin No Mnemonic Type Description 1 HS Horizontal Synchronization Output Signal 2 29 DGND G Ground for Digital Supply 3 DVDDIO P Digital I O Supply Voltage 1 8 V to 3 3 V 4 SFL Subcarrier Frequency Lock This pin contains serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder 5to 10 15 16 P7 to P2 P1 PO O Video Pixel Output Port 11 LLC Line Locked Output Clock for the Output Pixel Data Nominally 27 MHz but varies up or down according to video line length 12 XTAL1 This pin should connected to the 28 6363 MHz crystal or not connected if an external 1 8 V 28 6363 MHz clock oscillator source is used to clock the ADV7180 In crystal mode the crystal must be a fundamental crystal 13 XTAL Input Pin for the 28 6363 MHz Crystal This pin can be overdriven by an external 1 8 V 28 6363 MHz clock oscillator source In crystal mode the crystal must be a fundamental crystal 14 30 DVDD P Digital Supply Voltage 1 8 V 17 ELPF The recommended external loop filter must be connected this ELPF as shown in Figure 60 18 PVDD P PLL Supply Voltage 1 8 V 19 23 24 1 to Ain3 Analog Video Input Channels 20 VREFP Internal Voltage Reference Ou
113. FSC 3 0 3 5 4 0 4 5 5 0 5 5 6 0 FREQUENCY MHz Figure 35 PAL IF Filter Compensation 05700 053 05700 054 ADV7180 AV CODE INSERTION AND CONTROLS This section describes the controls that affect the following e Insertion of AV codes into the data stream e Data blanking during the vertical blank interval VBI e The range of data values permitted in the output data stream e The relative delay of luma vs chroma signals Some of the decoded VBI data is inserted during the horizontal blanking interval See the Gemstar Data Recovery section for more information BT 656 4 ITU R BT 656 4 Enable Address 0x04 7 Between Revision 3 and Revision 4 of the ITU R BT 656 standards the ITU has changed the toggling position for the V bit within the SAV EAV codes for NTSC The ITU R BT 656 4 standard bit allows the user to select an output mode that is compliant with either the previous or new standard For further information visit the International Telecommunication Union website Note that the standard change only affects NTSC and has no bearing on PAL When ITU R BT 656 4 is 0 default the ITU R BT 656 3 specification is used The V bit goes low at EAV of Line 10 and Line 273 When ITU R BT 656 4 is 1 the ITU R BT 656 4 specification is used The V bit goes low at EAV of Line 20 and Line 283 SD_DUP_AV Duplicate AV Codes Address 0x03 0 Depending on the output interface width
114. G is 00101 indicating the PAL VSYNC begin position For all NTSC PAL VSYNC timing controls the V bit in the AV code and the VSYNC signal on the VS pin are modified Register Register Name Write 0x31 VS FIELD Control 1 Ox1A 0x32 VS FIELD Control 2 0x81 0x33 VS FIELD Control 3 0x84 0x34 HS Position Control 1 0x00 0x35 HS Position Control 2 0x00 0x36 HS Position Control 3 0x7D 0x37 Polarity OxA1 OxE8 PAL V bit begin 0x41 0 9 PAL V bit end 0x84 OxEA PAL F bit toggle 0x06 PVBEGDELO PAL VSYNC Begin Delay on Odd Field Address 0 8 7 When PVBEGDELO is 0 default there is no delay Setting PVBEGDELO to 1 delays VSYNC going high on an odd field by a line relative to PVBEG PVBEGDELE PAL VSYNC Begin Delay on Even Field Address 0xE8 6 When PVBEGDELE is 0 there is no delay Setting PVBEGDELE to 1 default delays VSYNC going high on an even field by a line relative to PVBEG PVBEGSIGN PAL VSYNC Begin Sign Address 0xE8 5 Setting PVBEGSIGN to 0 delays the beginning of VSYNC Set for user manual programming Setting PVBEGSIGN to 1 default advances the beginning of VSYNC not recommended for user programming Rev J 52 of 114 pcc ADVANCE BEGIN OF VSYNC BY PVBEG 4 0 DELAY BEGIN OF VSYNC BY PVBEG 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO PVBEGDELO PVBEGDELE 0 1 t ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE ADVANCE BY 0
115. HS 11 01011 SVHS 10 01101 SVHS 12 01100 SVHS 11 01110 SVHS 13 01101 SVHS 12 01111 SVHS 14 01110 SVHS 13 10000 SVHS 15 01111 SVHS 14 10001 SVHS 16 10000 SVHS 15 10010 SVHS 17 10001 SVHS 16 10011 default SVHS 18 CCIR 601 10010 10100 to 11111 Do not use 10011 SVHS 18 CCIR 601 10100 The filter plots Figure 24 show the SVHS 1 narrowest to 10101 2 SVHS 18 widest shaping filter settings Figure 26 shows the 10110 PAL notch filter responses The NTSC compatible notches are 19111 shown in Figure 27 1000 COMBINED Y ANTIALIAS SVHS LOW PASS FILTERS 11001 NTSC NN1 Y RESAMPLE 11010 NTSC NN2 11011 NTSC NN3 N 11100 NTSC WN1 10 11101 NTSC WN2 me 11110 NTSC WN3 8 11111 Reserved a 30 pH 4 0 Wideband Y Shaping Filter Mode Address 0x18 4 0 50 WYSFM 4 0 bits allow the user to manually select a shaping 60 filter for good quality video signals for example CVBS with 3 stable time base luma component of YPrPb and luma component a 2 4 6 8 10 12 i of Y C The WYSEM bits are active only if the WYSFMOVR bit FREQUENCY MHz is set to 1 See the general discussion of the shaping filter settings in Figure 24 Y SVHS Combined Responses the Y Shaping Filter section Rev J Page 34 of 114 CHROMA FILTER Data from the digital fine clamp block is processed by the three sets of filters that follow Note that the data format at this point is CVBS for CVBS inputs
116. KB 78 4E Interrupt Status4 VDP_VITC_Q VDP_GS_VPS_ VDP_CGMS_ VDP_CCAPD_Q PDC UTC WSS CHNGD Q CHNG Q 79 4F Interrupt Clear 4 Ww VDP VITC CLR VDP GS 5 _ VDP _ VDP CCAPD 00x0x0x0 00 PDC UTC WSS CHNGD CHNG CLR CLR 80 50 Interrupt Mask 4 RW VDP VITC MSKB VDP GS VPS VDP _ VDP CCAPD 00x0x0x0 00 PDC_UTC_ WSS_CHNGD_ MSKB CHNG_MSKB MSKB 96 60 VDP_Config_1 RW WST PKT VDP_TTXT_ VDP_TTXT_ VDP_TTXT_ 10001000 88 DECODE_ TYPE_MAN_ TYPE 11 MANIO DISABLE ENABLE 97 61 VDP Config 2 RW AUTO DETECT 0001xx00 10 GS TYPE 98 62 VDP ADF Config 1 RW ADF ENABLE ADF MODE ADF MODEIO _ ADF_DID 4 ADF DID 3 ADF DID 2 ADF DID 1 ADF DID O 000101001 15 99 63 VDP ADF Config 2 RW DUPLICATE ADF ADF_SDID 5 50104 SDID3 SDID 2 0101 SDID O Ox101010 2 100 64 LINE MAN LINE PGM DATA DATA VBI DATA DATA Oxx0000 00 P318 3 P318 2 P318 1 P318 0 101 65 VDP LINE 00 RW VBI DATA VBI DATA _ DATA VBI DATA VBI DATA _ VBI DATA VBI DATA _ VBI DATA 00000000 00 P6 N23 3 P6 N23D2 P6 N23 1 P6_N23 0 P319_N286 3 P319_N286 2 P319 N286 1 P319 N286 0 102 66 VDP LINE 010 RW VBI DATA VBI DATA _ VBI DATA _ VBI DATA VBI DATA _ VBI DATA VBI DATA VBI DATA 00000000 00 P7 N24 3 P7 24121 P7 N24 1 P7 24 01 P320 N287 3 P320 N287 2 P320 N287 1 P320 N287 0 103 67 VDP LINE 011 RW VBI DATA VBI_DATA_ VBI_DAT
117. M 37 RESET RESET EXTERNAL gt NC 715 48 LOOP FILTER POWER DOWN gt QOPWRDWN i ELPF 1 1 Dvppio 3 3V l 1 1 385 ALSB 12 1 69kQ m TIE PC ADDRESS 42 5 KEEP CLOSE TO THE ADV7180 AND ON TIE LOW PC ADDRESS 40 V THE SAME SIDE OF PCB AS THE ADV7180 14 L 330 40 LLCO gt OSCLK 39 9 SDA gt OSDATA 5 330 a NOTES 1 NC NO CONNECT REFER TO ANALOG DEVICES CRYSTAL APPLICATION NOTE FOR PROPER CAPACITOR LOADING Figure 59 48 Lead LQFP Typical Connection Diagram Rev J Page 110 of 114 05700 061 ADV7180 ANALOG INPUT 1 0 1yF Dypp 1 8V Dyppio Avpp_1 8V 360 390 0 1uF 0 1pF 0 1 T d ANALOG INPUT 2 0 1yF v Pypp 1 8V 360 390 Dyppio 3 3V Dypp_1 8V 0 1uF Avypp 1 8V 10nF ANALOG INPUT 3 0 1uF 360 P 0 7 390 B L Aw gt ml an3 gt P2 9g p amp BIT 656 DATA RESET ADV7180KCP32Z LFCSP 32 KEEP VREFN AND VREFP CAPACITOR AS CLOSE AS POSSIBLE TO THE ADV7180 AND ON THE SAME SIDE OF THE AS THE 7180 0 1pF LOCATE CLOSE TO AND ON THE SAME SIDE AS THE ADV7180 1 1 28 63636MHz C 1 1 1 4kO ALSB TIED gt 2 ADDRESS 42h 9 ALSB TIED LOW gt PC ADDRESS 40h 50 sciK gt sDA gt lt uc lt sFL lt vs FiELD lt Pypp 1 8V EXTERNAL LOOP FILTER pz Eu Eg r
118. N20 3 22 N20 2 22 N20 1 P22 20 0 P335 N283 3 P335 N283 2 P335 N283 1 P335 N283 0 Rev J Page82 of 114 ADV7180 Address Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Reset Value Hex 118 76 VDP LINE 020 RW VBI DATA VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 00000000 00 P23_N21 3 P23_N21 2 P23_N21 1 P23_N21 0 P336 N284 3 P336 N284 2 P336 N284 1 P336 N284I0 119 77 VDP LINE 021 RW VBI DATA VBI DATA _ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI DATA _ VBI DATA _ 00000000 00 P24 22131 P24 N22 2 P24_N22 1 P24 N22I0 P337 N285 3 P337 N285 2 P337 N285 1 P337 285101 120 78 VDP STATUS R XT AVL VITC AVL GS DATA GS PDC VPS CGMS WSS AVL CC EVEN FIELD AVL TYPE UTC AVL 120 78 VDP STATUS _ Ww VITC CLEAR GS PDC VPS CGMS WSS _ CC CLEAR 00000000 00 CLEAR UTC CLEAR CLEAR 121 79 VDP CCAP R CCAP BYTE 1 7 BYTE 1 6 CCAP BYTE 1 5 CCAP BYTE 1 4 CCAP BYTE 1 3 CCAP BYTE 1 2 CCAP BYTE 1 1 CCAP BYTE 1 01 DAT
119. Noconnect No connect 1 0 1 5 3 1 1 O No connect 1 1 1 No connect No connect Reserved rS MUX enable 0 Disable This bit must be set manual setting of the 1 Enable to 1 for manual input signal muxing muxing OxDC Letterbox LB TH 4 0 sets the 0 1 1 0 0 Default threshold for the detection of Control 1 threshold value that black lines determines if a line is 01101 to 10000 increase threshold black 00000 to 01011 decrease threshold Reserved 1 0 1 Set as default OxDD Letterbox LB EL 3 0 programs the 1 1 0 0 LBdetection ends with the last line of Control 2 end line of the activity active video on a field 1100b 262 525 window for LB detection end of field LB SL 3 0 programs the 011 0 0 Letterbox detection aligned with the start line of the activity start of active video 0100b 23 286 NTSC window for LB detection start of field OxDE ST Noise ST NOISE 10 8 x x x Readback 1 ST_NOISE_VLD x When 1 ST_NOISE 10 0 is valid read only OxDF ST Noise ST NOISE 7 0 x x x x x x x x Readback 2 read only OxE1 SD Offset Cb SD OFF Cb 7 0 adjusts 0 0 312 mV offset applied to the Cb channel the hue by selecting the 0 OmV offset applied to the Cb channel offset for the Cb channel 1 1 1 1 1 1 1 1 312 mV offset applied to the Cb channel OxE2 SD Offset Cr SD OFF Cri 7 0 adjusts 0 312mVoffsetapplied to the Cr chann
120. P P 15 0 48 Lead LQFP 40 Lead LFCSP or 32 Lead LFCSP OF SEL 3 0 Format P 15 8 P 7 0 P 7 0 0000 to 0001 Reserved Reserved do not use 0010 16 bit at LLC 4 2 2 Y 7 0 CrCb 7 0 Not valid 0011 default 8 bit at LLC 4 2 2 default YCrCb 7 0 Three state YCrCb 7 0 0100 to 1111 Reserved Reserved do not use Rev J 76 of 114 ADV7180 GPO CONTROL The 64 lead 48 lead LQFP has four general purpose Table 103 General Purpose Output Truth Table outputs GPO These outputs allow the user to control other GPO ENABLE GPO 3 0 GPO3 GPO2 GPO1 GPOO 9 devices a system via the port of the device 70 lw z iz The 40 lead and 32 lead LFCSP do not have GPO pins 1 0000 0 0 0 0 GPO ENABLE General Purpose Output Enable 1 0001 0 0 0 1 Address 0x59 4 1 0010 0 0 1 0 1 0011 0 0 1 1 When GPO ENABLE is set to 0 all pins three stated 1 0100 0 1 0 0 When GPO ENABLE is set to 1 all GPO pins are in a driven 1 0101 0 1 0 1 state The polarity output from each GPO is controlled by 1 0110 0 1 1 0 GPO 3 0 for the 64 lead and 48 lead LOFP 1 0111 0 1 1 1 GPO 3 0 General Purpose Outputs Address 0x59 3 0 1000 d 0 1 1001 1 0 0 1 Individual control of the four GPO ports is achieved using 1 1010 1 0 1 0 GPO 3 0 1 1011 1 0 1 1 GPO ENABLE must be set to 1 for the GPO pins to become active 1 1100 1 1 0 0 GPO O0 1 1101 1 1 0 1
121. P318 VDP LINE 00 3 0 100 0x64 VBI DATA P319 N286 VDP LINE 00F 3 0 101 0x65 VBI DATA P320 N287 VDP LINE 010 3 0 102 0x66 VBI DATA P321 288 VDP LINE 011 3 0 103 0x67 VBI DATA P322 VDP LINE 012 3 0 104 0x68 VBI DATA P323 VDP LINE 013 3 0 105 0x69 VBI DATA P324 N272 VDP LINE 014 3 0 106 Ox6A VBI_DATA_P325_N273 VDP_LINE_015 3 0 107 0 6 VBI DATA P326 N274 VDP LINE 016 3 0 108 0 6 VBI DATA P327 275 VDP LINE 017 3 0 109 0x6D VBI_DATA_P328_N276 VDP_LINE_018 3 0 110 Ox6E VBI DATA P329 277 VDP LINE 019 3 0 111 Ox6F VBI DATA P330 N278 VDP LINE 01A 3 0 112 0x70 VBI DATA P331 279 VDP LINE 01B 3 0 113 0x71 VBI_DATA_P332_N280 VDP_LINE_01C 3 0 114 0x72 VBI_DATA_P333_N281 VDP_LINE_01D 3 0 115 0x73 VBI_DATA_P334_N282 VDP_LINE_01E 3 0 116 0x74 VBI_DATA_P335_N283 VDP_LINE_01F 3 0 117 0x75 VBI_DATA_P336_N284 VDP_LINE_020 3 0 118 0x76 VBI_DATA_P337_N285 VDP_LINE_021 3 0 119 0x77 Note that full field detection lines other than VBI lines of any standard can also be enabled by writing into the DATA _ P24 N22 3 0 and DATA P337 N285 3 0 registers So if VBI DATA P24 N22 3 0 is programmed with any teletext standard then teletext is decoded off for the entire odd field whether the data in line is teletext the actual standard is The corresponding register for the even field is DATA _ identified by the VDP TTXT TYPE MAN bit P337 N285 5 0 To program the VDP TTXT MAN bit the VDP TTXT TYPE
122. PO2 0 Outputs 0 to GPO3 1 Outputs 1 to GPO3 GPO ENABLE 0 GPO 3 0 three stated 1 GPO 3 0 enabled Reserved Ox8F Free Run Line Reserved 0 0 0 0 Setto default Length 1 LLC PAD SEL 2 0 enables olojo LLC nominal 27 MHz selected out manual selection of the on LLC pin clock for the LLC pin 1 0 1 LLC nominal 13 5 MHz selected out For 16 bit 4 2 2 out on LLC pin SEL 3 0 0010 Reserved 0 Set to default 0x99 CCAP1 CCAP1 7 0 closed x x X X x x x CCAP1 7 contains parity bit for Byte 0 read only caption data register Ox9A CCAP2 CCAP2 7 0 closed x x x X x x x CCAP2 7 contains parity bit for Byte 0 read only caption data register Ox9B Letterbox 1 LB LCT 7 0 letterbox x X xx xXx Reports the number of black lines This feature read only data register detected at the top of active video examines the active P video at the start 0x9C Letterbox 2 LB LCM 7 0 letterbox x Reports the number of black lines i 1 and end of each read only data register detected in the bottom half of active field it enables video if subtitles are detected format detection Ox9D Letterbox 3 LB LCB 7 0 letterbox x x x x x x X X Reports the number of black lines even if the video is read only data register detected at the bottom of active video not accompanied by a CGMS or WSS sequence OxB2 CRC enable Reserved 0 0 Setasdefault write only ENABLE enab
123. PS PDC UTC data read only 0x87 VDP GS VPS PDC UTC 3 GS VPS PDC UTC BYTE 3 7 0 Decoded Gemstar VPS PDC UTC data read only 0x88 VDP VPS PDC UTC 4 VPS PDC UTC BYTE 4 7 0 Decoded VPS PDC UTC data read only 0x89 VDP VPS PDC UTC 5 VPS PDC UTC BYTE 5 7 0 Decoded VPS PDC UTC data read only Ox8A VDP_VPS_PDC_UTC_6 VPS_PDC_UTC_BYTE_6 7 0 Decoded VPS PDC UTC data read only Ox8B VDP VPS PDC UTC 7 VPS PDC UTC BYTE 7 7 0 Decoded VPS PDC UTC data read only 0 8 VDP VPS PDC UTC 8 VPS PDC UTC BYTE 8 7 0 Decoded VPS PDC UTC data read only 0x8D VDP_VPS_PDC_UTC_9 VPS PDC UTC BYTE 9 7 0 Decoded VPS PDC UTC data read only Ox8E VDP VPS PDC UTC 10 VPS PDC UTC BYTE 10 7 0 Decoded VPS PDC UTC data read only Ox8F VDP VPS PDC UTC 11 VPS PDC UTC BYTE 11 7 0 Decoded VPS PDC UTC data read only 0x90 VDP_VPS_PDC_UTC_12 VPS_PDC_UTC_BYTE_12 7 0 Decoded VPS PDC UTC data read only 0x92 VDP VITC DATA 0 DATA 0 7 0 X X X X X X X X Decoded VITC data read only 0x93 VDP VITC DATA 1 VITC DATA 1 7 0 Decoded VITC data read only 0x94 VDP VITC DATA 2 DATA 217 0 X X X X X X X X Decoded VITC data read only 0x95 VDP VITC DATA
124. S Y RESAMPLE AMPLITUDE dB 05700 022 FREQUENCY MHz Figure 27 Combined Y Antialias Filter NTSC Notch Filters COMBINED C ANTIALIAS SHAPING FILTER C RESAMP 10 20 ATTENUATION dB amp 40 05700 023 0 1 2 3 4 5 6 FREQUENCY MHz Figure 28 Chroma Shaping Filter Responses ADV7180 CSFM 2 0 C Shaping Filter Mode Address 0x17 7 5 The C shaping filter mode bits allow the user to select from a range of low pass filters for the chrominance signal When switched in automatic mode the widest filter is selected based on the video standard format and user choice see Setting 000 and Setting 001 in Table 37 Table 37 CSFM Function CSFM 2 0 Description 000 default Autoselection 1 5 MHz bandwidth 001 Autoselection 2 17 MHz bandwidth 010 SH1 011 SH2 100 SH3 101 SH4 110 SH5 111 Wideband mode ADC 0 V to 1 V Place this circuit before all analog inputs to the ADV7180 ANALOG VIDEO INPUT 100nF lt AIN_OF_ADv7180 360 390 05700 024 Figure 29 Input Voltage Divider Network The minimum supported amplitude of the input video is determined by the ability of the ADV7180 to retrieve horizontal and vertical timing and to lock to the color burst if present There are separate gain control units for luma and chroma data Both can operate independently of each other The chroma unit however can als
125. S data Step 1 to Step 3 are required only because they have dedicated registers VDP Content Based Data Update For certain standards such as WSS CGMS Gemstar PDC UTC and VPS the information content in the signal transmitted remains the same over numerous lines and the user may want to be notified only when there is a change in the information content or loss of the information content The user must enable content based updating for the required standard through the GS_VPS_PDC_ UTC_CB_CHANGE and WSS_CGMS_CB_CHANGE bits Therefore the available bit shows the availability of that standard only when its content has changed Content based updating also applies to lines with lost data Therefore for standards like VPS Gemstar CGMS and WSS if no data arrives in the next four lines programmed the corresponding available bit in the VDP_STATUS register is set high and the content in the registers for that standard is set to 0 The user must write high to the corresponding clear bit so that when a valid line is decoded after some time the decoded results are available in the C registers with the available status bit set high If content based updating is enabled the available bit is set high assuming the clear bit was written in the following cases e data contents have changed e Data was being decoded and four lines with no data have been detected e No data was being decoded and new data is now being decoded
126. See Table 100 for output configuration for 8 bit and 16 bit modes 14 LLC O This is a line locked output clock for the pixel data output by the ADV7180 It is nominally 27 MHz but varies up or down according to video line length 15 48 NC No Connect Pins These pins are not connected internally 16 XTAL1 This pin should be connected to the 28 6363 MHz crystal or left as a no connect if an external 1 8 V 28 6363 MHz clock oscillator source is used to clock the ADV7180 In crystal mode the crystal must be a fundamental crystal 17 XTAL This is the input pin for the 28 6363 MHz crystal or this pin can overdriven by an external 1 8 V 28 6363 MHz clock oscillator source In crystal mode the crystal must be a fundamental crystal 18 44 DVDD P Digital Supply Voltage 1 8 V 21 PWRDWN A logic low on this pin places the ADV7180 in power down mode 23 28 32 AGND G Analog Ground 24 ELPF The recommended external loop filter must be connected to the ELPF pin as shown Figure 59 25 PVDD P PLL Supply Voltage 1 8 V 26 27 33 to 36 Am 1 to Ain6 Analog Video Input Channels 29 VREFP Internal Voltage Reference Output See Figure 59 for recommended output circuitry 30 VREFN Internal Voltage Reference Output See Figure 59 for recommended output circuitry 31 AVDD P Analog Supply Voltage 1 8 V 37 RESET System Reset Input Active low A minimum low reset pulse width of 5 ms is required to reset the ADV7180 circuitry
127. Setting Description 0x08 default Threshold for maximum luma edges to be interpreted as noise PEAKING GAIN USING BP FILTER FILTER RESPONSE dB 05700 052 0 1 2 3 4 5 6 7 FREQUENCY MHz Figure 33 Peaking Filter Responses DNR TH2 7 0 DNR Noise Threshold 2 Address OxFC 7 0 The DNR2 block is positioned after the luma peaking block and therefore affects the gained luma signal It operates in the same way as the DNRI block but there is an independent threshold control DNR_TH2 7 0 for this block This value is an unsigned 8 bit number used to determine the maximum edge that is interpreted as noise and therefore blanked from the luma data Programming a large value into DNR TH2 7 0 causes the DNR block to interpret even large transients as noise and remove them As a result the effect on the video data is more visible Programming a small value causes only small transients to be seen as noise and to be removed Table 52 DNR_TH2 7 0 Function Setting Description 0x04 default Threshold for maximum luma edges to be interpreted as noise Rev J Page 41 of 114 ADV7180 COMB FILTERS NTSC Comb Filter Settings comb filters of the ADV7180 have been greatly improved to These settings are used for NTSC M J CVBS inputs automatically handle video of all types standards and levels of NSFSEL 1 0 Split Filter Selection NTSC Address 0x19 3 2 quality
128. TE 10 6 BYTE 10 5 BYTE 10 4 BYTE 10 3 BYTE 10 2 BYTE 10 1 BYTE 10 0 143 8F VDP VPS PDC R VPS PDC UIC VPS PDC UTC VPS PDC UIC VPS PDC UTC VPS PDC UIC VPS PDC UTC 5 PDC UTC VPS PDC UTC 11 BYTE 11 7 BYTE 11 6 BYTE 11 5 BYTE 11 4 BYTE 11 3 BYTE 11 2 BYTE 11 1 BYTE 11 0 144 90 VDP VPS PDC R VPS VPS PDC UTC VPS PDC UIC VPS PDC UTC VPS PDC UIC VPS PDC UTC 5 PDC UTC VPS PDC UTC UTC 12 BYTE 12 7 BYTE 12 6 BYTE 12151 BYTE 12141 BYTE 12 3 BYTE 12 2 BYTE 12 1 BYTE 12 0 146 92 VDP VITC DATA 0 VITC DATA 0 7 VITC DATA 0 61 DATA 0 5 VITC DATA 0 41 VITC DATA 0 3 VITC DATA 0 2 VITC DATA O 1 VITC DATA 0 0 147 93 VDP VITC DATA 1 R DATA 1 7 VITC DATA 1 6 DATA 1 5 VITC DATA 1 41 VITC DATA 1 3 VITC DATA 1 2 VITC DATA 1 1 VITC DATA 10 148 94 VDP VITC DATA 2 DATA 2 7 VITC DATA 2 6 DATA 2 5 VITC DATA 2 41 VITC DATA 2 3 VITC DATA 2 2 VITC DATA 2 1 VITC DATA 210 149 95 VDP VITC DATA VITC DATA 3 7 VITC DATA 3 6 DATA 3 5 VITC DATA 3 41 VITC DATA 3 3 VITC DATA 3 2 VITC DATA 3 1 VITC DATA 310 150 96 VDP VITC DATA 4 R DATA 4171 VITC DATA 4 6 DATA 4 5 VITC DATA 4141 VITC DATA 4 3 VITC DATA 4 2 VITC DATA 4 1 VITC DATA 40 151 97 VDP DATA 5 R VITC DATA 5 7 VITC DATA 5 6 DATA 5 5 VITC DATA 5141 VITC DATA 5 3 VITC DATA 5 2 VITC DATA 5 1 VITC DATA 510 152 98 VDP VITC D
129. U 73 l 1 10 1 82nF i 1 69 l 1 KEEP CLOSE TO THE ADV7180 AND ON Figure 60 32 Lead LFCSP Typical Connection Diagram Rev J Page 111 of 114 THE SAME SIDE OF AS THE 7180 05700 056 ADV7180 OUTLINE DIMENSIONS 0 30 0 25 PIN 1 0 18 INDICATOR PIN 1 INDICATOR 0 50 BSC 3 75 3 60 SQ 3 55 T VEI 050 0 25 MIN TOP VIEW 0 40 0 30 FOR PROPER CONNECTION OF 0 80 THE EXPOSED PAD REFER TO 275 THE PIN CONFIGURATION AND i 0 05 MAX FUNCTION DESCRIPTIONS 0 70 sumus 0 02 NOM SECTION OF THIS DATA SHEET ry COPLANARITY SEATING LANE 0 20 REF COMPLIANT STANDARDS MO 220 WHHD 5 WITH EXCEPTION TO EXPOSED PAD DIMENSION Figure 61 32 Lead Lead Frame Chip Scale Package LFCSP_WQ 5mm x 5 mm Body Very Very Thin Quad CP 32 12 Dimensions shown in millimeters 6 10 6 00 sa PIN 1 5 90 INDICATOR PIN 1 INDICATOR TOP VIEW 0 35 FOR PROPER CONNECTION OF 0 80 THE EXPOSED PAD REFER TO 0 75 THE PIN CONFIGURATION AND 0 05 MAX FUNCTION DESCRIPTIONS 0 70 0 02 NOM SECTION OF THIS DATA SHEET COPLANARITY 0 08 SEATING 0 20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO 220 WJJD Figure 62 40 Lead Lead Frame Chip Scale Package LFCSP_WQ 6mm x 6 mm Body Very Very Thin Quad CP 40 9 Dimensions shown in millimeters Rev J Page 112 of 114 08 16 2010 B 05 06 2011 ADV7180 TOP VIEW PINS DOWN
130. US 1 1 1 ACTIVE p a EAV gt HA H BLANK gt a SAV gt a ACTIVE VIDEO _ VIDEO HS T d t t gt i HSE 10 0 HSB 10 0 i ma 4LLC mia c mine D 2 i i vee E Figure 37 HS Timing Rev J Page 47 of 114 05700 028 ADV7180 VS and FIELD Configuration The following controls allow the user to configure the behavior of the VS and FIELD output pins as well as the generation of embedded AV codes The 64 lead LQFP has separate VS and FIELD pins The 48 lead LQFP 40 lead LFCSP and 32 lead LFCSP do not have separate VS and FIELD pins but can output either VS or FIELD on Pin 45 48 lead LQFP Pin 37 40 lead LFCSP or Pin 31 32 lead LFCSP which is the VS FIELD pin SQPE Square Pixel Mode Address 0x01 2 The SQPE bit allows the user to select the square pixel mode This mode is not suitable for poor time based video sources This mode is recommended for professional applications only and should not be used with VCR or tuner sources Setting SOPE to 1 enables square pixel mode The LLC for NTSC is 24 5454 MHz and 29 5 MHz for PAL The crystal frequency does not change VS FIELD Address 0x58 0 This feature is used for the 48 lead LQFP 40 lead LFCSP and 32 lead LFCSP only The polarity of this bit determines what signal appears on the VS FIELD pin When this bit is set to 0 default the FIELD signal is output When this bit is set to 1 t
131. Up Sequence iet aceon 18 Power Down Sequence 18 Universal Power Supply sette 18 Analog enn Re HORE 19 Input Configuration eese tentent 20 Analog Input Muxing eere tentent 21 Antialiasing Filters eite nre EOS 22 Global Control Registers 0 23 Power Saving Modes eene 23 Reset Control bibet dette 23 Global Pin Control eene 23 Global Status Register seen 25 Identification cease teme to et RR Reed 25 Status T enceinte o 25 Autodetection Result 5 1 25 SAE 25 Status 3 Video Processor ede RARE 26 Roe DE 26 SD Chroma eR ERR era 26 Sync Processing iie e tete ee OP ERE RYE TEUER ORE 27 VBI Data Recovery esent 27 General Setup oet E RR 27 Color Controls usce 29 Clamp rer ere thee ere Rete teer 31 Luma Filtered a ee E Een 32 Chroma Filter creer IRR aaa 35 Op ratiori eit te tere rre e RETENIR HR at 36 Chroma Transient Improvement CTI ss 40 Digital Noise Reduction DNR and Luma Peaking Filter 41 Comb Filters dece AD IF Filter Compensation 44 AV Code Insertion and Controls sss 45 Synchronization Output Signals sss 47 SYNC PLOCESSING RP
132. User Sub Map Read Only When TTXT AVL is 0 teletext is not detected When TTXT AVL is 1 teletext is detected WST Packet Decoding For WST only the VDP decodes the magazine and row address of teletext packets and further decodes 8 x 4 hamming coded words of the packet This feature can be disabled using the WST PKT DECODE DISABLE bit Bit 3 Register 0x60 user sub map This feature is valid for WST only Table 80 WST Packet Description ADV7180 WST PKT DECODE DISABLE Disable Hamming Decoding of Bytes in WST Address 0x60 3 User Sub Map Setting WST PKT DECODE DISABLE to 0 enables hamming decoding of WST packets Setting WST PKT DECODE DISABLE to 1 default disables hamming decoding of WST packets For hamming coded bytes the dehammed nibbles are output along with some error information from the hamming decoder as follows e Input hamming coded byte D3 P3 D2 P2 D1 P1 DO PO bits in decoded order Output dehammed byte 1 EO 0 0 D3 D2 DI Di corrected bits Ei error information Table 79 Error Bits in the Dehammed Output Byte Output Data Bits E 1 0 Error Information in Nibble 00 No errors detected Okay 01 Error in P4 Okay 10 Double error Bad 11 Single error found and corrected Okay Table 80 describes the WST packets that are decoded Packet Byte Description Header Packet X 00 18 Magazine number Dehammed Byte 4 gne Row number Deha
133. Voltage DGND 0 3 V to Dvppio 0 3 V Analog Inputs to AGND AGND 0 3 V to Avop 0 3 V Maximum Junction Temperature 140 C max Storage Temperature Range 65 C to 150 C Infrared Reflow Soldering 20 sec 260 C This device is a high performance integrated circuit with an ESD rating of 2 kV and it is ESD sensitive Proper precautions should be taken for handling and assembly ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge A without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product This is a stress rating only functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied Operation beyond the maximum operating conditions for extended periods may affect product reliability Rev J 12 of 114 ADV7180 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 32 LEAD LFCSP 32 INTRQ 31 VS FIELD 30 DVDD 29 DGND 28 SCLK 27 SDATA 26 ALSB 125 RESET PIN1 INDICATOR ADV7180 LFCSP TOP VIEW Not to Scale NOT
134. YNC processor ENVSPROC Enable VSYNC Processor Address 0x01 3 This block provides extra filtering of the detected VSYNCs to improve vertical lock Setting ENVSPROC to 0 disables the VSYNC processor Setting ENVSPROC to 1 default enables the VSYNC processor VBI DATA DECODE The following are the two VBI data slicers on the ADV7180 the VBI data processor VDP and the VBI System 2 The VDP can slice both low bandwidth standards and high bandwidth standards such as teletext VBI System 2 can slice low data rate VBI standards only The VDP is capable of slicing multiple VBI data standards on SD video It decodes the VBI data on the incoming CVBS and Y C or YUV data The decoded results are available as ancillary data in output 656 data stream For low data rate VBI standards like CC WSS CGMS users can read the decoded data bytes from the registers The VBI data standards that can be decoded by the VDP are listed in Table 67 and Table 68 Table 67 PAL Table 68 NTSC Feature Standard Teletext System B and D ITU R BT 653 Teletext System C NABTS ITU R BT 653 EIA 516 Vertical Interval Time Codes VITC Not applicable Copy Generation Management EIA J CPR 1204 IEC 61880 System CGMS Gemstar Not applicable Closed Captioning CCAP EIA 608 Feature Standard Teletext System A C or D ITU R 653 Teletext System B WST ITU R BT 653 Video Programming System VPS ETSI EN 300 231 V 1 3 1 Vertical
135. YSFM 4 0 allows the user to select a different shaping filter mode for good quality composite CVBS component YPrPb and SVHS Y C input signals In automatic mode the system preserves the maximum possible bandwidth for good CVBS sources because they can be success fully combed as well as for luma components of YPrPb and Y C sources because they need not be combed For poor quality signals the system selects from a set of proprietary shaping filter responses that complements comb filter operation to reduce visual artifacts The decisions of the control logic are shown in Figure 23 VIDEO QUALITY BAD GOOD 1 0 AUTO SELECT LUMA SHAPING FILTER TO COMPLEMENT COMB SELECT WIDEBAND FILTER AS PER WYSFM 4 0 YSFM IN AUTO MODE 00000 OR 00001 SELECT AUTOMATIC WIDEBAND FILTER ADV7180 YSFM 4 0 Y Shaping Filter Mode Address 0x17 4 0 The Y shaping filter mode bits allow the user to select from a wide range of low pass and notch filters When switched in automatic mode the filter selection is based on other register selections such as detected video standard as well as properties extracted from the incoming video itself such as quality and time base stability The automatic selection always selects the widest possible bandwidth for the video input encountered The Y shaping filter mode operates as follows e Ifthe YSFM settings specify a filter that is YSFM is set to values other than 00000 o
136. a tuner usually show very large levels of noise 2100 mV A voltage clamp is unsuitable for this type of video signal Instead the ADV7180 employs a set of four current sources that can cause coarse 50 5 mA and fine 0 1 mA currents to flow into and away from the high impedance node that carries the video signal see Figure 22 The following sections describe the signals that can be used to influence the behavior of the clamping block CCLEN Current Clamp Enable Address 0x14 4 The current clamp enable bit allows the user to switch off the current sources in the analog front end altogether This may be useful if the incoming analog video signal is clamped externally When CCLEN is 0 the current sources are switched off When CCLEN is 1 default the current sources are enabled FINE CURRENT SOURCES N J COARSE CURRENT SOURCES ANALOG 4 VIDEO INPUT VIDEO PROCESSOR WITH DIGITAL FINE CLAMP 05700 017 Figure 22 Clamping Overview Rev J 31 of 114 ADV7180 DCT 1 0 Digital Clamp Timing Address 0x15 6 5 The clamp timing register determines the time constant of the digital fine clamp circuitry It is important to note that the digital fine clamp reacts quickly because it immediately corrects any residual dc level error for the active line The time constant from the digital fine clamp must be much quicker than the one from the analog blocks By default the time constant of the digi
137. ain becomes active if the CAGC 1 0 function is switched to manual fixed gain See Equation 2 for calculating a desired gain If read back this register returns the current gain value Depending on the setting in the CAGC 1 0 bits this is either e The chroma manual gain value CAGC 1 0 set to chroma manual gain mode e The chroma automatic gain value CAGC 1 0 set to any of the automatic modes Table 46 CG CMG Function CG 11 0 CMG 11 0 Read Write Description CMG 11 0 Write Manual gain for chroma path CG 11 0 Read Currently active gain 0 ChromaCalibrationFactor 2 Chroma_Gain where ChromaCalibrationFactor is a decimal value between 0 and 4095 Calculation of the Chroma Calibration Factor 1 Apply a CVBS signal with the color bars SMPTE bars test pattern content directly to the measurement equipment 2 Ensure correct termination of 75 O on the measurement equipment Measure chroma output levels 3 Reconnect the source to the CVBS input of the ADV7180 system that has a backend gain of 1 Repeat the measurement of chroma levels 4 Turn off the Chroma AGC and manually change the Chroma Gain Control Register CMG 11 0 until the chroma level matches that measured directly from the source This value in decimal is the chroma calibration factor CKE Color Kill Enable Address 0x2B 6 The color kill enable bit allows the optional color kill function to be
138. al range for video should be restricted to values between 16 and 235 for luma and 16 and 240 for chroma The range bit allows the user to limit the range of values output by the ADV7180 to the recommended value range The ADV7180 does not scale the data to fit within the smaller range Any value outside of the range is ignored In any case it ensures that the reserved values of 255d 0xFF and 00d 0x00 are not presented on the output pins unless they are part of an AV code header Table 61 RANGE Function When AUTO PDC ENis 1 default the ADV7180 automatically determines the LTA and CTA values to have luma and chroma aligned at the output LTA 1 0 Luma Timing Adjust Address 0x27 1 0 The luma timing adjust register allows the user to specify a timing difference between chroma and luma samples There is a functionality overlap with the CTA 2 0 register For manual programming use the following defaults e CVBS input LTA 1 0 00 e Y C input LTA 1 0 01 e YPrPb input LTA 1 0 01 Table 62 LTA Function LTA 1 0 Description 00 default No delay 01 Luma 1 clock 37 ns late 10 Luma 2 clock 74 ns early 11 Luma 1 clock 37 ns early Range Description 0 16 x Y x 235 16 x C P lt 240 1 default 1 lt lt 254 1 lt lt 254 AUTO PDC EN Automatic Programmed Delay Control Address 0x27 6 Enabling AUTO PDC EN activates a function within the ADV7180 that automatically pro
139. apacitance Cour 20 pF POWER REQUIREMENTS Digital Power Supply Dvop 1 65 1 8 2 V Digital I O Power Supply Dvobio 162 33 3 6 V PLL Power Supply Pvop 1 65 1 8 2 0 V Analog Power Supply Avop 1 71 18 1 89 V Digital Supply Current lovop 77 85 mA Digital 1 0 Supply Current Ipvppio 3 5 mA PLL Supply Current 12 15 Analog Supply Current lavoo CVBS input 33 43 mA CVBS input 43 53 mA Y C input 59 75 mA YPrPb input 77 94 mA Power Down Current lovop 6 10 uA lpvopio 0 1 1 levop 1 5 1 5 Total Power Dissipation in Power Down Mode 15 44 uW Power Up Time tewrup 20 ms 1 ADV7180KCP32Z ADV7180WBCP32Z and ADV7180WBST48Z only Applies to ADV7180WBST48Z ADV7180WBST48Z RL ADV7180KST48Z ADV7180KST48Z RL ADV7180BST48Z ADV7180BST48Z RL only 3 Guaranteed by characterization Typical current consumption values are recorded with nominal voltage supply levels and SMPTEBAR pattern gt Maximum current consumption values are recorded with maximum rated voltage supply levels and a multiburst pattern Typical Typ number is measured with DVDDIO 3 3 V and maximum Max number is measured with DVDDIO 3 6 V 7 CVBS input when CVBS IBIAS 3 0 User Map Register 0x52 Bits 3 0 equal 0b 1011 8 CVBS input when CVBS IBIAS 3 0 User Map Register 0x52 Bits 3 0 equal 0b 1101 Recommended setting 9 ADV7180 clocked Rev J Page 8 of 114 VIDEO SPECIFICATIONS ADV7180 Gua
140. ar decoding only on the required line PDC UTC PDC and UTC are data transmitted through Teletext Packet 8 30 Format 2 Magazine 8 Row 30 Design Code 2 or Design Code 3 and Packet 8 30 Format 1 Magazine 8 Row 30 Design Code 0 or Design Code 1 Therefore if PDC or UTC data is to be read through PC the corresponding teletext standard WST or PAL System B should be decoded by VDP The whole teletext decoded packet is output on the ancillary data stream The user can look for the magazine number row number and design code and qualify the data as PDC UTC or neither of these If PDC UTC packets are identified Byte 0 to Byte 12 are updated to the VDP GS VPS PDC UTC 0to VDP VPS PDC UTC 12 registers and the GS PDC VPS UTC AVI bit is set The full packet data is also available in the ancillary data format Note that the data available in the register depends on the status ofthe WST PKT DECODE DISABLE bit Bit 3 Subaddress 0x60 user sub map Rev J Page 67 of 114 ADV7180 Table 85 GS VPS PDC UTC Readback Registers Signal Name Register Location GS VPS PDC UTC BYTE O GS VPS PDC UTC BYTE 1 GS VPS PDC UTC BYTE 2 GS VPS PDC UTC BYTE 3 VPS PDC UTC BYTE 4 7 0 VPS PDC UTC BYTE 5 7 0 VPS PDC UTC BYTE 6 7 0 VPS PDC UTC BYTE 7 7 0 VPS PDC UTC BYTE 8 7 0 VPS PDC UTC BYTE 9 7 0 VPS PDC UTC BYTE 10 7 0 VPS PDC UTC BYTE 11 7 0 VPS PDC UTC BYTE 12 7 0 7 0 7 0 7 0 7 0 cm c
141. ates the properties of the incoming video over several fields taking vertical synchronization information into account Setting SRLS to 0 default selects the FREE RUN signal Setting SRLS to 1 selects the TIME WIN signal FSCLE fsc Lock Enable Address 0x51 7 The FSCLE bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits 1 0 in the Status 1 register This bit must be set to 0 when operating the ADV7180 in YPrPb component mode to generate a reliable HLOCK status bit When FSCLE is set to 0 default only the overall lock status is dependent on horizontal sync lock When FSCLE is set to 1 the overall lock status is dependent on horizontal sync lock and fsc lock CIL 2 0 Count Into Lock Address 0x51 2 0 CIL 2 0 determines the number of consecutive lines for which the lock condition must be true before the system switches into the locked state and reports this via Status 1 1 0 The bit counts the value in lines of video Table 25 CIL Function COL 2 0 Count Out of Lock Address 0x51 5 3 COL 2 0 determines the number of consecutive lines for which the out of lock condition must be true before the system switches into the unlocked state and reports this via Status 1 1 0 It counts the value in lines of video Table 26 COL Function COL 2 0 Number of Video Lines 000 1 001 2 010 5 011
142. ault AGC blank level to sync tip peak white algorithm on 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Freeze gain LAGT 1 0 Luma Automatic Gain Timing Address Ox2F 7 6 The luma automatic gain timing register allows the user to influence the tracking speed of the luminance automatic gain control This register only has an effect if the LAGC 2 0 register is set to 001 or 010 automatic gain control modes If peak white AGC is enabled and active see the Status 1 7 0 Address 0x10 7 0 section the actual gain update speed is dictated by the peak white AGC loop and as a result the LAGT settings have no effect As soon as the part leaves peak white AGC LAGT becomes relevant again Table 40 LAGT Function LG 11 0 Luma Gain Address 0x2F 3 0 Address 0x30 7 0 LMG 11 0 Luma Manual Gain Address 0x2F 3 0 Address 0x30 7 0 Luma gain 11 0 is a dual function register If all of these registers are written to a desired manual luma gain can be programmed This gain becomes active if the LAGC 2 0 mode is switched to manual fixed gain Equation 1 shows how to calculate a desired gain If read back this register returns the current gain value Depending on the setting in the LAGC 2 0 bits the value is one of the following e Luma manual gain value LAGC 2 0 set to luma manual gain mode e Luma automatic gain value LAGC 2 0 set to any of the automatic modes Table 41 LG LMG Function LG
143. autodetect enable 1 Enable NTSC EN NTSC 0 Disable autodetect enable 1 Enable AD PALM EN PALM 0 Disable autodetect enable 1 Enable AD PALN EN PALN 0 Disable autodetect enable 1 Enable AD P60 EN PAL 60 0 Disable autodetect enable 1 Enable AD 443 EN NTSC 4 43 0 Disable autodetect enable 1 Enable AD SECAM EN SECAM 0 Disable autodetect enable 1 Enable AD 5 525 EN SECAM 0 Disable 525 autodetect enable 1 Enable 0x08 Contrast CON 7 0 contrast adjust 1 Luma gain 1 0 00 0 this is the user control for 0x80 gain 1 contrast adjustment OxFF gain 2 2 Ox0A Brightness BRI 7 0 this register 1 0x00 0 IRE controls the brightness Ox7F 30 IRE of the video signal 0x80 30 IRE OxOB Hue HUE 7 0 this register Hue range contains the value for 90 to 4 90 the color hue adjustment Ox0C Default Value Y DEF_VAL_EN 0 Free run mode dependent on default value enable DEF_VAL_AUTO_EN 1 Force free run mode on and output blue screen DEF_VAL_AUTO_EN 0 Disable free run mode When lock is lost default value automatic 1 Enable automatic free run mode free run mode enable blue screen can be enabled to output stable timing clock and aset color DEF Y 5 0 default value is 010 1 1 0 1 Y 7 0 DEF Y 5 0 0 0 Default Y value Y this register holds the Y output in free run default value mode 0x0D Default Value C DEF_C 7 0 default value 0 1 1 1
144. bit The device has 249 subaddresses to enable access to the internal registers Therefore it interprets the first byte as the device address and the second byte as the starting subaddress The subaddresses auto increment allowing data to be written to or read from the starting subaddress A data transfer is always terminated by a stop condition The user can also access any unique subaddress register on a one by one basis without updating all the registers Stop and start conditions can be detected at any stage during the data transfer If these conditions are asserted out of sequence with normal read and write operations they cause an immediate jump to the idle condition During a given SCLK high period the user should only issue one start condition one stop condition or a single stop condition followed by a single start condition If an invalid subaddress is issued by the user the ADV7180 does not issue an acknowledge and returns to the idle condition In auto increment mode if the user exceeds the highest subaddress the following action is taken e mode the highest subaddress register contents continue to be output until the master device issues a no acknowledge This indicates the end of a read A no acknowledge condition occurs when the SDATA line is not pulled low on the ninth pulse e In write mode the data for the invalid byte is not loaded into any subaddress register A no acknowledge is issued by the ADV7180
145. checksum count cycle all checksum and carry bits are preset to 0 Any carry resulting from the checksum count cycle is ignored Table 74 Ancillary Data in Nibble Output Format Byte B9 B8 B7 B6 B5 B4 B3 B2 B1 BO Description 0 0 0 0 0 0 0 0 0 0 0 Ancillary data preamble 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 3 EP EP 0 PC DID6 2 4 0 0 0 DID data identification word 4 EP EP C SDID7 2 5 0 0 0 SDID secondary data identification word 5 EP EP 0 DC 4 0 0 0 Data count 6 EP EP Padding 1 0 VBI_DATA_STD 3 0 0 0 IDO User Data Word 1 7 0 LINE NUMBER 9 5 0 0 ID1 User Data Word 2 8 EP EP EVEN FIELD LINE NUMBER A 0 0 0 ID2 User Data Word 3 9 EP EP 0 0 0 VDP TTXT TYPE 1 0 0 0 ID3 User Data Word 4 10 EP EP 0 0 VBI WORD 1 7 4 0 0 104 User Data Word 5 11 EP EP 0 0 VBI WORD 1 3 0 0 0 ID5 User Data Word 6 12 EP EP 0 0 VBI WORD 2 7 4 0 0 ID6 User Data Word 7 13 EP EP 0 0 VBI WORD 2 3 0 0 0 ID7 User Data Word 8 14 EP EP 0 0 VBI WORD 3 7 4 0 0 ID8 User Data Word 9 Pad 0x200 these padding words may be present depending on ancillary data type user data word 3 1 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 51 8 Checksum CS 0 0 CS checksum word Rev J Page 58 of 114 Table 75 Ancillary Data in Byte Output Format ADV7180 This mode does not fully comply with ITU R BT 136
146. closed caption CCAP or Gemstar compatible Data packets are output if the corresponding enable bit is set see the GDECEL 15 0 Gemstar Decoding Even Lines Address 0x48 7 0 Address 0x49 7 0 and the GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address Ox4B 7 0 sections and the decoder detects the presence of data For video lines where no data is decoded no data packet is output even if the corresponding line enable bit is set Rev J Page 68 of 114 Each data packet starts immediately after the EAV code of the preceding line Figure 52 and Table 86 show the overall structure of the data packet Entries within the packet are as follows Fixed preamble sequence of 0x00 OxFF and OxFF DID The value for the DID marking a Gemstar or CCAP data packet is 0x140 10 bit value SDID which contains information about the video line from which data was retrieved whether the Gemstar transmission was in 1x or 2x format and whether it was retrieved from an even or odd field DATA IDENTIFICATION DATA OPTIONAL PADDING PREAMBLE FOR ANCILLARY DATA ADV7180 Data count byte giving the number of user data words that follow User data section Optional padding to ensure that the length of the user data word section of a packet is a multiple of four bytes requirement as set in ITU R BT 1364 e Checksum byte Table 86 lists the values within a generic data packet that is
147. compatible with the ADV7194 video encoder Reserved 0 Set to default 0x48 Gemstar GDECEL 15 8 see the 1 10 0 0 0 O GDECEL 15 0 16 individual enable bits LSB Line 10 Control 1 Comments column that select the lines of video even field MSB Line 25 0 49 Gemstar GDECEL 7 0 olo o LinetOtoLine 25 that the decoder Default do not Control 2 checks for Gemstar compatible data check for Gemstar compatible data on any lines 10 to 25 in even fields Rev J Page 93 of 114 ADV7180 Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes Ox4A Gemstar GDECOL 15 8 see the 0 0 0 0 0 0 0 0 GDECOL 15 0 16 individual enable bits LSB Line 10 Control 3 Comments column that select the lines of video odd field MSB Line 25 Ox4B Gemstar GDECOL 7 0 o Line 10to Line 25 that the decoder Default do not Control 4 checks for Gemstar compatible data check for Gemstar compatible data on any lines 10 to 25 in odd fields Ox4C Gemstar GDECAD controls the 0 Split data into half byte To avoid 00 FF code Control 5 manner decoded Gemstar 1 Output in straight 8 bit format data is inserted into the horizontal blanking period GDE SEL OLD ADF 0 Enables a new ancillary data system Re
148. ction window ends with the last active video line For an NTSC signal this window is from Line 262 to Line 525 By changing the bits to 1100 the detection window starts on Line 261 and ends on Line 254 Rev J Page 75 of 114 ADV7180 PIXEL PORT CONFIGURATION The ADV7180 has a very flexible pixel port that can be configured in a variety of formats to accommodate downstream ICs Table 100 Table 101 and Table 102 summarize the various functions that the ADV7180 pins can have in different modes of operation The ordering of components for example Cr vs Cb for Channel A Channel B and Channel C can be changed See the SWPC Swap Pixel Cr Cb Address 0x27 7 section Table 100 indicates the default positions for the Cr Cb components OF SEL 3 0 Output Format Selection Address 0x03 5 2 The modes in which the ADV7180 pixel port can be configured are under the control of OF SEL 3 0 See Table 102 for details The default LLC frequency output on the LLC pin is approximately 27 MHz For modes that operate with a nominal data rate of 13 5 MHz 0001 0010 the clock frequency on the LLC pin stays at the higher rate of 27 MHz For information on outputting the nominal 13 5 MHz clock on the LLC pin see the PAD SEL 2 0 LLC Output Selection Address 0x8F 6 4 section Table 100 64 Lead LQFP P15 to PO Output Input Pin Mapping SWPC Swap Pixel Cr Cb Address 0x27 7 This bit allows Cr and Cb samples to be swapped
149. d regardless of content Reserved x VDP VITC OQ 0 VITC data is not available in the VDP 1 VITC data is available in the VDP Reserved x Rev J Page 102 of 114 ADV7180 Bit Shading Indicates Interrupt and VDP Map Default State Address Register Bit Description 71615 4132 10 Comments Notes Ox4F Interrupt Clear 4 VDP CCAPD CLR 0 Do not clear Note that an interrupt write only 1 Clears VDP CCAPD in Register Ox4E for the CCAP Gemstar CGMS Reserved 0 WSS VPS PDC UTC and VDP CGMS WSS CHNGD CLR 0 Do not clear VITC data uses the VDP 1 Clears CGMS WSS CHNGD Q data slicer Reserved 0 VDP GS VPS PDC UTC CHNG CLR 0 Do not clear 1 Clears VDP GS VPS PDC UTC CHNG Reserved 0 VDP VITC CLR 0 Do not clear 1 Clears VDP VITC Reserved 0 0x50 Interrupt Mask 4 VDP CCAPD MSK 0 Masks VDP CCAPD Q Note that an interrupt 1 Unmasks VDP CCAPD Q in Register Ox4E for the CCAP Gemstar CGMS Reseed WSS VPS PDC UTC VDP CGMS WSS CHNGD MSK 0 Masks VDP CGMS WSS CHNGD VITC data uses the VDP 1 Unmasks VDP_CGMS_WSS_CHNGD_Q__ data slicer Reserved 0 VDP_GS_VPS_PDC_UTC_CHNG_MSK 0 Masks VDP GS VPS PDC UTC CHNG 1 Unmasks VDP GS VPS PDC UTC CHNG Q Reserved 0 VDP VITC MSK 0 Masks VDP VITC Q 1 Unmasks VDP VITC Reserved 0 0x60 VDP Co
150. data that should be made available in the C registers the user must program GS VPS PDC 1 0 Register Address 0x9C user sub map PC GS VPS PDC UTC 1 0 VDP Address 0x9C 7 6 User Sub Map Specifies which standard result is available for PC readback GS PDC VPS UTC CLEAR GS PDC VPS UTC Clear Address 0x78 4 User Sub Map Write Only Self Clearing Setting GS PDC VPS UTC CLEAR to 1 reinitializes the GS PDC VPS UTC data readback registers GS PDC VPS UTC AVL GS PDC VPS UTC Available Address 0x78 4 User Sub Map Read Only When GS PDC VPS UTC AVL is 0 no GS PDC VPS or UTC data is detected When GS PDC VPS UTC AVL is 1 one GS PDC VPS or UTC data is detected VDP 65 VPS PDC Readback Registers Address 0x84 to Address 0x90 See Table 85 for information on the readback registers VPS The VPS data bits are biphase decoded by the VDP The decoded data is available in both the ancillary stream and in the readback registers VPS decoded data is available in the VDP GS VPS PDC UTC 0to VDP VPS PDC UTC 12 registers Address 0x84 to Address 0x90 user sub map The GS PDC VPS UTC AVL bit is set if the user programmed PC GS VPS PDC UTC to 01 as explained in Table 84 Gemstar The Gemstar decoded data is made available in the ancillary stream and any one line of Gemstar is also available in the registers for evaluation purposes To read Gemstar results through t
151. dress 0x0C 1 This bit enables the automatic use of the default values for Y Cr and Cb when the ADV7180 cannot lock to the video signal Setting DEF VAL AUTO EN to 0 disables free run mode If the decoder is unlocked it outputs noise Setting DEF VAL EN to 1 default enables free run mode and a colored screen set by user programmable Y Cr and Cb values is displayed when the decoder loses lock CLAMP OPERATION The input video is ac coupled into the ADV7180 Therefore its dc value needs to be restored This process is referred to as clamping the video This section explains the general process of clamping on the ADV7180 and shows the different ways in which a user can configure its behavior The ADV7180 uses a combination of current sources and a digital processing block for clamping as shown in Figure 22 The analog processing channel shown is replicated three times inside the IC While only one single channel is needed for a CVBS signal two independent channels are needed for Y C SVHS type signals and three independent channels are needed to allow component signals YPrPb to be processed The damping can be divided into two sections e Clamping before the ADC analog domain current sources e Clamping after the ADC digital domain digital processing block The ADC can digitize an input signal only if it resides within the ADC 1 0 V input voltage range An input signal with a dc level that is too large or too sma
152. e Some follow on chips require the VS pin to change state only when HS is high or low When VSEHE is 0 default the VS pin goes low inactive in the middle of a line of video even field When VSEHE is 1 the VS pin changes state at the start of a line even field PVS Polarity VS Address 0x37 5 The polarity of the VS pin can be inverted using the PVS bit When PVS is 0 default VS is active high When PVS is 1 VS is active low Rev J 48 of 114 ADV7180 PF Polarity FIELD Address 0 37 3 Table 65 User Settings for NTSC See Figure 39 The polarity of the FIELD pin for the 64 lead LQFP part can be Register Register Name Write inverted using the PF bit 0x31 VS FIELD Control 1 Ox1A The FIELD pin can be inverted using the PF bit 0x32 VS FIELD Control 2 0x81 HO MUS 0x33 VS FIELD Control 3 0x84 When PF is 0 default FIELD is active high 0x34 HS Position Control When PF is 1 FIELD is active low 0x35 HS Position Control 2 0x00 0x36 HS Position Control 3 0x7D 0x37 Polarity 1 OxE5 NTSV V bit begin 0x41 OxE6 NTSCV bit end 0x84 OxE7 NTSC F bit toggle 0x06 FIELD 1 oa 15251 1 1 21 3 1 4 5 16 7 181 9 10111112 113 19 20 woo d LD DILL ae Uu uU u i VIDEO DE NVBEG 4 0 0x05 NVEND 4 0 0x04 1 656 4 f i 0 04 7 1 F T AA NFTOG 4 0 0x03 FIELD 2 r0 7 1262 i 1263 264 2651 266 267 268 269 270 2711 2721 273
153. e 10 1 14 Rev G to Rev H Changes to Figure dys 1 Changes to Figure 3 and Figure 4 sse 6 Changes to Analog Supply Current Parameter Table 3 8 Changes to Data and Control Outputs Parameter Table 5 10 Added Power Supply Sequencing Section Deleted Power On RESET Section sse Changes to Drive Strength Selection Data Section 24 Changes to Luma Gain Section sse 37 Changes to Comb Filters Section sse 42 Changes to Table 105 sss 80 Deleted Register Select SR7 to SRO 81 Changes to Table 107 itte ertet 84 Changes to Table 108 and Table Summary Statement 100 Deleted PC Programming Examples Section 106 Updated Outline Dimensions Lead to Pad Dimension 112 3 12 Rev F to Rev G Changed ADV7179 to ADV7391 Throughout 1 Changes to Figure 12 5 terrena 18 Changes to Table rerit reet septi e 19 Changes to Power On RESET Section and MUX EN Manual Input Muxing Enable Address 0xC4 7 Section 20 Changed NTSM to NTSC Throughout sss 24 Deleted ADV7190 ADV7191 and ADV7192 Throughout 27 Change to DEF C 7 0 Default Value C Address 0x0D 7 0 Mei P 29 Changes to Luma Filter Section
154. e 284 NTSC be set to 1 for these bits VBI DATA 23 N21 3 0 0 0 010 Sets standard to be decoded from to be effective Line 23 PAL Line 21 NTSC 0x77 VDP LINE 021 VBI DATA P337 N285 3 0 0 0 01 0 Sets VBI standard to decoded from MAN LINE PGM must Line 337 PAL Line 285 NTSC be set to 1 for these bits DATA P24 2213 0 o o o o Sets VBI standard to be decoded from 19 be effective Line 24 PAL Line 22 NTSC 0x78 VDP STATUS CC AVL 0 Closed captioning not detected CC_CLEAR resets the read only 1 Closed captioning detected CC AVL bit CC EVEN FIELD 0 Closed captioning decoded from odd field 1 Closed captioning decoded from even field CGMS WSS AVL 0 CGMS WSS not detected CGMS WSS CLEAR resets 1 CGMS WSS detected the CGMS_WSS_AVL bit Reserved 0 GS PDC VPS UTC AVL 0 GS PDC VPS UTC not detected GS PDC VPS UTC CLEAR 1 GS PDC VPS UTC detected resets the GS PDC VPS UTC AVL bit GS DATA 0 Gemstar 1x detected 1 Gemstar 2x detected AVL 0 VITC not detected VITC CLEAR resets the 1 VITC detected AVL bit AVL 0 Teletext not detected 1 Teletext detected VDP STATUS CLEAR CC CLEAR 0 Does not reinitialize the CCAP readback This is a self clearing bit write only registers 1 Reinitializes the CCAP readback registers Reserved 0 CGMS WSS CLEAR 0 Does not reinitialize the CGMS WSS This is a self clearing bit readback registers 1 Reinitializes the CGMS WSS readback registers Reserved 0 GS PDC VPS UTC
155. e 7 Parameter Symbol Test Conditions Min Unit THERMAL CHARACTERISTICS Junction to Ambient Thermal Osa 4 layer with solid ground plane 32 lead LFCSP 32 5 C W Resistance Still Air Junction to Case Thermal Resistance 4 layer with solid ground plane 32 lead LFCSP 23 C W Junction to Ambient Thermal Oia 4 layer PCB with solid ground plane 40 lead LFCSP 30 C W Resistance Still Air Junction to Case Thermal Resistance 4 layer with solid ground plane 40 lead LFCSP 3 C W Junction to Ambient Thermal 4 layer with solid ground plane 64 lead LOFP 47 C W Resistance Still Air Junction to Case Thermal Resistance 4 layer with solid ground plane 64 lead LOFP 11 1 C W Junction to Ambient Thermal 4 layer with solid ground plane 48 lead LOFP 50 C W Resistance Still Air Junction to Case Thermal Resistance 4 layer with solid ground plane 48 lead LOFP 20 C W Rev J Page 11 of 114 ADV7180 ABSOLUTE MAXIMUM RATINGS Table 8 Parameter Rating to AGND 2 2 V Dvoo to DGND 2 2V Pvoo to AGND 2 2 V to 4V to 0 3 V to 4 V to Dvpp 0 3 V to 0 9V Dvopio to 0 3V to 4 V Dvopio to Dvop 0 3 V to 4V Avop to 0 3V to 40 3 V Avop to Dvop 0 3V to 0 9V Digital Inputs Voltage DGND 0 3 V to Dvppio 0 3 V Digital Outputs
156. e analog circuitry groups Avpp Dvpp and Some graphic controllers use substantially different levels of power when active during active picture time and when idle during horizontal and vertical sync periods This can result in a measurable change in the voltage supplied to the analog supply regulator which can in turn produce changes in the regulated analog supply voltage This can be mitigated by regulating the analog supply or at least Pvpp from a different cleaner power source for example from a 12 V supply Using a single ground plane for the entire board is also recom mended Experience repeatedly shows that the noise performance is the same or better with a single ground plane Using multiple ground planes can be detrimental because each separate ground plane is smaller and long ground loops can result PLL Place the PLL loop filter components as close as possible to the ELPF pin It must also be placed on the same side of the PCB as the ADV7180 Do not place any digital or other high frequency traces near these components Use the values suggested in this data sheet with tolerances of 1096 or less VREFN AND VREFP Place the circuit associated with these pins as close as possible and on the same side of the PCB as the ADV7180 DIGITAL OUTPUTS BOTH DATA AND CLOCKS Try to minimize the trace length that the digital outputs have to drive Longer traces have higher capacitance requiring more
157. e interrupt on the VDP CCAPD signal VDP CGMS WSS CHNGD MSK Address 0x50 2 User Sub Map Setting VDP CGMS WSS CHNGD MSK to 0 default disables the interrupt on the CGMS WSS CHNGD signal Setting VDP CGMS WSS CHNGD MSK to 1 enables the interrupt on the CGMS WSS CHNGD signal VDP 65 VPS PDC UTC CHNG Address 0x50 4 User Sub Map Setting VDP GS VPS PDC CHNG MSK to 0 default disables the interrupt on the VDP GS VPS PDC UTC CHNG signal Setting VDP GS VPS PDC UTC CHNG to 1 enables the interrupt on the VDP GS VPS PDC UTC CHNG Q signal VDP VITC MSK Address 0x50 6 User Sub Map Setting VITC to 0 default disables the interrupt on the VDP_VITC_Q signal Setting VDP_VITC_MSK to 1 enables the interrupt on the VDP_VITC_Q signal Interrupt Status Register Details The following read only bits contain data detection information from the VDP module since the status bit is last cleared or unmasked VDP CCAPD Q Address Ox4E 0 User Sub Map When CCAPD is 0 default CCAP data is not detected When VDP CCAPD is 1 CCAP data is detected VDP CGMS WSS CHNGD OQ Address Ox4E 2 User Sub Map When VDP CGMS 55 CHNGD Q is 0 default CGMS or WSS data is not detected When VDP CGMS 55 CHNGD Q is 1 CGM WSS data is detected VDP GS VPS PDC UTC CHNG Address Ox4E 4 User Sub Map When VDP GS VPS PDC UTC
158. ecommended for user programming Rev J Page 50 of 114 ADV7180 NVEND 4 0 NTSC VSYNC End Address OxE6 4 0 NFTOG 4 0 NTSC Field Toggle Address OxE7 4 0 The default value of NVEND is 00100 indicating the NTSC The default value of NFTOG is 00011 indicating the NTSC VSYNC end position field toggle position For all NTSC PAL VSYNC timing controls both the V bit in For all NTSC PAL field timing controls both the F bit in the the AV code and the VSYNC signal on the VS pin are modified AV code and the field signal on the FIELD pin are modified NFTOGDELO NTSC FIELD Toggle Delay on Odd Field Address OxE7 7 1 0 When NFTOGDELO is 0 default there is no delay Setting NFTOGDELO to 1 delays the field toggle transition on an odd field by a line relative to NFTOG NFTOGDELE NTSC Field Toggle Delay on Even Field NOSROGRAMMING Address OxE7 6 When NFTOGDELE is 0 there is no delay Setting NFTOGDELE to 1 default delays the field toggle transition on an even field by a line relative to NFTOG NFTOGSIGN NTSC Field Toggle Sign Address OxE7 5 Setting NFTOGSIGN to 0 delays the field transition Set for user manual programming ADDITIONAL ADDITIONAL DELAY BY DELAY BY Setting NFTOGSIGN to 1 default advances the field transition KANE LEINE not recommended for user programming 05700 033 FIELD TOGGLE Figure 42 NTSC FIELD Toggle FIELD 1 pon 16221 16231 624 625 4 2 1 3 4 5 6 7 8 19
159. ed channel in enables power down of normal operation MUX2 and associated channel clamp and buffer 1 Power down 2 and associated MUX PDN channel operation Override 1 PWRDWN MUX 1 0 MUX1 and associated channel in enables power down of normal operation and associated channel clamp and buffer 1 Power down MUX1 and associated MUX PDN channel operation Override 1 PWRDWN MUX 0 0 MUXO and associated channel in enables power down of normal operation MUXO and associated channel clamp and buffer 1 Power down MUXO and associated MUX PDN channel operation Override 1 Reserved 9 70 1 Set as default 0x3D Manual Reserved 0 0 1 0 Set to default window CKILLTHR 2 0 0 00 NTSC PAL color kill at 0 596 CKE 1 enables control SECAM no color kil the color kill olola NTSC PAL color kill at lt 1 5 2 s must e enabled for SECAM color kil at lt 5 CKILLTHR 2 0 to 011 0 NTSC PAL color kill at 2 596 take effect SECAM color kill at 796 9 1 1 NTSC PAL color kill at 496 SECAM color kill at 896 1 010 NTSC PAL color kill at 8 596 SECAM color kill at 9 596 1 0 1 NTSC PAL color kill at 1696 SECAM color kill at 1596 1 1 0 NTSC PAL color kill at 3296 SECAM color kill at 3296 1 1 1 Reserved Reserved 1 Set to default 0x41 Resample Reserved Set to default control SFL INV controls the 0 SFL compatible with the ADV717x and behavior of the PAL ADV73xx video encoders switch bit 1 SFL
160. egister 0x77 of the user sub map These 4 bit line programming registers VBI DATA Px Nyand VBI DATA Px identify the VBI data standard that are decoded on Line X in PAL mode or on Line Y in NTSC mode The different types of VBI standards decoded DATA Nyand DATA shown in Table 70 Note that the X or Y value depends on whether the ADV7180 is in PAL or NTSC mode Rev J Page 54 of 114 Table 69 Default Standards on Lines for PAL and NTSC ADV7180 PAL 625 50 NTSC 525 60 Default VBI Default VBI Default VBI Default VBI Line No Data Decoded Line No Data Decoded Line No Data Decoded Line No Data Decoded 6 WST 318 VPS 23 Gemstar 1 286 Gemstar 1 7 WST 319 WST 24 Gemstar 1 287 Gemstar 1x 8 WST 320 WST 25 Gemstar 1 288 Gemstar 1x 9 WST 321 WST 10 NABTS 272 NABTS 10 WST 322 WST 11 NABTS 273 NABTS 11 WST 323 WST 12 NABTS 274 NABTS 12 WST 324 WST 13 NABTS 275 NABTS 13 WST 325 WST 14 VITC 276 NABTS 14 WST 326 WST 15 NABTS 277 VITC 15 WST 327 WST 16 VITC 278 NABTS 16 VPS 328 WST 17 NABTS 279 VITC 17 N A 329 VPS 18 NABTS 280 NABTS 18 N A 332 VITC 19 NABTS 281 NABTS 19 VITC 333 WST 20 CGMS 282 NABTS 20 WST 334 WST 21 CCAP 283 CGMS 21 WST 335 CCAP 22 4 full NABTS 284 CCAP odd field 22 CCAP 336 WST 285 full NABTS even field 23 WSS 337 4 full WST even field 24 4 full WST odd field Table 70 VBI Data Standards for Manual Configuration VBI DATA Px
161. el PE bs perks 0 0 0 OmV offset applied to the Cr channel Osettortae srenanne 111 1 1 1 1 1 1 312 mV offset applied to the Cr channel OxE3 SD Saturation Co SD SAT Cb 7 0 adjusts 0 0 0 0 0 0 0 O Gain on Cb channel 42 dB the saturation by affecting 71 0 0 0 0 0 0 0 Gain on channel 0 dB t SM HAUS T px ap v 1 1 1 1 1 Gain on Cb channel 6 dB Rev J Page 96 of 114 ADV7180 Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 0 4 SD Saturation Cr SD_SAT_Cr 7 0 adjusts 0 0 0 0 0 0 O Gain on Cr channel 42 dB the n by affecting 1 lo o o o o o o Gainon channel 0 dB t 1 1 GainonCbchannel 6 dB 5 NTSC V bit VBEG 4 0 number of 0 0 1 O 1 NTSC default ITU R BT 656 begin ines after count rollover to set V high VBEGSIGN 0 Set to low when manual programming 1 Not suitable for user programming VBEGDELE delay V bit 0 No delay going high by one line 1 Additional delay by one line relative to NVBEG even field VBEGDELO delay V bit 0 No delay going high by one line 1 Additional delay by one line relative to NVBEG odd field OxE6 NTSC V bit end VENDIA 0 number of 0 0 1 0 0 NTSC default
162. el mode Enable square pixel mode ENVSPROC Disable VSYNC processor Enable VSYNC processor Reserved Set to default BETACAM Standard video input Betacam input enable ENHSPLL Disable HSYNC processor Enable HSYNC processor Reserved Set to default Rev J Page84 of 114 ADV7180 Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 0x03 Output control SD DUP AV duplicates 0 AVcodesto suit 8 bit interleaved data the AV codes from the output luma into the chroma path 1 AV codes duplicated for 16 bit interfaces Reserved 0 Set as default OF SEL 3 0 allows the 0 0 0 0 Reserved user to choose from a set 0 0 01 1 Reserved f output fi t 16 bit at LLC 4 2 2 Options apply to 64 lead LQFP only 0 0 1 1 8 bit at LLC 4 2 2 ITU R BT 656 0 1 0 0 Reserved 1 Reserved 0 1 1 10 Reserved 0 1 1 1 Reserved 110 00 Reserved 11010 1 Reserved 110 1 Reserved 1 8 4 1 Reserved 1 110 Reserved 1 110 1 Reserved 1 1 110 Reserved 1 1 1 1 Reserved TOD three state output 0 Output pins enabled See also OE drivers this bit allows the and TRI user to three state the 1 Drivers three stated output drivers pixel outputs HS VS FIELD
163. ements of automotive applications Note that these automotive models may have specifications that differ from the commercial models and designers should review the product Specifications section of this data sheet carefully Only the automotive grade products shown are available for use in automotive applications Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models Note that the ADV7180 is a Pb free environmentally friendly product It is manufactured using the most up to date materials and processes The coating on the leads of each device is 10096 pure Sn electroplate The device is suitable for Pb free applications and can withstand surface mount soldering at up to 255 C 5 C In addition it is backward compatible with conventional SnPb soldering processes This means that the electroplated Sn coating can be soldered with Sn Pb solder pastes at conventional reflow temperatures of 220 C to 235 C PC refers to a communications protocol originally developed by Philips Semiconductors now NXP Semiconductors 2006 2015 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D05700 0 1 15 J Rev J 114 of 114
164. er which requires careful design ofthe printed circuit board PCB layout For example route ground shielding between all signals through tracks that are physically close together It is strongly recommended to connect any unused analog input pins to AGND to act as a shield ADV7180 MAN MUX EN Manual Input Muxing Enable Address 0xC4 7 To configure the ADV7180 analog muxing section the user must select the analog input Am1 to Am6 for the 64 lead LQFP and 48 lead devices or Am1 to Am3 for the 40 lead and 32 lead LFCSP devices that is to be processed by the ADC MAN MUX EN must be set to 1 to enable the following muxing blocks e MUXO0 2 0 ADC Mux Configuration Address 0xC3 2 0 e MUXI 2 0 ADC Mux Configuration Address 0xC3 6 4 e MUX2 2 0 ADC Mux Configuration Address 0xC4 2 0 The three mux sections are controlled by the signal buses MUX0 MUX1 MUX2 2 0 Table 15 explains the control words used The input signal that contains the timing information HS and VS must be processed by MUXO For example a Y C input configuration MUX0 should be connected to the Y channel and MUXI to the C channel When one or more muxes are not used to process video such as the CVBS input the idle mux and associated channel clamps and buffers should be powered down see the description of Register 0x3A in Table 107 Table 15 Manual Mux Settings for the ADC MAN MUX EN Must be Set to 1
165. er power dissipation LFCSP package options make the decoder ideal for space constrained portable applications The 64 lead LQFP package is pin compatible with the ADV7181C 1 The 48 Lead LQFP 40 lead LFCSP and 32 lead LFCSP use one pin to output VS or FIELD One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 2006 2015 Analog Devices Inc All rights reserved Technical Support www analog com ADV7180 TABLE OF CONTENTS eA TEE M 1 G n ral Descriptions iei tiere ree 1 Applications eere tih Ee pede 1 Functional Block Diagram seen 1 Revision History isss rierien 3 Introduction uet DER Ep 5 Analog Front Endi eerie eere 5 Standard Definition Processor see 5 Functional Block Diagrams seen 6 cuo ep TREE ERREUR TR ei 8 Electrical Characteristics eene 8 Video Specifications sy eerte te eei 9 Timing Specifications sse Analog Specifications Thermal Specifications Absolute Maximum Ratings eese 12 ESD Caution eee tet ree RUN 12 Pin Configurations and Function Descriptions 13 32 E ad 13 40 Tead DECS Posset HEREDI ERR EIE tein 14 64 Lead LQED t RR Ende 15 48 Lead LOPP oerte titt edite e nie een 17 Power Supply Sequencing eerte 18 Power
166. ew of the following sections is useful e MUX EN Manual Input Muxing Enable Address 0xC4 7 section for how component video YPrPb can be routed through the ADV7180 e Video Standard Selection section to select the various standards for example with and without pedestal The AGC algorithms adjust the levels based on the setting of the BETACAM bit see Table 42 Table 42 BETACAM Function PW UPD Peak White Update Address 0 2 0 The peak white and average video algorithms determine the gain based on measurements taken from the active video The PW UPD bit determines the rate of gain change LAGC 2 0 must be set to the appropriate mode to enable the peak white or average video mode in the first place For more information see the LAGC 2 0 Luma Automatic Gain Control Address 0x2C 6 4 section Setting PW UPD to 0 updates the gain once per video line Setting PW UPD to 1 default updates the gain once per field Chroma Gain CAGC 1 0 Chroma Automatic Gain Control Address 0x2C 1 0 The two bits of color automatic gain control mode select the basic mode of operation for automatic gain control in the chroma path BETACAM Description 0 default Assuming YPrPb is selected as input format Selecting PAL with pedestal selects MII Selecting NTSC with pedestal selects MII 1 Assuming YPrPb is selected as input format Selecting PAL without pedestal selects SMPTE Selecting NTSC wit
167. figures the way in which data is embedded in the video data stream The recovered data is not available through but is inserted into the horizontal blanking period of an ITU R BT 656 compatible data stream The data format is intended to comply with the recommendation by the International Telecommunications Union ITU R BT 1364 For more information visit the International Telecommunication Union website See Figure 52 GDE SEL OLD Address 0x4C 3 User Sub Map The ADV7180 has a new ancillary data output block that can be used by the VDP data slicer and the VBI System 2 data slicer The new ancillary data formatter is used by setting GDE SEL OLD ADF to 0 default See Table 74 and Table 75 for information about how the data is packaged in the ancillary data stream when this bit is set low To use the old ancillary data formatter to be backward compatible with the ADV7183B set GDE SEL OLD ADF to 1 The ancillary data format in this section refers to the ADV7183B compatible ancillary data formatter Setting SEL OLD ADF to 0 default enables a new ancillary data system for use with the VDP and VBI System 2 Setting GDE SEL OLD ADF to 1 enables the old ancillary data system for use with the VBI System 2 only ADV7183B compatible The format of the data packet depends on the following criteria e Transmission is 1x or 2x e Data is output in 8 bit or 4 bit format see the description of the bit e Data is
168. g high on an odd field by a line relative to NVBEG NVBEGDELE NTSC VSYNC Begin Delay on Even Field Address OxE5 6 When NVBEGDELE is 0 default there is no delay Setting NVBEGDELE to 1 delays VSYNC going high on an even field by a line relative to NVBEG NVBEGSIGN NTSC VSYNC Begin Sign Address 0xE5 5 Setting NVBEGSIGN to 0 delays the start of VSYNC Set for user manual programming Setting NVBEGSIGN to 1 default advances the start of VSYNC not recommended for user programming NVBEG 4 0 NTSC VSYNC Begin Address OxE5 4 0 The default value of NVBEG is 00101 indicating the NTSC VSYNC begin position 05700 031 For all NTSC PAL VSYNC timing controls both the V bit in the AV code and the VSYNC signal on the VS pin are modified 05700 032 VSYNC END Figure 41 NTSC VSYNC End NVENDDELO NTSC VSYNC End Delay on Odd Field Address 0xE6 7 When NVENDDELO is 0 default there is no delay Setting NVENDDELO to 1 delays VSYNC from going low on an odd field by a line relative to NVEND NVENDDELE NTSC VSYNC End Delay on Even Field Address 0 6 6 When NVENDDELE is set to 0 default there is no delay Setting NVENDDELE to 1 delays VSYNC from going low on an even field by a line relative to NVEND NVENDSIGN NTSC VSYNC End Sign Address OxE6 5 Setting NVENDSIGN to 0 default delays the end of VSYNC Set for user manual programming Setting NVENDSIGN to 1 advances the end of VSYNC not r
169. g input channels are powered down to conserve power However the antialiasing filters can be disabled or bypassed using the FILT MAN OVR control 10 BIT 86MHz x o d 05700 012 AVAILABLE IN 64 LEAD AND 48 LEAD PACKAGES Figure 17 Antialias Filter Configuration AA_FILT_MAN_OVR Antialiasing Filter Override Address OxF3 3 This feature allows the user to override the antialiasing filters on off settings which are automatically selected by INSEL 3 0 AA FILT EN Antialiasing Filter Enable Address OxF3 2 0 These bits allow the user to enable or disable the antialiasing filters on each of the three input channels multiplexed to the ADC When disabled the analog signal bypasses the AA filter and is routed directly to the ADC AA FILT EN Address OxF3 0 When AA EN 0 is 0 AA Filter 1 is bypassed When FILT EN 0 is 1 AA Filter 1 is enabled AA FILT EN Address OxF3 1 When AA EN 1 is 0 AA Filter 2 is bypassed When AA EN I is 1 AA Filter 2 is enabled AA FILT EN Address OxF3 2 When AA EN 2 is 0 AA Filter 3 is bypassed When FILT EN 2 is 1 AA Filter 3 is enabled MAGNITUDE dB PHASE Degrees Rev J Page 22of 114 1k 10k 100k 1M 10M 100 05700013 FREQUENCY Hz Figure 18 Antialiasing Filter Magnitude Resp
170. ges to Table 97 nacti dn 72 Changes to Table 99 deti iiini 73 Changes to Table 103 ter eo 80 Changes to Figure 54 2 110 1 06 Revision 0 Initial Version Rev J Page4 of 114 INTRODUCTION The ADV7180 is a versatile one chip multiformat video decoder that automatically detects and converts PAL NTSC and SECAM standards the form of composite S Video and component video into a digital ITU R BT 656 format The simple digital output interface connects gluelessly to a wide range of MPEG encoders codecs mobile video processors and Analog Devices digital video encoders such as the ADV7391 External HS VS and FIELD signals provide timing references for LCD controllers and other video ASICs that do not support the ITU R BT 656 interface standard The different package options available for the ADV7180 are shown in Table 2 ANALOG FRONT END The ADV7180 analog front end comprises a single high speed 10 bit analog to digital converter ADC that digitizes the analog video signal before applying it to the standard definition processor The analog front end employs differential channels to the ADC to ensure high performance in mixed signal applications The front end also includes a 3 channel input mux that enables multiple composite video signals to be applied to the ADV7180 Current clamps are positioned in front of the ADC to ensure that the video signal remains within the range of the converter A re
171. grams the LTA 1 0 and CTA 2 0 registers to have the chroma and luma data match delays for all modes of operation If AUTO PDC EN is set the LTA 1 0 and CTA 2 0 manual registers are not used If the automatic mode is disabled by setting the AUTO PDC EN bit to 0 the values programmed into the LTA 1 0 and CTA 2 0 registers become active When AUTO PDC EN is 0 the ADV7180 uses the LTA 1 0 and CTA 2 0 values for delaying luma and chroma samples See the LTA 1 0 Luma Timing Adjust Address 0x27 1 0 section and the CTA 2 0 Chroma Timing Adjust Address 0x27 5 3 section CTA 2 0 Chroma Timing Adjust Address 0x27 5 3 The chroma timing adjust register allows the user to specify a timing difference between chroma and luma samples This can be used to compensate for external filter group delay differences in the luma vs chroma path and to allow a different number of pipeline delays while processing the video downstream Review this functionality together with the LTA 1 0 register The chroma can be delayed or advanced only in chroma pixel steps One chroma pixel step is equal to two luma pixels The programmable delay occurs after demodulation where delay cannot be made by luma pixel steps For manual programming use the following defaults e CVBS input CTA 2 0 011 Y Cinput CTA 2 0 101 e YPrPb input CTA 2 0 110 Table 63 CTA Function CTA 2 0 Description 000 Not a valid setting 001 Chroma
172. grity of the ancillary data packet It is calculated by summing up D 8 2 of DID SDID the data count byte and all UDWs and ignoring any overflow during the summation Because all data bytes that are used to calculate the checksum have their two LSBs set to 0 the CS 1 0 bits are also always 0 CS 8 describes the logic inversion of CS 8 The value CS 8 is included in the checksum entry of the data packet to ensure that the reserved values of 0x00 and OxFF do not occur Table 88 to Table 91 outline the possible data packages Gemstar 2x Format Half Byte Output Mode Half byte output mode is selected by setting GDECAD to 0 full byte output mode is selected by setting GDECAD to 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Gemstar 1x Format Half byte output mode is selected by setting CDECAD to 0 full byte output mode is selected by setting CDECAD to 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Byte D 9 DI8 D 7 DI6 D 5 D 4 D 2 D 1 DI0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 1 Line 3 0 0 0 SDID 5 EP EP 0 0 0 0 1 0 0 0 Data count 6 0 0 Gemstar Word1 7 4 0 0 User data words 7 EP EP 0 0 Gemstar Word1 3 0 0 0 User data words 8 EP EP
173. he registers the user must program PC GS VPS PDC UTC to 00 as explained in Table 84 Table 84 PC 65 VPS PDC UTCT 1 0 Function PC GS VPS PDC UTC 1 0 Description 00 default Gemstar 1x 2x 01 VPS 10 PDC 11 UTC VDP supports autodetection of the Gemstar standard either Gemstar 1x or Gemstar 2x and decodes accordingly For the autodetection mode to work the user must set the AUTO DETECT GS TYPE bit Register 0x61 user sub map and program the decoder to decode Gemstar 2x on the required lines through line programming The type of Gemstar decoded can be determined by observing the GS DATA TYPE bit Register 0x78 user sub map AUTO DETECT GS TYPE Address 0x61 4 User Sub Map Setting AUTO DETECT GS TYPE to 0 default disables the autodetection of the Gemstar type Setting AUTO DETECT GS TYPE to 1 enables the autodetection of the Gemstar type GS DATA TYPE Address 0x78 5 User Sub Map Read Only Identifies the decoded Gemstar data type When GS DATA TYPE is 0 Gemstar 1x mode is detected Read two data bytes from Register 0x84 When 65 DATA TYPE is 1 Gemstar 2x mode is detected Read four data bytes from Register 0x84 The Gemstar data that is available in the register can be from any line of the input video on which Gemstar was decoded To read the Gemstar data on a particular video line the user should use the manual configuration described in Table 70 and Table 71 and enable Gemst
174. he VSYNC signal is output The 64 lead LQFP has dedicated FIELD and VSYNC pins ADV encoder compatible signals via the NEWAVMODE register follow e PVS PF HVSTIM VSBHO VSBHE VSEHO VSEHE For NTSC control NVBEGDELO NVBEGDELE NVBEGSIGN 4 0 NVENDDELO NVENDDELE NVENDSIGN NVEND 4 0 NFTOGDELO NFTOGDELE NFTOGSIGN NFTOG 4 0 For PAL control PVBEGDELO PVBEGDELE PVBEGSIGN PVBEG 4 0 PVENDDELO PVENDDELE PVENDSIGN PVEND 4 0 PFTOGDELO PFTOGDELE PFTOGSIGN PFTOG 4 0 NEWAVMODE New AV Mode Address 0x31 4 When NEWAVMODE is 0 EAV SAV codes are generated to suit Analog Devices encoders No adjustments are possible Setting NEWAVMODE to 1 default enables the manual position of the VSYNC FIELD and AV codes using Register 0x32 to Register 0x33 and Register OxE5 to Register OXEA Default register settings are CCIR656 compliant see Figure 38 for NTSC and Figure 43 for PAL For recommended manual user settings see Table 65 and Figure 39 for NTSC and Table 66 and Figure 44 for PAL HVSTIM Horizontal VS Timing Address 0x31 3 The HVSTIM bit allows the user to select where the VS signal is asserted within a line of video Some interface circuitry may require VS to go low while HS is low When HVSTIM is 0 default the start of the line is relative to HSE When HVSTIM is 1 the start of the line is relative to HSB VSBHO VS Begin Horizontal Position Odd Address 0x32 7
175. he interrupt based reading of the VDP data registers is as follows for the CCAP standard 1 Theuser unmasks the CCAP interrupt mask bit Register 0x50 Bit 0 user sub map 1 CCAP data occurs on the incoming video VDP slices CCAP data and places it into the VDP readback registers 2 The VDP CCAP available bit CC CAP goes high and the VDP module signals to the interrupt controller to stimulate an interrupt request for CCAP in this case 3 The user reads the interrupt status bits user sub map and sees that new CCAP data is available Register Ox4E Bit 0 user sub map 1 4 The user writes 1 to the CCAP interrupt clear bit Register 0x4F Bit 0 user sub map 1 in the interrupt space this is a self clearing bit This clears the interrupt on the INTRQ pin but does not have an effect in the VDP area 5 The user reads the CCAP data from the VDP area 6 user writes to Bit CC CLEAR in the VDP STATUS CLEAR register Register 0x78 Bit 0 user sub map 1 to signify the CCAP data has been read therefore the VDP CCAP can be updated at the next occurrence of CCAP 7 user goes back to Step 2 Interrupt Mask Register Details The following bits set the interrupt mask on the signal from the VDP VBI data slicer VDP CCAPD MSK Address 0x50 0 User Sub Map Setting VDP CCAPD to 0 default disables the interrupt on the VDP CCAPD Q signal Setting VDP_CCAPD_MSK to 1 enables th
176. he optimum Y filter the decoder does depending on the CVBS 01011 0 0 SVHS3 not change filter video source quality Oo 0 1 0 SVHS4 modes depending good vs poor 0 10 1 1 0 5 55 on video quality 0 0 1 1 1 SVHS6 fixed filter response 0 1 O O O SVHS7 the one selected 0ol1lolo 1 svHs8 is used for good o 1 o 1 0 svHs9 and bad quality 5 510 Mice 0 1 1 0 0 SVHS11 0 1 1 01 1 SVHS 12 0 1 1 1 0 SVHS 13 0 1 1 1 1 SVHS 14 0 SVHS15 1 SVHS 16 1 0 SVHS 17 1 5 518 601 0 0 PALNNI 0 PALNN2 110 1 0 1 1 PALWN1 0 0 PALWN2 1 1 0 NTSCNN1 1 O NTSCNN2 1 11 0 1 1 NTSCNN3 1 11 11 0 0 NTSCWN1 1 1 71 0 1 NTSCWN2 0 NTSC WN3 1 1 1 1 1 Reserved CSFM 2 0 C shaping filter 0 O0 O Autoselection 1 5 MHz Automatically mode allows selection olola Autoselection 2 17 MHz selects a C filter from a range of low pass based on video chrominance filters standard and if either auto mode is quality selected the decoder 0 1 0 SH1 Selects a C filter for selects the optimum C 01111 SH2 all video standards filter depending on the and for good and CVBS video source quality 1 010 SH3 bad video good vs bad nonauto 1 011 SH4 settings force a C filter for 1 1 10 SH5 i 2 quality 1 141 Wideband mode
177. hout pedestal selects SMPTE Selecting PAL with pedestal selects BETACAM Selecting PAL without pedestal selects BETACAM variant Selecting NTSC with pedestal selects BETACAM Selecting NTSC without pedestal selects BETACAM variant Table 43 CAGC Function CAGC 1 0 Description 00 Manual fixed gain use CMG 11 0 01 Luma gain used for chroma 10 default Automatic gain based on color burst 11 Freeze chroma gain Table 44 BETACAM Levels Name BETACAM mV BETACAM Variant mV SMPTE mV MII mV Y 0 to 714 including 7 5 pedestal 0 to 714 700 0 to 700 including 7 5 pedestal Pb and Pr 467 to 467 505 to 505 350 to 350 324 to 4324 Sync Depth 286 286 300 300 Rev J Page 38 of 114 ADV7180 1 0 Chroma Automatic Gain Timing Address 0x2D 7 6 The chroma automatic gain timing register allows the user to influence the tracking speed of the chroma automatic gain control This register has an effect only if the CAGC 1 0 register is set to 10 automatic gain Table 45 CAGT Function CAGT 1 0 Description 00 Slow 2 sec 01 Medium TC 1 sec 10 Reserved 11 default Adaptive CG 11 0 Chroma Gain Address 0x2D 3 0 Address 0x2E 7 0 CMG 11 0 Chroma Manual Gain Address 0x2D 3 0 Address 0x2E 7 0 Chroma gain 11 0 is a dual function register If written to a desired manual chroma gain can be programmed This g
178. ic of the ADV7180 evaluation boards contact a local Analog Devices field applications engineer or an Analog Devices distributor ANALOG INPUT 1 Dypp 1 8V 0 1pF Lit ANALOG_INPUT_2 0 1uF Dvyppio 360 390 0 1pF 0 1yF 0 1pF l 10nF 10nF T Avypp 1 8V 0 1pF F E Que A2 Pypp_1 8V 300 390 Dvppio 3 3V Dypp 1 8V 0 1 Avpp_1 8V 10nF ANALOG_INPUT_3 0 1uF lt 1 8 P 0 7 360 O O O O O O E i 23 8 8 8 1 gt s 2 29 a Aw2 gt OAw2 8 Po OZ PO gt 300 Ain3 5 YCrCb 1 amp BIT 656 DATA RESET gt SLO RESET 9 61 ole re ADV7180BCPZ pees r4 KEEP VREFN AND VREFP CAPACITOR AS CLOSE AS POSSIBLE TO THE ADV7180 AND ON THE SAME SIDE OF THE PCB AS THE ADV7180 26 0 1pF 25 VREFP uc oft lt LOCATE CLOSE AND ON THE INTRA O38 lt SAME SIDE AS THE ADV7180 snm C M SFLO lt sFL 1 1 OXTAL 1 37 4TpF VSIFIELDO 1 39 28 63636MHz 7 5 lt us 1 1 OXTAL1 i l 4TpF 1 MR Dvppio 32 ALSB Pypp 1 8V ALSB TIED HI gt IC ADDRESS 42h 9 ALSB TIED LOW gt ADDRESS 40h qur m Ee eed ee its 1 19 1 10nF 1 POWER DOWN gt QPWRDWN i 1 1 5 gt 34 DSCLK 7 1 1 69kQ 1 spA gt 33 SDATA Figure 57 40 Lead LFCSP Typical Connection Diagram
179. idth split filter Table 57 PSFSEL Function taps luma comb Fixed two line two taps luma comb PSFSEL 1 0 Description 00 Narrow 01 default Medium 10 Wide 11 Widest CCMP 2 0 000 default 100 101 110 111 Description Adaptive comb mode Disable chroma comb Fixed chroma comb top lines of line memory Fixed chroma comb all lines of line memory Fixed chroma comb bottom lines of line memory Configuration Adaptive three line chroma comb for CTAPSN 01 Adaptive four line chroma comb for CTAPSN 10 Adaptive five line chroma comb for CTAPSN 11 Fixed two line chroma comb for CTAPSN 01 Fixed three line chroma comb for CTAPSN 10 Fixed four line chroma comb for CTAPSN 11 Fixed three line chroma comb for CTAPSN 01 Fixed four line chroma comb for CTAPSN 10 Fixed five line chroma comb for CTAPSN 11 Fixed two line chroma comb for CTAPSN 01 Fixed three line chroma comb for CTAPSN 10 Fixed four line chroma comb for CTAPSN 11 CTAPSP 1 0 Chroma Comb Taps PAL Address 0x39 7 6 Table 58 CTAPSP Function YCMP 2 0 Luma Comb Mode PAL Address 0x39 2 0 Table 60 YCMP Function CTAPSP 1 0 Description 00 Do not use 01 PAL chroma comb adapts five lines three taps to three lines two taps cancels cross luma only 10 PAL chroma comb adapts five lines five taps to 11 default three lines three taps cancels cros
180. igured manually to correctly route the video from the analog input pins to the ADC The standard definition processor block which decodes the digital data must be configured to process the CVBS Y C or YPrPb format This is performed by INSEL 3 0 selection CONNECT ANALOG VIDEO SIGNALS TO ADV7180 SET INSEL 3 0 TO CONFIGURE VIDEO FORMAT USE PREDEFINED FORMAT ROUTING YES LQFP 64 LFCSP 40 LQFP 48 Y LFCSP 32 TABLE 13 Figure 16 Signal Routing Options INSEL 3 0 Input Selection Address 0x00 3 0 The INSEL bits allow the user to select the input format They also configure the standard definition processor core to process composite CVBS S Video Y C or component YPrPb format CONFIGURE ADC INPUTS USING MANUAL MUXING CONTROL BITS MUX 0 2 0 MUX_1 2 0 2 2 0 SEE TABLE 15 REFER TO TABLE 14 05700 011 INSEL 3 0 has predefined analog input routing schemes that do not require manual mux programming see Table 13 and Table 14 This allows the user to route the various video signal types to the decoder and select them using INSEL 3 0 only The added benefit is that if for example the CVBS input is selected the remaining channels are powered down Table 13 64 Lead and 48 Lead LQFP INSEL 3 0 INSEL 3 0 Video Format Analog Input 0000 Composite CVBS input 1 0001 Composite CVBS input on Ain2 0010 Composite CVBS input on Ain3 0011 Composite CVBS input on
181. ision high speed mixed signal device To achieve the maximum performance from the part it is important to have a well laid out PCB The following is a guide for designing a board using the ADV7180 ANALOG INTERFACE INPUTS Take care when routing the inputs on the PCB Keep track lengths to a minimum and use 75 Q trace impedances when possible In addition trace impedances other than 75 increase the chance of reflections POWER SUPPLY DECOUPLING It is recommended to decouple each power supply pin with 0 1 uF and 10 nF capacitors The fundamental idea is to have a decoupling capacitor within about 0 5 cm of each power pin In addition avoid placing the capacitor on the opposite side of the PCB from the ADV7180 because doing so interposes inductive vias in the path The decoupling capacitors must be located between the power plane and the power pin Current must flow from the power plane to the capacitor and then to the power pin Do not apply the power connection between the capacitor and the power pin Placing a via underneath the 100 nF capacitor pads down to the power plane is the best approach see Figure 56 VIA TO SUPPLY VIA TO GND 05700 046 Figure 56 Recommended Power Supply Decoupling Itis particularly important to maintain low noise and good stability of Pvpp Careful attention must be paid to regulation filtering and decoupling It is highly desirable to provide separate regulated supplies for each of th
182. ive Line 8 PAL Line 25 NTSC 0x68 VDP_LINE_012 VBI_DATA_P322 3 0 0 0 0 0 Sets VBI standard to be decoded from MAN_LINE_PGM must Line 322 PAL NTSC N A be set to 1 for these bits VBI_DATA_P9 3 0 Sets VBI standard to be decoded from to be effective Line 9 PAL NTSC N A 0x69 VDP_LINE_013 VBI DATA P323 3 0 0 0 0 0 Sets VBI standard to be decoded from MAN_LINE_PGM must Line 323 PAL NTSC N A be set to 1 for these bits VBI DATA P10 3 0 Sets VBI standard to be decoded from 10 be effective Line 10 PAL NTSC N A 0 6 VDP LINE 014 VBI DATA P324 N272 3 0 0 0 0 0 Sets VBI standard to be decoded from MAN LINE PGM must Line 324 PAL Line 272 NTSC be set to 1 for these bits VBI DATA P11 3 0 0 0 0 0 Sets VBI standard to be decoded from to be effective Line 11 PAL NTSC N A 0 6 VDP LINE 015 VBI DATA P325 N273 3 0 Sets VBI standard to be decoded from MAN LINE PGM must Line 325 PAL Line 273 NTSC be set to 1 for these bits VBI DATA P12 1013 0 Sets VBI standard to be decoded from to be effective Line 12 PAL Line 10 NTSC 0 6 VDP LINE 016 VBI DATA P326 N274 3 0 0 0 0 0 Sets VBI standard to be decoded from MAN LINE PGM must Line 326 PAL Line 274 NTSC be set to 1 for these bits DATA 13 N11 3 0 Sets VBI standard to be decoded from to be effective Line 13 PAL Line 11 NTSC 0x6D VDP_LINE_017 VBI_DATA_P327_N275 3 0 0 0 01 0 Sets VBI standard to
183. ive strength for 0711 Medium low drive strength 2x strength 1x the sync output signals 1 0 Medium high drive strength 3x 2 1 1 High drive strength 4x DR STR C and DR STR 1 0 selects 010 Low drive strength 1x DR STRis not the drive strength for 0 1 Medium low drive strength 2x recommended for the clock output signal 3 the optimal Medium high drive strength 3x performance of 1 1 High drive strength 4x the ADV7180 DR STR 1 0 selects the 010 Low drive strength 1x drive 2 for me data 01 1 Medium low drive strength 2x output signals can be lt increased or decreased 1 0 Medium high drive strength 3x EMC or crosstalk reasons 111 High drive strength 4 Reserved x x OxF8 IF comp IFFILTSEL 2 0 IF filter 0 0 0 Bypass mode 0 control selection for PAL and 2MHz 5 MHz NTSC filters NTSC O O 1 3dB 2 dB O 1 O 3 5 dB O 1 1 10dB 5 dB 1 0 0 Reserved 3 MHz 6 MHz PAL filters 1 O 2dB 2 dB 1 1 0 5dB 3 dB 1 1 1 7 5 dB Reserved 0 0 0 0 0 OxF9 VS mode EXTEND VS MAX FREQ 0 Limits maximum VSYNC frequency to control 66 25 Hz 475 lines frame 1 Limits maximum VSYNC frequency to 70 09 Hz 449 lines frame EXTEND VS MIN FREQ 0 Limits minimum VSYNC frequency to 42 75 Hz 731 lines frame 1 Limits minimum VSYNC frequency to 39 51 Hz 791 lines frame VS COAST MODE 1 0 010 Autocoast mode This value sets up 01 50 Hz coast mode ei output coast 1 10 6
184. lable with the ADV7180 The ADV7180 implements a patented ADLLT algorithm to track varying video line lengths from sources such as a VCR ADLLT enables the ADV7180 to track and decode poor quality video sources such as VCRs and noisy sources from tuner outputs VCD players and camcorders The ADV7180 contains a chroma transient improvement CTI processor that sharpens the edge rate of chroma transitions resulting in sharper vertical transitions The video processor can process a variety of VBI data services such as closed captioning wide screen signaling WSS copy generation management system CGMS EDTV Gemstar 1x 2x and extended data service XDS Teletext data slicing for world standard teletext WST along with program delivery control PDC and video programming service VPS are provided Data is transmitted via the 8 bit video output port as ancillary data packets ANC The ADV7180 is fully Macrovision certified detection circuitry enables Type I Type II and Type III protection levels to be identified and reported to the user The decoder is also fully robust to all Macrovision signal inputs 1 Based on 28 6363 MHz crystal between the XTAL and XTAL1 pins See INSEL 3 0 in Table 107 for the mandatory write for Y C S Video mode Table 2 ADV7180 Selection Guide Analog Inputs Part Number Package Type ADV7180KCP32Z 32 lead LFCSP ADV7180WBCP32Z Automotive 32 lead LFCSP ADV7180BCPZ
185. le CRC 0 Turn off CRC check checksum decoded from 1 CGMSD goes high with valid checksum FMS packet to validate CGMSD Reserved 0 0 0 1 1 Set as default Rev J Page 95 of 114 ADV7180 Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes OxC3 ADC Switch 1 MUXO 2 0 manual LQFP LFCSP MAN MUX EN 1 muxing control for MUXO 0 0 Noconnect No connect this setting controls which input is routed to the ADC 9 0 1 Ani Aw for processing 0 1 0 Aw2 No connect 0 1 1 Aw3 No connect 1 0 0 2 1 0 1 5 3 1 1 O No connect 1 1 1 No connect No connect Reserved 0 MUX1 2 0 manual LQFP LFCSP MAN MUX EN 1 muxing control for MUX1 ojojo No connect No connect this setting controls which input is routed to the ADC 0 0 1 No connect No connect for processing connect connect 0 1 1 An3 No connect Ain4 2 110 1 An5 An3 1 11 0 No connect 1 1 1 No connect No connect Reserved 0 OxC4 ADC Switch 2 MUX2 2 0 manual LQFP LFCSP MAN MUX EN 1 muxing control for MUX2 0 0 O Noconnect No connect this setting controls which ololi N N i input is routed to the ADC S COnnec OCONEE for processing 0 1 0 Aw2 No connect 0 1 1 No connect No connect 1 0 0
186. le Package LFCSP_WQ CP 32 12 ADV7180WBCPZ 40 C to 125 C 40 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 40 9 ADV7180WBCPZ REEL 40 C to 125 C 40 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 40 9 ADV7180WBSTZ 40 C to 125 C 64 Lead Low Profile Quad Flat Package LOFP ST 64 2 ADV7180WBSTZ REEL 40 C to 125 C 64 Lead Low Profile Quad Flat Package LQFP ST 64 2 ADV7180WBST48Z 40 C 85 C 48 Lead Low Profile Quad Flat Package LOFP ST 48 ADV7180WBSTA8Z RL 40 C to 85 C 48 Lead Low Profile Quad Flat Package LOFP ST 48 ADV7180KST48Z 10 C to 70 C 48 Lead Low Profile Quad Flat Package LOFP ST 48 ADV7180KSTA8Z RL 10 C to 70 C 48 Lead Low Profile Quad Flat Package LOFP ST 48 ADV7180BST48Z 40 C to 85 C 48 Lead Low Profile Quad Flat Package LOFP ST 48 ADV7180BST48Z RL 40 C to 85 C 48 Lead Low Profile Quad Flat Package LQFP ST 48 ADV7180BCP32Z 409 to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 32 12 ADV7180BCP32Z RL 40 C to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 32 12 EVAL ADV7180LQEBZ Evaluation Board for the 64 Lead LQFP EVAL ADV7180LFEBZ Evaluation Board for the 40 Lead LFCSP EVAL ADV7180 32EBZ Evaluation Board for the 32 Lead LFCSP 17 RoHS Compliant Part 2 W Qualified for Automotive Applications AUTOMOTIVE PRODUCTS The ADV7180W models are available with controlled manufacturing to support the quality and reliability requir
187. line chroma comb for CTAPSN 11 110 Fixed chroma comb all lines of line memory Fixed three line chroma comb for CTAPSN 01 Fixed four line chroma comb for CTAPSN 10 Fixed five line chroma comb for CTAPSN 11 111 Fixed chroma comb bottom lines of line memory Fixed two line chroma comb for CTAPSN 01 Fixed three line chroma comb for CTAPSN 10 Fixed four line chroma comb for CTAPSN 11 Rev J 42 of 114 2 0 Luma Comb Mode NTSC Address 0x38 2 0 Table 56 YCMN Function ADV7180 CCMP 2 0 Chroma Comb Mode PAL Address 0x39 5 3 Table 59 CCMP Function YCMN 2 0 Description Configuration 000 default Adaptive comb mode Adaptive three line three taps luma comb 100 Disable luma comb Use low pass notch filter see the Y Shaping Filter section 101 Fixed luma comb top Fixed two line two lines of line memory taps luma comb 110 Fixed luma comb all Fixed three line three 111 lines of line memory Fixed luma comb bottom lines of line memory PAL Comb Filter Settings These settings are used for PAL B G H I D PAL M PAL Combinational N PAL 60 and NTSC 4 43 CVBS inputs PSFSEL 1 0 Split Filter Selection PAL Address 0x19 1 0 The PSFSEL 1 0 control selects how much of the overall signal bandwidth is fed to the combs A wide split filter selection eliminates dot crawl but shows imperfections on diagonal lines The opposite is true for selecting a narrow bandw
188. ll is clipped at the top or bottom of the ADC range The primary task of the analog clamping circuits is to ensure that the video signal stays within the valid ADC input window so that the analog to digital conversion can take place It is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits within the ADC range ADV7180 After digitization the digital fine clamp block corrects for any remaining variations in dc level Because the dc level of an input video signal refers directly to the brightness of the picture transmitted it is important to perform a fine clamp with high accuracy otherwise brightness variations may occur Further more dynamic changes in the dc level almost certainly lead to visually objectionable artifacts and must therefore be prohibited The damping scheme has to complete two tasks It must acquire a newly connected video signal with a completely unknown dc level and it must maintain the dc level during normal operation To acquire an unknown video signal quickly the large current clamps must be activated It is assumed that the amplitude of the video signal at this point is of a nominal value Control of the coarse and fine current clamp parameters is performed automatically by the decoder Standard definition video signals may have excessive noise on them In particular CVBS signals transmitted by terrestrial broadcast and demodulated using
189. matically detects and converts standard analog baseband television signals compatible with worldwide NTSC PAL and SECAM standards into 4 2 2 component video data compatible with the 8 bit ITU R BT 656 interface standard The simple digital output interface connects gluelessly to a wide range of MPEG encoders codecs mobile video processors and Analog Devices Inc digital video encoders such as the ADV7391 External HS VS and FIELD signals provide timing references for LCD controllers and other video ASICs if required Accurate 10 bit analog to digital conversion provides professional quality Rev J Document Feedback Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result fromits use Specifications subjectto change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners APPLICATIONS Digital camcorders and PDAs Low cost SDTV PIP decoders for digital TVs Multichannel DVRs for video security receivers and video transcoding PCI USB based video capture and TV tuner cards Personal media players and recorders Smartphone multimedia handsets In car automotive infotainment units Rearview camera vehicle safety systems
190. mmed Byte 5 3n Page number Dehammed Byte 6 4 Page number Dehammed Byte 7 5 to 10 Control bytes Dehammed Byte 8 to Byte 13 11 to 42nd Raw data bytes Text Packets X 01 to X 25 15 Magazine number Dehammed Byte 4 2nd Row number Dehammed Byte 5 3 to 4274 Raw data bytes 8 30 Format 1 Packet 1 Magazine number Dehammed Byte 4 Design Code 0000 or 0001 2nd Row number Dehammed Byte 5 UTC 3n Design code Dehammed Byte 6 4 to 10 Dehammed initial teletext page Byte 7 to Byte 12 11 to 23d UTC bytes Dehammed Byte 13 to Byte 25 24th to 42nd Raw status bytes 8 30 Format 2 Packet 1 Magazine number Dehammed Byte 4 Design Code 0010 or 0011 2nd Row number Dehammed Byte 5 PDC 3nd Design code Dehammed Byte 6 4 to 10 Dehammed initial teletext page Byte 7 to Byte 12 11 to 23d PDC bytes Dehammed Byte 13 to Byte 25 24 to 42 Raw status bytes X 26 X 27 X 28 X 29 X 30 X 31 1 Magazine number Dehammed Byte 4 nd Row number Dehammed Byte 5 3n Design code Dehammed Byte 6 4 to 42nd Raw data bytes For X 26 X 28 and X 29 further decoding needs 24 x 18 hamming decoding Not supported at present Rev J Page 63 of 114 ADV7180 CGMS and WSS The CGMS and WSS data packets convey the same type of information for different video standards WSS is for PAL and CGMS is for NTSC therefore the CGMS and WSS readback registers are shared WSS is biphase coded the VDP performs a biphase decoding to produce the 14 ra
191. n is normal When the reset bit is 1 the reset sequence starts GLOBAL PIN CONTROL Three State Output Drivers TOD Address 0x03 6 This bit allows the user to three state the output drivers of the ADV7180 Upon setting the TOD bit the P15 to PO P7 to PO for the 48 lead 40 lead and 32 lead devices HS VS FIELD VS FIELD pin for the 48 lead 40 lead and 32 lead LFCSP and SFL pins are three stated The timing pins HS VS FIELD can be forced active via the TIM OE bit For more information on three state control see the Three State LLC Driver and the Timing Signals Output Enable sections Individual drive strength controls are provided via the DR STR x bits When TOD is 0 default the output drivers are enabled When TOD is 1 the output drivers are three stated Three State LLC Driver TRI LLC Address 0x1D 7 This bit allows the output drivers for the LLC pin ofthe ADV7180 to be three stated For more information on three state control refer to the Three State Output Drivers and the Timing Signals Output Enable sections Individual drive strength controls are provided via the DR STR x bits When TRI LLC is 0 default the LLC pin drivers work according to the DR STR C 1 0 setting pin enabled When LLC is 1 the LLC pin drivers are three stated Rev J Page 23 of 114 ADV7180 Timing Signals Output Enable OE Address 0x04 3 OE bit is regarded as an addition to
192. n the line blanking of the digital output CCIR656 stream This is available for all standards sliced by the VDP module When data is sliced on a given line the corresponding ancillary data packet is placed immediately after the next EAV code that occurs at the output that is data sliced from multiple lines are not buffered up and then emitted in a burst Note that due to the vertical delay through the comb filters the line number on which the packet is placed differs from the line number on which the data was sliced The user can enable or disable the insertion of VDP results that have been decoded into the 656 ancillary streams by using the ADF ENABLE bit ADF ENABLE Enable Ancillary Data Output Through 656 Stream Address 0x62 7 User Sub Map Setting ENABLE to 0 default disables the insertion of VBI decoded data into the ancillary 656 stream Setting ADF ENABLE to 1 enables the insertion of VBI decoded data into the ancillary 656 stream The user may select the data identification word DID and the secondary data identification word SDID through programming the ADF DID 4 0 and ADF SDID 5 0 bits respectively ADF DID 4 0 User Specified Data ID Word in Ancillary Data Address 0x62 4 0 User Sub Map This bit selects the data ID word to be inserted into the ancillary data stream with the data decoded by the VDP The default value of ADF DID 4 0 is 10101 ADF SDID 5 0 User Specified Secondary Data ID Wo
193. ndent on color burst horizontal sync depth amplitude taken from luma path Peak white Dependent on color burst amplitude taken from luma path Y C Dependent on Dependent on color burst horizontal sync depth amplitude taken from luma path Peak white Dependent on color burst amplitude YPrPb Dependent on Taken from luma path horizontal sync depth It is possible to freeze the automatic gain control loops This causes the loops to stop updating and the AGC determined gain at the time of the freeze to stay active until the loop is either unfrozen or the gain mode of operation is changed The currently active gain from any of the modes can be read back Refer to the description of the dual function manual gain registers LG 11 0 luma gain and CG 11 0 chroma gain in the Luma Gain and Chroma Gain sections ANALOG VOLTAGE RANGE SUPPORTED BY ADC 1V RANGE FOR ADV7180 MAXIMUM VOLTAGE MINIMUM CLAMP VOLTAGE LEVEL VIDEO PROCESSOR GAIN SELECTION ONLY DATA PRE PROCESSOR DPP 05700 025 Figure 30 Gain Control Overview Rev J Page 36 of 114 ADV7180 Luma Gain LAGC 2 0 Luma Automatic Gain Control Address 0x2C 6 4 The luma automatic gain control mode bits select the operating mode for the gain control in the luma path Table 39 LAGC Function LAGC 2 0 Description 000 Manual fixed gain use LMG 11 0 001 AGC blank level to sync tip peak white algorithm off 010 def
194. ndicates Interrupt and VDP Map Default State Address Register Bit Description 7165 4132 10 Comments Notes 0x45 Raw Status 2 CCAPD 0 No CCAPD data detected These bits are status read only VBI System 2 bits only they cannot be 1 CCAPD data detected VBI System 2 cleared or masked Register 0x46 is used for Reserved x x x this purpose EVEN_FIELD 0 Current SD field is odd numbered 1 Current SD field is even numbered Reserved x MPU_STIM_INTRQ 0 MPU_STIM_INTRQ 0 1 MPU_STIM_INTRQ 1 0x46 Interrupt Status 2 CCAPD_Q 0 Closed captioning not detected in the These bits can be cleared read only input video signal VBI System 2 or masked by Register 0x47 1 Closed captioning data detected in the and Register 0x48 res video input signal VBI System 2 pectively note that the interrupt in Register 0 46 GEMD Q 0 Gemstar data not detected in the input for the CCAP Gemstar video signal VBl System 2 CGMS and WSS data uses 1 Gemstar data detected in the input the Mode 1 data slicer video signal VBl System 2 Reserved x x SD_FIELD_CHNGD_Q 0 SD signal has not changed field from odd to even or vice versa 1 SD signal has changed Field from odd to even or vice versa Reserved x Not used Reserved x Not used MPU_STIM_INTRQ_Q 0 Manual interrupt not set 1 Manual interrupt set 0x47 Interrupt Clear 2 CCAPD CLR 0 Do not clear VBI System 2 Note that interrupt in write only 1 Clears CCAPD_Q bit VBl System 2 Register 0x46 for the
195. nfig 1 VDP TTXT TYPE MAN 1 0 0 0 PAL Teletext ITU BT 653 625 50 A NTSC reserved 0 1 PAL Teletext ITU BT 653 625 50 B WST NTSC Teletext ITU BT 653 525 60 B 110 PAL Teletext ITU BT 653 625 50 C NTSC Teletext ITU BT 653 525 60 C or EIA516 NABTS 1 1 PAL Teletext ITU BT 653 625 50 D NTSC Teletext ITU BT 653 525 60 D VDP TTXT TYPE MAN ENABLE 0 User programming of teletext type disabled 1 User programming of teletext type enabled WST PKT DECODE DISABLE 0 Enable hamming decoding of WST packets 1 Disable hamming decoding of WST packets Reserved 1 0 0 0 0x61 VDP Config 2 Reserved x x 0 O AUTO DETECT GS TYPE 0 Disable autodetection of Gemstar type 1 Enable autodetection of Gemstar type Reserved 0 62 VDP ADF Config 1 ADF DID 4 0 1 1011 011 User specified DID sent in the ancillary data stream with VDP decoded data ADF MODE 1 0 0 0 Nibble mode 0 1 Byte mode no code restrictions 1 0 Byte mode with 0x00 and OxFF prevented 1 1 Reserved ADF_ENABLE 0 Disable insertion of VBI decoded data into ancillary 656 stream 1 Enable insertion of VBI decoded data into ancillary 656 stream 0x63 VDP_ADF_Config_2 ADF_SDID 5 0 1 011 0 11 0 User specified SDID sent in the ancillary data stream with VDP decoded data Reserved x DUPLICATE ADF 0 Ancillary data packet is spread across the Y and C data streams 1 Ancillary data packet is duplicated on the Y and C data streams Rev J Page 103 of 114 ADV7180 Bit Shading Indicates
196. ntrol port SUB USR EN Address OxOE 5 This bit splits the register map at Register 0x40 USER MAP USER SUB MAP COMMON I C SPACE ADDRESS 0x00 2 Ox3F ADDRESS Ox0E BIT 5 0b ADDRESS 0x0E BIT 5 1b SPACE SPACE ADDRESS 0x40 gt OxFF ADDRESS 0x40 2 0x9C NORMAL REGISTER SPACE INTERRUPT AND VDP REGISTER SPACE Figure 55 Register Access User Map and User Sub Map SPAC 05700 050 ADV7180 2 SEQUENCER An sequencer is used when a parameter exceeds eight bits and is therefore distributed over two or more registers for example HSB 10 0 When such a parameter is changed using two or more I C write operations the parameter may hold an invalid value for the time between the first being completed and the last being completed In other words the top bits of the parameter may hold the new value while the remaining bits of the parameter still hold the previous value To avoid this problem the sequencer holds the updated bits of the parameter in local memory and all bits of the parameter are updated together once the last register write operation has completed The correct operation of the sequencer relies on the following e registers for the parameter in question must be written to in order of ascending addresses For example for HSB 10 0 write to Address 0x34 first followed by Address 0x35 and so on e other can take place between the two
197. ny pull up resistors connected to pins on the ADV7180 such as the SCLK pin and the SDATA pin to 1 8 V rather than 3 3 V 1 If it is not possible to power up the and 1 8 V supplies simultaneously the Dvonio supply must be powered up first When the Dvopo is stable power up the 1 8 V supplies as quickly as possible During power up take care to ensure that the Dvopio supply never drops below any of the 1 8 V supplies RESET PIN RESET PIN POWER UP En 5ms WAIT TIME 05700 100 Figure 12 Power Up Sequence of the 40 Lead LFCSP 48 Lead LQFP and 64 Lead LQFP 3 3V SUPPLIES VOLTAGE 1 8V SUPPLIES 5ms SUPPLIES RESET OPERATION RESET PIN POWER UP RESET PIN TIME 05700 101 Figure 13 Power Up Sequence of the 32 Lead LFCSP Rev J Page 18 of 114 ADV7180 ANALOG FRONT END MUX EN 3 8 05700 010 Figure 15 40 Lead and 32 Lead LFCSP Internal Pin Connections Rev J Page 19 of 114 ADV7180 INPUT CONFIGURATION The following are the two key steps for configuring the ADV7180 to correctly decode the input video 1 INSEL 3 0 to configure the routing and format decoding CVBS Y C or YPrPb For the 64 lead and 48 lead LQFP see Table 13 For the 40 lead and 32 lead LFCSP see Table 14 2 Ifthe input requirements are not met using the INSEL 3 0 options the analog input muxing section must be conf
198. o take its gain value from the luma path The possible AGC modes are shown in Table 38 Table 38 AGC Modes Figure 28 shows the responses of SH1 narrowest to SH5 widest in addition to the wideband mode shown in red GAIN OPERATION The gain control within the ADV7180 is done on a purely digital basis The input ADC supports a 10 bit range mapped into a 1 0 V analog voltage range Gain correction takes place after the digitization in the form ofa digital multiplier Advantages of this architecture over the commonly used programmable gain amplifier PGA before the ADC include the fact that the gain is now completely independent of supply temperature and process variations As shown in Figure 30 the ADV7180 can decode a video signal as long as it fits into the ADC window The components for this are the amplitude of the input signal and the dc level it resides on The dc level is set by the clamping circuitry see the Clamp Operation section If the amplitude of the analog video signal is too high clipping may occur resulting in visual artifacts The analog input range of the ADC together with the clamp level determines the maximum supported amplitude of the video signal Figure 29 shows a typical voltage divider network that is required to keep the input video signal within the allowed range of the Input VideoType Luma Gain Chroma Gain Any Manual gain luma Manual gain chroma CVBS Dependent on Depe
199. odd field line control 1 ITU R BT 470 compliant Line 23 first active comb 1 0 VBlend ine later Line 24 filtered line after VBI ends one line later Line 24 on odd field in PAL 1 1 ends two lines later Line 25 NVBIELCM 1 0 NTSC VBI 010 ends one line earlier Line 282 Controls position of even field line control o 1 ITU R BT 470 compliant Line 283 first active comb FA VBlend Line 284 filtered line after VBI ends one line later Line 284 on even field in NTSC 1 1 VBI ends two lines later Line 285 NVBIOLCM 1 0 NTSC VBI 0 VBI ends one line earlier Line 20 Controls position of odd field line control o 1 ITU R BT 470 compliant Line 21 b t US iltered line after 1 0 VBI ends one line later Line 22 on odd field in NTSC 1 1 ends two lines later Line 23 OxEC Vblank Control 2 PVBIECCM 1 0 PAL VBI 0 O Color output beginning Line 335 Controls the position even field color control 1 ITU R BT 470 compliant color output of first line that beginning Line 336 outputs color after m VBl on even field in 1 O Color output beginning Line 337 PAL 1 1 Color output beginning Line 338 PVBIOCCM 1 0 PAL VBI 0 Color output beginning Line 22 Controls the position odd field color control 1 ITU R BT 470 compliant color output of first line that beginning Line 23 outputs color after odd field in 1 JO Color output beginning Line 24 PAL 1 1 Color output beginning Line 25
200. of video is summed together At the end of a line this accumulated value is compared with a threshold and a decision is made as to whether or not a particular line is black The threshold value needed may depend on the type of input signal some control is provided via LB_TH 4 0 Detection at the Start of a Field The ADV7180 expects a section of at least six consecutive black lines of video at the top of a field After those lines are detected LB_LCT 7 0 reports the number of black lines that were actually found By default the ADV7180 starts looking for those black lines in sync with the beginning of active video for example immediately after the last VBI video line LB_SL 3 0 allows the user to set the start of letterbox detection from the beginning of a frame on a line by line basis The detection window closes in the middle of the field Detection at the End of a Field The ADV7180 expects at least six continuous lines of black video at the bottom of a field before reporting the number of lines actually found via the LB_LCB 7 0 value The activity window for letterbox detection end of field starts in the middle of an active field Its end is programmable via LB_EL 3 0 Detection at the Midrange Some transmissions of wide screen video include subtitles within the lower black box If the ADV7180 finds at least two black lines followed by some more nonblack video for example the subtitle followed by the remainder of the bot
201. on csccssssssesssssssesssescseseseseseseseseseseesees 47 Changes to PFTOG PAL Field Toggle Address OxEA 4 0 Secho c IRR NR RE e NIU E 49 Changes to VDP Manuel Configuration Section 50 Changes to Table 66 sss 51 Changes to Table 71 2 54 Changes to Table 72 d eiie 1 55 Changes to VPS Section and PDC UTC 63 Changes to Gemstar 2x Format Half Byte Output Mode EE 66 Changes to NTSC CCAP Data Section and PAL CCAP Data SOCTION M 69 Changes tO Figure 48 20 ter tt pet pie etes 74 Changes to Sequencer Section sss 75 Changes to Table 102 rette 76 Changes to Table 104 eret toi tiit 80 Changes to Table 105 ee ETE tiran Eia 97 Changes to Figure 53 iste et RS 108 Changes to EIgure54 109 Added Exposed Paddle Notation to Outline Dimensions 110 Changes to Ordering Guide see 111 2 07 to Rev B Changes to SFL_INV Subcarrier Frequency Lock Inversion Section Changes to Table 103 Register Ox41 Updated Outline Dimensions eee 11 06 Rev 0 to Rev A Changes to Table 10 and Table 11 sse 16 Changes to Table 3O 2 debe hene cite io 28 Changes to Gain Operation Section sss 33 Changes to Table 43 eset RR RR EEG 35 Char
202. onse 05700 014 1k 10k 100k 1M 10M FREQUENCY Hz Figure 19 Antialiasing Filter Phase Response ADV7180 GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip POWER SAVING MODES Power Down PDBP Address 0x0F 2 The digital supply of the ADV7180 can be shut down by using the PWRDWN pin or via see the PWRDWN Address OxOF 5 section PDBP controls whether the control or the pin has the higher priority The default is to give the pin PWRDWN priority This allows the user to have the ADV7180 powered down by default at power up without the need for an write When PDBP is 0 default the digital supply power is controlled by the PWRDWN pin the PWRDWN bit Address 0x0F 5 is disregarded When PDBP is 1 the PWRDWN bit has priority the pin is disregarded PWRDWN Address OxOF 5 When PDBP is set to 1 setting the PWRDWN bit switches the ADV7180 to a chip wide power down mode The power down stops the clock from entering the digital section of the chip thereby freezing its operation No bits are lost during power down The PWRDWN bit also affects the analog blocks and switches them into low current modes The interface is unaffected and remains operational in power down mode The ADV7180 leaves the power down
203. ot apply Rev J 64 of 114 ADV7180 CCAP CC EVEN FIELD Address 0x78 1 User Sub Map Two bytes of decoded closed caption data are available in the Read Only PC registers The field information of the decoded CCAP data Identifies the field from which the CCAP data is decoded can be obtained from the CC EVEN FIELD bit Register 0x78 When EVEN FIELD is 0 closed captioning is detected CC CLEAR Closed Caption Clear Address 0x78 0 from an odd field User Sub Map Write Only Self Clearing When CC EVEN FIELD is 1 closed captioning is detected Setting CC CLEAR to 1 reinitializes the CCAP readback from an even field VDP CCAP DATA 0 Address 0x79 7 0 User Sub CC AVL Closed Caption Available Address 0x78 0 Read Only User Sub Map Read Only Decoded Byte 1 of CCAP data VDP CCAP DATA 1 Address 0x7A 7 0 User Sub Map When CC AVL is 1 closed captioning is detected Read Only When AVL is 0 closed captioning is not detected Decoded Byte 2 of CCAP data 10 5 0 25us 12 91us 4 44 5 7 CYCLES OF 0 5035MHz CLOCK RUN IN s o 2 3 isle 7 oj 2 3 4 le 7 P P A 50 IRE A 1 I T T Y Y ag gt 40 IRE REFERENCE COLOR BURST VDP CCAP DATA VDP CCAP DATA 1 9 CYCLES A LEEREN FREQUENCY 3 579545MHz AMPLITUDE 40 IRE 10 003 5 27 3825 33 764us 8
204. oving the chroma component from a composite signal Y C separation must aim for best possible crosstalk reduction while still retaining as much bandwidth especially on the luma component as possible High quality Y C separation can be achieved by using the internal comb filters of the ADV7180 Comb filtering however relies on the frequency relationship of the luma component multiples of the video line rate and the color subcarrier fSC For good quality CVBS signals this relationship is known the comb filter algorithms can be used to separate luma and chroma with high accuracy In the case of nonstandard video signals the frequency relationship may be disturbed and the comb filters may not be able to remove all crosstalk artifacts in the best fashion without the assistance of the shaping filter block Rev J Page 32 of 114 An automatic mode is provided that allows the ADV7180 to evaluate the quality of the incoming video signal and select the filter responses in accordance with the signal quality and video standard YFSM WYSFMOVR and WYSFM allow the user to manually override the automatic decisions in part or in full The luma shaping filter has three control registers e YSFM 4 0 allows the user to manually select a shaping filter mode applied to all video signals or to enable an automatic selection depending on video quality and video standard WYSFMOVR allows the user to manually override the WYSFM decision e W
205. periods 1 1 Active until cleared 0x42 Interrupt Status 1 SD LOCK 0 No change These bits can be cleared read only 1 SD input has caused the decoder togo 97 masked in Register 0x43 from an unlocked state a locked state and Register 0x44 res pectively SD UNLOCK Q 0 No change 1 SD input has caused the decoder to go from a locked state to an unlocked state Reserved x x x SD_FR_CHNG_Q 0 No change 1 Denotes a change in the free run status MV PS CS 0 No change 1 Pseudo sync color striping detected see Register 0x40 INTRQ SEL 1 0 for selection Reserved x 0x43 Interrupt Clear 1 SD_LOCK_CLR 0 Do not clear write only 1 Clears SD_LOCK_Q bit SD_UNLOCK_CLR 0 Do not clear 1 Clears SD_UNLOCK_Q bit Reserved Not used SD FR CHNG CLR 0 Do not clear 1 Clears SD FR CHNG Q bit MV PS CS CLR 0 Do not clear 1 Clears MV PS CS Reserved x Not used 0x44 Interrupt Mask 1 SD LOCK MSK 0 Masks SD LOCK O bit read write 1 Unmasks SD LOCK Qbit SD UNLOCK MSK 0 Masks SD UNLOCK Q bit 1 Unmasks SD UNLOCK OQ bit Reserved Not used SD FR CHNG MSK 0 Masks SD FR CHNG Q bit 1 Unmasks SD_FR_CHNG_Q bit MV PS CS MSK 0 Masks MV PS CS OQ bit 1 Unmasks MV PS CS Reserved x Not used Rev J Page 100 of 114 ADV7180 Bit Shading I
206. phasized Care has also been taken to ensure that edge ringing and undesirable saturation or hue distortion are avoided Chroma transient improvements are needed primarily for signals that have severe chroma bandwidth limitations For those types of signals it is strongly recommended to enable the CTI block via CTI EN CTI EN Chroma Transient Improvement Enable Address 0 4 0 Setting CTI EN to 0 disables the CTI block Setting CTI EN to 1 default enables the CTI block CTI AB EN Chroma Transient Improvement Alpha Blend Enable Address 0x4D 1 The CTI AB EN bit enables an alpha blend function within the CTI block If set to 1 the alpha blender mixes the transient improved chroma with the original signal The sharpness of the alpha blending be configured via the CTI AB 1 0 bits For the alpha blender to be active the CTI block must be enabled via the EN bit Setting AB EN to 0 disables the CTI alpha blender Setting AB EN to 1 default enables the CTI alpha blend mixing function CTI AB 1 0 Chroma Transient Improvement Alpha Blend Address 0x4D 3 2 The AB 1 0 controls the behavior of alpha blend circuitry that mixes the sharpened chroma signal with the original one It thereby controls the visual impact of CTI on the output data For CTI AB 1 0 to become active the CTI block must be enabled via the EN bit and the alpha blender must be switched on via CTI AB EN
207. pin that is pull the pins low Power up the 3 3 V supply and 1 8 V supplies Dv and simultaneously When all supplies are fully asserted pull the PWRDWN pin high Note that this step can be ignored on the 32 lead LFCSP as the PWRDWN pin is not available Wait 5 ms then pull the RESET pin high When all power supplies the PWRDWN pin and the RESET pin are powered up and stable wait an additional 5 ms before initiating PC communication with the ADV7180 1 23V 3 3V SUPPLIES VOLTAGE PWRDWN PIN POWER UP j I 1 1 1 1 l SUPPLIES POWER UP PWRDWN PIN 5ms RESET OPERATION POWER DOWN SEQUENCE The ADV7180 supplies can be deasserted simultaneously as long as Dvpnio does not go below a lower rated supply UNIVERSAL POWER SUPPLY The ADV7180 can operate with a Dvppio supply at a nominal value of 1 8 V Therefore it is possible to power up all the supplies for the ADV7180 Dvpp Avpp and Dvppio to 1 8 V When is at a nominal value of 1 8 V power up the ADV7180 in the following manner 1 Follow the power up sequence described in the Power Up Sequence section but power up the Dvppio supply to 1 8 V instead of 3 3 V In addition power up the PWRDWN pin and the RESET pin to 1 8 V instead of 3 3 V Set the drive strengths of the digital outputs of the ADV7180 to their maximum setting See the Global Pin Control section Connect a
208. ponds to a read operation and Logic 0 corresponds to a write operation Table 104 C Address for ADV7180 ALSB R W Slave Address 0 0 0 40 0 1 0x41 1 0 0x42 1 1 0x43 To control the device on the bus a specific protocol must be followed First the master initiates a data transfer by establishing a start condition which is defined by a high to low transition on SDATA while SCLK remains high This indicates that an address data stream follows All peripherals respond to the start condition and shift the next eight bits the 7 bit address plus the R W bit The bits are transferred from MSB down to LSB The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse this is known as an acknowledge bit All other devices withdraw from the bus at this point and maintain an idle condition The idle condition is where the device monitors the SDATA and SCLK lines for the start condition and the correct transmitted address The R W bit determines the direction of the data Logic 0 on the LSB of SDATA SCLK 1 7 8 9 1 7 8 START ADDR R W ACK SUBADDRESS ACK the first byte means that the master writes information to the peripheral Logic 1 on the LSB of the first byte means that the master reads information from the peripheral The ADV7180 acts as a standard slave device on the bus The data on the SDATA pin is eight bits long supporting the 7 bit address plus the R W
209. puts The sync extraction is optimized to support imperfect video sources such as VCRs with head switches The actual algorithm used employs a coarse detection based on a threshold crossing followed by a more detailed detection using an adaptive interpolation algorithm The raw sync information is sent to a line length measurement and prediction block The output of this is then used to drive the digital resampling section to ensure that the ADV7180 outputs 720 active pixels per line The sync processing on the ADV7180 also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video VSYNC processor This block provides extra filtering of the detected VSYNCS to improve vertical lock HSYNC processor The HSYNC processor is designed to filter incoming HSYNCs that have been corrupted by noise providing much improved performance for video signals with a stable time base but poor SNR VBI DATA RECOVERY The ADV7180 can retrieve the following information from the input video e Wide screen signaling WSS e generation management system CGMS e Closed captioning CCAP e Macrovision protection presence e EDTV data e Gemstar compatible data slicing e Teletext e VITC VPS The ADV7180 is also capable of automatically detecting the incoming video standard with respect to Color subcarrier frequency e Field rate e Line rate
210. r 00001 the chosen filter is applied to all video regardless of its quality e Inautomatic selection mode the notch filters are only used for bad quality video signals For all other video signals wideband filters are used WYSFMOVR Wideband Y Shaping Filter Override Address 0x18 7 Setting the WYSFMOVR bit enables the use of the WYSEM 4 0 settings for good quality video signals For more information on luma shaping filters see the Y Shaping Filter section and the flowchart shown in Figure 23 When WYSFMOVR is 0 the shaping filter for good quality video signals is selected automatically Setting WYSFMOVR to 1 default enables manual override via WYSEM 4 0 NO USE YSFM SELECTED FILTER REGARDLESS OF VIDEO QUALITY 05700 018 Figure 23 YSFM and WYSFM Control Flowchart Rev J Page 33 of 114 ADV7180 Table 35 YSFM Function Table 36 WYSFM Function YSFM 4 0 Description 5 4 01 Description 00000 Automatic selection including a wide notch 00000 Do not use response PAL NTSC SECAM 00001 Do not use 00001 default Automatic selection including a narrow notch 00010 SVHS 1 response PAL NTSC SECAM 00011 SVHS 2 00010 SVHS 1 00100 SVHS 3 00011 SVHS 2 00101 SVHS 4 00100 SVHS 3 00110 SVHS 5 00101 SVHS 4 00111 SVHS 6 00110 SVHS 5 01000 SVHS 7 00111 SVHS 6 01001 SVHS 8 01000 SVHS 7 01010 SVHS 9 01001 SVHS 8 01011 SVHS 10 evr 01100 SV
211. r recommended output circuitry 27 AVDD P Analog Supply Voltage 1 8 V 31 RESET System Reset Input Active low minimum low reset pulse width of 5 ms is required to reset the ADV7180 circuitry 32 ALSB This pin selects the C address for the ADV7180 For ALSB set to Logic 0 the address selected for a write is Address 0x40 for ALSB set to Logic 1 the address selected is Address 0x42 33 SDATA 1 0 Port Serial Data Input Output Pin 34 SCLK Port Serial Clock Input The maximum clock rate is 400 kHz 37 VS FIELD Vertical Synchronization Output Signal Field Synchronization Output Signal 38 INTRQ Interrupt Request Output Interrupt occurs when certain signals are detected on the input video see Table 108 39 HS Horizontal Synchronization Output Signal EPAD EP The exposed pad must be connected to GND Rev J 14 of 114 64 LEAD LQFP INTRO HS DGND DVDDIO P11 P10 P9 P8 SFL DGND DVDDIO GPO1 GPOO P7 P6 P5 NC NO CONNECT ADV7180 lt pa QOcwc gt a zoo ousereS Gerad g4ho F gt gt 4 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 And geen 2 47 3 46 4 45 NC 5 44 NC 6 43 AGND ADV7180 1 42 NC 8 TOP VIEW 41 NC Not to Scale 9 40 AVDD 10 39 VREFN 11 38 VREFP 12 37 AGND 13 36 A2 14 35 Aint 15 34 TEST_0 16
212. ranteed by characterization Avpp 1 71 V to 1 89 V Dvpp 1 65 V to 2 0 V Dvppio 1 62 V to 3 6 V Pvpp 1 65 V to 2 0 V specified at operating temperature range unless otherwise noted Table 4 Parameter Symbol Test Conditions Comments Min Typ Max Unit NONLINEAR SPECIFICATIONS Differential Phase DP CVBS input modulate five step NTSC 0 6 Degrees Differential Gain DG CVBS input modulate five step NTSC 0 5 96 Luma Nonlinearity LNL CVBS input five step NTSC 2 0 96 NOISE SPECIFICATIONS SNR Unweighted Luma ramp 57 1 dB Luma flat field 58 dB Analog Front End Crosstalk 60 dB LOCK TIME SPECIFICATIONS Horizontal Lock Range 5 5 Vertical Lock Range 40 70 Hz fsc Subcarrier Lock Range 1 3 kHz Color Lock In Time 60 Lines Sync Depth Range 20 200 96 Color Burst Range 5 200 96 Vertical Lock Time 2 Fields Autodetection Switch Speed 100 Lines Chroma Luma Gain Delay CVBS 2 9 ns Y C 5 6 ns YPrPb 3 0 ns LUMA SPECIFICATIONS Luma Brightness Accuracy CVBS 1 V input 1 96 Luma Contrast Accuracy CVBS 1 V input 1 96 Rev J Page9 of 114 ADV7180 TIMING SPECIFICATIONS Guaranteed by characterization 1 71 V to 1 89 V 1 65 V to 2 0 V Dvppio 1 62 V to 3 6 V 1 65 V to 2 0 V specified at operating temperature range unless otherwise noted Table 5 Parameter Symbol Test Conditions Min Max Unit SYSTEM CLOCK AND CRYSTAL Nominal Frequency 28 6
213. rd in Ancillary Data Address 0x63 5 0 User Sub Map These bits select the secondary data ID word to be inserted in the ancillary data stream with the data decoded by the VDP The default value of ADF SDID 5 0 is 101010 DUPLICATE ADE Enable Duplication Spreading of Ancillary Data over Y and C Buses Address 0x63 7 User Sub Map This bit determines whether the ancillary data is duplicated over both Y and C buses or if the data packets are spread between the two channels When DUPLICATE ADF to 0 default is set the ancillary data packet is spread across the Y and C data streams When DUPLICATE ADF to 1 is set the ancillary data packet is duplicated on the Y and C data streams ADF 1 0 Determine the Ancillary Data Output Mode Address 0x62 6 5 User Sub Map These bits determine whether the ancillary data output mode is in byte mode or nibble mode Table 73 ADF MODE ADF MODE 1 0 Description 00 default Nibble mode 01 Byte mode no code restrictions 10 Byte mode but 0x00 and OxFF prevented 0x00 replaced by 0x01 OxFF replaced by OxFE 11 Reserved Rev J Page 57 of 114 ADV7180 The ancillary data packet sequence is explained in Table 74 and Table 75 The nibble output mode is the default mode of output from the ancillary stream when ancillary stream output is e enabled This format is in compliance with ITU R BT 1364 The following abbreviations are used in Table 74 and Table
214. rity Active low Active high 0x38 NTSC comb control YCMN 2 0 luma comb mode NTSC Adaptive three line three tap luma Use low pass notch Fixed luma comb two line Top lines of memory Fixed luma comb three line All lines of memory Fixed luma comb two line Bottom lines of memory CCMN 2 0 chroma comb mode NTSC Three line adaptive for CTAPSN 01 Four line adaptive for CTAPSN 10 Five line adaptive for CTAPSN 11 Disable chroma comb Fixed two line for CTAPSN 01 Fixed three line for CTAPSN 10 Fixed four line for CTAPSN 11 Top lines of memory Fixed three line for CTAPSN 01 Fixed four line for CTAPSN 10 Fixed five line for CTAPSN 11 All lines of memory Fixed two line for CTAPSN 01 Fixed three line for CTAPSN 10 Fixed four line for CTAPSN 11 Bottom lines of memory CTAPSN 1 0 chroma comb taps NTSC Not used Adapts three lines to two lines Adapts five lines to three lines ae o Adapts five lines to four lines 0x39 PAL comb control YCMP 2 0 luma comb mode PAL Adaptive five line three tap luma comb Use low pass notch Fixed luma comb three line Top lines of memory Fixed luma comb five line All lines of memory 2 o o o 2 o 2 o o Fixed luma comb three line
215. ry vital information EP and EP The EP bit is set to ensure even parity on the D 8 0 data word Even parity means there is always even number of 1s within the D 8 0 bit arrangement This includes the EP bit EP describes the logic inverse of EP and is output on D 9 The EP is output to ensure that the reserved codes of 00 and FF do not occur EF Even field identifier EF 1 indicates that the data was recovered from a video line on an even field 2x This bit indicates whether the data sliced was in Gemstar 1x or 2x format A high indicates 2x format The 2x bit determines whether the raw information retrieved from the video line was two bytes or four bytes The state of the GDECAD bit affects whether the bytes are transmitted straight that is two bytes transmitted as two bytes or whether they are split into nibbles that is two bytes transmitted as four half bytes Padding bytes are then added where necessary e Line 3 0 This entry provides a code that is unique for each of the possible 16 source lines of video from which Gemstar data may have been retrieved Refer to Table 96 and Table 97 Table 88 Gemstar 2x Data Half Byte Mode e DC 1 0 Data count value The number of UDWs in the packet divided by 4 The number of UDWs in any packet must be an integral number of 4 Padding may be required at the end as set in ITU R BT 1364 See Table 87 e CS 8 2 The checksum is provided to determine the inte
216. s the PAL switch bit in the SFL genlock telegram must be 0 for NTSC to work For the ADV7194 video encoder the PAL switch bit in the SFL must be 1 to work in NTSC If the state of the PAL switch bit is wrong a 180 phase shift occurs In a decoder encoder back to back system in which SFL is used this bit must be set up properly for the specific encoder used SFL_INV Subcarrier Frequency Lock Inversion Address 0x41 6 Setting SFL_INV to 0 default makes the part SFL compatible with the ADV717x and ADV73xx video encoders Setting SFL_INV to 1 makes the part SFL compatible with the ADV7194 video encoder Lock Related Controls Lock information is presented to the user through Bits 1 0 of the Status 1 register see the Status 1 7 0 Address 0x10 7 0 section Figure 21 outlines the signal flow and the controls available to influence the way the lock status information is generated FILTER THE RAW LOCK SIGNAL CIL 2 0 COL 2 0 STATUS 1 0 STATUS 1 1 05700 016 Figure 21 Lock Related Signal Path Rev J Page 28 of 114 ADV7180 SRLS Select Raw Lock Signal Address 0x51 6 Using the SRLS bit the user can choose between two sources for determining the lock status per Bits 1 0 in the Status 1 register See Figure 21 e The TIME WIN signal is based on a line to line evaluation of the horizontal synchronization pulse of the incoming video It reacts quite quickly e The FREE_RUN signal evalu
217. s enabled to switch off the current sources in the analog front VCLEN allows the user to 0 Normal Operation reset the clamp circuitry 1 Reset Clamp Circuitry Reserved 0 0 Set to default Rev J Page 87 of 114 ADV7180 Bits Main Map Shading Indicates Default State Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 0x15 Digital Clamp Reserved x x x x Set to default Control 1 DCFE digital clamp 0 Digital clamp on freeze enable 1 Digital clamp off DCT 1 0 digital clamp 010 Slow 1 sec timing E 0 1 Medium 0 5 sec time constant of the digital fine clamp circuitry 190 Fast TC 0 1 sec 1 1 TC dependent on video Reserved 0 Set to default 0x17 Shaping Filter YSFM 4 0 selects Y 0 0 0 0 0 Autowide notch for poor quality Decoder selects Control 1 shaping filter mode in sources or wideband filter with optimum Y CVBS only mode comb for good quality input shaping filter allows the user to select 0 0 0 0 1 Autonarrow notch for poor quality depending on a wide range of low pass sources or wideband filter with CVBS quality and notch filters if either comb for good quality input mode ele ten 0 1 If one of these the decoder selects 01010 1 SVHS 2 modes is selected t
218. s luma and hue error less well PAL chroma comb adapts five lines five taps to four lines four taps cancels cross luma and hue error well YCMP 2 0 Description Configuration 000 default Adaptivecomb mode Adaptive five lines three taps luma comb 100 Disable luma comb Use low pass notch filter see the Y Shaping Filter section 101 Fixed luma comb top Fixed three lines two lines of line memory taps luma comb 110 Fixed luma comb all Fixed five lines three 111 lines of line memory Fixed luma comb bottom lines of line memory taps luma comb Fixed three lines two taps luma comb Rev J Page 43 of 114 ADV7180 IF FILTER COMPENSATION IFFILTSEL 2 0 IF Filter Select Address OxF8 2 0 The IFFILTSEL 2 0 register allows the user to compensate for SAW filter characteristics on a composite input as would be observed on tuner outputs Figure 34 and Figure 35 show IF filter compensation for NTSC and PAL respectively The options for this feature are as follows e Bypass mode e NTSC consists of three filter characteristics e PAL consists of three filter characteristics See Table 107 for programming details AMPLITUDE dB AMPLITUDE dB Rev J 44 of 114 IF COMP FILTERS NTSC ZOOMED AROUND FSC 2 0 2 5 3 0 3 5 4 0 4 5 5 FREQUENCY MHz Figure 34 NTSC IF Filter Compensation o IF COMP FILTERS PAL ZOOMED AROUND
219. s the luma signal while at the same time attenuating out of band components The luma antialias filter YAA has a fixed response e Luma shaping filters YSH The shaping filter block is a programmable low pass filter with a wide variety of responses It can be used to selectively reduce the luma video signal bandwidth needed prior to scaling for example For some video sources that contain high frequency noise reducing the bandwidth of the luma signal improves visual picture quality A follow on video compression stage may work more efficiently if the video is low pass filtered The ADV7180 has two responses for the shaping filter one that is used for good quality composite component and SVHS type sources and a second for nonstandard CVBS signals The YSH filter responses also include a set of notches for PAL and NTSC However using the comb filters for separation is recommended e Digital resampling filter This block allows dynamic resampling of the video signal to alter parameters such as the time base of a line of video Fundamentally the resampler is a set of low pass filters The actual response is chosen by the system with no requirement for user intervention Figure 24 through Figure 27 show the overall response of all filters together Unless otherwise noted the filters are set into a typical wideband mode Y Shaping Filter For input signals in CVBS format the luma shaping filters play an essential role in rem
220. served Undefined Ox4D CTI DNR EN CTI enable 0 Disable CTI Control 1 Enable CTI EN enables the 0 Disable CTI alpha blender mixing of the transient 1 Enable CTI alpha blender improved chroma with the original signal CTI AB 1 0 controls the 010 Sharpest mixing behavior of the alpha 1 Sharp mixing blend circuitry E 1 0 Smooth mixing 1 1 Smoothest mixing Reserved 0 Set to default DNR_EN enable or bypass 0 Bypass the DNR block the DNR block 1 Enable the DNR block Reserved 12473 Set to default Ox4E CTI DNR C TH 7 0 specifies 1 1 Set to 0x04 for AV input Control 2 how big the amplitude set to OxOA for tuner input step must be to be steep ened by the CTI block 0x50 CTI DNR DNR_TH 7 0 specifies SO e Control 4 the maximum edge that is interpreted as noise and is therefore blanked 0x51 Lock count CIL 2 0 count into lock 0 O 0 Oneline of video determines the number of o o 1 Two lines of video lines the system must 0 1 0 Five lines of video remain in lock before a 5 1 10 lines of video showing a locked status 1 0 0 100lines of video 1 0 1 500lines of video 1 1 O 1000 lines of video 1 1 1 100 000 lines of video COL 2 0 count out of 1 line of video lock determines the olola 2 lines of video of the 0 1 0 5 lines of video Syn must rema our 0 1 1 10 lines of video of lock before showing a lost
221. sistor divider network is required before each analog input channel to ensure that the input signal is kept within the range of the ADC see Figure 29 Fine clamping of the video signal is performed downstream by digital fine clamping within the ADV7180 Table 1 shows the three ADC clocking rates that are determined by the video input format to be processed that is INSEL 3 0 These clock rates ensure 4x oversampling per channel for CVBS mode and 2x oversampling per channel for Y C and YPrPb modes Table 1 ADC Clock Rates Oversampling Input Format ADC Clock Rate MHz Rate per Channel CVBS 57 27 4x Y C S Video 86 2x YPrPb 86 2x ADV7180 STANDARD DEFINITION PROCESSOR The ADV7180 is capable of decoding a large selection of baseband video signals in composite S Video and component formats The video standards supported by the video processor include PAL B D I G H PAL 60 PAL M PAL N PAL Nc NTSC M J NTSC 4 43 and SECAM B D G K L The ADV7180 can auto matically detect the video standard and process it accordingly The ADV7180 has a five line superadaptive 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without requiring user intervention Video user controls such as brightness contrast saturation and hue are also avai
222. tal fine clamp is adjusted dynamically to suit the currently connected input signal Table 34 DCT Function DCT 1 0 Description 00 default Slow TC 1 sec 01 Medium TC 0 5 sec 10 Fast TC 0 1 sec 11 Determined by ADV7180 depending on the input video parameters DCFE Digital Clamp Freeze Enable Address 0x15 4 This register bit allows the user to freeze the digital clamp loop at any time It is intended for users who want to do their own clamping To do this disable the current sources for analog clamping via the appropriate register bits wait until the digital clamp loop settles and then freeze it via the DCFE bit When is 0 default the digital clamp is operational When DCFE is 1 the digital clamp loop is frozen LUMA FILTER Data from the digital fine clamp block is processed by the three sets of filters that follow Note that the data format at this point is CVBS for CVBS input or luma only for and YPrPb input formats Luma antialias filter YAA The ADV7180 receives video at a rate of 28 6363 MHz In the case of 4x oversampled video the ADC samples at 57 27 MHz and the first deci mation is performed inside the DPP filters Therefore the data rate into the ADV7180 is always 28 6363 MHz The ITU R BT 601 recommends a sampling frequency of 13 5 MHz The luma antialias filter decimates the oversampled video using a high quality linear phase low pass filter that preserve
223. te at the start of the line even field VSEHO 0 VS goes low in the middle of the line odd field 1 VS changes state at the start of the line odd field 0x34 HS Position HSE 10 8 HS end allows 0 O O HS output ends HSE 10 0 pixels after Using HSB and Control 1 positioning of the HS the falling edge of HSYNC HSE the user can output within the program the video line position and length Reserved 0 Setto 0 EC TM HSB 10 8 HS begin HS output starts HSB 10 0 pixels allows positioning of after the falling edge of HSYNC the HS output within the video line Reserved 0 Setto 0 0x35 HS Position HSB 7 0 see Address 0x34 0 Control 2 using HSB 10 0 and HSE 10 0 users can program the position and length of the HS output signal 0x36 HS Position HSE 7 0 see Address he T 20 ls 0 Control 3 0x35 description Rev J Page 91 of 114 ADV7180 Main Map Subaddress Register Bit Description Bits Shading Indicates Default State 7 6 5 4 3 2 1 0 Comments Notes 0x37 Polarity PCLK sets polarity of LLC 0 Invert polarity 1 Normal polarity as per the timing diagrams Reserved Set to 0 PF sets the FIELD polarity Active high Active low Reserved Set to 0 PVS sets the VS polarity Active high Active low Reserved Set to 0 PHS sets HS pola
224. tom black block it reports a midcount via LB LCM 7 0 If no subtitles are found LB LCM 7 0 reports the same number as LB LCB 7 0 There is a two field delay in reporting any line count parameter There is letterbox detected bit Read the LB LCT 7 0 and LB LCB 7 0 register values to determine whether the letterbox type video is present in the software LB LCTT 7 0 Letterbox Line Count Top Address 0x9B 7 0 LB LCM 7 0 Letterbox Line Count Mid Address 0x9C 7 0 LB LCB 7 0 Letterbox Line Count Bottom Address 0x9D 7 0 Table 98 LB LCx Access Information Signal Name Address LB LCT 7 0 Ox9B LB LCM 7 0 Ox9C LB_LCB 7 0 0 9 LB TH 4 0 Letterbox Threshold Control Address 0xDC 4 0 Table 99 LB TH Function LB TH 4 0 Description 01100 default Default threshold for detection of black lines 01101 to 10000 Increase threshold need larger active video content before identifying nonblack lines 00000 to 01011 Decrease threshold even small noise levels can cause the detection of nonblack lines LB SL 3 0 Letterbox Start Line Address 0xDD 7 4 The LB SL 3 0 bits are set at 0100 by default For an NTSC signal this window is from Line 23 to Line 286 By changing the bits to 0101 the detection window starts on Line 24 and ends on Line 287 LB EL 3 0 Letterbox End Line Address 0xDD 3 0 TheLB EL 3 0 bits are set at 1101 by default This means that the letterbox dete
225. tput See Figure 60 for recommended output circuitry 21 VREFN Internal Voltage Reference Output See Figure 60 for recommended output circuitry 22 AVDD P Analog Supply Voltage 1 8 V 25 RESET System Reset Input Active low A minimum low reset pulse width of 5 ms is required to reset the ADV7180 circuitry 26 ALSB This pin selects the C address for the ADV7180 For ALSB set to Logic 0 the address selected for a write is Address 0x40 for ALSB set to Logic 1 the address selected is Address 0x42 27 SDATA 1 0 Port Serial Data Input Output Pin 28 SCLK Port Serial Clock Input The maximum clock rate is 400 kHz 31 VS FIELD Vertical Synchronization Output Signal Field Synchronization Output Signal 32 INTRO Interrupt Request Output Interrupt occurs when certain signals are detected on the input video see Table 108 EPAD EP The exposed pad must be connected to GND Rev J Page 13 of 114 ADV7180 40 LEAD LFCSP 38 INTRQ 37 VSIFIELD 36 DVDD 35 DGND SCLK 33 SDATA 32 ALSB 31 RESET 40 39 DVDDIO 1 PIN 1 H SFL 2 INDICATOR H DGND 3 H DVDDIO 4 ADV7180 H P7 5 H P6 6 LFCSP H P5 7 TOP VIEW H PA 3 Not to Scale H P3 9 H P2 10 H NOTES 1 THE EXPOSED PAD MUST BE CONNECTED GND Figure 9 40 Lead LFCSP Pin Configuration Table 10 40 Lead LFCSP Pin Function Descriptions Pin No Mnemonic Type Description 1 4 DVDDIO P Digital I O Supply Voltage
226. two pixels early 010 Chroma one pixel early 011 default No delay 100 Chroma one pixel late 101 Chroma two pixels late 110 Chroma three pixels late 111 Not a valid setting Rev J Page 46 of 114 ADV7180 SYNCHRONIZATION OUTPUT SIGNALS HS Configuration The following controls allow the user to configure the behavior of the HS output pin only e Beginning of HS signal via HSB 10 0 e EndofHS signal via HSE 10 0 e Polarity of HS using PHS The HS begin HSB and HS end HSE registers allow the user to freely position the HS output pin within the video line The values in HSB 10 0 and HSE 10 0 are measured in pixel units from the falling edge of HS Using both values the user can program both the position and length of the HS output signal HSB 10 0 HS Begin Address 0x34 6 4 Address 0x35 7 0 The position of this edge is controlled by placing a binary number into HSB 10 0 The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV Code 00 00 XY see Figure 37 HSB is set to 00000000010b which is two LLC clock cycles from count 0 The default value of HSB 10 0 is 0x02 indicating that the HS pulse starts two pixels after the falling edge of HS Table 64 HS Timing Parameters See Figure 37 HSE 10 0 HS End Address 0x34 2 0 Address 0x36 7 0 The position of this edge is controlled by placing a binary number into HSE 10
227. ue for the color hue adjustment It allows the user to adjust the hue of the picture HUE 7 0 has a range of 90 with 0x00 equivalent to an adjustment of 0 The resolution of HUE 7 0 is 1 bit 0 79 The hue adjustment value is fed into the AM color demodulation block Therefore it applies only to video signals that contain chroma information in the form of an AM modulated carrier CVBS or Y C in PAL or NTSC It does not affect SECAM and does not work on component video inputs YPrPb Table 33 HUE Function HUE 7 0 Description Adjust Hue of the Picture 0x00 default Phase of the chroma signal 0 Ox7F Phase of the chroma signal 90 0x80 Phase of the chroma signal 4 90 DEF Y 5 0 Default Value Y Address 0x0C 7 2 When the ADV7180 loses lock on the incoming video signal or when there is no input signal the DEF Y 5 0 register allows the user to specify a default luma value to be output This value is used under the following conditions Ifthe DEF VAL AUTO EN bit is set to high and the ADV7180 has lost lock to the input video signal This is the intended mode of operation automatic mode e TheDEF VAL EN bit is set regardless of the lock status of the video decoder This is a forced mode that may be useful during configuration The DEF Y 5 0 values define the six MSBs of the output video The remaining LSBs are padded with 0s For example in 8 bit mode the output is Y 7 0 DEF Y 5
228. w WSS bits in the CGMS WSS readback registers and to set the CGMS WSS AVI bit CGMS WSS CLEAR CGMS WSS Clear Address 0x78 2 User Sub Map Write Only Self Clearing Setting CGMS WSS CLEAR to 1 reinitializes the CGMS WSS readback registers 38 4us 42 5us CGMS WSS AVL CGMS WSS Available Address 0x78 2 User Sub Map Read Only When CGMS WSS AVL is 0 CGMS WSS is not detected When CGMS WSS AVL is 1 CGMS WSS is detected VDP CGMS WSS 0 3 0 Address 0 70 3 0 VDP CGMS WSS DATA 1 7 0 Address 0x7E 7 0 VDP CGMS WSS DATA 2 7 0 Address 0x7F 7 0 User Sub Map Read Only These bits hold the decoded CGMS or WSS data Refer to Figure 48 and Figure 49 for the PC to WSS and CGMS bit mapping VDP CGMS WSS VDP CGMS WSS DATA 2 DATA 1 5 0 7 1 RUN IN START SEQUENCE CODE ACTIVE VIDEO 05700 039 Figure 48 WSS Waveform 100 IRE REF VDP CGMS WSS DATA 2 70 IRE 11 20s lt gt VDP_CGMS_WSS_ VDP_CGMS_WSS_DATA_1 DATA_0 3 0 49 15 0 5 5 SEQUENCE E 2 235ys 20ns 5 Figure 49 CGMS Waveform Table 81 CGMS Readback Registers Signal Name Register Location Address User Sub Map CGMS_WSS_DATA_0 3 0 VDP CGMS WSS DATA 0 3 0 125 0x7D CGMS_WSS_DATA_1 7 0 VDP CGMS WSS DATA 1 7 0 126 Ox7E CGMS WSS DATA 2 7 0 VDP CGMS WSS DATA 2 7 0 127 Ox7F These registers are readback registers default value does n

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