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MicroBlaze ™ Hardware Reference Guide

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1. OPB xferAck V V Figure 5 Multiple Bus Requests Fixed Priority Arbitration Combinational Grant Outputs With registered grant outputs there is a cycle between bus grant signals as shown in Figure 6 Using registered grant outputs from the OPB arbiter reduces the number of logic levels between registers and allows the OPB bus to run at a higher clock rate 0 1 2 3 4 5 6 7 1 1 12 1 megest 1 f Mreques Nd OPB_MGrant 1 m OPB MGrant 2 ET TA I TA OPB select 1 select m ON M2 select A OPB xferAck Figure 6 Multiple Bus Requests Fixed Priority Arbitration Registered Grant Outputs 66 www xilinx com March 2002 1 800 255 7778 On Chip Peripheral Bus OPB Arbiter Design Specification OPB Arbiter Design Parameters Table 1 OPB Arbiter Design Parameters XILINX To obtain an OPB Arbiter that is uniquely tailored to your system you can parameterize certain features in the OPB Arbiter design This allows you to have a high performance design that only utilizes the resources req
2. Byte address n n 1 n 2 n 3 Byte label 0 1 2 3 Word Byte significance MSByte LSByte Bit label 0 31 Bit significance MSBit LSBit Byte address n n 1 Byte label 0 1 Half word Byte significance MSByte LSByte Bit label 0 15 Bit significance MSBit LSBit Byte address n Byte label 0 Byte significance MSByte Bit label 0 7 Bit significance MSBit LSBit Figure 2 Big Endian Data Types Registers of the Timebase Watchdog Timer Registers used in assembly language programming are described in this section TWCSRO Control Status Register 0 TWCSR1 Control Status Register 1 TBR Timebase Register Figure 3 TBWDT Register Set www xilinx com 185 March 2002 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Timebase WDT Specification Address Map Table 3 TBWDT Register Address Map Address Register Hex Size Type Description TCSRO 0x00 Word R W Control Status Register 0 TCSR1 0x04 Word Control Status Register 1 state is mirrored in TCSRO for read TBR 0x08 Word R Timebase Register Timebase Register TBR Timebase Register is the output of a free running incrementing counter that clocks at the input clock rate no prescaling of the clock is done for this counter This register is read only and is reset by the following system reset Enabling the WDT after power on reset
3. MSB 32 bit Implementation LSB OPB Address IPR BAR 4 SIE BAR 16 CIE BAR 20 BAR 24 BAR 28 MSB 16 bit Implementation LSB OPB Address ISR BAR 0 IPR BAR 4 SIE BAR 16 CIE BAR 20 IVR BAR 24 MER BAR 28 8 bit Implementation MSB LSB OPB Address ISR BAR 0 IPR BAR 4 IER BAR 8 SIE BAR 16 CIE BAR 20 IVR BAR 24 MER BAR 28 Figure 26 OPB based Register Offsets and Alignment IntC Registers The eight registers visible to the programmer are shown in Table 13 and described in this section In the diagrams and tables that follow w refers to the width of the data bus DB Note If the number of interrupt inputs is less than the data bus width the inputs will start with INTO INTO maps to the LSB of the ISR IPR IER IAR SIE and CIE and additional inputs correspond sequentially to successive bits to the left 98 wwWwW xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Simple Interrupt Controller Specification XILINX Unless stated otherwise any register bits that are not mapped to inputs return zero when read and do nothing when written Table 13 IntC Registers and Base Address Offsets March 2002 www xilinx com MicroBlaze Hardware Reference Guide 1 800 255 7778 Register Name Abbreviation OPB Offset Interrupt Status Register
4. Signal Name Interface Description Clock OPB Rst OPB OPB Reset OPB ABus 0 31 OPB OPB Address Bus OPB 0 3 OPB Byte Enables OPB DBus 0 31 OPB OPB Data Bus OPB RNW OPB OPB Read Not Write OPB select OPB Select seqAddr OPB OPB Sequential Address JTAG UART DBus 0 31 OPB UART Data Bus JTAG UART errAck OPB Error Acknowledge JTAG_UART_retry OPB JTAG_UART Retry JTAG_UART_toutSup OPB O JTAG_UART Timeout Suppress JTAG UART xferAck OPB UART Transfer Acknowledge Interrupt Interrupt UART Interrupt RX External Receive Data TX External Transmit Data Debug SYS Rst Internal Reset signal to OPB V2 0 Debug Rst Internal Reset signal to MicroBlaze Ext BRK Internal 0 Break signal to MicroBlaze Ext NM BRK Internal O Non maskable break signal to MicroBlaze 206 www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide OPB JTAG UART Specification XILINX JTAG UART Address Map and Register Descriptions March 2002 Register Data Types and Organization Registers in the UART are accessed as one of three types byte 8 bits halfword 2 bytes and word 4 bytes All register accesses are on word boundaries to conform to the OPB IPIF register location convention
5. 1 800 255 7778 Page Signal Description in Ref 1 lt gt OPB Clock lt gt Rst OPB Reset Master ABus 0 31 Master address bus OPB 11 Master BE 0 3 Master byte enables OPB 16 Master busLock Master buslock OPB 9 Master DBus 0 31 Master write data bus OPB 13 Master request Master bus request OPB 8 Master RNW Master read not write OPB 12 Master select Master select OPB 12 Master seqAddr Master sequential address OPB 13 lt gt DBus 0 31 OPB read data bus OPB 13 lt nOPB gt _errAck OPB error acknowledge OPB 15 lt gt MGrant OPB bus grant OPB 9 nOPB retry OPB bus cycle retry OPB 10 nOPB timeout OPB timeout error OPB 10 lt gt xferAck OPB transfer acknowledge OPB 14 Table 2 Summary of OPB Slave only I O Page Signal Description in Ref 1 lt gt OPB Clock lt gt Rst OPB Reset Slave DBus 0 31 Slave data bus OPB 11 Slave errAck Slave error acknowledge OPB 15 Slave retry O Slave retry OPB 10 Slave toutSup Slave timeout suppress OPB 15 36 www xilinx com March 2002 MicroBlaze Hardware Reference Guide OPB Usage in Xilinx FPGAs Table 2 Summary of OPB Slave only I O Continued XILINX
6. 190 190 Operation 190 191 E M 191 MPD Pile Parameltets ect tette 192 Device Utilization and Performance 192 Parameterization ecciesie i e I DG RB e RE Ci ERR 193 OPB Timer Counter Specification 195 195 195 Beat re8 edicere De eet 195 Timer Counter Organization oiii inei iioii 195 Programming eile arde dieit discreti 196 Timer oni cde reet e En E E D dandetes UG M RIDE 196 Register Data Types and Organization sees eee ee nnne 196 Registers of the Timer Counter ceci triienimpm entire 198 Address aecenas 198 Isegister DescripliOnis oe emi tip e HEP D URS ccs asia 198 Implementation Pee 203 SUM ALY sehe ERROR Te eese 203 MPD Pile Parameters e REA RUN 203 Device Utilization and Performance Benchmarks eee 204 Par
7. 89 Interrupt Controller Overview tentent tnnt nenne 89 Simple Interrupt Controller Organization 92 Programming Model aicut ne o ro arbi ut laua sun d dee 95 Register Data Types and Organization 95 M 96 Programming th M 106 Pe 107 17 SUMUM ALY M 107 Parameter ZatiOM 107 OPB External Memory Controller EMC 111 SUMMA UP 111 Mm rH 111 EMC OVEIVIeEW rie etus 111 cul 111 Background ttt tette rte te egere 112 Parameters 112 EMC V O ELI c 114 OPB RUM MM 114 EMC Address and Register 85 2 22 2 116 EMC Control Register EMCQCR tree ease nece rre 117 EMC Block 117 Memory Data Types and Organization 117 Memory Controller OpetrdllOn 120 Basic Timing for Memory enne nennen tenentes 120 Connecting to Memory P 123 Example Memory ConnecHOns uu ond anis 124 viii www xilinx com M
8. RATER IR 57 Black Box Description BBD File sse 57 ioana ATE a i rA 58 FOLIA E E E 58 RE 58 Peripheral Analyze Order 59 Somn cT 59 59 i een 59 HDL Design 59 Scalable at eire 59 Internal Signals ierit e 60 Interrupt Signals tti rentre tete ad ee nr e re ENE eaka K ER aeie 60 3 state InOut Sigrials neret eoe reir ia dort us 60 On Chip Peripheral Bus OPB Arbiter Design Specification 61 SUMMAT ee 61 C 61 OPB Arbiter 61 OPB Arbitratior Protocol bna Urso tiae 61 OPB Arbiter Design Paratieters ueendcsmecnt cecinit tete euis onec 64 Allowable Parameter Combinations essen nnns 66 OPB Arbiter 66 Parameter Port 22 22 2 2241222 141 02 8423 00000848 67 OPB Arbiter Register Descriptions beer rte ee
9. Options Table 1 MHS Peripheral Options Option Values Default Definition CONFIGURATION 1 2 3 3 One of six configurations of the 4 5 6 MicroBlaze Bus interface HW_VER 1 00 a X Hardware version INSTANCE X User defined instance name Must be lower case CONFIGURATION Option Use the CONFIGURATION option to set one of the six configurations of the MicroBlaze bus interfaces Refer to the MicroBlaze Bus Interfaces document for more information Use the following to set the configuration CSET attribute CONFIGURATION value You can use short hand notation or descriptive notation for the configuration value For the short hand notation use an integer from 1 to 6 For the descriptive notation use the keywords iopb dopb ilmb and dlmb joined together with underscores The following examples show the same configuration CSET attribute CONFIGURATION 1 4 Short hand notation CSET attribute CONFIGURATION iopb dopb ilmb dlmb descriptive notation HW VER Option Use the HW VER option to set the hardware version as shown in the following example CSET attribute HW VER 1 00 a The version is specified as a literal of the form 1 00 a INSTANCE Option Use the INSTANCE option to set the instance name of peripheral This option is mandatory and the instance name must be specified in lower case CSET attribute INSTANCE my uartO0 MHS Sig nal Signals defined in the MHS file can have the following options Options Table 2 MHS
10. Page Signal Description in Ref 1 Slave xferAck Slave transfer acknowledge OPB 14 lt gt ABus 0 31 address bus OPB 11 lt gt BE OPB byte enable OPB 16 lt gt DBus 0 31 OPB data bus OPB 13 lt nOPB gt _RNW OPB read not write OPB 12 lt gt select select 12 lt nOPB gt _seqAddr OPB sequential address OPB 13 Table 3 Summary of OPB Master Slave Device Page Signal Description in Ref 1 lt gt OPB Clock lt gt Rst OPB Reset Master ABus 0 31 Master address bus OPB 11 Master BE 0 3 Master byte enables OPB 16 Master busLock Master buslock OPB 9 Master DBus 0 31 Master write data bus optional OPB 13 Master request Master bus request OPB 8 Master RNW Master read not write OPB 12 Master select Master select OPB 12 Master seqAddr Master sequential address OPB 13 lt gt DBus 0 31 OPB read data bus OPB 13 lt nOPB gt _errAck OPB error acknowledge OPB 15 lt gt MGrant OPB bus grant OPB 9 nOPB retry OPB bus cycle retry OPB 10 nOPB timeout OPB timeout error OPB 10 lt gt xferAck OPB transfer acknowledge OPB 14 Slave DBus 0 31 Slave data bus may optionally function as OPB 11 master write data bus if Master DBus not present Slave errAck Slave error acknowledge OPB 15
11. 10 pin header 0 1 spacing Figure 0 1 JTAG Connector The following table lists the pins signal names and signal functions for the connector Table 0 1 JTAG Connector Signals Pin Number Signal Name Function 1 REST This signal is normally not used and often the female part has a plug in the Pin 1 hole as the pin on the target board is cut off Alternatively this pin can be used for a JTAG state machine reset if needed 3 GND Digital signal ground 5 OSC Oscillator signal normally not used but can generate a clock up to 100 MHz 7 TRST Target reset This signal is normally an open collector and active low March 2002 www xilinx com 219 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Appendix Appendix B JTAG Connector Table 0 1 JTAG Connector Signals Pin Number Signal Name Function 9 POD POWER 3 3V This pin is used to supply the buffers in the tool with 3 3 or other low voltage By powering the buffers with a target voltage it is possible to interface to many different logic levels The power flows from the target board to the tool to power only buffers that drive the JTAG signals to the target board 2 TMS TMS line that is used to control the JTAG tap state machine 4 TCLK The JTAG clock 6 STOPPED Signal normally not used but the tool can optionally detect that the target system is
12. 138 Clock Handling tite deitatis Pad live 139 Programming 4 1 140 Register Data Types and Organization 140 oai ie Dati 140 Design 140 OPB UART Lite Specification eee 141 Summary UM 141 141 Features TT D MUERE 141 UART Lite Parameters 141 UART Lite VO 9 142 UART Address and Register 142 Register Data Types and Organization sse eee enne 142 Registers of the UART Lite teen beds 143 The Control register contains the UART Lite control 146 Address M 146 Design Implementation e DURER Eo 147 Device Utilization and Performance eee 147 March 2002 www xilinx com MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB JTAG UART Specification 149 rts data 149 odia e M 149 cim Poe orte ia CER
13. March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 101 XILINX OPB Simple Interrupt Controller Specification Interrupt Enable Register IER This is a read write register Writing a 1 to a bit in this register enables the corresponding interrupt input signal Writing a 0 to a bit disables the corresponding interrupt input signal Reading this register indicates which interrupt inputs are enabled where a one indicates the input is enabled and a zero indicates the input is disabled If there are fewer interrupt inputs than the width of the data bus writing a 1 to a non existing interrupt input does nothing and reading it will return zero The IER is shown in the following diagram and the bits are described in Table 16 IER Interrupt Enable Register INTn 2 INTn 4 TDI E Table 16 Interrupt Enable Register Bits Name Description Reset Value 0 INTn INTO Interrupt Input n Interrupt Input 0 0 to ns w 1 1 Interrupt enabled 1 where w is DB width 0 Interrupt disabled 102 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Simple Interrupt Controller Specification Interrupt Acknowledge Register IAR 5 XILINX The IAR is a write only location that clears the interrupt request associated with selected interrupt inputs Writing a one to a bit locat
14. Control Register Logic OPB Requests 3 Arbitration Logic c D 5 Watchdog Timer e E e gt OPB Grant Signals OPB Bus Lock Park Lock Logic March 2002 Figure 7 OPB Arbiter Top level Block Diagram www xilinx com 75 1 800 255 7778 XILINX 76 On Chip Peripheral Bus OPB Arbiter Design Specification When NUM MASTERS 1 the only logic in the OPB Arbiter is the Watchdog Timer The OPB Grant signal is set to VCC and all OPB Bus output signals are set to GND The following sections describe each module in the block diagram OPB Slave Interface IPIF The IPIF block implements a slave interface to the OPB and is only present in the design if C PROC INTRFCE 1 and C NUM MASTERS 1 Its address in the OPB memory map is determined by setting the parameter C BASEADDR All registers are addressed by an offset to C BASEADDR as shown in Table 4 The IPIF block outputs a register write clock enable and a register read clock enable for the register which was addressed depending on the type of data transfer specified by the master When the data transfer is complete the IPIF block generates the transfer acknowledge Control Register Logic The Control Register Logic block simply contains the OPB Arbiter Control Register described in section OPB Arbiter Control Register and is only present in the design
15. Data Receive Register DRR This double buffer receive register contains the data received from the SPI bus The received data is placed in this register after each complete transfer if the register is empty The SPI architecture does not provide a means for a slave to throttle traffic on the bus consequently the DRR is update following each completed transaction only if the DRR was read prior to the last SPI transfer If the DRR was not read i e is full then the most recently transferred data will be lost and a receive over run interrupt will occur The same condition can occur with a master SPI device as well For both master and slave SPI devices with a receive FIFO the data is buffered in the FIFO If a SPI transfers occur with the FIFO full then the most recently transferred data will be lost and a receive over run interrupt will occur The receive FIFO is read only If an attempt to read an empty receive register or FIFO is made then an OPB timeout error will occur because an acknowledgement will not be issued Table 11 shows specifics of the data format Table 11 SPI Data Receive Register Bit Definitions Bit assignment assumes 32 bit bus Reset Bit s Name Access Value Description 24 00 07 Read Only 0x00 SPI Receive Data 31 Slave Select Register SSR This field contains an N length vector that specifies the slave that the local master is to communicate with This vector is a act
16. 203 Table 8 OPB Timer Counter Performance and Resource Utilization Benchmarks Virtex II 2V1000 5 enne nennen nnne 204 xiv www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX Preface Overview of MicroBlaze Embedded Systems An embedded system built around MicroBlaze is comprised of the following MicroBlaze soft processor core On chip block RAM Standard bus interconnects On chip Peripheral Bus OPB peripherals A MicroBlaze system can range from a processor core with a minimum of local memory to a large system with many MicroBlaze processors sizable external memory and numerous OPB peripherals MicroBlaze applications can range from software based simple state machines to complex controllers for Internet appliances or other embedded applications Architecture Support You can use MicroBlaze systems in the following FPGA devices Virtex V Virtex E Virtex II Virtex II PRO Spartan IITM MicroBlaze Soft Processor Core The MicroBlaze soft processor core is central to the MicroBlaze embedded system This fast efficient 32 bit RISC processor includes the following features e Orthogonal instruction set 32 general purpose registers Separate instruction and data buses Harvard architecture e Built in interfaces to fast on chip memory and to IBM s industry standard On chip Peripheral Bus OPB Implementations in and later devices
17. P20 OPB Rst OPB Arbiter The OPB Arbiter contains addressable registers for read write operations as shown in Table 4 Register if the design has been parameterized to support a processor interface The base address for e these registers is set in the parameter C BASEADDR The registers are located at an offset of Descriptions 0x00000100 from BASEADDR Each register is addressable on 32 bit boundary Each priority level has a unique Priority Register which contains the master id for the master at that priority level The Priority Registers are readable and writable by the processor The number of priority levels and hence the number of Priority Registers will vary with the parameter C NUM MASTERS 70 www xilinx com March 2002 1 800 255 7778 On Chip Peripheral Bus OPB Arbiter Design Specification XILINX Table 4 shows all of the OPB Arbiter registers and their addresses when the maximum number of masters has been selected In this case 17 registers are required Table 4 OPB Arbiter Registers Register Name OPB Address Access Control Register BASEADDR 0x100 Read Write LVLO Priority Register BASEADDR 0x104 Read Write LVL1 Priority Register BASEADDR 0x108 Read Write LVL2 Priority Register BASEADDR 0x10C Read Write LVL3 Priority Register BASEADDR 0 110 Read Write LVL4 Priority Register BASEADDR 0x114 Read Write LVL5 Priority Reg
18. in std logic clkb in std logic dinb in std logic vector 7 downto 0 douta out std logic vector 7 downto 0 doutb out std logic vector 7 downto 0 web in std logic end component mem dp 0 Swap BRAM Little endian Data to Big endian Swap and LE order process begin for I in addra range loop addra I lt Instr Addr 29 1 end loop for I in addrb range loop addrb I lt Data Addr 29 1 214 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide VHDL Example XILINX end loop for I in 0 to 3 loop for J in 0 to 7 loop dinb I 8 J lt Data Write 3 I 8 7 J Instr 3 I1 8 7 J lt douta 1 8 Data_Read 3 I 8 7 J lt doutb I 8 J end loop end loop end process Swap_BE_and_LE_order BRAM Instantiation mem_dp_O_I mem dp O port map addra gt addra IN std_logic_VECTOR 9 downto 0 addrb gt addrb IN std_logic_VECTOR 9 downto 0 clka gt Clk IN std logic gt IN std logic dinb gt dinb 31 downto 24 IN std_logic_VECTOR 7 downto 0 douta douta 31 downto 24 OUT std_logic_VECTOR 7 downto 0 doutb gt doutb 31 downto 24 OUT std_logic_VECTOR 7 downto 0 web gt we 0 IN std logic BRAM OPB Example OPB uses big endian byte addressing while the BRAM uses little endian byte addressing To translate dat
19. 44 HW 44 INSTANCE OPON E M 44 MHS T 44 PRIORITY Option niter terre erre nma Pene 44 TYPE OPON M 45 Design Considerations aient itae bf t bdo Gc a ORA R 45 Defining Memory S16 cicer tirer natat inen I recu Ee enun 45 Defining Local Memory 45 Internal Signals actin aeneis pete b eec irr be erint rege 45 Interrupt Signals oderam eire eit ich er d ici sn 45 o cUPr 46 Microprocessor Peripheral Definition Format 47 SUMMATY SEEN D 47 atA E 47 Load 47 Using 48 49 49 49 M 50 MPD Attribute Naming Conventions 50 FAMILY Attribute ete e teer rie 51 C BASBADDR etre ten ene eee le xta ie 51 C Attribute err retener tette 51 vi www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX C NUM
20. MISO MSB PX lt lt i gt 55 Not defined but normally LSB of previously transmitted character Figure 4 Data Transfer SPI Bus with 1 24 0 for 8 bit character All SPI transfers are full duplex where 8 bit data character is transferred from the master to the slave and an independent 8 bit data character is transferred from the slave to the master This can be viewed as an 8 bit shift register in the SPI Master device and another 8 bit shift register in a SPI slave device that are connected as a circular 16 bit shift register The SPI specification details the timing and waveforms for byte transfers where the msb is shifted out first on the SPI bus but does not dictate the data content or sequence of data in the sense of address information or other information type All data written to the transmit register will be transmitted on the SPI bus and all data received on the SPI bus will be stored in a receive register for the user logic to interpret Transfer Beginning Period The definition of the transfer beginning period is taken directly from the M68HC11 Reference Manual this manual can be referenced for more details that are not reproduced herein All SPI transfers are started and controlled by a master SPI device As a slave the processor considers a transfer to begin with the first SCK edge CPHA 1 or the falling edge of SS N
21. T T INTn 1 INTn 3 INTn 5 INT1 INTO Table 18 Set Interrupt Enables Bits Name Description Reset Value 0 INTn INTO Interrupt Input n Interrupt Input 0 n a to n lt w 1 1 Set IER bit w 1 where wis DB width 0 0 action 104 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Simple Interrupt Controller Specification Clear Interrupt Enables CIE CIE is a location used to clear IER bits in a single atomic operation rather than using a read modify write sequence Writing a one to a bit location in CIE will clear the corresponding bit in the IER Writing zeros does nothing as does writing a one to a bit location that corresponds to a non existing interrupt input The CIE is also optional in the simple IntC and can be parameterized out of the implementation The CIE is shown in the following diagram and the bits are described in Table 19 CIE Clear Interrupt Enables INTn 2 INTn 4 TRI E T T XILINX T T INTn 1 INTn 3 INTn 5 INT1 INTO Table 19 Clear Interrupt Enables Bits Name Description Reset Value 0 INTn INTO Interrupt Input n Interrupt Input 0 n a to ns w 1 1 Clear IER bit w 1 where wis DB width 0 10 action March 2002 www xilinx com 105 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Simple Interrupt Controller Specification Interrupt Vector Register
22. 168 www xilinx com 1 800 255 7778 v1 00b MicroBlaze Hardware Reference Guide OPB Serial Peripheral Interface SPI Design Specification XILINX Table 8 SPI Control Register Bit Definitions Bit assignment assumes 32 bit bus Bit s Name Core Access Reset Value Description 27 CPHA Read Write 0 Clock Phase select bit Setting this bit selects one of two fundamentally different transfer formats See timing diagrams and discussion of diagrams 26 Tx FIFO Reset Read Write Transmit FIFO Reset This bit forces a reset of the FIFO pointer and asserts FIFO empty flag FIFO contents are unchanged This bit is reset automatically reset to 0 one OPB clock period after set to 1 This bit is unassigned when the SPI assembly in not configured with FIFOs 0 Transmit FIFO normal operation T Reset transmit FIFO pointer 25 Rx FIFO Reset Read Write Receive FIFO Reset This bit forces a reset of the FIFO pointer and asserts FIFO empty flag FIFO contents are unchanged This bit is reset automatically reset to 0 one OPB clock period after set to 1 This bit is unassigned when the SPI assembly in not configured with FIFOs 0 Transmit FIFO normal operation e 1 Reset receive FIFO pointer 24 Manual SS Assertion Enable Read Write Manual SS Assertion Enable This 70 55 assertion by Master state 1 SS follows data in Slave S
23. Parameter Values Device Resources fmax MHz C NUM MASTERS C DYNAM PRIORITY PARK PROC INTRFCE C REG GRANTS DWIDTH Slices Slice 4 input MAX c Flip Flops 10 1 N A N A N A N A N A 4 4 6 290 2 0 0 0 0 32 32 11 7 18 223 2 1 1 1 1 32 32 76 76 87 163 4 0 0 0 0 32 32 27 13 39 153 4 1 0 0 0 32 32 42 21 69 167 4 0 1 0 0 32 32 42 17 59 150 4 0 0 1 0 32 32 75 63 95 136 4 0 0 0 1 32 32 30 18 40 173 4 1 1 1 1 32 32 130 97 163 126 8 0 0 0 0 32 32 93 81 132 122 March 2002 www xilinx com 87 1 800 255 7778 XILINX On Chip Peripheral Bus OPB Arbiter Design Specification Table 9 OPB Arbiter FPGA Performance and Resource Utilization Benchmarks Virtex II 5 Continued 1 8 1 1 1 1 32 32 278 145 398 100 16 0 0 0 0 32 32 441 84 654 100 16 1 1 1 1 32 32 904 252 1477 82 Notes These benchmark designs contain only the OPB Arbiter with registered inputs outputs without any additional logic Benchmark numbers approach the performance ceiling rather than representing performance under typical user conditions 2 Different OPB data widths and OPB address widths are verified as part of the IPIF verification 3 Device resource numbers do not include the registers for the OPB Arbiter I O 4 Max frequency calculated with registers on the OPB Arbiter I O Specification Register Definitions and Addressing Exceptions To support parameterization of the nu
24. C structure mapping rules permit the use of padding skipped bytes to align scalars on desirable boundaries The structure mapping examples show each scalar aligned at its natural boundary This alignment introduces padding of four bytes between a and b one byte between d and e and two bytes between e and f The same amount of padding is present in both big endian and little endian mappings Note For the MicroBlaze core all operands in the ALU and GPRs and all pipeline instructions are big endian The big endian mapping of struct is shown in the following table The data is highlighted in the structure mappings Hexadecimal addresses are below the data stored at the address The contents of each byte as defined in the structure are shown as a number hexadecimal or character for the string elements Table 0 4 Big endian Mapping 11 12 13 14 0x00 0 01 0x02 0 03 0x04 0x05 0 06 0 07 21 22 23 24 25 26 27 28 0x08 0 099 0 0 0 0 0 0 0 OxOE OxOF 31 32 33 34 0x10 0 1 0x12 0x13 0 14 0x15 0x16 0x17 51 52 0x18 0 19 0 1 0 Ox1C 0x1D 0 0 61 62 63 64 0x20 0 21 0x22 0x23 0 24 0 25 0 26 0 27 Table 0 5 Little endian Mapping 14 13 12 11 0x00 0 01 0x02 0 03 0x04 0 05 0 06 0 07 28 27 26 25 24 23 22 21 0x08 0 099 0 0 0 0 0 0 0 OxOE OxOF
25. 170 SPI Gontrol Register CR iere ertt heit 170 Register SR sete decet rettet neret te terti dete 172 Data Transmit Register DER itd etae ettet rette ede to 173 Data Receive Register DRR tte 174 Slave Select Register SOR eicit petet n eire 174 Transmit FIFO Occupancy Register Tx FIFO 174 Receive FIFO Occupancy Register FIFO OCY sss 175 Design ImplementaliQfi pde 175 Target Lechrnology doa ppt neci i eo RO dee duret 175 Device Utilization and Performance Benchmarks sese 175 Flow 176 SPI Master and Slave Devices without FIFOS seen 176 SPI Master and Slave Devices where Registers FIFOs are Filled Before SPItranster 18 Started tette rae ERE E eg Indes 176 SPI Master and Slave Devices with FIFOs where some Initial Data is Written to FIFOs SPI transfer is started Data is written to the FIFOs as Fast or faster than the SPI 177 Platform Generator Considerations 7 sse 177 Specification Exceptions dr tiger tn 1 7 Exceptions to the Motorola s M68HC11 Rev 4 0 Reference Manual 177 Reference 178 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide
26. Programming Model 178 OPB General Purpose Input Output GPIO Specification Register Data Types and Organization Registers in the GPIO are accessed as one of the following types Byte 8 bits Half word 2 bytes Word 4 bytes Configuration The following table shows GPIO configurations and access type Table 1 GPIO Configuration and Access Type Configuration Access Type 32 bit slave OPB peripheral Word 16 bit peripheral Half word 8 bit peripheral Byte 32 bit 16 bit or 8 bit peripheral All register accesses are on word boundaries to conform to the OPB IPIF register location convention The addresses of the GPIO registers when configured as a 32 bit OPB slave are shown in the following table Table 2 GPIO Register Address Map 32 bit OPB Address Register Hex Size Type Description GPIO DATA 0x00 Word R W GPIO Data Register GPIO_TRI 0x04 Word R W GPIO Three state Register www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB General Purpose Input Output GPIO Specification XILINX The GPIO registers are organized as big endian data The bit and byte labeling for the big endian data types is shown in the following figure Byte address Byte label Byte significance Bit label Bit significance Byte address Byte label Byte significance Bit label Bit significance Byte address Byte label Byte signific
27. SH rdDBus 0 31 DOPB busLock SH_errAck usLoc DOPB_wrDBus 0 31 SI1 retry DOPB ABus 0 31 Required if more than DOPB RNW Slavet S timeout d DOPB BE 0 3 one master present DOPB select toutSup gt DOPB busLock DOPB gt Sl1_xferAck gt DOPB wrDBus 0 31 Bond DOPB rdDBus 0 31 side DOPB_RNW OPB DOPB_select arbiter DOPB rdDBus 0 31 DM ABus 0 31 gt DOPB_segAddr DOPB errAck gt DM_BE 0 3 gt DOPB errAck DOPB retry Ern DM busLock gt DOPB retry DOPB timeout gt MicroBlaze DM wrDBus 0 31 OR DOPB timeout DOPB xferAck Data OPB DM RNW like DOPB toutSup Interface DM select gt suttixes DOPB_xferAck DM_segAddr DOPB DOPB MGrant Y 0988 DM request Present for Bus Monitor functions IOPB rdDBus 0 31 1 rdDBus 0 31 IOPB errAck gt 1 errAck DOPB wrDBus 0 31 DOPB DBus 0 31 IOPB retr 4 Bri retry gt DOPB rdDBus 0 31 gt OR g y
28. in std ulogic 216 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide VHDL Example XILINX gt in std ulogic Fir y in std ulogic OPB gt in std ulogic BRAM Clk in std ulogic ABus LE 12 downto 2 in std logic vector 10 downto 0 bram Addr LE 12 downto 2 in std logic vector 10 downto 0 BRAM LE I I 1 8 1 downto I 8 out std logic vector 7 downto 0 gt Read Data LE I 1 8 1 downto I 8 out std logic vector 7 downto 0 SSRA gt SSRB gt CLKA gt gt ADDRA gt ADDRB gt DOA 0pb DOPA gt DOPB gt open out std logic vector 0 downto 0 open out std logic vector 0 downto 0 end generate By 8 March 2002 www xilinx com 217 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Appendix Appendix A MicroBlaze Endianness 218 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX Appendix Connector This appendix provides information on the standard 10 pin JTAG connector that can be used in a MicroBlaze system The following figure shows the JTAG connector pins and signal names Target Board Component Side KEY JTAG RESET 1 mE 2 TMS GND 4 5 4 TCLK OSC p 6 STOPPED TRST 7 M POD PWR 3 3v TSO DTOPC 9 10
29. 34 33 32 31 0x10 0 1 0x12 0 13 0 14 0x15 00x16 0 17 52 51 0x18 0 19 0 1 0 0 0 10 0 Ox1F 64 63 62 61 0x20 0 21 0x22 0 23 0 24 0 25 026 0 27 2002 www xilinx com 213 MicroBlaze Hardware Reference Guide 1 800 255 7778 7 XILINX Appendix Appendix A MicroBlaze Endianness VHDL Example BRAM LMB Example LMB uses big endian byte addressing while the BRAM uses little endian byte addressing To translate data between the two busses swap the data and address bytes Interface Between BRAM and MicroBlaze entity Local Memory is port Clk in std_logic Reset in boolean Instruction Bus Instr Addr in std logic vector 0 to 31 Instr out std logic vector 0 to 31 IFetch in std logic I AS in std logic IReady out std logic ports to Decode I Data Addr in std logic vector 0 to 31 Data Read out std logic vector 0 to 31 Data Write in std logic vector 0 to 31 D AS in std logic Read Strobe in std_logic Write Strobe in std logic DReady out std logic Byte Enable in std logic vector 0 to 3 end Local Memory architecture IMP of Local Memory is BRAM Component Declaration little endian component mem dp 0 is port addra in std logic vector 9 downto 0 addrb in std logic vector 9 downto 0
30. Enabling the WDT after the WDT has been disabled EWDT1 and EWDT2 must both be 0 to disable the WDT The WDT is enabled when either EWDT1 or EWDT2 are set to 1 Note that when the WDT mode is enable once the TBR can only be reset when the WDT is first enabled 1 TBR Control Status Register 0 TCSRO Control Status Register 0 contains the watchdog timer reset status watchdog timer state and watchdog timer enables WRS i T T T TBR 0 27 WDS EWDT2 Table 4 Control Status Register 0 TCSRO Bits Name Description Reset Value 0 27 TBR 0 27 Timebase Register Most significant 28 bits This read only field contains the most significant 28 bits of the timebase register The timebase register is mirrored here so that a single read can be used to obtain the count value and the watchdog timer state if the upper 28 bits of the timebase provide sufficient timing resolution 186 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Timebase WDT Specification Table 4 Control Status Register 0 TCSRO Continued XILINX Bits 28 Name WRS Description Watchdog Reset Status Indicates the WDT reset signal was asserted This bit is not cleared by a system reset so that it can be read after a system reset to determine if the reset was caused by a watchdog timeout Writing a 1 to this bit clears the watchdog reset status bit Writing a 0 to this bit
31. IOPB timeout Bri timeout IOPB toutSu gt 1 toutSup gt IOPB xferAc gt Present for Bus Monitor functions POPE IOPB wrDBus 0 31 _ IOPB DBus 0 31 to IOPB_rdDBus 0 31 OR DOPB ABus 0 31 IOPB Bri ABus 0 31 DOPB BE 0 3 Bridge Bri BE 0 3 DOPB busLock gt Bri_busLock gt DOPB wrDBus 0 31 BriD_wrDBus 0 31 ABus 0 31 DOPB RNW gt RNW gt IOPB_BE 0 3 DOPB_select 4 Bri select gt IOPB busLock DOPB segAddr gt Bri segAddr gt IOPB wrDBus 0 31 Bri MGrant gt Bri_request IOPB rdDBus 0 31 IOPB RNW IOPB select IOPB rdDBus 0 31 a IM ABus 0 31 a IOPB segAddr IOPB errAck gt IM BE 0 3 gt IOPB errAck IOPB retry rn IM busLock gt IOPB retry IOPB timeout gt MicroBlaze wrDBus O 331 7 OR IOPB timeout IOPB xferAck Instr OPB RNW like IOPB toutSup Interface IM select gt ifix IOPB xferAck IOPB IM segAddr Required IOPB MGrant Pa IM_request l side IOPB ABus 0 31 OPB IOPB BE 0 3 SI2 rdDBus 0 31 arbiter RNW gt Slave Si2 timeout 4 IOPB select SI2 toutSup a IOPB 512 xferAck gt Instruction side OPB Figure 10 OPB Interconnection breaking up read and write buses 24 www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide MicroBlaze Bus Interfaces 5 XILINX Data side OPB
32. Status Reg Control Reg TWCSRO TWCSR1 OPB Bus 32b Timebase Clock System Reset Timebase Rollover Interrupt WDT Interrupt WDT Reset Figure 1 Timebase WDT Organization The TBWDT has the following characteristics Consists of a free running 32 bit timebase counter that is used for both general purpose timing and the WDT facility The timebase counter always counts up from system reset and is read only WDT timeout interval is determined by which bit in the timebase is used as input to the WDT state machine WDT uses a dual expiration architecture 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 www xilinx com 183 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Programming Model 184 OPB Timebase WDT Specification After one expiration of the timeout interval an interrupt is generated and the WDT state bit is set to one in the status register If the state bit is not cleared by writing a 1 to the state bit before the next expiration of the timeout interval a WDT reset is generated A WDT reset sets the WDT reset status bit in the status register so that the application
33. T Enabled 27 DRR Read Write 0 Data Receive Register Full Receive Full enable FIFO Enable Enables this interrupt to be passed to the interrupt controller 70 Not enabled T Enabled 26 DRR Over Read Write 0 Receive FIFO Over run Enable Enables this run enable interrupt to be passed to the interrupt controller 70 Not enabled T Enabled 25 TxFIFO Read Write 0 Transmit FIFO Less Than or Equal to Half Near Empty Enable Enables this interrupt to be Empty passed to the interrupt controller enable e 70 Not enabled T Enabled 24 Read Write 0 Unassigned v1 00b MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 167 XILINX OPB Serial Peripheral Interface SPI Design Specification SPI Assembly Reset Descriptions The IPIF module in the SPI assembly has instantiated in it the IP reset module This module permits software reset of the SPI module independent of other modules in the system and has another register for test purposes SPI Control Register CR Bit assignment in the SPI Control Register is shown in Table 8 Bit assignment was made to follow the assignment pattern of Xilinx IPIF specifications and when possible follow the 68HC11 assignment pattern Table 8 SPI Control Register Bit Definitions Bit assignment assumes 32 bit bus Bit s Name Core Access Reset Value Description 31 LOOP Read W
34. XILINX OPB General Purpose Input Output GPIO Specification 179 SUMMATY RT 179 179 Features 179 GPIO 179 Programming s oco iri taies nrbi dat 180 Register Data Types and Organization 180 Registers of the ia actio ien tte onte 181 Address Map dies d 182 coils PT P UH 183 Operations M 183 d 183 SUM ALY reperiri eee 183 183 Parameteftza tloDi 184 OPB Timebase WDT Specification 185 SUMMA Y m 185 VETV EW emn 185 185 WDT Organizations octets 185 Programming 186 Register Data Types and Organization 186 Registers of the Timebase Watchdog Timer sess 187 Address Map esis 188
35. XILINX On Chip Peripheral Bus Arbiter Design Specification When the OPB Arbiter has been parameterized to support a processor interface C PROC INTRFCE 1 the Priority registers can still be loaded by the processor allowing the processor to change the priorities of the OPB Masters Also the arbiter can be set to operate in a fixed priority mode by the processor writing to the Control Register and negating the DPE bit However the pipeline registers between the arbitration logic and the register update logic are still present thereby delaying the grant outputs by an additional clock cycle ARB2BUS Data Mux When read of the OPB Arbiter Priority Registers or the OPB Arbiter Control Register is requested on the OPB the ARB2BUS Data Mux outputs the requested data to the IPIF which sends this data to the OPB with the required protocol This logic is only present in the design if PROC INTRFCE 1 and C NUM MASTERS 1 Arbitration Logic Figure 13 depicts the functional block diagram of arbitration logic for the OPB arbiter This logic is only present in the design if C NUM MASTERS 1 The pipeline registers are only present in the arbitration logic if DYNAM PRIORITY 1 All master request signals are input to the Prioritize Request block which consists of multiplexors which prioritize the master s requests into the signals req req Ivlm req and req based on the requesting masters priorities if PRV
36. other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 www xilinx com 133 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB ZBT Controller Design Specification ZBT Controller The I O signals for the ZBT Controller are listed in Table 2 Signals Table 2 ZBT COntroller I O Signals Signal Name Interface I O Description OPB Clock OPB Rst OPB Reset OPB ABus 0 31 OPB OPB Address Bus OPB BE 0 3 OPB OPB Byte Enables OPB DBus 0 31 OPB OPB Data Bus OPB RNW OPB OPB Read Not Write OPB select OPB OPB Select OPB OPB Sequential Address ZBT_DBus 0 31zbt OPB ZBT Controller Data Bus ZBT_errAck OPB ZBT Controller Error Acknowledge ZBT_retry OPB ZBT Controller Retry ZBT_toutSup OPB ZBT Controller Timeout Suppress ZBT_xferAck OPB ZBT Controller Transfer Acknowledge ZBT Feedback ZBT Clock for clock synchronization 2 FBOut IP Core O Feedback ZBT Clock for clock synchronization 2 IP Core ZBT Memory clock ZBT CKE N IP Core ZBT Memory clock enable ZBT OE N IP Core ZBT Memory output enable ZBT ADV LD N IP Core ZBT Memory Control signal ZBT LBO N IP Core Z
37. XILINX OPB Block RAM BRAM Specification Table 1 OPB_BRAM 131 Table 2 OPB BRAM Signals tette rere i atre tais 132 OPB ZBT Controller Design Specification Table 1 ZBT Controller 135 Table 2 COntroller Signals eene ein neret nnn 136 Table 3 Signal Connection eene cepere Greiner 137 OPB UART Lite Specification Table 1 UART Lite Parameters esee entrent etre 14 Table 2 UART Lite UO Signals unas bere ectetur tere irte 142 Table 3 Status Register reete eerte nnt cei dr cer 144 Table 4 Control Register CTRL essent 146 Table 5 OPB UART Lite Performance and Resource Utilization Benchmarks Virtex II 2 1000 5 147 OPB JTAG UART Specification Table 1 UART Parameters 2222 2 2 0000000000000000000000000000404 3 149 Table 2 JTAG UART Signals ooh eee me eem mea s 150 Table 3 Status Register ruroci greeted rite e erit re dread 152 Table 4 Control Register 153 Table 5 OPB JTAG UART Performance and Resource Utilization Benchmarks Virtex II 2V1000 5 154 OPB Serial Peripheral Interface SPI Design Specification Table 1 Parameters to Configure the SPI Assembly eese 163 Table 2 SPI Assembly
38. 0 Transmit FIFO is not full 1 Transmit FIFO is full Reset Value 29 TX FIFO EMPTY Transmit FIFO is empty Indicates if the transmit FIFO is empty 0 Transmit FIFO is not empty 1 Transmit FIFO is empty 30 RX FIFO FULL Receive FIFO is full Indicates if the receive FIFO is full 0 Receive FIFO is not full 1 Receive FIFO is full 31 RX FIFO VALID DATA Receive FIFO is has valid data Indicates if the receive FIFO has valid data 0 Receive FIFO is empty 1 Receive FIFO has valid data March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 147 XILINX Control Register CTRL REG OPB UART Lite Specification The Control register contains the UART Lite control Table 4 Control Register CTRL REG Bits 0 26 Name Reserved Description Not used Reset Value 27 ENABLE INTR Enable Interrupt for the UART 0 Disable interrupt signal 1 Enable interrupt signal 28 29 Reserved Not used 30 RST RX FIFO Reset Clear the receive FIFO When written to with a 1 the receive FIFO is cleared 0 Do nothing 1 Clear the receive FIFO 31 RST TX FIFO Reset Clear the transmit FIFO When written to with a 1 the transmit FIFO is cleared 0 Do nothing 1 Clear the transmit FIFO Address Map UART BASE ADDRESS 0 Read from Receive FIFO UART BASE ADDRESS 4 Write to transmit FIFO
39. 18 Figure 9 MicroBlaze Big Endian Data 19 Figure 10 OPB Interconnection breaking up read and write 22 Figure 11 OPB Interconnection with multi ported slave and no bridge 23 Figure 12 LMB Generic Write Operation sess eee e eene 26 Figure 13 LMB Generic Read Operation sese eee eee emen 26 Figure 14 LMB Single Cycle Back to Back Write Operation sse 26 Figure 15 LMB Single Cycle Back to Back Read 2 2 44 4222224 1 27 Figure 16 Back to Back Mixed Read Write Operation sess 27 OPB Usage in Xilinx FPGAs Figure 1 Figure 2 Byte lane usage for aligned transfers sss 33 OPB Interconnect with Mixed Device Types sss 37 Microprocessor Peripheral Definition Format Figure 1 Figure 2 Peripheral Directory Structure 48 IOBUF Implenientation o neeeneeotee Gomera dread 60 On Chip Peripheral Bus OPB Arbiter Design Specification Figure 1 OPB Fixed Bus Arbitration Combinational Grant Outputs 62 Figure 2 OPB Fixed Bus Arbitration Registered Grant Outputs ee 62 Figure 3 Continuous Master Bus Request Fixed Priority Combinational Grant Outputs sese ee eee 63 Figure 4 Continuous Master Bus Request Fixed Priority Registered Grant Outputs 63 Figure
40. Data output bus gated P12 SPI_xferAck OPB OR logic O Attachment transfer acknowledgement v1 00b www xilinx com 161 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Table 2 SPI Assembly I O Signals OPB Serial Peripheral Interface SPI Design Specification External Group label Signal Name Interface Signal Description P13 SPI errAck OPB OR logic Attachment bus error tied low P14 SPI toutSup OPB OR logic Attachment time out suppress tied low P15 SPI retry OPB OR logic Attachment retry tied low SPI P16 SOKI SPI SPI Bus Clock Input devices P17 SCK_O All SPI SPI Bus Clock Output devices P18 SCK_T All SPI SPI Bus Clock 3 state Enable devices 8 state when high P19 MOSI I All SPI Master out Slave in Input devices P20 MOSI All SPI Master out Slave in Output devices P21 MOSI T All SPI Master out Slave in 3 state devices Enable 3 state when high P22 MISO I SPI Master in slave out Input devices P23 MISO O All SPI Master in slave out Output devices P24 MISO_T All SPI Master in slave out 3 state devices Enable 3 state when high P25 SPISEL SPI master Local SPI slave select active devices low input P26 SS None Input of slave select vector of Included for length N Input where there are tool N SPI devices but not requirements connected 27 55
41. Revision T www xilinx com MicroBlaze Hardware Reference Guide 1 800 255 7778 List of Figures xiii List of Tables ttt ttt xvii XILINX OPB Usage in 31 SUMMATY REP RN 31 Sila HC 31 Xilinx OPB Usage TT iini ar ig 31 OPB anen EAEEREN EA RAER a 31 Xilinx OPB DEVICES sco eto E mo eee ets 32 Specifications for OPB Usage in Xilinx developed OPB 33 Legacy OPB Cc ner Hcet deo e 36 Mixed Systems neco a a eerte e iss van ine tech EORR 37 OPB pp 37 OPB MUN 38 Revision EHS O dre Ue t ME DR 40 Microprocessor Hardware Specification MHS Format 41 as 41 41 MHS Synta 41 COMENTS dokes 41 Peripheral 41 ASSIQNMENE 41 Ending a Peripheral 42 MES Example serer ese erret ettet nir eerie restet pe di ep ree tee 42 MHS Peripheral 44 CONFIGURATION
42. 0 In either CPHA format a transfer can be aborted by taking the SS N signal high which causes the SPI slave logic and bit counters to be reset In this implementation the software driver can deselect all slaves i e SS N is all ones to abort a transaction and it is by design the software responsibility to inhibit the user from changing slaves during a SPI single transfer or buffer transfer However the hardware does allow such a change in slave select Recall that in this implementation the transmit register is double buffered with the shift register Furthermore it is required that SS be asserted in all modes In slave configuration the data is transmitted from the transmit register on the first OPB rising clock edge following SS signal being asserted if data is available in the register or FIFO If data is not available then the under run interrupt is asserted Transfer Ending Period The definition of the transfer ending period is taken directly from the M68HC11 Reference Manual this manual can be referenced for more details which are not reproduced herein As stated in the manual a SPI transfer is technically complete when the SPIF flag is set but depending on the configuration of the SPI system there may be additional tasks to be v1 00b www xilinx com 157 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Serial Peripheral Interface SPI Design Specification performed before the system can consi
43. 1 2 3 4 5 6 E M request 1 OPB MNGrant 1 M1 busLock 1 select OPB xferAck _ _ Figure 15 Bus Locking Fixed Priority Combinational Grant Outputs Cycles 0 1 2 3 4 5 6 7 J L M request 1 Au IN SEM EE EN LN OPB MNGrant 1 M1 busLock 1 select OPB xferAck Figure 16 Bus Locking Fixed Priority Registered Grant Outputs Park Logic When PARK 1 the OPB Arbiter supports bus parking Bus parking is when a master s grant signal is asserted during valid arbitration cycles when no other master devices are requesting This reduces latency for the parked master eliminating the need for a request grant cycle when initiating a new OPB transfer Asserting a grant signal for parking is considered an arbitration since it determines which device controls the bus If dynamic priority mode is enabled the ID of the parked master will be shifted to the lowest priority slot of the Priority Register The master will remain parked its grant signal asserted so long as no other master asserts a request signal If the parked master and another master assert request at the same time the parked master will control the bus because the bus was parked on this master even though t
44. 1580 FPGA implementation does not support scan 1560 FPGA implementation does not support scan 1580 FPGA implementation does not support scan 1880 scanGate FPGA implementation does not support scan LSSD scanln FPGA implementation does not support scan 1580 scanOut FPGA implementation does not support scan Reference The following documents contain reference information important to understanding the OPB Documents Arbiter design 1 64 Bit On Chip Peripheral Bus Architectural Specification v2 0 On Chip Peripheral Bus Arbiter Core User s Manual v1 5 32 Bit Implementation March 2002 www xilinx com 89 1 800 255 7778 5 XILINX 90 On Chip Peripheral Bus Arbiter Design Specification wwWwW xilinx com March 2002 1 800 255 7778 XILINX 2002 Summary Overview Xilinx Embedded Processors OPB Peripherals OPB Simple Interrupt Controller Specification This document describes the specifications for a Simple Interrupt Controller for use in Xilinx FPGAs This document applies to the following peripherals opb intc v1 00b A Simple Interrupt Controller is composed of a bus centric wrapper that contains the IntC core and a bus interface The IntC core is a simple parameterized interrupt controller that along with the appropriate bus interface attaches to either the OPB On chip Peripheral Bus or the DCR Device Cont
45. 24 Read 0 Unassigned 170 www xilinx com v1 00b 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Serial Peripheral Interface SPI Design Specification XILINX Data Transmit Register DTR This register is write only and contains data to be transmitted on the SPI bus It is double buffered with the shift register The data is transferred from the register to the shift register following enable bit being set high in master mode or following SPISEL being active in slave mode If a transfer is in progress the data in the DTR is loaded in the shift register as soon as the data in the shift register is transferred to the receive register DRR and a new transfer starts The data in the DTR is held in the DTR until a subsequent write overwrites the data Table 10 shows specifics of the data format When a Transmit FIFO exists data is written directly in the FIFO and the register is simply in the FIFO The pointer is decremented at the time of completion of each SPI transfer The hardware that forwards data from the register or FIFO to shift register will never cause a write collision error Attempting to write to a full register or FIFO will not result in a write acknowledgement for the OPB transaction but rather an OPB timeout Table 10 SPI Data Transmit Register Bit Definitions Bit assignment assumes 32 bit bus Reset Bit s Name Access Value Description 24 DO 07 Write Only 0x00 SPI Transmit Data 31
46. 28 OPB Usage in Xilinx FPGAs Table 1 Summary of OPB Master only I O sees eee 34 Table 2 Summary of OPB Slave only 34 Table 3 Summary of OPB Master Slave Device 35 Table 4 Comparison of buses used in Xilinx embedded processor systems 39 Microprocessor Hardware Specification MHS Format 1 MHS Peripheral Options tet ener en edet ines iine ire 44 Table 2 MHS Signal Options eane ane aae eoi dedi 44 Table 3 Local Memory Sizes eren nier eee rc ine iri erii 45 Microprocessor Peripheral Definition Format Table 1 Reserved Peripheral Attribute 51 Table 2 MPD Peripheral ere rri 55 Table 3 MPD Signal Options eeieeuieonieneii irae prie eri i eer 56 On Chip Peripheral Bus OPB Arbiter Design Specification Table 1 OPB Arbiter Design 65 Table 2 OPB Arbiter Sign ls 5 inei bene rere dettes 66 Table 3 Parameter Port Dependencies 11e eene nenne 67 Tuble 4 OPB Arbiter e rete aterert 69 Table 5 OPB Arbiter Control Register n 69 March 2002 www xilinx com MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Table 6 OPB Arbiter Control Register Bit 70 Table 7 OPB Arbiter OPB Arbiter LVLn Priority 22 402222 72 Table
47. 64 www xilinx com March 2002 1 800 255 7778 On Chip Peripheral Bus OPB Arbiter Design Specification XILINX An OPB master device need not deassert its request upon receipt of a bus grant signal if it has multiple bus transfer cycles to perform Figure 3 shows an OPB arbitration cycle in which an OPB master asserts bus request continuously for four data transfer cycles The OPB Arbiter has been parameterized for fixed priority arbitration and combinational grant outputs therefore bus grant is asserted combinationally during valid arbitration cycles Cycles 0 1 2 3 2 5 2 M request 1 Y OPB_MGrant 1 ee MOS _ M1_busLock M1 select OPB xterack 120001 f AS ky AS Figure 3 Continuous Master Bus Request Fixed priority Combinational Grant Outputs When the OPB Arbiter has been parameterized for registered grant outputs and fixed priority the bus grants are registered as shown in the following figure Cycles 0 1 2 3 4 5 6 E B orsck 3 ES e M request 1 MGrani 1 y es M1 busLock M1 select OPB xferAck 2 1 Figure 4 Continuous Master Bus Request Fixed priority Registered Grant Outputs Even if an OPB master asserts request continuously it
48. ANDNI Rd Ra Imm 101011 Rd Ra Imm Rd Ra and IMM Imm 101100 00000 00000 Imm Imm 0 15 Im RTSD 101101 10000 Imm mm 101101 10001 Ra Imm PC s Imm MSR IE 1 RTBD 101101 10010 Ra Imm PC s Imm MSR BIP 0 BRID Imm 101110 00000 10000 Imm PC PC s Imm BRLID 101110 Rd 10100 Imm PC s Imm Rd BRAI Imm 101110 00000 01000 Imm PC s Imm BRAID Imm 101110 00000 11000 Imm PC s Imm BRALID 101110 Rd 11100 Imm PC s Imm Rd PC 101110 Rd 01100 Imm PC s Imm Rd PC MSR BIP 1 March 2002 www xilinx com 5 MicroBlaze Hardware Reference Guide 1 800 255 7778 5 XILINX Table 2 MicroBlaze Instruction Set Summary Continued The MicroBlaze Architecture 1 800 255 7778 Type A 0 5 6 10 11 15 16 20 21 31 Type B 0 5 6 10 11 15 16 31 Semantics 101111 00000 Ra Imm if Ra 0 PC s Imm BNEI 101111 00001 Ra Imm if Ra 0 PC PC s Imm 101111 00010 Ra Imm if Ra lt 0 PC s Imm BLEI 101111 00011 Ra Imm if Ra lt 0 PC PC s Imm 101111 00100 Ra Imm if Ra gt 0 PC PC s Imm 101111 00101 Ra Imm if Ra g
49. Default Parameter Allowed value to Constraint and Group Label Feature generic Name Values GUI VHDL type G9 OPB to SPI SCK C OPB SCK RATIO 2 4 16 32 2 type integer frequencies ratio NX16 for N 1 2 3 128 G10 Slave only mode C SPI SLAVE ONLY non zero Set to 0 type integer ded Disabled Not implemented at this time G11 Number of off chip C NUM OFFCHIP S 0 to the Set to 0 type integer Slave Selectbitsin S BITS Number of bits Disabled Must baless thain SS vector in OPB equal to NUM SS BITS G12 Total number of C NUM SS BITS 1 up to the 1 type integer 24 6 diced of bits Must be less than vector 3 b equal to the number of bits in the OPB databus SPI Assembly The I O signals for the SPI Assembly are listed in Figure 2 The interfaces referenced in this Signals table are shown in Figure 1 Table 2 SPI Assembly Signals External Group label Signal Name Interface Signal Description System P1 OPB Rst System Reset signal P2 IP2INTC Interrupt Interrupt signal to interrupt controller controller P3 Freeze System Software freeze command signal OPB P4 OPB OPB Bus clock P5 OPB select OPB Select signal from OPB P6 OPB RNW OPB OPB read write P7 OPB OPB sequential address P8 OPB BE OPB OPB byte enable P9 OPB ABus OPB OPB address bus P10 OPB DBus OPB OPB data bus P11 SPI DBus OPB OR logic
50. IVR The IVR is a read only register and contains the ordinal value of the highest priority enabled active interrupt input INTO always the LSB is the highest priority interrupt input and each successive input to the left has a correspondingly lower interrupt priority If no interrupt inputs are active then the IVR will contain all ones The IVR is optional in the simple IntC and can be parameterized out of the implementation The IVR is shown in the following diagram and described in Table 20 IVR Interrupt Vector Register 0 w 1 Interrupt Vector Number Table 20 Interrupt Vector Register Bits Name Description Reset Value 0 Interrupt Vector Ordinal of highest priority enabled all ones to Number active interrupt input w 1 106 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Simple Interrupt Controller Specification XILINX Master Enable Register MER This is a two bit read write register The two bits are mapped to the two least significant bits of the location The least significant bit contains the Master Enable ME bit and the next bit contains the Hardware Interrupt Enable HIE bit Writing a 1 to the ME bit enables the IRQ output signal Writing a 0 to the ME bit disables the IRQ output effectively masking all interrupt inputs The HIE bit is a write once bit At reset this bit is reset to zero allowing software to write to the ISR to generate interrupts for testing purposes and
51. In capture mode this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held until it is read 0 Hold counter or capture value 1 Reload generate value or overwrite capture value 28 CAPT1 Enable External Capture Trigger 0 Timer1 0 Disables external capture trigger 1 Enables external capture trigger 29 GENT1 Enable External Generate Signal 0 Timer1 0 Disables external generate signal 1 Enables external generate signal 30 UDT1 Up Down Count Timer1 0 0 Timer functions as up counter 1 Timer functions as down counter 31 MDT 1 Timer1 Mode 0 See the Timer Modes section 0 Timer mode is generate 1 Timer mode is capture Implementation I O Summary Table 5 Summary of Timer Core Signal Interface y o Description OPB OPB OPB Clock OPB Rst OPB OPB Reset OPB ABus 0 31 OPB OPB Address Bus BE 0 3 OPB Byte Enables OPB DBus 0 31 OPB Data Bus OPB RNW OPB OPB Read Not Write 202 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Timer Counter Specification Table 5 Summary of Timer Core XILINX Signal Interface y o Description OPB select OPB OPB Select OPB_segAddr OPB OPB Sequential Address DBus 0 31 OPB TC Data Bus errAck OPB TC Error Acknowledge TC retry OPB TC Retry toutSup OPB TC Timeout Suppress
52. Mn select coincident to the assertion of OPB timeout the master device should ignore OPB timeout and respond to the slave s OPB xferAck or OPB retry signal Cycles 0 1 15 16 17 18 19 OPBCIk 1 M request 1 M request 2 _ N 1 mA OPB_MGrani 2 X OPB select 1 Ed p us Y OPB xferAck OPB retry OPB toutSup mE OPB timeout Figure 21 Timeout Error 86 www xilinx com March 2002 1 800 255 7778 On Chip Peripheral Bus OPB Arbiter Design Specification Design Implementation XILINX To prevent a bus timeout an OPB slave must assert OPB toutSup OR of all slave s ToutSup within 16 cycles from the assertion of OPB select OPB toutSup will be used by the OPB Arbiter to suppress the assertion of OPB timeout and to suspend the timeout counter When OPB toutSup is asserted the timeout counter holds its current value When OPB toutSup is negated the timeout counter resumes counting OPB timeout error suppression is shown in Figure 22 Ces 0o J v 16 169 t6 Meget 101010112121 M request 2 220 1
53. OPB_MGrant 1 f ow NEN OPB select if mM B OPB xferAck T 5 l 1f i OPB retry MEC OPB toutSup quM OPB timeout 1 t Figure 22 OPB Timeout Error Suppression Device Utilization and Performance Benchmarks Since the OPB Arbiter is a module that will be used with other design pieces in the FPGA the utilization and timing numbers reported in this section are just estimates As the OPB Arbiter is combined with other pieces of the FPGA design the utilization of FPGA resources and timing of the OPB Arbiter design will vary from the results reported here In order to analyze the OPB Arbiter s timing within the FPGA a design was created that instantiated the OPB Arbiter with registers on all of the OPB Arbiter inputs and outputs This allowed a constraint to be placed on the clock net for the OPB Arbiter to yield more realistic timing results The fmax parameter shown in Table 9 was calculated with registers on the OPB Arbiter inputs and outputs However the resource utilizations reported in Table 9 do not include the registers on the OPB Arbiter inputs and outputs The OPB Arbiter benchmarks are shown in Table 9 for a Virtex II 5 FPGA using multi pass place and route Table 9 OPB Arbiter FPGA Performance and Resource Utilization Benchmarks Virtex II 5
54. XILINX OPB External Memory Controller EMC Figure 32 depicts the Memory Control State Diagram implemented in the EMC START valid write and prev access read and recover valid read and not prev access read and recover valid write and not prev access read and recover valid read and prev access read and recover or valid read and WRITE RE C not recover ASSERT OE count wait tc or valid write and not recover ASSERT WE count wait tc READ REC AFTER ACK Figure 32 EMC Memory Control State Diagram Memor Basic Timing for Memor g y Controller The Memory Controller is designed to connect to a variety of memory subsystem Operation configurations For detailed descriptions on the timing and protocol of the IDT 71 4165 SRAM and the Intel 28F128J3 StrataFlash refer to the appropriate data sheet However basic read and write timing diagrams are listed below Figure 33 and Figure 34 illustrate the basic read and write functions for the SRAM Table 32 defines the symbols used in the figures for the SRAM CEN ess Mem BEN a DQ 0 Data Valid Figure 33 Timing Waveform for SRAM Read Cycle 122 wwWwW xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB External Memory Controller EMC MEM A Mem CEN Mem BEN Mem WEN Mem DQ 0 P
55. default connection direction bus width Signal names are case sensitive Signal Direction Signals have three modes Signal mode indicates its driver direction and if the port can be read from within the peripheral The three modes and their accepted values are as follows e input input in i output output out o inout inout io MPD Example The following is an example file SELECT slave opb gpio Generics for vhdl or parameters for verilog cset attribute C BASEADDR 0x20000000 std logic vector cset attribute C HIGHADDR 0x200000FF std logic vector cset attribute C OPB DWIDTH 32 integer cset attribute C OPB AWIDTH 32 integer cset attribute C GPIO WIDTH 32 integer cset attribute C ALL INPUTS 0 integer Global ports CSET signal OPB in CSET signal OPB Rst OPB Rst in OPB signals CSET signal OPB ABus OPB ABus in 0 C OPB AWIDTH 1 CSET signal OPB BE OPB BE in 0 C OPB DWIDTH 8 1 CSET signal OPB DBus OPB DBus in 0 C OPB DWIDTH 1 CSET signal OPB RNW OPB RNW in CSET signal OPB select OPB select in CSET signal OPB segAddr segAddr in CSET signal GPIO DBus 51 DBus out 0 C OPB DWIDTH 1 CSET signal GPIO errAck Sl errAck out CSET signal GPIO retry Sl retry out CSET signal GPIO toutSup 51 toutSup out CSET signal
56. hdl vhdl UNIX XIL_MYPERIPHERALS opb_peripherals lt peripheral gt hdl vhdl PC XIL_MYPERIPHERALS opb_peripherals X9616 Figure 1 Peripheral Directory Structure Using Versions You can create multiple versions of your peripheral The version is specified as a literal of the form 1 00 a At the MHS level use the HW_VER attribute to set the hardware version The Platform Generator concatenates v and translates periods to underscores The peripheral name and HW VER are joined together to form a name for a search level in the load path For example if your peripheral is version 1 00 a then the MPD BBD and PAO files are found in the following location XIL MYPERIPHERALS opb peripherals peripheral v1 00 a data UNIX 9eXIL MYPERIPHERALS 96eopb peripherals peripheral v1 00 aWata www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Microprocessor Peripheral Definition Format XILINX MPD Syntax The MPD file is supplied by the IP provider and provides peripheral information to the Platform Generator This file lists ports and default connectivity to the OPB interface Attributes that you set in this file are mapped to generics for VHDL or parameters for Verilog Comments You can insert comments in the MPD file without disrupting processing The following are guidelines for inserting comments Precede comments with the pound sign f Comments can continue to the e
57. s Imm OR Rd Ra Rb 100000 Rd Rb 00000000000 or Rb AND Rd Ra Rb 100001 Rd Ra 00000000000 Ra and Rb 4 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide The MicroBlaze Architecture Table 2 MicroBlaze Instruction Set Summary Continued XILINX Type A 0 5 6 10 11 15 16 20 21 31 Type B 0 5 6 10 11 15 16 31 Semantics XOR Rd Ra Rb 100010 Rd Ra Rb 00000000000 Rd Ra xor Rb ANDN Rd Ra Rb 100011 Rd Ra Rb 00000000000 Ra Rb SRA Rd Ra 100100 0000000000000001 Rd 0 gt gt 1 31 SRC Rd Ra 100100 0000000000100001 Rd C gt gt 1 31 SRL Rd Ra 100100 0000000001000001 0 gt gt 1 C 31 8 Rd Ra 100100 0000000001100000 Rd 0 23 24 Rd 24 31 24 31 SEXT16 Rd Ra 100100 Ra 0000000001100001 Rd 0 15 Ra 16 Rd 16 31 Ra 16 31 MTS Sd Ra 100101 00000 Ra 110000000000000d Sd Ra where S1 is MSR MFS Rd Sa 100101 Rd 00000 100000000000000a Rd Sa where SO is PC and 1 is MSR 100110 00000 00000 Rb 00000000000 PC Rb Rb 100110 00000 10000 Rb 00000000000 PC PC Rb BR
58. the IBM OPB Arbiter specification This deviation is necessary due to the fact that the Park Master ID PID field will vary in width based on the number of masters supported in the design This field has been shifted so that it is LSB aligned and can be read easily by the software as an integer value Also the DPERW and PENRW bits have been added to provide information to the processor about the parameters chosen for the design and the accessibility of the DPE and PEN bits Since the processor requires more than one OPB bus cycle to update the www xilinx com 71 1 800 255 7778 5 XILINX On Chip Peripheral Bus Arbiter Design Specification master s priority levels the bit Priority Registers Valid PRV has been added to indicate that the Priority Registers are being modified and are not valid Table 6 OPB Arbiter Control Register Bit Definitions 72 Bit s Name Core Access Read Write 2 Reset Value 1 Description 0 DPE Read o 0 Dynamic Priority Enable Enables dynamic priority arbitration algorithm and update of the Priority Register 0 dynamic priority arbitration disabled 1 dynamic priority arbitration enabled DPERW Read Dynamic Priority Enable Bit Read Write This bit informs the software as to the access of the DPE bit If the OPB Arbiter is parameterized to only support fixed priority arbitration the DPE bit is always set to 0 to reflect that dynamic priori
59. 0 Address bus Mem A 12 29 A 17 0 Chip Enable low true MEM CEN 0 CS Output Enable low true MEM OEN OE Write Enable low true MEM WEN WE Byte Enable low true MEM BEN 0 1 BHE BLE 1 Data bus Mem DQ 16 31 0 15 0 Address bus Mem A 12 29 A 17 0 Chip Enable low true MEM CEN 0 CS Output Enable low true MEM OEN OE Write Enable low true MEM WEN WE Byte Enable low true MEM BEN 2 3 BHE BLE Example 2 This example shows the connection to 2 banks of 64 bit memory using 4 IDT71V416S SRAM parts per bank Table 38 Variables for Two Banks of SRAM Variable Value Definition BN 0 to 1 Memory bank number DN 0 to 3 Memory device number within a bank The memory device attached to the most significant bit in the memory subsystem is 0 device numbers increase toward the least significant bit MW 64 Width in bits of memory subsystem DW 16 Width in bits of data bus for memory device MAW 18 Width in bits of address bus for memory device March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 127 XILINX OPB External Memory Controller EMC Table 38 Variables for Two Banks of SRAM Continued Variable Value Definition AU 16 Width in bits of smallest addressable data word on the memory device AS 3 Address shift for address bus logo MW AU DW 8 HAW 32 Width of host address bus e g OPB or PLB in bits Table 39 Connection to 64
60. 0 00h Interrupt Pending Register 4 04h Interrupt Enable Register 8 08h Interrupt Acknowledge Register 12 0Ch Set Interrupt Enable Bits 16 10h Clear Interrupt Enable Bits CIE 20 14h Interrupt Vector Register IVR 24 18h Master Enable Register 28 1Ch 99 5 XILINX OPB Simple Interrupt Controller Specification Interrupt Status Register ISR When read the contents of this register indicate the presence or absence of an active interrupt signal regardless of the state of the interrupt enable bits Each bit in this register that is set to a 1 indicates an active interrupt signal on the corresponding interrupt input Bits that are 0 are not active The ISR register is writable by software until the Hardware Interrupt Enable HIE bit in the MER has been set Once that bit has been set software can no longer write to the ISR Given these restrictions when this register is written to any data bits that are set to 1 will activate the corresponding interrupt just as if a hardware input became active Data bits that are zero have no effect This allows software to generate interrupts for test purposes until the HIE bit has been set Once HIE has been set enabling the hardware interrupt inputs then writing to this register does nothing If there are fewer interrupt inputs than the width of the data bus writing a 1 to a non existing interrupt input does nothing and reading it will return zero The ISR is shown in the followi
61. 0 15 0 15 0 Address bus Mem A 11 28 A 17 0 Chip Enable low true MEM CEN 1 CS Output Enable low true MEM OEN OE Write Enable low true MEM WEN WE Byte Enable low true MEM BEN 0 1 BHE BLE 1 Data bus Mem 00 16 31 0 15 0 Address bus Mem A 11 28 A 17 0 Chip Enable low true MEM CEN 1 CS Output Enable low true MEM OEN OE Write Enable low true MEM WEN WE Byte Enable low true MEM BEN 2 3 BHE BLE 2 Data bus Mem 00 32 47 0 15 0 Address bus Mem A 11 28 A 17 0 Chip Enable low true MEM CEN 1 CS Output Enable low true MEM OEN OE Write Enable low true MEM WEN WE Byte Enable low true MEM BEN 4 5 BHE BLE 3 Data bus Mem 00 48 63 0 15 0 Address bus Mem A 11 28 A 17 0 Chip Enable low true MEM CEN 1 cs Output Enable low true MEM_OEN OE Write Enable low true MEM_WEN WE Byte Enable low true MEM_BEN 6 7 BHE BLE Connecting to Intel StrataFlash Because StrataFlash parts contain an identifier register a status register and a command interface the bit label ordering is critical to proper functioning The following tables show examples of how to connect the big endian EMC buses to the little endian StrataFlash parts The proper connection ordering is also indicated in a more general form in Table 35 StrataFlash parts have a x8 mode and a x16 mode selectable with the BYTE input pin To calculate the proper address shift the minimum addressable word is 8 bits for both x8 and x16 m
62. 1 TCR1 0x18 Word R Timer Counter Register 1 The TC registers are organized as big endian data The bit and byte labeling for the big endian data types is shown in the following figure Byte address n 1 2 3 Byte label 0 1 2 3 Word Byte significance MSByte LSByte Bitlabel 0 31 Bit significance MSBit LSBit Byte address n n 1 Byte label 0 1 Half word Byte significance MSByte LSByte Bit label 0 15 Bit significance MSBit LSBit Byte address i Byte label 0 Byte Byte significance MSByte Bit label 0 7 Bit significance MSBit LSBit Figure 2 Big Endian Data Types March 2002 www xilinx com 197 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Timer Counter Specification Register Descriptions Load Register TLRO TLR1 When the counter width has been configured as less than 32 bits the Load Register value is right justified TLRO and TLR1 The least significant counter bit is always mapped to Load Register bit 31 1 TLRO TLR1 Timer Counter Register TCRO TCR1 When the counter width has been configured as less than 32 bits the count value is right justified in TCRO TCR1 The least significant counter bit is always mapped to Timer Counter Register bit 31 1 TCRO TCR1 Control Status Register 0 TCSRO Control Status Register O contains the control and status bits for timer module 0 ENA
63. 3 LMB Bus Signals Signal Data Interface Instr Interface Type Description Addr 0 31 Data Addr 0 31 Instr Addr 0 31 Address bus Byte Enable 0 3 Byte Enable 0 3 not used Byte enables Data Write 0 31 Data Write 0 31 not used Write data bus AS D AS AS O Address strobe Read Strobe Read Strobe Read in progress Write Strobe Write Strobe not used Write in progress Data Read 0 31 Data Read 0 31 Instr 0 31 Read data bus Ready DReady IReady Ready for next transfer Clk Clk Clk Bus clock Addr 0 31 The address bus is an output from the core and indicates the memory address that is being accessed by the current transfer It is valid only when AS is high In multicycle accesses accesses requiring more than one clock cycle to complete Addr 0 31 is valid only in the first clock cycle of the transfer Byte Enable 0 3 The byte enable signals are outputs from the core and indicate which byte lanes of the data bus contain valid data Byte Enable 0 3 is valid only when AS is high In multicycle accesses accesses requiring more than one clock cycle to complete Byte Enable 0 3 is valid only in the first clock cycle of the transfer Valid values for Byte Enable 0 3 are shown in the following table Table 4 Valid Values for Byte Enable 0 3 Byte Lanes Used Byte Enable 0 3 Data 0 7 Data 8 15 Data 16 23 Data 24 31 0000 0
64. 5 491 353 5 495 196 5 498 979 5 498 989 5 499 192 5 500 608 5 500 609 5 502 000 5 502 440 5 504 439 5 506 518 5 506 523 5 506 878 5 513 124 5 517 135 5 521 835 5 521 837 5 523 963 5 523 971 5 524 097 5 526 322 5 528 169 5 528 176 5 530 378 5 530 384 5 546 018 5 550 839 5 550 843 5 552 722 5 553 001 5 559 751 5 561 367 5 561 629 5 561 631 5 563 527 5 563 528 5 563 529 5 563 827 5 565 792 5 566 123 5 570 051 5 574 634 5 574 655 5 578 946 5 581 198 5 581 199 5 581 738 5 583 450 5 583 452 5 592 105 5 594 367 5 598 424 5 600 263 5 600 264 5 600 271 5 600 597 5 608 342 5 610 536 5 610 790 5 610 829 5 612 633 5 617 021 5 617 041 5 617 327 5 617 573 5 623 387 5 627 480 5 629 637 5 629 886 5 631 577 5 631 583 5 635 851 5 636 368 5 640 106 5 642 058 5 646 545 5 646 547 5 646 564 5 646 903 5 648 732 5 648 913 5 650 672 5 650 946 5 652 904 5 654 631 5 656 950 5 657 290 5 659 484 5 661 660 5 661 685 5 670 896 5 670 897 5 672 966 5 673 198 5 675 262 5 675 270 5 675 589 5 677 638 5 682 107 5 689 133 5 689 516 5 691 907 5 691 912 5 694 047 5 694 056 5 724 276 5 694 399 5 696 454 5 701 091 5 701 441 5 703 759 5 705 932 5 705 938 5 708 597 5 712 579 5 715 197 5 717 340 5 719 506 5 719 507 5 724 276 5 726 484 5 726 584 5 734 866 5 734 868 5 737 234 5 737 235 5 737 631 5 742 178 5 742 531 5 744 974 5 744 979 5 744 995 5 748 942 5 748 979 5 752 006 5
65. 7778 XILINX EMC Address Map and Register Descriptions OPB External Memory Controller EMC The EMC supports up to 8 banks of SRAM and or Flash memory Each memory bank has an independent base address and address range The address range of a bank of memory is restricted to be a power of 2 If the desired address range is represented 2 then the n least significant bits of the base address must be 0 For example a memory bank with an addressable range of 16M 224 bytes could have a base address of 0000 and a high address of OxFFFFFFFF A memory bank with an addressable range of 64K 21 bytes could have a base address of 0 0000 and a high address of OXABCDFFFF The addresses for each bank of memory are shown in Table 28 Table 28 EMC Memory Banks Memory Base Address High Address Access Bank 0 C MEMO BASEADDR C MEMO HIGHADDR R W Bank 1 C MEM1 BASEADDR C MEM1 HIGHADDR R W Bank 2 C MEM2 BASEADDR C MEM2 HIGHADDR R W Bank 3 C MEM3 BASEADDR C MEM3 HIGHADDR R W Bank 4 C 4 BASEADDR 4 HIGHADDR R W Bank 5 C MEM5 BASEADDR C 5 HIGHADDR R W Bank 6 C MEM6 BASEADDR MEM6 HIGHADDR R W Bank 7 C MEM7 BASEADDR C MEM7 HIGHADDR R W 118 The EMC contains addressable control registers for write operations as shown in Table 29 The base address for these registers is set in the parameter C BASEADDR which represents the address of the Memory Bank Control Re
66. Addr Memory contents at location Addr data size aligned Table 2 MicroBlaze Instruction Set Summary 0 5 6 10 11 15 16 20 21 31 Type B 0 5 6 10 11 15 16 31 Semantics ADD Rd Ra Rb 000000 Rd Ra Rb 00000000000 Rb Rd Ra Rb 000001 Rb 00000000000 Rb 1 ADDC Rd Ra Rb 000010 Rd Ra Rb 00000000000 Rb Ra RSUBC 000011 Rb 00000000000 Rb Ra ADDK Rd Ra Rb 000100 Rd Ra Rb 00000000000 Rb RSUBK Rd Ra Rb 000101 Rd Ra Rb 00000000000 Rb Ra 1 ADDKC Rd Ra Rb 000110 Rd Ra Rb 00000000000 Ra RSUBKC Rd Ra Rb 000111 Rd Ra Rb 00000000000 ADDI Rd Ra Imm 001000 Rd Ra Imm Rd s Imm RSUBI 001001 Imm Rd s Imm Ra 1 ADDIC Rd Ra Imm 001010 Rd Ra Imm s Imm C RSUBIC Rd Ra Ilmm 001011 Rd Ra Imm s Imm ADDIK 001100 Imm Rd s Imm Ra RSUBIK Rd Ra Imm 001101 Rd Ra Imm Rd s Imm Ra 1 ADDIKC 001110 Rd Ra Imm Rd s Imm Ra C RSUBIKC Rd Ra lmm_ 001111 Rd Ra Imm s Imm MUL Rd Ra Rb 010000 Rd Ra Rb 00000000000 Rb Rd Ra Imm 011000 Rd Ra Imm Ra
67. BRAM Specification 142 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX 2002 Summary Overview UART Lite Parameters Xilinx Embedded Processors OPB Peripherals OPB UART Lite Specification This document describes the specifications for a UART core for the On chip Peripheral Bus OPB This document applies to the following peripherals opb uartlite v1 00a The UART Lite is a module that attaches to the OPB On chip Peripheral Bus and has the following features Features e OPB V2 0 bus interface with byte enable support Supports 8 bit bus interfaces One transmit and one receive channel full duplex 16 character transmit FIFO and 16 character receive FIFO Number of databits in a character is configurable 5 8 Parity can be configured for odd or even e Configurable baud rate To allow you to obtain a UART Lite that is uniquely tailored for your system certain features can be parameterized in a UART Lite design This allows you to configure a design that only utilizes the resources required by your system and operates with the best possible performance The features that can be parameterized in the Xilinx UART Lite design are shown in Table 1 Table 1 UART Lite Parameters Default Feature Description Parameter Name Allowable Values Value VHDL Type UART Lite Registers Base C_BASEADDR Valid Address Ra
68. C OPB AWIDTH 8 32 32 integer 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers as listed at http www xilinx com legal htm other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 www xilinx com MicroBlaze Hardware Reference Guide 1 800 255 7778 139 XILINX OPB Block RAM BRAM Specification OPB_BRAM signals for the OPB_BRAM are listed in Table 2 Signals Table 2 _ Signals Signal Name Interface I O Description OPB OPB Clock OPB Rst OPB OPB Reset OPB ABus 0 C OPB AWIDTH 1 OPB OPB Address Bus BE 0 C OPB DWIDTH 8 1 OPB OPB Byte Enables OPB DBus 0 C OPB DWIDTH 1 OPB OPB Data Bus OPB RNW OPB OPB Read Not Write OPB select OPB OPB Select seqAddr OPB OPB Sequential Address OPB BRAM DWIDTH 1 OPB BRAM Data Bus OPB BRAM errAck OPB O OPB BRAM Error Acknowledge OPB BRAM retry OPB O OPB BRAM Retry OPB BRAM toutSup OPB O OPB BRAM Timeout Suppress OPB BRAM xferAck OPB O OPB BRAM Transfer Acknowledge BRAM Other Other Port Clock Port BRAM Addr 0 31 Other Other Port Address Bus Port BRAM We 0 3 Other Other Port Byte Enables Port BRAM Write Data 0 31 Oth
69. CE 2 0 Output Enable low true MEM OEN Write Enable low true MEM 2 WE Reset Power down low true MEM_RPN RP Status low true MEM_STS 0 STS Byte mode select low true N A tie to GND BYTE Program enable high true N A tie to VCC 3 Data bus Mem DQ 24 31 DQ 7 0 Address bus Mem A 8 29 A 23 0 Chip Enable low true GND GND MEM 0 CE 2 0 Output Enable low true MEM OEN Write Enable low true MEM QWEN 3 Reset Power down low true MEM RPN Status low true MEM STS 0 STS Byte mode select low true N A tie to GND Program enable high true N A tie to VOC Notes 1 2 7 DQ 15 8 are not used and should be treated according to manufacturer s data www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide Xilinx Embedded Processors Peripherals XILINX OPB ZBT Controller Design Specification March 2002 Su mmary This document describes the specifications for a ZBT controller core for the On chip Peripheral Bus OPB This document applies to the following peripherals opb zbt controller v1 00a Overview The ZBT Memory Controller is a 32 bit peripheral that attaches to the OPB On chip Peripheral Bus and has the following features Features OPB V2 0 bus interface with byte enable support Supports 32 bit bus interfaces Supports memory width of 32 bits Operation The OPB Z
70. DIPA in std logic vector 0 downto 0 DIPB in std logic vector 0 downto 0 ENA in std ulogic ENB in std ulogic WEA in std ulogic WEB in std ulogic SSRA in std ulogic SSRB in std ulogic CLKA in std ulogic CLKB in std ulogic ADDRA in std logic vector 10 downto 0 ADDRB in std logic vector 10 downto 0 DOA out std logic vector 7 downto 0 DOB out std logic vector 7 downto 0 DOPA out std logic vector 0 downto 0 DOPB out std logic vector 0 downto 0 end component Swap BRAM Little endian Data to Big endian BE to LE for I in 0 to 31 generate dbus le I lt OPB DBus 31 1 bram write data le I lt BRAM Write Data 31 I BRAM Read Data I lt bram Read Data 31 ABus I lt ABus 31 1 bram Addr 1 lt BRAM Addr 31 1 end generate BE to LE BRAM Instantiation All_Brams for I in 0 to C_NO_BRAMS 1 generate By 8 if C_NO_BRAMS 4 generate RAMB16 S9 S9 I RAMB16_S9_S9 port map DIA gt DBUS LE I 1 8 1 downto I 8 in std logic vector 7 downto 0 DIB bram Write Data LE I 1 8 1 downto I 8 in std logic vector downto 0 DIPA gt null 1 in std logic vector 7 downto 0 DIPB gt null 1 in std logic vector 7 downto 0 ENA gt 1 in std ulogic ENB gt 1 in std ulogic WEA opb WE I in std ulogic WEB gt BRAM WE I
71. DOPB ABus 0 31 DOPB BE 0 3 SH rdDBus 0 31 DOPB busLock errAck DOPB_wrDBus 0 31 OPB SI1 retry DOPB ABus 0 31 Required if more than DOPB RNW Slavet S timeout d DOPB BE 0 3 one master present DOPB select toutSup gt DOPB busLock DOPB gt Sl1_xferAck gt DOPB wrDBus 0 31 Bond DOPB rdDBus 0 31 side DOPB_RNW OPB DOPB_select arbiter DOPB rdDBus 0 31 DM ABus 0 31 gt DOPB_segAddr DOPB errAck gt DM_BE 0 3 gt DOPB errAck DOPB retry Ern DM busLock gt DOPB retry DOPB timeout MicroBlaze DM_wrDBus 0 31 gt OR DOPB timeout DOPB xferAck _ DataOPB DM RNW like DOPB toutSup Interface DM select gt suttixes DOPB_xferAck DM_segAddr DOPB q DOPB MGrant DM request Present for Bus Monitor functions DOPB ABus 0 31 DOPB BE 0 3 gt SI2 rdDBus 0 31 gt DOPB wrDBus 0 31 DOPB DBus 0 31 DOPB busLock SI2 gt DOPB rdDBus 0 31 l OR DOPB wrDBus 0 31 SI2 retry gt DOPB
72. Each bit is One hot encoded active low interfaced to a slave select vector of length N SPI device Output P28 SS T Each bit is Single 3 state control signal for interfaced to a slave select vector of length N SPI device 8 state when high Port and Table 3 lists dependencies of ports and parameters on each parameter Parameter Dependencies 162 www xilinx com 1 800 255 7778 v1 00b MicroBlaze Hardware Reference Guide OPB Serial Peripheral Interface SPI Design Specification Table 3 Port and Parameter Dependencies for Slave Attachment 5 XILINX Parameter Group label generic name Affects Depends Relationship Description OPB G1 ID G2 MIR ENABLE None None G3 C BASEADDR None G6 Must be of length C OPB AWIDTH where lower order bits are zeros The number of lower order bits that are zero is equal to the number of continuous lower order bits in HIGHADDR that are non zero and not equal to the same bit in C BASEADDR G4 HIGHADDR None G3 G6 Included at request of Platform Generator Designers G5 C INTERRUPT PRESEN None None Software drivers available only T when present i e 1 G6 C OPB AWIDTH P9 G3 4 None Sets OPB address bus interface width G7 C OPB DWIDTH P8 P10 None Sets OPB data bus and byte enable interface widths SPI G8 C FIFO EXIST None None G9 C 5 RATIO P16 None Determines OPB to SCK fr
73. Fetch Decode Execute In the MicroBlaze parallel pipeline each stage is active on each clock cycle Three instructions can be executed simultaneously one at each of the three pipeline stages Even though it takes three clock cycles for each instruction to complete each pipeline stage can work on other instructions in parallel with and in advance of the instruction that is completing Within one clock cycle one new instruction is fetched another is decoded and a third is completed The pipeline effectively completes one instruction per clock cycle cycle 1 cycle 2 cycle 3 cycle4 5 instruction 1 Fetch Decode Execute instruction 2 Fetch Decode Execute instruction 3 Fetch Decode Execute 8 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide The MicroBlaze Architecture XILINX Branches Similar to other processor pipelines the MicroBlaze pipeline can originate control hazards that affect the pipeline execution rate When an instruction that changes the control flow of a program branches is executed and completed and eventually changes the program flow taken branches the previous pipeline work becomes useless When the processor executes a taken branch the instructions in the fetch and decode stages are not the correct ones and must be discarded or flushed from the pipeline The processor must refill the pipeline with the correct instructions taking thr
74. GPIO xferAck 51 xferAck out gpio signals CSET signal GPIO IO inout 0 C GPIO WIDTH 1 ENABLE MULTI END MPD Attribute This section provides syntax rules for attribute names for IP and systems MPD attributes Naming correlate to generics for VHDL or parameters for Verilog The attribute name must be HDL Conventions VHDL Verilog compliant VHDL and Verilog have certain naming rules and conventions that must be followed 52 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Microprocessor Peripheral Definition Format XILINX The Platform Generator automatically expands and populates certain reserved attributes This can help prevent errors when your peripheral requires information on the platform that is generated The following table lists the reserved attribute names Table 1 Reserved Peripheral Attribute Names March 2002 MicroBlaze Hardware Reference Guide Automatic Attribute Description Expansion C FAMILY FPGA Device Family X BASEADDR Base address of peripheral HIGHADDR High address of peripheral C LM BASEADDR Base address of Local Memory C LM HIGHADDR High address of Local Memory C NUM MASTERS Number of masters X C NUM SLAVES Number of slaves X C NUM INTR INPUTS Number of interrupt signals X AWIDTH Address width X DWIDTH OPB Data width X C FAMILY Attribute The FAMILY attribute defines the FP
75. IntC registers However a bigger memory map space allocated to the simple IntC will reduce the FPGA resources required for decoding the address For example BASEADDR 0x70800000 HIGHADDR 0x7080001F provides the maximum address decode resolution for an OPB IntC requiring the upper 27 address bits to be decoded This choice will increase the number of FPGA resources required for implementation and may adversely affect the maximum operating frequency of the system Conversely BASEADDR 0x70800000 C HIGHADDR Ox7FFFFFFF will significantly reduce the address decoding logic for an OPB IntC only the 4 upper address bits resulting in a smaller and faster implementation A similar situation exists for the DCR IntC with the exception that the addresses are only ten bits wide so the maximum address decode resolution for a DCR IntC requires seven upper address bits to be decoded Table 25 lists the top level generics parameters that are present in an OPB IntC Table 25 Generics Parameters for an OPB IntC Generic Name Description Type Valid Values C AWIDTH Width of the OPB address bus Integer 32 OPB DWIDTH Width of the OPB data buses Integer 8 16 32 March 2002 www xilinx com 111 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Simple Interrupt Controller Specification 112 wwwW xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX Xilinx Embedded Process
76. LSBit Figure 9 MicroBlaze Big Endian Data Types Core I O The MicroBlaze core implements separate buses for instruction fetch and data access denoted the side and D side buses respectively These buses are split into the following two bus types e OPB V2 0 compliant bus for OPB peripherals and memory controllers Local Memory Bus used exclusively for high speed access to internal block RAM BRAM All core I O signals are listed in Table 2 Page numbers prefaced by OPB reference IBM s 64 Bit On Chip Peripheral Bus Architectural Specifications Version 2 0 The core interfaces shown in the following table are defined as follows DOPB Data interface On chip Peripheral Bus DLMB Data interface Local Memory Bus BRAM only Instruction interface On chip Peripheral Bus ILMB Instruction interface Local Memory Bus BRAM only Core Miscellaneous signals March 2002 www xilinx com 21 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Table 2 Summary of MicroBlaze Core I O MicroBlaze Bus Interfaces Signal Interface Description Page DM ABus 0 31 DOPB Data interface OPB address bus OPB 11 DM BE 0 3 DOPB Data interface OPB byte enables OPB 16 DM busLock DOPB Data interface OPB buslock OPB 9 DM DBus 0 31 DOPB Data interface OPB write data bus OPB 13 DM request DOPB Data in
77. MASIERS Attribute teorema aet bo m epit 51 CUNUM SLAY ES ono eerte penne pta rra de a ona medie 52 C NUM INTR INPUTS 52 C OPB AWIDTIEI Attribute nere rete ee tenete xe eere re debes 52 CORB DWIDTEUAEDUte emen REO RE 52 MPD Signal Naming Conventions engen retreat tetra sentes 52 Global Ports neat retener e ope ene dier inei Re erii 52 Master sro T I 52 Slave OPB Ports x ceci mec niente tree ret eee Prieto ied i id e 53 MPD Reserved Signal sss 54 1 Q 54 Master OPB POEtS aceite 54 NEV COR Bs PORES 54 m TT 55 MPD Peripheral 55 ODEHOEf PE OUI RIPE 55 EDIF ue 56 INBYTE or OUTBYTE Option 56 MPD Signal OPHONS 56 acres MMC TES 56 EDGE ODBOLD teh semis DX oa PUREE VESE RRE EUER VPE 57 ENABLE Option etenim 57 ENDIAN EG be aS 57 OPO eerie ee ente oe RE a eee cuite o re 57 LEVEL OpEUOPk heit hs itam CH Seu eva ete Ee 57 i
78. Reg 31 32 1 1 1T 1 LVL2 Priority Reg 31 32 X 10 LVL3 Priority Reg 31 32 X m M request 0 LL wi e 12 M request 1 M EU NE M requesi 2 ee ee ee M request 3 V _ 0 T T oPB MGrnfi OPB NGrant 2 OPB MGrant 3 _ Figure 9 Fixed Priority Arbitration Registered Grant Outputs for 4 OPB Masters Dynamic Priority Parameterization C DYNAM PRIORITYz1 When the OPB Arbiter is parameterized to support dynamic priority arbitration dynamic priority arbitration mode is enabled at reset or at any other time by writing a 1 to the DPE bit of the Control Register Disabling dynamic priority arbitration mode by setting the DPE bit to 0 puts the OPB Arbiter into a fixed priority arbitration mode This effectively freezes the values of the Priority registers unless updated by an OPB write to the registers and thus its ordering of arbitration priorities among the attached master devices Setting the master priorities by software and not allowing them to update results in a static assignment of priority among the OPB masters Upon reset the Priority registers contains the reset values as described in Table 8 and the dynamic priority bit is enabled When dynamic priority arbitration mode is enabled the contents of the Priority Registers are reordered after every request
79. Register FIFO as required 7 Write all data to master transmit Register FIFO 8 Write enable bit to master control register which starts transfer 9 Wait for interrupt typically interrupt 30 or poll status for completion 10 Read interrupt registers of both master and slave SPI devices as required 11 Perform interrupt requests as required 12 Read status registers of both master and slave SPI devices as required 13 Perform actions as required or dictated by status register data SPI Master and Slave Devices with FIFOs where some initial data is written to FIFOs the SPI transfer is started data is written to the FIFOs as fast or faster than the SPI transfer and multiple discrete 8 bit transfers are transferred optional mode Follow these steps to successfully complete an SPI transaction 1 Start from proper state including SPI bus arbitration Configure master and slave interrupt enable registers as desired Write configuration data to master SPI device CR as required Write configuration data to slave SPI device CR as required Write the active low one hot encoded slave select address to the master SS register Write initial data to slave transmit FIFO as required Write initial data to master transmit FIFO Oo NO a Write enable bit to master control register which starts transfer 9 Continue writing data to both master and slave FIFOs 10 Wait for interrupt typically interrupt 30 or poll status for
80. Rst OPB Rst in Master OPB Ports For interconnection to the OPB all masters must provide the following connections for each connection to the OPB CSET signal Mn ABus M ABus out 0 C OPB AWIDTH CSET signal Mn BE M BE out 0 C OPB DWIDTH 8 1 CSET signal Mn busLock M busLock out CSET signal Mn DBus M DBus out 0 C OPB DWIDTH 1 CSET signal Mn request M request out CSET signal Mn RNW M RNW out CSET signal Mn select M select out CSET signal Mn segAddr M segAddr out CSET signal nOPB DBus OPB DBus in 0 C OPB DWIDTH 1 CSET signal nOPB errAck OPB errAck in CSET signal nOPB MGrant OPB MGrant in CSET signal nOPB retry OPB retry in CSET signal nOPB timeout OPB timeout in CSET signal nOPB xferAck OPB xferAck in Slave OPB Ports For interconnection to the OPB all slaves must provide the following connections for each connection to the OPB CSET signal lt Sln gt _DBus 51 DBus out 0 C OPB DWIDTH 1 CSET signal Sln 51 errAck out CSET signal lt Sln gt _retry 51 retry out CSET signal lt 51 gt toutSup 51 toutSup out CSET signal lt 51 gt xferAck 51 xferAck out CSET signal nOPB ABus OPB ABus in 0 C OPB AWIDTH 1 CSET signal nOPB BE OPB BE in 0 C OPB DWIDTH 8 1 CSET signal nOPB DBus OPB DBus in 0 C OPB DWIDTH 1 CSET signal nOPB RNW OPB RNW in CSET signal nOPB select OPB selec
81. Specification Figure 1 Timebase WDT eene eene 185 Figure 2 Big Endian Data 187 Figure 3 TBWDT Register uerit bet to ti c 187 Figure 4 WDT State Diagram 191 OPB Timer Counter Specification Figure 1 Timer Counter Organization sess eene 195 Figure 2 Big Endian Data 197 Figure Register 198 March 2002 www xilinx com ix MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX x www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Tables The MicroBlaze Architecture Table 1 Instruction Set Nomenclature 7 eee een nene 4 Table 2 MicroBlaze Instruction Set Summary 4 Table 3 General Purpose Registers 6 Table 4 Program Counter ee enim iiipin 7 Table 5 Machine Status Register 7 MicroBlaze Bus Interfaces Table 1 MicroBlaze Bus Configurations 12 Table 2 Summary of MicroBlaze Core 20 Table 2 LMB Signals eter de 24 Table 4 Valid Values for Byte 0 3 24 Table 5 Read Data Steering load to Register rD eese 28 Table 6 Write Data Steering store from Register rD 44422 24
82. Table 2 EMG VO Signals ee pee hide e ee hd E 114 Table 3 EMC Memory eher cede ice rette d 116 Table 4 EMC Control Registers o ouooocueneene iie nere iie niei 116 Table 5 EMC Control Register Bit Definitions eese eee 117 Table 6 Control Register Bit Functionality sees 117 Table 7 SRAM Parameter 121 Table 8 StrataFlash Parameter 122 Table 9 Variables used in Defining Memory Subsystem esee 124 Table 10 Memory Controller to Memory Interconnect 127 eee 124 Table 11 Variables for Simple SRAM Example eese 124 Table 12 Connection to 32 bit Memory using 2 IDT71V416S 125 Table 13 Variables for Two Banks of SRAM eee eee nee 125 Table 14 Connection to 64 bit Memory using 8 IDT71V416S 126 Table 15 Variables for StrataFlash x16 mode Example esee 128 Table 16 Connection to 32 bit Memory using 2 StrataFlash 128 Table 17 Variables for StrataFlash x8 mode 129 Table 18 Connection to 32 bit Memory using 4 StrataFlash 129 xii www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide
83. The addresses of the UART registers are shown in the Address Map section The JTAG_UART registers are organized as big endian data The bit and byte labeling for the big endian data types is shown in Figure 1 Byte address n n1 2 3 Byte label 0 1 2 3 Word Byte significance MSByte LSByte Bit label 0 31 Bit significance MSBit LSBit Byte address n n1 Byte label 1 Halfword Byte significance MSByte LSByte Bit label 0 15 Bit significance MSBit LSBit Byte address n Byte label 0 Byte Byte significance MSByte Bit label 0 7 Bit significance MSBit LSBit Figure 1 Big Endian Data Types Registers of the JTAG_UART Information on the following registers used in assembly language programming are described in this section Receive FIFO Read character from Receive FIFO Transmit FIFO write character into Transmit FIFO Status Read from Status Register Control Write to Control Register Figure 2 JTAG UART Register Set www xilinx com 207 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX 208 Status Register STATREG The Status register contains the status of the receive and transmit FIFO if interrupts are enabled and if there are any errors Table 3 Status Register OPB JTAG UART Specification Bits 0 26 Name Reserved Description Not used Reset Value 27 INT
84. UART BASE ADDRESS 8 Read from Status Register UART BASE ADDRESS 12 Write to Control Register Interrupts If interrupts are enabled an interrupt is generated when one of the following conditions is true 1 When there exists any valid character in the receive FIFO the interrupt stays active until the receive FIFO is empty 2 When the transmit FIFO goes from not empty to empty such as when the last character in the transmit FIFO is transmitted the interrupt is only active one clock cycle 148 www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide UART Lite Specification XILINX Design Device Utilization and Performance Benchmarks Implementation The following table shows approximate resource utilization and performance benchmarks for the OPB UART Lite The estimates shown are not guaranteed and can vary with FPGA family and speed grade implementation parameters user timing constraints and implementation tool version Only parameters that affect resource utilization are shown in the following table Table 5 OPB UART Lite Performance and Resource Utilization Benchmarks Virtex ll 2V1000 5 Parameter Values Device MAX Resources MHz Address C AW C_CLK_ C_BAUD C DAT C USE C ODD Flip 4 input fmax Bits in IDTH FREQ RATE A BITS PARITY PARITY Flops LUTs Decode 24 32 100 000 19 200 5 FALSE FAL
85. and have an interrupt strobe occur upon only the completion of a transfer Of course all status register bits are available for detailed information independent of the interrupt choice The reason for this option is that the interrupt module utilizes about 25 LUTs that can be eliminated if multiple interrupt functionality is www xilinx com v1 00b 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Serial Peripheral Interface SPI Design Specification XILINX sacrificed This option was implemented prior to optimizing the interrupt controller which at the time yielded much greater savings If the interrupt module is not implemented then the single interrupt condition is when the receive register or FIFO is full At this time software will not be developed utilizing the single interrupt scheme and it will be the responsibility of the user to provide software Interrupt Global Enable Descriptions A global enable is provided to globally enable or of more utility globally disable interrupts from the SPI device This bit is essentially ANDed with the input to the interrupt controller Bit assignment is shown Table 6 Unlike most other registers this bit is the MSB on the OPB This bit is read write and cleared upon reset Table 5 Interrupt Register Bit Definitions Bit assignment assumes 32 bit bus Reset Bit s Name Access Value Description 0 Interrupt Read Write 0 Interrupt Global Enable OPB bit 0 is the Gl
86. are complete Whenever this bit is negated the OPB Arbiter uses the masters IDs as their priority levels to perform bus arbitration Notes o 6 DWIDTH Reserved loge C NUM MASTERS 1 C OPB DWIDTH PID Read Write 0000 5 Parked Master ID These bits contain the 1092 NUM MASTERS ID of the master to park on if parking is OPB DWIDTH 1 OPB Arbiter parameterized to support fixed priority arbitration OPB Arbiter parameterized to support dynamic priority arbitration OPB Arbiter parameterized to not support bus parking OPB Arbiter parameterized to support bus parking The number of bits required by the PID field will vary with the number of masters supported by the OPB Arbiter A field width of 4 is shown here for the default value enabled and the Park On Master Not Last bit is set If the OPB Arbiter has been parameterized to only support fixed priority arbitration the DPE bit is setto 0 andis read only by the processor core The DPERW bit is then set to 0 and reflects the fact that the OPB Arbiter only supports fixed priority arbitration If the OPB Arbiter has been parameterized to support dynamic priority arbitration the DPE bit can be read from and written to by the processor The DPERW bit is set to 1 and reflects the fact that the priority mode of the arbiter can be controlled by the DPE bit Although the OPB Arbiter has been parameterized to support dynamic p
87. are then determined by the connection of master devices to the request grant signals The values of the Priority Registers are used in OPB arbitration whenever the PRV bit is asserted www xilinx com March 2002 1 800 255 7778 On Chip Peripheral Bus OPB Arbiter Design Specification XILINX Fixed priority arbitration for a 4 OPB Master system with combinational grant outputs is shown in Figure 8 Figure 9 shows the same system when configured with registered grant outputs with the master requests separated by an additional clock Cycles 0 1 2 3 4 5 6 7 8 9 10 LVLO Priority Reg 31 32 LVL1 Priority Reg 31 32 X LVL2 Priority Reg 31 32 X 10 LVL3 Priority Reg 31 32 X M request M request M request 0 1 2 M request 3 OPB MdGrant O 1 2 3 OPB NGrant OPB_MGrant OPB_MGrant Figure 8 Fixed Priority Arbitration Combination Grant Outputs for 4 OPB Masters Cycles 0 1 2 3 5 6 7 10 12 13 14 t5 16 17 t8 LVLO Priority Reg 31 32 Y 0 6 0 LVL1_Priority
88. be 0 The received character will be written into the receive FIFO The bit will be cleared when the status register is read 0 No parity error has occurred 1 A parity error has occurred 25 FRAME ERROR Frame Error Indicates that a frame error has occurred since the last time the status register was read Frame Error is defined as detection of a stop bit with the value 0 The receive character will be ignored and NOT written to the receive FIFO The bit will be cleared when the status register is read 0 No Frame error has occurred 1 A frame error has occurred 26 OVERUN ERROR Overrun Error Indicates that a overrun error has occurred since the last time the status register was read Overrun is when a new character has been received but the receive fifo is full The received character will be ignored and NOT written into the receive FIFO The bit will be cleared when the status register is read 0 No interrupt has occurred 1 Interrupt has occurred 27 INTR ENABLED Interrupts is enabled Indicates that interrupts is enabled 0 Interrupt is disabled 1 Interrupt is enabled 146 www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide UART Lite Specification Table 3 Status Register Continued XILINX Bits 28 Name TX FIFO FULL Description Transmit FIFO is full Indicates if the transmit FIFO is full
89. be enabled first CR 24 1 to assert SCK to the idle state prior to asserting Slave Select Note that the Master Transfer Inhibit bit CR 23 can be utilized to inhibit Master transactions until the Slave Select is asserted manually and all data registers are initialized as desired v1 00b www xilinx com 159 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX SPI Configuration Parameters OPB Serial Peripheral Interface SPI Design Specification When the above rules are followed the timing is essentially as presented for the automatic Slave Select assertion with the exception that assertion of Slave Select is under the user control and the number of bytes transferred is controlled by the user Note that the Master Transfer Inhibit can be asserted to permit loading of registers or FIFOs as needed This can be utilized before the first transaction and after any transaction that is allowed to complete Table 1 lists parameters required to be defined in configuring the SPI assembly via Platform related applications Table 1 Parameters to Configure the SPI Assembly Generator Although the OPB data bus is currently 32 bits and planned to go to only 64 bits the IPIF in the SPI assembly is parameterized to allow data bus widths less than 32 bits and up to 16 bytes This will permit use of the SPI attachment in other applications beyond CoreConnect Default Par
90. be parameterized in the EMC design to allow you to obtain an EMC that is uniquely tailored to your system This allows you to configure a design that only utilizes the resources required by your system and operates with the best possible performance The features that can be parameterized in the Xilinx EMC design are shown in Table 26 Table 26 EMC Parameters Default Feature Description Parameter Name Allowable Values Value VHDL Type Number of Memory Banks C NUM BANKS MEM 1 8 2 integer OPB Clock Period C OPB CLOCK PERIOD PS Integer number of 40000 integer picoseconds Control Register Bank Base C BASEADDR Valid Address None 9 std logic vector Address Range 9 Control Register Bank High C HIGHADDR Address range must None 4 std logic vector Address be a power of 2 and gt 1 3 Flash SRAM Base Address MEMx 2 BASEADDR Valid Address None 4 std_logic_vector x 0to7 Range Flash SRAM High Address _ 1 2 HIGHADDR Address range must std_logic_vector 0 07 be a power of 2 and lt OPB Address Space 3 OPB Data Bus Width C_OPB_DWIDTH 32 64 64 integer 114 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB External Memory Controller EMC Table 26 EMC Parameters XILINX Default Feature Description Parameter Name Allowable Values Value VHDL T
91. bit Memory using 8 IDT71V416S Parts EMC Signal Memory Device Signal BN DN Description MSB LSB MSB LSB 0 0 Data bus Mem_DQ 0 15 0 15 0 Address bus Mem A 11 28 A 17 0 Chip Enable low true MEM CEN 0 CS Output Enable low true MEM OEN OE Write Enable low true MEM WEN WE Byte Enable low true MEM BEN 0 1 BHE BLE 1 Data bus Mem 00 16 31 0 15 0 Address bus Mem A 11 28 A 17 0 Chip Enable low true MEM CEN 0 CS Output Enable low true MEM OEN OE Write Enable low true MEM WEN WE Byte Enable low true MEM BEN 2 3 BHE BLE 2 Data bus Mem DQ 32 47 0 15 0 Address bus Mem A 11 28 A 17 0 Chip Enable low true MEM CEN 0 cs Output Enable low true MEM_OEN OE Write Enable low true MEM_WEN WE Byte Enable low true MEM BEN 4 5 BHE BLE 3 Data bus Mem 00 48 63 0 15 0 Address bus Mem A 11 28 A 17 0 Chip Enable low true MEM CEN 0 CS Output Enable low true MEM OEN OE Write Enable low true MEM WEN WE Byte Enable low true MEM BEN 6 7 BHE BLE 128 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB External Memory Controller EMC XILINX Table 39 Connection to 64 bit Memory using 8 IDT71V416S Parts Continued BN 1 EMC Signal Memory Device Signal DN Description MSB LSB MSB LSB 0 Data bus Mem DQ
92. completion 11 Read interrupt registers of both master and slave SPI devices as required 12 Perform interrupt requests as required 13 Read status registers of both master and slave SPI devices as required 14 Perform actions as required or dictated by status register data Platform Platform Generator is the tool that will allow processor systems to be configured using building Generator blocks of IP Based on the configuration of the system and the IP in the system the Platform Considerations Generator tool will create the Configuration ROM CROM with information about each IP block and will set the parameters for each IP block based on the system configuration Certain system parameters will be input into Platform Generator such as the OPB clock frequency and the ratio of OPB to SCK frequencies C_OPB_SCK_RATIO which will affect system performance Platform Generator must also instantiate 3 state I O pins for SCK MOSI and MISO when the parameter C_NUM_OFFCHIP_SS BITS is non zero In addition a number of slave select bits given by C NUM OFFCHIP SS BITS must connected to 1 0 for off chip slave selection v1 00b www xilinx com 175 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Specification Exceptions Reference Documents OPB Serial Peripheral Interface SPI Design Specification Exceptions to the Motorola s M68HC11 Rev 4 0 Reference Manual A slave mode fault error interrupt was added to prov
93. debugging of application code through either software based debugging resident monitor debugging or hardware based JTAG debugging 16 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide MicroBlaze Bus Interfaces XILINX Configuration 3 Memory Interrupt Timer Controller Controller Counter Ext memory and WDT MicroBlaze CPU Core DOPB ILMB DLMB Dual Port Data side Instruction side LMB Data side LMB Other OPB Master Slave or Bridge Figure 5 Configuration 3 ILMB DOPB DLMB Purpose Use this configuration when your application code fits into the on chip BRAM but more memory may be required for data memory Critical sections of data memory can be allocated to the faster DLMB BRAM to improve your application s performance Depending on how much data memory is required the data side memory controller may not be present The data side OPB is also used for other peripherals such as UARTS timers general purpose I O additional BRAM and custom peripherals Typical Applications Data intensive controllers Small to medium state machines Characteristics This configuration allows the CPU core to operate at the maximum clock rate because of the simpler instruction side bus structure The instruction side LMB provides two cycle pipelined read access from the BRAM for an effective access rate of one instructio
94. developed OPB devices For detailed information on the IBM OPB refer to IBM s On Chip Peripheral Bus Architecture Specifications Version 2 1 OpbBus pdf The OPB is one element of IBM s CoreConnect architecture and is a general purpose synchronous bus designed for easy connection of on chip peripheral devices The OPB includes the following features 32 bit or 64 bit data bus Up to 64 bit address e Supports 8 bit 16 bit 32 bit and 64 bit slaves Supports 32 bit and 64 bit masters Dynamic bus sizing with byte halfword fullword and doubleword transfers e Optional Byte Enable support Distributed multiplexer bus instead of 3 state drivers Single cycle transfers between OPB master and OPB slaves not including arbitration Support for sequential address protocol e 16 cycle bus time out provided by arbiter e Slave time out suppress capability Support for multiple OPB bus masters e Support for bus parking Support for bus locking Support for slave requested retry Bus arbitration overlapped with last cycle of bus transfers The OPB is a full featured bus architecture with many features that increase bus performance Most of these features map well to the FPGA architecture however some can result in the inefficient use of FPGA resources or can lower system clock rates Consequently Xilinx uses an efficient subset of the OPB for Xilinx developed OPB devices However because of the flexible nature
95. disabling any hardware interrupt inputs Writing a one to this bit enables the hardware interrupt inputs and disables software generated inputs Writing a one also disables any further changes to this bit until the device has been reset Writing ones or zeros to any other bit location does nothing When read this register will reflect the state of the ME and HIE bits All other bits will read as zeros The MER is shown in the following diagram and is described in Table 21 MER Master Enable Register HIE T T Reserved ME Table 21 Master Enable Register Bits Name Description Reset Value 0 Unused Not used 0 to 3 w 2 HIE Hardware Interrupt Enable 0 0 Read SW interrupts enabled Write no effect 1 Read HW interrupts enabled Write Enable HW interrupts w 1 ME Master IRQ Enable 0 0 IRQ disabled all interrupts disabled 1 IRQ enabled all interrupts enabled March 2002 www xilinx com 107 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Simple Interrupt Controller Specification Programming the IntC This section provides an overview of software initialization and communication with an IntC Terminology The number of interrupt inputs that an IntC has is set by the C NUM INTR INPUTS generic described in Table 24 The first input is always IntO and is mapped to the LSB of the registers except IVR and MER A valid interrupt input
96. from idle denotes the start of a transfer the 68HC11 spec notes that SS N line may remain active low between successive transfers The spec text goes on to state that this format is useful in systems with a single master and single slave In the context of the 68HC 11spec transmit data is placed directly the shift register upon a write to the transmit register Hence it is the user s responsibility to insure that the data is properly loaded in the slave shift register prior to the first SCK edge Recall that in this implementation the transmit register is double buffered with the shift register therefore additional logic would be required to monitor the transmit register and asynchronously load the shift register asynchronously in the sense of SCK prior to the first shift whenever a write to the transmit register was performed In this implementation it was chosen instead to toggle the SS signal for all CPHA __ configurations and not support permitting SPISEL being held low It is required that all 55 __ signals be routed between SPI devices internally to the FPGA The result of toggling of the SS signal is a minimization of FPGA resources 156 www xilinx com v1 00b 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Serial Peripheral Interface SPI Design Specification XILINX Cycle 1 Cycle 2 Cycle 3 Cycles 4 6 Cycle 7 Cycle 8 SCK CPOL 1 5 SCK CPOL 0 N MSB 1 LSB
97. grant cycle moving the ID of the most recently granted master to the lowest Priority register and moving all other master IDs up one level of priority The dynamic priority arbitration mode operation results in an implementation of the least recently used LRU algorithm The lowest priority master ID will be March 2002 www xilinx com 77 1 800 255 7778 5 XILINX On Chip Peripheral Bus Arbiter Design Specification the one which was granted the bus most recently and the highest priority master ID will be the one which was granted the bus the least in the recent past The values to be loaded into the Priority registers are either the values written to the register from the OPB or a shift of the master ID from the next lowest Priority register In the case of the low Priority register the ID of the master last granted the bus is loaded into this register The master ID of the master granted the bus is loaded into the lowest Priority register and the IDs in all other Priority registers up to the priority of the one just granted move up one position in priority The Priority registers above the one just granted hold their master ID values A pipeline register exists between the arbitration logic and Priority Register update logic which delays the master grant signals by an additional clock Therefore if the OPB Arbiter is configured for dynamic priority arbitration and registered grant outputs the master grant signals will be outp
98. has no effect 0 WDT reset has not occurred 1 WDT reset has occurred Reset Value 29 WDS Watchdog Timer State Indicates the WDT period has expired The WDT_Reset signal will be asserted if the WDT period expires again before this bit is cleared by software Writing a 1 to this bit clears the watchdog timer state Writing a 0 to this bit has no effect 0 WDT period has not expired 1 WDT period has expired reset will occur on next expiration 30 EWDT 1 Enable Watchdog Timer Enable 1 This bit must be used in conjunction with the EWDT2 bit in the TWCSR 1 register BOTH bits must be 0 to disable the WDT 0 Disable WDT function 1 Enable WDT function 31 EWDT2 Enable Watchdog Timer Enable 2 This bit must be used in conjunction with the EWDT1 bit in the TCSRO register to disable the WDT BOTH bits must be 0 to disable the WDT This bit is READ ONLY in this register The value of EWDT2 can be modified only TWCSR1 0 WDT function is disabled 1 WDT function is enabled March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 187 XILINX OPB Timebase WDT Specification Control Status Register 1 TCSR1 Control Status Register 1 contains the second Watch Dog Timer WDT enable bit The WDT enable must be cleared in both TCSRO and TCSR2 to disable the WDT If the WDT is configured as enable once then the WDT cannot be disabled aft
99. is locked bus request and grant signals have no effect on bus arbitration The OPB master may proceed with data transfer cycles while asserting bus lock without engaging in bus arbitration and without regard to the state of the request and grant signals Grant signals will be generated if the master asserts its request signal The locked master s 82 www xilinx com March 2002 1 800 255 7778 On Chip Peripheral Bus OPB Arbiter Design Specification XILINX grant signal will be asserted in response to its request signal during valid arbitration cycles However the locked master need not assert its request or receive an asserted grant signal to control the bus The master owns the bus by virtue of asserting its bus lock signal after being granted the bus and before another valid arbitration cycle The master which asserted bus lock will retain control of the bus until bus lock is deasserted for at least one complete cycle The OPB arbiter will detect the bus lock signal and will continue to grant the bus to the current master regardless of other higher priority requests Figure 15 shows the OPB bus lock operation when the OPB Arbiter is configured for fixed priority arbitration and combinational grant outputs Figure 16 shows the OPB bus lock operation when the OPB Arbiter is configured for fixed priority arbitration and registered grant outputs Note that the bus grant signal is asserted one clock later Cycles 0
100. notice NOTICE OF DISCLAIMER Xilinx is providing this design code or information as is By providing the design code or information as one possible implementation of this fea ture application or standard Xilinx makes no representation that this implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation including but not limited to any war ranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose March 2002 www xilinx com 63 1 800 255 7778 XILINX On Chip Peripheral Bus OPB Arbiter Design Specification OPB Arbitration Protocol OPB Bus arbitration uses the following protocol 1 An OPB master asserts its bus request signal 2 The OPB Arbiter receives the request and outputs an individual grant signal to each master according to its priority and the state of the other requests 3 An OPB master samples its grant signal at the rising edge of the OPB clock In the following cycle the OPB master initiates a data transfer between the master and a slave by asserting its select signal The OPB Arbiter only issues a bus grant signal during valid arbitration cycles which are defined as either The OPB select and OPB busLo
101. occurring immediately after the active edge The third scheme shows the inactive edge occurring immediately before the active edge All three schemes are possible and should be detected by the interrupt detection circuitry without missing an interrupt or causing spurious interrupts One potential problem with edge sensitive interrupt schemes is their susceptibility to noise glitches Also it may be more difficult to remember and propagate multiple interrupts when the interrupt service routine does not handle all active interrupts In non auto vectoring interrupt designs it may be necessary for the software interrupt handler to service the highest priority interrupt and then check the status for any additional interrupts that may have arrived before returning from the interrupt handler Synchronization logic is usually necessary to avoid metastability problems with asynchronous inputs T Scheme 1 Scheme 2 Scheme 3 Interrupt Interrupt Occurs Acknowledge Figure 23 Schemes for Generating Edges Level Sensitive Interrupts In principle level sensitive interrupts are somewhat simpler to manage They are simpler to propagate when multiple sources are present and usually don t require additional synchronization logic The major problem with level sensitive interrupts stems from their inherent susceptibility to spurious interrupts and to missed interrupts due to problems that arise when trying to avoid spurious interrupts Simple Inter
102. possible contention errors All SCK MOSI and MISO pins of all devices are respectively hardwired together For all transactions a single SPI device is configured as a master and all other SPI devices on the SPI bus are configured as slaves The single master drives the SCK and MOSI pins to the SCK and MOSI pins of the slaves The uniquely selected slave device drives data out its MISO pin to the MISO master pin to realize full duplex communication The Nth bit of the SS N signal selects the Nth SPI slave with an active low signal All other __ slave devices ignore both SCK and MOSI signals In addition the non selected slaves i e SS pin high maintain their MISO pin so as to not interfere with SPI bus activities When external slave SPI devices are implemented SCK MOSI and MISO as well as the needed SS N signals are brought out to pins All signals are true 3 state bus signals and erroneous external bus activity can corrupt internal transfers when both internal and external devices are present You must insure that external pull up or pull down of external SPI 3 state signals are consistent with the sink source capability of the FPGA IO drivers Recall that the IO drivers can configured for different drive strengths as well as integral pull ups The 3 state signals for multiple external slaves can be implemented however the system designer desires but the external bus must follow the SPI 68HC11 specifications Figure 3 shows the timing
103. request 3 OPB MGrant 0 OPB MGrnt L OPB NGrant 1 OPB_MGrant 3 Figure 11 Dynamic Priority Arbitration Registered Grant Outputs 4 OPB Masters Block Diagram The block diagram for the Priority registers and the register update logic is shown in Figure 12 The gray shaded blocks represent the Priority Register update logic which is only present when the OPB Arbiter is parameterized to support Dynamic Priority arbitration 78 www xilinx com March 2002 1 800 255 7778 On Chip Peripheral Bus OPB Arbiter Design Specification XILINX shift priority reg LVLO opb m 0 3 grant p shift Priority Reg opb wrregce opb_data 0 31 E shift Iv priority hift IvI1 LVL1 SUN US Priority Reg y shift gt m i gt Ivlm_priority_r hift Iv gt 3n shift Priority Reg shift 5 E priority hift pe Vin dol Priority Reg master NUM MASTERS 2 NUM MASTERS 1 Figure 12 Priority Register Logic March 2002 www xilinx com 79 1 800 255 7778
104. signal is any signal that provides the correct polarity and type of interrupt input Examples of valid interrupt inputs are rising edges falling edges high levels and low levels hardware interrupts or software interrupts if HIE has not been set Each interrupt input can be selectively enabled or disabled masked The polarity and type of each hardware interrupt input is specified in the IntC generics C KIND OF INTR C KIND OF EDGE and KIND OF LVL see Table 24 Software interrupts do not have any polarity or type associated with them so until HIE has been set they are always valid Any valid interrupt input signal that is applied to an enabled interrupt input will generate a corresponding interrupt request within the IntC All interrupt requests are combined an OR function to form a single interrupt request output that can be enabled or disabled masked Initialization and Communication During power up or reset an IntC is put into a state where all interrupt inputs and the interrupt request output are disabled In order for the IntC to accept interrupts and request service the following steps are required 1 Eachbitin the IER corresponding to an interrupt input must be set to a one This allows the IntC to begin accepting interrupt input signals IntO has the highest priority and it corresponds to the least significant bit LSB in the IER 2 The MER must be programmed based on the intended use of the IntC There are two bits
105. support hardware multiply Bus Interconnects The data side and instruction side bus interfaces each have an interface to local memory called the Local Memory Bus or LMB and an interface to IBM s On chip Peripheral Bus OPB You can build systems that strictly adhere to a Harvard architecture or to share resources you can use a single OPB in conjunction with a bus arbiter provided as a MicroBlaze peripheral Since system requirements differ the MicroBlaze core is provided in six variations that supply only the LMB and OPB buses needed by your application March 2002 wwWwW xilinx com 1 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Preface Overview of MicroBlaze Embedded Systems The LMB bus provides guaranteed single cycle access to on chip block RAM This simple efficient single master bus protocol is ideal for interfacing to fast local memory The OPB is a 32 bit wide multi master bus that is ideal for connecting peripherals and external memory to the MicroBlaze processor core OPB Peripherals OPB peripherals complete the MicroBlaze hardware system and provide functions such as the following Watchdog timer General purpose timer counters Interrupt controller UARTs General purpose I O Memory controllers In addition you can define and add peripherals for custom functions or as an interface to a design residing in the FPGA www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Re
106. the Priority Register update logic Bus Parking When utilizing dynamic priority arbitration and the bus is parked on a particular bus master this bus master is moved to lowest bus priority In the IBM OPB Arbiter if another master requests the bus at the same time as the parked bus master the higher priority master will gain control of the bus In the Xilinx OPB Arbiter the parked bus master will gain control of the bus even though this master is at a lower priority Clock and Power Management The IBM OPB Arbiter Core supports clock and power management by gating clocks to all internal registers and providing a sleep request signal to a central clock and power management unit in the system This sleep request signal is asserted by the IBM OPB Arbiter to indicate when it is permissible to shut off clocks to the arbiter These functions are not supported in the Xilinx implementation of the OPB Arbiter therefore the following I O signal is not used e sleepReg the FPGA implementation of the OPB bus will not support sleep modes Scan Test Chains The IBM OPB Arbiter contains an internal scan chain for testing and verification purposes Xilinx FPGAs support boundary scan testing but the internal flip flops within the architecture do not provide for an internal scan chain Therefore the internal scan chain implemented in the IBM OPB Arbiter is not supported in the Xilinx implementation and the following signals are not used
107. the watchdog timer WDT remains the same across bus interface sizes March 2002 wwwW xilinx com 191 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Timebase WDT Specification 192 wwwW xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX Xilinx Embedded Processors OPB Peripherals OPB Timer Counter Specification March 2002 Summary This document describes the specifications for a timer counter core for the OPB bus This document applies to the following peripherals opb timer v1 00b Overview The TC Timer Counter is a 32 bit timer module that attaches to the OPB On chip Peripheral Bus and has the following features Features V2 0 bus interface with byte enable support Supports 32 bit bus interface Two programmable interval timers with interrupt event generation and event capture capabilities e Configurable counter width One Pulse Width Modulation PWM output Freeze input for halting counters during software debug Timer Counter Organization The TC is organized as two identical timer modules Each timer module has an associated register the Load Register that is used to hold either the initial value for the counter for event generation or a capture value depending on the mode of the timer The TC block diagram is shown in the following figure CaptureTrigO CaptureTrig1 OPB Bus TCSRO Control Status Control Sta
108. value is always written to the Load Register Subsequent capture events will update the Load Register and will overwrite the previous value whether it has been read or not counter can be set up to count either up or down bit UDT in the TCSR Pulse Width Modulation PWM Mode In PWM mode two timer counters are used as a pair to produce an output signal PWMO with a specified frequency and duty factor TimerO sets the period and Timer1 sets the high time for the PWMO output Characteristics PWM Mode has the following characteristics mode for both 0 and must be set to Generate Mode bit MDT in the TCSR set to 07 The PWMAO bit in TCSRO and PWMBO bit in TCSR1 must be set 1 to enable PWM mode GenerateOut signals must be enabled in the TCSR bit GENT set to 1 The PWMO signal is generated from the GenerateOut signals of 0 and Timer1 so these signals must be enabled in both timer counters assertion level of the GenerateOut signals for both timers in the pair must be set to 1 This is done by setting GENO ASSERT and 1 ASSERT to 1 counter can be set to count up or down Setting the PWM Period and Duty Factor The PWM period is determined by the generate value in TimerO s Load Register TLRO The PWM high time is determined by the generate value in Timer1 s Load Register TLR1 The period and duty factor are calcu
109. will not necessarily receive a valid grant signal Other OPB masters with higher bus priority may request the OPB and will be granted the bus according to OPB arbiter priority If an OPB master device needs a non interruptible sequence of bus cycles it can use the bus lock signal for this purpose Bus locking is described later in this document The OPB Arbiter supports both dynamic priority arbitration implementing a Least Recently Used LRU algorithm and fixed priority arbitration both are described in more detail later in this document Figure 5 shows multiple bus request or overlapped bus arbitration when the OPB arbiter is using fixed priority arbitration and combinational grant outputs Both OPB Master 1 and OPB Master 2 simultaneously request the bus Master 1 has a higher priority and is granted the bus During cycle 2 Master 1 completes its first transaction and Master 2 is granted the bus for cycle 3 Thus during cycle 2 the arbitration for the bus is overlapped with a data transfer This overlapped bus arbitration improves the bandwidth of the bus March 2002 www xilinx com 65 1 800 255 7778 XILINX On Chip Peripheral Bus OPB Arbiter Design Specification Cycles 0 1 2 3 4 5 6 7 8 M request 1 y M request 2 NS om m OPB_MGrant 2 LZ OPB_select M1 select M2 select
110. xferAck OPB TC Transfer Acknowledge CaptureTrigO Ext Capture Trigger 0 CaptureTrig1 Ext 1 GenerateOutO Ext Generate Output 0 GenerateOut1 Ext Generate Output 1 PWMO Ext Pulse Width Modulation Output 0 Interrupt Ext Interrupt Freeze Ext Freeze Count Value MPD File Parameters The opb timer mpd Microprocessor Peripheral Definition file contains a list of the peripheral s parameters that are fixed at FPGA configuration time The parameters are described in the following table Table 6 MPD Parameters Parameter FAMILY Description FPGA family one of virtex virtexe virtex2 virtex2p spartan2 or spartan2e Type string C COUNT WIDTH The width in bits of the counters in the OPB integer range 8 to 32 attached to the peripheral C ONE TIMER 0 Two timers are present integer ONLY 1 One timer is present No PWM mode C TRIGO ASSERT 0 CaptureTrigO input is low true std logic 1 CaptureTrigO input is high true C COUNT WIDTH The width in bits of the counters integer C TRIG1 ASSERT 70 CaptureTrig1 input is low true std logic 1 CaptureTrig1 input is high true C GENO ASSERT 0 GenerateOutO output is low true std logic 1 GenerateOutO output is high true C GEN1 ASSERT 0 GenerateOut1 output is low true std logic 1 GenerateOut1 output is high true C OPB AWIDTH The width i
111. 0 0011 halfword rD 16 23 rD 24 31 00 1100 halfword rD 16 23 rD 24 31 00 1111 word rD 0 7 rD 8 15 rD 16 23 rD 24 31 Note that other OPB masters may have more restrictive requirements for byte lane placement than those allowed by MicroBlaze OPB slave devices are typically attached left justified with byte devices attached to the most significant byte lane and halfword devices attached to the most significant halfword lane The MicroBlaze steering logic fully supports this attachment method www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide MicroBlaze Bus Interfaces XILINX Implementation Parameterization The following characteristics of the MicroBlaze bus interface can be parameterized Data Interface options OPB only LMB OPB Instruction Interface options LMB only LMB OPB OPB only March 2002 wwWwW xilinx com 31 MicroBlaze Hardware Reference Guide 1 800 255 7778 5 XILINX MicroBlaze Bus Interfaces 32 wwwW xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide XILINX 2002 Summary Overview Xilinx OPB Usage Xilinx Embedded Processors OPB Peripherals OPB Usage in Xilinx FPGAs This document describes how to use the IBM On chip Peripheral Bus OPB in Xilinx FPGAs This document provides guidelines and simplifications for efficient FPGA implementations and the subset of signals used in Xilinx
112. 0 255 7778 MicroBlaze Hardware Reference Guide OPB Simple Interrupt Controller Specification XILINX Programming Register Data Types and Organization Model All IntC registers are accessed through the OPB bus interface The base address for these registers is provided by a configuration parameter For an OPB IntC each register is accessed on a 4 byte boundary offset from the base address regardless of the width of the registers providing conformance to the OPB IPIF register location convention Since OPB addresses are byte addresses OPB IntC register offsets are located at integral multiples of four from the base address Table 13 illustrates the registers and their offsets from the base address for an OPB IntC Normally an OPB IntC is configured to be a 32 bit 16 bit or an 8 bit OPB peripheral that corresponds to the width of the processor data bus width Figure 26 shows the address offsets and alignment for the OPB IntC for these three bus widths The IntC registers are read as big endian data The bit and byte labeling for big endian data types is shown in Figure 25 Byte label Byte significance MSByte LSByte Halfword Bit significance MSBit LSBit Byte significance MSByte Byte Bit significance MSBit LSBit Figure 25 Data Types March 2002 www xilinx com MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Simple Interrupt Controller Specification
113. 001 X 0010 X 0100 X 1000 x 0011 X X 1100 X X 1111 X X X X 26 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide MicroBlaze Bus Interfaces 5 XILINX Data Write 0 31 The write data bus is an output from the core and contains the data that is written to memory It becomes valid when AS is high and goes invalid in the clock cycle after Ready is sampled high Only the byte lanes specified by Byte Enable 0 3 contain valid data AS The address strobe is an output from the core and indicates the start of a transfer and qualifies the address bus and the byte enables It is high only in the first clock cycle of the transfer after which it goes low and remains low until the start of the next transfer Read Strobe The read strobe is an output from the core and indicates that a read transfer is in progress This signal goes high in the first clock cycle of the transfer and remains high until the clock cycle after Ready is sampled high If a new read transfer is started in the clock cycle after Ready is high then Read Strobe remains high Write Strobe The write strobe is an output from the core and indicates that a write transfer is in progress This signal goes high in the first clock cycle of the transfer and remains high until the clock cycle after Ready is sampled high If a new write transfer is started in the clock cycle after Ready is high then Write Strobe remains high Data Read 0 31 The re
114. 1 or the master IDs if PRV 0 n C NUM MASTERS 1 m C NUM MASTERS 2 The prioritized request signals are then input into the priority encoder which determines which priority grant is asserted i e grant IvlO grant grant and grant lvln The prioritized grant signals are then input to the Assign Grants block to determine which master s grant signal is asserted based on the priority of that master again determined by examination of the master IDs in the Priority Registers if PRV 1 or the master IDs if PRV 0 The master s priority code selects the appropriate prioritized grant signal to be output to that master These intermediate grant signals are then registered if the OPB Arbiter is configured to support dynamic priority arbitration to reduce the number of logic levels between the arbitration logic and the Priority Register update logic Since the Priority Register update logic is not present when the OPB Arbiter is not configured to support dynamic priority arbitration these pipeline registers are not necessary and therefore are not present in the design The arbitration logic also contains the logic for detecting valid arbitration cycles which is input to the Park Lock logic Valid arbitration cycles are defined as when either the OPB select signal is deasserted indicating no data transfer is in progress or when OPB XferAck is asserted indicating the final cycle in a data transfer and OPB busLock is not asserted 80
115. 13 LMB Generic Read Operation 28 www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide MicroBlaze Bus Interfaces Back to Back Write Operation Typical LMB access 2 clocks per write Addr Byte Enable Data Write AS Read Strobe Data Read Ready XILINX X 1 l X _ BEO BE1 _ X D X Bi LX R3 cp 7 9 Figure 14 LMB Back to Back Write Operation Single Cycle Back to Back Read Operation Typical I side access 1 clock per read Addr 1 2 Byte Enable BEO X 1 BE Data Write Read Strobe EY i i _ Write Strobe Data Read Y DO Di i D2 y Ready UN 15 LMB Single Cycle Back to Back Read Operation Back to Back Mixed Read Write Operation Typical D side timing Addr X Rh Byte Enable BEO X X Data Write DO Read Strobe _ Write Strobe Data Read x Di X Ready gan NN 16 Back to Back Mixed Rea
116. 142 5 970 372 5 971 595 5 973 506 5 978 260 5 986 958 5 990 704 5 991 523 5 991 788 5 991 880 5 991 908 5 995 419 5 995 744 5 995 988 5 999 014 5 999 025 6 002 282 and 6 002 991 Re 34 363 Re 34 444 and Re 34 808 Other U S and foreign patents pending Xilinx Inc does not represent that devices shown or products described herein are free from patent infringement or from any other third party right Xilinx Inc assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made Xilinx Inc will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user Xilinx products are not intended for use in life support appliances devices or systems Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited Copyright 1991 2002 Xilinx Inc All Rights Reserved MicroBlaze Hardware Reference Guide www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide The following table shows the revision history for this document Version Revision 10 15 01 1 9 Initial MDK MicroBlaze Development Kit release 1 14 02 2 1 2 1 release 3 02 2 2 2 2 release 2002 www xilinx com MicroBlaze Hardware Reference Guide 1 800 255 7778 MicroBlaze Hardware Reference Guide www xilinx
117. 3 Configuration 1 OPB ILMB DOPB DLMB Purpose Use this configuration when your application requires more instruction and data memory than is available in the on chip block RAM BRAM Critical sections of instruction and data memory can be allocated to the faster ILMB BRAM to improve your application s performance Depending on how much data memory is required the data side memory controller may not be present The data side OPB is also used for other peripherals such as UARTS timers general purpose I O additional BRAM and custom peripherals The OPB to OPB bridge is only required if the data side OPB needs access to the instruction side OPB peripherals such as for software based debugging Typical Applications MPEG Decoder Communications Controller e Complex state machine for process control and other embedded applications e Set top boxes Characteristics Because of the extra logic required to implement two buses per side the maximum clock rate of the CPU may be slightly less than configurations with one bus per side This configuration allows debugging of application code through either software based debugging resident monitor debugging or hardware based JTAG debugging March 2002 www xilinx com 15 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX MicroBlaze Bus Interfaces Configuration 2 Memory OPB to OPB Memory Interrupt Timer Controller Bridge Controller Controller Co
118. 5 aze 6 tex2 microblaze 1 tex2 microblaze 2 tex2 microblaze 3 tex2 microblaze 4 tex2 microblaze 5 tex2 microblaze 6 edf edf edf edf edf edf edf edf edf edf edf edf edf edf edf edf edf edf edf edf edf edf edf edf 60 www xilinx com 1 800 255 7778 2002 MicroBlaze Hardware Reference Guide Microprocessor Peripheral Definition Format Peripheral Analyze Order PAO File moved to the hdl directory Comments XILINX A PAO Peripheral Analyze Order file is supplied by the IP provider and supplies information to the Platform Generator This file contains a list of HDL files that are needed for synthesis and defines the analyze order for compilation The value of the STYLE option in the MPD file determines whether or not a PAO file is required The HDL files used for synthesis must be You can insert comments in the PAO file without disrupting processing The following are guidelines for inserting comments Format Use the following format Precede comments with the pound sign Comments can continue to the end of the line Comments can be anywhere on the line lib library name hdl file basename Library name specifies the unique library for the peripheral and HDL file names are specified without a file extension All names are in lower case If your peripheral requires a certain version of a library then the library name is given with the version appen
119. 5 Multiple Bus Requests Fixed Priority Arbitration Combinational Grant OULD UG eT 64 March 2002 www xilinx com vii MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Figure 6 Multiple Bus Requests Fixed Priority Arbitration Registered Grant Outputs emet eerie 64 Figure 7 OPB Arbiter Top level Block 73 Figure 8 Fixed Priority Arbitration Combination Grant Outputs for 4 OPB Masters 75 Figure 9 Fixed Priority Arbitration Registered Grant Outputs for 4 OPB Masters 75 Figure 10 Dynamic Priority Arbitration Combinational Grant Outputs 4 OPB nennen 76 Figure 11 Dynamic Priority Arbitration Registered Grant Outputs 4 OPB Masters 76 Figure 12 Priority Register Logle ener teen rigen 77 Figure 13 Arbitration LOGIC pere er tercie cete 78 Figure 14 Park Lock Logic enero tere iion e e i dr tiae 80 Figure 15 Bus Locking Fixed Priority Combinational Grant Outputs 81 Figure 16 Bus Locking Fixed Priority Registered Grant 222 22 2 81 Figure 17 Bus Parking Fixed Priority Arbitration Combinational Grant Outputs 82 Figure 18 Bus Parking Dynamic Priority Arbitration Registered Grant Outputs 82 Figure 19 Bus Parking on Master Not Last Fixed Priority Arbitration Combinational Grant eene 83 Figure 20 Bus Parking o
120. 752 035 5 754 459 5 758 192 5 760 603 5 760 604 5 760 607 5 761 483 5 764 076 5 764 534 5 764 564 5 768 179 5 770 951 5 773 993 5 778 439 5 781 756 5 784 313 5 784 577 5 786 240 5 787 007 5 789 938 5 790 479 5 790 882 5 795 068 5 796 269 5 798 656 5 801 546 5 801 547 5 801 548 5 811 985 5 815 004 5 815 016 5 815 404 5 815 405 5 818 255 5 818 730 5 821 772 5 821 774 5 825 202 5 825 662 5 825 787 5 828 230 5 828 231 5 828 236 5 828 608 5 831 448 5 831 460 5 831 845 5 831 907 5 835 402 5 838 167 5 838 901 5 838 954 5 841 296 5 841 867 5 844 422 5 844 424 5 844 829 5 844 844 5 847 577 5 847 579 5 847 580 5 847 993 5 852 323 5 861 761 5 862 082 5 867 396 5 870 309 5 870 327 5 870 586 5 874 834 5 875 111 5 877 632 5 877 979 5 880 492 5 880 598 5 880 620 5 883 525 5 886 538 5 889 411 5 889 413 5 889 701 5 892 681 5 892 961 5 894 420 5 896 047 5 896 329 5 898 319 5 898 320 5 898 602 5 898 618 5 898 893 5 907 245 5 907 248 5 909 125 5 909 453 5 910 732 5 912 937 5 914 514 5 914 616 5 920 201 5 920 202 5 920 223 5 923 185 5 923 602 5 923 614 5 928 338 5 931 962 5 933 023 5 933 025 5 933 369 5 936 415 5 936 424 5 939 930 5 942 913 5 944 813 5 945 837 5 946 478 5 949 690 5 949 712 5 949 983 5 949 987 5 952 839 5 952 846 5 955 888 5 956 748 5 958 026 5 959 821 5 959 881 5 959 885 5 961 576 5 962 881 5 963 048 5 963 050 5 969 539 5 969 543 5 970
121. 76 Priority Registers 74 Program Counter PC 7 programmer registers 94 R read steering 30 Register Data Types and Organization 97 Register Definitions 88 Registered grant outputs 64 retry 41 S Scalable Datapath 57 Scan Test Chains 89 Serial Peripheral Interface 151 Set Interrupt Enables SIE 95 104 Simple IntC Registers 98 Simple Interrupt Controller 91 Special Purpose Registers 7 SPI 151 Status Register STATREC 145 208 StrataFlash 129 130 131 T target word first 41 TBWDT TimeBase WatchDog Timer 183 TC Timer Counter 193 Timebase Operation 188 Timebase Register TBR 186 timebase wdt mpd Microproces sor Peripheral Definition 190 timeout 41 timer mpd Microprocessor Periph eral Definition 203 TYPE 46 47 Type instructions 4 Type B instructions 4 U UART Lite 143 V variable burst 41 Watchdog Timer 86 WDT timeout interval 183 write steering 30 Z Controller 133 Zilog Z80 92 222 www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide
122. 8 OPB Arbiter LVLn Priority Register Bit Definitions eee 72 Table 9 OPB Arbiter FPGA Performance and Resource Utilization Benchmarks Virtex II 5 Poets eine 85 Table 10 OPB Arbiter Register Block 85 Table 11 OPB Arbiter Device Capabilities Bit Definitions 2 5 85 Table 12 Xilinx OPB Arbiter I O Signal Variations 86 OPB Simple Interrupt Controller Specification Table 1 IntC Registers and Base Address 97 Table 2 Interrupt Status 98 Table 3 Interrupt Pending Register 7 cios eene 99 Table 4 Interrupt Enable Register eee eene en nnn 100 Table 5 Interrupt Acknowledge Register eee 101 Table 6 Set Interrupt Enables retener repre ter teer ien 102 Table 7 Clear Interrupt Enables certet mette ritenere sinn 103 Table 8 Interrupt Vector Register 104 9 Master Enable Register isisisi 105 Table 10 Core IntC Summary eounoceuieeei reete iet iic 107 Table 11 OPB IntC Summary 107 Table 12 Generics Parameters Common to all IntC Instantiations 108 Table 13 Generics Parameters for an OPB IntC 2 5 see 109 OPB External Memory Controller EMC Table 1 EMC Parameters acce pereo aee neret 112
123. Address Bus OPB BE 0 C OPB DWIDTH 8 1 OPB OPB Byte Enables OPB 0 OPB DWIDTH 1 OPB Data Bus OPB RNW OPB OPB Read Not Write OPB select OPB OPB Select OPB OPB Sequential Address MemCon 0 OPB DWIDTH 1 OPB O Memory Controller Data Bus MemCon errAck OPB O Memory Controller Error Acknowledge MemCon retry OPB O Memory Controller Retry MemCon toutSup OPB O Memory Controller Timeout Suppress MemCon xferAck OPB O Memory Controller Transfer Acknowledge Mem STS 0 C NUM BANKS 1 IP Core Memory Status Signal Mem 0 MEM WIDTH 1 IP Core Memory Input Data Bus Mem DQ O 0 C MEM WIDTH 1 IP Core O Memory Output Data Bus Mem DQ T IP Core O Memory Output 3 state Signal Mem A 0 C OPB AWDITH 1 IP Core O Memory Address Bus Mem RPN IP Core O Memory Reset Power Down Mem CEN 0 C NUM BANKS MEM 1 IP Core O Memory Chip Enables Mem OEN IP Core O Memory Output Enable Mem WEN IP Core O Memory Write Enable Mem QWEN 0 C MEM WIDTH 8 1 IP Core O Memory Qualified Write Enables Mem BEN 0 C MEM WIDTH 8 1 IP Core O Memory Byte Enables OPB Timing This section describes the basic read and write timing for the OPB For detailed descriptions refer to the IBM OPB Specification v2 0 An OPB cycle is initiated with a master request The highest priority request is granted the bus and in the next cycle the master asserts the bus select signal and begins the transf
124. BT Controller provides an interface between the OPB and external ZBT memories The controller supports OPB data bus widths of 32bits and memory subsystem widths of 32 bits This controller supports the OPB V2 0 byte enable architecture OPB ZBT To allow you to obtain an ZBT Controller that is uniquely tailored for your system certain Controller features can be parameterized in the ZBT Controller design This allows your to configure a P t design that only utilizes the resources required by your system and operates with the best arameters possible performance The features that can be parameterized in the Xilinx ZBT Controller design are shown in Table 1 Table 1 ZBT Controller Parameters Default Feature Description Parameter Name Allowable Values Value VHDL Type ZBT Memory Base Address C BASEADDR Valid Address std logic vector Range 2 ZBT Memory Address Width C ZBT ADDR SIZE 2 31 17 integer Implement ZBT Clock C EXTERNAL DLL 0 Do implement 0 integer synchronization 1 Do not implement Notes 1 Address range specified by C BASEADDR must be a power of 2 2 No default value is specified for C BASEADDR to insure that the actual value is set if the value is not set a compiler error is generated These generics must be a power of 2 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers as listed at http www xilinx com legal htm
125. BT Memory Control signal ZBT CE1 N IP Core ZBT Memory Select signal ZBT CE2 N IP Core ZBT Memory Select signal ZBT CE2 IP Core ZBT Memory Select signal ZBT RW N IP Core ZBT Memory Read Write signal ZBT A 0 C ZBT ADDR SIZE 1 IP Core ZBT Memory Address ZBT BW N 0 3 IP Core ZBT Memory Byte Enable ZBT IO 1 0 31 IP Core ZBT Memory Input Data Bus ZBT IO O 0 31 IP Core ZBT Memory Output Data Bus ZBT IO T IP Core ZBT Memory Output 3 state Signal ZBT IOP 1 1 4 IP Core ZBT Memory Input Parity Data Bus ZBT O 1 4 IP Core ZBT Memory Output Parity Data Bus ZBT T IP Core ZBT Memory Output Parity 3 state Signal 134 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB ZBT Controller Design Specification XILINX Connecting to The following table shows how to connect a ZBT controller and SAMSUNG K7N163601M Memory OC15 512kword x 32 The ZBT controller does not support sleep mode burst mode parity checking or parity generating Table 3 Signal Connection SAMSUNG ZBT Controller K7N163601M OC15 ZBT A 0 19 0 19 ZBT CLK ZBT CKE N CKE ZBT RW WE ZBT ADV LD N ADV ZBT OE N OE ZBT CE1 N CS1 ZBT 10 24 31 DQA 0 7 ZBT 10 16 23 DQB 0 7 ZBT 10 8 15 DQC 0 7 ZBT 10 0 7 DQD 0 7 ZBT BW N 4 BWA ZBT BW N 2 BWB ZBT BW N 1 BWC ZBT BW N 0 BWD Need to be tied to VCC C
126. DT errAck OPB TBWDT Error Acknowledge TBWDT retry OPB TBWDT Retry TBWDT toutSup OPB TBWDT Timeout Suppress TBWDT xferAck OPB TBWDT Transfer Acknowledge WDT Reset Ext Watchdog Timer Reset Asserted upon second expiration of the WDT timeout interval Timebase Interrupt Ext Timebase Rollover Interrupt Asserted as one clock period wide pulse upon rollover of the timebase from OxFFFFFFFF to 0x00000000 Interrupt Ext Watchdog Timer Interrupt Goes high and stays high until the WDS bit is cleared in the TWCSRO register March 2002 www xilinx com 189 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Timebase WDT Specification MPD File Parameters The opb timebase wdt mpd Microprocessor Peripheral Definition file contains a list of the peripheral s parameters that are fixed at FPGA configuration time The parameters described in the following table Table 7 MPD Parameters the peripheral Parameter Description Type INTERVAL Indicates the exponent for setting the integer length of the WDT interval WDT interval 2C WDT INTERVAL x ENABLE __ Indicates WDT enable behavior integer ONCE 0 WDT can be repeatedly enabled and disabled via software 1 WDT can only be enabled once no disable possible after initial enable C OPB AWIDTH The width of the address bus attached integer to the peripheral C OPB DWIDTH The width of t
127. F CSET attribute C BASEADDR OxFFFFDO000 CSET signal Irq Interrupt CSET signal Int int periph CSET signal _ 1 sys clk SELECT SLAVE opb zbt controller CSET attribute HW VER 1 00 a CSET attribute INSTANCE myzbtl CSET attribute C BASEADDR OxFF800000 CSET attribute C HIGHADDR OxFF8000FF CSET attribute C ZBT ADDR SIZE 17 CSET signal 2 Clk FB ZBT FB CSET signal ZBT ZBT CSET signal ZBT OE N ZBT OE N CSET signal ZBT ADV LD N ZBT ADV LD N CSET signal 2 LBO N ZBT LBO CSET signal ZBT ZBT CSET signal ZBT CE2 N ZBT CE2 N CSET signal ZBT CE2 ZBT CE2 CSET signal ZBT RW N ZBT RW N CSET signal ZBT CKE ZBT CSET signal ZBT A ZBT A CSET signal ZBT BW N ZBT BW N CSET signal ZBT IO ZBT IO CSET signal ZBT IOP ZBT IOP CSET signal OPB sys clk SELECT MASTER microblaze CSET attribute HW VER 1 00 a CSET attribute INSTANCE microblazel CSET attribute CONFIGURATION 1 CSET signal Interrupt Interrupt CSET signal Clk sys_clk CSET attribute C LM HIGHADDR 0x00007fff CSET attribute C LM BASEADDR 0x00000000 END March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 45 XILINX Microprocessor Hardware Specification MHS Format MHS Peripheral Peripherals defined in the MHS can have the following options
128. GA device family This attribute is automatically populated by the Platform Generator Format CSET attribute C FAMILY family string Where the family is spartan2 virtex virtexe or virtex2 C BASEADDR Attribute The BASEADDR attribute defines the base address of the peripheral This attribute is not populated by the Platform Generator Format CSET attribute C BASEADDR base std logic vector 0 to 31 Where base is a hexadecimal value C HIGHADDR Attribute The C HIGHADDR attribute defines the base address of the peripheral This attribute is not populated by the Platform Generator Format CSET attribute C HIGHADDR high std logic vector 0 to 31 Where high is a hexadecimal value C NUM MASTERS Attribute The C NUM MASTERS attribute defines the number of masters in the system This attribute is automatically populated by the Platform Generator Format CSET attribute C NUM MASTERS num integer www xilinx com 53 1 800 255 7778 XILINX MPD Signal Naming Conventions Microprocessor Peripheral Definition Format Where num is an integer value C NUM SLAVES Attribute The NUM SLAVES attribute defines the number of slaves in the system This attribute is automatically populated by the Platform Generator Format CSET attribute C NUM SLAVES num integer Where num is an integer value C NUM INTR INPUTS Attribute The NUM INTR INPUTS attribute defines the number
129. I O are configured as integer inputs results in lower resource utilization if only inputs are needed 0 I O are programmable as input or output 1 All I O are inputs Parameterization The following characteristics of the GPIO can be parameterized Base address for the GPIO registers Width of OPB data bus attached to the peripheral Width of OPB address bus attached to the peripheral Number of GPIO bits I Os input only or programmable as input or output www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX March 2002 Summary Overview Xilinx Embedded Processors OPB Peripherals OPB Timebase WDT Specification This document describes the specifications for a 32 bit free running timebase and watchdog timer core for the OPB bus This document applies to the following peripherals timebase v1 00a The TBWDT TimeBase WatchDog Timer is a 32 bit peripheral that attaches to the OPB On chip Peripheral Bus and has the following features Features OPB V2 0 bus interface with byte enable support Supports 32 bit 16 bit and 8 bit bus interfaces Watchdog timer WDT with selectable timeout period and interrupt Configurable WDT enable enable once or enable disable e One 32 bit free running timebase counter with rollover interrupt Timebase WDT Organization The TBWDT block diagram is shown in the following figure Control
130. ID is contained in the Park Master ID PMID field of the OPB Arbiter Control Register This master s grant signal will be asserted during valid arbitration cycles when no other master s request signal is asserted Figure 19 shows bus parking on the 84 www xilinx com March 2002 1 800 255 7778 On Chip Peripheral Bus OPB Arbiter Design Specification XILINX master specified in the Control Register for a 4 OPB master system when the OPB Arbiter is parameterized for fixed priority arbitration and combinational grant outputs Cycles 0 1 2 3 4 5 6 7 8 9 10 OPBCIk Control register 0 31 0011 10000000000000000000000000000 LVLO Priority Reg 31 32 00 LVL1 Priority Reg 31 32 X 01 LVL2 Priority Reg 31 32 10 Priority Reg 31 32 X 11 M request 0 MW seater M_request 2 M request 3 OPB MGrant 0 OPB MGrant 1 f IN OPB MGrant 2 OPB MGrant 3 Figure 19 Bus Parking on Master Not Last Fixed Priority Arbitration Combinational Grant Outputs Park on Last Master When bus parking is enabled bit PEN 1 in the OPB Arbiter Control Register and C PARK 1 and Park on Master Not Last is negated bit PMNL 0 in the OPB Arbiter Control Register the bus will be parke
131. IDTH Flops LUTs Decode 24 32 210 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX Appendix A MicroBlaze Endianness This chapter describes big endian and little endian data objects and how to use little endian data with the big endian MicroBlaze soft processor This chapter includes the following sections e Origin of Endian Definitions Bit Naming Conventions e Data Types and Endianness VHDL Example Origin of Endian The terms Big Endian and Little Endian come from Part I Chapter 4 of Jonathan Swift s Gulliver s Travels Here is the complete passage from the edition printed in 1734 by George Faulkner in Dublin our Histories of six Thousand Moons make no Mention of any other Regions than the two great Empires of Lilliput and Blefuscu Which two mighty Powers have as I was going to tell you been engaged in a most obstinate War for six and thirty Moons past It began upon the following Occasion It is allowed on all Hands that the primitive Way of breaking Eggs before we eat them was upon the larger End But his present Majesty s Grand father while he was a Boy going to eat an Egg and breaking it according to the ancient Practice happened to cut one of his Fingers Whereupon the Emperor his Father published an Edict commanding all his Subjects upon great Penalties to break the smaller End of their Eggs The Peop
132. Instruction Decode Register File Instruction Buffer 32 X 32b Figure 1 MicroBlaze Core Block Diagram 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers as listed at http www xilinx com legal htm other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 www xilinx com 13 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX MicroBlaze Bus Interfaces MicroBlaze bus interfaces are available in six configurations as shown in the following figure Figure 2 MicroBlaze Bus Configurations The optimal configuration for your application depends on code size and data spaces and if you require fast access to internal block RAM The performance implications and supported memory models for each configuration is shown in the following table Table 1 MicroBlaze Bus Configurations Core Debug Configuration Fmax available Memory Models Supported 1 IOPB ILMB DOPB DLMB 110 SW JTAG Large external instruction memory Fast internal instruction memory BRAM Large external data memory Fast internal data memory BRAM 2 IOPB DOPB DLMB 125 SW JTAG Large external instruction memory Large external data memory Fast internal data memory BRAM 3 ILMB DOPB DLMB 125 SW JTAG Fast internal instruction memory BRAM Large external dat
133. K 0 CSET attribute C PROC INTRFCE 0 CSET attribute C REG GRANTS CSET signal OPB Clk sys cl ll p SELECT SLAVE opb timer CSET attribute HW VER 1 00 a CSET attribute INSTANCE mytimerl CSET attribute C HIGHADDR OxFFFFAOFF CSET attribute C BASEADDR OxFFFFAO000 CSET signal CaptureTrigO0 CaptureTrig0O CSET signal CaptureTrigl CaptureTrigl CSET signal CompareOut0O CompareOutO0 CSET signal CompareOutl CompareOut1 CSET signal PWMO PWMO CSET signal OPB_Clk sys_clk 44 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Microprocessor Hardware Specification MHS Format XILINX CSET signal Interrupt int_periph PRIORITY 2 SELECT SLAVE opb_gpio CSET attribute HW_VER 1 00 a CSET attribute INSTANCE mygpiol CSET attribute C HIGHADDR OxFFFFCOFF CSET attribute C BASEADDR OxFFFFCOO00 CSET signal GPIO IO External IO CSET signal OPB Clk sys clk END SELECT SLAVE opb intc CSET attribute HW VER 1 00 a CSET attribute INSTANCE myintcl CSET attribute C HIGHADDR OxFFFFDOF
134. K SPISEL o SS 0 o SS 1 359 bd Figure 2 Multi master Configuration Block Diagram Slave only devices which not shown only SPISEL 154 local slave select port and do not have SS N remote slave select port The SCK signal is driven by the SPI Master controlling the bus and regulates the flow of data The master must be configured at the time of system configuring to transmit data at a one of four baud rates The 68HC11 SPI specification prescribes baud rate selection via bits in the control register however in this FPGA implementation the baud rate is selected via a parameter that fixes the baud rate at the time of system configuration The FPGA permits reconfiguration by resetting the parameters and rebuilding the system This approach was adopted to reduce FPGA resource requirements One bit of data is transferred per SCK clock period Data is shifted on one edge of SCK and is sampled on the opposite edge when the data is stable Consistent with the 68HC11 SPI specification selection of clock polarity and a choice of two fundamentally different clocking protocols on an 8 bit oriented data transfer is possible via bits in the control register www xilinx com v1 00b 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Serial Peripheral Interface SPI Design Specification XILINX The clock phase and polarity or idle state can be modified for SPI data tran
135. LD Rd Rb 100110 Rd 10100 Rb 00000000000 PC PC Rb Rd BRA Rb 100110 00000 01000 Rb 00000000000 PC Rb BRAD Rb 100110 00000 11000 Rb 00000000000 PC Rb BRALD Rd Rb 100110 Rd 11100 Rb 00000000000 PC Rb Rd PC BRK Rd Rb 100110 Rd 01100 Rb 00000000000 PC Rb Rd MSR BIP 1 BEQ Ra Rb 100111 00000 Rb 00000000000 if Ra 0 PC PC Rb BNE Ra Rb 100111 00001 Ra Rb 00000000000 if Ra 0 PC PC Rb BLT Ra Rb 100111 00010 Ra 00000000000 if lt 0 PC PC Rb Ra Rb 100111 00011 Rb 00000000000 if Ra lt 0 PC PC Rb 100111 00100 Rb 00000000000 if Ra gt 0 PC PC Rb 100111 00101 Rb 00000000000 if gt 0 PC PC Rb BEQD 100111 10000 00000000000 if Ra 0 PC PC Rb BNED 100111 10001 Rb 00000000000 if 0 PC PC Rb BLTD Ra Rb 100111 10010 Ra 00000000000 if Ra lt 0 PC Rb BLED Ra Rb 100111 10011 Ra Rb 00000000000 if Ra lt 0 PC PC Rb BGTD Ra Rb 100111 10100 00000000000 if gt 0 PC Rb BGED 100111 10101 00000000000 if Ra gt 0 PC PC Rb ORI Rd Ra Imm 101000 Rd Ra Imm Rd Ra or s Imm ANDI Rd Ra Imm 101001 Rd Ra Imm Rd Ra and s Imm XORI Rd Ra Imm 101010 Rd Ra Imm Rd Ra xor s Imm
136. LL TOINT ENITO ARHTO GENTO MDTO 2 2 2 i 2 T T T T T PWMAO ENTO LOADO CAPTO UDTO Table 3 Control Status Register 0 TCSRO Bits Name Description Reset Value 0 20 Reserved 21 ENALL Enable Timers 0 0 No effect on timers 1 Enable all timers counters run This bit is mirrored in all control status registers and is used to enable all counters simultaneously Writing a 1 to this bit sets ENALL ENTO and Writing a 0 to this register clears ENALL but has no effect on ENTO and 198 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Timer Counter Specification Table 3 Control Status Register 0 TCSRO Continued XILINX Bits 22 Name PWMAO Description Enable Pulse Width Modulation for 0 0 Disable pulse width modulation 1 Enable pulse width modulation PWM requires using TimerO and Timer1 together as a pair TimerO sets the period of the PWM output and Timer1 sets the high time for the PWM output For PWM Mode and MDT1 must be 0 and C GENO and GEN1 ASSERT must be 1 Reset Value 0 23 TINTO TimerO Interrupt Indicates that the condition for an interrupt on this timer has occurred If the timer mode is capture and the timer is enabled this bit indicates a capture has occurred If the mode is generate this bit indicates the counter has rolled over Mus
137. MHS file syntax is case insensitive however signal and attribute names are case sensitive Attribute settings in the MHS file have priority over the equivalent attribute setting in the Microprocessor Peripheral Definition MPD file Refer to the Microprocessor Peripheral Definition Format document for more information on MPD file syntax Comments You can insert comments in the MHS file without disrupting processing Comments begin with a pound sign and continue to the end of the line Peripheral Type There are two types of peripherals e master Slave Peripheral names are in lower case Use the following format at the beginning of a peripheral definition SELECT peripheral type peripheral name Use the following format for a master peripheral SELECT master peripheral name Use the following format for a slave peripheral SELECT slave peripheral name Assignment Type There are two types of assignments attribute Signal Use the following format for assignment statements CSET assignment type name valu 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers as listed at http www xilinx com legal htm other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 www xilinx com 43 MicroBlaze Hardware R
138. MicroBlaze Hardware Reference Guide March 2002 XILINX The Xilinx logo shown above is a registered trademark of Xilinx Inc ASYL FPGA Architect FPGA Foundry NeoCAD NeoCAD EPIC NeoCAD PRISM NeoROUTE Timing Wizard TRACE XACT XILINX XC2064 XC3090 XC4005 XC5210 and XC DS501 are registered trademarks of Xilinx Inc The shadow X shown above is a trademark of Xilinx Inc All XC prefix product designations A K A Speed Alliance Series AllianceCORE BITA CLC Configurable Logic Cell CoolRunner CORE Gen erator CoreLINX Dual Block EZTag FastCLK FastCONNECT FastFLASH FastMap Fast Zero Power Foundation HardWire IRL LCA LogiBLOX Logic Cell LogiCORE LogicProfessor MicroBlaze MicroVia MultiLINX NanoBlaze PicoBlaze PLUSASM PowerGuide Power Maze QPro RealPCl RealPCl 64 66 Selectl O SelectRAM SelectRAM Silicon Xpresso Smartguide Smart IP SmartSearch Smartspec SMARTSwitch Spartan TrueMap UIM VectorMaze VersaBlock VersaRing Virtex WebFitter WebLINX WebPACK XABEL XACTstep XACTstep Advanced XACTstep Foundry XACT Floorplanner XACT Performance XAM XAPP X BLOX X BLOX plus XChecker XDM XDS XEPLD Xilinx Foundation Series XPP XSI and ZERO are trademarks of Xilinx Inc The Programmable Logic Company and The Pro grammable Gate Array Company are service marks of Xilinx Inc other trademarks are the property of their respective owners Xilinx Inc doe
139. MicroBlaze Hardware Reference Guide OPB Serial Peripheral Interface SPI Design Specification XILINX Design Implementation Target Technology The intended target technology is a Virtex Il FPGA Device Utilization and Performance Benchmarks This section will be updated when the design has been completed It will contain the resources and timing for various values of the parameters Since the SPI Assembly is a module that will be used with other design pieces in the FPGA the utilization and timing numbers reported in this section are just estimates As the SPI Assembly is combined with other FPGA designs the utilization of FPGA resources and timing of the SPI Assembly will vary from the results reported here In order to analyze the SPI timing within the FPGA a design was created that instantiated the SPI Assembly with registers on all of the SPI ports This allowed a constraint to be placed on the clock net for the SPI Assembly to yield more realistic timing results Using this method the clock frequency register to register varied from 110 125 MHz depending on the actual place and route of the design in the FPGA The SPI Assembly benchmarks are shown in Table 15 for a Virtexll 5 FPGA Table 15 SPI Assembly FPGA Performance and Resource Utilization Benchmarks Virtexll 5 Parameter Values For Example Device Resources 2 GEN3 4 Slices Slice 4 input MAX CMB REG F
140. O E E CURTIS EH ERE DEED 149 UART Parameters ese inertes et e e yr ades 149 JTAG_UART UO Signale 150 UART Address Map and Register 151 Register Data Types and Organization 1 sss 151 Registers ofthe UAR ierre titer etin ther terit 151 The Control register contains the control of the JTAG UART 153 Address M 153 Design nplemgbnlaliOD 154 Device Utilization and Performance Benchmarks sess 154 ce ee A 155 0 nre 155 155 SPI Device 155 A 156 SPI 157 SPI Configuration on eco a lente bodie 163 SPI Assembly VO Signals d ode pbi FE madi 164 Port and Parameter Dependencies sss 166 SPI Register tob reet erede use i CHA QE 166 SPI Interrupt Registers enses tee sr ss 167 SPLAssembly Reset Descriptions cere netten
141. OPB OPB Read Not Write OPB select OPB OPB Select seqAddr OPB OPB Sequential Address GPIO DBus 0 31 OPB GPIO Data Bus GPIO errAck OPB GPIO Error Acknowledge GPIO retry OPB O GPIO Retry GPIO toutSup OPB O GPIO Timeout Suppress GPIO xferAck OPB GPIO Transfer Acknowledge GPIO 00 31 Ext General Purpose Input Outputs Number of I O bits is configurable at FPGA configuration direction of each I O bit is programmable at run time March 2002 www xilinx com 181 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX 182 OPB General Purpose Input Output GPIO Specification MPD File Parameters The opb gpio mpd Microprocessor Peripheral Definition file contains a list of the peripheral s parameters that are fixed at FPGA configuration time The parameters are described in the following table Table 7 MPD Parameters Parameter Description Type C OPB AWIDTH Width of the address bus attached to integer the peripheral OPB DWIDTH Width of the data bus attached to the integer peripheral BASEADDR Indicates the base address of this std logic vector peripheral expressed as a 0 to AWIDTH 1 std logic vector HIGHADDR Indicates the highest address occupied std logic vector by this peripheral expressed as a standard logic vector 0 to AWIDTH 1 C GPIO WIDTH Width of the GPIO bus number of integer GPIO bits used C_ALL_INPUTS Indicates that all
142. OPB usage that apply primarily to mixed systems Notes e Conversion cycles are only required when a master generates a transfer request to a slave that is larger than the slave s width and the slave is capable of indicating that it March 2002 www xilinx com 39 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Usage in FPGAs accepted a smaller transfer than the master requested hence requiring with a conversion cycle e Byte enable masters cannot directly generate conversion cycles They require a conversion cycle generator in the Byte Enable Interface BEIF device This is because byte enable masters do not receive any size information in the acknowledge from the slave Byte enable slaves cannot cause generation of conversion cycles A consequence of this is that any master accessing a byte enable slave can only transfer data up to the size of the slave Transfers larger than the slave size will result in either 1 no response from the slave time out 2 an errAck from the slave or 3 lost data the actual result depends on how the decode and acknowledge logic is implemented in the slave e Conversion cycle generator logic in BEIF is required only for byte enable device to legacy OPB V2 0 device transfers Write mirroring and read steering in the V2 1 specification is based on left justified peripherals A more complex slave attachment can be used instead of left justification OPB The f
143. PHERALS opb_peripherals lt ip gt simmodels PC The netlist and simmodels directories can have their own underlying directory structure because the BBD file manages the relative file locations However the directories must mirror each other Each file is listed with the file extension of the hardware implementation netlist Since implementation netlists have multiple file extensions such as edn edf edo ngo it is important to identify the format For simulation the Platform Generator uses the file extension vhd for VHDL simulation and v for Verilog BBD Example The following is an example BBD file C FAMILY CONFIGURATION FIL virtex virtex virtex virtex virtex virtex Spartan2 Spartan2 Spartan2 Spartan2 Spartan2 Spartan2 virtexe virtexe virtexe virtexe virtexe virtexe vir vir Vir vir vir vir tex2 tex2 tex2 tex2 tex2 tex2 1 Pr C Por vir vir vir vir vir vir vir vir vir vir vir vir vir vir vir vir vir vir vir vir vir vir vir vir ES tex microbl tex microbl tex microbl tex microbl tex microbl tex microbl tex microbl tex microbl tex microbl tex microbl tex microbl tex microbl tex microbl tex microbl tex microbl tex microbl tex microbl tex microbl aze 1 aze 2 aze 3 aze 4 aze 5 aze 6 aze 1 aze 2 aze 3 aze 4 aze 5 aze 6 aze 1 aze 2 aze 3 aze 4 aze
144. Q0 LVL1 Priority Reg 31 32 01 10 11 00 01 LVL2 Priority Reg 31 32 X10 iX 100 X L0 0 LVL3 Priority Reg 31 32 X 11 X 00 X 01 X 10 X 11 M request 0 jf bu M request 1 L 0p pp LN M request 2 M request 3 OPB MGrant 0 OPB MNMGrant 1 OPB_MGrant 2 OPB MGrant 3 Figure 18 Bus Parking Dynamic Priority Arbitration Registered Grant Outputs When the grant outputs are registered the parked master s grant will assert once negate and then stay asserted This allows the internal arbitration state machine a clock cycle to check if OPB select is asserted before parking This case occurs when a request from a master is aborted but the grant is in the internal pipeline When PARK 1 bus parking is enabled or disabled by the value of the Park Enable control bit in the OPB Arbiter Control Register see Table 6 The bus can either be parked on the master who was last granted the bus or on a specified master as indicated by the Park Master ID bits in the OPB Arbiter Control Register If bus parking is not desired the park logic can be eliminated by setting PARK O Park on Master Not Last When bus parking is enabled bit PEN 1 in the OPB Arbiter Control Register and C PARK 1 and Park on Master Not Last is selected bit PMNL 1 in the OPB Arbiter Control Register the bus will be parked on the master whose
145. R ENABLED Interrupts is enabled Indicates that interrupts is enabled 0 Interrupt is disabled 1 Interrupt is enabled 28 TX FIFO FULL Transmit FIFO is full Indicates if the transmit FIFO is full 0 Transmit FIFO is not full 1 Transmit FIFO is full 29 TX FIFO EMPTY Transmit FIFO is empty Indicates if the transmit FIFO is empty 0 Transmit FIFO is not empty 1 Transmit FIFO is empty 30 RX FIFO FULL Receive FIFO is full Indicates if the receive FIFO is full 0 Receive FIFO is not full 1 Receive FIFO is full 31 RX FIFO VALID DAT A Receive FIFO is has valid data Indicates if the receive FIFO has valid data 0 Receive FIFO is empty 1 Receive FIFO has valid data www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide OPB JTAG UART Specification XILINX Control Register CTRL REG The Control register contains the control of the JTAG_UART Table 4 Control Register CTRL REG Bits Name Description Reset Value 0 26 Reserved Not used 27 ENABLE INTR Enable Interrupt for the JTAG_UART 0 0 Disable interrupt signal 1 Enable interrupt signal 28 29 Reserved Not used 0 30 RST_RX_FIFO Reset Clear the receive FIFO 0 When written to with a 1 the receive FIFO is cleared 0 Do nothing 1 Clear the receive FIFO 31 RST TX FIFO Reset Clear the transmit FIFO 0 When written to with a 1 the transmit FIFO is cleared 0 Do n
146. RNW SI2 timeout DOPB select 512 toutSup Present for Bus Monitor functions DOPB SI2 xferAck g IOPB_wrDBus 0 31 IOPB_DBus 0 31 OPB rdDBus 031 OR IOPB ABus 0 31 Slave2 IOPB BE 0 3 multi SI2 rdDBus 0 31 gt IOPB busLock gt ported 512 errAck gt IOPB wrDBus 0 31 5 2 retry gt IOPB ABus 0 31 IOPB RNW gt Sl2_timeout gt IOPB_BE 0 3 IOPB select SI2 toutSup gt IOPB busLock IOPB d Sl2_xferAck gt IOPB wrDBus 0 31 IOPB rdDBus 0 31 IOPB RNW IOPB select IOPB rdDBus 0 31 IM ABus 0 31 a IOPB segAddr IOPB errAck gt IM BE 0 3 gt IOPB errAck IOPB ret IM busLock IOPB retr OPB timeout MicroBlaze g OR OPB timeout IOPB xferAck Instr OPB IM RNW like IOPB toutSup Interface IM select A IOPB xferAck IM segAddr IOPB q IOPB MGrant IM request ii Instruction side OPB Figure 11 OPB Interconnection with multi ported slave and no bridge March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 25 XILINX MicroBlaze Bus Interfaces LMB Bus Definition The Local Memory Bus LMB is a synchronous bus used primarily to access on chip block RAM It uses a minimum number of control signals and a simple protocol to ensure that local block RAM is accessed in a single clock cycle LMB signals and definitions are shown in the following table All LMB signals are high true Table
147. S2 Need to be tied to GND CS2 Need to be tied to GND ZZ Need to be tied to GND LBO Address The generic C_ZBT_ADDR_SIZE specifies the number of address signals to the ZBT memory Mapping Since all accesses are word the generic specifies the number of address bits for word accesses For example 512 KWord memory needs 19 address bits 2719 512288 The address decoding uses OPB_A 0 to 29 C_ZBT_ADDR_SIZE and the generic C_BASEADDR to determine if the OPB access is to the ZBT memory March 2002 www xilinx com 135 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Timing Diagrams 136 OPB ZBT Coniroller Design Specification read uses five OPB clock cycles to complete and a write uses 2 OPB clock cycles The write is faster because pipelining is used for the ZBT controller and the ZBT memories Figure 1 shows a simple read access Figure 2 shows two successive writes to illustrate the write pipelining OPB CIk OPB ABus OPB RNW OPB DBus OPB XferAck ZBT A ZBT CE ZBT RW N ZBT IO OPB CIk OPB ABus OPB RNW OPB DBus OPB XferAck ZBT A ZBT CE ZBT RW N ZBT IO Figure 1 Read Cycle www xilinx com 1 800 255 7778 2 3 4 5 6 Addres
148. SE 48 88 000 24 32 100 000 19 200 6 FALSE FALSE 49 92 000 24 32 100 000 19 200 7 FALSE FALSE 50 95 000 24 32 100 000 19 200 8 FALSE FALSE 51 100 000 24 32 40 000 38 400 8 FALSE FALSE 49 97 158 000 24 32 100 000 19 200 6 TRUE FALSE 57 108 137 000 24 32 100 000 19 200 7 TRUE FALSE 57 108 137 000 March 2002 www xilinx com 149 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB UART Lite Specification 150 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX 2002 Summary Introduction Intellectual Property Specification OPB Peripherals OPB Serial Peripheral Interface SPI Design Specification This document presents specifications for the VHDL implementation of Motorola s Serial Peripheral Interface SPI in a Xilinx FPGA The original specifications closely followed Motorola s M68HC11 Rev 4 0 Reference Manual and this document emphasizes the M68HC 11 specifications However the design was enhanced with a number of exceptions and enhancements as described in this document The default mode of operation has been changed to a manual slave select operation not included in the M68HC11 specification This document applies to the following peripherals opb spi v1 00b The Serial Peripheral Interface SPI is a full duplex synchronous channel that supports a four wire interface receive transmit clock and slave sel
149. SPI state machine in order to perform a SPI transfer This can occur only when the SPI device is in slave mode All zeros are loaded in the shift register and transmitted by the slave in an under run condition 27 DRR Full Read Write 1 to clear Data Receive Register FIFO Full Interrupt 27 is the Data Receive Register Full interrupt Without FIFOs this bit is set at the end of a SPI byte transfer by a one clock period strobe to the interrupt register With FIFOs this bit is set at the end of the SPI byte transfer when the receive FIFO has been filled by a one clock period strobe to the interrupt register 26 DRR Over run Read Write 1 to clear Receive Register FIFO Over run Interrupt 26 is the Receive FIFO over run interrupt This bit is set by a one clock period strobe to the interrupt register when an attempt to write data to a full receive register or FIFO is made by the SPI state machine in order to complete a SPI transfer This can occur when the SPI device is in either master or slave mode 25 Tx FIFO Near Empty Read Write 1 to clear Transmit FIFO Less Than or Equal to Half Empty Interrupt 25 is the Transmit FIFO near empty interrupt This bit is set by a one clock period strobe to the interrupt register when the occupancy value is decremented from 1000 to 0111 Note that 0111 means there are 8 characters in the FIFO to be transmitted This interrupt exists only i
150. Signal Options Option Values Default Definition PRIORITY integer X Interrupt priority TYPE INTERNAL EXTERNAL Scope of signal EXTERNAL PRIORITY Option Use the PRIORITY option to set the priority of an interrupt signal CSET signal Interrupt interrupt bus PRIORITY num The highest priority is 1 The num value is the priority of the interrupt signal among all interrupts 46 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Microprocessor Hardware Specification MHS Format XILINX TYPE Option Use the TYPE option to set the scope of a signal CSET signal signal name connection TYPE type value The type value is either EXTERNAL or INTERNAL By default only OPB and signals are defined as INTERNAL All other signals are defined as EXTERNAL Design This section provides general design considerations Considerations T Defining Memory Size Memory sizes are based on C BASEADDR and HIGHADDR settings Use the following format when defining memory size CSET attribute C HIGHADDR OxFFFFOOFF CSET attribute C BASEADDR 0 0000 All memory sizes must be 2 where n is a positive integer and 2 boundary overlaps are not allowed Defining Local Memory Size Local Memory LM size is based on C LM BASEADDR and LM HIGHDADDR settings and only predefined sizes of LM are allowed Otherwise MUX stages must be
151. Signals eese ener nennen nnn 164 Table 3 Port and Parameter Dependencies for Slave Attachment 166 Table 4 SPI Assembly Registers and Offset from 167 Table 5 Interrupt Register Bit Definitions Bit assignment assumes 32 bit bus 168 Table 6 Interrupt Register Bit Definitions Bit assignment assumes 32 bit bus 169 Table 7 SPI Control Register Bit Definitions Bit assignment assumes 32 bit bus 171 Table 8 SPI Status Register Bit Definitions Bit assignment assumes 32 bit bus 172 Table 9 SPI Data Transmit Register Bit Definitions Bit assignment assumes 32 bit ee eee nen 174 Table 10 SPI Data Receive Register Bit Definitions Bit assignment assumes 32 bit 174 Table 11 SPI Slave Select Address Register Bits Bit assignment assumes 32 bit 174 Table 12 Transmit FIFO Occupancy Register Bits Bit assignment assumes 32 bit eee eene een 175 Table 13 Receive FIFO Occupancy Register Bits Bit assignment assumes 32 bit 175 March 2002 www xilinx com xiii MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Table 14 SPI Assembly FPGA Performance and Resource Utilization Benchmarks Virtex lI 5 tee eret imer ree rb e d eec 176 OPB General Purpose Input Output GPIO Specification Table 1 GPIO Configuration and Access 180 Table 2 GPIO Register Address Map 32 bit esses 180 Ta
152. Slave retry O Slave retry OPB 10 Slave toutSup Slave timeout suppress OPB 15 Slave xferAck Slave transfer acknowledge OPB 14 lt gt ABus 0 31 address bus OPB 11 lt gt BE OPB byte enable OPB 16 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 37 XILINX Legacy OPB Devices Table 3 Summary of OPB Master Slave Device I O Continued OPB Usage in Xilinx FPGAs Page Signal yo Description in Ref 1 lt gt RNW read not write OPB 12 nOPB select OPB select OPB 12 lt gt OPB sequential address OPB 13 Notes on the signal sets Xilinx developed OPB devices do not support dynamic bus sizing and therefore do not use the following legacy signals Mn dwXfer Mn fwXfer Mn hwXfer dwAck fwAck and hwAck Since Xilinx developed OPB devices are byte enable only the beXfer and beAck signals are not required and so are not used The signals required for masters and slaves are separate from the signals present in the OPB interconnect The OPB interconnect the OR gates and other logic required to connect OPB devices supports the full OPB V2 1 specification i e all signals are present Thus the OPB interconnect does not limit a design to byte enable devices and supports designs in which a mix of byte enable legacy and OPB V2 0 devices are present
153. The bit and byte labeling for the big endian data types is shown in Figure 30 Byte address n 1 2 3 n 4 5 6 7 Byte label 0 1 2 3 4 5 6 7 Word Byte significance MSB LSB Bitlabel 0 63 Bit significance MSBit LSBit Byte address n n 1 n 2 n 3 Byte label 0 1 2 3 Word Byte significance MSByte LSByte Bit label 0 31 Bit significance MSBit LSBit Byte address n nei Byte label 0 1 Halfword Byte significance MSByte LSByte Bit label 0 15 Bit significance MSBit LSBit Byte address Byte label 0 Byte Byte significance MSByte Bit label 0 7 Bit significance MSBit LSBit Figure 30 Big Endian Data Types 120 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB External Memory Controller EMC XILINX Figure 31 depicts the Memory Control Block Diagram implemented in the EMC Host Bus PLB or OPB IPIF Bus Interface External Bus Memory Controller Input Output Registers Control Address Read Data Write Data Page Address Data Steering muxin Detection Decode Control Signal Wait State Generation Generation Device Interconnect MEMORY BANKS 0 TO 7 Figure 31 EMC Memory Control Block Diagram March 2002 www xilinx com 121 MicroBlaze Hardware Reference Guide 1 800 255 7778
154. The bus interconnect will not limit the use of any feature of the V2 1 specification Although byte enable devices are the preferred and most efficient OPB devices in Xilinx devices some designs may also use legacy OPB devices or fully V2 0 compliant devices However a legacy device cannot communicate directly with a byte enable device because they use different signal sets An interface layer between the byte enable device and the legacy device is required This interface is called the Byte Enable Interface BEIF device 38 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Usage in Xilinx FPGAs XILINX Mixed Systems The system shown below represents a design with a mix of byte enable legacy and OPB V2 0 devices The BEIF device converts the legacy type signals to byte enable type signals and vice versa OPB V2 0 OPB V2 0 Legacy Legacy OPB Bus Master Slave Master Slave Monitor or test only BEIF BEIF BEIF BEIF BEIF OPB OPB Arbiter Byte Enable Byte Enable Byte Enable Byte Enable PLB to OPB Master1 Master2 Slave Slave2 Bridge Figure 2 OPB Interconnect with Mixed Device Types The BEIF device contains the following logic not all of which must be used in all situations Signal translation for byte enable device to legacy device transfers Master BE is translated to the appropriate Master hwXfer Master fwXfer and Master dwXfer lt gt is transla
155. Xilinx Embedded Processors MicroBlaze MicroBlaze Bus Interfaces This document describes the Local Memory Bus LMB and On chip Peripheral Bus OPB interfaces The MicroBlaze core is organized as a Harvard architecture with separate bus interface units for data accesses and instruction accesses Each bus interface unit is further split into a Local Memory Bus LMB and IBM s On chip Peripheral Bus OPB The LMB provides single cycle access to on chip dual port block RAM The OPB interface provides a connection to both on and off chip peripherals and memory Features The MicroBlaze bus interfaces include the following features e OPB V2 0 bus interface with byte enable support see IBM s 64 Bit On Chip Peripheral Bus Architectural Specifications Version 2 0 LMB provides simple synchronous protocol for efficient block RAM transfers e LMB provides guaranteed performance of 125 MHz for local memory subsystem The block diagram in Figure 1 depicts the MicroBlaze core with the bus interfaces defined as follows DOPB Data interface On chip Peripheral Bus DLMB Data interface Local Memory Bus BRAM only Instruction interface On chip Peripheral Bus ILMB Instruction interface Local Memory Bus BRAM only Core Miscellaneous signals Clock Reset Interrupt Instruction side Data side bus interface bus interface Add Sub P Counter Shift Logical Multiply
156. _Logic n a OPB seqAddr in OPB sequential address enable Std Logic n a toutSup out IntC timeout suppress Std Logic n a IntC_retry out IntC retry request Std_Logic n a Parameterization The following characteristics of the IntC are parameterizable Base address for the Simple IntC registers and the upper address of the memory space occupied by the IntC C_BASEADDR C_HIGHADDR Edge or level sensitivity on interrupt inputs as well as the polarity KIND OF INTR C KIND OF EDGE C KIND OF LVL Edge pulse or level IRQ generation and the polarity of the IRQ output IRQ IS LEVEL IRQ ACTIVE March 2002 www xilinx com 109 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Simple Interrupt Controller Specification Address bus width OPB AWIDTH e Bus interface Normally 8 bit 16 bit 32 bit data widths for the OPB IntC DWIDTH number of interrupt inputs is parameterizable up to the width of the data bus C NUM INTR INPUTS presence of the IPR HAS presence of the SIE and CIE C HAS SIE C HAS CIE e The presence of the IVR HAS IVR Table 24 lists the top level generics parameters that are common to all variations of an IntC Table 24 Generics Parameters Common to all IntC Instantiations Generic Name Description Type Valid Values C FAMILY Target FPGA family type not String spartan2 spa
157. a between the two buses swap the data and address bytes Interface Between BRAM and MicroBlaze library IEEE use IEEE std logic 1164 all entity OPB BRAM is generic BASEADDR std logic vector 0 to 31 000 0000 C NO BRAMS natural 4 be 4 8 16 32 only C VIRTEXII boolean true port Global signals OPB Clk in std logic OPB Rst in std logic OPB signals OPB ABus in std logic vector 0 to 31 OPB BE in std logic vector 0 to 3 OPB RNW in std logic OPB select in std logic OPB seqAddr in std logic OPB DBus in std logic vector 0 to 31 OPB BRAM DBus out std logic vector 0 to 31 OPB BRAM errAck out std logic BRAM retry out std logic OPB BRAM toutSup out std logic OPB BRAM xferAck out std logic March 2002 www xilinx com 215 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Appendix Appendix A MicroBlaze Endianness OPB BRAM signals other port BRAM in std logic BRAM Addr in std logic vector 0 to 31 BRAM WE in std logic vector 0 to 3 BRAM Write Data std logic vector 0 to 31 BRAM Read Data out std logic vector 0 to 31 end entity OPB BRAM architecture IMP of OPB BRAM is BRAM Component Declaration little endian component RAMB16 S9 S9 port DIA in std logic vector 7 downto 0 DIB in std logic vector 7 downto 0
158. a counter was implemented which permits the simultaneous setting of status bits and interrupts for both master and slave SPI devices It is noted that in the case of an external SPI slave device SCK can be asynchronous with the internal clock of the external slave device hence this vhdl design cannot be used with external slaves that do not utilize the OPB clock When the SPI assembly is configured with FIFOs and a series of consecutive SPI 8 bit character transfers are performed status bits and interrupts do indicate completion of the first SPI and the last The only way to monitor when intermediate transfers are completed is to monitor the receive FIFO occupancy number There is also an interrupt when the transmit FIFO is less than half full Complete details on interrupts is discussed in a later section Optional FIFOs One option to the system designer via Platform Generator is to include FIFOs in the SPI assembly as shown in Figure 1 Since SPI is full duplex both transmit and receive FIFOs are instantiated as a pair When FIFOs are implemented the slave select address is required to be the same for all data buffered in the FIFOs This is required because a FIFO for the slave select address is not implemented Both transmit and receive FIFOS are 16 bytes deep and are accessed via single OPB transactions since burst mode is not supported The transmit FIFO is write only When data is written in the FIFO the occupancy number is incremented an
159. a memory Fast internal data memory BRAM 4 IOPB ILMB DOPB 110 JTAG for ILMB Large external instruction memory memory Fast internal instruction memory SW for IOPB Large external data memory memory 5 125 SW JTAG Large external instruction memory Large external data memory 6 ILMB DOPB 125 JTAG Fast internal instruction memory Large external data memory 1 ILMB memory can debugged via a software resident monitor if the second port of the dual ported ILMB BRAM is connected to an OPB BRAM memory controller See Figure 6 and Figure 8 14 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide MicroBlaze Bus Interfaces XILINX Typical Peripheral Placement This section provides typical peripheral placement and usage for each of the six configurations Because there are many options for interconnecting a MicroBlaze system you should use the following examples as guidelines for selecting a configuration closest to your application Configuration 1 Memory OPB to OPB Memory Interrupt Timer Controller Bridge Controller Controller Counter Ext memory Ext memory and WDT MicroBlaze CPU Core Data side OPB IOPB DOPB ILMB DLMB Dual Port B Block RAM Instruction side OPB Instruction side LMB Data side LMB Other OPB Master Slave or Bridge Figure
160. a single byte to the designated output device The function inbyte is used to read a singe byte from the designated input device Format SELECT IP peripheral name INBYTE boolean value OUTBYTE boolean value Where boolean value is either TRUE or FALSE Refer to the MicroBlaze Libraries documentation for more information Signals defined in the MPD file can have the following options Table 3 MPD Signal Options Option Values Default Definition BUS string X Bus ownership of a signal EDGE RISING X Interrupt edge sensitivity FALLING ENABLE MULTI SINGLE 3 state enable control SINGLE ENDIAN BIG BIG Endianess LITTLE INITIALVAL GND Driver value on unconnected inputs GND LEVEL HIGH X Interrupt level sensitivity LOW TYPE INTERNAL EXTERNAL Scope of signal EXTERNAL BUS Option The bus ownership of a signal is specified by the BUS option Format CSET signal IOPB timeout OPB timeout in BUS bus label Where the bus is a string www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Microprocessor Peripheral Definition Format XILINX Black Box Description BBD File EDGE Option The edge sensitivity of an interrupt signal is specified by the EDGE option Format CSET signal Interrupt out EDGE edge value TYPE INTERNAL Where edge value is RISING or FALLING ENABLE Option 3 state sig
161. able Platform Generator uses a search priority mechanism to locate peripherals as follows 1 Search current directory 2 Search XIL MYPERIPHERALS opb peripherals UNIX or X IL_MYPERIPHERALS opb_peripherals PC 3 Search MICROBLAZE hw coregen UNIX or MICROBLAZE hw coregen PC The first two search areas 1 and 2 have the same underlying directory structure The third search area has the CORE Generator directory structure For search areas 1 and 2 the peripheral name is the name of the root directory From the root directory the underlying directory structure is as follows 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 www xilinx com 49 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX 50 Microprocessor Peripheral Definition Format data hdl netlist simmodels For example if the XIL MYPERIPHERALS environment is set then the MPD BBD and PAO files are found in the following location XIL_MYPERIPHERALS opb_peripherals lt peripheral gt data UNIX XIL_MYPERIPHERALS opb_peripherals lt peripheral gt data PC The VHDL files are found in the following location XIL_MYPERIPHERALS opb_peripherals lt peripheral gt
162. actual address of the service routine The UIC does not support vector generation for the non critical interrupts relying instead on the interrupt vector generation mechanism within the 405 core This mechanism is similar to a hard vector except that the vector used is programmable by the software Simple IntC The interrupt controller described in this document is intended for use in a hard vector interrupt system It does not directly provide an auto vectoring capability However it does provide a vector number that can be used in a software based vectoring scheme Basic terminology and pros and cons of edge and level sensitive inputs are described in the remainder of this section The functionality of the IntC is described in the sections that follow March 2002 www xilinx com 93 MicroBlaze Hardware Reference Guide 1 800 255 7778 5 XILINX OPB Simple Interrupt Controller Specification Edge Sensitive Interrupts Figure 23 illustrates the three main types of edge generation schemes using rising edges for the active edge in this example In all three schemes the device generating the interrupt provides an active edge and some time later the generator produces an inactive edge in preparation for generating a new interrupt request In the first scheme the inactive edge is depicted as occurring when the interrupt is acknowledged This is identical to generating a level sensitive interrupt The second scheme shows the inactive edge
163. ad data bus is an input to the core and contains data read from memory Data Read 0 31 is valid on the rising edge of the clock when Ready is high Ready The signal is an input to the core and indicates completion of the current transfer and that the next transfer can begin in the following clock cycle It is sampled on the rising edge of the clock For reads this signal indicates the Data Read 0 31 bus is valid and for writes it indicates that the Data Write 0 31 bus has been written to local memory CIk All operations on the LMB are synchronous to the MicroBlaze core clock March 2002 www xilinx com 27 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX LMB Bus Operations The following diagrams provide examples of LMB bus operations Generic Write Operation Addr Byte Enable Data Write AS Read Strobe Write Strobe Data Read Ready MicroBlaze Bus Interfaces X Cum N DO 1 Mr Figure 12 LMB Generic Write Operation Generic Read Operation Addr Byte Enable Data Write AS Read Strobe Write Strobe Data Read Ready 1X 1 X um 1111 Ey EET 00 ED Figure
164. al If you have only optimized hardware netlists you must specify the BLACKBOX value within the MPD file In this case only the BBD file is read by the Platform Generator If you have a mix of optimized hardware netlists and HDL files you must specify the MIX value within the MPD file In this case the PAO and BBD files are read by the Platform Generator If you have only HDL files you must specify the HDL value within the MPD file In this case only the PAO file is read by the Platform Generator Format SELECT IP peripheral name STYLE value Where value is BLACKBOX MIX or HDL The default value is HDL March 2002 www xilinx com 57 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX MPD Signal Options 58 Microprocessor Peripheral Definition Format EDIF Option In hierarchal mode this option directs the Platform Generator to write an EDIF file for the peripheral In flatten mode the EDIF option is ignored since the entire system is synthesized to an EDIF file Format SELECT IP peripheral name EDIF TRUE INBYTE or OUTBYTE Option The INBYTE and OUTBYTE options indicate that the peripheral can act as an input or output device respectively These options indicate to the Library Generator libgen that the peripheral has the peripheral name inbyte inbyte peripheral name outbyte and outbyte functions defined The function outbyte is used to write
165. allowed The actual number is limited by the performance that is desired NOTICE XILINX IS PROVIDING THIS DESIGN CODE OR INFORMATION AS IS BY PROVIDING THIS DESIGN CODE OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE APPLICATION OR STANDARD XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers as listed at http www xilinx com legal htm other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 www xilinx com 151 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Serial Peripheral Interface SPI Design Specification SPI Device Features Four signal interface MOSI MISO SCK and SS SS bit for each slave on the SPI bus Three signal in out in out 3 state for implementing 3 state SPI device in outs to support multi master configu
166. ameter Allowed value to Constraint and Group Label Feature generic Name Values GUI VHDL type OPB G1 Platform Builder C DEV BLK ID See Platform 4 type integer assigned device ID Builder number specification G2 Enable Disable C DEV MIR ENABL non zero 0 type integer Model ID register E included zero not included G3 Base address for C BASEADDR Vector of None type assembly IPIF and length std logic vector SPI module OPB AWID TH G4 Permits alias of C HIGHADDR C BASEADD C BASE type address space by R any 2 n 1 ADDR std logic vector ki h a Default value in GUI assumes C IP REG BAR O FFSET X60 G5 Include interrupt C INTERRUPT PRE non zero Set to 1 type integer module required for SENT included zero multiple interrupt Disabled Drivers require this to be 1 see text conditions Possible future option G6 OPB address bus C OPB AWIDTH 32 type integer width Includes bits for byte addressing G7 OPB databus width C OPB DWIDTH 32 type integer SPI G8 Both receive and C FIFO EXIST non zero 1 i e type integer transmit FIFOs included zero included not included 160 www xilinx com v1 00b 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Serial Peripheral Interface SPI Design Specification Table 1 Parameters to Configure the SPI Assembly 5 XILINX
167. ance Bit label Bit significance n n 1 n 2 n 3 0 1 2 3 MSByte LSByte 0 31 MSBit LSBit n n 1 0 1 Half word MSByte LSByte 0 15 MSBit LSBit n 0 MSByte 0 7 MSBit LSBit Figure 2 Big Endian Data Types Registers of the GPIO Information on the registers used in assembly language programming are described in this section GPIO DATA GPIO TRI March 2002 MicroBlaze Hardware Reference Guide Figure 3 GPIO Register Set www xilinx com 1 800 255 7778 GPIO Data Register GPIO Three state Register Word 179 XILINX OPB General Purpose Input Output GPIO Specification Address Map Table 3 GPIO Register Address Map 32 bit OPB Address Register Hex Size Type Description GPIO DATA 0x00 Word R W GPIO Data Register GPIO TRI 0x04 Word R W GPIO Three state Register GPIO Data Register GPIO_DATA Description 1 GPIO DATA Table 4 GPIO DATA Register Bits Name Description Reset Value 0 31 GPIO DATA GPIO Data 0 For programmed as inputs R reads value on input pin W no effect For I O programmed as outputs R reads value in GPIO data register W writes value to GPIO data register and output pin GPIO Three state Register GPIO_TRI Description 0 31 1 GPIO TRI Table 5 GPIO TRI Register Bits Name Description Reset Val
168. ant signals which are sent to the OPB master devices during valid arbitration cycles as shown in Figure 14 The OPB Arbiter can be parameterized to register the master grant signals by setting the parameter C REG GRANTS to 1 Grant Last locked 0 n __ Register Lock Logic OPB buslock gt OPB_MGrani 0 n M request 0 n park enable Grant Logic p Park Logic park_master_notlast gt park master id gt grant 0 n arb cycle C NUM MASTERS 1 Figure 14 Park Lock Logic Grant Last Register The Grant Last Register holds the state of the grant outputs from the last request grant arbitration cycle This information is used to determine which master currently has control of the bus to implement bus locking and park on last master parking Lock Logic If an OPB master asserts the bus lock signal upon assuming control of the bus the OPB arbiter will continue to grant the OPB to the master which locked the bus Bus lock signals from all attached masters are ORed together to form OPB busLock which is an input to the OPB Arbiter When OPB busLock is asserted bus arbitration is locked to the last granted master as indicated by the Grant Last register All other master Grant outputs are gated off and will not be asserted regardless of the state of the Request inputs or the programmed priorities When the OPB bus
169. arch 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX bebe quia iie LR 124 amp 2 M M 125 Connecting to Intel StrataFlash sss eee nennen nnns 127 M 128 Example d ies 129 OPB Block RAM BRAM Specification 131 SUMMA 131 OV OT VLC Wee ette eet 131 NER ERU AA 131 1 0 131 OPB BRAM V O Signals uad oa vin a 132 Programming Model aac dh oett bie 132 Supported Memory Sizes eene ripetere eei p e iE eerie Poets 132 Register Data Types and Organization 133 OPB ZBT Controller Design Specification 135 SUMMAT E 135 VOR V1 CW ies oie e ope rr bae bae ini tens 135 Cad 135 Piscis H 135 OPB ZBT Controller Parameters sse 135 ZBT Controller VO 136 Connecting to Memory uiuat eii a DEED HM RR UN MR cr Eras UR 137 Address M Pping 137 Timme ils
170. ardware The first error detection mechanism in hardware to be discussed is contention error detection that detects when an SPI device configured as a master is selected i e its SS bit is asserted by another SPI device simultaneously configured as master As noted before the master being selected as a slave immediately drives its outputs as necessary to avoid hardware damage due to simultaneous drive contention Simultaneously with driving outputs to a safe condition the master sets the mode fault error bit in the status register This bit is automatically cleared by reading the status register Following a MODF error the master must be disabled and re enabled with correct data This may require clearing the FIFOs when configured with FIFOs A similar error detection mechanism in hardware has been implemented for SPI slave devices The error detected is when a SPI device configured as a slave but is not enabled and is selected i e its SS bit is asserted by another SPI device When this condition is detected interrupt bit 30 is set by a strobe to the interrupt register if the interrupt module is included in the assembly This error detection does not exist if the interrupt module is not included in the SPI assembly Under run and over run conditions error detection is provided as well Under run conditions can happen only in slave mode of operation where a master commands a transfer but the slave does not have data in the transmit reg
171. armeterization i et Te VE Ere VR C EXPL Fe ER CERE E EE ia De 204 March 2002 www xilinx com MicroBlaze Hardware Reference Guide 1 800 255 7778 xi XILINX MicroBlaze Endianness 205 Origin of 205 aha oa 206 bit Naming C onvenlblOD 206 Data Types Endianness 206 VHDL 208 BRAM LMB Exatiple ett 208 BRAM ORB Example entro tires terrse 209 li T O 213 xii www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Figures The MicroBlaze Architecture Figure 1 Figure 2 MicroBlaze Core Block Diagram sese ene en nnn 3 Big Endian Data Types reticere onte e re 9 MicroBlaze Bus Interfaces Figure 1 MicroBlaze Core Block Diagram eee enn 11 Figure 2 MicroBlaze Bus Configurations sss nnn 12 Figure 3 Configuration 1 enn 13 Figure 4 Configuration 2 1 14 Figure 5 Configuration 3 ILMB DOPB DLMB sess eee eee enne 15 Figure 6 Configuration 4 IOPB ILMB DODBDPB esee enne 16 Figure 7 Configuration 5 IOPB DOPB eene entente tenen 17 Figure 8 Configuration 6
172. ber The interrupt vector number is determined on a per device basis and is either at a fixed location relative to the interrupt request level or is supplied by the interrupting device as part of the interrupt acknowledge cycle Interrupt request level seven is non maskable and the other six levels can be masked by software Interrupt request level one has the lowest priority and interrupt request level seven has the highest priority All the peripherals on chip can be programmed to request an interrupt on any of the seven levels Interrupt request levels one through six behave as level sensitive interrupts in that as long as that level is active interrupt requests will be generated The level must be maintained by the interrupting device until the interrupt has been acknowledged by the processor Interrupt request level seven behaves like an edge sensitive interrupt since only one interrupt request is generated each time that level is entered and the level must be exited and re entered to generate another interrupt MIPS MIPS CPUS have eight interrupt sources six of which are for hardware interrupts and the remaining two are for software interrupts There is no priority all interrupts are considered 92 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Simple Interrupt Controller Specification XILINX equal Each interrupt can be masked by the software and there is a global interrupt enable MIPS only sup
173. ble 3 GPIO Register Address Map 32 bit esses 182 Table 4 GPIO DATA Register oett rere 182 Table 5 GPIO EREResistet eere e tete eet Gen ie oer ebore riens 182 Table 6 Summary of GPIO I O 32b OPB interface sse 183 Table 72 MPD Parameters eerte eterne tere ei etd nier eet ins 183 OPB Timebase WDT Specification Table 1 TBWDT Configuration and Access Type sees eee 186 Table 2 TBWDT Register Address 186 Table 3 TBWDT Register Address Map 0 eee ene nene 188 Table 4 Control Status Register 0 5 sees nene 188 Table 5 Control Status Register 1 5 422442201 190 Table 6 Summary of Timebase WDT Core 191 Table 7 MPD Parameters ieiiena siete dese tees a ies 192 Table 8 OPB Timebase WDT Performance and Resource Utilization Benchmarks Virtex II 2V1000 5 sse nnne n nnne 192 OPB Timer Counter Specification Table 1 TC Configuration and Access 196 Table 2 TC Register Address Map 32b bus interface sess 197 Table 3 TC Register Address Map 32b bus interface esses 198 Table 4 Control Status Register 0 5 sse eene 199 Table 5 Control Status Register 1 201 Table 6 Summary of Timer Core eee eene 203 Table 7 MPD Parameters ota feinen
174. byte enable architecture is an optional subset of the OPB V2 0 specification and is ideal for low overhead FPGA implementations such as MicroBlaze The OPB data bus interconnects are illustrated in Figure 10 The write data bus from masters and bridges is separated from the read data bus from slaves and bridges to break up the bus OR logic In minimal cases this can completely eliminate the OR logic for the read or write data buses Optionally you can OR together the read and write buses to create the correct functionality for the OPB bus monitor Note that the instruction side OPB contains a write data bus tied to 0x00000000 and a RNW signal tied to logic 1 so that its interface remains consistent with the data side OPB These signals are constant and generally are minimized in implementation A multi ported slave is used instead of a bridge in the example shown in Figure 11 This could represent a memory controller with a connection to both the IOPB and the DOPB In this case the bus multiplexing and prioritization must be done in the slave The advantage of this approach is that a separate I to D bridge and an OPB arbiter on the instruction side are not required The arbiter function must still exist in the slave device March 2002 www xilinx com 23 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX MicroBlaze Bus Interfaces Data side OPB DOPB ABus 0 31 DOPB BE 0 3
175. ck are deasserted indicating that no data transfer is in progress e Overlapped arbitration cycle The OPB xferAck is asserted indicating the final cycle in a data transfer and OPB busLock is not asserted Arbitration in this cycle allows another master to begin a transfer in the following cycle avoiding the need for a dead cycle on the bus You can configure the Xilinx OPB Arbiter to have either registered or combinational grant outputs Registered grant outputs are asserted one clock after each arbitration cycle resulting in one dead cycle on the bus However registered grant outputs allow the OPB bus to run at higher clock rates Figure 1 shows the fixed OPB arbitration protocol with combinational grant outputs Figure 2 shows the fixed OPB arbitration protocol when the OPB Arbiter has been parameterized to have registered grant outputs Cycles 0 1 2 3 4 5 6 jf OPB MNGrant 1 M1 busLock M1 select IN OPB xferAck Figure 1 OPB Fixed Bus Arbitration Combinational Grant Outputs Cycles 0 2 3 4 5 6 M request 1 OPB MGrant 1 M1 busLock M1 select OPB xferAck Figure 2 OPB Fixed Bus Arbitration Registered Grant Outputs
176. cknowledge 76 P6 OPB 0 OPB AWIDTH 1 IPIF OPB address bus 76 P7 OPB BE 0 C OPB DWIDTH 8 1 IPIF OPB byte enables 76 P8 OPB 0 DWIDTH 1 IPIF OPB data bus 76 P9 OPB RNW IPIF Read not Write OR of all master RNW 76 signals P10 segAddr IPIF sequential address 76 Arbitration P11 M 0 NUM MASTERS 1 Arbitration Logic Request from OPB Masters 80 Signals OPB xferAck Arbitration Logic Transfer Acknowledge indicating end of 80 data transfer cycle OR of all slave xferAcks P13 OPB_select Arbitration Logic Master has taken control of the bus OR 80 86 Watchdog Timer of all master selects P14 retry Watchdog Timer Bus cycle retry OR of all slave retrys 86 P15 Watchdog Timer Suppress timeout OR of all slave 86 toutSups 16 timeout Watchdog Timer 0 Timeout signal for 86 P17 busLock Park Lock Logic Bus lock OR of all master buslocks 82 P18 NUM MASTERS 1 Park Lock Logic 0 Grant to OPB Masters 82 System P19 System System clock P20 OPB Rst System System Reset active high Notes 1 Name has been modified slightly from that in the IBM OPB Arbiter specification to support parameterization of the number of masters 68 www xilinx com March 2002 1 800 255 7778 On Chip Peripheral Bus OPB Arbiter Design Specification XILINX The sig
177. clock phase and polarity External ports selected via a parameter for off chip slave interconnects off chip masters not supported Optional transmit and receive FIFOs implemented as a pair only Local loopback capability for testing The Xilinx SPI design allows you to tailor the SPI Assembly to suit your application by setting certain parameters to enable or disable features The parameterizable features of the design are discussed in the SPI Configuration Parameters section The basic SPI device consists of a register module and the SPI module Optional FIFOs and support are discussed in a later section The register block includes all memory mapped registers as shown in Figure 1 and resides on the Xilinx OPB As shown in Figure 3 the SPI module consists of transmitter and receiver sections a parameterized baud rate generator BRG and a control unit The registers are an 8 bit status register an 8 bit control register an N bit slave select register and a pair of 8 bit transmit receiver registers In the 68HC11 implementation the transmit register is transparent to the shift register and the receive register is double buffered with the shift register In this implementation without FIFOs both the transmit and receive register are double buffered Hardware prevents data transfer from the transmit buffer to the shift register while an SPI transfer is in progress consequently the write collision error described in the MC68HC11 Refere
178. code can determine if the last system reset was a WDT reset WDT can only be disabled by writing to two distinct addresses reducing the possibly of inadvertently disabling the WDT in the application code Register Data Types and Organization TBWDT registers are accessed as one of the following types Byte 8 bits Half word 2 bytes Word 4 bytes Configuration The following table shows TBWDT configurations and access type Table 1 TBWDT Configuration and Access Type Configuration Access Type 32 bit slave OPB peripheral Word 16 bit peripheral Half word 8 bit peripheral Byte 32 bit 16 bit or 8 bit peripheral All register accesses are on word boundaries to conform to the OPB IPIF register location convention The addresses of the TBWDT registers when configured as a 32 bit OPB slave are shown in the following table Table 2 TBWDT Register Address Map Address Register Hex Size Type Description TCSRO 0x00 Word R W Control Status Register 0 TCSR1 0x04 Word Control Status Register 1 state is mirrored in TCSRO for read TBR 0x08 Word Timebase Register www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Timebase WDT Specification XILINX The TBWDT registers are organized as big endian data The bit and byte labeling for the big endian data types is shown in the following figure
179. com March 2002 1 800 255 7778 Contents Preface Overview of MicroBlaze Embedded Systems H MicroBlaze Soft Processor Core 1T sese Bus Intetconnects gone irre E HER A OPB SUNN c e M General Purpose Registers 0 1 Special Purpose Registers ete eet era en eni pr hr nd Prio P UO m P Pipeline Architecture onn eo meo cecidit one dti cere re eee BtancheS ice ederent Load Store 00 Interrupts and 42 666 6 Interrupts EXCOPtONS Bus aoi qao itii URINE RM Typical Peripheral oett nite inerte a G NAE OPB Bus Configuration iue o odisti rete LMB Bus IJefitUtiORi steer E tr cecinere LMB Read and Write Data Tip SMS TEAL OM Parameterization P
180. d Write Operation March 2002 www xilinx com 29 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX 30 MicroBlaze Bus Interfaces Read and Write Data Steering The MicroBlaze data side bus interface performs the read steering and write steering required to support the following transfers byte halfword and word transfers to word devices byte and halfword transfers to halfword devices e byte transfers to byte devices MicroBlaze does not support transfers that are larger than the addressed device These types of transfers require dynamic bus sizing and conversion cycles that are not supported by the MicroBlaze bus interface Data steering for read cycles is shown in Table 5 and data steering for write cycles is shown in Table 6 Table 5 Read Data Steering load to Register rD Register rD Data Address Byte Enable Transfer 30 31 0 3 Size rD 0 7 rD 8 15 rD 16 23 rD 24 31 001 bye Bye 10 0010 byte Byte2 01 0100 byte Byte1 00 1000 byte 10 0011 halfword Byte2 Byte3 00 1100 halfword 1 00 1111 word ByteO Byte1 Byte2 Byte3 Table 6 Write Data Steering store from Register rD Write Data Bus Bytes Address Byte Enable Transfer 30 31 0 3 Size 1 2 Byte3 11 0001 byte rD 24 31 10 0010 byte rD 24 31 01 0100 byte rD 24 31 00 1000 byte rD 24 31 1
181. d debugging Typical Applications MPEG Decoder Communications Controller e Complex state machine for process control and other embedded applications Set top boxes Characteristics This configuration allows the CPU core to operate at the maximum clock rate because of the simpler instruction side bus structure However instruction fetches on the OPB are slower than fetches from BRAM on the LMB Overall processor performance is lower than implementations using LMB unless a large percentage of code is run from the internal instruction history buffer This configuration allows debugging of application code through either software based debugging resident monitor debugging or hardware based JTAG debugging March 2002 www xilinx com 19 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX MicroBlaze Bus Interfaces Configuration 6 Memory Interrupt Timer Controller Controller Counter Ext memory and WDT MicroBlaze CPU Core Data side OPB Instruction side LMB BRAM Memory Other OPB Controller Master Slave or Bridge Dual Port Block RAM Figure 8 Configuration 6 ILMB DOPB Purpose Use this configuration when your application code fits into the on chip ILMB BRAM but more memory may be required for data memory The data side OPB is used for one or more external memory controllers and other peripherals such as UARTS timers general purpose additional BRAM and custom periphera
182. d on the master which was most recently granted the bus as indicated by the Grant Last register This master s grant signal will be asserted during valid arbitration cycles when no other master s request signal is asserted Figure 20 shows bus parking on the last master with the OPB Arbiter parameterized for fixed priority arbitration and combinational grant outputs for a 4 OPB Master system Cycles 0 1 2 3 4 5 7 8 9 to 1 Control register 0 31 X 00100000000000000000000000000000 LVLO Priority Reg 31 32 X 00 LVL1 Priority Reg 31 32 1 01 LVL2 Priority Reg 31 32 10 Priority Reg 31 32 11 M request 0 M request 1 M request 2 M request 3 T OPB MGrant 0 LJ OPB_MGrant 1 I OPB MGrant 2 OPB MGrant 3 Figure 20 Bus Parking on Last Master Fixed Priority Arbitration Combinational Grant Outputs March 2002 www xilinx com 85 1 800 255 7778 XILINX On Chip Peripheral Bus OPB Arbiter Design Specification Grant Logic The Grant Logic block determines the final grant signals to the OPB Masters based on the intermediate grant signals from the arbitration logic and the
183. d slave interrupt enable registers as desired Write configuration data to master SPI device CR as required Write configuration data to slave SPI device CR as required Write the active low one hot encoded slave select address to the master SS register Write data to slave transmit register as required Write data to master transmit register to start transfer Wait for interrupt typically interrupt 30 or poll status for completion Read interrupt registers of both master and slave SPI devices as required Perform interrupt requests as required Read status registers of both master and slave SPI devices as required Perform actions as required or dictated by status register data SPI Master and Slave Devices where Registers FIFOs are filled before SPI transfer is started and multiple discrete 8 bit transfers are transferred optional mode Follow these steps to successfully complete an SPI transaction 1 2 3 Start from proper state including SPI bus arbitration Configure master and slave interrupt enable registers as desired Write configuration data to master SPI device CR as required Write configuration data to slave SPI device CR as required 174 www xilinx com v1 00b 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Serial Peripheral Interface SPI Design Specification XILINX 5 Write the active low one hot encoded slave select address to the master SS register 6 Write all data to slave transmit
184. d when a SPI transfer is completed the number is decremented As a consequence of this operation aborted SPI transfers still has the data available for a retry of the transmission The occupancy number is a read only register If a write of data is attempted when the FIFO is then no acknowledgement is given and a bus timeout will occur Interrupts associated with the transmit FIFO include Data Transmit FIFO Empty Transmit FIFO Half Empty and Transmit FIFO Under run See the later section on interrupts for details The receive FIFO is read only When data is read from the FIFO the occupancy number is decremented and when a SPI transfer is completed the number is incremented If a read is attempted when the FIFO is empty then no acknowledgement is given and a bus timeout will occur Data is automatically written to the FIFO from the SPI module shift register after the completion of a SPI transfer If the receive FIFO is full and more data is received then a Receive FIFO Overflow interrupt is issued When this happens all data attempted to be written to the full receive FIFO by the SPI module is lost The other interrupt associated with the receive FIFO is the Receive FIFO Full interrupt SPI transfers when the SPI assembly is configured with FIFOs can be started in two different ways depending on when the enable bit in the control register is set If the enable bit is set prior to the first data being loaded in the FIFO then the SPI trans
185. ded For example if you request version 1 00 a then the library name is library name v1 00 a PAO Example The following is an example PAO file lib lib lib common vl 00 a common types pkg common 1 00 a pselect gpio 1 00 a gpio core lib gpio 1 00 a HDL Design This section includes HDL design considerations Considerations Scalable Data path Using an MPD option declaration you can automatically scale data path width Bus expressions are evaluated as arithmetic equations Format CSET signal name default connection direction A B Where A and B are an arithmetic expression MPD Example The following is an example file SELECT IP my peripheral Generics for vhdl or parameters for verilog CSET attribute C BASEADDR 0 00000 std logic vector 0 to 31 CSET attribute C MY PERIPH AWIDTH 17 integer Global ports CSET signal OPB Clk in CSET signal OPB Rst in y peripheral signals CSET signal MY ADDR out 0 C PERIPH AWIDTH 1 OPB signals March 2002 www xilinx com 61 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX 62 Microprocessor Peripheral Definition Format END By default if the vectors are larger than one bit the Platform Generator determines the range specification on buses as either big endian or little endian However if the vector is one bit width th
186. der the transfer complete In this VHDL implementation and when configured without FIFOs the equivalent of the SPIF bit is the bit 30 in the status register which is the Rc_Full bit Setting of this bit denotes the end of a transfer and that data is available in the receive register In this configuration bit 27 of the interrupt register which is the Data Receive Register Full interrupt is asserted as well The data received is clocked in the receive register on the same clock edge as interrupt 27 being asserted When the SPI device is configured as a master without FIFOs status register bits 31 and 28 are cleared status register bits 29 and 30 are set and interrupt bits 27 and 30 are set on the first rising OPB clock edge after at the end of the eighth SCK cycle Note that the end of the eighth SCK cycle is a transition on for CPHA 0 but is not denoted by a transition on SCK for CPHA 1 However the master internal clock provides this SCK edge which prompts the setting clearing of the bits noted When the SPI device is configured as a slave setting clearing of the bits discussed above for a master coincides with the setting clearing of the master bits for both cases of 0 and CPHA 1 Recall that for CPHA 1 i e no SCK edge denoting the end of the eighth clock period the slave has no way of knowing when the end of the eighth SCK period occurs unless an OPB clock period counter was included in the SPI slave device In this design
187. diagram for an SPI data transfer when the clock phase CPHA is set to 0 The waveforms are shown for both positive and negative clock polarities of SCK i e CPOL 1 and 0 Recall the with CPHA 1 data is valid on the first clock edge rising or falling depending on CPOL Therefore SCK signal remains in the idle state until one half period following assertion of the slave select line which denotes the start of a transaction Since assertion of the SS N line denotes the start of a transfer it must be de asserted and reasserted for sequential byte transfers to the same slave device v1 00b www xilinx com 155 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Serial Peripheral Interface SPI Design Specification SCK Cycles 4 6 SCK Cycle 7 SCK Cycle 8 ax SCK Cycle 1 SCK Cycle 2 SCK CPOL 1 SCK CPOL 0 PE MOSI 6 5 MISO 6 5 SS Not defined but normally MSB of character just received Figure 3 Data Transfer on the SPI Bus with 0 and 24 0 for 8 bit character Figure 4 shows the timing diagram for an SPI transfer when the clock phase CPHA is set to 1 Waveforms are shown for both positive and negative clock polarities of The first cycle begins with a transition of SCK signal from its idle state and this denotes the start of the data transfer Because the clock transition
188. e It has thirty two 32 bit general purpose registers and two 32 bit special purpose registers General Purpose Registers RO R31 The thirty two 32 bit General Purpose Registers are numbered 0 through 31 RO is defined to always have the value of zero Anything written to RO is discarded and zero is always read 0 31 T RO R31 Table 3 General Purpose Registers RO R31 Bits Name Description Reset Value 0 31 RO through General Purpose Register 0x00000000 R31 RO through R31 are 32 bit general purpose registers RO is always zero 6 www xilinx com March 2002 MicroBlaze Hardware Reference Guide The MicroBlaze Architecture XILINX Special Purpose Registers Program Counter PC The Program Counter is the 32 bit address of the next instruction word to be fetched It can be read by accessing RPC with an MFS instruction It cannot be written to using an MTS instruction 31 Table 4 Program Counter PC Bits Name Description Reset Value 0 31 PC Program Counter 0x00000000 Address of next instruction to fetch Machine Status Register MSR The Machine Status Register contains the carry flag and enables for interrupts and buslock It can be read by accessing RMSR with an MFS instruction When reading the MSR bit 29 is replicated in bit O as the carry copy MSR can be written to with an MTS instruction Writes to MSR are delayed one clock cycle When writing to MSR using MTS the value written take
189. e performance The features that can be parameterized in the Xilinx UART design are shown in Table 1 Table 1 JTAG UART Parameters Notes 1 Address range specified by BASEADDR and HIGHADDR must be a power of 2 2 No default value is specified for C BASEADDR and HIGHADDR to insure that the actual value is set if the value is not set a compiler error is generated These generics must be a power of 2 Default Feature Description Parameter Name Allowable Values Value VHDL Type JTAG UART Registers C BASEADDR Valid Address std logic vector Base Address Range 2 JTAG UART Registers HIGHADDR Valid Address std logic vector HIGH Address Range 2 Target Family C_FAMILY Xilinx FPGA families virtex2 strings OPB Data Bus Width C_OPB_DWIDTH 32 32 integer OPBAddress Bus Width C OPB AWIDTH 8 32 32 integer 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers as listed at http www xilinx com legal htm other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 205 XILINX JTAG UART Signals Table 2 JTAG UART I O Signals OPB JTAG UART Specification The I O signals for the JTAG_UART are listed in Table 2
190. e 68 OPB Arbiter Control Register sisis iseis sss 69 OPB Arbiter Priority Registers 72 March 2002 www xilinx com MicroBlaze Hardware Reference Guide 1 800 255 7778 vii XILINX OPB Arbiter Block cou eb p mde 73 Slave Interface 74 Control Register LOgiC di rime ttis 74 Priority Register Logic there lt 74 ARB2BUS Data Mux inicteene itemm aen amen adam iem 77 Arbitration Logic usce tenete ir Por deett ri ridere teens 78 Park Lock Logic ierit eee tree re tiit rte iiie iei dere 79 Watchdog Timer aeree tem ended eed alee meant 84 Design CUM D tn da Dd 85 Device Utilization and Performance 85 Specification Exceptions C 85 86 Priority Level 1 eere tenen ree 86 Grant 86 Parking eere rere etie den 86 Clock and Power Management 86 Scan Test CHAINS zs 87 Reference DOCUNIents uude nro rti a Hi id V b Hood I DR EU M RE UHR 87 OPB Simple Interrupt Controller Specification 89 conari M 89 lla PI 89 lu
191. e while the SPI device is configured as a slave but is not enabled This bitis set immediately upon SS going active and continually set if SS is active and the device is not enabled v1 00b MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 165 5 XILINX OPB Serial Peripheral Interface SPI Design Specification Table 6 Interrupt Register Bit Definitions Bit assignment assumes 32 bit bus Bit s Name Access Reset Value Description 29 DTR Empty Read Write 1 to clear 0 Data Transmit Register FIFO Empty Interrupt 29 is the Data Transmit Register FIFO Empty interrupt Without FIFOs this bit is set at the end of a SPI byte transfer by a one clock period strobe to the interrupt register With FIFOs this bit is set at the end of the SPI byte transfer when the transmit FIFO is emptied by a one clock period strobe to the interrupt register See section on definition of end of transfer In the context of the 68HC11 Reference Manual when configured without FIFOs this interrupt is equivalent in information content to the complement of SPI transfer complete flag SPIF interrupt bit 28 DTR Under run Read Write 1 to clear Transmit Register FIFO Under run Interrupt 28 is the Transmit Register FIFO under run interrupt This bit is set by a one clock period strobe to the interrupt register when data is request from an empty transmit register FIFO by the
192. ect between one master and one slave The original specifications followed closely Motorola s M68HC11 Rev 4 0 Reference Manual There are difference from the 68HC11 specification that should be reviewed when utilizing this SPI Assembly see Specification Exceptions The Version B specification has extended functionality including a manual slave select mode This mode allows you to manually control the slave select line directly by the data written to the slave select register This allows transfers of an arbitrary number of bytes without toggling the slave select line until all bytes are transferred In this mode you must toggle the slave select by writing the appropriate data to the slave select register The manual slave select mode is the default mode of operation This parameterized module permits additional slaves with automatic generation of the required decoding of the individual slave select outputs by the master Additional masters can be added as well however means to detect all possible conflicts are not implemented with this interface standard but rather require the software to arbitrate bus control in order to eliminate conflicts At this time only SPI slave devices are allowed off chip This is an artifact of software master control arbitration which can not be guaranteed if off chip masters were allowed and is due to issues with asynchronous external clocks as well Essentially any number of internal slave and master SPI devices is
193. ections to the external memory devices to avoid incorrect data and address connections The following tables show the correct mapping of memory controller pins to memory device pins March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 125 XILINX OPB External Memory Controller EMC Table 34 Variables used in Defining Memory Subsystem Variable Allowed Range Definition BN 0 to 7 Memory bank number DN 0 to 127 Memory device number within a bank The memory device attached to the most significant bit in the memory subsystem is 0 device numbers increase toward the least significant bit MW 8 to 128 Width in bits of memory subsystem DW 1 to 128 Width in bits of data bus for memory device MAW 1 to 32 Width in bits of address bus for memory device AU 1 to 128 Width in bits of smallest addressable data word on the memory device AS 20 Address shift for address bus logo MW AU DW 8 HAW 1 to 64 Width of host address bus e g OPB or PLB in bits Table 35 Memory Controller to Memory Interconnect Description EMC Signal MSB LSB Memory Device Signal MSB LSB Data bus Mem DQ DN DW DN 1 DW 1 D DW 1 0 Address bus Mem A HAW MAW AS HAW AS 1 A MAW 1 0 Chip Enable low true MEM_CEN BN CEN Output Enable low true MEM_OEN OEN Write Enable low true MEM_WEN WEN for devices that have byte enables or do not require byte enables Byte Enable Qualifi
194. ed Write Enable low true MEM_QWEN INT DN DW 8 WEN for devices that require byte enables and do not have them Byte Enable low true MEM_BEN INT DN DW 8 INT DN 1 DW 8 1 BEN DW 8 1 0 Example Memory Connections 126 Example 1 This example shows the connection to 32 bit memory using 2 IDT71V416S SRAM parts Table 36 Variables for Simple SRAM Example Variable Value Definition BN 0 Memory bank number DN 0 to 1 Memory device number within a bank The memory device attached to the most significant bit in the memory subsystem is 0 device numbers increase toward the least significant bit MW 32 Width in bits of memory subsystem DW 16 Width in bits of data bus for memory device www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB External Memory Controller EMC Table 36 Variables for Simple SRAM Example Continued XILINX Variable Value Definition MAW 18 Width in bits of address bus for memory device AU 16 Width in bits of smallest addressable data word on the memory device AS 2 Address shift for address bus logo MW AU DW 8 HAW 32 Width of host address bus e g OPB or PLB in bits Table 37 Connection to 32 bit Memory using 2 IDT71V416S Parts Memory Device Signal DN Description EMC Signal MSB LSB MSB LSB 0 Data bus Mem_DQ 0 15 0 15
195. ee clock cycles for a taken branch adding a latency of two cycles for refilling the pipeline MicroBlaze uses two techniques to reduce the penalty of taken branches One technique is to use delay slots and another is use of a history buffer Delay Slots When the processor executes a taken branch and flushes the pipeline it takes three clock cycles to refill the pipeline By allowing the instruction following a branch to complete this penalty is reduced Instead of flushing the instructions in both the fetch and decode stages only the fetch stage is discarded and the instruction in the decode stage is allowed to complete This effectively produces a delayed branch or delay slot Since the work done on the delay slot instruction is not discarded this technique effectively reduces the branch penalty from two clock cycles to one Branch instructions that allow execution of the subsequent instruction in the delay slot are denoted by a D in the instruction mnemonic For example the BNE instruction does not execute the subsequent instruction in the delay slot whereas BNED does execute the next instruction in the delay slot before control is transferred to the branch location Load Store MicroBlaze can access memory in the following three data sizes Architecture Byte 8 bits e Halfword 16 bits Word 32 bits Memory accesses are always data size aligned For halfword accesses the least significant address bit is forced to 0 Similarly
196. eference Guide 1 800 255 7778 XILINX Microprocessor Hardware Specification MHS Format Use the following format for attributes CSET attribute name valu Attribute names are case sensitive Use the following format for signals CSET signal name connection Signal names are case sensitive Ending a Peripheral Definition Use the following format to end a peripheral definition END MHS Example The following is an example MHS file SELECT bus v20 CSET attribute HW VER 1 00 a CSET attribute INSTANCE myopb CSET signal OPB sys_clk CSET signal SYS_Rst sys_reset SELECT slave opb_bram CSET attribute HW_VER 1 00 a CSET attribute INSTANCE mybraml CSET attribute C HIGHADDR OxFFFFIFFF CSET attribute C BASEADDR 0 CSET signal _ 1 sys_clk END SELECT SLAVE opb_uartlite CSET attribute HW_VER 1 00 a CSET attribute INSTANCE myuartlitel CSET attribute C HIGHADDR OxFFFF80FF CSET attribute C BASEADDR OxFFFF8000 CSET signal RX 1 CSET signal TX 1 ET signal OPB Clk sys clk CSET signal Interrupt int periph PRIORITY 1 D SELECT SLAVE opb arbiter CSET attribute HW VER 1 02 b CSET attribute INSTANCE myarbiterl CSET attribute C HIGHADDR OxOOFF90FF CSET attribute C BASEADDR OxOOFF9000 CSET attribute C PAR
197. egister when the external capture signal is asserted The TINT bit is also set in TCSR on detection of the capture event The counter can be configured as an up or down counter for this mode selectable by the UDT bit in TCSR The ARHT bit controls whether the capture value is overwritten with a new capture value before the previous TINT flag is cleared This mode is useful for time tagging external events while simultaneously generating an interrupt Characteristics Capture Mode has the following characteristics The capture signal can be configured to be low true or high true The capture signal is sampled within the TC with the _ The capture event is defined as the transition on the sampled signal to the asserted state For example if the capture signal is defined to be high true then the capture event is when the sampled synchronized to the OPB signal transitions from 0 to 1 When the capture event occurs the counter value is written to the Load Register This value is called the capture value When the ARHT bit Auto Reload Hold is set to 0 and the capture event occurs the capture value is written to the Load Register The Load Register will hold this capture value until the Load Register is read If the Load Register is not read subsequent capture events will not update the Load Register and will be lost When the ARHT bit Auto Reload Hold is set to 1 and the capture event occurs the capture
198. elect bit forces the data in the Slave Select register to be asserted on the SS output anytime the device is configured as a master and the device is enabled SPE asserted This bit has no effect on slave operation machine register 23 Master Transaction Inhibit Read Write Master Transaction Inhibit This bit inhibits Master transactions in the same way Freeze functions This bit has no effect on slave operation e 70 Master transactions enabled T Master transactions inhibited v1 00b MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 169 XILINX OPB Serial Peripheral Interface SPI Design Specification SPI Status Register SR Bit assignment in the SPI Status Register is shown in Table 9 Bit assignment was made to fol low the assignment pattern of Xilinx IPIF specifications and when possible follow the 68HC11 assignment pattern The status register is read only Note reset default values Table 9 SPI Status Register Bit Definitions Bit assignment assumes 32 bit bus Reset Bit s Name Access Value Description 31 Rc Empty Read 1 Receive Empty When a receive FIFO exists this bit will be set high when the receive FIFO is empty the occupancy of the FIFO is decremented with each FIFO read operation When FIFOs don t exist this bit is set high when the receive register has been read This bit is cleared at the end of a successfu
199. emarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice www xilinx com 3 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Instructions The MicroBlaze Architecture All MicroBlaze instructions are 32 bits and are defined as either Type A or Type B Type A instructions have up to two source register operands and one destination register operand Type B instructions have one source register and a 16 bit immediate operand which can be extended to 32 bits by preceding the Type B instruction with an IMM instruction Type B instructions have a single destination register operand Instructions are provided in the following functional categories arithmetic logical branch load store and special Table 2 lists the MicroBlaze instruction set Refer to the MicroBlaze Instruction Set Architecture document for more information on these instructions Table 1 describes the instruction set nomenclature used in the semantics of each instruction Table 1 Instruction Set Nomenclature Symbol Description Ra RO R31 General Purpose Register source operand a Rb RO R31 General Purpose Register source operand b Rd RO R31 General Purpose Register destination operand C Carry flag MSR 29 Sa Special Purpose Register source operand Sd Special Purpose Register destination operand 5 Sign extend argument x to 32 bit value
200. en the range cannot be determined and Platform Generator defaults to big endian style notation To change this default behavior use the ENDIAN option Format CSET signal mysignal in 0 0 ENDIAN LITTLE This builds the VHDL equivalent mysignal in std logic vector 0 downto 0 Internal Signals Set internal signals with the TYPE INTERNAL option Format CSET signal mysignal out TYPE INTERNAL By default only OPB and signals are defined as INTERNAL All other signals are defined as EXTERNAL External signals are available through the port declaration in the top level module Interrupt Signals Interrupt signals are identified by the EDGE or LEVEL option 3 state InOut Signals At the MHS MPD level there is a listing for an inout port in the MPD file that allows you to map to itin the MHS file In the MPD file a 3 state signal is identified by the inout direction mode and the port name must be ioname MY IP X9617 Figure 2 IOBUF Implementation The Platform Generator expands the inout port in the MPD file to three ports in the port declaration section of the HDL file and writes out the RTL code to infer the IOBUF This port expansion occurs because if the top level is synthesized without IO insertion the 3 states on the inout ports are inferred as BUFTs at the CLB level However they should be inferred as IOBUFs at the IOB level Platform Generator infers the 3 state
201. ence Guide 1 800 255 7778 137 5 XILINX OPB ZBT Controller Design Specification Programming Register Data Types and Organization Model The ZBT controller is organized as big endian data The bit and byte labeling for the big endian data types is shown in Figure 4 Byte address n n 1 n 2 n 3 Byte label 0 1 2 3 Word Byte significance MSByte LSByte Bit label 0 31 Bit significance MSBit LSBit Byte address ned Byte label 0 1 Halfword Byte significance MSByte LSByte Bit label 0 15 Bit significance MSBit LSBit Byte address n Byte label 0 Byte Byte significance MSByte Bit label 0 7 Bit significance MSBit LSBit Figure 4 Big Endian Data Types Implementation Design Tips To achieve the highest fmax on the ZBT controller the Xilinx implementation tools must force flip flops to the IO pads This option is turned off by default 138 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX 2002 Summary Overview OPB BRAM Parameters Xilinx Embedded Processors OPB Peripherals OPB Block RAM BRAM Specification This document describes the specifications for an OPB BRAM core for the MicroBlaze soft processor and other embedded processors This document applies to the following peripherals opb bram v1 00a The OPB BRAM is a module that attaches to the OPB On chip Periph
202. equency ratio G10 C SPI SLAVE ONLY P16 18 P20 None Not implemented at this time but will be in the future G11 C NUM OFFCHIP SS BI Number of G12 Defines the number of bits in the TS pins assigned SS vector that go off chip i e off chip SPI slave devices Must be less than or equal to NUM SS BITS G12 C NUM SS BITS P26 28 None Defines the number of bits in the SS vector v1 00b www xilinx com 163 MicroBlaze Hardware Reference Guide 1 800 255 7778 5 XILINX SPI Register Descriptions 164 OPB Serial Peripheral Interface SPI Design Specification The SPI assembly contains addressable registers for read write operations as shown in Table 4 The base address is set by the parameter C BASEADDR and all SPI register addresses are calculated by an offset from C BASEADDR The first SPI register is at offset C IP REG BAR OFFSET The IPIF also contains the interrupt registers and IP reset module which are both optional registers Addresses of both register sets are calculated by an offset from BASEADDR All bit indices are relative the OPB bus The highest bit index is the Isb In this document bit assignment will be made assuming a 32 bit OPB assignment for either wider or narrower buses follows the same convention Table 4 shows addresses of all the SPI registers the IPIF interrupt registers and the IP Reset module The transmit FIFO occupancy and Receive FIFO occupancy only exist when the SPI assembly is configured
203. er is not an actual register It is a write only location used to clear interrupt requests Note The next two address locations are not registers but provide helper functions that make setting and clearing IER bits easier Set Interrupt Enables SIE is a write only location that provides the ability to set selected bits within the IER in one atomic operation rather than requiring a read modify write sequence Clear Interrupt Enables CIE is a write only location that provides the ability to clear selected bits within the IER in a single atomic operation Both SIE and CIE are optional in the Simple IntC and can be parameterized out of the design to reduce FPGA resource consumption by the IntC Interrupt Vector Register is a read only register that contains the ordinal value of the highest priority interrupt that is active and enabled The IVR is optional and can be parameterized out of the design to reduce IntC FPGA resources Master Enable Register MER is a read write two bit register used to enable or disable the IRQ output and to enable hardware interrupts when hardware interrupts are enabled software interrupts are disabled until the IntC is reset Bus Interface The core interrupt controller functionality is designed with a simple bus interconnect interface For a particular bus interface all that is required is a top level bus centric wrapper that instantiates the IntC core and the desired bus interface
204. er Other Port Write Data Bus Port BRAM Read Data 0 31 Other Other Port Read Data Bus Port Programming Model 4BRAMSs gt 2 Kbyte 8BRAMSs gt 4 Kbyte 16 BRAMs gt 8 Kbyte 32 gt 16 Kbyte The following sizes are supported for Virtex Il and Virtex II PRO 4 gt 8 Kbyte e 8BRAMs gt 16 Kbyte 16 gt 32 Kbyte 32 gt 64 Kbyte 140 Supported Memory Sizes The following sizes are supported for Virtex Virtex E and Spartan ll www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide OPB Block RAM BRAM Specification Register Data Types and Organization The are organized as big endian data The bit and byte labeling for the big endian data types is shown in Figure 1 Byte address Byte label Byte significance Bit label Bit significance Byte address Byte label Byte significance Bit label Bit significance Byte address Byte label Byte significance Bit label Bit significance March 2002 MicroBlaze Hardware Reference Guide n n 1 n 2 n 3 0 1 2 3 MSByte LSByte 0 31 MSBit LSBit n n 1 0 1 Halfword MSByte LSByte 0 15 MSBit LSBit n 0 Byte MSByte 0 7 MSBit LSBit Figure 1 Big Endian Data Types www xilinx com 1 800 255 7778 XILINX Word 141 XILINX OPB Block RAM
205. er The transfer is completed with the return of transfer acknowledge retry or error acknowledge 116 www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide OPB External Memory Controller EMC XILINX Cycles 0 1 2 3 4 5 6 7 M1 request ge E _ OPB_M1Grant OPB select M1 select l M1_RNW M1 ABus valid address SI xferAck A SI DBus valid data B E 1 SI DBusEn Figure 27 Basic OPB Data Transfer Cycles 0 1 2 3 4 5 6 7 wear LL Lf Ll Ll Ld M1 request OPB_M1Grant E 6 NJ NJ M1 select OPB xferAck Lf Af OPB ABus 1 2 OPB DBus DO D1 D2 D3 Figure 28 OPB Data Transfer with Continuous Master Request Cycles 0 1 2 3 4 5 6 7 Tq M request 1 OPB MGrani 1 p select m A OPB ABus MN EN OPB_DBus 00 D1 A 02 1 select E M1 RNW M1 ABus D1 voc A NND o M1 DBusEn 91 DBus SI DBusEn A Figure 29 OPB Full Word Read Write March 2002 wwwW xilinx com 117 MicroBlaze Hardware Reference Guide 1 800 255
206. er ID i e Master 0 will have level 0 priority highest Master 1 will have level 1 priority and Master n will have level n priority Once the PRV bit has been asserted the values in the Priority Registers will again be used to determine OPB ownership The Priority Register can be accessed from the OPB for read and write operations Note that regardless of the priority mode selected for the OPB Arbiter even if the OPB Arbiter has been parameterized to fixed priority arbitration the processor core can set the desired priority levels of the OPB masters by writing to these registers The top level block diagram for the OPB Arbiter is shown in Figure 7 The IPIF block is the OPB bus interface block that handles the OPB bus protocol for reading and writing the Priority Registers and the Control Register within the OPB Arbiter The ARB2BUS data mux contains the data multiplexor required to output data to the OPB bus during a read cycle The Arbitration Logic block determines which incoming request has the highest priority and the Park Lock Logic block determines which master should be granted the bus based on this priority as well as whether the bus is locked or if bus parking is enabled The Watchdog Timer asserts the OPB timeout signal if a slave response OPB xferAck OPB retry or OPB toutSup has not been received within 16 clock cycles of the master taking control of the bus Priority Register Logic a ie IP2BUS Data
207. er halfword transfer byte transfer Mn ABus 30 31 00 Mn ABus 30 31 00 Mn ABus 30 31 10 Mn ABus 30 31 00 Mn 1111 Mn BE 1100 Mn BE 0011 Mn BE 1000 Data Bus Data Bus Data Bus 0 7 0 7 0 7 8 15 8 15 16 23 16 23 16 23 24 31 24 31 24 31 byte transfer byte transfer byte transfer Mn 30 31 01 Mn 30 31 10 Mn ABus 30 31 11 Mn BE 0100 Mn BE 0010 Mn BE 0001 Figure 1 Byte lane usage for aligned transfers All OPB slave devices that require a continuous address space i e use of all byte lanes will implement an attachment to the OPB bus that is as wide as the OPB data width regardless of device width This eliminates the need for left justification on the OPB bus and eliminates the need for masters to mirror write data As an example consider an 8 bit memory device that must be addressed at consecutive byte addresses being attached to a 32 bit OPB The 8 bit memory device must implement a 32 bit wide attachment to the in the bus attachment data is steered from the proper byte lane into the 8 bit device for writes and from the 8 bit device onto the proper byte lane for reads The simplest way to accomplish this is with a multiplexer for steering the writes and a connection from the 8 bit device to all byte lanes essentially mirroring to all byte lanes for reads convention registers in all OPB slave devices are aligned to word boundaries lowest
208. er it has been enabled Operation 188 EWDT2 Table 5 Control Status Register 1 TCSR1 Bits Name Description Reset Value 0 30 Reserved 31 EWDT2 Enable Watchdog Timer Enable 2 0 This bit must be used in conjunction with the EWDT1 bit in the TCSRO register to disable the WDT BOTH bits must be 0 to disable the WDT This bitis WRITE ONLY in this register The value of EWDT2 can be read back only TWCSR1 0 WDT function is disabled 1 WDT function is enabled Timebase Operation The timebase is a 32 bit up counter that is incremented by one on the rising edge of the clock provided to the TBWDT This counter is reset to zero when the Reset input is high or when the WDT is enabled The TBR contains the full timebase count value 32 bits The TWCSRO contains the most significant 28 bits of the timebase count as well as the WDT enable and status bits The timing resolution from the upper 28 bits of the timebase count is x 16 is the period of the input clock As a result a single access be used to read the state of the watchdog times as well as a reduced resolution version of the timebase An interrupt signal is provided that pulses high for one clock period as the counter rolls over from OxFFFFFFFF to 0x00000000 This interrupt be used by the software to keep track of how many timebase rollovers have occurred WDT Operation The timeout interval is configured by a pa
209. eral Bus and has the following features Features e OPB V2 0 bus interface with byte enable support Number of is configurable Handles byte half word and word transfers Other port of the BRAM is available for customer designs e Handles Virtex Virtex E Spartan ll Virtex Il and PRO type of BRAM To allow you to obtain an BRAM that is uniquely tailored for your system certain features be parameterized in the BRAM design This allows you to configure a design that only utilizes the resources required by your system and operates with the best possible performance The features that can be parameterized Xilinx BRAM designs are shown in Table 1 Table 1 OPB BRAM Parameters Notes 1 Address range specified by C BASEADDR and C HIGHADDR must be a power of 2 2 No default value is specified for C BASEADDR and HIGHADDR to insure that the actual value is set if the value is not set a compiler error is generated These generics must be a power of 2 Default Feature Description Parameter Name Allowable Values Value VHDL Type OPB BRAM Registers C BASEADDR Valid Address std logic vector Base Address Range OPB BRAM Registers HIGHADDR Valid Address std logic vector HIGH Address Range 2 Target Family C FAMILY Xilinx FPGA families virtex2 strings OPB Data Bus Width C OPB DWIDTH 32 32 integer OPBAddress Bus Width
210. f the SPI Assembly is configured with FIFOs 166 www xilinx com 1 800 255 7778 v1 00b MicroBlaze Hardware Reference Guide OPB Serial Peripheral Interface SPI Design Specification XILINX Table 6 Interrupt Register Bit Definitions Bit assignment assumes 32 bit bus Reset Bit s Name Access Value Description 24 Read 0 Unassigned Interrupt Enable Descriptions The SPI assembly has interrupt enable features Bit assignment in the Interrupt enable register is shown in Table 7 The interrupt enable register is read write All bits are cleared upon reset Table 7 Interrupt Register Bit Definitions Bit assignment assumes 32 bit bus Reset Bit s Name Access Value Description 31 MODF set Read Write 0 Mode Fault Error Flag Enable Enables this enable interrupt to be passed to the interrupt controller 70 Not enabled T Enabled 30 Slv_MODF Read Write 0 SIv MODF Enable Enables this interrupt to be enable passed to the interrupt controller 70 Not enabled T Enabled 29 DTREmpty Read Write 0 Data Transmit Register FIFO Empty enable Enable Enables this interrupt to be passed to the interrupt controller 70 Not enabled T Enabled 28 DTR Read Write 0 Transmit FIFO Under run Enable Enables Under run this interrupt to be passed to the interrupt enable controller 70 Not enabled
211. fer begins immediately after the write to the master transmit FIFO If the FIFO is emptied via SPI transfers before additional bytes are written to the transmit FIFO an interrupt will be asserted When the OPB SPI SCK frequency ratio is sufficiently small this scenario is highly probable Alternatively the FIFO can 158 www xilinx com v1 00b 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Serial Peripheral Interface SPI Design Specification XILINX be load with up to 16 bytes and then the enable bit can be set which starts the SPI transfer In this case an interrupt is issued after all bytes are transferred In all cases more data can be written to the transmit FIFOs to increase the number of bytes transferred before emptying the FIFOs Local Master Loopback Mode Local master loopback mode although not included in the 68HC11 Reference Manual has been implemented to expedite testing When this mode is selected via setting the Loop bit in the control register the transmitter output is internally connected to the receiver input The receiver and transmitter operate normally except that received data from remote slave is ignored This mode is meaningful only when the SPI device is configured as a master Hardware Error Detection The SPI architecture relies mainly on software controlled bus arbitration for multi master configurations to avoid conflicts and errors but limited error detection is implemented in the SPI h
212. ference Guide Xilinx Embedded Processors MicroBlaze XILINX The MicroBlaze Architecture March 2002 Summary This document describes the architecture for the MicroBlaze 32 bit soft processor core Overview The MicroBlaze embedded soft core is a reduced instruction set computer RISC optimized for implementation in Xilinx field programmable gate arrays FPGAs See Figure 1 for a block diagram depicting the MicroBlaze core Features The MicroBlaze embedded soft core includes the following features Thirty two 32 bit general purpose registers e 32 bit instruction word with three operands and two addressing modes Separate 32 bit instruction and data buses that conform to IBM s OPB On chip Peripheral Bus specification e Separate 32 bit instruction and data buses with direct connection to on chip block RAM through a LMB Local Memory Bus e 32 bit address bus Single issue pipeline e Hardware multiplier in Virtex ll and subsequent devices Instruction side Data side bus interface bus interface Add Sub ILMB P Counter Shift Logical Multiply Instruction Decode Register File Instruction Buffer 32 X 32b IOPB Figure 1 MicroBlaze Core Block Diagram 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers as listed at http www xilinx com legal htm other trad
213. for word accesses the two least significant address bits are forced to 0 MicroBlaze is a Big Endian processor and uses the Big Endian address and labeling conventions shown in Figure 2 when accessing memory The following abbreviations are used e MSByte Most Significant Byte e LSByte Least Significant Byte e MSBit Most Significant Bit e LSBit Least Significant Bit March 2002 www xilinx com 9 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX The MicroBlaze Architecture Byte address n n 1 n 2 n 3 Byte label d 1 2 3 Word Byte significance MSByte LSByte Bitlabel 0 31 Bit significance MSBit LSBit Byte address n n1 Byte label 5 1 Halfword Byte significance MSByte LSByte Bit label 0 15 Bit significance MSBit LSBit Byte address n Byte label 0 Byte Byte significance MSByte Bitlabel 0 7 Bit significance MSBit LSBit Figure 2 Big Endian Data Types When Reset or a Debug Rst occurs MicroBlaze starts executing from address 0 PC and MSR are reset to the default values When an Ext Brk occurs MicroBlaze starts executing from address 0x18 and stores the return address in register 16 An Ext is not executed if the BIP bit in MSR is active equal to 1 When an Ext NM Brk occurs MicroBlaze starts executing from address 0x18 and stores the return address in register 16 This occurs When an interrupt occurs MicroBlaze st
214. ganization 119 MHS 43 49 MHS example 44 MHS signal options 46 MicroBlaze Core Block Diagram 3 MicroBlaze 3 Microprocessor Hardware Specification 43 49 Microprocessor Peripheral Defini tion MPD File 51 Microprocessor System Definition MSD format 43 49 MIPS 92 mixed systems 39 Motorola 68332 92 O OCM 40 On chip Peripheral Bus OPB 13 On Chip Peripheral Bus OPB Arbiter 63 OPB 33 40 OPB Arbiter Block Diagram 75 OPB Arbiter I O Signals 68 OPB Arbitration Protocol 64 OPB BRAM 139 OPB Bus Configuration 23 OPB General Purpose Input Output 177 OPB interface 94 OPB JTAG_UART 205 OPB Master Inputs 55 OPB Master Outputs 55 56 OPB Serial Peripheral Interface 151 OPB Slave Inputs 56 OPB Slave Interface IPIF 76 OPB Slave Outputs 55 OPB Timebase WDT 183 OPB Timer Counter 193 OPB UART Lite 143 OPB V2 0 devices 34 opb_arbiter 63 opb_bram 139 opb_gpio 177 opb intc 91 opb jtag uart 205 opb memcon 113 opb spi 151 opb timebase wdt 183 opb timer 193 opb uartlite 143 opb zbt controller 133 P PAO Peripheral Analyze Order 49 Parameter Port Dependencies 69 Parameter Combinations 68 Parameterization 109 Performance Benchmarks 87 Peripheral Analyze Order PAO File 61 Peripheral Placement 15 Pipeline Architecture 8 Platform Generator 49 50 PLB 40 power signals 48 PRIORITY 46 Priority Level Nomenclature 89 Priority Register 70 Priority Register Logic
215. ger 1 integer 1 integer UART Lite I O The I O signals for the UART Lite are listed in Table 2 Signals Table 2 UART Lite I O Signals Signal Name Interface I O Description OPB_Clk OPB OPB Clock OPB Rst OPB OPB Reset OPB ABus 0 31 OPB OPB Address Bus OPB BE 0 3 OPB OPB Byte Enables OPB DBus 0 31 OPB OPB Data Bus OPB RNW OPB OPB Read Not Write OPB select OPB OPB Select segAddr OPB OPB Sequential Address UART DBus 0 31 OPB UART Data Bus UART errAck OPB UART Error Acknowledge UART retry OPB O UART Retry UART OPB O UART Timeout Suppress UART xferAck OPB O UART Transfer Acknowledge Interrupt Interrupt UART Interrupt RX External Receive Data TX External O Transmit Data JTAG UART Register Data Types and Organization Address Map and Register Descriptions Registers in the UART Lite are accessed as one of three types byte 8 bits halfword 2 bytes and word 4 bytes All register accesses are on word boundaries to conform to the OPB IPIF register location convention The addresses of the UART Lite registers are provided in the Address Map section 144 www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide OPB UART Lite Specification XILINX The UART Lite registers are organized as big endian data The bit and byte labeling for the big endian data type
216. gister Table 29 shows all of the EMC control registers and addresses when all memory banks are used Only control registers for memory banks that are used are present in the design Table 29 EMC Control Registers Register Name OPB Address Access MEMO Control Register EMCCRO BASEADDR 0x00 Write MEM Control Register EMCCR1 BASEADDR 0x04 Write MEM Control Register EMCCR2 BASEADDR 0x08 Write MEMS Control Register EMCCR3 BASEADDR 0x0C Write Control Register EMCCR4 BASEADDR 0x10 Write 5 Control Register EMCCR5 BASEADDR 0x14 Write 6 Control Register EMCCR6 BASEADDR 0x18 Write MEM7 Control Register EMCCR7 BASEADDR 0 1 Write Notes 1 This design can accommodate up to 8 Banks of Flash and or SRAM and are therefore designated as C MEMO BASEADDR C MEM1 BASEADDR etc 2 Each bank of memory s control register is the same as described below Note The register definitions and address locations of the Xilinx EMC deviate from the IBM EBC specification This deviation is necessary as a slave only implementation for the EBC and because there is no DCR interface March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 OPB External Memory Controller EMC XILINX EMC Control Register EMCCR The EMC Control Register is shown below The first row of the table is the bit location the second row conta
217. gnal 1 Enables external generate signal 30 UDTO Up Down Count 0 0 0 Timer functions as up counter 1 Timer functions as down counter 31 MDTO 0 Mode 0 See the Timer Modes section 0 Timer mode is generate 1 Timer mode is capture Control Status Register 1 TCSR1 Control Status Register 1 contains the control and status bits for timer module 1 ENALL T1INT ARHT1 GENT1 T T T T T PWMBO LOAD1 CAPT1 UDT1 Table 4 Control Status Register 1 TCSR1 Bits Name Description Reset Value 0 20 Reserved 200 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Timer Counter Specification Table 4 Control Status Register 1 TCSR1 Continued XILINX Bits 21 Name ENALL Description Enable All Timers 0 No effect on timers 1 Enable all timers counters run This bit is mirrored in all control status registers and is used to enable all counters simultaneously Writing a 1 to this bit sets ENALL ENTO and Writing a 0 to this register clears ENALL but has no effect on ENTO Reset Value 0 22 PWMBO Enable Pulse Width Modulation for Timer1 0 Disable pulse width modulation 1 Enable pulse width modulation PWM requires using TimerO and Timer1 together as a pair TimerO sets the period of the PWM output and Timer1 sets the high time for the PWM out
218. h burst 41 fixed priority arbitration 65 Flash Memory Controller 133 G General Purpose Input Output 177 General Purpose Registers RO R31 6 Generics Parameters 110 GPIO General Purpose Input Output 177 GPIO Organization 177 GPIO Register Address Map 178 180 gpio mpd Microprocessor Periph eral Definition 182 GPIO DATA Register 180 GPIO OE Register 180 Grant Outputs 89 HW VER 46 I O Signals 88 I O Summary 109 IBM PowerPC 405GP Universal In terrupt Controller UIC 93 IDT71V416S 126 127 INSTANCE 46 Instruction Set Nomenclature 4 Intel 8051 92 internal signals 47 Interrupt Acknowledge Register IAR 95 103 interrupt detection and request generation 94 Interrupt Enable Register IER 102 Interrupt Pending Register IPR 95 101 interrupt signal 188 interrupt signals 47 Interrupt Status Register ISR 95 100 Interrupt Vector Register IVR 106 Interrupts 10 J JT AG connector 219 UART 205 L legacy devices 34 level sensitive interrupts 94 little endian 211 LMB 40 LMB Bus Definition 26 LMB Bus Signals 26 Load Store Architecture 9 Local Memory Bus LMB 13 Machine Status Register 7 H Master Enable Register MER 95 DOR Hard tor int t sch 92 vi troll ti 122 Decode 8 ard vector interrupt schemes memory controller operation March 2002 www xilinx com 221 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Memory Data Types and Or
219. he CIE clears the corresponding bit s in the IER without affecting any other IER bits The IntC is implemented to minimize area Consequently all configurable elements within the design are based on generics parameters and any unused or unselected capabilities are not implemented see the Parameterization section Summary The following tables provide information on I O signals I Os that are common for all IntC types are shown in Table 22 Table 23 shows I Os that are specific to an OPB Table 22 Core IntC Summary Port Name Direction Description Type Range Intr in Interrupt intputs Std Logic Vector C NUM INTR INPUTS 1 downto 0 Irq out IntC interrupt request output Std Logic n a Table 23 OPB IntC Summary Port Name Direction Description Type Range in OPB clock Std Logic n a OPB Rst in OPB reset active high Std Logic n a OPB select in OPB select Std Logic n a OPB ABus in OPB address bus Std Logic Vector 0 to C OPB AWIDTH 1 OPB RNW in OPB read not write enable read Std Logic n a high write low OPB BE in OPB byte enables Std Logic Vector 0 to C OPB DWIDTH 8 1 OPB DBus in OPB data bus OPB to IntC Std Logic Vector 0 to C OPB DWIDTH 1 DBus out IntC data bus IntC to OPB Std Logic Vector 0 to C OPB DWIDTH 1 IntC_xferAck out IntC transfer acknowledge Std_Logic n a IntC_ErrAck out IntC error acknowledge Std
220. he data bus attached to integer by this peripheral expressed as a standard logic vector BASEADDR Indicates the base address of this std logic vector peripheral expressed as a 0 to C AWIDTH 1 std logic vector HIGHADDR Indicates the highest address occupied std logic vector 0 to C AWIDTH 1 Device Utilization and Performance Benchmarks The following table shows approximate resource utilization and performance benchmarks for the OPB Timer Counter The estimates shown are not guaranteed and can vary with FPGA family and speed grade parameters selected for implementation user timing constraints and implementation tool version Only parameters that affect resource utilization are shown in the following table Table 8 OPB Timebase WDT Performance and Resource Utilization Benchmarks Virtex Il 2V1000 5 Parameter Values Device Resources fax MHz Address C_AWIDTH Slices Slice 4 input MAX Bits in Flip Flops LUTs Decode 24 32 111 63 155 190 www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide OPB Timebase WDT Specification XILINX Parameterization The following characteristics of the TBWDT can be parameterized Base address for the TBWDT registers Behavior of WDT enable enable once or enable many e interval Future parameterization Bus interface 8 bit 16 bit or 32 bit The internal architecture of
221. his master is at a lowest priority Figure 17 illustrates this behavior when the OPB Arbiter is configured to support fixed priority arbitration and combinational grant outputs Figure 18 illustrates this behavior when the OPB Arbiter is configured to support dynamic priority arbitration when the OPB Arbiter is configured to support dynamic priority arbitration and registered grant outputs March 2002 www xilinx com 83 1 800 255 7778 XILINX On Chip Peripheral Bus OPB Arbiter Design Specification Cycles 0 1 2 3 4 5 6 7 Control register 0 31 00110000000000000000000000000000 0 Priority Reg 31 32 o LVL1 Priority Reg 31 32 01 j LVL2_Priority_Reg 31 32 Y 100 Priority Reg 31 32 X 11 M request 0 _ p df T 1 M request 1 M request 2 M request 3 OPB MGrant 0 OPB MGrant 1 OPB_MGrant 2 OPB MGrant 3 1 Figure 17 Bus Parking Fixed Priority Arbitration Combinational Grant Outputs 0 1 2 s 4 s e 7z s 9 10 t 12 13 14 15 t6 opec 111 111 Control register 0 31 11111100000000000000000000000011 LVLO Priority Reg 31 32 00 01 10 11
222. ibit bit This initializes and MOSI but inhibits transfer Write to Slave Select Register to manual assert of SS vector Write the above configuration data to master SPI device CR but clear inhibit bit which starts transfer Wait for interrupt typically interrupt 30 or poll status for completion Wait time will depend on clock ratio Set Master Transaction Inhibit bit to service interrupt request Writing new data to master register FIFOs and slave device then clear Master Transaction Inhibit bit to continue N 8 bit character transfer Note that an overrun of the receive register FIFO can occur if the receive register FIFOs are not read properly Also note that SCK will have stretched idle levels between byte transfers or groups of byte transfers if utilizing FIFOs and that MOSI can transition at end of a byte transfer or group of transfers but will be stable at least one half SCK period prior to sampling edge of SCK Repeat previous two steps until all data is transferred Write all ones to slave select register or exit manual slave select assert mode to deassert SS vector while SCK and MOSI are in the idle state Disable devices as desired SPI Master and Slave Devices without FIFOs performing one 8 bit transfers optional mode Follow these steps to successfully complete an SPI transaction 1 o M AR 9 10 11 12 Start from proper state including SPI bus arbitration Configure master an
223. ics Lists ports and default connectivity for the OPB interface as defined by IBM For example the MPD file can include information that maps signal UART_xferAck to SI xferAck e contain attributes set by you Supplied by the IP provider Any MPD option is overwritten by the equivalent MHS assignment refer to the Microprocessor Hardware Specification Format document for more details e individual peripheral documentation contains information on all MPD file options Depending on your peripheral design you may need to use Black Box Description BBD or Peripheral Analyze Order PAO files The BBD file manages file locations of optimized hardware netlists for the black box sections of the peripheral design The PAO file contains a list of HDL files that are needed for synthesis and defines the analyze order for compilation For more information on the Platform Generator refer to the MicroBlaze Software Reference Guide Refer to Figure 1 for a depiction of the peripheral directory structure On a UNIX system the OPB peripherals reside in the following location MICROBLAZE hw coregen On a PC the OPB peripherals reside in the following location MICROBLAZE hw coregen To specify additional directories you can use one of the following options e Current directory where Platform Generator was launched not where the MHS resides Set the Platform Generator P option or the MYPERIPHERALS environment vari
224. ide an interrupt if a SPI device is configured as a slave and is selected when not enabled In this design the data transmit and data receive registers have independent addresses This is an exception to the 68HC11 specification which calls for the two registers to have the same address All SS signals are required to be routed between SPI devices internally to the FPGA This is because toggling of the SS signal is utilized in slaves to minimize FPGA resources Manual control of the SS signals is provided by setting bit 24 in the command register When this bitis set the vector in the slave select register is asserted when the device is configured as a master and is enabled When this mode is enabled multiple bytes can be transferred without toggling the SS vector A control bit is provided to inhibit master transfers This bit is effective in any master mode but has main utility in manual control of the SS signals In this implementation without FIFOs both the transmit and receive register are double buffered Hardware prevents data transfer from the transmit buffer to the shift register while an SPI transfer is in progress consequently the write collision error described in the MC68HC11 Reference Manual can not occur In the 68HC11 implementation the transmit register is transparent to the shift register which necessitates the write collision error WCOL detection hardware however it is not required or implemented in this implementatio
225. if C NUM MASTERS gt 1 Priority Register Logic The Priority Register logic contains the Priority Registers and the logic to update the priority of the OPB masters Descriptions of the OPB Arbiter Priority Registers are found in section OPB Arbiter Register Descriptions The Priority Registers are only present in the design if NUM 5 gt 1 Priority Register Update Logic Fixed Priority Parameterization C DYNAM PRIORITYzO When the OPB Arbiter is parameterized to support only fixed arbitration the dynamic priority enable bit in the Control Register is permanently disabled The Priority Registers are loaded at reset with the value of the Master ID which matches the priority level of the register For example the LVLO Priority Register is loaded with 0 to represent the ID of Master 0 Likewise the LVLn Priority Register is loaded with the bit encoding of n to represent the ID of Master n as shown in Table 8 The Priority Registers can be loaded with different Master IDs by writing to the Priority Registers if C PROC INTRFCE 1 therefore the priorities of the OPB Masters can be changed as desired by software The Priority Registers Valid PRV bit in the Control Register is negated whenever the processor modifies the Priority Registers and is asserted whenever the modification is complete The ID of the masters are used to determine OPB ownership whenever the bit is negated The relative priorities of the OPB Masters
226. ig Endian Data 133 viii www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX OPB ZBT Controller Design Specification Figure Ts Read Cycles 52 setate erue en 138 Figure 2 Write Cycle di nie i eee t iit te reddas 138 Figure3 Clock Synchronization isisisi einen tti nter 139 Figure4 Big Endian Data Types 4 eene here 140 OPB UART Lite Specification Figure 1 Big Endian Data 143 Figure 2 Lite Register Set sse eee eene 143 OPB JTAG UART Specification Figure 1 Big Endian Data then eria it iae EEES 151 Figure 2 UART Register nene nnn 151 OPB Serial Peripheral Interface SPI Design Specification Figure 1 SPI Assembly Top level Block Diagram eee 157 Figure 2 Multi master Configuration Block Diagram sese eee 158 Figure 3 Data Transfer on the SPI Bus with 0 sees eee 159 Figure 4 Data Transfer on SPI Bus with CPHAS1 159 OPB General Purpose Input Output GPIO Specification Figure 1 GPIO Block Diagram seri 179 Figure2 Big Endian Data ertet tenerte teet aene Pura iie roe sive 181 Figure 3 Register Set sss eene nennen 181 OPB Timebase WDT
227. ignal is the OR of the interrupts from the two counters The interrupt service routine must poll the TCSR s to determine the Source or sources of the interrupt The interrupt status bit TINT in the TCSR can only be cleared by writing a 1 to it Writing 0 to it has no effect on the bit Since the interrupt condition is an edge the counter rollover or the capture event it can cleared at any time and will not indicate an interrupt condition until the next interrupt event Register Data Types and Organization TC registers are accessed as one of the following types Byte 8 bits A Half word 2 bytes Word 4 bytes Configuration The following table shows TC configurations and access type Table 1 TC Configuration and Access Type Configuration Access Type 32 bit slave OPB peripheral Word The addresses of the TC registers are shown in the following table Table 2 TC Register Address Map Address Register Hex Size Type Description TCSRO 0x00 Word R W Control Status Register 0 TLRO 0x04 Word R W Load Register 0 TCRO 0x08 Word R Timer Counter Register 0 196 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX OPB Timer Counter Specification Table 2 TC Register Address Map Address Register Hex Size Type Description TCSR1 0x10 Word R W Control Status Register 1 TLR1 0x14 Word R W Load Register
228. ils and timing diagrams please refer to the description of the SPI bus in the Motorola 68HC11 Reference Manual The SPI bus to a given slave device N th device consists of four wires Serial Clock SCK Master Out Slave In MOSI Master In Slave Out MISO and Slave Select SS N SCK MOSI and MISO are shared signals for all slaves and masters Each master SPI device has the functionality to generates an active low one hot encoded SS N vector where each bit is assigned as a SS signal to each slave SPI device It is possible for SPI Master Slave devices to be both internal to the FPGA and SPI Slave devices to be external to the FPGA package when external slave devices are to be on the SPI bus SPI pins are automatically instantiated This option is chosen via Platform Generator Multiple SPI Master Slave devices are diagrammed in Figure 2 When a SPI device is slave only then the slave select register and multiple SS N outputs are not included in that device implementation Slave only option is selected via Platform Generator v1 00b www xilinx com 153 MicroBlaze Hardware Reference Guide 1 800 255 7778 5 XILINX OPB Serial Peripheral Interface SPI Design Specification SS 0 SS 1 SS 2 SS 3 SPI Device 0 SPI Device 1 MOSI MISO id e SPI Device 2 MOSI MISO bd e SCK SPISEL o W 52 SPI Device 3 MOSI MISO e SC
229. in the MER the Hardware Interrupt Enable HIE and the Master IRQ Enable ME The ME bit must be set to enable the interrupt request output 3 If software testing is to be performed the HIE bit must remain at its reset value of zero Software testing can now proceed by writing a one to any bit position in the ISR that corresponds to an existing interrupt input A corresponding interrupt request is generated if that interrupt is enabled and interrupt handling proceeds normally 4 Once software testing has been completed or if software testing is not performed a one is written to the HIE bit which enables the hardware interrupt inputs and disables any further software generated interrupts 5 After a one has been written to the HIE bit any further writes to this bit have no effect This feature prevents stray pointers from accidentally generating unwanted interrupt requests while still allowing self test software to perform system tests at power up or after a reset Reading the ISR indicates which inputs are active If present the IPR indicates which enabled inputs are active Reading the optional IVR provides the ordinal value of the highest priority interrupt that is enabled and active For example if the IVR is present and a valid interrupt signal has occurred on the Int3 interrupt input and nothing is active on Int2 Int1 and IntO reading the IVR will provide a value of three If IntO becomes active then reading the IVR provides a va
230. ins the reset value for that bit Table 30 shows the Control Register bit definitions The Control Register definition deviates from the IBM EBC specification because the DCR is not supported in the design FS 1 1 Table 30 EMC Control Register Bit Definitions Bit s Name Core Access Reset Value Description 0 29 Reserved 30 PM Read Write o Page Mode Enable Determines whether or not in page detection logic is created with a corresponding decrease in read access time for in page reads 0 Page Mode is Disabled 1 Page Mode is Enabled 31 FS Read Write o Fast Slow Mode Enable Determines the number of Wait States required based on the input timing parameters 0 Slow Access Time T Fast Access Time Table 31 EMC Control Register Bit Functionality Read Write PM Enable FS Enable Function Read 0 0 Slow access 0 1 Fast access 1 X Fast in page slow not in page Write X 0 Slow access X 1 Fast access EMC Block Memory Data Types and Organization Diag ram Depending on the size of the bus attached to the processor memory can be accessed through the EMC as follows byte 8 bits halfword 2 bytes word 4 bytes doubleword 8 bytes e 128 bit 16 bytes March 2002 www xilinx com 119 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB External Memory Controller EMC For the OPB data is organized as big endian
231. ion in the IAR will clear the interrupt request that was generated by the corresponding interrupt input Writing zeros does nothing as does writing a one to a bit that does not correspond to an active input or for which an interrupt input does not exist The IAR is shown in the following diagram and the bits are described in Table 17 IAR Interrupt Acknowledge Register INTn INTn 2 INTn 4 E T T INTn 1 INTn 3 T T INTn 5 INT1 INTO Table 17 Interrupt Acknowledge Register Bits Name Description Reset Value 0 INTn INTO Interrupt Input n Interrupt Input 0 n a to ns w 1 1 Clear Interrupt w 1 where wis DB width 0 0 action March 2002 www xilinx com 103 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Simple Interrupt Controller Specification Set Interrupt Enables SIE SIE is a location used to set IER bits in a single atomic operation rather than using a read modify write sequence Writing a one to a bit location in SIE will set the corresponding bit in the IER Writing zeros does nothing as does writing a one to a bit location that corresponds to a non existing interrupt input The SIE is optional in the simple IntC and can be parameterized out of the implementation The SIE is shown in the following diagram and the bits are d escribed in Table 18 SIE Set Interrupt Enables INTn 2 INTn 4 T T
232. is needed for the OPB In this case all other parameters are meaningless 2 C REG GRANTS should only be set to 0 indicating that the Grant outputs are combinational if the desired OPB frequency is less than the fmax specified for this parameter 3 When bus parking is supported the parking mode park on last master or park on master id is set in the OPB Arbiter Control Register If C PROC INTRFCE is 0 the parking mode is park on last master 4 When C PROC INTRFCE is 0 none of the OPB Arbiter registers are accessible 5 No default value will be specified for C BASEADDR to insure that the actual value is set i e if the value is not set a compiler error will be generated 6 Address range specified by C BASEADDR and C HIGHADDR must be at least Ox1FF and must be a power of 2 March 2002 www xilinx com 1 800 255 7778 67 XILINX OPB Arbiter I O Signals On Chip Peripheral Bus OPB Arbiter Design Specification Allowable Parameter Combinations The only restriction on parameter combinations in the Xilinx OPB Arbiter design is that the address range specified by C BASEADDR and C HIGHADDR is a power of 2 To allow for the register offset within the OPB Arbiter design the range specified by C BASEADDR and HIGHADDR must be at least Ox1FF The clock frequency of the OPB specified in the Platform Builder tool must be low enough to allow for combinational Grant outputs Therefore the parameter C REG GRANTS can on
233. ister BASEADDR 0x118 Read Write LVL6 Priority Register BASEADDR 0x11C Read Write LVL7 Priority Register BASEADDR 0x120 Read Write LVL8 Priority Register BASEADDR 0 124 Read Write LVL9 Priority Register BASEADDR 0x128 Read Write LVI10 Priority Register BASEADDR 0x12C Read Write LVL11 Priority Register BASEADDR 0x130 Read Write LVL12 Priority Register BASEADDR 0 134 Read Write LVL13 Priority Register BASEADDR 0x138 Read Write LVL14 Priority Register BASEADDR 0x13C Read Write LVL15 Priority Register BASEADDR 0 140 Read Write The register definitions and address locations of the Xilinx OPB Arbiter deviate from the IBM OPB Arbiter specification This deviation is necessary to support parameterization of the number of OPB Masters See section Specification Exceptions for more information OPB Arbiter Control Register The OPB Arbiter Control Register is shown in Table 5 for the case where the OPB Arbiter has been parameterized for fixed priority arbitration without bus parking with a data width of 32 bits The reset values for the DPE DPERW PEN and PENRW bits vary based on the parameterization of the arbitration and bus parking scheme Table 5 OPB Arbiter Control Register DPE PEN B 502022 DPERW PENRW PRV March 2002 b d moe T Reserved Table 6 shows the Control Register bit definitions The Control Register definition deviates from
234. ister or FIFO for transfer When a such a request is made the slave under run interrupt is asserted and the slave shift register is loaded with all zeros for transmission Over run can happen to both master and slave devices where a transfer occurs when the receive register or FIFO is full When such a transfer occurs the data received in that transfer is not registered i e it is lost and the over run interrupt bit 26 is asserted Software Freeze Command Operation The software freeze command impacts only master operation and not slave operation When a freeze command is asserted i e Freeze signal goes high the master completes any transfer in progress but does not initiate a subsequent SPI transfer until the freeze signal is pulled low Operation is identical to as if the SPI master transmit register FIFO is empty when the Freeze signal is asserted SPI Protocol with Manual Slave Select Assertion This section briefly describes the SPI protocol where Slave Select SS N is manually asserted by the user i e CR 24 1 This is the default configuration The mode is provided to permit transfers of an arbitrary number of bytes without toggling Slave Select until all the bytes are transferred In this mode where CR 24 1 the data in the Slave Select Register appears directly on the SS N output As described earlier SCK must be stable before assertion of Slave Select therefore when manual slave select mode is utilized the SPI master must
235. ive low one hot encoded vector SS N Actual assignment of slaves to specific bits is performed by Platform Generator This register is read write Table 12 shows specifics of the data format The index of SS N increments in the opposite direction to that of the OPB bit index OPB bit index 31 is bit zero of SS N OPB bit index 30 is bit index 1 of SS N and so on The reason for reversing the order of index incrementing is considerations in software driver development v1 00b www xilinx com 171 MicroBlaze Hardware Reference Guide 1 800 255 7778 5 XILINX OPB Serial Peripheral Interface SPI Design Specification Table 12 SPI Slave Select Address Register Bits Bit assignment assumes 32 bit bus Reset Bit s Name Access Value Description 31 1 Slave Address Read all 15 Active low one hot encoded slave select to 31 Write vector of length N bits N must be less than or equal to the databus width Note that SS N increments in the opposite direction to that of the OPB bit index 172 Transmit FIFO Occupancy Register Tx FIFO OCY This field contains the occupancy number greater than one for the Transmit FIFO when the SPI assembly is configured with FIFOs The actual occupancy is the binary value plus 1 This register is read only and does not exist when the assembly is configured without FIFOs The Transmit FIFO Empty Interrupt or Status Bit is the only reliable way to determine if the FIFO i
236. ize since all size information is contained in the byte enable signals The byte enable architecture by itself does not permit dynamic bus sizing since there is only one acknowledge signal for each transfer The OPB V2 0 specification and later allows you to build systems that are legacy only byte enable only or mixed Devices that only support the byte enable signaling are called byte enable devices OPB V2 0 Devices Devices that support both byte enable signaling and legacy signaling are called OPB V2 0 devices Systems that have both legacy signaling and byte enable signaling can perform dynamic bus sizing Note that legacy devices do not support byte enable transfers Xilinx OPB Devices These various transfer protocols have several implications for Xilinx OPB device implementations Conversion Cycles Dynamic bus sizing as supported by legacy devices results in conversion cycles which are extra transfer cycles that re transfer data when the master initiated transfer is larger than the slave response For example in a legacy system if a master writes a 32 bit word to a slave and the 8 bit device slave responds that it only accepted 8 bits of the transfer then the master must perform three additional conversion cycles to transfer all of the data to the slave Generating conversion cycles requires more logic increases the complexity of the master and is not an efficient use of FPGA resources The byte enable architecture provide
237. l SPI transfer 30 Rc Full Read 0 Receive Full When a receive FIFO exists this bit will be set high when the receive FIFO is full the occupancy of the FIFO is incremented with the completion of each SPI transaction When FIFOs don t exist this bit is set high when an SPI transfer has completed When FIFOs don t exist Rc Empty and Rc Full are complements 29 Tx Empty Read 1 Transmit Empty When atransmit FIFO exists this bit will be set high when the transmit FIFO is empty the occupancy of the FIFO is decremented with the completion of each SPI transfer When FIFOs don t exist this bit is cleared with the completion of a SPI transfer Either with or without FIFOs this bit is cleared upon an OPB write to the FIFO or transmit register 28 Tx Full Read 0 Transmit Full When a transmit FIFO exists this bit will be set high when the transmit FIFO is full When FIFOs don t exist this bit is set high when an OPB write to the register has been made and it is cleared when the SPI transfer has completed 27 MODF Read 0 Mode Fault Error Flag This flag is set if the SS signal goes active while the SPI device is configured as a master MODF is automatically cleared by reading the SR MODF does generate an interrupt with a single cycle strobe when the MODF bit transitions from a low to a high 70 No error j Error condition detected 26 Read 0 Unassigned 25 Read 0 Unassigned
238. lated as follows When counters are configured to count up UDT 0 PERIOD TLRO 2 x OPB CLOCK PERIOD HIGH TIME 2 x OB CLOCK PERIOD March 2002 www xilinx com 195 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Timer Counter Specification When counters are configured to count down UDT 1 PERIOD MAX COUNT TLRO 2 x OPB CLOCK PERIOD HIGH TIME COUNT 2 x OPB CLOCK PERIOD where MAX COUNT is the maximum count value for the counter such as OXFFFFFFFF for a 32 bit counter Interrupts The TC interrupt signals can be enabled or disabled with the ENIT bit in the TCSR The interrupt status bit TINT in the TCSR cannot be disabled and always reflects the current state of the timer interrupt In Generate Mode a timer interrupt is caused by the counter rolling over the same condition used to reload the counter when ARHT is set to 1 In Capture Mode the interrupt event is the capture event Characteristics of the interrupts are e Interrupt events can only occur when the timer is enabled In Capture Mode this prevents interrupts from occurring before the timer is enabled interrupt signal goes high for one clock cycle when the interrupt condition is met and the interrupt is enabled in the TCSR The interrupt is asserted on the rising edge of the interrupt signal e A single interrupt signal is provided The interrupt s
239. le so highly resented this Law that our Histories tell us there have been six Rebellions raised on that Account wherein one Emperor lost his Life and another his Crown These civil Commotions were constantly fomented by the Monarchs of Blefuscu and when they were quelled the Exiles always fled for Refuge to that Empire It is computed that eleven Thousand Persons have at several Times suffered Death rather than submit to break their Eggs at the smaller End Many hundred large Volumes have been published upon this Controversy But the Books of the Big Endians have been long forbidden and the whole Party rendered incapable by Law of holding Employments During the Course of these Troubles the Emperors of Blefuscu did frequently expostulate by their Ambassadors accusing us of making a Schism in Religion by offending against a fundamental Doctrine of our great Prophet Lustrog in the fifty fourth Chapter of the Brundrecal which is their Alcoran This however is thought to be a mere Strain upon the text For the Words are these That all true Believers shall break their Eggs at the convenient End and which is the convenient End seems in my humble Opinion to be left to every Man s Conscience or at least in the Power of the chief Magistrate to determine Now the Big Endian Exiles have found so much Credit in the Emperor of Blefuscu s Court and so much private Assistance and Encouragement from their Party here at home that a bloody War has bee
240. linx OPB Arbiter design to deviate slightly from the IBM OPB Arbiter specification These parameters are described in the OPB Arbiter Design Parameters section OPB Arbiter Features Overview The OPB Arbiter is a soft IP core designed for Xilinx FPGAs and contains the following features Optional OPB slave interface included in design a design parameter e OPB Arbitration arbitrates between 1 16 OPB Masters the number of masters is parameterizable arbitration priorities among masters programmable via register write priority arbitration mode configurable via a design parameter Fixed priority arbitration with processor access to read write Priority Registers Dynamic priority arbitration implementing a true least recent used LRU algorithm e Two bus parking modes selectable Control Register write park on selected OPB master specified in Control Register park on last OPB master which was granted OPB access e Watchdog timer which asserts the OPB time out signal if a slave response is not detected within 16 clock cycles Registered or combinational Grant outputs configurable via a design parameter 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and further disclaimers as listed at http www xilinx com legal htm other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without
241. lip Flops LUTs Notes 1 These benchmark designs contain only the with registered inputs outputs without any additional logic Benchmark numbers approach the performance ceiling rather than representing performance under typical user conditions Device resource utilization can be estimated by the following formula TBD Flow This section provides information on setting the SPI registers to initiate and complete bus Description transactions SPI Master Device with or without FIFOs where the slave select vector is asserted manually via command register bit 24 assertion This flow permits the transmittal of N bytes in a single toggling of the slave select vector default mode Follow these steps to successfully complete an SPI transaction 1 Start from proper state including SPI bus arbitration 2 Configure master interrupt enable registers as desired 3 Configure target slave SPI device as required 4 Write initial data to master transmit register FIFO This assumes that the SPI Master is disabled 5 Insure Slave Select Register has all ones v1 00b www xilinx com 173 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX 10 11 12 13 OPB Serial Peripheral Interface SPI Design Specification Write configuration data to master SPI device CR as desired including setting bit 24 for manual asserting of SS vector and setting both enable bit and Master Transfer Inh
242. lization 8 Assumes DCR operates at same clock rate as PLB and each DCR access requires 5 clock cycles The number of clock cycles per DCR transfer is dependent on how many DCR devices are present in the system Each additional DCR device adds latency to all DCR transfers March 2002 MicroBlaze Hardware Reference Guide www xilinx com 41 1 800 255 7778 5 XILINX Revision History 42 OPB Usage in Xilinx FPGAs The following table shows the revision history for this document Date 10 17 01 10 19 01 12 10 01 3 20 02 Version 1 0 1 1 1 2 1 3 Revision Initial Xilinx version Minor editorial changes Added links to bus references Changed Figure 2 and other minor edits Updated for MDK 2 2 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX 2002 Summary Overview MHS Syntax Xilinx Embedded Processors MicroBlaze Microprocessor Hardware Specification MHS Format This document describes the Microprocessor Hardware Specification MHS format for MicroBlaze In the initial phase of MicroBlaze platform design you create an MHS Microprocessor Hardware Specification file that is used by the Platform Generator This file defines your platform configuration and includes the following e Peripherals e One of six configurations of the MicroBlaze bus interfaces e Connectivity of the system Address space In general
243. locations of optimized hardware netlists for the black box sections of your peripheral design The value of the STYLE option in the MPD file determines whether or not you need a BBD file March 2002 www xilinx com 59 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Microprocessor Peripheral Definition Format The black box simulation netlists for HDL simulation must be moved to the simmodels directory and the black box hardware netlists for implementation must be moved to the netlist directory The simmodels and netlist directories can have their own underlying directory structure however they must mirror each other Comments You can insert comments in the BBD file without disrupting processing Comments begin with a pound sign and continue to the end of the line Format The BBD format is a look up table chart that lists netlist files The first line is the header of the look up table There can be as many entries as necessary in the header to make a selection Header entries are tailored by MPD options The last column of the table must be the FILES column For implementation the last column lists the relative path to the file from XIL MYPERIPHERALS opb peripherals ip netlist UNIX XIL_MYPERIPHERALS opb_peripherals lt ip gt netlist PC For simulation the last column lists the relative path to the file from XIL MYPERIPHERALS opb peripherals ip simmodels UNIX XIL_MYPERI
244. logic required to implement two buses per side the maximum clock rate of the CPU may be slightly less than configurations with one bus per side This configuration allows debugging of application code through either software based debugging resident monitor debugging or hardware based JTAG debugging However software based debugging of code in the ILMB BRAM can only be performed if a BRAM memory controller is included on the D side OPB bus to provide write access to the LMB BRAM 18 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide MicroBlaze Bus Interfaces XILINX Configuration 5 Memory OPB to OPB Memory Interrupt Timer Controller Bridge Controller Controller Counter Ext memory Ext memory and WDT MicroBlaze CPU Core Data side OPB Instruction side OPB Other OPB Master Slave or Bridge Figure 7 Configuration 5 IOPB DOPB Purpose Use this configuration when your application requires external instruction and data memory In this configuration all of the instruction and data memory is resident in off chip memory or on chip memory on the OPB buses The data side OPB is used for one or more external memory controllers and other peripherals such as UARTs timers general purpose I O BRAM and custom peripherals The OPB to OPB bridge is only required if the data side OPB needs access to the instruction side OPB peripherals such as for software base
245. lowing outputs for each connection to the OPB Sln DBus Sln errAck Sln retry lt Sin gt _toutSup Sln xferAck Where S n is a meaningful name or acronym for the slave output An additional requirement on S n is that it must not contain the string OPB upper or lower case or mixed case so that slave outputs will not be confused with bus outputs TMR xferAck UART xferAck INTC xferAck MemCon xferAck March 2002 www xilinx com 55 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Microprocessor Peripheral Definition Format MPD Reserved OPB Slave Inputs For interconnection to the OPB all slaves must provide the following inputs for each connection to the OPB nOPB ABus nOPB BE nOPB DBus nOPB RNW nOPB select nOPB segAddr Where nOPB is a meaningful name or acronym for the slave input An additional requirement on nOPB is that the last three characters must contain the string OPB upper or lower case or mixed case OPB DBus IOPB DBus DOPB DBus 1 OPB DBus The Platform Generator establishes connectivity of the OPB and LMB busses to peripherals Sig nal through a common set of signal connections nnection Connections Ports For interconnection to the global ports CSET signal OPB
246. ls Typical Applications Minimal controllers Small to medium state machines Characteristics This configuration allows the CPU core to operate at the maximum clock rate because of the simpler instruction side bus structure The instruction side LMB provides two cycle pipelined read access from the BRAM for an effective access rate of one instruction per clock This configuration allows debugging of application code through either software based debugging resident monitor debugging or hardware based JTAG debugging However software based debugging of code in the ILMB BRAM can only be performed if a BRAM memory controller is included on the D side OPB bus to provide write access to the LMB BRAM 20 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide MicroBlaze Bus Interfaces Bit and Byte XILINX The MicroBlaze buses are labeled using a big endian naming convention The bit and byte Labeling labeling for the MicroBlaze data types is shown in the following figure Byte address n n 1 n 2 n 3 Byte label 0 1 2 3 Word Byte significance MSByte LSByte Bit label 0 31 Bit significance MSBit LSBit Byte address i ned Byte label 0 1 Halfword Byte significance MSByte LSByte label 0 15 significance MSBit LSBit Byte address i Byte label 0 Byte Byte significance MSByte Bit label 0 7 Bit significance MSBit
247. lue of zero If no interrupts are active or it is not present reading the IVR returns all ones Acknowledging an interrupt is achieved by writing a one to the corresponding bit location in the IAR An interrupt acknowledge clears the corresponding interrupt request However if a valid interrupt signal remains on that input another edge occurs or an active level still exists on the corresponding interrupt input a new interrupt request output is generated Also all interrupt requests are combined to form the Irq output so any remaining interrupt requests that have not been acknowledged will cause a new interrupt request output to be generated The software can disable the interrupt request output at any time by writing a zero to the ME bit in the MER This effectively masks all interrupts for that IntC Alternatively interrupt inputs can be selectively masked by writing a zero to each bit location in the IER that corresponds to an 108 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Simple Interrupt Controller Specification Implementation XILINX input that is to be masked If present SIE and CIE provide a convenient way to enable or disable mask an interrupt input without having to read mask off and then write back the IER Writing a one to any bit location s in the SIE sets the corresponding bit s in the IER without affecting any other IER bits Writing a one to any bit location s in t
248. lues which assign level 0 highest priority to Master 0 level 1 next highest priority to Master 1 level 2 priority to Master 2 etc The number of bits required by the master ID within each Priority Register will vary based on the number of masters support by the OPB Arbiter The master ID will always be aligned to the LSB position within the register so that the master ID will appear as an integer when accessed by software Notes 1 OPB Arbiter refers to the priority levels as High Medium High Medium Low and Low since it only implemented arbitration among 4 masters Since the Xilinx implementation of the OPB arbiter supports parameterization of the number of OPB masters in the system numbers are used to represent priority levels instead of text descriptors Level 0 will always remain the highest priority level regardless of the number of masters implemented The higher the level number the lower the priority Table 7 OPB Arbiter OPB Arbiter LVLn Priority Register Reserved LnPM Table 8 OPB Arbiter LVLn Priority Register Bit Definitions Bit s Name Core Access Reset Value Description 0 C OPB DWIDTH Reserved 092 NUM MASTERS 1 C OPB DWIDTH LnPM Read Write mmmm 1 Level n Priority Master ID This field log2 C_NUM_MASTERS contains the ID of the master at level C_OPB_DWIDTH 1 n priority 2 Notes 1 mmmm represents the bit encoding of the Master ID at this priority le
249. ly be set to 0 if the value of the OPB frequency is less than the fmax specified for this parameter The number of OPB masters can be parameterized to 1 master Though no arbitration is necessary when there is only one OPB master the OPB Arbiter contains the watchdog timer for the OPB andis therefore needed in the system When there is only 1 OPB master there will be no Control Register or Priority Registers therefore there will be no OPB slave interface on the OPB Arbiter Since there will not be an OPB slave interface the OPB Arbiter when parameterized for 1 OPB master will not have a Configuration ROM CROM entry When NUM MASTERS is set to 1 all other parameters are meaningless Also when C PROC INTRFCE is set to 0 the OPB Arbiter registers are not accessible and there is no CROM entry for the OPB Arbiter The I O signals for the OPB Arbiter are listed in Table 2 The interfaces referenced in this table are shown in Figure 7 in the OPB Arbiter block diagram Table 2 OPB Arbiter Signals Initial Grouping Signal Name Interface State Description Page OPB Slave P1 DBus 0 C OPB DWIDTH 1 IPIF 0 Arbiter output data bus 76 Signals P2 xferAck IPIF O 0 Arbiter transfer acknowledge 76 P3 Retry IPIF 0 Arbiter retry 76 P4 ARB ToutSup IPIF 0 Arbiter timeout suppress 76 P5 ARB ErrAck IPIF 0 Arbiter error a
250. mber of masters the Xilinx OPB Arbiter uses a separate Priority Register for each priority level Since the number of Priority Registers can vary the OPB Arbiter Control Register is placed at the base address of the OPB Arbiter so that its location doesn t vary Since the number of bits required for the master IDs will vary with the number of masters the fields in the Control Register and the Priority Registers that contain master IDs are LSB aligned The bit ordering of these registers is therefore different than that specified in the IBM OPB Arbiter specification The Control Register also contains additional bits DPERW PENRW not in the IBM OPB Arbiter specification The DPERW bit indicates whether the DPE bit can be modified the PENRW bit indicates whether the PEN bit can be modified and the PRV bit indicates whether the Priority Registers contain valid data i e all master IDs are contained in a Priority Register Signals The signal DbusEn is no longer an signal The gating of the OPB Arbiter s data bus with the enable signal is done internally within the IPIF Module The master request signals and master grant signals have been combined into a bus with an index that varies with the number of masters This modification more easily supports the parameterization of the number of masters supported by the Xilinx OPB Arbiter Table 12 summarizes the signal name modifications and variations Table 12 Xilin
251. module There are currently two types of bus interfaces available providing either an OPB IntC or a DCR IntC The On chip Peripheral Bus OPB interface provides a slave interface on the OPB for transferring data between the OPB IntC and the processor The OPB IntC registers are memory mapped into the OPB address space and data transfers occur using OPB byte enables The register addresses are fixed on four byte boundaries and the registers and the data transfers to and from them are always as wide as the data bus The number of interrupt inputs is configurable up to the width of the data bus which is also set by a configuration parameter In either bus interface the base address for the registers is set by a configuration parameter Since the inputs and the output are configurable several Simple IntC instances can be cascaded to provide any number of interrupt inputs regardless of the data bus width A block diagram of the IntC is shown in Figure 24 March 2002 www xilinx com 95 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Simple Interrupt Controller Specification Bus Wrapper IntC Core Level Edge Detection IRQ i amp Generation gt Synchronization Int_inputs Reg_addr Valid rd Valid wr Data in Bus Interface Bus OPB DCR Figure 24 Interrupt Controller Organization 96 www xilinx com March 2002 1 80
252. n The interrupt enable bit SPIE defined by the 68HC11 specifications which resides in the 68HC11 control register has been moved to the interrupt bit wise enable register In the position of the SPIE bit is a bit to select local master loopback mode for testing This is not specified in the 68HC11 specification but is in the 8260 specification and it is supported in this implementation An option is implemented in the this FPGA design to implement FIFOs on both transmit and receive Full Duplex only An option is implemented in this FPGA design to select slave only mode however this option is not part of the 68HC11 specification This was implemented to reduce FPGA resource required when slave only operation is desired The baud rate generator is specified by Motorola to be programmable via bits in the control register however in this FPGA design the baud rate generator is programmable via parameters in the VHDL implementation Furthermore in addition to the prescribed ratios of 2 4 16 and 32 all integer multiples of 16 up to 2048 are allowed The following documents contain reference information important to understanding the SPI design 1 Motorola s M68HC11 Rev 4 0 Reference Manual e Motorola s MPC8260 PowerQUICC User s Manual 4 1999 Rev 0 176 www xilinx com v1 00b 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX Xilinx Embedded Processors Peripherals OPB General Purpose Input Out
253. n Last Master Fixed Priority Arbitration Combinational Grant 1 eene 83 Figure 21 OPB Timeout Error 84 Figure 22 OPB Timeout Error Suppression eee eee 84 OPB Simple Interrupt Controller Specification Figure 1 Schemes for Generating 4 040 92 Figure 2 Interrupt Controller Organization sees 94 Figure Data Types uias atten eter Gad atris tet dar ber va 95 Figure 4 OPB based Register Offsets and Alignment 96 OPB External Memory Controller EMC Figure 1 Basic OPB Data 115 Figure 2 OPB Data Transfer with Continuous Master 115 Figure 3 OPB Full Word Read Write sess 115 Figure 4 Big Endian Data eterne Drei nter 118 Figure 5 EMC Memory Control Block 5 eee 119 Figure 6 EMC Memory Control State Diagram 120 Figure 7 Timing Waveform for SRAM Read Cycle sees eee 120 Figure 8 Timing Waveform for SRAM Write Cycle sees eee 121 Figure 9 Waveform for Page mode and Standard Word byte Read Operation 122 Figure 10 Waveform for Write 122 OPB Block RAM BRAM Specification Figure 1 B
254. n Set Architecture documentation for more information on software breaks Hardware Breaks Hardware breaks are performed by asserting the external break signal When a hardware break occurs MicroBlaze stops the current execution to handle the break MicroBlaze branches to address 0x00000018 and uses the General Purpose Register 16 to store the address of the instruction that was to be executed when the break occurred MicroBlaze also disables future breaks by setting the Break In Progress BIP flag in the Machine Status Register setting bit 28 to 1 in MSR The instruction located at the address where the current PC points to is not executed Hardware breaks are only handled when there is no break in progress the Break In Progress flag is set to 0 The Break In Progress flag has higher precedence than the Interrupt Enabled flag While no interrupts are handled when the Break In Progress flag is set breaks that occur when interrupts are disabled are handled immediately However it is important to note that non maskable hardware breaks are always handled immediately Equivalent Pseudocode1 116 lt lt 0x00000018 MSR IE lt 1 March 2002 www xilinx com 11 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX The MicroBlaze Architecture 12 wwwW xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide XILINX 2002 Summary Overview Bus Configurations
255. n bits of the address bus integer March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 203 XILINX Table 6 MPD Parameters Continued OPB Timer Counter Specification Parameter C OPB DWIDTH Description The width in bits of the data bus attached to the peripheral Type integer BASEADDR Indicates the base address of this peripheral expressed as a std logic vector std logic vector 0 to C AWIDTH 1 HIGHADDR Indicates the highest address occupied by this peripheral expressed as a standard logic vector std logic vector 0 to AWIDTH 1 Device Utilization and Performance Benchmarks The following table shows approximate resource utilization and performance benchmarks for the OPB Timer Counter The estimates shown are not guaranteed and can vary with FPGA family and speed grade parameters selected for implementation user timing constraints and implementation tool version Only parameters that affect resource utilization are shown in the following table Table 7 OPB Timer Counter Performance and Resource Utilization Benchmarks Virtex Il 2V1000 5 Parameter Values Device Resources fax MHz Address C_AWIDTH Slices Slice 4 input MAX Bits in Flip Flops LUTs Decode 4 32 238 254 130 8 32 245 258 130 16 32 253 260 131 24 32 261 260 130 Parameterization The following characteristics of
256. n carried on between the two Empires for six and thirty Moons with various Success during which Time we have lost Forty Capital Ships and a much greater Number of smaller Vessels together with thirty March 2002 www xilinx com 211 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Appendix Appendix A MicroBlaze Endianness Definitions thousand of our best Seamen and Soldiers and the Damage received by the Enemy is reckoned to be somewhat greater than ours However they have now equipped a numerous Fleet and are just preparing to make a Descent upon us and his Imperial Majesty placing great Confidence in your Valour and Strength hath commanded me to lay this Account of his Affairs before you Data are stored or retrieved in memory in byte half word word or double word units Endianness refers to the order in which data are stored and retrieved Little endian specifies that the least significant byte is assigned the lowest byte address Big endian specifies that the most significant byte is assigned the lowest byte address Note Endianness does not affect single byte data Bit Naming Conventions The MicroBlaze architecture uses a bus and register bit naming convention in which the most significant bit MSB name incorporates zero 0 As the significance of the bits decreases across the bus the number in the name increases linearly so that a 32 bit vector has a least significant bit LSB name equal t
257. n interrupt acknowledge cycle the interrupting device jams a restart instruction onto the data bus which causes program execution to continue at one of eight hard coded locations Mode 1 is a hard vector interrupt with a single hard vector similar to the NMI but at a different location Mode 2 is a fully auto vectored interrupt mode In this mode the interrupt controller is actually distributed between the processor and the Z80 family peripherals During an interrupt acknowledge cycle the interrupting device places the low eight bits of the interrupt service routine address on the data bus The processor provides the upper eight bits from a dedicated register that is loaded by software NMI always has a higher priority than INT Multiple devices can be attached to either interrupt input using a wired or configuration Additionally in Mode 2 devices on the INT input can be daisy chained to provide additional interrupt priorities The INT input can be masked by software Motorola 68332 The 68332 has seven active low level sensitive interrupt request inputs IRQ1 to IRQ7 These inputs correspond to the seven interrupt request levels of the CPUS core Devices internal or external request service by activating a particular interrupt level If that level is not masked then the processor acquires the appropriate interrupt vector number and obtains the service routine address from a 256 location interrupt vector table indexed by the interrupt vector num
258. n per clock This configuration allows debugging of application code through either software based debugging resident monitor debugging or hardware based JTAG debugging March 2002 www xilinx com 17 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX MicroBlaze Bus Interfaces Configuration 4 Memory OPB to OPB Memory Interrupt Timer Controller Bridge Controller Controller Counter Ext memory Ext memory and WDT MicroBlaze CPU Core Data side OPB Instruction side OPB Instruction side LMB BRAM Memory Other OPB Controller Master Slave or Bridge Block RAM Figure 6 Configuration 4 OPB ILMB DOPB Purpose Use this configuration when your application requires more instruction and data memory than is available in the on chip BRAM Critical sections of instruction memory can be allocated to the faster ILMB BRAM to improve your application s performance The data side OPB is used for one or more external memory controllers and other peripherals such as UARTs timers general purpose I O additional BRAM and custom peripherals The OPB to OPB bridge is only required if the data side OPB needs access to the instruction side OPB peripherals such as for software based debugging Typical Applications e MPEG Decoder Communications Controller e Complex state machine for process control and other embedded applications e Set top boxes Characteristics Because of the extra
259. nal ARB_DBusEn is not an output of the Xilinx OPB Arbiter as the IPIF module internally gates the OPB Arbiter data bus with the enable signal The following signals listed in the IBM OPB Arbiter core are not supported e sleepReqg the FPGA implementation of the OPB bus will not support sleep modes 1580 FPGA implementation does not support scan 1580 FPGA implementation does not support scan 1580 FPGA implementation does not support scan 1880 scanGate FPGA implementation does not support scan 1880 scanln FPGA implementation does not support scan 1580 scanOut FPGA implementation does not support scan Parameter The width of many of the OPB Arbiter signals depends on the number of OPB masters in the Port design In addition when certain features are parameterized away the related input signals are unconnected and the related output signals are set to a constant values The dependencies Dependencies between the OPB Arbiter design parameters and signals are shown in Table 3 Table 3 Parameter Port Dependencies Name Affects Depends Relationship Description Design G1 NUM MASTERS G2 G8 04 G5 The width of the request and grant buses are set by the Parameters P1 P2 G7 number of masters in the design P6 P11 The only logic present in the OPB Arbiter design when NUM MASTERS 1 is the watchdog timer therefo
260. nals can have multi bit enable control or a single bit enable control on the bus This is specified with the ENABLE option Format wi CSET signal mysignal inout 0 31 ENABLE enable_value Where enable_value is SINGLE or MULTI SINGLE is the default value Refer to the HDL Design Considerations section for more information on designing 3 state signals at the HDL level ENDIAN Option The endianess of a signal is specified by the ENDIAN option Format CSET signal mysignal out A B ENDIAN endian value Where endian_value is BIG or LITTLE BIG is the default value INITIALVAL Option The driver val on unconnected input signals is specified by the INITIALVAL option Format CSET signal mysignal in INITIALVAL init value Where init_value is VCC or GND GND is the default value LEVEL Option The level sensitivity of an interrupt signal is specified by the LEVEL option Format CSET signal Interrupt out LEVEL level_value Where evel_value is HIGH or LOW TYPE Option The scope of a signal is set with the TYPE option Format CSET signal mysignal out TYPE type_value Where type_value is either EXTERNAL or INTERNAL By default only OPB and LMB signals are defined as INTERNAL All other signals are defined as EXTERNAL The BBD Black Box Description file is supplied by the IP provider and supplies input to the Platform Generator The BBD file manages the file
261. nce Manual can not occur and the WCOL flag is not supported All registers are accessed directly from the Xilinx OPB which is a subset of IBM s 64 bit OPB utilizing byte enables see IBM s 64 Bit On Chip Peripheral Bus document for details As shown in Figure 1 optional FIFOs can be implemented on both receive and transmit paths 152 www xilinx com v1 00b 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Serial Peripheral Interface SPI Design Specification XILINX Register SPI Module Module E Interrupt Regs pe 4 gt BRG SPI Ports Status Reg gt p Y SCK Control Reg d 5 8 mso s 8 gt MOSI Slave Sel 8 amp SS N Transmit Tx FIFO c System DTR SPISEL 4 lt Control Unit Figure 1 SPI Assembly Top level Block Diagram SPI Protocol with Automatic Slave Select Assertion This section describes the SPI protocol where Slave Select SS N is asserted automatically by the SPI Master device i e CR 24 0 This is not the default configuration but was the only mode of operation in the first specification of this device This operation follows closely the specification in Motorola 68HC11 Reference Manual For more deta
262. nd of the line Comments can be anywhere on the line Format Use the following format at the beginning of a peripheral definition SELECT ip type peripheral name Peripheral names are lower case The SELECT keyword signifies the beginning of a new peripheral Use the following format for assignment statements CSET type name valu Use the following format to end a peripheral definition END IP Type There are six types of IP e master Slave master slave e bus bridge e ip Use the following format for a master peripheral SELECT master peripheral name Use the following format for a slave peripheral SELECT slave peripheral name Peripheral names are in lower case Assignment Type There are two types of assignments attribute Signal Attribute Use the following format for attributes CSET attribute name value data type Attribute names are case sensitive The MPD syntax requires the attribute data type for VHDL This requirement will be eliminated in subsequent releases because Verilog does not require a data type for its parameters This will allow the MPD to be written generically without modification for a specific HDL language March 2002 www xilinx com 51 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Microprocessor Peripheral Definition Format Signal Use the following format for signals CSET signal name
263. ng diagram and the bits are described in Table 14 ISR Interrupt Status Register INTn 2 INTn 4 TRI T T T T INTn 1 INTn 3 INTn 5 INT1 INTO Table 14 Interrupt Status Register Bits Name Description Reset Value 0 INTn INTO Interrupt Input n Interrupt Input 0 0 to n lt w 1 0 Read Not active Write No action w 1 where w is DB width 1 Read Active Write SW interrupt 100 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Simple Interrupt Controller Specification Interrupt Pending Register IPR XILINX This is an optional register in the simple IntC and can be parameterized out of an implementation Reading the contents of this register indicates the presence or absence of an active interrupt signal that is also enabled Each bit in this register is the logical AND of the bits in the ISR and the IER If there are fewer interrupt inputs than the width of the data bus reading a non existing interrupt input will return zero The IPR is shown in the following diagram and the bits are described in Table 15 IPR Interrupt Pending Register INTn 2 INTn 4 T T INTn 1 INTn 3 ires INT1 Table 15 Interrupt Pending Register Bits Name Description Reset Value 0 INTn INTO Interrupt Input n Interrupt Input 0 0 to n lt w 1 0 Not active w 1 where wis DB width Active
264. nge 2 None std logic vector Address UART Lite Registers High C HIGHADDR Valid Address Range 2 1 std logic vector Address Target Family FAMILY Xilinx FPGA families virtex2 strings OPB Bus Width C OPB AWIDTH 32 32 integer OPB Data Bus Width C OPB DWIDTH 32 32 integer C CLK FREQ Clock frequency of the OPB system clock integer ex 125000000 125 000 00 integer driving the UART Lite peripheral in Hz 0 C BAUDRATE Baud rate of the UART Lite in bits per integer ex 9600 19 200 integer second 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers as listed at http www xilinx com legal htm other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 143 XILINX Table 1 UART Lite Parameters OPB UART Lite Specification Feature Description C DATA BITS Parameter Name The number of data bits in the serial frame Allowable Values integer 5 to 8 C USE PARITY Determines whether parity is used or not Integer 1 use parity 0 do not use parity C ODD PARITY If parity is used determines whether parity is odd or even integer 1 odd parity 0 even parity Default Value VHDL Type 8 inte
265. not running if this signal is held high 8 TSI DFPC JTAG data input to the target silicon from the tool 10 TSO DTOPC JTAG TSO signal that is an output from the target board silicon to the tool 220 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Index A address pipelining 41 addressable registers 70 Addressing 88 aligned transfers 35 ARB2BUS Data Mux 80 Arbitration Logic 80 ARM 93 Auto vectoring interrupt schemes 92 BEIF 39 big endian 211 Black Boxes 57 Block RAM 139 BRAM 139 Branches 9 bus locking 41 Bus Parking 89 byte enable devices 34 C cache fill 41 capture mode 195 Clear Interrupt Enables CIE 95 105 Clock and Power Management 89 combinational grant outputs 64 compare mode 194 CONFIGURATION 46 Control Register 71 Control Register REC 148 209 Control Register Bit Definitions 72 Control Register Logic 76 Control Status Register 0 TCSRO 186 198 Control Status Register 1 TCSR1 188 200 conversion cycles 34 39 CoreConnec 33 D defining local memory size 47 defining memory size 47 Delay Slots 9 Device Utilization 87 Dynamic bus sizing 34 dynamic bus sizing 33 dynamic priority arbitration 65 E edge generation schemes 94 EMC 113 EMC Control Register EMCCR 119 EMC I O signals 116 EMC parameters 114 Endianness 211 Exceptions 11 Execute 8 External Memory Controller 113 F Fetch 8 fixed lengt
266. o 31 Other Xilinx interfaces such as the PCT Core use the opposite convention in which a name with a 0 represents the LSB vector position Data Types and Endianness Hardware supported data types for MicroBlaze are word half word and byte The data organization for each type is shown in the following tables Table 0 1 Word Data Type Byte address n 1 2 3 Byte label 0 1 2 3 Byte significance MSByte LSByte Bit label 0 31 Bit significance MSBit LSBit Table 0 2 Half Word Data Type Byte address n 1 Byte label 0 1 Byte significance MSByte LSByte Bit label 0 15 Bit significance MSBit X LSBit Table 0 3 Byte Data Type Byte address n Byte label 0 Byte significance MSByte Bit label 0 7 Bit significance MSBit X LSBit 212 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Data Types and Endianness XILINX The following C language structure includes various scalars and character strings The comments indicate the value assumed to be in each structure element These values show how the bytes comprising each structure element are mapped into storage struct 1 int a Ox1112 1314 word long long b 0x2122 2324 2526 2728 double word char c 0x3132 3334 word char d 7 A B C D E F G array of bytes short e 0x5152 halfword int f 0x6162 6364 word
267. o gain access to all OPB slave devices e Device Control Register DCR interface Sharing of the I O pins on the module with the SDRAM controller IBM specification number v C12E0622 HSPLB MC The OPB Memory Controller provides an interface between the OPB and one to eight external banks of memory components such as the Intel StrataFlash or the IDT71V416S SRAM memory The controller supports OPB data bus widths of 8 to 128 bits and memory subsystem widths of 8 to 128 bits You can configure the controller to support page mode reads that can be up to six times faster than non page reads The in page detection logic is automatically configured out of the controller if page mode is not required The Flash memory controller is organized much like an SRAM interface This controller assumes that the Flash programming circuitry is built into the Flash components and that the command interface to the Flash is handled in software The controller provides basic read write control signals and the ability to configure the access times for read read in page write and recovery times when switching from read to write or write to read This controller supports the OPB V2 0 byte enable architecture Any access size up to the width of the OPB data bus is permitted Limitations may apply when the memory components limit the allowed transfer types such as memory devices configured in 16 bit or 32 bit mode with no byte enable support Certain features can
268. obal Interrupt Global Enable bit Enables all Enable individually enabled interrupts to be passed to the interrupt controller Q0 Not enabled 1 Enabled 1 31 Read 0 Unassigned Interrupt Signal Descriptions When the interrupt module is included up to seven unique interrupt conditions are possible depending upon whether the system is configured with FIFOs or not A system without FIFOs has 6 interrupts that are sent to the IPIF interrupt module where some are redundant as discussed below The IPIF interrupt module has a register that can enable each interrupt independently Bit assignment in the Interrupt register for a 32 bit databus is shown in Table 6 The interrupt register is read only and bits are cleared by writing a 1 to the bit s being cleared All bits are cleared upon reset Table 6 Interrupt Register Bit Definitions Bit assignment assumes 32 bit bus Reset Bit s Name Access Value Description 31 MODF Read Write 1 to clear 0 MODF Interrupt 31 is the Mode Fault Error Flag This interrupt is generated if the SS signal goes active while the SPI device is configured as a master This bit is set immediately by upon SS going active by a transition of the MODF status bit from low to high 30 SIv MODF Read Write 1 to clear MODF Interrupt 30 is the slave Mode Fault Error Flag This interrupt is generated if the SS signal goes activ
269. ode since AO always selects a byte March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 129 5 XILINX Example 3 This example shows the connection to 32 bit memory using 2 StrataFlash parts in x16 mode supports byte read but no byte write smallest data type that can be written is 16 bit data OPB External Memory Controller EMC Table 40 Variables for StrataFlash x16 mode Example Variable Value Definition BN 0 Memory bank number DN 0 to 1 Memory device number within a bank The memory device attached to the most significant bit in the memory subsystem is 0 device numbers increase toward the least significant bit MW 32 Width in bits of memory subsystem DW 16 Width in bits of data bus for memory device MAW 24 Width in bits of address bus for memory device AU 8 Width in bits of smallest addressable data word on the memory device AS 1 Address shift for address bus logo MW AU DW 8 HAW 32 Width of host address bus e g OPB or PLB in bits Table 41 Connection to 32 bit Memory using 2 StrataFlash Parts StrataFlash Signal DN Description EMC Signal MSB LSB MSB LSB 0 Data bus Mem DQ 0 15 DQ 15 0 Address bus Mem A 7 30 A 23 0 Chip Enable low true GND GND MEM 0 CE 2 0 Output Enable low true MEM OEN Write Enable low true MEM 0 Reset Po
270. of FPGAs you can also implement systems utilizing OPB devices that are fully OPB V2 1 compliant OPB Options Legacy Devices Previous to OPB V2 0 there was a single signaling protocol for OPB data transfers This protocol which is also present in OPB V2 0 and later specifications supports dynamic bus sizing through the use of transfer qualifiers and acknowledge signals The transfer qualifiers 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm All other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 www xilinx com 33 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Usage in FPGAs denote the size of the transfer initiated by the master and the acknowledge signals indicate the size of the transfer from the slave Devices that support this type of dynamic bus sizing are called legacy devices Byte enable Devices Starting with OPB V2 0 IBM introduced an optional alternate transfer protocol based on Byte Enables In the byte enable architecture each byte lane of the data bus has an associated byte enable signal For each transfer the byte enable signals indicate which byte lanes have valid data This eliminates the need for separate transfer qualifiers that indicate the transfer s
271. of interrupt inputs This attribute is automatically populated by the Platform Generator Format CSET attribute C NUM INTR INPUTS num integer Where num is an integer value C OPB AWIDTH Attribute The C NUM AWIDTH attribute defines the OPB address width This attribute is automatically populated by the Platform Generator Format CSET attribute C OPB AWIDTH num integer Where num is an integer value C OPB DWIDTH Attribute The C NUM DWIDTH attribute defines the OPB data width This attribute is automatically populated by the Platform Generator Format CSET attribute C OPB DWIDTH num integer Where num is an integer value This section provides naming conventions for OPB signal names These conventions are flexible to accommodate MicroBlaze and other systems that have more than one OPB and more than one OPB port per component For peripheral OPB ports the names must start with a capital letter and must be HDL VHDL or Verilog compliant As with any language VHDL and Verilog have certain naming rules and conventions that you must follow Global Ports The names for the global ports of a peripheral such as clock and reset signals are standardized The name for the clock signal is OPB and the reset signal is OPB_Rst You can use any name for other global ports such as the interrupt signal Master OPB Ports OPB V2 0 naming conventions should be followed for that part of the identifier foll
272. ollowing table illustrates the major embedded processor bus architectures used in Xilinx Comparison and lists some of their characteristics Each bus has different capabilities in terms of data transfer rates multi master capability and data bursting The use of a particular bus is dictated by the processor used the data bandwidth required in the application and availability of peripherals The OPB is a general purpose peripheral bus that can be effectively used in many design situations PLB Processor Local Bus IBM PLB Reference OPB On chip Peripheral Bus IBM OPB Reference OCM On chip Memory interface OCM Reference LMB Local Memory Bus Xilinx MicroBlaze Bus Interfaces DCR Device Control Register bus IBM DCR Reference 40 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Usage in Xilinx FPGAs XILINX Table 4 Comparison of buses used in Xilinx embedded processor systems CoreConnect Buses Other Buses Feature PLB OPB DCR OCM LMB Processor family 405 405 405 405 MicroBlaze MicroBlaze Data bus width 64 32 32 32 32 Address bus width 32 32 10 32 32 Clock rate MHz max 100 125 125 375 125 Masters max 8 16 1 1 1 Masters typical 2 8 2 8 1 1 1 Slaves max limited only by hardware resources 1 1 Slaves typical 2 6 2 8 1 8 1 1 Data rate
273. ontain unique master IDs Though the arbiter will still function properly in this circumstance a particular master will not have a priority level associated with it and therefore will never receive a grant if it issues a request This could cause the OPB to hang Therefore whenever the processor begins to modify the priority levels of the masters it first negates the PRV bit in the Control Register indicating to the arbitration logic that the Priority Register values should not March 2002 www xilinx com 73 1 800 255 7778 XILINX On Chip Peripheral Bus OPB Arbiter Design Specification be used in bus arbitration In this case the arbitration logic will use the masters IDs as their priority level until the PRV bit has been asserted The OPB Arbiter Control Register can be accessed from the OPB bus only if the OPB Arbiter is parameterized to support a processor interface C PROC INTRFCE 1 OPB Arbiter Priority Registers Each Priority Register holds the master ID of the OPB master at that priority level as shown in Table 8 Each master s relative priority is determined by its ID s location within these registers The LVLO Priority Register holds the ID of the master with highest priority level 0 the LVL 1 Priority Register holds the ID of the master with the next highest priority level 1 and so on TheLVL C NUM MASTERS 1 Priority Register holds the ID of the master with lowest priority These registers are reset to va
274. ops the current execution to handle the interrupt request MicroBlaze branches to address 0x00000010 and uses the General Purpose Register 14 to store the address of the instruction that was to be executed when the interrupt occurred It also disables future interrupts by clearing the Interrupt Enable flag in the Machine Status Register setting bit 30 to 0 in MSR The instruction located at the address where the current PC points to is not executed Interrupts do not occur if the BIP bit in the MSR register is active Interrupts Exceptions and Breaks independent of the BIP bit value in MSR Interrupts equal to 1 Equivalent Pseudocode r14 PC PC 0x00000010 MSR IE lt 0 10 March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 The MicroBlaze Architecture XILINX Exceptions When an exception occurs MicroBlaze stops the current execution to handle the exception MicroBlaze branches to address 0x00000008 and uses the General Purpose Register 17 to store the address of the instruction that was to be executed when the exception occurred The instruction located at the address where the current PC points to is not executed Equivalent Pseudocode rl7 lt PC lt 0x00000008 Breaks There are two kinds of breaks e Software internal breaks Hardware external breaks Software Breaks To perform a software break use the brk and brki instructions Refer to the Instructio
275. or all interrupt inputs In either case some interrupt controllers allow you to program the polarity of the interrupt inputs and whether they are level or edge sensitive Some may allow the priority of an interrupt to be programmed as well Some popular embedded processors and their associated interrupt controllers mechanisms are described in the following paragraphs Intel 8051 As in many single chip solutions the interrupt controller for the 8051 is embedded into the functionality of the CPU and on chip peripherals The 8051 micro controller utilizes a hard vector approach for handling interrupts There is a unique hard vector address associated with external interrupt 0 timer 0 external interrupt 1 timer 1 and the serial port You can program interrupts for high or low priority There is an interrupt enable bit for each interrupt source as well as a bit for enabling or disabling all interrupts You can program the two external interrupt inputs to be either edge sensitive falling edge or level sensitive active low Zilog Z80 The Z80 supports both hard vector and auto vector modes for interrupts The Non Maskable Interrupt NMI input utilizes a hard vector and cannot be disabled by software This interrupt is an active low level sensitive interrupt The other interrupt input INT which is also an active low level sensitive interrupt supports three different modes Mode 0 provides compatibility with the 8080 microprocessor During a
276. ors OPB Peripherals OPB External Memory Controller EMC March 2002 Summary This document provides the design specification for the External Memory Controller EMC Intellectual Property IP solution This document applies to the following peripherals opb memcon v1 00a Introduction This specification defines the architecture and interface requirements for the EMC This module supports data transfers between the On chip Peripheral Bus OPB and external memory devices such as SRAM and Flash devices Example devices for use with this controller are the Integrated Device Technology Inc IDT71V416S SRAM and the Intel 28F128J3A StrataFlash Memory Devices The EMC module is organized to be an OPB slave only device which differs from the IBM EBC specification The Xilinx EMC design allows you to tailor the EMC to suit your application by setting certain parameters to enable or disable features Quick links are provided to the following sections EMC Parameters EMC Signals EMC Address Map and Register Descriptions Connecting to Memory SRAM and SirataFlash EMC Overview Features The EMC is a soft IP core designed for Xilinx FPGAs and has the following features Parameterized for up to a total of eight memory SRAM Flash banks Separate base addresses and address range for each bank of memory Separate Control Register for each bank of memory to control memory mode OPB V2 0 bus interface with byte enable support Suppo
277. othing 1 Clear the transmit FIFO Address Map UART BASE ADDRESS 0 Read from Receive FIFO JTAG UART BASE ADDRESS 4 Write to transmit FIFO UART BASE ADDRESS 8 Read from Status Register JTAG UART BASE ADDRESS 12 Write to Control Register Interrupts If interrupts are enabled an interrupt is generated when one of the following conditions is true 1 When there exists any valid character in the receive FIFO the interrupt stays active until the receive FIFO is empty 2 When the transmit FIFO goes from not empty to empty such as when the last character in the transmit FIFO is transmitted the interrupt is only active one clock cycle March 2002 www xilinx com 209 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB JTAG UART Specification Design Device Utilization and Performance Benchmarks Implementation The following table shows approximate resource utilization and performance benchmarks for the OPB JTAG The estimates shown not guaranteed and can vary with FPGA family and speed grade implementation parameters user timing constraints and implementation tool version Only parameters that affect resource utilization are shown in the following table Table 5 OPB JTAG UART Performance and Resource Utilization Benchmarks Virtex 2V1000 5 Parameter Device fax Values Resources MHz Address AW Flip 4 input fax Bits in
278. ow if picoseconds Data Sheet previous access was Write of particular 6 Memory Device Notes 3 values for memory banks 0 to 7 4 This design can accommodate up to 8 Banks of Flash and or SRAM The address range generics are designated as MEMO BASEADDR C MEM1 BASEADDR C MEMO HIGHADDR MEM1 HIGHADDR etc 5 Address range specified by C BASEADDR and HIGHADDR must be a power of 2 and gt 0 01 C MEMx BASEADDR and MEMx HIGHADDR must be a power of 2 and less than or equal to the OPB address space 6 No default value is specified for C BASEADDR and HIGHADDR AND MEMx BASEADDR MEMx HIGHADDR to insure that the actual value is set if the value is not set a compiler error is generated These generics must be a power of 2 and encompass the memory size for C MEMx BASEADDR C MEMx HIGHADDR 7 Write enable low time is the maximum of C WR ADDR TO OUT FAST SLOW PS and C WR MIN PULSE WIDTH 8 As specified by the memory device data sheet March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 115 XILINX EMC Signals Table 27 I O Signals OPB External Memory Controller The I O signals for the are listed in Table 27 Signal Name Interface I O Description OPB_Clk OPB OPB Clock OPB Rst OPB Reset OPB 0 OPB AWIDTH 1 OPB OPB
279. owing the last underscore in the name 54 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Microprocessor Peripheral Definition Format XILINX OPB Master Outputs For interconnection to the OPB all masters must provide the following outputs for each connection to the OPB Mn ABus Mn BE Mn busLock Mn DBus Mn request Mn RNW Mn select Mn segAddr Where Mn is a meaningful name or acronym for the master output An additional requirement on Mn is that it must not contain the string OPB upper or lower case or mixed case so that master outputs are not confused with bus outputs IM request Bridge request DMAE request O20B request OPB Master Inputs For interconnection to the OPB all masters must provide the following inputs for each connection to the OPB nOPB DBus nOPB errAck nOPB MGrant nOPB retry nOPB timeout nOPB xferAck Where nOPB is a meaningful name or acronym for the master input An additional requirement on nOPB is that the last three characters must contain the string OPB upper or lower case or mixed case IOPB DBus DOPB DBus OPB DBus 1 OPB DBus Slave OPB Ports OPB V2 0 naming conventions should be followed for that part of the identifier following the last underscore in the name OPB Slave Outputs For interconnection to the OPB all slaves must provide the fol
280. peak 1600 MB s 500 MB s 500 MB s 500 MB s 500 MB s Data rate typical 533 MB s 167 MB s 100 MB s 333 MB s 333 MB s Concurrent read write Yes No No No No Address pipelining Yes No No No No Bus locking Yes Yes No No No Retry Yes Yes No No No Timeout Yes Yes No No No Fixed burst Yes No No No No Variable burst Yes No No No No Cache fill Yes No No No No Target word first Yes No No No No FPGA resource usage High Medium Low Low Low Compiler support for Yes Yes No Yes Yes load store Notes 1 Maximum clock rates are estimates and are presented for comparison only The actual maximum clock rate for each bus is dependent on device family device speed grade design complexity and other factors 2 Peak data rate is the maximum theoretical data transfer rate at the clock rate shown for each bus 3 The typical data rates are intended to illustrate data rates that are representative of actual system configurations The typical data is highly dependent on the application software and system hardware configuration 4 Assumes primarily cache line fills minimal read write concurrency 66 7 bus utilization 5 Assumes minimal use of sequential address capabilities and 3 clock cycles per OPB transfer 6 The OCM controller operates at the PPC405 core clock rate but its data transfer rate is limited by the access time of the on chip memory The typical data rate assumes 66 7 bus utilization 7 Assumes 66 7 bus uti
281. pecifications for OPB Usage in Xilinx developed OPB Devices Xilinx developed OPB devices adhere to the following OPB usage rules The width of the OPB data buses and address buses is 32 bits Note that some peripherals may parameterize these widths but currently only 32 bit buses are supported Peripherals that are smaller than 32 bits can be attached to the OPB with a corresponding restriction in addressing For example an 8 bit peripheral at base address A can be attached to byte lane 0 but can only be addressed at A A 4 A 8 etc OPB devices masters and slaves are byte enable devices These devices do not support the legacy data transfer signals and therefore do not support dynamic bus sizing OPB masters do not mirror data to unused byte lanes See Figure 1 for the byte lane usage for aligned transfers OPB devices masters and slaves are required to output logic zero when they are inactive This eliminates the need for the Mn DBusEn and SIn DBusEn signals external to the master or slave The enable function is still implemented within the device byte enables and the least significant address bits will be driven by all masters and will contain consistent information Examples of byte lane usage for aligned transfers are shown below in Figure 1 Data Bus Data Bus Data Bus Data Bus 0 7 0 7 0 7 0 7 8 15 E E 8 15 E 8 15 E 1623 o 1623 o 1623 o 1623 o 24 31 24 31 24 31 24 31 word transfer halfword transf
282. ports a hard vector mechanism but the vector address can be programmed to be in a non cachable or cachable memory segment An external interrupt controller could provide additional interrupt inputs and a priority encoding scheme but there is no mechanism for providing auto vectoring As a result the job of prioritizing interrupts and branching to the proper interrupt service routine is done by the software ARM The ARM architecture provides two external interrupt inputs FIQ and IRQ FIQ is higher priority than IRQ but both can be masked by software Each interrupt has a hard vector associated with it and its own status register and subset of general purpose registers An external interrupt controller could provide additional interrupt inputs with priority but there is no auto vectoring capability IBM PowerPC 405GP Universal Interrupt Controller UIC The UIC for the PowerPC 405GP provides 19 internal and 7 external interrupts Eighteen of the internal interrupts are active high level sensitive The other internal interrupt is edge sensitive and active on the rising edge The seven external interrupts are programmable as to polarity and sensitivity Each interrupt source can be programmed to source the critical or non critical input to the 405 core All interrupts can be masked and the current interrupt state can be read by the processor The UIC supports prioritized auto vectoring for the critical interrupts either through a vector table or the
283. put GPIO Specification March 2002 Su mmary This document describes the specifications for a general purpose input output core for the OPB bus This document applies to the following peripherals opb gpio v1 00a Overview The GPIO General Purpose Input Output is a 32 bit peripheral that attaches to the OPB On chip Peripheral Bus and has the following features Features OPB V2 0 bus interface with byte enable support Supports 32 bit 16 bit and 8 bit bus interfaces Each GPIO bit dynamically programmable as input or output Number of GPIO bits configurable up to size of data bus interface Can be configured as inputs only to reduce resource utilization GPIO Organization The GPIO is a simple peripheral consisting of two registers and a multiplexer for reading register contents and the GPIO signals The GPIO block diagram is shown in the following figure GPIO TRI GPIO WIDTH GPIO DATA OPB DBUS 2 GPIO IO GPIO WIDTH GPIO DBUS Figure 1 GPIO Block Diagram 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm All other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 www xilinx com 177 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX
284. put For PWM Mode and must be 0 and C GENO and GEN1 ASSERHT must be 1 23 Timer1 Interrupt Indicates that the condition for an interrupt on this timer has occurred If the timer mode is capture and the timer is enabled this bit indicates a capture has occurred If the mode is generate this bit indicates the counter has rolled over Must be cleared by writing a 1 Read 0 No interrupt has occurred 1 Interrupt has occurred Write 0 No change in state of T1INT 1 Clear T1INT clear to 07 24 Enable Timer1 0 Disable timer counter halts 1 Enable timer counter runs 25 ENIT1 Enable Interrupt for Timer1 Enables the assertion of the interrupt signal for this timer Has no effect on the interrupt flag in TCSR1 0 Disable interrupt signal 1 Enable interrupt signal March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 201 XILINX OPB Timer Counter Specification Table 4 Control Status Register 1 TCSR1 Continued Bits Name Description Reset Value 26 LOAD1 Load Timer1 0 0 No load 1 Loads timer with value in TLR1 27 ARHT1 Auto Reload Hold Timer1 0 When the timer is in generate mode this bit determines whether the counter reloads the generate value and continues running or holds at the termination value
285. rameter to be 2WDT CLOCKS clock cycles where WDT CLOCKS is any integer from 8 to 31 The WDT interval is set at FPGA configuration time and cannot be modified dynamically through a control register The state of the WDT is given by the WDS bit in the TWCSRO register If the WDT interval expires while the WDS bit is 1 the WDT reset signal is asserted An interrupt is provided when the WDS bit is set so that the software can clear the bit before the second expiration of the WDT The WDS bit is cleared by writing a 1 to it Writing a 0 to the WDS bit has no effect The WDT state diagram is shown in the following figure www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Timebase WDT Specification Implementation Summary XILINX count WDT interval WDT expired once WDS cleared by software interrupt count WDT interval Reset set WDT reset to 1 Figure 4 WDT State Diagram Table 6 Summary of Timebase WDT Core I O set WDS to 1 generate WDT Signal Interface yo Description Page OPB CIk OPB OPB Clock OPB Rst OPB OPB Reset OPB ABus 0 31 OPB OPB Address Bus BE 0 3 OPB Byte Enables OPB DBus 0 31 OPB OPB Data Bus OPB RNW OPB OPB Read Not Write OPB select OPB OPB Select seqAddr OPB OPB Sequential Address TBWDT DBus 0 31 OPB TBWDT Data Bus TBW
286. ration within the FPGA Full duplex operation e Works with times 8 bit data characters in default configuration The default mode implements manual control of the SS output via data written to the slave select register which appears directly on the SS output when the master is enabled This mode can be used only with external slave devices In addition an optional operation where the SS output is toggled automatically with each 8 bit character transfer by the master device internal state machine can be selected via a bit in the command register for SPI master devices Supports back to back character transmission and reception Master and slave SPI modes supported Multi master environment supported implemented with 3 state drivers and requires software arbitration for possible conflict e MMulti slave environment supported automatic generation of additional master slave select signals e Continuous transfer mode for automatic scanning of a peripheral Supports maximum clock rates of up to one half the OPB clock rate both master and slave modes when both SPI devices are in the same FPGA part routing constraints of SPI bus signals must be incorporated in map par process In anticipation of remote master operation slaves operation supports one fourth the OPB clock rate artifact of asynchronous SCK clock relative to the OPB clock which requires clock synchronization Parameterizable baud rate generator Programmable
287. rdware Reference Guide 1 800 255 7778 XILINX Microprocessor Hardware Specification MHS Format processor The MicroBlaze processor s interrupt is level sensitive Consequently any other level sensitive interrupt line from a peripheral can be connected directly However if the peripheral s interrupt line is edge sensitive then you must use the interrupt controller If you connect an edge sensitive signal to a level sensitive signal you may miss an interrupt Use the following format to set interrupt signals CSET signal mysignal interrupt bus PRIORITY n Power Signals Power signals are signals that are constantly driven with either VCC or GND Use the following format to set power signals CSET signal mysignal power signal In this example power signal is either net vcc or gnd Platform Generator expands net vcc or net gnd to the appropriate vector size 48 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide 2002 Summary Overview Load Path Xilinx Embedded Processors MicroBlaze Microprocessor Peripheral Definition Format This document describes the Microprocessor Peripheral Definition MPD format for MicroBlaze The Platform Generator allows you to partition your peripherals into one or more reusable modules The MPD file provides peripheral information to the Platform Generator and has the following characterist
288. re P17 P18 many parameters and signals are unconnected in this case If C OPB DWIDTH 8 and C PARK 1 and PROC INTRFCE 1 then C NUM MASTERS must be 4 because there is only 2 bits for the park master id in the Control Register G2 DYNAM PRIORITY G1 Unconnected if C NUM MASTERS 1 G3 C REG GRANTS G1 Unconnected if C NUM MASTERS 1 G4 PARK G1 G1 Unconnected if C NUM MASTERS 1 G5 C PROC INTRFCE G1 G6 G8 G1 Unconnected if C NUM MASTERS 1 G11 P1 P2 6 10 G6 BASEADDR G1 G5 Unconnected if C PROC INTRFCE 0 or G11 C NUM MASTERS 1 Range specified by BASEADDR and HIGHADDR must be at least Ox1FF G7 C_OPB_DWIDTH G1 P1 P8 G1 G5 Unconnected if C_PROC_INTRFCE 0 or C_NUM_MASTERS 1 G8 C_OPB_AWIDTH P6 P7 G1 G5 Unconnected if C_PROC_INTRFCE 0 or C_NUM_MASTERS 1 G9 C DEV BLK ID G1 G5 Unconnected if C PROC INTRFCE 0 or C NUM MASTERS 1 G10 C DEV MIR ENABLE G1 G5 Unconnected if C PROC INTRFCE 0 or C NUM MASTERS 1 G11 HIGHADDR G1 G5 Unconnected if C PROC INTRFCE 0 or G6 NUM MASTERS 1 Range specified by BASEADDR and HIGHADDR must be at least Ox1FF March 2002 www xilinx com 69 1 800 255 7778 XILINX On Chip Peripheral Bus OPB Arbiter Design Specification Table 3 Parameter Port Dependencies Continued Name Affects Depends Relationship Description Signals P1 ARB 0 DWIDTH 1 G1 G5 Width varies with the size of the OPB Data b
289. results of the park and lock logic The OPB Arbiter can be parameterized so that the grant signals are either registered outputs are combinational outputs Registering the grant signals allows for higher OPB clock frequencies at the cost of a 1 cycle arbitration latency Combinational grant outputs allow the grant signals to be asserted within the same clock cycle as the Master request signals however the overall clock frequency of the OPB will be affected Basic OPB arbitration using registered grant outputs is shown in Figure 2 Watchdog Timer The watchdog timer generates the OPB timeout signal within the 16th cycle following the assertion of OPB select if there is no response from a slave OPB xferAck or OPB retry and if toutSup is not asserted by an addressed slave device to suppress the timeout This logic is always present in the OPB Arbiter design Upon assertion of OPB timeout the master device which initiated the transfer cycle must terminate the transfer by deasserting Mn select in the cycle following the assertion of OPB timeout as shown in Figure 21 If OPB busLock is not asserted the OPB Arbiter will perform a bus arbitration in the cycle in which select is deasserted If OPB busLock is asserted the requesting master retains control of the OPB but must still deassert Mn select following the assertion of OPB timeout for at least one cycle If OPB xferAck or OPB retry are asserted in the 16th cycle following the assertion of
290. revious Data Valid XILINX Data Valid Mem DQ I Data In Valid Figure 34 Timing Waveform for SRAM Write Cycle Table 32 SRAM Parameter Description Symbol READ CYCLE 1 tro Read Cycle Time taa Address Access Time tacs Chip Select Access Time Output Enable Low to Output Valid toH Output Hold from Address Change ipe Byte Enable Low to Output Valid WRITE CYCLE Write Cycle Time taw Address Valid to End of Write tew Chip Select Low to End of Write tgw Byte Enable Low to End of Write Address Set up Time Address Hold from End of Write Write Pulse Width Data Valid to End of Write Data Hold Time tow Write Enable High to Output Low Z Notes 1 Refer to IDT71V416S Data Sheet for specific timing parameters 2 WEN is HIGH for Read Cycle 3 Address must be valid prior to or coincident with the later CEN BEN transition LOW otherwise tAA is the limiting parameter 4 Write Cycle Timing is WEN controlled March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 123 XILINX OPB External Memory Controller EMC Figure 35 and Figure 36 illustrate the basic read and write functions for StrataFlash Table 33 defines the symbols used in the figures for StrataFlash eM 9020 gt MEM A 0 2 Addre
291. riority arbitration the OPB Arbiter can be put in a fixed priority arbitration mode by negating the DPE bit As a result both priority modes are available and supported If the OPB Arbiter has been parameterized to not support bus parking the PEN bit is set to 0 The PENRW bit is then set to 0 and reflects the fact that the PEN bit is read only by the processor core If the OPB Arbiter has been parameterized to support bus parking the PEN bit can be read from and written to by the processor The PENRW bit is set to 1 and reflects the fact that the bus parking mode of the arbiter can be controlled by the PEN PMN and PID bits of the Control Register Although the OPB Arbiter has been parameterized to support bus parking bus parking can be disabled by negating the PEN bit Also if the OPB Arbiter has been parameterized to not include a processor or OPB slave interface the Control Register is not accessible As a result the parking mode will be set to park on the last master which is the default value in the Control Register of the PMN bit In order to park on the master whose ID is contained in the Control Register the OPB Arbiter must be parameterized to support a processor interface so that the Control Register can be set up appropriately Since the processor will require multiple bus cycles to update the masters priority levels in the Priority Registers there will exist some period of time in which the Priority Registers will not c
292. rite 0 Local loopback mode Enables local loopback operation and is functional only in master mode 70 Normal operation 71 Loopback mode The transmitter output is internally connected to the receiver input The receiver and transmitter operate normally except that received data from remote slave is ignored Note that the interrupt enable bit which resides in the this bit position of the 68HC11 specification resides in the interrupt enable register in this implementation see exceptions 30 SPE Read Write 0 SPI System Enable select bit Setting this bit high enables the SPI devices as noted below Q SPI System OFF Both master and slave outputs are in 3 state and slave inputs ignored 1 SPI System ON Master outputs active e g MOSI and SCK in idle state and slave outputs will become active if SS becomes asserted Master will start transfer when transmit data is available 29 MSTR Read Write if 0 MSTR Setting this bit configures the SPI master slave device as a slave or master if that option option is is implemented via parameters If slave implemented only option is implemented then this bit is Read Only if fixed to 0 slave only 70 Slave configuration option is 1 Master configuration implemented 28 CPOL Read Write 0 Clock Polarity select bit Setting this bit defines clock polarity Q Active high clock SCK idles low e 1 Active low clock idles high
293. rol Register Bus It can be used in embedded PowerPC systems Virtex ll PRO devices and in MicroBlaze soft processor systems There are currently two versions of the Simple Interrupt Controller OPB IntC OPB interface IntC DCR interface In this document IntC and Simple IntC are used interchangeably to refer to functionality or interface signals that are common to all variations of the Simple Interrupt Controller However when its necessary to make a distinction the interrupt controller is referred to as OPB IntC or DCR IntC Features A Simple Interrupt Controller has the following features Modular design provides a core interrupt controller functionality that is instantiated within a bus interface design currently the OPB and DCR buses are supported e OPB V2 0 bus interface with byte enable support IBM SA 14 2528 01 64 bit On chip Peripheral Bus Architecture Specifications Version 2 0 e Supports data bus widths of 8 bits 16 bits or 32 bits for OPB interface Number of interrupt inputs is configurable up to the width of the data bus Easily cascaded to provide additional interrupt inputs e Interrupt Enable Register for selectively disabling individual interrupt inputs Master Enable Register for disabling the interrupt request output Each input is configurable for edge or level sensitivity edge sensitivity can be configured for rising or falling level sensitivity can be active high or low Automa
294. rtan2e currently used virtex virtexe virtex2 virtex2pro C Y Row placement directive not Integer Any valid row value for the selected currently used target family C X Column placement directive Integer Any valid column value for the selected not currently used target family C U SET User set for grouping not String intc currently used BASEADDR Base address for accessing the Std Logic Vector Any valid 32 byte boundary address for IntC registers the IntC instance 1 C HIGHADDR Upper address value of the Std Logic Vector Any valid address for the IntC instance memory map entry for the IntC Used in conjunction with C BASEADDR to determine the number of upper address bits to use for address decoding that is at least 32 bytes 8 words greater than C BASEADDR NUM INTR INPUTS Number of interrupt inputs Integer 1 up to the width of the data bus C KIND OF INTR Type of interrupt for each input X none 1 edge 0 level Std Logic Vector A little endian vector the same width as the data bus containing a 0 or 1 in each position corresponding to an interrupt input C KIND OF EDGE Type of each edge sensitive input X 1 rising 0 falling Std Logic Vector A little endian vector the same width as the data bus containing a 0 or 1 in each position corresponding to an interrupt input C KIND OF LVL Type of each level sensitive inpu
295. rts 128 bit 64 bit 32 bit 16 bit and 8 bit bus interfaces Supports memory width of 128 bits 64 bits 32 bits 16 bits or 8 bits Memory width is independent of OPB bus width memory width must be less than or equal to OPB bus width Configurable wait states for read write read in page read recovery before write and write recovery before read Optional faster access for in page read accesses page size 8 bytes System clock frequency of up to 133 MHz 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm All other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 www xilinx com 113 MicroBlaze Hardware Reference Guide 1 800 255 7778 5 XILINX Parameters OPB External Memory Controller EMC EMC Background The EMC implements the hardware and software functionality of the IBM External Bus Controller operating as a slave on the OPB The EMC module receives instructions from the OPB to read and write to external SRAMs and Flash The implementation does not include the features of the External Master Interface as described in the IBM External Bus Controller Functional Specification v C12E0623 Additional features that are not implemented are as follows Attachment of an external master device t
296. rupt Controller Organization The Simple IntC is organized into the following three functional units Interrupt detection and request generation Programmer registers Bus interface Interrupt Detection Interrupt detection can be configured for either level or edge detection for each interrupt input If edge detection is chosen synchronization registers are also included Interrupt request generation is also configurable as either a pulse output for an edge sensitive request or as a level output that is reset when the interrupt is acknowledged 94 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Simple Interrupt Controller Specification XILINX Programmer Registers The interrupt controller contains the following programmer accessible registers Interrupt Status Register ISR is a read write register that when read indicates which interrupt inputs are active pre enable bits Writing to the ISR allows software to generate interrupts until the HIE bit has been enabled nterrupt Pending Register IPR is a read only register that provides an indication of interrupts that are active and enabled post enable bits The IPR is an optional register in the simple IntC and can be parameterized away to reduce FPGA resources required by an IntC e Interrupt Enable Register IER is a read write register whose contents are used to enable selected interrupts nterrupt Acknowledge Regist
297. s NE Data L VOU d x Address 0 lt Data Figure 2 Write Cycle 2 3 4 5 6 x Address1 X Address2 X A Data1 x Data2 b L X Address1 X Address2 Ly Yt March 2002 MicroBlaze Hardware Reference Guide OPB 2 Controller Design Specification Clock Handling XILINX Since ZBT memories are clocked and all timing on signals to the memories is referencing the ZBT clock careful handling of the clock is important Since all signals to the ZBT are driven from the OPB_CIk the ZBT clock must be synchronized to the OPB_CIk You can do this with a DLL as shown in Figure 3 The controller has a generic C_EXTERNAL_DLL that specifies if the peripheral implements the DLL If there is more than one ZBT controller in a design the number of DLLs can exceed the number of available DLLs Consequently a more centralized handling of the clocks is required In this case one DLL synchronizes all ZBT clocks and each of the controllers must inhibit the implementing of the DLL C EXTERNAL 1 This centralized DLL drives all ZBT clocks and requires that the loads on each of the ZBT clocks is equal Figure 3 Clock Synchronization EXTERNAL DLL 0 DLL OPB Os adn ZBT MEMORY pcikfb clkO ZBT Clk Load1 Load2 ZBT Clk Load2 ZBT_Clk_fb X March 2002 www xilinx com MicroBlaze Hardware Refer
298. s effect one clock cycle after executing the MTS instruction Any value written to bit O is discarded T T CC Reserved BIP C IE BE Table 5 Machine Status Register MSR Bits Name Description Reset Value 0 CC Arithmetic Carry Copy 0 Copy of the Arithmetic Carry bit 29 Read only 1 27 Reserved 28 BIP Break in Progress 0 0 No Break in Progress 1 Break in Progress Source of break can be software break instruction or hardware break from Ext Brk or Ext NM Brk pin March 2002 www xilinx com MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX The MicroBlaze Architecture Table 5 Machine Status Register MSR Continued Bits Name Description Reset Value 29 C Arithmetic Carry 0 0 No Carry Borrow 1 Carry No Borrow 30 IE Interrupt Enable 0 0 Interrupts disabled 1 Interrupts enabled 31 BE Buslock Enable 0 0 Buslock disabled on data side OPB 1 Buslock enabled on data side OPB Buslock Enable does not affect operation of ILMB DLMB or IOPB Pipeline This section describes the MicroBlaze pipeline architecture Pipeline Architecture The MicroBlaze pipeline is a parallel pipeline divided into three stages e Fetch Decode e Execute In general each stage takes one clock cycle to complete Consequently it takes three clock cycles ignoring any delays or stalls for the instruction to complete cycle 1 cycle 2 cycle 3
299. s empty reading this register cannot be used to determine if the FIFO is empty An attempt to write to this register does not yield an acknowledgement but rather an OPB timeout Table 13 shows specifics of the data format Table 13 Transmit FIFO Occupancy Register Bits Bit assignment assumes 32 bit bus Reset Bit s Name Access Value Description 24 Reserved Read 0x0 Reserved 27 28 Occupancy Read Bit 4 is the MSB The binary value plus 1 31 Value yields the occupancy Receive FIFO Occupancy Register Rc FIFO OCY This field contains the occupancy number greater than one for the Receive FIFO when the SPI assembly is configured with FIFOs The actual occupancy is the binary value plus 1 This register is read only and does not exist when the assembly is configured without FIFOs The Receive FIFO Empty Status Bit is the only reliable way to determine if the FIFO is empty reading this register cannot be used to determine if the FIFO is empty An attempt to write to this register does not yield an acknowledgement but rather an OPB timeout Table 14 shows specifics of the data format Table 14 Receive FIFO Occupancy Register Bits Bit assignment assumes 32 bit bus Reset Bit s Name Access Value Description 24 Reserved Read 0x0 Reserved 27 28 Occupancy Read Bit 4 is the MSB The binary value plus 1 31 Value yields the occupancy www xilinx com v1 00b 1 800 255 7778
300. s a simple alternative to this problem and is easier to implement in an FPGA Write Mirroring and Read Steering Another consequence of supporting devices smaller than the bus size is write mirroring and read steering In the OPB specification devices smaller than the bus size are always left justified aligned toward the most significant side of the bus so that the byte lanes associated with the smaller devices are easily determined For example a byte wide peripheral is always located on the most significant byte of the bus The peripheral writes and reads data using this byte lane You can simplify the design of OPB masters by using a byte enable only no write mirroring architecture A small degree of added complexity is required for peripherals that are smaller than the bus size if OPB masters do not mirror data Ideal FPGA Implementation of OPB based System The ideal FPGA implementation of an OPB based system has the following features Requires no conversion cycles e Uses only the byte enable architecture as specified in the OPB specification Does not require masters to mirror write data These characteristics help determine how Xilinx developed OPB devices are implemented The detailed specifications that describe how the OPB is used in Xilinx intellectual property are provided in the next section 34 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Usage in Xilinx FPGAs XILINX S
301. s at the top level to ensure that the inout ports are always associated to the IOBUF Inout ports are currently defined at the top level since the only internal signals are those defined as an input or an output There are no inout signals defined internally that need a BUFT It is important to note that the 3 state enables all active low to allow a direct connection to the OBUFT of the IOBUF www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Xilinx Embedded Processors OPB Peripherals On Chip Peripheral Bus OPB Arbiter Design Specification XILINX March 2002 Su mmary This document provides the design specification for the On Chip Peripheral Bus OPB Arbiter This document applies to the following peripherals opb arbiter v1 02c Introduction The OPB Arbiter design described in this document incorporates the features contained in the IBM On chip Peripheral Bus Arbiter Core manual version 1 5 for 32 bit implementation This manual is referenced throughout this document and is considered the authoritative specification Any differences between the IBM OPB Arbiter implementation and the Xilinx OPB Arbiter implementation are explained in the Specification Exceptions section The Xilinx OPB Arbiter design allows you to tailor the OPB Arbiter to suit your application by setting certain parameters to enable disable features In some cases setting these parameters may cause the Xi
302. s is shown in Figure 1 Byte address n n1 2 3 Byte label 0 1 2 3 Word Byte significance MSByte LSByte Bit label 0 31 Bit significance MSBit LSBit Byte address n n1 Byte label 9 1 Halfword Byte significance MSByte LSByte Bit label 0 15 Bit significance MSBit LSBit Byte address n Byte label 0 Byte Byte significance MSByte Bit label 0 7 Bit significance MSBit LSBit Figure 1 Big Endian Data Types Registers of the UART Lite Information on the following registers used in assembly language programming are described in this section Receive FIFO Read character from Receive FIFO Transmit FIFO Write character into Transmit FIFO Status Read from Status Register Control Write to Control Register Figure 2 UART Lite Register Set March 2002 www xilinx com 145 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Status Register STATREG The Status register contains the status of the receive and transmit FIFO if interrupts are enabled and if there are any errors Table 3 Status Register OPB UART Lite Specification Bits 0 23 Name Reserved Description Not used Reset Value 24 PAR ERROR Parity Error Indicates that a parity error has occurred since the last time the status register was read If the UART is configured without any parity handling this bit will always
303. s not assume any liability arising out of the application or use of any product described or shown herein nor does it convey any license under its patents copyrights or maskwork rights or any rights of others Xilinx Inc reserves the right to make changes at any time in order to improve reliability function or design and to supply the best product possible Xilinx Inc will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products Xilinx Inc devices and products are protected under one or more of the following U S Patents 4 642 487 4 695 740 4 706 216 4 713 557 4 746 822 4 750 155 4 758 985 4 820 937 4 821 233 4 835 418 4 855 619 4 855 669 4 902 910 4 940 909 4 967 107 5 012 135 5 023 606 5 028 821 5 047 710 5 068 603 5 140 193 5 148 390 5 155 432 5 166 858 5 224 056 5 243 238 5 245 277 5 267 187 5 291 079 5 295 090 5 302 866 5 319 252 5 319 254 5 321 704 5 329 174 5 329 181 5 331 220 5 331 226 5 332 929 5 337 255 5 343 406 5 349 248 5 349 249 5 349 250 5 349 691 5 357 153 5 360 747 5 361 229 5 362 999 5 365 125 5 367 207 5 386 154 5 394 104 5 399 924 5 399 925 5 410 189 5 410 194 5 414 377 5 422 833 5 426 378 5 426 379 5 430 687 5 432 719 5 448 181 5 448 493 5 450 021 5 450 022 5 453 706 5 455 525 5 466 117 5 469 003 5 475 253 5 477 414 5 481 206 5 483 478 5 486 707 5 486 776 5 488 316 5 489 858 5 489 866
304. s to count up or down selectable by the UDT bit in TCSR when it is enabled On transition of the carry out of the counter the counter stops or automatically reloads the generate value from the Load Register and continues counting selectable by the ARHT bit in TCSR The TINT bit is set in TCSR and if enabled the external GenerateOut signal is driven to 1 for one clock cycle If enabled the interrupt signal for the timer is driven to 1 for one clock cycle This mode is useful for generating repetitive interrupts or external signals with a specified interval Characteristics Generate Mode has the following characteristics The value loaded into the Load Register is called the generate value e Onstartup the generate value in the Load Register must be loaded into the counter by setting the Load bit in the TCSR This applies whether the counter is set up to Auto Reload or Hold when the interval has expired Setting the Load bit to 1 loads the counter with the value in the Load Register The Load bit must be cleared before the counter is enabled for proper operation When the ARHT bit Auto Reload Hold is set to 1 and the counter rolls over from all 15 to all 05 when counting up or from all 0 s to all 15 when counting down the generate value in the Load Register will be automatically reloaded into the counter and the counter will continue to count If the GenerateOut signal is enabled bit GENT in the TCSR an output pulse
305. sfers with programmable bits in the control register The clock polarity CPOL bit selects an active high i e idles low or active low clock i e idle high The clock phase CPHA bit can be set to select one of two fundamentally different transfer formats If 0 data is valid on the first SCK edge rising or falling after SS N has been asserted If 1 data is valid on the second SCK edge rising or falling after SS N has asserted Determination of whether the edge of interest is rising or falling edge depends on the idle state i e CPOL setting The clock phase and polarity must be identical for the master SPI device and the selected slave device Figure 3 and Figure 4 shows four possible clock behaviors and these diagrams are discussed in more detail below Both the MOSI and MISO port behaviors are different depending on the whether the SPI device is configured as a master or a slave When configured as a master the MOSI port is a serial data output port and the MISO is a serial data input port The opposite is true when the device is configured as a slave the MISO port is a slave serial data output port and the MOSI is a serial data input port There may be only one master and one slave transmitting data at any given time The bus architecture provides limited contention error detection i e multiple devices driving the shared MISO and MOSI signals and requires the software to provide arbitration to prevent most
306. ss Valid Address vaid Address Valid Address RH pt 6 Mem CEN Ve t et ELQV EHQZ Mem gt M GHQZ Mem WEN fox Mem DQ 0 Data Data Valid Data Valid Valid fm F le taro Figure 35 Waveform for Page mode and Standard Word byte Read Operation 5 X 9 X E YF MEM A Address Valid Address Valid X ie XE tw Mem WEN _ Mem DQ 0 DIN DIN Valid SRD DIN Figure 36 Waveform for Write Operations Table 33 StrataFlash Parameter Description Symbol 1 READ ONLY tavav Read Write Cycle Time tavav Address to Output Delay tei CEN to Output Delay teLav OEN to Non Array Output Delay teL CEN to Output Low Z to Output Low Z teHaz CEN High to Output in High Z 124 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB External Memory Controller XILINX Table 33 StrataFlash Parameter Description Symbol icuoz Parameter OEN High to Output in High Z tou Output Hold from Address CEN or OEN Change Whichever occurs first CEN High to CEN Low Page Address Access Time Write Opera
307. t 1 high 0 low Std Logic Vector A little endian vector the same width as the data bus containing a 0 or 1 in each position corresponding to an interrupt input 110 www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide OPB Simple Interrupt Controller Specification XILINX Table 24 Generics Parameters Common to all IntC Instantiations Generic Name Description Type Valid Values C HAS IPR Indicates the presence of IPR Integer 0 not present 1 present C HAS SIE Indicates the presence of SIE Integer 0 not present 1 present C HAS CIE Indicates the presence of CIE Integer 0 not present 1 present C HAS IVR Indicates the presence of IVR Integer 0 not present 1 present C IRQ IS LEVEL Indicates whether the Irq output Integer 0 edge generation 2 edge 1 level generation C IRQ ACTIVE Indicates the sense of the Irq Std Logic 0 falling low output l rising high Notes 1 C_BASEADDR must begin on a 32 byte address boundary for OPB and an 8 word boundary for DCR For an OPB IntC this means the low 5 address bits must be zero For a DCR IntC this means the low three address bits must be zero 2 C HIGHADDR is required to be at least C BASEADDR 31 for an OPB IntC or C BASEADDR 7 for a DCR IntC in order to provide space for the eight 32 bit addresses used by the simple
308. t 0 PC PC s Imm BEQID 101111 10000 Ra Imm if Ra 0 PC PC s Imm BNEID 101111 10001 Ra Imm if Ra 0 PC PC s Imm BLTID 101111 10010 Ra Imm if Ra lt 0 PC PC s Imm BLEID 101111 10011 Ra Imm if Ra lt 0 PC PC s Imm BGTID 101111 10100 Ra Imm if Ra gt 0 PC PC s Imm BGEID 101111 10101 Ra Imm if Ra gt 0 PC PC s Imm LBU Rd Ra Rb 110000 Rd Ra Rb 00000000000 Addr Rb Rd 0 23 0 Rd 24 31 Addr LHU Rd Ra Rb 110001 Rd Ra Rb 00000000000 Addr Rb Rd 0 15 0 Rd 16 31 Addr LW Rd Ra Rb 110010 Rd Ra Rb 00000000000 Addr Rb Rd Addr SB Rd Ra Rb 110100 Rd Ra Rb 00000000000 Addr Ra Rb Addr Rd 24 31 SH Rd Ra Rb 110101 Rd Ra Rb 00000000000 Addr Rb Addr Rd 16 31 SW Rd Ra Rb 110110 Rd Ra Rb 00000000000 Addr Rb Addr Rd LBUI Rd Ra Imm 111000 Rd Ra Imm Addr s Imm Rd 0 23 0 Rd 24 31 Addr LHUI Rd Ra Imm 111001 Rd Ra Imm Addr s Imm Rd 0 15 0 Rd 16 31 Addr LWI 111010 Imm Addr s Imm Rd Addr SBI Rd Ra Imm 111100 Rd Ra Imm Addr s Imm Addr Rd 24 31 SHI Rd Ra Imm 111101 Rd Ra Imm Addr s Imm Addr Rd 16 31 SWI Rd Ra Imm 111110 Rd Ra Imm Addr Ra s Imm Addr Registers MicroBlaze is a fully orthogonal architectur
309. t in 56 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide Microprocessor Peripheral Definition Format XILINX CSET signal nOPB segAddr segAddr in LMB Ports Only the MicroBlaze processor is allowed interconnection to the LMB The following connections are reserved CSET signal Instr Addr Instr Addr out 0 31 CSET signal Instr Instr in 0 31 CSET signal IFetch IFetch out CSET signal I AS I AS out CSET signal IReady IReady in CSET signal Data Addr Data Addr out 0 31 CSET signal Data Read Data Read in 0 31 CSET signal Data Write Data Write out 0 31 CSET signal D AS D AS out CSET signal Read Strobe Read Strobe out CSET signal Write Strobe Write Strobe out CSET signal DReady DReady in CSET signal Byte Enable Byte Enable out 0 3 MPD Peripheral Peripherals defined in the MPD file can have the following options Options Table 2 MPD Peripheral Options Option Values Default Definition STYLE BLACKBOX HDL Design style MIX HDL EDIF TRUE FALSE Synthesize HDL to a hardware FALSE implementation netlist INBYTE TRUE X The functions inbyte and FALSE peripheral inbyte are defined OUTBYTE TRUE X The functions outbyte and FALSE peripheral outbyte are defined STYLE Option The STYLE option defines the design composition of the peripher
310. t be cleared by writing 1 Read 0 No interrupt has occurred 1 Interrupt has occurred Write 0 No change in state of TOINT 1 Clear TOINT clear to 07 24 ENTO Enable TimerO 0 Disable timer counter halts 1 Enable timer counter runs 25 ENITO Enable Interrupt for 0 Enables the assertion of the interrupt signal for this timer Has no effect on the interrupt flag in TCSRO 0 Disable interrupt signal 1 Enable interrupt signal 26 LOADO Load TimerO 0 No load 1 Loads timer with value in TLRO March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 199 XILINX OPB Timer Counter Specification Table 3 Control Status Register 0 TCSRO Continued Bits Name Description Reset Value 27 ARHTO Auto Reload Hold 0 0 When the timer is in Generate Mode this bit determines whether the counter reloads the generate value and continues running or holds at the termination value In Capture Mode this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held 0 Hold counter or capture value 1 Reload generate value or overwrite capture value 28 CAPTO Enable External Capture Trigger 0 0 0 Disables external capture trigger 1 Enables external capture trigger 29 GENTO Enable External Generate Signal 0 0 0 Disables external generate si
311. t error OPB 10 IOPB xferAck Instruction interface OPB transfer acknowledge OPB 12 Data Addr 0 31 DLMB Data interface LB address bus 26 Byte Enable 0 3 DLMB Data interface LB byte enables 26 Data Write 0 31 DLMB Data interface LB write data bus 27 D AS DLMB Data interface LB address strobe 27 Read Strobe DLMB Data interface LB read strobe 27 Write Strobe DLMB Data interface LB write strobe 27 Data Read 0 31 DLMB Data interface LB read data bus 27 22 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide MicroBlaze Bus Interfaces XILINX Table 2 Summary of MicroBlaze Core Continued Signal Interface Description Page DReady DLMB Data interface LB data ready 27 Instr Addr 0 31 ILMB Instruction interface LB address bus 26 AS ILMB Instruction interface LB address strobe 27 IFetch ILMB Instruction interface LB instruction fetch 27 Instr 0 31 ILMB Instruction interface LB read data bus 27 IReady ILMB Instruction interface LB data ready 27 Interrupt Core Interrupt Reset Core Core reset Clk Core Clock Debug Rst Core Reset signal from OPB JTAG UART Ext BRK Core Break signal from JTAG UART Ext NM BRK Core Non maskable break signal from OPB JTAG UART Bus OPB Bus Configuration Organization The MicroBlaze OPB interfaces are organized as byte enable capable only masters The
312. ted to the appropriate lt gt hwXfer lt gt fwXfer and lt gt dwXfer Slave hwXfer Slave fwXfer and Slave dwXfer are translated to Slave xferAck lt gt hwXfer nOPB fwXfer and nOPB dwxXfer are translated to lt nOPB gt _xferAck The correct lower address bits are also generated e Signal translation for legacy device to byte enable device transfers Master hwXfer Master fwXfer and Master dwXfer are translated to Master lt gt hwXfer lt gt fwXfer and nOPB dwXfer are translated to lt gt Slave xferAck is translated to Slave hwXfer Slave fwXfer and Slave dwXfer lt nOPB gt _xferAck is translated to lt gt hwXfer nOPB fwXfer and lt nOPB gt _dwxXfer Mirroring and steering logic Conversion cycle generator for byte enable device to legacy device transfers With this architecture systems that do not require full V2 1 features for example systems that contain only Xilinx IP do not need to instantiate the BEIF and hence optimally use the available FPGA resources Systems that require legacy or OPB V2 0 devices must instantiate the BEIF although the most costly part of the BEIF the conversion cycle generator only needs to be instantiated if conversion cycles are possible not all slaves will cause generation of conversion cycles OPB Usage The following are general notes on
313. terface OPB bus request OPB 8 DM RNW DOPB Data interface OPB read not write OPB 12 DM select DOPB Data interface OPB select OPB 12 DM DOPB Data interface OPB sequential address OPB 13 DOPB DBus 0 31 DOPB Data interface OPB read data bus OPB 13 DOPB errAck DOPB Data interface OPB error acknowledge OPB 15 DOPB NGrant DOPB Data interface OPB bus grant OPB 9 DOPB retry DOPB Data interface OPB bus cycle retry OPB 10 DOPB timeout DOPB Data interface OPB timeout error OPB 10 DOPB xferAck DOPB Data interface OPB transfer acknowledge OPB 14 IM ABus 0 31 Instruction interface OPB address bus OPB 11 IM BE 0 3 Instruction interface OPB byte enables OPB 16 IM busLock Instruction interface buslock OPB 9 IM DBus 0 31 Instruction interface OPB write data bus always 0x00000000 OPB 13 IM request Instruction interface OPB bus request OPB 8 IM RNW Instruction interface OPB read not write tied to 0 OPB 12 IM select Instruction interface OPB select OPB 12 IM segAddr Instruction interface OPB sequential address OPB 13 IOPB DBus 0 31 Instruction interface OPB read data bus OPB 13 IOPB errAck Instruction interface OPB error acknowledge OPB 15 IOPB MGrant Instruction interface OPB bus grant OPB 9 IOPB retry Instruction interface OPB bus cycle retry OPB 10 IOPB timeout Instruction interface OPB timeou
314. the TC can be parameterized Base address for the TC registers Assertion level for CaptureTrig and GenerateOut signals high true or low true Future parameterization number of timer counter modules 204 www xilinx com 1 800 255 7778 March 2002 MicroBlaze Hardware Reference Guide XILINX 2002 Summary Overview JTAG UART Parameters Xilinx Embedded Processors OPB Peripherals OPB JTAG UART Specification This document describes the specifications for a JTAG_UART core for the On chip Peripheral Bus OPB This document applies to the following peripherals opb jtag uart v1 00b The JTAG_UART is a module that attaches to the OPB On chip Peripheral Bus and has the following features Features e Mimics UART functionality to MicroBlaze but sends data over JTAG OPB V2 0 bus interface with byte enable support Supports 8 bit bus interfaces e One transmit and one receive channel full duplex e 16 character transmit FIFO and 16 character receive FIFO Requires xmd or xmdterm to run on host for JTAG communication Able to reset system and MicroBlaze Able to assert break signals to MicroBlaze To allow you to obtain a JTAG_UART that is uniquely tailored for your system certain features can be parameterized in the JTAG UART design This allows you to configure a design that only utilizes the resources required by your system and operates with the best possibl
315. tic edge synchronization when inputs are configured for edge sensitivity e Output interrupt request pin is configurable for edge or level generation edge generation configurable for rising or falling level generation configurable for active high or low Interrupt Controller Overview Interrupt controllers are used to expand the number of interrupt inputs a computer system has available to the CPU and optionally provide a priority encoding scheme Modern CPUs provide one or more interrupt request input pins that allow external devices to request service 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 www xilinx com 91 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX OPB Simple Interrupt Controller Specification by the CPU There are two main interrupt request mechanisms used by CPUs Auto vectoring interrupt schemes provide an interrupt request signal to the processor and during the interrupt acknowledge cycle the interrupt controller provides all or some portion of the address of the interrupt service routine Hard vector interrupt schemes provide one or more fixed locations in memory one for each interrupt request input or one location f
316. tions Power up and standby Write block erase write buffer or program set up Write block erase or write buffer confirm or valid address and data Automated erase delay Read status register or query data n mc QO gt Write read array command terwL CEN WEN Low to WEN CEN Going Low twp Write Pulse Width tpvwH Data Setup to WEN CEN Going High tavwH Address Setup to WEN CEN Going High tWHEH CEN WEN Hold from WEN CEN High twHDx Data Hold from WEN CEN High twHAX Address Hold from WEN CEN High twpH Write Pulse High tWHGL Write Recovery before Read Notes 1 Refer to Intel 28F128J3A Data Sheet for specific timing parameters Connecting to The three primary considerations for connecting the controller to memory devices are the width Memory of the OPB data bus the width of the memory subsystem and the number of memory devices used The width of the memory subsystem is the maximum width of data that can be read from or written to the memory subsystem The memory width must be less than or equal to the OPB data bus width The data and address signals at the memory controller are labeled with big endian bit labeling for example D 0 31 D 0 is the MSB Most memory devices are either endian agnostic they can be connected either way or little endian D 31 0 with D 31 as the MSB Note Exercise caution with the conn
317. tus TCSR1 32b Counter TCRO TCR1 OPB Bus GenerateOut1 Interrupt Logic TC Interrupt PWMO Figure 1 Timer Counter Organization 2002 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice March 2002 MicroBlaze Hardware Reference Guide www xilinx com 193 1 800 255 7778 5 XILINX OPB Timer Counter Specification The generate value is used to generate a single interrupt at the expiration of an interval or a continuous series of interrupts with a programmable interval The capture value is the timer value that has been latched on detection of an external event The clock rate of the timer modules is OPB no prescaling of the clock is performed All of the TC interrupts OR ed together to generate a single external interrupt signal The interrupt service routine reads the control status registers to determine the source of the interrupt Programming Timer Modes Model You can use a Generate Mode a Capture Mode or a Pulse Width Modulation PWM Mode with the two timer counter modules Generate Mode In Generate Mode the value in the Load Register is loaded into the counter and the counter begin
318. two address bits are 00 regardless of the size of the data in the register or the size of the peripheral March 2002 www xilinx com 35 MicroBlaze Hardware Reference Guide 1 800 255 7778 XILINX Usage in FPGAs Master and Slave I O OPB masters will adhere exactly to the signal set shown in Table 1 OPB slaves will adhere exactly to the signal set shown in Table 2 Devices that are both master and slave will adhere exactly to the signal set shown in Table 3 Page numbers referenced in the tables apply to both the OPB V2 0 specification and the OPB V2 1 specification both from IBM signals shown must be present except for the one signal shown as optional lt Master gt _DBus 0 31 for devices that are both master and slave No additional signals for OPB interconnection may be added The naming convention is as follows Master represents a master name or acronym that starts with an upper case letter Slave represents a slave name or acronym that starts with an upper case letter nOPB represents an OPB identifier for masters or slaves with more than OPB attachment and must start with an uppercase letter and end with upper case For devices with a single OPB attachment the lt gt identifier should default to OPB for example OPB ABus All other parts of the signal name must be referenced exactly as shown including case Table 1 Summary of OPB Master only I O
319. ty arbitration is not available Q0 DPE bit is read only e 1 DPE bit is read write PEN Read Write Park Enable Enables parking on a master when no other masters have requests asserted 0 parking disabled T parking enabled PENRW Read Park Enable Bit Read Write This bit informs the software as to the access of the PEN bit If the OPB Arbiter is parameterized to not support bus parking the PEN bit is always set to 0 to reflect that bus parking is not available e 70 PEN bit is read only 1 PEN bit is read write PMN Read Write Park On Master Not Last When parking is enabled this bit determines if the arbiter parks on the master who was last granted the bus or on the master specified by the Parked Master ID bits 70 park on the master who had just been granted the bus e 1 park on the master specified by the Parked Master ID bits www xilinx com 1 800 255 7778 March 2002 On Chip Peripheral Bus OPB Arbiter Design Specification XILINX Table 6 OPB Arbiter Control Register Bit Definitions Continued Bit s Name Core Access Reset Value Description PRV Read Write Priority Registers Valid This bit indicates that the Priority Registers all contain unique master IDs This bit is negated by the processor before the processor modifies the Priority Registers and is asserted by the processor when the modifications
320. ue 0 31 GPIO TRI GPIO Three state Control Bit all bits 1 Direction Each pin of the GPIO is individually programmable as an input or output For each bit 0 pin configured as output 1 I O pin configured as input 180 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB General Purpose Input Output GPIO Specification XILINX A write to the GPIO DATA register causes the written data to appear on the GPIO I O port for I Os that are configured as outputs The DATA register reads either the content of the GPIO DATA register for I Os configured as outputs or the GPIO I O port for I Os configured The GPIO TRI register configures the I O as either input or output Each bit of the I O port has a corresponding bit in the GPIO register Each I O bit can be individually configured as input or output If only inputs are required the ALL INPUTS parameter can be set to true As a result the GPIO TRI register and the read multiplexer are removed from the logic to reduce Operation GPIO Operation as inputs resource utilization Implementation Summary Table 6 Summary of GPIO 1 32b OPB interface Signal Interface Description Page OPB OPB Clock OPB Rst OPB OPB Reset OPB ABus 0 31 OPB OPB Address Bus OPB 0 3 OPB OPB Byte Enables OPB DBus 0 31 OPB OPB Data Bus OPB RNW
321. uired by your system The features that you can parameterize in the Xilinx OPB Arbiter design are shown in the following table Default Grouping Number Feature Description Parameter Name Allowable Values Value VHDL Type Arbiter G1 Number of OPB C NUM MASTERS 100 16 4 integer Features Masters G2 Priority Mode C DYNAM PRIORITY 1 Dynamic 0 Fixed integer 0 Fixed G3 Registered Grant C REG GRANTS 1 Registered Grant 1 integer Outputs Outputs Registered 0 Combinational ao Grant Outputs 2 PERS G4 Bus Parking PARK 1 Bus parking 0 Bus integer supported 3 parking not 0 Bus parking not supported supported OPB G5 OPB Slave Interface C PROC INTRFCE 1 OPB slave 0 OPB integer Interface interface supported slave 0 OPB slave interface interface not not supported 4 supported G6 OPB Arbiter Base BASEADDR Valid Address None S std logic vector Address Range G7 OPB Data Bus C_OPB_DWIDTH 8 16 32 64 128 32 integer Width G8 OPB Address Bus C_OPB_AWIDTH 16 32 32 Width G9 Device Block 106 ID See note 6 integer G10 Module Identification MIR ENABLE See note 6 integer Register Enable G11 OPB High Address C HIGHADDR Address range must 5 integer be a power of 2 and gt 0x1FF 7 Notes 1 When C NUM MASTERS 1 no arbitration is necessary however the watchdog timer is included in the arbiter and
322. unter Ext memory Ext memory and WDT MicroBlaze CPU Core Data side OPB Instruction side OPB Data side LMB Other OPB Master Slave or Bridge Block RAM Figure 4 Configuration 2 OPB DOPB DLMB Purpose Use this configuration when your application requires more instruction and data memory than is available in the on chip BRAM In this configuration all of the instruction memory is resident in off chip memory or on chip memory on the instruction side OPB Depending on how much data memory is required the data side memory controller may not be present The data side is also used for other peripherals such as UARTS timers general purpose I O additional BRAM and custom peripherals The OPB to OPB bridge is only required if the data side OPB needs access to the instruction side OPB peripherals such as for software based debugging Typical Applications e MPEG Decoder Communications Controller e Complex state machine for process control and other embedded applications e Set top boxes Characteristics This configuration allows the CPU core to operate at the maximum clock rate because of the simpler instruction side bus structure Instruction fetches on the OPB however are slower than fetches from BRAM on the LMB Overall processor performance is lower than implementations using LMB unless a large percentage of code is run from the internal instruction history buffer This configuration allows
323. us G7 This output is grounded if C PROC INTRFCE 0 or NUM MASTERS 1 P2 ARB xferAck G1 G5 This output is grounded if C PROC INTRFCE 0 or NUM MASTERS 1 P3 ARB Retry This output is always grounded P4 ToutSup This output is always grounded P5 ARB ErrAck This output is always grounded P6 OPB 0 AWIDTH 1 G1 G5 Width varies with the size of the OPB Address bus G8 This input is unconnected if PROC INTRFCE 0 or NUM MASTERS 1 P7 OPB OPB DWIDTH 8 1 G1 G5 Width varies with the size of the OPB Address bus G8 This input is unconnected if C PROC INTRFCE 0 NUM MASTERS 1 P8 OPB DBUS 0 C OPB DWIDTH 1 G1 G5 Width varies with the size of the OPB Data bus G7 This input is unconnected if C_PROC_INTRFCE 0 or C_NUM_MASTERS 1 P9 OPB RNW G1 G5 This input is unconnected if C_PROC_INTRFCE 0 or C_NUM_MASTERS 1 P10 OPB seqAddr G1 G5 This input is unconnected if C_PROC_INTRFCE 0 or C_NUM_MASTERS 1 P11 M_request 0 C_NUM_MASTERS 1 G1 Width varies with the number of OPB masters This input is unconnected if C NUM MASTERS 1 P12 OPB xferAck P13 OPB select P14 OPB retry P15 OPB toutSup P16 OPB timeout P17 OPB busLock G1 This input is unconnected if C NUM MASTERS 1 P18 OPB MGrant 0 C NUM MASTERS 1 G1 Width varies with the number of OPB masters This output is set to 1 if C NUM MASTERS 1 P19
324. us e g OPB or PLB in bits Table 43 Connection to 32 bit Memory using 4 StrataFlash Parts StrataFlash Signal DN Description EMC Signal MSB LSB MSB LSB 0 Data bus Mem DQ 0 7 DQ 7 0 Address bus Mem A 8 29 A 23 0 Chip Enable low true GND GND MEM 0 CE 2 0 Output Enable low true MEM OEN Write Enable low true MEM 0 Reset Power down low true MEM RPN Status low true MEM STS 0 STS Byte mode select low true N A tie to GND Program enable high true N A tie to VOC 1 Data bus Mem DQ 8 15 DQ 7 0 Address bus Mem A 8 29 A 23 0 Chip Enable low true GND GND MEM 0 CE 2 0 Output Enable low true MEM OEN OE Write Enable low true MEM_QWEN 1 WE Reset Power down low true MEM_RPN RP Status low true MEM_STS 0 STS Byte mode select low true N A tie to GND BYTE Program enable high true N A tie to VCC VpEN March 2002 MicroBlaze Hardware Reference Guide www xilinx com 1 800 255 7778 131 XILINX 132 OPB External Memory Controller EMC Table 43 Connection to 32 bit Memory using 4 StrataFlash Parts StrataFlash Signal DN Description EMC Signal MSB LSB MSB LSB 2 Data bus Mem DQ 16 23 DQ 7 0 Address bus Mem A 8 29 A 23 0 Chip Enable low true GND GND MEM 0
325. used to build bigger memories and this can slow memory access to LM For Virtex Virtex E Spartan ll devices the maximum allowed memory size is 16 KBytes which uses 32 select For Virtex Il and Virtex Il PRO devices the maximum allowed memory size is 64 KBytes which also uses 32 select BlockRAMSs Verify that your FPGA device resources can adequately accommodate your local memory instruction and data sizes Table 3 Local Memory Sizes Architecture Memory Size KBytes Spartan ll 2 4 8 16 Virtex 2 4 8 16 Virtex E 2 4 8 16 Virtex ll 8 16 32 64 Virtex Il PRO 8 16 32 64 Use the following format to define LM size CSET attribute C LM HIGHADDR 0x00001FFF CSET attribute C LM BASEADDR 0x00000000 LM must begin at address 0x00000000 Internal Signals Use the TYPE INTERNAL attribute to set internal signals as shown in the following example CSET signal mysignal internal connection TYPE INTERNAL By default only OPB and LMB signals are defined as INTERNAL All other signals are defined as EXTERNAL External signals are available through the port declaration of the top level module All points of connection to the internal signal must have the TYPE INTERNAL option Interrupt Signals Interrupt signals are set with a priority and the highest priority is 1 If there is only one interrupt defined in the platform then you may be able to connect it directly to the MicroBlaze March 2002 www xilinx com 47 MicroBlaze Ha
326. ut 2 clocks after a valid arbitration cycle Dynamic priority arbitration for a 4 OPB master system with combinational grant outputs is shown in Figure 10 Figure 11 shows dynamic priority arbitration for a 4 master OPB system with registered grant outputs odes 0 1 2 3 4 5 7 8 9 10 11 12 osc 1 1 1 LITT LVLO Priority Reg 31 32 00 X p 10 1 po ya LVL1 Priority Reg 31 32 01 10 11 00 01 10 LVL2 Priority Reg 31 32 10 D d o 10 X LVL3 Priority Reg 31 32 IK bo b IX ho IX m M request 0 M request 1 f M request 2 y M request 3 o OPB MGrant 0 Tc N OPB_MGrant 1 OPB NGrant 1 E OPB NGrant 3 Figure 10 Dynamic Priority Arbitration Combinational Grant Outputs 4 OPB Masters 0 1 2 4 5 6 7 10 1 12 13 14 15 16 17 BEN LVLO Priority Reg 31 32 00 X Ot X 10 X 14 X 10 YX j LVL1_Priority 31 32 107 XY 10 J LVL2 Priority Reg 31 32 10 11 00 01 10 11 LVL3 Priority Reg 31 32 ul X Too Y Tol X Tao X I X Tool y M request 1 M request 2 M
327. vel 1 0 NUM MASTERS 1 Each master ID must be contained in one of the Priority Registers otherwise that master s request will be ignored by the arbiter since it has no priority value and a grant to that master will never be asserted This could cause the bus to stall since there is no mechanism in the OPB specification for a master to timeout while waiting for a grant Therefore each Priority Register must contain a unique master ID and all master IDs must be contained in one of the Priority Registers Since the processor can not update the Priority Registers in a single OPB transaction there may be several clock cycles in which a particular master ID is not contained within a Priority Register Therefore the Priority Registers Valid PRV bit in the Control Register is used to indicate that the values of the Priority Registers are being modified and should not be used in OPB arbitration The processor negates this bit before modifying the 74 www xilinx com March 2002 1 800 255 7778 On Chip Peripheral Bus OPB Arbiter Design Specification XILINX OPB Arbiter Block Diagram o o Slave em lt Interface IPIF Priority Registers and then asserts this bit when the modification is complete The processor will insure that whenever the PRV bit is asserted all master IDs have been assigned a priority When the PRV bit is negated the OPB arbiter will assign priority based on the mast
328. via parameters to include FIFOs Note that the transmit and receive registers have independent addresses which differs from the 68HC11 specification where the same address is to be assigned to the two independent registers Table 4 SPI Assembly Registers and Offset from BAR OPB Address Access Read Write Register Name Interrupt Global Enable Register C_BASEADDR 0X1C Interrupt Register C_BASEADDR 0X20 Read Write 1 to clear Interrupt Enable Register C_BASEADDR 0X28 Read Write Reset Module C_BASEADDR 0X40 Read Write Control Register CR C_BASEADDR 0X060 Read Write Status Register SR C_BASEADDR 0X064 Read Data Transmit Register DTR C_BASEADDR 0X068 Write whether it is a single register or the transmit FIFO Data Receive Register DRR C_BASEADDR 0X06C Read whether it is a single register or the receive FIFO Slave Select Register SSR C_BASEADDR 0X070 Read Write Transmit FIFO Occupancy C_BASEADDR 0X074 Read Does not exist if FIFOs are not present Receive FIFO Occupancy C_BASEADDR 0X078 Read Does not exist if FIFOs are not present SPI Interrupt Registers Interrupt Module Specifications The interrupt registers are in the interrupt model which is instantiated in the IPIF module of the SPI assembly The SPI assembly has the option to include the interrupt module which permits multiple conditions for interrupt or to not include the module
329. wer down low true MEM RPN Status low true MEM STS 0 STS Byte mode select low true N A tie to VCC Program enable high true N A tie to VOC 1 Data bus Mem 00 16 31 DQ 15 0 Address bus Mem A 7 30 A 23 0 Chip Enable low true GND GND MEM 0 CE 2 0 Output Enable low true MEM OEN OE Write Enable low true MEM_QWEN 2 WE Reset Power down low true MEM_RPN RP Status low true MEM_STS 0 STS Byte mode select low true N A tie to VCC BYTE Program enable high true N A tie to VCC VpEN 130 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB External Memory Controller EMC Example 4 This example shows the connection to 32 bit memory using 4 StrataFlash parts in x8 mode supports byte reads and writes Table 42 Variables for StrataFlash x8 mode Example XILINX Variable Value Definition BN 0 Memory bank number DN 0 to 3 Memory device number within a bank The memory device attached to the most significant bit in the memory subsystem is 0 device numbers increase toward the least significant bit MW 32 Width in bits of memory subsystem DW 8 Width in bits of data bus for memory device MAW 24 Width in bits of address bus for memory device AU 8 Width in bits of smallest addressable data word on the memory device AS 2 Address shift for address bus logo MW AU DW 8 HAW 32 Width of host address b
330. will be generated one clock period in width This is useful for generating a repetitive pulse train with a specified period e When the ARHT bit Auto Reload Hold is set to 0 and the counter rolls over from all 15 to all 05 when counting up or from all 0 s to all 1 s when counting down the counter will hold at the current value and will not reload the generate value If the generate out signal is enabled bit GENT in the TCSR an output pulse will be generated one clock period in width This is useful for a one shot pulse that is to be generated after a specified period of time counter be set up to count either up or down bit UDT in the TCSR If the counter is set up as a down counter the generate value is the number of clocks in the timing interval The period of the GenerateOut signal is the generate value times the clock period When the counter is set to count down TIMING INTERVAL TLRx 2 x OPB CLOCK PERIOD When the counter is set to count up TIMING INTERVAL MAX COUNT TLRx 2 x OPB CLOCK PERIOD where MAX COUNT is the maximum count value of the counter such as OXFFFFFFFF for a 32 bit counter GenerateOout signals can be configured as high true or low true 194 www xilinx com March 2002 1 800 255 7778 MicroBlaze Hardware Reference Guide OPB Timer Counter Specification XILINX Capture Mode In Capture Mode the value of the counter is stored in the Load R
331. www xilinx com March 2002 1 800 255 7778 On Chip Peripheral Bus OPB Arbiter Design Specification 5 XILINX PRV M request 0 n Ivi 0 n priority reg Prioritize Requests 0 Master ID Select Lvl1 Master ID eoe Master ID LvlmSelect Select Lvin Master ID o o e T gt gt q rei req re Priority Encoder s S s 8 Assign Grants t II 159 YY YY MO Priority p A Select M1 Priority Select NE Mm Priority 88 Mn Priority grantO granti grantm Pipeline Register Figure 13 Arbitration grant 0 n Logic grantn n C NUM MASTERS 1 m C NUM MASTERS 2 only present when configured for dynamic priority arbitration March 2002 www xilinx com 1 800 255 7778 81 XILINX On Chip Peripheral Bus Arbiter Design Specification Park Lock Logic The Park Lock logic processes the raw or registered grant outputs from the Arbitration Logic and is only present in the design if C NUM 5 5 gt 1 It provides for the parking if PARK 1 and locking functionality of the OPB Arbiter and generates the final gr
332. x OPB Arbiter I O Signal Variations IBM OPB Arbiter Signal Name Xilinx OPB Arbiter Signal Name ARB DBusEn no longer an I O signal ARB XferAck 51 XferAck MO request M1 request M request O C NUM MASTERS 1 M2 request M3 request OPB MoOGrant OPB_M1Grant OPB MGrant 0 C NUM MASTERS 1 OPB MeGrant OPB 88 www xilinx com March 2002 1 800 255 7778 On Chip Peripheral Bus OPB Arbiter Design Specification XILINX Priority Level Nomenclature The IBM OPB Arbiter refers to the priority levels as High Medium High Medium Low and Low since it only implemented arbitration among 4 OPB masters Since the Xilinx implementation of the OPB arbiter supports parameterization of the number of OPB masters in the system it was decided that numbers should be used to represent priority levels instead of text descriptors Level 0 will always remain the highest priority level regardless of the number of masters implemented The higher the level number the lower the priority Grant Outputs The IBM OPB Arbiter only outputs combinational bus grant signals for both fixed and dynamic priority arbitration The Xilinx OPB Arbiter can be configured to output combinational or registered bus grants Also when the Xilinx OPB Arbiter is configured to support dynamic priority arbitration the bus grants will be output one clock after the arbitration cycle due to a pipeline register between the arbitration logic and
333. ype OPB Address Bus Width C OPB AWIDTH 8 32 32 integer Width of Data Bus to C MEM WIDTH C DWIDTH 64 integer Memory Devices Address access time for C RD ADDR TO OUT SLOW PS 1 Integer number of Refer to integer reads when picoseconds Data Sheet EMCCRx 0 0 or of particular 1 and access Memory is out of page 9 Device Address valid to end of write C ADDR TO OUT SLOW PS Integer number of Refer to integer when 0 0 5 6 picoseconds Data Sheet of particular Memory Device Minimum time that write C WR MIN PULSE WIDTH PS x Integer number of Refer to integer enable goes low follows picoseconds Data Sheet address being driven out of particular Applies to all writes 5 9 Memory Device Address access time for C RD ADDR TO OUT FAST PS 1 Integer number of Refer to integer reads when picoseconds Data Sheet EMCCRx 0 1 or of particular EMCCR x 1 1 and access Memory is in page Device Address valid to end of write C WR ADDR TO OUT FAST PS x Integer number of Refer to integer when 0 1 56 picoseconds Data Sheet of particular Memory Device Delay inserted before Write C RD RECOVERY BEFORE WR PS 1 Integer number of Refer to integer Enable goes low if previous picoseconds Data Sheet access was Read 6 of particular Memory Device Delay inserted before C WR RECOVERY BEFORE RD PS 1 Integer number of Refer to integer Output Enable goes l

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