2 structure of the pxi
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1. 3 Place the PXI C1553 module into an open slot in your chassis 4 Screw the PXI C1553 board into the top rail with the captive screw at the top of the faceplate 5 Connect system with power source and turn on the power to your system Board Connectors The PXI C1553 provides user access to the MIL STD 1553 Bus signals Discrete I O signals and IRIG B Input Output Signals at the front panel 68 pin VHDCI J4 connector 1553 Hardware Manual 3 2 3 2 1 Technologies Connections to the I O Signals Connection to the MIL STD 1553 Interface The MIL STD 1553 bus interface of the PXI C1553 non EF supports up to four dual redundant 1553 channels For each channel both transformer coupled and direct coupled connections are provided The transformer coupled signals can be connected directly to a stub of a MIL STD 1553 coupler The direct coupled connections can be connected directly to the MIL STD 1553 bus Both the direct and transformer coupled signals are provided at the front panel connector J3 Additionally the transformer coupled signals are provided at the rear I O connector 14 The MIL STD 1553 bus interface of the PXI C1553 EF also supports up to four dual redundant 1553 channels For each channel one of four bus coupling modes can be independently programmed as described in the table below The MIL STD 1553 bus signals of the 1 1553 modules are only provided at the front panel connector J3 Table 3 22. INTRODUCTION General Document History Version Date Author Description V01 00 Rev A October 2010 MAISSA Created document Amarawardana December Melissa P V01 00 Rev B 2010 Kinarawatdaha Format revisions Melissa Updated connector cable specifications TOO Connecting the AIT Module to the Bus V01 00 Rev D September Drew Dingman Bill Updated connector cable specifications 2011 Fleissner This document comprises the Hardware User s Manual for the PXI C1553 hardware module which is a member of AIT s family of advanced MIL STD 1553 test and simulation modules This document covers the hardware installation the board connections a general description of the hardware architecture and specific electrical and physical technical data of the module For programming information refer to the appropriate reference documents listed in the Applicable Documents section of this manual The PXI C1553 modules are capable of operations in both 3 3 V PCI and PCI X systems The modules can be used to simulate monitor and inject protocol errors in MIL STD 1553A B systems and can provide up to 4 MIL STD 1553 Dual Redundant interfaces The Full Function variant of the module is capable of simultaneously supporting the operations of a Bus Controller BC Bus Monitor BM and up to 31 Remote Terminals RT The Single Function variant of the module is capable of supporting either BC operations or BM and M
3. 3 23 1553 Front Panel Connector 43 For applications not using the break out cables provided the PXI C1553 non EF front panel connector 13 68 VHDCI connector that provides access to the transformer coupled and direct coupled MIL STD 1553 databus signals four redundant channels IRIG B Input Output signals and the Discrete I O signals Pinouts for the PXI C1553 are given below PXI C1553 Hardware Manual 17 Technologies Table 3 2 3 I PXI C1553 Front Panel Connector J3 Pin Assignment VIO IN IN DOO 0 6 Lg 48 17 18 19 20 NM a 29 24 25 26 E GN 28 29 30 CHA 4B DC CHA 4B XC CHA 4A DC CHA 4A XC Jupe CHA 3B XC CHA 3A DC CHA _ CHA 2B DC CHA 2B XC CHA 2A DC CHA 2A XC p ma e camo B 32 CHA 1B 66 CHA 1B XC 34 Bidr 68 CHA 1A XC 18 1553 Hardware Manual Technologies Table 3 2 3 II Signal Descriptions Signa pDescpion id IRIG B Output Signal IRIG OUT hRIG B Output Signal Dann No Connection PXI C1553 Hardware Manual 19 Technologies 3 2 4 PXI C1553 EF Front Panel Connector 43 For applications not using the break out cables provided the PXI C1553 EF Extended
4. 1 Bus Coupling Modes Direct Bus signal provided at front panel is direct coupled and can be connected directly to the 1553 bus Transformer Bus signal provided at the front panel is transformer coupled and can be connected directly to a stub of a bus coupler Network A properly terminated bus network is simulated on the PXI C1553 EF card and a bus stub is provided at the front panel connector the bus signal at the front panel can be connected directly to a transformer coupled MIL STD 1553 device Isolated No bus signal is provided at the front panel the front panel bus signal pins are disconnected from the internal circuitry of the PXI C1553 EF module The MIL STD 1553 specification clearly defines the process of coupling subsystems to the bus This connection called a stub has two coupling options direct coupled and transformer coupled In addition to these two methods of connecting to the bus a direct to device network coupling configuration is also an option three methods are described in this section The Flight Director bus analyzer software allows the user to select isolated transformer direct or network coupling through the system setup controls Use of an AIT module without the Flight Director software is accomplished with library setup calls PXI C1553 Hardware Manual 9 Technologies 3 24 1 Direct Coupling Direct coupling connects subsysten terminal device directly to the bus and can only be used in
5. Functionality the pinout for the PXI C1553 EF front panel connector are different than those for the PXI C1553 due to the fact that the PXI C1553 EF supports multiple software programmable bus coupling modes on the same front panel pins Pinouts for the PXI C1553 EF are given below 20 PXI C1553 Hardware Manual Technologies Table 3 2 4 PXI C1553 EF Front Panel Connector J3 Pin Assignment eno pics poe eim OJO 009 e e e e e Biar 3 3 4 4 4 4 4 4 4 4 4 4 pos O p CHA 3 2 51210 5 2 5 29 Sm CHA __ GND Bar _ NC NC Biar NC f 35 36 37 8 9 0 1 2 3 4 5 6 7 8 9 50 51 52 5 54 55 56 57 58 59 61 62 63 64 65 67 N N N N N N N N N N 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 2 5 295 2 5 2 o 7 10 11 12 13 14 17 9 0 2 3 4 5 6 7 8 9 0 1 2 3 4 3 PXI C1553 Hardware Manual 21 Technologies 3 2 5 PXI C1553 EF Rear I O Connectory 44 The rear 14 connector of the PXI C1553 or PXI C1553 EF is DIN64 male connector that provides access to the Bus signals IRIG B signals and the Discrete I O signals 22 PXI C1553 Hardware Manual Technologies Table
6. Operating Voltage Current 3 3 TBD 5V TBD 12V TBD 12V TBD Temperature Operating 0 C to 470 C Storage 40 C to 85 C Humidity 0 to 95 non condensing PXI C1553 Hardware Manual 29 Technologies 5 NOTES 51 Acronyms and Abbreviations ADC Analog to Digital Converter AFDX Avionics Full Duplex Databus ALBI Local Bus Interface ANSI American National Standards Institute ARINC Aeronautical Radio Incorporated ARM Advanced RISC Machine BC Bus Controller BIP Bus Interface Processor BIU Bus Interface Unit CM Chronological Bus Monitor cPCI Compact PCI CPLD Coupled CPU Central Processing Unit DAC Digital to Analog Converter DC DC Direct Current to Direct Current power conversion DIP Data Interface Processor DMA Direct Memory Access DRAM Dynamic Random Access Memory DSUB D Subminiature EDO Enhanced Data Output EEPROM Electrically Erasable and Programmable Read Only Memory EPROM Erasable Programmable Read Only Memory FIFO First in First out FLASH Page oriented electrical erasable and programmable memory FPGA Field Programmable Gate Array GND Ground TEEE Institute of Electric and Electronic Engineers IRIG Inter Range Instrumentations Group IRIG B Inter Range Instrumentations Group Time code Format Type B I O Input Output LCA Logic Cell Array XILINX Programmable Gate Array LED Light emitting Diode MIL STD Military Standard OWL Object Wrapper Library PC Personal Computer PCI Periphera
7. STD 1553 Bus Monitor MIL STD 1553 Replay Time Tagging IRIG Input 32 bit 33 MHz PCI plus PXI Trigger Bus PXI System Clock and PXI Star Trigger 3U Hybrid Slot Compatible PXI Module 256 Mbyte DDR2 SDRAM 128MB for channel data 128MB for onboard processor PXI C1553 EF Up to 4 Dual Redundant MIL STD 1553 channels with programmable coupling and output voltage are supported PXI C1553 Up to 4 Dual Redundant MIL STD 1553 channels with both transformer and direct coupling modes are supported Each channel independently capable of simultaneous Bus Controller Bus Monitor and Remote Terminal up to 31 simulation Major Framing Minor Framing and Acyclic message transfer scheduling Inter message Gap Scheduling Full error injection capabilities in support of AS4112 RT Validation Testing e Automatic Bus Retries Full Mode Code generation support Simultaneously supports 31 RTs e Programmable Response Times 250 ns increments Full Error Injection Intelligent Mode Code responses e Passive receive only monitor mode operations Chronologically time tags and stores all bus traffic e Error detection and notifications including detection of Gap and Response time violations low bit word counts parity errors sync errors and status work exceptions Complex Triggering and Filtering e Programmable Pre Post Trigger storage Replay of stored bus monitor data Replay can be sy
8. amp 3 0 PCI to PCI Bridge Architecture Specification Revision 1 1 1 3 2 Product Specific Documents AIT MIL STD 1553 Getting Started Manual provides detailed instructions to assist first time users of AIT MIL STD 1553 interface modules with software installation hardware setup and starting a sample project AIT MIL STD 1553 Object Wrapper Library Reference Manual provides a detailed description of the high level object oriented programming interface between host application programs and the PXI C1553 PXI C1553 Hardware Manual 5 6 Technologies 2 STRUCTURE OF THE PXI C1553 MODULE The structure of the PXI C1553 module is shown in Figure 2 below Figure 2 Structure of the PXI C1553 IRIG B Encoder Decoder MIL STD 1553A B 128 MByte 128 MByte Tx Rx Buffers Core FPGA PowerPC DDR2 RAM PowerPC DDR2 RAM Back Plane PXI C1553 Hardware Manual Technologies The primary components of the PXI C1553 are PCI to PCI Bridge This bridge allows multiple devices namely the PMC1553 and PXI Trigger IO controller on the on card PCI bus This bus runs at 33 333 MHz whereas the CompactPCI backplane may run at 66 MHz or 33 MHz MIL STD 1553 Core PowerPC FPGA The MIL STD 1553 Core and PowerPC is implemented in a Xilinx Virtex 4 The PowerPC operates at 250MHz and is capable of hosting time critical user application functions The MIL STD 1553 Core supports simultaneous Bus Controller Bus Monito
9. software selectable This allows the user to connect directly to a single terminal device without the need for any bus coupling The network coupling mode selected by the user via software controls provides a terminated network simulation on the AIT module for direct connection between AIT module software and the terminal under test Figure 3 2 1 3 Direct to Device Network Coupling PXI C1553 Hardware Manual 13 Technologies 3 2 2 PXI C1553 Breakout Cables The PXI C1553 and PXI C1553 EF modules are delivered with one of three cable assemblies which provide only transformer coupled outputs for non and software selectable coupling for the EF single channel card is delivered with one break out cable Part Number CBL VHDCI 1553 1 It includes two Twinax BNC connectors for each of the MIL STD 1553 bus connections e A dual channel card is delivered with one break out cable Part Number CBL VHDCI 1553 2 It includes four Twinax BNC connectors for each of the MIL STD 1553 bus connections quad channel card is delivered with one break out cable Number CBL VHDCI 1553 4 It includes eight Twinax BNC connectors for each of the MIL STD 1553 bus connections and one 15 pin standard DSUB breakout connector to provide access to the IRIG Digital DIO and the Voltage I O VIO control signal Figure 3 2 2 PXI C1553 Cable Assemblies AIT amp CBL VHDCI 1553 1 Deliv
10. the following sections Section 1 INTRODUCTION contains an overview of this manual Section 2 STRUCTURE OF THE PXI C1553 describes the physical hardware interfaces on the PXI C1553 using a block diagram and a description of each main component Section 3 INSTALLATION describes the steps required to install the PXI C1553 device and to connect the device to other external interfaces including the MIL STD 1553 databus IRIG B and discretes Section 4 TECHNICAL DATA describes the technical specification of the PXI C1553 Section 5 NOTES contains a list of acronyms and abbreviations used in this manual 4 PXI C1553 Hardware Manual Technologies 1 3 Applicable Documents The following documents shall be considered to be a part of this document to the extent that they are referenced herein In the event of conflict between the documents referenced and the contents of this document the contents of this document shall have precedence 1 3 1 Industry Documents MIL STD 1553B Department of Defense Interface Standard for Digital Time Division Command Response Multiplex Data Bus Notice 1 4 January 1996 MIL STD 1760 1 August 2003 Department of Defense Interface Standard for Aircraft Store Electrical Interconnection System PICMG 2 0 R3 0 CompactPCI Specification PXI Hardware Specification Revision 2 2 PXI Systems Alliance PXI Hardware Specification Revision 2 2 ECN 1 PXI Systems Alliance PCI Local Bus Specification R2 3
11. 2 PX C1553M EF 4 PX C1553S E F 1 PX C1553S EF 2 F 3 PX C1553S E Simultaneous BC 31 RTs and BM operations IRIG B Input Output 10 programmable discretes PXI backplane triggers and timing synchronization 1 2 and 4 channel single function interfaces for PXI BC or 31 RTs or BM and 31 RT monitor only operations IRIG B Input Output 10 programmable discretes PXI backplane triggers and timing synchronization 1 2 and 4 channel simulate only interfaces for PXI BC or 31 RTs and 31 RT monitor only operations IRIG B Input Output 10 programmable discretes PXI backplane triggers and timing synchronization 1 2 and 4 channel extended full function interfaces for PXI Simultaneous BC 31 RTs and BM operations Programmable bus coupling output voltage IRIG B Input Output 10 programmable discretes PXI backplane triggers and timing synchronization 1 2 and 4 channel single function interfaces for PXI BC or 31 RTs or BM and 31 RT monitor only operations Programmable bus coupling output voltage IRIG B Input Output 10 programmable discretes PXI backplane triggers and timing synchronization 1 2 and 4 channel simulate only interfaces for PXI BC or 31 RTs and 31 RT monitor only operations Programmable bus coupling output voltage IRIG B Input Output 10 programmable discretes PXI backplane triggers and timing synchronization PXI C1553 Hardware Manual 3 ec 1 2 How This Manual is Organized This manual is comprised of
12. 3 2 5 PXI C1553 EF Rear I O Connector J4 Pin Assignments J4 Row Pini NEM k k ak k k IRIG_IN IRIG_OUT CHA_4B_XC CHA 2B XC PXI C1553 Hardware Manual 23 vens Technologies 2 0 3 CHA 2B 24 PXI C1553 Hardware Manual 3 2 6 3 2 7 3 2 8 Technologies PXI XJ4 Connector Table 3 2 6 XJ4 Connector pxtrice GNO PxSTAR PXCLKIO GND 7 GND PXTRIG PXTRIGO 8 ano RSV GNO RSV PXLBLe PXLBRe GND IRIG Connections The IRIG IN and OUT signals of the PCI C1553 and PCI C1553 EF are provided at both the front panel connector J4 The IRIG IN and IRIG_OUT signals shall be connected depending on the time tagging method used as described below Single module with no external IRIG source No connections required Multiple modules with no common synchronization requirement No connections required e Single or multiple modules with external IRIG source Connect IRIG source to IRIG IN and GND of all modules e Multiple AIT modules with no external IRIG source Connect the OUT signal and the GND of the module you have chosen as the time master to all IN and GND signals of all boards including the master s Discrete Connections Ten Discrete I O signals are provided at the front panel connector J4 Each discrete can be operated as an output or an i
13. Manual is Organized rapi rri enata ear beer e repaid 4 1 8 DOC UNISTS om 5 1 3 1 Industry Documents sesso ao up sabia Disp ha sU pug 5 1 3 2 Product Specific Documents uror taret rr obrera rena 5 Section 2 STRUCTURE OF THE 1553 MODULE 6 Section 3 INST ALLAT ION 8 3 1 Installing the PX G T1559 Module eiae 8 3 1 1 Installation Instructions uscite 8 o 8 3 2 Connections to the VO Signals 9 3 2 1 Connection to the MIL STD 1553 9 321 Direct gem LE m 10 3 2 1 2 Transformer CODI 2 ela trn da etes deb temere 11 3 2 1 3 Direct to Device Network 13 2 PREG 1500 OBDIBS uei eti poii D apodo 14 3 2 3 PXI 01553 Front Panel Connector 17 3 2 4 PXI C1553 EF Front Panel Connector 33 20 3 2 5 PXI G 1553 EF Rear VO 22 3 2 6 Connector de EE 25 3 2 7 IRIG ONS 25 3 2 8 Discrete Connections eae esas 25 Section 4 TECHNICAL 27 PXI C1553 Hardware Manual ies In Technologies Saction 5 NOTES 30 5 1 Acronyms and Abbreviations iesu eia 30 Section 6 APPENDIX 32 PXI C1553 Hardware Manual 1 1 Technologies
14. a 3703 N 200th Street Omaha NE 68022 Tel 866 246 1553 402 763 9644 Fax 402 763 9645 aviftech com sales aviftech com PHI C1553 Hardware Manual 1 2 4 Steam MIL STD 1553 Testand Simulation Module for cPCI PXI September 201 1 V01 00 Rev D Technologies PHI C1553 Hardware Manual 1 2 4 Stream MIL STD 1553 Testand Simulation Module for cPCI PXI V01 00 Rev D September 2011 1 Technologies t 4 EN Bane m 4 El f AERE ar Gar Haas Fi Y 4 1 QA Avionics Interface Technologies Omaha Headquarters Design amp Production Center 3703 N 200th Street 2689 Commons Boulevard Omaha NE 68022 Suite 201 Tel 866 246 1553 Beavercreek OH 45431 402 763 9644 Tel 937 427 1820 Fax 402 763 9645 Fax 937 427 1281 ext 202 Eastern Sales Office Western Territory Office 34 Country Road 9221 E Baseline Road East Hampstead NH 03826 Suite A 109 432 Tel 603 378 0957 Mesa AZ 85212 Tel 480 354 0142 Notice The information provided in this document is believed to be accurate No responsibility is assumed by AIT for its use No license or rights are granted by implication in connection therewith Specifications are subject to change without notice 2011 AIT ees Table of Contents Section 1 1 EO e mo eL 1 1 2 How This
15. connections under one foot in length Since a direct coupled stub provides only limited isolation in the event of a device subsystem or terminal short transformer coupling is normally the recommended method of connecting to the bus Figure 3 2 1 1 Direct Coupling 1 Bus A Stub Length One Foot Max 10 1553 Hardware Manual Technologies 3 2 1 2 Transformer Coupling Transformer coupling utilizes a bus coupler that contains an isolation transformer and isolation resistors Transformer coupling extends the stub length to 20 feet and provides electrical isolation better impedance matching and higher noise rejection characteristics than direct coupling The electrical isolation prevents a terminal fault or stub impedance mismatch from affecting bus performance Figure 3 2 1 2 I Bus Coupler 2 Stub Bus Coupler Connecting to the bus using transformer coupling requires a coupler for each subsystem terminal device and proper termination on the bus Figure 3 2 1 2 II Terminal Device Connection Cables Aircratt orLab hne d PXI C1553 Hardware Manual 11 Technologies Figure 3 2 1 2 III Transformer Coupling 78 Q Terminators Pd 12 1553 Hardware Manual 3 2 1 3 Technologies Direct to Device Network Coupling Direct to Device Network coupling is an option with AIT modules The AIT design includes onboard bus network circuitry that is
16. ered with the PXI C1553 1 14 1553 Hardware Manual Technologies AIT CBL VHDCI 1553 2 Delivered with the PXI C 1553 2 E 15 00 12 00 P1 J9 J2 J3 J4 0 45 J6 f 37 8 M is EH A d AIT amp CBL VHDCI 1553 4 Delivered with the PXI C1553 4 If the customer application requires IRIG or other signals for a single or dual channel card normally shipped standard only with a quad channel card customers may order the quad channel cable from AIT s Price List For assistance contact your AIT Sales Engineer or call AIT at 1 402 763 9644 AIT will make any custom cable configurations and or length required PXI C1553 Hardware Manual 15 Technologies Table 3 2 2 Breakout Cable Pinout Pin __SignalName___ MIL bus twinax BNC connections CHA 1A CHA 1A XC CHA 1B CHA 1B XC CHA 2A XC CHA 2A XC CHA 2B XC CHA 2B XC CHA XC CHA 3A XC CHA XC CHA 3B XC CHA 4A XC CHA 4A XC CHA 4B CHA 4B XC 15 pin Standard VIO IN IRIG OUT IRIG IN GND DIO8 DIO7 DIO5 DIO4 DIO3 DIO2 DIO1 GND 16 1553 Hardware Manual Technologies
17. formation products EIPs including subassemblies that exceed limits specified in SJ T1 1363 2006 Table 1 Toxic or Hazardous Substances or Elements in Product Toxic or hazardous Substances or Elements Hexavale Lea nt Polybrominate Polybrominat Component d Mercur Cadmiu Chronium d Biphenyls ed Diphenyl Pb Hg m Cd Ethers PBDE 1553 4 Channel Carrier for PMC 1553 Hardware Standoff HEX 5mm x 10mm M2 5 Aluminum Clear finish Hardware Screw Metric M2 5 x 5mm Hardware Faceplate Overlay Hardware Face Plate PXI 1553 PMC 1553 Channel Conduction Cooled Parts List Product Marking Explanations In accordance with the requirements specified in SJ T11364 2006 all AIT EIPs sold in People s Republic of China are marked with a pollution control marking The following marking applies to AIT products 32 PXI C1553 Hardware Manual This marking indicates that some homogeneous substance within the EIP contains toxic or hazardous substances or elements above the requirements listed in SJ T11363 2006 These substances are identified in Table 1 The size or function of some products may prevent them from being directly marked These products still meet SJ T11364 2006 requirements and their marking information is covered by this document Environmentally Friendly Use Period The number in the marking shown as 40 in the illustration above refers to the EIP s en
18. l Component Interconnect PCIe Peripheral Component Interconnect Express PMC PCI Mezzanine Card PROM Programmable Read Only Memory 30 PXI C1553 Hardware Manual PSC PXI PXIe RISC RS 232 RT RTPTP SDK SIMM SRAM SSRAM TCP UART USB VME VME64 XMC Technologies PCI and System Controller PCI Extensions for Instrumentation PCI Extensions for Instrumentation Express Random Access Memory Reduced Instruction Set Computer Read Modify Write Recommended Standard No 232 US Norm Remote Terminal Remote Terminal Production Test Plan Received Data Software Development Kit Single Inline Memory Module Static Random Access Memory Synchronous Static Random Access Memory To be determined Time Code Processor Transistor Transistor Logic Transmitted Data Universal Asynchronous Receiver and Transmitter Universal Serial Bus VERS Amodule Eurocard VME 64bit extension VME Extensions for Instrumentation PCI Express Mezzanine Card PXI C1553 Hardware Manual 31 Technologies 6 APPENDIX A Avionics Interface Technologies Product Information for People s Republic of China This document provides product information as required by the People s Republic of China Electronic Industry Standard SJ T11364 2006 Marking for Control of Pollution Caused by Electronic Information Products Table 1 lists toxic or hazardous substances or elements contained in Avionics Interface Technologies AIT electronic in
19. nchronized across channels modules 46 bit IRIG time tag IRIG time microseconds since start of second Resolution 1 us Width 14 BCD digits 400 days Signal Type Single ended analog Signal Waveform Amplitude modulated sine wave or PXI C1553 Hardware Manual 27 Technologies IRIG Output Discretes Connectors Dimensions Weight Supply Voltages Modulation Ratio Input Amplitude Input Impedance Coupling Time Jitter Lock time Signal Type Signal Waveform Modulation Ratio Output Amplitude Output Impedance square wave 3 1 to 6 1 0 2Vpp to 3Vpp gt 3k Ohm AC Coupled 5nS typical module to module depending on input signal quality 1 to 5 seconds depending on input signal quality Single ended analog Amplitude modulated sine wave 3 1 1 5 volts 1 3 Ohmss typ designed for 50 Ohm load 10 Fully programmable as input or output discrete signals Inputs Outputs 14 Min Logic 1 2 5 Max Logic 0 0 8V Tolerant of up to 30V input Software configurable as open collector or emitter followers Maximum load 100mA Emitter Follower configuration capable of providing up to 5V signal without external VIO IN supply or up to 30V signal with external VIO IN supply 3U CompactPCI 100mm x 160mm 0 6 lbs 3 3V 5 5 5 12V 5 12V 5 28 PXI C1553 Hardware Manual Technologies Power Total Power
20. nput The discrete outputs can be configured in software as open collector current sink emitter follower current source or a TTL like output In the case of the emitter follower configuration VIO IN may be provided from an external source and used to externally set the high output voltage level If VIO IN is not provided externally then the onboard 5V supply is used External pull up or pull down resistors must be selected to ensure that the output load does not exceed 100mA An output voltage decrease will be seen as loads increase as described below PXI C1553 Hardware Manual 25 Technologies Table 3 2 8 Output Voltage Load 10mA 70mA 100mA 1 ogic 0 output powered by onboard 5V VIO Load Po ee ogic 1 output powered by externally provided 30V at VIO_IN Load 10mA r r 100mA Logic 0 output powered by externally provided 30V at VIO IN jLoadd Output Voltage load up to 100mA The discrete input Logic 1 minimum voltage is 42 5 V The input Logic 0 maximum voltage is 0 8 All discrete inputs are protected up to 30V Note An optional onboard pull up resistor to onboard 5V supply or the externally provided VIO IN may be provided Please consult factory for details 26 PXI C1553 Hardware Manual Technologies TECHNICAL DATA PCI Interface Form Factor Memory MIL STD 1553 Channels MIL STD 1553 Bus Controller MIL STD 1553 Remote Terminals MIL
21. oltage can be varied between 140 mVp p and 7Vp p measured with 36 Ohm load When transformer bus coupling is used the output voltage can be varied between 410 mVp p and 19Vp p measured with 73 Ohm load The onboard coupling circuits allow software to control the bus coupling mode of each of the four channels independently and set them in either direct transformer network or isolated mode For definitions of these modes see Table 3 2 4 I PXI C1553 Hardware Manual 7 8 qms cn Technologies 3 1 1 3 1 2 INSTALLATION Installing the PXI C1553 Module The PXI C1553 features full PCI plug and play capability There are no jumpers switches on the board which have to be modified by the user Note We recommend that you use a wrist strap for any installations If there is no wrist wrap available then touch a metal plate on your system to ground yourself and discharge any static electricity during the installation work The following instructions describe how to install the PXI C1553 Follow the instructions carefully to avoid any damage on the device Installation Instructions e To Install the PXI C1553 Module 1 Shut down your system and all peripheral devices Unplug the power cord from the wall outlet Inserting or removing modules with power applied may result in damage to the module devices 2 Remove any chassis panel covers necessary to gain access to a PXI CompactPCI peripheral slot
22. onitor only RT operations or up to 31 RT simulation operations The Simulator Only variant of the module is capable of simultaneously supporting BC operations up to 31 RT simulations and up to 31 RT monitor only operations Both Transformer and Direct MIL STD 1553 bus coupling modes are supported Additionally an extended function variant of the module PXI C1553 EF provides additional functions that support software programmable MIL STD 1553 bus coupling Transformer Direct Network or Isolated and software programmable output voltages The modules provide an onboard IRIG B Time Decoder Encoder in support of time synchronization with external equipment Each module may be configured to synchronize its internal clock to an input IRIG B time signal Additionally the module may also be configured as an IRIG B time source capable of providing a reference time signal The PXI C1553 module provide 10 programmable as input or output discretes Each PXI C1553 Hardware Manual 1 Technologies discrete is capable of up to 30 V operations with an external power supply 2 PXI C1553 Hardware Manual Technologies Table 1 1 PXI C1553 Variants 1553 1 1 2 and 4 channel full function interfaces for PXI 1553 2 1553 4 1553 1 1553 2 1553 4 15538 1 15535 2 15535 3 1553 1 1553 2 1553 4 PX C1553M EF 1 PX C1553M EF
23. r and Remote Terminal up to 31 functions on each of the available four bus interfaces Full error injection and error detection capabilities are provided SDRAM Two 128MB banks of SDRAM provide storage for bus transmit amp receive buffers and for PowerPC program and data stores MIL STD 1553 Transceivers and Coupling circuits The Transceivers and Coupling circuits provide both transformer and direct coupling access to all four dual redundant bus interfaces IRIG B Encoder Decoder The IRIG B Decoder allows the PXI C1553 module to synchronize its time tagging clock source to an external IRIG B time source The IRIG B Encoder allows the PXI C1553 module to output an IRIG B time signal derived from the modules onboard time tagging clock so that external equipment may be synchronized to the module This IRIG time may be reset by the PXI STAR signal if configured through software to do so Discrete Drivers and Buffers Ten discrete signals are provided each independently programmable as an input or output In support of MIL STD 1760 applications outputs can be used to driver up to 30V signals with the help of an external power supply and inputs can tolerate up to 30V signals The variable output voltage MIL STD 1553 transceivers provide for the generation of variable voltage bus signals The output voltage is controlled by an software programmable control voltage via the digital potentiometers When direct bus coupling is used the output v
24. vironmentally friendly use period EFUP The EFUP is the number of years from the date of manufacture that toxic or hazardous substances or elements contained in EIPs will not leak or mutate under the normal operating conditions described in the EIP user documentation resulting in any environmental pollution bodily injury or damage to assets Note Except as expressly stated herein and as required under mandatory provisions of regulations of the People s Republic of China Avionics Interface Technologies makes no representation or warranty of any kind expressed or implied with respect to the EFUP and expressly disclaims any representations or warranties expressed or implied with respect to the EFUP Original Equipment Manufactured OEM EIPs SJ T11364 2006 specifies that OEM EIPs shipped by AIT should include hazardous substance information and EFUP markings Table 1 applies to products that do not supply OEM product information Manufacture Date Contact your local sales representative to obtain the manufacture date of your product Waste Electrical and Electronic Equipment WEEE EU Customers At the end ofthe product life cycle all products must be sent to a WEEE recycling center For more information about WEEE recycling centers National Instruments WEEE initiatives and compliance with WEEE Directive 2002 96 EC on Waste Electrical and Electronic Equipment visit ni com environment weee htm PXI C1553 Hardware Manual 33
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