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CMX32M Hardware Manual - RTD Embedded Technologies, Inc.

1. Changing Ranges Real Time Clock Control OvervieW Accessing the RTC Registers Watchdog Timer Control Thermal Management Thermal Monitor Further Temperature Reduction Power Management Enabling Enhanced Intel SpeedStep Technology Core 2 Advanced Configuration and Power Interface ACPI men Power Button Modes Low Power Wake Options AT vs ATX Power Supplies ATX Power Supply Signals Reducing Power Consumption Multi Color LED Reset Status Register Features and Settings That Can Affect Boot Quick Add On Cards With BIOS Extensions VGA Hard Drive Monitor BDM 610000075 Rev D Table of Contents 63 64 64 64 65 65 65 65 66 67 67 67 67 67 67 68 68 69 71 77 77 77 77 78 78 78 80 81 81 81 81 82 82 82 82 82 83 83 83 84 85 87 87 87 87 87 87 87 vil Boot Device
2. Bit 7 6 5 4 3 2 1 0 Mode R W R W Ww Ww R W R W R W R WC Default 0 0 0 0 0 0 0 1 Field Rsvd Rsvd Clear Reset Rsvd Rsvd GO SW Trig SW Trig Write a 1 to generate a trigger to scan through the Channel Gain Table regardless of the state of the Go bit Will read 0 while the scan is happening and 1 when completed GO Set to 1 to begin continuous sampling based on the Pacer Clock Reset Write 1 to reset all aAIO registers including the Clear functions Always reads 0 Clear Write 1 to stop sampling clear the Filters and reset the Scatter Gather and Offset counters Always reads 0 Ox9E2 CH IRQ STAT Register Bit 7 6 5 4 3 2 1 0 Mode R R R R R R R R Default 0 0 0 0 0 0 0 0 Field Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Chx A 1 indicates that an interrupt is pending from channel x of the Channel Gain Table This bit is set regardless of CH IRQ This isa non stick register and will be cleared when the interrupt condition is cleared in the Channel Gain Table BDM 610000075 Rev D Chapter 4 Using the cpuModule 69 70 Ox9E3 CH IRQ ENA Register Bit 7 6 5 4 3 2 1 0 Mode R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Field Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Chx Writing a 1 enabled generation of an interrupt when the same bit of the CH IRQ STAT register goe
3. Due to system latency it is recommended that the Watchdog be refreshed at about half of the reset time out period or half of the interrupt time out period whichever is applicable Register Description The Advanced Watchdog Timer has a Setup Register and a Runtime Register The Setup Register is set by the BIOS and can be adjusted by entering the BIOS Setup Utility and going to Advanced Miscellaneous RTD Features The Setup Register may also be read by the driver to determine if the Watchdog is enabled and the interrupt and base address that it is using EN Note Enabling the watchdog timer in the BIOS does not actually arm it The watchdog timer can be armed by accessing I O address 985h as explained below Table 55 Advanced Watchdog Setup Register 98Bh D7 D6 D5 D4 D3 D2 D1 00 Reserved WDT IRQ Reg Enable Select Interrupt for WDT 0 Watchdog timer is disabled and 000 Disabled Runtime Register will not appear 001 IRQ5 in map 010 IRQ7 1 Watchdog Timer is enabled 011 IRQ10 Runtime Register will appear in 100 IRQ11 map 101 IRQ12 110 Reserved 111 Reserved Table 56 Advanced Watchdog Runtime Register 985h D7 D6 DS D4 D3 D2 D1 DO WDT_Active WDT_IRQ_Ena Reserved WDT IRQ Time WDT_RST_Time 0 Watchdog 0 Watchdog Select Interrupt Select Reset time timer is interrupt is time for for WDT disabled disabled WDT 00 2 00s 1 Watchdog is 1 Watchdog 00 0 25s 01 0 505 armed and interrupt is 01 0 50s
4. Table76 Ethernet 9 Pin D Connector female IDAN Pin RJ 45 Pin Signal CPU Pin 1 3 1 2 4 C 3 3 1 A TX 5 4 7 D 7 5 Ground 9 6 6 B RX 2 7 5 C 4 8 2 A TX 6 9 8 D 8 BDM 610000075 Rev D BDM 610000075 Rev D Table 77 Audio 15 Pin D Connector female Appendix C Dimensions and Pinout IDAN Pin Signal Function In Out CPU Pin 4 1 MIC_L Left Microphone Input in 1 2 MIC_R Right Microphone Input in 2 3 rsvd Reserved 3 4 GND Signal Ground GND 4 5 FRONT L Front Headphone Left Output out 5 6 FRONT R Front Headphone Right Output out 6 7 rsvd Reserved 7 8 rsvd Reserved 8 9 REAR L Rear Left Line Output out 9 10 REAR R Rear Right Line Output out 10 11 CENTER Center Line Output out 11 12 SUB Sub woofer Output out 12 13 SP OUT S PDIF Digital output out 13 14 GND Signal Ground GND 14 15 GND Signal Ground GND 16 107 108 CMX32M cpuModule BDM 610000075 Rev D Appendix D Additional Information Application Notes RTD offers many application notes that provide assistance with the unique feature set of the CMX32M cpuModule For the latest application notes refer to the RTD website Drivers and Example Programs To obtain the latest versions of drivers and example programs for this cpuModule refer to the RTD website Interrupt Programming For more information about interrupts and writing interrupt service routines refer to
5. Simple Operation The simplest operating mode is using software to start the sampling and poll the aAIO for the result This mode does not require setting up DMA buffers or setting up the Scatter Gather Table In order to use this mode perform the following steps 1 Open the board as described in Board Open on page 77 2 Write channel and input configuration in CGT Register if needed default is 10V single ended 3 Doa software start conversion 4 Poll A D done bit about 20 microseconds or wait for A D Done interrupt 5 Read data from A D Result Alternately the continuous sample bit can be set In this case the value read from the A D Result register is the last captured sample DMA Based Operation For higher performance sampling a DMA engine is provided This engine uses a scatter gather table for each channel The scatter gather table can have up to 64 entries each of which is a 4kB buffer that is 4kB aligned At the completion of entry of the scatter gather table an interrupt can be generated DMA transfers can be stopped and or the table can be restarted BDM 610000075 Rev D Chapter 4 Using the cpuModule 67 The scatter gather method allows continuous sampling at the maximum sample rate with the least amount of operating system intervention Because each channel has its own scatter gather table the data for each channel is located in a separate area in system memory Therefore the application software doesn t
6. 4 ccc ccc cece cece cece Hee System Recovery i cessere cde px DS VP TEE gt gu oen OR HA Reto Reset Button Recovety sas osa ho ah Load Default BIOS Settings sss Serial Power On Self Test POST Code BIOS Boot Block Recovery Appendix A Hardware Reference Jumper Settings and Locations Onboard PCI PCle Physical Dimensions sss Board F TRAE DS AppendixB Troubleshooting Common Problems and Troubleshooting a PC 104 5 How to Obtain Technical AppendixC IDAN Dimensions and Pinout IDAN Dimensions and Connectors External 1 O Connections Appendix D Additional Information Application Notes cece cee cece eee e Drivers and Example Interrupt Programming Serial Port 0000000000 PC 104Specifications sss AppendixE Limited
7. LVDS Flat Panel output e Two Gigabit Ethernet Intel 82567LM PHY ICH9M Controller PRO1000 Series Intel 82574IT Controller PRO1000 Series 10 100 1000 Auto negotiation Jumbo Frame Support 9kB PXE network Boot Smart Speed operation for automatic speed reduction on faulty cable plants Automatic MDI MDI X crossover capable e Software configurable RS 232 422 485 serial ports 16550 compatible UARTS for high speed 120 Ohm Termination resistors for RS 422 485 through BIOS Configuration Each serial port connector can be configured as two limited serial ports for a total of four serial ports Fully jumperless configuration e Advanced Digital I O aDIO Rev D One 8 bit bit programmable I O with Advanced Digital Interrupt Modes One 4 bit port programmable as input or output Event Mode Interrupt generates an interrupt when any input bit changes Match Mode Interrupt generates an interrupt when input bits match a preset value Chapter 1 Introduction 7 External Strobe Mode latches 8 data inputs and generates and interrupt TwoStrobes can be configured as readable inputs e Advanced Analog I O aAIO Eight single ended or four differential analog inputs Upto 100kHz sample rate 16 bit resolution Oto 5V 5 0 to 4 10V and 10V input ranges Per channel digital filtering Per channel threshold detection generates an interrupt when signal crosses high or low threshold Advanced DMA e Each c
8. The specific uses of the unlisted RTC registers will depend on the BIOS version loaded on the cpuModule Contact RTD s technical support for more information Note RIC registers that are not listed above are used by the BIOS and should be considered Reserved BDM 610000075 Rev D Chapter 4 Using the cpuModule 79 Watchdog Timer Control The cpuModule includes a Watchdog Timer which provides protection against programs hanging or getting stuck in an execution loop where they cannot respond correctly The watchdog timer consists of a counter a reset generator and an interrupt generator When the counter reaches the interrupt time out it can generate an interrupt When the counter reaches the reset time out the system is reset The counter is refreshed or set back to zero by reading from a specific register The watchdog can also be put into an inactive state in which no resets or interrupts are generated The ability to generate an interrupt allows the application to gracefully recover from a bad state For example consider a system that has a reset time out of 2 seconds interrupt time out of 1 second and the watchdog timer is refreshed every 0 5 seconds If something goes wrong an interrupt is generated The Interrupt service routine then attempts to restart the application software If it is successful the application is restarted in much less time than a full reboot would require If it is not successful the system is rebooted
9. recommends using these drivers instead of accessing the registers directly Digital 1 Register Set Table 42 Port 0 Data I O Address 9COh D7 D6 D5 D4 D3 D2 D1 DO P0 7 P0 6 P0 5 P0 4 P0 3 0 2 P0 1 P0 0 Port 0 Data register is a read write bit direction programmable register A particular bit can be set to input or output A read of an input bit returns the value of port 0 A read of an output bit returns the last value written to Port 0 A write to an output bit sends that value to port 0 Table 43 Port 1 Data I O Address 9C1h D7 D6 D5 D4 D3 D2 D1 DO Reserved Reserved Reserved Reserved P1 3 1 2 P1 1 P1 0 Port 1 Data register is a read write byte direction programmable register A read on this register when it is programmed to input will read the value at the aDIO connector A write on this register when it is programmed as output will write the value to the aDIO connector A read on this register when it is set to output will read the last value sent to the aDIO connector Table44 Multi Function I O Address 9C2h D7 D6 D5 D4 D3 D2 D1 DO The multi function register is a read write register whose contents are set by the DIO Control register See the DIO Control register description for a description of this register 60 CMX32M cpuModule BDM 610000075 Rev D Table 45 DIO Control I O Address 9C3h Read Access D7 D6 DS D4 03 02 D1 DO Strobe 0 Status Strobe 1 Status 0 strobe 0 no strobe 1 strobe 1 str
10. 10 0 755 can generate enabled 10 0 75s 11 1 00s resets and 11 1 00s interrupts Reading the Runtime Register also refreshed the watchdog timer 80 CMX32M cpuModule BDM 610000075 Rev D Thermal Management The cpuModule has several thermal features which can be used to monitor and control the board s temperature when extreme operating conditions are prevalent Thermal Monitor The Intel Thermal Monitor is a feature on the CMX32M that automatically throttles the CPU when the CPU exceeds its thermal limit The maximum temperature of the processor is defined as the temperature that the Thermal Monitor is activated The thermal limit and duty cycle of the Thermal Monitor cannot be modified EN Note The CPU and PCB temperatures displayed in the BIOS are approximate and should not be used to validate a cooling solution Fan Mode The CPU fan can be controlled by the CPU when connected to the switched fan power connector CN15 Three fan modes are supported which can be toggled in the BIOS setup When the fan is not always on the CPU s power consumption is reduced and the life of the fan is increased e Always On When in this mode the fan is always powered by the CPU e 70 This mode allows the system to keep the fan turned off until the CPU reaches 70C In this mode the fan will slowly transition between on and off to prevent oscillations This is the best mode for applications that will spend most of th
11. 5 TXD Transmit Data out 3 6 RXD Receive Data in 8 7 Reseved 4 8 Reseved 9 9 10 GND Signal Ground out 5 9 7 5 3 1 Note When using the serial port in RS 485 mode the serial transmitters are enabled and disabled under software control The transmitters are enabled by manipulating the Request To Send RTS signal of the serial port controller This signal is controlled by writing bit 1 of the Modem Control Register MCR as follows e f MCR bit 1 1 then RTS 0 and serial transmitters are disabled e f MCR bit 1 0 then RTS 1 and serial transmitters are enabled Note For more information on the serial port registers including the MCR refer to the Serial Port Programming reference in Appendix D BDM 610000075 Rev D Chapter 3 Connecting the cpuModule 35 Dual Serial Port Modes The serial port connectors can be configured as dual serial ports in the BIOS The mapping between the connectors and COM port numbers is shown in Table 20 The supported combinations of serial port modes are listed in Table 21 which also includes a reference to the corresponding connector pinout Table20 Dual Serial Port Connections Connector COMA COMB CN7 COM 1 COM 3 CN8 COM 2 COM 4 Table 21 Dual Serial Port Modes COMA COM B Pinout Reference RS 232 RS 232 Table 22 RS 422 RS 232 Table 23 RS 422 RS 422 Table 24 RS 485 RS 232 Table 23 RS 485 RS 485 Table 24 Ta
12. D PCle 104 Type 2 Bus 1 Top Connector CN1 carries the signals of the PCle 104 PCle bus These signals match definitions found in the PCI 104 Express amp PCle 104 Specification Version 2 01 from the PC 104 Embedded Consortium Table 30 lists the pinouts of the PC 104 Express bus connector WARNING Not all PCle cards are compatible with the PCle 104 Type 2 connector Be sure that all of the boards attached to this bus are compatible before powering the system BDM 610000075 Rev D Table30 PCle 104 Type 2 Bus Signal Assignments Top View Pin Signal Signal Pin 1 USB PE RST4 2 3 3 3V 3 3V 4 5 USB_1p USB_Op 6 7 USB_1n USB_On 8 9 GND GND 10 11 PEx1_1Tp PEx1 OTp 12 13 PEx1_1Tn PEx1_0Tn 14 15 GND GND 16 17 PEx1_2Tp PEx1_3Tp 18 19 PEx1_2Tn PEx1_3Tn 20 21 GND GND 22 23 PEx1_1Rp PEx1 ORp 24 25 PEx1 1Rn 2 PEx1_ORn 26 27 GND A GND 28 29 PEx1_2Rp PEx1_3Rp 30 31 PEx1_2Rn PEx1_3Rn 32 33 GND GND 34 35 PEx1_1Clkp PEx1 OCIkp 36 37 PEx1_1Clkn PEx1_0Clkn 38 39 5V_Always 5V_Always 40 41 PEx1_2Clkp PEx1 3Clkp 42 43 PEx1_2Clkn PEx1_3Clkn 44 45 CPU_DIR PWRGOOD 46 47 SMB_DATA Reserved 48 49 SMB_CLK Reserved 50 51 n c PSON 52 Chapter 3 Connecting the cpuModule 43 44 2 cpuModule Table30 PCle 104 Type 2 Bus Signal Assignments Top View Pin Signal Signal Pin 53 STKO ST
13. D2 D1 DO Utility Reset System Power Good Main 5V Input Memory Power 1 clear reset 1 clear reset 1 clear reset 1 clear reset CPU Core Power SIO Power Good Management Power Standby Power 1 clear reset 1 clear reset 1 clear reset 1 clear reset BDM 610000075 Rev D Chapter 4 Using the cpuModule 85 1 O Address t 457h D7 D6 D5 D4 D3 D2 D1 DO Table 62 Reset Status Description and Priorities Reset Reset Signal Priority Utility Reset gt CPU Core Power 5 System Power 4 SIO Power 3 Main Power 45V 2 Management Power 2 Memory Power 2 Standby Power 1 Description Utility connector push button reset CPU core powers supply Power supplies that are not for standby power Power monitored by the Super I O Main input power cpuModule 45V Power used in management mode Power to onboard memory banks Standby power supplies When a reset is asserted all resets with a higher reset priority will also be asserted For example if the standby power reset is asserted all other resets will also be asserted 2 The BIOS allows the user to change the function of the utility connector s push button reset Even if the push button is not configured as a reset this bit will always read a 1 asserted when the reset button has been 86 2 cpuModule pushed BDM 610000075 Rev D Features and Settings That Can Affect Boot Time The boot time of a system is dependent upon numerous system
14. Default JP5 2 Reserved open JP6 2 Used to disable the Bus Stacking Error detection See PCle 104 Type 1 Compatibility open on page 50and PCle 104 Type 2 Compatibility on page 45 pins 1 2 Disable Bus Stacking Error detection open Enable Bus Stacking Error detection normal operation JP9 3 Select power for flat panel backlight bottom side pins 2 3 pins 1 2 12 V pins 2 3 5 V BDM 610000075 Rev D Appendix A Hardware Reference 91 Onboard PCI PCle Devices The CMX32M cpuModule has several onboard PCI PCle devices all of which are listed in the table below This table shows a typical configuration and the actual devices may change based on BIOS settings Table 65 Onboard PCI Devices 92 CMX32M cpuModule Device ID Vendor ID Description 2A40 8086 Host Bridge 2A41 8086 PCI to PCI Bridge PCle x16 2A42 8086 Primary Display Controller 2A43 8086 Secondary Display Controller 10F5 8086 Ethernet Controller CN20 2937 8086 USB UHCI 4 2938 8086 USB UHCI 5 2939 8086 USB UHCI 6 293C 8086 USB EHCI 2 293E 8086 HD Audio Controller 2940 8086 PCI to PCI Bridge PCle 104 x1 1 2942 8086 PCI to PCI Bridge PCle 104 x1 2 2944 8086 PCI to PCI Bridge PCle 104 x1 3 2946 8086 PCI to PCI Bridge PCle 104 1 4 2948 8086 PCI to PCI Bridge to Shared Links 2934 8086 USB UHCI 1 2935 8086 USB UHCI 2 2936 8086 USB UHCI 3 293A 8086 USB EHCI 1 2917 8086 LPC Bridge
15. Farthest from CPU Shared No To other Shared 50 CMX32M cpuModule BDM 610000075 Rev D Optional RTC Battery Input CN13 The optional RTC battery input is the connection for an external backup battery This battery is used by the cpuModule when system power is removed in order to preserve the date and time in the real time clock Connecting a battery is only required to maintain time when power is completely removed from the cpuModule A battery is not required for board operation Table34 Optional RTC Battery Input CN 13 Pin Signal Function 1 BAT RTC Battery Input 2 GND Ground WARNING This optional RTC battery connector CN13 should be left unconnected if the utility port connector CN5 has a battery connected Fan Power Switched CN15 The switched fan power connector CN15 is an optional fan connector which allows the system to power the fan when the processor temperature reaches high temperatures To utilize this connector refer to the Thermal Management section on page 81 Table35 Fan Power Switched CN15 Pin Signal Function 1 CPU FAN PWM 5 Volts DC switched 2 GND Ground 3 FAN TACH Fan Tachometer Input BDM 610000075 Rev D Chapter 3 Connecting the cpuModule 51 52 CMX32M cpuModule BDM 610000075 Rev D Chapter 4 Using the cpuModule This chapter provides information for users who wish to develop their own applications programs for the CMX32M cpuModule This chapter includes informati
16. GND Ground GND 5 Y1P LVDS Data 1 out 6 YIM LVDS Data 1 out 7 DDC DATA Panel Detection Data in out 8 GND Ground GND 9 Y2P LVDS Data 2 out 10 Y2M LVDS Data 2 out 11 GND Ground GND 12 GND Ground GND 13 YCP LVDS Clock out 14 YCM LVDS Clock out 15 Y3P LVDS Data 3 out 16 Y3M LVDS Data 3 out 17 GND Ground GND 18 FP VCC Power for flat panel electronics out 19 FP VBKLT Power for flat panel backlight out 20 BKLT CTRL Backlight Brightness Control PWM out 1 The DDC signals use a 3 3 V signal level and are not 5 V tolerant Facing the connector pins the pinout is 19 17 15 13 11 9 7 5 3 1 9 D D T D T D pere ee Eo ee Em E L9 20 18 16 14 12 10 8 6 4 2 Table 13 lists several LVDS panels that were tested with this cpuModule When evaluating a panel be used with this cpuModule review the specifications of the tested panels to assure compatability Table 13 Tested LVDS Panels Manufacturer Model Number Resolution Color Depth Optrex 517560121 1024 768 18 bit Optrex T 51639D084JU FW A AB 1024 x 768 24 bit BDM 610000075 Rev D Chapter 3 Connecting the cpuModule 31 SATA Disk Chip Socket U6 The SATA Disk Chip socket is an 18 pin socket in a 32 pin format that supports miniature SATA flash disk chips The socket allows a true SATA device to be attached to the board with either a socketed or soldered connection Such devices are supported by all major
17. Warranty 2 cpuModule 87 88 88 88 EUR 88 BDM 610000075 Rev D Chapter 1 Introduction This manual provides comprehensive hardware and software information for users developing with the CMX32M PCle 104 cpuModule Note Read the specifications beginning on page 11 prior to designing with the cpuModule A This manual is organized as follows Chapter 1 Introduction introduces main features and specifications Chapter 2 Getting Started provides abbreviated instructions to get started quickly Chapter 3 Connecting the cpuModule provides information on connecting the cpuModule to peripherals Chapter 4 Using the cpuModule provides information to develop applications for the cpuModule including general cpuModule information detailed information on storing both applications and system functions and using utility programs Hardware Reference lists jumper locations and settings physical dimensions and processor thermal management Appendix B Troubleshooting offers advice on debugging problems with your system AppendixC IDAN Dimensions and Pinout provides connector pinouts for the cpuModule installed in an RTD Intelligent Data Acquisition Node IDAN frame AppendixD Additional Information lists sources and websites to support the cpuModule installation and configuration Appendix E Limited Warranty BDM 610000075
18. a CRT VGA monitor will reduce power consumption e Fan Mode Set the fan to auto mode so it is used only when the processor reaches high temperatures This option will only effect the fan if it is connected to the switched fan power connector CN15 e Multi Color LED Can be disabled the BIOS BDM 610000075 Rev D Chapter 4 Using the cpuModule 83 Multi Color LED The CMX32M hasa Multi Color LED which can be enabled or disabled in the BIOS setup screen The color of the LED indicates the status of the board as shown in Table 57 Color Green Blue Red Yellow Red Green White Cyan Blue Green Magenta Blue Red Blink Table 57 LED Colors Description Normal Operation SATA Activity cpuModule is in reset cpuModule is in Standby cpuModule is approaching thermal limit Ethernet Link at 100 Mbps or Bus Stacking Error Ethernet Link at 1000 Mbps Ethernet Activity 1 If power is applied to the cpuModule while jumper JP5 is installed the LED will be red This does not indicate that the board is in reset 2 TheLED will remain White until the system is shut down The LED can also be controlled manually by writing to Port 984h as shown in Table 58 and Table 59 Table58 Multi Color LED I O Address 984h D7 D6 D5 Reserved Reserved Reserved D4 D3 D2 D1 00 Reserved Reserved Multi Color LED The following table lists the color displayed and the value written 1 O Port 984h Value 0x00 0x08 0x
19. amd Accessories ix RR ete RE 5 Bo rd Features ooo oae eI espe Ier e Tp RI PNE SUE Pese UE es 6 7 do 9 Block Did 10 IIBER 11 Physical Characteristics 11 Power Consumption S HERR Pergit Ducem bon eee 11 Operating cnn age EA 11 Electrical Characteristics EA IEEE OM Aa ERO CER V 12 Contact Information erc tessa RU ea ERU Ce RR ERROR 14 Chapter 2 Getting Started Connector Locations Ren UR ned 16 Selecting the Stack Order for the CMX32M ete teen 18 Meredocip UE 19 Connecting to the Stack ern e a prre te y exa ape 20 Connecting the Utility Cable orte i herbe RPG PR doles isl e bb DAR Ra 21 Connecting a Keyboard oce tepore eee EI P rede Madea ved iu net nte te vues 21 Booting the CMX32M cpuModule for the First 00 00 21 Chapter 3 Connecting the cpuModule Proper Grounding Techniques I He 24 Connector Locations 2 soos sod bees Au I EA CER NEXU EON E eos oe ka 24 Auxiliary Power meses nana 26 Utility Port Con
20. cpuModule BDM 610000075 Rev D Ox9F8 THRESH LOW Register Bit 16 0 Mode R W Default 0x8000 Field THRESH_LOW THRESH LOW This register sets the low threshold for this channel It contains a 16 bit 2 s complement value with the same 305 175 microvolt resolution 20V 65536 for all ranges The high threshold must be greater than low threshold The default for low threshold is the maximum negative value If the A D reading for this channel is less than the low threshold the IRQ_STAT Thresh Low bit is set Ox9FA THRESH HIGH Register Bit 16 0 Mode R W Default 0x7FFF Field THRESH_HIGH THRESH HIGH This register sets the high threshold for this channel It contains a 16 bit 2 complement value with the same 305 175 microvolt resolution 20V 65536 for all ranges The high threshold must be greater than low threshold The default for the high threshold is the maximum positive value If the A D reading for this channel is greater than the high threshold the IRQ STAT Thresh High bit is set BDM 610000075 Rev D Chapter 4 Using the cpuModule 75 Ox9FC SGT DATA This register is used to view and modify the data in the Scatter Gather Table It is indexed both by SELECT CGT Channel to select the channel and SGT ROW to select the row in the table The Scatter Gather Table consists of a list of up to 64 entries Each entry contains the physical address of a buffer that i
21. heat pipes for fanless operation RTD modules installed in IDAN frames are called building blocks IDAN building blocks maintain the simple but rugged stacking concept of PC 104 and PC 104 Plus Each RTD module is mounted in its own IDAN frame and all connections are brought to the walls of each frame using standard PC connectors No connections are made from module to module internal to the system other than through the PC 104 bus enabling quick interchangeability and system expansion without hours of rewiring and board redesign The CMX32M cpuModule can also be purchased as part of a custom built RTD HiDAN or HiDANplus High Reliability Intelligent Data Acquisition Node This appendix provides the dimensions and pinouts of the CMX32M installed in an IDAN frame Contact RTD for more information on high reliability IDAN HiDAN and HiDANplus PC PCI 104 systems mimm IDAN Adhering to the PC 104 stacking concept IDAN allows you to build a customized system with any combination of RTD modules IDAN Heat Pipes Advanced heat pipe technology maximizes heat transfer to heat sink fins HiDANplus Integrating the modularity of IDAN with the ruggedization of HiDAN HiDANplus enables connectors on all system frames with signals running between frames through a dedicated stack through raceway BDM 610000075 Rev D Appendix C IDAN Dimensions and Pinout 99 IDAN Dimensions and Connectors 15 pin D female 26 pin high den
22. is disabled in Setup 58 CMX32M cpuModule BDM 610000075 Rev D Non Standard Serial Port Modes It is possible to change the input clock rate for the UARTs of the cpuModule by selecting the Serial Port Baud Rates option in the Serial Port Configuration menu of the BIOS Setup Changing the option from Normal to Non Standard will allow the serial port to operate at higher speeds This transforms bits 7 5 of the Divisor Latch High Byte of the UART into selections for alternate clock rates The following table describes the bit operations and the resulting divide by one baud rate Table41 Divisor Latch High and Low Bytes Divisor Latch High Byte Divisor Baud Rate Error Latch Low Bit7 Bit 6 Bit 5 Bits 4 0 Byte 0 0 0 0x00 0x01 115 200 0 16 1 0 0 0x00 0x01 460 800 0 16 1 1 0 0x00 0x01 921 600 0 16 0 0 1 0x00 0x01 1 500 000 0 16 To achieve non standard baud rates divide the baud rate you require by one of the non standard divisors 460 800 921 600 and 1 500 000 If the result is a whole number substitute that value for the Divisor Latch Low Byte For example to achieve a baud rate of 750 000 select the Divisor Latch High Byte for 1 500 000 and set the Divisor Latch Low Byte to 2 Note The signaling mode of the output will limit the highest baud rate achievable For RS 232 mode EN the maximum suggested baud rate is 230 400 For 422 485 modes the maximum is 1 500 000 Note When using the non standard high speed serial port modes it
23. is highly recommended to use hardware flow control whenever possible BDM 610000075 Rev D Chapter 4 Using the cpuModule 59 Advanced Digital I O Ports aDIO This board supports 12 bits of TTL CMOS compatible digital TTL signaling These I O lines are grouped into two ports Port 0 and Port 1 Port 0 is bit programmable Port 1 is byte programmable Port 0 supports RTD s Advanced Digital Interrupt modes The three modes are strobe match and event Strobe mode generates an interrupt and latches Port 0 when the strobe input transitions from low to high Match mode generates an interrupt when an 8 bit pattern is received in parallel that matches the match mask register Event mode generates an interrupt when a change occurs on any bit In any mode masking can be used to monitor selected lines When the CPU boots all digital lines are programmed as inputs meaning that the digital I O line s initial state is undetermined If the digital 1 O lines must power up to a known state an external 10 resistor must be added to pull the line high or low The 8 bit control read write registers for the digital I O lines are located from I O address 9COh to 9C4h These registers are written to zero upon power up From 9COh to 9C4h the name of these registers are Port 0 data Port 1 data Multi Function DIO Control and Wake Control register EN Note RTD provides drivers that support the aDIO interface on popular operating systems RTD
24. may use Setup to configure the serial ports as RS 422 or RS 485 In this case you must connect the serial port to an RS 422 or RS 485 compatible device When using RS 422 or RS 485 mode you can use the serial ports in either half duplex two wire or full duplex four wire configurations For half duplex 2 wire operation you must connect RXD to TXD and connect RXD to TXD EN Note The cpuModule has a 120 2 termination resistor Termination is usually necessary on all RS 422 receivers and at the ends of the RS 485 bus Termination resistors can be enabled in the BIOS setup utility When using full duplex typically in RS 422 mode connect the ports as shown in Table 17 Table 17 Full Duplex Connections Port 1 Port 2 RXD TXD TXD RXD RXD TXD TXD RXD When using half duplex in RS 485 mode connect the ports as shown in Table 18 Table 18 Half Duplex RS 485 Mode From To Port 1 TXD Port 1 RXD Port 1 TXD Port 1 RXD Port 1 TXD Port 2 RXD Port 1 RXD Port 2 TXD 34 2 cpuModule BDM 610000075 Rev D RS 422 and RS 485 Mode Pinout Table 19 provides the serial port connector pinout when RS 422 or RS 485 modes are enabled Facing the serial port connector the pinout is Table 19 Serial Port in RS 422 485 Mode Pin Signal Function In Out DB 9 1 Reserved 1 2 Reserved 6 3 RXD Receive Data in 2 4 TXD Transmit Data out 7
25. must therefore use I O addresses in the range of 0 1023 decimal or 000 3FF hex The upper I O addresses are used for PCI I O devices and are automatically assigned by the BIOS or operating system at boot time Note If you add any PC 104 modules or other peripherals to the system you must ensure they do not use EN reserved addresses listed below or malfunctions will occur The exception to this is if the resource has been released by the user Table 39 lists addresses reserved for the CMX32M cpuModule Table39 1 Addresses Reserved for the CMX32M cpuModule Address Range hex Bytes Device 000 00Fh 16 DMA Controller 010 01Fh 16 Reserved for CPU 020 021h 2 Interrupt Controller 1 022 02Fh 13 Reserved 040 043h 4 Timer 060 064h Keyboard Interface 070 071h 2 Real Time Clock Port 080 08Fh 16 DMA Page Register 0A0 0A1h 2 Interrupt Controller 2 0CO ODFh 32 DMA Controller 2 OFO OFFh 16 Math Coprocessor 100 101h 2 Video Initialization 1FO 1FFh 16 Hard Disk 200 201h 2 Reserved 238 23Bh 4 Bus Mouse 2E8 2EFh 8 Serial Port 2F8 2FFh 8 Serial Port 3E8 3EFh 8 Serial Port 3F8 3FFh 8 Serial Port 980 9BFh 64 Reserved 9C0 9C4h 5 aDIO 9C5 9DFh 27 Reserved 9EO 9FF 32 aAlO 1 Ifa floppy or IDE controller is not connected to the system the I O addresses listed will not be occupied 2 Ifa PS 2 mouse is not connected to the system the I O addresses listed will not be occupied 3 The I O addresses fo
26. need to de interlace the data The following steps are needed to use DMA operation 1 Open the board as described in Board Open on page 77 2 Allocate needed DMA buffers 3 Program Scatter Gather table 4 Write channel and input configuration in CGT Register if needed default is 10V single ended 5 Start conversion 6 Wait for DMA interrupt 7 Update Scatter Gather table if needed 8 Process or move data if needed 9 Repeat to Step 6 Registers Register Map Table51 aAIO Register Map Name 1 O Port 31 24 23 16 15 8 7 0 Control 0 09 0 CH IRQ CH IRQ STAT MODE RESET SELECT 3 0 Pacer Clock Divider 0 09 4 PACER DIVIDER Advanced Setup 0 09 8 Reserved CUR SGT ROW CUR BUFFER OFFSET Indexed registers controlled by 0 09 0 2 0 Channel Control OxO9EC FILTER CON SGT ROW CH MODE NEXT CHANNEL Result Ox09FO AD_RESULT Interrupt Ox09F4 IRQ_ENA IRQ STAT Threshold 0 09 8 THRESH HIGH THRESH LOW DMA Buffer Ox09FC SGT_DATA 68 CMX32M cpuModule BDM 610000075 Rev D Control Registers Ox9EO0 SELECT Register Bit 7 6 5 4 3 2 1 0 Mode R R R R R R W R W R W Default 0 0 0 0 0 0 0 0 Field Rsvd Rsvd Rsvd Rsvd Rsvd CGT Channel CGT Channel Selects the channel to be displayed in the Channel Gain Table Registers See Channel Gain Table Registers on page 71 Ox9E1 MODE RESET Register
27. on Note By default cpuModules are shipped with Fail Safe Boot ROM enabled When Fail Safe Boot ROM is enabled the system will boot to it exclusively BDM 610000075 Rev D Chapter 2 Getting Started 21 22 CMX32M cpuModule BDM 610000075 Rev D Chapter 3 Connecting the cpuModule This chapter provides information on all CMX32M cpuModule connectors Proper Grounding Techniques page 24 Connector Locations page 24 Auxiliary Power CN3 page 26 Utility Port Connector CN5 page 27 SVGA Video Connector CN18 page 30 LVDS Flat Panel Video Connector CN19 page 31 SATA Disk Chip Socket U6 page 32 Serial Port 1 CN7 and Serial Port 2 CN8 page 33 Advanced Digital aDIO Port CN6 page 38 Advanced Analog 1 aAIO Port CN10 page 39 USB 2 0 Connector CN17 page 40 Ethernet 10 100 1000Base T and TX Connectors CN20 and CN30 page 41 High Definition Audio CN11 page 42 PCle 104 Type 2 Bus CN1 Top page 43 PCle 104 Type 1 Bus CN2 Bottom page 47 Optional RTC Battery Input CN13 page 51 Fan Power Switched CN15 page 51 BDM 610000075 Rev D Chapter 3 Connecting the cpuModule 23 Proper Grounding Techniques Before removing the CMX32M from its static bag proper grounding techniques must be used to prevent electrostatic discharge ESD damage to the cpuModule Common grounding procedures include an anti static mat on a workbench which may connect to
28. should always be set for the last entry in the table even if the STOP flag is also set This flag is only checked for Channel 1 VALID Flag to indicate that this is a valid entry DMA data will only be transferred if the VALID flag is set This flag is checked for all channels 76 2 cpuModule BDM 610000075 Rev D BIOS Setup Register This register is for the BIOS to enable aAIO and set the interrupt Ox9CE aAIO SETUP Register Bit 7 6 5 4 3 1 0 Mode R R R R R W R W Default 0 0 0 0 0 0 Field Rsvd Rsvd Rsvd Rsvd ENA IRQ ENA Set to 1 to enable aAIO IRQ Set the IRQ 000 Disabled 001 IRQS 010 IRQ7 011 IRQ10 100 IRQ11 101 IRQ12 110 IRQ3 111 IRQ6 Usage Notes Board Open If the shift register that controls the A D is reset in the middle of a transfer the next sample that you try to get may be bad The only time that this problem could happen is if the system is reset CTRL ALT DEL etc in the middle of sampling However the following procedure will ensure that correct data will be available for the first sample 1 Perform a Board Reset to make sure all the registers are default 2 Do a software triggered sample 3 Wait for it to be done 4 Perform a Board Reset to reset the sample counter Changing Ranges The channel ranges are only actually updated during sampling If for example you are sampling a 3V signal in the 0 5V range then stop sampl
29. system care must be taken to ensure good power connections The power and ground leads must be twisted together or as close together as possible to reduce lead inductance A separate lead must be used for each of the power pins All 5V pins and all ground pins must be connected Do not use wire smaller than 20 gauge and the length of the wire must not exceed 2 ft The power supply solution must be verified by measuring voltage at the Auxiliary Power Connector and verifying that it does not drop below 4 75 V The voltage at the connector should be checked with an oscilloscope while the system is operational WARNING f you connect power incorrectly the module will almost certainly be destroyed Please verify power connections to the module before applying power Table7 Auxiliary Power Connector CN3 Pin Signal Function 1 GND Ground 2 5V 5 Volts DC 3 GND Ground 4 5V 5 Volts DC 5 GND Ground 6 GND Ground 7 5V 5 Volts DC 8 5V_STDBY 5V Standby ATX 9 5V 5 Volts DC 10 PSON Power Supply On ATX 1 For more information on the style signals 5V Standby and PSON refer to the Power Management section in Chapter 4 Using the cpuModule 26 2 cpuModule BDM 610000075 Rev D Utility Port Connector CN5 The utility port connector implements the following functions PC AT compatible keyboard port PS 2 mouse port Speaker port 0 1W output Hardware Reset input Soft Pow
30. that holds ROM DOS e Quick Boot mode BDM 610000075 Rev D Chapter 1 Introduction 9 Block Diagram The next figure shows a simplified block diagram of the CMX32M cpuModule Single Core Processor 17 LI LI 17 LI LI 1GB or 2GB Surface Mount GMCH DDR2 800 Dual Channel Memory North Bridge m n RTD Custom SATA Fe ASIC Disk Chip LPC Interface VO Hub RS 232 422 485 COM1 COM3 Transceiver Gigabit South Bridge 4 Ethernet Port PCle Switch 4 00000 Super lt RS 232 422 485 COM 2 Transceiver ew COM 4 2nd Gigabit ii i Ethernet Port PS 2 Mouse and Keyboard PCIe x16 PCle x1 RTD Enhanced BIOS o e a a 5 PCle 104 Bus Type 2 vvv PCle 104 Bus Type 1 Figure 2 CMX32McpuModule Simplified Block Diagram You can easily customize the cpuModule by stacking 104 or PCle 104 modules such as video controllers Digital Signal Processors drive carriers LAN controllers or analog and digital data acquisition modules Stacking modules onto the cpuModule avoids expensive installations of backplanes and card cages and preserves the module s compactness The cpuModule uses the RTD Enhanced AMI BIOS Drivers in the BIOS allow booting from hard disk Disk Chip or boot block flash thus enabling the system to be used with traditional disk drives
31. the following book Interrupt Driven PC System Design by Joseph McCivern ISBN 0929392507 Serial Port Programming For more information about programming serial port UARTS consult the following book Serial Communications Developer s Guide by Mark Nielson ISBN 0764545701 PC 104Specifications A copy of the latest PC 104specifications can be found on the webpage for the PC 104 Embedded Consortium http www pc104 org BDM 610000075 Rev D Appendix D Additional Information 109 110 CMX32M cpuModule BDM 610000075 Rev D AppendixE _ Limited Warranty RTD Embedded Technologies Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from RTD Embedded Technologies Inc This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period RTD Embedded Technologies will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to RTD Embedded Technologies All replaced parts and products become the property of RTD Embedded Technologies Before returning any product for repair customers are required to contact the factory for a Return Material Authorization number This limited warranty does not extend to any products which have been damaged as a result of accident misuse abu
32. then be placed in a standby mode and the aDIO interrupt will wake the system During system standby a 32kHz clock is used for the aDIO instead of an 8 33 MHz clock Therefore transitions must be at least 30 us in order to trigger a wake event If the aDIO is to be used for a wake event only and not an interrupt the Int Mask bit can be set in the Wake Control Register This will block the interrupt but still allow a wake event to occur The various settings for Wake Enable and Int Mask are shown in Table 49 below Table 49 Interrupt and Wake Event Generation WakeEnable Int Mask Function 0 0 Interrupt Only 0 1 No Interrupt or Wake event is generated 1 0 Interrupt and Wake Event 1 1 Wake Event Only BDM 610000075 Rev D Chapter 4 Using the cpuModule 63 Advanced Analog I O aAIO Features e Eight single ended or four differential analog inputs e Up to 100kHz sample rate e 16 bit resolution e Oto 5V 5V 0 to 10V and 10V input ranges Software configurable e Per channel digital filtering e Per channel threshold detection generates an interrupt when signal crosses high or low threshold e Advanced DMA Each channel has it s own DMA buffer Buffer chaining prevents interrupt latency problems DMA to anywhere in 4GB address space Block Diagram The Figure below shows the functional block diagram of aAlO The various parts of the block diagram are discussed in the following sections DMA Engi
33. 00 1000Base T and TX Connectors CN20 and CN30 41 High Definition Audio 11 cee ene I IH mH sese 42 PCle 104 2 Bus CN1 c cece cece ee HH eme mesh 43 PCle 104 Type 2 Compatibility eee tree prre peepee hee exe ee SOOO e nete Sada eileen 45 PCIE LINK Configuration saie 46 PCle PeersTO Peer eese CER EROR 46 PCle 104 Type 1 Bus 2 cece eee nec m mes ees 47 PCI 104 Express PCle Bus 5 II He eme eene 49 PGLEXPress x16 E Em 49 PCle 104 Type T Compatibility rrt hh CENE UE Ripper ve dr piae 50 PCle Link Configuration ER co RR TED E SUELE EU EE IEEE 50 Optional RTC Battery Input 1 III hme ee 51 Fan Power Switched 15 sse heh e esr hern 5 Chapter 4 Using the cpuModule The RTD Enhanced AMI BIOS 54 Configuring the RTD Enhanced AMI 5 IH emen 54 Entering the BIOS Setup iii iie osuere die EF EHRNPEPRBROREREDEENER 54 Field Selection ci eR an eve e VE E Epi eR Ea E NEN E M ME NER 54 Main Menu Setup Fields erred iene 55 Memory Map a 56 Address Map 3s 57 Hardware Interru
34. 09 0x0A 0x0B 0x0C 0x0D OxOE OxOF 84 2 cpuModule Table 59 Manual LED Colors Color Automatic see Table 57 Off will reduce system power consumption Blue Green Cyan Green Blue Red Magenta Red Blue Yellow Red Green White Red Green Blue BDM 610000075 Rev D Reset Status Register The cpuModule has several different signals on board which can cause a system reset If a reset occurs the reset status register can be used to see which reset or resets have been asserted on the cpuModule The user has the ability to see which resets have been asserted Resets can also be cleared e Examine Resets Reading from I O port 0x987 will indicate if a reset has been asserted If a 1 is read the corresponding reset has been asserted If a 0 is read from the bit the reset has not been asserted e Clear Reset Each reset can be cleared by writing a 1 to the selected bit of I O port 0x987 Table 60 Reset Status I O Address 987h Read Access D7 D6 D5 D4 D3 D2 D1 Utility Reset System Power Good Main 5V Input Memory Power 1 reset asserted 1 reset asserted 1 reset asserted 1 reset asserted 0 no reset 0 no reset 0 no reset 0 no reset CPU Core Power SIO Power Good Management Power Standby Power 1 reset asserted 1 reset asserted 1 reset asserted 1 reset asserted 0 noreset 0 noreset 0 noreset 0 noreset Table61 Reset Status I O Address 987h Write Access D7 D6 D5 D4 D3
35. 10 PinDILPin Signal Function 3 1 B RX Receive 10 100 6 2 B RX Receive 10 100 4 3 C 5 4 Cc 1 5 A TX Transmit 10 100 2 6 A TX Transmit 10 100 7 7 D 8 8 D 9 AGND Ethernet Ground 10 AGND Ethernet Ground 9 5 3 1 BDM 610000075 Rev D Chapter 3 Connecting the cpuModule 41 High Definition Audio 11 A full featured HD Audio compliant audio port is available on CN11 It provides a stereo microphone line level input 5 1 surround sound line level output and a stereo headphone output The front line level outputs also serves as a headphone outputs It is capable of driving a 32 Ohm load No configuration is required to switch between headphone and line output Table29 Audio Connector CN11 10 Pin DIL Pin Signal Function In Out 1 MIC LIN_L Left Microphone Line Input in 2 MIC LIN_R Right Microphone Line Input in 3 rsvd Reserved 4 GND Signal Ground GND 5 FRONT L Front Headphone Left Output out 6 FRONT R Front Headphone Right Output out 7 rsvd Reserved 8 rsvd Reserved 9 REAR L Rear Left Line Output out 10 REAR R Rear Right Line Output out 11 CENTER Center Line Output out 12 SUB Sub woofer Output out 13 SP OUT S PDIF Digital output out 14 GND Signal Ground GND 15 rsvd Reserved 16 GND Signal Ground GND 15 13 11 9 7 5 3 1 C oor wwe me oe e 16 14 12 10 8 6 4 2 42 CMX32M cpuModule BDM 610000075 Rev
36. 10000075 Rev D Chapter 3 Connecting the cpuModule 39 USB 2 0 Connector CN17 Two USB 2 0 compliant connectors are available on connector CN 17 Table 27 provides the pinout of the USB connector Note For proper operation at USB 2 0 speeds be sure to use a cable that is rated for USB 2 0 such as the cable kit supplied by RTD Table27 USB Connector CN17 Pin Signal Function In Out 1 VCC1 Supply 5 V to USB1 out 2 vcc2 Supply 5 V to USB2 out 3 DATA1 Bidirectional data line for USB1 in out 4 DATA2 Bidirectional data line for USB2 in out 5 DATA1 Bidirectional data line for USB1 in out 6 DATA2 Bidirectional data line for USB2 in out 7 GND Ground out 8 GND Ground out 9 GND Ground out 10 GND Ground out Facing the connector pins the pinout of CN17 is 40 2 cpuModule 9 7 e we 10 8 5 3 1 6 4 2 BDM 610000075 Rev D Ethernet 10 100 1000Base T and TX Connectors CN20 and CN30 This connector provides a 10 100 1000Base T Ethernet connection Table 28 provides the pinout of the Ethernet connector For 1000Base T all four pairs are used for transmit and receive To use the onboard 10 100 1000 Ethernet controller Echernet must be enabled in the BIOS When enabled the multi color LED will blink to indicate an Ethernet connection For more information refer to the Multi Color LED section on page 84 Table28 Ethernet Connector CN20 RJ 45 Pin
37. 2928 8086 SATA Controller 2930 8086 SMBus Controller 292D 8086 SATA Controller 8509 10B5 PCI to PCI Bridge Shared Link x1s 10D3 8086 Ethernet Controller CN30 BDM 610000075 Rev D Physical Dimensions Figure 10 shows the mechanical dimensions of the CMX32M cpuModule 1 1250 1 2250 1 4000 1 8155 n TE Basen 1115 nemine _ 2 9375 jmmmmmmmmmmM Figure 10 CMX32M Physical Dimensions 0 005 inches Board Spacing In order to facilitate larger heatsink solutions the CMX32M is designed to use a 22mm standoff between it and the board above it The PCle 104 connector on the top is specially designed to accommodate the 22mm board spacing when mated with a standard connector BDM 610000075 Rev D Appendix A Hardware Reference 93 When attaching a board below the CMX32M the standard 0 600 board spacing is used 94 CMX32M cpuModule BDM 610000075 Rev D AppendixB Troubleshooting Many problems you may encounter with operation of your CMX32M cpuModule are due to common errors This appendix includes the following sections to help you get your system operating properly Common Problems and Solutions page 96 Troubleshooting a PC 104 System page 97 How to Obtain Technical Support page 98 BDM 610000075 Rev D Appendix B Troubleshooting 95 Common Problems and Solutions Table 66 lists some of the common problems you may encounter while using your CMX32M cpuModule and sugg
38. 33V 0 0 V 0 4 V 2 0 V 55V 0 5 V 0 8 V 500 mA 25 V 25 V 42 typical 31 kQ typical 1 VaMs 10 k Ohms 32 Ohms 1000pF 1 000 Vkms 0 316 0 100 Venus 0 032 20 k Ohm 7 5pF 2 0V 3 6V 500 mA 1 Maximum DC undershoot below ground must be limited to either 0 5V or 10mA During transitions the device pins may undershoot to 2 0V or overshoot to 7 0V provided it is less than 10ns with the forcing current limited to 200 mA 2 Only required to maintain date and time when power is completely removed from the system Not required for board operation Chapter 1 Introduction 13 Contact Information RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 USA Phone 1 814 234 8087 Fax 1 814 234 5218 E mail sales rtd com techsupport rtd com Internet http www rtd com 174 CMX32M cpuModule BDM 610000075 Rev D Chapter2 Getting Started For many users the factory configuration of the CMX32M cpuModule can be used to get a PC 104 system operational You can get your system up and running quickly by following the simple steps described in this chapter which are 1 Before connecting the cpuModule the user must be properly grounded to prevent electrostatic discharge ESD For more information refer to Proper Grounding Techniques on page 24 Connect power Connect the utility harness Connect a keyboard Default BIOS configuration Fail Safe Boot ROM mb G
39. 6 CN6 is configured as an aDIO port aDIO is 12 digital bits configured as 8 bit programmable and 4 bit port programmable I O providing any combination of inputs and outputs Match event and strobe interrupt modes mean no more wasting valuable processor time polling digital inputs Interrupts are generated when the 8 bit programmable digital inputs match a pattern or on any value change event Bit masking allows selecting any subgroup of 8 bits The strobe input latches data into the bit programmable port and generates an interrupt Refer to Advanced Digital I O Ports aDIO page 60 for information on programming the aDIO Table25 aDIO Pinout CN6 Pin Function CN6 Pin Function 1 P0 0 2 P0 1 3 P0 2 4 P0 3 5 P0 4 6 P0 5 7 P0 6 8 P0 7 9 strobe 0 10 strobe 1 11 P1 0 12 P1 1 13 1 2 14 1 3 15 GND 16 5 V 1 Available during standby 38 CMX32M cpuModule BDM 610000075 Rev D Advanced Analog I O aAIO Port CN10 The Advanced Analog I O connector provides eight channels of analog input When used in conjunction with the aDIO port it allows the cpuModule to be a complete single board data acquisition system For more information on using the aAIO port refer to Advanced Analog I O aAIO page 64 Table26 aAIO Pinout CN10 Pin Function CN10 Pin Function 1 Channel 1 2 Channel 2 3 Channel 3 4 Channel 4 5 Channel 5 6 Channel 6 7 Channel 7 8 Channel 8 9 GND 10 GND BDM 6
40. CMX32M cpuModules 1 sa User s Manual BDM 610000075 Revision D www rtd com 1509001 and AS9100 Certified Accessing the Analog World CMX32M User s Manual RTD Document Number BDM 610000075 Revision D Copyright 2009 2012 Embedded Technologies Inc All rights reserved Trademarks Advanced Analog I O Advanced Digital I O aAIO aDIO a2DIO Autonomous SmartCal Catch the Express cpuModule dspFramework dspModule expressMate ExpressPlatform HiDANplus MIL Value for COTS prices multiPort PlatformBus and PC 104EZ are trademarks and Accessing the Analog World dataModule IDAN HiDAN RTD and the RTD logo are registered trademarks of RTD Embedded Technologies Inc formerly Real Time Devices Inc PS 2 is a trademark of International Business Manchines Inc PCI PCI Express and PCle are trademarks of PCI SIG PC 104 PC 104 Plus PCI 104 PCle 104 PCI 104 Express and 104 are trademarks of the PC 104 Embedded Consortium All other trademarks appearing in this docoument are the property of their respective owners Failure to follow the instructions found in this manual may result in damage to the product described in this manual or other components of the system The procedure set forth in this manual shall only be performed by persons qualified to service electronic equipment Contents and specifications within this manual are given without warran
41. Ex16 OR 1 p 116 117 PEx16 OR 9 n PEx16 OR 1 n 118 119 GND GND 120 121 PEx16 OR 10 p PEx16 OR 2 p 122 123 PEx16 OR 10 n PEx16 OR 2 n 124 125 GND GND 126 127 PEx16 OR 11 p PEx16 OR 3 p 128 129 PEx16 OR 11 n PEx16 OR 3 n 130 131 GND GND 132 133 PEx16 OR 12 p PEx16 OR 4 p 134 135 PEx16 OR 12 n PEx16 OR 4 n 136 137 GND GND 138 139 PEx16 OR 13 p PEx16 OR 5 p 140 141 PEx16 OR 13 n PEx16 OR 5 n 142 143 GND GND 144 145 PEx16 OR 14 p PEx16 OR 6 p 146 147 PEx16 OR 14 n PEx16 OR 6 n 148 149 GND GND 150 151 PEx16 OR 15 p PEx16 OR 7 p 152 153 PEx16 OR 15 n PEx16 OR 7 n 154 155 GND GND 156 1 Signals marked with are active low Specification Version 2 01 from the PC 104 Embedded Consortium PCI Express x16 Link The PCI Express x16 link on the PCI 104 Express connector can be used as a single x16 x8 x4 or x1 link It cannot be bifurcated into two x8 or x4 links In order to reduce power and heat dissipation the PCI Express x16 link utilizes a Low Power PCI Express interface as described in the PCI Express Architecture Mobile Graphics Low Power Addendum to the PCI Express Base Specification Revision 1 3 It is therefore recommended that any card that utilizes the PCle x16 link is placed directly adjacent to the CPU BDM 610000075 Rev D Chapter 3 Connecting the cpuModule 49 When used for non graphics applications the x16 link should only be used as a x8 x4 or x1 link Use of the full x16 width is only for a graphics
42. IO Compare register If you do not set them first the contents of the DIO Compare register could be lost because the Event mode latches in Port 0 into the DIO Compare register 62 CMX32M cpuModule BDM 610000075 Rev D CLOCK DIGITAL INPUT IRQ OUT Figure 6 aDIO Match Mode Strobe Mode Another interrupt mode supported by aDIO is Strobe mode This allows the strobe pin of the DIO connector to trigger an interrupt A low to high transition on the strobe pin will cause an interrupt request The request will remain high until the Clear Register is read from Additionally the Compare Register latched in the value at Port 0 when the Strobe pin made a low to high transition No further strobes will be available until a read of the Compare Register is made You must read the Compare Register and then clear interrupts so that the latched value in the compare register is not lost To enter Strobe mode set bits 4 3 of the DIO Control register to 01 Wake on aDIO The aDIO Strobe Match and Event interrupt can be used to generate a wake event This event can wake the CPU from any power down mode including Soft Off S5 Wake from aDIO will work as long at 5V Standby power is applied to the board To use the aDIO to wake the system Wake from aDIO must first be enabled in the BIOS setup utility Then the aDIO is configured in the appropriate interrupt mode The Wake Enable bit is then set in the Wake Control Register at 0x9C4 The CPU can
43. K1 54 55 GND GND 56 57 Reserved Reserved 58 59 Reserved Reserved 60 61 GND GND 62 63 Reserved Reserved 64 65 Reserved Reserved 66 67 GND GND 68 69 Reserved Reserved 70 71 Reserved Reserved 72 73 GND GND 74 75 Reserved Reserved 76 77 Reserved 2 Reserved 78 79 GND 2 GND 80 81 SATA 1Tp SATA OTp 82 83 SATA 1TIn SATA OTn 84 85 GND GND 86 87 88 89 90 91 GND GND 92 93 Reserved Reserved 94 95 Reserved Reserved 96 97 GND GND 98 99 Reserved Reserved 100 101 Reserved Reserved 102 103 GND GND 104 BDM 610000075 Rev D Table30 PCle 104 Type 2 Bus Signal Assignments Top View Pin Signal Signal Pin 105 STK2 Reserved 106 107 GND GND 108 109 Reserved Reserved 110 111 Reserved Reserved 112 113 GND GND 114 115 Reserved Reserved 116 117 Reserved Reserved 118 119 GND GND 120 121 Reserved Reserved 122 123 Reserved Reserved 124 125 GND GND 126 127 Reserved Reserved 128 129 Reserved Reserved 130 131 GND GND 132 133 SATA 1Rp SATA ORp 134 135 SATA 1Rn SATA ORn 136 137 GND GND 138 139 140 141 142 143 GND GND 144 145 Reserved Reserved 146 147 Reserved Reserved 148 149 GND GND 150 151 Reserved Reserved 152 153 Reserved Reserved 154 155 GND GND 156 1 Signals marked with are active low PCle 104 Type 2 Compatibility The PCle 104 Type 2 connector is compatible with any PCI 104 Express or PCle 104 peripheral module that does not use the x16 Link This includes any car
44. OM2 amp 4 2x5 0 1 3M 89110 0001 CN10 Connector 2x5 0 1 3M 89110 0001 CN11 Audio Connector 2x8 0 1 3M 89116 0001 CN13 RTC Battery Input optional 1x2 2mm FCI 69305 002LF CN15 Fan Power switched 1x3 2mm FCI 69305 003LF CN17 USB 2 0 2x5 0 1 3M 89110 0001 CN18 Video SVGA 2x5 2mm FCI 89947 710LF CN19 Flat Panel Video LVDS 2x10 2mm FCI 89947 720LF CN20 Ethernet 2x5 0 1 3M 89110 0001 CN30 Ethernet 2x5 0 1 3M 89110 0001 U6 SATA Disk Chip Socket 18 pin 0 1 na Chapter 3 Connecting the cpuModule 25 Auxiliary Power CN3 The Auxiliary Power connector CN3 can be used to supply power to devices that are attached to the cpuModule These devices include hard drive front end boards for data acquisition systems and other devices Power can also be conveyed to the module through the Auxiliary Power connector CN3 The cpuModule only requires 5 VDC and ground for operation A Standby 5V may also be supplied to allow the system to support Standby power states Note Although it is possible to power the cpuModule through the Auxiliary Power connector the preferred method is to power it through the bus connector from a power supply in the stack The cpuModule can have large current transients during operation which make powering it through wires difficult Powering through the bus eliminates such problems as voltage drop and lead inductance If using the Auxiliary Power connector to power the
45. Rev D Chapter 1 Introduction 1 CMX32M cpuModules RTD s CMX32M cpuModule represents the latest in high performance energy efficient embedded computing solutions Based on the Intel Montevina platform it features a 64 bit Penryn processor coupled with a GS45 chipset It includes a source synchronous Front Side Bus FSB operating up to 1066 MHz and up to 6 MB of L2 cache This cpuModule is available either with a dual core Core 2 Duo processor or a single core Celeron M processor The Core 2 Duo processor features Enhanced Intel SpeedStep technology which enables real time dynamic switching between multiple voltage and frequency points This results in optimal performance without compromising low power A dual channel DDR2 memory interface operating at up to 800 MHz ensures adequate memory bandwidth to keep up with both processors All memory chips are soldered directly onto the board The video interface is provided by an Analog SVGA output and an LVDS flat panel output The two outputs are independent and can display separate images and display timings Maximum resolution is 2048 x 1536 High speed peripheral connections include USB 2 0 with up to 480 Mb sec data throughput A Serial ATA SATA controller provides a fast 3 0 Gbps connection to the hard drives Network connectivity is provided by an integrated 10 100 1000 Mbps Ethernet controller Other features include two RS 232 422 485 COM ports AC97 audio Advanced Analo
46. S Port 71 0 mA lo 1 0 mA SVGA Port 80 mA lo 80 mA 4 0 mA lg 80 mA R 3k R 3k Min 0 5A 250 mV 1 125 V 2 97 2 4 V 0 0 V 2 4 V 0 0 V 2 0 V 0 3 V 5 0 V 10 0 V 2 4 V 25 V Max 5 0A 450 mV 1 375 V 1 0 A 1 8 A 3 3 V 0 33 V 3 6 V 0 8 V 3 3 V 0 5 V 3 3 V 0 4 V 5 5 V 0 8 V 500 mA 10 0 V 5 0 V 25V 0 8 V BDM 610000075 Rev D BDM 610000075 Rev D luritvec Table4 Electrical Characteristics Parameter Test Condition Serial Ports RS 422 485 Differential Output 50 Ohm Differential Output 27 Ohm Common Mode 27 or 50 Output Ohm Differential Input 7V lt Vem lt 7V Threshold Absolute Max Input Voltage aDIO Output Voltage High 4 0 mA Output Voltage Low lg 8 0 Input Voltage High Input Voltage Low Supply current aAlO Absolute maximum Input Voltage Absolute minimum Input Voltage Input Impedance Unipolar Bipolar Audio Full Scale Output Voltage External Load Line Output Impedance External Load Headphone Impedance Output External Load Capacitance Full Scale Input 0 dB Boost Voltage 10 dB Boost 20 dB Boost 30 db Boost Input Impedance Input Capacitance Utility Port Connector CN5 Input RTC Voltage Utility Supply Current Min Max 2 0 V 6 0 V 15V 6 0 V 0 0 V 3 0 V 0 3 V 0 3 V 25 V 25V 2 4 V
47. X supply is used to power the cpuModule lower power modes can be achieved During these low power modes the standby power from the ATX power supply provides power to a small circuit on the CPU which is used to watch for a system wake event ATX Power Supply Signals The auxiliary power connector CN3 provides two ATX style signals 5V Standby and PSON The 45V Standby rail is used to power certain parts of the cpuModule when the main power supply is turned off i e during Suspend to RAM S3 Hibernate S4 or Soft Off 55 power modes The PSON signal is an active low open drain output that signals the power supply to turn on Use of these signals allows the power consumption to drop to below 1W during standby modes and still enable any of the wake events Reducing Power Consumption In addition to the CPU s low power modes power consumption can further be reduced by making some modifications to the BIOS setup When the following features are modified the CPU s power consumption will decreases e Speed Setting the processor to its minimum speed in the BIOS will reduce power consumption e Memory Speed Changing the DDR DRAM clock frequency will reduce power consumption however memory performance will also be reduced e Ethernet Can be disabled in the BIOS e Serial Ports Can be disabled in the BIOS e LVDS Flat Panel If an LVDS panel is not connected to the cpuModule while using a VGA monitor setting the BIOS to use only
48. add in card with the integrated graphics disabled The signals on the x16 link can also be used for additional outputs from the Integrated Graphics Device Contact RTD tech support for more details PCle 104 Type 1 Compatibility The PCle 104 Type 1 connector is compatible with any PCI 104 Express or PCle 104 Type 1 or Universal peripheral module This includes any card that uses the PCle x1 links PCle x16 link USB or a power supply If a card is installed that is not compatible with the Type 1 connector the CPU will keep the system in soft off and the LED will be Cyan to indicate that there is a Bus Stacking Error If this feature is not desired JP6 can be installed to disable the Bus Stacking Error detection feature PCle Link Configuration This cpuModule supports a total of eight PCle x1 links The chipset however only provides five PCle x1 links Four of the links on CN1 and CN2 are connected directly to the chipset The other four are connected through a PCle packet switch and share the bandwidth ofa single x1 link back to the chipset The links that are connected to the PCle switch do not support wake from S3 D3cold Only wake from S1 is supported Table 33 below shows the configuration of the PCle x1 links on Table33 2 Link Configuration Link BIOS Name Location Connection 53 Wake support PCle Peer To Peer 3 Link 3 Closest to CPU Direct Yes No 2 Link 2 Direct Yes No 1 Link 1 Direct Yes No 0 PCle Switch
49. an anti static wrist strap also known as an ESD wrist strap on the wrist of the technician or engineer Connector Locations Figure 5 shows the connectors and the SATA Disk Chip socket of the CMX32M cpuModule SVGA Ethernet CN30 HD Audio CN11 Video CN18 B LVDS Flat Panel COM2 amp 4 CN19 CN8 COM1 amp 3 CN7 aAlO CN10 Switched Fan CN15 USB 2 0 7 hee BM m d de aDIO 3 2 CN6 Ethernet Lu D CN20 gt i 7 Apacer t E Multi i gus Function E e irt CN5 Auxiliary Power PCle Bus Battery Disk Chip CN3 CN1 amp CN2 CN13 U6 Figure5 CMX32M Connector Locations Note Pin 1 of each connector is indicated by a white silk screened square on the top side of the board EN and a square solder pad on the bottom side of the board Pin 1 of the bus connectors match when stacking PC 104 modules 24 CMX32M cpuModule BDM 610000075 Rev D Table6 2 Basic Connectors BDM 610000075 Rev D Connector Function Size and Pitch Mating Connector CN1 PCle 104 Type 2 Bus Top 156 pin 0 635mm Samtec ASP 129646 03 CN2 PCle 104 Type 1 Bus Bottom 156 0 635mm Samtec ASP 129637 03 CN3 Auxiliary Power 1x10 0 1 FCI 65039 027LF CN5 Utility Port 2x5 0 1 3M 89110 0001 CN6 aDIO 2x8 0 1 3M 89116 0001 CN7 Serial Port 1 COM1 amp 3 2x5 0 1 3M 89110 0001 CN8 Serial Port 2 C
50. ble 22 RS 232 and COM B RS 232 36 2 cpuModule Signal Function In Out DB 9 1 DCD1 COM A Data Carrier Detect in 1 2 RXD2 COM B Receive Data in 6 3 RXD1 COM A Receive Data in 2 4 RTS1 COM A Request To Send out 7 5 TXD1 COM A Transmit Data out 3 6 CTS1 COM A Clear To Send in 8 7 TXD2 COM B Transmit Data out 4 8 Ring Indicate in 9 9 10 GND Signal Ground 5 BDM 610000075 Rev D Table23 RS 422 485 and COM B RS 232 BDM 610000075 Rev D Pin Signal Function In Out DB 9 1 DCD1 COM A Data Carrier Detect in 1 2 RXD2 COM B Receive Data in 6 3 RXD1 COM A Receive Data in 2 4 TXD1 COM A Transmit Data out 7 5 TXD1 COM A Transmit Data out 3 6 RXD1 COM A Receive Data in 8 7 TXD2 COM B Transmit Data out 4 8 Ring Indicate in 9 9 10 GND Signal Ground 5 Table24 RS 422 485 and COM B RS 422 485 Pin Signal Function In Out DB 9 1 RXD2 COM B Receive Data in 1 2 RXD2 COM B Receive Data in 6 3 RXD1 COM A Receive Data in 2 4 TXD1 COM A Transmit Data out 7 5 TXD1 COM Transmit Data out 3 6 RXD1 COM A Receive Data in 8 7 TXD2 COM Transmit Data out 4 8 TXD2 COM B Transmit Data out 9 9 10 GND Signal Ground 5 Chapter 3 Connecting the cpuModule 37 Advanced Digital I O aDIO Port CN
51. d that uses the PCle x1 links USB or a power supply In addition this connector can be used to add SATA devices to the system If a card is installed that is not compatible with the Type 2 connector the CPU will keep the system in soft off and the LED will be Cyan to indicate that there is a Bus Stacking Error If this feature is not desired JP6 can be installed to disable the Bus Stacking Error feature BDM 610000075 Rev D Chapter 3 Connecting the cpuModule 45 PCle Link Configuration This cpuModule supports a total of eight PCle x1 links The chipset however only provides five PCle x1 links Four of the links on CN1 and CN2 are connected directly to the chipset The other four are connected through a PCle packet switch and share the bandwidth ofa single x1 link back to the chipset The links that are connected to the PCle switch do not support wake from S3 D3cold Only wake from S1 is supported Table 31 and below shows the configuration of the PCle x1 links on CN1 Table31 CN1 Link Configuration Link BIOS Name Location Connection 53 Wake support Peer To Peer 0 Link 0 Closest to CPU Direct Yes No 1 PCle Switch Shared No To other Shared 2 PCle Switch Shared No To other Shared 3 PCle Switch Farthest from CPU Shared No To other Shared PCle Peer To Peer Peer to Peer transactions are transactions directly between two PCle peripheral cards An example of this is writing data directly from a data acquisit
52. dix C Dimensions and Pinout 101 102 CMX32M cpuModule Table69 COM1 COM2 RS 232 9 D Connector male IDAN Pin Signal Function Mode 1 DCD Data Carrier Detect Input 2 RXD Receive Data Input 3 TXD Transmit Data Output 4 DTR Data Terminal Ready Output 5 GND Ground 6 DSR Data Set Ready Input 7 RTS Request To Send Output 8 CTS Clear To Send Input 9 RI Ring Indicator Input Table 70 COM1 COM2 RS 422 485 9 Pin D Connector male IDAN Pin Signal Function Mode 1 Reserved 2 RXD Receive Data Input 3 TXD Transmit Data Output 4 Reserved 5 GND Ground 6 Reserved 7 TXD Transmit Data Output 8 RXD Receive Data Input 9 Reserved BDM 610000075 Rev D Table71 aDIO 26 Pin D Connector female IDAN Pin Port CPU Pin 1 P0 0 1 2 P0 1 2 3 P0 2 3 4 P0 3 4 5 P0 4 5 6 P0 5 6 7 P0 6 7 8 P0 7 8 9 Strobe 0 9 10 Strobe 1 10 11 P1 0 11 12 P1 1 12 13 P1 2 13 14 P1 3 14 15 GND 15 16 5V 16 17 reserved 18 reserved 19 GND 20 GND 21 GND 22 GND 23 GND 24 reserved 25 reserved 26 reserved BDM 610000075 Rev D Appendix C Dimensions and Pinout 103 Table72 9 Pin D Connector male IDAN Pin aAlO Port CPU Pin 1 Channel 1 1 2 Channel 3 3 3 Channel 5 5 4 Channel 7 7 5 GND 9 6 Channe
53. e CU Connect a VGA monitor to the SVGA connector Refer to the remainder of this chapter for details on each of these steps BDM 610000075 Rev D Chapter 2 Getting Started 15 Connector Locations Figure 3 shows the connectors and the SATA Disk Chip socket of the CMX32M cpuModule SVGA Ethernet CN30 HD Audio CN11 Video CN18 B LVDS Flat Panel COM2 amp 4 CN19 CN8 COM1 amp 3 CN7 aAlO CN10 Switched Fan CN15 USB 2 0 CN17 aDIO CN6 Ethernet CN20 gt t Multi Function CN5 Pd SATA Auxiliary Power PCle Bus Battery Disk Chip CN3 CN1 amp CN2 CN13 U6 Figure3 CMX32M Connector Locations EN Note Pin 1 of each connector is indicated by a white silk screened square on the top side of the board iV square solder pad on the bottom side of the board 16 2 cpuModule BDM 610000075 Rev D Table5 CMX32M Basic Connectors Connector Function Size and Pitch Mating Connector CN1 PCle 104 Type 2 Bus Top 156 pin 0 635mm Samtec ASP 129646 03 CN2 PCle 104 Type 1 Bus Bottom 156 pin 0 635mm Samtec ASP 129637 03 CN3 Auxiliary Power 1x10 0 1 FCI 65039 027LF CN5 Utility Port 2x5 0 1 3M 89110 0001 CN6 aDIO 2x8 0 1 3M 89116 0001 CN7 Serial Port 1 COM1 amp 3 2x5 0 1 3M 89110 0001 CN8 Serial Port 2 COM2 amp 4 2x5 0 1 3M 89110 0001 CN10 aAIO Connector 2x5 0 1 3M 89110 0001 CN11 Aud
54. e PCI Express x16 Lane TwoUSB 2 0 SMBus e Advanced Thermal Management Thermal Monitor throttles processor and memory to prevent thermal runaway Auto Fan Control only runs fan when needed SMBus Temperature Monitor for CPU and board temperature Mini Fan Heatsink with Auto Fan control Passive Structural Heatsink amp Heatpipes in IDAN and HiDAN System Configurations e Advanced Programmable Interrupt Controller APIC 24 interrupt channels with APIC enabled 15 in legacy PIC mode High Precision Event Timer e Advanced Configuration and Power Interface ACPI ACPI 3 0 Compliant Supported power down modes 1 Power On Suspend S3 Suspend to S4 Hibernate and S5 Soft Off Clock Throttling and Clock Stop for to Support 6 CMX32M cpuModule BDM 610000075 Rev D 610000075 Wake events include aDIiO Interrupt e Wake on LAN e Real Time Clock e COM port Ring e Power Switch etc e Network Boot supported by Intel PXE e 2 compliant Real Time Clock external battery required e Nonvolatile storage of CMOS settings without battery e Advanced Watchdog timer e Complete PC compatible Single Board Computer e SVGA controller Onboard with 3D Acceleration Intel Graphics Media Accelerator 4500MHD Generation 5 0 graphics engine with 10 cores Dynamic Video Memory up to 256MB DirectX 10 Support Supports Windows Vista Aero Glass Effects Analog SVGA Output
55. e actual boot time of the CPU However the CPU may boot before the monitor powers on NVRAM Updates System configuration data is stored in the onboard NVRAM When the system configuration changes this information must be updated If an update is necessary it will happen at the end of POST the BIOS will display an Updating NVRAM message The NVRAM update takes a few seconds and increases the boot time Once the NVRAM is updated boot times will return to normal NVRAM updates only happen when the system configuration changes They do not happen spuriously They are usually triggered by adding or removing a PCI device from a stack Updates can also be triggered by altering the Plug n Play configuration of the BIOS Boot Device Order The BIOS contains a list of devices to try booting from If you wish to boot to a particular device for example a hard drive make sure that it is first in the boot order This will speed up boot times BDM 610000075 Rev D Chapter 4 Using the cpuModule 87 System Recovery Reset Button Recovery The CMX32M provides several methods for recovering from an incorrectly configured system In order to enter the recovery mode follow the steps below 1 Remove power from the system including standby power 2 Press and hold the reset button attached to the Utility Connector 3 Apply power to the system while continuing to hold the reset button 4 Wait the amount of time shown in Table 63 for the desi
56. e time below OC e Variable The fan will spin slowly until the CPU reaches 60C and then will increase speed Maximum speed is reached when the CPU reaches 75C Further Temperature Reduction The cpuModule s temperature is directly related to power consumption Reducing the power consumption of the CPU will have an effect on the CPU s temperature Suggested methods for reducing the CPU s power consumption can be found in the Power Management section on page 82 BDM 610000075 Rev D Chapter 4 Using the cpuModule 81 Power Management The CMX32M cpuModule supports various powering mechanisms which allow the cpuModule to monitor power consumption and temperature and achieve minimal power consumption states These unique features include Enhanced Intel SpeedStep Technology Core 2 Duo only thermal monitoring and thermal throttling as well as low power modes including ACPI configurations Various wake options are also available to resume normal system power Enabling Enhanced Intel SpeedStep Technology Core 2 Duo When enabled Enhanced Intel SpeedStep Technology can give application software greater control over the processor s operating frequency and input voltage This allows the system to easily manage power consumption dynamically This feature can be enabled or disabled in the BIOS When enabled the feature can be set to several different modes which are described below e Disabled The processor speed is set to its maximum o
57. ed on the value of SELECT CGT CHANNEL in on page 69 These can be though of as rows in a scan table each associated with a specific A D channel When a scan is started either by the pacer clock or a software trigger channel 1 is sampled Then the NEXT CHANNEL pointer is followed to select the next channel to scan The NEXT CHANNEL pointer is followed until it is a value of 0 which ends the scan There are a few implications 1 Thefirst channel to be scanned must always be Channel 1 2 Each channel may only be sampled once per scan 3 scan list must end with a NEXT CHANNEL of 0 Otherwise the channels will continue to scan without waiting for the pacer clock The channel associations for CGT CHANNEL and NEXT CHANNEL are shown below Table 52 Channel Gain Table Channels BDM 610000075 Rev D CGT_CHANNEL NEXT_CHANNEL Value 0 1 Single Ended Channel 1 Pin 1 Channel 2 Pin 2 Channel 3 Pin 3 Channel 4 Pin 4 Channel 5 Pin 5 Channel 6 Pin 6 Channel 7 Pin 7 Channel 8 Pin 8 Differential Ch1 Ch2 Ch2 Ch1 Ch3 Ch4 Ch4 Ch3 Ch5 Ch6 Ch6 5 Ch7 Ch8 Ch8 Ch7 Chapter 4 Using the cpuModule 71 Ox9EC NEXT CHANNEL Register Bit 7 6 5 4 3 2 1 0 Mode R R R R R R W Default 0 0 0 0 0 Channel 1 Field Rsvd Rsvd Rsvd Rsvd Rsvd NEXT CHANNEL NEXT CHANNEL The next channel to sample i
58. em wake functions Thermal Press Enter to select Monitor the cpuModule temperature or activate thermal or fan modes Exit Press Enter to select Save or discard changes and exit the BIOS or load the default BIOS settings Note Future BIOS versions may have slightly different setup menus and options BDM 610000075 Rev D Chapter 4 Using the cpuModule 55 Memory Table 38 shows how memory in the first megabyte is allocated in the system Table38 First Megabyte Memory Map Address hex Description C0000 FFFFFh ROM 256 KB BIOS in Flash EPROM shadowed into DRAM during runtime C0000 EFFFFh Run time user memory space Usually memory between C0000h and CFFFFh is used for the BIOS of add on VGA video cards A0000 BFFFFh Normally used for video RAM as follows EGA VGA 0A0000 0AFFFFh Monochrome 0B0000 0B7FFFh CGA 0B8000 0BFFFFh 00502 9FFFFh DOS reserved memory area 00400 00501h BIOS data area 00000 003FFh Interrupt vector area Memory beyond the first megabyte can be accessed in real mode by using EMS or a similar memory manager See your OS or programming language references for information on memory managers 56 2 cpuModule BDM 610000075 Rev D Address As with all standard PC 104 boards the I O total I O space is 64k in size However because early processors only addressed 10 address lines SA0 SA9 the first 1k is used for legacy I O devices Any ISA add on modules you install
59. er Button input Battery input for Real Time Clock Table 8 provides the pinout of the multi function connector Table8 Utility Port Connector CN5 Pin Signal Function In Out 1 SPKR Speaker Output open collector out 2 PWR 5 out 3 RESET Manual Push Button Reset in 4 PWRSW Soft Power Button in 5 KBD Keyboard Data in out 6 KBC Keyboard Clock out 7 GND Ground 8 MSC Mouse Clock out 9 BAT RTC Battery Input in 10 MSD Mouse Data in out Facing the connector pins the pinout is Speaker 10 9 7 5 3 1 5 8 6 4 PWR A speaker output is available on pins 1 and 2 of the multi function connector These outputs are controlled by a transistor to supply 0 1 W of power to an external speaker The external speaker should have 8 Q impedance and be connected between pins 1 and 2 BDM 610000075 Rev D Chapter 3 Connecting the cpuModule 27 Keyboard A PS 2 compatible keyboard can be connected to the multi function connector Usually PC keyboards come with a cable ending with a 5 pin male PS 2 connector Table 9 lists the relationship between the multi function connector pins and a standard PS 2 keyboard connector Table9 Keyboard Connector Pins CN5 Pin Signal Function PS 2 5 KBD Keyboard Data 1 6 KBC Keyboard Clock 5 7 GND Ground 3 2 PWR Keyboard Power 45 V 4 To ensure correct operation check that the keyboard is either an AT compatible keyboard or a switchable XT AT keyboa
60. ests possible solutions If you are having problems with your cpuModule review this table before contacting RTD Technical Support Problem cpuModule will not boot Table 66 Troubleshooting Cause no power or wrong polarity Solution check for correct power on the PC 104 Plus PCI bus connector incorrect Setup reboot and press Delete to run Setup defective or misconnected device on bus check for misaligned bus connectors remove other cards from stack incorrect PCle 104 cards installed LED is Cyan See PCle 104 Type 1 Compatibility on page 50and PCle 104 Type 2 Compatibility on page 45 cable connected backwards verify all cables are connected correctly cpuModule keeps rebooting problem with power supply reset switch is on watchdog timer is not being serviced quickly enough check for correct power on the PC 104 Plus PCI bus connector check that the reset button is not pushed in verify that the watchdog timer is being refreshed before it times out cpuModule will not boot from particular drive or device erratic operation device not bootable use sys command on drive or reformat the device using the s switch device not formatted power not connected to boot drive excessive bus loading format drive using s switch connect power cable to floppy or hard drive reduce number of modules in stack remove termination components from bus signals remove any powe
61. external 3 3V rails are not used by the cpuModule Any requirements on these signals are driven by other components in the system such as an LVDS Flat Panel or a PCI device 2 5V Standby is used to power the board when the main supply is turned off power down modes 53 55 It is not required for board operation 3 With supplied heat sink solution Depending on the CPU usage performance may degrade as the ambient temperature approaches the maximum Contact RTD Tech Support for more information BDM 610000075 Rev D Chapter 1 Introduction 11 Electrical Characteristics The table below lists the Electrical Characteristics of the CMX32M Operating outside of these parameters may cause permanent damage to the cpuModule 12 CMX32M cpuModule Symbol loc Table4 Electrical Characteristics Parameter Overcurrent Limit Differential Output Voltage Offset Voltage Supply Current for Panel Electronics Supply Current for Backlight Output Voltage High DDC FP ENABLK Output Voltage Low DDC FP ENABLK Input Voltage High DDC Input Voltage Low DDC Output Voltage High HSYNC VSYNC Output Voltage Low HSYNC VSYNC Output Voltage High DDC Output Voltage Low DDC Input Voltage High DDC Input Voltage Low DDC Supply Current for DDC Electronics Serial Ports RS 232 Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Test Condition USB Ports Each port LVD
62. ff the corresponding bit in the DIO Compare register Writing a one to a bit in this register masks off the corresponding bit in the DIO Compare register When all bits are masked off the aDIOs comparator is disabled This condition means Event and Match mode will not generate an interrupt This register is used by Event and Match modes Compare Register A Read Write register used for Match Mode Bit values in this register that are not masked off are compared against the value on Port 0 A Match or Event causes bit 6 of DIO Control to be set and if the aDIO is in Advanced interrupt mode the Match or Event causes an interrupt BDM 610000075 Rev D Chapter 4 Using the cpuModule 61 Table 48 Wake Control 1 O Address 9C4h D7 D6 D5 D4 D3 D2 D1 DO Reserved Int Mask Wake Enable 1 Interrupt is masked 1 Interrupt triggers a Wake Event O Interrupt is enabled O Interrupt does not trigger a wake event Port 1 Data register is a read write byte direction Interrupts In order to use an interrupt with aDIO the interrupt must first be selected in the BIOS setup utility under Advanced I O Devices aDIO Configuration aDIO Interrupt The Digital I O can use interrupts 3 5 6 7 10 11 and 12 The interrupt must also be reserved so that is it not assigned to PCI devices To reserve the interrupt enter the BIOS under PCIPnP and change the interrupt you wish to use to Reserved Then select the appropriate interrupt mode in the DIO Control
63. figuring the RTD Enhanced AMI BIOS The cpuModule Setup program allows you to customize the cpuModule s configuration Selections made in Setup are stored on the board and are read by the BIOS at power on Entering the BIOS Setup You can run Setup by rebooting the cpuModule and repeatedly pressing the Delete key When you are finished with Setup save your changes and exit The system will automatically reboot Field Selection To move between fields in Setup use the keys listed below Table36 Setup Keys Key Function Move between fields PgUp PgDn Selects next previous values in fields Enter Go to the submenu for the field Esc To previous menu then to exit menu 54 2 cpuModule BDM 610000075 Rev D Main Menu Setup Fields The following is a list of Main Menu Setup fields Table37 Main Menu Setup Fields Field Active Keys Selections Main Press Enter to select Access system information such as BIOS version EPLD version and CMOS time and date settings Advanced Press Enter to select Setup advanced cpuModule features PCIPnP Press Enter to select Set PnP and PCI options and control system resources Boot Press Enter to select Set the system boot sequence Security Press Enter to select Setup the supervisor and user access passwords or enable boot sector virus protection Power Press Enter to select Control power management settings including power supply type and syst
64. g I O aAIO and Advanced Digital I O RTD has gone the extra mile to include additional advanced features for maximum flexibility These include a SATA Disk Chip socket that allows flash drive with a standard SATA interface to be attached to the board either socketed or soldered An Advanced Watchdog Timer is provided that can generate an interrupt or reset when the timer expires SDRAM is soldered directly to the board for high vibration resistance The CMX32M is also available in a rugged fanless IDAN enclosure Ethernet CN30 HD Audio CN11 SVGA Video CN18 LVDS Flat Panel COM2 amp 4 CN19 CN8 COM1 amp 3 CN7 aAlO CN10 Switched Fan CN15 USB 2 0 CN17 aDIO CN6 Ethernet Multi Function CN5 Em SATA Auxiliary Power PCle Bus Battery Disk Chip CN3 CN1 amp CN2 CN13 U6 Figure 1 CMX32M cpuModule top view 2 CMX32M cpuModule BDM 610000075 Rev D Enhanced Intel SpeedStep Core 2 Duo only Enhanced Intel SpeedStep Technology has revolutionized thermal and power management by giving operating systems greater control over the processor s operating frequency and input voltage Systems can easily manage power consumption dynamically Today s embedded systems are demanding greater performance at equivalent levels of power consumption Legacy hardware support for backplanes board sizes and thermal solutions have forced design teams to place greater emphasis on power and thermal budgets In
65. hannel has its own DMA buffer e Buffer chaining prevents interrupt latency problems e to anywhere in 4GB address space e TwoUSB 2 0 Universal Serial Bus Ports Supports 480 Mb s high speed 12Mb s full speed and 1 5Mbs low speed peripherals 500 mA Q 5 Vdc provided per port USB Boot capability e Serial ATA SATA with RAID support Transfer rate up to 3Gb sec Integrated AHCI controller RAID O and 1 supported through Intel Matrix Storage Technology Compatability mode supports legacy operating systems e Disk Chip Socket Miniature SATA Flash Disk Chip Capacities up to 32GB Natively supported by all major operating systems e High Definition Audio Support 5 1 Surround Line Output Headphone Output Linelevel input Microphone input e Utility port PC AT compatible keyboard port PS 2 Mouse Port Speaker port 0 1W output Hardware Reset input Soft Power Button input Battery input for Real Time Clock e Power I O Power signals 1 During the time of this manual s publication 32GB was the largest available SATA Disk Chip capacity 8 CMX32M cpuModule BDM 610000075 Rev D BIOS e Enhanced AMI BIOS e User configurable using built in Setup program e Nonvolatile storage of CMOS settings without battery e Boot Devices Standard Devices floppy disk hard disk etc SATA Disk Chip USB Device Network Fail Safe Boot ROM e Surface mount Flash chip
66. he utility port connector CN5 The utility harness from the RTD cable kit provides a small speaker two connectors for the keyboard and mouse a push button for resetting the system a soft power button and a lithium battery to provide backup power for the real time clock Refer to Utility Port Connector CN5 on page 27 to connect devices to the utility port connector Connecting a Keyboard You may plug a PC AT compatible keyboard directly into the PS 2 connector of the utility harness in the cable kit You may also use a USB keyboard plugged into any of the USB connectors Note Many keyboards are switchable between PC XT and AT operating modes with the mode usually EN selected by a switch on the back or bottom of the keyboard For correct operation with this cpuModule you must select AT mode Booting the CMX32M cpuModule for the First Time You can now apply power to the cpuModule You will see e A greeting message from the VGA BIOS if the VGA BIOS has a sign on message e The cpuModule BIOS version information e Amessage requesting you press Delete to enter the Setup program e A message to press F11 to choose the boot device If you don t press Delete the cpuModule will try to boot from the current settings If you press Delete the cpuModule will enter Setup Once you have configured the cpuModule using Setup save your changes and reboot Note You may miss the initial sign on messages if your monitor takes a while to power
67. ing connect a 9V signal and start sampling in the 0 10V range the input to the A D will be over driven The A D requires approximately 150us to recover from an over driven condition When changing ranges be sure to start sampling before applying a signal that would be outside of the previous range BDM 610000075 Rev D Chapter 4 Using the cpuModule 77 Real Time Clock Control Overview The cpuModule is equipped with a Real Time Clock RTC which provides system date and time functions When the cpuModule is turned off a battery must be attached to the utility connector to provide power to the RTC Without power the RTC will lose the date time information when the system is turned off The RTC also provides an alarm function This may be used to generate an interrupt at a particular time and day This feature is commonly used to wake up the system from Sleep Standby to run a scheduled task defragment the hard drive back up files etc In addition to the date time alarm functions the RTC contains several bytes of battery backed RAM commonly called CMOS memory In a typical desktop PC the CMOS memory is used by the BIOS to store user settings This RTD cpuModule uses onboard flash to store user BIOS settings To preserve compatibility with traditional PCs the RTD Enhanced BIOS also mirrors the user settings from flash in CMOS Therefore the contents of CMOS may be overwritten at boot time and should be treated as read only Acce
68. io Connector 2x8 0 1 3M 89116 0001 CN13 RTC Battery Input optional 1x2 2mm FCI 69305 002LF CN15 Fan Power switched 1x3 2mm FCI 69305 003LF CN17 USB 2 0 2x5 0 1 3M 89110 0001 CN18 Video SVGA 2x5 2mm FCI 89947 710LF CN19 Flat Panel Video LVDS 2x10 2mm FCI 89947 720LF CN20 Ethernet 2x5 0 1 3M 89110 0001 CN30 Ethernet 2x5 0 1 3M 89110 0001 U6 SATA Disk Chip Socket 18 pin 0 1 n a WARNING If you connect power incorrectly the module will almost certainly be damaged or destroyed Such damage is not covered by the RTD warranty Please verify connections to the module before applying power Power is normally supplied to the cpuModule through the PCle bus connectors CN1 or CN2 If you are placing the cpuModule onto a PC 104 stack that has a power supply you do not need to make additional connections to supply power If you are using the cpuModule without a PC 104 stack or with a stack that does not include a power supply refer to Auxiliary Power CN3 on page 26 for more details BDM 610000075 Rev D Chapter 2 Getting Started 17 Selecting the Stack Order for the CMX32M There are several things to consider when selecting the order of boards in the stack Before selecting the order be sure to determine which bus connector on each board is the Active bus Typically if a peripheral module has both PCle and PCI bus connectors only the PCle is active and the PCI is pass through The following is a
69. ion card to a DSP card without first writing to the host CPU s memory The PCIe links that are directly connected to the chipset do not support Peer to Peer transactions The shared PCle links support peer to peer transactions to other shared links This is reflected in Table 31 above 46 2 cpuModule BDM 610000075 Rev D PCle 104 Type 1 Bus CN2 Bottom Connector CN2 carries the signals of the PCle 104 PCle bus These signals match definitions found in the PCI 104 Express amp PCle 104 Specification Version 2 01 from the PC 104 Embedded Consortium Table 32 lists the pinouts of the PCle 104 bus connector WARNING Not all PCle cards are compatible with the PCle 1 connector Be sure that all of the boards attached to this bus are compatible before powering the system BDM 610000075 Rev D Table32 PCle 104 Type 1 Bus Signal Assignments Top View Pin Signal Signal Pin 1 USB PE RST4 2 3 3 3V 3 3V 4 5 USB_1p USB_Op 6 7 USB_1n USB_On 8 9 GND GND 10 11 PEx1_1Tp PEx1 OTp 12 13 PEx1_1Tn PEx1_0Tn 14 15 GND GND 16 17 PEx1_2Tp PEx1_3Tp 18 19 PEx1_2Tn PEx1_3Tn 20 21 GND GND 22 23 PEx1_1Rp PEx1 ORp 24 25 PEx1 1Rn 2 PEx1_ORn 26 27 GND A GND 28 29 PEx1_2Rp PEx1_3Rp 30 31 PEx1_2Rn PEx1_3Rn 32 33 GND GND 34 35 PEx1_1Clkp PEx1 OCIkp 36 37 PEx1_1Clkn PEx1_0Clkn 38 39 5V_Always 5V_Always 40 41 PEx1_2Clkp PEx1 3Clkp 42 43 PEx1_2Clk
70. l 2 2 7 Channel 4 4 8 Channel 6 6 9 Channel 8 8 Table 73 Panel 20 Pin mini D Connector female IDAN Pin Signal Name CPU Pin 1 LVDS_YAPO 1 2 LVDS_DDCPCLK 3 3 LVDS_YAP1 5 4 LVDS_DDCPDATA 7 5 LVDS_YAP2 9 6 GND 11 7 LVDS_CLKAP 13 8 LVDS_YAP3 15 9 GND 17 10 FP_BKLT 19 11 LVDS_YAMO 2 12 GND 4 13 LVDS_YAM1 6 14 GND 8 15 LVDS_YAM2 10 16 GND 12 17 LVDS_CLKAM 14 18 LVDS_YAM3 16 19 FP_VCC 18 20 LVDS_BKLTCTL 20 104 2 cpuModule BDM 610000075 Rev D BDM 610000075 Rev D Table 74 SVGA 15 Pin High Density D Connector female IDAN Pin Signal Function CPU Pin 1 Red Red Analog Output 4 2 Green Green Analog Output 6 3 Blue Blue Analog Output 8 4 Reserved Reserved 5 GND Ground 9 6 GND Ground 9 7 GND Ground 9 8 GND Ground 10 9 45V 5 Volts 7 10 GND Ground 10 11 Reserved Reserved 12 DDC Data Monitor data 5 13 HSYNC Horizontal Sync 2 14 VSYNC Vertical Sync 1 15 DDC CLK Monitor Clock 3 Appendix C IDAN Dimensions and Pinout 105 106 2 cpuModule Table75 USB 9 Pin D Connector male IDAN Pin Signal Function Mode 1 5 V to USB1 output 2 Data USB1 USB1 Data input output 3 Data USB1 USB1 Data input output 4 GND Ground 5 GND Ground 6 vcc2 5 V to USB2 output 7 Data USB2 USB2 Data input output 8 Data USB2 USB2 Data input output 9 GND Ground
71. l Gain Table Analog to Digital Converter The Analog to Digital Converter used in aAIO is a 16 bit 100 ksps converter There is no calibration required and is typically accurate to within 10mV Programmable Digital Filter The programmable digital filter provides a single pole Infinite Impulse Response IIR filter on each channel This is a unity gain filter The filtered data has a value of D 4X Qe 1 NewSample n ORDER 2 D The response of the filter is shown in Figure 2 below Table 1 below shows the 3 dB cutoff for each of the filter settings Both the Figure and the Table are relative to the per channel sample rate f which is 40MHz PACERDIVIDER 1 BDM 610000075 Rev D Chapter 4 Using the cpuModule 65 dB Filter Gain 0 0001 0 001 0 01 0 1 1 Frequency Relative to FS Figure8 Filter Response with each ORDER Value Table50 Filter Cutoff Frequency ORDER 3 dB Cutoff 0 n a 1 0 114791 f 2 0 045995 f 3 0 021236 f 4 0 010255 f 5 0 005042 f 6 0 002501 f 7 0 001246 f Threshold Detect Threshold detection logic is provided to generate an interrupt when a channel crosses a high or low threshold The thresholds can be individually set and monitored for each channel Threshold crossings are only detected for a channel when that channel is sampled 66 2 cpuModule BDM 610000075 Rev D Data Output Direct Read The result from the most recent A D con
72. list of rules to use to determine the stack order 1 The PCle connectors above and below the CPU have completely separate signals Therefore it is possible to attach boards to the PCle connector above and below the CPU Any board that uses a PCle x16 x8 or x4 link must be stacked below the CPU It is recommended that these boards be directly below the CPU See PCI Express x16 Link on page 49 for details Any boards that a SATA link must be stacked above the CPU An example of this is hard drive carrier boards Any board that uses a PCle or SATA link must be within six boards of the CPU To preserve power integrity it is recommended that there be no more than six boards between the CPU and the power supply In order to maintain maximum performance over the full temperature range it is recommended that a PCle spacer be used between the CPU and any board immediately above it A maximum of four PCI boards may be attached to any PCI bus The PCle to PCI bridge must be at one end of the PCI bus segment and all of the peripheral cards at the other end There may be up to eight PCI pass through connectors between the PCle to PCI bridge and the peripheral cards There must be no more than two boards between the first PCI peripheral and the last PCI peripheral If there are four PCI peripheral cards in a PCI bus segment there may not be any PCI pass through connections between them 18 CMX32M cpuModule BDM 610000075 Rev D Stack Exam
73. n PEx1_3Clkn 44 45 CPU_DIR 5V PWRGOOD 46 47 SMB_DATA PEx16_Clkp 48 49 SMB_CLK PEx16_Clkn 50 51 n c PSON 52 Chapter 3 Connecting the cpuModule 47 48 2 cpuModule Table32 PCle 104 Type 1 Bus Signal Assignments Top View Pin Signal Signal Pin 53 WAKE 54 55 GND GND 56 57 PEx16_0T 8 p PEx16_0T 0 p 58 59 PEx16_0T 8 n PEx16_0T 0 n 60 61 GND GND 62 63 PEx16 OT 9 p PEx16 OT 1 p 64 65 PEx16_OT 9 n PEx16_0T 1 n 66 67 GND GND 68 69 PEx16 OT 10 p PEx16 OT 2 p 70 71 PEx16 OT 10 n PEx16 OT 2 n 72 73 GND GND 74 75 PEx16_0T 11 p PEx16_0T 3 p 76 77 16_07 1 2 PEx16_0T 3 n 78 79 GND 2 GND 80 81 PEx16 OT 12 p PEx16 OT 4 p 82 83 PEx16_0T 12 n PEx16_0T 4 n 84 85 GND GND 86 87 PEx16_0T 13 p PEx16_0T 5 p 88 89 PEx16 OT 13 n PEx16 OT 5 n 90 91 GND GND 92 93 PEx16 OT 14 p PEx16_0T 6 p 94 95 PEx16 OT 14 n PEx16_0T 6 n 96 97 GND GND 98 99 PEx16 OT 15 p PEx16 OT 7 p 100 101 PEx16 OT 15 n PEx16 OT 7 n 102 103 GND GND 104 BDM 610000075 Rev D PCI 104 Express PCle Bus Signals For a complete description of the PCI 104 Express Bus Signals consult the PCI 104 Express amp PCle 104 Table32 PCle 104 Type 1 Bus Signal Assignments Top View Pin Signal Signal Pin 105 SDVO DAT PENA SDVO CLK 106 107 GND GND 108 109 PEx16 OR 8 p PEx16_OR 0 p 110 111 PEx16 OR 8 n PEx16_OR 0 n 112 113 GND GND 114 115 PEx16 OR 9 p P
74. n the Channel Gain Table Read only during sampling Ox9ED CH MODE Register Bit 7 6 5 4 3 2 1 0 Mode R R R W R W R R W Default 0 0 0 0 0 101 Field Rsvd Rsvd DMA Rsvd Rsvd RANGE RANGE Selects the range of this channel and differential single ended as show below Read only during sampling Table 53 Channel Mode Value SE DIFF Range 0 000 DIFF 5V 1 001 DIFF 10V 2 010 DIFF 0 to 5V 011 DIFF 0 to 10V 4 100 SE 5V 5 101 SE 10V 6 110 SE 0 to 5V 7 111 SE 0 to 10V Set to 1 to enable DMA Data will be moved to the DMA buffer as soon as it is available 72 CMX32M cpuModule BDM 610000075 Rev D Ox9EE SGT ROW Register Bit 7 6 5 4 3 2 1 0 Mode R R W Default 0 0 Field Reserved SGT ROW SGT ROW The row in the Scatter Gather Table that is visible and can be modified by the SGT DATA register at Ox9FC Ox9EF FILTER CON Register Bit 7 6 5 4 3 2 1 0 Mode R R R R R R W Default 0 0 0 0 0 0 Field Rsvd Rsvd Rsvd Rsvd Rsvd ORDER ORDER Selects the order of the filter for this channel A value of 000 disables the filter See Programmable Digital Filter on page 65 Ox9F0 AD RESULT Register Bit 31 0 Mode R Default 0x00000000 Field AD RESULT AD RESULT The current value of the A D converter for this channel after filtering This is a 32 bit 2 s complement value with same 76 294 microvol
75. ne AD_RESULT Register Threshold Detect Channel Gain Table Figure 7 aAlO Block Diagram 64 2 cpuModule BDM 610000075 Rev D Analog Inputs The input multiplexer in aAlO accepts eight single ended analog inputs Any combination of ranges can be used for these inputs Pairs of analog inputs can be combined to form up to four differential inputs Channel Gain Table A Channel Gain table is provided to control the mode and range of each channel and the order that they are sampled in Each row in the scan table is associated with a specific A D channel When a scan is started either by the pacer clock or a software trigger channel 1 is sampled Then the NEXT CHANNEL pointer is followed to select the next channel to scan The NEXT CHANNEL pointer is followed until it is a value of 0 which ends the scan There are a few implications 1 Thefirst channel to be scanned must always be Channel 1 2 Each channel may only be sampled once per scan 3 Thescan list must end with a NEXT CHANNEL of 0 Otherwise the channels will continue to scan without waiting for the pacer clock The Channel Gain Table contains all of the channel specific settings and status This includes the mode single ended or differential and range It also contains the filter and threshold setting as well as the interrupt status and enable bits The A D Result register which returns the last conversion for this channel is also within the Channe
76. nector 5 e III een 27 5 conocen eios etos di 27 ric n 28 MOUSE AA E 28 System RESET een esee er EX xr amen 28 Soft Power dick pape 28 BACEN PP 29 SVGA Video Connector 18 30 BDM 610000075 Rev D Table of Contents v LVDS Flat Panel Video Connector 19 I hen 31 SATA Disk Chip Socket UG sssssssssssssssssssssss IH eme e hehehe 32 Installing and Configuring the SATA Disk Chip cesses ene 32 Serial Port 1 CN7 and Serial Port 2 8 emen 33 SerialPort UART csse soa ete UN ER ER IUE UNA MINER KNEE EHE 33 65 232 Serial Port Default vr ea e a RR 33 RS 422 or RS 485 Serial Port d e e e Ye xu 34 RS 422 and RS 485 Mode Pinout me heme hh he sehen 35 Dual Serial Port 222222 a eo rer Er 36 Advanced Digital I O aDIO Port teen m mesh 38 Advanced Analog I O aAIO Port CN10 6 I mesh 39 USB 2 0 Connector 17 _ ccc cnn eee hee esse aene 40 Ethernet 10 1
77. obe Digital IRQ Mode Multi Function 00 Disabled Register Select Digital IRQ Status 01 strobe Mode Port 1 Direction 00 clear mode 0 no digital interrupt 10 event mode 0 input 01 port 0 direction 1 digital interrupt 11 match mode 1 output 10 mask register 11 compare register Table 46 DIO Control I O Address 9C3h Write Access D7 06 05 04 03 02 01 00 Reserved Digital IRQ Mode Multi Function 00 Disabled Register Select 01 strobe Mode Port 1 Direction 00 clear mode _ 10 event mode 0 input 01 port 0 direction 11 match mode 1 output 10 mask register 11 compare register Table 47 Multi Function at Address 9C2h read write 00 clear X X X X X X X X Oin 1 out 01PortOdirection O 1 0 0 mask 1 mask 10 DIO mask M7 M6 M5 M4 M3 M2 M1 MO read write 11 compare C7 C6 C5 C4 C3 C2 Ci 1 Contents based on bits DO and 01 of DIO Control Clear Register A read to this register Clears the IRQs and a write to this register sets the DIO Compare DIO Mask DIO Control Port 1 and Port 0 to zeros A write to this register is used to clear the board Port 0 Direction Register Writing a zero to a bit in this register makes the corresponding pin of the aDIO connector an input Writing a one to a bit in this register makes the corresponding pin of the aDIO connector an output Mask Register Writing a zero to a bit in this register will not mask o
78. odule is available with a selection of processors and memory sizes The cpuModule can also be purchased as part of an Intelligent Data Acquisition Node IDAN building block which consists of the cpuModule and a milled aluminum IDAN frame The IDAN building block can be used in just about any combination with other IDAN building blocks to create a simple but rugged PC 104 stack Refer to Appendix C IDAN Dimensions and Pinout for more information The CMX32M cpuModule can also be purchased as part of a custom built RTD HiDAN or HiDANplus High Reliability Intelligent Data Acquisition Node Contact RTD for more information on its high reliability PC 104 systems CMX32M Model Options The basic cpuModule model options are shown below Refer to the RTD website www rtd com for more detailed ordering information and any new variations that may be available Cable Kits and Accessories Table 1 Part Number CMX32MVD1860HR 2048 CMX32MVD1860HR 1024 CMX32MVD1200HR 2048 CMX32MVD1200HR 1024 CMX32MCS1200HR 2048 CMX32MCS1200HR 1024 CMX32M cpuModule Model Options Description Core 2 Duo Dual Core 1 86 GHz 2GB DDR2 SDRAM Core 2 Duo Dual Core 1 86 GHz 1GB DDR2 SDRAM Core 2 Duo Dual Core 1 20 GHz 2GB DDR2 SDRAM Core 2 Duo Dual Core 1 20 GHz 1GB DDR2 SDRAM Celeron Single Core 1 20 GHz 2GB DDR2 SDRAM Celeron Single Core 1 20 GHz 1GB DDR2 SDRAM For maximum flexibility RTD does not provide cables with the cpuModule You may wi
79. on on the following topics The RTD Enhanced AMI BIOS page 54 Memory Map page 56 Address Map page 57 Hardware Interrupts page 58 Advanced Digital Ports aDIO page 60 Advanced Analog I O aAIO page 64 Real Time Clock Control page 78 Watchdog Timer Control page 80 Thermal Management page 81 Power Management page 82 Multi Color LED page 84 Reset Status Register page 85 Features and Settings That Can Affect Boot Time page 87 System Recovery page 88 BDM 610000075 Rev D Chapter 4 Using the cpuModule 53 The RTD Enhanced AMI BIOS The RTD Enhanced AMI BIOS is software that interfaces hardware specific features of the cpuModule to an operating system OS Physically the BIOS software is stored in a Flash EPROM on the cpuModule Functions of the BIOS are divided into two parts The first part of the BIOS is known as POST power on self test software and it is active from the time power is applied until an OS boots begins execution POST software performs a series of hardware tests sets up the machine as defined in Setup and begins the boot of the OS The second part of the BIOS is known as the CORE BIOS It is the normal interface between cpuModule hardware and the OS which is in control It is active from the time the OS boots until the cpuModule is turned off The CORE BIOS provides the system with a series of software interrupts to control various hardware devices Con
80. operating systems and do not require special drivers Table 14 SATA Disk Chip Socket U6 Pin Signal Pin Signal 1 GND 32 Vcc 3 3V 2 RX 31 GND 3 RX 30 n c 4 GND 29 n c 5 TX 28 n c 6 TX 27 7 GND 26 Reserved 8 no pin 25 no pin 9 no pin 24 no pin 10 no pin 23 no pin 11 no pin 22 no pin 12 no pin 21 no pin 13 no pin 20 no pin 14 no pin 19 no pin 15 Reserved 18 Reserved 16 n c 17 GND 1 TXand RX are the transmit and receive respectively of the Disk Chip Installing and Configuring the SATA Disk Chip To ensure proper installation of the SATA Disk Chip follow the following configuration steps 1 2 3 Always work at an ESD protected workstation and wear a grounded wrist strap Remove power from the system Insert the Disk Chip in the SATA Disk Chip Socket U6 aligning pin 1 with the square solder pad on the board Apply power to the system Re enter the BIOS and set the boot order of the system accordingly 32 CMX32M cpuModule BDM 610000075 Rev D Serial Port 1 CN7 and Serial Port 2 8 Serial Port 1 COM1 is implemented on connector CN7 and Serial Port 2 is implemented on connector CN8 The serial ports are normally configured as PC compatible full duplex RS 232 ports but you may use the BIOS Setup program to reconfigure these ports as half duplex RS 422 or full duplex RS 422 or RS 485 If you reconfigure the ports you must also select the I O addre
81. or nonmechanical drives Boot from USB devices and network are also supported The cpuModule and BIOS are also compatible with any real time operating systems for PC compatible computers although these may require creation of custom drivers to use the aDIO aAIO and watchdog timer 10 CMX32M cpuModule BDM 610000075 Rev D Specifications Physical Characteristics e Dimensions 116mm L x 99mm W x 24mm 4 6 L x 3 9 W x 0 95 H e Weight Approximately 0 20 Kg 0 44 Ib with Heatsink Power Consumption Exact power consumption depends on the actual application Table 2 lists power consumption for typical configurations and clock speeds Table2 cpuModule Power Consumption Module Speed RAM Power Typ Heavy CPU Heavy CPU Load amp Gfx Load CMX32MVD1860 1 86 GHz 1024 MB 21 0 W 31 5 W 33 0 W CMX32MVD1200 1 20 GHz 1024 MB 15 8 W 21 0 W 23 0 W CMX32MCS1200 1 20 GHz 1024 MB 13 3 W 16 0 W 19 5 W Operating Conditions Table 3 Operating Conditions Symbol Parameter Test Condition Min Max Vecs 5V Supply Voltage 4 75V 5 25V Vccs 3 3V Supply Voltage Vcci2 12V Supply Voltage 5V Standby Voltage 475V 5 25V 5V Standby Current 500mA Ta Ambient Operating MVD1860 40 70 Temperature Ta Ambient Operating MVD1200 40 85 Temperature MCS1200 Ts Storage Temperature 25 85C Rh Humidity Non Condensing 0 90 MTBF Mean Time Before 23C 275 000 Failure hours 1 The 12Vand
82. or to operate for short durations at a higher frequency than the thermal solution or ambient temperature would otherwise allow The thermal limit and duty cycle of the Thermal Monitor cannot be modified A second thermal monitor is used to throttle the memory interface when the memory controller or the memory approaches it s thermal limit This ensures proper operation even under the harshest conditions The thermal monitors operate independently of each other aDIO with Wake on aDIO RTD s exclusive aDIO is 12 digital bits configured as 8 bit direction programmable and 4 bit port direction programmable I O plus 2 strobe inputs giving you any combination of inputs and outputs Match event and strobe interrupt modes mean no more wasting valuable processor time polling digital inputs Interrupts are generated when the 8 bit direction programmable digital inputs match a pattern or on any value change event Bit masking allows selecting any subgroup of eight bits The strobe input latches data into the bit programmable port and generates an interrupt Any of the interrupt modes can be used to generate a wake event from any standby powerdown mode aAlO RTD s exclusive aAIO provides 8 single ended or 4 differential analog inputs providing a single board data acquisition solution Each input have a range or 5 10V 0 5V or 0 10V A maximum sample rate of 100kHz is shared between the channels A minimum sample rate of 9mHz one sam
83. perating frequency e Enabled The processor speed is controlled by the operating system Advanced Configuration and Power Interface ACPI The cpuModule supports several different ACPI low power modes including the 1 53 4 and S5 sleeping states The BIOS setup utility provides an option to select between S1 and S3 as the Standby state Sleep modes S4 and S5 are setup by the operating system The cpuModule s ACPI suspend modes are described below e 51 Power on Suspend The S1 low power state consumes the most power of all supported ACPI sleep modes In this mode the CPU stops executing instructions but power to the CPU and RAM is maintained e 53 Suspend to RAM Everything in the system is powered off except for the system memory When the system wakes from this mode operating systems allow applications to resume where they left off as the state of the application is preserved in memory 54 Hibernate When the system enters this state the operating system will save the current state of applications and relevant data to disk thus allowing the system RAM to be powered down e S5 Soft Off The system is in a soft off state and must be rebooted when it wakes Power Button Modes The soft power button input of the utility port connector CN5 can be configured by the operating system as a suspend button transition to S1 or S3 or as soft power button transition to S5 Consult your operating system documentation fo
84. ple The figure below shows an example of a complete system stack Most systems will be a subset of this example This example stack may be further expanded with PCle to PCle bridges or a PCle to PCI bridge PCle x1 Peripheral PCle PCle x1 Peripheral PCle Unconnected amp Unused PCle x1 Peripheral PCI Bus Segment PCle PCle 1 Peripheral PCle and SATA within PCle six boards of CPU USB Peripheral with pass through PCI USB Peripheral with pass through PCI PCI PCle SATA Hard Drive Carrier PCle Spacer to improve Spacer li PCle cooling CMX32M CPU PCle PCle x16Peripheral PCle PCle x1 Peripheral PCle No more than eight PCle x1 Peripheral PCI Pass Through PCle Connectors PCle x1 Peripheral PCle PCle x1 to PCI Bridge C Power Supply PCle and SATA within PCI PCle six boards of CPU no USB Peripheral with pass through PCI more than six boards PCI PCle between CPU and USB Peripheral with pass through power supply PCI PCle PCI Peripheral PCI All four PCI PCI Peripheral with pass through ISA Peripherals PCI ISA together PCI Peripheral with pass through ISA ISA PCI Peripheral with pass through ISA ISA Unconnected amp Unused ISA Bus Segment Figure 4 System Stacking Example BDM 610000075 Rev D Chapter 2 Getting Started 19 Connecting to the Stack The bus connectors of the cpuModule are simply plugged onto a PC 104 stack to connect
85. ple every 107 seconds allows unobtrusive background monitoring of signals The input range and mode differential vs single ended can be individually selected for each channel Any number of channels can be selected for sampling Advanced features include a programmable single pole IIR filter on each channel This allows the hardware to remove noise from the input signal The filter can be individually enabled and the coefficients adjusted for each channel The cutoff frequency can be adjusted down to 0 1296 of the sample rate BDM 610000075 Rev D Chapter 1 Introduction 3 The also provides interrupts on threshold crossing A high and low threshold can be set for each channel After sampling is started an interrupt can be generated if any of the signals cross the threshold This removes some of the CPU load for simple monitoring tasks ADMA engine with a scatter gather table allows efficient robust handling of data Up to 64 DMA buffers can be assigned to each channel After filling each buffer an interrupt can be generated to inform the driver that buffer is full so that the driver can empty it or assign a new buffer Because many buffers can be assigned interrupt latency problems are mitigated Also since each channel has it s own buffer software does not have to de interlace the data The DMA engine can send the data to anywhere in 4GB memory space 4 CMX32M cpuModule BDM 610000075 Rev D Ordering Information The CMX32M cpuM
86. pts eund 58 Non Standard Serial Port 59 Advanced Digital I O Ports 01 ccc cee cence e e memes hee 60 Digital O Register Sets EP e EI DRM E NER ER RR 60 Port 1 Data register is a read write byte direction cece 62 Interr pts as 62 Advanced Digital Interrupts e emnes 62 Event Mode sieves melee Re PUn DUC C D 62 E 62 apple 63 vi CMX32M cpuModule BDM 610000075 Rev D Wake on aDIO Advanced Analog I O aAIO F at res osse e er EH Block 1 Channel Gain Table Analog to Digital Converter Programmable Digital Filter Threshold Detect Data Direct DMA Engine Operating Simple Operation DMA Based Operation Register z erp ERR RR Register Control Registers Channel Gain Table Registers BIOS Setup Register Usage Board
87. r information on how to configure it The power button will always cause a transition to S5 if pressed for 4 seconds or longer without interaction from the operating system Low Power Wake Options The cpuModule supports several methods of waking from a low power state Several of these wake options are BIOS configurable and can be accessed directly from the Power menu in the BIOS setup e Resume aDIO This option allows the system to use an aDIO Strobe Match or Event interrupt to generate a wake event This event can wake the CPU from any power down mode including Soft Off S5 For more information refer to the section titled Wake on aDIO on page 63 e Resume on PME When enabled the system can wake when a signal is applied to the PME signal on the PCI bus or the WAKE signal on the PCle bus This includes wake up on onboard LAN controller 82 CMX32M cpuModule BDM 610000075 Rev D e Resume on RTC Alarm The RTC Alarm allows the system to turn on at a certain time every day AT vs ATX Power Supplies Both AT and ATX power supplies may be used with the CMX32M cpuModule however AT power supplies do not provide any standby power to the cpuModule When an AT power supply is used to power the system low power modes that require a standby power to wake the system will not be fully supported ATX power supplies do provide a standby power thus allowing the system to utilize all low power modes supported by the hardware When an AT
88. r supply bus terminations power supply noise power supply limiting examine power supply output with oscilloscope glitches below 4 75 VDC will trigger a reset add bypass caps examine power supply output with oscilloscope check for voltage drop below 4 75 Vpc when hard drive or floppy drive starts add bypass caps insufficient cabling through power connector increase wire gauge to connector power through bus connectors temperature too high add fan processor heatsink or other cooling device s See Thermal Management on page 81 memory address conflict check for two hardware devices e g Ethernet SSD Arcnet PCMCIA trying to use the same memory address check for two software devices e g EMM386 PCMCIA drivers etc trying to use the same memory addresses check for hardware and software devices trying to use the same memory address check for an address range shadowed see Advanced Setup screen while in use by another hardware or software device address conflict check for another module trying to use I O addresses reserved for the cpuModule between 010h and 01Fh check for two modules e g dataModules PCMCIA cards Ethernet trying to use the same I O addresses 96 2 cpuModule BDM 610000075 Rev D Problem keyboard does not work Table66 Troubleshooting Cause keyboard interface damaged by misconnection wrong keyboard type Solution e check if ke
89. r the serial port are selected in the BIOS Setup utility 4 IfaDIO is disabled the I O addresses listed will not be occupied BDM 610000075 Rev D Chapter 4 Using the cpuModule 57 Hardware Interrupts EN Note lf you add any expansion modules or other peripherals to the system you must ensure they do not use interrupts needed by the cpuModule or malfunctions will occur The CMX32M cpuModule supports the standard PC interrupts listed in Table 40 Interrupts not in use by hardware on the cpuModule itself are listed as available Similarly if the operating system is using APIC more IRGs will be available Table 40 Hardware Interrupts Used on the CMX32M cpuModule Interrupt Normal Use 0 Timer 0 1 Keyboard 2 Cascade of IRQ 8 15 3 COM2 4 COM1 5 Available 6 Available 7 Available 8 Real Time Clock 9 Available routed to IRQ 2 10 Available 11 Available 12 Mouse 14 SATA hard disk 15 SATA Disk Chip socket 1 IRQs 14 and 15 may be available if the SATA controller is not configured in Compatability Mode Will claim an IRQ line that is required by a legacy device To reserve an IRQ for a legacy device refer to the Note The cpuModule has onboard PCI devices that will claim IRQ lines In some instances a PCI device PnP PCI Configuration Setup fields in the BIOS Note A devices hardware interrupt will be available for use if the given device is not present in the system and the device
90. rd set to AT mode Switchable keyboards are usually set by a switch on the back or bottom of the keyboard Mouse A PS 2 compatible mouse can be connected to the multi function connector Table 10 lists the relationship between the multi function connector pins and a standard PS 2 mouse connector Table 10 Mouse Connector Pins CN5 Pin Signal Function PS 2 10 MSD Mouse Data 1 8 MSC Mouse Clock 5 7 GND Ground 3 2 PWR Keyboard Power 5 V 4 System Reset Pin 3 of the multi function connector allows connection of an external push button to manually reset the system The push button should be normally open and connect to ground when pushed The type of reset generated by this button can be set in the BIOS configuration utility Soft Power Button Pin 4 of the multi function connector allows connection of an external push button to send a soft power signal to the system The push button should be normally open and connect to ground when pushed For more information on the modes of the Soft Power Button refer to the Power Management section in Chapter 4 Using the cpuModule 28 CMX32M cpuModule BDM 610000075 Rev D Battery Pin 9 of the multi function connector is the connection for an external backup battery This battery is used by the cpuModule when system power is removed in order to preserve the date and time in the real time clock Connecting a battery is only required to maintain time when power is completely removed f
91. red recovery mode 5 Release the reset button allowing the system to boot Table 63 Reset Button Recovery Modes Hold Time Mode 0 4 seconds No recovery mode System will stay in reset while button is pressed 4 8 seconds Load Default BIOS Settings 8 12 seconds Serial POST Code Output 12 seconds BIOS Boot Block Recovery Load Default BIOS Settings Loading BIOS defaults allows recovery from an incorrectly configured display device incorrect boot options and many other incorrect settings It is also a good starting point when making BIOS changes After restoring defaults the BIOS settings should be reviewed and modified as needed The default BIOS can be restored either by using Reset Button Recovery or the Load Defaults option in the BIOS Serial Power On Self Test POST Code Output The POST Codes represents a series of events that take place in a system during the Power On Self Test If the POST fails the system will not boot as expected Knowing which POST code the failure occurred may help system debug This recovery mode configures serial port connector CN7 as dual RS 232 and sends the POST codes on the second port i e pin 7 is the transmit pin The port settings are 115kbps 8 bits no parity one stop bit When using this recovery mode the POST codes can be logged on another computer running terminal software Contact RTD technical support for more details BIOS Boot Block Recovery This recovery mode allows yo
92. register Also verify that the Int Mask bit is cleared in the Wake Control register Advanced Digital Interrupts There are three Advanced Digital Interrupt modes available These three modes are Event Match and Strobe The use of these three modes is to monitor state changes at the aDIO connector Interrupts are enabled by writing to the Digital IRQ Mode field in the DIO Control register Event Mode When this mode is enabled Port 0 is latched into the DIO Compare register at 8 33 MHz The aDIO circuitry includes deglitching logic The deglitching requires pulses on Port 0 to be at least 120 ns in width As long as changes are present longer than that the event is guaranteed to register Pulses as small as 60 ns can register as an event but they must occur between the rising and falling edge of the 8 33 MHz clock To enter Event mode set bits 4 3 of the DIO Control register to 10 Match Mode When this mode is enabled Port 0 is latched into the DIO Compare register at 8 33 MHz The aDIO circuitry includes deglitching logic The deglitching requires pulses on Port 0 to be at least 120 ns in width As long as changes are present longer than that the match is guaranteed to register Pulses as small as 60 ns can register as a match but they must occur between the rising and falling edge of the 8 33 MHz clock To enter Match mode set bits 4 3 of the DIO Control register to 11 Note Make sure bits 4 3 are set BEFORE writing the D
93. rom the cpuModule A battery is not required for board operation WARNING The optional RTC battery input connector CN13 should be left unconnected if the multi function connector CN5 has a battery connected to pin 9 BDM 610000075 Rev D Chapter 3 Connecting the cpuModule 29 SVGA Video Connector CN18 Table 11 provides the pinout of the video connector Table 11 SVGA Video Connector CN18 Pin Signal Function In Out 1 VSYNC Vertical Sync out 2 HSYNC Horizontal Sync out 3 DDCSCL Monitor Communications Clock out 4 RED Red Analog Output out 5 DDCSDA Monitor Communications Data bidirectional 6 GREEN Green Analog Output out 7 PWR 5 out 8 BLUE Blue Analog Output out 9 GND Ground out 10 GND Ground out Facing the connector pins of the SVGA Video connector CN18 the pinout is O PWR DDCSDA DDCSCL VSYNC 30 2 cpuModule BDM 610000075 Rev D LVDS Flat Panel Video Connector CN19 Table 12 provides the pinout of the Flat Panel Video connector CN19 FP VCC is configured for 3 3V by default Contact RTD to have FP VCC configured for 5 V FP VBKLT can be either 5 V or 12 V and can be selected with JP9 See Jumper Settings and Locations on page 90 for more details Table 12 Flat Panel Video Connector CN19 Pin Signal Function In Out 1 YOP LVDS Data 0 out 2 YOM LVDS Data 0 out 3 DDC CLK Panel Detection Clock out 4
94. s 4kB in size and 4kB aligned It also contains a flag to indicate that the entry is valid The Channel 1 Table also includes flags to stop DMA transfers restart the SGT or generate and interrupt These are flags that effect all channels and are only stored in the channel 1 table The DMA engine will transfer data using the same row of the SGT and the same offset for all channels This guarantees that the captured data is synchronized The DMA engine will always iterate through the SGT even if DMA is not enabled for any channels The Scatter Gather Table is not cleared at power up or during reset Therefore software must assume that it contains random invalid data Ox9FC SGT DATA Register Bit 31 12 11 9 8 7 6 5 4 0 Mode R W R R W R W R W R W R Default X X X X X X 00000 Field ADDRESS Rsvd IRQ STOP RESTART VALID Rsvd ADDRESS The upper 20 bits of a DMA buffer 4k in size and 4k aligned The DMA data will start at an offset of 0 into the buffer After it is full the DMA engine will advance to the next row in the table based on the flags IRQ Flag to generate and interrupt after this buffer is full The interrupt will be generated for all channels that DMA is enabled on This flag is only checked for Channel 1 STOP Flag to stop DMA on all channels after this buffer is full This flag is only checked for Channel 1 RESTART Flag to restart the SGT at row 0 after this buffer is full This flag
95. s high Ox9E4 PACER DIVIDER Register Bit 31 0 Mode R W Default 0x00000000 Field PACER_DIVIDER PACER_DIVIDER A 32 bit divider for the pacer clock Read only during sampling When the pacer clock rolls over the Channel Gain Table is scanned at a rate of 100kHz This register should only be modified when sampling is stopped The time between scans is ScanRate 40MHz PACERDIVIDER 1 The maximum sample rate is 100kHz The maximum scan rate is 100kHz divided by the number of channels scanned Any PACER DIVIDER value that would yield a sample rate of greater than 100kHz has undefined results except a PACER_DIVIDER value of 0x00000000 will sample at the fastest rate possible Ox9E8 CUR BUFFER OFFSET Register Bit 16 12 11 0 Mode R R Default 0 0 Field Reserved CUR BUFFER OFFSET CUR BUFFER OFFSET The offset into the current 4kB DMA buffer where data will be written next This is the same value for every channel i e the channels are always synchronized CMX32M cpuModule BDM 610000075 Rev D Ox9EA CUR SGT ROW Register Bit 7 5 4 3 0 Mode R R Default 0 0 Field Reserved CUR SGT ROW CUR SGT ROW The current row in the Scatter Gather Table that will be used for the next transfer This is the same value for every channel i e the channels are always synchronized Channel Gain Table Registers The registers described in this section are paged bas
96. se such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by RTD Embedded Technologies acts of god or other contingencies beyond the control of RTD Embedded Technologies or as a result of service or modification by anyone other than RTD Embedded Technologies Except as expressly set forth above no other warranties are expressed or implied including but not limited to any implied warranties of merchantability and fitness for a particular purpose and RTD Embedded Technologies expressly disclaims all warranties not stated herein All implied warranties including implied warranties for merchantability and fitness for a particular purpose are limited to the duration of this warranty In the event the product is not free from defects as warranted above the purchaser s sole remedy shall be repair or replacement as provided above Under no circumstances will RTD Embedded Technologies be liable to the purchaser or any user for any damages including any incidental or consequential damages expenses lost profits lost savings or other damages arising out of the use or inability to use the product Some states do not allow the exclusion or limitation of incidental or consequential damages for consumer products and some states do not allow limitations on how long an implied warranty lasts so the above limitations or exclusions may not apply to you This warranty gi
97. settings as well as devices attached to a system This section addresses some devices and settings that can increase or decrease a system s boot time Quick Boot The BIOS contains a Quick Boot option that minimizes the boot time of the system Quick Boot eliminates the exhaustive tests that are performed during Power On Self Test POST while maintaining the functionality of the board By enabling the Quick Boot feature your system can achieve 5 second boot times Add On Cards With BIOS Extensions Some add on cards have an integrated BIOS extension The most common examples are SCSI controllers and network cards with boot ROMs During POST the BIOS executes the card s extension code This extension code is third party code which is beyond RTD s control The BIOS extension will most likely increase the boot time Exactly how much it increases boot time will depend on the particular card and firmware version VGA Controller VGA controllers have a VGA BIOS that must be initialized during POST It can take some time to initialize the VGA BIOS Exactly how long will depend on the particular VGA controller and BIOS version Hard Drive Type During Hard Drive initialization each device must be probed Some devices take longer to probe 2 5 inch hard drives tend to take longer than 3 5 inch ones because they spin at a lower RPM Monitor Type Some monitors take a while to power on Desktop flat panels are especially slow This does not affect th
98. sh to purchase the CMX32M cpuModule cable kit P N XK CM95 which contains Multi function utility harness keyboard socket battery reset speaker Two serial port cables DIL 10 to DSUB 9 VGA monitor cable DIL 10 to high density 15 pin DSUB aDIO cable DIL 16 to DSUB 25 Two USB cables 5 pin SIL to USB A PCle 104 Type 2 break out board to connect SATA and USB Audio Cable DIL 16 to five 3 5mm Jacks Two Ethernet cables DIL 10 to RJ 45 For additional accessories refer to the RTD website BDM 610000075 Rev D Chapter 1 Introduction 5 Board Features e Processor Part Number Speed Cores L2 Cache FSB Speed CMX32MVD1860 1 86GHZ Two 6 MB 1066 MHz CMX32MVD1200 1 20 GHz Two 3 MB 800 MHz CMX32MCS1200 1 20 GHz One 1MB 800 MHz Intel 64 architecture for 64 bit processing Enhanced Intel SpeedStep Technology and dynamic FSB frequency switching Core 2 Duo only Enhanced Intel Dynamic Acceleration Technology and Enhanced Multi Threaded Thermal Management Core 2 Duo only Supports enhanced Intel Virtualization Technology Core 2 Duo only 45nm process e 1 GB or 2GBytes BGA DDR2 SDRAM Dual channel memory interface 800MHz Data Rate per channel Surface Mounted for maximum reliability e Stackable 156 pin PCle 104 Type 2 bus on top Four PCI Express x1 Lanes TwoSATA 2 0 TwoUSB 2 0 SMBus e Stackable 156 pin PCle 104 Type 1 bus on bottom Four PCI Express x1 Lanes On
99. sity D female module P N Adam Tech DB15SD module P N Adam Tech HDT26SD mating P N Adam Tech DB15PD mating P N Adam Tech HDT26PD 6 pin mini DIN female module P N Adam Tech MDE006W mating P N Adam Tech MDP006 9 pin D male module P N Adam Tech DEO9PD mating P N Adam Tech DEO9SD 1 604 1 164 1 176 964 596 436 De Sp P 415 000 FRONT 2 3 lt N 20 pin mini D female 15 pin high density D female 9 pin D male module P N 3M 10220 6212VC module P N Adam Tech HDT15SD module P N Adam Tech DEO9PD mating P N 10120 3000VE matingP N Adam Tech HDT15PD matingP N Adam Tech DEO9SD Z 1 604 1 189 415 000 Lig 096 S6ee c S80 l 000 REAR Figure 11 IDAN CMX32M Connectors 1 Heatsink fins not shown in Figure 11 extend 0 75 inches from the sides of the IDAN frame 2 Use40mm for this frame when calculating bolt lengths 100 CMX32M cpuModule BDM 610000075 Rev D External I O Connections BDM 610000075 Rev D Table 67 PS 2 Mouse 6 Pin mini DIN Connector female IDAN Pin Signal Function 1 MDAT Mouse Data 2 Reserved 3 GND Ground 4 5V 5 Volts 5 MCLK Mouse Clock 6 Reserved Table 68 Keyboard 6 mini DIN Connector female IDAN Pin Signal Function 1 KDAT Keyboard Data 2 Reserved 3 GND Ground 4 5 5 5 KCLK Keyboard Clock 6 Reserved Appen
100. ss and corresponding interrupt using Setup Table 15 provides the standard I O addresses and corresponding interrupts Table 15 Serial Port Settings 1 O Address hex IRQ 03F8 IRQ4 02F8 IRQ3 03E8 IRQ4 02 8 IRQ3 Serial Port UART The serial ports are implemented with a 16550 compatible UART Universal Asynchronous Receiver Transmitter This UART is capable of baud rates up to 115 2 kbaud in 16450 and 16550A compatible mode and includes a 16 byte FIFO Refer to any standard PC AT hardware reference for the register map of the UART For more information about programming UARTS refer to Appendix D RS 232 Serial Port Default The default serial port mode is full duplex RS 232 With this mode enabled the serial port connectors must be connected to RS 232 compatible devices Table 16 provides the serial port connector pinout and shows how to connect to an external DB 25 or DB 9 compatible serial connector Table 16 Serial Port in RS 232 Mode Pin Signal Function In Out DB 25 DB 9 1 DCD Data Carrier Detect in 8 1 2 DSR Data Set Ready in 6 6 3 RXD Receive Data in 3 2 4 RTS Request To Send out 4 7 5 TXD Transmit Data out 2 3 6 CTS Clear To Send in 5 8 7 DTR Data Terminal Ready out 20 4 8 RI Ring Indicate in 22 9 9 10 GND Signal Ground 7 5 BDM 610000075 Rev D Chapter 3 Connecting the cpuModule 33 Facing the serial port s connector pins the pinout is RS 422 or RS 485 Serial Port You
101. ssing the RTC Registers You may access the RTC date time and CMOS memory using the Index and Data Registers located at I O addresses 70h and 71h e Address 70h is the Index register It must be written with the number of the register to read or write Valid values are 00h to 7Fh e Address 71h is the Data register It contains the contents of the register pointed to by the Index To read write an RTC register you must first set the Index register with the register number and then read write the Data register A list of key RTC registers is shown in Table 54 below Table54 Real Time Clock Registers Registers Registers Function hex decimal 00h 0 RTC Seconds 02h 2 RTC Minutes 04h 4 RTC Hours 06h 6 RTC Day of Week 07h 7 RTC Day of Month 08h 8 RTC Month 09h 9 RTC Year 10 Status Register e Bit 7 RTC Update In Progress Read Only RTC registers should not be accessed when this bit is high e Bits 6 4 Divider for 32 768 KHz input should always be 010 e Bits 3 0 Rate select for periodic interrupt 78 CMX32M cpuModule BDM 610000075 Rev D Table54 Real Time Clock Registers Registers Registers Function hex decimal OBh 11 RTC Status Register B e Bit7 Inhibit Update When high the RTC is prevented from updating e Bit6 Periodic Interrupt Enable When high the RTC IRQ will be asserted by the periodic interrupt e Bit5 Alarm Interrupt Enable When high the RTC IRQ
102. t resolution for all ranges Range Bits 31 18 17 16 15 2 1 5V 0 0 0 A D Data 0 to 10V 0 0 A D Data 5 to 5V Sign Extend Sign Extend A D Data 2 Complement 10 to 10V Sign Extend A D Data 2 Complement 0 BDM 610000075 Rev D Chapter 4 Using the cpuModule 73 Ox9F4 IRQ STAT Register Bit 7 6 5 4 3 2 1 0 Mode R R R C R C R C R C R R C Default 0 0 0 0 0 0 0 0 Field Rsvd Rsvd Thresh Thresh DMA DMA Rsvd Sample High Low Error A T indicated the condition exists regardless of IRQ Write 1 to clear Sample A sample has been converted DMA An SGT row with the IRQ bit set has been filled DMA Error DMA for this channel didn t get serviced in time gap in data Thresh Low Channel is below the low threshold Thresh High Channel is above the high threshold Ox9F6 IRQ ENA Register Bit 7 6 5 4 3 2 1 0 Mode R R R W R W R W R W R R W Default 0 0 0 0 0 0 0 0 Field Rsvd Rsvd Thresh Thresh DMA DMA Rsvd Sample High Low Error T allows in interrupt to be generated if the corresponding bit in IRQ STAT is set Sample A sample has been converted DMA An SGT row with the IRQ bit set has been filled DMA Error DMA for this channel didn t get serviced in time gap in data Thresh Low Channel is below the low threshold Thresh High Channel is above the high threshold 74 CMX32M
103. tel has extended architectural innovation for saving power by implementing new features such as Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology allows the processor performance and power consumption levels to be modified while a system is functioning This is accomplished via operating system or application software which changes the processor speed and the processor core voltage while the system is operating A variety of inputs such as system power source processor thermal state or operating system policy are used to determine the proper operating state The software model behind Enhanced Intel SpeedStep Technology has ultimate control over the frequency and voltage transitions This software model is a major step forward over previous implementations of Intel SpeedStep technology Legacy versions of Intel SpeedStep technology required hardware support through the chipset Enhanced Intel SpeedStep Technology has removed the chipset hardware requirement and only requires the support of the voltage regulator processor and operating system Centralization of the control mechanism and software interface to the processor and reduced hardware overhead has reduced processor core unavailability time to 10 us from the previous generation unavailability of 250 ps Thermal Monitor The Intel Thermal Monitor is a feature on the CMX32M that automatically throttles the CPU when the CPU exceeds its thermal limit This allows the process
104. to other devices Follow the procedure below to ensure that stacking of the modules does not damage connectors or electronics WARNING Do not force the module onto the stack Wiggling the module or applying too much pressure may damage it If the module does not readily press into place remove it check for bent pins or out of place keying pins and try again For mechanical dimensions including board to board spacing see Physical Dimensions on page 93 1 Turn off power to the PC 104 system or stack Always work at an ESD protected workstation and wear a grounded wrist strap Select and install stand offs to properly position the cpuModule on the stack Remove the cpuModule from its anti static bag Check that pins of the bus connector are properly positioned D wk WY OM Check the stacking order make sure all of the busses used by the peripheral cards are connected to the cpuModule 7 Hold the cpuModule by its edges and orient it so the bus connector pins line up with the matching connector on the stack 8 Gently and evenly press the cpuModule onto the PC 104 stack 20 CMX32M cpuModule BDM 610000075 Rev D Connecting the Utility Cable The multi function connector CN5 implements the following interfaces e PC AT compatible keyboard e 5 2 mouse port e Speaker port 0 1W output e Hardware Reset input e Battery input for Real Time Clock e Power Button input To use these interfaces you must connect to t
105. ttery connect a backup battery to the multi function connector Troubleshooting a PC 104 System If you have reviewed the preceding table and still cannot isolate the problem with your CMX32M cpuModule please try the following troubleshooting steps Even if the resulting information does not help you find the problem it will be very helpful if you need to contact technical support 1 Simplify the system Remove items one at a time and see if one particular item seems to cause the problem 2 Swap components Try replacing items in the system one at a time with similar items BDM 610000075 Rev D Appendix B Troubleshooting 97 How to Obtain Technical Support If after following the above steps you still cannot resolve a problem with your CMX32M cpuModule please gather the following information e cpuModule model BIOS version and serial number e Listofall boards in system e List of settings from cpuModule Setup program e of autoexec bat and config sys files if applicable e Description of problem e Circumstances under which problem occurs Then contact RTD Technical Support Phone 814 234 8087 Fax 814 234 5218 E mail techsupportGrtd com 98 CMX32M cpuModule BDM 610000075 Rev D AppendixC IDAN Dimensions and Pinout cpuModules like all other RTD PC PCI 104 modules can be packaged in Intelligent Data Acquisition Node IDAN frames which are milled aluminum frames with integrated heat sinks and
106. ty and are subject to change without notice RTD Embedded Technologies Inc shall not be liable for errors or omissions in this manual or for any loss damage or injury in connection with the use of this manual Revision History Revision Date Reason for Change A 6 13 11 Initial Release B 7 11 11 Corrected Headphone Load Impedance in Table 4 on page 12 Corrected aAIO connector number in Table 26 on page 39 Corrected Audio pinout in Table 29 on page 42 2 17 12 Updated block diagram to clarify x1 links Clarified the meaning of AD RESULT register page 73 Added CN numbers to Figure 11 IDAN CMX32M Connectors page 100 D 9 21 12 Corrected LVDS Connector pin count and mating connector in Table 5 CMX32M Basic Connectors 17 and Table 6 CMX32M Basic Connectors 25 il CMX32M cpuModule BDM 610000075 Rev D CMX32M cpuModules www rtd com 1509001 and AS9100 Certified Accessing the Analog World iv CMX32M cpuModule BDM 610000075 Rev D Table of Contents Chapter 1 Introduction CMX32M cpuModules RUE pede ue 2 Enhanced Intel SpeedStep Core 2 Duo only HH e emen 3 nomiue 3 aDIO with 0 cece eee he he eme ehe he eme eh he he ehe ehe 3 Ordering Information s occcsececseisese ses e secl e ge aa DE eee Debs 5 CMX32M M del Options terra rex eese e E C oodd 5 Cable Kits
107. u to re load a BIOS that has been corrupted The BIOS can be loaded from a file on a USB key or other removable drive In order for this to work the boot block of the BIOS must still be intact Contact RTD tech support for more details 88 CMX32M cpuModule BDM 610000075 Rev D Appendix A Hardware Reference This appendix provides information on CMX32M cpuModule hardware including Jumper Settings and Locations page 90 Onboard PCI PCle Devices page 92 Physical Dimensions page 93 BDM 610000075 Rev D Appendix A Hardware Reference 89 Jumper Settings and Locations Many cpuModule options are configured by positioning jumpers Jumpers are labeled on the board as JP followed by a number Some jumpers have three pins allowing three settings e Pins 2 connected indicated as 1 2 e 2 and 3 connected indicated as 2 3 e pins connected 1 2 3 OOO Some jumpers have two pins allowing two settings e Pins 2 connected indicated as closed e Pins 2 unconnected indicated as open 1 2 Figure 9 shows the jumper locations that are used to configure the cpuModule Table 64 lists the jumpers and their settings JP5 T HH EE T j 6 zzz mom Apacer 90 2 cpuModule BDM 610000075 Rev D Figure9 2 Jumper Locations top side Table 64 CMX32M Jumpers Jumper Pins Function
108. version for a specific channel is always available in the AD RESULT register within the scan table The value returned is a 32 bit 25 complement value with same 76 294 microvolt resolution for all ranges DMA Engine For data collection operations a DMA engine is provided that will transfer the data results directly into system memory This allows maximum data transfer rate with minimal interaction from the host software In order to minimize the effects of interrupt latency multiple DMA buffers can be defined in a Scatter Gather Table Scatter Gather Table The DMA Engine contains a Scatter Gather Table SGT for each of the eight inputs The Scatter Gather Table consists of a list of up to 64 entries Each entry contains the physical address of a buffer that is 4kB in size and 4kB aligned It also contains a flag to indicate that the entry is valid The Channel 1 Table also includes flags to stop DMA transfers restart the SGT or generate and interrupt These are flags that effect all channels and are only stored in the channel 1 table The DMA engine will transfer data using the same row of the SGT and the same offset for all channels This guarantees that the captured data is synchronized The DMA engine will always iterate through the SGT even if DMA is not enabled for any channels The Scatter Gather Table is not cleared at power up or during reset Therefore software must assume that it contains random invalid data Operating Modes
109. ves you specific legal rights and you may also have other rights which vary from state to state RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 USA Website www rtd com BDM 610000075 Rev D Appendix E Limited Warranty 111 112 CMX32M cpuModule BDM 610000075 Rev D
110. will be asserted when the current time matches the alarm time e Bit4 Update Ended Interrupt Enable When high the RTC IRQ will be asserted every time the RTC updates once per second e Bit3 Square Wave Enable Not used e Bit2 Data Mode Sets the data format of the RTC clock calendar registers 02 BCD 1 binary This is typically set to BCD mode e Bit 1 Hours Byte Format Sets the hour byte to 12 or 24 hour time 0 12 hour 1224 hour This is typically set to 24 hour mode e BitO Daylight Savings Enable When high the RTC will automatically update itself for Daylight Savings Time It is recommended to leave this bit low and let the operating system manage time zones and DST OCh 12 RTC Status Register C Read Only e Bit 7 IRQ Flag Indicates that the Real Time Clock IRQ is asserted Goes high whenever one of the enabled interrupt conditions in Register B occurs e Bit6 Periodic Flag e Bit 5 Alarm Flag e Bit 4 Update Ended Flag e Bit 3 0 Reserved Reading this register will also clear any of set flag IRQ Periodic Alarm Update Ended Note that even if the interrupt source is not enabled in Register B the flags in Register C bits 4 5 and 6 may still be set ODh 13 RTC Status Register D e Bit7 Valid Time Date always reads 1 e Bit 6 Reserved e Bits 5 0 RTC Alarm Day of the Month Altering the contents of any unlisted RTC register may interfere with the operation of your cpuModule
111. yboard LEDs light verify keyboard is an AT type or switch to AT mode floppy drive light always on two hard drives will not work but one does cable misconnected both drives configured for master check for floppy drive cable connected backwards set one drive for master and the other for slave operation consult drive documentation floppy does not work data error due to drive upside down orient drive properly upright or on side will not boot when video card is removed illegal calls to video controller look for software trying to access nonexistent video controller for video sound or beep commands abnormal video flat panel is enabled disable the flat panel in the BIOS can only use 640 x 480 resolution in Windows flat panel is enabled disable the flat panel in the BIOS video drivers not installed install the video drivers will not boot from PCMCIA hard drive booting from PCMCIA is not supported boot from SSD use autoexec bat to load PCMCIA drivers run application from PCMCIA card COM port will not work in RS 422 or RS 485 modes not configured for RS 422 485 correctly configure serial port in Setup program COM port will not transmit in RS 422 or RS 485 mode not enabling transmitters control RTS bit of Modem Control Register to enable transmitters see Serial Port descriptions date and time not saved when power is off no backup ba

CMX32M Hardware Manual - RTD Embedded Technologies, Inc.

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