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ada1200 manual - RTD Embedded Technologies, Inc.

1. eerte ttes 1 4 P6 DMA Acknowledge Channel Factory Setting Disabled eet 1 4 P7 8254 Timer Counter Clock Sources Factory Settings CLK1 XTAL CLK2 OTI PCK 1 5 P8 Interrupt Source and Channel Factory Setting Jumpers on OT2 amp G Interrupt Chs Disabled 1 6 P9 DAC 1 Output Voltage Range Factory Setting 5 to 5 VOLS nnn 1 7 P10 DAC 2 Output Voltage Range Factory Setting 5 to 5 VOILS nn 1 8 P11 A D Data Word Bit State Set Factory Setting sese 1 8 P12 A D Converter Status External Gate 2 Monitor Factory Setting EOC A D Converter Status 1 9 S1 Base Address Factory Setting 300 hex 768 decimal nan 1 9 Pull up Pull down Resistors on Digital I O Lines sss 1 10 Resistor Configurable cM 1 12 CHAPTER 2 BOARD INSTALLATION 2 1 A MM D EE 2 3 External alGi ccn MERE 2 3 Connecting the Analog Input Pins sese sese 24 Connecting the Trigger In and Trigger Out Pins Cascading Boards esas 2 4 Connecting the Analog Outputs ADA1200 Only sss 2 5 Connecting the Timer Counters and Digital UO 2 5 Running the 1200DIAG Diagnostics Program sscsssssssssssssessssssssssssssssssecsssnsessssasssessussssssussssssecssssssesucsaseesccnseesee 2 5 CHAPTER 3 HARDWARE DESCRIPTION 3 1 A D Conversion dadas 3 3 A E a a a AOS 3 3 AID COlVELHEE A O A AO 3 3 Data Transfer AAA nn NN 3 4 D A Converters ADA 1200 Only
2. Required Equipment The following equipment is required for calibration Precision Voltage Source 10 to 10 volts Digital Voltmeter 5 1 2 digits Small Screwdriver for trimpot adjustment While not required the 1200DIAG diagnostics program included with example software is helpful when performing calibrations Figure 5 1 shows the board layout with the trimpots located along the top edge of the board TR2 and TR3 at left TR7 in middle and TR1 TR4 and TR6 at right a Jl 2 00 o oc Py D L sne q EET a am AD678 D O E CET S V80S IH 00000000 D 00000000 00000000 00000000000000 uM UE sE 88 Le T o o Di j o Qe son Q 272 SE Ca o o 006000096555 X im de D1200 ADA1200 dcs ED Qo DOD 1 DATA ACQUISITION amp Sam SYSTEM 00000 Sood fr e ques 74HCTS74 Q D 74HCT74 D 74HCT74 0000000000 70000000 YH000000 1000000000000 10000000 eha mi 2 ES D 74HCTo4 7000000000000 5 mE n 0000000000007 00980009000 oo o oo 82055 oo 00000000 oo 000000 uy D R 0000000000 x amp D Go do Real Time Devices Inc State College PA 16804 USA ol 9 o o o lo o Fig 5 1 Board Layout 5 3 A D Calibration Two procedures are used to calibrate the A D converter for all input voltage ranges The first procedure cali brates the converter for the unipolar range 0 to 10 volts and the second procedure calibrates the bipolar ra
3. Since the Control Word Register and the three Counters have separate addresses selected by the A4 Ao inputs and each Control Word specifies the Counter it applies to SCO SC1 bits no special in ers Control Word Counter 0 LSB of count Counter 0 MSB of count Counter 0 Control Word Counter 1 LSB of count Counter 1 MSB of count Counter 1 Control Word Counter 2 LSB of count Counter 2 MSB of count Counter 2 2200200 002222002 E eo Control Word Counter 0 Counter Word Counter 1 Control Word Counter 2 LSB of count Counter 2 LSB of count Counter 1 LSB of count Counter 0 MSB of count Counter 0 MSB of count Counter 1 MSB of count Counter 2 0000 2 gt oOo 00 0 _ D gt NOTE struction sequence is required Any programming sequence that follows the conventions above is ac ceptable A new initial count may be written to a Counter at any time without affecting the Counters pro grammed Mode in any way Counting will be affected as described in the Mode definitions The new count must foliow the programmed count format If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter Otherwise the Counter will be loaded with an incorrect count mb Control Word Co
4. BIT SELECT 0 1 2 3 4 516 7 fo afoj ajo 10 1 ololsitleloj l le jofojojo 111111182 BIT SET RESET FLAG O ACTIVE 231256 7 Figure 7 Bit Set Reset Format interrupt Control Functions When the 82C55A is programmed to operate in mode 1 or mode 2 control signals are provided that can be used as interrupt request inputs to the CPU The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset function of port C This function allows the Programmer to disallow or allow a specific 1 O device to interrupt the CPU with out affecting any other device in the interrupt struc ture INTE flip flop definition BIT SET INTE is SET Interrupt enable BIT RESET INTE is RESET Interrupt disable Note All Mask flip flops are automatically reset during mode selection and device Reset 3 129 intel 82C55A Operating Modes Mode 0 Basic Input Output This functional con figuration provides simple input and output opera tions for each of the three ports No handshaking is required data is simply written to or read from a specified port MODE 0 BASIC INPUT 3 130 Mode 0 Basic Functional Definitions e Two 8 bit ports and two 4 bit ports Any port can be input or output Outputs are latched Inputs are not latched 16 different Input Output configurations are po
5. Below the CLK pins are three pairs of pins labeled CLK2 These pins are used to select the clock source for TC2 OTI connects the output of TC1 to the clock input of TC2 Installing a jumper here cascades all three timer counters a feature necessary when using SIGNAL MATH or ATLANTIS application software see Appendixes D and E XTAL is the on board 8 MHz clock and EC2 is connected to the same external clock source as EC1 P2 45 The last two pins on this header PCK and ET let you use the pacer clock PCK or an external trigger ET to trigger A D conversions A jumper must be placed on PCK in order to use the pacer clock output from TC1 Or you can place the jumper across ET and connect any external trigger to P2 39 to trigger the A D converter NOTES You must disconnect the pacer clock by removing the PCK jumper and install the jumper of ET whenever you use the external trigger line You must have one jumper installed on one of the two CLK selections and one jumper installed on one of the three CLK2 selections P7 XTAL EC1 OT1 XTAL EC2 PCK ET CLK1 CLK2 Fig 1 6 8254 Timer Counter Clock Source Jumpers P7 1200 Roc VO CONNECTOR i TO A D 2 TRIGGER P7 TIMER COUNTER CLK 0 GATE TIMER COUNTER CLK GATE TIMER COUNTER CLK EXT GATE 2 GATE PIN 441 T OUT 2 POR 7772 Fig 1 7 8254 Timer Counter Circuit Block Diagram P8 Inter
6. Clearing and Setting Bits in a Port When you clear or set one or more bits in a port you must be careful that you do not change the status of the other bits You can preserve the status of all bits you do not wish to change by proper use of the AND and OR binary operators Using AND and OR single or multiple bits can be easily cleared in one operation To clear a single bit in a port AND the current value of the port with the value b where b 255 2h Example Clear bit 5 in a port Read in the current value of the port AND it with 223 223 255 2 and then write the resulting value to the port In BASIC this is programmed as V INP PortAddress V V AND 223 OUT PortAddress V 4 9 To set a single bit in a port OR the current value of the port with the value b where b 2 Example Set bit 3 in a port Read in the current value of the port OR it with 8 8 25 and then write the resulting value to the port In Pascal this is programmed as V Port PortAddress V V OR 8 Port PortAddress V Setting or clearing more than one bit at a time is accomplished just as easily To clear multiple bits in a port AND the current value of the port with the value b where b 255 the sum of the values of the bits to be cleared Note that the bits do not have to be consecutive Example Clear bits 2 4 and 6 in a port Read in the current value of the port AND it with 171 171 255 2 2 2
7. D De Ds D4 D3 D D Do L1 COUNT STATUS er 2 cur 1 eur o o RD 1 Ds O Latch count of selected counter s D4 O Latch status of selected counter s D3 1 Select counter 2 Da 1 Select counter 1 D 1 Select counter 0 Do Reserved for future expansion must be O Figure 10 Read Back Command Format The read back command may be used to latch multi ple counter output latches OL by setting the COUNT bit D5 0 and selecting the desired coun ter s This single command is functionally equiva lent to several counter latch commands one for each counter latched Each counter s latched count is held until it is read or the counter is repro grammed That counter is automatically unlatched when read but other counters remain latched until they are read If multiple count read back commands are issued to the same counter without reading the intel 82C54 count all but the first are ignored i e the count which will be read is the count at the time the first read back command was issued The read back command may also be used to latch status information of selected counter s by setting STATUS bit D4 0 Status must be latched to be read status of a counter is accessed by a read from that counter The counter status format is shown in Figure 11 Bits D5 through DO contain the counter s programmed Mode exactly as written in the last Mode Control Word OUTPUT bit D7 contains the c
8. Fig 4 6 Interrupts Flow Diagram interrupt service routine ISR Program interrupt source Eh 31 D A Conversion Flow Diagram Figure 4 7 This flow diagram shows you how to generate a voltage output through the D A converter ADA1200 only A conversion is initiated each time the high byte MSB is written to the D A converter Continue Stop Program Fig 4 7 D A Conversion Flow Diagram 4 32 CHAPTER 5 CALIBRATION This chapter tells you how to calibrate the 1200 using the 1200DIAG calibration program included in the example software package and six trimpots on the board These trimpots calibrate the A D converter gain and offset and the D A X2 multiplier output 5 1 5 2 This chapter tells you how to calibrate the A D converter gain and offset and the D A converter X2 multiplier ADA1200 only All A D and D A ranges are factory calibrated before shipping Any time you suspect inaccurate readings you can check the accuracy of your conversions using the procedure below and make adjustments as necessary Using the 1200DIAG diagnostics program is a convenient way to monitor conversions while you calibrate the board Calibration is done with the board installed in your system You can access the trimpots at the edge of the board Power up the system and let the board circuitry stabilize for 15 minutes before you start calibrating
9. 4 99878V Input Voltage 4 99634V 1000 0000 0000 0111 1111 1110 A D Converted Data 1000 0000 0001 0111 1111 1111 Table 5 2 A D Converter Bit Weights Bipolar Twos Complement mouwen ao om 5 5 Bipolar Range Adjustments 10 to 10 Volts To adjust the bipolar 20 volt range 10 to 10 volts change the jumper on P3 so that it is installed across the 20V pins Leave the P4 and P11 jumpers at Then set the input voltage to 5 0000 volts and adjust TR 1 until the Output matches the data in the table below Data Value for Calibrating Bipolar 20 Volt Range 10 to 10 volts TR1 Input Voltage 5 0000V A D Converted Data 0100 0000 0000 D A Calibration ADA1200 The D A converter requires no calibration for the X1 ranges 0 to 5 and 5 volts The following paragraph describes the calibration procedure for the X2 multiplier ranges To calibrate for X2 0 to 10 or 10 volts set the DAC output voltage range to 0 to 10 volts jumpers on X2 and 5 on P9 AOUTI or P10 AOUT2 Then program the corresponding D A converter DAC1 or DAC2 with the digital value 2048 The ideal DAC output for 2048 at X2 0 to 10 volt range is 5 0000 volts Adjust TRS for AOUTI and TR6 for AOUT2 until 5 0000 volts is read at the output Table 5 3 lists the ideal output voltages per bit weight for unipolar ranges and Table 5 4 lists the ideal output voltages for bipolar ranges me EC Te s we
10. AD1200 ADA1200 User s Manual FU Real Time Devices Inc Accessing the Analog World ISO9001 and AS9100 Certified AD1200 ADA1200 User s Manual JLD REAL TIME DEVICES INC 820 North University Drive Post Office Box 906 State College Pennsylvania 16804 USA Phone 814 234 8087 FAX 814 234 5218 Published by Real Time Devices Inc 820 N University Dr P O Box 906 State College PA 16804 USA Copyright O 1992 by Real Time Devices Inc All rights reserved Printed in U S A Rev A 9234 Table of Contents INTRODUCTION ud e tast il Analog to Digital Conversion or soonest diia i 3 Digital to Analog Conversion ADA1200 On sese sees i 3 8254 TUREN IA A ERNST i 3 A NA RM i 4 What Comes With Your BA oe i 4 A A edad nee hen twats i 4 Applications Software and Toolkit ssssssssssssscssscsessssssessssssncssucssnssucsnesssesssssssensssssessssusestecussuessusssesensesesssses i 4 Hardware ACCESS HIES od gio i 4 Using This Manual tia 14 When You Need Help ee a o i 4 CHAPTER 1 BOARD SETTINGS vesse enesenn 1 1 Factory Configured Switch and Jumper Settings cccsssssessssssesscsssssessessecucsecseseesecsesussucsesecsecsessssucassevagsnsceseeces 1 3 P3 Analog Input Voltage Range Factory Setting 10 Volts nnen 1 4 P4 Analog Input Voltage Polarity Factory Setting sss sese 1 4 P5 DMA Request Channel Factory Setting Disabled
11. If a trigger is re ceived after writing a new count but before the end of the current period the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current counting cycle In mode 2 a COUNT of 1 is illegal MODE 3 SQUARE WAVE MODE Mode 3 is typically used for Baud rate generation Mode 3 is similar to Mode 2 except for the duty cycle of OUT OUT will initially be high When half the ini tial count has expired OUT goes low for the remain der of the count Mode 3 is periodic the sequence above is repeated indefinitely An initial count of N results in a square wave with a period of N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low while OUT is low OUT is set high immediately no CLK pulse is required A trigger reloads the Counter with the initial count on the next CLK pulse Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This allows the Counter to be synchronized by software also Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current half cycle of the square wave the Counter will be loaded with the new count on the next CLK pulse and counting will cont
12. When a Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE input is always sampled on the rising edge of CLK In Modes 0 2 3 and 4 the GATE input is level sensitive and the logic level is sampled on the rising edge of CLK In Modes 1 2 3 and 5 the GATE input is rising edge sensitive In these Modes a rising edge of GATE trigger sets an edge sensi tive flip flop in the Counter This flip flop is then sam pled on the next rising edge of CLK the flip flop is reset immediately after it is sampled In this way a trigger will be detected no matter when it occurs a high logic level does not have to be maintained until the next rising edge of CLK Note that in Modes 2 and 3 the GATE input is both edge and level sensi tive In Modes 2 and 3 if a CLK source other than the system clock is used GATE should be pulsed immediately following WR of a new count value COUNTER New counts are loaded and Counters are decre mented on the falling edge of CLK The largest possible initial count is 0 this is equiva lent to 216 for binary counting and 104 for BCD counting The Counter does not stop when it reaches zero In Modes 0 1 4 and 5 the Counter wraps around to the highest count either FFFF hex for binary count ing or 9999 for BCD counting and continues count ing Modes 2 and 3 are periodic the Coun
13. port Port C is used for control and status for the 8 bit bi directional bus port Port A Bidirectional Bus I O Control Signal Definition INTR Interrupt Request A high on this output can be used to interrupt the CPU for input or output oper ations Output Operations OBF Output Buffer Full The OBF output will go low to indicate that the CPU has written data out to port A ACK Acknowledge A low on this input enables the tri state output buffer of Port A to send out the data Otherwise the output buffer will be in the high impedance state INTE 1 The INTE Flip Flop Associated with OBF Controlled by bit set reset of PCs input Operations STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that data has been loaded into the input latch INTE 2 The INTE Flip Flop Associated with IBF Controlled by bit set reset of PC4 3 136 intel 82C55A CONTROL WORD 9C 1 INPUT O OUTPUT PORT B 1 INPUT 0 OUTPUT 231256 18 Figure 13 MODE Control Word 231256 19 Figure 14 MODE 2 PERIPHERAL BUS 23125620 Figure 15 MODE 2 Bidirectional NOTE Any sequence where WR occurs before ACK and STB occurs before RD is permissible INTR IBF e MASK e STB RD OBF e MASK e ACK e WR FO a e er a en 3 137 MODE 2 AND MODE 0 INPUT CONTROL WORD D D D
14. see idealiter Betadine enen del ed nn eaoana 3 4 Timer Counters cc ISP 3 4 Digital I O Programmable Peripheral Interface sss 3 5 UT O ei ass e tia dac isum etc AM aA eds Ed e DE D P 3 5 CHAPTER 4 BOARD OPERATION AND PROGRAMMING nanna Detining the VO A O heeten BA 0 Read Status Start Convert Read Write sss sss sese BA 1 Read A D Data Update DAC Outputs Read Write sss sss BA 2 Reset Write Only seerd ste ederland eed Ear Ta easi BA 3 Reserved e VI ETAT TDI BA 4 PPI Port A Digital YO Read Write sss BA 5 PPI Port B Channel Board Functions Select Read Write nnn BA 6 PPI Port C Digital YO Read Write essen aan BA 7 8255 PPI Control Word Write On senesan BA 8 8254 Timer Counter 0 Read Write senses BA 9 8254 Timer Counter 1 Read Write sese BA 10 8254 Timer Counter 2 Read Write sese BA 11 8254 Control Word Write Only sese BA 12 D A Converter 1 LSB ADA1200 Write Only cccscccscssscsssssssssssssssecesecececsssssrsesesesececesecscesesesee BA 13 D A Converter 1 MSB ADA1200 Write Only sss sese BA 14 D A Converter 2 LSB ADA1200 Write Only sss sese BA 15 D A Converter 2 MSB ADA12200 Write Only sss sss Programming the 1 1 A O RA Clearing and Setting Bits in PO tias A a ee ls en Enabling and Disabling the External Trigger essea Enabling and Disabling Interrupts ssssscssssesscsssesessnecseesscnsesseseeanssecsscs
15. 19 and connect the low side of the device to an ANALOG GND P2 18 or P2 20 Connecting the Timer Counters and Digital I O For all of these connections the high side of an external signal source or destination device is connected to the appropriate signal pin on the P2 I O connector and the low side is connected to any DIGITAL GND Running the 1200DIAG Diagnostics Program Now that your board is ready to use you will want to try it out An easy to use menu driven diagnostics program 1200DIAG is included with your example software to help you verify your board s operation You can also use this program to make sure that your current base address setting does not contend with another device 2 5 CHAPTER 3 HARDWARE DESCRIPTION This chapter describes the features of the 1200 hardware The major circuits are the A D the D A the timer counters and the digital I O lines This chapter also describes the hardware select able interrupts The 1200 board has four major circuits the A D the D A ADA1200 only the timer counters and the digital T O lines Figure 3 1 shows the block diagram of the board This chapter describes the hardware which makes up the major circuits and hardware selectable interrupts 16 8 E ANALOG INPUTS 5V TO 45V RANGE SELECT RESISTOR TO TUN A D 5 VOLTS CONFIGURABLE 19 3v 19 19 CONVERTER 0TO 10 VOLTS GAIN 210 VOLTS TRIGGER IN TRIGGER OUT BUFFERS AND CONTROL PULL UP D
16. 4 bit Port C digital input and digital output data groups Port C Upper and Port C Lower between the board and an external device A read transfers data from the external device through P2 and into PPI Port C a write transfers the written data from Port C through P2 to an external device BA 7 8255 PPI Control Word Write Only When bit 7 of this word is set to 1 a write programs the PPI configuration The PPI must be programmed so that Port B is a Mode 0 output port as shown below X don t care m Mode Set Flag Port C Lower A 1 active O output Mode Select 1 input 00 mode 0 01 mode 1 Port B 1x mode 2 0 output 1 input Port A 0 output Mode Select 1 input 0 mode 0 1 mode 1 G B Port C Upper L ee EAE ARER be J 0 output 1 input i GroupA E AN The table below shows the control words for the 16 possible Mode 0 Port I O combinations The control words which set Port B as an input cannot be used on the 1200 8255 Port I O Flow Direction and Control Words Mode 0 El a Tele Upper Port B Lower oup owu 10990099 me o ow ou ej EN Output 81 MIOS T ma T ELM s 92 vou vooroor oven ooroo ma vooroor ma eren When bit 7 of the PPI control word is set to 0 a write can be used to individually program the Port C lines Input Output Se
17. 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and interrupt control signals MODE 2 is a strobed bi directional bus configuration The 82C55A is fabricated on Intel s advanced CHMOS Ill technology which provides low power consumption with performance equal to or greater than the equivalent NMOS product The 82C55A is available in 40 pin DIP and 44 pin plastic leaded chip carrier PLCC packages OMECTIONAL DATA BUS 231256 1 Figure 1 82C55A Block Diagram 231256 2 Figure 2 82C55A Pinout Diagrams are for pin reference only Package sizes are not to scale September 1987 3 124 Order Number 231256 004 intel B2C55A Table 1 Pin Description Pin Number Dip PLCC Name and Function O PORT A PINS 0 3 Lower nibble of an 8 bit data output latch buffer and an 8 bit data input latch 6 1 READ CONTROL This input is low during CPU read operations CHIP SELECT A low on this input enables the 82C55A to respond to RD and WR signals RD and WR are ignored otherwise ADDRESS These input signals in conjunction RD and WA control the selection of one of the three ports or the control word registers A1 0 8 9 Ay Ao RD WR CS input Operation Read _o jo lof 1 o Bena Bais Bua _o io o PotB DaaBu Lo 1 o o DaaBus Pona Jo 1 1 o o DataBus Pons jt ol 1 o fo data us Ponc pt ot 2 o o DataBus
18. A D converted data for bipolar conversions Chapter 4 BA 4 1 explains this in more detail NOTE P11 and P4 must be set the same for proper board operation Set P4 to the same polarity P11 Fig 1 12 A D Data Word Bit State Set Jumper P11 P12 A D Converter Status External Gate 2 Monitor Factory Setting EOC A D Converter Status This header connector shown in Figure 1 13 lets you select either the A D converter status or the external gate input of timer counter 2 to be available for monitoring at bit 3 of the status word BA 0 The A D converter status provides a direct read of the A D converter s availability for starting conversions This line goes low when a conversion starts then goes high when the conversion is completed Chapter 4 provides a more detailed explanation of this status signal EOC EG2 P12 Fig 1 13 A D Converter Status External Gate 2 Monitor Jumper P12 S1 Base Address Factory Setting 300 hex 768 decimal One of the most common causes of failure when you are first trying your board is address contention Some of your computer s I O space is already occupied by internal I O and other peripherals When the 1200 board attempts to use I O address locations already used by another device contention results and the board does not work To avoid this problem the 1200 has an easily accessible five position DIP switch S1 which lets you select any one of 32 starting addresses in th
19. Counter Latch Com mand Like a Control Word this command is written to the Control Word Register which is selected when Ay Ag 11 Also like a Control Word the SCO SC1 bits select one of the three Counters but two other bits D5 and D4 distinguish this command from a Control Word Ay Ap 11 CS 0 RD 1 WR 0 D7 De Ds D4 D3 D2 D Do ser sco o o TX DX X T3 SC1 SCO specify counter to be latched SC1 SCO Counter Read Back Command D5 D4 00 designates Counter Latch Command X don t care NOTE Don t care bits X should be O to insure compatibility with future Intel products Figure 9 Counter Latching Command Format The selected Counter s output latch OL latches the count at the time the Counter Latch Command is received This count is held in the latch until it is read by the CPU or until the Counter is reprogrammed The count is then unlatched automatically and the OL returns to following the counting element CE This allows reading the contents of the Counters on the fly without affecting counting in progress Multiple Counter Latch Commands may be used to latch more than one Counter Each latched Coun ter s OL holds its count until it is read Counter Latch Commands do not affect the programmed Mode of the Counter in any way If a Counter is latched and then some time later latched again before the count is read the second Counter Latch Command is ignored The count read
20. IRQs are numbered 0 through 7 Two of the most common mistakes when writing an ISR are forgetting to clear the interrupt status of the 1200 and forgetting to issue the EOI command to the 8259 interrupt controller before exiting the ISR Data Transfers Using DMA Direct Memory Access DMA transfers data between a peripheral device and PC memory without using the processor as an intermediate Bypassing the processor in this way allows very fast transfer rates All PCs contain the necessary hardware components for accomplishing DMA However software support for DMA is not included as part of the BIOS or DOS leaving you with the task of programming the DMA controller yourself With a little care such programming can be successfully and efficiently achieved The following discussion is based on using the DMA controller to get data from a peripheral device and write it to memory The opposite can also be done the DMA controller can read data from memory and pass it to a periph eral device There are a few minor differences mostly concerning programming the DMA controller but in general the process is the same The following steps are required when using DMA Choose a DMA channel Allocate a buffer Calculate the page and offset of the buffer Set the DMA page register Program the DMA controller Program device generating data 1200 Wait until DMA is complete Disable DMA Each step is detailed in the following paragraphs PIN
21. In this block enter the IRQ channel number which corresponds to your jumper setting on P8 Timer IT Timer Counter Interrupt This block is not used on the 1200 and should be left blank LabTech SW IT LABTECH NOTEBOOK Software Interrupt This sets the software interrupt address where LABTECH NOTEBOOK s labLINX driver is installed The factory setting is 60 This setting can be ignored when running SIGNAL MATH A D Parameters Six A D board parameters are listed resolution number of channels active DMA channel gain loss and input voltage polarity Resolution and number of channels are fixed by the program for your board End of Convert Timer Counter Interrupt Channel Interrupt Channel Base Address Software Interrupt Address A D DMA D A DMA Channel Channel Select Select External Gain External Gain amp Loss ee 983 amp Loss X Bipolar A D Unipolar M Bipolar E h i Select ze Load Menu D A Unipolar Bipolar Select Fig D 4 ADAINST EXE Screen D 5 If you are using DMA transfer you must enter the channel number which corresponds to the jumper settings in the DMA channel block Valid channels numbers are 1 and 3 The next two blocks gain and loss are provided so that you can make adjustments for external gain or loss other than the programmable gain settings available on the board If your input signal is externally attenuated then you can adjust for this by setting a value other than 1 for
22. L2 9 esc 0 3 1 9 EC es up px KE resque p 5 lol To To a AA WREE ER E HE EE ON 4 11 Enabling and Disabling the External Trigger Any time you use the external trigger or the pacer clock this bit at port BA 5 must be set high to enable A D conversions Enabling and Disabling Interrupts Any time you use interrupts this bit at port BA 5 must be set high to enable the IRQ circuitry Conversion Modes Triggering The 1200 has three triggering conversion modes Figure 4 1 shows the timing diagram for A D conversions This section describes the conversion modes Internal vs External Triggering With internal triggering also called software triggering conversions are initiated by writing a value to the START CONVERT port at BA 0 on the board With external triggering conversions are initiated by applying a high TTL signal to the external TRIGGER IN pin P2 39 Any TTL signal can be used as a trigger source In fact you can use the timer counter outputs as a trigger source k 5 psec Trigger End of Convert EOC S iss use gt Read Fig 4 1 A D Conversion Timing Diagram All Modes 4 12 Software trigger In this mode a single specified channel is sampled whenever a value is written to the START CONVERT port BA 0 The active channel is the one specified in the PPI Port B port This is the easiest of all triggering modes It can be used
23. and then write the resulting value to the port In C this is programmed as v inportb port address v v amp 171 outportb port_address v To set multiple bits in a port OR the current value of the port with the value b where b the sum of the individual bits to be set Note that the bits to be set do not have to be consecutive Example Set bits 3 5 and 7 in a port Read in the current value of the port OR it with 168 168 2 2 2 and then write the resulting value back to the port In assembly language this is programmed as mov dx PortAddress in al dx or al 168 out dx al Often assigning a range of bits is a mixture of setting and clearing operations You can set or clear each bit individually or use a faster method of first clearing all the bits in the range then setting only those bits that must be set using the method shown above for setting multiple bits in a port The following example shows how this two step operation is done Example Assign bits 3 4 and 5 in a port to 101 bits 3 and 5 set bit 4 cleared First read in the port and clear bits 3 4 and 5 by ANDing them with 199 Then set bits 3 and 5 by ORing them with 40 and finally write the resulting value back to the port In C this is programmed as v inportb port_address v v amp 199 v v 40 outportb port address v A final note Don t be intimidated by the binary operators AND and OR and try to use operators for
24. has transferred all the data it was programmed to transfer If you leave DMA enabled and it has not transferred all the data it was programmed to transfer it will resume transfers the next time data appears at the A D converter This can spell disaster if your program has ended and the buffer has be reallocated to another application I O Port OAH Channel Select Mask Bit 00 Channel 0 O unmask 01 Channel 1 1 mask 10 Channel 2 11 Channel 3 4 22 DMA Mode Register The DMA mode register is used to set parameters for the DMA channel you will be using The read write bits are self explanatory the read mode cannot be used with the 1200 Autoinitialization allows the DMA controller to automatically start over once it has transferred the requested number of bytes Decrement means the DMA controller should decrement its offset counter after each transfer the default is increment You can use either the demand or single transfer mode when transferring data The demand mode transfers data to the PC on demand for fastest transfer rate The single transfer mode forces the DMA controller to relinquish every other cycle so that the proces sor can take care of other tasks I O Port OBH Transfer Mode Channel Select Autoinitialization 00 demand di 00 Channel 0 01 single transfer 0 disable 01 Channel 1 10 block 1 enable 10 Channel 2 11 cascade 11 Channel 3 Offset Counter 0 increment
25. in a wide variety of applications such as sample every time a key is pressed on the keyboard sample with each iteration of a loop or watch the system clock and sample every five seconds See the SOFTTRIG sample program in C and Pascal and the SINGLE sample program in BASIC Pacer Clock In this mode conversions are continuously performed at the pacer clock rate To use this mode you must program the pacer clock to run at the desired rate see the pacer clock discussion later in this chapter The PCK jumper on P7 must be installed to use the pacer clock This is the ideal mode for filling an array with data Triggering is automatic so your program is spared the chore of monitoring the pacer clock to determine when to sample See the MULTI sample program in C and Pascal External Trigger In this mode a single conversion is initiated by the rising edge of an external trigger pulse This mode is implemented when an external device is used to determine when to sample See the EXTTRIG sample program in C and Pascal Starting an A D Conversion Software triggered single conversions are started by writing to the START CONVERT port atBA 0 The value you write is irrelevant For single conversions you must write to this port to initiate every conversion Externally triggered single conversions and multiple conversions triggered by the pacer clock through the external trigger are started by the first pulse present after the external trigger has b
26. is disconnected an on board pull up resistor automatically pulls the gate high enabling the timer counter The output from timer counter 1 is available at the T C OUT 1 pin P2 42 and timer counter 2 s output is available at T C 2 OUT P2 44 where they can be used for interrupt generation as an A D trigger or for counting functions The timer counters can be programmed to operate in one of six modes depending on your application The following paragraphs briefly describe each mode Mode 0 Event Counter Interrupt on Terminal Count This mode is typically used for event counting While the timer counter counts down the output is low and when the count is complete it goes high The output stays high until a new Mode 0 control word is written to the timer counter Mode 1 Hardware Retriggerable One Shot The output is initially high and goes low on the clock pulse following a trigger to begin the one shot pulse The output remains low until the count reaches 0 and then goes high and remains high until the clock pulse after the next trigger Mode 2 Rate Generator This mode functions like a divide by N counter and is typically used to generate a real time clock interrupt The output is initially high and when the count decrements to 1 the output goes low for one clock pulse The output then goes high again the timer counter reloads the initial count and the process is repeated This sequence continues indefinitely Mode 3 Squar
27. it from the bag hold the board at the edges and do not touch the components or connectors Before installing the board in your computer check the jumper and switch settings Chapter 1 reviews the factory settings and how to change them If you need to change any settings refer to the appropriate instructions in Chapter 1 Note that incompatible jumper settings can result in unpredictable board operation and erratic response To install the board 1 2 Turn OFF the power to your computer Remove the top cover of the computer housing refer to your owner s manual if you do not already know how to do this 3 Select any unused short or full size expansion slot and remove the slot bracket 4 Touch the metal housing of the computer to discharge any static buildup and then remove the board from its antistatic bag Holding the board by its edges orient it so that its card edge bus connector lines up with the expansion slot connector in the bottom of the selected expansion slot After carefully positioning the board in the expansion slot so that the card edge connector is resting on the computer s bus connector gently and evenly press down on the board until it is secured in the slot NOTE Do not force the board into the slot If the board does not slide into place remove it and try again Wiggling the board or exerting too much pressure can resultin damage to the board or to the computer After the board is insta
28. loss If you have an external gain factor then you can adjust for this condition Numbers must be entered as whole decimal values The factory default setting for gain and loss is 1 For a bipolar input range an X should be placed before Bipolar on the screen default setting For unipolar operation remove the X D A Parameters ADA1200 Only Six D A board parameters are listed resolution number of channels active DMA channel gain loss and input voltage polarity Resolution and number of channels are fixed For the ADA1200 DMA is not used and should be left blank Gain and loss are provided so that you can make adjustments for external gain or loss as described above for the A D parameters For a bipolar output range an X should be placed before Bipolar on the screen default setting For unipolar operation remove the X APPENDIX E CONFIGURING THE 1200 FOR ATLANTIS If you have purchased ATLANTIS data acquisition and real time monitoring application software for your 1200 please note that the ATLANTIS drivers for your board must be loaded from your example software disk into the same directory as the ATLANTIS EXE program When running ATLANTIS you must change some of the 1200 s on board jumpers from their factory set positions Before using ATLANTIS on the 1200 board check the following switch and jumpers 1 Base address P7 8254 timer counter I O configuration P8 Interrup
29. me 4 24 D A Converter Bipolar Calibration Table Ideal Output Voltage in millivolts 4095 Max Output 4997 6 9995 1 512 ow ces cms om omms H mw sea Os NN NN o ces E 1 e omes ms Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters for timing and counting functions such as frequency measurement event counting and interrupts Two of the timer counters are cascaded and can be used for the pacer clock The remaining timer counter is available for your use Figure 4 3 shows the timer counter circuitry l 1 I 1 I I l 1 4 1200 1 0 CONNECTOR TO A D P2 TRIGGER P7 TIMER COUNTER CLK GATE TIMER COUNTER CLK GATE EXT GATE 2 PIN 441T C OUT 2 OUT Fig 4 3 8254 Programmable Interval Timer Circuit Block Diagram 4 25 Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT They can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in the 1 0 map section at the beginning of this chapter One of two clock sources the on board 8 MHz crystal or the external clock P2 45 can be selected as the clock input to TCO or TC2 The diagram shows how these clock sources are connected to the timer counters Two gate sources are available at the 1 0 connector P2 41 and P2 46 When a gate
30. port locations on the board These I O ports were defined in the previous section Most high level languages such as BASIC Pascal C and C and of course assembly language make it very easy to read write these ports The table below shows you how to read from and write to 1 O ports using some popular programming languages wums me we Port Address Data Assembly mov dx Address mov dx Address in al dx mov al Data out dx al In addition to being able to read write the I O ports on the 1200 you must be able to perform a variety of operations that you might not normally use in your programming The table below shows you some of the operators discussed in this section with an example of how each is used with Pascal C and BASIC Note that the modulus operator is used to retrieve the least significant byte LSB of a two byte word and the integer division operator is used to retrieve the most significant byte MSB Language Modulus integer Division C 8 a b c a b c a b amp c MOD DIV AND OR a bMODc a bDIVc a b AND c a bORc BASIC MOD backsiash AND OR a bMODc a b c a bANDc a bORc Many compilers have functions that can read write either 8 or 16 bits from to an 1 O port For example Turbo Pascal uses Port for 8 bit port operations and PortW for 16 bits Turbo C uses inportb for an 8 bit read of a port and inport for a 16 bit read Be sure to use only 8 bit operations with the 1200
31. shot pulse continues until the new count expires CWz12 158 3 UU CWs12 LSB 3 UHF CWz12 LSB 2 EF FF O 0 jer tee a 3 231244 9 Figure 16 Mode 1 MODE 2 RATE GENERATOR This Mode functions like a divide by N counter It is typicially used to generate a Real Time Clock inter rupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for one CLK pulse OUT then goes high again the Counter re loads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N the sequence repeats every N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low during an output pulse OUT is set high immediately A trigger reloads the Counter with the initial count on the next CLK pulse OUT goes low N CLK pulses after the trigger Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse OUT goes low N CLK Pulses after the initial count is writ ten This allows the Counter to be synchronized by software also CWxi4 LS8x3 Iis tule ste CW 14 5824 LS8 25 231244 10 NOTE A GATE transition should not occur one clock prior to terminai count Figure 17 Mode 2 3 92 T intel 82C54 Writing a new count while counting does not affect the current counting sequence
32. the last conversion the output of the corresponding DAC will not change BA 2 Reset Write Only Resets internal registers so that the board is ready to start conversions The data written is irrelevant the act of writing to this address clears the board A reset command sets the internal byte pointer to read the LSB on the next read resets the DRQ and IRQ registers and resets clears the DMA done bit BA 0 bit 1 BA 3 Reserved BA 4 PPI Port A Digital VO Read Write Transfers the 8 bit Port A digital input and digital output data between the board and an external device A read transfers data from the external device through P2 and into PPI Port A a write transfers the written data from Port A through P2 to an external device BA 5 PPI Port B Channel Board Functions Select Read Write Programs the analog input channel and enables the IRQ and external trigger Reading this register shows you the current settings IRQ Enable 0 IRQ disabled 1 IRQ enabled External Trigger Enable 0 Disabled 1 Enabled Analog Input Channel Select 0000 channel 1 0001 channel 2 0010 channel 3 0011 channel 4 0100 channel 5 0101 channel 6 0110 channel 7 0111 channel 8 1000 channel 9 1001 channel 10 1010 channel 11 1011 channel 12 1100 channel 13 1101 channel 14 1110 channel 15 1111 channel 16 BA 6 PPI Port C Digital VO Read Write Transfers the two
33. transfer Remember that each digitized sample from the 1200 consists of 2 bytes so the count that you write to the DMA controller should be equal to the number of samples x 2 1 The single mask register and mode register are described below The clear byte pointer sets an internal flip flop on the DMA controller that Keeps track of whether the LSB or MSB will be sent next to registers that accept both LSB and MSB Ordinarily you never need to write to this port but itis a good habit to do so before programming the DMA controller Writing any value to this port clears the flip flop Address hex decimal Register Description Channel 1 Page Offset write 2 bytes LSB first Channel 1 Count write 2 bytes LSB first Channel 3 Page Offset write 2 bytes LSB first Channel 3 Count write 2 bytes LSB first Single Mask Register Mode Register write only Clear Byte Pointer Flip Flop write only DMA Single Mask Register The DMA single mask register is used to enable or disable DMA on a specified DMA channel You should mask disable DMA on the DMA channel you will be using while programming the DMA controller After the DMA controller has been programmed and the 1200 has been programmed to sample data you can enable DMA by clearing the mask bit for the DMA channel you are using You should manually disable DMA by setting the mask bit before exiting your program or if for some reason sampling is halted before the DMA controller
34. v m H wm m oem 99 ow ems an ow ome ae ow em m BEE HERE EI ems A E 2 4414 4 8828 1 2207 2 4414 0 0000 0 0000 Table 5 4 D A Converter Bipolar Calibration Table ideal Output Voltage in millivolts oma 9 D Baer 12 pom 4995 1 9990 2 4997 6 9995 1 5000 0 10000 0 5 7 5 8 APPENDIX A 1200 SPECIFICATIONS A 2 AD1200 ADA1200 Characteristics Typical 25 C Interface Switch selectable base address I O mapped Jumper selectable interrupts DMA channel Analog Input 16 single ended inputs Input impedance each channel nne eese onensenensenee gt 10 megohms CNO resistor configurable A T 5 10 or 0 to 10 volts Guaranteed linearity across input ranges 5 9 5 and Oto 9 5 volts Overvoltage protection anvenensensens ens ensenenneeneenseenrsvensensenvene enne 35 Vdc Settling time gain 1 oo anenarssenvenserenseensnr ennen seneenvensensenevanensen 5 usec max AID CONVOMMCN p O AD678 TYPO t Successive approximation AS A rte ttt ribera deed end 12 bits 2 44 mV O 10V 4 88 mV 20V ICT Re t1 bit typ Conversion speed eee irre bes rer nri fere denti cop encanto leerer 5 psec typ ThroughpUt TOE 125 kHz Pacer Clock Range using on board 8 MHZ clock nere
35. you can enjoy maximum use of its features even in the most complex applications We assume that you already have an understanding of data acquisition principles and that you can customize the example software or write your own applications programs When You Need Help This manual and the example programs in the software package included with your board provide enough information to properly use all of the board s features If you have any problems installing or using this board contact our Technical Support Department 814 234 8087 during regular business hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 When sending a FAX request please include your company s name and address your name your telephone number and a brief description of the problem i 4 CHAPTER 1 BOARD SETTINGS The AD1200 and ADA 1200 boards have jumper and switch settings you can change if necessary for your application The 1200 is factory configured with the most often used settings The factory settings are listed and shown on a diagram in the beginning of this chapter Should you need to change these settings use these easy to follow instructions before you install the board in your computer Note that by installing resistor packs at three locations around the 8255 PPI and soldering jumpers in the desired locations in the associated pads you can configure the 16 available digital I O line
36. 0 RR 5 6 APPENDIX A 1200 SPECIFICATIONS E A den O O APPENDIX B P2 CONNECTOR PIN ASSIGNMENTS vesse essen AERAR B 1 APPENDIX C COMPONENT DATA SHEETS esaeen ennn e C 1 APPENDIX D CONFIGURING THE 1200 FOR SIGNAL MATH D 1 APPENDIX E CONFIGURING THE 1200 FOR ATLANTIS T M RN A M iii LIST OF ILLUSTRATIONS 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 1 13 1 14 1 15 1 16 1 17 1 18 2 1 2 2 2 3 3 1 3 2 4 1 4 2 4 3 4 4 4 5 4 6 4 7 5 1 Board Layout Showing Factory Configured Settings ccccsssssssssssssssssesssecesssssesessssssscececssssessasecesers 1 3 Analog Input Voltage Range Jumper P3 sese 1 4 Analog Input Voltage Polarity Jumper P4 s sssssssssssssscessssessesssssssnscessscncsessessesecsessesnssssesssssossssessvesecaes 1 4 DMA Request Channel Jumper PS esse esen 1 4 DMA Acknowledge Channel Jumper Pp sss sese eenn 1 5 8254 Timer Counter Clock Source Jumpers PT 1 5 8254 Timer Counter Circuit Block Diagram sss sss eenn 1 6 Interrupt Channel Jumper P8 ve sss sees essen 1 6 Pulling Down the Interrupt Request Line s sssssssscsssssscecersccescsesessorscscseseessssssssscscsesessssssecsosceseceseres 1 7 DAC 1 Output Voltage Range Jumper P9 sss sss sese 1 8 DAC 2 Output Voltage Range Jumper P10 aesae 1 8 A D Data Word Bit State Set Jumper PIL 1 9 A D Converter Status External Gate 2 Moni
37. 1 BCD Counter Select 00 Counter 0 Counter Mode Select 01 Counter 1 000 Mode 0 event count 10 Counter2 Read Load 001 Mode 1 programmable 1 shot 11 read back setting 00 latching operation 010 Mode 2 rate generator 01 read load LSB only 011 Mode 3 square wave rate generator 10 read load MSB only 100 Mode 4 software triggered strobe 11 read load LSB then MSB 101 Mode 5 hardware triggered strobe BA 12 D A Converter 1 LSB ADA1200 Write Only Programs the DAC1 LSB eight bits BA 13 D A Converter 1 MSB ADA1200 Write Only Programs the DACI MSB four bits into DO through D3 D4 through D7 are irrelevant BA 14 D A Converter 2 LSB ADA1200 Write Only Programs the DAC2 LSB eight bits BA 15 D A Converter 2 MSB ADA1200 Write Only Programs the DAC2 MSB four bits into DO through D3 D4 through D7 are irrelevant Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X Bit11 Bit10 Bit9 Bit 8 Programming the 1200 This section gives you some general information about programming and the 1200 board and then walks you through the major 1200 programming functions These descriptions will help you as you use the example programs included with the board and the programming flow diagrams at the end of this chapter All of the program descrip tions in this section use decimal values unless otherwise specified The 1200 is programmed by writing to and reading from the correct I O
38. 1 and 5 triggers are sampled on each rising clock edge A second trigger within 120 ns 70 ns for the 82C54 2 of the rising clock edge may not be detected 3 Low going glitches that violate tpwx ipw may cause errors requiring counter reprogramming 4 Except for Extended Temp See Extended Temp A C Characteristics below 5 Sampled not 100 tested Ta 25 C 6 If CLK present at Two min then Count equals N 2 CLK pulses Two max equals Count N 1 CLK pulse Two min to Twc max count will be either N 1 or N 2 CLK pulses 7 in Modes 1 and 5 if GATE is present when writing a new Count value at Twa min Counter will not be triggered at Twa max Counter will be triggered 8 If CLK present when writing a Counter Latch or ReadBack Command at Tc min CLK will be reflected in count value latched at Tc max CLK will not be reflected in the count value latched Writing a Counter Latch or ReadBack Command between Tc min and Tw max will result in a latched count vallue which is one least significant bit EXTENDED TEMPERATURE Ta 40 C to 85 C for Extended Temperature _ Parameter 8254 82542 A ee e TC 25 25 25 we Gate Dota forSamping 25 25 25 intel 82054 WAVEFORMS WRITE DATA BUS 231244 14 DATA BUS e e 231244 15 RECOVERY 231244 16 3 98 intel 82054 CLOCK AND GATE 231244 17 Last byte of count being written A C TESTING INPUT
39. 2 shows the timer counter circuitry Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT They can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in Chapter 4 The command word also lets you set up the mode of operation The six programmable modes are Mode 0 Event Counter Interrupt on Terminal Count Mode 1 Hardware Retriggerable One Shot Mode 2 Rate Generator Mode 3 Square Wave Mode 1200 Ts 1 0 CONNECTOR I TO A D P2 TRIGGER P7 TIMER COUNTER EXT GATE 2 PIN 441 T C OUT 2 Pa n e e e e Fig 3 2 8254 Timer Counter Circuit Block Diagram 3 4 Mode 4 Software Triggered Strobe Mode 5 Hardware Triggered Strobe Retriggerable These modes are detailed in the 8254 Data Sheet reprinted from Intel in Appendix C Digital O Programmable Peripheral Interface The programmable peripheral interface PPI is used for digital I O functions This high performance TTL CMOS compatible chip has 24 digital I O lines divided into two groups of 12 lines each Group A Port A 8 lines and Port C Upper 4 lines Group B Port B 8 lines and Port C Lower 4 lines Port A and Port C are available at the external I O connector P2 Port B is dedicated to on board functions and is not available for your use You can use the 16 lines of Ports A and C in one of these three PPI operating modes Mode 0 Basic input out
40. 220s000nenenensonunenesssenonnenensnnensnennensnensnenenensenannnesnnnessennnnsennenennnnenene 4 27 C and Pascal Programs eazis oer ose eureri ep re Ren e da ie cscosutecutnecsiccusceass assestoesisied 4 27 BASIC Programs cccssasssscsecscateasasscisavensossvesssnsitsosesseedes bob iois or aana i aseaine NE S tecateccescerisssass ied 4 27 Flow Diagtams o dei 4 29 Single Convert Flow Diagram Figure 4 4 sss enesenn ennenen 4 29 DMA Flow Diagram Figure 4 5 aio 4 30 Interrupts Flow Diagram Figure 4 6 ssssssssssssssscesssecscecersseseessssssssecceceeessesenessseseesscesesussasacsescacssnsness 4 31 D A Conversion Flow Diagram Figure 4 7 ssscscsssssssesssscscecesssssesssesssssesscescecesessussscecesesscececesensesesneneee 4 32 CHAPTER 5 CALIBRA TION nl Required Equipment za u iaa sds erhaltene 5 3 A D Calibration ssvssisscucsisssssccsssasessasesssancensaseacescovesteasesesseteessscueadesosaesesacdeactetascoatosdocdeota bocedcesoiutentbessaeddc saead 5 4 Unipolar Calibration 4 i cerit terere trier ede tales sacescesnscdestssed Lr zts area reper en eedt ae Dancer Wma doves 5 4 STs bT Te schienen sduscevacsssvadeovsssssheeseecsedhdeasacsesabutdvadeeseskoosceersleaslsasolessecesieeusecccieens 5 5 Bipolar Range Adjustments 5 to 5 VOS sese 5 5 Bipolar Range Adjustments 10 to 10 VOIts csecsssscssesessscssesssssssssesessescecessesssssessssssesssssssucenscsssvscscneees 5 6 D A Calibration ADA120
41. 6 8255 PPI Control Word Program PPI configuration BA 7 8254 Timer Counter 0 Used for pacer clock Read count value Load count register BA 8 8254 Timer Counter 1 Used for pacer clock Read count value Load count register BA 9 8254 Timer Counter 2 Available for external use Read count value Load count register BA 10 8254 Timer Counter Control Word Program counter mode BA 11 D A Converter 1 LSB Program DAC1 LSB BA 12 Not used Program DAC1 MSB BA 13 Program DAC2 LSB BA 14 D A Converter 1 MSB Program DAC2 MSB BA 15 Reserved gt Oo o o e o 2 SUsQis OPIO gt IO 202012 meinen 22102109 oslosio o aloalo 39 358 5 Z lZ wal Sl o to m Uu gt lee w Qo co gt a a o 0 7 4 3 BA 0 Read Status Start Convert Read Write A read provides the five status bits defined below The end of convert bit goes high when a conversion is complete and does not go low until the data is read useful information when using external triggering to start conversions The DMA done bit goes high when you are in the DMA mode and the DMA transfer is complete The IRQ status bit goes high when an interrupt has occurred and stays high until a reset command is sent BA 2 D3 shows the status of either the A D converter status signal or the external gate input for timer counter 2 depending on the setting of jumper P12 Unlike the EOC status at bit 0 the A D converter status goes low whe
42. 9 minutes to 5 usec Ice MSR e CMOS 82C55 Number of linas TTT 16 n pernicie aa od aaa dulden TTU CMOS Configurable with optional LO pull up pull down resistors High level output voltage ennensesnenvenvensenvensenvenvenenseassestenrsnn 4 2V min Low level output voltage nan snssnsvensen sneven ennenennesnenvenenrens 0 45V max High level input voltage en nannnurnssursvoneneeneneneen 2 2V min 5 5V max Low level input voltage sees sese esse ee eee senenn eee 0 3V min 0 8V max AAA ses vers davateecesnsceacvectsoceevancdebstieudssdascaseseteuse 10 pA Input capacitance euch A 10 pF Output capacitance ie act A vs denen 20 pF D A Converter ADA1200 Only eenen sans tnus AD7237 Analog oulpUuls 2 eere retreat crece rone veelal vetus ai ostebiass 2 channels Se dede 12 bits Output ranges E 0 to 5 5 or O to 10 volts Guaranteed linearity across output ranges 0 to 5 5 and 0 to 9 2 volts Relative accuracy A t1 bit max Full scale accuracy esee essen eeenetn cn ron rn conca roscar tasa conan sensa aaa 5 bits max Tni eT 1 bit max SING THM Ossi riadas 10 usec max linen pee CMOS 82C54 Three 16 bit down counters 2 cascaded 1 independent 6 programmable operating modes Counter input source naaar eenn vereen External clock 8 MHz max
43. CR 2 C New count is loaded into CE CR CE Null count 1 Null count 0 1 Only the counter specified by the contro word will have its null count set to 1 Null count bits of other Counters are unaffected 2 If the counter is programmed for two byte counts least significant byte then most significant byte null count goes to 1 when the second byte is written Figure 12 Null Count Operation If multiple status latch operations of the counter s are performed without reading the status all but the first are ignored i e the status that will be read is the status of the counter at the time the first status read back command was issued Both count and status of the selected counter s may be latched simultaneously by setting both COUNT and STATUS bits D5 D4 0 This is func tionally the same as issuing two separate read back commands at once and the above discussions ap ply here also Specifically if multiple count and or status read back commands are issued to the same counter s without any intervening reads all but the first are ignored This is illustrated in Figure 13 If both count and status of a counter are latched the first read operation of that counter will return latched Status regardless of which was latched first The next one or two reads depending on whether the counter is programmed for one or two type counts return latched count Subsequent reads return un latched count Results Cou
44. Cono Disable Function x x x x 1 DataBus 3 State x x 1 1 o pataBus 3 State PORT C PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B PCo 3 14 17 16 19 vo PORTC PINS 0 3 Lower nibble of Port C PBo 7 20 22 1 O PORT B PINS 0 7 An 8 bit data output latch buffer and an 8 24 28 bit data input buffer SYSTEM POWER 5V Power Supply Veo 2 e D7 0 27 34 I O DATA BUS Bi directional tri state data bus lines connected to system data bus RESET RESET A high on this input clears the contro register and all ports are set to the input mode WRITE CONTROL This input is low during CPU write operations PA7_4 37 40 VO PORT A PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input latch No Connect intel 82C55A 82C55A FUNCTIONAL DESCRIPTION General The 82C55A is a programmable peripheral interface device designed for use in Intel microcomputer sys tems Its function is that of a general purpose 170 component to interface peripheral equipment to the microcomputer system bus The functional configu ration of
45. E A Controlled by bit set reset of PCs INTE B Controlled by bit set reset of PCo 3 135 82C55A MODE 1 PORT A CONTROL WORD D Ds Dy D D D D D tfo je eID Pas te INPUT 0 OUTPUT MODE 1 PORT B CONTROL WORD D De Ds D D 0 D Dy LPS gt e DJ Figure 11 MODE 1 Strobed Output 231256 16 intel Combinations of MODE 1 82C55A Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed 1 0 applications CONTROL WORD D De Ds D D D D D OBR vols Je DS er 1 INPUT PORT A STROBED INPUT PORT B STROBED OUTPUT CONTROL WORD D D Ds D D Dz D er q 0 OUTPUT RD PORT A STROBED OUTPUT PORT B STROBED INPUT 231256 17 Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus 1 O This functional configuration provides a means for com municating with a peripheral device or structure on a single 8 bit bus for both transmitting and receiving data bidirectional bus 1 0 Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1 Interrupt generation and enable disable functions are also available MODE 2 Basic Functional Definitions Used in Group A only e One 8 bit bi directional bus port Port A and a 5 bit control port Port C e Both inputs and outputs are latched The 5 bit contro
46. E CYCLE Test a rn E Gaas R CE LE Address Hold Time After WR T 20 ms PortsA amp B 20 ns Ponc um WErwewa 3 w tow Dat Setup Tmo Bore WET wo m DW og Data Hold Time After WAP 30 ms PomsasB 30 ns Porc 3 142 intel 82C55A me cune OTHER TIMINGS Parameter WA ito0utpue aso Peripheral Data Before RD o Peripheral Data After RD o tak ACK Pulse width 20 Per Data Before STB High 20 _ Por Data Aftor STBHigh so R ACK OtoQutput ACK 1toQuiputioat 20 WA 1to0BF 0 woe AOK 0t00BF 1 SB otmE 14 f AD ttoBr 0 terr ts r STB 1to INTR 1 tAIT ACK 1 to INTR 1 0 tw r WR Oto INTR Reset Pulse Width NOTE 1 INTR T may occur as early as WR 2 Pulse width of initial Reset pulse after power on must be at least 50 Sec Subsequent Reset pulses may be 500 ns minimum tsT tao 150 _ 160 5 o 3 143 inter 82C55A WAVEFORMS MODE 0 BASIC INPUT C A1 A0 me NS tap o gt 231256 22 MODE 0 BASIC OUTPUT 231256 23 Fa o ete m a IA EE T 3 144 intel 82C55A WAVEFORMS Continued MODE 1 STROBED INPUT INPUT FROM _ PERIPHERAL 231256 24 231256 25 3 145 intel 82C55A WAVEFORMS Continued MODE 2 BIDIREC
47. L SYSTEM 0000 GN 225 fi EL s o ele oo EE 74HCT574 D 74HCT74 D 74HCT74 O 000000000 70000000 70000000 000000000000 83 jooeonno B eater 000000000000 5 je 000000000000 0088000000 en Dd e amp D do Real Time Devices Inc State College PA 16804 USA Fig D 1 1200 Board Layout S1 Base Address SIGNAL MATH assumes that the base address of your 1200 is the factory setting of 300 hex 768 decimal If you change this setting you must run the ADAINST program and reset the base address NOTE When using the ADAINST program you can enter the base address in decimal or hexadecimal notation When entering a hex value you must precede the number by a dollar sign for example 300 D 3 P7 8254 Timer Counter I O Configuration The 8254 must be configured with the three jumpers placed between the pins as shown in Figure D 2 This configuration is the same as the factory setting After setting the jumpers verify that each is in the proper location Any remaining jumpers must be removed from the P7 header connector P7 XTAL loo lec OT1 XTAL EC2 PCK ET CLK1 CLK2 Fig D 2 8254 Timer Counter Clock Source Jumpers P7 P3 Interrupts To select an IRQ channel and an interrupt source you must install three jumpers on this header connector To configure this header for SIGNAL MATH place one jumper across the pins of your desired IRQ channel place the second jumper acr
48. NEN Choosing a DMA Channel There are a number of DMA channels available on the PC for use by peripheral devices The 1200 can use either DMA channel 1 or DMA channel 3 The factory setting is DMA disabled You can arbitrarily choose one or the other by setting the jumpers on P5 and P6 as described in Chapter 1 in most cases either choice is fine Occa sionally though you will have another peripheral device for example a tape backup or Bernoulli drive that also uses the DMA channel you have selected This will certainly cause erratic results and can be hard to detect The best approach to pinpoint this problem is to read the documentation for the other peripheral devices in your system and try to determine which DMA channel each uses Allocating a DMA Buffer When using DMA you must have a location in memory where the DMA controller will place data from the 1200 board This buffer can be either static or dynamically allocated Just be sure that its location will not change while DMA is in progress The following code examples show how to allocate buffers for use with DMA In Pascal Var Buffer Array 1 10000 of Byte static allocation Or Var Buffer Byte dynamic allocation Buffer GetMem 10000 4 19 In C char Buffer 10000 static allocation Or char Buffer dynamic allocation Buffer calloc 10000 0 In BASIC DIM BUFFERS 5000 Calculating the Page and Offset of
49. ONSE QUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITA TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLU SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VAR Y FROM STATE TO STATE room mem
50. OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT INPUT OUTPUT gt war L 231244 18 A C Testing Inputs are driven at 2 4V for a logic 1 and 0 45V for a logic 0 Timing measurements are made at 2 0V for a logic 1 and 0 8V for a logic 0 231244 19 C 150 pF C includes jig capacitance 3 99 Intel 82C55A Programmable Peripheral Interface Data Sheet Reprint 2 R intel 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE m Compatible with all Intel and Most m Control Word Read Back Capability eht bannen m Direct Bit Set Reset Capability m High Speed Zero Wait State AD ive Capabilit Operation with 8 MHz 8086 88 and m Po cum ve Capability on all 1 0 nu Available in 40 Pin DIP and 44 Pin PLCC m 24 Programmable 1 O Pins RS x m m Available in EXPRESS m Low Power CHMOS Standard Temperature Range m Completely TTL Compatible Extended Temperature Range The Intel 82C55A is a high performance CHMOS version of the industry standard 8255A general purpose programmable 1 O device which is designed for use with all Intel and most other microprocessors It provides 24 1 0 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82C55A is pin compatible with the NMOS 8255A and 8255A 5 In MODE O each group of 12 1 O pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have
51. OWN RESISTORS VO CONNECTOR D A CONVERTER poe Fig 3 1 AD1200 ADA1200 Block Diagram A D Conversion Circuitry The1200 performs analog to digital conversions on up to 16 single ended software selectable analog input channels The following paragraphs describe the A D circuitry Analog Inputs The input voltage range is jumper selectable for 5 to 5 volts 10 to 10 volts or O to 10 volts Resistor configurable gain lets you amplify lower level signals to more closely match the board s input ranges This gain circiutry is described in Chapter 1 Overvoltage protection to 35 volts is provided at the inputs A D Converter The AD678 12 bit successive approximation A D converter accurately digitizes dynamic input voltages in 3 microseconds for a maximum throughput rate of 200 kHz for the converter alone The AD678 contains a sample and hold amplifier a 12 bit A D converter a 5 volt reference a clock and a digital interface to provide a complete A D conversion function on a single chip Its low power CMOS logic combined with a high precision low noise design give you accurate results Conversions are initiated through software internally triggered or by using an external trigger brought onto the board through the I O connector An on board pacer clock can be used to control the conversion rate Conversion modes are described in Chapter 4 Board Operation and Programming 3 3 Data Transfer The convert
52. ROL WORD 10 0 0 0 D D 0 Ds Ds CONTROL WORD 11 0 Ds Ds D D D 0 Do Pere 231256 11 intel 82C55A MODE 0 Contigurations Continued CONTROL WORD 12 0 Oy Ds O D Dz D Do CONTROL WORD 613 D O D D D D D Op Operating Modes MODE 1 Strobed input Output This functional configuration provides a means for transferring I O data to or from a specified port in conjunction with strobes or handshaking signals in mode 1 Port A and Port B use the lines on Port C to generate or accept these handshaking signals CONTROL WORD 614 Dj Dy OD De D D D Do CONTROL WORD 15 D De D D s D O Do 231256 12 Mode 1 Basic functional Definitions Two Groups Group A and Group B Each group contains one 8 bit data port and one 4 bit control data port The 8 bit data port can be either input or output Both inputs and outputs are latched e The 4 bit port is used for control and status of the 8 bit data port AAA A ee 3 133 intel 82C55A Input Control Signal Definition STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that the data has been loaded into the input latch in essence an ac knowledgement IBF is set by STB input being low and is reset by the rising edge of the RD input INTR Interrupt Request A high on this output can be us
53. Read Write 1 decrement 01 write 10 read not used with 1200 Programming the DMA Controller To program the DMA controller follow these steps 1 Clear the byte pointer flip flop 2 Disable DMA on the channel you are using 3 Write the DMA mode register to choose the DMA parameters 4 Write the LSB of the page offset of your buffer 5 Write the MSB of the page offset of your buffer 6 Write the LSB of the number of bytes to transfer 7 Write the MSB of the number of bytes to transfer 8 Enable DMA on the channel you are using Programming the 1200 for DMA Once you have set up the DMA controller you must program the 1200 for DMA The following steps list this procedure 1 Set up the 8255 PPI for Port B output 2 Set up the timer counters for the desired transfer rate 3 Enable DMA and external trigger 4 Monitor DMA done bit NOTE If the DMA is set up in the single transfer mode each DMA transfer takes two read cycles to com plete Therefore in single transfer you can run the 1200 at speeds up to about 100 kHz so the DMA transfer rate can keep up with the board s conversion rate The demand mode supports even higher transfer rates However rates faster than 125 kHz even in the demand mode may give unreliable results Monitoring for DMA Done There are two ways to monitor for DMA done The easiest is to poll the DMA done bit in the 1200 status register BA 0 While DMA is in progress the bi
54. TAL EC1 OT1 XTAL EC2 PCK XTRIG CLK1 CLK2 Fig E 2 8254 Timer Counter Clock Source Jumpers P7 P8 Interrupts To select an IRQ channel and an interrupt source you must install three jumpers on this header connector To configure this header for ATLANTIS place one jumper across the pins of your desired IRQ channel place the second jumper across the pins labeled OT2 and place third jumper across the pins labeled G Make certain that there are no other jumpers on this connector Also make sure that the IRQ channel you have selected is not used by any other device in your system Figure E 3 shows you how to configure P8 for IRQ channel 3 P8 OT2 ET EOC DMA IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 G Fig E 3 Interrupts and Interrupt Channel Jumpers P8 E 4 F 1 APPENDIX F WARRANTY LIMITED WARRANTY Real Time Devices Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DE VICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to REAL TIME DEVICES All replaced parts and products become the property of REAL TIME DE
55. TIONAL DATA FROM 8080 TO 8265 Ez EA PERIPHERAL BUS DATA FROM DATA FROM PERIPHERAL TO 8255 8255 TO PERIPHERAL DATA FROM 8255 TO 6080 231256 26 Note Any sequence where WR occurs before ACK AND STB occurs before RD i D is permissible INTR IBF e MASK e STB e RD OBF e MASK e ACK e WR WRITE TIMING READ TIMING 12775 MIGM IMPEDANCE 77 231256 27 A C TESTING INPUT OUTPUT WAVEFORM 231256 29 A C Testing Inputs Are Driven At 2 4V For A Logic 1 And 0 45V f For A Logic 0 Timing Measurements Are Made At 2 0V For A meq Is Set At Various Voltages During Testing To Guarantee Logic 1 And 0 8 For A Logic 0 The Specification C Includes Jig Capacitance 231256 30 3 146 APPENDIX D CONFIGURING THE 1200 FOR SIGNAL MATH D 1 D 2 Jumper and Switch Settings When running SIGNAL MATH you may have to change some of the 1200 s on board jumpers from their factory set positions Before using SIGNAL MATH on the 1200 board check the following switch and jumpers S1 Base address P7 8254 timer counter I O configuration P8 Interrupts The board layout is shown in Figure D 1 2 xn BASE ADDRESS E 00000 synon 859999 R H e L AD678 USED Ene bee m Oc 0 Oc D ooooooou ens odi 00000000 00000000 B a Jon op Je o 000000090090 90992 AD1200 ADA1200 os TRI BE DATA ACQUISITION amp CONTRO
56. VICES Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAM AGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the control of REAL TIME DEVICES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS EX PRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAM AGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR C
57. Word or an initial count Both RD and WR are qualified by CS RD and WR are ignored unless the 82054 has been selected by holding CS low 3 85 CONTROL WORD REGISTER The Control Word Register see Figure 4 is selected by the Read Write Logic when Ay Ap 11 If the CPU then does a write operation to the 82C54 the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters The Control Word Register can only be written to status information is available with the Read Back Command DATA BUS BUFFER a gt 2 Ei z w E z 231244 5 Figure 4 Block Diagram Showing Control Word Register and Counter Functions COUNTER 0 COUNTER 1 COUNTER 2 These three functional blocks are identical in opera tion so only a single Counter will be described The internal block diagram of a single counter is shown in Figure 5 The Counters are fully independent Each Counter may operate in a different Mode The Control Word Register is shown in the figure it is not part of the Counter itself but its contents de termine how the Counter operates 82C54 EG CONTROL a ET 231244 6 Figure 5 internal Block Diagram of a Counter The status register shown in the Figure when latched contains the current contents of the Control Word Register and status of the output and null count flag See detailed explanation o
58. a unipolar range of 0 to 10 volts The board is factory set for 5 to 5 volts Overvoltage protection to 35 volts is provided at the inputs The high performance A D converter supports resistor configurable gain circuitry so that you can customize the input gain A D conversions are performed in 5 microseconds and the maximum throughput rate is 125 kHz Conversions are controlled through software by an on board pacer clock or by an external trigger brought onto the board through the I O connector The converted data can be transferred through the PC data bus to PC memory in one of two ways by using the microprocessor or by using direct memory access DMA The mode of transfer is software selectable and the DMA channel is chosen by jumper settings on the board The PC data bus is used to read and or transfer data to PC memory In the DMA transfer mode you can make continuous transfers directly to PC memory without going through the processor l Digital to Analog Conversion ADA1200 Only The digital to analog D A circuitry on the ADA 1200 features two independent 12 bit analog output channels with individually jumper selectable output ranges of 5 to 5 volts 10 to 10 volts 0 to 5 volts or 0 to 10 volts Data is programmed into the D A converter and a conversion is automatically triggered for a channel through a single write operation Access through DMA is not available 8254 Timer Counter An 8254 programmable interval timer con
59. a Buffer Once you have a buffer into which to place your data you must inform the DMA controller of the location of this buffer This is a little more complex than it sounds because the DMA controller uses a page offset memory scheme while you are probably used to thinking about your computer s memory in terms of a segment offset scheme Paged memory is simply memory that occupies contiguous non overlapping blocks of memory with each block being 64K one page in length The first page page 0 starts at the first byte of memory the second page page 1 starts at byte 65536 the third page page 2 at byte 131072 and so on A computer with 640K of memory has 10 pages of memory The DMA controller can write to or read from only one page without being reprogrammed This means that the DMA controller has access to only 64K of memory at a time If you program it to use page 3 it cannot use any other page until you reprogram it to do so When DMA is started the DMA controller is programmed to place data at a specified offset into a specified page for example start writing at byte 512 of page 3 Each time a byte of data is written by the controller the offset is automatically incremented so the next byte will be placed in the next memory location The problem for you when programming these values is figuring out what the corresponding page and offset are for your buffer Most compilers contain macros or functions that allow you to directly determi
60. alibration results Table 5 1 A D Converter Bit Weights Unipolar Straight Binary Ideal Input Voltage millivolts A D Bit Weight 0 to 10 Volts 5 4 Data Values for Calibrating Unipolar 10 Volt Range 0 to 10 volts Offset TR7 Converter Gain TR2 Input Voltage 1 22070 mV Input Voltage 9 49829 V 0000 0000 0000 1111 0011 0010 A D Converted Data 0000 0000 0001 1111 0011 0011 Bipolar Calibration Bipolar Range Adjustments 5 to 5 Volts Two adjustments are made to calibrate the A D converter for the bipolar range of 5 to 5 volts One is the offset adjustment and the other is the full scale or gain adjustment Trimpot TR3 is used to make the offset adjustment and trimpot TR2 is used for gain adjustment Before making these adjustments make sure that the jumper on P3 is set for 10V and the jumpers on P4 and P11 are set for Use analog input channel 1 and set it for a gain of 1 while calibrating the board Connect your precision voltage source to channel 1 Set the voltage source to 4 99878 volts start a conversion and read the resulting data Adjust trimpot TR3 until it flickers between the values listed in the table below Next set the voltage to 4 99634 volts and repeat the procedure this time adjusting TR2 until the data flickers between the values in the table Data Values for Calibrating Bipolar 10 Volt Range 5 to 5 volts Offset TR3 Converter Gain TR2 Input Voltage
61. ammed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis A POM PAPA B A 10 VO PO PB CONTROL CONTROL PA P OR HO OR HO Arte A Pe vo AAA PAP 172o CONTROL 77h 231256 5 Figure 5 Basic Mode Definitions and Bus interface 82C55A CONTROL WORD PORT C LOWER Y INPUT 0 OUTPUT PORT 8 1 INPUT 0 OUTPUT MODE SELECTION PORT C UPPER Y INPUT 0 OUTPUT MODE SELECTION 00 MODE O MODE SET FLAG Y ACTIVE 231256 6 Figure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but after a cursory review of the complete device operation a simple logical I O approach will surface The design of the 82C55A has taken into account things such as effi cient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the maximum use of the available pins Single Bit Set Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction This feature re duces software requirements in Control based appli cations When Port C is being used as status control for Port A or B these bits can be set or reset by using the Bit Set Reset operation just as if they were data output ports 3 128 intel 82C55A BIT SET RESET 1 8ET S O RESET
62. ch is selected when A4 Ag 11 The Control Word itself specifies which Counter is being programmed By contrast initial counts are written into the Coun ters not the Control Word Register The Ay Ag in puts are used to select the Counter to be written into The format of the initial count is determined by the Control Word used D De Ds D4 D3 D2 D Do scr sco pws awo m2 wi mo Bco SC Select Counter SC1 SCO o oe estar or Select Counters Le sect Counter Read Back Command See Read Operations KEEN RW Read Write RW1 RWO Counter Latch Command see Read Operations Read Write least significant byte only ENTE Read Write most significant byte only 1 1 Read Write least significant byte first then most significant byte NOTE Don t care bits X should be O to insure compatibility with future Intel products M MODE EE Binary Counter 16 bits Binary Coded Decimal BCD Counter 4 Decades Figure 7 Contro Word Format 3 87 intel 82054 Write Operations The programming procedure for the 82054 is very flexible Only two conventions need to be remem bered 1 For each Counter the Control Word must be written before the initial count is written 2 The initial count must follow the count format specified in the Control Word least significant byte only most significant byte only or least sig nificant byte and then most significant byte
63. d major concern when writing your ISR is to make it as short as possible in terms of execution time Spending long periods of time in your ISR may mean that other important interrupts are being ignored Also if you spend too long in your ISR it may be called again before you have completed handling the first run This often leads to a hang that requires a reboot Your ISR should have this structure Push any processor registers used in your ISR Most C and Pascal interrupt routines automatically do this for you Put the body of your routine here Clear the interrupt bit on the 1200 by writing any value to BA 2 Issue the EOI command to the 8259 interrupt controller by writing 20H to port 20H Pop all registers pushed on entrance Most C and Pascal interrupt routines automatically do this for you 4 17 The following C and Pascal examples show what the shell of your ISR should be like In C void interrupt ISR void Your code goes here Do not use any DOS functions outportb BaseAddress 2 0 Clear 1200 interrupt outportb 0x20 0x20 Send EOI command to 8259 In Pascal Procedure ISR Interrupt begin Your code goes here Do not use any DOS functions Port BaseAddress 2 0 Clear 1200 interrupt Port 20 20 Send EOI command to 8259 end Saving the Startup Interrupt Mask Register IMR and Interrupt Vector The next step after writing the ISR is to sav
64. e Wave Mode Similar to Mode 2 except for the duty cycle output this mode is typically used for baud rate generation The output is initially high and when the count decrements to one half its initial count the output goes low for the remainder of the count The timer counter reloads and the output goes high again This process repeats indefinitely Mode 4 Software Triggered Strobe The output is initially high When the initial count expires the output goes low for one clock pulse and then goes high again Counting is triggered by writing the initial count Mode 5 Hardware Triggered Strobe Retriggerable The output is initially high Counting is triggered by the rising edge of the gate input When the initial count has expired the output goes low for one clock pulse and then goes high again Digital I O The 16 8255 PPI based digital 1 O lines can be used to transfer data between the computer and external devices The digital input lines can have pull up or pull down resistors installed as described in Chapter 1 Example Programs and Flow Diagrams Included with the 1200 is a set of example programs that demonstrate the use of many of the board s features These examples are written in C Pascal and BASIC Also included is an easy to use menu driven diagnostics program 1200DIAG which is especially helpful when you are first checking out your board after installation and when calibrating the board Chapter 5 Before usi
65. e computer s I O Should the factory setting of 300 hex 768 decimal be unsuitable for your system you can select a different base address simply by setting the switches to any one of the values listed in Table 1 2 The table shows the switch settings and their corresponding decimal and hexadecimal in parentheses values Make sure that you verify the order of the switch numbers on the switch 1 through 5 before setting them When the switches are pulled forward they are OPEN or set to logic 1 as labeled on the DIP switch package When you set the base address for your board record the value in the table inside the back cover Figure 1 14 shows the DIP switch set for a base address of 300 hex 768 decimal Fig 1 14 Base Address Switch S1 Table 1 2 Base Address Switch Settings S1 Base Address Switch Setting Base Address Switch Setting Decimal Hex 54321 Decimal Hex 54321 5121000 10000 528 210 10001 544 220 10010 560 230 00011 10011 576 240 10100 592 250 10101 608 260 10110 624 270 10111 IE EI 656 290 11001 672 2A0 11010 688 2B0 11011 704 1 2C0 11100 EE EETY 736 2E0 11110 752 2F0 LEEN Pull up Pull down Resistors on Digital I O Lines The 8255 programmable peripheral interface provides 16 TTL CMOS compatible digital I O lines which can be interfaced with external devices These lines are divided into three groups eight Port A lines four Port C Lo
66. e loaded from the interrupt vector table the processor begins executing the code located at CS IP When the interrupt routine is completed the CS IP and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and execution resumes from the point where it was interrupted Using Interrupts in Your Programs Adding interrupts to your software is not as difficult as it may seem and what they add in terms of performance is often worth the effort Note however that although it is not that hard to use interrupts the smallest mistake will often lead to a system hang that requires a reboot This can be both frustrating and time consuming But after a few 4 16 tries you ll get the bugs worked out and enjoy the benefits of properly executed interrupts In addition to reading the following paragraphs study the INTRPTS source code included on your 1200 program disk for a better understand ing of interrupt program development Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the interrupt service routine ISR This is the routine that will automatically be executed each time an interrupt request occurs on the specified IRQ An ISR is different than standard routines that you write First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must clear the
67. e mask status of an IRQ line bit 0 is for IRQO bit 1 is for IRQ and so on If a bit is set equal to 1 then the corresponding IRQ is masked and it will not generate an interrupt If a bit is clear equal to 0 then the corresponding IRQ is unmasked and can generate interrupts The IMR is programmed through port 21H nar mos mos nas mas maz mas oo orna For all bits 0 IRQ unmasked enabled 1 IRQ masked disabled End of Interrupt EOI Command After an interrupt service routine is complete the 8259 interrupt controller must be notified This is done by writing the value 20H to I O port 20H What Exactly Happens When an Interrupt Occurs Understanding the sequence of events when an interrupt is triggered is necessary to properly write software interrupt handlers When an interrupt request line is driven high by a peripheral device such as the 1200 the interrupt controller checks to see if interrupts are enabled for that IRQ and then checks to see if other interrupts are active or requested and determines which interrupt has priority The interrupt controller then interrupts the proces sor The current code segment CS instruction pointer IP and flags are pushed on the stack for storage and a new CS and IP are loaded from a table that exists in the lowest 1024 bytes of memory This table is referred to as the interrupt vector table and each entry is called an interrupt vector Once the new CS and IP ar
68. e the startup state of the interrupt mask register and the interrupt vector that you will be using The IMR is located at I O port 21H The interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 bit 4 byte pointers and is located in the first 1024 bytes of memory Segment 0 Offset 0 You can read this value directly but it is a better practice to use DOS function 35H get interrupt vector Most C and Pascal compilers provide a library routine for reading the value of a vector The vectors for the hardware interrupts are vectors 8 through 15 where IRQO uses vector 8 IRQ uses vector 9 and so on Thus if the 1200 will be using IRQ3 you should save the value of interrupt vector 11 Before you install your ISR temporarily mask out the IRQ you will be using This prevents the IRQ from requesting an interrupt while you are installing and initializing your ISR To mask the IRQ read in the current IMR at 1 O port 21H and set the bit that corresponds to your IRQ remember setting a bit disables interrupts on that IRQ while clearing a bit enables them The IMR is arranged so that bit O is for IRQO bit 1 is for IRQ1 and so on See the paragraph entitled Interrupt Mask Register IMR earlier in this chapter for help in determining your IRQ s bit After setting the bit write the new value to 1 0 port 21H With the startup IMR saved and the interrupts on your IRQ temporarily disabled you can assi
69. ed data can be transferred through the PC data bus to PC memory in one of two ways by using the microprocessor or by using direct memory access DMA Data bus transfers take more processor time to execute They use polling and interrupts to determine when data has been acquired and is ready for transfer DMA places data directly into the PC s memory one byte at a time with minimal use of processor time DMA transfers are managed by the DMA controller as a background function of the PC letting you operate at higher throughput rates The maximum throughput rate of the 1200 is 125 kHz D A Converters ADA 1200 Only Two independent 12 bit analog output channels are included on the ADA1200 The analog Outputs are gener ated by two 12 bit D A converters with independent jumper selectable output ranges of 5 10 0 to 5 or 0 to 10 volts The 10 volt range has a resolution of 4 88 millivolts the 5 and 0 to 10 volt ranges have a resolution of 2 44 millivolts and the 0 to 5 volt range has a resolution of 1 22 millivolts Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters to support a wide range of timing and counting functions Two of the timer counters TCO and TC1 are cascaded so that they can be used for the pacer clock The pacer clock is described in Chapter 4 You can use the remaining timer counter TC2 for counting applications or cascade it to TCO and TC1 for timing applications Figure 3
70. ed to interrupt the CPU when an input device is requesting service INTR is set by the STB is a one IBF is a one and INTE is a one It is reset by the falling edge of RD This procedure allows an input device to re quest service from the CPU by simply strobing its data into the port INTE A Controlled by bit set reset of PC4 INTE B Controlled by bit set reset of PCo BROM PERIPHERAL MODE 1 PORT A CONTROL WORD D De D O D Dz D De sloft mb PC 1 INPUT MODE 1 PORT 8 CONTROL WORD D De D D Dy D O Do INDI Xd 231256 13 Figure 8 MODE 1 Input 231256 14 Figure 9 MODE 1 Strobed Input 3 134 Output Control Signal Definition OBF Output Buffer Full F F The OBF output will go low to indicate that the CPU has written data out to the specified port The OBF F F will be set b the rising edge of the WR input and reset by ACK input being low ACK Acknowledge Input A low on this input informs the 82C55A that the data from Port A or Port B has been accepted In essence a response from the peripheral device indicating that it has received the data output by the CPU INTR Interrupt Request A high on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU INTR is set when ACK is a one OPF is a one and INTE is a one It is reset by the falling edge of WR INT
71. een enabled Monitoring Conversion Status DMA Done or End of Convert The A D conversion status can be monitored through the DMA done flag or through the end of convert EOC bit in the STATUS port at BA 0 When doing DMA transfers you will want to monitor the DMA done flag for a transition from low to high This tells you when the DMA transfer is complete and data has been placed in the PC s memory The EOC line is available for monitoring conversion status when performing single conversions not using DMA transfer When the EOC goes from low to high the A D converter has completed its conversion and the data is ready to read The EOC line stays high following a conversion until the data has been read Then the line goes back to low until the next conversion is complete Reading the Converted Data Two successive reads of port BA 1 provide the LSB and MSB of the 12 bit A D conversion in the format defined in the UO map section at the beginning of this chapter The LSB must always be read first followed by the MSB The output code and the resolution of the conversion vary depending on the input voltage range selected Bipolar conversions are in twos complement form and unipolar conversions are straight binary When a bipolar value is read you must first convert the result to straight binary and then calculate the voltage The conversion formula is simple for values greater than 2047 you must subtract 4096 from the value to get the si
72. equence is triggered by writing the initial count GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after the initial count is written If a new count is written during counting it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens intel 82054 1 Writing the first byte has no effect on counting 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to be retriggered by software OUT strobes low N 1 CLK pulses after the new count of N is written CW 18 LSB 3 Palou rs 12 ole lel tei ro CWs18 LS8B 3 Isuju tm oisislolelole CW 18 1S8 3 LSB 2 ojojojo jojo ter EOS E Ee t Eo Lel 2 31244 12 Figure 19 Mode 4 MODE 5 HARDWARE TRIGGERED STROBE RETRIGGERABLE OUT will initially be high Counting is triggered by a rising edge of GATE When the initial count has ex pired OUT will go low for one CLK pulse and then go high again After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a trigger This CLK pulse does not decrement the cou
73. eral devices to generate interrupts on the same computer the PC bus has eight different interrupt request IRQ lines A transition from low to high on one of these lines generates an interrupt request which is handled by the PC s interrupt controller The interrupt controller checks to see if interrupts are to be acknowledged from that IRQ and if another interrupt is already in progress it decides if the new request should supersede the one in progress or if it has to wait until the one in progress is done This prioritizing allows an interrupt to be interrupted if the second request has a higher priority The priority level is based on the number of the IRQ IRQO has the highest priority IRQ1 is second highest and so on through IRQ7 which has the lowest Many of the IRQs are used by the standard system resources IRQO is used by the system timer IRQ is used by the key board IRQ3 by COM2 IRQ4 by COMI and IRQ6 by the disk drives Therefore it is important for you to know which IRQ lines are available in your system for use by the 1200 board 8259 Programmable Interrupt Controller The chip responsible for handling interrupt requests in the PC is the 8259 Programmable Interrupt Controller To use interrupts you need to know how to read and set the 8259 s interrupt mask register IMR and how to send the end of interrupt EOI command to the 8259 Interrupt Mask Register IMR Each bit in the interrupt mask register IMR contains th
74. eset Figure 4 Port A B C Bus hold Configuration E 3 127 gs nn Ree R en intel 82C55A OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software Mode 0 Basic input output Mode 1 Strobed Input output Mode 2 Bi directional Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one level by the internal bus hold devices see Figure 4 Note After the reset is removed the 82C55A can remain in the input mode with no addi tional initialization required This eliminates the need for pullup or pulldown devices in all CMOS de signs During the execution of the system program any of the other modes may be selected by using a single output instruction This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost any I O structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display computa tional results Group A could be progr
75. et FP OFS amp Buffer get offset of buffer linear address segment 16 offset calculate a linear address page linear address 65536 determine page corresponding to this linear address page_offset linear address 65536 determine offset into the page In BASIC S VARSEG BUFFER O VARPTR BUFFER LA S 16 0 PAGE INT LA 65536 POFF LA PAGE 65536 Beware There is one big catch when using page based addresses The DMA controller cannot write properly to a buffer that straddles a page boundary A buffer straddles a page boundary if one part of the buffer resides in one page of memory while another part resides in the following page The DMA controller cannot properly write to such a buffer because the DMA controller can only write to one page without reprogramming When it reaches the end of the current page it does not start writing to the next page Instead it starts writing back at the first byte of the current page This can be disastrous if the beginning of the page does not correspond to your buffer More often than not this location is being used by the code portion of your program or the operating system and writing data to it will almost always causes erratic behavior and an eventual system crash You must check to see if your buffer straddles a page boundary and if it does take action to prevent the DMA controller from trying to write to the portion that continues on t
76. et the pacer clock frequency at 100 kHz using the on board 8 MHz clock source this equation becomes Divider 1 x Divider 2 8 MHz 100 kHz gt 80 8 MHz 100 kHz 4 14 After you determine the value of Divider 1 x Divider 2 you then divide the result by the least common denomi nator The least common denominator is the value that is loaded into Divider 1 and the result of the division the quotient is loaded into Divider 2 In our example above the least common denominator is 2 so Divider 1 equals 2 and Divider 2 equals 80 2 or 40 The table below lists some common pacer clock frequencies and the counter settings using the on board 8 MHz clock source After you calculate the decimal value of each divider you can convert the result to a hex value if it is easier for you when loading the count into the 16 bit counter To set up the pacer clock on the 1200 follow these steps 1 Select a clock source the 8 MHz on board clock or an external clock source 2 Program Timer Counter 0 for Mode 2 operation 3 Program Timer Counter 1 for Mode 2 operation 4 Load Divider 1 LSB 5 Load Divider 1 MSB 6 Load Divider 2 LSB 7 Load Divider 2 MSB The pacer clock starts running as soon as the last divider is loaded A D conversions can be started and stopped by enabling and disabling the external trigger Timer Counter 1 Timer Counter 0 8 MHz Divider 1 Divider 2 Pacer Clock Fig 4 2 Pace
77. etely TTL Compatible m Handles Inputs from DC to 8 MHz 10 MHz for 82C54 2 diaas bria Modes m Available in EXPRESS lal d cot eno m Status Read Back Command Standard Temperature Range Extended Temperature Range _ m Avallable in 24 Pin DIP and 28 Pin PLCC The Intel 82C54 is a high performance CHMOS version of the industry standard 8254 counter timer which is designed to solve the timing control problems common in microcomputer system design It provides three independent 16 bit counters each capable of handling clock inputs up to 10 MHz All modes are software programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253 Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator programmable one shot and in many other applications The 82C54 is fabricated on Intel s advanced CHMOS Ill technology which provides low power consumption with performance equal to or greater than the equivalent HMOS product The 82C54 is available in 24 pin DIP and 28 pin plastic leaded chip carrier PLCC packages Ds De Dr NC Vcc WR RD L 3 Bus BUFFER 231244 3 231244 1 Figure 1 82C54 Block Diagram 231244 2 Diagrams are for pin reference only Package sizes are not to scale Figure 2 82C54 Pinout September 1989 3 83 Order Number 231244 005 intel 82054 Table 1 Pin Description Eele aa E DP Pece a EEE Data Bidirectio
78. f the Read Back command The actual counter is labelled CE for Counting Ele ment It is a 16 bit presettable synchronous down counter OLm and OL are two 8 bit latches OL stands for Output Latch the subscripts M and L stand for Most significant byte and Least significant byte respectively Both are normally referred to as one unit and called just OL These latches normally fol low the CE but if a suitable Counter Latch Com mand is sent to the 82C54 the latches latch the present count until read by the CPU and then return to following the CE One latch at a time is enabled by the counter s Control Logic to drive the internal bus This is how the 16 bit Counter communicates over the 8 bit internal bus Note that the CE itself cannot be read whenever you read the count it is the OL that is being read Similarly there are two 8 bit registers called CRm and CR for Count Register Both are normally referred to as one unit and called just CR When a new count is written to the Counter the count is 3 86 stored in the CR and later transferred to the CE The Control Logic allows one register at a time to be loaded from the internal bus Both bytes are trans ferred to the CE simultaneously CRm and CR are cleared when the Counter is programmed In this way if the Counter has been programmed for one byte counts either most significant byte only or least significant byte o
79. g INTR IBF and OBF can be written or an interrupt enable flag can be either set or reset Port C lines programmed as inputs including ACK and STB lines associated with Port C are not affected by a Set Reset Port C Bit command Writing to the corresponding Port C bit positions of the ACK and STB lines with the Set Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illus trated in Figure 18 Current Drive Capability Any output on Port A B or C can sink or source 2 5 mA This feature allows the 82C55A to directly drive Darlington type drivers and high voltage displays that require such sink or source current 3 139 intel 82C55A INPUT CONFIGURATION Reading Port C Status D De Ds D Da D2 Di Do in Mode 0 Port C transfers data to or from the pe vo vo tera INTE INTRa INTE 186 INTRa ripheral device When the 82C55A is programmed to IBFA INTEA Es IBFs function in Modes 1 or 2 Port C generates or ac nee NC PA ROUP B cepts hand shaking signals with the peripheral de REM l 99 vice Reading the contents of Port C allows the pro OUTPUT CONFIGURATIONS grammer to test or verify the status of each pe D Dg Ds D4 D3 Do OD Do ripheral device and change the program flow ac JOL VOl INTRa INT Ka oer wres vo vo rn wres Ss wr GROUP A GROUP B There is no special instruction to read the status in formation from Port C A normal read o
80. ger input P2 39 and output P2 43 so that conversions can be started based on external events or so that two or more boards can be cascaded and run synchronously in a master slave configuration By cascading two or more boards as shown in Figure 2 3 they can be triggered to start an A D conversion at the same time sampling uncertainty is less than 50 nanoseconds When you cascade boards be sure to set each board for a different base address see Chapter 1 or system contention will result NOTE When cascading boards the sampling uncertainty is less than 50 nanoseconds If this level of uncer tainty is too great for your application you can connect the trigger signal to the trigger input of each board In this configuration the boards are not cascaded but rather driven by the same trigger pulse at the same time and the sampling uncertainty is reduced to less than 5 nanoseconds If you apply an external trigger to the board s trigger in pin note that a jumper should be installed on ET on P7 see Chapter 1 The board is triggered on the positive edge of the pulse and the pulse duration should be at least 100 nanoseconds 2 4 1200 VO CONNECTOR P2 BOARD 11 MASTER BOARD 2 SLAVE Fig 2 3 Cascading Two Boards for Simultaneous Sampling Connecting the Analog Outputs ADA1200 Only For each of the two D A outputs connect the high side of the device receiving the output to the AOUT channel P2 17 or P2
81. gn of the voltage For example if your output is 2048 you subtract 4096 2048 4096 2048 This result corresponds to 5 volts or 10 volts depending on your binary range For values of 2047 or less you simply convert the result The key digital codes and their input voltage values are given for each range in the three tables which follow 4 13 5V twos complement 4 998 volts MSB 0111 1111 1111LSB 42 500 volts 00244 volts 5 000 volts 1 LSB 2 44 millivolts 10V twos complement Input Voltage 49 995 volts MSB 0111 1111 1111 LSB 45 000 volt 00488 volts 10 000 volts 1 LSB 4 88 millivolts A D Unipolar Code Table 0 to 10V straight binary Input Voltage 49 99756 volts 5 00000 vats Programming the Pacer Clock Two of the three 16 bit timer counters in the 8254 programmable interval timer are cascaded to form the on board pacer clock shown in Figure 4 2 When you want to use the pacer clock for continuous A D conversions you must program the clock rate To find the value you must load into the clock to produce the desired rate you first have to calculate the value of Divider 1 Timer Counter 0 and Divider 2 Timer Counter 1 shown in the diagram The formulas for making this calculation are as follows Pacer clock frequency Clock Source Frequency Divider 1 x Divider 2 Divider 1 x Divider 2 Clock Source Frequency Pacer Clock Frequency To s
82. gn the interrupt vector to point to your ISR Again you can overwrite the appropriate entry in the vector table with a direct memory write but this is a bad practice Instead use either DOS function 25H set interrupt vector or if your compiler provides it the library routine for setting an interrupt vector Remember that vector 8 is for IRQO vector 9 is for IRQ1 and so on If you need to program the source of your interrupts do that next For example if you are using the program mable interval timer to generate interrupts you must program it to run in the proper mode and at the proper rate Finally clear the bit in the IMR for the IRQ you are using This enables interrupts on the IRQ Restoring the Startup IMR and Interrupt Vector Before exiting your program you must restore the interrupt mask register and interrupt vectors to the state they were in when your program started To restore the IMR write the value that was saved when your program started to 1 O port 21H Restore the interrupt vector that was saved at startup with either DOS function 35H get interrupt vector or use the library routine supplied with your compiler Performing these two steps will guarantee that the interrupt status of your computer is the same after running your program as it was before your program started running 4 18 Common Interrupt Mistakes Remember that hardware interrupts are numbered 8 through 15 even though the corresponding
83. he next page You can reduce the size of the buffer or try to reposition the buffer However this can be difficult when using large static data structures and often the only solution is to use dynamically allocated memory Setting the DMA Page Register Oddly enough you do not inform the DMA controller directly of the page to be used Instead you put the page to be used into the DMA page register which is separate from the DMA controller as shown in the table below The location of this register depends on the DMA channel being used DMA Channel Location of Page Register sen UE aia 821130 4 21 The DMA Controller The DMA controller is a complex chip that occupies the first 16 bytes of the PC s I O port space A complete discussion on how it operates is beyond the scope of this manual only relevant information is included here The DMA controller is programmed by writing to the DMA registers in your PC The table below lists these registers Note that when you write 16 bit values to any of these registers such as to the Count registers you must write the LSB first followed by the MSB If you are using DMA channel 1 write your page offset and count to ports 02H and 03H if you are using channel 3 write your page offset and count to ports 06H and 07H The page offset is simply the offset that you calculated for your buffer see discussion above Count indicates the number of bytes that you want the DMA controller to
84. imer counter to microcomputers which can be implemented with designed for use with Intel microcomputer systems the 82C54 are It is a general purpose multi timing element that can be treated as an array of I O ports in the system software Real time clock Even counter Digital one shot Programmable rate generator Square wave generator Binary rate multiplier Complex waveform generator Complex motor controller The 82C54 solves one of the most common prob lems in any microcomputer system the generation of accurate time delays under software control In stead of setting up timing loops in software the pro grammer configures the 82C54 to match his require ments and programs one of the counters for the de 82054 Block Diagram DATA BUS BUFFER This 3 state bi directional 8 bit buffer is used to in terface the 82C54 to the system bus see Figure 3 COUNTER 0 E e 3 2 3 lt z z w S z 231244 4 Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC The Read Write Logic accepts inputs from the sys tem bus and generates control signals for the other functional blocks of the 82C54 A and Ag select one of the three counters or the Control Word Regis ter to be read from written into A low on the RD input tells the 82C54 that the CPU is reading one of the counters A low on the WR input tells the 82054 that the CPU is writing either a Control
85. interrupt status of the 1200 and write an end of interrupt command to the 8259 controller Finally when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET The IRET automatically pops the flags CS and IP that were pushed when the interrupt was called If you find yourself intimidated by interrupt programming take heart Most Pascal and C compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the procedure you must do this yourself Other than this and the few exceptions discussed below you can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR we recommend that you stick to the basics just something that will convince you that it works such as incrementing a global variable NOTE If you are writing an ISR using assembly language you are responsible for pushing and popping registers and using IRET instead of RET There are a few cautions you must consider when writing your ISR The most important is do not use any DOS functions or routines that call DOS functions from within an ISR DOS is not reentrant that is a DOS function cannot call itself In typical programmi
86. inue from the new count Otherwise the new count will be loaded at the end of the current half cycle Mode 3 is implemented as follows Even counts OUT is initially high The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses When the count expires OUT changes value and the Counter is re loaded with the initial count The above process is repeated indefinitely Odd counts OUT is initially high The initial count minus one an even number is loaded on one CLK pulse and then is decremented by two on succeed ing CLK pulses One CLK pulse after the count ex pires OUT goes low and the Counter is reloaded with the initial count minus one Succeeding CLK pulses decrement the count by two When the count expires OUT goes high again and the Counter is reloaded with the initial count minus one The above process is repeated indefinitely So for odd counts 3 93 OUT will be high for N 1 2 counts and low for N 1 2 counts CWs amp 6 15004 L e Juuuuuuuuuuunu tall helle eres CWet6 L8Ba5 GEE ETEHEDE EIS PE ee CWais 18824 PULL our ala el 231244 11 NOTE A GATE transition should not occur one clock prior to terminal count Figure 18 Mode 3 MODE 4 SOFTWARE TRIGGERED STROBE OUT will be initially high When the initial count ex pires OUT will go low for one CLK pulse and then go high again The counting s
87. lled secure the slot bracket back into place and put the cover back on your computer The board is now ready to be connected via the external I O connector at the rear panel of your computer External I O Connections Figure 2 1 shows the 1200 s P2 I O connector pinout Refer to this diagram as you make your I O connections AIN1 AIN2 AIN3 AIN4 AINS AIN9 AIN10 AIN11 AIN12 AIN13 AING AIN14 AIN7 3 alas AINS AIN16 AOUT1 ANALOG GND aoutz 9 9 ANALOG anp ANALOG GND 3 ANALOG GND rar 16363 por Pas 3 9 Pce pas 1 3 Pcs pas 63 G3 Pcs Pas 6362 Pcs Paz 16363 pcz Par 6369 per pao 6363 pcn TRIGGER IN 6369 DIGITAL GND EXT GATE 1 6362 vic ovr 1 TRIGGER OUT 6363 Tc our 2 EXT CLK 6363 ExT GATE 2 12 VOLTS 62683 5 voLTs 12 VOLTS 6369 piairaL ann Fig 2 1 P2 I O Connector Pin Assignments 2 3 Connecting the Analog Input Pins Connect the high side of the analog input to one of the analog input channels AIN1 through AIN16 and connect the low side to an ANALOG GND pins 18 and 20 22 on P2 Figure 2 2 shows how these connections are made NOTE It is good practice to connect all unused channels to ground as shown in the following diagrams Failure to do so may affect the accuracy of your results 1200 UO CONNECTOR P2 Fig 2 2 Analog Input Connections Connecting the Trigger In and Trigger Out Pins Cascading Boards The 1200 board has an external trig
88. ms to aid you in programming The example programs included on the disk in your board package are listed at the end of this chapter These programs written in Turbo C Turbo Pascal and BASIC include source code to simplify your applications programming 4 1 Defining the VO Map The I O map for the AD1200 and ADA 1200 is shown in Table 4 1 below As shown the board occupies 16 consecutive I O port locations The base address designated as BA can be selected using DIP switch S1 as de scribed in Chapter 1 Board Settings This switch can be accessed without removing the board from the computer Sl is factory set at 300 hex 768 decimal The following sections describe the register contents of each address used in the 1 O map Table 4 1 AD1200 ADA1200 I O Map Address Register Description Read Function Write Function Decimal Read Status Start Convert Read status word Start A D conversion BA 0 Simultaneously update Read converted data LSB DAC 1 and DAC 2 Read Data Update DACs first then MSB ADA1200 only BA 1 Resets board so that it is ready to start A D conversions BA 2 Notused Notusea Bara Program Port A digital output 8255 PPI Port A Read Port A digital input lines lines BA 4 8255 PPI Port B Program channel external Channel Board Functions Read Port B bits trigger enable IRQ enable BA 5 Program Port C digital output 8255 PPI Port C Read Port C digital input lines lines BA
89. mula in Figure 1 17 Capacitor C36 is provided so that you can add low pass filtering in the gain circuit If your input signal is a slowly changing one and you do not need to measure it at a higher rate you may want to add a capacitor at C36 in order to reduce the input frequency range and in turn reduce the noise on your input signal The formula for setting the frequency is given in the diagram Figure 1 17 shows how the gain circuitry is configured solder short 1 12 Remove Solder Short Between These 2 Pads on Bottom Side of Board 00000 fT66600 9909090000000U Db AD678 999628 0000000 and bid i LAH CH en ws 20000000 E D 74HCTO4 0000000 a 0000000000 Real Time Devices irc Stats College PA 18804 USA Fig 1 18 Diagram for Removal of Solder Short 1 14 CHAPTER 2 BOARD INSTALLATION The 1200 is easy to install in your IBM PC XT AT or compat ible computer It can be placed in any slot short or full size This chapter tells you step by step how to install and connect the board After you have installed the board and made all of your con nections you can turn your system on and run the 1200DIAG board diagnostics program included on your example software disk to verify that your board is working 2 1 Board Installation Keep the board in its antistatic bag until you are ready to install it in your computer When removing
90. n a conversion starts and then goes high as soon as the conversion is completed When the input has been sampled and a conversion is in progress this line goes low At this time the analog input channel can be changed allowing maximum throughput for channel scanning A write starts an A D conversion data written is irrelevant A D CONVERTER Status 0 converting 1 not converting EXT GATE 2 Status monitors external gate 2 line End of Convert 0 2 no EOC 1 conversion done DMA Done 0 DMA not done IRQ Status 1 DMA done 0 No IRQ 1 IRQ BA 1 Read A D Data Update DAC Outputs Read Write Two successive reads provide the LSB first followed by the MSB for each A D conversion as defined below If a conversion is started before this data is read from the previous conversion the data will be lost When j jumpers on P4 and P11 are set for bipolar conversions the data word s four most significant bits match the most significant bit of the A D converted data bit 11 This is necessary to provide the correct twos complement representation of the converted data When P4 and P11 are set for unipolar conversions these top four bits are 0 Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit 2 Bit 1 Bit 0 on or oe Te os es ee Tor Too Bit 11 Bit11 Bit11 Bit11 Bit11 Bit10 Bit9 A write simultaneously starts a D A conversion in both DACs data written is irrelevant If the data written to either channel has not been updated since
91. nal tri state data bus lines connected to system data bus ciko 9 10 ClockO ClockimputofCounterO ouro 10 12 O Outputo OutputofCountero GaTEO 1 13 Gateo GateinputofCourter0 GND 12 14 Ground Powersupplyconnecton our 13 3136 O Outt OutputofCountert GATE1 14 417 1 Gate1 GateinputofCountert c1 15 186 Clock1 ClockinputofCountert GarE2 16 19 Gate2 GateinputofCounter2 our2 17 20 O Out2 OutputofCounter2 c k2 18 21 Clock 2 ClockinputofCounter2 Counter 2 Ay Ao 20 19 23 22 Address Used to select one of the three Counters Control Word Register or the Control Word Register for read or write operations Normally connected to the system address bus CS 21 24 Chip Select A low on this input enables the 82C54 to respond to RD and WR signals RD and WR are ignored lia Lol Bl WINE NUR E ar operations MCA EE Write Control This input is low during CPU write operations Voc 204 2 o Power 5V power supply connection NC 111525 NoComet Counter O Counter 1 sired delay After the desired delay the 82C54 will FUNCTIONAL DESCRIPTION interrupt the CPU Software overhead is minimal and variable length delays can easily be accommodated General Some of the other counter timer functions common The 82C54 is a programmable interval t
92. ne the segment and offset of a data structure but not the page and offset Therefore you must calculate the page number and offset yourself Probably the most intuitive way of doing this is to convert the segment offset address of your buffer to a linear address and then convert that linear address to a page offset address The table below shows functions macros for determining the segment and offset of a buffer C FP_SEG FP_OFF s FP_SEG amp Buffer o FP_OFF amp Buffer Seg Ofs S Seg Buffer O Ofs Buffer BASIC VARSEG VARPTR S VARSEG BUFFER O VARPTR BUFFER Once you ve determined the segment and offset multiply the segment by 16 and add the offset to give you the linear address Make sure you store this result in a long integer or DWORD or the results will be meaningless The page number is the quotient of the division of the linear address by 65536 and the offset into the page is the remainder of that division Below are some programming examples for Pascal C and BASIC 4 20 In Pascal get segment of buffer get offset of buffer calculate a linear address determine page corresponding to this linear Segment SEG Buffer Offset OFS Buffer Linear Address Segment 16 Offset Page LinearAddress DIV 65536 nn address PageOffset LinearAddress MOD 65536 determine offset into the page In C segment FP_SEG amp Buffer get segment of buffer offs
93. ng this will not happen because of the way DOS is written But what about when using interrupts Then you could have a situation such as this in your program If DOS function X is being executed when an interrupt occurs and the interrupt routine makes a call to DOS function X then function X is essentially being called while it is already active Such a reentrancy attempt spells disaster because DOS functions are not written to support it This is a complex concept and you do not need to understand it Just make sure that you do not call any DOS functions from within your ISR The one wrinkle is that unfortunately it is not obvious which library routines included with your compiler use DOS functions A rule of thumb is that routines which write to the screen or check the status of or read the keyboard and any disk I O routines use DOS and should be avoided in your ISR The same problem of reentrancy exists for many floating point emulators as well meaning you may have to avoid floating point real math in your ISR Note that the problem of reentrancy exists no matter what programming language you are using Even if you are writing your ISR in assembly language DOS and many floating point emulators are not reentrant Of course there are ways around this problem such as those which involve checking to see if any DOS functions are currently active when your ISR is called but such solutions are well beyond the scope of this discussion The secon
94. ng the software included with your board make a backup copy of the disk You may make as many backups as you need C and Pascal Programs These programs are source code files so that you can easily develop your own custom software for your 1200 board In the C directory 1200 H and 1200 INC contain all the functions needed to implement the main C programs H defines the addresses and INC contains the routines called by the main programs In the Pascal directory 1200 PNC contains all of the procedures needed to implement the main Pascal programs Analog to Digital SOFTTRIG Demonstrates how to use the software trigger mode for acquiring data EXTTRIG Similar to SOFTTRIG except that an external trigger is used MULTI Shows how to fill an array with data using a software trigger Timer Counters TIMER A short program demonstrating how to program the 8254 for use as a timer Digital I O DIGITAL Simple program that shows how to read and write the digital I O lines Digital to Analog DAC Shows how to use the DACs Uses A D channel 1 to monitor the output of DAC1 WAVES A more complex program that shows how to use the 8254 timer and the DACs as a waveform generator Interrupts INTRPTS Shows the bare essentials required for using interrupts INTSTRM A complete program showing interrupt based streaming to disk DMA DMA Demonstrates how to use DMA to transfer acquired data to a memory buffer Buffer can be written to disk and viewed with
95. nges 5 10 volts Table 5 1 shows the ideal input voltage for each bit weight for the unipolar straight binary range and Table 5 2 shows the ideal voltage for each bit weight for the bipolar twos complement ranges Unipolar Calibration Two adjustments are made to calibrate the A D converter for the unipolar range of 0 to 10 volts One is the offset adjustment and the other is the full scale or gain adjustment Trimpot TR7 is used to make the offset adjustment and trimpot TR2 is used for gain adjustment This calibration procedure is performed with the board set up for a 0 to 10 volt input range Before making these adjustments make sure that the jumper on P3 is set for 10V and the jumpers on P4 and P11 are set for Use analog input channel 1 and set it for a gain of 1 while calibrating the board Connect your precision voltage source to channel 1 Set the voltage source to 1 22070 millivolts start a conversion and read the resulting data Adjust trimpot TR7 until it flickers between the values listed in the table at the top of the next page Next set the voltage to 9 49829 volts and repeat the procedure this time adjusting TR2 until the data flickers between the values in the table Note that the value used to adjust the full scale voltage is not the ideal full scale value for a 0 to 10 volt input range This value is used because it is the maximum value at which the A D converter is guaranteed to be linear and ensures accurate c
96. nly the other byte will be zero Note that the CE cannot be written into whenever a count is written it is written into the CR The Control Logic is also shown in the diagram CLK n GATE n and OUT n are all connected to the out side world through the Control Logic 82C54 SYSTEM INTERFACE The 82C54 is treated by the systems software as an array of peripheral I O ports three are counters and the fourth is a control register for MODE program ming Basically the select inputs Ag A connect to the Ap A4 address bus signals of the CPU The CS can be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder such as an Intel 8205 for larger sys tems COUNTER COUNTER o 2 SS i es AAA A AA OUT GATE CLK OUT GATE CLK OUT GATE CLK COUNTER 1 231244 7 Figure 6 82C54 System Interface OPERATIONAL DESCRIPTION General After power up the state of the 82C54 is undefined The Mode count value and output of all Counters are undefined How each Counter operates is determined when it is programmed Each Counter must be programmed before it can be used Unused counters need not be programmed Control Word Format Aj Ap 11 CS 0 RD 1 Programming the 82C54 Counters are programmed by writing a Control Word and then an initial count The control word format is shown in Figure 7 All Control Words are written into the Control Word Register whi
97. nt so for an initial count of N OUT does not strobe low until N 1 CLK pulses after a trigger A trigger results in the Counter being loaded with the initial count on the next CLK pulse The counting sequence is retriggerable OUT will not strobe low for N 1 CLK pulses after any trigger GATE has no effect on OUT If a new count is written during counting the current counting sequence will not be affected If a trigger occurs after the new count is written but before the current count expires the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there CWs A LSB 3 Ine lebalalst lstelels CW 1A LSB 3 MUY CWziA L5B 3 LSR e 5 Pele tw telat sists leralel eis 231244 13 Figure 20 Mode 5 3 94 82C54 Signal Low Status Or Going Rising Modes Low Disables Enables counting counting 1 Initiates counting 2 Resets output after next clock 1 Disables counting 2 Sets output immediately high 1 Disables Enables counting Initiates counting counting Initiates Enables 2 Sets output counting counting immediately high Disables Enables counting counting Initiates counting Figure 21 Gate Pin Operations Summary NOTE 0 is equivalent to 216 for binary counting and 104 for BCD counting Figure 22 Minimum and Maximum initial Counts Operation Common to All Modes Programming
98. nt and status latched for Counter 0 Command ignored status already latched for Counter 1 Figure 13 Read Back Command Example 82054 los Ab walala Lo o o 0 writeinto Countero io 110lol1 Write into Counter 1 Lo o 1 o wrtitoCouterz Lo 1 o 1 4 write contro word Lo o t o 0 ReadtromCountero 0 o o 1 ReadtromGounter1 olol J lJlo Read from Counter 2 Lo o 1 1 No Operation 3 State o 1 1 x x No Operation 3 State Figure 14 Read Write Operations Summary Mode Definitions The following are defined for use in describing the operation of the 82054 CLK PULSE a rising edge then a falling edge in that order of a Counter s CLK input TRIGGER a rising edge of a Counter s GATE in put COUNTER LOADING the transfer of a count from the CR to the CE refer to the Functional Descrip tion MODE 0 INTERRUPT ON TERMINAL COUNT Mode 0 is typically used for event counting After the Control Word is written OUT is initially low and will remain low until the Counter reaches zero OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Coun ter GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After the Control Word and initial count are written to a Counter the initial count will be loaded on the ne
99. o lt lt Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera fional sections of this specification is not implied Ex posure to absolute maximum rating conditions for extended periods may affect device reliability Units Test Conditions puo tod c v V lou 2 5 mA lou 2 5 mA loH 100 pA pA Vin Voc to OV Note 1 Ports A B C Rext 5000 Note 4 mA es a Port A only Ports A B C pA Voc 5 5V Vin Voc or GND Port Conditions If I P Open High O P Open Only With Data Bus High Low CS High Reset Low Pure Inputs Low High intel 82C55A CAPACITANCE TA 25 C Vcc GND OV _ symbol Parameter Min Max Units Test Conditions Input Capacitance 10 pF Unmeasured pins fe 1 MHz NOTE 5 Sampled not 100 tested A C CHARACTERISTICS Ta 0 to 70 C Voc 5V 10 GND OV Ta 40 C to 85 C for Extended Temperature BUS PARAMETERS READ CYCLE Test A gt AA era on Kissel o Te a wa Rbuewam 5 m wo Da Day nom ws w Cue ROT woetaroaing Io 5 w wy Recovery Tmo beween FORE zo ns WRIT
100. of 10 hex is written to the counter 4 LSB stands for Least Significant Byte of count 5 Numbers below diagrams are count values The lower number is the least significant byte The upper number is the most significant byte Since the counter is programmed to Read Write LSB only the most significant byte cannot be read N stands for an undefined count Vertical lines show transitions between count values Figure 15 Mode 0 intel 82054 MODE 1 HARDWARE RETRIGGERABLE ONE SHOT OUT will be initially high OUT will go low on the CLK pulse following a trigger to begin the one shot pulse and will remain low until the Counter reaches zero QUT will then go high and remain high until the CLK pulse after the next trigger After writing the Control Word and initial count the Counter is armed A trigger results in loading the Counter and setting OUT low on the next CLK pulse thus starting the one shot pulse An initial count of N will result in a one shot pulse N CLK cycles in dura tion The one shot is retriggerable hence OUT will remain low for N CLK pulses after any trigger The one shot pulse can be repeated without rewriting the same count into the counter GATE has no effect on OUT If a new count is written to the Counter during a one shot pulse the current one shot is not affected un less the Counter is retriggered in that case the Counter is loaded with the new count and the one
101. or on board 8 MHz clock Counter outputs eree eee eee Available externally used as PC interrupts Counter gate SOUICe essere esse essere nennen External gate or always enabled Miscellaneous Inputs Outputs PC bus sourced 5 volts 12 volts ground Current Requirements 140 mA 5 volts 32 mA 12 volts 30 mA 9 12 volts Connector 50 pin right angle shrouded header Size Short slot 3 875 H x 5 25 W 99mm x 134mm A 4 APPENDIX B P2 CONNECTOR PIN ASSIGNMENTS B 2 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AOUT1 AOUT2 ANALOG GND PA7 PAG PAS PA4 PA3 PA2 PA1 PAO TRIGGER IN EXT GATE 1 TRIGGER OUT EXT CLK 12 VOLTS 12 VOLTS Goo QOOOOGO OOGOOO AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN16 ANALOG GND ANALOG GND ANALOG GND PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO DIGITAL GND T C OUT 1 T C OUT 2 EXT GATE 2 5 VOLTS DIGITAL GND P2 Connector B 3 B 4 APPENDIX C COMPONENT DATA SHEETS Intel 82C54 Programmable Interval Timer Data Sheet Reprint intel 82054 CHMOS PROGRAMMABLE INTERVAL TIMER m Compatible with all Intel and most m Three independent 16 bit counters other microprocessors B Low Power CHMOS B High Speed Zero Wait State Icc 10 mA e 8 MHz Count Operation with 8 MHz 8086 88 and frequency 80186 1688 Compl
102. oss the pins labeled EOC and place third jumper across the pins labeled G Make certain that there are no other jumpers on this connector Also make sure that the IRQ channel you have selected is not used by any other device in your system Figure D 3 shows you how to configure P8 for IRQ channel 3 P8 OT2 ET EOC DMA IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 G Fig D 3 Interrupts and Interrupt Channel Jumpers P8 D 4 Running ADAINST After the jumpers and switch are set and the 1200 board is installed in the computer you are ready to configure SIGNAL MATH so that it is compatible with your board s settings This is done by running the ADAINST driver installation program After running the program open ADA1200 EXE from the Open a File menu You will see a screen similar to the screen shown in Figure D 4 below The factory default settings are shown in the illustration Your settings may or may not match the default settings depending on whether you have made changes to these settings before Base Address The board s base address setting is entered in the upper right block as shown in the diagram The factory setting for all Real Time Devices boards is 300 hex 768 decimal The base address can be entered as a decimal or hexadecimal value hex values must be preceded by a dollar sign for example 300 Refer to your board s manual if you need help in determining the correct value to enter EOC IT End of Convert Interrupt
103. pA CLK Freq DC CS Voc All Inputs Data Bus Voc All Outputs Floating IccsB1 Vcc Supply Current Standby pA CLK Freq DC CS Voc All Other Inputs 1 O Pins Van Outputs Open Ow Input Capacitance 10 fe 1MHz Cyo VOCapctane DD 20 pr Output Capacitance p 7 29 2 AR ORE A C CHARACTERISTICS TA 0 C to 70 C Voc 5V 10 GND 0V TA 40 C to 85 C for Extended Temperature BUS PARAMETERS Note 1 READ CYCLE Parameter eme rmm a in es Sane Bore RB e jos es e sabi potore d of pa Jm ess Hold Time at ROT 9 gt 9 ms tee puse matas ej ms tap Data Delay tom BL a Luo Data Delay trom Adaress 220 tor FOT toDataFioating 5 9 s es m tev Commana Recovery Time 20 NOTE 1 AC timings measured at Voy 2 0V Vo 0 8V 3 96 intel 82054 A C CHARACTERISTICS Continued WRITE CYCLE Parameter Parameter 82cs4 e2cs42 tcLK Clock Period 125 DC 100 High Pulse Width 30 3 Low Pulse Width 50 3 Clock Rise Time Clock Fall Time ate Width High ate Width Low ate Setup Time to CLK T Gate Hold Time After CLK T Output Delay from CLK J utput Delay from Gate LK Delay for Loading 4 ate Delay for Sampling 4 UT Delay from Mode Write CLK Set Up for Count Latch O tpwL T if l W o o m 50 2 ii O O Q teL NOTES 2 in Modes
104. patible into a high speed high performance data acquisition and control system Installed within a single expansion slot in the computer each 1200 series board features 16 single ended analog input channels 12 bit 5 microsecond analog to digital converter with 125 kHz throughput 5 10 or 0 to 10 volt input range Resistor configurable gain Three conversion modes DMA transfer Trigger in and trigger out for external triggering or cascading boards 16 TTL CMOS 8255 based digital I O lines which can be configured with pull up or pull down resistors Three 16 bit timer counters two cascaded for pacer clock Two 12 bit digital to analog output channels with dedicated grounds ADA1200 only 5 10 0 to 5 or 0 to 10 volt analog output range ADA1200 only Turbo Pascal Turbo C and BASIC source code diagnostics program The following paragraphs briefly describe the major functions of the board A more detailed discussion of board functions is included in Chapter 3 Hardware Operation and Chapter 4 Board Operation and Programming The board setup is described in Chapter 1 Board Settings Analog to Digital Conversion The analog to digital A D circuitry receives up to 16 single ended analog inputs and converts these inputs into 12 bit digital data words which can then be read and or transferred to PC memory The analog input voltage range is jumper selectable for bipolar ranges of 5 to 5 volts or 10 to 10 volts or
105. peration of Figure 17a MODE 1 Status Word Format Port C is executed to perform this function D7 AAE 1 _ GROUP A GROUP B Defined By Mode 0 or Mode 1 Selection Figure 17b MODE 2 Status Word Format interrupt Enable Flag Alternate Port C Pin Signal Mode INTE B ACKg Output Mode 1 or STBg input Mode 1 INTE A2 STBA Input Mode 1 or Mode 2 Peces INTE A1 ACK Output Mode 1 or Mode 2 Figure 18 Interrupt Enable Flags in Modes 1 and 2 3 140 intel 82C55A ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 C to 70 C Storage Temperature 65 C to 150 C Supply Voltage 0 5 to 8 0V Operating Voltage 4V to 7V Voltage on any Input GND 2V to 6 5V Voltage on any Output GND 0 5V to Voc 0 5V Power Dissipation o oo 1 Watt D C CHARACTERISTICS Symbol Parameter va Vit Input Low Voltage Input High Voltage Output Low Voltage a Port Hold High Leakage Current Port Hold Low Overdrive Current iho Port Hold High Overdrive Current 3 Voc Supply Current IccsB Voc Supply Current Standby NOTES E 1 Pins Ay Ao CS WR RD Reset D o gt Data Bus Ports B C oo 3 Outputs open 4 Limit output current to 4 0 mA 3 141 VoH Output High Voltage a Voc 0 4 lor Output Float Leakage Current 10 pA Vin Voc to OV Note 2
106. put Lets you use simple input and output operation for a port Data is written to or read from the specified port Mode 1 Strobed input output Lets you transfer I O data from Port A in conjunction with strobes or hand shaking signals Mode 2 Strobed bidirectional input output Lets you communicate bidirectionally with an external device through Port A Handshaking is similar to Mode 1 These modes are detailed in the 8255 Data Sheet reprinted from Intel in Appendix C Interrupts The 1200 has four jumper selectable interrupt sources end of convert DMA done the external trigger and the output of timer counter 2 The end of convert signal can be used to interrupt the computer when an A D conversion is completed The DMA done is used in the DMA mode to generate an interrupt whenever a DMA transfer is completed The external trigger at the I O connector can be used to generate an interrupt whenever the trigger line changes states from low to high Or the output of timer counter 2 can generate an interrupt whenever the count reaches 0 Chapter 1 tells you how to set the jumpers on the interrupt header connector P7 and Chapter 4 describes how to program interrupts 3 5 CHAPTER 4 BOARD OPERATION AND PROGRAMMING This chapter shows you how to program and use your 1200 board It provides a complete description of the I O map a detailed description of programming operations and operating modes and flow diagra
107. r Clock Block Diagram Divider 1 Divider 2 Pacer Clock decimal hex decimal hex 125 kHz 2 0002 32 0020 100 kHz 2 0002 40 0028 50 kHz 2 0002 80 0050 zu 40070180 210002 0007 oF 100 Hz 2 0002 40000 9C40 Interrupts What Is an Interrupt An interrupt is an event that causes the processor in your computer to temporarily halt its current process and execute another routine Upon completion of the new routine control is returned to the original routine at the point where its execution was interrupted Interrupts are very handy for dealing with asynchronous events events that occur at less than regular intervals Keyboard activity is a good example your computer cannot predict when you might press a key and it would be a waste of processor time for it to do nothing while waiting for a keystroke to occur Thus the interrupt scheme is used and the processor proceeds with other tasks Then when a keystroke does occur the keyboard interrupts the processor and the processor gets the keyboard data places it in memory and then returns to what it was doing before it was interrupted Other common devices that use interrupts are modems disk drives and mice 4 15 Your 1200 board can interrupt the processor when a variety of conditions are met By using these interrupts you can write software that effectively deals with real world events Interrupt Request Lines To allow different periph
108. r Port C Lower and PCH is for Port C Upper Figure 1 15 shows these pads To operate as pull ups solder a jumper wire between the common pin middle pin of the three and the V pin For pull downs solder a jumper wire between the common pin middle pin and the G pin Figure 1 16 shows Port A lines with pull ups Port C Lower with pull downs and Port C Upper with no resistors 1 10 SR nro B d ol oslo o 9 O AD678 of jo So 0 fo o El of jojo a ua of logo o _jo o cb ope 2000000090004 0000 1 NN IM Jon D me a 505865000550 6000 Ern EEE were DO D um CR 0000000 30000000 4800000000000 Lo 58000000 2000000000000 9005000000 Real Time Devices inc Stam College PA 16804 USA Fig 1 15 Pull up Pull down Resistor Circuitry 1 11 PORT A PAO 7 PORT C LOWER PAO 3 Fig 1 16 Adding Pull ups and Pull downs to Digital 1 0 Lines Resistor Configurable Gain The1200 has resitor configurable gain to customize the gain setting for a specific application Note that when you use this feature and set up the board for a gain of other than 1 all of the 16 input channels will operate only at your custom gain setting The resistor configurable gain is derived by adding resistors R1 and R2 trimpot TR4 and capacitor C36 all located in the upper center and right areas of the board The resistors and trimpot combine to set the gain as shown in the for
109. r system is already using your selected DMA channel channel contention will result causing erratic operation DRO1 DRQ3 P5 Fig 1 4 DMA Request Channel Jumper P5 P6 DMA Acknowledge Channel Factory Setting Disabled This header connector shown in Figure 1 5 lets you select channel 1 or 3 for DMA transfers This line the DMA acknowledge line DACK must be set to the same channel as the DRQ line on P5 The factory setting is DMA disabled jumper in a stored position Note that if any other device in your system is already using your selected DMA channel channel contention will result causing erratic operation 1 4 DACK1 DACK3 P6 Fig 1 5 DMA Acknowledge Channel Jumper P6 P7 8254 Timer Counter Clock Sources Factory Settings CLK1 XTAL CLK2 OTI PCK This header connector shown in Figure 1 6 lets you select the clock sources for the 8254 timer counters TCO TC1 and TC2 TCO and TC are cascaded to form the pacer clock You must install two or three jumpers in order to properly use the timer counter features including the pacer clock Figure 1 7 shows a block diagram of the timer counter circuitry to help you in making these connections The clock source for TCO and TC1 is selected by placing a jumper on XTAL or EC1 on CLK1 the two pairs of pins at the top of the header XTAL is the on board 8 MHz clock and EC1 is an external clock source you connect through the external I O connector P2 45
110. rupt Source and Channel Factory Setting Jumpers on OT2 amp G Interrupt Channels Disabled This header connector shown in Figure 1 8 lets you connect any one of four interrupt sources to any of six interrupt channels IRQ2 highest priority channel through IRQ7 lowest priority channel To activate a channel you must install a jumper vertically across the desired IRQ channel Figure 1 8a shows the factory setting Figure 1 8b shows interrupt source OT2 connected to IRQ3 P8 P8 OT2 OT2 ET l ET EOC i EOC DMA DMA Fig 1 8a Fig 1 8b Interrupt Source Factory Setting IRQ7 OT2 Connected to IRQ3 IRQ7 IRQ6 IRQ6 ROS IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 G G Fig 1 8 Interrupt Channel Jumper P8 On the right side of the header you can select any one of four signal sources to generate an interrupt An interrupt source is chosen by placing a jumper across the desired pair of pins The interrupt sources available are the A D end of convert EOC DMA done DMA external trigger ET and the output of timer counter 2 OT2 1 6 When jumpered the bottom pair of pins on P8 labeled G connects a 1 kilohm pull down resistor to the output of a high impedance tri state driver which carries the interrupt request signal This pull down resistor drives the interrupt request line low whenever interrupts are not active Whenever an interrupt request is made the tri state buffer is enabled forcing the output high and generating an interrup
111. s sible in this Mode 231256 8 231256 9 i intel 82C55A MODE 0 Port Definition DE wa ir PORT C PORTC De o o o Pome porto rome ponte o o o o oureur ourur o output output o o o ourur ourur 1 output o o o ourur oureur 2 input OUTPUT o o 1 1 ourur ourur a meur meur Lo o o ourur meur 4 output Lo o t ourur mer s oureur Lo a 1 o oureur wur e meurt OUTPUT o 1 1 1 oureur wur 7 INPUT eur 1 o o o meu oureur s output 1 o po 1 mur ourur e output L3 o 1 o meur ourur 10 Pur outpuT L3 o 1 s wer ouru s INPUT wer L3 o o meu we 2 oureur pa s o s mer meur 13 oureur aif af 1 o input meu 4 L3 oco 4 weu eur s MODE 0 Configurations CONTROL WORD 0 CONTROL WORD 2 D Os Ds 0 D O D Do D D Ds O Dz D D D CONTROL WORD 1 CONTROL WORD 3 D D D D D D D D De Ds D D Do Da 0 D rare 231256 10 3 131 MODE 0 Configurations Continued CONTROL WORD 4 De De EERE Ba Da D B CONTROL WORD 96 a 0 OQ D D Dy D D CONTROL WORD 6 D De Ds D D D D Do CONTROL WORD 87 O Dj D O D D D Da CONTROL WORD 46 D D D D Dy O D D CONTROL WORD 9 D Dg Ds D D 0 D Dy CONT
112. s D D D D D DD Ko MODE 2 AND MODE 1 OUTPUT CONTROL WORD D De Ds D 0 D D Op DON Te RX 82C55A MODE 2 AND MODE 0 OUTPUT CONTROL WORD D De Ds D 0 D D D LU DD e Te me Cao 1 INPUT MODE 2 AND MODE 1 INPUT CONTROL WORD Dj De Ds D Dy O D Do Mi bpd DS 231256 21 Figure 16 MODE Y Combinations 3 138 82C55A Mode Definition Summary Special Mode Combination Considerations There are several combinations of modes possible For any combination some or all of the Port C lines are used for control or status The remaining bits are either inputs or outputs as defined by a Set Mode command During a read of Port C the state of all the Port C lines except the ACK and STB lines will be placed on the data bus In place of the ACK and STB line States flag status will appear on the data bus in the PC2 PC4 and PC6 bit positions as illustrated by Figure 18 Through a Write Port C command only the Port C pins programmed as outputs in a Mode 0 group can be written No other pins can be affected by a Write Port C command nor can the interrupt enable flags be accessed To write to any Port C output pro grammed as an output in a Mode 1 group or to MODE 0 OR MODE 1 ONLY change an interrupt enable flag the Set Reset Port C Bit command must be used With a Set Reset Port C Bit command any Port C line Programmed as an output includin
113. s issued lets you take the next reading from a different channel at a different gain Program 8255 PPI Port B out Clear Registers Reset Select Channel End of Convert EOC 1 Read LSB Read MSB Stop Program Fig 4 4 Single Conversion Flow Diagram Change Channel Yes 4 29 DMA Flow Diagram Figure 4 5 This flow diagram shows you how to take samples and transfer the data directly into the computer s memory You can use DMA channel 1 or 3 to transfer data to the computer s memory The pacer clock can be used to set the sampling interval Program 8255 PPI Port B out Clear Registers Reset Program 8254 TCO 8 TC1 for desired transfer rates Select Channel Program DMA Controller Enable DMA 8 External Trigger DMA Done 1 v Yes Stop Program Fig 4 5 DMA Flow Diagram 4 30 Interrupts Flow Diagram Figure 4 6 This flow diagram shows you how to program an interrupt routine for your 1200 The diagram parallels the interrupts discussion included earlier in this chapter You can use this diagram in conjunction with the detailed text in this chapter to develop an interrupt program for your 1200 Clear Board Save startup IMR value Select IRQ source Save startup interrupt vector Clear IRQ bit in IMR Set IRQ bit in IMR Body of user program Vector new Restore startup interrupt vector Restore startup MR value Stop Program
114. s shown in the address decode table in the pin descriptions Figure 6 shows the control word format for both Read and Write operations When the control word is read bit D7 will always be a logic 1 as this implies control word mode information Ports A B and C The 82C55A contains three 8 bit ports A B and C All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 82C55A Port A One 8 bit data output latch buffer and one 8 bit input latch buffer Both pull up and pull down bus hold devices are present on Port A Port B One 8 bit data input output latch buffer Only pull up bus hold devices are present on Port B Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B Only pull up bus hold devices are present on Port C See Figure 4 for the bus hold circuit configuration for Port A B and C intel 82C55A BIDIRECTIONAL DATA BUS INTERNAL DATA NOTE WR 231256 4 Port pins loaded with more than 20 pF capacitance may not have their logic level guaran teed following a hardware r
115. s to be pulled up or pulled down This procedure is explained near the end of this chapter Also note that by installing components at R1 R2 TR4 and C36 you can add your own resistor configurable gain The gain circuitry is described at the end of this chapter 1 1 Fa bo ex av 1 2 P3 Analog Input Voltage Range Factory Setting 10 Volts This header connector shown in Figure 1 2 sets the analog input voltage range for 10 or 20 volts Note that if the jumper is installed on 20V then P4 can only be set for bipolar The input ranges allowed by the 1200 are 5 10 and 0 to 10 volts P3 33 N r Fig 1 2 Analog Input Voltage Range Jumper P3 P4 Analog Input Voltage Polarity Factory Setting This header connector shown in Figure 1 3 sets the analog input voltage polarity for unipolar or bipolar Note that if the jumper on P3 is installed on 20V then P4 can only be set for bipolar The input ranges allowed by the 1200 are 5 10 and 0 to 10 volts P4 Fig 1 3 Analog Input Voltage Polarity Jumper P4 PS DMA Request Channel Factory Setting Disabled This header connector shown in Figure 1 4 lets you select channel 1 or 3 for DMA transfers This line the DMA request line DRQ must be set to the same channel as the DACK line on P6 The factory setting is DMA disabled jumper in a stored position Note that if any other device in you
116. t You can monitor the interrupt status through bit 2 in the status word I O address location BA 0 After the interrupt has been serviced the reset command returns the IRQ line low disabling the tri state buffer and pulling the output low again Figure 1 9 shows this circuit Because the interrupt request line is driven low only by the pull down resistor you can have two or more boards which share the same IRQ channel You can tell which board issued the interrupt request by monitoring each board s IRQ status bit NOTE When you use multiple boards that share the same interrupt only one board should have the G jumper installed The rest should be disconnected Whenever you operate a single board the G jumper should be installed INT SOURCE IRQ STATUS INTERRUPT REGISTER INTERRUPT CLR Fig 1 9 Pulling Down the Interrupt Request Line P9 DAC 1 Output Voltage Range Factory Setting 5 to 5 volts This header connector shown in Figure 1 10 sets the output voltage range for DAC 1 at 0 to 5 5 0 to 10 or 10 volts Two jumpers must be installed one to select the range and one to select the multiplier The two rightmost jumpers select the range bipolar 5 or unipolar 5 The two leftmost jumpers select the multiplier X2 or X1 When a jumper is on the X2 multiplier pins the range values become 10 and 10 The table below shows the four possible combinations of jumper settings and the diagram shows the factor
117. t Reset l Bit Set Reset Function Bit 0 set bit to 0 0 active Bit Select 1 set bit to 1 000 PCO 001 PC1 010 PC2 011 PC3 100 PC4 101 PC5 110 PC6 111 PC7 4 6 For example if you want to set Port C bit 0 to 1 you would set up the control word so that bit 7 is 0 bits 1 2 and 3 are 0 this selects PCO and bit 0 is 1 this sets PCO to 1 The control word is set up like this 0 x X X 0 0 0 1 Sets PCO to 1 written to BA 7 X don t care Set Reset i Function Bit Set PCO Bit Select 000 PCO BA 8 8254 Timer Counter 0 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded This counter is cascaded with TC1 to form the 32 bit on board pacer clock BA 9 8254 Timer Counter 1 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded This counter is cascaded with TCO to form the 32 bit on board pacer clock BA 10 8254 Timer Counter 2 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded This counter can be cascaded to TCO and TC1 or it can be used independently BA 11 8254 Control Word Write Only Accesses the 8254 control register to directly control the three timer counters BCD Binary 0 binary
118. t is clear 0 When DMA is complete the bit is set 1 The second way to check is to use the DMA done signal to generate an interrupt An interrupt can immediately notify your program that DMA is done and any actions can be taken as needed Both methods are demonstrated in the sample C and Pascal programs the polling method in the program named DMA and the interrupt method in DMASTRM y 4 23 Common DMA Problems Make sure that your buffer is large enough to hold all of the data you program the DMA controller to transfer Check to be sure that your buffer does not straddle a page boundary Remember that the number of bytes for the DMA controller to transfer is equal to twice the number of samples This is because each sample is two bytes in size If you terminate sampling before the DMA controller has transferred the number of bytes it was programmed for be sure to disable DMA by setting the mask bit in the single mask register Make sure that the board is not running too fast for DMA transfers D A Conversions ADA 1200 Only The two D A converters can be individually programmed to convert 12 bit digital words into a voltage in the range of 5 10 0 to 5 or 0 to 10 volts DACI is programmed by writing the 12 bit digital data word to BA 8 DAC is identical with the data word written to BA 10 The following tables list the key digital codes and corresponding output voltages for the D A converters a IE ee
119. t your board s application Application Software and Drivers Our custom application software packages provide excellent data acquisition and analysis support Use SIGNAL MATH for integrated data acquisition and sophisticated digital signal processing and analysis or ATLANTIS for real time monitoring and data acquisition rtdLinx and rtdLinx labLinx drivers provide full featured high level interfaces between the 1200 and custom or third party software including LABTECH NOTEBOOK NOTEBOOK XE and LT CONTROL rtdLinx source code is available for a one time fee Our Pascal and C Programmer s Toolkit provides routines with documented source code for custom programming Hardware Accessories Hardware accessories for the 1200 include the MX32 analog input expansion board which can expand a single input channel on your 1200 to 16 differential or 32 single ended input channels MR series mechanical relay output boards OP series optoisolated digital input boards the TS16 temperature sensor board the TB50 terminal board and XB50 prototype terminal board for easy signal access and prototype development the EX XT and EX AT extender boards for simplified testing and debugging of prototype circuitry and XP50 twisted pair wire flat ribbon cable assembly for external interfacing Using This Manual This manual is intended to help you install your new board and get it running quickly while also providing enough detail about the board and its functions so that
120. tains three 16 bit 8 MHz timer counters to support a wide range of timing and counting functions Two of the timer counters are cascaded and can be used internally for the pacer clock The third is available for counting applications or it can be cascaded to the other two timer counters i 3 Digital VO The 1200 has 16 TTL CMOS compatible digital I O lines which can be directly interfaced with external devices or signals to sense switch closures trigger digital events or activate solid state relays These lines are provided by the on board 8255 programmable peripheral interface chip Pads for installing and activating pull up or pull down resistors are included on the board Installation procedures are given near the end of Chapter 1 Board Settings What Comes With Your Board You receive the following items in your 1200 package AD1200 or ADA 1200 interface board Software and diagnostics diskette with Turbo Pascal Turbo C and BASIC source code User s manual If any item is missing or damaged please call Real Time Devices Customer Service Department at 814 234 8087 If you require service outside the U S contact your local distributor Board Accessories In addition to the items included in your 1200 package Real Time Devices offers a full line of software and hardware accessories Call your local distributor or our main office for more information about these accessories and for help in choosing the best items to suppor
121. ter reloads itself with the initial count and continues counting from there 3 95 intel 82054 ABSOLUTE MAXIMUM RATINGS Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam Ambient Temperature Under Bias 0 C to 70 C age to the device This is a stress rating only and Storage Temperature 65 to 150 C functional operation of the device at these or any Supply Voltage 0 5to 8 0V other conditions above those indicated in the opera Operating Voltage 4Vto 7V tional sections of this specification is not implied Ex Voltage on any Input GND 2Vto 6 5V posure to absolute maximum rating conditions for Voltage on any Output GND 0 5Vto Vcc 0 5V extended periods may affect device reliability Power Dissipation 1 Watt D C CHARACTERISTICS Ta 0 C to 70 C Voc 5Vt 10 GND 0V Ta 40 C to 85 C for Extended Temperature Max Test Conditions vi Input Low Voltage 08 OMNCM CC UMP lo 2 5 mA Min Units 05 v input High Votags 20 Vop os V PEM EA Vit V Y Output Low Voltage V Von V lon 25mA V Ion 100 pA Input Load Current 20 Vin Vcc to OV Output Float Leakage Current 10 pA Vour Voc to 0 0V a Voc Supply Current mA S 8MHz 82054 IccsB Vcc Supply Current Standby
122. ternal trigger and DMA enable Port B is programmed at I O address location BA 5 Analog Input IRQ Enable Channel Select IRQ disabled 0000 channel 1 1000 channel 9 1 IRQ enabled 0001 channel 2 1001 channel 10 0010 channel 3 1010 channel 11 External Trigger Enable 0011 lt channel 4 1011 channel 12 0 Disabled 0100 channel5 1100 channel 13 1 Enabled 0101 Channel 6 1101 channel 14 0110 channel 7 1110 channel 15 0111 channel 8 1111 channel 16 To use Port B for these control functions the 8255 must be initialized so that Port B is set up as a Mode 0 output port This is done by writing this data to the PPI control word at I O address BA 7 X don t care 1 X X X X 0 0 X o os os oa os o2 01 oo Clearing the Board It is good practice to start your program by resetting the 1200 board You can do this by writing to the RESET port located at BA 2 The actual value you write to this port is irrelevant After resetting the board following power up it is a good idea to take an A D reading and throw it away to make sure the converter is initialized and contains no unwanted data Selecting a Channel To select a conversion channel you must assign values to bits O through 3 in the PPI Port B port at BA 5 The table below shows you how to determine the bit settings Lx fx fx x Len los anl en es Channe CH3 CH2 cH CHO Channel cus CH2 1 BERN ZENTREN
123. the 82C55A is programmed by the system software so that normally no external logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to inter face the 82C55A to the system data bus Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words It accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Control Groups Group A and Group B Controls The functional configuration of each port is pro grammed by the systems software In essence the CPU outputs a control word to the 82C55A The control word contains information such as mode bit set bit reset etc that initializes the func tional configuration of the 820554 nn we am ee Each of the Control blocks Group A and Group B accepts commands from the Read Write Control Logic receives control words from the internal data bus and issues the proper commands to its as sociated ports Control Group A Port A and Port C upper C7 C4 Control Group B Port B and Port C lower C3 CO The control word register can be both written and read a
124. the included VIEWDAT program DMASTRM Demonstrates how to use DMA for disk streaming Very high continuous acquisition rates can be obtained BASIC Programs These programs are source code files so that you can easily develop your own custom software for your 1200 board Analog to Digital SINGLE Demonstrates how to use the single convert internal trigger mode for acquiring data EXTTRIG Demonstrates how to use the external trigger to acquire data SCAN Demonstrates how to scan channels to acquire data 4 27 Timer Counters TIMER Digital VO DIGITAL Digital to Analog DASCAN DMA DMA A short program demonstrating how to program the 8254 for use as a timer Simple program that shows how to read and write the digital I O lines Demonstrates D A conversion Shows how to take samples and transfer them to PC memory using DMA 4 28 Flow Diagrams The following paragraphs provide descriptions and flow diagrams for some of the 1200 s A D and D A conver sion functions These diagrams will help you to build your own custom applications programs Single Convert Flow Diagram Figure 4 4 This flow diagram shows you the steps for taking a single sample on a selected channel A sample is taken each time you send the Start Convert command All of the samples will be taken on the same channel until you change the value in the PPI Port B register BA 5 Changing this value before each Start Convert command i
125. tor Jumper P12 0 ccccsscssssscsssecescssssssssasececececssesecesseeseece 1 9 LERNER 1 9 Pull up Pull down Resistor Circuitry nen eneenenenenen eenen enteneneenenenveneneenenensenenen 1 11 Adding Pull ups and Pull downs to Digital YO Lines sss essen 1 12 Gain Circuitry and Formulas for Calculating Gain and f sss 1 13 Diagram for Removal of Solder Short sss eenn 1 14 P2 I O Connector Pin Assignments a rsenenenonenevensenenenenensensnensaenenenevereanenensseorseesenensns 2 3 Analog Input Connections a nein 2 4 Cascading Two Boards for Simultaneous Sampling s essessssessesssseessesesesssecssssssssssscsnseessesusessaceseee 2 6 AD1200 ADA1200 Block Diagram ca ssssoisssnssassvevsssassdensaossssasedvensauilscaitesostscastduteste iesssessisenbsoseresacden eves 3 3 8254 Timer Counter Circuit Block Diagram eese esen 3 4 A D Conversion Timing Diagram All Modes sse 4 12 Pacer Clock Block Diagram las 4 15 8254 Timer Counter Circuit Block Diagram ssscssesssssssessesessssssssssessessssessssssscsnsssscsussesuesessesussecses 4 25 Single Conversion Flow Diagram essen 4 29 DMA Flow Diagram O O aen EEE 4 30 Interrupts Flow Diagram nn near 4 31 D A Conversion Flow Diagram ADA1200 Only sss sss 4 32 Board BST M e ai i a 5 3 INTRODUCTION The AD1200 and ADA1200 Advanced Industrial Control boards turn your IBM PC XT AT or com
126. ts Figure E 1 shows the board layout BASE ADDRESS 51 Kr q EE doo fcc ORR oT ere 0 me D AD678 E o 00000000000000q opu 9 000000000000 3 0000 8E Ay re corp anil PST ep Ca of TEE 398 EK S V80S IH 00000000 amp D C B 00000000 5050000000000 9 0000 AD1200 ADA1200 Q DOD de FEE Nees EI Ei PATA ACOUISITION gt CONTROL SYSTEM s 0000 600000 ji une oe 7AHCTS74 Q D 74HCT74 D 74HCT74 0000000000 70000000 oo 3000000000000 88 10000000 ES D74HcTo4 e 0900909009000009 x ca ue 000000000000 0006000000 peat 1 C106 a eres gt ar ur 29 89 00000000004 6000000000 4000000 f Ee 0000000000 0000000000 0000000000 x main cu OD dio Ps Real Time Devices Inc State College PA 16804 USA a 000000 Fig E 1 1200 Board Layout S1 Base Address ATLANTIS assumes that the base address of your 1200 is the factory setting of 300 hex see Chapter 1 If you changed this setting you must run the ATINST program and reset the base address NOTE The ATINST program requires the base address to be entered in decimal notation P7 8254 Timer Counter I O Configuration The 8254 must be configured with the three jumpers placed between the pins as shown in Figure E 2 This configuration is the same as the factory setting After setting the jumpers verify that each is in the proper location Any remaining jumpers must be removed from the P7 header connector E 3 X
127. ucenssecsuesecsnsssssssssesecsusasesussvesues COCOS a Starting an A D Conversion A dida Monitoring Conversion Status DMA Done or End of Convert annae Reading the Converted Data mica nn iii What Is an Iner T ss II II A ee teder 4 15 Interrupt Request Lines inneren 4 16 What Exactly Happens When an Interrupt Occurs erssesssssasssesnsnssnennenennensennnnsnnenennnnnnnnnnnnnenenennennennnnansennen 4 16 Using Interrupts in Your Programs sscsscsssssssssessesoesesscsscssesscsssssssconssessssvecessssnscusnseussesacsecsssucaesarsscaesesenee 4 16 Saving the Startup Interrupt Mask Register IMR and Interrupt Vector eene 4 18 Restoring the Startup IMR and Interrupt Vector cssssssssssssesessessssssscsssesececsececsectecsesesscseracsessesersesecerees 4 18 Common Interrupt Mistakes divida 4 19 Data Transfers Using DMA scssssssscscscscssessccssssnssesesssssessescssssssssssssesunscsesecenenesesscesscsesessassesssacatseszecesacasaseveees 4 19 Monitoring for DMA Done sy sa csc c cstccsessesceiscnccscsnsnsassicosssessedasoonchsosscondeseeodecctastsnsuaviese oss ossavsesiess sceuctscceebentes 4 23 Common DMA Problems MM een ine ee 4 24 D A Conversions ADA1200 Only csscsssscscsssssssssscsccssssssescsescsssssesssessssssatsssccsnsesesesescacceseeeasataceeasacecseeteres 4 24 Timer Countels essa ro 2 Eos acid 4 25 Digital ore EE 4 26 Example Programs and Flow Diagrams 200
128. unter 2 Control Word Counter 1 Control Word Counter 0 LSB of count Counter 2 MSB of count Counter 2 LSB of count Counter 1 MSB of count Counter 1 LSB of count Counter 0 MSB of count Counter O 0000 a um 00220023 Z h Control Word Counter 1 Control Word Counter 0 LSB of count Counter 1 Control Word Counter 2 LSB of count Counter 0 MSB of count Counter 1 LSB of count Counter 2 MSB of count Counter 0 MSB of count Counter 2 G A GG k G A DP 0002022 In all four examples all counters are programmed to read write two byte counts These are only four of many possible programming sequences Figure 8 A Few Possible Programming Sequences Read Operations It is often desirable to read the value of a Counter without disturbing the count in progress This is easi ly done in the 82C54 There are three possible methods for reading the counters a simple read operation tne Counter 3 88 Latch Command and the Read Back Command Each is explained below The first method is to per form a simple read operation To read the Counter which is selected with the A1 AO inputs the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic Other wise the count may be in the process of changing when it is read giving an undefined result intel 82C54 COUNTER LATCH COMMAND The second method uses the
129. urrent state of the OUT pin This allows the user to monitor the counter s output via software possibly eliminating some hardware from a system D4 D3 D2 Di Do D De Ds NULL EEE D7 1 Out Pin is 1 0 Out Pin is O Dg 1 Null count 0 Count available for reading Ds Do Counter Programmed Mode See Figure 7 Figure 11 Status Byte NULL COUNT bit D6 indicates when the last count written to the counter register CR has been loaded into the counting element CE The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions but until the count is loaded into the counting element CE it can t be read from the counter If the count is latched or read before this time the count value will not reflect the new count just written The operation of Null Count is shown in Figure 12 Command D De Ds D4 D3 D2 Dy Do RBS jojo BED ERDE Description 1 Read back count and status of Counter 0 1 lolo Read back status of Counter i Status latched for Counter 1 1 1 Read back status of Counters 2 1 Status latched for Counter 2 but not Counter 1 PAE Os at CACA Os Read back count of Counter 2 Count latched for Counter 2 1 1 1 Read back count and status of Count latched for Counter 1 Counter 1 but not status Read back status of Counter 1 CAUSES Null count 1 THIS ACTION A Write to the control word register B Write to the count register
130. wer lines and four Port C Upper lines The eight lines of Port B are used for internal board functions You can install and connect pull up or pull down resistors for any or all of these three groups of lines You may want to pull lines up for connection to switches This will pull the line high when the switch is disconnected Or you may want to pull lines down for connection to relays which control turning motors on and off These motors turn on when the digital lines controlling them are high The Port A lines of the 8255 automatically power up as inputs which can float high during the few moments before the board is first initialized This can cause the external devices connected to these lines to operate erratically By pulling these lines down when the data acquisition system is first turned on the motors will not switch on before the 8255 is initialized To use the pull up pull down feature you must first install 10 kilohm resistor packs in any or all of the three locations near the 8255 labeled PA PCL and PCH PA takes a 10 pin pack and PCL and PCH take 6 pin packs Figure 1 15 shows a blowup of the PA PCL and PCH resistor pack locations After the resistor packs are installed you must connect them into the circuit as pull ups or pull downs Locate the three hole pads on the board below the resistor packs They are labeled G for ground on one end and V for 5V on the other end The middle hole is common PA is for Port A PCL is fo
131. which you have a better intuition For instance if you are tempted to use addition and subtraction to set and clear bits in place of the methods shown above DON T Addition and subtraction may seem logical but they will not work if you try to clear a bit that is already clear or set a bit that is already set For example you might think that to set bit 5 of a port you simply need to read in the port add 32 2 to that value and then write the resulting value back to the port This works fine if bit 5 is not already set But what happens when bit 5 is already set Bits O to 4 will be unaffected and we can t say for sure what happens to bits 6 and 7 but we can say for sure that bit 5 ends up cleared instead of being set A similar problem happens when you use subtraction to clear a bit in place of the method shown above Now that you know how to clear and set bits we are ready to look at the programming steps for the 1200 board functions 4 10 A D Conversions The following paragraphs walk you through the programming steps for performing A D conversions Detailed information about the conversion modes is presented in this section You can follow these steps on the flow dia grams at the end of this chapter and in our example programs included with the board In this discussion BA refers to the base address Initializing the 8255 PPI The eight Port B lines of the 8255 PPI control the channel selection programmable IRQ and ex
132. will be the count at the time the first Counter Latch Command was issued With either method the count must be read accord ing to the programmed format specifically if the Counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other read or write or pro 3 89 gramming operations of other Counters may be in serted between them Another feature of the 82C54 is that reads and writes of the same Counter may be interleaved for example if the Counter is programmed for two byte counts the following sequence is valid 1 Read least significant byte 2 Write new least significant byte 3 Read most significant byte 4 Write new most significant byte If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between reading the first and second byte to another routine which also reads from that same Counter Otherwise an incorrect count will be read READ BACK COMMAND The third method uses the Read Back command This command allows the user to check the count value programmed Mode and current state of the OUT pin and Null Count flag of the selected coun ter s The command is written into the Control Word Reg ister and has the format shown in Figure 10 The command applies to the counters selected by set ting their corresponding bits D3 D2 D1 1 cS 0 WR 0 AO A1 11
133. xt CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not go high until N 1 CLK pulses after the initial count is written If a new count is written to the Counter it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 1 Writing the first byte disables counting OUT is set low immediately no clock pulse required 2 Writing the second byte allows the new count to be loaded on the next CLK pulse 3 91 This allows the counting sequence to be synchroniz ed by software Again OUT does not go high until N 1 CLK pulses after the new count of N is written If an initial count is written while GATE 0 it will Still be loaded on the next CLK pulse When GATE goes high OUT will go high N CLK pulses later no CLK pulse is needed to load the Counter as this has already been done CW 10 QU te GATE r ee s EIER LSB 4 CW 10 S853 o c uc BEE eee pene CW 10 18823 1 822 GATE gt _ _ _ gs PA NS ALLET FEF 231244 8 NOTE The Following Conventions Apply To All Mode Timing Diagrams 1 Counters are programmed for binary not BCD counting and for Reading Writing least significant byte LSB only 2 The counter is always selected CS always low 3 CW stands for Control Word CW 10 means a control word
134. y setting This header does not have to be set the same as P10 l Voltage Range 5 to 5 volts 0 to 5 volts 10 to 10 volts 0 to 10 volts 1 7 P9 DAC1 X2 X1 5 5 Fig 1 10 DAC 1 Output Voltage Range Jumper P9 P10 DAC 2 Output Voltage Range Factory Setting 5 to 5 volts This header connector shown in Figure 1 11 sets the output voltage range for DAC 2 at 0 to 5 5 0 to 10 or 10 volts Two jumpers must be installed one to select the range and one to select the multiplier The two rightmost jumpers select the range bipolar 5 or unipolar 5 The two leftmost jumpers select the multiplier X2 or X1 When a jumper is on the X2 multiplier pins the range values become 10 and 10 The table below shows the four possible combinations of jumper settings and the diagram shows the factory setting This header does not have to be set the same as P9 Jumpers Left to Right _ Voltage Range and Polarity La ow Se 3 o er o o a or or o 10 to 10 volts Oto 10 volts P10 DAC2 X2 X1 5 5 Fig 1 11 DAC 2 Output Voltage Range Jumper P10 P11 A D Data Word Bit State Set Factory Setting This header connector shown in Figure 1 12 sets the state of the unused four bits in the 8 bit MSB of the 16 bit A D data word This header ensures that these four topmost bits are set at O for unipolar conversions and at the same state as the most significant bit of the 12 bit

ada1200 manual - RTD Embedded Technologies, Inc.

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