PCI2390 User`s Manual
Contents
1. ON CD ON CD ON or ona ona B uu ON CD ON CD ON CD i ON CD 2 4 Indicator 5VD 5V power supply indicator on for normal PCI2390 Data Acquisition V6 21 Chapter 3 Signal Connectors 3 1 The Definition of Signal Connector 37 core plug on the CNI pin definition 19 CLKO GATEO 37 a M 18 OUTO UP DWO 36 O l 17 CLEI GATE 35 z i l 16 OUTI UP DWI 34 c x 15 CLE GATE 33 M 14 OUT2 UP DW2 32 O l 13 CLK3 GATES 31 x m _ 12 OUT3 UP DW3 30 O 9 11 CLK4 GATE4 29 O l 10 OUT4 UP DW4 28 O n 4 Q CLKS GATES 27 Q _ OUTS UP DW5 26 a 7 CLK6 GATE6 25 l 6 OUT6 UP DW6 DA z 3 _ 5 CLK7 GATE 23 U 5 4 OUT UP DW 22 a 5 3 5VO GND 21 2 GND 5VO 20 GND CLKO 7 Timer counter clock source input GATEO 7 Timer counter input gating OUTO 7 Timer Counter output UP_DWO0 7 Input Timer counter count mode input When UP_DW 0 it is backward counter when UP_DW 1 it is up counter Output 5V power Counter signal ground PCI2390 Data Acquisition 3 2 The Definition of DI DO Connector 20 core plug on the PI pin definition DIO DI7 Digital input DO0 DO7 Digital output SV power supply PWR DGND GND 5V DIO DI2 DI4 DI6 DOO DO2 DO4 DO6 DGND Digital ground 19 5V DH DI3 DI5 DI7 DOI DO3 DOS DO7 DGND V6 21 PCI2390 Data Acquisition V6 21 Chapter 4 Connection Way2. PCI2390 User s Manual g Beijing ART Technologv Development Co Ltd PCI2390 Data Acquisition V6 21 Contents a TS a E A E E EE E E E E E E E EE E E EA E E E 2 SEE EA 3 Chapter 2 Components Layout Diagram and a Brief Description ss sse ssennnnnnnnnnnnnnnnzznnnenznzznnnnzzzznranznznnzzznnannnnnnnnzzana 5 2 1 Th Main Component Lay ont Did Oral 244 s4229x26052500004304636944638 49186p93608950405018523469 389839088k0e30083894904446x32 0158E049600860a3646863 5 22 enal bau COU UE CC LON scesa NEERA 5 2 PDS CAID Or DIE 1111 0212 NN NEN AN NO 5 DZ Ae MVC ALOE PA NN YN NENN NR RYN CHRAFF I 6 cC an SIC C O TO ENEI E IE state 7 3 1 The Definition of Signal Connector eee eeeeeeeeeeeeeeeeeeeeeeaaaaaeaeeesseseeeeeeeeeeeeeeeaas 7 5 2 The Dermition or DIDO Connecbof rara 8 Chapter 4 Connection Ways for Each SIGHQI co c1 n0 019k 0000015855 k0 00 kh 9 REI ERROR FYRFYFYR NYFFRYN EF RR DOB FYFYR FFF FRY FYNY NIW 9 1 2 Digital Outp t OMG HOT a CRT FRAN RY FYFYR FY EEF FFY FRY FEE ENTRY CRYN 9 Me e E IE ORO Y OR SRO RR RY CAR FRY CF ARA ERYR A ER FR NR FA 9 SPOSI AIA 10 Isl Ba uu COR e 10 ALLORA 13 Chapter 6 Notes and Warranty POLICY iii 17 GLO a re 17 PAN CERT FRY YEAR FYRFYFYR CRED FFY FF FFEFRYN UF EY FY Y FFAW YF FC EFYRNWY 17 Products Rapid Installation and SclE checK ene iaa in eee ON GN iaia 18 1010011011010 11071718 i E E 18 CGIE R
3. Time diagram is shown in Figure 3 Mode 2 OUT GATE H GATE f fo a 1 TU a 8 1 8 OUT n 4 Figure 3 Mode 3 Sguare wave mode Similar to Mode 2 the counter loads the initial value of n start counting from the n 1 when the signal of GATE has a rising edge timer counter begins to count by subtracting 1 each time The OUT terminal output high level when the count value is more than half of the initial count value and it turn to low level when the count value is less than half of the initial value If the initial count value n is an even number then output 1 1 square wave if the initial count value a is odd number the output has remained high level during the previous n 1 2 count period but the output becomes low level during the post n 1 2 count period that is high level has one clock cycle than low level Set a new initial value during a counting period the counter start a new count cycle next time When GATE 0 the count is prohibited when GATE 1 the count is permitted Time diagram is shown in Figure 4 BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 11 PCI2390 Data Acquisition V6 21 Mode 3 Figure 4 Mode 4 Software triggered strobe Under this mode the counter starts counting after is given the initial value n and OUT becomes high level When the count value becomes 0 it immediately outputs a negative pulse which is equal to the width of one c
4. immediately to count by adding 1 and the output becomes low level When the value turns to M the output becomes and keeps high level until given the initial value or reset If a counter which is counting is given a new value the counter recount from the new initial value GATE 1 enables counting GATE 0 disables counting Time diagram is shown in Figure 7 Mode 0 UK ILILILILILILILILILILILILII TIM WR n d d yh M4 M3M2 MT M M 2 MET M our GAIE H WR n M 4 GATE M Mead M 2 Mei M OUT Figure 7 Mode 1 Hardware retriggerable ONE SHOT The mode can work under the role of GATE of gating signal When given the initial value OUT becomes high level if GATE signal has a rising edge the counter immediately begins to count at this time the output OUT turns to low level When the count ends in other word the count value turns to M the output OUT becomes high level the output width of one shot is deceived by the difference between M and initial value n that is M n If a counter which is counting is given a new value it does not affect the current operation Only when the value turns to M and there is a GATE rising edge BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 13 PCI2390 Data Acquisition V6 21 the counter will begin to count from the new value If there is a GATE rising edge when the counter is working the current counting is stopped and re start counting from the initial v
5. the after sales services we offer please read the following carefully 1 Before using ART s products please read the user manual and follow the instructions exactly When sending in damaged products for repair please attach an RMA application form which can be downloaded from www art control com 2 All ART products come with a limited two year warranty gt The warranty period starts on the day the product is shipped from ART s factory gt For products containing storage devices hard drives flash cards etc please back up your data before sending them for repair ART is not responsible for any loss of data gt Please ensure the use of properly licensed software with our systems ART does not condone the use of pirated software and will not service systems using such software ART will not be held legally responsible for products shipped with unlicensed software installed by the user 3 Our repair service is not covered by ART s guarantee in the following situations Damage caused by not following instructions in the User s Manual Damage caused by carelessness on the user s part during product transportation Damage caused by unsuitable storage environments i e high temperatures high humidity or volatile chemicals V Y VY Damage from improper repair by unauthorized ART technicians gt Products with altered and or damaged serial numbers are not entitled to our service 4 Customers are responsible for shipping co
6. O RIA 18 BE Cri IRE RR RR 18 BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 2 PCI2390 Data Acquisition V6 21 Chapter 1 Overview In the fields of Real time Signal Processing Digital Image Processing and others high speed and high precision data acquisition modules are demanded ART PCI2390 data acquisition module which brings in advantages of similar products that produced in china and other countries is convenient for use high cost and stable performance ART PCI2390 is a data acquisition module based on PCI bus It can be directly inserted into IBM PC AT or a computer which is compatible with PCI2390 to constitute the laboratory product quality testing center and systems for different areas of data acquisition waveform analysis and processing It may also constitute the monitoring system for industrial production process Unpacking Checklist Check the shipping carton for any damage If the shipping carton and contents are damaged notify the local dealer or sales for a replacement Retain the shipping carton and packing material for inspection by the dealer Check for the following items in the package If there are any missing items contact your local dealer or sales gt PCI2390 Data Acquisition Board gt ART Disk a user s manual pdf b drive c catalog gt Warranty Card FEATURES Digital Input gt Channel No 8 gt Electrical Standard TTL compatible gt High Voltage 2V gt Lo
7. alue So the output single pulse has been widened Time diagram is shown in Figure 8 Mode 1 WR n id 4 GATE ee J ne M 4 Med M Z MET M OUT GATE f M 4 MES M2 k4 M3 M 2 MET M OUT n M 4 ii Figure 8 Mode 2 Rate Generator Set this mode the counter loads the initial value of n start counting from the n 1 OUT becomes high level when the count value reaches M the OUT becomes low level After a CLK cycle OUT restore high level and then the counter automatically load the initial value n restart counting from the n 1 Therefore the output terminal will continue to output negative pulse whose width is equal to one clock cycle the clock number between the two negative pulses 1s equal to the difference between M and initial value that is M n Set a new initial value during a counting period the counter start a new count cycle next time GATE 1 enables counting GATE 0 disables counting Time diagram is shown in Figure 9 Mode 2 as wt LILI ET LE CEEE G G G EG E WR Lema Fp Ina fe n IMs bl MET M Me Me M 1 mM Mi M Mi OUT GATE H GATE MRS Me il PM M a il 4 M Z fid 1 M OUT n M4 Figure 9 Mode 3 Square wave mode Similar to Mode 2 the counter loads the initial value of n start counting from the n 1 when the signal of GATE has a rising edge timer counter begins to count by adding 1 each time The OUT terminal output high level when the first half count is completed an
8. counter immediately begins to count at this time the output OUT turns into low level When the count ends in other word the count value turns to 0 the output OUT turns to high level the output width of one shot is deceived by initial value If a counter which is counting is given a new value it does not affect the current operation Only when the value turns to 0 and there is a GATE rising edge the counter will begin to count from the new value If there is a GATE rising edge when the counter is working the current counting is stopped and re start counting from the initial value So the output single pulse has been widened Time diagram is shown in Figure 2 PCI2390 Data Acquisition V6 21 Mode 1 Figure 2 Mode 2 Rate Generator Set this mode the counter loads the initial value of n start counting from the n 1 OUT becomes high level when the count value reaches 0 the OUT becomes low level After a CLK cycle OUT restore high level and then the counter automatically load the initial value n restart counting from the n 1 Therefore the output terminal will continue to output negative pulse whose width is equal to one clock cycle the clock number between the two negative pulses is equal to the initial value that is given to the counter Set a new initial value during a counting period the counter start a new count cycle next time When GATE 0 the count is prohibited when GATE 1 the count is permitted
9. d it turn to low level when carries out the second half count If the initial count value n is an odd number then output 1 1 square wave if the initial count value a is even number the output has remained high level during the previous M n 1 2 count period but the output becomes low level during the post M n 1 2 count period that is high level has one clock cycle than low level Set a new initial value during a counting period the counter start a new count cycle next time GATE 1 enables counting GATE 0 disables counting BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 14 PCI2390 Data Acquisition V6 21 Time diagram is shown in Figure 10 Mode 3 WR n M 4 nzM 3 Il 4 il 2 M1 Ml Weis WEY M 1 MA WM Z fil 1 M l 2 OUT GATE id 4 fil 3 M 2 M 1 M Mel Med fil 2 fil 1 M M34 Ma OUT n M 5 Figure 10 Mode 4 Software triggered strobe Under this mode the counter starts counting after is given the initial value n and OUT becomes high level When the count value becomes M it immediately outputs a negative pulse which is equal to the width of one clock cycle If given a new count value when counting it will be effective immediately GATE 1 enables counting GATE 0 disables counting Time diagram is shown in figure 11 Mode 4 l 4 il 3 Ml 2 M 1_M Figure 11 Mode 5 Software triggered strobe Under this mode when the signal of GATE is on the rising edge the counter starts to count so it is called
10. hardware trigger the output OUT has remained high level When the count value becomes M it outputs a negative pulse which is equal to the width of one clock cycle And then the rising edge of GATE signal can re trigger the counter starts to count from the initial count value again in the count period the output has remained high level If a counter which is counting is given a new value it does not affect the current operation Only when the value turns to M and there is a GATE rising edge the counter will begin to count from the new value Time diagram is shown in figure 12 PCI2390 Data Acquisition V6 21 Mode 5 GLK J LAI LILLA TT FG amp Y IYgWidb GATE OUT n M 4 id 4 Mes M 2 MELT M IM 4 fil 5 fid 4 il 1 fid 4 Mes fil 2 Mi OM Figure 12 PCI2390 Data Acquisition V6 21 Chapter 6 Notes and Warranty Policy 6 1 Notes In our products packing user can find a user manual a PCI2390 module and a quality guarantee card Users must keep quality guarantee card carefully if the products have some problems and need repairing please send products together with quality guarantee card to ART we will provide good after sale service and solve the problem as quickly as we can When using PCI2390 in order to prevent the IC chip from electrostatic harm please do not touch IC chip in the front panel of PCI2390 module 6 2 Warranty Policy Thank you for choosing ART To understand your rights and enjoy all
11. lock cycle If given a new count value when counting it will be effective immediately When GATE 0 the count is prohibited when GATE 1 the count 1s permitted Time diagram is shown in figure 5 Mode 4 eK LLL LL LLL WR n 4 x 4 3 2 1 0 UI GATE H __ GATE 4 8 2 4 pn OUT i Figure 5 Mode 5 Software triggered strobe Under this mode when the signal of GATE is on the rising edge the counter starts to count so it is called hardware trigger the output OUT has remained high level When the count value becomes 0 it outputs a negative pulse which 1s egual to the width of one clock cycle And then the rising edge of GATE signal can re trigger the counter starts to count from the initial count value again in the count period the output has remained high level If a counter which is counting Is given a new value it does not affect the current operation Only when the value turns to 0 and there is a GATE rising edge the counter will begin to count from the new value Time diagram is shown in figure 6 PCI2390 Data Acquisition V6 21 Mode 5 Figure 6 5 2 Up Counter To facilitate the description make M 4294967295 Di the maximum count for the addition If the initial value 1s 4294967291 then recorded as M 4 if it is 4294967292 then recorded as M 3 and so on Mode 0 Interrupt on terminal count In this mode when the initial value assigned if GATE is high level the counter
12. nition connect the signal acquisition data and test whether AD is normal or not Connect the input pins to the corresponding output pins and use the testing procedure to test whether the switch is normal or not Delete Wrong Installation When you select the wrong drive or viruses lead to driver error you can carry out the following operations In Resource Explorer open CD ROM drive run Others gt SUPPORT gt PCl bat procedures and delete the hardware information that relevant to our boards and then carry out the process of section I all over again we can complete the new installation
13. s for Each Signal 4 1 Digital Input Connection DIO switch signal lq 4 Pl DI2 e DI7 T A switch device switch device DGND Figure 4 1 digital signal input connection 4 2 Digital Output Connection DOO switch signal a DOI x di DO2 DO7 eb i c9 switch device bed switch A DGND egg Figure 4 2 digital signal output connection 4 3 Timer Counter Connection GND _J Figure4 3 Timer counter connection 9 PCI2390 Data Acquisition V6 21 Chapter 5 Timer Counter Function 5 1 Backward Counter Mode 0 Interrupt on terminal count In this mode when the initial value assigned if GATE is high level the counter immediately to count by subtracting 1 and the output becomes low level When the value turns to 0 the output becomes and keeps high level until given the initial value or reset If a counter which is counting is given a new value the counter recount from the new initial value When GATE O the count is prohibited when GATE 1 the count is permitted Time diagram is shown in Figure 1 Mode 0 WR n 4 m 4 3 2 1 O mm A or mem 2 1 PB 21 f Figure 1 Mode 1 Hardware retriggerable ONE SHOT The mode can work under the role of GATE of gating signal When given the initial value OUT becomes high level if GATE signal has a rising edge the
14. sts to transport damaged products to our company or sales office 5 To ensure the speed and guality of product repair please download an RMA application form from our company website BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 17 PCI2390 Data Acquisition V6 21 Products Rapid Installation and Self check Rapid Installation Product driven procedure is the operating system adaptive installation mode After inserting the disc you can select the appropriate board type on the pop up interface click the button driver installation or select CD ROM drive in Resource Explorer locate the product catalog and enter into the APP folder and implement Setup exe file After the installation pop up CD ROM shut off your computer insert the PCI card If it is a USB product it can be directly inserted into the device When the system prompts that it finds a new hardware you do not specify a drive path the operating system can automatically look up it from the system directory and then you can complete the installation Self check At this moment there should be installation information of the installed device in the Device Manager when the device does not work you can check this item Open Start gt Programs gt ART Demonstration Monitoring and Control System gt Corresponding Board gt Advanced Testing Presentation System the program is a standard testing procedure Based on the specification of Pin defi
15. the hardware configuration and software programming The following four place numbers are expressed by the binary system When DIP switch points to ON that means 1 and when it points to the other side that means 0 As they are shown in the following diagrams place ID3 is the high bit IDO is the low bit and the black part in the diagram represents the location of the switch Test software of the company often uses the logic ID management equipments and at this moment the physical ID DIP switch is invalid If you want to use more than one kind of the equipments in one and the same system at the same time please use the physical ID as much as possible As for the differences between logic ID and physical ID please refer to the function explanations of CreateDevice and CreateDeviceEx of The Prototype Explanation of Device Object Management Function in PCI2390S software specification BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 5 PCI2390 Data Acquisition V6 21 ID3 D2 IDI IDO ON NE GTA 1 2 3 4 The above chart shows 1111 so it means that the physical ID is 15 ID3 ID2 IDI IDO ON a 1 2 9 4 The above chart shows 0111 so it means that the physical ID is 7 ON ID3 ID2 IDI IDO ON 1 2 3 4 The above chart shows 0101 so it means that the physical ID is 5 OFF 0 OFF 0 OFF 0 OFF 0 OFF 0 OFF 0 OFF 0 OFF 0 ON CD
16. w Voltage 0 8V Digital Output gt Channel No 8 Electrical Standard TTL compatible High Voltage 2 4V Low Voltage 0 5V Initial Power on Value Low level V Y V V Up Backward Counter Channel No 8 gt Resolution 32 bit gt Counter Mode UP_DWn controls 1 is up counter 0 is backward counter gt Count Mode 6 modes software selection BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 3 PCI2390 Data Acquisition V6 21 Electrical Standard TTL compatible Gate GATEn Rising edge falling edge high level and low level Counter Output OUTn high level low level Optical Isolation Voltage 2500V Operating Temperature 0 C 50 C VV VV V WV Storage Temperature 20 C 70 C Others gt Onboard Clock 80MHz Dimension 131mm L 91 5mm W 16mm H 4 PCI2390 Data Acquisition V6 21 Chapter 2 Components Layout Diagram and a Brief Description 2 1 The Main Component Layout Diagram DIDI 25WD Enit PR R r P Pir IIITIITIEITBSIEEETPT YIPFEIREIIRSWISI RESO k 2 2 Signal Input Output Connector CNI analog signal input connector P1 digital input output port 2 3 Physical ID of DIP Switch DIDI Set physical ID number When the PC is installed more than one PCI2390 you can use the DIP switch to set a physical ID number for each board which makes it very convenient for users to distinguish and visit each board in the progress of
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