CAEN V556 rev0
Contents
1. ae di AA 10 3 8 RESET FAST CLEAR INPUT eee dan 11 3 9 OUTPUT BUFFER 11 3 10 OUTPUT BUFFER 12 3 17 INTERRUPT GENERATION drea ondsinnet arinetan iiaia avinen 13 4 NME INTERFACE seder AEA waa 14 4 1 ADDRESSING CAPABILITY 14 4 2 DATA TRANSFER 14 4 3 MODULE IDENTIFIER WORDS aeien nii 16 4 4 HF REGISTER uer endda 17 4 5 RESET REGISTER vadere akaa kawada 17 4 6 Banka 18 4 7 OUTPUT BUFFER 19 4 8 ER REGISTER ude AA 20 4 95 DELAY REGISTER 20 4 10 THRE REGISTER 22 4 11 REGISTER 22 412 INTERRUPT REGISTER ikea etg 23 5 MOD V556 INTERRUPTER een ine 24 5 1 INTERRUPTER CAPABILITY 24 5 2 INTERRUPT LEVEL riain antante d ia ntan iiaa UA 24 5 3 INTERRUPT STATUS ID AE AA EER AEEA EAA 24 5 4 INTERRUPT2. the Output Buffer is set to the HF mode the Interrupt start condition is set to 0 Interrupt on buffer Half Full the Interrupt level is set to 0 the FC bit is set to 0 the RST input works as RESET ONO OT The same action are performed if the VME signal SYSRES is active CAE 04 03 96 V556 User s Manual 4 6 CONTROL REGISTER Base address 1A read write 14143414 Ed ca EES re re re a ef ef eee Enable ch 0 Enable ch 1 Enable ch 2 Enable ch 3 Enable ch 4 Enable ch 5 Enable ch 6 Enable ch 7 FIFO HALF FULL read only FIFO FULL read only FIFO EMPTY read only FAST CLEAR SELECTION Fig 4 3 Mod V556 Control Register E lt 7 0 gt Enable channel lt 7 0 gt 0 channel n Peak Detection disabled 1 channel n Peak Detection enabled These bits are cleared in the following cases by accessing via VME the address Base 1C Reset Register by generating the VME signal SYSRES at Power On HF Output Buffer half full bit read only 0 Output Buffer is half full FE Output Buffer empty bit read only 0 Output Buffer is empty Output Buffer full bit read only 0 Output Buffer is full FC Fast Clear selection 0 pulse in the RST input acts as RESET of the module 1 A pulse in the RST input acts as a FAST CLEAR of the module Bits 8 to 11 are unused and are read as one on the VME data bus CAE 04 03 96 V556 User s Manual 4 7
3. 7 no channel was in the selected range e Inthe Trigger n 8 three channels 0 1 and 3 the selected range First datum read trigger 6 and 7 Fig 4 6 Mod V556 Output Buffer Data Packet FIFO Structure Trigger nr 5 ch 2 and ch 5 converted Trigger nr 8 ch 0 ch 1and ch 3 converted 4 8 FF REGISTER Base address 16 read write A VME access read or write to this location set the Output Buffer in the FF mode the mode is available at the bit 12 of the Delay Register e Delay Register lt 12 gt 0 HF mode e Delay Register lt 12 gt 1 FF mode 4 9 DELAY REGISTER Base address 14 read write The bits lt 7 6 gt of the Delay Register enable to program a delay value between the end of the GATE and the start of conversion The programmable values are from 700 ns to 4 7 us in steps of 0 5 us This delay allows the generation of the FAST CLEAR Bit 12 is read only The status of the bit 12 shows the Output Buffer operating mode i AG Banh atte aS Seas eS coat DELAY VALUE i rina sn tu vous tana uit SONI MA DA Output Buffer operating mode Fig 4 8 Mod V556 Delay Register BM Output Buffer operating mode 0 HF mode 1 FF mode 20 CAE 04 03 96 V556 User s Manual 4 10 THRH REGISTER Base address 12 write only This register High Threshold Register allows to set the 8 bit value of the High Thres
4. In the Trigger n 6 and n 7 no channel was in the selected range In the Trigger n 8 three channels 0 1 and 3 were in the selected range 15 14 13 12 1 410 9 8 17 6 5 4 3 2 1 0 Datum channel 1 Datum channel Fig 3 2 Mod V556 Output Buffer Data Packet FIFO Structure Trigger nr 5 Event cnt 5 Mult 1 trigger 6 and 7 no channel converted ch 2 and ch 5 converted Trigger nr 8 Event cnt 8 Mult 2 ch 0 ch 1and ch 3 converted CAER 04 03 96 V556 User s Manual 3 11 INTERRUPT GENERATION The operations of the V556 VME INTERRUPTER are fully programmable via VME it is possible e to set the VME interrupt level e to program the VME interrupt vector STATUS ID e to program the interrupt generation on the Output Buffer HALF FULL or on the Output Buffer NOT EMPTY this is controlled by the bit 2 of the Interrupt Register e Interrupt Register lt 12 gt 0 Interrupt on Output Buffer HALF FULL e Interrupt Register lt 12 gt 1 Interrupt on Output Buffer NOT EMPTY CAE 04 03 96 V556 User s Manual 4 VME INTERFACE 4 1 ADDRESSING CAPABILITY The module works in A32 A24 mode This means that the module address must be specified in a field of 32 or 24 bits The Address Modifiers code recognized by the module are AM 39 standard user data access AM 3D standard supervisor data access AM 09 extended user data access AM 0D extended supervisor p
5. IDENTIFIER WORDS Base address FA FC FE read only The Three words located at the highest address on the page are used to identify the module as shown in figure 4 1 Module s serial number Base 4 Yo FE Manufacturer number Module type Base 4 Yo FC Fixed code F5 Fixed code Base FA Fig 4 2 Module Identifier Words At the address Base FA the two particular bytes allow the automatic localization of the module For the Mod V556 the word at address Base FC has the following configuration Manufacturer 000010 b Type of module 0000110110 b CAE 04 03 96 V556 User s Manual The word located at the address Base FE identifies the single module via the module s serial number and any change in the hardware for example the use of faster Conversion Logic will be shown by the Version number 4 4 HF REGISTER Base address 1E read write A VME access read or write to this location set the Output Buffer in the HF mode the mode is available at the bit 12 of the Delay Register e Delay Register lt 12 gt 0 HF mode e Delay Register lt 12 gt 1 FF mode 4 5 RESET REGISTER Base address 1C read write A VME access read or write to this location causes the following the event counter is set to 0 the output buffer is reset FIFO EMPTY all the channels are disabled Control Register lt 7 0 gt cleared the delay is set to 0
6. Interrupt Register INT Interrupt start condition 0 Interrupt on Output Buffer HALF FULL 1 Interrupt on Output Buffer NOT EMPTY 22 CAE 04 03 96 V556 User s Manual 5 MOD V556 INTERRUPTER 5 1 INTERRUPTER CAPABILITY The Mod V556 houses VME RORA INTERRUPTER D08 o type This implies the following e it responds to 8 bit 16 bit and 32 bit interrupt acknowledge cycles providing an 8 bit STATUS ID on the VME data lines 000 007 it removes its interrupt request when some on board registers are accessed by VME MASTER RORA Release On Register Access 5 2 INTERRUPT LEVEL The interrupt level corresponds to the value stored in the Interrupt Register lt 15 13 gt The register is available at the VME address Base 00 5 3 INTERRUPT STATUS ID The interrupt STATUS ID is 8 bit wide and it is contained in the Interrupt Register lt 7 0 gt address Base 00 5 4 INTERRUPT GENERATION Via VME it is possible to program the Interrupt Generation on the Output Buffer HALF FULL or on the Output Buffer NOT EMPTY this is controlled by the bit 12 of the Interrupt Register e Interrupt Register lt 12 gt 0 Interrupt on Output Buffer HALF FULL e Interrupt Register lt 12 gt 1 Interrupt on Output Buffer NOT EMPTY 5 5 INTERRUPT REQUEST RELEASE The V556 INTERRUPTER removes its Interrupt request depending on the selected operating mode according to the following 1 If FIFO NOT EMPTY mode is selected
7. by reading out the FIFO until it doesn t become EMPTY 2 If FIFO HALF FULL mode is selected by reading out the FIFO until it doesn t become less than HALF FULL 23 CAER 04 03 96 V556 User s Manual 5 6 INTERRUPT SEQUENCE if the FIFO becomes NOT EMPTY or HALF FULL according to selected mode it requests interrupt by driving an Interrupt Request line IRQ1 7 low according to the Interrupt Register lt 15 13 gt value during the subsequent acknowledge cycle it places on the VME data lines D00 D07 the STATUS ID it is the byte contained in the 8 LSB of the Interrupt register address Base 00 ifa VME MASTER accesses the FIFO it releases the VME interrupt request line once the Interrupt condition is removed FIFO EMPTY if FIFO NOT EMPTY mode was selected or FIFO NOT EMPTY if FIFO HALF FULL was selected 24 CAE 04 03 96 V556 User s Manual 6 REFERENCES 1 Cottini E Gatti V Svelto sliding scale analog to digital converter for pulse height analysis in Proc Int Symp Nuclear Paris Nov 1963 2 VMEbus Specification Manual Revision C 1 October 1985 3 G Bianchetti et al Specification for VMEbus CRATE Type V430 CERN EP January 1990 25
8. of the Control register FC bit e Control register lt 15 gt 0 RESET e Control register lt 15 gt 1 FAST CLEAR If the RST INPUT works as a RESET FC bit in in Control Register set to 0 a pulse sets the board in the following state the event counter is set to 0 the output buffer is reset FIFO EMPTY all the channels are disabled Control Register lt 7 0 gt cleared the delay is set to 0 the Output Buffer is set to the HF mode the Interrupt start condition is set to 0 Interrupt on buffer Half Full the Interrupt level is set to 0 00 After the module must initialized again The VME Reset access to address Base 1 and the generation of the VME signal SYSRES perform the same actions moreover these operations set to 0 the FC bit If the RST input works as FAST CLEAR FC bit in in Control Register set to 1 pulse generated after the end of the gate within the window set with the delay register aborts the conversion The event counter is not incremented 3 9 OUTPUT BUFFER UTILIZATION The output buffer is arranged in FIFO logic 512 x16 bit Two utilization mode are programmable via VME HF Half Full mode The Module does not accept any trigger Module BUSY when the number of data stored is greater than the half size of the FIFO FF FIFO Full mode The Module does not accept any trigger Module BUSY when the FIFO is full In this operating mode it is possibl
9. 4 LOW AND HIGH THRESHOLD SETTING The Control Logic converts only the channels that have values lying in a range between a High and Low Threshold The threshold values are 8 bit wide and are programmable via VME by a write access in two write only registers e Low Threshold Register THRL reg VME address Base 10 e High Threshold Register THRH reg VME address Base 12 CAER 04 03 96 V556 User s Manual 3 5 ADC DYNAMIC RANGE The sliding scale correction reduces slightly the dynamic range of the ADC the 12 bit digital output is valid from 0 to 3840 values from 3841 to 4095 are not correct The usable range of the analog input of the ADC is 0 15 V 3 75 V The conversion of an analog input that is greater than the upper limit could lead to an unpredictable digital output coding in the range from 0 to 255 The User should use the high threshold to maintain the analog input of the ADC under this upper limit The recommended High Threshold values are less then C7 hex 3 6 GATE INPUT If the module is not BUSY the leading edge of a NIM pulse on the GATE input trigger e starts the Peak value conversion of the enabled channels The trailing edge of a NIM pulse on the GATE input trigger e stops the Peak value conversion of the enabled channels e sets the BUSY output to 1 Module Busy e increments the Event Counter This is a high impedance input and is provided with two bridged connectors for daisy chaining thi
10. 6 DETECTOR GATE PEAK IRQ GATE i INT LEVEL STATUS ID 5 CONTROL LOGIC RST or FAST CLEAR Fig 1 1 Mod V556 Block Diagram CAE 04 03 96 V556 User s Manual CHAE 04 03 96 V556 User s Manual 2 SPECIFICATIONS 2 1 PACKAGING 1 unit wide VME unit Height 6U 2 2 EXTERNAL COMPONENTS Refer to fig 2 1 CONNECTORS No 8 IN 0 7 input connectors LEMO 00 type for the 8 single channel inputs No 2 GATE input connectors LEMO 00 type two bridged connectors for daisy chaining for the GATE input signals No 2 RST input connectors LEMO 00 type two bridged connectors for daisy chaining for the RST input signals No 2 BUSY output connectors LEMO 00 type two bridged connectors for daisy chaining for the BUSY output signal DISPLAYS No 1 DTACK green LED VME Selected it lights up during a VME access 2 3 INTERNAL COMPONENTS Refer to fig 2 2 SWITCHES No 6 rotary switches for the module VME Base address selection CAER 04 03 96 V556 User s Manual 2 4 CHARACTERISTICS OF THE SIGNALS INPUT CHANNELS positive polarity DC coupled 1 KQ impedance Shape square wave or semigaussian pulses with risetime gt 100 ns Input range 0 to 4096 mV 0 15 to 3 75 V suggested GATE Std NIM level high impedance min width 200 ns RST Std NIM level high impedance min width 10 ns BUSY Std TTL open collector output
11. AE 04 03 96 V556 User s Manual 1 DESCRIPTION 1 1 FUNCTIONAL DESCRIPTION The Model V 556 is a 1 unit wide VME module that houses 8 Peak Sensing Analog to Digital Conversion channels able to detect and convert the peak value of the analog signals fed to the relevant connectors The basic structure of the circuit is a multistretcher configuration For each channel the relevant stretcher detects the peak value of the input signal during the time interval in which GATE input signal is TRUE The channels can accept input pulses with a dynamic range from 0 V to 4 096 V The outputs of the eight stretcher sections are multiplexed and subsequently converted by a fast 12 bit ADC module 1 psec conversion time The ADC module adopts a sliding scale technique to improve the differential linearity The board houses 12 bit counter Event Counter for the trigger counting it is increased whenever a pulse is sent to the GATE input Via VME it is possible to enable disable each channel to set Low and High Threshold for the Zero Suppression and to program a delay between the end of the GATE and the Start of the conversion Only the enabled channels are converted if the value lies in between the Low and the High Threshold the result is stored in an Output Buffer that can be read via VME The Output Buffer is arranged in a FIFO logic 512 x16 bit The module houses VME RORA INTERRUPTER via VME it is possible to program the int
12. BUFFER Base address 18 read only In this Buffer are available the data packets stored during the conversion sequence if at least one Peak Detection output value is lying in the selected range The first word of the packet is header it contains the event counter value and the number of the channels in the range this number also indicates the data packet length The other words contain the 12 bit converted Peak values together with the corresponding channel number The bit 15 of the word distinguishes between header and channel data e Output Buffer lt 15 gt 1 header e Output Buffer lt 15 gt 0 channel data 1 MULT EVENT COUNTER Event Counter value Number of channels converted 1 Fig 4 4 Output Buffer Data Packet Header EVENT CNT 12 bit Event Counter It counts the pulse on the GATE input it is inhibited if the Module is Busy MULT Multiplicity It indicates the number of channels in the range MULT 1 number of channel i e the packet length MULT 0 one channel 5 CH NUM CHANNEL DATA 12 bit Channel data Channel number Fig 4 5 Mod V556 Output Buffer Channel Data The following figure shows an example of the Output Buffer structure e first datum written is HEADER 5 e In the Trigger n 5 two channels 2 and 5 were in the selected range CAE 04 03 96 V556 User s Manual e Inthe Trigger n 6 and
13. CAE 04 03 96 V556 User s Manual TABLE OF CONTENTS TABLE OF CONTENTS ua i LIST OFS FIGURES ii LIST OF TABLES ii Ie DESCRIPTION ai Jesus d nn awa 1 1 1 FUNCTIONAL 1 2 SPECIFICATIONS 242 hana 4 2 1 PAGKAGING 4 2 2 EXTERNAL COMPONENTS aanika 4 2 3 INTERNAL 4 2 4 CHARACTERISTICS OF THE 51 1 5 4 4 222 5 2 5 PERFORMANCES AND TEST 5 1 5 2 2 5 2 6 POWER REQUIREMENTS 5 3 OPERATING MODES sea Stet tale antics be area ne arsen raude 8 3 1 GENERAL 8 3 2 OPERATION 8 3 3 ENABLE DISABLE CHANNEL 9 3 4 LOW AND HIGH THRESHOLD 9 3 5 ADC DYNAMIC 10 3 0 GATE EE ME 10 7 BUSY OUTPUT
14. GENERATION aaa kitawa riia nikanawa inao inaia 24 5 5 INTERRUPT REQUEST RELEASE maina nana 24 5 6 INTERRUPT SEQUENCE 25 une ke ee then 26 CAE 04 03 96 V556 User s Manual LIST OF FIGURES Fig 1 1 Mod V556 Block Diagram AA 3 Fig 231 M0d V556 Front Pana sunneste teite den 6 Fig 2 2 Mod V556 Components Locations ia KA KA aaa 7 Fig 3 1 Mod V556 Acquisition 9 Fig 3 2 Mod V556 Output Buffer data packet FIFO 12 Fig 4 1 V556 Base Address 15 Fig 4 2 Module Identifier Words Si Wa aa 16 Fig 4 3 Mod V556 Control iii 18 Fig 4 4 Output Buffer Data Packet 19 Fig 4 5 Mod V556 Output Buffer Channel 19 Fig 4 6 Mod V556 Output Buffer Data Packet FIFO 20 Fig 4 8 Mod V556 Delay Register iii 21 Fig 4 9 V556 THRA Bil AA AA 22 Fig 4 10 Mod V556 THRL 22 Fig 4 11 Mod V556 Interrupt 23 LIST OF TABLES Table 4 1 Address Map for the Mod 556 16 CH
15. active high 1 This is a high impedance input and is provided with two bridged connectors for daisy chaining Note that the high impedance makes this input sensitive to noise so the chain has to be terminated on 50 Q on the last module the same is needed also if one module only is used whose input has thus to be properly matched 2 5 PERFORMANCES AND TEST RESULTS Differential non linearity 2 between 10 and 90 of the range Integral non linearity 0 1 Conversion time 2 Minimum 3 us 13 us 2 This is the time spent in the entire conversion sequence see 3 2 the minimum value is obtained when all the 8 values are not in the range selected and hence there is no ADG conversions Substantially it is the Control Logic scan time The max value is obtained when all the 8 values are in the range selected and therefore converted and stored in the output buffer 2 6 POWER REQUIREMENTS 12 500 12V 100 mA 5V 1 3 A 5V 500 mA CAE 04 03 96 V556 User s Manual CAE Mod V556 a 000000 Inputs 0 7 gt w GATE input gt RESET FAST CLEAR input lt VME selected LED BUSY output 9 9 9 8 CH PEAK SENSING ADC Fig 2 1 Mod V556 Front Panel CAER 04 03 96 V556 User s Manual VME P1 connector Rotary switches for Base address selection Paux connector for CERN VMEbus crate
16. e to utilize all the memory location but it is possible to lose some data If the FIFO becomes full during a conversion sequence CAE 04 03 96 V556 User s Manual 3 10 OUTPUT BUFFER STRUCTURE During the conversion sequence if at least one Peak Detection output value is lying in the range identified by the High and Low Thresholds the Control Logic stores in the output buffer the following words e header that contains the event counter value and the number of the channels the range this number also indicates the number of subsequent words in the FIFO related to that event e 12 bit converted Peak values together with the corresponding channel number If no channel is in the correct range the Output Buffer is not written The Output Buffer is available at VME address BASE 18 The bit 15 of the Output Buffer indicates if the word read is a header or a channel data e Output Buffer lt 15 gt 1 header e Output Buffer lt 15 gt 0 channel data The status of the Output Buffer is available in the Control Register e Control Register lt 12 gt 0 Output Buffer is Half full e Control Register lt 14 gt 0 gt Output Buffer is Empty e Control Register lt 13 gt 0 Output Buffer is Full The following figure shows an example of the Output Buffer structure see also fig 4 4 4 5 The first datum written is HEADER 5 In the Trigger n 5 two channels 2 and 5 were in the selected range
17. errupt generation on the Output Buffer HALF FULL or on the Output Buffer NOT EMPTY A front panel LED DTACK lights up each time the module generates the VME signal DTACK An open collector signal BUSY is available on the front panel This allows to obtain a wired OR Global Busy signal The BUSY is a high impedance output and is provided with two bridged connectors for daisy chaining The V556 Model uses the P1 and P2 connectors of VME and the auxiliary connector for the CERN V430 VMEbus crate Jaux Dataway The module works in A24 A32 mode the recognized Address Modifier codes are AM 3D standard supervisor data access AM 39 standard user data access AM 0D extended supervisor data access AM 09 extended user data access CHAE 04 03 96 V556 User s Manual The module s Base Address is fixed by 6 internal rotary switches housed on two piggy back boards plugged into the main printed circuit board The Base Address can be selected in the range 00 0000 lt gt FF 00 A24 mode 0000 0000 lt gt FFFF FFO0 A32 mode The data transfer occurs in D16 mode IDENTIFIER gt IN INPUT 0 DETECTOR GATE VME IN PEAK INPUT 1 DETECTOR GATE INTERFACE IN PEAK INPUT 2 DETECTOR GATE IN PEAK INPUT 3 DETECTOR GATE i UTPUT 1 BUFFER i INPUT 4 DETECTOR GATE VME BUS IN PEAK INPUT 5 DETECTOR GATE 3 PEAK INPUT
18. hold This value can range from 0 to 4 V 00 to FF with a resolution of approximately 16 mV count 15 14 15 14 11109 8 7 6 5 4 2 1 0 Fig 4 9 Mod V556 THRH Register The usable range of the analog input of the ADC is 0 15 V 3 75 V The conversion of an analog input that is greater than the upper limit could lead to an unpredictable digital output coding in the range from 0 to 255 The User should use the High Threshold to maintain the analog input of the ADC under this upper limit The recommended High Threshold values are less then C7 hex 4 11 THRL REGISTER Base address 10 write only This register Low Threshold Register allows to set the 8 bit value of the Low Threshold This value can range from 0 to 4 V 00 to FF with a resolution of approximately 16 mV count N B this value must be lower than the High Threshold value 14141312 ide 7 6 5 fa s e 1 fo Fig 4 10 Mod V556 THRL Register 21 CAE 04 03 96 V556 User s Manual 4 12 INTERRUPT REGISTER Base address 0 read write This register contains the value of the interrupt level and the STATUS ID that the V556 INTERRUPTER places on the VME data bus during the interrupt acknowledge cycle Bits 8 to 11 are unused and are read as one on the VME data bus Skee STATUS ID INT LEV 19191918 iojo Interrupt STATUS ID Interrupt start condition Interrupt level Fig 4 11 Mod V556
19. least one value is lying in the range e header is stored in the output buffer it contains the event counter value and the number of the channels in the range e the sampled values in the range are converted and the 12 bit values obtained are stored in the Output Buffer together with the corresponding channel number e if no value falls in the range no channel is converted and no data is written in the Output Buffer e increments the Event Counter e The Busy is removed and the module is ready for the next acquisition Figure 3 1 summarizes the operation sequence here described CAER 04 03 96 V556 User s Manual Prog Delay Conversion Time Gate Width GATE i sequence Fig 3 1 Mod V556 Acquisition Sequence 3 3 ENABLE DISABLE CHANNEL OPERATION Via VME It is possible to enable disable the Peak Detection section of each channel The bit lt 7 0 gt of the Control Register controls the status of the 8 Peak Detection sections e Control Register lt n gt 0 gt channel Peak Detection disabled e Control Register lt n gt 1 channel Peak Detection enabled The Control Register is available at the VME address Base 1A All the Peak Detection sections are disabled Control Register lt 7 0 gt cleared in the following cases e accessing via VME the address Base 1C Reset Register e by generating the VME signal SYSRES e at Power On 3
20. rogram access The module s Base Address is fixed by 6 internal rotary switches housed on two piggy back boards plugged into the main printed circuit board The Base Address can be selected in the range 00 0000 lt gt Yo FF FF00 A24 mode 0000 0000 lt gt FFFF 00 A32 mode The Base Address reserves in this way a page of 256 bytes for the module The Address Map of the V556 module is shown in Table 4 1 4 2 DATA TRANSFER CAPABILITY The internal registers and the Output Buffer are accessible in D16 mode CAE 04 03 96 V556 User s Manual Base address bit lt 23 20 gt Base address bit lt 19 16 gt Base address bit lt 15 12 gt God Base address bit lt 11 8 gt Base address bit lt 31 28 gt Base address bit lt 27 24 gt Fig 4 1 V556 Base Address Setting CAE 04 03 96 V556 User s Manual Table 4 1 Address Map for the Mod V556 ADDRESS REGISTER CONTENT TYPE Base FE Version amp Series read only Base FC Manufacturer amp module type read only Base YoFA Fixed code read only Base F8 Not used Base 1 Register read write Base 1C Reset Register read write Base 1A Control Register read write Base 18 Output Buffer read only Base 16 FF Register read write Base 14 Delay Register read write Base 12 THRH Register write only Base 10 THRL Register write only Base 0E Not used Base 02 Not used 4 3 MODULE
21. s allows to control easily a system of many units Note that the high impedance makes this input sensitive to noise so the chain has to be terminated on 50 Q on the last module the same is needed also if one module only is used whose inputs have thus to be properly matched 3 7 BUSY OUTPUT An open collector signal BUSY is available on the front panel This is a high impedance output and is provided with two bridged connectors for daisy chaining this allows to obtain a wired OR Global Busy signal of a system of many units Each module sets to 1 its Busy output after the trailing edge of a pulse on the GATE input Module Busy and releases it to 0 at the end of the conversion sequence When the Module is Busy it does not accept another GATE pulse If many units are connected in daisy chain mode via the GATE and BUSY signal after a pulse on the GATE input trigger the Global Busy signal is set to 1 and it is released to 0 only when all the V556 modules in the chain have completed the conversion sequence and the entire system is ready to accept another trigger CAE 04 03 96 V556 User s Manual This avoids that some modules in the chain accept another trigger while other modules are still Busy This could cause a lack of coherence in the overall data the event counter value of different modules could not be coherent 3 8 RESET FAST CLEAR INPUT It is possible to program the the function of this input via the bit lt 15 gt
22. type V430 VME P2 connector Component side of the board Fig 2 2 Mod V556 Components Locations CAE 04 03 96 V556 User s Manual 3 OPERATING MODES 3 1 GENERAL INFORMATION The module V556 houses 8 Peak Detection channels The Peak Detection outputs are multiplexed and subsequently converted by a high speed ADC module A Control Logic controls the conversion sequence it converts and stores in the Output Buffer only the channels that have values lying in range between High and Low Threshold When the module is Busy it sets to TTL logic level 1 the Busy output Moreover each channel can be individually inhibited via VME The module is Busy during the conversion sequence and when the Output Buffer is not ready to accept data Buffer full 3 2 OPERATION SEQUENCE If the module is not Busy and at least one channel is enabled the leading edge of a NIM pulse on the GATE input e starts the Peak Detection on the enabled channels The trailing edge of the GATE signal stops the corresponding Peak Detection section and sets the BUSY output to 1 Module Busy It is possible to program delay up to 8 us between the end of the GATE and the Start of conversion via the Delay Register When the programmed Delay time is over the Control Logic starts the conversion sequence e the output of all the Peak Detection sections are sampled e the Control Logic checks if the sampled value in the selected range e If at
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