User Manual
Contents
1. Cycle 10Hz 100Hz OV Vcc Voltage levels 50 Duty Cycle 8KHz fundamental Duty Cycle 10 90 in 10 steps 800Hz fundamental Duty Cycle 10 90 in 10 steps 80Hz fundamental Duty Cycle 10 90 in 10 steps High going pulse 20uSec wide every 247 cycles of the FM High signal High going pulse 20uSec wide every 2147 cycles of the FM High signal Output toggle every 247 cycles of the FM High signal Output toggle every 2147 cycles of the FM High signal Resistor Capacitor low pass filter integrator with a time constant of approximately 1mSec buffered by unity gain opamp Page 10 RS232 Port Pin out Pin 1 4 6 7 8 9 N C Pin 2 Tx when linked for 1 1 cable Pin 3 Rx when linked for 1 1 cable Pin 5 System and connector Ground I O mapping RS232 Port Normal mode Tx P50 TxDO Rx P51 RxDO Programming mode Tx P84 TxD1 Rx P85 RxD1 Waveform Generator Independent control and user configurable No 2144 processor dependence LED1 P83 Active low enable LED2 P86 Active low enable SW1 P91 switch to ground SW2 P92 switch to ground Liquid Crystal Display LCD data port Mapped into external data bus LCD Enable P82 LCD R W P81 LCD RS P80 The LCD should be read and written like a standard peripheral device located at 80000H Analog inputs AN1 P73 via link AN2 P74 via link Temperature P75 via link Temperature Sensor Sensor type LM35 Analog Amplifier Linear Opamp2. Gain is 10 Resultant scaling 100mVolts DC per C Effective range 0 C to 50 C Page 11 Copyright November 2001 Syonics Technologies P L Disclaimer This evaluation board is intended for evaluation of the Hitachi H8S 2144 micro controller and is not intended for use in life support automotive or aerospace applications mission critical systems Syonics Technologies has a policy of continuous improvement These specifications and features may change at anytime without notification HDI M is a Hitachi product and is downloadable from the web It is not distributed nor warranted by Syonics Technologies For additional information please contact Syonics Technologies Pty Ltd PO Box 3043 Frankston 3199 Victoria Australia Web www syonics com au END Page 12 Copyright November 2001 Syonics Technologies P L
3. external memory area The extra RAM on the board will now be available to applications and code testing Since the flash memory is specified at 100 R W cycles it is advisable to load and run applications in external RAM until they are debugged then they may be flashed The HDI M software from Hitachi will allow these RAM loading and debugging facilities Refer to the Hitachi HDI M documentation for operational notes When linking the application to run in RAM make sure to set the target code to run at 20000H Programming software The software to download the application code to the 2144 part is the Syonics Technologies ACL download tool This software runs on a windows platform and performs all the functions necessary to connect to the part and download the required code The operation is to set the 2144 into boot mode using the BOOT switch the boot LED should be on Start the ACL code In the boxed KERNEL area of the screen click browse and find the krnl2144 a37 file This is the kernel program that gets downloaded into the 2144 RAM to perform all the programming functions Next click browse in the application box and browse to the application code you wish to download to the 2144 device Ensure the serial port is connected and press down load The ACL tool will show what is happening at the different stages of programming the part and will eventually display Reset to run At this time the download has been succe
4. 32 port for communication with Syonics ACL flash download program and general communications Preloaded software to run the LCD and peripherals Automatic boot mode selection and signal routing allow direct connection of the 2144 CPU to the Syonics download tool Page 3 Copyright November 2001 Syonics Technologies P L System information The 2144 EVB board from Syonics Technologies has a large range of peripherals that allow the user to evaluate most chip functions Timer functions such as external counting event counting capture compare and pulse width measurement can be easily evaluated using the waveform generator as detailed below It is a simple matter of placing links to connect the appropriate waveform generator output to the desired timer input set the VCO level using the potentiometer and start experimenting with the timers Analog sources are available for A D measurement An LC display provides some simple information output Experiment and see what the 2144 evaluation system can do System Block Diagram Comms Port RS232 Level RS232 Power Supply 5V Selector Converter Port SCI 0 and 1 18 432MHz Clock Generator 128K words 0 SRAM 0 Temperature pS Sensor 2144 CPU Timers Memory Decode Pin Jumper Waveform generator RESET and Matrix Circuit Boot Timing s 3 D A Converter DC Level Output BOOT RESET Analog Source Analog Source Page 4 Copyright November 2001 Syonics Technolo
5. g Syonics TOR OIOGIeS E H8S 2144 Evaluation B oard oe id HIT 2144EVBCPU Versi 1 0 Introduction This 2144 evaluation system is designed to provide the user with an appreciation of the Hitachi H8S 2144 micro controller and the on chip peripherals This 2144EVB card can be used with the HDI M 2144 Hitachi Debug Interface Monitor This package consists of the following 1 The 2144 EVB CPU card circuit board 2 ADC power jack to allow an external power supply to be connected 3 A3 5 diskette containing the preloaded software and the Syonics Technologies ACL download tool software 4 RS232 9 pin to 9 pin serial cable 5 This user manual 6 Data CDs The following diagram details the layout of the 2144 EVB card RS232 Tx Rx swap link all bi Tx Rx LEDs iming and Sync outputs Yo a Ground Power LED Power Input a 605000005000 ses 060500000 0000000 Power Regulator Vref User Switches aa and LEDs lelejleie lere ele Waveform Generator Eoaea Timing and Sync outputs eo y RAM RAM 0 2144 LOW HIGH CPU BYTE BYTE 7 Beneath LCD Waveform Generator Beneath LCD System Clock Generators Waveform Gernerator FM and PWM outputs e im a e a 2 a E al e E o a a e o O DOOD0dod0d o O DODdd0 E a eaeeag co Temperature ERR E Q e 180 O Sensor IC HE AnalogTP Analog ANO ane 7 a Connector Links Boot Swi
6. gies P L Data Buffer RS232 Port The DB9 on the options board is connected to the 2144 SCI ports via an RS232 level translation IC and a steering logic IC which selects between SCI1 and SCIO depending on the operation mode The code supplied with the evaluation board Syonics_2144 mot will send a message out the RS232 port via SCIO at 9600 baud at the system clock speed of 18 432MHZ 8N1 protocol This will display a message on a standard terminal or terminal program running on a PC In addition the 2144 is flashed using the same RS232 port but must use SCI1 So when setting the evaluation board into boot mode the serial port is routed to SCI1 This is done automatically when boot mode is selected Two links are available on the board to allow Tx Rx swap over If using a 1 1 cable then place the links horizontally if using a null modem cable place the links vertically RS232 Jumper Link Positions eje og 1 1 cable Null Modem Cable Liquid Crystal Display The LCD on the board is a 16 character x 2 line character display It has integral LED back lighting that runs continuously The display is mapped into the memory space at 80000H with the control signals for the LCD run from I O ports Refer to the schematic diagram for details The contrast for the LCD is adjusted using the pot below the display Switches and LEDs There are two switches and associated LEDs connected to the 2144 processor The switches are switch t
7. mode 2 by default That is with MDO jumper set and MD1 jumper open For flash programming the board needs to be in mode 0 and Port 9 0 9 1 and 9 2 need to be high The port 9 inputs are pulled high by the 2144 EVB card and MD1 is controlled by the on board boot circuitry This EVB card will come with an application program loaded into the flash memory and will begin execution at 0000H By default the card will begin running in mode 2 If new data is to be loaded into the flash ie HDI M several things have to happen 1 Mode selection Make sure the MDO link is in place Press the BOOT button on the board for Ye sec and the mode will change to mode 0 in to micro controller The circuitry will perform all necessary timing for the Mode lines and the reset line The RS232 comm port will be switched from SCIO to SCI1 The micro controller will then be ready to accept commands and data from a host programming application 2 In this case the host will be the Syonics Technologies ACL Application Code Loader software which is available on the supplied CD or from the web site link at the end of this user manual The ACL software will establish all the necessary timing to allow a new application to be loaded into the flash memory of the 2144 3 Once new code has been flashed in reset the board and the 2144 EVB card will restart in mode 2 running the newly flashed application This 2144 EVB board normally runs in mode 2 which gives access to the
8. o FTID timer input of the 2144 The duty cycle of the PWM can be varied using the VCO control The shaded areas of the diagram show the connections The FTID signal pins are all connected horizontally as shown and the PWMHigh signal pins are connected vertically Timer linking matrix TRIGGER SIGNALS elig MKRSHAT ele MKRLONG igh FRSHRT ove TIMER INPUTS ejojoje e eje PWMLow On the actual PCB silkscreen waveforms are shown in place of text as shown here Page 9 Copyright November 2001 Syonics Technologies P L Specifications Power Input Power Consumption System Clock speed Sub Clock Speed System Voltage External Mapped RAM Analog Sources LCD Waveform Generator FM High Output FM Mid Output FM Low Output PWM High Output PWM Mid Output PWM Low Output MRKSHRT output MRKLONG output FRSHRT output FRLONG output D A converter Copyright November 2001 Syonics Technologies P L 8 14VDC or 9 12VAC Centre Pin of DC Jack is Positive 200mA 18 432MHz 32 768KHz 5 Volts DC to microcontroller logic circuitry 128K words mapped at 20000H 5FFFFH Use only 20000 5F800 3 2 potentiometers and 1 analog temperature sensor LED backlit 16 x 2 character intelligent display Manufactured by Winstar refer to Winstar LCD web site for details 1kHz 10KHz OV Vcc Voltage levels 50 duty cycle 100Hz 1KHz OV Vcc Voltage levels 50 Duty
9. o ground and are connected to P91 and P92 Two LEDs next to these switches are active low enable and are connected to P83 and P86 The switches are used to access different menus on the LCD when running the sample code but may be used for any function outside this application Page 5 Copyright November 2001 Syonics Technologies P L Analog Sources There are three on board analog sources available to the A D circuitry Two of these sources are analog potentiometers and the other is a LM35 temperature sensor A variable analog reference is supplied on the Vref pot and will vary the analog reference between 0 and Vcc This analog reference voltage becomes the Vref for the CPU and the reference for the top of the analog potentiometers One analog source is an LM35 temperature sensor This sensor will output a DC voltage dependent on the ambient temperature The output of the temperature sensor is amplified by 10 using an opamp The resulting DC level is a rise of 100mV per degree C from near zero volts This will give a temperature range of 0 C to 50 C for a 0 to 5VDC swing The three analog sources are connected to the processor via links located to the left of the potentiometers Place the links to connect the analog sources to the 2144 If these analog sources are not to be used and the corresponding processor inputs are to come from elsewhere then it is recommended the link be removed to avoid damage to the amplifier and to the potentiomete
10. rs from external voltage sources Refer to the schematic diagram for details Refer to the data sheet for the National LM35DZ temperature sensor for operation details D A Converter The 2144 board contains circuitry to build a simple digital to analog converter Using a resistor capacitor low pass filter a good analog voltage can be produced The time constant is 1mSec RC combination It is recommended that the input frequency to this circuit be more than 5 times this rate ie 5KHz for minimum ripple of the filter output By varying the duty cycle of this input waveform the resultant output voltage can be varied between 0 2 VDC and 5VDC An op amp buffers the filter output The D A can be run from the waveform generator PWMHigh output or from any of the 2144 timer outputs As an additional feature the D A voltage can be looped back into the analog inputs for conversion So a closed loop system can be built and evaluated PWM Waveform DC level Output tL gt Page 6 Copyright November 2001 Syonics Technologies P L Boot Mode and mode pins The 2144 processor like many other Hitachi processors will run in many different operation modes These modes allow internal ROM and RAM to be enabled and disabled as well as enabling external memory thus giving access to the full address space The mode is set by the 2 mode pins MDO and MD1 These inputs are available as jumper pins on the 2144 EVB card The evaluation board will run in
11. set counters By using these signals in conjunction with the FM signals software can be written to evaluate virtually all timer functions available Page 8 Copyright November 2001 Syonics Technologies P L The frequency and PWM duty cycles are all varied together using the VCO potentiometer Considerable work as gone unto ensuring a stable and predictable output All output signals are synchronous That is they all change state with in 200nSec of each other Also all outputs from the waveform generator are run as open collector drives A 1K ohm pull up resistor to Vcc on each output is either pulled to ground for a low or opened to be pulled up to Vcc for a high level This Vcc can be either 3 3VDC or 5 0VDC depending on the Vcc selection on the CPU card Therefore the output of the waveform generator is both inherently protected from shorts to adjacent signals and immune to supply voltage variation A 5 0VDC supply on the options board maintains a steady voltage reference to the waveform generator for A D conversion accuracy All the outputs from the waveform generator are present on test pins These test pins lie next to input pins to the timers on the 3664 micro controller It is a simple matter to identify the output required from the waveform generator and link it to the required input to the 3664 Refer to the diagram below for a summary of the connections The example shown here will connect the PWMHigh signal of the waveform generator t
12. ssful so press the reset button on the 2144 board and the main code will start executing Refer to the documentation supplied with the ACL tool or the on line help for specific operation of the ACL Page 7 Copyright November 2001 Syonics Technologies P L Waveform Generator The on board waveform generator will generate FM frequency Modulation PWM Pulse Width Modulation as well as framing pulses and marker pulses as detailed below FMHigh Freq Mod 1KHz 10KHz FMMid Freq Mod 100Hz 1KHz FMLow Freq Mod 10Hz 100Hz PWMHigh Pulse Width Mod 10 90 duty cycle at 8KHz PWMMid Pulse Width Mod 10 90 duty cycle at 800Hz PWMLow Pulse Width Mod 10 90 duty cycle at 80 Hz FRLong Framing Pulse Long Waveform goes high at 0 count and low again after 2147 FMHigh pulses The waveform will remain low for 2147 counts then repeat FRShrt Framing Pulse Short Waveform goes high at 0 count and low again after 247 FMHigh pulses The waveform will remain low for 247 counts then repeat MKR Long Marker Pulse Long Positive going pulse every 2147 FMHigh pulses MRK ShortMarker Pulse Short Positive going pulse every 247 FMHigh pulses These 10 signals are available to the micro controller timer inputs They connect via the headers and jumpers as labelled on the circuit board The frequencies and Duty cycle are variable using the VCO potentiometer located on the circuit board The frequency range varies by a fac
13. tch Reset Switch and LED and LED Page 2 Copyright November 2001 Syonics Technologies P L Features This controller card is designed to allow the user to evaluate the 2144 and peripherals with ease and with a maximum of flexibility The following outlines the major features DC power input will accept a 2 1mm DC jack The plug pack if supplied will power the card and peripherals at 9 12 VDC and up to 200mAmp On board voltage regulator converts the incoming voltage to 5 0VDC required for the circuit operation On board waveform generator which produces both FM and PWM waveforms in three frequency bands Refer to section Waveform Generator for further details Using links these waveforms can be routed into the timer peripherals On board analog temperature sensor for some real world measurement A variable A D reference and two analog potentiometers allow evaluation of the A D section Hardware D A converter using RC OPAMP and PWM signals allow D A conversion 16 character x 2 line LCD for information display Headers with all available CPU signals labelled for signal monitoring or expansion 18 432MHz system clock 32 768KHz sub clock Two switches and associated LEDs as well as a power LED a RESET LED and two LEDs for RS232 communications status Large on board RAM area which allows loading and running application code without the need to program flash Use of Hitachi HDI M software aids this process RS2
14. tor of 10 for each of the three FM outputs and the duty cycle varies from 10 to 90 in 10 increments at each of the three frequencies The Frame and Marker waveforms are always the same number of pulses and are linked to the FM High output frequency The signals are intended to be used as follows e FMHigh FMMid and FMLow These three raw FM signals have a 50 or 1 1 duty cycle and are synchronous with each other They are intended to be used as clock inputs to timer counters or as clock sources for A D conversion sampling rate time base or simple timing inputs e PWMHigh PWMMid and PWMLow These three signals are intended to be used by the capture compare features of the timer peripherals They can also be used as timing references and clock sources e FRLong and FRShrt These two signals are intended to start stop and reset counters The signals correlate to the FMHigh signal where the FRLow will count 247 FMHigh falling edge transitions then toggle its state The FRLong signal also correlates to the FMHigh signal and will count 2147 falling edge transitions These numbers chosen are arbitrary and are not referenced to anything e MRKlong and MRKshrt These two signals are very similar in function to the FRShrt and FRLong signals with the exception that when the count value is reached the signal will go high for approximately 12uSec then return low thus marking the each 247 or 2147 count These 4 signals are intended to start stop and re
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