Home

open the User`s Manual

1. From Xylon License Key Generator Sent 6 9 2012 17 47 To Ee Subject Xylon Core License Delivery 1D 03512090617423596 Attachments 03512090617423596_ip_xap_349logicvcml_eval_flexim lic 568 B gt Merere THIS IS AN AUTOMATICALLY GENERATED EMAIL Please do not reply to this message All requests for support should be directed m Designed by XYLON You can download the evaluation IP core deliv You will need your login email and password for access to Xylo eb download area This email contains the license s for the core s you requested It enables you tg use the core s at the level authorized by the License Type indicated in the table at the bottom of this page A full license allows you to use the core in Full Access mode Cal download link NOTE A full license means that purchased or evaluation IP core can be fully implemented into the Xilinx FPGA The IP core licenses are attached to this e mail 03512090617423596_ip_xap_349logicvcml_eval_flexim lic NOTE You can alternatively download the license archive by clicking here You must access this downloads evaluation license by September 13 2012 After this date the license archive will be removed from the website Figure 20 Step 4 E mail with logicBRICKS License and Download Instructions Copyright Xylon d o o 2015 All Rights Reserved Page 28 of 46 i logiREF MEDIA ZED mm Reference De
2. Implement support for a single color format No Select single color format g 4 KS Bought IP license available oe Cancel K Figure 3 Example of logicBRICKS IP Configuration GUI Click on the Documentation icon in the GUI opens the User s Manual of the logicBRICKS IP core 2 2 Evaluation logicBRICKS IP Cores Xylon offers free evaluation logicBRICKS IP cores which enable full hardware evaluation Import into the Xilinx ISE Platform Studio XPS and Vivado Design Suite IP parameterization through the tool GUI interface Bitstream generation If you need to simulate logicBRICKS IP cores please contact Xylon The logicBRICKS evaluation IP cores are run time limited and cease to function after some time Proper operation can be restored by bitstream reloading Besides this run time limitation there are no other functional differences between the evaluation and fully licensed logicBRICKS IP cores Evaluation logicBRICKS IP cores are distributed as parts of the Xylon reference designs http Awww logicbricks com logicBRICKS Reference logicBRICKS Design aspx Specific IP cores can be downloaded from Xylon s web shop http www logicbricks com Products IP Cores aspx Copyright Xylon d o o 2015 All Rights Reserved Page 10 of 46 Ewe logiREF MEDIA ZED mewa mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 2 3 logicBRICKS IP Cores Used in This Design
3. the keyboard connected to the micro USB port o in graphical menu use up and down arrows for iteration over examples enter key for starting selected example Q letter key for exiting the example o in console outside of graphical menu use whole keyboard to write commands directly to the screen console the mouse connected to the micro USB port for interacting with Qt examples serial terminal program baud rate 115200 8N1 and USB UART connection to the ZedBoard telnet connection and Ethernet connection with the ZedBoard 8 3 1 BootUp Menu Your ZedBoard will eventually boot up to the graphical menu from which you can start different demo applications or switch to the Linux terminal To enter the graphical menu from the Linux console run the following command in the root of the file system Linux directory source profile lf you want to prevent ZedBoard from entering graphical menu on the startup please rename config profile file on the SD card to any other name Please do not rename or remove init sh file from the SD card since it performs startup initializations required for applications to run properly Please note that graphical menu shows up only on the console on the monitor attached to your ZedBoard kit If you control the ZedBoard kit by a PC through a serial UART link the graphical menu is not available Copyright Xylon d o o 2015 All Rights Reserved Page 41 of 46 mm Designed by XYLON logiREF MEDIA ZED Refe
4. 2 3 1 logiWIN Versatile Video Input The logiWIN is a frame grabber IP core designed to capture video input stream and give an output video formatted in variety of digital video formats Its functions include scaling cropping positioning and masking of the output image by non rectangular masks Interlaced input PAL NTSC video streams can be de interlaced The interface to the frame buffer or the video memory is designed for SDRAM SDR or DDR or SRAM implementation Supports Xilinx Zynq 7000 All Programmable SoC and all Xilinx FPGA families Maximum input and output resolutions are 2048 x 2048 pixels Supports different digital video input formats TU656 PAL and NTSC and ITU1120 RGB YUV 4 2 2 Supports different digital video output formats RGB YUV 4 2 2 Can switch between two video inputs with different video format Built in YCrCb to RGB converter YUV to RGB converter and RGB to YCrCb converter Embedded image color enhancements contrast saturation brightness and hue separately for ITU and YUV Real time video scale up zoom in up to 64x Real time video scale down zoom out down to 16 times Lossless 2x scaling down or 4x in the cascade scaling mode Supports video input cropping and smooth image positioning ARM AMBA AXI4 Lite bus compliant register interface Configurable video memory interface XMB Xylon Memory Bus or ARM AMBA AXI4 Compressed stencil buffer in BRAM mask over output buffer Supports pi
5. Copyright Xylon d o o 2015 All Rights Reserved Page 18 of 46 T logiREF MEDIA ZED mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 3 7 Optional Direct Rendering Manager DRM Driver The DRM Linux device driver enables user space applications to control the logiC VC ML IP core display controller in Linux operating system by using its layer and other capabilities for displaying complex and flicker free images on LCDs or monitor displays with different display resolutions Not used in the logiREF MEDIA ZED reference design Linux kernel device driver for DRM subsystem Works with the logiCVC ML v4 x and 5 x display controller IP core Fully compatible with the FreeDesktop DRM library Supports the following pixel formats 32 bit pixel format RGB32 DRGB and ARGB32_ARGB 16 bit pixel format RGB16 RGB565 and YUV4 2 2 Support provided by Xylon More info http Awww logicbricks com Products Xylon Linux logiC VC DRM driver aspx A Xylon s adaptation of the Xilinx Base Targeted Reference Design TRD for use with the ZedBoard from Avnet Electronics Marketing uses Xylon DRM driver More info http Awww logicbricks com logicBRICKS Reference logicBRICKS Design Ported Xilinx TRD to ZedBoard aspx Xylon distributes the Xilinx Base TRD for the ZedBoard kit with permission from Xilinx Inc Copyright Xylon d o o 2015 All Rights Reserved Page 19 of 46 Ewe logiR
6. controller for LCD and CRT displays which enables an easy video and graphics integration into embedded systems based on Xilinx programmable technology Though its main function is to provide flexible display control it also includes a level of hardware acceleration alpha blending panning buffering of multiple frames etc The logiCVC ML IP core can directly drive a common PC monitor through the ADV7511 High Definition Multimedia Interface HDMI transmitter available on the ZedBoard The logiREF MEDIA ZED reference design includes the logiBITBLT 2D graphics accelerator that off loads the ARM dual core Cortex A9 Core processing system and increases graphics performance The logiBITBLT IP core supports fast copying moving up and down scaling image flipping alpha blending and Porter amp Duff compositing operations between different graphics objects For 3D graphic acceleration there is the logi3D Scalable 3D Graphics Accelerator IP core designed to support the OpenGL ES 1 1 API a royalty free cross platform API for full function 2D and 3D graphics on embedded systems including consoles phones appliances and vehicles The memory subsystem is an essential part of any graphics based system It must ensure enough storage space for GUI elements and application code and a fast interface to assure enough memory bandwidth for a flicker free display output The ZedBoard includes two 16 bit DDR3 memories connected as one 512MB 32 bit memo
7. Framebuffer aspx 3 4 logiCLK Programmable Clock Generator Driver This standard Linux Common Clock Framework CCF device driver enables developers to fully control Xylon s logiCLK Programmable Clock Generator IP core from any kernel space driver through the CCF interface or user space application and drivers through the SYSFS interface The logiCLK IP core oa provides six independent clock outputs that can be controlled by the driver and dynamically reconfigured in a working Xilinx device The driver accepts the input clock frequency and desired output frequencies as input parameters and automatically programs the logiCLK configuration bits Standard Linux CCF device driver Developed for the Xylon logiCLK Programmable Clock Generator IP core Easy configuration and preset from standard Linux Device Tree file Main logiCLK IP features provides twelve independent clock outputs Six outputs configurable by the IP generics only Six outputs can be dynamically configured by the driver Available from Xylon as open source software Copyright Xylon d o o 2015 All Rights Reserved Page 17 of 46 Ewe logiREF MEDIA ZED wm a mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a More info htto www logicbricks com Products Xylon Linux logiCLK driver asox 3 5 XylonQPA Plugin for Qt 5 4 High resolution graphics content require a very high usage of the SoC processing system an
8. Linux device driver Desired pixel clock frequency is determined from the video mode and set accordingly To learn more about this IP core please read the datasheet http www logicbricks com Documentation Datasheets IP logiCLK_hds pdf 7 3 Linux Frame Buffer Changing Display Resolutions Linux Framebuffer is a standard Linux driver that abstracts the graphics hardware and allows application software to access it through a well defined interface Software designers can use it with no need to know anything about the underlying hardware IP cores in Xilinx Zynq 7000 All Programmable SoC or FPGA device The Linux Framebuffer delivered with the logiREF MEDIA ZED reference design is adopted by Xylon to fully support the logiCVC ML display controller IP core Xylon Framebuffer driver is located in Xilinx Linux Kernel github repository Latest Framebuffer driver version is provided in this installation for instructions how to configure driver and build the Linux kernel please check software Linux kernel readme txt or download Users manual document Copyright Xylon d o o 2015 All Rights Reserved Page 36 of 46 Ewe logiREF MEDIA ZED mewa mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a htto www logicbricks com Documentation Datasheets SW Xylon Linux FrameBuffer pdf Note that Xylon provides Device Tree Source dts file with IP core configuration information specific to this refe
9. User s Manual September 2 2015 Version v1 00 a 1 INTRODUCTION logiIREF MEDIA ZED is the pre verified logicBRICKS reference design that presents Xylon solutions for multimedia processing under the Linux operating system running on the Xilinx Zynq 7000 All Programmable SoC The design includes logicBRICKS IP cores for 2D and 3D graphics video and display processing and connecting of digital audio devices The included Linux demo applications demonstrate how to implement video frame grabbing audio recording and playback and how to design various graphics Human Machine Interfaces HMI including the HMI developed by the Qt a leading cross platform application and UI development framework The list of the Xylon provided and maintained Linux software drivers and libraries includes Advanced Linux Sound Architecture ALSA Video4Linux2 Linux Framebuffer driver XylonQPA 2D plugin for 2D accelerated Qt application framework and the OpenGL ES 1 1 API The reference design is prepared for the ZedBoard development kit from Avnet Electronics Marketing which is expanded by the Avnet FMC IMAGEON HDMI Input Output module Figure 1 to support external video source connections Figure 1 The ZedBoard Development Kit Running V4L2 Video Capture Demo Copyright Xylon doo 2015 All Rights Reserved Page 5 of 46 Ewe logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v
10. logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a opt qt examples declarative demos snake snake SABB runs with xylonqpa opt qt examples declarative demos snake snake SAFB runs with linuxfb Note SABB and SAFB are defined in config profile as export ABB platform xylongpa fb dev fb3 plugin evdevmouse plugin evdevkeyboard export AFB platform linuxfb fb dev fb3 plugin evdevmouse plugin evdevkeyboard 8 3 4 Running Audio Demo App In the screen console type in bash gt mnt app i2s test linux mnt test stereo 44100Hz 16bit PCM wav twav Play the test stereo 44100 sound bash gt mnt app i2s test linux tmp sound wav twav r48000 dl10 Record a test sound for 10 seconds in 48kH sampling rate 8 3 5 Running Video Capturing Demo App In the screen console type in bash gt mnt app fgtest linux conoff o dev fbl s 1280x720 Capturing video in full screen bash gt mnt app tgqtest linux pont o dev fbl s 1280x720 sc Run the video scaling cropping demo 8 4 Change the Demo Applications or Design New Applications from Scratch 8 4 1 Xilinx Development Software The logiREF MEDIA ZED reference design and Xylon logicBRICKS IP cores are fully compatible with Xilinx development tools Vivado Design Suite 2014 4 Future design releases shall be synchronized with the newest Xilinx development tools Licensed users of Xil
11. logil2S IP XACT core ESL logiREF MEDIA ZED wm a mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a Directory Purpose navigation page through the reference design doc necessary for regenerating project from TCL scripts data Design constraints files XDC Po project Vivado project related directories Poses 1 Block design GUI script and HDL wrappers lt RK e pga LL ZedBoard MEDIA reference design bitstream Fs create project html Instructions for building Vivado project from scratch eae kend Standalone bare metal drivers for logicBRICKS IP cores with documentation and examples SS WR O DSSS anus are sored Ges o l User s Manuals are stored in doc subdirectories eegen xyl oslib Xylon OS abstraction library for Xilinx Xilkernel embedded kernel use in standalone non OS applications software o readme html Navigation page through the software files and instructions for building binaries Linux kernel and device tree configuration files Qt5 XylonQPA plugin for 2D acceleration E E Linux apps Qt application HDMI demo logi3D demo Qtperf benchmarking application audio processing and input video capture and processing demo SS as WE Framebuffer fill utility Utility script for creating boot bim file Prepared binaries ready for download SDK workspace Xilinx SDK workspace folder for building bare metal applicatio
12. o o 2015 All Rights Reserved Page 35 of 46 Ewe logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a Bp RST_OUT Bp LOCKED OSC_CLK e CLKO PLLE2 BASE p gt CLK1 p gt CLK2 p gt CLK3 p gt CLK4 B CLK5 RST_N SPLB AXI4 Lite REGISTERS p gt CLKO_DRP p gt CLK1_DRP DRP INTERFACE p gt CLK2_DRP e CLK3_DRP p gt CLK4_DRP p gt CLK5_DRP PLLE2_ADV Figure 26 logiCLK Architecture The logiCLK clock generator IP core is designed to provide frequency synthesis clock network de skew and jitter reduction It has twelve independent fully configurable clock outputs Six clock outputs are dynamically reconfigurable by mean of the Dynamic Reconfiguration Port DRP The DRP gives the system designer access to the configuration and status registers of the PLL and behaves like a set of memory mapped registers One dynamically configurable clock output is connected directly to the logiCVC ML IP core s VCLK input port It means that the VCLK clock frequency can be changed while design is running and consequently the pixel clock PIX_CLK dynamically changes When the Xylon Linux Framebuffer driver is configured to use the logiCLK as a pixel clock generator the required pixel clock frequency is automatically adjusted for a particular video resolution through common clock framework connected to logiCLK CCF
13. 1 00 a The logiREF MEDIA ZED reference design is available for free and can be downloaded from htto www logicbricks com logicBRICKS Reference logicBRICKS Design Multimedia for Zyng AP SsoC ZedBoard aspx The logiREF MEDIA ZED reference design provides system designers with everything they need to develop multimedia applications on the Xilinx Zyng 7000 AP SoC It includes evaluation logicBRICKS IP cores and hardware design files prepared for Xilinx Vivado Design Suite and hardware developers can customize the provided design through the Vivado IP Integrator IPI The provided standard software drivers enable software developers to work fast and efficiently with the Zynq 7000 AP SoC without knowing the hardware implementation details and in the same way as with any SoC Aside from the logicBRICKS software support for the Linux OS Xylon also provides bare metal software drivers for non OS use and for other popular operating systems running on the Zynq 7000 AP SoC To learn more about the available software support please visit htto www logicbricks com logicBRICKS Reference logicBRICKS Design OS IP Core Support aspx 1 1 Design Deliverables 1 1 1 Hardware Design Files Configuration bitstream file for the programmable logic and the SDK export of the reference design that allows for an immediate start and software changes ZedBoard reference design prepared for the Vivado Design Suite Xylon evaluation logicBRICKS IP cor
14. 48x2048 display resolutions Support for higher display resolutions available on request Supports up to 5 layers the last one configurable as a background layer Configurable layers size position and offset Alpha blending and Color keyed transparency allows blending of video and graphics content on the screen Copyright Xylon doo 2015 All Rights Reserved Page 12 of 46 Ewe logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a Pixel layer or Color Lookup Table CLUT aloha blending mode can be set for each layer independently Packed pixel layer memory organization RGB 8bpp 8bpp using CLUT 16bpp Hi color RGB565 and True color 24bpp RGB888 YCbCr 16bpp 4 2 2 and 24bpp 4 4 4 Support for multiple display interfaces Parallel display data bus RGB or YCbCr 12x2 bit 15 bit 16 bit 18 bit or 24 bit Digital Video ITU 656 PAL and NTSC LVDS output format 3 or 4 data pairs plus clock Camera link output format 4 data pairs plus clock DVI output format Configurable CoreConnect PLBv4 6 Xylon XMB or ARM AMBA AXI4 memory interface data width 32 64 or 128 Programmable layer memory base address and stride Simple programming due to small number of control registers Supports synchronization to external parallel input Versatile and programmable sync signals timing Double triple buffering enables flicker free reproduction Display power o
15. EF MEDIA ZED mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 10 REVISION HISTORY by Initial Xylon release This demo is 1 00 a September 2 2015 D Skugor R Kon urat based on the older logiREF ZHMI FMC Xylon demo Copyright Xylon d o o 2015 All Rights Reserved Page 46 of 46
16. EF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 4 GET AND INSTALL THE REFERENCE DESIGN Xylon offers several free logicBRICKS reference designs for different hardware platforms Short descriptions of all Xylon logicBRICKS reference designs can be found at http www logicbricks com logicBRICKS Reference logicBRICKS Design aspx A quick access to specific reference design is also possible through the main downloads navigation page http www logicbricks com logicBRICKS Reference logicBRICKS Design Xylon Reference Designs Navigation Page aspx Only registered logicBRICKS users can download logicBRICKS reference designs Unregistered users will be re directed to the User Login page The download link is automatically sent by an e mail which means that the registration process requires access to the e mail account Xylon reference logicBRICKS designs can be downloaded as cross platform Java JAR self extracting installers 4 1 Registration Process Registration is very quick and simple If you experience any trouble during the registration process please contact Xylon Technical Support support logicbricks com Copyright Xylon d o o 2015 All Rights Reserved Page 20 of 46 mm Designed by XYLON logiREF MEDIA ZED Reference Design User s Manual Sulon September 2 2015 Version v1 00 a Solutions logicBRICKS Downloads Documentation
17. Induded r Xylon logicbricks com logicbricks logicvc 4 1 Repository d users dskugor hp_projects hp069 AL scratchpad hardware logicbricks src Figure 2 logicBRICKS IP Cores Imported into the Vivado Catalog Some of the latest logicBRICKS IP cores are provided in the Vivado compatible version only Please visit our web site or contact Xylon to learn more about the tools compatibility of the specific logicBRICKS IP core Copyright Xylon doo 2015 All Rights Reserved Page 9 of 46 Ewe logiREF MEDIA ZED wm up mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a The Figure 2 shows logicBRICKS IP cores imported into Vivado Design Suite while the Figure 3 shows a typical logicBRICKS IP core s configuration GUI E Ka F Re customize IP e kes P eg 2D Graphics Accelerator Bit Block Transfer 5 3 d Documentation L IP Location Show disabled ports Component Name logibitbit_0 IP core license and version Registers interface Memory settings User setting Operations Enable 8 bit anti aliased font expand operations Enable Pattern fill operations Enable Porter Duff operations Enable Global alpha in Porter Duff operations Enable Scale operations Implement bilinear scaling Line size Scale step integer part Scale step fraction Enable Move with ROP in negative direction operations Yes eSources Internal buffers implementation BRAM v or format
18. News amp Events Step 1 logicbricks com account English Register About us f Products Markets Solutions lees D Xylon logicBRICKS d SA Graphics for Xilinx Zyna 7000 Zeg tor Xtina 70702 Evatuatior 16 Get wlerence c logicBRICKS Downloads Documentation News amp Events Figure 5 Registration Process Step 2 mme Login W Shopping Cart ES e English See Register A About us aD Xylon logicBRICKS f e a mas D 2 Products Graphics for Xilinx Zynq 7000 Markets Click to get reference designs for Xilinx 20702 Evaluation Boord Solutions logicBRICKS Your account has been created Check your e mail for details about activating your account Downloads Documentation News amp Events Figure 6 Registration Process Step 3 Copyright Xylon doo 2015 All Rights Reserved If you are the registered logicBRICKS user please type in your Username and Password Unregistered users should click on the Register button which will open the registration form Step 2 Unregistered users should fill in the registration form from the Figure 5 Please take care on required form s fields Your Username is an actual e mail account used for communication with Xylon logicBRICKS Xylon accepts only valid company e mail accounts Step 3 As soon as your registration form gets accepted by Xylon you get a confirmation message Please check your e mail to find a link tha
19. REF ZGPU ZED_150421 lis Browse 1 License On and subject to the terms of this Agreement Xylon hereby grants Licensee a nonexclusive non transferable non sublicensable personal revocable and royalty free license to evaluate the SoC and FPGA IP cores softwere drivers softwere programs materials data and documentation identified in Exhibit A collectively the Licensed Materials solely for the purpose of evaluating the Licensed Materials for use with Xilinx SoC and FPGA device s and solely within Licensee s premises Licensee may install and use the Licensed Materials at one 1 development seat at only one Licensee s site Use of the Licensed Materials for any other purpose or by any third party other than Licensee is prohibited 2 Ownership The Licensed Materials are licensed not sold Except for the limited license granted in Section 1 above Licensee acknovdedges that all intellectual property rights in and to the Licensed Materials and all copies thereof are and will remain the sole property of Xylon or its suppliers and that no additional rights are granted or conferred by implication estoppel or otherwise The Licensed Materials are protected by laws and international treaty provisions covering intellectual property and industrial rights 3 Restrictions Licensee shall not decrypt decompile reverse engineer disassemble or otherwise reduce to a human perceivable form the Licensed Materials delivered in non human r
20. ataidniianeusntieaesansdnneny 7 1 2 BLS Ye a dee 7 1 2 1 Quick Evaluation with no HW and or SW Changes ccccccseeccceceeeeceeseeeceeesaeeeceesaeeeees 7 1 2 2 Develop Standalone and Linux Software no HW Changes cccccsecceseeeeteeeeeseeeeeeeeeees 7 1 2 3 Full Media SoC Customization HW and SW Changes ssessseessesensesrrresrrresrrrnsrrresrrren 8 1 3 XILINX DEVELOPMENT SOFTWARE cecceceececeececceceeceeeeceeeeceeneceeeeeeeeeeeeeeeeeseeneceeneeaeeenesenneseenes 8 2 LOGICBRICKS IP CORES siiceceicoicscsccciscedessccctsencenssvecedeesdusccensivcccouicewanceuevccwontaseaesstewescceisenceswevele 9 2 1 ABOUT LOGICBRICKS IP LIBRARY c cccececeecececeececeeeeeeceeeeeeceeeeeeceeaeseceeaeseeeeaeeeeenaeneeeneneness 9 2 2 EVALUATION LOGICBRICKS IbPCGopnEse 10 2 3 LOGICBRICKS IP CORES USED IN THIS DEN 11 2 3 1 logiWIN Versatile Video INOUE eenegen egen eessen dene eege eeneg 11 2 3 2 logil2S Audio Data Receiver TranSmitter cccccccccsececeeeeeeeeseeeeseeeeeeeeseueeseeeseneeseeeeaes 12 2 3 3 logiCVC ML Compact Multilayer Video Controller aannannannnannnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnne 12 2 3 4 logiBITBLT Block Transfer 2D Graphics ACGcelerator 13 2 3 5 logi8D Scalable 3D Graphics Accelerator ccccccccceececeeeeseeeceeeeseeeeeeeeseeeeaaeeseneeseeeeaes 14 2 3 6 logiCLK Programmable Clock Generator 14 2 4 LOGICBRICKS IP CORES FOR VupEObRpOCESoING s sensssnnnsonenenenerennrnrnrnrnrne
21. ch is located in your logiREF MEDIA ZED installation directory section 4 Software Documentation or open directly software readme html file to find relevant documentation for using the logiREF MEDIA ZED software deliverables This file contains links to software documents and instructions related to Standalone Bare Metal software Linux software 9 1 Software Instructions Standalone Software FSBL instructions Standalone software drivers code and documentation and examples zed_board_init application HDMI initialization and pixel clock setting Building standalone applications Running standalone applications with the ZedBoard setup for standalone applications 9 2 Software Instructions Linux Software Xylon provides the Linux Framebuffer driver ALSA driver V4L2 driver Qt5 XylonQPA plugin Qt HMI example and OpenGL ES 1 1 library driver for Linux Zynq toolchain Linux kernel and file system used for development and demonstrations of Xylon drivers are provisions of Xylon Linux Kernel building instructions and dts files Qt5 XylonQPA plugin general information and building instructions Xylon 3D graphics acceleration library binaries instructions for building 3D applications code examples Audio demo application Video capturing demo application Running Linux applications with the ZedBoard setup for the precompiled SD card image Copyright Xylon d o o 2015 All Rights Reserved Page 45 of 46 T logiR
22. d can cause an overall application s performance bottleneck XylonQPA plugin enables Qt 5 4 Graphics User Interfaces GUI accelerated by the logiBITBLT 2D graphics accelerator IP core that improves graphics performance and offloads the processing system for other system tasks linuxfb based Qt 5 4 plugin for Linux OS Enables 2D accelerated GUI on Xilinx Zyng 7000 AP SoC Works with the lightweight graphics engine built of logicBRICKS IP cores o logiCVC ML Compact Multilayer Video Controller o logiBITBLT Bit Block 2D Graphics Accelerator Supports the following HW accelerated graphics operations 32 bit pixel format RGB382_ DRGB and ARGB382_ARGB Solid rectangle fill Blend rectangle fill aloha supplied as 8 bit value Copy rectangle Blend rectangle Blend rectangle alpha as 8 bit value Stretch rectangle Stretch blend rectangle Stretch blend rectangle alpha as 8 bit value Support provided by Xylon More info htto www logicbricks com Products XylonQPA HMI plugin aspx 3 6 OpenGL ES 1 1 API The logi3D IP core is specifically designed for the Xilinx Zynq 7000 All Programmable SoC family SoC designers can implement attractive 3D graphics including advanced GUls by combining the logi3D with their application specific IP cores in a plug and play manner Standard OpenGL ES 1 1 API for the logi3D IP core Support provided by Xylon More info htto www logicbricks com Products Xylon OpenGL ES APIl asox
23. d with different CPUs Hardware implemented 3D graphics algorithms Occlusion culling Gouraud shading MIP MAP level of the texture per pixel Texture filtering point sampling bilinear filtering and trilinear filtering Fog function per vertex Alpha Blending Full Screen Anti aliasing Parametrical VHDL design that allows tuning of slice consumption and features set Available for Xilinx Vivado Design Suite and ISE Design Suite XPS implementation tools More info http Awww logicbricks com Products logi3D aspx Datasheet htto www logicbricks com Documentation Datasheets IP logi3D hds pdf 2 3 6 logiCLK Programmable Clock Generator The logiCLK is a programmable clock generator IP core featuring twelve independent and fully configurable clock outputs While six clock outputs can be fixed by generic parameters prior to the implementation the other six clock Outputs can be either fixed by generics or dynamically reconfigured in a SE working device The Dynamic Reconfiguration Port DRP interface gives system designers the ability to change the clock frequency and other clock parameters while the design is running by mean of a set of PLL registers Copyright Xylon d o o 2015 All Rights Reserved Page 14 of 46 Ewe logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a Supports Xilinx Zyng 7000 All Programmable SoC 7 series and Spartan 6 FPGAs Pr
24. e SD card with precompiled demos and run Note there should be no linux sad directory on the SD card but only the contents of that directory The precompiled Linux demo applications can be launched and controlled by on board push buttons or mouse and keyboard combination Qt graphics demos require use of the mouse to interact with the application and cannot be fully controlled by the push buttons Set up your ZedBoard as shown on the Figure 28 Table 4 Plug the Avnet FMC IMAGEON into the on board FMC connector Copyright Xylon d o o 2015 All Rights Reserved Page 38 of 46 Ewe logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a Set the jumpers Table 4 Connect the HDMI or HDMI to DVI video cable to a PC monitor Plug in the speakers to LINE OUT connector Plug in an external audio source e g pc sound card line out to the LINE IN connector Connect external video source e g PC graphic card output to HDMI IN on FMC IMAGEON default maximum resolution of the video source 1280x720 60Hz with HDMI or DVI to HDMI cable Connect mouse and keyboard to the USB OTG or if you don t use mouse keyboard connect the serial or Ethernet cable for remote control Insert the SD card in J12 slot Connect the power supply cable Jumpers settings for the SD boot mode Jumper Name Setting Jumper Name Setting Mio enable Table 4 Jumpe
25. e bus compliant Memory layout configurable for big or little endianness Copyright Xylon d o o 2015 All Rights Reserved Page 13 of 46 Ewe logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a Parametrical VHDL design that allows tuning of slice consumption and features set Available for Xilinx Vivado Design Suite and ISE Design Suite XPS implementation tools More info htto www logicbricks com Products logiBIT BLT aspx Datasheet htto www logicbricks com Documentation Datasheets IP logiBITBLT hds pdf 2 3 5 logi3D Scalable 3D Graphics Accelerator The logi3D Scalable 3D Graphics Accelerator IP core is a 3D Graphics Processing Unit GPU IP core developed for embedded systems based on the Xilinx Zynq 7000 All Programmable SoC The IP is designed to support the OpenGL ES 1 1 API specifications a royalty free cross platform API for full function 2D and 3D graphics on embedded systems including consoles phones appliances and vehicles Graphics Accelerator IP designed to support the OpenGL ES 1 1 API Common Profile Conformant to the AMBA AXI4 bus specifications from ARM Compatible with popular operating systems Linux Android and Microsoft Windows Embedded Compact FPGA resource effective 3D acceleration ARM Cortex A9 CPU Core with NEON runs the geometry engine and optimizes the IP s size The logi3D can be use
26. e library provides IP cores optimized for Xilinx FPGA and Zynq 7000 All Programmable SoC logicBRICKS IP cores shorten development time and enable fast design of complex embedded systems based on Xilinx All Programmable devices The key features of the logicBRICKS IP cores are Compatibility with the Xilinx Vivado Design Suite and optionally with the ISE Design Suite logicBRICKS can be used in the same ways as Xilinx IP cores and require no skills beyond general tools knowledge logicBRICKS users can setup IP core feature sets and programmable logic utilization through Xilinx implementation tools GUI Each logicBRICKS IP core comes with the extensive documentation reference design examples and can be evaluated on reference hardware platforms Xylon provides evaluation logicBRICKS IP cores to enable risk free evaluation prior to purchase Broad software support from bare metal software drivers to standard software drivers for different operating systems OS Standard software support allows graphics designers and software developers to use logicBRICKS in a familiar and comfortable way Xylon assures skilled technical support gt Search Lei ai 5 Name d s License LC Alliance Partners Xylon ZF 2D Graphics Accelerator Bit Block Transfer ou Induded logicbricks com logicbricks logibitblt 5 3 27 Audio 125 Transmitter Receiver oducti Induded icbricks com logicbricks logii2s 0 0 27 Bitmap 2 5D Graphics Accelerato
27. eadable form Licensee shall not hypothecate rent lend time share assign convey sell sublicense display distribute loan lease or vi ad gt Next o Quit Previous gt Next auit Figure 9 Installation Process Step 1 Figure 10 Installation Process Step 2 MW Xylon logiREF ZGPU ZED Installatio TT ns P Sien logiREF ZGPU ZED Installato ke le mg Designed by XYLON Mires Designed by XYLON amp Pack installation progress E userirkoncurat DesignsT oUpdate np069 AK scratchpad makeDeliverables iogiREF ZGPU ZED_156674161_outp n Files2 77 Overall installation progress 216 v Installation has completed successfully 4 iy auit Done Figure 11 Installation Process Step 3 Figure 12 Installation Process Step 4 4 2 1 Filesystem Permissions of the Installed Directory Windows 7 The reference design installed in the default path C Program Files xylon will inherit read only filesystem permissions from the parent directory This will block you in opening the hardware project file in Xilinx Vivado tools Therefore it is necessary to change the filesystem permissions for the current user to Full control preferably Copyright Xylon d o o 2015 All Rights Reserved Page 23 of 46 Ewe logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Versi
28. es logiWIN Versatile Video Input logil2S Audio Transmitter Receiver logiBITBLT Bit Block Transfer 2D Graphics Accelerator logi3D Scalable 3D Graphics Accelerator logiCVC ML Compact Multilayer Video Controller logiCLK Programmable Clock Generator 1 1 2 Software logicBRICKS standalone bare metal drivers with driver examples Zynq FSBL sources and the Xilinx SDK project custom version for standalone applications ALSA Advanced Linux Sound Architecture driver for the logil2S IP core V4L2 Video4Linux2 driver for the logiWIN IP core XylonQPA plugin for Qt 5 4 supports logiBITBLT 2D graphics accelerator Linux Framebuffer driver for the logiGVC ML IP core display controller Linux driver for the logiCLK programmable clock source HMI demo application that uses Qt application framework for GUI capabilities Copyright Xylon doo 2015 All Rights Reserved Page 6 of 46 Ewe logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a logi3D example sources and binaries OpenGL ES 1 1 library for the logi3D IP core may be provided on request 1 1 3 Binaries Precompiled SD card image for the fastest demo startup First Stage Bootloader FSBL Standalone logiCVC ML and logiBITBLT examples Linux binaries uboot devicetree dtb root file system uramdisk ulmage kernel with the Xylon Framebuffer V4L2 and ALSA drivers OpenGL ES 1 1 simple example a
29. esign Suite 2014 4 project restore Full guidelines can be found in the vivado media create project html file The vivado media xpr file from your installation directory is the Vivado Design Suite project file that opens the project Open this file with the Vivado and explore the design Figure 24 In order to re implement or change the provided reference design please go to Xylon s web site www logicbricks com and acquire evaluation licenses for the logicBRICKS IP cores see chapter 5 GETTING LOGICBRICKS EVALUATION LICENSES logiREF MEDIA ZED gis DT BE eg nas vo mon me iguee by RYLOM ue D o CH rar 0 s La as d ne ad Aen o Leen zg 9 tw zm miade EE KI Os sate om nae v Sin amp eee e A i 1s BI pen mee Aneu i gt ral a sae p Ae rat B ag ee j ame RICKS Saade gt J gt eaman mse puede ej jar m eee b mage z e zo x Sri oe im eee ee E egen air nmn ks es D E m waar D aa ge rm geneet a J ama ne rei 1 title HHHH LI i UI HAHH a 739313 h 14 HDH EEE Se TTT III Figure 24 Vivado Block Design Diagram logiREF MEDIA ZED Project to open the GUI and click on the Documentation icon to open the document logicBRICKS User s Manuals contain all necessary information about the IP cores features architecture registers m
30. from Avnet Electronics Marketing Avnet FMC IMAGEON HDMI Input Output module HDMI or DVI to HDMI video cable for video input source default maximal resolution 1280x720 60HZz HDMI or HDMI to DVI video cable for 1024x768 capable monitor The reference design supports output resolutions up to 1920x1080 60Hz but the default setting is 1024x768 60 Hz Audio playback recording Headphones Speakers Audio cable to connect ZedBoard s LINE IN connector with external audio source SD card min 256MB optional A keyboard USB Micro B cable or a control serial link USB UART or Ethernet between PC and the ZedBoard optional USB Micro B cable USB hub mouse and keyboard optional USB Micro B cable for debug UART optional Ethernet cable for Telnet connection optional Xilinx JTAG Parallel cable USB for standalone application development The majority of provided demo applications can be controlled by on board push buttons and do not require keyboard and mouse connections The reference design has been tested on the ZedBoard Rev C 8 2 Set Up the ZedBoard for Use with Precompiled Linux Demos from the SD Card Xylon provides Linux video audio Qt and 3D demo binaries in the software ready for download linux_ sd directory of the delivery If you want to run prepared demos copy the contents of the 1inux sd directory to the root directory on the FAT32 formatted SD card setup the evaluation hardware Figure 28 plug in th
31. g S X E By clicking Next you are accepting the following ang XYLON TECHNOLOGY EVALUATION LICENSE AGREEMENT RICKS Designed by XYLON FOR logiREF ZGPU ZED REFERENCE DESIGN Designed by XYLON IMPORTANT UNLESS SUPERSEDED BY A SIGNED LICENSE AGREEMENT BETWEEN YOU AND XYLON THIS XYLON LICENSE AGREEMENT AGREEMENT IS A LEGAL AGREEMENT BETWEEN YOU AND XYLON D O O PROVIDING YOU WITH THE LICENSE TO USE THE LICENSED MATERIALS UNDER THE TERMS AND CONDITIONS OF THIS AGREEMENT CAREFULLY READ THIS LICENSE AGREEMENT AGREEMENT BY CLICKING THE ACCEPT OR AGREE BUTTON OR OTHERWISE ACCESSING DOWNLOADING INSTALLING OR USING THE LICENSED MATERIALS YOU AGREE ON BEHALF OF LICENSEE TO BE BOUND BY THIS AGREEMENT LICENSEE OR YOU MEANS THE CORPORATION OR OTHER LEGAL ENTITY TO WHICH XYLON D O O A CROATIAN CORPORATION WITH AN OFFICE AT FALLEROVO SETALISTE 22 10000 ZAGREB REPUBLIC OF CROATIA XYLON HAS ISSUED THE LICENSE DESCRIBED HEREIN IF YOU DO NOT AGREE TO ALL OF THE TERMS AND CONDITIONS OF THIS AGREEMENT DO NOT CLICK THE ACCEPT OR AGREE BUTTON AND DO NOT ACCESS DOWNLOAD INSTALL OR USE THE LICENSED MATERIALS AS USED HEREIN THE EFFECTIVE DATE MEANS THE DATE ON WHICH LICENSEE CLICKS THE ACCEPT OR AGREE BUTTON IDENTIFIED ABOVE PURCHASES OR OTHERWISE ACCESSES DOWNLOADS INSTALLS OR USES THE LICENSED MATERIALS WHICHEVER OCCURS FIRST Select the installation path C Program Files x86 xylon logi
32. ght Xylon d o o 2015 All Rights Reserved Page 27 of 46 m logiREF MEDIA ZED mm Reference Design Sulon User s Manual September 2 2015 Version v1 00 a Home About us Products Markets Solutions logicBRICKS Downloads Documentation News t My logicBRICKS LZ i Obtain Evaluation License Change Password e Xylon logic BRICKS Ii Nig Request Eval IP Core d Graphics for Xilinx Zynq 7000 CR Click to get r eference designs for Xilinx ZC702 Evaluation Board SS A IP Core Activation Create Case Subscribe to Newsletter Downloads MAC Address You will be able to use evaluation license on one e development workstation Please enter your Sun Host D 3 workstation MAC address for MS Windows and Linux 00 00 00 00 00 00 platforms or Sun HostiD for Solaris platforms Figure 18 Step 3 Licensing logicBRICKS Evaluation IP Cores My logicBRICKS oe Se AE EA Obtain Evaluation License Chass Passwort A gt Xylon logicBRICKS j Graphics for Xilinx Zynq 7000 Request Eval IP Core IP Core Activation Create Case Subscribe to Newsletter Downloads License key will be created and send to your e mail address Figure 19 Step 3 Confirmation Message Step 4 You will get an e mail with the license key file and full instructions for setting up the license key and downloading the logicBRICKS IP core Please follow the provided instructions
33. gure 14 Please select the Request Eval IP Core tab in the left menu Home Aboutus Products Markets Solutions logicBRICKS Downloads Documentation News amp E My logicBRICKS Quick Info My logicBRICKS View Data an IP Cores and Design Services for Xilinx All Programmable Change Password en OTN E ess zonon Video Video ae gt a CG Request Eval IP Core Kam Processing Analytics Le by 7 SH gt x E Es ots tae IP Core Activation A H H SE ae Ai fi es SSC F ARA a bat e f iere Create Case Graphics QW KC K Situational Awareness d Your FPGA Partner in Smarter Vision Subscribe to Newsletter Downloads Welcome to logicBRICKS Registered Users Section Within this section you can Quickly get instructions on how to download install or purchase logicBRICKS products View Data View and update your user data logicBRICKS profile Quick Info Change Password Change your logicBRICKS password Knowledge Base Access and search the knowledge base Figure 14 Step 1 My logicBRICKS Navigation Page Step 2 Select the evaluation logicBRICKS IP core and click on Obtain evaluation license key link Figure 15 If you are entitled to get the evaluation logicBRICKS IP core you will be immediately asked your Ethernet MAC ID number or Sun Host ID as described in the Step 3 Figure 18 If the evaluation logicBRICKS IP cores list looks differently from the one shown on Figure 15 f
34. inx tools can use their existing software installation for the logiREF MEDIA ZED evaluation and modifications 8 4 2 Set Up Linux System Software Development Tools Set of ARM GNU tools are required to build the Linux software and applications The complete tool chain for the Zynq 7000 All Programmable SoC can be obtained from the Xilinx ARM GNU Tools wiki Copyright Xylon d o o 2015 All Rights Reserved Page 43 of 46 Ewe logiREF MEDIA ZED wm a mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a page http wiki xilinx com zyng tools Access to tools requires a valid registered Xilinx user login name and password 8 4 3 Set Up git Tools Git is a free Source Code Management SCM tool for managing distributed version control and collaborative develooment of software It provides the developer a local copy of the entire development project files and the very latest changes to the software Visit http wiki xilinx com using git to get instructions how to use Xilinx git To get the latest version of Xylon logicBRICKS software drivers for Linux operating system please visit Xylon s git https github com logicbricks Copyright Xylon d o o 2015 All Rights Reserved Page 44 of 46 Ewe logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 9 SOFTWARE DOCUMENTATION Please use the start html file whi
35. le transformations on multiple video inputs in a real time Programmable homographic transformation enables cropping resizing rotating transiting and arbitrary combinations Arbitrary non homographic transformations are supported by programmable Memory Look Up Tables MLUT More info htto www logicbricks com Products logiVIEW aspx Datasheet htto www logicbricks com Documentation Datasheets IP logiIVIEW_ hds pdf logilSP Image Signal Processing ISP Pipeline The logilSP Image Signal Processing Pipeline IP core is a full high definition ISP pipeline designed for digital processing and image quality enhancements of an input video stream in Smarter Vision embedded designs based on Xilinx Zyng 7000 All Programmable SoC and 7 series FPGA devices More info http Awww logicbricks com Products logiISP aspx Datasheet http www logicbricks com Documentation Datasheets IP logilISP_hds pdf Copyright Xylon d o o 2015 All Rights Reserved Page 15 of 46 Ewe logiREF MEDIA ZED wm a mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 3 LINUX SOFTWARE DRIVERS Get the latest software drivers versions at https github com logicbricks 3 1 Video4Linux Driver The logiWIN IP core and the logiWIN V4L2 software driver enable easy implementations of video capturing applications running on the Xilinx Zyng 7000 AP SoC or FPGA device A comprehensive logicBRICKS software suppo
36. logiREF MEDIA ZED Xylon logicBRICKS Multimedia Reference Design for Xilinx Zynq 7000 All Programmable SoC based ZedBoard from Avnet Electronics Marketing User s Manual Version 1 00 a logiREF MEDIA ZED_v1_00_a docx Ewe logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a mm Designed by XYLON All rights reserved This manual may not be reproduced or utilized without the prior written permission issued by Xylon This publication has been carefully checked for accuracy However Xylon does not assume any responsibility for the contents or use of any product described herein Xylon reserves the right to make any changes to product without further notice Our customers should ensure to take appropriate action so that their use of our products does not infringe upon any patents Copyright Xylon doo logicBRICKS is a registered Xylon trademark All other trademarks and registered trademarks are the property of their respective owners Copyright Xylon d o o 2015 All Rights Reserved Page 2 of 46 ee TogiREF MEDIA ZED mam A mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 1 INTRODUCTION BEE 5 1 1 DESIGN D ELMERARBLES a A a N A A a aaan a AA AMA M A a aA N 6 tihi Hardware Re IT 6 1 1 2 SOMWAN CN 6 Wo TIVES S a acacia saracatacnndiecasamcicdosaesineasapsieinatentnieugradeteuecdi
37. n sequencing control signals Parametrical VHDL design that allows tuning of slice consumption and features set Available for Xilinx Vivado Design Suite and ISE Design Suite XPS implementation tools More info htto www logicbricks com Products logiC VC ML aspx Datasheet htto www logicbricks com Documentation Datasheets IP logiCVC ML_hds pdf 2 3 4 logiBITBLT Block Transfer 2D Graphics Accelerator This 2D graphics accelerator speeds up the most common GUI operations and off loads the processor The logiBITBLT transfers graphics objects from one to another part of system s on screen or off screen video memory and performs different operations during transfers such as ROP2 raster operations bitmap scaling stretching and flipping Porter amp Duff compositing rules or transparency Supports Xilinx Zyng 7000 AP SoC and all Xilinx FPGA families Available SW drivers for Linux and Microsoft Windows Embedded Compact OS Supports move operations in positive and negative direction Supports 16 different ROP2 operations Integrated bitmap flipping and optional up down scaling Porter Dutf composition with without global alpha Color keyed transparency source and destination Anti aliased 8 bit font expansion Pattern fill with 8x8 pixels patterns Solid fill with any of the supported color formats Supported color formats RGB8 ARGB8 RGB16 ARGB16 RGB24 and ARGB24 Control of pixel alpha blending factors ARM AMBA AXI4 and AXI4 Lit
38. nd Xylon 3D demo Pre compiled demo applications showing 2D and 3D accelerations HMI audio recording playback and input video capture and processing 1 2 Usage Modes The logiREF MEDIA ZED reference design can be used in different ways which are listed in this paragraph and thoroughly explained throughout this document 1 2 1 Quick Evaluation with no HW and or SW Changes Download and install the logiREF MEDIA ZED reference design see chapter A GET AND INSTALL THE REFERENCE DESIGN Setup the demo hardware and use the provided SD card image to run precompiled demo applications paragraph 8 2 Set Up the ZedBoard for Use with Precompiled Linux Demos From the SD Card 1 2 2 Develop Standalone and Linux Software no HW Changes Download and install the logiREF MEDIA ZED reference design chapter A GET AND INSTALL THE REFERENCE DESIGN Setup the demo hardware paragraph 8 2 Set Up the ZedBoard for Use with Precompiled Linux Demos From the SD Card Use the provided Zyng 7000 AP SoC as it is binaries Follow instructions for working with logicBRICKS stand alone bare metal or Linux drivers please get the full instructions in the start htm file from your installation root directory Develop software applications prior to the availability of the actual target system Product is based on a published Khronos specification and is expected to pass the Khronos Conformance Testing Process Current conformance status can be fo
39. ns Table 1 Explanation of Directories in logiREF MEDIA ZED Reference Design Copyright Xylon d o o 2015 All Rights Reserved Page 25 of 46 Ew logiREF MEDIA ZED wom w mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 5 GETTING LOGICBRICKS EVALUATION LICENSES Please note that the logiREF MEDIA ZED reference design installation provides you with everything needed to run the provided demo applications or to use change the provided software source code However if you wish to make any changes on the hardware design files such as to remove add or reconfigure some of the provided IP cores you have to obtain evaluation IP licenses from Xylon The following pages describe the procedure for getting and licensing evaluation logicBRICKS IP cores that takes several minutes to complete If you experience any trouble during this process please contact Xylon Technical Support support logicbricks com You must be logged in to the Xylon website using your logicBRICKS user name and password to get an access to evaluation logicBRICKS IP cores Unregistered users will be re directed to the User Login page Paragraph 4 1 Registration Process explains this simple registration procedure Step 1 Logged in users get the My logicBRICKS tab in the main www logicbricks com navigation menu Click on it and you will be directed to your main web page for communication with Xylon logicBRICKS Fi
40. odes of operation etc To access logicBRICKS IP core user s manuals double click on the specific IP core Copyright Xylon d o o 2015 All Rights Reserved Page 33 of 46 Ewe logiREF MEDIA ZED wm a mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 7 VIDEO OUTPUT CLOCKING The logiREF MEDIA ZED reference design uses Xylon logiCVC ML IP core to drive inputs into an Analog Devices ADV7511 HDMI Transmitter which is configured to display the 1080p60 resolution 1920x1080 16 bit YCbCr 4 2 2 image on a regular PC monitor The ADV7511 HDMI Transmitter driver is integrated with the Xylon Framebuffer software driver for the Linux OS ADV7511 HDMI Transmitter driver is also provided for the bare metal applications see the software SDK workspace zed board init application Xylon logicBRICKS IP cores and provided software can be used in many different hardware setups and with many different display types Therefore in order to be able to fully utilize the graphics provided with the reference design for the ZedBoard and to properly use logicBRICKS products in other hardware setups designers should understand the video clocking scheme implemented in the logiREF MEDIA ZED reference design 7 1 logiCVC ML Standard Display Resolutions and Pixel Clock For full information about setting up the display interface controlled by the logiCVC ML Compact Multilayer Video Controller IP core plea
41. on v1 00 a To change the user permissions for C Program Files xylon directory and all of its subdirectories right click on the C Program Files xylon directory and select Properties Under Security tab select Edit Select Users group in the list and check Full control checkbox in the Allow column 4 3 Directory Structure Figure 13 gives a top level view of the directories and files included with the logiREF MEDIA ZED reference design for the ZedBoard development kit Table 1 explains the purpose of directories Please use the start html file located in the installation root directory as a jump start navigation page for exploring the reference design m INSTALLATION ROOT doc vivado_media hardware software a Ea S start html project e evaluation licenses pdf 3 m drivers Sal Linux vivado_media xpr i logiBITBLT SW files Get makeBin Se kl data rt logiCLK SW Files Ready for test logiCVC SW Files scripts et logiWIN SW Files G Sal SDK_workspace a A SW SERVICES readme html Sal ered FF xyl_oslib keng m logicbricks hdl Li kel ui lib create_project html Sal Sal logiBITBLT IP XACT core logi3D IP XACT core Sal logiCLK IP XACT Ges core logiWIN IP XACT ae core Figure 13 Directory Structure Copyright Xylon d o o 2015 All Rights Reserved Page 24 of 46 logiCVC ML IP XACT core
42. ontrol bits in the DTYPE and CTRL registers please refer to the logiCVC ML User s Manual paragraph 10 2 Register Description A special clock module is needed outside of the logiCVC ML IP core to support the functionality of adjustable PIX_CLK clock frequencies changeable display resolutions This reference design uses Xylon s auxiliary IP core the logiCLK Programmable Clock Generator IP core To learn more about this IP core please read the datasheet http www logicbricks com Documentation Datasheets IP logiCLK hds pdf i GPI 4 0 GPO 4 0 SS REGISTERS z EN V EN BLIGHT EXTERNAL PARALLEL INPUT clk ctrl data VIDEO MEMORY E CURR_VBUFF 9 0 ACCESS BLOCK HSYNC E_NEXT_VBUFF 9 0 I SYNC VSYNC E SW VBUFF 4 0 lt GENERATOR ER II er BLANK E SW_GRANT 4 0 CVC_CURR_VBUFF 9 0 a E VMEM MEMORY B PLB XMB AXI ADDRESS NEE RENGE GENERATOR DS MULTILAYER OUTPUT ALPHA STANDARD VEER ie BLENDER CONVERTER LVDS _CLK LVDS_CLKN GE ACCE ITU_CLK_IN eens CONTROL C LVDS Camera link PARALLEL EE ITU656 DVI PLLVCLK_LOCKED INTERRUPT Figure 25 logiCVC ML Architecture 7 2 Utility Clock Module Alongside graphics logicBRICKS IP cores Xylon has included a small utility clock module the logiCLK Programmable Clock Generator IP core to enable users to easily change display resolutions from the logiREF MEDIA ZED reference design see Figure 26 Copyright Xylon d
43. ontroller Figure 22 shows an example architecture featuring only the logiCVC ML display controller IP core Such a configuration provides no video and audio processing or graphics acceleration in the programmable logic and all graphic contents must be fully drawn by the Processing System PS The consumption of programmable logic resources is minimal The Figure 26 shows a clocking structure detail please see the chapter 7 VIDEO OUTPUT CLOCKING Copyright Xylon d o o 2015 All Rights Reserved Page 31 of 46 m logiREF MEDIA ZED mm Reference Design Sulon Designed by XYLON User s Manual 6 2 Memory Layout 0 MB logiBITBLT logiWiIN 256 MB logiCVC layer 2 256MB 25920 kB logiCVC layer 3 256MB 32400 kB logiCVC layer 1 256MB 58320 kB logiCVC layer 0 256MB 84240 kB logi3D 512 MB Figure 23 logiREF MEDIA ZED Memory Layout IP Core Memory Access Memory Stride Display Memory MB pixels HxV pixels logiCVC 256 511 2048 up to 1920x1080 logiBITBLT 0 511 2048 e logi3D 256 511 2048 E logiWIN 0 511 2048 up to 1280x720 Table 2 logicBRICKS IP Cores Memory Addressing Copyright Xylon doo 2015 All Rights Reserved Page 32 of 46 rm logiREF MEDIA ZED mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 6 3 Restoring Full SoC Design from Xylon Deliverables Xylon provides all necessary design files and TCL scripts to enable full Vivado D
44. or example as the list presented by the Figure 16 please fill in and submit the request form Figure 17 and allow us some time to process your request Scroll down to get to the request form For instructions how to find your Ethernet MAC or host ID please visit http Awww logicbricks com Documentation Article aspx articleID KBA 01186 MOJXKD Copyright Xylon d o o 2015 All Rights Reserved Page 26 of 46 7 logiREF MEDIA ZED mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a Home Aboutus Products Markets Solutions logicBRICKS Downloads Documentation News amp E My logicBRICKS a Evaluation License Change Password EN Xylon logicBRICKS Request Eval IP Core Graphics for Xilinx Zynq 7000 ous rs IP Core Activation LU Click to get reference designs for Xilinx ZC 702 Evaluation Board zs Create Case Click to get the IP license key Subscribe to Newsletter iiine Status Downloads logiCVC ML EVAL 1M Not Activated Obtain evaluation license key logWIN EVAL 1M Not Activated Obtain evaluation license key logiBITBLT EVAL 1M Not Activated Obtain evaluation license key Figure 15 Step 2 Selecting logicBRICKS IP Core for Licensing Home About us Products Markets Solutions logicBRICKS Downloads Documentation News amp E My logicBRICKS TE Evaluation License Change Password P V d So gt D Xylon logicBRICKS 3 A Reques
45. ord select master or slave Configurable active clock edge Supports three different justification modes normal corresponds to the mode specified in the 12S specification by Philips left and right Configurable TX and RX FIFO depth from 512 up to 4096 samples L R word Supports word length up to 16 bits ARM AMBA AxXI4 Lite bus compliant Parametrical VHDL design that allows tuning of slice consumption and features set Available for Xilinx Vivado Design Suite and ISE Design Suite XPS implementation tools Available Linux ALSA driver More info http Awww logicbricks com Products logil2S aspx Datasheet hitp www logicbricks com Documentation Datasheets IP logil2S hds pdf 2 3 3 logiCVC ML Compact Multilayer Video Controller The logiCVC ML IP core is an advanced display graphics controller for LCD and CRI displays which enables an easy video and graphics integration into embedded systems with Xilinx Zyng 7000 All Programmable SoC and FPGAs This IP core is the cornerstone of all 2D and 3D GPUs Though its main function is to provide flexible display control it also includes hardware acceleration functions three types of aloha blending panning buffering of multiple frames etc Supports Xilinx Zyng 7000 AP SoC and all FPGA families Display controller IP core for LCD and CRT displays can be tailored for special display types Available SW drivers for Linux Android QNX and Microsoft Windows Embedded Compact 64x1 to 20
46. ovides 12 independent clock outputs that can be configured by generic parameters 6 outputs can be dynamically configured through the DRP interface 6 outputs can be configured by generics only Input clock frequency range depends on the used device s speed grade Spartan 6 19 540 MHz 7 series 19 1066 MHz Output clocks frequency range Spartan 6 3 125 400 MHz 7 series 6 25 741 MHz Configurable ARM AMBA AXI4 Lite and CoreConnect PLBv4 6 compliant registers interface software support for Linux and Microsoft Windows Embedded Compact operating systems Parametrical VHDL design that allows tuning of slice consumption and features set Available for Xilinx Vivado Design Suite and ISE Design Suite XPS implementation tools More info http Avww logicbricks com Products logiCLK aspx Datasheet hitp www logicbricks com Documentation Datasheets IP logiCLK_hds pdf 2 4 logicBRICKS IP Cores for Video Processing Xylon offers several logicBRICKS IP cores for video processing on Xilinx Zynq 7000 All Programmable SoC and FPGA programmable devices which can be used as extensions to Xylon logicBRICKS IP cores demonstrated by the logiIREF MEDIA ZED reference design All logicBRICKS IP cores support ARM AMBA AXI4 on chip bus and can be easily mixed together or with Xilinx and third party IP cores logiVIEW Perspective Transformation and Lens Correction Image Processor Removes fish eye lens distortions and executes programmab
47. r A O A ETE E E 35 7 3 LINUX FRAME BUFFER CHANGING DISPLAY RESOLUTIONS asaensnnonesennnrnnnnnrnrnrnernrrrnerrrrrnen 36 see e Le Eo By EEN 38 8 1 REQUIRED HARDWARE ssasasananannnennnennnnnnononnrnrnrnrrrn rnrn ennan ArAnA REAA EEE EEEE DEDEDE RARER EREEREER EPAD E CEE ennnen 38 8 2 SET UP THE ZEDBOARD FOR USE WITH PRECOMPILED LINUX DEMOS FROM THE SD CARD 38 Copyright Xylon doo 2015 All Rights Reserved Page 3 of 46 ee TogiREF MEDIA ZED mam A mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 8 3 RUNNING PRECOMPILED DEMOS FROM THE SD CGApplMAaGE 40 8 3 1 BootUp Menu 41 83 2 RUNNING sD Domo ADS EN 42 8 3 3 RUNNING QT Demo Apps 42 8 3 4 Running Audio DEMO App 43 8 350 Running Video Capt rnng Demo ADD NEE 43 8 4 CHANGE THE DEMO APPLICATIONS OR DESIGN NEW APPLICATIONS FROM SCRATCH nan n nnn 43 8 4 1 Xilinx Development Software nannoannnennnennnnnennnnnsnrnnerrnnrrrrrrrnrrrnnrrenrrnnrrsnrrnnrrnnrrnnrenenen 43 8 4 2 Set Up Linux System Software Development Tools 43 oA Sr UPOL TOOG eai EEE eee E ee rere 44 9 SOFTWARE DOCUMENTA TION WE 45 9 1 SOFTWARE INSTRUCTIONS STANDALONE SOFTWARE ssicnninsstcnisostcmmstsntsensnunaaimearbinaiansamctnnth 45 9 2 SOFTWARE INSTRUCTIONS LINUX SOFTWARE EE 45 10 REVISION HISTOR E 46 Copyright Xylon doo 2015 All Rights Reserved Page 4 of 46 Ewe logiREF MEDIA ZED wm p mm Reference Design Sulon Designed by XYLON
48. r oduc Induded icbricks com logicbricks logibmp 0 0 P DC Bus Master Control ller Production Induded icbricks com logicbricks logii2c 0 0 RE Oe EE TC EE E TE Stee P Perspectiv ve Tran nsfor mation and Lens Correction Image Proce essor Gg AXI4 Stream Production Induded logicbricks com logicbricks logiview 0 0 7 F Scalable 3D Graphics Accelerator AXI4 Production Induded logicbricks com logicbricks logi3d 1 5 3 SD Card Host Controller AXI4 Production Induded logicbricks com logicbricks logisdhc 0 0 Automotive amp Industrial HL AXI Infrastructure BaseIP gt Basic Elements Communication amp Networking e Debug amp Verification Digital Signal Processing Embedded Processing 4 Ze a s ab Multilayer Video Controller 4 1 Rev 2 ces AXI4 The logiCVC ML IP core is an EH ced display aa raphic controller that e ebe an easy video and graphics integration into embedded systems with the Xilinx Zyng 7000 AP SoC and FPGA can be used as a standalone graphics IP core or as a part of larger graphics systems al end other Xylon logicBRICKS IP cores gates ed by the Xilinx VW aon et ator IPI integrated software solution and designers familiar with this tool ough IP drag and dro saci interface The logiCVC ML comes readya to use mm design Higher resolutions are available on request Currently Xylon offers Z software drivers for use with Linux Android and Microsoft Windows Embedded Compact operating ra Production cense
49. rence Design User s Manual September 2 2015 Sulon Version v1 00 a September 2 205 Version v1 0 8 log iREF MEDIA ZED reference design by Xuylon Use five user buttons Clocated on the opposite end of zed power switch or corresponding keys on USE keyboard to choose which demo to run Actions to keys mapping North button south button West button East button Up arrow key Up arrow key Enter key Q letter key Following demos are available QT graphic examples ALSA examples YideotLinux examples City navigation Rotating portrait Cluster demo Menu simple demo Dynamic scene Color animation anake sane game Weather anchor layout tper f Flay a test sound Record sound Flay the recorded sound Video capturing demo scale crop demo Figure 29 logiREF MEDIA ZED Boot Up Graphics Menu 8 3 2 Running 3D Demo Apps In the screen console type in mnt 3dDemo mnt 3dDemo mnt 3dDemo mnt 3dDemo elf a starts elf b starts elf c starts elf f starts Photo album demo Avionics demo City flying demo Auto Instrument Cluster demo These commands start the demo Control demos by keys A or D left right E select and Q quit In some demos you can also use keys W X R and F CTRL C key combination stops the demo 8 3 3 Running QT Demo Apps In the screen console type in Copyright Xylon d o o 2015 All Rights Reserved Page 42 of 46 Ewe
50. rence design When using the Linux kernel with this reference design user must use the Xylon dts dtb files located in the software Linux kernel linux xlnx v2014 4 directory instead of the ones provided by Xilinx Figure 27 shows an excerpt from Xylon dts file logicve O logicvee40030000 4 compatible xylon logicvc 4 00 a reg lt 0x40030000 Ox6000 gt InterrupU parenc EE d scugie UP interrupts lt 0 57 05 background layer bits per pixel lt 32 gt background layer type rgb hsync active low VSYNC active Low Size position pixel stride lt 2048 gt layer O address lt 0Ox138F4000 gt buffer offset lt 1080 gt bits per pixel lt 32 gt type rgb transparency pixel be layer 1 address lt 0x11FA4000 gt buffer offset lt 1080 gt bits per pixel lt 32 gt type rgb transparency layer be layer 2 address lt 0x1l0000000 gt buffer offset lt 1080 gt bits per pixel lt 32 gt type rgb transparency layer be layer 3 address lt 0x11950000 gt Figure 27 Video Mode Definitions An Excerpt from the Linux dts Copyright Xylon d o o 2015 All Rights Reserved Page 37 of 46 Ewe logiREF MEDIA ZED wm a mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 8 QUICK START 8 1 Required Hardware A full evaluation of the provided reference design requires ZedBoard development kit
51. rnrnrnrrrnrrrnrnrnrnne 15 3 LINUX SOFTWARE DRIVERS ccccceececeeceeseceececeeceeeeeueeesuseesuseeeeseuseseuseueuseesaseuseseueeseusensaes 16 3 1 VIDE O4LNUX DRIVER ate ees etn espns dane arcadia N EEEE 16 3 2 ADVANCED LINUX SOUND ARCHITECTURE ALSA DIER 16 3 3 SC IER PY E 17 3 4 LOGICLK PROGRAMMABLE CLOCK GENERATOR DRIVER ceecececeecececeececeeeececeeeeseeeeeeneeenaeees 17 3 5 XYLONQPA PLUGIN FOR QT BA 18 3 6 OPENGLES E E EE 18 3 7 OPTIONAL DIRECT RENDERING MANAGER DRM DER 19 4 GET AND INSTALL THE REFERENCE DESIGN ccccecsecsssecseeeneceseecuseecnseeenecesnecesesens 20 4 1 REGISTRATION PROCES EE EES EE EE EE EE 20 4 2 INSTALLATION HpOCESg r tnra rA rA rAr A RARER EAE AEEEEEEEA DEDEDE RARER EnEn nnee 22 4 2 1 Filesystem Permissions of the Installed Directory Windows Z A 23 4 3 DIRECTORY Ren BI 24 5 GETTING LOGICBRICKS EVALUATION LICENSESG oc ccc eceneececeseeseceseeseseseeseeeeeneeeeeans 26 LOGIREF MEDIA ZED DESIGN winicicceienccdecedicedncescedewscadedecesncedncestcedexesccedvecniedeusetvedauedeeedauceseeees 29 6 1 DESIGN CUSTOMIZATION EE 30 6 2 MEMORY WEA En 32 6 3 RESTORING FULL SOC DESIGN FROM XYLON DELIVERABLES ceceecececeeceeeeceseeceeneceeeeeeeness 33 7 VIDEO QUTPUT CLOCKING isiciccvictcdecpciccdececiisiewesacewtneanesuensasesesesdescencanewacnceduwemnepacesgunpaeesmueanvaad 34 7 1 LOGICVC ML STANDARD DISPLAY RESOLUTIONS AND PIXEL CGLOCk 34 7 2 OTLET GLOSK NODULE arrena
52. roller implemented in the Zyng 7000 SoC programmable logic The logiWIN Versatile Video Input IP core implements the frame grabbing feature This IP core receives the video stream from the Avnet FMC IMAGEON board ADV7611 HDMI Receiver which can be further scaled cropped and stored into the video memory implemented in the DDR3 SDRAM memory The HDMI Receiver receives the HDMI or DVI video and transforms it into 1TU1120 video standard for logiWIN video input This is an 8 bit parallel YUV video with embedded syncs Maximum supported input video resolution is 128x720 60Hz high definition video The Zedboard audio codec is controlled through the logil2S audio transmitter receiver IP core The audio codec connects to microphone and hedphones loudspeakers through the ZedBoard connectors In the logiREF MEDIA ZED reference design a LINE IN input connector on the ZedBoard J8 is used as input for audio source LINE OUT output connector on the ZedBoard J6 is used for processed audio output The audio codec on the ZedBoard can be configured to use MIC input connector on the ZedBoard J7 for microphone input and HPH OUT output connector J5 for audio output to headphone set Graphics features like bitmaps operations aloha blending overlays rotations scaling LCD display control 3D rendering and others are supported by three separated logicBRICKS IP cores The logiCVC ML Compact Multilayer Video Controller IP core is an advanced display graphics
53. rs Set Up for Booting from the SD Card Copyright Xylon d o o 2015 All Rights Reserved Page 39 of 46 Ewe logiREF MEDIA ZED pomp mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a VIDEO OUTPUT HDMI DVI IMAGEON FMC reg bn t VIDEO INPUT we e KM 5 ti USB OTG KEYBOARD MOUSE wi UL ALI U CETTE eee ore eck Figure 28 The ZedBoard Rev C Setup for the logicBRICKS Reference Design For full explanation of the ZedBoard s features and settings please check the documentation provided with the kit and visit http zedboard org support documentation 1521 8 3 Running Precompiled Demos from the SD Card Image To quickly start precompiled Linux demos make sure that you have the SD card with the precompiled image plugged in the board s slot and all jumpers setup as described in the previous paragraph To control the precompiled demos you can use four user push buttons out of five available placed in the shape of a cross on the ZedBoard presuming that video output HDMI port is located on the North side use North and South buttons for iterations through examples West button for starting the selected example East button for exiting the example Copyright Xylon d o o 2015 All Rights Reserved Page 40 of 46 Ewe logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a
54. rt for Linux operating system enables software designers to use graphics logicBRICKS IP cores with no need to know anything about the underlying hardware IP cores Enables easy video capture under Linux OS Can be used with the Xilinx All Programmable devices Developed for the Xylon logiWIN Versatile Video Input IP core Supports input image cropping up down scaling picture positioning start stop video Supported video inputs RGB and YUV4 2 2 ITU656 PAL and NTSC and ITU1120 Supported video outputs V4L2 PIX_FMT_RGB565 V4L2 PIX_FMT_RGB32 V4L2 PIX_FMT_YUYV Available from Xylon as open source software More info htto www logicbricks com Products Xylon Video4Linux logiWIN Driver aspx 3 2 Advanced Linux Sound Architecture ALSA Driver Xylon ALSA software driver enables an easy use of the logil2S Audio Transmitter Receiver IP core in Xilinx Zyng 7000 AP SoC and FPGA based systems running Linux OS The logil2S IP core is compatible with the 12S serial bus interface standard used for connecting digital audio devices This IP core enables easy implementations of the audio recording and playback functionality Enables audio recording and playback in Xilinx All Programmable devices Developed for the Xylon logil2S Audio Transmitter Receiver IP core Supported functions Play TX and Record RX 16 bit stereo PCM samples Supported PCM sample rates 8 kHz 192 kHz Configurable HW FIFO levels to fine
55. ry module The memory is connected to the hard memory controller in the Zynq 7000 AP SoC Processor Subsystem PS 6 1 Design Customization The provided reference design can be customized within the Xilinx Vivado IP Integrator tool in different ways Please note that any changes in the provided reference design require evaluation IP Copyright Xylon doo 2015 All Rights Reserved Page 30 of 46 m logiREF MEDIA ZED mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a licenses for logicBRICKS IP cores The licensing process is described in the chapter 5 GETTING LOGICBRICKS EVALUATION LICENSES Possible design changes include Change logicBRICKS IP settings i e change number of graphics layers controlled by the logiCVC ML display controller IP core Remove some logicBRICKS IP cores Le remove all graphics accelerators and use only the logiCVC ML display controller IP core or remove the 3D acceleration and work with the 2D graphics only etc Add more instances of logicBRICKS IP cores Le add second logiCVC ML IP core and drive two displays with different graphics content Add your own or third party IP cores to various combinations of logicBRICKS IP cores gt ep Can UART SPI CAN 12C L as sn pn wn BR Cla aen wi ww eicht E Processing System ADV7511 BI logicvc ML Processing system 7 DISPLAY Figure 22 A Minimal Zynq 7000 AP SoC Display C
56. se refer to the logiCVC ML Users Manual This chapter focuses on the pixel clock generation and control since it depends on the overall system s architecture to a great extent Table 3 shows required pixel clock s frequencies for several popular display resolutions Properly implemented display interface must respect the expected display signals timings which are based on the requested pixel clock Wrong pixel clock causes wrong timings on the display interface and as a consequence wrong or missing picture on the display It is visible from the table that graphic controller must be able to source different pixel clocks in order to support multiple display resolutions HD 720p 1280x720 HD 1080i 1920x1080 SXGA 1280x1024 HD1080p 1920x1080 Table 3 Pixel Clock Common Video Resolutions The logiCVC ML internal structure is shown on the block diagram on Figure 25 The VCLK video clock signal controls all circuits inside the logiGVC ML IP core except the video memory subsystem Copyright Xylon d o o 2015 All Rights Reserved Page 34 of 46 Ewe logiREF MEDIA ZED wm up mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a AXI4 related circuits and registers AXI4 Lite The VCLK clock signal frequency should be set equal to the pixel clock needed for specific display resolution Table 3 The pixel clock output PIX_CLK is proportional to the VCLK clock input and to c
57. sign Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 6 LOGIREF MEDIA ZED DESIGN GigE Flash QSPI el WI UART SPI ARM e CAN I2C TETT WS GPIO tex Controller NIE PLAY Intelligent Processors by ARM Processing System Xilinx Zynq 7020 Programmable Logi HDMI DVI AX 4 Lite ADV7511 logiCVC ML AU S logiBITBLT S 2D Graphics T Accelerator m O W l logil2S logi3D ADAU1761 Audio 12S 3D Graphics AUDIO CODEC TX RX Accelerator Processing system 7 VIDEO IN HDMI DVI logiWIN gt ik Versatile Video Input MIXED 3RD PARTY Figure 21 logiREF MEDIA ZED Reference Design Block Diagram logiCLK Clock Generator Module and other utility IP cores are not shown Figure 21 shows the simplified block diagram of the logiREF MEDIA ZED reference design Design clocking structures are not shown Please read the chapter 7 VIDEO OUTPUT CLOCKING and explore the design files to understand the clocking structure The logiREF MEDIA ZED reference design provides a full framework for development of multimedia embedded applications based on the Xilinx Zyng 7000 AP SoC logicBRICKS IP cores Copyright Xylon d o o 2015 All Rights Reserved Page 29 of 46 Ewe logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a work as a video frame grabber graphics hardware accelerators display and audio cont
58. t Eval IP Core K SD i ilinx N D7 Graphics for Xilinx Zynq 7000 IP Core Activation UY Click to get reference designs for Xilinx ZC702 Evaluation Board Create Case Subscribe to Newsletter Name Status Downloads logiC VC ML EVAL 1M Activated Already activated IP licenses logiWVIN EVAL 1M Activated logiBITBLT EVAL 1M Activated Figure 16 Step 2 A List of Already Activated logicBRICKS IP Licenses logiJART EVAL 1M Not Activated Obtain evaluation license key Your company can get one evaluation license per product per year If your company already used evaluation license in last year you cannot obtain evaluation license automatically In that case please fill form with request for additional evaluation license Subject logiCVC ML IP Core Evaluation License NRS KERS co SEA NN CH IP Core logic VC ML EVAL 1M l Message Text I would like use your evaluation IP core wit h the ssReesg development kit Figure 17 Step 1 Licensing logicBRICKS Evaluation IP Cores Step 3 Evaluation logicBRICKS IP licenses are tied to your Ethernet MAC address or Sun Host ID Figure 18 and can be used on a single working station only Fill in this address and click on the Request License Key button You should get the confirmation message Figure 19 If you do not get the confirmation message please contact Xylon Technical Support support logicbricks com Copyri
59. t activates your logicBRICKS account If you do not get the confirmation message in several minutes please check your Spam Filter or Junk Mail directory If you have not received the confirmation message please contact Xylon support Page 21 of 46 Ewe logiREF MEDIA ZED wm p mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a Home Aboutus Products Markets Solutions togicBRICKS Downloads Documentation News amp Events Activate Account Solutions logicBRICKS Downloads You have successfully activated your account Documentation Figure 7 Registration Process Step A mme Velcome ggalic vionnr Log Ou Shopping Cart e A Home Contacts Stemap 7 Legal Notice Support Figure 8 Registration Process Step 5 4 2 Installation Process Graphics and vg tome Video for Ki E AC A Zynq 7000 Ain i E vO yng About us J Xylon logicBRICKS S f vd EPP and F s Products Graphics for Xilinx Zynq 7000 gt Markets Click to get reference designs for Xilinx ZC 702 Evaluation Board Ven SIE X OY Step 4 Click on the logicBRICKS web account activation link in the received e mail and you will get the confirmation status message Please login to proceed Step 5 As soon as you select an appropriate logicBRICKS reference design and installer for your operating system from the Downloads Navigation Page link bello
60. tune system s interrupt load Copyright Xylon d o o 2015 All Rights Reserved Page 16 of 46 Ewe logiREF MEDIA ZED wm up mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a Auto detect Master Slave TX RX streaming configurations Available from Xylon as open source software More info htto www logicbricks com Products Xylon ALSA logil2S Audio Driver aspx 3 3 Framebuffer Driver Linux Framebuffer is a standard Linux driver that abstracts the graphics hardware and allows application software to access it through a well defined interface Software designers can use it with no need to know anything about the underlying hardware IP cores in Xilinx Zyng 7000 All Programmable SoC or FPGA device The Linux Framebuffer enables easy display control by the logiCVC ML display controller IP core Linux kernel driver Developed for the Xylon logiCVC ML Compact Multilayer Video Controller IP core Supports logiCVC ML multilayering capabilities Some of the supported display controller s features Resolutions from 64x1 up to 2048x2048 up to 5 layers with programmable blending features packed pixel layer memory organization RGB and YUV formats Double triple buffering for flicker free reproduction Support for different pixel clock sources Enables multi display system configurations Available from Xylon as open source software More info htto www logicbricks com Products Xylon Linux
61. und at www khronos org conformance Copyright Xylon d o o 2015 All Rights Reserved Page 7 of 46 Ewe logiREF MEDIA ZED wm ep mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 1 2 3 Full Media SoC Customization HW and SW Changes Download and install the logiREF MEDIA ZED reference design chapter 4 GET AND INSTALL THE REFERENCE DESIGN Setup the demo hardware paragraph 8 2 Set Up the ZedBoard for Use with Precompiled Linux Demos From the SD Card Obtain logicBRICKS evaluation licenses from Xylon chapter 5 GETTING LOGICBRICKS EVALUATION LICENSES Use the provided Zyng 7000 AP SoC to add or remove more logicBRICKS IP cores and or third party IP cores or to change logicBRICKS IP settings through the GUI Implement new Zynq 7000 AP SoC design Develop software by following instructions listed in the start bim file from your installation root directory 1 3 Xilinx Development Software The logiREF MEDIA ZED reference design and Xylon logicBRICKS IP cores are fully compatible with Vivado Design Suite 2014 4 Future design releases shall be synchronized with the newest Xilinx development tools Copyright Xylon doo 2015 All Rights Reserved Page 8 of 46 EL logiREF MEDIA ZED wm a mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 2 LOGICBRICKS IP CORES 2 1 About logicBRICKS IP Library Xylon s logicBRICKS IP cor
62. w you will get an e mail with the download link for the selected reference design installation http Awww logicbricks com logicBRICKS Reference logicBRICKS Design Xylon Reference Designs Navigation Page aspx downloaded as a cross platform Java JAR self extracting installer Please make sure Installation process is quick and easy Each logicBRICKS reference design can be that you have installed the JRE Java Runtime Environment version 6 or higher Double click on the installer s icon to run the self installing executable to unpack and install the reference design on your PC At the beginning you will be requested to accept the reference design evaluation license Figure 9 For installation in Linux OS please follow instructions htto www logicbricks com logicBRICKS Reference logicBRICKS Design Xylon Reference Designs Linux Installation aspx Copyright Xylon d o o 2015 All Rights Reserved Page 22 of 46 rm logiREF MEDIA ZED mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a lf you agree with the conditions from the evaluation license click NEXT and select the installation path for your logicBRICKS reference design Figure 10 The installation process takes several minutes It generates the directory structure described in the paragraph 4 3 Directory Structure H Xylon logiREF ZGPU ZED Installatio Pe g b Ee MH Xylon logiREF ZGPU ZED Installation E e
63. xel alpha blending program the alpha channel in the output video stream Provides Bob and Weave de interlacing algorithms Supported Big and Little Endianness memory layout Double or triple buffering for flicker free video Parametrical VHDL design that allows tuning of slice consumption and features set Available for Xilinx Vivado Design Suite and ISE Design Suite XPS implementation tools More info http Avww logicbricks com Products logiWIN aspx Datasheet http www logicbricks com Documentation Datasheets IP logiWIN_hds paf Copyright Xylon d o o 2015 All Rights Reserved Page 11 of 46 Ewe logiREF MEDIA ZED wm up mm Reference Design Sulon Designed by XYLON User s Manual September 2 2015 Version v1 00 a 2 3 2 logil2S Audio Data Receiver Transmitter The logil2S enables audio recording and playback functionality in the Xilinx Zyngq 7000 AP SoC and FPGAs by connecting them to external audio devices via the I2S bus interface standard The IP core offers different configuration options Le configurable number of audio transmitters and and receivers up to 8 clock master or slave option etc Xylon provides the ALSA driver for audio processing within the Linux operating system Supports Xilinx Zyng 7000 AP SoC and all Xilinx FPGA families Supports up to eight individual 12S instances with the following features Configurable as receiver or transmitter Configurable as clock master or slave Configurable as w

open the User`s Manual

Contents

Download Pdf Manuals

Related Search

Related Contents