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MPC82L52_54 User Manual, v1.1.doc

1. ECAPnH Extended 9 MSB bit associated with to become 9 bit register used PWM mode ECAPnL Extended 9 bit MSB bit associated with CCAPnL to become 9 bit register used in PWM mode This document information is the intellectual property of Megawin Technology Co Ltd 35 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 7 2 Operation Modes of the The following Table shows the CCAPMn register settings for the various PCA functions Table PCA Module Modes MATn TOGn PWMn ECCFn Module Function 0 0 0 0 0 0 0 X 1 0 0 0 0 X 16 bit capture by a positive edge trigger on CEXn X 0 1 0 0 0 X 16 bit capture by a negative edge trigger on CEXn X 1 1 0 0 0 X 16 bit capture by a transition on CEXn 1 0 0 1 0 0 X M6 bit Software Timer 1 0 0 1 1 0 X 16 bit High Speed Output 1 0 0 0 0 1 0 18 6 Pulse Width Modulator PWM 7 2 1 Capture Mode To use one of the PCA modules in the capture mode either one or both of the bits CAPN and CAPP for that module must be set The external CEX input for the module is sampled for a transition When a valid transition occurs the PCA hardware loads the value of the PCA counter registers CH and CL into the mo
2. B1 0 P2MO Port2 Mode Register 0 P2MO 6 P2MO 5 2 0 4 2 0 2 P2MO 1 2 1 2 Mode Register 1 2 1 6 2 1 5 2 1 4 2 1 2 2 1 1 P3MO Port3 Mode Register 0 0 5 0 4 0 2 1 1 Port3 Mode Register 1 P3M1 5 P3M1 4 1 2 P3M1 1 x PCA Counter DFH DEH DDH DCH DBH DAH D9H D8H CCON control Register DH CR 4 CCF3 CCF2 1_ ccro 00 008 PCA Counter CMOD Mode Register D9H CIDL 52 CPS1 ECF 0xxxx000B PCA Counter HB F9H 00H PCA Counter LB E9H 00H Module DAH ECOMO TOGO PWMO ECCFO x0000000B Com Cap Register Modulet DBH ECOM1 1 1 MAT1 1 ECCF1 x0000000B Com Cap Register 2 Module2 DCH ECOM2 CAPP2 CAPN2 TOG2 PWM2 x0000000B Com Cap Register Modules DDH CAPN3 MAT3 TOG3 PWM3 x0000000B Com Cap Register CCAPOH PCA Module0 Capture AH Register CCAPOL PCA ModuleO Capture EAH Register LB PCA Module1 Capture PCA Module1 Capture Genet Register LB EBH 00H PCA Module2 Capture CCAP2L PCA Module2 Capture ECH E Register LB PCA Module3 Capture CCAP3H Register HB FDH 00H PCA Module3 Capture CCAP3L Register LB EDH 00H This doc
3. 0 X X X SPI disabled input input input port pins Salve 1 0 0 0 selected output input input Selected as slave 1 0 1 0 Slave Hi Z input input Not selected not selected Mode change to slave Slave i e if SS is driven low and 1 0 0 1E 0 by mode output input input MSTR will be cleared to 0 by change H W automatically MOSI and SPICLK are at high Master Hi Z Hi Z impedance to avoid bus idle contention when the Master is 1 0 1 1 idle Master MOSI and SPICLK are push pull active output output when the Master is active 1 1 X 0 Slave output input input 1 1 X 1 Master input output output X means don t care 6 2 1 Additional Considerations for a Slave When CPHA is 0 SSIG must be 0 and SS pin must be negated and reasserted between each successive serial byte transfer If the SPDAT register is written while SS pin is active low a write collision error results and WCOL is set The operation is undefined if CPHA is 0 and SSIG is 1 When is 1 SSIG be 0 or 1 If SSIG 0 the 55 pin may remain active low between successive transfers can be tied low at all times This format is sometimes preferred for use in systems having a signle fixed master and a single slave configuration 6 2 2 Additional Considerations for a Master In SPI transfers are always initiated by the master If the SPI
4. bit 128 direct bit addressable bits in internal RAM any VO pin control or status bit This document information is the intellectual property of Megawin Technology Co Ltd 71 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 19 1 Arithmetic Operations Mnemonic Description Byte a Cydia ARITHMETIC OPERATIONS ADD A Rn Add register to Acc 1 2 ADD A direct Add direct byte to Acc 2 3 ADD A Ri Add indirect RAM to Acc 1 3 ADD A data Add immediate data to Acc 2 2 ADDC A Rn Add register to Acc with Carry 1 2 ADDC A direct Add direct byte to Acc with Carry 2 3 A Ri Add indirect RAM to Acc with Carry 1 3 ADDC A data Add immediate data to Acc with Carry 2 2 SUBB A Rn Subtract register from Acc with borrow 1 2 SUBB A direct Subtract direct byte from Acc with borrow 2 3 SUBB A Ri Subtract indirect RAM from Acc with borrow 1 3 SUBB A data Subtract immediate data from Acc with borrow 2 2 INC A Increment Acc 1 2 INC Rn Increment register 1 3 INC direct Increment direct byte 2 4 INC Ri Increment indirect RAM 1 4 INC DPTR Increment data pointer 1 1 DEC A Decrement Acc 1 2 DEC Rn register 1 3 DEC direct Decrement direct byte 2 4 DEC QRi Decrement indirect RAM 1 4 MUL AB Multiply A and B 1 4 DIV AB Divide A by B 1 5 DA
5. 16 Bit Tim er Counter Note Module 2 amp 3 are only for MPCS2L E 54 The PCA timer is a common time base for all modules and can be programmed to run at 1 12 the oscillator frequency 1 2 the oscillator frequency the Timer 0 overflow or the input on pin P3 4 The clock source for the timer is determined by the CPS1 and CPSO bits in the CMOD register as follows CMOD PCA Counter Mode Register 7 6 5 4 3 2 1 0 CIDL CPS1 CPSO ECF CIDL counter idle control CIDL 0 lets the PCA counter continue functioning during idle mode CIDL 1 lets the PCA counter be gated off during idle mode 51 50 PCA counter clock source select bits 0 Internal clock Fosc 12 Where Fosc is the system clock 0 Internal clock Fosc 2 1 Timer 0 overflow 1 External clock at the ECI pin P3 4 Enable PCA counter overflow interrupt ECF 1 enables an interrupt when CF bit in CCON register is set 0 1 0 1 In the CMOD SFR are two additional bits associated with the PCA They are CIDL which allows the PCA to stop during idle mode and ECF which when set causes an interrupt if the PCA overflow flag CF in the CCON SFR is set either when the counter overflows or by software The following figure shows these functions This document information is the intellectual property of Megawin Technology Co Ltd 32 Megawin Technology Co Ltd 1999 right reserv
6. ADCTL AD Control Register 7 6 5 4 3 2 1 0 ADCON SPEED1 SPEEDO ADCI ADCS CHS2 CHS1 CHSO ADCON Cleared to turn off the ADC block Set to turn on the ADC block SPEED1 SPEEDO conversion speed selection 00 840 clock cycles are taken for a conversion 01 630 clock cycles are taken for a conversion 10 420 clock cycles are taken for a conversion 11 210 clock cycles are taken for a conversion ADCS ADC start bit which is set by software and automatically cleared by hardware ADCI ADC interrupt flag which is set by hardware and should be cleared by software CHS2 CHSO channel selection 000 select 1 0 as the analog input 001 select 1 1 as the analog input 010 select 1 2 as the analog input 011 select P1 3 as the analog input 100 select P1 4 as the analog input 101 select P1 5 as the analog input 110 select P1 6 as the analog input 111 select P1 7 as the analog input This document information is the intellectual property of Megawin Technology Co Ltd 39 Megawin Technology Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 Prior to using the ADC function users should 1 enable the ADC block by setting the ADCON bit 2 select the analog input pin by bits CHS2 CHSO and 3 configure the selected pin to its nput Only mode by P1M0 and P1M1 registers Now user can start the A to D conversion by setting th
7. Ox2E 0x0000 Ox2DFF 11 5 0 2 00 0 2 00 4 0x30 0x0000 Ox2FFF 12 0KB 0x3000 0x3000 3 5KB 0x32 0x0000 Ox31FF 12 5KB 0x3200 0x3200 Ox3DFF 3 0KB 0x34 0x0000 0x33FF 13 0KB 0x3400 0x3400 Ox3DFF 2 5KB 0x36 0x0000 Ox35FF 13 5KB 0x3600 0x3600 Ox3DFF 2 0KB 0x38 0x0000 Ox37FF 14 0KB 0x3800 0x3800 Ox3DFF 1 5KB 0x0000 0x39FF 14 5KB 0x3A00 0x3A00 0x3DFF 1 0x3G 0x0000 0x3BFF 15 0x3C00 0x3C00 0x3DFF 0 5 gt 0x3E 0x0000 0x3DFF 15 5KB NA NA This document information is the intellectual property of Megawin Technology Co Ltd Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 59 CF MEGAWIN MPC82L52 54 MAKE YOU WIN MPC82E52 54 Table 12 3f ISP 1 5KB ISP start address 0x3800 For MPC82L E 54 Available AP memory IAP memory IAPLB Range Size low boundary Range Size 0x02 0x0000 0x01FF 0 5KB 0x0200 0x0200 Ox37FF 13 5KB 0x04 0x0000 OxOSFF 1 0KB 0x0400 0x0400 Ox37FF 13 0KB 0x06 0x0000 0x05FF 1 5KB 0x0600 0x0600 Ox37FF 12 5KB 0x08 0x0000 0x07FF 2 0KB 0x0800 0x0800 Ox37FF 12 0KB OXOA 0 0000 0x09FF 2 5KB 0 0 00 00 0x37FF 11 5KB OXOC 0 0000 OxOBFF 3 0 0 00 0 0 00 0x37FF 11 0 0x0E 0x0000 0x0DFF
8. P1M1 7 1 1 6 P1M1 5 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 This document information is the intellectual property of Megawin Technology Co Ltd 13 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 2 0 Port2 Mode Register 0 7 6 5 4 3 2 1 0 P2MO 7 2 0 6 2 0 5 2 0 4 2 0 3 2 0 2 P2MO 1 2 0 0 P2M1 Port2 Mode Register 1 7 6 5 4 3 2 1 0 2 1 7 P2M1 6 P2M1 5 2 1 4 P2M1 3 P2M1 2 P2M1 1 2 1 0 Port3 Mode Register 0 7 6 5 4 3 2 1 0 7 0 5 4 P3MO 3 0 2 P3MO 1 0 1 Port3 Mode Register 1 7 6 5 4 3 2 1 0 1 7 P3M1 5 P3M1 4 P3M1 3 P3M1 2 P3M1 1 P3M1 0 2 1 4 Quasi bidirectional Port pins in quasi bidirectional mode are similar to the standard 8051 port pins A quasi bidirectional port can be used as an input and output without the need to reconfigure the port This is possible because when the port outputs a logic high itis weakly driven allowing an external device to pull the pin low When the pin outputs low itis driven strongly and able to sink a large current There are three pull up transistors in the quasi bidirectional output that serve different purposes One of these pull ups called the very weak pull u
9. 15 I O pins 23 VO pins P1 0 P1 7 8 2 52 pa g pas P3 7 7 PO O PO 3 4 I P1 0 P1 7 8 MPC82L E 54 Oe P2 0 P2 7 8 2 P3 0 P3 5 P3 7 7 2 0 2 7 8 2 1_ Port Configurations All these port pins can be individually and independently configured to one of four modes quasi bidirectional standard 8051 port push pull output open drain output or input only high impedance All port pins are in the quasi bidirectional mode after power up or reset Each port pin has a Schmitt triggered input to improve input noise rejection Each port has two configuration registers to configure the I O type for each port pin see the following Table Table Port Configuration Settings PxMO y 1 Port Mode 0 0 Quasi bidirectional 0 1 Push Pull Output 1 0 Input Only High Impedance Hi Z 1 1 Open Drain Output Where x 0 1 2 or 3 and y 0 7 Registers PxM0 and PxM1 are described as follows POMO Port0 Mode Register 0 7 6 5 4 3 2 1 0 POMO 3 POMO 2 POMO 1 POMO O 1 PortO Mode Register 1 7 6 5 4 3 2 1 0 POM1 3 POM1 2 POM1 1 1 0 P1MO Port1 Mode Register 0 7 6 5 4 3 2 1 0 P1MO 7 P1MO 6 1 5 1 0 4 P1M0 3 P1MO 2 P1MO 1 1 0 0 P1M1 Port1 Mode Register 1 7 6 5 4 3 2 1 0
10. 7 gt MEGAWIN MAKE YOU WIN MPC82L52 54 MPC82E52 54 Flow Chart for Verify using Byte Read ISPEN 1 enable ISP function and initialize ISPCR 2 0 0 01 select Read Mode Byte_address 0 IFADRH High byte of Byte address IFADRL Low byte of Byte address SCMD 0x46 then SCMD 0xB9 trigger ISP processing by sequential writing Increment Byte_address Compare got data in IFD with wanted data he same NO A Check end of address This document information is the intellectual property of Megawin Technology Ltd Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 53 ry MPC82L52 54 47 WIN MPC82E52 54 11 3 Demo of the ISP code EE KE RERAEE REE ee eee dee eode dee eee ee oe ISP modes s kk ik dee ed dede HORROR OR RO KERR ER RE KERR IFD DATA OE2h IFADRH DATA OE3h IFADRL DATA OE4h DATA OE5h SCMD DATA OE6h ISPCR DATA OE7h Fr MOV ISPCR 410000011b ISPCR 7 1 enable ISP PISPCR 2 0 2011 for Fosc 11 0592MHz 1 Page Erase Mode 512 bytes per page MOV IFMT 03h select Page Erase Mod MOV IFADRH 111 pa
11. Decimal Adjust Acc 1 4 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 MEGAWIN 82152 54 46 YOU WIN MPC82E52 54 19 2 Loqic Operations Mnemonic Description Byte LOGIC OPERATIONS ANL A Rn register to 1 2 ANL A direct AND direct byte to Acc 2 3 ANL A Ri AND indirect RAM to Acc 1 3 A data AND immediate data to Acc 2 2 ANL direct A AND Acc to direct byte 2 4 ANL direct data AND immediate data to direct byte 3 4 ORL A Rn OR register to Acc 1 2 ORL A direct OR direct byte to Acc 2 3 ORL Ri OR indirect RAM to Acc 1 3 ORL A data OR immediate data to Acc 2 2 ORL direct A OR Acc to direct byte 2 4 ORL direct data OR immediate data to direct byte 3 4 XRL A Rn Exclusive OR register to Acc 1 2 XRL A direct Exclusive OR direct byte to Acc 2 3 A Ri Exclusive OR indirect RAM to Acc 1 3 A data Exclusive OR immediate data to Acc 2 2 direct A Exclusive OR Acc to direct byte 2 4 XRL direct data Exclusive OR immediate data to direct byte 3 4 CLR A Clear Acc 1 1 CPL A Complement Acc 1 2 RL A Rotate Acc Left 1 1 RLC A Rotate Acc Left through the Carry 1 1 RR A Rotate Acc Right 1 1 RRC A Rotate Acc Right through the Carry 1 1 SWAP A Swap nibbles within the Acc 1 1 This document information is the intellectual property of Megawin Technolo
12. XTAL1 P4 4 SS AINA INTO P3 2 P1 3 AIN3 INT1 P3 3 P1 2 AIN2 ECI TO0 P3 4 P1 1 AIN1 CEX1 T1 P3 5 P1 0 AINO vss P3 7 CEXO SkinnyDIP 20 This document information is the intellectual property of Megawin Technology Co Ltd 5 Megawin Technology Co Ltd 1999 right reserved Version 1 1 09 2006 MEGAWIN MPC82L52 54 amp 4 YOU 82 52 54 821 54 2 2 vcc 2 3 P2 1 RST RST P2 0 CEX2 RXD P3 0 P4 7 SPICLK AIN7 RXD P3 0 P4 7 SPICLK AIN7 TXD P3 1 P1 6 MISO AING TXD P3 1 P1 6 MISO AING XTAL2 P1 5 MOSI AIN5 XTAL2 P1 5 MOSVAINS XTAL1 P1 4 SS AIN4 XTAL1 P1 4 SS AIN4 INTO P3 2 P1 3 AIN3 INTO P3 2 P4 3 AIN3 INT1 P3 3 P1 2 AIN2 INT1 P3 3 P1 2 AIN2 ECI T0 P3 4 P1 1 AIN1 ECVTO P3 4 P1 1 AIN1 CEX1 T1 P3 5 P1 0 AINO CEX1 T1 P3 5 P1 0 AINO vss P3 7 CEXO CEX3 P2 4 P3 7 CEXO P2 5 P2 7 SkinnyDIP 20 vss Pas 5 20 SkinnyDIP 28 SOP 28 SSOP 28 This document information is the intellectual property of Megawin Technology Co Ltd Megawin Technology Ltd 1999 right reserved Version 1 1 09 2006 CF MEGAWIN MPC82L52 54 MAKE YOU WIN M PC82E52 54 1 2 Special Function Registers SFRs MPC82L E 52 SFRs SYMBOL DESCRIPTION ADDRESS amp SYMBOL Accumulator NEM D7H D6H D5H Dan D2H D1H E SP DPH DPL MISO MOSI BDH BCH B8H Interrupt Priority PPCA LVD PSPI ADC PS
13. for ISP processing Flow Chart for Page Erase ISPEN 1 enable ISP function and initialize ISPCR 2 0 IFMT 0x03 select Page Erase Mode address 0 IFADRH High byte of address Page address Page_address 0x0200 IFADRL Low byte of address Increment Page address lt q 512 bytes per page SCMD 0x46 then SCMD 0xB9 trigger ISP processing by sequential writing NO Check end of Page This document information is the intellectual property of Megawin Technology Ltd 51 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 MAKE YOU WIN _ 7 gt MEGAWIN MPC82L52 54 MPC82E52 54 Flow Chart for Byte Program ISPEN 1 enable ISP function and initialize ISPCR 2 0 IFMT 0x02 select Byte Program Mode Byte 5 lt 0 writing IFADRH High byte of Byte address IFADRL Low byte of Byte address IFDzdata to be programmed SCMD 0x46 then SCMD 0xB9 trigger ISP processing by sequential Increment Byte_address Check end of address NO A This document information is the intellectual property of Megawin Technology Ltd Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 52 _
14. 00H P1M0 0 1 1 Porti Mode Register 1 92H 1 1 7 1 1 6 1 1 5 P1M1 3 1 1 2 P1M1 1 Port3 Mode Register 0 P3MO 7 5 P3MO 3 2 1 0 P3M1 Port3 Mode Register 1 B2H P3M1 7 P3M1 5 PCA Counter CCON Control Register P3M1 3 1 2 1 1 1 0 00xxxx00B PCA Counter Register Oxxxx000B ME Counter HB OL jPCACoutenlB Counter PCA Counter LB PCA Module0 Com Cap Register ECOMO CAPPO CAPNO MATO TOGO x0000000B PCA 1 1 Com Cap Redist r ECOM1 CAPP1 CAPN1 MAT1 TOG1 x0000000B PCA Module0 Capture Register 0 Capture Register LB PCA Module1 Capture Register Module1 Capture Register LB PCAPWMO PWM Mode auxiliary 0 ECAPOL xxxxxx00B PCAPWM PWM Mode auxiliary 1 SPSTAT SPI Status Register SPIF WCOL ECAP1H ECAP1L xxxxxx00B 00 SPCTL SPI Control Register SSIG DORD MSTR CPOL CPHA SPR1 SPR0 SPDAT SPI Data Register ISPCR ISP Control EE ISPEN SWBS SWRST ICK2 ICK1 ICKO 0000x000B IFMT Flash Mode Table Flash Mode Table MS1 MSO xxxxx000B IFADRH ISP Flash Addres
15. Range Size IAP low boundary Range Size 0x02 0x0000 0x01FF 0 5KB 0x0200 0x0200 Ox3DFF 15 0KB 0x04 0x0000 OxOSFF 1 0KB 0x0400 0x0400 Ox3DFF 14 5 0x06 0x0000 0x05FF 1 5KB 0x0600 0x0600 Ox3DFF 14 0KB 0x08 0x0000 0x07FF 2 0KB 0x0800 0x0800 Ox3DFF 13 5KB OXOA 0 0000 0x09FF 2 5 0x0A00 0x0A00 Ox3DFF 13 0KB 0x0C 0x0000 3 0KB 0 0 00 0 0 00 12 5 0x0E 0x0000 0x0DFF 3 5KB 0x0E00 0 0 0 0x3DFF 12 0 0x10 0x0000 OxOFFF 4 0KB 0x1000 0x1000 11 5KB 0x12 0x0000 0x11FF 4 5KB 0x1200 0 1200 Ox3DFF 11 0KB 0x14 0x0000 Ox13FF 5 0KB 0x1400 0x1400 Ox3DFF 10 5 0x16 0x0000 0x15FF 5 5KB 0x1600 0x1600 Ox3DFF 10 0KB 0x18 0x0000 0x17FF 6 0KB 0x1800 0x1800 Ox3DFF 9 5 0 0000 0x19FF 6 5 0x1A00 0x1A00 9 0KB 0x1C 0x0000 Ox1BFF 7 0KB 0x1C00 0 1 00 8 5 0x0000 Ox1DFF 7 5 0x1E00 0 1 00 8 0KB 0x20 0x0000 Ox1FFF 8 0x2000 0x2000 OX3DFF 7 5KB 0x22 0x0000 0x21FF 8 5KB 0x2200 0x2200 Ox3DFF 7 0KB 0x24 0x0000 Ox23FF 9 0KB 0x2400 0x2400 Ox3DFF 6 5KB 0x26 0x0000 0x25FF 9 5KB 0x2600 0x2600 Ox3DFF 6 0KB 0x28 0x0000 0x27FF 10 0KB 0x2800 0x2800 Ox3DFF 5 5KB 2 0x0000 0x29FF 10 5KB 0 2 00 0 2 00 5 0 2 0x0000 Ox2BFF 11 0KB 0x2C00 0 2 00 4 5
16. being serviced if the interrupt is enabled previously Once the IAP is complete the CPU continues running and the interrupts in the queue will be serviced immediately if the interrupt flag is still active Users however should be aware of the following 1 Any interrupt can not be serviced in time during the CPU halts for IAP processing 2 The low level triggered external interrupts INTO and INT1 should keep active until the IAP is complete or they will be neglected This document information is the intellectual property of Megawin Technology Ltd 63 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 13 Programmable System Clock The system clock or CPU clock of the device is programmable and source selectable The user can program the system clock frequency by 2 register and select the clock source by the hardware option bit ENROSGC which can only be programmed by a universal Programmer Writer The following diagram shows the clock structure System Clock Structure Clock Divider Xosc 020000 default XTAL1 620001 5 VERE 020190 ot oll ot oll0 orol Divided Xosc FOSC System CPU Clock Selected by CKS2 CKS1 CKS0 Internal RCosc ENROSC RC Oscillator Hareware Option 1 Disabled default 0 Enabled 2 Power
17. comparator For examples a If ECAPnH 0 amp CCAPnH 0x00 b If ECAPnH 0 amp CCAPnH 0x40 c If ECAPnH 0 amp CCAPnH 0xCO d If ECAPnH 1 amp CCAPnH 0x00 i e 0x000 the duty cycle is 100 i e 0 040 the duty cycle is 75 i e 0 0 0 the duty cycle is 25 i e 0 100 the duty cycle is 0 Function Block Diagram 9 Bits CCAPnH ECAPnL CCAPnL 0 0 CL I ECAPnL CCAPnL 1 9 BIT COMPARATOR 10 gt ECAPnL CCAPnL 9 Bits CL i oveRrLow 86290 TIMER COUNTER E 7 1 0 0 0 0 1 0 This document information is the intellectual property of Megawin Technology Ltd 38 Megawin Technology Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 8 Analog to Digital Converter ADC MPC82L E 52 and MPC82L E 54 have a built in ADC implemented by SAR approach with 8 bit and 10 bit resolution respectively The ADC has eight multiplexed analog inputs sharing pins of Port 1 a control register ADCTL and conversion result registers ADC ADCH 8 ADCL as shown in the block diagram ADC Block Diagram ADCTL Register ADCON SPEED1 SPEEDO CHS2 CHS1 CHSO M Register for MPC82L E 52 er e es es er Jane register Register for MPC82L E 52 10 hit DAC for MPC82L E 54
18. this case another master can drive this pin low to select this device as an SPI slave and start sending data to it To avoid bus contention the becomes a slave As a result of the becoming slave the MOSI and SPICLK pins forced to be an input and MISO becomes an output The SPIF flag SPSTAT is set and if the interrupt is enabled an SPI interrupt will occur User software should always check the MSTR bit If this bit is cleared by slave select and the user wants to continue to use the SPI as a master the user must set the MSTR bit again otherwise it will stay in slave mode 6 2 4 Write Collision The SPI is single buffered in the transmit direction and double buffered in the receive direction New data for transmission can not be written to the shift register until the previous transaction is complete The WCOL SPSTAT 6 bit is set to indicate data collision when the data register is written during transmission In this case the data currently being transmitted will continue to be transmitted but the new data i e the one causing the collision will be lost While write collision is detected for both a master or a slave it is uncommon for a master because the master has full control of the transfer in progress The slave however has no control over when the master will initiate a transfer and therefore collision can occur For receiving data received data is transferred into a parallel read data bu
19. 0000 0x05FF 1 5KB 0x0600 0x0600 0x1 FFF 6 5KB 0x08 0x0000 0x07FF 2 0KB 0x0800 0x0800 0x1FFF 6 0KB OXOA 0 0000 0x09FF 2 5KB 0 0 00 0x0A00 Ox1FFF 5 5KB 0x0C 0x0000 OxOBFF 3 0KB 0 0 00 0 0 00 0x1FFF 5 0x0E 0x0000 0x0DFF 3 5KB 0x0E00 OxOEO00 0x1FFF 4 5KB 0 10 0 0000 OxOFFF 4 0 1000 0 1000 0x1FFF 4 0 12 0 0000 0x11FF 4 5 0 1200 0x1200 Ox1FFF 3 5KB 0x14 0x0000 Ox13FF 5 0KB 0x1400 0x1400 Ox1FFF 3 0KB 0x16 0x0000 Ox15FF 5 5KB 0x1600 0x1600 Ox1FFF 2 5KB 0x18 0x0000 0x17FF 6 0KB 0x1800 0x1800 Ox1FFF 2 0KB Ox1A 0x0000 Ox19FF 6 5KB 0x1A00 0x1A00 Ox1FFF 1 5KB 0 1 0x0000 7 0KB 0 1 00 0x1C00 Ox1FFF 1 0KB Ox1E 0x0000 Ox1DFF 7 5KB 0x1E00 0 1 00 Ox1FFF 0 5KB gt 0x20 0x0000 Ox1FFF 8 NA NA This document information is the intellectual property of Megawin Technology Ltd Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 57 20 Table 12 3b 1 MEGAWIN MAKE YOU WIN ISP start address 0x1C00 MPC82L52 54 MPC82E52 54 For MPC82L E 52 Available AP memory IAP memory Range Size IAP low boundary Range Size 0x02 0x0000 0x01FF 0 5KB 0x0200 0x0200 Ox1BFF 6 5KB 0x04 0x0000 OxOSFF 1 0KB 0x0400 0x0400 Ox1BFF 6 0KB 0x06 0x
20. 0000 0x05FF 1 5KB 0x0600 0x0600 Ox1BFF 5 5KB 0x08 0x0000 0x07FF 2 0KB 0x0800 0x0800 Ox1BFF 5 0KB OXOA 0 0000 0x09FF 2 5KB 0 0 00 0x0A00 Ox1BFF 4 5KB 0x0G 0x0000 0x0BFF 3 0KB 0x0C00 0x0C00 Ox1BFF 4 0KB OxOE 0x0000 OxODFF 3 5KB OxOEO0 OxOEO00 Ox1BFF 3 5KB 0x10 0x0000 OxOFFF 4 0KB 0x1000 0x1000 Ox1BFF 3 0KB 0x12 0x0000 0x11FF 4 5KB 0x1200 0x1200 Ox1BFF 2 5KB 0x14 0x0000 Ox13FF 5 0KB 0x1400 0x1400 Ox1BFF 2 0KB 0x16 0x0000 0x15FF 5 5KB 0x1600 0x1600 Ox1BFF 1 5KB 0x18 0x0000 0x17FF 6 0KB 0x1800 0x1800 Ox1BFF 1 0KB 0 0000 0x19FF 6 5KB 0x1A00 0x1A00 Ox1BFF 0 5KB gt 0x1C 0x0000 Ox1BFF 7 0KB NA NA Table 12 3c ISPZ2KB ISP start address 0x1800 For MPC82L E 52 Available AP memory IAP memory Range Size IAP low boundary Range Size 0x02 0x0000 0x01FF 0 5KB 0x0200 0x0200 0x17FF 5 5KB 0x04 0x0000 OxOSFF 1 0KB 0x0400 0x0400 0x17FF 5 0KB 0x06 0x0000 0x05FF 1 5KB 0x0600 0x0600 0x17FF 4 5KB 0x08 0x0000 0x07FF 2 0KB 0x0800 0x0800 0x17FF 4 0KB OXOA 0 0000 0x09FF 2 5KB 0 0 00 0x0A00 0x17FF 3 5KB 0x0G 0x0000 0x0BFF 3 0KB 0x0C00 0x0C00 0x17FF 3 OxOE 0x0000 OxODFF 3 5KB OxOEO0 OxOEO00 0x17FF 2 5KB 0x10 0x0000 OxOFFF 4 0x1000 0x1000 0x17FF 2 0KB 0x12 0x0000 0x11FF 4 5KB 0x1200 0x1200 Ox17FF 1
21. 100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are trended as don t cares In most cases interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon reset SADDR SFR address 0A9H and SADEN SFR address 0B9H are leaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t cares This effectively disables the Automatic Addressing mode and allows the micro controller to use standard 80C51 type UART drivers which do not make use of this feature 1 1 E 0 RECEIVED ADDRESS DO 07 COMPARATOR PROGRAMMED ADDRESS COMPARATOR UART MODE 2 OR MODE AND SM2 1 INTERRUPT IF REN 1 RB8 1 AND RECEIVED ADDRESS PROGRAMMED ADDRESS WHEN OWN ADDRESS RECEIVED CLEAR SM2 TO RECEIVE DATA BYTES WHEN ALL DATA BYTES HAVE BEEN RECEIVED SET SM2 TO WAIT FOR NEXT ADDRESS This document information is the intellectual property of Megawin Technology Co Ltd 23 Megawin Technology Co Ltd 1999 right reserved Version 1 1 09 2006 CF MEGAWIN MPC82L52 54 MAKE YOU WIN M PC82E52 54 6 Serial Peripheral Interface The MPC82L E 52 54 provide another high speed serial communication interface the SPI interface SPI is a full duplex high speed and synchronous communication bus with two operation mode
22. 12 the user can select an alternate clock source the Fosc The bit 7 and bit 6 in AUXR provide this selection AUXR Auxiliary Register 7 6 5 4 3 2 1 0 TOX12 T1X12 URMOX6 EADCI ESPI ENLVFI 0 12 Timer 0 clock source select Set to select Fosc as the clock source and clear to select Fosc 12 T1X12 Timer 1 clock source select Set to select Fosc as the clock source and clear to select Fosc 12 Note Both these two bits are 0 after power up or reset and thus select Fosc 12 as the clock source by default like the standard 8051 does The following figures show the selection of alternate clock source for Timer 0 and Timer1 4 1 Mode 0 TLx 4 0 THx 7 0 x Interrupt Where OSC means Fosc the system clock 4 2 Mode 1 Interrupt Where OSC means Fosc the system clock This document information is the intellectual property of Megawin Technology Co Ltd 18 Megawin Technology Co Ltd 1999 right reserved Version 1 1 09 2006 OO MPC82L52 54 47 WIN MPC82E52 54 4 33 Mode 2 Interrupt Where OSC means Fosc the system clock 4 4 Mode 3 Where OSC means Fosc the system clock This document information is the intellectual property of Megawin Technology Co Ltd 19 Megawin Technology Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 5 Serial Port 5 1_ Baudrat
23. 3 5KB 0x0E00 OxOEO00 Ox37FF 10 5KB 0x10 0x0000 OxOFFF 4 0x1000 0x1000 OX37FF 10 0KB 0x12 0x0000 Ox11FF 4 5KB 0x1200 0x1200 0x37FF 9 5KB 0x14 0x0000 0x13FF 5 0KB 0x1400 0x1400 0x37FF 9 0 0x16 0x0000 0x15FF 5 5KB 0x1600 0x1600 0x37FF 8 5KB 0x18 0x0000 0x17FF 6 0KB 0x1800 0x1800 0x37FF 8 0KB Ox1A 0x0000 Ox19FF 6 5KB Ox1A00 0x1A00 Ox37FF 7 5KB 0 1 0 0000 0x1BFF 7 0 0x1C00 0x1C00 0x37FF 7 0 1 0 0000 0x1DFF 7 5 0 1 00 0 1 00 0x37FF 6 5 0 20 0 0000 0x1FFF 8 0 2000 0 2000 7 6 0KB 0 22 0 0000 0x21FF 8 5 0 2200 0 2200 0x37FF 5 5 0 24 0 0000 0x23FF 9 0 0 2400 0 2400 0x37FF 5 0 0 26 0 0000 0x25FF 9 5KB 0 2600 0 2600 0x37FF 4 5 0 28 0 0000 0x27FF 10 0KB 0 2800 0 2800 0x37FF 4 0 2 0 0000 0x29FF 10 5 0 2 00 0 2 00 0x37FF 3 5KB 0 2 0x0000 Ox2BFF 11 0 2 00 0 2 00 0x37FF 3 0KB Ox2E 0x0000 Ox2DFF 11 5 0 2 00 0 2 00 0x37FF 2 5KB 0 30 0x0000 Ox2FFF 12 0KB 0x3000 0x3000 2 0KB 0x32 0x0000 Ox31FF 12 5KB 0x3200 0x3200 Ox37FF 1 5KB 0x34 0x0000 Ox33FF 13 0KB 0x3400 0x3400 Ox37FF 1 0KB 0x36 0x0000 Ox35FF 13 5KB 0x3600 0x3600 Ox37FF 0 5KB gt 0x38 0x0000 0x37FF 14 0KB NA NA This document information is the intellectual property of Megawin Technology Co
24. 400 0x2400 4 0KB 0x26 0x0000 0x25FF 9 5KB 0x2600 0x2600 Ox3SFF 3 5KB 0x28 0x0000 0x27FF 10 0KB 0x2800 0x2800 Ox3SFF 3 2 0x0000 0x29FF 10 5KB 0x2A00 0x2A00 Ox33FF 2 5KB 0 2 0x0000 Ox2BFF 11 0KB 0x2C00 0 2 00 0x33FF 2 0KB Ox2E 0x0000 Ox2DFF 11 5KB 0x2E00 0 2 00 Ox33FF 1 5KB 0x30 0 0000 Ox2FFF 12 0KB 0x3000 0x3000 OX33FF 1 0KB 0x32 0x0000 Ox31FF 12 5KB 0x3200 0x3200 0x33FF 0 5KB gt 0x34 0x0000 Ox33FF 13 0KB NA NA This document information is the intellectual property of Megawin Technology Ltd Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 61 249 MEGAWIN MAKE YOU WIN MPC82L52 54 MPC82E52 54 Table 12 3h ISP23 5KB ISP start address 0x3000 For MPC82L E 54 Available AP memory IAP memory IAPLB Range Size low boundary Range Size 0x02 0x0000 0x01FF 0 5KB 0x0200 0x0200 Ox2FFF 11 5 0x04 0x0000 1 0KB 0x0400 0x0400 Ox2FFF 11 0KB 0x06 0x0000 OXOBEF 1 5KB 0x0600 0x0600 Ox2FFF 10 5KB 0x08 0x0000 0x07FF 2 0KB 0x0800 0x0800 Ox2FFF 10 0KB OXOA 0 0000 0x09FF 2 5KB 0 0 00 00 Ox2FFF 9 5KB 0x0G 0x0000 0x0BFF 3 0KB 0x0C00 0x0C00 0x2FFF 9 0KB 0x0E 0x0000 0x0DFF 3 5KB 0x0E00 0 0 0 0x2FF
25. 5KB 0x14 0x0000 Ox13FF 5 0KB 0x1400 0x1400 0x17FF 1 0KB 0x16 0x0000 OX15FF 5 5KB 0x1600 0x1600 0x17FF 0 5KB gt 0x18 0x0000 0 17 6 0KB NA NA Table 12 3d ISPZ3KB ISP start address 0x1400 For MPC82L E 52 Available AP memory IAP memory IAPLB Range Size IAP low boundary Range Size 0x02 0x0000 0x01FF 0 5KB 0x0200 0x0200 Ox13FF 4 5KB 0x04 0x0000 OxOSFF 1 0x0400 0x0400 Ox13FF 4 0x06 0x0000 0x05FF 1 5KB 0x0600 0x0600 Ox13FF 3 5KB 0x08 0x0000 0x07FF 2 0KB 0x0800 0x0800 Ox13FF 3 0KB OXOA 0 0000 0x09FF 2 5KB 0x0A00 0x0A00 Ox13FF 2 5KB 0x0C 0x0000 OxOBFF 3 0KB 0 0 00 0 0 00 Ox13FF 2 0KB OxOE 0x0000 OxODFF 3 5KB OxOEO0 OxOEO00 Ox13FF 1 5KB 0x10 0x0000 OxOFFF 4 0KB 0x1000 0x1000 Ox13FF 1 0KB 0x12 0x0000 0x11FF 4 5KB 0x1200 0x1200 Ox13FF 0 5KB gt 0x14 0x0000 0x13FF 5 0KB NA NA This document information is the intellectual property of Megawin Technology Co Ltd Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 58 CF MEGAWIN MAKE YOU WIN 12 3 2 MPC82L E 54 IAP memory Table 12 3e No ISP MPC82L52 54 MPC82E52 54 For MPC82L E 54 Available AP memory IAP memory IAPLB
26. 6 3 1 SPI Slave Transfer Format with 0 30 6 3 2 SPI Slave Transfer Format with 1 30 6 3 3 SPI Master Transfer Format with CPHA O sesse ees see ese ee ee ee ee ee ee ee ee ee ee 31 6 3 4 SPI Master Transfer Format with 1 sesse ee ee ee ees ee ee ee ene ee ee ee ee ee ee ee 31 7 Programmable Counter Array 222 22 adesse cuna de ee ee GR EN RE Ee 32 7 1 Introduction to the 32 7 2 Operation Modes of the essens see Res EG EE Re ER ERK EE re Eks 36 7 221 36 This document information is the intellectual property of Megawin Technology Ltd 2 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 3 MEGAWIN MPC82L52 54 MAKE YOU WIN MPC82E52 54 7 2 2 16 bit Software Timer 37 7 2 3 High Speed Output 37 72 4 PWM Oo S EE EE EE 38 8 Analog to Digital Converter 39 u ia PE PS 41 91 Interrupt uuu t 43 9 2 Note Interrupt during ses eek Su Se NS RANK 44 10 One time Ena
27. 66 518622 67 17 XTAL Oscillating and Reset 68 WAP si Ba ie Es ARE OE 68 172 ie EE EN ER EE ER EE N EN 68 18 Hardware Options UU mt 69 gt 71 191 Arithmetic Operations conem EE ERKEN ER ERGE ER GER EREGAS Re MR RUIN de 72 NE ees ei OE N AR ER EA EE 73 19 3 Data Transfer ee ee 74 19 4 Boolean Variable 75 19 5 Program and Machine GOUD ses EN Ee GE RE AR GE 76 This document information is the intellectual property of Megawin Technology Co Ltd 3 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 Preface The User Manual describes only the special amp new features which the MPC82L E 52 and MPC82L E 54 have while the standard 8051 MCU doesn t have It provides a great help for users to use these two chips This document information is the intellectual property of Megawin Technology Co Ltd 4 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 s Y MEGAWIN MPC82L52 54 T S wake YOU WN MPC82E52 54 1 General 1 1 Pin Assignment MPC82L E 52 RST RXD P3 0 P1 7 SPICLK AIN7 TXD P3 1 P1 6 MISO AIN6 XTAL2 P1 5 MOSI AIN5
28. BH Serial Port 0023H SPI or ADC SPIF ADCI 002 T ae lowest priority 0033H Note CCF2 and CCF3 are available only in MPC82L E 54 The following SFRs are associated with the interrupts Among them the IPH Interrupt Priority High register makes the four level interrupt structure possible IE Interrupt Enable Register 7 6 5 4 3 2 1 0 LVD ESPI ADC ES ET1 EX1 ETO EXO EA Global disable bit If EA 0 all interrupts are disabled If EA 1 each interrupt can be individually enabled or disabled by setting or clearing its enable bit EPCA LVD PCA amp LVD interrupts enable bit ESPI ADC SPI amp ADC interrupts enable bit ES Serial Port interrupt enable bit ET1 Timer 1 interrupt enable bit EX1 External interrupt 1 enable bit ETO Timer 0 interrupt enable bit External interrupt O enable bit IP Interrupt Priority Register 7 6 5 4 3 2 1 0 PPCA LVD PSPI ADC PS PT1 PX1 PTO 8 interrupts priority bit PSPI SPI 8 ADC interrupts priority bit PS Serial interrupt priority bit PT1 Timer 1 interrupt priority bit PX1 External interrupt 1 priority bit Timer 0 interrupt priority bit PX0 External interrupt 0 priority bit This document information is the intellectual property of Megawin Technology Co Ltd 41 Megawin Tech
29. CR 2 0 SWRST 1 trigger S W reset Do ISP programming to update the Application code Y Now CPU will re boot from AP memory End and run Application code normally This document information is the intellectual property of Megawin Technology Co Ltd 49 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 Method 2 Boot from ISP memory through AP memory while HWBS and HWBS2 are disabled For MPC82L E 54 the 2 must also disabled Power on with HWBS disabled and ISP memory exists CPU will boot from AP memory and run Application code Check the user defined NO ISP condition do ISP SWBS 1 select boot from ISP memory Run Application code SWRST 1 trigger S W reset normally CPU will re boot from ISP memory and run ISP code ISPEN 1 enable ISP function and initialize ISPCR 2 0 Do ISP programming to update the Application code This document information is the intellectual property of Megawin Technology Co Ltd 50 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 11 2 Operation Flow of ISP The following figures show the flow chart for the various ISP modes used in the ISP code
30. Control Register 2 7 6 5 4 3 2 1 0 CKS2 CKS1 CKSO CKS2 CKS1 50 System clock select bits CKS2 CKS1 CKSO Fosc System clock 0 0 0 Xosc default 0 0 1 Xosc 2 0 1 0 Xosc 4 0 1 1 Xosc 8 1 0 0 Xosc 16 1 0 1 Xosc 32 1 1 0 Xosc 64 1 1 1 Xosc 128 Where Xosc is the frequency of the signal on XTAL1 pin In the default state the reset value of 2 is 0x00 so the system clock frequency is the same as that on the XTAL1 pin The user can modify at any time to get a new system clock which will be active just after the modifying is completed This feature is especially useful for further power saving in idle mode as long as the user programs a non zero value to the CKS 2 0 bits before entering the idle mode This document information is the intellectual property of Megawin Technology Co Ltd 64 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 14 Wake up from Power down Mode When the CPU is put into power down mode the external interrupts INT0 and INT1 can be used to wake up the CPU if any of them is enabled Once the CPU is wakened up the interrupt service routine is serviced until the instruction is encountered and the next instruction to be executed will be the one following the instruction that put the CPU into power down mode The following figure shows the po
31. E CM 5 Imer Foaling id a FADIA R d I 1 I I I 1 i i wee BLAF S FFF Note CCF2 and are available only in MPC82L E 54 This document information is the intellectual property of Megawin Technology Co Ltd 43 Megawin Technology Co Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 9 2 Note on Interrupt during ISP IAP During ISP IAP the CPU halts for a while for internal ISP IAP processing At this time the interrupt will queue up for being serviced if the interrupt is enabled previously Once the ISP IAP is complete the CPU continues running and the interrupts in the queue will be serviced immediately if the interrupt flag is still active Users however should be aware of the following 1 Any interrupt can not be serviced in time during the CPU halts for ISP IAP processing 2 The low level triggered external interrupts INTO and INT1 should keep active until the ISP IAP is complete or they will be neglected This document information is the intellectual property of Megawin Technology Co Ltd 44 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 10 One time Enabled Watchdog Timer WDT The WDT is intended as a recovery method in situations where the CPU may be subjected t
32. F 8 5KB 0x10 0x0000 OxOFFF 4 0KB 0x1000 0x1000 OX2FFF 8 0KB 0x12 0x0000 0x11FF 4 5KB 0x1200 0x1200 Ox2FFF 7 5KB 0x14 0 0000 5 0KB 0x1400 0x1400 Ox2FFF 7 0KB 0x16 0x0000 Ox15FF 5 5KB 0x1600 0 1600 Ox2FFF 6 5KB 0x18 0x0000 Ox17FF 6 0KB 0x1800 0x1800 Ox2FFF 6 0KB 0 0000 0x19FF 6 5KB 0x1A00 0x1A00 Ox2FFF 5 5KB 0x1C 0x0000 Ox1BFF 7 0KB 0x1C00 0 1 00 Ox2FFF 5 0 0000 Ox1DFF 7 5 0x1E00 Ox1E00 Ox2FFF 4 5KB 0x20 0x0000 Ox1FFF 8 0KB 0x2000 0x2000 OX2FFF 4 0KB 0x22 0x0000 0x21FF 8 5KB 0x2200 0x2200 Ox2FFF 3 5KB 0x24 0x0000 Ox23FF 9 0KB 0x2400 0x2400 Ox2FFF 3 0x26 0x0000 0x25FF 9 5KB 0x2600 0x2600 Ox2FFF 2 5KB 0x28 0x0000 0x27FF 10 0KB 0x2800 0x2800 Ox2FFF 2 0KB 0 2 0x0000 0x29FF 10 5KB 0 2 00 0 2 00 Ox2FFF 1 5 0 2 0x0000 Ox2BFF 11 0 0x2C00 0x2C00 Ox2FFF 1 0KB 0 2 0x0000 Ox2DFF 11 5 0 2 00 0 2 00 Ox2FFF 0 5 gt 0 30 0x0000 Ox2FFF 12 0KB NA NA This document information is the intellectual property of Megawin Technology Co Ltd Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 62 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 12 4 Note on In Application Programming During In Application Programming the CPU halts for a while for internal IAP processing At this time the interrupt will queue up for
33. GA WIN MPC82E52 54 16 Built in Oscillator MPC82L E 52 54 have a built in oscillator with the rough oscillating frequency of 6MHz It can be used to replace the external crystal oscillator in the application which doesn t need an exact oscillating frequency To enable the built in oscillator users should enable the hardware option ENROSC by universal Writer Programmer Typically the oscillating frequency is about 6MHz at room temperature 25 C And the variation may be up to 30 over the temperature of 40 C to 85 C 30 at 40 C and 30 at 85 C So it is only for the application which doesn t ask an exact oscillating frequency This document information is the intellectual property of Megawin Technology Co Ltd 67 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 17 and Reset Circuitry 17 1 XTAL Oscillatinq As shown in the XTAL Oscillating Circuit to achieve successful and exact oscillating the C1 and C2 about 20pF 150pF are necessary regardless of enabled or disabled OSCDN within the whole operation frequency range XTAL Oscillating Circuit MPC82L E 52 54 XTAL2 e XTAL1 C1 C2 17 2 Reset Circuitry When power is turned on the circuit holds the RST pin high for an amount of time that depends on the capacitor value and the rate at
34. Ltd Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 60 CF MEGAWIN MPC82L52 54 MAKE YOU WIN MPC82E52 54 Table 12 3g ISP 2 5KB ISP start address 0x3400 For MPC82L E 54 Available AP memory IAPLB Range Size IAP low boundary Range Size 0x02 0x0000 0x01FF 0 5KB 0x0200 0 0200 Ox33FF 12 5kB 0x04 0x0000 OxOSFF 1 0KB 0x0400 0x0400 Ox33FF 12 0KB 0x06 0x0000 0x05FF 1 5KB 0x0600 0x0600 Ox33FF 11 5KB 0x08 0x0000 0x07FF 2 0KB 0x0800 0x0800 0x33FF 11 0KB OXOA 0 0000 0x09FF 2 5KB 0 0 00 00 0x33FF 10 5KB 0x0G 0x0000 0x0BFF 3 0KB 0x0C00 0x0C00 0x33FF 10 0 0x0E 0x0000 0x0DFF 3 5KB 0x0E00 OxOEO00 0x33FF 9 5KB 0x10 0 0000 4 0x1000 0x1000 0X33FF 9 0KB 0x12 0x0000 0x11FF 4 5KB 0x1200 0x1200 0x33FF 8 5KB 0x14 0x0000 0x13FF 5 0KB 0x1400 0x1400 0x33FF 8 0KB 0x16 0x0000 0x15FF 5 5KB 0x1600 0x1600 0x33FF 7 5KB 0x18 0x0000 0x17FF 6 0KB 0x1800 0x1800 0x33FF 7 0KB 0x1A 0x0000 0x19FF 6 5KB 0x1A00 0x1A00 0x33FF 6 5KB 0x1G 0x0000 0x1BFF 7 0KB 0x1C00 0x1C00 0x33FF 6 Ox1E 0x0000 0x1DFF 7 5KB 0x1E00 0x1E00 5 5KB 0x20 0x0000 Ox1FFF 8 0x2000 0x2000 5 0x22 0x0000 0x21FF 8 5KB 0x2200 0x2200 Ox33FF 4 5KB 0x24 0x0000 0x23FF 9 0KB 0x2
35. MATn Match control When MATn 1 a match of the PCA counter with this module s compare capture Register causes the CCFn bit in CCON to be set TOGn Toggle control When TOGn 1 a match of the PCA counter with this module s compare capture register causes the CEXn pin to toggle PWMn PWM control PWMn 1 enables the CEXn pin to be used as a pulse width modulated output ECCFn Enable CCFn interrupt Enables compare capture flag CCFn in the CCON register to generate an interrupt Note The bits CAPNn CCAPMn 4 and CAPPn CCAPMn 5 determine the edge on which a capture input will be active If both bits are set both edges will be enabled and a capture will occur for either transition This document information is the intellectual property of Megawin Technology Co Ltd 34 Megawin Technology Co Ltd 1999 right reserved Version 1 1 09 2006 CF MEGAWIN MPC82L52 54 MAKE YOU WIN M PC82E52 54 There are two additional registers associated with each of the PCA modules CCAPnH and CCAPnL They are the registers that store the 16 bit count when a capture occurs or a compare should occur When a module is used in the PWM mode in addition to the above two registers an extended register PCAPWMnh is used to improve the range of the duty cycle of the output The improved range of the duty cycle starts from 096 up to 10095 with a step of 1 256 PCAPWMO PCAPWM1 PCAPWM2 PCAPWMS PWM Mode Auxiliary Registers 7 6 5 4 3 2 1 0
36. O TRO IE1 171 IE0 ITO ean Timer 1 High HEEN N 9EH 9DH 9 9BH 99H SCON Serial Port Control sm Or SMi SM2 TB8 b RB8 PCON Power Control 87H SMOD SMODO 00xx0000B This document information is the intellectual property of Megawin Technology Ltd 9 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 The following SFRs are new added BIT ADDRESS amp SYMBOL RESET VALUE 000000xxB xxxxx000B x0000000B SYMBOL DESCRIPTION AUXR Auxiliary Register PCON2 Power Control 2 Interrupt Priority High B7H 5H 6H TOX12 71X12 URMOX6 EADCI ESPI ENLVFI 2 CKS2 CKS1 50 PSPIH_ LUD PSH PTI PXH PXH save SADDR memes EN ADCON SPEED1 SPEEDO ADCI ADCS 52 CHS1 CHSO ADCTL ADC Control Register ADC Result ADCH Higher 8 bits ADC Result BOSE Lower 2 bits WDTCR Watch dog Timer WRF ENW CLRW WIDL PS2 PSI 50 0 000000 POMO PortO Mode Register 0 POMO 2 POMO 1 00H 1 PortO Mode Register 1 POM1 2 1 1 00H P1MO 1 Mode Register 0 1 0 6 P1M0 5 1 0 4 1 0 2 1 1 P1M1 Port1 Mode Register 1 P1M1 6 P1M1 5 1 1 4 P1M1 2 9 B8 B7 B6 B5 B4 B3 B2
37. PTI 1 AEH ADH ACH ABH ASH ASH Interrupt Enable EA EPCALVD ESPLADO ES ETO Exo TMOD GATE C T M1 MO GATE M1 BDH 8BH 89H TCON Control TFi TRI IE1 IT1 IEO 0 High High 9EH 9AH 99H SCON Serial Port Control SMOFE SMi SM2 REN 1788 RB8 PCON Control SMOD SMODO 00xx0000B This document information is the intellectual property of Megawin Technology Co Ltd 7 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 CF MEGAWIN MAKE YOU WIN MPC82L52 54 MPC82E52 54 The following SFRs are new added SYMBOL DESCRIPTION MSB BIT ADDRESS amp SYMBOL RESET VALUE AUXR Auxiliary Register TOX12 1 12 URMOX6 EADCI ESPI ENLVFI 5 000000xxB PCON2 Power Control 2 E CKS2 CKS1 CKSO xxxxx000B PPCAH PSPIH Interrupt Priority High LVD ADC PT1H PX1H SADEN Slave Address Mask PXOH 0000000 00H son memes ADCTL ADC Control Register ADCON SPEED1 SPEEDO ADCS CHS2 CHS1 ADC Resun B7 85 B3 B2 B1 BO NM WDTCR Watch dogTimer WRF P1MO Port Mode Register 0 91H 1 0 7 1 0 6 1 0 5 WIDL 1 0 3 1 0 2 52 PS1 P1M0 1 xxH 50 0x000000B
38. Port Pin SS 6 1 2 Dual Device where either can be a Master Slave Two devices are connected to each other and either device can be a master or a slave When no SPI operation is occurring both can be configured as masters with MSTR 1 SSIG 0 and P1 4 SS configured in quasi bidirectional mode When any device initiates a transfer it can configure P1 4 as an output and drive it low to force a mode change to slave in the other device MOSI MOSI Master Slave SPICLK Slave Master SS SS This document information is the intellectual property of Megawin Technology Co Ltd 26 Megawin Technology Co Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 6 1 3 Single Master amp Multiple Slaves For the master can use any port pin including P1 4 SS to drive the SS pins of the slaves For all the slaves SSIG is 0 and are selected by their corresponding SS pins Slave 1 SPICLK SPICLK F ies Master Slave 2 This document information is the intellectual property of Megawin Technology Co Ltd 27 Megawin Technology Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 6 2 Configuring the SPI Table SPI Master and Slave Selection SPEN SSIG SS MSTR MISO MOSI SPICLK SPCTL 6 SPCTL 7 pin sPcrL4 Mode pin pin pin He ts 1 4 1 7
39. and the SADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1 A unique address for slave 1 would be 1100 0001 since a 1 in bit O will exclude slave 0 Both slaves can be selected at the same time by an address which has bit 0 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000 In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0 Slave 0 SAD 1100 0000 SADI 1001 Given 1100 0 0 Zw lI ps p p Slave 1 SADDR 1110 0000 SADEN 1111 1010 Given 1110 0 0 This document information is the intellectual property of Megawin Technology Co Ltd 22 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 SY MEGAWIN MPC82L52 54 MAKE YOU WIN MPC82E52 54 Slave 2 SADDR 1110 0000 SADEN 1111 1100 Given 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit 0 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0
40. bled Watchdog Timer 45 11 In System Programming 16 nete ss Res es ed Ne meet mote tape tacitis 48 11 1 Bootfrom ISP memory to run ISP code 49 11 2 Operation Flow of SP es RE SERE Es geed ee ees ke EE int eie 51 11 3 Demo of the ME o RESET 54 11 4 Note on In System Programming 0000 55 12 In Application Programming IAP 56 12 1 IAP memory 56 12 2 Update the data in the 56 12 3 IAP memory vs Settings of ISP memory and 57 12 3 1 MPC82L E 52 57 12 3 2 MPC82L E 54 AP melOFy 59 12 4 Note on 4 4 24 000000 63 13 Programmable System Clock du se UN UO Par tan dpud Rod 64 14 Wake up from Power down 65 15 Power On and Brown Out Detection oo mieten 66 15 1 P W r Ori R 66 15 2 Brown Out Detection ERK Ed DE ee DR Re Ee Reede eek Re
41. ck 4 3 Mode 2 ee ee EE ee ee ee EE ee ee ee ee EE ee ee 18 43 Mode 2 EER EE um i M cH 19 AA ModE ii u uu uu T EE 19 SEE EER EA AE AN ER Ee N AE RA OE AA De AR AE He 20 5 1 Ee ese 20 5 2 Enhanced Feature Frame Error 2 0 21204 410 21 5 3 Enhanced Feature Automatic Address 22 6 Serial Peripheral Interface 5 24 6 1 Typical SPI Configurations outs dud 26 6 1 1 Single Master amp Single 26 6 1 2 Dual Device where either be Master or a Slave 26 6 1 3 Single Master Multiple 27 6 2 Configuring the Tm 28 6 2 1 Additional Considerations for 1 0 0 4002 11 6 nnns 28 6 2 2 Additional Considerations for a Master 28 6 23 Mode Charge on 4SsS EO ERRARE 29 624 Write eo IE of ME OE EN 29 6 2 5 SPI Cleele Rate Select odisea roe a N aa 29 6 3 Data Mode EE 30
42. d byte contains either the Given address or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Automatic address recognition is shown in the following figure The 8 bit mode is called Mode 1 In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address Mode 0 is the Shift Register mode and SM2 is ignored Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two special Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to be used and which bits are don t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme Slave 0 SADDR 1100 0000 SADEN 1111 1101 Given 1100 00 0 Slave 1 SADDR 1100 0000 SADEN 1111 1110 Given 1100 000X In the above example SADDR is the same
43. damaged users should take care the total current not more than 40 for sourcing or sinking regardless of a 3 3V device or a 5V device That means that the device can source total 40mA and sink total 40mA at the same time without causing any damage to itself This document information is the intellectual property of Megawin Technology Co Ltd 16 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 gw MPC82L52 54 Ad MEGA WIN MPC82E52 54 3 On chip expanded RAM XRAM In addition to the standard 256 bytes of internal RAM the MPC82L E 54 has on chip 256 bytes of expanded RAM XRAM User can use or MOVX DPTR to access them Since these MOVX instructions are modified for XRAM accessing the status of PO P2 and P3 7 RD are not affected while these instructions are executed Using the XRAM in Software For KEIL C51 compiler to assign the variables to be located at XRAM the pdata or xdata definition should be used After being compiled the variables declared by pdata and xdata will become the memories accessed by MOVX Ri and MOVX DPTR respectively Thus the MPC82L E 54 hardware can access them correctly The user can get the following descriptions from the Keil Software Cx51 Compiler User s Guide Explicitly Declared Memory Types You may specify where variables are stored by including a memory type specifier 1n the variable declaration T
44. dule s capture registers CCAPnL and CCAPnH If the CCFn and the ECCFn bits for the module are both set an interrupt will be generated Function Block Diagram gt PCA INTERRUPT PCA TIMER COUNTER CAPTURE CCAPnH CCAPnL m pi 0 1 1 0 2 0 OR 1 This document information is the intellectual property of Megawin Technology Ltd 36 Megawin Technology Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 7 2 2 16 bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the module s CCAPMnh register The PCA timer will be compared to the module s capture registers and when a match occurs an interrupt will occur if the CCFn and the ECCFn bits for the module are both set Function Block Diagram e je e WRITE TO CCAPnH RESET 2 INTERRUPT WRITETO CCAPnH CCAPnL Co GOES CCAPnL i ENABLE 16 BIT COMPARATOR 0 PCA TIMER COUNTER 0 0 1 0 0 7 2 3 High Speed Output Mode In this mode the CEX output associated with the PCA module will toggle each time a match occurs between the PCA counter and the module s capture registers To activate this mode the TOG MAT and ECOM bits in the module s CCAPMn register must be set Function Block Diagram WRITE TO CCAPnH RESET PCA INTERRUPT WRITE TO TO CCFn CCAP
45. e ADCS bit The conversion time is controlled by bits SPEED1 and SPEEDO Normally 210 clock cycles are enough for a conversion under Fosc 12MHz For higher Fosc 420 clock cycles may be needed Once the conversion is finished the hardware will 1 automatically clear the ADCS bit 2 load the conversion result into the ADC register for MPC82L E 52 and ADCH ADCL registers for MPC82L E 54 and 3 set the interrupt flag ADCI User can check if the conversion is finished by polling the ADCI flag If the ADC interrupt is enabled by setting bits EADCI AUXH 4 ESPI ADC IE 5 the CPU will enter its nterrupt Service Routine when the conversion is completed And the ADCI flag should be cleared by software Refer to Section 9 for interrupt of the ADC Note the ADC should be powered off before entering idle mode to reduce power consumption This document information is the intellectual property of Megawin Technology Co Ltd 40 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 MP C82L52 54 MPC82E52 54 MEGAWIN MAKE YOU WIN LS 20 9 Interrupt The MPC82L E 52 54 has a 9 source 4 level interrupt structure The 9 interrupt sources and their interrupt vectors are shown in the following table Table Interrupt Sources Source Request Bits Polling Priority Vector Address INTO IEO highest priority 0003H Timer 0 TFO 000BH INT1 IE1 0013H Timer 1 TF1 001
46. e Setting All the four operation modes of the serial port are the same as those of the standard 8051 except the baudrate setting The bit 6 and bit 5 in AUXR provide a new option for the baudrate setting as listed below Table Baudrate Setting Serial Port Mode Compatible to standard 8051 New option Mode 0 Baudrate Fosc 12 Baudrate Fosc 2 if AUXR 5 URM0X6 is 0 if AUXR 5 URM0X6 is 1 Mode A Baudrate 2870 32 x Fosc 12x 256 TH1 Baudrate 25 97 42 x Fosc 256 TH1 if AUXR 6 T1X12 is 0 if AUXR 6 T1X12 is 1 Mode 2 Baudrate 2SMOD 64 x Fosc Where Fosc is the system clock AUXR Auxiliary Register 7 6 5 4 3 2 1 0 TOX12 T1X12 6 EADCI ESPI ENLVFI T1X12 Timer 1 clock source select Set to select Fosc as the clock source and clear to select Fosc 12 URMOX6 Serial Port mode 0 baudrate select Note Since these two bits are 0 after any reset it is compatible to the standard 8051 by default This document information is the intellectual property of Megawin Technology Co Ltd 20 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 5 2 Enhanced Feature Frame Error Detection While the SMODO bit in PCON bit 6 is set the hardware will set the FE bit SCON 7 when an invalid stop bit is detected The FE bit is not cleared by valid frames but should be cleared by sof
47. e the following Table PS2 PS1 PSO Prescaler value 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 In addition to being initialized by software the WDTCR register can also be automatically initialized at power up by the hardware options HWENW HWWIDL and HWPS 2 0 which should be programmed by a universal Writer or Programmer as described below If HWENW is programmed to enabled then hardware will automatically do the following initialization for the WDTCR register at power up 1 set ENW bit 2 load HWWIDL into WIDL bit and 8 load HWPS 2 0 into PS 2 0 bits For example If HWWIDL and HWPS 2 0 are programmed to be 1 and 5 respectively then WDTCR will be initialized to be 0x2D when MCU is powered up as shown below WDTCR Vatch Dog Timer Control Register 7 6 5 3 2 1 0 WRF ENVY CLRW WIDL PS2 PS1 PSO HWENW HWWIDL HWPS 2 0 This document information is the intellectual property of Megawin Technology Ltd 45 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 fy 7 gt MEGAWIN YOU WIN MPC82L52 54 MPC82E52 54 WDT Block Diagram 182 18 12 8 bit prescalar Where Fosc is the system clock WDT overflow period Tes overflow period is determined the formula 2 x 12 x Prescaler Fosc 15 bit Timer WDTCR Register The following Table
48. echnology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 19 Instruction Set The Instruction Set is fully compatible with that of the standard 8051 except the execution time i e the number of clock cycles required to execute an instruction The shortest execution time is just one system clock cycle 1 Fosc and the longest is 6 system clock cycles 6 Fosc The MOVX instructions however are omitted for MPC82L E 52 and function modified for MPC82L E 54 for XRAM access Prior to introducing the Instruction Set users should take care the following notes Rn Working register RO R7 of the currently selected Register Bank direct 128 internal RAM locations any port control or status register QRi Indirect internal RAM location addressed by register RO or R1 data 8 Dit constant included in instruction datal6 16 bit constant included in instruction 16 bit destination address Used by LCALL and LJMP A branch can be anywhere within the addr16 64K byte program memory address space 11 bit destination address Used by ACALL and AJMP The branch will be within the same 2K byte 11 e of program memory the first byte of the following instruction Signed 8 bit offset byte Used by SJMP and all conditional jumps Range is 128 to 127 bytes 1 dur dis relative to first byte of the following instruction
49. ed Version 1 1 09 2006 CF MEGAWIN MPC82L52 54 MAKE YOU WIN M PC82E52 54 PCA Timer Counter PCA V MODULES TIMER 0 OVERFLOW Je4 10 UP COUNTER EXTERNAL INPUT E exer DH forol IN sisi Where OSC means Fosc the system clock The CCON register contains the run control bit for the PCA and the flags for the PCA timer and each module To run the PCA the CR bit CCON 6 must be set by software The PCA is shut off by clearing this bit The CF bit CCON 7 is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set The CF bit can only be cleared by software CCFO CCF3 are the flags for module 0 module 3 respectively and they are set by hardware when either a match or a capture occurs These flags also can only be cleared by software CCON PCA Counter Control Register 7 6 5 4 3 2 1 0 CF CR 2 CCF1 CCF0 CF PCA Counter Overflow flag Set by hardware when the counter rolls over CF flag can generate an interrupt if bit ECF in CMOD is set CF may be set by either hardware or software but can only be cleared by software CR PCA Counter Run control bit Set by software to turn the PCA counter on Must be cleared by software to turn the PCA counter off CCF3 Module 3 interrupt flag Set by hardware when a match o
50. er The range of the IAP memory depends on the contents of IAPLB as listed below lower boundary IAPLB 7 0 x256 and IAP higher boundary ISP start address 1 Where the IAPLB must be an even number Section 12 3 lists all the possible ranges for IAP memory versus different ISP size and programmed IAPLB 12 2 Update the data in the IAP memory Because the IAP memory is part of Flash memory only Page Erase is provided for Flash erasing To update one byte in the users can not directly program the new datum into that byte The following steps show the correct updating procedure Step1 Step2 Step3 Step4 Save the whole page data 512 bytes to a buffer also with size of 512 bytes Erase this page using Page Erase mode of ISP Update the wanted byte s in the buffer Program the updated data out of the buffer into this page using Byte Program mode of ISP EE Owe To read the data in the IAP memory users can use either the MOVC A A DPTR instruction or the Read mode of ISP Users might ask Where is the buffer The buffer comes from the internal RAM The buffer size however might not be 512 bytes due to the limitation of RAM size According to the available size of the internal RAM which can be dedicated for the buffer we can know how many bytes in each Flash page can be used as the non volatile storage That is if 128 bytes can be dedicated for the buffer then only 128 bytes i
51. ffer so that the shift register is free to accept a second character However the received character must be read from the Data Register SPDAT before the next character has been completely shifted in Otherwise the previous data is lost WCOL be cleared in software by writing 1 to the bit 6 2 5 SPI Clock Rate Select The SPI clock rate selection in master mode uses the SPR1 and SPRO bits in the SPCTL register as shown below SPR1 SPRO SPI Clock Rate Fosc 128 Where Fosc is the system clock This document information is the intellectual property of Megawin Technology Co Ltd 29 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 6 3 Data Mode Clock Phase Bit CPHA allows the user to set the edges for sampling and changing data The Clock Polarity bit CPOL allows the user to set the clock polarity The following figures show the different settings of CPHA 6 3 1 SPI Slave Transfer Format with CPHA 0 Clock Cycle 1 Data 4 sampled SPICLK CPOL 0 SPICLK CPOL 1 1st bit MOSI Slave Input MISO 5 Slave Output 3 5 Not defined if SSIG 0 This edge is used by the slave to shift out the 1st bit of each data byte while CPHA D 6 3 2 SPI Slave Transfer Format with 1 Clock Cycle Data sampled i SPICLK CPOL 0 MOSI Slave Input MISO Slave Output No
52. ge address in IFADRH amp IFADRL MOV IFADRL MOV SCMD 46h trigger ISP processing MOV SCMD 0B9h Now in processing will halt here until complete F 2 Byte Program Mode OV IFMT 02h select Byte Program Mode MOV IFADRH 111 byte address IFADRH 6 IFADRL MOV IFADRL OV TED 22 fill the data to be programmed in IFD MOV SCMD 46h trigger ISP processing MOV SCMD 0B9h Now in processing will halt here until complete 3 Verify using Read Mode MOV 01 select Byte Read Mod OV IFADRH fill byte address in IFADRH 6 IFADRL OV IFADRL MOV SCMD 46h trigger ISP processing OV SCMD f0B9h Now in processing will halt here until complete OV IFD data will be in IFD CJNE A wanted ISP error compare with the wanted valu ISP error This document information is the intellectual property of Megawin Technology Co Ltd 54 Megawin Technology Co Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 11 4 Note on In System Proqramming During In System Programming the CPU halts for a while for internal ISP processing At this time the interrupt will queue up for being serviced if the interrupt is enabled previously Once the ISP is complete the CPU continues running and the interrupts in the queue will be serviced immediately if t
53. gy Ltd Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 73 Only used by MPC82L E 54 to access the expanded RAM This document information is the intellectual property of Megawin Technology Co Ltd Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 MEGAWIN MPC82L52 54 MAKE YOU WIN M PC82E52 54 19 3 Data Transfer Mnemonic Description Byte a ae DATA TRANSFER MOV A Rn Move register to Acc 1 1 MOV A direct Move direct byte o Acc 2 2 MOV A Ri Move indirect RAM to Acc 1 2 MOV A data Move immediate data to Acc 2 2 MOV Rn A Move Acc to register 1 2 MOV Rn direct Move direct byte to register 2 4 MOV Rn data Move immediate data to register 2 2 MOV direct A Move Acc to direct byte 2 3 MOV direct Rn Move register to direct byte 2 3 MOV direct direct Move direct byte to direct byte 3 4 MOV direct Ri Move indirect RAM to direct byte 2 4 MOV direct data Move immediate data to direct byte 3 3 MOV Ri A Move Acc to indirect RAM 1 3 MOV Ri direct Move direct byte to indirect RAM 2 3 MOV Ri data Move immediate data to indirect RAM 2 3 MOV DPTR datal6 Load DPTR with a 16 bit constant 3 3 MOVC A A DPTR Move code byte relative to DPTR to Acc 1 4 MOVC A A PC Move code byte relative to PC to Acc 1 4 MOVX A Ri Note Move exte
54. he following table summarizes the available memory type specifiers Memory Type Description Program memory 64 KBytes accessed by opcode MOVC A DPTR Directly addressable internal data memory fastest access to variables 128 bytes Indirectly addressable internal data memory accessed across the full internal address space 256 bytes Bit addressable internal data memory supports mixed bit and byte access 16 bytes External data memory 64 KBytes accessed by opcode MOVX DPTR Extended RAM and ROM memory spaces up to 16MB accessed by user defined routines or specific chip extensions Philips 80C51MX Dallas 390 Paged 256 bytes external data memory accessed by opcode Rn As with the signed and unsigned attributes you may include memory type specifiers in the variable declaration Example char data varl char code text ENTER PARAMETER unsigned long xdata array 1001 float idata x y z unsigned int pdata dimension unsigned char xdata vector 10 4 4 char bdata flags This document information is the intellectual property of Megawin Technology Ltd 17 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 4 Timer 0 and Timer 1 After power up or reset the default function and operation of Timer 0 and Timer 1 is fully compatible with the standard 8051 MCU The only difference is that besides Fosc
55. he interrupt flag is still active Users however should be aware of the following 1 Any interrupt not be serviced in time during the CPU halts for ISP processing 2 The low level triggered external interrupts INTO and INT1 should keep active until the ISP is complete or they will be neglected This document information is the intellectual property of Megawin Technology Co Ltd 55 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 12 Application Programming IAP First please refer to Section 1 3 for Flash Memory Configuration The MPC82L E 52 54 is In Application Programmable IAP which allows some region in the Flash memory to be used as non volatile data storage while the application program is running This useful feature can be applied to the application where the data must be kept after power off Thus there is no need to use an external serial EEPROM such as 93 46 24C01 and so on for saving the non volatile data 12 1 IAP memory Boundary Range In fact the operating of IAP is the same as that of ISP except the Flash range to be programmed is different The for ISP is located within the AP memory while the range for IAP is located within the configured IAP memory Prior to using the IAP feature users should configure an IAP memory by programming a proper value to the option APLB 7 0 using a universal Writer or Programm
56. ion registers are related to the operation This document information is the intellectual property of Megawin Technology Co Ltd 24 Megawin Technology Co Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 SPCTL SPI Control Register 7 6 5 4 3 2 1 0 SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 SSIG SS is ignored If SSIG 1 MSTR decides whether the device is a master or slave If SSIG 0 the SS pin decides whether the device is a master or slave SPEN SPI enable If SPEN 1 the SPI is enabled If SPEN O the SPI interface is disabled and all SPI pins will be general purpose ports DORD SPI data order 1 The LSB of the data byte is transmitted first 0 The MSB of the data byte is transmitted first MSTR Master Slave mode select CPOL SPI clock polarity select 1 SPICLK is high when idle The leading edge of SPICLK is the falling edge and the trailing edge is the rising edge 0 SPICLK is low when idle The leading edge of SPICLK is the rising edge and the trailing edge is the falling edge CPHA SPI clock phase select 1 Data is driven on the leading edge of SPICLK and is sampled on the trailing edge 0 Data is driven when SS pin is low SSIG 0 and changes on the trailing edge of SPICLK Data is sampled on the leading edge of SPICLK Note If SSIG 1 CPHA must not be 1 otherwise the operation is not defi
57. is enabled SPEN 1 and selected as master writing to the SPI data register SPDAT by the master starts the SPI clock generator and data transfer The data will start to appear on MOSI about one half SPI bit time to one SPI bit time after data is written to SPDAT Before starting the transfer the master may select a slave by driving the SS pin of the corresponding device low Data written to the SPDAT register of the master is shifted out of MOSI pin of the master to the MOSI pin of the slave And at the same time the data in SPDAT register of the selected slave is shifted out on MISO pin to the MISO pin of the master After shifting one byte the SPI clock generator stops setting the transfer completion flag SPIF and an interrupt will be created if the SPI interrupt is enabled The two shift registers in the master CPU and slave CPU can be considered as one distributed 16 bit circular shift register When data is shifted from the master to the slave data is also shifted in the opposite direction simultaneously This means that during one shift cycle data in the master and the slave are interchanged This document information is the intellectual property of Megawin Technology Co Ltd 28 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 6 2 3 Mode SS pin If SPEN 1 SSIG 0 MSTR 1 and SS pin 1 the SPI is enabled in master mode In
58. ives the pull down transistor of the port pin when the port register contains a logic 0 To use this configuration in application a port pin must have an external pull up typically a resistor tied to VDD The pull down for this mode is the same as for the quasi bidirectional mode In addition the input path of the port pin in this configuration is also the same as quasi bidirectional mode port latch data gt input data 2 1 3 Input Only Hi Z input only configuration is a Schmitt triggered input without any pull up resistors on the pin input data x 2 1 4 Push Pull Output The push pull output configuration has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port register contains a logic 1 The push pull mode may be used when more source current is needed from a port output In addition the input path of the port pin in this configuration is also the same as quasi bidirection mode strong port latch data input data This document information is the intellectual property of Megawin Technology 15 Megawin Technology Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 2 2 Maximum Ratings for Port Outputs While port pins function as outputs which can source or sink a current to prevent the device from being permanently
59. ll LCALL addrie6 Long subroutine call 2 6 3 6 RET Return from subroutine 1 4 RETI Return from interrupt subroutine 1 4 AJMP addr11 Absolute jump 2 3 LJMP addr16 Long jump 3 4 SJMP rel Short jump 2 3 JMP A DPTR Jump indirect relative to DPTR 1 3 JZ rel Jump if Acc is zero 2 3 JNZ rel Jump if Acc not zero 2 3 JC rel Jump if Carry is set 2 3 JNC rel Jump if Carry not set 2 3 JB bit rel Jump if direct bit is set 3 4 JNB bit rel Jump if direct bit not set 3 4 JBC bit rel Jump if direct bit is set and then clear bit 3 5 A direct rel Compare direct byte to Acc and jump if not equal 3 5 A data rel Compare immediate data to Acc and jump if not equal 3 4 Rn data rel Compare immediate data to register and jump if not equal 3 4 CJNE Ri data rel Compare immediate data to indirect RAM and jump if not 3 5 DJNZ Rn rel Decrement register and jump if not equal 2 4 DJNZ direct rel Decrement direct byte and jump if not equal 3 5 NOP No operation 1 1 This document information is the intellectual property of Megawin Technology Ltd Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 76
60. n each page can be used as the following Figure shows Of course if only 64 bytes dedicated for the buffer then 128 is replaced with 64 In detailed description if the available buffer size is 128 bytes and total 260 bytes of non volatile storage are needed the user should configure 1 5K bytes 3 Flash pages because 260 128 128 4 E 3 pages of IAP memory for this application This document information is the intellectual property of Megawin Technology Ltd 56 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 MPC82L52 54 MPC82E52 54 MAKE YOU WIN fy 7 2 MEGAWIN only 128 bytes used 4 IAP lower boundary One Flash page 512 bytes only 128 bytes used 1 One Flash page 512 bytes only 128 bytes used 1 One Flash page 512 bytes IAP memory only 128 bytes used 1 512 bytes IAP higher boundary 12 3 IAP memory vs Settings of ISP memory and IAPLB As we have known the IAP memory and ISP memory are user configured Table 12 3a Table 12 3h show a variety of settings 12 3 14 MPC82L E 52 IAP memory Table 12 3a No ISP For MPC82L E 52 Available AP memory IAP memory IAPLB Range Size IAP low boundary Range Size 0x02 0x0000 0x01FF 0 5KB 0x0200 0x0200 Ox1FFF 7 5KB 0x04 0x0000 0x03FF 1 0KB 0x0400 0x0400 0x1FFF 7 0 0x06 0x
61. nL ENABLE PCA TIMER COUNTER se u 0 0 1 1 0 This document information is the intellectual property of Megawin Technology Ltd 37 Megawin Technology Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 7 2 4 PWM Mode All of the PCA modules can be used as PWM outputs The frequency of the output depends on the clock source for the PCA timer All of the modules will have the same frequency of output because they all share the PCA timer The duty cycle of each module is determined by the module s capture register CCAPnL and the extended 9 pit ECAPnL When the 9 bit value of 0 CL is ess than the 9 bit value of ECAPnL CCAPnL the output will be low and if equal to or greater than the output will be high When CL overflows from OxFF to 0x00 ECAPnL CCAPnL is reloaded with the value of ECAPnH CCAPnH This allows updating the PWM without glitches The PWMn and bits in the module s register must be set to enable the PWM mode Using the 9 bit comparison the duty cycle of the output can be improved to really start from 096 and up to 10095 The formula for the duty cycle is Duty Cycle 1 ECAPnH CCAPnH 256 Where CCAPnH is the 8 bit value of the CCAPnH register and ECAPnH bit 1 in the PCAPWMn register is 1 bit value So ECAPnH CCAPnH forms a 9 bit value for the 9 bit
62. ndary IAPLB x256 3 IAP higher boundary z ISP start address 1 Total Flash Memory 8KB IAP lower boundary Nonvolatile data IAP memory IAP higher boundary ISP start address I ISP code ISP memory 3KB 2KB 1KB 0KB Ox1FFF Y Y MPC82L52 MPC82E52 MPC82L E 54 With total Flash Memory 15 5K bytes Note D 1 1 ISP start address has four options 0x3000 if ISP 3 5KB or 0x3400 if 5 2 5 or application ap memory 0x3800 if 5 1 5 or 0x3E00 if no ISP 2 IAP lower boundary IAPLB x256 3 IAP higher boundary z ISP start address 1 1 Total Flash Memory IAP lower boundary 15 5KB Nonvolatile data IAP memory IAP higher boundary ISP start address ISP code ISP memory 3 5KB 2 5KB 1 5KB 0KB Y Y MPC82L54 MPC82E54 This document information is the intellectual property of Megawin Technology Co Ltd 12 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 2 VO Ports The MPC82L E 52 has two I O ports P1 and while the MPC82L E 54 has four I O ports PO P1 P2 and The exact number of I O pins available depends on their package type see the following Table Table Pins Available v s Package Type SkinnyDIP 28 SkinnyDIP 20 ag PLCC 32 SOP 20 SSOP 28 27 I O pins
63. ned SPR1 SPRO0 SPI clock rate select when in master mode 00 Fosc 4 01 Fosc 16 10 Fosc 64 11 Fosc 128 Where Fosc is the system clock SPSTAT SPI Status Register 7 6 5 4 3 2 1 0 SPIF WCOL SPIF SPI transfer completion flag When serial transfer finishes the SPIF bit is set and an interrupt is generated if the ESPI AUXR 3 bit the ESPI ADC IE 5 bit and the EA IE 7 bit are set If SS pin is driven low when SPI is in master mode with SSIG 0 SPIF will also be set to signal the mode change The SPIF is cleared in software by writing 1 to this bit WCOL SPI write collision flag The WCOL bit is set if the SPI data register SPDAT is written during a data transfer The WCOL flag is cleared in software by writing 1 to this bit SPDAT SPI Data Register 7 6 5 4 3 2 1 0 MSB LSB SPI data buffer for transmit and receive This document information is the intellectual property of Megawin Technology Co Ltd 25 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 6 1 Typical SPI Confiqurations 6 1 1 Single Master amp Single Slave For the master can use any port pin including P1 4 SS to drive the SS pin of the slave For the slave SSIG is 0 and SS pin is used to select the slave MOSI MOSI Master SPICLK SPICLK
64. nology Co Ltd 1999 All right reserved Version 1 1 09 2006 821 52 54 WIN MPC82E52 54 IPH Interrupt Priority High Register 7 6 5 4 3 2 1 0 PPCAH_LVD PSPIH_ADC PSH PT1H PX1H LVD amp LVD interrupts priority bit high PSPIH ADC SPI amp ADC interrupts priority bit high PSH Serial Port interrupt priority bit high PT1H Timer 1 interrupt priority bit high PX1H External interrupt 1 priority bit high Timer 0 interrupt priority bit high PXOH External interrupt O priority bit high The IPH register when combined with the IP register determines the priority of each interrupt The priority of each interrupt is determined as shown in the following table IPH x IP x Interrupt Priority Level 1 1 Level 3 highest priority 1 0 Level 2 0 1 Level 1 0 0 Level 0 lowest priority For example if IPH 3 1 0 then Timer 1 has the priority level equal to 2 which is higher than level 1 with IPH 3 IP 3 0 1 or level 0 with IPH 3 IP 3 0 0 This document information is the intellectual property of Megawin Technology Co Ltd 42 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 9 1_ Interrupt Architecture 2 ite Lescl Incem IP amp IPH IE Reglstar Reglsters
65. o software upset The WDT consists of a 15 bit free running counter an 8 bit prescaler and a control register WDTCR To enable the WDT users must set ENW bit WDTCR 5 When the WDT is enabled the counter will increment one by an interval of 12 x Prescaler Fosc And now the user needs to clear it by writing 1 to the CLRW bit WDTCR 4 before WDT overflows When WDT overflows the MCU will reset itself and re start Why is the called One time Enabled It is because Once the WDT is enabled 1 there is no way to disable it except power on reset 0 The WDTCR register will keep the previous programmed value unchanged after hardware RST pin reset software reset and WDT reset For example if the WDTCR is Ox2D it still keeps at Ox2D rather than 0x00 after these resets Only power on reset can initialize it to 0x00 WDTCR Watch Dog Timer Control Register 7 6 5 4 3 2 1 0 WRF ENW CLRW WIDL PS2 PS1 50 Note This is Write only register WRF WDT reset flag When WDT overflows this bit is set by H W It should be cleared by software ENW Enable WDT Set to enable WDT Note Once set it can only be cleared by power on reset CLRW Clear WDT Writing 1 to this bit will clear WDT Note It has no need to be cleared by writing O WIDL WDT in Idle mode Set this bit to let WDT keep counting while the MCU is in the Idle mode PS2 PS1 Prescaler select Se
66. p is turned on whenever the port register for the pin contains a logic 1 This very weak pull up sources a very small current that will pull the pin high if it is left floating A second pull up called the weak pull up is turned on when the port register for the pin contains a logic 1 and the pin itself is also at a logic 1 level This pull up provides the primary source current for a quasi bidirectional pin that is outputting a 1 If this pin is pulled low by the external device this weak pull up turns off and only the very weak pull up remains on In order to pull the pin low under these conditions the external device has to sink enough current to over power the weak pull up and pull the port pin below its input threshold voltage The third pull up is referred to as the strong pull up This pull up is used to speed up low to high transitions on a quasi bidirectional port pin when the port register changes from a logic 0 to a logic 1 When this occurs the strong pull up turns on for two CPU clocks quickly pulling the port pin high port latch data input data lt Ma IOO Im This document information is the intellectual property of Megawin Technology Co Ltd 14 Megawin Technology Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 2 1 2 Open Drain Output The open drain output configuration turns off all pull ups and only dr
67. r capture occurs Must be cleared by software CCF2 PCA Module 2 interrupt flag Set by hardware when a match or capture occurs Must be cleared by software CCF1 PCA Module 1 interrupt flag Set by hardware when a match or capture occurs Must be cleared by software CCFO PCA Module 0 interrupt flag Set by hardware when a match or capture occurs Must be cleared by software This document information is the intellectual property of Megawin Technology Ltd 33 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 The PCA interrupt system is shown below PCA Interrupt System PCA TIMERICOUNTER MODULE 0 o o r TO MODULE 1 INTERRUPT PRIORITY DECODER gt MODULE 2 MODULE 3 Each module has special function register associated with it These where n 2 0 1 2 and 3 for module 0 to module 3 respectively See the register description as follows 1 2 PCA Module Compare Capture Registers 7 6 5 4 3 2 1 0 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn ECOMn Enable Comparator ECOMn 1 enables the comparator function CAPPn Capture Positive CAPPn 1 enables positive edge capture CAPNn Capture Negative CAPNn 1 enables negative edge capture
68. r decreases to than LVD voltage it is set by hardware and should be cleared by software 15 2 Brown Out Detection Besides the POR voltage there is a higher threshold voltage LVD voltage Low Voltage Detection voltage for brown out detection The LVD voltage is 2 3V and 3 7V for MPC82L52 54 and MPC82E52 54 respectively When the VCC power decreases to the LVD voltage the Low Voltage Flag LVF bit PCON 5 will be set by hardware Note that during power up this flag will also be set and the user should clear it by software for the following brown out detecting This flag can also generate an interrupt if bits ENLVFI AUXR 2 and LVD IE 6 are both set to 1 Refer to Section 9 Interrupt Further once brown out happens the user can 1 enable the option to let the CPU enter reset state and or 2 enable the option LVFWP to inhibit any writing to the Flash memory Although the CPU can still work well between the ranges 1 9 2 3V for MPC82L52 54 and 3 3 3 7V for MPC82E52 54 they are not safe enough for the ISP IAP operation especially writing Flash memory So we strongly recommend the user to use Low Voltage Detection combined with enabling the options ENLVR or LVFWP if the IAP feature is used in his application This document information is the intellectual property of Megawin Technology Co Ltd 66 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 Ad ME
69. rnal RAM 8 bit address to Acc 1 3 DPTR Note Move external RAM 16 bit address to Acc 1 3 MOVX QRi A Note Move Acc to external RAM 8 bit address 1 4 MOVX QDPTR A Note Move Acc to external RAM 16 bit address 1 3 PUSH direct Push direct byte onto Stack 2 4 POP direct Pop direct byte from Stack 2 3 XCH A Rn Exchange register with Acc 1 3 XCH A direct Exchange direct byte with Acc 2 4 A Ri Exchange indirect RAM with Acc 1 4 XCHD A Ri Exchange low order digit indirect RAM with Acc 1 4 Note 74 ry MPC82L52 54 47 WIN MPC82E52 54 19 4 Boolean Variable Manipulation Mnemonic Description Byte ae BOOLEAN VARIABLE MANIPULATION CLR C Clear Carry 1 1 CLR bit Clear direct bit 2 4 SETB C Set Carry 1 1 SETB bit Set direct bit 2 4 CPL Complement Carry 1 1 CPL bit Complement direct bit 2 4 ANL C bit AND direct bit to Carry 2 3 ANL C bit AND complement of direct bit to Carry 2 3 ORL C bit OR direct bit to Carry 2 3 ORL C bit OR complement of direct bit to Carry 2 3 MOV C bit Move direct bit to Carry 2 3 MOV bit C Move Carry to direct bit 2 4 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 MEGAWIN 821 52 54 YOU WIN MPC82E52 54 19 5_ Proqram and Machine Control Mnemonic Description Byte IPROAGRAM MACHINE CONTROL ACALL addr11 Absolute subroutine ca
70. rsal Writer or Programmer is locked to OxFF for security disabled Not locked OSCDN enabled Oscillating gain is reduced down for EMI reduction disabled Normal gain HWBS2 only for 821 54 enabled In addition to power up the reset from RST pin will also force MCU to boot from ISP memory if ISP memory is configured disabled Where MCU boots from is determined by HWBS ENROSC enabled Enable built in RC oscillator disabled Disable built in RC oscillator HWENW accompanied with arguments HWWIDL and HWPS 2 0 enabled Automatically enable Watch dog Timer by hardware when MCU is powered up It means that In the WDTCR register HAN will automatically 1 set ENW bit 2 load HWWIDL into WIDL bit and 3 load HWPS 2 0 into P5S 2 0 bits For example If HWWIDL and HWPS 2 0 are programmed to be 1 and 5 respectively then WDTCR will be initialized to be 0x2D when MCU is powered up as shown below This document information is the intellectual property of Megawin Technology Co Ltd 69 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 821 52 54 Ad MEGA WIN MPC82E52 54 WDTCR Watch Dog Timer Control Register 6 5 4 3 2 0 WRF ENW CLRW WIDL HWENW HWWIDL HWPS 2 0 disabled No action on Watch dog Timer when MCU powered up This document information is the intellectual property of Megawin Technology Ltd 70 Megawin T
71. ry MPC82L52 54 47 WIN MPC82E52 54 Megawin MPC82L52 54 MPC82E52 54 User Manual By Vincent Y C Yu This document information is the intellectual property of Megawin Technology Co Ltd 1 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 SY MEGAWIN MPC82L52 54 MAKE YOU WIN MPC82E52 54 Contents Prela66 u occa ON ON OE OE ON OE ME N 4 uuu GE Ie Tere TS Tere 5 1 a eee ae 5 1 2 Special Function Registers 5 7 1 3 Flash Memory 12 2 aid tie ees 13 21 Porn HE AE EE EE 13 Quasti bidirectional iiri eri rei e eee Ee E e a E ve C d eL EE Ed 14 2 1 2 Open Drain 15 21 9 Mp t Only AR ER 15 2 1 4 PushPullOUPUL ES M P 15 2 2 Maximum Ratings for Port Outputs SS EER ER Se 16 On chip expanded RAM XRAM 17 4 Timer 0 and Timer nemen 18 4 Mode ER RE a EE eee 18 4 2 Model re n DE EE AE ER DR ER ED ee 18 Where OSC means Fosc the system clo
72. s High IFADRL ISP Flash Address Low ISP Flash Data ISP Sequential PONN Command Notes bit addressable reserved bit This document information is the intellectual property of Megawin Technology Co Ltd Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 CF MEGAWIN MPC82L52 54 MAKE YOU WIN M PC82E52 54 MPC82L E 54 SFRs SYMBOL DESCRIPTION EI ADDRESS amp SYMBOL C Accumulator pneus Program Status Word r E paH m Di H 000000 0 om oer om en pot e 87 86H 85H 84H 83H 82H 81H 80H 207 6 5 04 PO2 PO 97H 95H 94H 93H 92H 90H w bra 217 P16 PLS PA P2 PA 10 AIN7 AN6 ANS AN3 SPICLK MISO MOSI SS AGH A4H A3H pa gt P27 P26 P25 P24 P23 P22 P21 P20 CEX3 CEX2 6H BSH B2H P35 P34 P33 P32 P31 P3230 Porta Ti TO NTO 11111118 CEX ECI BDH BCH B8H Priority _ LVD PSPI ADC PS 1 PX1 PTO 0000000 AEH ADH ACH ABH ASH 18 interrupt Enable EA LVD ESPLADC ES ETO EX0 TMOD Timer Mode GATE M1 MO GATE C T M1 MO BDH 8CH BB 89H TCON Control TF1 TRI TF
73. s Master mode and Slave mode Up to 3 Mbps can be supported in either Master or Slave mode under the 12MHz system clock It has a Transfer Completion Flag SPIF and Write Collision Flag WCOL in the SPI status register SPSTAT register SPI Block Diagram P1 6 MISO 1 5 MOSI P17 SPICLK P14 55 SSIG sPEN lt sPR1 SPCTL ser The SPI interface has four pins SPICLK MOSI MISO and SS SPICLK MOSI and MISO are typically tied together between two or more SPI devices Data flows from master to slave on the MOSI Master Out Slave In pin and flows from slave to master on the MISO Master In Slave Out pin The SPICLK signal is output in the master mode and is input in the slave mode If the SPI system is disabled i e SPCTL 6 0 these pins function as normal I O pins SS is the optional slave select pin In a typical configuration an SPI master asserts one of its port pins to select one SPI device as the current slave An SPI slave device uses its SS pin to determine whether it is selected But if SPEN SPCTL 6 0 or SSIG SPCTL 7 1 the SS pin is ignored Note that even if the SPI is configured as a master MSTR 1 it can still be converted to a slave by driving the SS pin low if SSIG 2 0 Should this happen the SPIF bit SPSTAT 7 will be set See section Mode change on SS pin The following special funct
74. s the intellectual property of Megawin Technology Co Ltd 65 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 15 Power On Flag and Brown Out Detection 15 1 Power On Flag The CPU will not start to work until the VCC power rises up to the Power On Reset POR threshold voltage 1 9V and 3 3V for MPC82L52 54 and MPC82E52 54 respectively It means the state is activated whenever the VCC level is below the POR voltage Power On Flag POF bit PCON 4 is set to 1 by the activated POR signal Two occasions make the POR signal activated 1 during power up i e cold start or 2 when VCC power falls below the POR voltage It helps users to check if the running of the CPU begins from cold reset power up or warm reset such as RST pin reset software reset ISPCR 5 or Watchdog Timer reset The POF bit should be cleared by software PCON Power Control Register 7 6 5 4 3 2 1 0 SMOD SMODO LVF POF GF1 GFO PD IDL POF Power ON Flag POF is set to 1 by hardware during power up i e cold start or when VCC power drops below the POR voltage It can be set or reset under software control and is not affected by any warm reset such as RST pin reset software reset ISPCR 5 and WDT reset Note that it should be cleared by software LVF Low Voltage Flag Once brown out condition is detected VCC powe
75. shows the WDT overflow period for MCU running at 6MHz and 12MHz The period is the maximum interval for the user to clear the WDT to prevent from chip reset Table WDT Overflow Period at Fosc 6MHz amp 12MHz PS2 PS1 PSO Prescaler value Fosc 6MHz Fosc 12MHz 0 0 0 2 131 072 ms 65 536 ms 0 0 1 4 262 144 ms 131 072 ms 0 1 0 8 524 288 ms 262 144 ms 0 1 1 16 1 048 s 524 288 ms 1 0 0 32 2 097 s 1 048 s 1 0 1 64 4 194 s 2 097 s 1 1 0 128 8 389 s 4 194 s 1 1 1 256 16 778 s 8 389 s This document information is the intellectual property of Megawin Technology Co Ltd Megawin Technology Co Ltd 1999 right reserved Version 1 1 09 2006 46 ry MPC82L52 54 Ad MEGA WIN MPC82E52 54 Sample code for WDT Condition Fosc 6MHz Target WDT Overflow Period 1 048 seconds WDTCR_buf DATA 30h declare a buffer for WDTCR register because WDTCR is Write only register Start F ase f lt MOV WDTCR buf 400h clear buffer for WDTCR register ANL WDTCR_buf 0F8h 52 51 50 0 1 1 prescaler 16 ORL WDTCR buf 403h Fosc 6MHz Overflow Period 1 048s MOV WDTCR WDTCR buf ORL WDTCR buf 20h enable WDT MOV WDTCR WDTCR buf write to WDTCR register main loop ORL WDTCR buf 410h clear MOV WDTCR WDTCR_buf puel 7 main loop ANL WDTCR buf 40DFh disable WDT MOV WDTCR WDTCR buf This document information is the intellec
76. t defined SS if SSIG 0 This document information is the intellectual property of Megawin Technology Co Ltd 30 Megawin Technology Co Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 WIN MPC82E52 54 6 3 3 SPI Master Transfer Format with CPHA 0 Clock Cycle 1 Enable SPI es Data sampled SPICLK CPOL 0 SPICLK CPOL 1 1st bit 1 MOSI Master Output MISO Master Input SS if SSIG 0 Clock Cycle Data A sampled 1 SPICLK CPOL 0 SPICLK CPOL 1 1st bit N MOSI Master Output MISO Master Input SS if SSIG 0 This document information is the intellectual property of Megawin Technology Co Ltd 31 Megawin Technology Co Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 7 Proqrammable Counter Array PCA 7 1 Introduction to the The Programmable Counter Array PCA is a special 16 bit Timer that has four 16 bit capture compare modules associated with it Each of the modules can be programmed to operate in one of four modes rising and or falling edge capture software timer high speed output or PWM pulse width modulation output Each module has a pin associated with it module 0 is connected to P3 7 module 1 to P3 5 module 2 to P2 0 and module 3 to P2 4 The basic PCA configuration is shown in the figure as follows PCA Configuration P3 7 C
77. the ISP timing according to Fosc the system clock as listed below Fosc CKS2 CKS1 CKSO 30 24 MHz 0 0 0 24 20 MHz 0 0 1 20 12 MHz 0 1 0 12 6 MHz 0 1 1 6 3MHz 1 0 0 3 2MHz 1 0 1 2 1MHz 1 1 0 lt 1MHz 1 1 1 IFMT ISP Mode Register 7 6 5 4 3 2 1 0 MS1 MSO MS1 amp 50 Used to select the ISP mode as listed below MS1 50 ISP Mode 0 0 Standby 0 1 Read 1 0 Byte Program 1 1 Page Erase This document information is the intellectual property of Megawin Technology Co Ltd 48 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 CF MEGAWIN MPC82L52 54 MAKE YOU WIN M PC82E52 54 11 1 Boot from ISP memory to run ISP code To run the ISP code the CPU should boot from the ISP memory By means of the following two methods the CPU can boot from the ISP memory Method 1 Directly Boot from ISP memory while HWBS HWBS2 is enabled For MPC82L E 54 not only Power but also Reset from RST pin Power on if HWBS2 enabled and ISP memory exists with HWBS enabled and ISP memory exists And now HWBS is don t Now CPU will boot from ISP memory and run ISP code ISPEN 1 enable ISP function SWBS 0 select boot from AP memory and initialize ISP
78. tual property of Megawin Technology Co Ltd 47 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 11 In System Proqramminqg ISP First please refer to Section 1 3 for Flash Memory Configuration The Flash program memory supports both parallel programming and serial In System Programming ISP Parallel programming mode offers high speed programming ISP allows a device to be reprogrammed in the end product under software control The capability to field update the application firmware makes a wide range of applications possible Prior to using the ISP feature users should configure an ISP memory using a universal Writer or Programmer Several SFRs are related to ISP IFADRH ISP Flash address high register IFADRL ISP Flash address low register IFD ISP Flash data register SCMD ISP sequential command register filled sequentially with 0x46 then OxB9 to trigger ISP operation ISPCR ISP Control Register 7 6 5 4 3 2 1 0 ISPEN SWBS SWRST CFAIL CKS2 CKS1 CKS0 ISPEN Set to enable ISP function SWBS Software boot select Set to select booting from ISP memory and clear to select booting from AP memory after software reset SWRST Write 1 to trigger software reset CFAIL ISP fail flag It is set by H W if something error during ISP processing and should be cleared by S W CKS2 CKSO Set
79. tware SCON Serial Port Control Register 7 6 5 4 3 2 1 0 SMO FE SM1 SM2 REN TB8 RB8 TI RI SMO FE SMO Serial Port Mode when SMODO 0 FE Frame Error bit when SMODO 1 PCON Power Control Register 7 6 5 4 3 2 1 0 SMOD SMODO LVF POF GF1 GFO PD IDL SMODO Clear to let SCON 7 function as SMO and set to let SCON 7 function as FE os AX o1 A s X o X os X os X or X START DATA BYTE ONLY IN STOP MODE 2 3 BT SET FE BIT IF STOP BIT IS 0 FRAMING ERROR 5 0 TO UART MODE CONTROL ws Res 0 SCON 7 SMO 1 7 FE This document information is the intellectual property of Megawin Technology Ltd 21 Megawin Technology Co Ltd 1999 right reserved Version 1 1 09 2006 ry MPC82L52 54 WIN MPC82E52 54 5 3 Enhanced Feature Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled by setting the SM2 bit in SCON In the 9 bit UART modes mode 2 and mode 3 the Receive Interrupt flag RI will be automatically set when the receive
80. ument information the intellectual property of Megawin Technology Ltd 10 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 CF MEGAWIN MPC82L52 54 MAKE YOU WIN M PC82E52 54 Continued Mode auxiliary ECAPOL xxxxxx00B PCAPWM1 em Mode auxiliary ECAP1H ECAP1L xxxxxx00B PCAPWM2 xL Mode auxiliary ECAP2H ECAP2L xxxxxx00B PCAPWM3 2 Mode auxiliary ECAP3L xxxxxx00B SPSTAT SPI Status Register 00xxxxxxB SPCTL SPI Control Register DORD MSTR SPRI SPRO SPDAT SPI Data Register ISPCR ISP Control 5 SWBS SWRST CFAIL ICK2 ICK1 ICKO 0000 000 FMT IFMT ISP Flash Mode Table Flash Mode Table i MS1 MSO xxxxx000B IFADRH em Address IFADRL ju Flash Address 122 Flash Data ISP Sequential addressable reserved bit This document information is the intellectual property of Megawin Technology Co Ltd 11 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 1 3 Flash Memory Configuration MPC82L E 52 With total Flash Memory 8K bytes Note A A 1 ISP start address has four options 0x1400 if ISPZ3KB or PES 0x1800 if ISP 2KB or Application AP memory 0 1 00 if ISPZ1KB or 0x2000 if no ISP 2 IAP lower bou
81. wer down wake up sources Power down Wake up Sources IE0 Wake up IE1 if in power down EX1 EA Sample Code for Wake up from Power down is used in this example ck ck ck ck Ck KOK amp K KOK Ck ck KOK KOK Ck k KOK K k KOK KOK KOK ck k KOK ck k k k ke KOK k ka ke ko k ko k k ck k ko k ko ka k k ko k k k kao kao sk k KOK RR KK Wake up from power down by INTO interrupt e K k k k k k k k K k k K k K k KOK k K K k k k K K x lt k k k K k K K k k k k k K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ko k k K INTO BIT 0B2H PESE EA BIT PIB T EXO BIT 0 CSEG A 0000h JMP start CSEG A 0003h INTO interrupt vector address 0003h JMP IEQ isr TEG CLR EXO P do something ius RETI start i SETB INTO pull high E3 2 CLR IEO clear INTO interrupt flag SETB ITO may select falling edge low level triggered SETB EA enable global interrupt SETB EXO enable INTO interrupt ORL PCON 402h put MCU into power down mode P Now CPU is in power down mode puel Resume operation INTO is triggered by a falling edge the MCU will wake up enter IEO isr and then return here to run continuously NOP Note here must be a NOP EET This document information i
82. which it charges To ensure a valid reset the RST pin must be held high long enough to allow the oscillator to start up plus two machine cycles The following Table shows the best combinations which are adequate to all different operating frequencies C 1uF 4 7uF 10uF R About 130K About 27K About 15K Reset Circuit VDD C RST R MPC82L E 52 54 This document information is the intellectual property of Megawin Technology Ltd 68 Megawin Technology Co Ltd 1999 All right reserved Version 1 1 09 2006 ry MPC82L52 54 47 WIN MPC82E52 54 18 Hardware Options The MPC82L E 52 54 have the following hardware options All the options should be programmed by using a universal Writer or Programmer IAPLB 7 0 IAP Lower Boundary which must be an even number The boundary is determined by IAP lower boundary IAPLB x 256 LVFWP enabled Enable LVFWP Low Voltage Flash Write Protection while IAP or ISP programming disabled Disable LVFWP ENLVR enabled Enable Low Voltage Reset LVR disabled Disable LVR HWBS enabled When power up MCU will boot from ISP memory if ISP memory is configured disabled MCU always boots from AP memory SB enabled Code dumped on a universal Writer or Programmer is scrambled for security disabled Not scrambled LOCK enabled Code dumped amp Device ID read on a unive

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