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SH7612 E8000 Emulator HS7612EDD81H User`s Manual

1. 36 Allocatable Memory Area of PC Interface 39 PC Interface Board Switch oo eene nennen 40 Installing the PC Interface Board sese 41 Connecting the E8000 Station to the PC Interface Board 42 Ethernet Interface re eto Euren RE Oo bep 46 Cheapernet Interface minnis ue ede Hee ee e 47 RS 232C Interface eii eae etie atc e ie E EEE E 48 Bidirectional Parallel Interface essere 49 IPW Wand0Ow 50 File Menu and Setting Menu sss nenne nene nennen 51 Communication Setting eene nennen nenne 52 Screen Set ng ret e eret to POE E 53 Eat Menu nonne D ogni pi tete aat ent bent 54 Power On Procedures for LAN Interface 57 Power On Procedures for RS 232C Interface ssssseeeeee 62 ES000 5yst miDISK ua sis e eat iet trii t e HR 75 Part II Emulator Function Guide Figure 1 1 Figure 1 2 Cycle Reset Mode erede eR tend 114 Trigger Signal Output Timing sese nennen nennen 115 Rev 1 0 09 00 page ix of xiv HITACHI Figure 1 3 Figure 1 4 Figure 1 5 Figure 1 6 Figure 1 7 Figure 1 8 Figure 1 9 Figure 1 10 Figure 1 11 Figure 1 12 Figure 1 13 Figure 1 14 Figure 1 15 Figure 1 16 Figure 1 17 Figure 1 18 Figure
2. Pin No Pin Name Pin No Pin Name Pin No Pin Name 1 32 D7 63 D30 2 RES 33 D8 64 D31 3 VCC 34 VCC4 65 BGR 4 GND 35 D9 66 BRLS 5 GND 36 GND4 67 DACKO 6 NC 37 D10 68 DACK1 7 NC 38 D11 69 DREQO 8 GND 39 D12 70 DREQ1 9 MD4 40 D13 71 WAIT 10 NC 41 D14 72 RAS 11 VCC1 42 VCC5 73 VCC8 12 MD3 43 D15 74 CAS OE 13 GND1 44 GND5 75 GND8 14 EXTAL 45 D16 76 DQMUU WE3 15 MD2 46 D17 77 DQMUL WE2 16 NC 47 D18 78 DOMLU WE1 17 GND 48 D19 79 DQMLL WEO 18 CKIO 49 D20 80 CAS3 19 VCC2 50 VCC6 81 CAS2 20 MD1 51 D21 82 CAST 21 GND2 52 GND6 83 CASO 22 53 D22 84 CKE 23 DO 54 D23 85 RD 24 D1 55 D24 86 VCC9 25 D2 56 D25 87 REFOUT 26 VCC3 57 D26 88 GND9 27 D3 58 VCC7 89 BS 28 GND3 59 D27 90 cso 29 D4 60 GND7 91 CS1 30 D5 61 D28 92 CS2 31 D6 62 D29 93 CS3 HITACHI Rev 1 0 09 00 page 415 of 423 Table C 2 Pin Assignment of the HS7612EBH81H cont Pin No Pin Name Pin No Pin Name Pin No Pin Name 94 CS4 122 A18 150 TCK PA13 95 RD WR 123 A19 151 VCC16 96 AO 124 A20 152 TMS PA12 97 A1 125 VCC14 153 GND16 98 A2 126 A21 154 TDI PA11 99 VCC10 127 GND14 155 VCC17 100 A3 128 A22 156 TDO PA10 101 GND10 129 A23 157 GND17 102 A4 130 A24 158 PA9 STS2 103 A5 131 PB15 SRCKO SCK2 159 PA8 STXD2 104 A6 132 PB14 SRSO RXD2 160 WDTOVF PA7 105 A7 133 PB13 SRXDO TXD2 161 FTCI PA6 106 A8 134
3. PLEASE SELECT NO 1 9 L E Q X To terminate input enter E Q or X followed by RET Entering E RET saves the new specifications in the emulator flash memory initiates the LAN board and terminates LH command execution PLEASE SELECT NO 1 9 L E Q X E RET LAN CONFIGURATION FILE WRITE OK Y N Y RET FM Rev 1 0 09 00 page 60 of 423 HITACHI Entering RET saves the new specifications in the emulator flash memory without initializing the LAN board and terminates LH command execution PLEASE SELECT NO 1 9 L E Q X RET LAN CONFIGURATION FILE WRITE OK Y N Y RET FM Entering X RET terminates LH command execution without saving the new specifications PLEASE SELECT NO 1 9 L E Q X X RET FM When the emulator waits for a flash memory management tool command prompt FM entering Q RET terminates the flash memory management tool FM Q RET START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ 9 Turn off the E8000 station 10 Check that S7 and S8 in console interface switch SW1 on the E8000 station rear panel are turned off to the right and on to the left respectively 11 Turn on the power switch at the E8000 station rear panel 12 Execute the TELNET command on the host computer 13 The following messages are displayed and the internal system tests are executed E8000 MONITOR HS8000ESTO2SR Vm n C
4. essere ener 9 Optional Component Specifications essere 9 Contents of E8000 System Disk 19 Console Interface Settings sees eerte 37 PC Interface Board Specifications essere 38 Switch Settings for Memory Areas sse eene eene 40 Host Computer Interface Specifications 43 Ethernet and Cheapernet Specifications esee 44 Recommended Transceiver and Transceiver Cable esses 46 Recommended BNC T Type Connector and Thin Wire Cable 47 Emulator Monitor Commands essen ne eene 63 Flash Memory Management Tool Commands eee 65 Part II Emulator Function Guide Table 1 1 Table 1 2 Table 1 3 Table 1 4 Table 1 5 Table 1 6 Table 1 7 Table 1 8 Table 1 9 Table 1 10 Table 2 1 Table 3 1 Table 3 2 Table 3 3 Table 4 1 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 7 6 Table 7 7 SH7612 Functions eer OI RI RE 105 Emulation Functions ce ita eet eret 106 Host Computer Interface Functions esee 113 Specifiable Hardware Break Conditions sseeeeeee 119 Maximum Specifiable Numbers in Trace Mode sese 132 Maximum Number of Measurable Subroutines sse 140 Execution St t s Display 2 een teer P a an RENE PEE ER 147 Operating Status Display
5. 8 2 3 INTFC_VERIFY IV Verifies memory contents against host computer file Serial interface Command Format e Verification INTFC_VERIFY A lt offset gt lt load module type gt lt file name gt RET lt offset gt Value to be added to the address lt load module type gt Load module type R SYSROF type load module S S type load module H HEX type load module M Memory image file E ELF type load module Default SYSROF type load module lt file name gt File name in the host computer Description e Verification Verifies data transferred from the host computer against data in memory via the serial interface Use interface software IPW for the host computer INTFC VERIFY load module type gt lt file name gt RET Ifa verification error occurs all errors will be displayed in the following format lt ADDR gt lt FILE gt lt MEM gt XXXXXXXX yy y ZZ Z XXXXXXXX Verification error address yy y Load module data in hexadecimal and ASCII characters zz z Memory data in hexadecimal and ASCII characters An offset value to be added or subtracted can be specified for the address of an SYSROF type ELF type S type or HEX type load module INTFC VERIFY offset S file name gt If an offset is specified a verification address is calculated as follows Verification address load module address offset Rev 1 0 09 00 page 350 of 423 HITACHI INTFC_VER
6. Table 7 1 Emulation Commands Usable Unusable in Command Function Parallel Mode lt register gt Modifies and displays register contents Unusable ABORT Terminates emulation in parallel mode Usable ALIAS Sets displays and cancels aliases Usable ASSEMBLE Assembles program one line each Unusable BACKGROUND Sets and displays user interrupts in command Unusable INTERRUPT input wait state BREAK Sets displays and cancels software Only display function is breakpoints available BREAK CONDITION Sets displays and cancels hardware break conditions Only display function is available BREAK CONDITION UBC Sets displays and cancels hardware break conditions Only display function is available BREAK SEQUENCE Sets displays and cancels software sequential breakpoints Only display function is available CHECK Tests SH7612 pin status Unusable CLOCK Sets and displays clock Only display function is available CONFIGURATION Saves and restores configuration information Unusable and displays a list CONVERT Converts data Usable DATA CHANGE Replaces memory data Unusable DATA SEARCH Searches for memory data Unusable DISASSEMBLE Disassembles and displays memory contents Usable DUMP Displays memory contents Usable END Cancels parallel mode Usable EXECUTION MODE Sets and displays execution mode Unusable FILL Writes data to memory Unusable Rev 1 0 09 00 page 183
7. Enables or disables the BREQ signal bus request signal inputs during user program execution e To disable the BREQ signal inputs during emulator operation and user program execution EXECUTION MODE BREQ D RET e To enable the BREQ signal inputs during emulator operation and user program execution EXECUTION MODE BREQ E RET Rev 1 0 09 00 page 242 of 423 HITACHI EXECUTION_MODE Specifies the minimum time to be measured for GO command execution e To set the minimum time to 1 6 us EXECUTION MODE RET e To set the minimum time to 406 ns EXECUTION_MODE TIME 2 RET e To set the minimum time to 20 ns EXECUTION MODE TIME 3 RET Specifies whether to continue program execution and whether to output a pulse from the trigger output pin when hardware break conditions set by the BREAK CONDITION UBCI UBC2 commands are satisfied e To terminate program execution and not output a pulse when hardware break conditions are satisfied EXECUTION MODE TRGU D RET e To terminate program execution and output a pulse when hardware break conditions are satisfied EXECUTION MODE TRGU M RET e To continue program execution and output a pulse when hardware break conditions are satisfied EXECUTION MODE TRGU E RET Specifies whether to continue program execution and whether to output a pulse from the trigger output pin when hardware break conditions set by the BREAK CO
8. BREAK_SEQUENCE 2 To display the specified pass points and reset point BS PASS PASS PASS PASS PASS PASS PASS RET POINT T NO2 T NO3 POIN POIN POINT POINT POINT POINT NO4 NOS RESET POINT 00004 00004 00004 00004 00004 00004 00004 000 100 200 300 400 500 600 00002000 3 To cancel the reset point BS R RET 0000 0000 0000 0000 0000 0000 0000 0000 4 To cancel the pass points and reset point BS BS RET R RET Rev 1 0 09 00 page 222 of 423 HITACHI 7 2 10 CHECK CH Tests SH7612 pins Command Format e Test CHECK RET Description e Test Tests the status of the SH7612 pins shown in table 7 13 Table 7 13 SH7612 Pin Test Pin Name Error Status RES RESET signal is fixed low NMI NMI signal is fixed low WAIT WAIT signal is fixed low BREQ BREQ signal is fixed low IRLO IRLO signal is fixed low IRL1 IRL1 signal is fixed low IRL2 IRL2 signal is fixed low IRL3 IRL3 signal is fixed low CKPREQ CKPREQ signal is fixed low If an error occurs FAILED AT lt pin name gt is displayed Example When the IRLO signal is low CH RET FAILED AT IRLO Rev 1 0 09 00 page 223 of 423 HITACHI CLOCK 7 2 11 CLOCK CL Sets or displays clock Command Format Setting CLOCKA lt clock gt RET Display CLOC
9. k kkkkkkkkk COB A0G 00 A0 00000000 MO 00000000 X0 00000000 Y A1G 00 A1 00000000 1 00000000 X1 00000000 Y RUN TIME D 0000H 00M 01S 000004US 750NS BREAK KEY 4 Enter TRACE B RET to display the TRACE B RET trace information acquired under the specified condition BP AB DB MA RW ST IRL NMI RES VCC PRB D 000039 01001010 70FF8800 EXT R PRG 1111 1 1 1 1 1111 D 000038 01001014 88F80009 EXT R PRG 1111 1 1 1 1 1111 5 Enter TRACE CONDITION AI TRACE CONDITION A1 RET RET to cancel the trace acquisition condition Rev 1 0 09 00 page 99 of 423 HITACHI 4 3 3 Parallel Mode During program execution in parallel mode the memory contents can be displayed or modified by the following procedures Operations 1 After executing the GO command enter RET to move to parallel mode 2 Enter DUMP 1002000 100200F RET to display the memory contents from addresses H 1002000 to H 100200F in parallel mode 3 Enter MEMORY 1001019 FD RET to modify the memory contents of address H 1001019 to H FD in parallel mode 4 To exit from parallel mode enter END RET 5 To terminate program execution enter the BREAK key Rev 1 0 09 00 page 100 of 423 Display Message GO 1001000 RET PC XXXXXXXX RET Moves to parallel mode DUMP 1002000 100200F RET Dump display MEMORY 1001019 FD RET END RET PC XXXXXXXX PC XXXXXXXX BREAK PC XX
10. lt comment gt Lk A Any instruction mnemonic described in the SH7612 Series Programming Manual and any assembler directive listed in table 1 9 can be used Any mnemonic described in the SH Series Programming Manual can be used table 1 10 A character string after a semicolon is considered to be comment Items within square brackets can be omitted However some lt operand gt values for specific instructions are required Indicates a space Notes 1 Continuation lines cannot be input 2 The default for radix of constants is set by the RADIX command Table 1 9 Assembler Directives Directive Operand Description A DATA s A lt value gt lt value gt e Reserves an area for initialized fixed length data The size of the area is equal to the unit length given by s B byte W word or L longword Default size is L e f any value exceeds the capacity of the size code 5 an error occurs e Aline can contain up to 40 bytes A RES s A value e Reserves data areas The number of areas is given by value The size of each area is given by s B byte W word or L longword Default size is L e Up to 4 294 967 295 byte area can be reserved at one time Rev 1 0 09 00 page 151 of 423 HITACHI Table 1 10 Operand Descriptions Format Addressing Mode Remarks Rn Register direct Rn General register name SP can be specified inst
11. Bidirectional parallel interface SAVE Saves program in host computer Unusable Bidirectional parallel interface VERIFY Verifies memory contents against host computer file Unusable Bidirectional parallel interface Rev 1 0 09 00 page 343 of 423 HITACHI 8 2 Host Computer Related Commands This section provides details of host computer related commands in the format shown in figure 8 1 Command Name No Command Name Abbr Function Command Format Function 1 Command input format Function 2 Command input format parameter 1 Parameter description 1 parameter 2 Parameter description 2 Description Function 1 Description of function 1 Function 2 Description of function 2 Notes Examples Command Name Full command name Abbr Abbreviated command name Function Command function Command Format Command input format for each function Description Function and usage in detail Notes Warnings and restrictions for using the command If additional information is not required this item is omitted Examples Command usage examples Figure 8 1 Description Format of Host Computer Related Command Rev 1 0 09 00 page 344 of 423 HITACHI Symbols used in the command format have the following meanings a b lt gt Ee RET Parameters enclosed by can be omitted One of the parameters enclosed by and separated by th
12. Rev 1 0 09 00 page 316 of 423 MA RW STS IRL NMI RI JSR RO OP EXT R PRG 1111 OV RO R1 OP EX PRG 1111 OV RO R4 EX PRG 1111 EX DAT 1111 EX PRG 1111 HITACHI ES BRO VCC PRB 1 1 1 1111 1 1 1 1111 1 1 1 1 1111 1 1 l T1171 To specify a display range by bus cycle pointers and display bus cycle information instruction mnemonic information in bus cycle units T D 20 D 16 BP B RET BP AB DB RW STS IRL NMI RES VCC PRB D 000020 00002014 AFF40009 EXT PRG 1111 1 1 1 1 1111 00002014 00002000 00002016 NOP D 000019 00002000 A0060009 EXT R PRG 1111 1 18 ty WII 00002000 00002010 00002022 NOP D 000018 00002010 400B0009 EXT PRG 1111 1 1 1 TAL 00002010 JSR RO 00002012 D 000017 00002020 21020009 EXT PRG 1111 1 1 1 1 1111 00002020 OV L RO R1 a 00002022 OP D 000016 00002024 6403000B EXT PRG 1111 1 1 1 1 1111 i 00002024 OV RO R4 2 00002026 RTS To specify a display range by bus cycle pointers and display bus cycle information in bus cycle units T D 20 D 16 BP N RET BP AB DB RW STS IRL NMI RES VCC PRB D 000020 00002014 AFF40009 EXT PRG 1111 1 1 1 1 1111 D 000019 00002000 A0060009 EXT PRG 1111 1 2 1 1111 D 000018 00002010 400B0009 EXT PRG 1111 1 T 1 1 1111 D 000017 00002020 21020009 EXT
13. software breakpoint to be cancelled Address of the software breakpoint to be cancelled Note When an odd address is specified it is rounded down to an even address Description e Setting Sets a software breakpoint at the specified address by replacing its contents with a break instruction H 0000 GO command emulation terminates when the break instruction is executed The instruction at the software breakpoint itself is not executed Up to four breakpoints can be set each time this command is issued and a maximum of 255 breakpoints can be set in total A software breakpoint can only be set in a RAM area including standard emulation memory because the contents of the specified address is replaced with a break instruction to cause a break Do not set software breakpoints at any of the addresses below Note Address that holds an illegal instruction H 0000 Areas other than CSO to CS4 excluding internal RAM area Address where the BREAK CONDITION UBC2 command settings are satisfied refer to the following descriptions Address containing a slot delayed branch instruction refer to the following descriptions Address of the lower 16 bits of a 32 bit DSP instruction If a software breakpoint is set at an address in either a cache area or cache through area a break will occur in both areas Rev 1 0 09 00 page 199 of 423 HITACHI BREAK By specifying the number of times a breakpoint must be
14. BREAK SEQUENCE RET PASS POINT NO 1 xxxxxxxx yyyy PASS POINT NO 2 XXXXXXXX yyyy PASS POINT NO 3 xxxxxxxx yyyy PASS POINT NO 4 xxxxxxxx yyyy PASS POINT NO 5 yyyy PASS POINT NO 6 XXXXXXXX yyyy PASS POINT NO 7 XXXXXXXX yyyy RESET POINT XXXXXXXX yyyy a b a Address If nothing is specified a blank is displayed b Number of times passed The number of times the pass point was passed is displayed in hexadecimal If it exceeds H FFFF counting restarts from H O The number of times passed is cleared by the next GO command Rev 1 0 09 00 page 220 of 423 HITACHI BREAK_SEQUENCE e Cancellation Cancels specified pass points or a reset point Cancellation of pass points BREAK_SEQUENCE RET Cancellation of a reset point BREAK_SEQUENCE R RET Note In parallel mode if a command for example memory access is executed and the emulation stops at a pass point or the reset point at the same time command execution may not take place In this case 78 EMULATOR BUSY is displayed Re enter the command If the termination interval is short the emulator may not enter parallel mode or commands cannot be executed in parallel mode Examples 1 To set pass points at addresses H 4000 H 4100 H 4200 and H 4300 in that order and a reset point at address H 2000 BS 4000 4100 4200 4300 RET BS 2000 R RET Rev 1 0 09 00 page 221 of 423 HITACHI
15. START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T L RET E8000 IP ADDRESS 0 0 0 0 128 1 1 1 RET Rev 1 0 09 00 page 73 of 423 HITACHI T 3 6 5 T T Initiates the diagnostic program Command Format e Initiation T RET Description e Initiation Initiates the diagnostic program Example To initiate the emulator diagnostic program START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T RET The diagnostic program is then initiated Rev 1 0 09 00 page 74 of 423 HITACHI 3 7 3 7 1 System Program Installation E8000 System Disk The emulator contains one floppy disk SH7612 E8000 SYSTEM 1 SYSTEM HS7612EDD81SF Vm n 2 PC I F HS8000EIW01SF Vm n 3 DIAGNOSTIC TEST Vm n XX XX XX HITACHI E8000 Figure 3 25 E8000 System Disk The E8000 system disk with a 1 44 Mbyte format is for PC This floppy disk contains the following six files E8000 SYS SHCNF761 SYS SHDCT761 SYS SETUP CC IPW EXE DIAG SYS E8000 SYS SHCNF761 SYS and SHDCT761 SYS are system programs that must be installed to the emulator flash memory with emulator monitor command F flash memory management tool initiation SETUP CC is a file for writing the system prog
16. esee rennen en eene nenne nene 148 Assembler Directives ope e po errespe e diee tive n 151 Operand Descriptions ien Repente ler teet 152 Differences between Initial Values of the SH7612 and Emulator Registers 155 SH7612 Operating Mode Selection 158 Setting and State of Operating Mode seen 159 80 Bus Width Selection esses nne nennen enne 159 Bus Timing Bus Clock 30 2 ener nennen 165 Emulation Commands sissies ee e Eea ee Rhe re ERREUR DRE 183 Subcommands for Line Assembly eene 193 Causes of BACKGROUND INTERRUPT Command Termination 196 Maximum Conditions for Each Break Type sss 202 Specifiable Conditions BREAK CONDITION 1 8 203 Specifiable Conditions BREAK CONDITION 1 8 205 Specifiable Conditions BREAK CONDITION CI C8 eee 207 Rev 1 0 09 00 page xii of xiv HITACHI Table 7 8 Table 7 9 Table 7 10 Table 7 11 Table 7 12 Table 7 13 Table 7 14 Table 7 15 Table 7 16 Table 7 17 Table 7 18 Table 7 19 Table 7 20 Table 7 21 Table 7 22 Table 7 23 Table 7 24 Table 7 25 Table 7 26 Table 7 27 Table 7 28 Table 7 29 Table 7 30 Table 7 31 Table 7 32 Table 7 33 Table 7 34 Table 7 35 Table 7 36 Table 7 37 Table 7 38 Table 7 39 Table 8 1 Table 9 1 Table
17. GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000001 00000001 00000002 00000003 00000004 00000005 00000006 00000007 R8 15 00000008 00000009 0000000A 0000000B 00000000 0000000C 0000000D 000FFEO00 DSR200000000 k kkkkkkkk COB A0G 00 A0 00000000 0 00000000 0 00000000 0 00000000 1 00 A1 00000000 M1 00000000 1 00000000 1 00000000 00001000 MOV RO R1 ONE STEP END RET Rev 1 0 09 00 page 309 of 423 HITACHI STEP_OVER PC 00001004 SR 000000F0 000000000000 IIII00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 R8 15 00000008 00000009 0000000A 0000000B 00000000 0000000C 0000000D 000FFEO00 DSR200000000 kkkkkkkkk COB A0G 00 A0 00000000 0 00000000 0 00000000 0 00000000 A1G 00 A1 00000000 1 00000000 1 00000000 1 00000000 00001002 MOV 00 RO ONE STEP END RET PC 00001008 SR 000000F0 000000000000 IIII00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 R8 15 00000008 00000009 0000000A 0000000B 00000000 0000000C 0000000D 000FFEO00 DSR200000000 k kkkkkkkk k CO
18. HITACHI CLOCK Note If U user system clock is specified and the following clock signal problem occurs the E8000 system program may terminate In this case 6 USER SYSTEM NOT READY is displayed The E8000 system program must be quit with the QUIT command and restarted e User system clock signal is not being received even when U is specified and the user system clock is being used Vcc is supplied with no problem Examples 1 To use the user system clock signal CL U RET RESET BY E8000 CLOCK USER 2 To use the emulator internal clock signal CL E RET RESET BY E8000 CLOCK EML 3 To display the current clock signal CL RET CLOCK EML Rev 1 0 09 00 page 225 of 423 HITACHI CONFIGURATION 7 2 12 CONFIGURATION CNF Saves and restores configuration information and displays a list Command Format e Saving CONFIGURATIONA lt configuration number gt A lt comment gt S RET e Restoration CONFIGURATIONA lt configuration number gt RET e List display CONFIGURATION RET configuration number 1 or 2 lt comment gt Comment on the defined configuration information A comment can contain of one to 32 characters not counting the semicolon Description e Saving Saves configuration information various emulation information that are listed in table 7 14 in the emulator flash memory CONFIGURATION
19. Multiple characters can be included inside the quotation marks within the specified data size as shown below Example AB H4142 2 byte data Rev 1 0 09 00 page 180 of 423 HITACHI e Expression An expression can be described using numeric constants character constants and operators As an operator addition or subtraction can be specified Examples D 10 H 20 20 4 1 File Name A file name can be specified as a command parameter The general file name format is as follows lt drive name gt lt file name gt lt extension gt 6 2 Special Key Input The emulator supports special key functions to facilitate keyboard operations In the following description CTRL X means pressing the CTRL and X keys simultaneously 6 2 1 Command Execution and Termination e Command execution RET Enters all characters on that line regardless of the cursor position and executes the command e Command termination CTRL C BREAK Terminates command execution characters typed so far are lost and the emulator enters command input wait state 6 2 2 Display Control e Display stop CTRL 5 Temporarily stops display Resumes display by entering CTRL and Q keys e Display restart CTRL Resumes display Rev 1 0 09 00 page 181 of 423 HITACHI 6 2 3 Command Re entry e Display last entered line CTRL L Redisplays the last line entered Pressing these keys will repeatedly redisplay up to 16 lines an
20. No verification Rev 1 0 09 00 page 268 of 423 HITACHI MEMORY Description e Display modification data is omitted the emulator displays memory contents at the specified address and enters input wait state of the modification data The user can then enter data and modify memory contents this process can then be repeated for the next address If option N is not specified the data to be modified is read and verified Memory contents are displayed and modified data is input in the following format Notes 1 MEMORY lt address gt RET XXXXXXXX lt data gt lt option gt RET XXXXXXXx Address of data to be modified yyyyyyyy Memory contents displayed in modification units data New data Data length is considered to be the same as that of the data displayed on the screen If only the RET key is pressed data is not modified and the next address is displayed option The unit of display or modification can be changed or the address can be incremented or decremented When data is specified option is processed after the data is modified When data is not specified a semicolon can be omitted to specify options L W period Table 7 19 lists option functions Data in the internal I O area is never verified When the contents of the reserved area are modified without specifying N no verification a verify error may occur
21. PC 01001012 SR 000000F0 000000000000 GBR 00000000 VBR 00000000 MACH 00000000 MACL 0000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000001 000000rF 00000011 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 DSR200000000 X X xo koe keel ie COB A0G 00 A0 00000000 0 00000000 0 00000000 0 0000 A1G 00 1 00000000 M1 00000000 1 00000000 1 0000 RUN TIME D 0000H 00M 00S 000038US 400NS lt ADDR gt 01001012 lt CNT gt 0005 lt PASS gt 0005 HITACHI 4 3 2 Conditional Trace The acquisition of trace information during program execution can be limited by the following procedures Operations Display Message 1 Enter BREAK RET to cancel the BREAK RET breakpoint set in the example of section 4 3 1 Break with Pass Count Condition 2 Enter TRACE CONDITION 1 TRACE CONDITION A1 A 1001010 1001014 R RET A 1001010 1001014 R RET to get trace information only while the program counter is between addresses H 1001010 and H 1001014 3 Enter GO 1001000 RET to start 1001000 RET executing the program then the PC 01001010 BREAK key to terminate the program execution BREAK PC 01001012 SR 000000F0 000000000000 GBR 00000000 VBR 00000000 MACH 00000000 MACL RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 00000000 00000000 00000000 00 R8 15 00000000 00000000 00000000 00000000 00 DSR 200000000
22. PRG 1111 1 1 T l1 LELI D 000016 00002024 6403000B EXT R PRG 1111 1 1 1 1 SITXIT Rev 1 0 09 00 page 317 of 423 HITACHI TRACE_CONDITION_A B C 7 2 41 TRACE CONDITION A B C TCA TCB TCC Specifies displays and cancels a trace condition Command Format e Setting TRACE_CONDITION_ A B C 1 2 3 4 5 6 7 8 AS lt start address gt lt end address gt ST RET Subroutine trace TRACE_CONDITION_ A B C 1 2 3 4 5 6 7 8 A lt condition gt A lt condition gt A lt condition gt R RET Range trace TRACE_CONDITION_ A B C 1 2 3 4 5 6 7 8 AS lt start address gt lt end address gt A lt condition gt A lt condition gt A lt condition gt SR RET Subroutine range trace TRACE_CONDITION_ A B C 1 2 3 4 5 6 7 8 A lt condition gt A lt condition gt A lt condition gt S RET Trace stop e Display TRACE_CONDITION_ A B C 1 2 3 4 5 6 7 8 RET TRACE_CONDITION_ A B C RET e Cancellation TRACE CONDITION A B C 1 2 3 4 5 6 7 8 RET TRACE CONDITION A B C RET A B C Trace condition type 1 2 3 4 5 6 7 8 Trace condition number When omitted all conditions will be displayed or canceled start address Start address of subroutine end address End address of subroutine condition Trace conditions to be specified ST Subroutine trace mode specification R Range trace mode specification SR Subroutine range trace mode specification S Trace stop specification
23. e Cycle reset mode R n 1 to 12 A RESET signal is input to the SH7612 at the intervals given in table 7 15 and program execution continues In this mode all break conditions and trace conditions are invalidated e Temporary invalidation of break conditions If the N option is specified software breakpoints set with the BREAK or BREAK_SEQUENCE command and hardware break conditions set with the BREAK CONDITION A B C or BREAK CONDITION UBC command are invalidated temporarily and user program emulation continues The breakpoints and break conditions are invalidated only within one GO command emulation If the N option is not specified in the next GO command emulation breakpoints and break conditions are validated again e Time interval measurement mode 1 The execution time from the point when the BREAK CONDITION UBC2 condition is satisfied until the BREAK CONDITION UBCI condition is satisfied is measured After BREAK CONDITION 2 condition satisfaction user program execution stops when BREAK CONDITION UBC conditions are satisfied In this case BREAK CONDITION SB will be dispalyed as a cause of termination e Time interval measurement mode 2 The total execution time from the point when the BREAK CONDITION UBC2 condition is satisfied until the BREAK CONDITION UBCI condition is satisfied is measured Even if these break conditions are satisfied the program does not stop and the execution time between BREAK CONDITION UBC
24. EV chip board AMA 7 ML HS7612EBH81H or HS7612EBK81H HS8000ESTO2H o External probe User system trigger output pins a station Figure 2 1 Emulator Hardware Components Rev 1 0 09 00 page 11 of 423 HITACHI 2 1 1 E8000 Station Components Front Panel HITACHI E8000 Figure 2 2 E8000 Station Front Panel 1 POWER lamp Lit up when the E8000 station power is on 2 RUN lamp Lit up when the user program is running Rev 1 0 09 00 page 12 of 423 HITACHI Rear Panel Figure 2 3 E8000 Station Rear Panel 1 Power switch Turning this switch to I input supplies power to the emulator E8000 station and EV chip board 2 Fuse box Contains a 3 A 250 V AC fuse or T3 15A 3 AC power connector For a AC100 120 V 200 240 V power supply 4 Cheapernet connector For a Cheapernet cable Marked BNC 5 Ethernet connector For an Ethernet cable Marked LAN Rev 1 0 09 00 page 13 of 423 HITACHI 6 Parallel interface connector For a parallel interface cable with the host PCIF board Conforms to IEEE P1284 ECP mode Marked PARALLEL 7 PC interface cable connector For the PC interface cable which connects the PC to the E8000 station Marked PCIF 8 Host interface switches For selecting the host interface Specifies the connection of the LAN interface RS 232C interface or PC I F board When the RS 232C interface is used the data bit length stop bit length or parity set
25. Hexadecimal is used at emulator initiation Numbers may be entered in any radix at any time provided that each value is prefixed with the appropriate character Table 7 22 Radix and Input Examples Radix Input Example Binary B 1010 Octal Q 2370 Decimal D 6904 Hexadecimal H AF10 Fixed point X 0 6634049566 Rev 1 0 09 00 page 290 of 423 HITACHI e Display RADIX Displays the currently set radix as follows Radix charact Examples RADIX Radix character er displayed as one of the following B BINARY Q 0CTAL D DECIMAL H HEXADECIMAL X FIXED POINT 1 To set the radix to decimal RX RET B 10 RET 10 is input in decimal 2 To display the current radix RX RADIX D DI ECIMAL Rev 1 0 09 00 page 291 of 423 HITACHI REGISTER 7 2 33 REGISTER R Displays register contents Command Format e Display REGISTER RET Description e Display Displays all register contents The DSR register setting bits bits 3 to 1 are displayed as shown in table 7 23 Table 7 23 DSR Register Setting Bits DSR Register Setting Bits Display Bit2 Biti COB 0 0 0 Carry or borrow NEG 0 0 1 Negative ZER 0 1 0 Zero OVF 0 1 1 Overflow SGT 1 0 0 Signed greater than SGE 1 0 1 Signed greater than or equal Example To display all register contents R RET PC 00005C60 SR 000000F0 000000000000 IIII00 GB
26. RET addrl RESET lt address gt RESET execute after MPU reset address starting address if deleted executes from current PC lt breakaddr gt address when stopping the program mode R lt n gt cycle reset mode 1 to 12 N temporarily invalidates break conditions Il time interval measurement mode 1 I2 time interval measurement mode 2 SB sequential break mode UBC TB time out break mode default normal mode Rev 1 0 09 00 page 261 of 423 HITACHI HISTORY 7 2 23 HISTORY HT Displays input command history Command Format e Display HISTORY RET Displays all input commands HISTORY lt history number gt RET Displays the input command of the specified history number lt history number gt History number 1 to 16 Description e Display Displays the 16 commands most recently input including the HISTORY command in the input order If history number is entered the command corresponding to history number is displayed as shown below and the emulator enters command input wait state When the RET key is pressed the displayed command is executed Note Subcommands cannot be displayed by the HISTORY command Example HISTORY RET 1 MAP 2 MAP 0 FFFFFF U 3 F 0 1000 FF 4 B 300 5 BCA1 A 104 6 HISTORY HISTORY 5 RET 1 A 104 Enters command input wait state Rev 1 0 09 0
27. Rev 1 0 09 00 page 326 of 423 HITACHI TRACE_CONDITION_A B C A bit mask in 1 bit or 4 bit units can be specified for the address condition of the TRACE CONDITION command When a bit is masked the condition is satisfied irrespective of its bit value To implement the mask specify each digit to be masked at input as an asterisk Table 7 34 shows address mask specification examples Example The following condition is satisfied when the lower four bits of the address condition are not specified TRACE CONDITION A1 A H 400000 5 RET Table 7 34 Address Mask Specifications TRACE CONDITION Radix Mask Unit Example Mask Position Binary 1 bit B 01101 Bits 2 to 0 are masked Hexadecimal 4 bits 50 Bits 11 to 0 are masked Note When address 2 is not specified for an address condition address 1 gt can be consecutively masked from the lowest bit It is not possible to mask any desired bit position as shown in the following examples Examples Allowed TRACE CONDITION 1 A H 10 R Not allowed TRACE CONDITION A1 A H 1 00 R TRACE CONDITION A1 A H 100 10 R A bit mask in 1 bit or 4 bit units can be specified for the data IRL or PRB condition of the TRACE CONDITION A B C command When a bit is masked the condition is satisfied irrespective of its bit value To implement the mask specify each digit to be masked at input as an asterisk Table 7 35 shows the
28. sys OK CONF OK LAN NO FIRM OK TRON NO DIAG NO INI OK MON OK FM Q RET START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ HITACHI Manual System Program Load by RS 232C Interface To use the emulator files E8000 SYS SHCNF761 SYS and SHDCT761 SYS must be installed in the emulator flash memory If the emulator is connected to the host computer via the RS 232C interface the E8000 system program can be loaded with the following procedures Note that the E8000 system disk is assumed to be inserted in drive A of the host computer It takes approximately 20 minutes Operations Display Message 1 Initiate IPW in the E8000 system floppy disk 2 Power on the emulator For details on the power on procedures refer to section 3 5 2 Power On Procedures for RS 232C Interface 3 Emulator monitor command prompt START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ 4 Enter F RET to initiate the flash S F L T F RET memory management tool The FM emulator displays prompt FM and waits for a flash memory management tool command 5 Enter SL RET to load the system FM SL RET program 6 Enter 1 RET to select PC as the SELECT LOAD No 1 PC or 2 WS 1 RET host computer type and 1 RET SELECT INTERFACE 1 RS 232C or 2 PARALLEL 1 RET select RS 232C serial interface as the interface meth
29. 00 MD4 0 1F REMAINING EMULATION MEMORY S 4MB Rev 1 0 09 00 page 64 of 423 HITACHI 3 6 3 F F Initiates the flash memory management tool Command Format e Flash memory F RET management tool Description e Flash memory management tool Initiates the flash memory management tool The flash memory management tool can use the commands listed in table 3 9 Table 3 9 Flash Memory Management Tool Commands Command Function DIR Displays system file loading status LH Defines the host name and IP address of the host computer to be connected Q Terminates the flash memory management tool RTR Defines routing information for remote network SL Loads the E8000 system program SN Defines the subnet mask value Note RTR and SN commands be used only when the LAN board HS7000ELNO2H is used Example To initiate the flash memory management tool START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T F RET FM gt Rev 1 0 09 00 page 65 of 423 HITACHI DIR DIR DIR Displays system file loading status Command Format e Display DIR RET Description e Display Displays system file loading status Displays OK for correctly loaded system file NG for abn
30. 1 To specify the operating mode as mode 2 and store configuration information MD C RET E8000 MODE MD4 0 1F 2 RET CONFIGURATION STORE OK Y N Y RET START E8000 S START E8000 F FLASH MEMORY TEST L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ 2 To display the SH7612 operating mode in the emulator MD RET MODE 00 MD4 0 1F Rev 1 0 09 00 page 274 of 423 HITACHI MOVE 7 2 28 MOVE MV Transfers memory contents Command Format e Move data MOVEA lt start address gt A lt end address gt A number of bytes A destination address RET start address gt Start address of source area lt end address gt End address of source area lt number of bytes gt The number of bytes to be transferred lt destination address gt Start address of destination Description e Move data Transfers the contents of the memory area specified with start address and end address or number of bytes to an address range starting with destination address Transfer is usually performed from the start address However if destination address 18 set within the range from start address to end address or number of bytes transfer is performed from the end address or start address number of bytes Verifies the transfer If a verification error occurs FAILED AT xxxxxxx
31. Command Format e FTP interface termination BYE RET Description e FTP interface termination Terminates the FTP interface and changes the prompt to a colon To re establish the FTP interface enter the FTP command For details refer to section 9 3 6 FTP Example To terminate the FTP interface FTP BYE RET bye command success Rev 1 0 09 00 page 367 of 423 HITACHI CD 9 3 4 CD CD Changes the directory name of the FTP server Command Format e Directory change CD A lt directory name gt RET lt directory name gt Name of new directory Description e Directory change Changes the current directory of the FTP server connected host computer to the specified directory The modified directory must be formatted depending on which host computer is connected via the FTP interface Example To change the current directory of the FTP server to subdir FTP gt CD subdir RET cd command success FTP gt Rev 1 0 09 00 page 368 of 423 HITACHI CLOSE 9 3 5 CLOSE CLOSE Disconnects the host computer from the FTP interface Command Format e FTP interface disconnection CLOSE RET Description e FTP interface disconnection Disconnects the FTP interface from the host computer to which it is currently connected Before changing host computers disconnect the FTP interface with this command and re connect with the OPEN command For details refer to section 9 3 13 OPEN Example
32. Displays the remote network routing information Command Format e Display ROUTER RET Description e Display Displays the routing information defined with the emulator monitor flash memory management tool command RTR Note Routing information can be defined with the emulator monitor flash memory management tool command RTR Example To display the defined routing information RTR RET No IP ADDRESS NET ID No IP ADDRESS NET ID 01 128 1 1 80 168 1 1 0 02 128 1 1 50 160 1 1 0 Rev 1 0 09 00 page 384 of 423 HITACHI STA 9 3 16 STA STA Displays the file type to be transferred Command Format e Display STA RET Description e Display Displays in the following format the file type binary or ASCII to be transferred by the LAN_LOAD LAN_SAVE or LAN_VERIFY command FTP gt STA RET type mode is BINARY Binary FTP gt STA RET type mode is ASCII ASCII Example To display the file type to be transferred FIP gt STA RET type mode is BINARY FTP gt Rev 1 0 09 00 page 385 of 423 HITACHI SUBNET 9 3 17 SUBNET SN Displays the subnet mask value Command Format e Display SUBNET RET Description e Display Displays the subnet mask value defined with the emulator monitor flash memory management tool command SN SUBNET RET SUBNET MASK xxx xxx xxx xxx H yy H yy H yy H yy a b a Subnet mask value in decimal b Subnet mask value in hexa
33. H 00000000 A1G The value before reset AO Al MO M1 X0 X1 YO Y1 The value before reset Since the reset values of RO to R14 in the SH7612 are not fixed the initial values must be set by a program Rev 1 0 09 00 page 187 of 423 HITACHI lt register gt Examples 1 To set H 5C60 in PC H FFEOO in SP in and H 11 in R2 and then display all registers PC 5C60 RET SP FFEOO RET R1 FF RET R2 11 RET R RET PC 00005C60 SR 000000F0 000000000000 IIII00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 O00FFEO00 5 00000000 A0G 00 A0 00000000 M0 00000000 X0 00000000 0 00000000 1 00 A1 00000000 M1 00000000 X1 00000000 1 00000000 2 To modify the contents of control registers in interactive mode PC RET PC 00001000 2000 RET SR 000003F3 000000000000 MOIIIIOOST 303 RET PR 00000000 RET Rev 1 0 09 00 page 188 of 423 HITACHI ABORT 7 2 2 ABORT AB Terminates emulation in parallel mode Command Format e Termination ABORT RET Description e Termination Terminates GO command execution in parallel mode prompt and c
34. HITACHI STEP_INFORMATION Description Specification Displays register information executed instruction information memory contents and cause of termination during STEP and STEP_OVER command execution This command also selects the register information and memory contents which are to be displayed PC 00001000 SR 000000F0 000000000000 TIII00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 b RO 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000FFE00 c 5 00000000 ____ A0G 00 A0 00000000 M0 00000000 X0 00000000 Y0 00000000 A1G 00 1 00000000 M1 00000000 1 00000000 Y1 00000000 d 00001002 MOV 00 RO MEMORY 0000 80 00 04 00 FF FO 00 02 00 10 00 02 00 OF 00 00 00 f STACK OOOFFFEO 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 g STEP NORMAL END a System and control register information PC SR PR GBR VBR MACH MACL RS RE and MOD b General register information RO to R15 c DSP register information DSR A0G AO MO MI YO and Y1 d Address and assembler instruction mnemonic of the executed instruction Memory contents display f Stack contents display g Cause of termination
35. HS7612EDD81H User s Manual Renesas Electronics Rev 1 0 2000 09 www renesas com Cautions 1 Hitachi neither warrants nor grants licenses of any rights of Hitachi s or any third party s patent copyright trademark or other intellectual property rights for information contained in this document Hitachi bears no responsibility for problems that may arise with third party s rights including intellectual property rights in connection with use of the information contained in this document 2 Products and product specifications may be subject to change without notice Confirm that you have received the latest product standards or specifications before final design purchase or use 3 Hitachi makes every attempt to ensure that its products are of high quality and reliability However contact Hitachi s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other characteristics Hitachi bears no responsibility
36. In this INPUT USER NAME username RET example username is entered 7 Enter the password In this INPUT PASS WORD password RET example password is entered 8 Enter the directory containing the INPUT SYSTEM DIRECTORY RET system file In this example RET is entered to select the current directory of the host computer 9 Enter Y RET to allow system LOAD E8000 SYSTEM FILE OK Y N Y RET program E8000 SYS to beloaded in INPUT FILE NAME 8000 5 5 RET the emulator flash memory Then COMPLETED enter system program file name E8000 SYS Rev 1 0 09 00 page 81 of 423 HITACHI Operations 10 Enter Y RET to allow configuration file SHCNF761 SYS to be loaded in the emulator flash memory Then enter configuration file name SHCNF761 SYS 11 Enter Y RET to allow firmware file SHDCT761 SYS to be loaded in the emulator flash memory Then enter firmware file name SHDCT761 SYS 12 Enter N RET not to load the ITRON debugger 13 Enter N RET not to load the diagnostic program 14 Enter DIR RET to check whether the necessary files have been loaded 15 Enter Q RET to terminate the flash memory management tool 16 Installation is completed Rev 1 0 09 00 page 82 of 423 Display Message LOAD CONFIGURATION FILE OK Y N Y RET INPUT FILE NAME SHCNF761 SYS RET COMPLETED LOAD FIRMWARE FILE OK Y N Y RET INPUT FILE NAME SHDCT761 SYS RET COMPLETED LOAD ITRON DEBUGGER
37. To disconnect the FTP interface and change the host computer to be connected FTP CLOSE RET bye command success FTP OPEN HOST1 RET Username ABC RET Password RET login command success FTP gt Rev 1 0 09 00 page 369 of 423 HITACHI 9 3 6 Connects host computer and emulator via the FTP interface Command Format e FTP interface connection FTP lt host name gt RET lt host name gt Name of the host computer to be connected with the FTP server The host computer name must be already defined with the flash memory management tool Description e FTP interface connection Connects the host computer and emulator via the FTP interface to enable data transfer with the LAN_LOAD LAN_SAVE or LAN_VERIFY command The host name specified in this command must be defined with the flash memory management tool If host name gt has been defined enter the user name and password in the following format After FTP command execution the prompt changes from a colon to FTP gt Emulation commands can be executed even after FTP connection FTP lt host name gt RET Username a RET Password b RET login command success FTP gt c a Enter user name b Enter password c An FTP prompt is displayed after FTP connection Note A password must be specified before a host computer can be connected via the FTP interface If no password is specified s
38. address PC or data conditions e Specification of the satisfaction sequence up to two points HITACHI Table 1 2 Emulation Functions cont Command Type Break condition setting cont Reference Command Function Section BREAK Sets hardware break conditions 2 7 2 7 CONDITION A B C Execution is forcibly stopped when the specified conditions are satisfied a maximum of 24 points Address bus value or data bus value Access type Read write condition Delay count One channel Pass count specification Eight channels External probe value System control signals NOT condition e Amaximum of seven condition specifications and one reset point condition specification External probe trigger signal e B channel eight channels and UBC two channels of SH7612 BREAK Sets software break conditions 7 2 6 e Sets up to 255 breakpoints e Sets pass count Rev 1 0 09 00 page 107 of 423 HITACHI Table 1 2 Emulation Functions cont Command Type Command Reference Function Section Displays execution instruction mnemonic 7 2 40 Displays the following data for each bus cycle e Address bus value or data bus value e Access area and status e Instruction mnemonic e SH7612 I O control signals e External probe value e Time stamp 20 ns 1 6 us 52 us Trace data TRACE acquisition and display TRACE_ CONDITION Rev 1 0 09 00 page 108 of 423 Sets displays and c
39. and waits for an emulation command Display Message FM gt Q RET START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ S F L T S RET SH7612 E8000 C HS7612EDD81SF Vm n Ltd 1997 Ltd Copyright Hitachi License Material of Hitachi CONFIGURATION FILE LOADING HARDWARE REGISTER READ WRITE CHECK SYSTEM LOADING FIRMWARE LOADING FIRMWARE TEST BY E8000 EML FIRMWARE EMULATOR EMULATOR RESET CLOCK MCU TYPE SH7612 MODE 00 MD4 0 1F REMAINING EMULATION MEMORY S 4MB Rev 1 0 09 00 page 87 of 423 HITACHI 4 2 2 Specifying the SH7612 Operating Mode Specify the emulator operating mode by the following procedures Operations Display Message 1 Enter MODE C RET to specify the emulator operating mode 2 The message shown on the right is displayed 3 To select operating mode H 10 of the SH7612 for example enter 10 RET 4 After the above entry has been completed the emulator asks if the mode settings should be stored in the flash memory To store the mode settings enter Y RET After that the emulator operates in the mode specified above whenever initiated If N RET is entered MODE command execution terminates without storing the mode settings and the emulator enters emulation command input wait state 5 After the above specification has been completed the E8000 system program automatically terminat
40. command BP Bus cycle pointers specified as pointer values Default is the instruction pointer display information Information to be displayed B Displays bus cycle information and instruction mnemonic information N Displays bus cycle information Default Displays instruction mnemonic information Description e Display Displays trace information acquired during user program execution Trace information is displayed in instruction mnemonics or in bus cycle units according to the specified option a If option specification is omitted displays instruction mnemonic information in instruction units TRACE RET b Ifthe B option is specified displays bus cycle information and instruction mnemonic information in bus cycle units TRACE B RET c Ifthe N option is specified displays bus cycle information in bus cycle units TRACE N RET Rev 1 0 09 00 page 311 of 423 HITACHI The display range be specified with pointers in bus cycle units bus cycle pointer instruction units instruction pointer The pointer value is specified as a relative value from the point where a delay start condition is satisfied see the following note Trace information acquired before the delay start condition is satisfied is displayed with a minus To specify a bus cycle pointer the BP option must be selected The default 15 the instruction pointer Note When a delay count con
41. displayed INVALID FIRMWARE SYSTEM 1 EMULATOR FIRMWARE NOT READY 1 PIRMWARE SYSTEM FILE NOT FOUND iii i The incorrect MCU device control board is connected Please check the MCU type and use the appropriate emulator system program or exchange the device control board ii The device control board is not connected correctly Connect the device control board to the emulator correctly iii Correct system program for the device control board is not loaded in the memory Re install the correct emulator system program and restart the emulator f The RES signal is input to the MCU and the specified clock type is displayed Note is not executed if an error has occurred in step c d or e g The MCU type is displayed h The MCU operating mode on the emulator and the status of user system mode selection pins i MCU pins are being checked For details refer to section 7 2 10 CHECK Note h is not executed if an error has occurred in step d or e j The remaining emulation memory size that can be assigned k The emulator system program is initiated and the command input wait state is entered Emulator System Failure If an invalid exception occurs during emulator monitor or emulator system program execution the system shuts down No key input from the key board will be received but the following message is displayed exception PCZxxxxxxxx E8000 SYSTEM DOWN If an
42. interface leading to connection or contact failure Make sure that the emulator station is placed in a secure position so that it does not move during use nor impose stress on the user interface Rev 1 0 09 00 page VI of VI HITACHI Preface Thank you for purchasing the emulator for the Hitachi microcomputer SH7612 CAUTION Read section 3 Preparation before Use in Part I E8000 Guide of this user s manual before using the emulator product Incorrect operation will damage the user system the emulator product and the user program The emulator is an efficient software and hardware development tool for systems based on Hitachi microcomputer SH7612 By exchanging the device control board and the EV chip board this emulator can also be used for other microcomputers This manual describes the emulator functions and operations Please read this manual carefully in order to gain a full understanding of the emulator s performance In particular be sure to read section 1 2 Warnings in Part I E8000 Guide A 3 5 inch system floppy disk in PC 1 44 MB format is packaged together with the EV chip board SH7612 E8000 SYSTEM 1 SYSTEM HS7612EDD81SF 2 PC I F HS8000EIW01 SF Vm n 3 DIAGNOSTIC TEST Vm n XX XX XX HITACHI E8000 Figure E8000 System Disk Rev 1 0 09 00 page i of xiv HITACHI Before using the system disk back up it to a floppy disk according to the instructions in the manuals
43. or TRACE SEARCH command it acquires no trace information In parallel mode the emulator returns to normal mode after one command execution and displays the current PC At this time if trace information acquisition has stopped the emulator restarts acquisition Commands usable in parallel mode are listed in table 7 1 Rev 1 0 09 00 page 117 of 423 HITACHI Notes 1 When memory standard emulation memory or internal I O is accessed with the MEMORY command DUMP command or DISASSEMBLE command in parallel mode there are some restrictions with respect to user program execution e Standard emulation memory When accessing standard emulation memory in parallel mode the user program temporarily halts This pause lasts for about 546 us during user system clock operation Therefore realtime emulation cannot be performed e Internal RAM and I O When accessing internal I O the user program temporarily halts This pause lasts for about 546 us during user system clock operation Therefore realtime emulation cannot be performed e In the above two cases the emulator pauses at the following timing MEMORY command At each memory access DUMP command In 16 byte units DISASSEMBLE command In 4 byte units 2 During execution of the TRACE TRACE SEARCH TRACE_CONDITION_A B C or TRACE_MEMOEY command the emulator stops trace information acquisition 3 The emulator cannot enter parallel mode when executing emulation in the foll
44. specified subroutine execution e User specification time lt Measured value User program execution breaks e User specification time gt Measured value Execution time is measured Rev 1 0 09 00 page 144 of 423 HITACHI 1 8 Trigger Output During user program execution the emulator outputs a low level pulse from the trigger output probe under the following two conditions e Trace condition satisfaction e Hardware break condition satisfaction When using this pulse as an oscilloscope trigger input signal it becomes easy to adjust the user system hardware For example waveforms can be seen when the user program goes to a specified point Trace Condition Satisfaction When the trigger output is specified using the TRGB and TRGU options of the EXECUTION_MODE command a low level pulse is output from the trigger output probe at bus cycles corresponding to the specified condition The trigger signal is output from the end of the corresponding bus cycle until the end of the next bus cycle If the conditions are satisfied in consecutive bus cycles the trigger output remains low Hardware Break Condition Satisfaction During emulation a low level pulse is output from the trigger output pin at the end of the bus cycle during which the hardware break condition is satisfied The trigger signal is output from the end of the corresponding bus cycle until the end of the next bus cycle If the conditions are satisfied in consecutive bus cyc
45. 0 00000000 Y A1G 00 A1 00000000 M1 00000000 1 00000000 Y 01001012 CMP EQ 00 R0 STEP NORMAL END HITACHI 4 2 8 Setting Hardware Break Conditions Various hardware break conditions can be specified by the following procedures Operations Display Message 1 Enter BREAK RET to cancel the BREAK RET software breakpoint 2 To confirm the cancellation BREAK RET execute the BREAK command 45 NOT FOUND enter BREAK RET 45 NOT FOUND shows that no software breakpoint is set 3 To specify that program execution BREAK CONDITION UBC1 A 100FFF8 W RET should terminate when data is written to address H 100FFFS enter BREAK CONDITION UBCI 100 8 W RET 4 Enter GO 1001000 RET to start GO 1001000 RET executing the program from address H 1001000 5 When the break condition is PC 01001012 SR 000000F0 000000000000 satisfied the information shown on GBR 00000000 VBR 00000000 00000000 MACL the right is displayed BREAK RS 00000000 RE 00000000 MOD 00000000 CONDITION shows that GO R0 7 00000000 00000000 00000000 00000000 00 command execution has terminated R8 15 00000000 00000000 00000000 00000000 00 because the break condition was 5 00000000 kk X satisfied A0G 00 A0 00000000 MO 00000000 0 00000000 Y A1G 00 1 00000000 M1 00000000 1 00000000 Y RUN TIME D 0000H 00M 00S 000006US 400NS BREAK CONDITION UBC1 Rev 1 0
46. 004088 01001018 AFFD0009 Dp 004080 01001018 AFFD0009 D 004072 01001018 AFFD0009 Rev 1 0 09 00 page 102 of 423 Display Message TRACE SEARCH A 1001018 RET MA RW ST EXT R PRG EXT R PRG EXT R PRG HITACHI IRL NMI RES 1112 gt 21 T 1111 1 al 1 1111 1 1 1 VCC PRB 1111 TILE 1111 Part II Emulator Function Guide Section Emulator Functions 1 1 Overview This emulator is a hardware and software support tool for the development of systems incorporating the SH7612 In addition to a DSP and a high speed CPU the SH7612 contains a timer serial communication interface an SIO a DMAC and Hitachi UDI Hitachi User Debug Interface on the same chip Table 1 1 SH7612 Functions Function SH7612 Maximum memory size that can be managed 160 Mbytes Maximum external bus width 32 bits Cache memory 4 kbytes Internal RAM 16 kbytes DMAC 2 channels Interrupt controller Five external interrupt sources NMI and IRLO to IRL3 Serial I O SIO 3 channels Serial communication Asynchronous or clock 1 channel interface synchronization Timer 16 bit free running timer 1 channel I O port 14 bits PortA 16 bits Port B The emulator operates in just the same way as the SH7612 on the user system and enables realtime emulation of the user system with functions for debugging hardware and software The emulator consists of an emulator station and an evaluation chip board hereafter c
47. 010305US 500NS D 00010 D 0000H 00M 10S 010305US 250NS 010305US 500NS D 00010 001000US 250NS D 00005 010305US 500NS D 00010 TOTAL RUN TIME D 0001H 00M 408 022917US 5 To cancel all registered subroutines PA RET Rev 1 0 09 00 page 288 of 423 HITACHI QUIT 7 2 31 QUIT Q Terminates E8000 system program Command Format e Termination QUIT RET Description e Termination Terminates the E8000 system program and puts the emulator monitor in command input wait state QUIT RET START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ Example To terminate the E8000 system program Q RET START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ Rev 1 0 09 00 page 289 of 423 HITACHI RADIX 7 2 32 RADIX RX Specifies and displays radix for numeric input Command Format e Specification RADIXA lt radix gt RET e Display RADIX RET lt radix gt Radix to be used for input of numeric values H Hexadecimal default at system program initiation D Decimal Q Octal B Binary X Fixed point Description e Specification Specifies the radix used by the emulator to interpret numbers entered on the command line The RADIX command sets the radix to be used for numbers entered simply as numbers
48. 1 9 2 9 3 Dy EAN TAGS PEACE ccc teret e td ow 359 OVerVIe Wu esce EEEE ie e piti e ive i ndr ere gie dade 359 GAN Data Transfer xe EE te UE REEF ER 361 9 2 1 Setting the Data Transfer Environment nennen 361 9 2 2 JDatasTranster zoe eter vete heic we ee CT ee 362 9 2 3 Notes on FIP Interface ster thee eere teet ener ee 362 TAN Commands za caeteri iier Pe eie eroe antes Or t UPPER HE 363 OBC E LRL 365 LET pe S E E E E E AE 366 Rev 1 0 09 00 page vii of xiv HITACHI 9 3 3 ails creeds Baie Pie eee hig Rite ld ee 367 CDs Balas hak Se ren e ete t D D leta E 368 9 3 5 CLOSE iscsi a RR ee as E Ee h 369 9 3 6 ive dere teet p ed i dece ions 370 9 3 7T etn t DM tet P ete 372 93 8 LAN HOST aues teeth edet n ahs 373 9 3 9 LAN LOAD icd nehm abet pits 374 9 3 10 LAN iude enin 376 9 3 11 EAN VERIEY unos rr Do e 378 SEM PAS 380 9 313 OPEN 5i ient tase iba te end 381 9 3 14 PWD oux ue ERRAT e n rione 383 9 3 15 ROUTER ehe Hebe ee mete iter eds 384 9 3 16 ST Agta Ried Ga en oes Ratan Sell 385 9317s SUBNET pope aote etre equipe eben ntl pleted 386 9 3 18 EOGOUT nen men pne 387 Section I0 Error Messages onan pre tubi pb bti Rec ded tat 389 10 1 Emulator Error Messages nennen nennen nennen eren enne ens
49. 1 19 Figure 1 20 Figure 1 21 Figure 1 22 Figure 1 23 Figure 1 24 Figure 1 25 Figure 1 26 Figure 1 27 Figure 1 28 Figure 4 1 Figure 4 2 Figure 4 3 Figure 5 1 Figure 7 1 Figure 7 2 Figure 8 1 Figure 9 1 Transition to Parallel 116 Parallel inicie eere eve es S OA SE Ea 117 Break with Address Bus Value esee enne enne 120 Break with Data V altes isein idis piein i a enne ene 120 Break with Read Wnte 5 etie ea eter 121 Break with Delay Count Specification nennen 122 Break with Number of Times Break Condition is Satisfied 123 Break with PC Value Specification essere 124 Break with Sequential Specification eessseeeeeeeee nen 125 Normal Break Software Break sese enne 127 Sequential Break ice o neue open UE OPERE 128 Sequential Break Reset Point Specification esse 129 External Probe Signal 131 Free Trace Execution Baie GB 133 Subroutine Trace Specification d eoe P ee deserere Roe eee ASE doing 133 Trace Acquisition Condition seseeeeeeeeeeeeeeee nennen nennen rene 134 Trace Stop Condition Specification seen 135 Subroutine Displ y nre eee iecur RO 137 Normal Mode Time Measurement Range sese 138 Time Interval Meas
50. 3 8 These commands initiate the E8000 system program manage flash memory set an IP address for LAN interface and execute the diagnostic program After turned on the emulator displays the following monitor initiation message and waits for an emulator monitor command input Display Message E8000 MONITOR HS8000ESTO2SR Vm n Copyright C Hitachi Ltd 1995 Licensed Material of Hitachi Ltd TESTING RAM 0123 START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ Table 3 8 Emulator Monitor Commands Command Function S E8000 system program initiation F Flash memory management tool initiation L Emulator IP address setting T Diagnostic program initiation Rev 1 0 09 00 page 63 of 423 HITACHI 3 6 2 S S Initiates the E8000 system program Command Format e Initiation S RET Description Initiation Initiates the E8000 system program Example To initiate the E8000 system program START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T S RET I SH7612 E8000 HS7612EDD81SF Vm n Copyright C Hitachi Ltd 1997 Licensed Material of Hitachi Ltd CONFIGURATION FILE LOADING HARDWARE REGISTER READ WRITE CHECK FIRMWARE SYSTEM LOADING EMULATOR FIRMWARE TEST RESET BY E8000 CLOCK EML MPU TYPE SH7612 MODE
51. 389 10 2 IBM PC Interface Software Error Messages esseeeeeeeeeeeenee nennen 398 Part Appendices Appendix A c ed am dte eap punt ud ud 403 AT Serial Connector une ep uu muU OUO ON 403 A2 Parallel Connector sss es eto ponere p p teu e reo 404 VAN Connectors on eee Shik ee ipa Aes Mes Ceara is Ries eis 406 AA Serial Interface Cable oie oot det e PEE eee PEE Ite P D tpe cent 407 Appendix Emulator External Dimensions and 1 408 Appendix C Connecting the Emulator to the User System 409 1 Connecting to the User System ntes te hee ERE 409 C 1 1 Connection Using the HS7612EBHS1H eee een 410 C 1 2 Connection Using the HS7612EBK581H eee 413 C 2 User Interface Pin Assignment nennen eren nennen ren rennen enne 415 C 3 Precautions for User System Connection esses een eene 421 Appendix D Memory Map 632 55 at cated tee hn dis t ipti e M Mn e tendis 422 Appendix E JASCIDCOdeS castos cie ette tud tui mm ipd iion d bua ete 423 Rev 1 0 09 00 page viii of xiv HITACHI Figures PartI E8000 Guide Figure 1 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 2 8 Figure 2 9 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9
52. 6 7 8 A RET A B C Breaktype 1 2 3 4 5 6 7 8 Break number When omitted all conditions will be displayed or cancelled condition Hardware break condition refer to tables 7 5 to 7 7 for details Description e Setting Specifies hardware break conditions BREAK CONDITION Program execution stops when the specified conditions are satisfied The specifiable conditions for the three types of hardware breaks BREAK CONDITION are summarized in tables 7 5 to 7 7 respectively Table 7 4 Maximum Conditions for Each Break Type Break Type Maximum Remarks Conditions BREAK 8 The maximum specifiable number of conditions is CONDITION A reduced by the number of conditions set with the TRACE CONDITION A command BREAK 8 The maximum specifiable number of conditions is CONDITION B reduced by the number of conditions set with the TRACE CONDITION B command BREAK 8 The maximum specifiable number of conditions is CONDITION C reduced by the number of conditions set with the PERFORMANCE ANALYSIS and TRACE CONDITION C commands Rev 1 0 09 00 page 202 of 423 HITACHI BREAK_CONDITION_A B C Table 7 5 Specifiable Conditions BREAK CONDITION A1 A8 Item and Input Format Address condition A lt address 1 gt lt address 2 gt Description When only lt address 1 gt is specified the condition is satisfied when the address bus value matches the specified value When both
53. 83 INVALID OPERAND SIZE An invalid operand size was specified with the ASSEMBLE command Processing was performed with the correct size 84 INVALID ABSOLUTE An invalid operand address was specified with ADDRESS the ASSEMBLE command Processing was performed with the maximum address allowed 86 INTERNAL AREA An area other than CSO to CS4 was also to be processed Processing specified with the MEMORY command is performed normally but other command processings are performed for only the CSO to CS4 areas 87 INTERNAL I O AREA The internal I O area was accessed 88 RESERVED AREA A reserved area was accessed 92 PERFORMANCE ANALYSIS The minimum unit for execution performance TABLE BUSY measurement cannot be changed during execution time measurement by the PERFORMANCE_ANALYSIS command Delete the PERFORMANCE_ANALYSIS command setting and change the minimum unit Table 10 2 Host I O Error Codes Error Code Description and Solution D1 Parity error The parity bit specified with the DIP switch must match the host computer specifications D2 Overrun error The emulator control method is not recognized by the host computer D3 Framing error The baud rate and stop bit specified with the DIP switch must match the host computer specifications D4 Load module format error The load module format of the transferred file is incorrect Check the file contents DC Timeout error Check the connection between the emulator and host computer Also c
54. A b e Address range displayed by the STEP command SP c e Display size for stack contents Rev 1 0 09 00 page 147 of 423 HITACHI 1 10 Emulation Monitoring Function The SH7612 emulator monitors the emulation status such as memory accesses or user program execution Two kinds of status are monitored e SH7612 operating status e User system power and clock status SH7612 Operating Status When executing the program with the GO command the emulator monitors the operating status When the status changes the operating status display is updated The update interval can be selected from no display 200 ms and 2 s with the MON option of the EXECUTION_MODE command With this function the user can observe the progress of the program The operating status display and its meaning are shown in table 1 8 For details refer to the description on operating status display in section 7 2 21 GO Table 1 8 Operating Status Display Display Meaning RUNNING The user program execution is initiated This message is displayed once when GO command execution is started or when parallel mode is canceled Note that this message will be deleted when PC xxxxxxxx is displayed PC XXXXXXXX The program fetch address being executed is displayed with intervals of about 200 ms When specifying the LEV option with the GO command the satisfied level of the hardware sequential break is displayed VCC DOWN User system Vcc power voltage
55. A break occurs before the instruction at address H 1000 is executed Instruction p cC Figure 1 12 Normal Break Software Break Note When specifying the number of times the break condition is satisfied before generating a normal break the emulator firmware is activated every time the program passes the break condition address As a result the program will not operate in realtime When the program passes the break condition address the emulator executes the instruction at the address for one step then returns to program execution At this time the BREAK CONDITION UBC2 becomes invalid because the BREAK CONDITION UBC2 is used to perform the step execution of the break address Rev 1 0 09 00 page 127 of 423 HITACHI Sequential Break A sequential break occurs seven pass points max when certain conditions satisfied in a specified order A reset point can be specified in addition to these pass points If the reset point is passed all sequential break conditions up to that point become invalid and the emulator rechecks from the first break condition Figure 1 13 illustrates the usual sequential break and figure 1 14 describes a sequential break when a reset point is specified Break condition The break condition is satisfied when instructions at addresses H 1000 and H 2000 have been User program executed in sequence flow 1000 2000 1000 Break condition 1 No break occurs 2000 when instruc
56. Alsace e oisi ed aite seien 314 Vec Voltage Display noo o tre Det ee eO Den en 315 Specifiable Conditions in Each Trace Mode seeeee 320 Specifiable Conditions TRACE CONDITION 4A eee 321 Specifiable Conditions TRACE CONDITION B eee 323 Specifiable Conditions TRACE CONDITION eee 325 Address Mask Specifications CONDITION 327 Mask Specifications TRACE CONDITION A B C esee 327 Shipment Defaults of TRACE DISPLAY MODE 332 Display of Minimum Time Stamp 336 Specifiable Conditions TRACE SEARCH eene 338 Mask Specifications TRACE SEARCH 341 Host Computer Related Commandis eese 343 LAN Gomiiands tee EI EUN EIER RAE SEHE wy hues ONERE ee EISE UNES 360 Emulator Error Messages eerte ueniet 389 Host I O Brror Codes 4 eet itte tert subs rore terr Ie eet ebrio sees 394 LAN VO Error Messages tente pec tee Re e ere Eee 395 Process Code for LAN I O Error Messages cesccesseesecssecssecseeeseeeseeeeeeeeeeeenes 397 Interface Software Error Messages sess eene 398 Part HI Appendices Table A 1 Table A 2 Signal Names and Usage of Serial Connector sss 403 Signal Names of Parallel Connector
57. BS Sets displays and cancels software breakpoints with pass sequence specification Command Format e Setting BREAK_SEQUENCEA lt pass point gt A lt pass point gt A lt pass point A lt pass point gt A lt pass point gt A lt pass point gt A lt pass point gt RET Pass point setting BREAK_SEQUENCEA lt reset point gt R RET Reset point setting e Display BREAK_SEQUENCE RET e Cancellation BREAK SEQUENCE A RET Pass point cancellation BREAK SEQUENCH A 5 R RET Reset point cancellation pass point Addresses two to seven points R Reset point specification reset point gt Address one point Note When an odd address is specified it is rounded down to an even address Description e Setting Sets pass points to enable the break for which the pass sequence is specified sequential break GO command emulation terminates when these pass points have been passed in the specified sequence Notes 1 Do not set a pass point or a reset point at any of the addresses below Address specified with the BREAK command Address that holds an illegal instruction H 0000 Areas other than CSO to CS4 excluding internal RAM area Address where BREAK CONDITION UBC 2 settings are satisfied refer to the following description Address containing a slot delayed branch instruction refer to the following description Address of the lower 16 bits of a 32 bit DSP instruction 2 Pass points or a
58. CAUTION Check the external probe direction and connect the external probe to the emulator station correctly Incorrect connection will damage the probe or connector When an external probe is connected to the emulator probe connector on the emulator station s rear panel it enables external signal tracing and multibreak detection Figure 3 5 shows the external probe connector External probe connector Pini External probe Pin 2 Pin 3 Enlarged view Probe PinNo Name Signal Name Remarks 1 1 Probe input 0 Synchronous break input pin Probe input 1 Probe input 2 Probe input 3 RUN break state RUN state identification signal output pin Trigger output Trigger mode output pin GND GND connection pin Figure 3 5 External Probe Connector Rev 1 0 09 00 page 30 of 423 HITACHI 3 2 4 Selecting the Clock This emulator supports three types of clock for the SH7612 a crystal oscillator attached on the EV chip board external clock input from the user system and the emulator internal clock The clock is specified with the CLOCK command This emulator can use a clock source of up to the SH7612 maximum operating frequency of 66 MHz quadruple of external clock frequency 16 5 MHz m X Crystal oscillator 8 to 16 5 MHz CLOCK command U External clock 1 to 33 MHz E Emulator internal clock 15 MHz Crystal Oscillator A crystal oscillator is not supplied with the emulator
59. CONDITION An A break condition specified with the BREAK_CONDITION_An command was satisfied n 1 to 8 BREAK CONDITION Bn A break condition specified with the BREAK_CONDITION_Bn command was satisfied n 1 to 8 BREAK CONDITION Cn A break condition specified with the BREAK_CONDITION_Cn command was satisfied n 1 to 8 BREAK CONDITION UBC1 2 Multiple break conditions specified with the BREAK CONDITION UBC1 2 commands were satisfied BREAK CONDITION Multiple break conditions specified with the BREAK CONDITION A A1 8 A1 to A8 command were satisfied BREAK CONDITION Multiple break conditions specified with the BREAK CONDITION B B1 8 B1 to B8 command were satisfied BREAK CONDITION Multiple break conditions specified with the BREAK CONDITION C C1 8 C1 to C8 command were satisfied BREAK CONDITION SB A sequential break condition specified with the BREAK CONDITION UBC1 2 commands was satisfied BREAK KEY The CTRL C keys were pressed or the ABORT command was executed for forcible termination BREAKPOINT Emulation stopped at a software breakpoint specified with the BREAK command BREAK SEQUENCE A condition for passing software breakpoints specified with the BREAK SEQUENCE command was satisfied ILLEGAL INSTRUCTION A break instruction H 0000 was executed NO EXECUTION The user program was not executed this message is displayed only for the RESULT comm
60. DATA The specified data is invalid Correctly enter the data 23 INVALID ADDRESS The specified address or address range is invalid Correctly enter the address 24 DATA OVERFLOW The specified data is more than 4 bytes Correctly specify the data 27 INVALID CONDITION Invalid conditions are specified Correctly enter the conditions 28 DOUBLE DEFINITION The item has already been defined Check the item to be defined 29 TOO MANY ALIASES Too many aliases are specified Delete any unnecessary alias and re specify 31 INSUFFICIENT MEMORY The size of emulation memory to be allocated with the MAP command was not available Emulation memory was allocated within the available memory size 32 INVALID ASM MNEMONIC An instruction mnemonic in an assembly language statement is invalid Correct the instruction mnemonic 33 INVALID ASM OPERAND An operand in an assembly language statement is invalid Correct the operand 34 ALREADY ASSIGNED A condition cannot be specified by the Rev 1 0 09 00 page 390 of 423 BREAK_CONDITION_A B C TRACE_CONDITION_A B C PERFORMANCE_ANALYSIS command Too many conditions are specified Cancel a condition for another command and re specify HITACHI Table 10 1 Emulator Error Messages cont Error No 35 Error Message CANNOT USE THIS MODE Description and Solution GO The GO command cannot be executed because settings for the execution mode are invalid Correctly specify the settings necessary
61. Display Displays STEP information according to the specified contents However the address and assembler instruction mnemonic of each executed instruction are not displayed Rev 1 0 09 00 page 305 of 423 HITACHI STEP_INFORMATION Examples 1 To display only the contents of system and control registers PC SR PR GBR VBR MACH MACL RS RE and MOD during STEP or STEP_OVER command execution SI 1 RET 2 To display no register information during STEP or STEP OVER command execution SI RET 3 To display memory contents from addresses 80 to H FB87 during STEP or STEP OVER command execution SI A FB80 FB87 RET 4 To display contents according to the specified display information SI RET PC 00001004 SR 000000F0 000000000000 IIII00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000FFEO00 DSR 00000000 FAKE RRR KK ek ERK COB A0G 00 A0 00000000 M0 00000000 X0 00000000 0 00000000 A1G 00 1 00000000 1 00000000 X1 00000000 1 00000000 00001002 MOV 00 RO MEMORY OOOOFF80 00 04 00 FF FO 00 02 00 10 00 02 00 OF 00 00 00 STACK OOOFFFEO 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5 NORMAL END Rev 1 0 09 00 page
62. Display Displays defined aliases as follows ALIAS RET alias name 1 gt lt alias definition 1 gt alias name 2 gt lt alias definition 2 gt alias name 3 gt lt alias definition 3 e Cancellation Cancels the specified alias ALIAS A alias name gt RET When no alias name is specified cancels all aliases ALIAS RET Note An alias itself cannot be included in the alias definition contents Rev 1 0 09 00 page 190 of 423 HITACHI ALIAS Examples 1 To define the alias name for the command to display the contents of register FRCOH as SHOW_FRCOH ALI SHOW FRCOH D 0D000042 1 B RET 2 To display all defined aliases ALI RET SHOW FRCOH D 0D000042 1 B SHOW FRCOL D 0D000043 Q1 B LT 11 test abs 3 To cancel the alias with alias name LT ALI LT RET Rev 1 0 09 00 page 191 of 423 HITACHI ASSEMBLE 7 2 4 ASSEMBLE A Assembles program one line each Command Format e Line assembly ASSEMBLE A lt address gt RET lt address gt The address where the object program is to be written Description e Line assembly After displaying the memory contents at the specified address the emulator enters subcommand input wait state Line input in subcommand input wait state is assembled into machine code which is written to memory Assembly is continued until a period finishing subcommand is entered The input and output formats are as follow
63. EV Chip Board Rev 1 0 09 00 page 408 of 423 HITACHI Appendix Connecting the Emulator to the User System C 1 Connecting to the User System AN WARNING Always switch OFF the emulator and user system before connecting or disconnecting any CABLES Failure to do so will result in a FIRE HAZARD and will damage the user system or emulator or result in PERSONAL INJURY Also the USER PROGRAM will be LOST The emulator is connected to the user system by using the QFP type EV chip board HS7612EBH81H or the connector type EV chip board HS7612EBK81H Table C 1 EV Chip Boards and User Interfaces EV Chip Board User Interface HS7612EBH81H 176 pin QFP NQPACK176SD HS7612EBK81H Specific connector FX2 100P 1 27SVL x 2 Note The NQPACK176SD is manufactured by TOKYO ELETECH CORPORATION The FX2 100P 1 27SVL is manufactured by Hirose Electric Co Ltd Rev 1 0 09 00 page 409 of 423 HITACHI 1 1 Connection Using the HS7612EBH81H AN WARNING Always switch OFF the emulator and user system before connecting or disconnecting any CABLES Failure to do so will result in a FIRE HAZARD and will damage the user system or emulator or result in PERSONAL INJURY Also the USER PROGRAM will be LOST Notes 1 For more details on the HS7612EBHS1H refer to the user s manual supplied with the EV chip board 2 This EV chip board can only be used in combination with the specific QFP socket NQPACK176SD Mount the 176 pin QFP so
64. FILE OK Y N N RET LOAD DIAGNOSTIC FILE OK Y N N RET FM DIR RET FILE ID STATUS SYS OK CONF OK LAN NO FIRM OK TRON NO DIAG NO INI OK MON OK FM gt Q RET START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ HITACHI 3 8 E8000 System Program Initiation When the emulator is turned on while S4 in DIP SW1 is turned off to the right and a manual system program load method is selected the emulator enters monitor command input wait state and the E8000 system program must be loaded and initiated by monitor commands If S4 in DIP SWI has been turned on to the left and the automatic system program load method is selected the E8000 system program is automatically loaded and initiated 3 8 1 Initiation on Emulator Monitor If S is entered followed by RET when the emulator is in monitor command input wait state the E8000 system program in the emulator flash memory is initiated Display at E8000 System Program Initiation START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T S RET SH7612 E8000 HS7612EDD81SF Vm n Copyright C Hitachi Ltd 1997 Licensed Material of Hitachi Ltd CONFIGURATION FILE LOADING HARDWARE REGISTER READ WRITE CHECK FIRMWARE SYSTEM LOADING EMULATOR FIRMWARE TEST RESET BY E8000 CLOCK EML MCU TYPE SH7612 MODE 00 MD4 0 1F REMAINING EMULATION
65. Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17 Figure 3 18 Figure 3 19 Figure 3 20 Figure 3 21 Figure 3 22 Figure 3 23 Figure 3 24 Figure 3 25 Emulator for the SH7 612 eie iret ertet pert ad ete P 4 Emulator Hardware Components essere eene 11 E8000 Station Front Panel esee eene ener 12 E8000 Station Rear Panel srice renr ere E K ree nennen 13 Device Control Boards ssc rera enkore sost Evenen ES PERSER recte es 15 EV Chip Board HS7612EBH81H 1 oo sess 16 Emulator Software Components essere nennen 18 System Configuration Using a LAN Interface seseseeeeeenee 20 System Configuration Using an RS 232C or Bidirectional Parallel Interface 21 System Configuration Using a PC Interface Board sss 22 Emulator Preparation Flow Chart sees 24 Connecting the Device Control Board sss 26 Connecting Trace Cables to the E8000 Station sse 28 Connecting Trace Cables to the EV Chip Board see 29 External Probe Connector eode wii d ng ren s 30 Installing the Crystal 32 Connecting the System 34 Connecting the Frame Ground 35 Console Interface Switches
66. Format Address condition A lt address 1 gt lt address 2 gt Description When only lt address 1 gt is specified the condition is satisfied when the address bus value matches the specified value When both lt address 1 gt and lt address 2 gt are specified the condition is satisfied when the address bus value is in the range from lt address 1 gt to lt address 2 gt If the NOT option is specified the condition is satisfied when the address bus value does not match the specified value This condition can be masked Data condition D lt 1 byte value gt NOT WD lt 2 byte value gt NOT LD lt 4 byte value gt NOT The condition is satisfied when the data bus value matches the specified value When D WD or LD is specified the break condition is satisfied when the address is accessed in bytes words or longwords respectively If the NOT option is specified the condition is satisfied when the data bus value does not match the specified value This condition can be masked Read Write condition R Read W Write The condition is satisfied in a read cycle R is specified or a write cycle W is specified Access type DAT Execution cycle DMA DMA cycle VCF Vector fetch cycle Default All bus cycles described above including program fetch cycle The condition is satisfied when the bus cycle type matches the specified type Multiple access types cannot be specified ei
67. Ground Rev 1 0 09 00 page 34 of 423 HITACHI If it is difficult to separate the signal ground from the frame ground insert the user system power cable and the emulator s power cable into the same outlet figure 3 8 so that the ground lines of the cables are maintained at the same ground potential The user system must be connected to an appropriate ground so as to minimize noise and the adverse effects of ground loops When connecting the EV chip board and the user system confirm that the ground pins of the EV chip board are firmly connected to the user system s ground Emulator power User system power cable _ ess cable Ground 100 120 V or 200 240 V AC power Figure 3 8 Connecting the Frame Ground Rev 1 0 09 00 page 35 of 423 HITACHI 3 3 System Connection The following describes the procedure for connecting the emulator to a work station or a host computer See figure 2 3 for the connector arrangement in the E8000 station Console Interface Setting The settings of the transfer rate data bit length stop bit length and parity can be changed Use console interface switches SW1 and SW2 on the back of the E8000 station to change the settings Switches SW1 and SW2 also include switches for the use of the console interface the LAN interface or the PC interface The console interface consists of 16 switches eight switches in both SW1 and SW2 as shown in figure 3 9 The switch state becomes on when the s
68. MODE RET MODE xx MD4 0 nn a a Operating mode xx and operating mode selection pin status on the user system MD4 0 nn refer to table 7 20 If a value other than those shown in the table is displayed as nn the SH7612 does not operate correctly Check the user system When the user system is not connected nn is displayed as 1F Rev 1 0 09 00 page 272 of 423 HITACHI MODE Table 7 20 Operating Mode Selection Pin Status and Display CSO Area Bus Width Clock Mode MD4 MD3 MD2 MD1 MDO Display nn Low Low Low Low Low 0 Low Low Low Low High 1 Low Low Low High Low 2 High High High High High 1F MODE Notes 1 The emulator operating mode is specified with the MODE command regardless of the operating mode selection pin MD4 to MDO status on the user system 2 The emulator does not operate correctly if clock mode 4 5 or 6 is selected unless the clock signal is input from the user system Make sure to input the clock signal from the user system When the user system is not connected select clock mode 0 1 2 or 3 with the MODE command and restart the emulator If clock mode 4 5 or 6 is selected and the E8000 does not activate normally the command wait state is entered if the break key is input Select correct mode with the MODE command 3 For available emulator operating modes refer to the Hardware Manual of the SH7612 HITACHI Rev 1 0 09 00 page 273 of 423 MODE Examples
69. Minimum distance 2 5m 0 5m between nodes Network cable Diameter 0 4 inch 1 02 cm Diameter 0 25 inch 0 64 cm 50 Q shielded coaxial cable 50 Q shielded coaxial cable RG 58A U Network connector N type connector BNC connector Transceiver cable Diameter 0 38 inch 0 97 cm Ethernet cable to be connected to the 15 pin D SUB connector Rev 1 0 09 00 page 44 of 423 HITACHI Network Layer e JP Internet Protocol Transmits and receives data in datagram format Does not support IP options Does not have subnet mask functions when HS7000ELNO1H is used Supports subnet mask functions when HS7000ELNO2H is used Does not support broadcast communications e ICMP Internet Control Message Protocol Supports only echo reply functions e ARP Address Resolution Protocol Calculates Ethernet addresses from IP addresses by using broadcast communications Transport Layer e TCP Transmission Control Protocol Logically connects the emulator to the workstation e UDP User Datagram Protocol Not supported Session Presentation and Application Layers e FTP File Transfer Protocol The emulator operates as a client e TELNET Teletype Network The emulator operates as a server Note The emulator communicates through routers or gateways for the HS7000ELN02H but not for the HS7000ELN01H 3 3 7 System Connection Examples N WARNING Always switch OFF the emulator and user system before connecting o
70. Mode Normal Mode Function This mode executes only user program emulation Until a break condition is satisfied the emulator executes the user program When a hardware break condition or software break condition is satisfied the emulator stops the program execution When a number of times or sequential break for the software break condition is specified the emulator stops only for a moment the program execution every time the specified address is passed and then resumes program execution Normal Mode Specification Specifying no option with the GO command sets normal mode 1 3 2 Cycle Reset Mode Cycle Reset Mode Function The emulator inputs the RES signal to the SH7612 after a specified time during realtime emulation and repeats the execution from the reset state When the RES signal is input to the SH7612 a low level pulse is output to the trigger output probe concurrently This function is useful to observe the waveform from the initial state such as power on reset to a specified time User program Re execution from Program flow Low level pulse is output to the trigger output probe RES input to the SH7612 after gt gt tre specified time Figure 1 1 Cycle Reset Mode Rev 1 0 09 00 page 114 of 423 HITACHI Cycle Reset Mode Specification Set as GO command option to specify cycle reset mode For details refer to section 7 2 21 GO Emulation Stop In cycle reset mode hardware bre
71. Multiple access types cannot be specified either select one of the access types on the left or specify none Rev 1 0 09 00 page 321 of 423 HITACHI TRACE_CONDITION_A B C Table 7 31 Specifiable Conditions TRACE_CONDITION_A cont Item and Input Format External probe condition PRB lt value gt Description The condition is satisfied when all of the emulator s external probe signals match the specified values Specify lt value gt as 1 byte data Each bit corresponds to a probe number as follows 3 2 1 0 lt Bit X x X X lt Specified value 4 3 2 1 lt Probe number x 0 Low level 1 High level This condition can be masked External interrupt condition 1 NMI L or NMI H The condition is satisfied when the NMI signal matches the specified level NMI or NMI L The condition is satisfied when NMI is low NMI H The condition is satisfied when NMI is high External interrupt condition 2 IRL lt value gt Rev 1 0 09 00 page 322 of 423 The condition is satisfied when all of the IRL signals match the specified values Specify lt value gt as 1 byte data Each bit corresponds to an IRL number as follows 3 2 1 0 lt Bit x X lt Specified value 1 0 lt IRL number x 0 Low level 1 High level x x 3 2 The condition can be masked HITACHI TRACE_CONDITION_A B C Table 7 32 Specifiable Conditions TRACE CONDITION B Item and Input
72. OK Y N RET INPUT COMMAND B SHDCT761 SYS RET LOAD ITRON DEBUGGER FILE OK Y N N RET LOAD DIAGNOSTIC FILE OK Y N N RET Rev 1 0 09 00 page 71 of 423 HITACHI 5 SN SN Defines the subnet mask value Command Format e Definition SN lt subnet mask value gt C RET e Display SN RET Description e Definition Defines the subnet mask value FM gt SN subnet mask value RET FM e Save Saves the setting specifications in the E8000 station when the C option is specified gt 5 subnet mask value RET LAN CONFIGURATION FILE WRITE OK Y N Y RET FM gt e Display Displays the subnet mask value FM SN RET SUB NET MASK xxx xxx xxx xxx H xx H xx H xx H xx Examples 1 To define 255 255 255 0 as the subnet mask value and save the setting specifications in the E8000 station FM gt SN 255 255 255 0 C RET LAN CONFIGURATION FILE WRITE OK Y N Y RET FM 2 To display the subnet mask value FM gt SN RET SUB NET MASK 255 255 255 0 H FF H FF H FF H 00 gt Rev 1 0 09 00 page 72 of 423 HITACHI 3 6 4 L L Sets the emulator IP address Command Format e Setting L RET Description e Setting Sets the emulator IP address Example To set the IP address of the E8000 station to 128 1 1 1
73. PLLGND Not connected m PLLGND Vcc 4 7 DREQO DREQ1 DREQO DREQ1 DACKO DACK1 DACKO DACK1 Figure 4 3 User System Interface Circuits cont Rev 1 0 09 00 page 169 of 423 HITACHI SH7612 User system LVT16244 MDO MD4 MDo MD4 LVT16652 x TCK LVT16244 Control circuit TMS TDI TDO x2 TCK Vcc connected 9 TMS TDI 4 7 KQ TDO LVT16244 LVT163373 LVT16244 LVT163373 Figure 4 3 User System Interface Circuits cont Rev 1 0 09 00 page 170 of 423 HITACHI SH7612 User system VHC244 External probes EXT1 4 EQC7128bEQC VHC244 Trigger Trigger output pin output pin Execution Execution state signal state signal input input Figure 4 3 User System Interface Circuits cont Rev 1 0 09 00 page 171 of 423 HITACHI Rev 1 0 09 00 page 172 of 423 HITACHI Section 5 Troubleshooting The emulator internal system test checks the emulator s internal RAM and registers at power on and at system program initiation 5 1 Internal System Test Internal System Test at Power On The emulator checks its internal RAM and registers at power on While tests are in progress the following messages are displayed E8000 MONITOR HS8000ESTO2SR Vm n Copyright C Hitachi Ltd 1995 a Licensed Material of Hitachi Ltd ESTING b RAM 0123 START E8000 S START E8000 F FLASH MEMORY TOOL c L SET LAN PARAMET
74. RET PLEASE SELECT NO 1 9 L E Q X L RET NO lt HOST NAME gt lt IP ADDRESS gt NO lt HOST NAME gt lt IP ADDRESS gt 01 host 128 2141 02 03 04 05 06 07 08 09 E8000 ADDRESS PLEASE SELECT NO 1 9 L E Q X E RET LAN CONFIGURATION FILE WRITE OK Y N RET FM gt Rev 1 0 09 00 page 68 of 423 HITACHI Q Q Terminates the flash memory management tool Command Format e Termination Q RET Description e Termination Terminates the flash memory management tool Example To terminate the flash memory management tool FM gt Q RET START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T Rev 1 0 09 00 page 69 of 423 HITACHI RTR RTR RTR Defines the remote network routing information Command Format e Definition RTR RET Description e Definition Defines the remote network routing information Enter the IP address and network number as follows after the specified number is entered and the emulator prompts them FM RTR RET PLEASE SELECT NO 1 10 L E Q X definition number RET IP ADDRESS router IP address RET NET ID network number RET e Display Entering L RET displays the list of the
75. Ready DTR High when emulator s power is on 5 Ground GND Connected to the emulator s frame ground 6 Data Set Ready DSR Not connected 7 Request To Send RTS High when emulator s power is on 8 Clear To Send CTS Not connected 9 Not connected Rev 1 0 09 00 page 403 of 423 HITACHI 2 Parallel Connector Figure A 2 shows the parallel connector pin alignment at the emulator station Table A 2 lists signal names ES gt D gt 25 r i Figure 2 Parallel Connector Pin Alignment at the Emulator Station Rev 1 0 09 00 page 404 of 423 HITACHI Table A 2 Signal Names of Parallel Connector Pin No Signal Name Pin No Signal Name 1 PeriphAck 19 SignalGround 2 Xflag 20 SignalGround 3 PeriphClk 21 SignalGround 4 nPeriphRequest 22 SignalGround 5 nAckReverse 23 SignalGround 6 Data1 LSB 24 SignalGround 7 Data2 25 SignalGround 8 Data3 26 SignalGround 9 Data4 27 SignalGround 10 Data5 28 SignalGround 11 Data6 29 SignalGround 12 Data7 30 SignalGround 13 Data8 MSB 31 SignalGround 14 nReverseRequest 32 SignalGround 15 HostClk 33 SignalGround 16 IEEE1284 active 34 SignalGround 17 HostAck 35 SignalGround 18 HostLogicHigh 36 PeripheralLogicHigh Rev 1 0 09 00 page 405 of 423 HITACHI LAN Connector Figure A 3 shows the LAN connector pin alignment at the emulator station Table A 3 lists signal names Figure LAN Connector Pin Alignment
76. S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ HITACHI Manual System Program Load by LAN Interface To use the emulator files E8000 SYS SHCNF761 SYS and SHDCT761 S YS must be installed in the emulator flash memory If the emulator is connected to the host computer via the LAN interface the E8000 system program can be loaded with the following procedures Transfer all files on the system floppy disk to the host computer using the FTP before installation For details on the transfer method refer to the host computer user s manual It takes approximately one minute Operations Display Message 1 Power on the emulator For details START E8000 on the power on procedures refer S START E8000 to section 3 5 1 Power On F FLASH MEMORY TOOL Procedures for LAN Interface L SET LAN PARAMETER Confirm the emulator monitor T START DIAGNOSTIC TEST command prompt is displayed S F L T _ 2 Enter F RET to initiate the flash S F L T F RET memory management tool The FM emulator displays prompt FM and waits for a flash memory management tool command 3 Enter SL RET to load the system FM SL RET program 4 Enter 2 RET to select WS as the SELECT LOAD No 1 PC or 2 WS 2 RET host computer type since the LAN interface is used 5 Enter the host computer name In INPUT SYSTEM LOADING HOST NAME hostname RET this example hostname is entered 6 Enter the user name
77. The CKIO pin can become the Hi Z state Mode 3 The PLL2 circuit operates The CKIO pin is always in the Hi Z state The control bit of the FMR can switch between operation and stop of the PLL2 circuit Mode 4 The PLL1 circuit operates Operate the PLL1 circuit with the same External phase between a clock input from the CKIO pin and the LSI internal clock input clock ld The PLL2 circuit always stops The control bit of the FMR can switch between operation and stop of the PLL1 circuit Mode 5 The PLL1 circuit operates Operate the PLL1 circuit when the phases of a clock input from the CKIO pin and the LSI internal clock lo Eo are shifted by 1 46 cycles behind the system clock The PLL2 circuit always stops The control bit of the FMR can switch between operation and stop of the PLL1 circuit Mode 6 Both the PLL1 and PLL2 circuits always stop Set mode 6 when operating the SH7612 with the same frequency clock as a clock input from the CKIO pin Notes 1 Operating modes 0 to 3 Operating modes 0 to 3 are not supported when a crystal oscillator is connected to the XTAL and EXTAL pins To use a crystal oscillator in these modes connect it to the EV chip board crystal oscillator terminal 2 High impedance Rev 1 0 09 00 page 158 of 423 HITACHI Table 3 2 shows the relationship between the combination of 2 to MDO pins and the operating mode Do not switch between p
78. USE AND RESULTS OBTAINED FROM THE EMULATOR PRODUCT Rev 1 0 09 00 page II of VI HITACHI State Law Some states do not allow the exclusion or limitation of implied warranties or liability for incidental or consequential damages so the above limitation or exclusion may not apply to you This warranty gives you specific legal rights and you may have other rights which may vary from state to state The Warranty is Void in the Following Cases Hitachi shall have no liability or legal responsibility for any problems caused by misuse abuse misapplication neglect improper handling installation repair or modifications of the emulator product without Hitachi s prior written consent or any problems caused by the user system All Rights Reserved This user s manual and emulator product are copyrighted and all rights are reserved by Hitachi No part of this user s manual all or part may be reproduced or duplicated in any form in hard copy or machine readable form by any means available without Hitachi s prior written consent Other Important Things to Keep in Mind 1 Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi s semiconductor products Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein 2 No license is granted by implication or otherwise und
79. Use one that has the same frequency as that of the user system When using a crystal oscillator as the SH7612 clock source the frequency must be from 8 to 16 5 MHz When using frequencies outside this range supply an external clock from the user system N WARNING Always switch OFF the emulator and user system before connecting or disconnecting the CRYSTAL OSCILLATOR Failure to do so will result in a FIRE HAZARD and will damage the user system and emulator or will result in PERSONAL INJURY The USER PROGRAM will be LOST Use the following procedure to install the crystal oscillator 1 Check that the emulator power switch is turned off Ensure that the power lamp on the left side of the E8000 station s front panel is not lit 2 Attach the crystal oscillator into the terminals on the EV chip board figure 3 6 Rev 1 0 09 00 page 31 of 423 HITACHI Enlarged view Crystal oscillator terminals Figure 3 6 Installing the Crystal Oscillator 3 Turn on the user system power and then the emulator power X crystal oscillator will then be automatically specified in the CLOCK command Using the crystal oscillator enables execution of the user program at the user system s operating frequency even when the user system is not connected External Clock Use the following procedure to select the external clock N WARNING Always switch OFF the emulator and user system before connecting or disconnecting the EV CHIP BOARD
80. and the USER SYSTEM Failure to do so will result in a FIRE HAZARD and will damage the user system and the emulator or will result in PERSONAL INJURY The USER PROGRAM will be LOST 1 Check that the emulator power switch is turned off Ensure that the power lamp on the left side of the E8000 station s front panel is not lit 2 Connect the EV chip board to the user system and supply a clock through the EXTAL pin from the user system 3 Turn on the user system power and then the emulator power U external clock will then be automatically specified in the CLOCK command Emulator Internal Clock Specify E 15 MHz with the CLOCK command Rev 1 0 09 00 page 32 of 423 HITACHI Reference When the emulator system program is initiated the emulator automatically selects the SH7612 clock source according to the following priority 1 External clock when supplied from the user system 2 Crystal oscillator when attached to the EV chip board 3 15 MHz emulator internal clock Rev 1 0 09 00 page 33 of 423 HITACHI 3 2 5 Connecting the System Ground The emulator s signal ground is connected to the user system s signal ground via the EV chip board In the E8000 station the signal ground and frame ground are connected figure 3 7 At the user system connect the frame ground only do not connect the signal ground to the frame ground E8000 station Signal ground Frame ground Ground Figure 3 7 Connecting the System
81. assembler Linkage editor Host computer Figure 2 6 Emulator Software Components Rev 1 0 09 00 page 18 of 423 HITACHI Table 2 1 Contents of E8000 System Disk File Name E8000 SYS Contents E8000 system program Description Controls the EV chip board and processes commands such as emulation commands Loaded into the emulator memory SHDCT761 SYS SH7612 control program Controls the SH7612 in the EV chip board Loaded into the emulator memory SHCNF761 SYS Configuration file Contains SH7612 operating mode and MAP information IPW EXE Interface program Operates on the Microsoft Windows95 of the PC and communicates with the emulator DIAG SYS Diagnostic program Loaded into the emulator station memory for testing and maintenance SETUP CC Load file Loads files E8000 SYS SHDCT761 SYS Note See section 3 7 System Program Installation and SHCNF761 SYS to the emulator memory Rev 1 0 09 00 page 19 of 423 HITACHI 2 3 System Configuration The E8000 station can be connected to the host computer via a LAN interface optional LAN board an RS 232C interface or a bidirectional parallel interface 2 3 1 System Configuration Using a LAN Interface By installing an optional LAN board in the E8000 station the emulator can communicate with a workstation using a LAN interface The LAN board contains connectors for both Cheapernet 1OBASE2 and Ethernet IOBASES5 The system configura
82. at the Emulator Station Table A 3 Signal Names Pin No Signal Name 1 Not connected 2 COL 3 TX 4 5 RX 6 GND 7 8 Ls 9 COL 10 TX 11 12 RX 13 12 14 15 Rev 1 0 09 00 page 406 of 423 HITACHI A 4 Serial Interface Cable Figure A 4 shows the wiring for the serial interface cable Emulator serial connector The numbers represent connector pin numbers Figure A 4 Serial Interface Cable Note that the serial interface cable provided may not be suitable for some host computers In that case use the wiring shown in figure A 5 Emulator Emulator serial connector serial connector The numbers represent connector pin numbers The numbers represent connector pin numbers a X ON X OFF control Figure A 5 Serial Interface Cable Using Other Cables Rev 1 0 09 00 page 407 of 423 HITACHI Appendix Emulator External Dimensions and Weight Figures B 1 and B 2 show the external dimensions and weight of the emulator station and EV chip board respectively Emulator station pod interface cable Unit mm Weight of the emulator station 5 05 kg Figure B 1 External Dimensions and Weight of the Emulator Station LES ee be E oes Toe 115 0 Hoo CEST HS7612EBK81H Weight of the EV chip board HS7612EBH81H 0 180 kg Unit mm HS7612EBK81H 0 170 kg Figure B 2 External Dimensions and Weight of the
83. be satisfied when the address is a multiple of four Rev 1 0 09 00 page 325 of 423 HITACHI TRACE_CONDITION_A B C b Access to a 16 bit bus area e Longword access Longword data is accessed in two word access cycles Only word data WD and a multiple of two can be specified as the data and address conditions respectively 16 bits must be specified as the data bus width e Word access Word data is accessed in one bus cycle Only word data WD and a multiple of two can be specified as the data and address conditions respectively 16 bits must be specified as the data bus width e Byte access Byte data is accessed in one bus cycle Only byte data D can be specified as the data condition Both even and odd address values can be specified as the address condition 16 bits must be specified as the data bus width Note that the data condition must be specified in combination with a specific address condition If no address condition is specified or if the address is masked the data condition will be satisfied when the address is a multiple of two c Access to an 8 bit bus area All addresses can be accessed in byte units Longword data and word data are accessed in four byte access cycles and two byte access cycles respectively Both even and odd addresses can be specified as the address condition Note however that only byte data D is valid for the data condition Eight bits must be specified as the data bus width
84. break does not occur When this mode is specified PC breaks are invalid Condition 2 is satisfied Condition 1 is satisfied Condition 2 is satisfied Condition 1 is satisfied Condition 2 is satisfied Condition 2 is satisfied Condition 1 is satisfied Condition 2 is satisfied lt BREAK key lt BREAK key Measurement time a b Measurement time d Figure 1 23 Time Interval Measurement Mode 2 Rev 1 0 09 00 page 139 of 423 HITACHI 17 2 Subroutine Time Measurement and Number of Times Measurement The subroutine time and number of times the subroutines are executed can be measured based on the total program execution time by the PERFORMANCE_ANALYSIS command Specify the subroutine to be measured with start and end addresses The maximum number of subroutines which can be measured is shown in table 1 6 Table 1 6 Maximum Number of Measurable Subroutines Measurement Mode Maximum Number of Measurable Subroutines Time measurement mode 1 8 Time measurement mode 2 Time measurement mode 3 8 4 Access count to specified area 4 Number of nested subroutine calls 4 The measurement results are displayed in the following three ways e Numerical ratio of a specified subroutine execution time to a total execution time e Bar graph indicating the ratio of a specified subroutine execution time to a total execution time e Numerical value of specified subroutine execution time For de
85. cache through area 32 Mbytes CS1 cache through area 32 CS2 cache through area 32 Mby CS3 cache through area 32 Mby CS4 cach Reserved Associative purge 128 Mbytes Address pis d ytes e through area 32 Mbytes read write 512 Reserved Data array read write 4 Kbytes Reserved SDRAM mode setting 16 kbytes Internal peripheral module Exception vector table 256 bytes Externa area burst ROM 32 Mbytes External area 32 Mbytes External area synchronous DRAM 32 Mbytes External area DRAM synchronous DRAM 32 Mbytes External area I O device 2 Mbytes Figure D 1 Memory Map Rev 1 0 09 00 page 422 of 423 HITACHI Appendix ASCII Codes 1 n 5 z x N E ras Up Lower four bits Figure E 1 ASCII Codes Rev 1 0 09 00 page 423 of 423 HITACHI SH7612 E8000 Emulator User s Manual Publication Date 1st Edition September 2000 Published by Electronic Devices Sales amp Marketing Group Semiconductor amp Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hitachi Kodaira Semiconductor Co Ltd Copyright Hitachi Ltd 2000 All rights reserved Printed in Japan
86. can be traced at realtime For details refer to section 1 5 Realtime Trace Function Figure 1 18 illustrates the trace acquisition condition User program Nd Trace memory Trace acquisition condition is satisfied Break condition When the user program stops is satisfied the trace buffer stores trace information from the address at which the trace acquisition condition was satisfied Figure 1 18 Trace Acquisition Condition Rev 1 0 09 00 page 134 of 423 HITACHI Trace Stop Parallel Mode When a trace stop condition is specified the emulator acquires trace information until the specified condition is satisfied At this point trace acquisition stops and the emulator prompts for command input in parallel mode although realtime emulation does not stop Refer to section 1 3 3 Parallel Mode for details Once the trace stop conditions have been satisfied and the trace information has been displayed the user can specify the trace stop condition again The user can specify the following conditions e Address bus or data bus value e Read write condition e Access type DAT VCF e External probe value e System control signal BREQ e NOT condition e Delay count H 1
87. cannot be specified either select one of the access types on the left or specify none The data conditions of the BREAK CONDITION UBCI break are satisfied when the address bus and data bus values match the specified values The data bus the SH7612 internal bus is always 32 bits long Note the following when specifying break conditions e Longword access Longword data is accessed in one bus cycle Only longword data LD and a multiple of four can be specified as the data and address conditions respectively e Word access Word data is accessed in one bus cycle Only word data WD and a multiple of two can be specified as the data and address conditions respectively e Byte access Byte data is accessed in one bus cycle Only byte data D can be specified as the data condition Both even and odd address values can be specified as the address condition Rev 1 0 09 00 page 215 of 423 HITACHI BREAK_CONDITION_UBC A bit mask in 1 bit or 4 bit units can be specified for the address PC and data conditions of the BREAK CONDITION_UBC1 2 command When a bit is masked the condition is satisfied irrespective of its bit value To implement the mask specify each digit to be masked at input as an asterisk Table 7 12 shows mask specification examples Example 1 The following condition is satisfied when the lower four bits of the address condition are not specified BREAK CONDITION UBCI A H 400000 RET
88. defined host computer e Initiation Entering E RET saves the new specifications in the emulator flash memory and initiates the LAN board Entering Q RET saves the new specifications in the emulator flash memory without initializing the LAN board and terminates LH command execution Entering X RET terminates LH command execution without saving the new specifications Example To define router IP address 128 1 2 1 for network number 128 1 2 0 as the routing information FM gt RTR RET PLEASE SELECT NO 1 10 L E Q X 1 RET IP ADDRESS 128 1 2 1 RET NET ID 128 1 2 0 RET PLEASE SELECT NO 1 10 L E Q X L RET NO IP ADDRESS lt NET ID gt NO IP ADDRESS lt gt 01 128 1 2 1 128 1 2 0 02 PLEASE SELECT NO 1 10 L E Q X E RET LAN CONFIGURATION FILE WRITE OK Y N Y RET FM Rev 1 0 09 00 page 70 of 423 HITACHI SL SL SL Loads the system program Command Format e Load SL RET Description e Load Loads the system program Example To load the system program FM gt SL RET SELECT LOAD No 1 PC or 2 WS 1 RET SELECT INTERFACE 1 RS 232C or 2 PARALLEL 2 RET E8000 SYSTEM FILE OK Y N Y RET INPUT COMMAND B E8000 SYS RET LOAD CONFIGURATION FILE OK Y N Y RET INPUT COMMAND B SHCNF761 SYS RET LOAD FIRMWARE FILE
89. display all emulator commands HELP RET lt All commands are displayed in their full names and abbreviations e To display a command input format HELPA command name gt RET A command input format is displayed In this example an abbreviation of the command name can be entered as command name Rev 1 0 09 00 page 179 of 423 HITACHI 6 1 3 Word Definition Constants or file names can be entered as command parameters or options Spaces A or commas can be inserted between words Words are described below Constants Numeric constants character constants and expression can be used as constants e Numeric constants The following shows numeric constant formats A radix is entered at the head of a numeric constant S nnnnnnnn S Radix of a constant B Binary Q Octal D Decimal H Hexadecimal X Fixed point Default Value specified with the RADIX command nnnnnnnn Value based on the radix 4 byte value maximum Example To indicate 100 in decimal D 100 If the radix is omitted the radix specified with the RADIX command is automatically used Example If the radix is omitted while hexadecimal is specified with the RADIX command entering 10 means H 10 e Character constants Enclosed with single or double quotation marks If a single or double quotation mark is used as data add two sequential quotation marks Example 1 A H 41 Example 2 H 27 single quotation mark
90. displayed c In time interval measurement modes 1 and 2 the maximum execution time from the point when the BREAK CONDITION UBC 2 condition is satisfied until the BREAK CONDITION condition is satisfied is displayed d In time interval measurement modes 1 and 2 the minimum execution time from the point when the BREAK CONDITION UBC 2 condition is satisfied until the BREAK CONDITION UBC I condition is satisfied is displayed Rev 1 0 09 00 page 294 of 423 HITACHI RESULT In time interval measurement modes 1 and 2 the average execution time from the point when the BREAK CONDITION_UBC2 condition is satisfied until the BREAK _ CONDITION condition is satisfied is displayed f User program execution time in decimal According to the TIME option of the EXECUTION MODE command the maximum measurable time is 488 124 or 6 hours where the minimum measurement time is 1 6 us 406 ns or 20 ns respectively If the period exceeds the maximum measurable time it is displayed as g Cause of termination Note Displayed register contents show values at program termination not the current values Example To display execution results RT RET PC 00005C60 SR 000000F0 000000000000 IIII00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000rFF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 0000
91. eene 405 Rev 1 0 09 00 page xiii of xiv HITACHI Table A 3 Table C 1 Table C 2 Table C 3 Table C 4 Signal Names ani is sain Sas Sie Sina Ae ee 406 EV Chip Boards and User Interfaces 0 0 0 0 ee ee eeeesecesecesecsseceeeceeeaeeeaeeeeeeeeeenens 409 Pin Assignment of the HS7612EBHS8IH oo eee eene 415 Pin Assignment of the HS7612EBK81H User Interface USER I F1 417 Pin Assignment of the HS7612EBK81H User Interface USER I F2 419 Rev 1 0 09 00 page xiv of xiv HITACHI Part I E8000 Guide 11 Section 1 Overview Overview This system is an efficient software and hardware development support tool for application systems using the SH7612 microcomputer developed by Hitachi Ltd The SH7612 MCU contains the following components on a single chip DSP High speed CPU Timer Serial communication interface SIO DMAC Hitachi UDI Hitachi User Debug Interface port The emulator operates in place of the SH7612 MCU and performs realtime emulation of the user system The emulator also provides functions for efficient hardware and software debugging The emulator consists of an emulator E8000 station an SH7612 device control board and an evaluation chip board hereafter referred to as an EV chip board as shown in figure 1 1 The EV chip board is directly installed onto the user system Rev 1 0 09 00 page 3 of 423 HITACHI LAN board HS7000ELNO1H or HS7000ELN
92. eite eitis 190 Tad ASSEMBLE sion Rei eU Ee Ut e I e reb 192 7 2 5 BACKGROUND INTERRUPT eteinen e a eene nennen enne 194 T20 BREAK aee nrp na eit ode n ee iea eter re ii end 199 7 2 7 BREAK CONDITION 202 7 2 8 BREAK CONDITION UBC 5 pite He qe ti eet teenth Pertenece 213 7 2 9 BREAK SEQUENCE une e E E e n pt eee ELE 219 1210 CHECK e 223 7 22 11 CEOCRK 3 ages essed RR E epp Me 224 7 22 12 4 CONFIGURATION 5 eee teh eet deci teet op Eee 226 12 13 CONVERT nct ae PE et Dette 228 DATA CHANGE abi eni e Ree ius 230 F219 DATACSEARCLL noii DO PORE 232 7 216 DISASSEMBLE mer ions eai 234 7 2 11 DUMP i RA PE A a ese doy Be res 237 72 18 BND id ene en uH hin ee ae QUU 240 7 219 EXECUTION MODE iere etre m tee en P 241 3 2 20 PILL s nnt cite Seed Rae ie A Bais Shi eae ts Seles RSS 247 3 2 21 GO sued eere e gen thee gunner a 249 7 522 HBEB iun ESRB GNE 259 1752 23 HISTORY 1 enr ptt teen ee bte aec rd ee o dede 262 Rev 1 0 09 00 page vi of xiv HITACHI 42 24 ND watts ote Souter the Bite hee on ite Pit en Read eS pes 263 72 25 eta RU e eU iE are ER QI n 264 12 20 MEMORY Sa SS I Re 268 7227 MODE ehe o iei i he d dte eee eti deeds 272 1 22 28 HDD D UR HEODeP UR Re Ie 275 7 2 29 MOVE TO ca rene eripe shart 2
93. environment Source level debugging Graphic display of trace information A PC board for interfacing with a PC enabling high speed downloading 1 Mbyte min of user programs SH7612 E8000 Hitachi Debugging Interface option can be loaded into the PC to enable Graphic display operations in a multi window environment Source level debugging Rev 1 0 09 00 page 5 of 423 HITACHI 1 2 Warnings CAUTION READ the following warnings before using the emulator product Incorrect operation will damage the user system and the emulator product The USER PROGRAM will be LOST 1 Check all components with the component list after unpacking the emulator 2 Never place heavy objects on the casing 3 Observe the following conditions in the area where the emulator is to be used Make sure that the internal cooling fans on the sides of the E8000 station must be at least 20 cm 8 away from walls or other equipment Keep out of direct sunlight or heat Refer to section 1 3 Environmental Conditions Use in an environment with constant temperature and humidity Protect the emulator from dust Avoid subjecting the emulator to excessive vibration For details refer to section 1 3 Environmental Conditions 4 Protect the emulator from excessive impacts and stresses 5 Before using the emulator s power supply check its specifications such as power output voltage and frequency For details of the power su
94. error occurs re execute using another system disk If an error still occurs inform a Hitachi sales agency of the error Rev 1 0 09 00 page 175 of 423 HITACHI 5 2 Troubleshooting Procedure This section provides a troubleshooting Problem Analysis Diagram PAD see figure 5 1 to reduce the time taken by troubleshooting As you work through the diagram e Follow the instructions that request operator assistance or intervention e Note that system defect means that the emulator station is malfunctioning Execute the diagnostic program as described in the Diagnostic Program Manual HS7612TM81ME and inform a Hitachi sales agency of the test results in detail because a system defect may be caused by a number of reasons Rev 1 0 09 00 page 176 of 423 HITACHI Emulator system System failure defect START System defect Emulator monitor Console message connected Yes displayed correctly Power lamp Connect on with correctly power on No Check power supply breaker fuse outlet to emulator Set power Defect in source supply power or emulator power Breaker fuse Failure fails again occurred Power lamp defect Emulator fan working Internal system Switch test at power on defect passed System defect System program initiated correctly Correct system program installed Re instal
95. for failure or damage when used beyond the guaranteed ranges Even within the guaranteed ranges consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail safes so that the equipment incorporating Hitachi product does not cause bodily injury fire or other consequential damage due to operation of the Hitachi product 5 This product is not designed to be radiation resistant No one is permitted to reproduce or duplicate in any form the whole or part of this document without written approval from Hitachi 7 Contact Hitachi s sales office for any questions regarding this document or Hitachi semiconductor products IMPORTANT INFORMATION READ FIRST READ this user s manual before using this emulator product e KEEP the user s manual handy for future reference Do not attempt to use the emulator product until you fully understand its mechanism Emulator Product Throughout this document the term emulator product shall be defined as the following products produced only by Hitachi Ltd excluding all subsidiary products e Emulator station e Device control board e EV chip board The user system and a host computer are not included in this definition Purpose of the Emulator Product This emulator product is a software and hardware development tool for systems employing the Hitachi microcomputer HD6417612 hereafter referred to as SH7612 By exchang
96. for the specified execution mode 37 TOO MANY POINTS Too many points are specified Remove any unnecessary settings and re enter 38 SET POINT IS NOT IN RAM A write protected address is specified by the BREAK or BREAK SEQUENCE command Specify a correct address 39 BUFFER EMPTY TRACE or TRACE SEARCH The trace buffer is empty Check trace conditions and execution state and re execute Then display trace information 42 CANNOT CHANGE ATTRIBUTE OF X Y MEMORY AREA An attempt was made to change the memory attribute of the internal memory area Allocate emulation memory to areas other than the internal memory area 43 CANNOT RECOVER XXXXXXXX The break instruction at the address where a breakpoint is specified with the BREAK or BREAK_SEQUENCE command could not be recovered after GO command execution terminates Accordingly a break instruction remains at the breakpoint address A hardware error might have occurred Correct the error and reload and re execute the program 44 VERIFY ERROR A verification error occurred when modifying memory contents Writing to ROM was attempted or there was a hardware error Check the memory area 45 NOT FOUND The specified data or information was not found Correctly specify data 46 BREAKPOINT ADDRESS The memory contents of the specified address cannot be modified in parallel mode because the address is used by the BREAK
97. function to display user program contents in mnemonics This function is performed with the DISASSEMBLE command and enables to debug without referencing to a program list For details refer to section 7 2 16 DISASSEMBLE Rev 1 0 09 00 page 153 of 423 HITACHI Rev 1 0 09 00 page 154 of 423 HITACHI Section 2 Differences between SH7612 and the Emulator When the emulator system is initiated or when the emulator resets the SH7612 as a result of a command such as the CLOCK command switching the clock or the RESET command note that the general registers and part of the control registers are initialized Table 2 1 Differences between Initial Values of the SH7612 and Emulator Registers State Emulator initiation power on Register PC RO to R14 R15 SP SR PR VBR GBR MACH MACL DSR MOD RS RE AO 1 MO M1 XO X1 YO Y1 A1G Note Xis an undefined value Emulator Reset vector value H 00000000 Stack pointer value H 000000F0 H 00000000 H 00000000 H 00000000 H 00000000 H 00000000 H 00000000 H 00000000 H 00000000 H 00000000 H 00000000 H 00000000 H 00000000 H 00 SH7612 Reset vector value Undefined Stack pointer value H 00000XFX Undefined H 00000000 Undefined Undefined Undefined H 00000000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined The emulator s user system interface is provided with pull up resistors and a buffer causing the signal
98. instruction is executed The replaced instruction at the address is not executed After the GO command is executed the contents at the specified address will be replaced with a break instruction and the user program will be executed When the user program execution stops the break instruction will be replaced again with the contents at the specified address Therefore the contents at the specified address can be accessed immediately after the user program execution using the DISASSEMBLE command or the DUMP command However note that a break instruction will be read if the memory contents at the break address are accessed in the parallel mode No software break must be specified immediately after a delayed branch instruction at a slot instruction If specified a slot invalid instruction interrupt will occur at the branch instruction execution and a break will not occur The software break can be performed in the following two ways e Normal break e Sequential break Rev 1 0 09 00 page 126 of 423 HITACHI Normal Break A break occurs before executing the breakpoint instruction specified with the BREAK command At this time the following can be specified e Number of breakpoints 255 points max e Number of times the break condition is satisfied A break occurs after executing the breakpoint instruction a specified number of times The maximum number to specify is 65 535 H FFFF User program Program flow
99. interface cable or and interface board bidirectional parallel interface cable Connect the PC interface cable BRUN Sec 3 3 5 Figure 3 1 Emulator Preparation Flow Chart Rev 1 0 09 00 page 24 of 423 HITACHI 3 2 Emulator Connection 3 2 1 Connecting the Device Control Board At shipment the device control board is packed separately from the E8000 station Connect the device control board to the E8000 station according to the following procedure Also use the following procedure to connect them after remove the device control board from the E8000 station to change the device control board N WARNING Always switch OFF the emulator and user system before connecting or disconnecting any CABLES Failure to do so will result in a FIRE HAZARD and will damage the user system and the emulator or will result in PERSONAL INJURY The USER PROGRAM will be LOST 1 Check that the emulator power switch is turned off Ensure that the power lamp on the left side of the E8000 station s front panel is not lit 2 Remove the AC power cable of the E8000 station from the outlet if the cable is connected to the outlet 3 Remove the back panel from the E8000 station For the slot to which the device control board is to be connected DCONT is marked 4 Connect the device control board to the E8000 station When connecting the board prevent the upper or lower side
100. internal clock is selected instead e When initiating the emulator system program the emulator selects the SH7612 clock automatically in the following order When an external clock is supplied from the user system selects the user clock When a crystal oscillator is installed to the emulator pod selects the crystal oscillator Selects the emulation clock 15 MHz Check of the I O signals The emulator checks the connection with the user system at system initiation By this check abnormalities such as short circuits of a user system interface signal can be detected The signals to be checked are as follows RES BREQ WAIT IRLO to IRL3 and NMI The CHECK command can check the same signals that are checked at system initiation For details refer to section 7 2 10 CHECK Rev 1 0 09 00 page 146 of 423 HITACHI Emulator Execution Status Display The emulator can display execution status information listed in table 1 7 To display the execution status use the STATUS command For details refer to section 7 2 36 STATUS Table 1 7 Execution Status Display Display Command Description MODE xx SH7612 operating mode RADIX xx Radix type BREAK xx Number of breakpoints specified with the BREAK command HOST xx Host computer interface condition CLOCK xx Type of clock EML USER XTAL EML_MEM S xxxxxxB Remaining standard emulation memory STEP_INFO REG a e Register information displayed by the STEP command
101. interrupt STEP execution may not terminate STEP lt number of execution steps gt lt start address gt lt stop PC gt J RET The following instructions are valid when the J option is specified BT BF BRA JMP BSR JSR BTS BFS BRAF BSRF TRAPA If the R option is specified instruction mnemonics and register information are displayed only during execution within the opening routine At that time single step execution continues until the instruction at lt stop PC gt is executed The jump addresses of branch instructions such as JSR or BSR are not displayed Although this function is similar to the STEP_OVER command function the latter is recommended because of its faster execution time STEP number of execution steps lt start address gt lt stop PC gt R RET If a break occurs while executing a subroutine with R option specification the subroutine start address and its instruction mnemonic are displayed No interrupts are accepted during STEP command execution unless the I option has been specified After the STEP command has been executed so long as it was not forcibly terminated and if no other command has been entered single step execution can be continued by simply pressing the RET key 1 Single step execution is achieved by using the hardware break function BREAK CONDITION UBC2 command Accordingly conditions specified with the BREAK CONDITION UBC2 command are invalid when using the
102. is satisfied satisfied Figure 1 21 Normal Mode Time Measurement Range Time Interval Measurement Mode 1 The emulator measures the elapsing between the satisfaction of hardware break conditions 2 BREAK CONDITION UBC2 and 1 BREAK CONDITION UBCI Condition 2 _ Condition 2 __ Condition 2 is satisfied is satisfied is satisfied Condition 2 b is satisfied Condition 1 Y Condition 1 _ _ BREAK key is satisfied is satisfied Measurement time a Measurement time b Measurement time c Figure 1 22 Time Interval Measurement Mode 1 In this mode even if break condition 2 is satisfied a break does not occur A break occurs after the hardware break condition 2 and then break condition 1 are satisfied Rev 1 0 09 00 page 138 of 423 HITACHI Even if break condition 2 is satisfied many times before break condition 1 the emulator measures the time from the first occasion on which break condition 2 is satisfied When this mode is specified PC breaks are invalid Time Interval Measurement Mode 2 In this mode the time intervals between the satisfaction of break condition 2 BREAK_CONDITION_UBC2 and break condition 1 BREAK CONDITION UBCI are added together This mode is selected by specifying option 12 with the GO command In time interval measurement mode 1 a break occurs after the hardware break condition 2 and then break condition 1 are satisfied However in this mode even if break condition 1 is satisfied a
103. lt address 1 gt and lt address 2 gt are specified the condition is satisfied when the address bus value is in the range from lt address 1 gt to lt address 2 gt This condition can be masked Data condition D lt 1 byte value gt WD lt 2 byte value gt LD lt 4 byte value gt The condition is satisfied when the data bus value matches the specified value When D WD or LD is specified the break condition is satisfied when the address is accessed in bytes words or longwords respectively This condition can be masked Read Write condition R Read W Write The condition is satisfied in a read cycle R is specified or a write cycle W is specified Access type DAT Execution cycle DMA DMA cycle VCF Vector fetch cycle Default All bus cycles described above including program fetch cycle The condition is satisfied when the bus cycle type matches the specified type Multiple access types cannot be specified either select one of the access types on the left or specify none External probe condition PRB lt value gt The condition is satisfied when all of the emulator s external probe signals match the specified values Specify lt value gt as 1 byte data Each bit corresponds to a probe number as follows 3 2 1 0 lt Bit X x X X lt Specified value 4 3 2 1 lt Probe number x 0 Low level 1 High level This condition can be masked Rev 1 0 09 00 page 203
104. of 423 HITACHI Table 7 1 Emulation Commands cont Usable Unusable in Command Function Parallel Mode GO Executes realtime emulation Unusable HELP Displays all commands and command format Usable HISTORY Displays all input commands Usable ID Displays the version number of the E8000 Usable system program MAP Specifies and displays memory attribute Unusable MEMORY Displays and modifies memory contents Usable MODE Specifies and displays the SH7612 operating Unusable mode MOVE Transfers memory contents Unusable MOVE_TO_RAM Moves ROM contents to standard emulation Unusable memory PERFORMANCE _ Specifies cancels initializes and displays Usable ANALYSIS performance analysis data QUIT Terminates E8000 system program Unusable RADIX Specifies and displays radix for numeric input Usable REGISTER Displays register contents Unusable RESET Resets SH7612 Unusable RESULT Displays execution results Unusable STATUS Displays emulator execution status Usable STEP Performs single step execution Unusable STEP INFORMATION Specifies and displays information during Unusable single step execution STEP_OVER Performs single step execution except for Unusable subroutines TRACE Displays trace buffer contents Usable TRACE CONDITION Specifies displays and cancels trace Usable A B C acquisition conditions TRACE_DISPLAY_ Specifies and displays trace information display Usable MODE mode TR
105. of 423 HITACHI BREAK_CONDITION_A B C Table 7 5 Specifiable Conditions BREAK CONDITION A1 A8 cont Item and Input Format External interrupt condition 1 NMI L or NMI H Description The condition is satisfied when the NMI signal matches the specified level NMI or NMI L The condition is satisfied when NMI is low NMI H The condition is satisfied when NMI is high External interrupt condition 2 IRL lt value gt Rev 1 0 09 00 page 204 of 423 The condition is satisfied when all of the IRL signals match the specified values Specify lt value gt as 1 byte data Each bit corresponds to an IRL number as follows 3 2 1 0 lt Bit x X lt Specified value 1 0 lt IRL number x 0 Low level 1 High level X x 3 2 The condition can be masked HITACHI BREAK_CONDITION_A B C Table 7 6 Specifiable Conditions BREAK CONDITION 1 8 Item and Input Format Address condition A lt address 1 gt lt address 2 gt Description When only lt address 1 gt is specified the condition is satisfied when the address bus value matches the specified value When both lt address 1 gt and lt address 2 gt are specified the condition is satisfied when the address bus value is in the range from lt address 1 gt to lt address 2 gt If the NOT option is specified the condition is satisfied when the address bus value does not match the specified value Th
106. or BREAK_SEQUENCE command 47 FTP NOT CONNECTED The command cannot be executed because the FTP interface is not connected Connect the FTP interface with the FTP command Rev 1 0 09 00 page 391 of 423 HITACHI Table 10 1 Emulator Error Messages cont Error No Error Message Description and Solution 48 FTP ALREADY CONNECTION The FTP interface has already been connected Disconnect the FTP interface and re enter the command 49 CONDITION ALREADY USED The condition cannot be specified because another command has already specified it 50 RESERVED AREA A reserved area was accessed 51 INTERNAL I O AREA The internal I O area was accessed 52 INTERNAL AREA An attempt was made to access an area other than CSO to CS4 This area cannot be accessed with this command Check the specified address 54 INVALID CONFIGURATION The configuration file in emulator flash memory is FILE invalid Re install the configuration file from the system disk 55 CONFIGURATION FILE NOT The configuration file was not found in the FOUND emulator flash memory Re install the configuration file from the system disk 56 INVALID CONFIGURATION The configuration file in emulator flash memory CHECK ERROR contains invalid data Re install the configuration file from the system disk 57 ILLEGAL INSTRUCTION The memory contents of the address specified ADDRESS with the BREAK or BREAK_SEQUENCE command is a break instructi
107. page 230 of 423 HITACHI DATA_CHANGE If data 1 is not found at any point in the replacement range the following message is displayed 45 NOT FOUND Memory modification with this command can be performed only in areas CSO to CS4 or the internal memory areas Examples 1 To replace 2 byte data H 6475 in the address range from 7000 to H 7FFF with H 5308 with confirmation message DC 6475 5308 7000 7FFF W RET 00007508 CHANGE Y N Y RET 00007530 CHANGE Y N N RET 2 replace 4 byte data DATA in the address range from H FB80 to H FE00 with DATE without confirmation message DC DATA DATE FB80 FE00 L Y RET Rev 1 0 09 00 page 231 of 423 HITACHI DATA_SEARCH 7 2 15 DATA SEARCH DS Searches for memory data Command Format e Search DATA_SEARCHA lt data gt A lt start address gt A lt end address gt A lt number of bytes gt lt size gt AN RET lt data gt Data to be searched for start address gt Search start address Default 0 end address gt Search end address Default Maximum address of H FFFFFFFF lt number of bytes gt The number of bytes to be searched for Default Maximum address of H FFFFFFFF same as end address gt lt size gt Length of data to be searched for B 1 byte W 2 bytes L 4 bytes Default 1 byte N Data other than the specified data is searched for Description e Search
108. reached when setting the breakpoint program execution terminates when reaching the breakpoint for the specified number of times Note When multiple passes are specified for a breakpoint the program must be temporarily stopped each time a software breakpoint is passed to update the pass count and user program emulation continues until the number of times the breakpoint must be passed is satisfied As a result realtime emulation is not performed Example To generate a break when the instruction at address 300 is executed five times BREAK 300 5 RET Software breakpoints are ignored during STEP and STEP_OVER command execution so the pass count is not updated at this time When execution starts at the address set with the BREAK command immediately after execution starts the BREAK_CONDITION_UBC2 command settings are invalidated Therefore even though a BREAK_CONDITION_UBC2 command setting is satisfied immediately after execution start GO command execution does not terminate Ifa software breakpoint is set at a slot delayed branch instruction a slot illegal instruction interrupt occurs instead of terminating program execution Make sure not to set a software breakpoint at a slot delayed branch instruction Display Display format is as follows BREAK RET lt ADDR gt lt CNT gt lt PASS gt XXXXXXXX 7777 b c a Setting address b Specified pass count hexadecimal c Value of pass
109. satisfied when the lower four bits of the address condition are not specified BREAK CONDITION A H 400000 RET Table 7 8 Address Mask Specifications BREAK CONDITION Radix Mask Unit Example Mask Position Binary 1 bit B 01110 Bits 2 to 0 are masked Hexadecimal 4 bits H 000F50 Bits 7 to 0 are masked Note When address 2 gt is not specified for an address condition address 1 gt can be consecutively masked from the lowest bit It is not possible to mask any desired bit position as shown in the following examples Examples Allowed BREAK CONDITION A1 10 Not allowed BREAK_CONDITION_A1 A H 1 00 BREAK CONDITION A1 A H100 10 A bit mask in 1 bit or 4 bit units can be specified for the data IRL or PRB condition of the BREAK CONDITION A B C command When a bit is masked the condition is satisfied irrespective of its bit value To implement the mask specify each digit to be masked at input as an asterisk Table 7 9 shows these mask specification examples Example The following condition is satisfied when address 3000000 is the address condition and bit 0 is zero in the byte data condition BREAK CONDITION A H 3000000 D B Q RET Table 7 9 Mask Specifications BREAK CONDITION Radix Mask Unit Example Mask Position Allowed Condition Binary 1 bit B 01 1010 Bits 0 and 5 are masked Data D WD LD IRL or PRB Hexa 4 bits H F 50 Bits 15 to 8 are ma
110. shown in the following Figure 3 19 shows the File menu and Setting menu locations in the interface software IPW display File F HS8000EIWOTSF V1 1 4 SereenG chi Ltd 1996 pot Material of Hitachi Ltd Figure 3 19 File Menu and Setting Menu Rev 1 0 09 00 page 51 of 423 HITACHI 1 Clicking COMM in the Setting menu displays the Communication Setting box figure 3 20 The Communication Setting box can also be displayed by pressing Alt S keys and then the C key Set the communications conditions to be the same as those of the DIP switches on the E8000 station rear panel Communication Setting Baud rate B Serial Port P 1200 2400 c 4800 COM c 19200 36400 7 1 bit Data bit D Stop bit S B bits None X ON X OFF Parity P Flow control F CANCEL Figure 3 20 Communication Setting Box Rev 1 0 09 00 page 52 of 423 HITACHI 2 Selecting Screen in the Setting menu displays the Screen Setting box figure 3 21 The Screen Setting box can also be displayed by pressing Alt S keys and then the S key Font Font Style T erminal Courier Courier New Fixedsys Terminal Effects O Strikeout C Underline yZz Color Figure 3 21 Screen Setting Box Rev 1 0 09 00 page 53 of 423 HITACHI 3 Clicking Exit in the File menu terminates interface software I
111. the specified memory contents in the host computer connected via the FTP interface Command Format e Save LAN SAVEA cstart address gt A lt end address gt A number of bytes lt load module type gt ALF lt file name RET start address gt Start memory address end address gt End memory address number of bytes The number of bytes to be saved oad module type Load module type S S type load module H HEX type load module M Memory image file Default S type load module LF Adds an LF code H 0A to the end of each record file name File name in the host computer Description e Save Saves the specified memory contents in the host computer connected via the FTP interface An S type HEX type or M type load module can be saved An SYSROF type or ELF type load module cannot be saved Before executing this command connect the emulator to the host computer with the FTP command The current save address is displayed as follows SAVING ADDRESS xxxxxxxx XXXXXXXx Current save address continuously updated When save is completed the start and end memory addresses are displayed as follows TOP ADDRESS lt start address gt END ADDRESS lt end address gt When the LF option is specified the emulator adds an LF code to the end of each record in addition to a CR code H OD Rev 1 0 09 00 page 376 of 423 HITACHI LAN SAVE Notes 1 Do not save data in t
112. time measurement mode 1 Rev 1 0 09 00 page 280 of 423 HITACHI PERFORMANCE_ANALYSIS e Subroutine call count measurement mode Counts the number of times the subroutine defined by lt subroutine name gt lt start address gt and lt end address gt calls the subroutine specified by lt called subroutine address range gt The subroutine execution time is measured using subroutine execution time measurement mode 1 Table 7 21 lists the measurement modes that can be specified by each PERFORMANCE_ANALYSIS command When break conditions or trace conditions have been set subroutines may not be set to their maximum number Table 7 21 Measurement Modes for Each Command Measurement Mode PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 Subroutine execution time O O O O measurement mode 1 Subroutine execution time O O O measurement mode 2 Subroutine execution time X O X X O X measurement mode 3 Area access count O X O X X O X measurement mode Subroutine call count X O X X O X measurement mode Note O Mode can be specified X Mode cannot be specified Up to eight subroutines can be specified when using only subroutine execution time measurement mode 1 or 2 for measurement However only up to four subroutines can be specified in subroutine execution time measurement mode 3 area access count measurement mode and subroutine call count measurement mode This comman
113. to addresses D 10 and D 10 at trace information display TDM PTR D 10 D 10 RET 2 To display the specified contents TDM RET PTR D 000010 D 000010 DISPLAY ITEM A D MA RW ST IRL NMI RES BREQ VCC PRB 3 To specify not to display external probe information PRB as bus cycle information at trace information display with the TRACE or TRACE SEARCH command TDM PRB D RET Rev 1 0 09 00 page 333 of 423 HITACHI TRACE_MODE 7 243 MODE TMO Specifies and displays trace information acquisition mode Command Format e Setting TRACE MODE ADMA D E AREF D E AOVFB D E ATIME 0 1 2 3 C RET Display TRACE MODE RET DMA Specifies whether trace information acquisition for DMA cycles are enabled D Disables trace information acquisition for DMA cycles E Enables trace information acquisition for DMA cycles default at emulator shipment REF Specifies whether trace information acquisition for refresh cycles are enabled D Disables trace information acquisition for refresh cycles E Enables trace information acquisition for refresh cycles default at emulator shipment OVFB Specifies whether a break occurs when the trace buffer overflows D A break does not occur when the trace buffer overflows default at emulator shipment E A break occurs when the trace buffer overflows TIME Specifies the minimum time stamp unit 0 Acquires trace information o
114. types cannot be specified DMA DMA cycle either select one of the access types on the left or specify VCF Vector fetch cycle nong Default All bus cycles described above including program fetch cycle Address and data conditions are satisfied when address bus values and data bus values match the specified values Note the following when specifying trace conditions a Access to a 32 bit bus area Longword access Longword data is accessed in one bus cycle Only longword data LD and a multiple of four can be specified as the data and address conditions respectively Word access Word data is accessed in one bus cycle Only word data WD and a multiple of two can be specified as the data and address conditions respectively 32 bits must be specified as the data bus width Note that the data condition must be specified in combination with a specific address condition If no address condition is specified or if the address is masked the data condition will be satisfied when the address is a multiple of four Byte access Byte data is accessed in one bus cycle Only byte data D can be specified as the data condition Both even and odd address values can be specified as the address condition 32 bits must be specified as the data bus width Note that the data condition must be specified in combination with a specific address condition If no address condition is specified or if the address is masked the data condition will
115. written to address is satisfied R2 F000000 Figure 1 7 Break with Read Write Rev 1 0 09 00 page 121 of 423 HITACHI Delay Count and Number of Times Break Condition is Satisfied These functions can only be specified with the BREAK_CONDITION_UBC1 and BREAK_CONDITION_B commands Note that these functions cannot be specified together specify one function at a time In delay count specification a break occurs when the above break condition address bus value data bus value or read write condition is satisfied and the emulator executes the bus cycle for a specified number of times 65 535 max When specifying this condition specify it in combination with any of the above break conditions Note For the BREAK_CONDITION_UBC1 command only a satisfaction count can be specified Break condition H 50 bus cycles are executed after the address H 2000 User program prog is accessed Program flow e Specification A 2000 DELAY 50 Break condition is satisfied No break occurs H 50 bus cycles Break occurs H 50 bus E cycles after the satisfaction E of the condition Figure 1 8 Break with Delay Count Specification Rev 1 0 09 00 page 122 of 423 HITACHI In number of times break condition is satisfied specification a break occurs when the above break condition address bus value data bus value or read write condition is satisfied for a specified number of times 65 535 max When specifying this con
116. xxxxxx if a delay count condition is specified as a break or trace condition the delay will be indicated as a positive value D xxxxxx b Instruction address c Instruction mnemonic d Instruction operand To display trace information in bus cycle units uses the following format Time Stamp Display BP AB DB MA RW STS IRL NMI RES BRQ PRB TIME_STAMP D XXxxxx _ XXXXXXXX XXXXXXXX XXX x XXX XXXX x x x x XXxHxxMxxSxxxxxxUxxxN b c d e f g h i G k m Clock Cycle Display BP AB DB MA RW STS IRL NMI RES BRQ VCC PRB CLK D Xxxxxx XXXXXXXX XXXXXXXX XXX x XXX XXXX x x x x XXXX n a Bus cycle pointer Number of bus cycles from an instruction where a delay count condition is satisfied In bus cycles which prefetch instructions the instruction mnemonics and instruction addresses are displayed as described above When two instructions are executed in one bus cycle both mnemonics are displayed along with the address of the first instruction Although the pointer usually has a negative value D xxxxxx when a delay count condition is specified as a break or trace condition the delay will be indicated as a positive value D xxxxxx b Address bus value Rev 1 0 09 00 page 313 of 423 HITACHI Data bus value According to the SH7612 access size longword word and byte values are displayed at the digits corresponding to the bus line
117. 0 09 00 page 293 of 423 HITACHI RESULT 7 2 35 RESULT RT Displays execution results Command Format Display RESULT RET Description Display Displays current register contents execution time and the GO STEP or STEP_OVER command termination cause The display format is as follows RESULT RET PC 00005C60 SR 000000F0 000000000000 ITTI00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 a RS 00000000 RE 00000000 MOD 00000000 0 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000FFE00 5 00000000 ____ A0G 00 0 00000000 M0 00000000 X0 00000000 Y0 00000000 A1G 00 A1 00000000 M1 00000000 X1 00000000 Y1 00000000 I TIME D 0000H 00M 00S 000000US 000NS 00 0 E COUNT D 00000 b MAX D 0000H 00M 00S 000000US 000NS MIN D 0000H 00M 00S 000000US 000NS c and d AVE D 0000H 00M 00S 000000US 000NS e RUN TIME D 0000H 00M 00S 000018US 000NS f lt cause of termination gt g a The register contents at emulation termination b In time interval measurement modes 1 and 2 execution time from the point when the BREAK CONDITION 2 condition is satisfied until the BREAK CONDITION _ UBC condition is satisfied is displayed In only time interval measurement mode 2 the execution count during this period is also
118. 0 page 262 of 423 HITACHI ID 7 2 24 ID ID Displays version number of E8000 system program Command Format e Display ID RET Description e Display Displays the version and revision numbers of the SH7612 E8000 system program Example To display the version and revision numbers of the SH7612 E8000 system program ID RET SH7612 E8000 HS7612EDD81SF Vm n Copyright C Hitachi Ltd 1997 Licensed Material of Hitachi Ltd Rev 1 0 09 00 page 263 of 423 HITACHI 7 2 25 MP Specifies and displays memory attribute Command Format e Specification MAPA cstart address A end address memory attribute RET e Display MAP A lt start address A end address gt RET start address gt Start address of memory area whose attribute is to be specified or displayed end address End address of memory area whose attribute is to be specified or displayed memory attribute Memory type U Memory in the user system cancels emulation memory usage S Standard emulation memory in emulator SW Standard emulation memory in emulator with write protection Description e Specification Allocates standard emulation memory to areas CSO to CS4 in 1 Mbyte units The emulation memory can be write protected by specifying SW as the memory attribute The start address is rounded down to 0 or a multiple of H 100000 and the end address is rounded up to a multiple of H 100000 mi
119. 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000020 20 20 20 20 20 20 20 20 20 20 20 45 38 30 30 30 E8000 2 To display 20 bytes of memory dump from address H FB80 in 4 byte units D FB80 20 L RET lt ADDRESS gt lt D A T A gt lt ASCII CODE 0000FB80 00000000 00000001 00000002 00000003 0000FB90 00000000 00000001 00000002 00000003 We SOLES EASE EM Rev 1 0 09 00 page 238 of 423 HITACHI DUMP 3 To display a memory dump in 32 bit fixed point units from addresses H F000 to H F3FF D F000 F3FF XL RET lt ADDRESS gt lt HEX gt lt FIXED POINT gt 0000F000 70000000 0 8750000000 0000 004 40000000 0 5000000000 0000F008 60000000 0 7500000000 0000F3FC 77400000 0 9921875000 4 To display a memory dump in 16 bit fixed point units from addresses H F000 to D F000 F3FF XW RET lt ADDRESS gt HEX FIXED POINT 0000F000 7000 0 87500 0000F002 4000 0 50000 0000 004 6000 0 75000 7740 0 99218 Rev 1 0 09 00 page 239 of 423 HITACHI END 7 2 18 END Cancels parallel mode Command Format e Cancellation END RET Description e Cancellation Cancels parallel mode during GO command execution Entering the END command clears old trace information and starts storing new trace information Example To cancel parallel mode during GO command execution G RET PC 00
120. 0 and its password as PASSWORD Operations Display Message 1 Enter FTP HITACHI RET to connect the emulator to the host computer using the FTP server The emulator asks for the user name Enter E8000 RET The emulator asks for the password Enter PASSWORD RET The message shown on the right which indicates that the emulator and the host computer have been connected is displayed The prompt becomes FTP gt To load program PROGRAM MOT enter LAN LOAD S PROGRAM MOT RET This example assumes that the load module is S type FTP HITACHI RET Username E8000 RET Password PASSWORD RET login command success FTP FTP LAN LOAD S PROGRAM MOT RET While loading the address to which LOADING ADDRESS xxxxxxxx the program is being loaded is displayed as shown on the right 7 When the program has been loaded TOP ADDRESS 01001000 the start address of the program END ADDRESS 0100101F TOP ADDRESS and its end address END ADDRESS are displayed Entering BYE RET terminates the FTP server connection The message shown on the right is displayed Rev 1 0 09 00 page 90 of 423 FTP 2BYE RET bye command success HITACHI 4 2 5 Executing the Program Execute the loaded program by the following procedures Operations Display Message 1 Set the initial values of the SP RET registers Enter SP RET to set the R15 SP xxxxxxxx O100FFFC RET stack pointer SP reg
121. 000 MOD 00000000 RO 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000FFEO00 DSR 00000000 FRE RRR KK eek eee A0G 00 A0 00000000 0 00000000 0 00000000 0 00000000 A1G 00 1 00000000 1 00000000 X1 00000000 1 00000000 00001070 5 ADDRESS Rev 1 0 09 00 303 of 423 HITACHI STEP_INFORMATION 7 2 38 STEP INFORMATION SI Specifies and displays information during single step execution Command Format e Specification STEP INFORMATION Acregister information AA start address gt A end address gt A number of bytes gt ASP lt stack display byte count gt RET e Display STEP_INFORMATION RET lt register information gt Register to be displayed 1 Displays PC SR PR GBR VBR MACH MACL RS RE and MOD 2 Displays RO to R15 3 Displays DSR AO AOG Al MO X1 YO and Y1 ALL All register information is output default at emulator initiation No information displayed Default ALL lt start address gt Start address of memory dump lt end address gt End address of memory dump Default is 16 bytes of memory beginning at lt start address gt lt number of bytes gt Number of bytes of memory dump Default is 16 bytes lt stack display byte count gt Number of bytes of stack contents Rev 1 0 09 00 page 304 of 423
122. 0000 00000000 00000000 00000000 00000000 00000000 00000000 000FFE00 DSR 00000000 x X ook eee A0G 00 A0 00000000 M0 00000000 X0 00000000 YO 00000000 A1G 00 A1 00000000 M1 00000000 X1 00000000 Y1 00000000 RUN TIME D 0000H 00M 00S 002241US 000NS BREAKPOINT Rev 1 0 09 00 page 295 of 423 HITACHI STATUS 7 2 36 STATUS ST Displays emulator execution status Command Format e Display STATUS RET Description e Display Displays emulator execution status in the following format MODE a RADIX b BREAK c HOST d STEP INFO REG e A f SP g CLOCK h MEM S a MODE xx SH7612 operating mode specified with the MODE command b RADIX xxx Default input number type BIN Binary OCT Octal DEC Decimal HEX Hexadecimal FIX Fixed point c BREAK D xxx Number of breakpoints decimal d HOST x1x2x3x4x5 Interface conditions with serial port 1 Baud rate BPS Bits per second 1 2400 BPS 2 4800 BPS 3 9600 BPS 4 19200 BPS 5 38400 BPS x2 Data length for one character 8 8bits 7 7 bits x3 Parity N None E Even O Odd x4 Number of stop bits 1 1 stop bit 2 2 stop bits x5 Busy control method X X ON X OFF control RTS CTS control Rev 1 0 09 00 page 296 of 423 HITACHI STATUS e STEP_INFO REG x1 x2 x3 Register information displayed with the STEP command 1 2 3 1 Space 2 Space 3 Space Control register PC SR
123. 00000000 1 00000000 X1 00000000 Y1 00000000 00001000 MOV RO R1 STEP NORMAL END Rev 1 0 09 00 page 302 of 423 HITACHI STEP 2 To perform single step execution from addresses H 1060 to H 1070 with information displayed only for branch instructions S FFFF 1060 1070 J RET PC 0000106A SR 000000F0 000000000000 IIII00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000FFEO00 DSR 000000000 X x x Xo x kk COB A0G 00 A0 00000000 0 00000000 X0 00000000 0 00000000 A1G 00 1 00000000 1 00000000 X1 00000000 Y1 00000000 00001064 JMP RO 00001066 NOP PC 0000106E SR 000000F0 000000000000 IIII00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000FFEO00 DSR 00000000 FARK RK KKK e kde c0B A0G 00 0 00000000 M0 00000000 X0 00000000 0 00000000 A1G 00 1 00000000 1 00000000 X1 00000000 Y1 00000000 0000106 BT 00001070 PC 00001072 SR 000000F0 000000000000 IIII00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000
124. 003400 RET Parallel mode entered M FD80 RET 0000FD80 00 FF RET Command execution in parallel mode 0000FD81 00 RET E RET Parallel mode cancellation PC 00003800 Rev 1 0 09 00 page 240 of 423 HITACHI EXECUTION_MODE 7 2 19 EM Specifies and displays execution mode Command Format e Setting EXECUTION_MODE ABREQ lt BREQ option gt ATIME lt TIME option gt ATRGU lt TRGU option gt ATRGB lt TRGB option gt AMON lt MON option gt AWAIT lt WAIT option gt ACT lt CT option gt AMB lt MB option gt AUBC lt UBC option gt C RET e Setting EXECUTION_MODE C RET interactive mode lt BREQ option gt lt TIME option gt lt TRGU option gt TRGB option Specifies whether the BREQ bus request signal inputs are enabled E Enables the BREQ signal inputs default at emulator shipment D Disables the BREQ signal inputs Specifies the minimum time to be measured for the GO command execution 1 1 6 us default at emulator shipment 2 406ns 3 20ns When hardware break conditions set by the BREAK CONDITION _ UBC 1 2 command are satisfied specifies whether a pulse is output from the trigger output pin of the emulator without a break E Outputs a trigger without a break M Break occurs and outputs a trigger D Break occurs but does not output a trigger default at emulator shipment When hardware break conditio
125. 09 00 page 95 of 423 HITACHI 4 2 9 Displaying Trace Information Trace information acquired during program execution can be displayed in various ways as follows Operations 1 To display the instruction mnemonic information enter TRACE RET IP D 000008 D 000007 D 000006 p 000005 p 000004 p 000003 p 000002 p 000001 p 000000 2 To display the trace information in ADDR 00 00 00 00 00 00 00 00 00 CD D CO OO CO 0 4 gt 000 002 004 006 008 00A 00C 00E 010 bus cycle units enter TRACE B RET BP AB D 000008 01001000 D 000007 01001004 01001000 D 000006 01001008 01001002 01001004 D 000005 0100100C 01001006 001008 00101C 001010 00100A 00100C 001014 00100 OOFFF8 001010 001018 D 000004 D 000003 D 000002 D 000001 CX A CE 0X Go CX 05 D 000000 DB 101 E201D405 6323321C 24266133 0100FFFC 70FF8800 8BF80009 00000002 AFFE0009 Rev 1 0 09 00 page 96 of 423 MA EXT EXT EXT EXT EXT EXT EXT EXT EXT Display Message TRACE RET OV OV OV OV L OV ADD OV L OV ADD TRACE B RET RW STS IRL PRG 1111 PRG 1111 MOV PRG 1111 MOV MOV PRG 1111 MOV L MOV DAT 1111 PRG 1111 ADD MOV L PRG 1111 MOV DAT 1111 ADD PRG 1111 HITACHI OPERAND OA RO 01 R1 01 R2 0
126. 10 1 Table 10 2 Table 10 3 Table 10 4 Table 10 5 Address Mask Specifications BREAK_CONDITION_A B C 209 Mask Specifications BREAK CONDITION A B C 209 Specifiable Conditions BREAK CONDITION 214 Specifiable Conditions BREAK CONDITION 2 215 Mask Specifications BREAK CONDITION 1 2 216 SH7612 Pin Test ioter rete ete ei etiem 223 Saved Configuration Information eese retener enne 226 Cycle Reset Lies 2 teet RUE Becta UE 251 Restrictions for Realtime Emulation Modes seen 252 Causes of GO Command Termination essere eene 255 Execution Status Display tette von Ene eite io Nee eet uiua 256 MEMORY Command Options essere eee eene 270 Operating Mode Selection Pin Status and Display sees 273 Measurement Modes for Each Command sene 281 Radix Examples eR UE re EHE 290 DSR Register Setting Bits sess eene nennen 292 Causes of STEP Command Termination eese 300 Causes of STEP OVER Command Termination eee 309 MA Display Rh emeret as ec pr e eti b Ie recess 314 R W Display enge cei oT PRETEREA Hanes 314 STS Display
127. 100101C R4 R2 R3 R1 R2 R2 R4 R3 R1 FF RO NMI RES BRO VCC PRB 1 1 1 1 1111 1 1 1 ji 1111 0A RO 1 1 1 1 1111 01 R1 01 R2 1 1 1 1 lici 0100101C R4 R2 R3 1 1 1 1 DIPL 1 1 1 1 R1 R2 R2 R4 1 1 1 1111 R3 R1 1 1 1 1 alga ai fFF RO i 1 I 1111 Operations Display Message 3 To temporarily stop the trace TRACE B RET information display enter CTRL CTRL S stops trace information display S To continue the trace information CTRL restarts trace information display enter CTRL Q display CTRL S and CTRL Q are also effective with other information displays Rev 1 0 09 00 page 97 of 423 HITACHI 4 3 Application Examples 4 3 1 Break with Pass Count Condition The pass count condition can be set to a breakpoint by the following procedures Operations 1 Enter BREAK 1001012 5 RET to terminate program execution immediately after address H 1001012 is passed five times 2 To start execution from address H 1001000 enter GO 1001000 RET 3 When address H 1001012 is passed five times the data shown on the right is displayed and GO command execution terminates 4 Entering BREAK RET displays the breakpoint address the specified count and the pass count as shown on the right The pass count is cleared when the GO command is entered again Rev 1 0 09 00 page 98 of 423 Display Message BREAK 1001012 5 RET GO 1001000 RET
128. 100C E00A OV 0A RO 0000100E 6053 OV R5 RO 00001010 1658 OV L R5 20 R6 00001012 5568 OV L 20 R6 R5 00001014 6053 OV R5 RO 00001016 880A CMP EQ 0A RO 00001018 8902 BT 00001020 0000101A E001 OV 01 R0 0000101C 380C ADD RO R8 0000101E 0009 OP RET ADDR CODE OPERAND 00001020 2100 OV B RO R1 00001022 2201 OV W RO R2 00001024 2302 OV L RO R3 Rev 1 0 09 00 page 235 of 423 HITACHI DISASSEMBLE 3 To disassemble and display five instructions starting from address H 2000 DA 2000 5 RET ADDR CODE INEMONIC OPERAND 00002000 F80A70A2 PADD PMULS X0 YO MO OVX W 4 XO OVY W R6 YO 00002004 000B RTS 00002006 0009 OP 00002008 1F01 OV L 4 R15 0000200A 6673 OV R7 R6 Rev 1 0 09 00 page 236 of 423 HITACHI DUMP 7 2 47 DUMP D Displays memory contents Command Format e Display DUMPAs start address A end address gt A number of bytes gt lt display RET lt start address gt Start address for memory dump lt end address gt End address for memory dump lt number of bytes gt Size of data for memory dump If is omitted this value is determined as lt end address gt or lt number of bytes gt according to the inequalities given below Default is 256 bytes as size End address start address gt lt specified value Number of bytes lt start address gt gt specified
129. 18US 000NS BREAKPOINT Rev 1 0 09 00 page 93 of 423 HITACHI 4 2 7 Executing a Single Step A single step can be executed using the single step function by the following procedures Operations 1 The program counter points to the next address to be executed when the GO command terminates Entering STEP RET here executes only a single instruction The information shown on the right is displayed 01001010 ADD FF RO shows the address and mnemonic code executed by the STEP command and STEP NORMAL END shows that single step execution has terminated To repeat single step execution enter only RET This can be repeated until another command is executed Rev 1 0 09 00 page 94 of 423 Display Message STEP RET PC 01001012 SR 000000F0 000000000000 GBR 00000000 VBR 00000000 MACH 00000000 MACL RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 00000000 00000000 00000000 00 R8 15 00000000 00000000 00000000 00000000 00 DSR 00000000 X eee COB A0G 00 A0 00000000 MO 00000000 X0 00000000 Y A1G 00 A1 00000000 M1 00000000 X1 00000000 Y 01001010 FF STEP NORMAL END ADD RET PC 01001014 SR 000000F0 000000000000 GBR 00000000 VBR 00000000 MACH 00000000 MACL RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 00000000 00000000 00000000 00 R8 15 00000000 00000000 00000000 00000000 00 5 00000000 A0G 00 A0 00000000 00000000
130. 1H or 1 HS7612EBK81HE HS7612EBH81H HS7612EBH81HE description notes 1 4 3 Options In addition to the E8000 station and EV chip board components the options listed in table 1 5 are also available Refer to each option manual for details on these optional components Table 1 5 Optional Component Specifications Item Model Name LAN board HS7000ELNO1H HS7000ELNO2H Specifications TCP IP communications protocol Ethernet 10BASE5 Cheapernet 10BASE2 PC interface board HITACHI HS6000EII01H ISA bus Rev 1 0 09 00 page 9 of 423 Rev 1 0 09 00 page 10 of 423 HITACHI Section 2 Components 2 1 Emulator Hardware Components The emulator consists of an E8000 station an SH7612 device control board and an SH7612 EV chip board as shown in figure 2 1 The emulator station includes a serial interface cable RS 232C and a parallel interface cable conforms to IEEE P1284 and is for the ECP mode for the host computer interface By installing a LAN board option the emulator can be connected to a workstation via the LAN interface By installing a PC interface board option to a PC to be used the emulator can be connected to the PC via the ISA bus LAN board H or HS7000ELNO2H a option Device control board E A HS7612EDD81H Bidirectional parallel interface cable PC interface board PC interface cable 56000 1 option Serial interface cable TUM pr Trace cables
131. 2 EXTAL 36 N C 70 GND 3 XTAL NC 37 GND 71 D22 4 GND 38 CASLH DQMLU 72 D23 WE1N 5 DO 39 CASLL DQMLL 73 GND WEON 6 D1 40 GND 74 D26 7 GND 41 CAST 75 D27 8 D4 42 CASO 76 GND 9 D5 43 GND 77 D30 10 GND 44 REFOUT 78 D31 11 D8 45 BS 79 GND 12 D9 46 GND 80 DACKO 13 GND 47 CS2 81 DACK1 14 D12 48 CS3 82 GND 15 D13 49 GND 83 WAIT 16 GND 50 CAP1 NC 84 RAS 17 D16 51 UVCC 85 GND 18 D17 52 GND 86 CASHH DQMUU WE3N 19 GND 53 N C 87 CASHL DQMUL WE2N 20 D20 54 CKIO 88 GND 21 D21 55 GND 89 CAS3 22 GND 56 D2 90 CAS2 23 D24 57 D3 91 GND 24 D25 58 GND 92 CKE 25 GND 59 D6 93 RD 26 D28 60 D7 94 GND 27 D29 61 GND 95 50 28 GND 62 D10 96 CS1 29 BGR 63 D11 97 GND HITACHI Rev 1 0 09 00 page 419 of 423 Table C 4 Pin Assignment of the HS7612EBK81H User Interface USER I F2 cont Pin No Pin Name Pin No Pin Name Pin Pin Name 30 BRLS 64 GND 98 CS4 31 GND 65 D14 99 RD WR 32 DREQO 66 D15 100 GND 33 DREQ1 67 GND 34 GND 68 D18 Rev 1 0 09 00 page 420 of 423 HITACHI C 3 Precautions for User System Connection When connecting the EV chip board to the user system note the following 1 Secure the E8000 station location Place the E8000 station and EV chip board so that the station to EV chip board interface cable is not bent or twisted as shown in figure C 7 A bent or twisted cable will impose stress on the user interface leading to connection or contact failure Make sure that the emulat
132. 2 I condition satisfaction is added to the previous measured time e BREAK CONDITION sequential break mode Realtime emulation stops only when break conditions set with the BREAK _ CONDITION UBC1 2 command are satisfied in the sequence of the BREAK CONDITION 2 condition followed by the BREAK CONDITION UBCI condition e Timeout break mode A break occurs when the timeout or execution count condition specified with the PERFORMANCE ANALYSIS command is satisfied Rev 1 0 09 00 page 250 of 423 HITACHI GO Table 7 15 Cycle Reset Times Value of n Reset Interval 6 5 us 9 8 us 50 us 100 us 500 us 1 ms 5 ms 10 50 A 100 ms 500 ms N 15 The restrictions for each mode at emulation are listed in table 7 16 Rev 1 0 09 00 page 251 of 423 HITACHI GO Table 7 16 Restrictions for Realtime Emulation Modes Modes Cycle reset mode Restrictions Software breakpoints specified with the BREAK or BREAK_SEQUENCE command are ignored Hardware break conditions specified with the BREAK_CONDITION_A B C or BREAK_CONDITION_UBC command are ignored All conditions specified with the TRACE_CONDITION_A B C command are ignored Parallel mode cannot be entered Break prohibition e Software breakpoints specified with the BREAK or BREAK SEQUENCE mode command are ignored e Hardware br
133. 306 of 423 HITACHI STEP_OVER 7 2 39 STEP_OVER SO Performs single step execution except for subroutines Command Format e Execution STEP OVER lt start address gt I RET lt start address gt Start address of single step execution Default is the current PC address I Interrupt permission during single step execution Description e Execution Beginning at lt start address gt performs single step execution of instructions except for subroutines called by the BSR JSR BSRF or TRAPA instruction If a BSR JSR BSRF or TRAPA instruction is executed acts as if the subroutine called by the BSR JSR BSRF or TRAPA instruction is a single instruction If an instruction other than BSR JSR BSRF or TRAPA is executed register contents and the executed instruction are shown after each instruction is executed like in the STEP command Ifa BSR JSR or BSRF instruction is executed sets a PC break before the instruction following the slot delayed branch instruction for the BSR JSR or BSRF instruction and executes the user program The instruction following the slot delayed branch instruction is not executed During STEP_OVER command execution register contents can be displayed in the following format The register information and memory contents are displayed according to the STEP INFORMATION command specifications Rev 1 0 09 00 page 307 of 423 HITACHI STEP_OVER PC 0000100
134. 4 8 Rev 1 0 09 00 page 165 of 423 HITACHI Adjust the hardware by taking the above into account The basic bus cycle two states and control signal input timing are shown in figures 4 1 and 4 2 respectively The user system interface circuits connected to the user system are shown in figure 4 3 tAD tAD RD Read cycle D31 to DO Read cycle WEn Write cycle D31 to DO Write cycle Figure 4 1 Basic Bus Cycle Rev 1 0 09 00 page 166 of 423 HITACHI 1 tress tin tnmis BREQRH tress teREaRS Figure 4 2 Control Signal Timing HITACHI Rev 1 0 09 00 page 167 of 423 SH7612 CS0 CS4 CASO CAS3 RD WR DQMLL WEO DQMLU WE1 DQMUL WE2 DQMUU WE3 TxD1 TxD2 RxD1 RxD2 SCK1 SCK2 SRxDO SRxD2 SRCKO0 SRCK2 SRSO SRS2 STxDO STxD2 STCKO STCK2 STSO STS2 FTOA FTOB FTCI FTI User system CS0 CS4 CASO CAS3 RD WR DQMLL WEO DQMLU WE1 DQMUL WE2 DQMUU WE3 TxD1 TxD2 RxD1 RxD2 SCK1 SCK2 SRxDO SRxD2 SRCKO0 SRCK2 SRS0 SRS2 STxDO STxD2 STCKO STCK2 STSO STS2 FTOA FTOB FTCI FTI Figure 4 3 User System Interface Circuits Rev 1 0 09 00 page 168 of 423 HITACHI SH7612 User system EPM7128 LVT163373 bd 4 7 kQ LVT16244 EPM7128 L VT16244 x2 LVT16244 Vcc IRLO IRL3 IRLO IRL3 LVT163373 LVT22V10 PLLVCC Not connected PLLVCC CAP2 Not connected 2
135. 4 SRz000000F0 000000000000 IIII00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000FFE00 DSR200000000 1x 2 k 2 e eee e ete ak kk kk COB A0G 200 A0 00000000 MO0 00000000 X0 00000000 YO 00000000 A1G 00 A1200000000 M1 00000000 X1 00000000 Y1 00000000 b lt address gt lt instruction mnemonic gt c MEMORY lt memory contents gt d STACK lt stack contents gt e lt cause of termination gt a Register information b Address and mnemonics of the executed instruction c Memory contents display d Stack contents display e Cause of termination refer to table 7 25 After the STEP_OVER command has been executed so long as it was not forcibly terminated and if no other command has been entered single step execution can be continued by simply pressing the RET key Software breakpoints specified with the BREAK or BREAK_SEQUENCE command and hardware break conditions specified with the BREAK_CONDITION_A B C or BREAK_ CONDITION_UBC1 2 command are invalid during STEP OVER command execution Interrupts are not accepted during STEP_OVER command execution unless the I option is specified Ifa break occurs during subroutine execution the address and instruction mnemonics of the instruc
136. 407 Serial Interface Cable Using Other Cables 407 External Dimensions and Weight of the Emulator Station sss 408 External Dimensions and Weight of the EV Chip 408 Rev 1 0 09 00 page x of xiv HITACHI Figure 1 Figure C 2 Figure C 3 Figure C 4 Figure C 5 Figure C 6 Figure C 7 Figure D 1 Figure E 1 Connection of the HS7612EBH8 1H eese nennen 411 Component Installation Size Restriction sese 411 Connector Installation Location on the User System sees 412 Connection of the HS7612EBKS81H 4 eene eene 413 Component Installation Size Restriction sese 414 Connector Installation Location on the User System sees 414 Examples of Securing the Emulator Station esee 421 Memory at eme eR er REUS NR EDEN EE const 422 eniin Dee ete oen pete 423 Rev 1 0 09 00 page xi of xiv HITACHI Tables PartI E8000 Guide Table 1 1 Table 1 2 Table 1 3 Table 1 4 Table 1 5 Table 2 1 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 3 7 Table 3 8 Table 3 9 Environmental Conditions eese eee nennen nre 7 E8000 Station Components HS8000ESTO2H eene 8 Device Control Board Components essere 8 EV Chip Board Components
137. 76 7 2 30 PERFORMANCE ANALYSISI1 8 1 esee eene 278 7 2 3 QUIT uiii ene ede RON UE in dU DEI 289 13 32 RADIX iini eene Dre bh erede er 290 1 2 33 REGISTER teen ee eet rte Ga AA Oa Er Its 292 1 2 34 iens oe OTRO EIN op on Nn en 293 12 35 RESULT eei E A AA 294 7 22 36 ES PAD US s hee o ede cuss e te edere etes 296 DOT STEP murem nu ESPECIE Bailes BA a 298 7 2 38 SILER INFORMATIONS eret P deg 304 72339 STEPL OVER nins RE POSUERE dM 307 1 2 40 TRACE iiu bus rep RUE quU EURO EDU 311 7 241 TRACE CONDITION A B C oirrese neuehep eem ote Reiter 318 7 2 42 TRACE DISPLAY MODBE itt e etre t he reti qb wana dees Ss 331 7 2 43 TRACE MODE eene e ep OR DDR ir iR EES 334 7 2 44 TRACE SEARCH ee eR EU D eR 337 Section 8 Data Transfer from Host Computer Connected 8 1 8 2 by RS 232C Intet faces 343 OVeEtyIe We so OUO OEC e quen E Oed VERRE 343 Host Computer Related Commands eese eene 344 824 ANTEC LOADS cad oh net ie Ip eben 346 8 22 INTEC SAV Eoen Maeve Pe E qur 348 8 273 INTEC VERIFY needa ava meetin ae ene 350 824 IEOAD inopes quia em beat tiia uds 352 822 5 SAVE ponet Sep Gee Deer m bep Se Ue 354 8 2 6 VERET nat etie eate etit ere rac tus 356 Section 9 Data Transfer from Host Computer Connected 9
138. 8 Bussstate Controllet oen beam 162 3 3 9 System Controller S YSC teet reete ee ENEE Re TER e E 163 Rev 1 0 09 00 page v of xiv HITACHI Section 4 User System Interface oie iiia 165 sections Troubleshooting a a as 173 Sal Internal System Test eec oett ce ie Hen pie eiie ee dente 173 5 2 Troubleshooting Procedure essere ener een nennen 176 Section 6 Command Input and Display see 179 6T Command Syntax cete onte m eU pe EUR ete e Ep ere et 179 6 1 1 Command Input Format seien peter dere Sesen Sepso e aeS 179 6 1 2 Help Function sses on eoe em t iet ete nde eee od 179 6 3 Word Definition eere dp HERO RED Hg Peer ere ehe reitera 180 6 2 Special Key Inp t 5s ete eee e SEO UE UE 181 6 2 1 Command Execution and Termination sese 181 6 2 2 Display Control cag iS Sees Sat ae Gel ates ERES 181 6 23 sCommand Re entry un te E qn PEE EIE aep dons 182 6 2 4 Cursor Control and Character Editing esee 182 Section 7 Emulation Commands onore pretii tede ie dee ertet 183 Tl OVERVIEW emesis 183 7 2 Emulation Commands eee hve PERI RR E ots 185 7 2 geb m eie deo ed x 186 7 2 2 ABORT uuu enum 189 72 3 ALIAS totae aet eec imt duh
139. 9 00 page 396 of 423 HITACHI Table 10 4 Process Code for LAN I O Error Messages Error No Process 01 Initialization 02 TELNET data transfer 03 TELNET close 04 TELNET open 10 FTP connection 20 File transmission 30 File reception 40 FTP disconnection 50 Directory modification 60 Directory display 70 Current directory display 80 File transfer binary specification 90 File transfer ASCII specification AO Forcible termination HITACHI Rev 1 0 09 00 page 397 of 423 10 2 IBM PC Interface Software Error Messages The IBM PC interface software outputs error messages on the IBM PC Table 10 5 lists error messages descriptions of the errors and error solutions Table 10 5 Interface Software Error Messages Error Message INTFC ERROR ABORT BY BREAK Description and Solution File transfer has been forcibly terminated by pressing the BREAK STOP or CTRL C keys INTFC ERROR ALREADY ASSIGNED The specified command is already being executed Re execute the command after command execution has been completed INTFC ERROR EMULATOR NOT READY The debugger power has been turned off or a cable connected to the debugger has been disconnected Check that the debugger power is turned on and that cables are connected correctly and restart If the same error occurs again inform a Hitachi sales agency INTFC ERROR ENVIRONMENT NOT SPECIFIED The specifie
140. ACE_CONDITION_A B command conditions cannot be set to the same channel number For example when conditions have already been set to TRACE CONDITION Al no conditions can be set to BREAK CONDITION AI To set new conditions cancel previously set conditions When conditions have already been set with the CONDITION or PERFORMANCE ANALYSIS command conditions cannot be set to the same channel number For example when conditions have already been set to CONDITION or PERFORMANCE ANALYSISI no conditions can be set to BREAK CONDITION To set new conditions cancel previously set conditions Examples 1 To generate a break when byte data H 10 is accessed at address H F000000 BCA1 A F000000 D 10 RET 2 To generate a break when data is written to address H 1000000 BCA2 A 1000000 W DAT RET 3 To generate a break when reading data in address H 2000000 1 2000000 R RET Rev 1 0 09 00 page 211 of 423 HITACHI BREAK_CONDITION_A B C 4 To display the specified conditions BCA RET 1 A F000000 D 10 BCA2 A 1000000 W DAT BCA3 BCA4 BCA5 BCA6 7 BCA8 5 To cancel the specified conditions 1 RET BCB1 RET Rev 1 0 09 00 page 212 of 423 HITACHI BREAK_CONDITION_UBC 7 2 8 BREAK_CONDITION_UBC BCU Specifies displays and cancels hardware break conditions Command Format e Setting BREA
141. ACE_MODE Specifies and displays trace information Unusable acquisition mode TRACE_SEARCH Searches for and displays trace information Usable Rev 1 0 09 00 page 184 of 423 HITACHI 7 2 Emulation Commands This section provides details of emulation commands in the format shown in figure 7 1 Command Name No Command Name Abbr Function Command Format Function 1 Command input format Function 2 Command input format parameter 1 Parameter description 1 parameter 2 Parameter description 2 Description Function 1 Description of function 1 Function 2 Description of function 2 Notes Examples Command Name Full command name Abbr Abbreviated command name Function Command function Command Format Command input format for each function Description Function and usage in detail Notes Warnings and restrictions for using the command If additional information is not required this item is omitted Examples Command usage examples Figure 7 1 Emulation Command Description Format Symbols used in the command format have the following meanings Parameters enclosed by can be omitted a b One of the parameters enclosed by and separated by that is either a or b must be specified lt gt Contents shown in lt gt are to be specified or displayed The entry specified just before this symbol can be repeated A Indicates a space Used only fo
142. ALYSIS 1 3 5 7 A subroutine name A lt start address range gt A lt end address range gt I3 RET Subroutine execution time measurement mode 3 PERFORMANCE ANALYSIS 1 3 5 7 A subroutine name A lt start address A end address AC accessed area address range gt A lt access type RET Area access count measurement mode PERFORMANCE ANALYSISA 1 3 5 7 A subroutine name A lt start address A end address S C called subroutine address range RET Subroutine call count measurement mode PERFORMANCE ANALYSIS 1 2 3 4 5 6 7 8 A RET PERFORMANCE ANALYSISA I RET PERFORMANCE ANALYSIS A A V RET n Subroutine number lt subroutine name gt Name of the subroutine whose execution performance is to be measured start address gt Subroutine entry address end address gt Subroutine exit address Rev 1 0 09 00 page 278 of 423 HITACHI lt timeout value gt lt specified count gt lt start address range gt lt end address range gt lt accessed area address range gt lt access type gt lt called subroutine address range gt PERFORMANCE_ANALYSIS Timeout value of execution time measurement Can be set for only the PERFORMANCE_ANALYSIS1 command Display format xxx yy zz nnnnnn xxx Hour yy Minute ZZ Second nnnnnn Microsecond Specifiable range 0 to 999 yy 0to 59 77 0to59 nnnnnn 0 to 999999 Execution count limit Can be set
143. B A0G 00 A0 00000000 0 00000000 0 00000000 0 00000000 A1G 00 A1 00000000 1 00000000 1 00000000 1 00000000 00001004 BSR 00002020 Subroutine is not displayed 00001006 NOP SUBROUTINE END RET PC 0000100A SR 000000F0 000000000000 IIII00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 R8 15 00000008 00000009 0000000A 0000000B 00000000 0000000C 00000000 000FFEO00 DSR200000000 k k kkkkkkkk COB A0G 00 A0 00000000 M0 00000000 X0 00000000 0 00000000 A1G 00 A1 00000000 1 00000000 X1 00000000 Y1 00000000 00001008 NOP ONE STEP END Rev 1 0 09 00 page 310 of 423 HITACHI 7 2 40 TRACE T Displays trace information Command Format e Display TRACE A lt start pointer gt lt end pointer gt BP lt display information gt RET lt start pointer gt Start pointer of trace display Default is the PTR option of the TRACE_DISPLAY_MODE command lt end pointer gt End pointer of trace display Default is the PTR option of the TRACE_DISPLAY_MODE command Trace up until the break condition is satisfied is displayed This option is usually necessary except for displaying trace information during delays when a delay count condition is specified by the BREAK_CONDITION_B or TRACE_CONDITION_B
144. C option is specified the following message is displayed to confirm with the user whether to overwrite the existing configuration information in the emulator flash memory CONFIGURATION STORE OK Y N a RET a Y Stores the specifications as configuration information in the emulator flash memory Hereafter when the emulator is activated the saved specifications go into effect N Does not overwrite configuration information The existing specifications are valid Rev 1 0 09 00 page 335 of 423 HITACHI TRACE_MODE e Display Displays the specified trace mode in the following format TRACE MODE RET DMA x REF x OVFB y TIME zzzzz x Enables or disables trace information acquisition for DMA cycles and refresh cycles E Trace information is acquired D No trace information is acquired y A break occurs when the trace buffer overflows 77777 Minimum time stamp unit Table 7 37 Display of Minimum Time Stamp Unit Display Description CLK Acquires trace information on the number of clock cycles Does not acquire trace information on time stamp 20ns 20 nanoseconds 1 6us 1 6 microseconds 52us 52 microseconds Examples 1 To set the minimum time stamp unit to 20 ns TMO TIME 1 RET 2 To display the specified contents TMO RET DMA F OVFB D TIME 20ns Rev 1 0 09 00 page 336 of 423 HITACHI TRACE_SEARCH 7 2 44 TRACE SEARCH TS Search
145. C2 settings are ignored when a stop address is specified with the GO command or during STEP and STEP OVER command execution Executing addresses containing software breakpoints set by the BREAK or BREAK SEQUENCE command invalidates the BREAK CONDITION UBC2 settings Make sure not to set software breakpoints at addresses where the BREAK CONDITION UBC 2 settings are satisfied A slot delayed branch instruction cannot terminate user program execution before a PC break Occurs setting an execution stop condition for a PC break at a slot delayed branch instruction will stop emulation before executing the branch destination instruction The BREAK CONDITION settings are implemented by the SH7612 user break controller Accordingly when the condition that the UBC is used by the user system is specified with the UBC option of the EXECUTION MODE command this command cannot be used Examples 1 To generate a break when byte data H 10 is accessed at address H F000000 BCU1 A F000000 D 10 RET 2 To generate a break when data is written to address H 1000000 BCU2 A 1000000 W DAT RET Rev 1 0 09 00 page 217 of 423 HITACHI BREAK_CONDITION_UBC 3 To display the specified conditions BCU RET BCU1 A F000000 D 10 BCU2 A 1000000 W DAT 4 To cancel the specified conditions BCU1 RET BCU2 RET Rev 1 0 09 00 page 218 of 423 HITACHI BREAK_SEQUENCE 7 2 9 BREAK_SEQUENCE
146. CLOCK CNF CONFIGURATION CV CONVERT DC DATA CHANGE DS DATA SEARCH DA DISASSEMBLE D DUMP E END EM EXECUTION MODE F FILL GO HE HELP HT HISTORY ID ID MP MAP M MEMORY MD MODE MV MOVE MOVE TO RAM PA 1 2 3 4 5 6 7 8 PERFORMANCE ANALYSIS 1 2 3 4 5 6 7 8 Q QUIT RX RADIX R REGISTER RS RESET RT RESULT ST STATUS S STEP SI STEP INFORMATION SO STEP OVER T TRACE TCA 1 2 3 4 5 6 7 8 TRACE CONDITION A 1 2 3 4 5 6 7 8 TCB 1 2 3 4 5 6 7 8 TRACE CONDITION B 1 2 3 4 5 6 7 8 TCC 1 2 3 4 5 6 7 8 TRACE CONDITION C 1 2 3 4 5 6 7 8 TDM TRACE DISPLAY MODE TMO TRACE MODE TS TRACE SEARCH L LOAD SV SAVE V VERIFY L INTFC LOAD IS INTFC SAVE V INTFC VERIFY 5 ASC BIN BIN BYE BYE CD CD CLOSE CLOSE FTP FTP LAN LAN LH LAN HOST E LAN LOAD LSV LAN SAVE LV LAN VERIFY LO LOGOUT 15 LS OPEN OPEN PWD PWD RTR ROUTER 5 STA SN SUBNET Rev 1 0 09 00 page 260 of 423 HITACHI Note Usable in parallel mode No Unusable in parallel mode Available only for display in parallel mode Available when the FTP server is open Displays command format when command name is specified HE command name RET Displays command format Example To display GO command format HE GO RET Executes real tim mulation G lt addr1 gt Xbreakaddr lt mode gt LEV
147. CONDITION or PERFORMANCE ANALYSIS1 no conditions can be set to TRACE CONDITION To set new conditions cancel previously set conditions Examples 1 To specify a trace stop condition TCA1 A 4320 S RET Rev 1 0 09 00 page 329 of 423 HITACHI TRACE_CONDITION_A B C 2 To specify a range trace condition TCA2 A 2000 27FF R RET 3 To specify a subroutine range trace condition TCB1 S 21000 13FF A 2000 27FF SR RET 4 To display specified trace conditions RET 1 A 4320 S TCA2 A 2000 27FF R TCA3 TCA4 5 TCA6 TCA7 TCA8 5 To cancel the trace condition specified with the TRACE CONDITION A3 command TCA3 RET 6 To cancel all trace conditions specified with the TRACE CONDITION A command TCA RET Rev 1 0 09 00 page 330 of 423 HITACHI TRACE_DISPLAY_MODE 7 2 42 TRACE_DISPLAY_MODE TDM Specifies and displays trace information display mode Command Format e Setting TRACE DISPLAY MODEAPTR sstart pointer end pointer JA display item gt D E A display item gt D E C RET e Display TRACE DISPLAY MODE RET start pointer Default start pointer for trace information display and search emulator shipment D 4095 end pointer Default end pointer for trace information display and search emulator shipment D 4095 display item Information to be displayed at trace information
148. CV Converts data Command Format e Conversion CONVERTA lt data gt RET CONVERTA lt expression gt RET lt data gt Data to be converted lt expression gt Addition or subtraction lt data gt lt data gt lt data gt lt data gt Description e Conversion Converts data to hexadecimal decimal octal binary fixed point and ASCII formats Input data is handled as 4 byte values If there is no corresponding ASCII character including undisplayable character a period is displayed instead CONVERT lt data gt RET D xxx Q xxx B xxx xxxx a b c d e X X XXX f a Hexadecimal display b Decimal display c Octal display d Binary display e ASCII display f Fixed point display 7 If the H D Q X radix is not specified for data at data input the radix specified with the RADIX command is assumed Note When an expression includes fixed point values the fixed point values are converted as 4 byte values before the expression is converted Therefore the expression cannot be converted correctly Rev 1 0 09 00 page 228 of 423 HITACHI Examples 1 To convert hexadecimal data H 7F CV H 7F RET H 7F D 127 Q 177 B 1111111 X 0 0000000591 2 To convert the expression CV 31 16 RET H 41 D 65 Q 101 B 1000001 X 0 0000000303 HITACHI CONVERT Rev 1 0 09 00 page 229 of 423 DATA_CHANG
149. D 000063 01000003 44 EXT W DAT 1110 1 1 1 l D 000062 01000022 3344 EXT DAT 1111 1 1 1 1 1111 D 000060 01000040 11223344 EXT W DAT 1111 1 1 1 ICH 2 To search for the last bus cycle where IRLO is low TS IRL B Q L RET BP AB DB RW ST IRL NMI RES BRQ VCC PRB D 000063 01000003 44 EXT W DAT 1110 1 1 1 1 1111 Rev 1 0 09 00 page 342 of 423 HITACHI Section 8 Data Transfer from Host Computer Connected by RS 232C Interface 8 1 Overview When the emulator is connected to a host computer by the RS 232C interface data can be transferred between the host computer and the emulator or between the host computer and memory in the user system connected to the emulator This enables the following transmission of host computer load module files e Loads a load module file in the host computer to user system memory e Saves data in the user system memory as a load module file in the host computer Commands listed in table 8 1 can be used to transfer data between the emulator and host computer Table 8 1 Host Computer Related Commands Usable Unusable Command Function in Parallel Mode INTFC_LOAD Loads program from host computer Unusable Serial interface INTFC_SAVE Saves program in host computer Unusable Serial interface INTFC VERIFY Verifies memory contents against host computer file Unusable Serial interface LOAD Loads program from host computer Unusable
150. E 7 2 14 CHANGE DC Replaces memory data Command Format e Replacement DATA CHANGEA data 1 gt A lt data 2 gt A lt start address gt A end address2 AQ number of bytes gt lt size gt AY RET lt data 1 gt Old data data 2 New data lt start address gt Start address of the memory area to be changed lt end address gt End address of the memory area to be changed lt number of bytes gt The number of bytes in the memory area to be changed lt size gt Length of data B 1 byte W 2 bytes L 4 bytes Default 1 byte Y Specify Y if a confirmation message is not necessary If Y is specified data in all assigned areas is replaced without a confirmation message Description e Replacement Replaces lt data 1 gt in the specified memory area set by the lt start address gt and lt end address gt or the lt number of bytes gt with lt data 2 gt and verifies the results If option Y is specified data is replaced without confirmation messages If option Y is not specified the following message is displayed whenever the data specified by lt data 1 gt is found xxxxxxxx CHANGE Y N y RET XXXXxxxx Address where data 1 gt was found y Y data 1 is replaced with data 2 gt N Datais not replaced continues to search for another occurrence of the specified data To terminate this command before reaching end address gt press the CTRL C keys Rev 1 0 09 00
151. E E specification of the TRACE DISPLAY MODE command Time stamp display is disabled in the default setting n The number of clock cycles required from the end of the previous bus cycle to the end of this bus cycle Up to 255 H FF clocks are counted If the number exceeds 255 it is displayed as The clock cycle cannot be displayed together with the time stamp display m Rev 1 0 09 00 page 315 of 423 HITACHI Note When the display is in bus cycle units the following message is displayed as the emulator cycle following the last bus cycle of user program execution Note that this emulator cycle does not affect user program execution cycles Examples 1 To display all trace information with only instruction mnemonics T RET IP D 000004 D 000003 D 000002 D 000001 D 000000 ADDR 00002010 00002012 00002020 00002022 00002024 JSR OP OV L OP OV L OPERAND RO RO R1 RO R4 2 To display bus cycle information and instruction mnemonic information in bus cycle units from five instructions before the point where a delay count condition was satisfied T 5 B RET BP D 000005 D 000004 x D 000003 D 000002 D 000001 D 000000 AB 00002010 00002012 00002010 00002020 00002022 00002020 00002024 00002024 0F000000 00002028 E8000 DB 400B0009 21020009 E 6403000B 00002020 00090009
152. ELF type S type or HEX type load module LOAD lt offset gt S lt file name RET If an offset is specified a load address is calculated as follows Load address load module address gt offset Rev 1 0 09 00 page 352 of 423 HITACHI LOAD Notes 1 Do not load data to the area other than the internal memory areas and areas CSO to CS4 2 Verification is not performed during load If the program must be verified use the VERIFY command For details refer to section 8 2 6 VERIFY Examples 1 To load SYSROF type load module F11 ABS L F11 ABS RET TOP ADDRESS 00007000 END ADDRESS 00007FFF 2 To load S type load module ST MOT B L S ST MOT RET TOP ADDRESS 00000000 END ADDRESS 00003042 Rev 1 0 09 00 page 353 of 423 HITACHI SAVE 8 2 5 SAVE SV Saves program in host computer Bidirectional parallel interface Command Format e Save SAVEA lt start address gt A lt end address gt A lt number of bytes gt lt load module type gt ALF lt file name gt RET lt start address gt Start memory address lt end address gt End memory address lt number of bytes gt Number of bytes to be saved lt load module type gt Load module type S S type load module H HEX type load module Default S type load module LF Adds an LF code to the end of each record lt file name gt File name in the host computer Descripti
153. ELP Displays all commands 7 2 22 HISTORY Displays the history of the input command 7 2 23 ALIAS Alias function 7 2 8 e Defines aliases ID Displays versions of the system program 7 2 24 ABORT Stops emulation in parallel mode 7 2 2 END Cancels parallel mode 7 2 18 QUIT Quits system program 7 2 31 Rev 1 0 09 00 page 112 of 423 HITACHI Table 1 3 Host Computer Interface Functions Reference Command Type Command Function Section Serial interface INTFC_LOAD Loads program from host computer 8 2 1 INTFC_SAVE Saves program in host computer 8 2 2 INTFC_VERIFY Verifies memory contents against host 8 2 3 computer files Bi directional LOAD Loads program from host computer 8 2 4 parallel interface SAVE Saves program in host computer 8 2 5 VERIFY Verifies memory contents against host 8 2 6 computer files 13 Realtime Emulation The emulator enables realtime emulation with a clock frequency of 66 MHz for the SH7612 with no wait states Realtime emulation consists of the following three modes e Normal mode Executes only emulation e Cycle reset mode Forcibly inputs the RES signal to the SH7612 periodically e Parallel mode Enables the user to display and modify memory and display trace information during user program execution The user can select the mode which best suits the user s debugging needs The following describes each of these modes Rev 1 0 09 00 page 113 of 423 HITACHI 1 3 1 Normal
154. ER T START DIAGNOSTIC TEST S F L T a Emulator monitor start message b Internal RAM and registers are being tested A number from 0 to 3 is displayed as each of the four internal RAM blocks has been tested If an error occurs the address write data and read data are displayed as follows RAM ERROR ADDR xxxxxxxx W DATA xxxxxxxx R DATA xxxxxxxx After RAM testing is completed the registers are tested No data will be displayed if an error does not occur If an error occurs the following message is displayed xxxx REGISTER ERROR W DATA xx R DATA xx xxxx Name of emulator internal register where an error occurs c The emulator monitor is in command input wait state Note Operation continues if an error occurs in step b but the error should be investigated according to section 5 2 Troubleshooting Procedure without loading the emulator system program Rev 1 0 09 00 page 173 of 423 HITACHI Internal System Test at Emulator System Program Initiation The emulator system program performs internal system tests mainly on the emulator registers at its initiation SH7612 E8000 HS7612EDD81SF Vm n Copyright C Hitachi LTD 1997 a Licensed Material of Hitachi Ltd CONFIGURATION FILE LOADING b HARDWARE REGISTER READ WRITE CHECK c FIRMWARE SYSTEM LOADING d EMULATOR FIRMWARE TE
155. ET 0000F000 0 87544 0 875 RET 0000F002 0 45637 0 5 RET 0000F004 0 39285 RET 4 To write data H 10 to address H FEO0 without displaying the memory contents M FEOO 10 RET HITACHI Rev 1 0 09 00 page 271 of 423 MODE 7 2 27 MODE MD Specifies or displays SH7612 operating mode Command Format e Specification MODE C RET e Display MODE RET Description e Specification Interactively specifies the SH7612 operating mode in the emulator as shown below MODE C RET E8000 MODE MD4 0 xx a RET CONFIGURATION STORE OK Y N b RET a Operating mode Input hexadecimal values to specify MD4 to MDO bits b Confirmation message for configuration information storage Y The specified parameters are stored as configuration information in the emulator flash memory N The specified parameters are not stored as configuration information and command execution is terminated If Y is input in b stores the settings as configuration information in the emulator flash memory When the emulator is initiated after configuration information storage it emulates in the stored operating mode The E8000 system program terminates after the SH7612 operating mode is set and must then be re initiated e Display Displays the SH7612 operating mode in the emulator the operating mode selection pin MD4 to MDO status on the user system and the operating mode setting method in the following format
156. Example 2 The following condition is satisfied when address 3000000 is the address condition and bit 0 is zero in the byte data condition BREAK CONDITION UBCI A H 3000000 D B 0 Table 7 12 Mask Specifications BREAK CONDITION UBC1 2 Radix Mask Unit Example Mask Position Allowed Condition Binary 1 bit B 01 1010 Bits O and 5 are masked Address data D WD LD or PC Hexa 4 bits H F 50 Bits 15 to 8 are masked Address data D WD LD decimal or PC e Display Displays specified conditions The character string that was input for specifying conditions will be displayed as it was input If break numbers 1 and 2 are omitted break conditions for both break types are displayed For BREAK CONDITION break conditions satisfaction count after the previous break condition was satisfied is displayed Ifno break condition is specified a blank is displayed BREAK CONDITION UBC RET BCUI UBCI break setting BCU2 UBC2 break setting xxx Satisfaction count after the condition is satisfied Rev 1 0 09 00 page 216 of 423 HITACHI BREAK_CONDITION_UBC Cancellation Cancels specified conditions When break numbers 1 and 2 are omitted all break conditions are cancelled Cancellation of all break conditions BREAK_CONDITION_UBC RET Cancellation of BREAK CONDITION UBC2 break conditions BREAK CONDITION UBC2 RET Notes 1 The BREAK CONDITION UB
157. HI PERFORMANCE_ANALYSIS k Access type of accessed area in area access count measurement mode DAT Execution cycle DMA DMA cycle 1 Called subroutine address range in subroutine call count measurement mode m Total run time Execution time and count displayed as numerical values Option V is specified PERFORMANCE_ANALYSIS V RET NO NAME MODE RATE RUN TIME E COUNT 1 SUBA 12 D 10 0 D 0000H 00M 05S 001000US 250NS D 00005 a b c d e f MAX D 0000H 00M 05S 001000US 250NS MIN D 0000H 00M 05S 001000US 250NS g h AVE _ D 0000H 00M 05S 001000US 250NS D 2 SUBB D 20 0 D 0000H 00M 108 010305U8 500NS D 00010 AVE D 0000H 00M 058 001000US 250NS 3 SUBC I3 D 20 0 D 0000H 00M 108 010305U8 500NS D 00010 AVE D 0000H 00M 058 001000US 250NS 4 5 SUBD AC D 10 0 D 0000H 00M 058 001000US 250NS D 00005 7 SUBE SC D 20 0 D 0000H 00M 108 010305US 500NS D 00010 TOTAL RUN TIME D 0001H 00M 50S 000020US 250NS 0 a Subroutine number b Subroutine name up to 8 characters are displayed c Time measurement mode Subroutine execution time measurement mode 1 I2 Subroutine execution time measurement mode 2 I3 Subroutine execution time measurement mode 3 AC Area access count measurement mode SC Subroutine call count measurement mode d Execution time ratio as a percentage e Execution time Rev 1 0 09 00 page 285 of 423 HITACHI PERFORMANCE_ANALYSIS f Area acce
158. IFY Note Do not verify data in the area other than the internal memory areas and areas CSO to CS4 Example To verify SYSROF type load module F1 ABS against the memory contents IV F1 ABS RET lt ADDR gt lt FILE gt lt MEM gt 00001012 00 Rev 1 0 09 00 page 351 of 423 HITACHI LOAD 8 2 4 LOAD L Loads program from host computer Bidirectional parallel interface Command Format e Load LOAD A lt offset gt lt load module type gt lt file name gt RET lt offset gt Value to be added to the load module address lt load module type gt Load module type R SYSROF type load module S S type load module H HEX type load module M Memory image file E ELF type load module Default SYSROF type load module file name File name in the host computer Description Load Loads a user program from the host computer into user system memory via the bidirectional parallel interface Use interface software IPW for the host computer to transfer the specified file to the emulator via the bidirectional parallel interface Enter Be before the command to request data output to the host computer XB LOAD load module type gt lt file name gt RET When loading is completed the start and end addresses are displayed as follows TOP ADDRESS start address gt END ADDRESS end address An offset value to be added can be specified for the address of an SYSROF type
159. K RET lt clock gt One of the following clock signals E Emulator internal CLOCK signal 16 5 MHz U User system CLOCK signal X Crystal oscillator CLOCK signal 8 to 16 5 MHz Description Setting When clock mode 0 1 2 or 3 is specified as SH7612 clock mounted on the emulator selects emulator clock signals from the user system from crystal oscillator on the EV chip board or from the emulator internal clock installed in the emulator Resets the SH7612 when a clock is selected and consequently internal I O registers and control registers return to their reset values Displays the specified clock signal If the user system clock U is specified but the user system clock signal is not input an error occurs and the emulator internal clock E is set instead when clock mode is 0 1 2 or 3 At emulator initiation the user system clock U crystal oscillator on the EV chip board X and emulator internal clock E are selected in that order and the correct clock signal is set The emulator internal clock signal cannot be selected when clock mode 4 5 or 6 is specified with the MODE command Be sure to input the clock signal from the user system to use the emulator Display Displays the current clock signal CLOCK RET CLOCK used clock used clock EML Emulator internal clock 16 5 MHz USER User system clock X TAL Crystal oscillator clock 8 to 16 5 MHz Rev 1 0 09 00 page 224 of 423
160. K_CONDITION_UBC 1 2 A lt condition gt A lt condition gt A lt condition gt RET Display BREAK CONDITION UBC 1 2 RET e Cancellation BREAK CONDITION UBC 1 2 A RET 1 2 UBC break number When omitted all conditions will be displayed or cancelled lt condition gt Hardware break condition refer to tables 7 10 and 7 11 for details Description e Setting Specifies hardware break conditions BREAK_CONDITION_UBC Program execution stops when the specified conditions are satisfied The specifiable conditions for the two kinds of hardware breaks are summarized in tables 7 10 and 7 11 respectively The BREAK_CONDITION_UBC conditions can also be satisfied in sequential break mode program execution stops only when and 2 settings are satisfied in the sequence of UBC2 break condition followed by UBC1 break condition The sequential break can be specified with the GO command Rev 1 0 09 00 page 213 of 423 HITACHI BREAK_CONDITION_UBC Table 7 10 Specifiable Conditions BREAK_CONDITION_UBC1 Item and Input Format Address condition A lt address gt PC lt address gt P XA X bus address gt YA lt Y bus address gt Description The condition is satisfied when the address bus value matches the specified value When is selected the address bus in data access or program fetch cycles is specified and when is selected the address bus in program fetch cycl
161. L C keys or the BREAK key stops program execution Rev 1 0 09 00 page 129 of 423 HITACHI 1 5 Realtime Trace Function The emulator can trace SH7612 external bus information during realtime emulation without affecting the user system The emulator can fetch external bus information of the SH7612 address or data and the external probe value up to 131 070 bus cycles Trace information is referenced with the TRACE command Display of this information enables a check on executed program Trace information e Address bus 28 bits PC value 32 bits e Data bus physical address 32 bits e External probe One e Number of bus cycle clocks 9 8 bits a maximum of 255 kbytes e Trace of memory contents 32 bits internal 32 bits Emulator displays trace information in the following methods e Displays the trace information as mnemonic in bus cycle units e Searches for the specified information and displays it Use the TRACE SEARCH command 1 5 1 Trace Timing Trace information is acquired in trace memory synchronized with rising edges in the T3 cycles of the CLK signal Note Because external probe signal input is not synchronized with the CLK signal it may not be possible to log all the changes in the external probe signal In each bus cycle the clock number is the number of clock CLK cycles between the end of the previous bus cycle and the end of the current bus cycle Figure 1 15 shows an example of the external probe si
162. MANCE_ANALYSIS 2 To display addresses of the set subroutines PA A RET NO NAME 1 SUBA 2 SUB P B 3 SUBC 5 SUBI ACCI 7 SUB CAL MODE TX T2 T3 AC ESS SC L SUB ADDRE SS 00000100 00001FF0 COUNT D 00000 00005000 00007FF0 00010000 0001008F 00020000 00020098 00002030 0000207F FFFFFFO00 FFFFFF7F DAT 00020100 0002FFFF 00030000 00030060 TOTAL RUN TIME D 0001H 00M 40S 022917US 000NS 3 To display execution time ratio in graph form PA RET NO NAME MODE 1 SUBA 11 2 SUBB I2 3 SUBC I3 4 5 SUBD AC ACCESS 7 SUBE 5 lt CALL SUB gt TOTAL RUN TIME D 15 0 D 20 0001 0 10 20 30 40 50 60 70 80 90 100 KKKKK KKKKKKKKKK KKKKKKKKKK KKKKKKKK KKK KKKKKKKKKK KKK 00M 40S 022917US 000NS Rev 1 0 09 00 page 287 of 423 HITACHI PERFORMANCE_ANALYSIS 4 To display execution time and count in numerical form PA V RET NO NAME 1 SUBA AVE 2 SUBH MAX AVE 3 SUBC AVE 5 SUBD 7 SUBE MODE RATE RUN TIME Il D 10 0 D 0000H 00M D 0000H 00M 05S 001000US 250NS I2 D 20 0 D 0000H 00M D 0000H 00M 10S 010305US 250NS D 0000H 00M 10S 010305US 250NS I3 D 20 0 D 0000H 00M D 0000H 00M 10S 010305US 250NS AC D 10 0 D 0000H 00M SC D 20 0 D 0000H 00M MIN 056 5106 055 105 105 E COUNT 001000US 250NS D 00005
163. MEMORY S 4MB Rev 1 0 09 00 page 83 of 423 HITACHI 3 8 2 Automatic Initiation of E8000 System Program If S4 in DIP SW1 has been turned on to the left and the automatic system program load method is selected the E8000 system program is automatically loaded and initiated and the emulator waits for an emulation command Display at Power On Power on E8000 MONITOR HS8000ESTO2SR Vm n Copyright C Hitachi Ltd 1995 Licensed Material of Hitachi Ltd TESTING RAM 0123 SH7612 E8000 HS7612EDD81SF Vm n Copyright C Hitachi Ltd 1997 Licensed Material of Hitachi Ltd CONFIGURATION FILE LOADING HARDWARE REGISTER READ WRITE CHECK FIRMWARE SYSTEM LOADING EMULATOR FIRMWARE TEST RESET BY E8000 CLOCK EML MCU TYPE SH7612 MODE 00 MD4 0 1F REMAINING EMULATION MEMORY S 4MB If the E8000 system program is automatically initiated without being loaded to the emulator flash memory after displaying an error message the emulator enters monitor command input wait state Make sure to load the E8000 system program to the emulator flash memory before initiation E8000 SYSTEM PROGRAM NOT FOUND START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ Rev 1 0 09 00 page 84 of 423 HITACHI Section 4 Operating Examples 4 1 Emulator Operating Examples This section covers explanations on how to operate the emulator using examples Sections 4 2 Basic Exampl
164. MI 4 11 75 PB8 SRS1 CTS 8 CKPREQ CKM 42 A10 76 PB9 SRCK1 RTS 9 CKPACK 43 GND 77 PB10 STXDO TXD1 10 IVECF 44 A7 78 PB11 STSO RXD1 11 GND 45 A6 79 GND 12 FTOA PA4 46 GND 80 NC 13 FTI PA5 47 81 24 14 FTCI PA6 48 A2 82 GND 15 WDTOVF PA7 49 GND 83 A21 16 GND 50 CAP2 NC 84 A20 17 TMS PA12 51 MD3 85 GND 18 TCK PA13 52 MD4 86 A17 19 NC 53 GND 87 A16 20 TRST 54 GND 88 GND 21 GND 55 TRLO 89 A13 22 PB4 STXD1 TIOCB1 56 90 12 TCLKC 23 PB5 STS1 TIOCA1 57 TRL2 91 GND 24 PB6 STCK1 TIOCB2 58 IRL3 92 AQ TCLKD 25 PB7 SRXD TIOCA2 59 GND 93 A8 26 GND 60 TXD PAO 94 GND 27 PB12 STCKO SCK1 61 RXD PA1 95 A5 HITACHI Rev 1 0 09 00 page 417 of 423 Table C 3 Pin Assignment of the HS7612EBK81H User Interface USER I F1 cont Pin No Pin Name Pin No Pin Name Pin No Pin Name 28 PB13 SRXDO TXD2 62 SCK PA2 96 A4 29 PB14 SRSO RXD2 63 FTOB CKPO 97 GND 30 PB15 SRCKO SCK2 64 GND 98 A1 31 GND 65 PA8 STXD2 99 AO 32 A23 66 PAS STS2 100 GND 33 A22 67 TDO PA10 34 GND 68 TDI PA11 Note Connect to the ground of the user system When this pin is connected to the ground the emulator regards that the emulator is connected to the user system Rev 1 0 09 00 page 418 of 423 HITACHI Table C 4 Pin Assignment of the HS7612EBK81H User Interface USER I F2 Pin No Pin Name Pin No Pin Name Pin No Pin Name GND 35 CAS OE 69 D19
165. MNEMONIC OPERAND lt address gt lt machine code gt lt mnemonic gt lt operand gt If end address gt or number of instructions is omitted 16 instructions are disassembled and displayed If there is no applicable instruction DATA W xxxx is displayed If start address is an odd address DATA B xx is displayed Immediately after executing this command except when it is forcibly terminated by the CTRL C keys or BREAK key or by an error pressing the RET key will disassemble and display the next 16 lines of data Disassemble can be performed only in areas CSO to CS4 or the internal memory areas Rev 1 0 09 00 page 234 of 423 HITACHI DISASSEMBLE Examples 1 To disassemble and display six instructions starting from address H 1000 DA 1000 6 RET ADDR CODE MNEMONIC OPERAND 00001000 E000 MOV 00 R0 00001002 2100 MOV B RO R1 00001004 2201 RO R2 00001006 430B JSR R3 00001008 0009 NOP 0000100 3400 CMP EQ RO R4 2 To disassemble and display 16 instructions starting from address H 1000 and to disassemble and display furthermore 16 instructions by only entering RET DA 1000 RET ADDR CODE NEMONIC OPERAND 00001000 1F01 OV L RO 4 R15 00001002 6673 OV R7 R6 00001004 E001 OV 1 0 00001006 3708 SUB RO R7 00001008 1F52 OV L R5 8 R15 0000100A 1F43 OV L RA Q C R15 0000
166. NDITION B command are satisfied e To continue program execution and output a pulse when the hardware break condition set by the BREAK CONDITION command is satisfied EXECUTION MODE TRGB 1 RET e To continue program execution and output a pulse when any hardware break condition set by the BREAK CONDITION B command is satisfied EXECUTION MODE TRGB A RET e To terminate program execution and not output a pulse when hardware break conditions are satisfied EXECUTION MODE TRGB D RET Rev 1 0 09 00 page 243 of 423 HITACHI EXECUTION_MODE Specifies time interval for execution status display during GO command execution e To not display PC EXECUTION_MODE MON 0 RET e To display PC every 200 ms EXECUTION MODE MON I RET e To display PC every 2 s EXECUTION MODE MON 2 RET Enables or disables user wait e To disable user wait EXECUTION_MODE WAIT D RET e To enable user wait EXECUTION MODE WAIT E RET Enables or disables the cache access trace disable the cache access trace EXECUTION MODE CT D RET To enable the cache access trace EXECUTION MODE CT E RET Enables or disables the multi break function e To disable the multi break function EXECUTION MODE MB D RET e To enable the multi break function EXECUTION MODE MB E RET Enables or disables UBC use by the user program e To disable UBC use by the user progra
167. Notes 1 Only the BREAK_CONDITION_B7 can be specified for the delay count specification 2 Orepresents specifiable item Rev 1 0 09 00 page 119 of 423 HITACHI Address Bus Value A break occurs when the SH7612 address bus value matches the specified condition Break condition When the address bus value is 1204 Specification A 1204 User program Break iE Break occurs when the b instruction is condition MOV L R1 R2 fetched is satisfied Figure 1 5 Break with Address Bus Value Data Bus Value A break occurs when the SH7612 data bus value matches the specified condition The emulator checks both program fetch and data access for the condition The data size must be selected from longword access LD word access WD or byte access D Break condition When the data bus value is 12 Specification D 12 User program Break ad Break occurs when the condition __ MOV 12 R1 E 12 is fetched is satisfied MOV R1 R2 Figure 1 6 Break with Data Bus Value Rev 1 0 09 00 page 120 of 423 HITACHI Read Write Condition A break occurs when the SH7612 s RD and RDWR signal levels match the specified conditions Usually the read write condition is specified together with the address or data conditions Break condition When writing 01 to address H F000000 Specification A F000000 W User program NOP Break MOV 01 Break occurs when 01 condition p MOV B R1 R2 is
168. O2H ip PRO Device control board A HS7612EDD81H Bidirectional parallel interface cable HS7612EBK81H PC interface board PC interface cable option 2 HS6000EII01H E Serial interface cable option ___ a Trace cables EV chip board Y HS7612EBH81H 8000 station HS8000ESTO2H m External probe User system trigger output pins Figure 1 1 Emulator for the SH7612 The emulator provides the following features e Realtime emulation of the SH7612 at 66 MHz e A wide selection of emulation commands promoting efficient system development e On line help functions to facilitate command usage without a manual e Efficient debugging enabled by variable break functions and a mass storage trace memory 128 kcycles e Command execution during emulation for example Trace data display Emulation memory display and modification e Measurement of subroutine execution time and count for evaluating the execution efficiency of user programs e 4 Mbyte standard emulation memory for use as a substitute user system memory Rev 1 0 09 00 page 4 of 423 HITACHI An optional LAN board for interfacing with workstations enabling high speed downloading 1 Mbyte min of user programs The LAN board contains Ethernet LOBASES and Cheapernet 10BASE2 interfaces SH7612 Integration Manager option can be loaded into the workstation to enable Graphic display operations in a multi window
169. OAD An offset value to be added can be specified for the address of an SYSROF type ELF type S type or HEX type load module LAN LOAD offset S file name gt RET If an offset is specified a load address is calculated as follows Notes Load address load module address offset 1 Do not load data to the area other than the internal memory areas and areas CSO to CS4 2 Verification is not performed during load If the program must be verified use the LAN VERIFY command For details refer to section 9 3 11 LAN VERIFY 3 Before loading an SYSROF type load module the file type must be changed to binary code with the BIN command At emulator initiation binary code is selected as the default However if is selected with the ASC command change the file type to binary code with the BIN command before loading For details refer to section 9 3 2 BIN Example To load an SYSROF type load module enter the following command line F11 ABS indicates the host computer file name Before entering the LAN LOAD command connect the emulator to the host computer with the FTP command FTP HOST1 RET TOP ADDR ESS END ADDRI EPS ESS Username USER1 RET Password RET login command success FTP gt LL F11 ABS RET LOADING ADDRESS 00007000 00007000 00007FFF HITACHI Rev 1 0 09 00 page 375 of 423 LAN SAVE 9 3 10 LAN SAVE LSV Saves
170. OFF Setting at shipment LAN OFF ON PC interface board ON ON Notes 1 Switches S1 S2 S3 S5 and S6 of SW1 are not used Use these switches with the off state Console interface settings must be performed before the E8000 station power is turned on 2 If the settings of the console interface S7 and S8 of SW1 are incorrect the initiation of the E8000 station cannot be confirmed on the screen After turning off the E8000 station power correct the interface settings See section 3 5 Power On Procedure for Emulator 3 The console interface includes an RS 232C interface and a bidirectional parallel interface 3 3 1 PC Interface Board Specifications Table 3 2 lists the PC interface board specifications Table 3 2 Interface Board Specifications Item Specifications Available host computer ISA bus specification PC or compatible machine System bus ISA bus specification Memory area 16 kbytes Memory area setting Can be set at every 16 kbytes in the range from H C0000 to H EFFFF with a switch Rev 1 0 09 00 page 38 of 423 HITACHI 3 3 2 Switch Settings of the PC Interface Board Memory area Setting The PC interface board uses a 16 kbyte memory area on the PC The memory area to be used must be allocated to the memory area on the PC with a switch on the PC interface board Any 16 kbytes in the range of H C0000 to H EFFFF can be allocated figure 3 10 Addresses to be allocated must not overlap the memory address
171. PB12 STCKO SCK1 162 FTI PA5 107 VCC11 135 PB11 STSO RXD1 163 FTOA PA4 108 AQ 136 PB10 STXDO TXD1 164 FTOB CKPO 109 GND11 137 PB9 SRCK1 RTS 165 SCK PA2 110 A10 138 VCC15 166 VCC18 111 VCC12 139 PB8 SRS1 CTS 167 RXD PA1 112 A11 140 GND15 168 GND18 113 GND12 141 PB7 SRXD1 TIOCA2 169 TXD PAO 114 12 142 PB6 STCK1 TIOCB2 170 IVECF TCLKD 115 A13 143 PB5 STS1 TIOCA1 171 CTPACK 116 14 144 PB4 STXD1 TIOCB1 172 CKPREQ CKM TCLKC 117 VCC13 145 PB3 SRCK2 TIOCAO 173 IRL3 118 A15 146 PB2 SRS2 TIOCBO 174 IRL2 119 GND13 147 PB1 SRXD2 TIOCCO 175 TCLKA 120 16 148 PBO STCK2 TIOCDO 176 TRLO TCLKB 121 17 149 TRST Notes 1 Pay attention to board design so that mode change is enabled with this pin during debugging with the E10 emulator E10 series 2 Connect to the ground of the user system When this pin is connected to the ground the emulator regards that the emulator is connected to the user system Rev 1 0 09 00 page 416 of 423 HITACHI Tables C 3 and 4 list the pin assignment of the 100 pin connector for the HS7612EBK8 1H Table C 3 Pin Assignment of the HS7612EBK81H User Interface USER I F1 Pin No Pin Name Pin No Pin Name Pin No Pin Name 1 NC 35 A19 69 GND 2 MDO 36 A18 70 PBO STCK2 TIOCDO TCLKB 3 MD1 37 GND 71 PB1 SRXD2 TIOCCO TCLKA 4 MD2 38 A15 72 PB2 SRS2 TIOCBO 5 RES 39 A14 73 PB3 SRCK2 TIOCAO 6 GND 40 GND 74 GND 7 N
172. PR GBR VBR MACH MACL RS RE and MOD information is displayed No control register PC SR PR GBR VBR MACH MACL RS RE and MOD information is displayed General register RO to R15 information is displayed No general register RO to R15 information is displayed DSP register DSR A0 AOG Al A1G MO MI XO X1 YO and Y1 information is displayed No DSP register DSR AO AOG Al MO XO YO and Y1 information is displayed f Memory address range displayed with the STEP command g SP xxxxxxxx Display size of stack contents h CLOCK xxxx Clock signal type EML Emulator internal clock USER User system clock XTAL Crystal oscillator clock i EML_MEM S xMB Remaining size of standard emulation memory Example xMB Remaining size of standard emulation memory To display the emulator status ST RET MODE 2 RADIX HEX BREAK D 001 HOST 38N1X STEP_INFO REG 12 A 3 SP CLOCK EML EML MEM S 4MB Rev 1 0 09 00 page 297 of 423 HITACHI STEP 7 2 37 STEP S Command Format Performs single step execution e Single step STEP A number of execution steps gt A lt start address gt number of execution steps start address stop PC display option Rev 1 0 09 00 page 298 of 423 lt stop PC A display option gt AI RET Number of steps to be e
173. PW Interface software IPW can also be terminated by pressing Alt F keys and then the X key figure 3 22 Note that in the following conditions a termination request is ignored and interface software IPW will not be terminated File transfer between the emulator and host computer Automatic command input from a file Pile Es NTERFACE HS8000EIWOTSF V1 1 opyright C Hitachi Ltd 1996 pos Material of Hitachi Ltd Figure 3 22 Exit Menu Note Set communication setting and screen setting in the Setting menu immediately after IPW initiation because they are not saved at IPW termination Rev 1 0 09 00 page 54 of 423 HITACHI 3 4 3 Debugging Support Functions Interface software IPW supports the following two debugging functions e Automatic command input from a host computer file e Logging acquisition The start of automatic command input or start and end of logging acquisition can be specified when the emulator is in command input wait state the emulator prompt is or Automatic Command Input The file from which commands are to be input command file is specified with lt and lt file name gt when the emulator is in command input wait state Do not insert a space between lt and lt file name gt Example lt FILENAME RET Commands are sequentially read from the specified command file and transferred to the emulator As in the following example when the command file is specified commands in that fi
174. R 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000FFE00 DSR200000000 k kkkkkkkk COB A0G 00 A0 00000000 0 00000000 x0 00000000 Y0 00000000 A1G 00 A1 00000000 M1 00000000 1 00000000 1 00000000 Rev 1 0 09 00 page 292 of 423 HITACHI RESET 7 2 34 RESET RS Resets SH7612 Command Format e Reset RESET RET Description e Reset Resets the SH7612 The SH7612 system register control register general register and DSP register contents will be reset to the following values RO to R14 The value before reset VBR H 00000000 R15 SP Power on reset vector value GBR The value before reset MACH The value before reset MACL The value before reset PC Power on reset vector value SR H 000000F0 PR The value before reset RS RE The value before reset MOD The value before reset DSR H 00000000 The value before reset AO Al MO M1 X0 X1 YO Y1 The value before reset The internal I O register contents will also be reset Note In the SH7612 the initial value of the registers must be set in the program because the register contents are not stable after the SH7612 is reset Example To reset the SH7612 RS RET RESET BY E8000 Rev 1
175. RACE STOP is displayed Rev 1 0 09 00 page 319 of 423 HITACHI TRACE_CONDITION_A B C Table 7 30 Specifiable Conditions in Each Trace Mode Command No Subroutine Trace Range Trace TCA1 Subroutine Range Trace X Trace Stop TCA2 TCA3 TCA4 TCA5 TCA6 TCA7 TCA8 TCB1 TCB2 TCB3 TCB4 TCB5 TCB6 TCB7 TCB8 TCC1 TCC2 TCC3 TCC4 TCC5 TCC6 TCC7 x x TCC8 Oil O Oi O O O O O Oi O Ol Ol Oi Oi Ol OI OI O O O O O O O All 16 24 Note O Condition can be specified X Condition cannot be specified Rev 1 0 09 00 page 320 of 423 HITACHI x x x x x x x x o o xl o x o x x x x x x x AR TRACE_CONDITION_A B C When conditions for subroutine trace range trace or subroutine range trace are specified together the trace acquisition conditions for each mode are ORed If no conditions are specified for these modes free trace is assumed When the specified trace stop condition is satisfied trace information acquisition stops and the emulator enters parallel mode and waits for command input To resume trace information acquisition exit parallel mode with the END command Inrange trace or trace stop mode the items shown
176. RAM will be LOST Notes 1 For more details on the HS7612EBKS1H refer to the user s manual supplied with the EV chip board 2 This EV chip board can only be used in combination with the specified connector FX2 100P 1 27SVL manufactured by Hirose Electric Co Ltd Mount the specific connector FX2 100P 1 27S VL manufactured by Hirose Electric Co Ltd on the user system to connect the emulator Figure C 4 shows the connection of the HS7612EBK81H figure C 5 shows the size restriction for the installed components of the HS7612EBK81H and figure C 6 shows the connector installation location on the user system HS7410PWB20H HS7420PWB50H USER IF1 A USER IF2 Connector FX2 100P 1 27SVL Hirose Electric Co Ltd User system Figure C 4 Connection of the HS7612EBK81H Rev 1 0 09 00 page 413 of 423 HITACHI EV chip board HS7612EBK81H User system socket FX2 100P 1 27SVL User system board Hirose Electric Co Ltd Unit mm Figure C 5 Component Installation Size Restriction N Connector center line Unit mm External frame of Tolerance 0 1 the EV chip board Figure C 6 Connector Installation Location on the User System Rev 1 0 09 00 page 414 of 423 HITACHI C 2 User Interface Pin Assignment Table C 2 lists the pin assignment of the 176 pin QFP IC socket for the HS7612EBH81H Table C 2 Pin Assignment of the HS7612EBH81H
177. RSONAL INJURY The USER PROGRAM will be LOST This section describes how to set the host computer interface when the emulator is connected to a host computer The host computer connector marked SERIAL is located on the E8000 station s rear panel Connecting this connector to a host computer via the RS 232C interface cable enables data transfer between the emulator and the host computer Table 3 4 lists the host computer interface specifications The system program can be loaded to the E8000 station memory with the bidirectional parallel interface At this time confirm that the printer driver is specified by the PC settings Use a host computer to which the bidirectional parallel interface can be applied See section 3 7 System Program Installation Table 3 4 Host Computer Interface Specifications Specifications Signal level RS 232C High 5 to 15 V Low 5to 15V Transfer rate 2400 4800 9600 19200 38400 bits per second BPS Synchronization method Asynchronous method Start bit length 1 bit Data bit length 7 8 bits Stop bit length 1 2 bits Parity Even odd or none Control method X ON X OFF control RTS CTS control Host Computer Interface Settings at Emulator Start Up When the emulator is turned on or when the emulator system program is initiated the host computer interface settings are determined by the console interface switches in the same way as in the console interface the control method wil
178. RW ST IRL NMI RES BREQ VCC PRB TIME and CLK E Display is enabled D Display is disabled Note TIME and CLK cannot be set as E display enabled at the same time Table 7 36 shows the default of each trace item display at emulator shipment Table 7 36 Shipment Defaults of TRACE DISPLAY MODE Command Trace Items Default at Shipment A D MA RW ST IRL NMI RES BREQ VCC and PRB E TIME and CLK D When the C option is specified the following message is displayed to confirm with the user whether to overwrite the existing configuration information in the emulator flash memory TRACE DISPLAY MODE C RET CONFIGURATION STORE OK Y N a RET a Y Stores the specifications as configuration information in the emulator flash memory Hereafter when the emulator is activated the saved specifications go into effect N Does not overwrite configuration information The existing specifications are valid Rev 1 0 09 00 page 332 of 423 HITACHI TRACE_DISPLAY_MODE e Display Displays the specified trace mode as shown below TRACE DISPLAY MODE RET PTR D yyyyyy D yyyyyy DISPLAY ITEM zzzz zzzz yyyyyy Default values of start and end bus cycle pointers for trace information display and search 7777 Information to be displayed at trace information display A D MA RW ST IRL NMI RES BREQ VCC PRB TIME and CLK Examples 1 To set the default values of the pointers
179. Reference Command Type Command Function Section Single step STEP Executes one step at atime and displays the 7 2 37 execution STEP_OVER following 7 2 39 STEP_ 7 2 38 INFORMATION e Instruction mnemonic e Memory contents e Register contents Displays the above data for a specified routine until a specified address is reached The above operations are performed for a specified number of steps or until a specified address is reached Specifies information to be displayed during single step execution Executes subroutine as a single step Memory access MEMORY Displays or modifies memory contents 7 2 26 DUMP e Displays or modifies memory contents in Tad 1 2 or 4 byte units e DUMP displays fixed points of memory contents MAP Specifies memory attributes in a 1 Mbyte unit 7 2 25 e User memory e Write protected e Emulation memory Standard 4 Mbytes FILL Writes data in specified pattern 7 2 20 DATA_SEARCH Searches for and replaces data in specified 7 2 15 DATA CHANGE pattern 7 2 14 Rev 1 0 09 00 page 110 of 423 HITACHI Table 1 2 Emulation Functions cont Reference Command Type Command Function Section Clock selection CLOCK e Selects emulator internal clock EML 7 2 11 15 MHz e Selects user system clock 1 to 33 MHz e Selects crystal oscillator of EV chip board 8to 16 5 MHz Register access REGISTER Displays and modifies SH7612 register 7 2 33 contents Line assembly ASSEMBLE Assembles instruction
180. Rev 1 0 09 00 page 318 of 423 HITACHI TRACE_CONDITION_A B C Description Setting Specifies a trace acquisition condition trace mode for user program emulation GO command execution Trace condition numbers are automatically set to trace conditions in their specified order The specified trace acquisition condition trace mode will apply for trace acquisition following this command execution Free Trace Acquires trace information during all bus cycles if no conditions have been set with this command Subroutine Trace Acquires trace information such as instructions and operands in the range subroutine specified by lt start address gt and lt end address gt However note that if the specified subroutine calls another subroutine trace information on the called subroutine is not acquired Range Trace Acquires trace information during bus cycles in which the specified condition is satisfied Subroutine Range Trace Accesses instructions and operands in the subroutine specified by lt start address gt and lt end address gt and acquires trace information during bus cycles in which the specified condition is satisfied Trace Stop Stops trace information acquisition when the specified condition is satisfied and enters command input wait state in parallel mode Though realtime emulation continues trace information acquisition is not possible in parallel mode If a trace stop condition is satisfied T
181. ST e RESET BY E8000 f CLOCK EML f MPU TYPE SH7612 g MODE xx MD4 0 xx h FAILED AT xxxx i REMAINING EMULATION MEMORY S 4MB 0 E a Emulator system program start message Vm nn indicates the version number b Configuration file is being loaded If an invalid configuration file is assigned the following message is displayed 54 IINVALID CONFIGURATION FILE If no configuration file is contained in the memory the following message is displayed 55 CONFIGURATION FILE NOT FOUND Re install the configuration file c The emulator control registers are being checked If an error occurs one of the following messages is displayed xxx REGISTER ERROR W DATA xxxx R DATA xxxx SHARED RAM ERROR ADDR xxxxxx W DATA R DATA xxxxxxxx BxTBM ERROR ADDR xxxxxx W DATA R DATA xxxxxxxx FIRM RAM ERROR ADDR W DATA R DATA xxxxxxxx An error occurred in the register xxx Name of emulator internal register where an error occurs BOTRAR ECT BOCNR BOMDCNR BOMASCR BOCECR BIMDCNR BIMASCR BICECR MAPRO MAPRI MAPR2 MAPR3 Gi An error occurred in the shared RAM ii An error occurred in the trace buffer memory iv error occurred in the firm RAM area Rev 1 0 09 00 page 174 of 423 HITACHI ii iii iv d e The device control board is being tested If an error occurs the following message is
182. START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ S F L T F RET FM FM SL RET SELECT LOAD No 1 PC or 2 WS 1 RET SELECT INTERFACE 1 RS 232C or 2 PARALLEL 2 RET LOAD E8000 SYSTEM FILE OK Y N Y RET INPUT COMMAND B A E8000 SYS RET COMPLETED Rev 1 0 09 00 page 77 of 423 HITACHI Operations 8 Enter Y RET to allow configuration file SHCNF761 SYS to be loaded Then enter the parallel transfer command to load SHCNF761 SYS in the current directory on the PC to the emulator flash memory Enter Y RET to allow firmware file SHDCT761 SYS to be loaded Then enter the parallel transfer command to load SHDCT761 SYS in the current directory on the PC to the emulator flash memory 10 Enter N RET not to load the ITRON debugger 11 Enter N RET not to load the diagnostic program 12 Enter DIR RET to check whether the necessary files have been loaded 13 Enter Q RET to terminate the flash memory management tool 14 Installation is completed Rev 1 0 09 00 page 78 of 423 Display Message LOAD CONFIGURATION FILE OK Y N Y RET INPUT COMMAND B A SHCNF761 SYS RET COMPLETED LOAD FIRMWARE FILE OK Y N Y RET INPUT COMMAND B A SHDCT761 SYS RET COMPLETED LOAD ITRON DEBUGGER FILE OK Y N N RET LOAD DIAGNOSTIC FILE OK Y N N RET FM gt DIR RET FILE ID STATUS
183. STEP command 2 Software breakpoints specified with the BREAK or BREAK SEQUENCE command ignored during single step execution Rev 1 0 09 00 page 301 of 423 HITACHI STEP 3 If a delayed branch instruction is executed during single step emulation single step execution stops after the instruction immediately following the delayed branch instruction is executed Therefore two instruction mnemonics are displayed 4 If break conditions specified with the BREAK_CONDITION_A B C or BREAK_CONDITION_UBC command are satisfied STEP execution may terminate without executing a single instruction 5 If the condition that the UBC use is enabled is specified with the UBC option of the EXECUTION_MODE command the STEP command cannot be used If this is attempted the following error message is displayed and STEP command execution is terminated 8 UBC IS USED BY USER SYSTEM Examples 1 To execute a program one step at a time starting from the address given by the current PC S RET PC 00001002 SR 000000F0 000000000000 IIII00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000 DSR 00000000 FARK RRR KK eek ERK A0G 00 0 00000000 0 00000000 X0 00000000 0 00000000 A1G 00 1
184. Searches for lt data gt from the start address to the end address or for the specified lt number of bytes gt All addresses where lt data gt is found are displayed If data is not found the following message is displayed 45 NOT FOUND Ifthe option is specified data other than the specified data is searched for Search with this command can be performed only in areas CSO to CS4 or the internal memory areas Rev 1 0 09 00 page 232 of 423 HITACHI DATA_SEARCH Examples 1 To search for 1 byte data H 20 in the address range from H FB80 to H FF7F DS 20 H FB80 H FF7F RET 0000FBFB 0000FCCD 2 search for data other than 2 byte data H O in H 100 bytes starting from address H 1000 DS 0 1000 9100 WN RET 45 NOT FOUND Rev 1 0 09 00 page 233 of 423 HITACHI DISASSEMBLE 7 2 16 DISASSEMBLE DA Disassembles and displays memory contents Command Format e Display DISASSEMBLEA lt cstart address gt A lt end address gt A lt number of instructions gt RET lt start address gt Start address of disassembly lt end address gt End address of disassembly lt number of instructions gt The number of instructions to be disassembled Description e Display Disassembles the specified memory contents and displays addresses machine codes mnemonics and operands in the following format As many lines as necessary are used for the display ADDR CODE
185. System Program Installations nennen nennen nein nee 75 3 7 1 E8000 System Disk eee eee 75 382 Installation ioco ere iere rp UU qe 76 3 8 E8000 System Program Initiation eeeeeeeeeeeeeneeeeenen nennen 83 3 8 1 Initiation on Emulator Monitor 83 3 8 2 Automatic Initiation of E8000 System Program esee 84 Section 4 Operating 85 4 Emulator Operating Examples sss nennen eene enne 85 42 Basic Examples seien ene opa ORO DOR I ERE ERREUR 86 4 2 1 Preparing for Connection of the LAN Host Computer sse 86 4 2 2 Specifying the SH7612 Operating Mode sese 88 4 2 3 Allocating Standard Emulation Memory and Specifying Attributes 89 4 2 4 Loading the User Program more e ees 90 4 25 Executng the Prograin ciet eR el eh eee es 91 4 2 6 Setting a Software Breakpoint sess nennen 93 4 2 71 Single Step secet te eeepc 94 4 2 8 Setting Hardware Break Conditions sese 95 4 29 Displaying Trace Information essent 96 43 Application Examples eco nte Get reti e e etri er eec eet 98 4 3 1 Break with Pass Count Condition sesenta 98 4 3 2 Conditional 99 4 3 3 Parallel MOd 4 iet eti ete e Ree
186. TION_A B C Table 7 6 Item and Input Format External interrupt condition 1 NMI L or NMI H Specifiable Conditions BREAK CONDITION 1 8 cont Description The condition is satisfied when the NMI signal matches the specified level NMI or NMI L The condition is satisfied when NMI is low NMI H The condition is satisfied when NMI is high External interrupt condition 2 IRL lt value gt The condition is satisfied when all of the IRL signals match the specified values Specify lt value gt as 1 byte data Each bit corresponds to an IRL number as follows 3 2 1 0 lt Bit x X lt Specified value 1 0 lt 0 Low level 1 High level x x 3 2 IRL number The condition can be masked Satisfaction count specification COUNT lt value gt value H 1 to H FFFF The condition can be specified in combination with any of the address data read write access type external probe and external interrupt conditions The complete condition combination is satisfied when the other specified condition has been satisfied for the specified number of times Delay count specification DELAY lt value gt value H 1 to H 7FFF Rev 1 0 09 00 page 206 of 423 This condition can be specified in combination with any of the address data read write access type external probe and external interrupt conditions The complete condition combination is satisfied when the specified number o
187. TY Hitachi warrants its emulator products to be manufactured in accordance with published specifications and free from defects in material and or workmanship Hitachi at its option will repair or replace any emulator products returned intact to the factory transportation charges prepaid which Hitachi upon inspection determine to be defective in material and or workmanship The foregoing shall constitute the sole remedy for any breach of Hitachi s warranty See the Hitachi warranty booklet for details on the warranty period This warranty extends only to you the original Purchaser It is not transferable to anyone who subsequently purchases the emulator product from you Hitachi is not liable for any claim made by a third party or made by you for a third party DISCLAIMER HITACHI MAKES NO WARRANTIES EITHER EXPRESS OR IMPLIED ORAL OR WRITTEN EXCEPT AS PROVIDED HEREIN INCLUDING WITHOUT LIMITATION THEREOF WARRANTIES AS TO MARKETABILITY MERCHANTABILITY FITNESS FOR ANY PARTICULAR PURPOSE OR USE OR AGAINST INFRINGEMENT OF ANY PATENT IN NO EVENT SHALL HITACHI BE LIABLE FOR ANY DIRECT INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY NATURE OR LOSSES OR EXPENSES RESULTING FROM ANY DEFECTIVE EMULATOR PRODUCT THE USE OF ANY EMULATOR PRODUCT OR ITS DOCUMENTATION EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES EXCEPT AS EXPRESSLY STATED OTHERWISE IN THIS WARRANTY THIS EMULATOR PRODUCT IS SOLD AS IS AND YOU MUST ASSUME ALL RISK FOR THE
188. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 24 N S AS 10 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise
189. UPT command An interrupt is acceptable while the emulator is waiting for command input 3 3 3 Control Input Signals RES WAIT BREQ The SH7612 control input signals are RES WAIT and BREQ The RES WAIT and BREQ signals are valid during execution with either the GO command or STEP command Therefore while the emulator is waiting for command input the user cannot input RES WAIT or BREQ signals to the SH7612 The BREQ signals will not be input to the SH7612 during user program execution when the BREQ signal is masked that is the option BREQ D is specified using the EXECUTION_MODE command Rev 1 0 09 00 page 161 of 423 HITACHI 3 3 4 Serial Communication Interface The serial communication interface signals are connected to the user system directly from the SH7612 on the emulator pod Therefore like the 16 bit FRT the interface is valid during the command input wait state as well as emulation For example when writing data to the Transmit Data Register SCTDR and clearing the Transmit Data Empty TDRE of the Status Register SCSSR after the serial communication interface output has been prepared data is output to the TxD pin 3 3 5 16 Bit Free Running Timer FRT The 16 bit FRT operates during the command input wait state as well as during emulation Even after the user program has stopped when a break condition is satisfied after the user program has been started with a GO command the 16 bit FRT continues to operate Ther
190. XX 09 XXXXXX XXX XXX XXX XXX Example To display all of the defined host computer names and IP addresses LH RET NO HOST NAME IP ADDRESS HOST NAME IP ADDRESS gt 01 HOSTI 128 1 1 1 02 HOST2 128 1 1 4 03 HOSTX 128 1 1 8 04 05 06 07 08 09 Rev 1 0 09 00 page 373 of 423 HITACHI LAN LOAD 9 3 9 LAN LOAD LL Loads a load module file from the host computer to memory via the FTP interface Command Format e Load LAN LOAD A lt offset gt lt load module type gt lt file name gt RET lt offset gt Value to be added to the load module address lt load module type gt Load module type R SYSROF type load module S S type load module H HEX type load module M Memory image file E ELF type load module Default SYSROF type load module file name gt File name in the host computer Description Load Loads a load module file from the host computer to memory via the FTP interface Before executing this command the emulator must be connected to the host computer with the FTP command For details refer to section 9 3 6 FTP The current load address is displayed as follows LOADING ADDRESS xxxxxxxx XXXxxxxx Current load address continuously updated When loading is completed the start and end addresses are displayed as follows TOP ADDRESS start address END ADDRESS end address Rev 1 0 09 00 page 374 of 423 HITACHI LAN L
191. XXXXXX PC 01001012 SR 000000F0 000000000000 GBR 00000000 VBR 00000000 MACH 00000000 MACL RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 00000000 00000000 00000000 00 R8 15 00000000 00000000 00000000 00000000 00 DSR200000000 k k kkkkkkkk COB A0G 00 0 00000000 0 00000000 0 00000000 Y A1G 00 1 00000000 M1 00000000 1 00000000 Y RUN TIME D 0000H 00M 03S 000034US 750NS BREAK KEY HITACHI Operations Display Message 6 Enter DISASSEMBLE 1001000 DISASSEMBLE 1001000 100101F RET 100101F RET to confirm that the program has been changed by memory modification in parallel mode ADDR CODE MNEMONIC OPERAND 01001000 E00A MOV 0A RO 01001002 E101 MOV 01 R1 01001004 E201 MOV 01 R2 01001006 D405 MOV L 0100101C R4 01001008 6323 MOV R2 R3 0100100A 321C ADD R1 R2 01001000C 2426 MOV L R2 R4 0100100E 6133 MOV 01001010 ADD FF RO 01001012 8800 CMP EQ 00 RO 01001014 8BF8 BF 01001008 01001016 0009 NOP 01001018 AFFD BRA 01001016 Changed 0100101A 0009 NOP 0100101C 0 10 DATA W 0101 0100101E 0000 DATA W 0000 Rev 1 0 09 00 page 101 of 423 HITACHI 4 3 4 Searching Trace Information A particular part of the acquired trace information can be searched for using the TRACE SEARCH command as follows Operations Enter TRACE_SEARCH A 1001018 RET to display the parts of trace information in which the address bus value is H 1001018 BP AB DB D
192. a different network to the emulator A maximum of ten routing information can be defined Enter the number to be defined and then the IP address and the network number of the router FM RTR RET NO ENTRY DATA PLEASE SELECT NO 1 10 L E Q X 1 RET 01 IP ADDRESS router IP address RET 01 NET ID network number RET Enter E RET and terminate the RTR command to enable the input contents and save the settings in the emulator PLEASE SELECT NO 1 10 L E Q X E RET LAN CONFIGURATION FILE WRITE OK Y N Y RET FM Enter Q RET to terminate the flash memory management tool FM Q RET Store the host name and IP address of the host computer in the emulator To transfer data between the host computer and emulator initiate the FTP server to connect the host computer to the emulator Before the FTP server is initiated the host name and IP address of the host computer must be stored in the emulator flash memory The following describes how to specify the host name and IP address When the F command flash memory management tool initiation is entered while the emulator waits for an emulator monitor command the emulator displays prompt FM and waits for a flash memory management tool command refer to table 3 9 START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T F RET FM Rev 1 0 09 00 page 59 of 423 HITACHI Next enter the LH command
193. a in memory in the following format Before executing this command connect the emulator to the host computer with the FTP command FTP gt LAN_VERIFY lt load module type gt lt file name gt RET Ifa verification error occurs the address and its contents are displayed as follows lt ADDR gt lt FILE gt lt MEM gt XXXXXXXX yy y ZZ Z XXXXXXXX Verification error address y Load module data in hexadecimal and ASCII characters zz z Memory data in hexadecimal and ASCII characters An offset value to be added or subtracted can be specified for the address of an SYSROF type ELF type S type or HEX type load module FTP gt LAN_VERIFY lt offset gt S lt file gt RET If an offset is specified a verification address is calculated as follows Verification address lt load module address gt lt offset gt Rev 1 0 09 00 page 378 of 423 HITACHI Notes LAN_VERIFY 1 Do not verify data in the area other than the internal memory areas and areas CSO to CS4 2 Before verifying an SYSROF type load module the file type must be changed to binary code with the BIN command At emulator initiation binary code is selected as the default However if ASCII is selected with the ASC command change the file type to binary code with the BIN command before verifying For details refer to section 9 3 2 BIN Example To verify SYSROF type load module file F11 ABS in the host compute
194. able 3 which connects the emulator to the EV chip board 2 Station to EV chip board interface connector CN2 For trace cable 2 which connects the emulator to the EV chip board 3 Station to EV chip board interface connector CN1 For trace cable 1 which connects the emulator to the EV chip board 4 Crystal oscillator terminals For installing a crystal oscillator to be used as an external clock source for the SH7612 5 User system connector For connecting the user system 6 Board connector For connecting HS7410PWB20H and HS7410PWB30H 7 HS7410PWB20H Includes connectors for interfacing with the E8000 station 8 HS7420PWB30H or HS7420PWB50H 2 Includes connectors QFP 176 for interfacing with the user system Rev 1 0 09 00 page 16 of 423 HITACHI Notes 1 For the EV chip board there are a QFP176 IC socket type HS7612EBH81H and a two 100 pin connector type HS7612EBK81H which can be selected in accordance with the user application 2 The HS7420PWB50H has a connector 2 x 100 pin to be connected to the user system Rev 1 0 09 00 page 17 of 423 HITACHI 2 2 Emulator Software Components The emulator s software components are illustrated in figure 2 6 The device control board contains a 3 5 inch floppy disk The system disk files are described in table 2 1 2 8000 E8000 system program Loadable file types S type files HEX type files SYSROF type files Interface software C compiler Cross
195. able 7 3 Causes of BACKGROUND INTERRUPT Command Termination Message Termination Cause ILLEGAL INSTRUCTION An illegal instruction was executed RESET BY E8000 The emulator terminates program execution with the RESET signal because an error has occurred in the user system LOOP PROGRAM ADDRESS The executing address of the loop program for accepting user IS NOT IN RAM interrupts is not in the RAM area therefore the loop program cannot be executed STOPPED IN INTERRUPT A break occurred during the user interrupt processing PROCESS Notes 1 In command input wait state BRA or NOP instruction instruction code H AFFE0009 is set to the address of the loop program for accepting user interrupts and executed Note the following Do not specify the address of the loop program for accepting user interrupts in the ROM area If the specified address is in the ROM area the loop program cannot be executed Specify an address within the RAM area and enable user interrupts select option E again Specify the address of the loop program for accepting user interrupts within an area that is not used by the user program The loop program requires a 4 byte area When the address of the loop program for accepting user interrupts is specified the memory contents before this specification are not stored Therefore the contents of the loop program address is a BRA instruction even after user interrupts are disabled or after the l
196. ad module address offset Note Do not verify data in the area other than the internal memory areas and areas CSO to CS4 Example To verify SYSROF type load module F1 ABS against the memory contents V Fl1 ABS RET lt ADDR gt lt FILE gt lt MEM gt 00001012 Sq OO Rev 1 0 09 00 page 357 of 423 HITACHI Rev 1 0 09 00 page 358 of 423 HITACHI Section 9 Data Transfer from Host Computer Connected by LAN Interface 91 Overview The optional LAN board supports the FTP client function This function enables the following data transfer between the emulator and the host computer connected via the LAN interface e Loads a load module file in the host computer to user system memory e Saves data in the user system memory as a load module file in the host computer e Transfers files between the emulator and host computer The emulator supports the LAN commands listed in table 9 1 to transfer data between the emulator and the host computer These commands are explained in section 9 3 LAN Commands Rev 1 0 09 00 page 359 of 423 HITACHI Table 9 1 LAN Commands Usable Unusable Command Function in Parallel Mode ASC Specifies the file type to be transferred as ASCII Usable BIN Specifies the file type to be transferred as binary Usable BYE Terminates the FTP interface Usable Re connects the FTP interface with the FTP command CD Changes the directory of the FTP server Usable CLOSE Disconnects th
197. ak address is specified Rev 1 0 09 00 page 257 of 423 HITACHI GO Examples 1 To reset the SH7612 and start emulation from the reset vector PC address G RESET RET PC 00001130 2 To start emulation from address H 1000 and stop emulation just before address H 2020 is executed G 1000 2020 RET 3 To start emulation from the current PC address in sequential break mode BREAK CONDITION UBC G SB RET PC 00004250 4 To start emulation from the current PC address and modify memory contents in parallel mode G RET PC 00010204 FEFO RET 0000FEF0 FE FF RET OOOOFEF1 FF RET END RET PC 00011456 Rev 1 0 09 00 page 258 of 423 HITACHI HELP 7 2 22 HELP HE Displays all commands and command format Command Format e Display HELP RET All commands are displayed HELP A lt command gt RET Command format is displayed Description e Display Displays all emulator command names and abbreviations Rev 1 0 09 00 page 259 of 423 HITACHI HELP HE RET lt REGISTER gt AB ABORT ALI ALIAS A ASSEMBLE BI BACKGROUND INTERRUPT BREAK BCA 1 2 3 4 5 6 7 8 BREAK CONDITION A 1 2 3 4 5 6 7 8 BCB 1 2 3 4 5 6 7 8 BREAK CONDITION B 1 2 3 4 5 6 7 8 BCC 1 2 3 4 5 6 7 8 BREAK CONDITION C 1 2 3 4 5 6 7 8 BCU 1 2 BREAK CONDITION UBC 1 2 BS BREAK SEQUENCE CH CHECK CL
198. ak conditions and software break conditions are invalid To stop emulation press the CTRL C keys or the BREAK key Trigger Signal Output Timing in Cycle Reset Mode In cycle reset mode the RES signal is output to the SH7612 regardless of the SH7612 operating status when the time specified by the command has elapsed Figure 1 2 shows the timing in which the TRIG signal is output to the trigger output probe in cycle reset mode Time specified by the command e 1 1 TRIG I 3 25 us Figure 1 2 Trigger Signal Output Timing Rev 1 0 09 00 page 115 of 423 HITACHI 1 3 3 Parallel Mode Parallel Mode Function In parallel mode the emulator can display and modify memory or display trace information during realtime emulation However during memory contents display or modification realtime emulation cannot be performed Parallel Mode Specification Parallel mode can be activated during GO command realtime emulation by any of the following methods as shown in figure 1 3 e Press the RET key e Press the space key e Satisfy a trace stop condition specified by the TRACE_CONDITION_A B C command If any of the above occurs the emulator will display a prompt and enter parallel mode command input wait state Emulation however continues without interruption Input the END E command to return to the normal mode Input the ABORT AB command to stop user program execution in th
199. al probe and external interrupt conditions The complete condition combination is satisfied when the other specified condition has been satisfied for the specified number of times This condition can only be specified for trace stop Delay count specification DELAY lt value gt value H 1 to H 7FFF Rev 1 0 09 00 page 324 of 423 This condition can be specified in combination with any of the address data read write access type external probe and external interrupt conditions The complete condition combination is satisfied when the specified number of bus cycles has been executed after the other specified condition is satisfied This condition can only be specified for trace stop This condition can only be specified with the TRACE _ CONDITION_B7 command HITACHI TRACE_CONDITION_A B C Table 7 33 Specifiable Conditions TRACE CONDITION C Item and Input Format Description Address condition When only address 1 is specified the condition is satisfied A lt address 1 gt lt address 2 gt when the address bus value matches the specified value When both lt address 1 gt and lt address 2 gt are specified the condition is satisfied when the address bus value is in the range from lt address 1 gt to lt address 2 gt This condition can be masked Access type DAT Execution cycle The condition is satisfied when the bus cycle type matches the specified type Multiple access
200. alled the EV chip board The EV chip board should be connected directly to the user system 1 2 Specification The main features of the emulator are its emulation functions and its host computer interface functions as listed in tables 1 2 and 1 3 respectively Rev 1 0 09 00 page 105 of 423 HITACHI Table 1 2 Emulation Functions Command Type Command Reference Function Section Realtime GO Performs realtime emulation in the following 7 2 21 emulation cases The operating frequency is 66 MHz at max e Executes until a hardware or software break condition is satisfied or until the CTRL C or BREAK key is pressed e Cycle reset mode Executes while the RES signal is sent to the SH7612 at fixed intervals This mode is effective to observe waveforms after reset e Parallel mode Displays trace data and modifies memory contents during emulation EXECUTION_ Specifies execution mode 7 2 19 MODE Break condition BREAK Sets hardware break conditions 1 7 2 8 setting e Normal break Execution is forcibly Rev 1 0 09 00 page 106 of 423 stopped when the specified conditions are satisfied a maximum of two points Address bus value or data bus value X Y memory bus PC program counter value Read write condition Delay Count Pass count specification only for BREAK_CONDITION_UBC1 e Mask specification for address and data conditions Bit by bit specification is enabled for
201. ancels parallel mode When GO command execution is terminated by the ABORT command in parallel mode BREAK KEY is displayed as the termination cause Example To terminate GO command emulation in parallel mode G RESET RET PC 00001022 RET To enter parallel mode AB RET PC 00005C60 SR 000000F0 000000000000 ITIIO0 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000FFEO00 DSR200000000 k kkkkkkkkk COB A0G 00 A0 00000000 0 00000000 0 00000000 0 00000000 1 00 A1 00000000 M1 00000000 X1 00000000 1 00000000 RUN TIME D 000H 00M 03S 000409US 120NS BREAK KEY Rev 1 0 09 00 page 189 of 423 HITACHI ALIAS 7 2 3 ALIAS ALI Sets displays and cancels aliases Command Format e Setting ALIASA lt alias name gt A lt alias definition RET e Display ALIAS RET e Cancellation ALIAS A A alias name gt RET ALIAS A RET alias name gt Alias definition name alias definition Alias definition contents Description e Setting Sets aliases for commands Up to 40 aliases can be set An alias name is defined with up to 16 characters and an alias definition with up to 230 characters ALIAS A alias name gt A alias definition RET e
202. ancels trace condition 7 2 41 Traces data only when a condition is satisfied Address bus value NOT condition Read write condition Access type e Stops trace when a trace stop condition is satisfied Address bus value or data bus value Read write condition Access type External probe value System control signals NOT condition Delay count e Subroutine trace HITACHI Table 1 2 Emulation Functions cont Reference Command Type Command Function Section Trace data TRACE _ e Low pulse is output from the trigger output 7 2 41 ae and ee terminal when conditions are satisfied i t t isplay conl eon Address bus value or data bus value Read write condition Access type External probe value System control signals NOT condition Delay count TRACE Searches for trace data 7 2 44 SEARCH TRACE MODE Specifies and displays trace information 7 2 48 acquisition mode Performance PERFORMANCE A maximum of eight measurement modules 7 2 30 _ANALYSIS1 Time intervals 20 ns 6 hours 406 ns 124 to 8 hours and 1 6 s 488 hours A maximum of 65 535 execution count measurements e Subroutine measurement Subroutine execution count Access count to specified area in the subroutine Access count from a subroutine parent to another subroutine child Rev 1 0 09 00 page 109 of 423 HITACHI Table 1 2 Emulation Functions cont
203. and RESET BY E8000 The emulator forcibly terminates program execution with the RESET signal because an error has occurred in the user system STOP ADDRESS Emulation stopped at the break address specified with the GO command SUBROUTINE TIMEOUT The timeout condition specified with the PERFORMANCE_ANALYSIS1 command was satisfied Rev 1 0 09 00 page 255 of 423 HITACHI GO Table 7 17 Causes of GO Command Termination cont Message Cause of Termination SUBROUTINE COUNT The execution count limit specified with the OVERFLOW PERFORMANCE_ANALYSIS1 command was exceeded TRACE BUFFER The trace buffer overflowed OVERFLOW MULTI BREAK Emulation stopped by the multi break During user program execution the SH7612 execution status is displayed Displayed contents are shown in table 7 18 This status is monitored at time intervals specified with the MON option of the EXECUTION_MODE command and if there is a difference from the previous status the status is displayed Table 7 18 Execution Status Display Display BACK Meaning BACK signal is low PC XXXXXXXX During user program execution the program fetch address is displayed according to the time intervals specified with the MON option in the EXECUTION MODE command RESET RESET signal is low The SH7612 has been reset RUNNING User program execution has started This message is displayed once when GO comm
204. and execution starts or when parallel mode is cancelled Note that this message will be deleted when second message in this table is displayed TOUT A XXXxxxxx XXxxxxxx Address bus value Bus cycle stops for 80 us or more The address bus value is displayed Note that this message is also displayed when the SH7612 enters sleep or standby mode and bus cycle stops for 80 ps or more VCC DOWN User system Vcc power voltage is 2 65 V or less The SH7612 is not operating correctly Displayed only when the user clock is selected WAIT XXXXXXXX Address bus value WAIT signal is low The address bus value is displayed The address bus value is not displayed during refresh cycles BREQ BREQ signal is low PACK Clock pause signal is low Rev 1 0 09 00 page 256 of 423 HITACHI GO Ifthe TB option is specified user program execution stops when the timeout value or execution count limit specified with the PERFORMANCE_ANALYSIS1 command is exceeded Notes 1 When a hardware break condition set by the BREAK_CONDITION_A B C command is satisfied during program execution the program does not terminate until at least one of the instructions that have been already fetched is executed If another hardware break is satisfied before the user program terminates several termination causes will be displayed For further details s
205. and the following message is displayed FM gt LH RET NO lt HOSTNAME gt lt IPADDRESS gt NO lt HOSTNAME gt IP ADDRESS gt 01 XXXXXX XXX XXX XXX XXX 02 XXXXXX XXX XXX XXX XXX 03 XXXXXX XXX XXX XXX XXX 04 XXXXXX XXX XXX XXX XXX 05 XXXXXX XXX XXX XXX XXX 06 XXXXXX XXX XXX XXX XXX 07 XXXXXX XXX XXX XXX XXX 08 XXXXXX XXX XXX XXX XXX 09 XXXXXX XXX XXX XXX XXX E8000 IP ADDRESS PLEASE SELECT NO 1 9 L E Q X Up to nine pairs of host names and IP addresses can be specified Input a number from 1 to 9 The emulator prompts the host name Enter a name with up to 15 characters After that the emulator prompts the IP address PLEASE SELECT NO 1 9 L E Q X 1 RET 01 HOST NAME xxxxxx name of host computer RET 01 IP ADDRESS xxx xxx xxx xxx IP address of host computer RET After the IP address has been specified the emulator will prompt for another selection number When connecting more than one host computer continue specifying the host names and IP addresses To confirm the specifications enter L RET as follows PLEASE SELECT NO 1 9 L E Q X L RET NO HOSTNAME lt IPADDRESS gt NO lt HOSTNAME gt IP ADDRESS gt 01 XXXXXX XXX XXX XXX XXX 02 XXXXXX XXX XXX XXX XXX 03 XXXXXX XXX XXX XXX XXX 04 XXXXXX XXX XXX XXX XXX 05 XXXXXX XXX XXX XXX XXX 06 XXXXXX XXX XXX XXX XXX 07 XXXXXX XXX XXX XXX XXX 08 XXXXXX XXX XXX XXX XXX 09 XXXXXX XXX XXX XXX XXX E8000 IP ADDRESS
206. ash memory management tool command LH Turn off the E8000 station 10 Turn off to the right S7 and turn on to the left S8 in SW1 on the E8000 station rear panel i 11 Power on the E8000 station Execute the TELNET command on the host computer for connection to the emulator Initiation messages are displayed Internal system test is executed Test result OK 14 Emulator monitor command input wait state 14 Error message is displayed Figure 3 23 Power On Procedures for LAN Interface Rev 1 0 09 00 page 57 of 423 HITACHI The following describes the power on procedures when using the LAN interface 1 Check that S7 and S8 in console interface switch SW1 on the E8000 station rear panel are turned off to the right 2 Run interface software IPW EXE on the host computer connected to the emulator via the RS 232C interface 3 Turn on the power switch at the E8000 station rear panel 4 The emulator waits for an emulator monitor command 5 Specify the emulator IP address The optional LAN board supports the TCP IP protocol When the host computer is connected to the emulator via the LAN interface the IP address internet address of the emulator must be specified with emulator monitor command L Press L and then the RET key The set IP address is displayed Make sure the IP address is correct The 32 bit IP addr
207. at is either a or b must be specified Contents shown in lt gt are to be specified or displayed The entry specified just before this symbol can be repeated Indicates a space Used only for command format description Pressing the RET key Although italic and bold characters are used throughout this manual to indicate input it is not used in the command format parts of these descriptions Rev 1 0 09 00 page 345 of 423 HITACHI INTFC_LOAD 8 2 1 INTFC LOAD IL Loads program from host computer Serial interface Command Format e Load INTFC_LOAD A lt offset gt lt load module type gt lt file name gt RET lt offset gt Value to be added to the load module address lt load module type gt Load module type R SYSROF type load module S S type load module H HEX type load module M Memory image file E ELF type load module Default SYSROF type load module file name File name in the host computer Description Load Loads a user program from the host computer into user system memory via the serial interface Use interface software IPW for the host computer INTFC LOADYJ load module type gt lt file name gt RET When loading is completed the start and end addresses are displayed as follows TOP ADDRESS start address END ADDRESS end address gt An offset value to be added can be specified for the address of an SYSROF type ELF type S type or HEX type load modul
208. be connected via TELNET or the RS 232C interface Rev 1 0 09 00 page 360 of 423 HITACHI 9 2 LAN Data Transfer 9 2 1 Setting the Data Transfer Environment The optional LAN board enables data transfer between the emulator and host computer via the FTP interface The transfer environment must be specified before starting data transfer as follows Note that the optional LAN board supports the FTP client function only Procedure 1 Specify the host computer environment including the host computer name and IP address to the network database of the host computer For details refer to the appropriate host computer s User s Manual 2 Specify the following emulator environment a Emulator IP address Specify the emulator IP address with the emulator monitor command L Since the emulator IP address is written to the emulator flash memory it needs not to be written each time the LAN interface is used The emulator IP address can be modified as required b Host computer IP address host computer connected via FTP interface With the emulator monitor flash memory management tool command LH specify the name and IP address of the host computer to be connected to the emulator via the FTP interface when initiating the E8000 system program Since the specified host name and IP address are written to the emulator flash memory they need not to be written each time the LAN interface is used The host computer name and IP address can be mod
209. because the modified data is read as undefined Rev 1 0 09 00 page 269 of 423 HITACHI MEMORY Table 7 19 MEMORY Command Options Option Description B Modification in 1 byte units W Modification in 2 byte units L Modification in 4 byte units XW Modification in 16 bit fixed point units XL Modification in 32 bit fixed point units Odd address modification in 1 byte units E Even address modification in 1 byte units Display of previous address contents Display of current address contents Command termination Default Display of next address contents When specifying lt address gt and lt data gt memory contents are modified immediately and the emulator waits for the next command input MEMORY H FFF0 H F8 RET Examples 1 To modify memory contents from address H 1000 M 1000 RET 00001000 00 FF RET 00001001 01 10 RET 00001002 22 RET 00001003 00 30 W RET 00001004 0000 2 1234 RET 00001006 1100 RET 00001004 1234 L RET 00001004 12341100 12345678 RET 00001008 00000000 RET Rev 1 0 09 00 page 270 of 423 HITACHI MEMORY 2 To modify memory contents from address H 8000 in 2 byte units without verification 8000 W RET 00008000 0000 FF RET 00008002 0002 1000 RET 00008004 FFF2 RET 3 To modify memory contents from address H F000 in 16 bit fixed point units M F000 XW R
210. can begin at any register RO to R14 R15 SP PC SR PR GBR VBR MACH MACL RS RE MOD AO Al MO XO YO DSR Rev 1 0 09 00 page 186 of 423 HITACHI lt register gt Display format for modifying registers in interactive mode is as follows register RET register yyyyyyyy RET register yyyyyyyy RET yyyyyyyy data Inputs the value to be newly set Terminates the command i Displays the previous register Only RET Does not modify the register displays the following one To display all register contents use the REGISTER command Note Registers are set as follows at emulator initiation RO to R14 H 00000000 VBR H 00000000 R15 SP Power on reset vector value GBR H 00000000 MACH H 00000000 MACL H 00000000 PC Power on reset vector value SR H 000000F0 PR H 00000000 RS RE H 00000000 MOD H 00000000 DSR H 00000000 H 00 AO Al MO YO H 00000000 If the SH7612 is reset by the emulator RESET or CLOCK command registers are set as follows RO to R14 The value before reset VBR H 00000000 R15 SP Power on reset vector value GBR The value before reset MACH The value before reset MACL The value before reset PC Power on reset vector value SR H 000000F0 PR The value before reset RS RE The value before reset MOD The value before reset DSR
211. cessed in one bus cycle Only longword data LD and a multiple of four can be specified as data and address conditions respectively e Word access Word data is accessed in one bus cycle Only word data WD and a multiple of two can be specified as the data and address conditions respectively e Byte access Byte data is accessed in one bus cycle Only byte data D can be specified as the data condition Both even and odd addresses can be specified as the address condition b Access to a 16 bit bus area e Longword access Longword data is accessed in two word access cycles Only word data WD and a multiple of two can be specified as the data and address conditions respectively e Word access Word data is accessed in one bus cycle Only word data WD and a multiple of two can be specified as the data and address conditions respectively e Byte access Byte data is accessed in one bus cycle Only byte data D can be specified as the data condition Both even and odd address values can be specified as the address condition c Access to an 8 bit bus area All addresses can be accessed in byte units Longword data and word data are accessed in four byte access cycles and two byte access cycles respectively Both even and odd addresses can be specified as the address condition Note however that only byte data D is valid for the data condition Rev 1 0 09 00 page 340 of 423 HITACHI TRACE_SEARCH A bit ma
212. cket NQPACK176SD manufactured by TOKYO ELETECH CORPORATION on the user system to connect the emulator Pin assignment is the same as for the actual SH7612 chip Refer to the Pin Assignment in the SH7612 Hardware Manual Figure C 1 shows the connection of the HS7612EBH81H figure C 2 shows the size restriction for the installed components of the HS7612EBH81H and figure C 3 shows the connector installation location on the user system Rev 1 0 09 00 page 410 of 423 HITACHI HS7410PWB20H HS7420PWB30H The four corners of HS7420PWB30H and the QFP connection part must be fixed with screws 1 1 1 1 I 1 x User system EV chip board HS7612EBH81H User system socket User system board NQPACK176SD TOKYO ELETECH CORPORATION Unit mm Figure C 2 Component Installation Size Restriction Rev 1 0 09 00 page 411 of 423 HITACHI Pin 1 mark External frame of the EV chip board A Center line of the IC socket E Pattern inhibition area Unit mm Figure C 3 Connector Installation Location on the User System Rev 1 0 09 00 page 412 of 423 HITACHI C 1 2 Connection Using the HS7612EBK81H AN WARNING Always switch OFF the emulator and user system before connecting or disconnecting any CABLES Failure to do so will result in a FIRE HAZARD and will damage the user system or emulator or result in PERSONAL INJURY Also the USER PROG
213. computer file Bidirectional parallel interface Command Format e Verification VERIFY A lt offset gt lt load module type gt lt file name gt RET lt offset gt Value to be added to the address lt load module type gt Load module type R SYSROF type load module S S type load module H HEX type load module M Memory image file E ELF type load module Default SYSROF type load module lt file name gt File name in the host computer Description e Verification Verifies data transferred from the host computer against data in memory via the bidirectional parallel interface Use interface software IPW for the host computer Enter BA before the command to request data output to the host computer XB VERIFY load module type gt lt file name RET Ifa verification error occurs all errors will be displayed in the following format lt ADDR gt lt FILE gt lt MEM gt NI XXXXXXXX yy y 77 7 XXXXXXXx Verification error address y Load module data in hexadecimal and ASCII characters zz z Memory data in hexadecimal and ASCH characters Rev 1 0 09 00 page 356 of 423 HITACHI VERIFY An offset value to be added or subtracted can be specified for the address of an SYSROF type ELF type S type or HEX type load module B VERIFY offset S lt file name RET If an offset is specified a verification address is calculated as follows Verification address lo
214. configuration number comment S RET Table 7 14 Saved Configuration Information Item Description Software breakpoints Information set by the BREAK and BREAK SEQUENCE commands Hardware break conditions Information set by the BREAK CONDITION A B C and BREAK CONDITION UBC commands Trace conditions Information set by the TRACE CONDITION A B C TRACE DISPLAY MODE and TRACE MODE commands Performance analysis data Information set by the PERFORMANCE ANALYSIS command Memory map Information set by the MAP command Emulation operating mode Information set by the EXECUTION MODE command Aliases Information set by the ALIAS command Background interrupt data Information set by the BACKGROUND INTERRUPT command Rev 1 0 09 00 page 226 of 423 HITACHI CONFIGURATION e Restoration Restores the configuration information saved in the emulator flash memory CONFIGURATION lt configuration number gt RET e List display Displays the configuration information saved in the emulator flash memory CONFIGURATION RET 1 comment 2 comment Examples 1 To save configuration information with comment CNFI CNF 1 1 S RET 2 To restore configuration information saved under configuration number 1 CNF 1 RET 3 To display the configuration information list CNF RET 1 CNF1 2 ETC Rev 1 0 09 00 page 227 of 423 HITACHI 7 2 13 CONVERT
215. contents in the specified load module type in a host computer file via the serial interface Use interface software IPW for the host computer An S type or HEX type load module can be saved An SYSROF type or ELF type load module cannot be saved INTFC SAVE start address end address gt lt load module type file name RET When save is completed the start and end memory addresses are displayed as follows TOP ADDRESS start address gt END ADDRESS end address When the LF option is specified the emulator adds an LF code to the end of each record in addition to a CR code H OD in the S type or HEX type load module Rev 1 0 09 00 page 348 of 423 HITACHI INTFC_SAVE Notes 1 Do not save data in the area other than the internal memory areas and areas CSO to CS4 2 Verification is not performed after save If the program must be verified use the INTFC_ VERIFY command For details refer to section 8 2 3 INTFC_VERIFY 3 If the specified file name already exists an overwrite confirmation message is displayed If N is entered to halt save some unnecessary characters may be output to the following line Example To save memory contents in the address range from H 7000 to H 7FFF in host computer file F11 MOT in the S type load module format IS 7000 7FFF F11 MOT RET TOP ADDRESS 00007000 END ADDRESS 00007FFF Rev 1 0 09 00 page 349 of 423 HITACHI INTFC_VERIFY
216. counter shows how many times the specified address has been passed at GO command termination in hexadecimal Note The pass counter is cleared by the next GO command Rev 1 0 09 00 page 200 of 423 HITACHI BREAK e Cancellation Cancels software breakpoints Breakpoints can be cancelled in the following two ways Cancellation of specified software breakpoints A maximum of four breakpoints can be cancelled with one command BREAK lt software breakpoint gt lt software breakpoint gt RET Cancellation of all software breakpoints BREAK RET Examples 1 To set a software breakpoint at address H 100 B 100 RET 2 To generate a break when address H 6004 has been passed three times B 6004 3 RET 3 To display set software breakpoints B RET lt ADDR gt lt CNT gt PASS 00000100 0001 0000 00006004 0003 0000 4 To cancel the software breakpoint at address H 100 B 100 RET 5 To cancel all software breakpoints B RET Rev 1 0 09 00 page 201 of 423 HITACHI BREAK_CONDITION_A B C 7 2 7 BREAK_CONDITION_A B C BCA BCB BCC Specifies displays and cancels a hardware break condition Command Format e Setting BREAK_CONDITION_ A B C 1 2 3 4 5 6 7 8 A lt condition gt A lt condition gt A lt condition gt RET e Display BREAK_CONDITION_ A B C 1 2 3 4 5 6 7 8 RET e Cancellation BREAK CONDITION A B C 1 2 3 4 5
217. cters e To overwrite FILENAME gt FILENAME RET To add to FILENAME gt gt FILENAME RET e To terminate logging to FILENAME gt RET To overwrite the existing file enter Y when the following message is displayed INTFC ERROR FILE ALREADY EXISTS OVERWRITE Y N a RET a Y Overwrites the existing file with the new file N Terminates command execution Addresses during load save or verification cannot be logged Rev 1 0 09 00 page 56 of 423 HITACHI 3 5 Power On Procedures for Emulator The emulator power on procedures differ in each system configuration Power on the emulator in the appropriate way for the system configuration as shown below 3 5 1 Power On Procedures for LAN Interface Figure 3 23 shows the power on procedures when the LAN interface is used Turn off to the right S7 and S8 in SW1 on the E8000 station rear panel Run interface software IPW EXE on the host computer connected via the RS 232C interface Power on the E8000 station Emulator monitor command input wait state Select L to set the IP address of the E8000 station Define the subnet mask value with the flash memory management tool command SN when using the LAN board HS7000ELNO2H Define the routing information with the flash memory management tool command RTR when using the LAN board HS7000ELNO2H Define the host computer name with the fl
218. d cannot be executed during program execution by the STEP or STEP OVER command Rev 1 0 09 00 page 281 of 423 HITACHI PERFORMANCE_ANALYSIS If timeout value is specified in the PERFORMANCE_ANALYSIS1 command and the subroutine execution time exceeds the specified timeout value a break occurs To enable this make sure to specify TB as the mode with the GO command If specified count is specified in the PERFORMANCE ANALYSISI command and the subroutine execution count reaches the specified count a break occurs To enable this make sure to specify TB as the mode with the GO command Note An execution count that is exceeded is detected when the program passes through the subroutine end address Consequently a subroutine execution count that is equivalent to the specified count plus one and the correponding subroutine execution time are displayed Cancellation Cancels measuring execution performance for the specified subroutine number If the subroutine number is omitted all subroutines assigned for execution performance measurement are canceled Initialization Clears the current execution time and count for all subroutines as well as the total run time The total run time begins to be measured only after a subroutine to be measured by this command is assigned If no subroutines are assigned the total run time is not measured Display Displays specified subroutine addresses or performance m
219. d environment variable name could not be found Specify the environment variable name with the SET command INTFC ERROR FILE ALREADY EXISTS OVERWRITE Y N The specified IBM PC file already exists Enter Y to transfer any way after deleting the file enter N to cancel transfer INTFC ERROR FILE CLOSE ERROR An error has occurred while closing an IBM PC file INTFC ERROR FILE DELETE ERROR An error has occurred while deleting an IBM file Check the specified file name INTFC ERROR FILE NOT FOUND The IBM PC file specified at load cannot be found or the file name contains an error Check the specified file name INTFC ERROR FILE OPEN ERROR The directory to which the specified IBM PC file is to be saved is full or the file name contains an error INTFC ERROR FILE READ ERROR An error has occurred while reading an IBM PC file INTFC ERROR FILE RENAME ERROR Rev 1 0 09 00 page 398 of 423 An error has occurred while changing an IBM PC file name Check the specified file name HITACHI Table 10 5 Interface Software Error Messages cont Error Message INTFC ERROR FILE WRITE ERROR Description and Solution An error has occurred while writing to an IBM PC file The available memory on the disk is insufficient INTFC ERROR INVALID COMMAND An invalid command has been sent from the debugger INTFC ERROR I O ERROR An I O error has occurred during file trans
220. d then return to the last line again e Display last entered command lt command name gt When a period is entered after a command the previously input parameters of that command are displayed If two periods are entered after a command parameters of two commands prior to the entered command are displayed This key input is useful for executing commands with the same parameters again Example D 1000 1010 RET Execution of another command D RET D 1000 1010 Displays the parameters specified in the previous DUMP command execution and enters command input wait state 6 2 4 Cursor Control and Character Editing e Move cursor backwards CTRL H e Move cursor to word starting position CTRL T e Delete one character CTRL D e Cancel line CTRL X e Advance cursor CTRL W e Insert space CTRL U e Tab over CTRL I Rev 1 0 09 00 page 182 of 423 Moves the cursor one position backwards Moves the cursor to the first position of the word the character following the space Deletes a character at the cursor position Deletes the contents of the entire line Moves the cursor one position forwards Inserts a space at the cursor Moves the cursor to the 10 s multiple 1 th column HITACHI Section 7 Emulation Commands 7 1 Overview The emulator provides a wide range of functions such as break trace and performance analysis Table 7 1 lists the emulation commands that enable these functions
221. de a break occurs when hardware break conditions UBC2 and UBCI have been satisfied in that order When executing the user program specify the mode option of the GO command as a sequential break option SB Unless the option is specified a sequential break does not occur In this case break occurs whenever each break condition is satisfied Specify the break condition with the BREAK CONDITION UBC1 2 commands The user can specify either of the address bus value the data bus value or the read write condition in the above e Sequential break mode When break condition UBC2 and then break condition UBC1 are satisfied a break occurs Note When the sequential break option SB of the GO command is specified while the BREAK CONDITION UBCI1 or 2 or both are not specified the error message below will be output At this time a user program will not be executed 35 CAN NOT USE THIS MODE Initiation condition User program is executed in sequential break mode User program from address H 2000 Program Specification GO 2000 SB flow Break condition 2 is satisfied No break occurs Break condition When break condition 1 is satisfied after 1 is satisfied break condition 2 a break occurs Figure 1 11 Break with Sequential Specification Rev 1 0 09 00 page 125 of 423 HITACHI 1 4 2 Software Break The contents at the specified address are replaced with a break instruction The program execution stops when the break
222. decimal Note The subnet mask value can be defined with the emulator monitor flash memory management tool command SN Example To display the defined subnet mask value SN RET SUBNET MASK 255 255 255 128 H FF H FF H FF H 80 Rev 1 0 09 00 page 386 of 423 HITACHI LOGOUT 9 3 18 LOGOUT LO Disconnects from the TELNET Command Format e TELNET disconnection LOGOUT RET Description e TELNET disconnection Disconnects the emulator from the TELNET This command is valid only when the emulator is connected to the host computer via the TELNET interface Example To disconnect the emulator from the TELNET interface LO RET Rev 1 0 09 00 page 387 of 423 HITACHI Rev 1 0 09 00 page 388 of 423 HITACHI 10 1 Section 10 Error Messages Emulator Error Messages The E8000 system program outputs error messages in the format below Table 10 1 lists error messages descriptions of the errors and error solutions lt error message gt Error No Table 10 1 Emulator Error Messages Error No Error Message Description and Solution 1 INTERNAL ERROR nn An error occurred in the E8000 system program or station Error code nn gives specific details Contact a Hitachi sales agency and inform them of the code and state 2 HOST I O ERROR nn An I O error occurred in data transfer between the emulator and host computer Error code nn gives specific details Refer
223. display A address bus D data bus MA memory area type RW read write ST status IRL IRL signals NMI NMI signal RES RESET signal BREQ BREQ signal VCC VCC voltage state PRB external probe TIME time stamp and CLK clock cycle C Stores the settings as configuration information in the emulator flash memory Description e Setting Specifies the default values of start and end pointers for trace information display and search which are used when the pointer values are not specified in the TRACE or TRACE SEARCH command Trace information in the emulator is available for approximately 128 000 bus cycles Use this command to specify the range of the default values when all trace information is not required The specified pointers will function as bus cycle pointers in the TRACE SEARCH command and according to the option as instruction or bus cycle pointers in the TRACE command The pointer value ranges from 131070 to 131070 When exceeding this range start and end pointers are automatically specified as 131070 and 131070 respectively TRACE DISPLAY MODE D 2048 D 2048 RET Rev 1 0 09 00 page 331 of 423 HITACHI TRACE_DISPLAY_MODE Sets trace items to be displayed as bus cycle information at trace information display with the TRACE or TRACE SEARCH command TRACE DISPLAY MODE Azzzz E D RET zzzz Information to be displayed at trace information display A D MA
224. dition specify it in combination with any of the above break conditions Break condition The address H 2000 is accessed for H 50 times User program Specification A 2000 COUNT 50 TO Break occurs after the address Break condition is SA H 2000 is accessed for H 50 times satisfied Program flow Branch instructions etc Figure 1 9 Break with Number of Times Break Condition is Satisfied Rev 1 0 09 00 page 123 of 423 HITACHI PC Value BREAK_CONDITION_UBC1 2 A break occurs when the SH7612 program counter PC value satisfies the specified condition The break timing depends on the P option setting as follows e PC value without option P PC 1000 Break after execution A break occurs after the instruction at the specified address is executed e PC value followed by option P PC 1000 P Break before execution A break occurs before the instruction at the specified address is executed Break after execution Break condition Break occurs after the instruction at address H 1004 1000 is executed Break 1002 Specification PC 1004 condition ys 1004 At break RO 2 User program is satisfied Break before execution Break condition Break occurs before the instruction at address H 1004 is executed Specification PC 1004 P At break RO 1 Figure 1 10 Break with PC Value Specification Rev 1 0 09 00 page 124 of 423 HITACHI Sequential Break Condition In sequential break mo
225. dition is specified with the BREAK_CONDITION_B or TRACE_CONDITION_B command the combination of conditions also specified is handled as a delay start condition Delay starts to be counted when the delay start condition is satisfied When no delay start condition has been specified or termination has been caused by another reason the pointer value will be relative to the latest trace information Pointer Trace information Oldest information Display start pointer Delay count Display range condition satisfied Display end pointer Latest information Figure 7 2 Display Range Specified by Pointers Pointer default is as follows a If lt start pointer gt is omitted the start pointer specified by the PTR option of the TRACE DISPLAY MODE command is used b If end pointer is omitted the end pointer specified by the PTR option of the TRACE DISPLAY MODE command is used Rev 1 0 09 00 page 312 of 423 HITACHI To display only instruction mnemonics of the executed instructions uses the following format IP ADDR MNEMONIC OPERAND D xxxxxx XXXXXXXX XX XX XX XX a b c d a Instruction pointer Relative instruction location based on the instruction where a delay count condition is satisfied An instruction pointer begins with an asterisk to differentiate it from a bus cycle pointer Although the pointer usually has a negative value D
226. dress range e Unused standard emulation memory size in hexadecimal S xMB Standard emulation memory When no address is specified the memory attributes of all memory areas are displayed in the format shown above Rev 1 0 09 00 page 265 of 423 HITACHI Notes 1 If there 15 not enough standard emulation memory to satisfy the specification the memory attribute is specified only for the memory area available 2 Standard emulation memory cannot be allocated to areas other than areas CSO to CS4 3 A memory attribute cannot be allocated to a range that includes a cache area cache through area or reserved area 4 An area to which emulation memory is allocated cannot be used as user system memory For example if area CSO is assigned to emulation memory area CSO cannot be used as user system memory However areas CS1 to CS4 can be used as user system memory 5 A cache area and cache through area specified in standard emulation memory are handled as the same area Accordingly when the map is allocated to either of them it is allocated to both areas Memory attributes in both areas are displayed 6 For specifications of internal memory refer to the Hardware Manual of the SH7612 Examples 1 To allocate standard emulation memory to the address range from H 1000000 to H 10FFFFF MP 1000000 10FFFFF S RET REMAINING EMULATION MEMORY S 3MB 2 To allocate standard emulation memory to the ad
227. dress range from H 2000000 to H 20FFFFF with write protection MP 2000000 20FFFFF SW RET REMAINING EMULATION MEMORY S 2MB Rev 1 0 09 00 page 266 of 423 HITACHI 3 To display the memory address ranges and attributes of allocated standard emulation memory the internal memory address ranges and the internal I O address range MP RET 01000000 010FFFFF S 21000000 210FFFFF S 02000000 020FFFFF SW 22000000 220FFFFF SW X RAM AREA 1000F000 0000FFFF Y RAM AREA 1001F000 0001FFFF INTERNAL I O FFFF8000 FFFFBFFF FFFFFCOO FFFFFDBF FFFFFEO0 FFFFFFFF REMAINING EMULATION MEMORY S 2MB 4 To cancel write protection for the standard emulation memory allocated to the address range from H 2000000 to H 20FFFFF MP 2000000 20FFFFF S RET REMAINING EMULATION MEMORY S 2MB Rev 1 0 09 00 page 267 of 423 HITACHI MEMORY 7 2 26 MEMORY M Command Format e Display modification address data option N Displays or modifies memory contents MEMORY A address A data option AN RET Address of memory area whose contents are to be displayed or modified Data to be written to the specified address Length of display or modification units B 1 byte units W 2 byteunits L 4 byte units XW 16 bit fixed point units XL 32 bit fixed point units O Odd address 1 byte units E Even address 1 byte units Default 1 byte units
228. e INTFC LOAD lt offset gt S lt file name RET If an offset is specified a load address is calculated as follows Load address load module address gt offset Rev 1 0 09 00 page 346 of 423 HITACHI INTFC_LOAD Notes 1 The load module can be loaded only to the internal memory areas or areas CSO to CS4 2 Verification is not performed during load If the program must be verified use the INTFC_ VERIFY command For details refer to section 8 2 3 INTFC_VERIFY Examples 1 To load SYSROF type load module F11 ABS IL F11 ABS RET TOP ADDRESS 00007000 END ADDRESS 00007FFF 2 To load S type load module ST MOT IL S ST MOT RET TOP ADDRESS 00000000 END ADDRESS 00003042 Rev 1 0 09 00 page 347 of 423 HITACHI INTFC_SAVE 8 2 2 INTFC_SAVE IS Saves program in host computer Serial interface Command Format e Save INTFC_SAVEA lt start address gt A lt end address gt A Q number of bytes lt load module type ALF file name RET start address gt Start memory address end address gt End memory address number of bytes Number of bytes to be saved lt load module type Load module type S S type load module H HEX type load module Default S type load module LF Adds an LF code to the end of each record file name gt File name in the host computer Description e Save Saves the specified memory
229. e Enter the F command to initiate the flash memory management tool in the monitor command input wait state 2 Enter LH RET to store the host name and IP address of the host computer 3 Enter 1 as the selection number HITACHI RET as the host name and 128 1 1 10 RET as the IP address After that the emulator prompts the user to select another number 4 Enter E RET to enable the settings and to exit interactive mode 5 The emulator confirms whether to save the settings in the configuration file with the above settings 6 Enter Y RET to save the settings Rev 1 0 09 00 page 86 of 423 Display Message START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T F RET FM FM gt LH RET NO lt HOST NAME gt lt IP ADDRESS gt NO lt HOST 01 02 03 04 05 06 07 08 09 E8000 IP ADDRESS 128 1 1 1 PLEASE SELECT NO 1 9 L E Q X _ PLEASE SELECT NO 1 9 L E Q X 1 RET 01 HOST NAME HOST A HITACHI RET 01 IP ADDRESS 128 1 1 1 128 1 1 10 RET PLEASE SELECT NO 1 9 L E Q X PLEASE SELECT NO 1 9 L E Q X E RET LAN CONFIGURATION FILE WRITE OK Y N CONFIGURATION FILE WRITE OK Y N Y RET gt Operations 7 Enter Q RET to terminate the flash memory management tool and enter the monitor command input wait state 8 Enter S RET to re initiate the emulator The emulator is re initiated
230. e MAP or MOVE TO RAM command For details refer to the MAP command 73 BREAK POINT IS DELETED A XXXXXXXX A software breakpoint specified at the displayed address was cancelled because the contents of the address were modified with the user program 74 CANNOT SET A XXxxxxxx A breakpoint cannot be specified at the displayed address by the BREAK or BREAK SEQUENCE command before GO command execution A hardware error might have occurred or the contents of the memory address might be a break instruction H 0000 Correct the error and reload and re execute the program 77 ALL BREAKPOINT DELETED All software breakpoints specified by the BREAK or BREAK_SEQUENCE command were cancelled 78 EMULATOR BUSY The emulator was processing a break processing in parallel mode so another command could not be executed Re enter the command This error occurs when software breakpoints are set with the BREAK or BREAK_SEQUENCE command 81 TRACE CONDITION RESET Satisfied trace conditions are all reset when parallel mode is entered When parallel mode is terminated the trace conditions are rechecked from the beginning Rev 1 0 09 00 page 393 of 423 HITACHI Table 10 1 Emulator Error Messages cont Error No Error Message Description and Solution 82 ODD ADDRESS An instruction was written to an odd address with the ASSEMBLE command Processing was initiated from the odd address
231. e 5 7612 control registers PC SR PR GBR VBR MACH MACL RS RE MOD e SH7612 general registers RO to R15 e DSP registers of SH7612 DSR A0G AO MO YO e Instruction address e Instruction mnemonic e Memory contents e Cause of termination 1 6 1 Single Step Execution Single step execution has three modes one in which all the instructions are displayed one in which only branch instructions are displayed and another in which instructions of a subroutine executed at first are displayed To execute this function use the STEP command or to execute a subroutine in a single step use the STEP_OVER command Displaying All Instructions The emulator displays the specified information after every instruction Branch Instruction Display The information is only displayed at branch instructions listed below BT BF BRA BSR JMP JSR BTS BFS BRAF BSRF TRAPA Rev 1 0 09 00 page 136 of 423 HITACHI Subroutine Display When a subroutine is called the information for the subroutine executed at first is displayed race information is acquired Figure 1 20 Subroutine Display This function interrupts the execution state display at the JSR BSR or BSRF instruction in the designated subroutine and resumes the execution state display when the instruction placed immediately after the JSR BSR or BSRF instruction is executed After that if another JSR BSR or BSRF instruction i
232. e data is accessed in one bus cycle Only byte data D can be specified as the data condition Both even and odd address values can be specified as the address condition 16 bits must be specified as the data bus width Note that the data condition must be specified in combination with a specific address condition If no address condition is specified or if the address is masked the data condition will be satisfied when the address is a multiple of two c Access to an 8 bit bus area All addresses can be accessed in byte units Longword data and word data are accessed in four byte access cycles and two byte access cycles respectively Both even and odd addresses can be specified as the address condition Note however that only byte data D is valid for the data condition Eight bits must be specified as the data bus width Rev 1 0 09 00 page 208 of 423 HITACHI BREAK_CONDITION_A B C A bit mask in 1 bit or 4 bit units can be specified for the address condition of the BREAK CONDITION A B C command When a bit is masked the condition is satisfied irrespective of its bit value To implement the mask specify each digit to be masked at input as an asterisk When address 2 is not specified for an address condition address 1 gt can be consecutively masked from the lowest bit It is not possible to mask any desired bit position Table 7 8 shows address mask specification examples Example The following condition is
233. e emulator re enters the F FLASH MEMORY TOOL monitor command input wait state L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ 6 Installation is completed Rev 1 0 09 00 page 76 of 423 HITACHI Manual System Program Load by Bidirectional Parallel Interface To use the emulator files E8000 SYS SHCNF761 SYS and SHDCT761 SYS must be installed in the emulator flash memory If the emulator is connected to the host computer via the bidirectional parallel interface the E8000 system program can be loaded with the following procedures Note that the E8000 system disk is assumed to be inserted in drive A of the host computer It takes approximately one minute Operations 1 Initiate IPW in the E8000 system floppy disk Power on the emulator For details on the power on procedures refer to section 3 5 2 Power On Procedures for RS 232C Interface Emulator monitor command prompt Enter F RET to initiate the flash memory management tool The emulator displays prompt FM gt and waits for a flash memory management tool command Enter SL RET to load the system program Enter 1 RET to select PC as the host computer type and 2 RET to select parallel interface as the interface method Enter Y RET to allow system program E8000 SYS to be loaded Then enter the parallel transfer command to load E8000 SYS in the current directory on the PC to the emulator flash memory Display Message START E8000 S
234. e host computer from the FTP interface Usable Re connects the host computer to the FTP interface with the OPEN commana FTP Connects the host computer and emulator via the FTP Usable interface LAN Displays emulator IP address Usable LAN_HOST Displays all defined host computers Usable LAN_LOAD Loads a load module file from the host computer to Unusable memory via the FTP interface LAN_SAVE Saves the specified memory contents in the host computer Unusable connected via the FTP interface LAN_VERIFY Verifies memory contents against the host computer file Unusable connected via the FTP interface LS Displays the host computer directory connected via the Usable FTP interface OPEN Connects the host computer to the FTP interface Usable PWD Displays the current directory name of the host computer Usable connected via the FTP interface ROUTER Displays routing information Usable STA Displays the type of file to be transferred Usable SUBNET Displays the subnet mask value Usable LOGOUT Disconnects from the TELNET Usable Note The optional LAN board supports the TELNET server function in addition to the FTP client function When the emulator is connected to the host computer through TELNET the emulator can be disconnected from the TELNET with the LOGOUT command For details on the TELNET interface refer to section 3 5 1 Power On Procedure for LAN Interface in Part E8000 Guide Note that the FTP can
235. e host computer interface processing may remain uncompleted In this case the FTP interface cannot be re established correctly even if the emulator is re initiated Rev 1 0 09 00 page 362 of 423 HITACHI 9 3 LAN Commands This section provides details of LAN commands in the format shown in figure 9 1 Command Name No Command Name Abbr Function Command Format Function 1 Command input format Function 2 Command input format parameter 1 Parameter description 1 parameter 2 Parameter description 2 Description Function 1 Description of function 1 Function 2 Description of function 2 Notes Examples Command Name Full command name Abbr Abbreviated command name Function Command function Command Format Command input format for each function Description Function and usage in detail Notes Warnings and restrictions for using the command If additional information is not required this item is omitted Examples Command usage examples Figure 9 1 LAN Command Description Format HITACHI Rev 1 0 09 00 page 363 of 423 Symbols used in the command format have the following meanings I a b lt gt de RET Parameters enclosed by can be omitted One of the parameters enclosed by and separated by that is either a or b must be specified Contents shown in are to be specified or displayed The entry specified just befo
236. e parallel mode By pressing the RET key or space key or by satisfying the trace stop condition _ _ _ Mie Normal mode Parallel mode executing executing a user program END command a user program GO command BREAK CTRL C ABORT command or break condition Command input satisfaction wait state Figure 1 3 Transition to Parallel Mode Rev 1 0 09 00 page 116 of 423 HITACHI User program Program flow By pressing the RET key A prompt is By pressing the space key E displayed and By satisfying the trace stop the emulator waits for condition parallel mode Program does not stop Figure 1 4 Parallel Mode Note that debugging differs in parallel mode operation depending on the method used to activate it as follows e By pressing the RET key or satisfying a trace stop condition The emulator stops acquiring trace information as soon as parallel mode is entered The emulator can execute multiple commands entered by the user in parallel mode The parallel mode continues even after the command execution is terminated The END command terminates the parallel mode and returns the emulator to normal mode displays the current PC At this time the emulator restarts trace information acquisition e By pressing the space key The emulator continues trace information acquisition however while the emulator executes TRACE TRACE CONDITION
237. ead of R15 SR SR Status register GBR GBR Global base register VBR VBR Vector base register MACH MACH High order multiply and accumulate register MACL MACL Low order multiply and accumulate register PR PR Procedure register SSR SSR Saving status register SPC SPC Saving program counter Rn Register indirect Rn General register name Rn Register indirect with Rn General register name post incrementation Rn Register indirect with General register name pre decrementation disp Rn Register indirect with disp Displacement value displacement Rn General register name RO Rn Register indirect with RO Rn General register name index disp GBR GBR indirect with disp Displacement value displacement GBR Global base register RO GBR GBR indirect with RO General register name index GBR Global base register disp PC PC relative with disp Displacement value displacement PC PC value within vector address table aaaa PC relative aaaa Address value Usable with BF BT BRA and BSR instructions imm Immediate imm Immediate data value Notes 1 For the address value immediate data value and displacement values the formula addition or subtraction can be used However disassemble is displayed only in address value 2 If the immediate data value is different from the specified operation size an error occurs Rev 1 0 09 00 page 152 of 423 HITACHI 111 3 Disassembly The emulator has a disassembly
238. eak conditions specified with the BREAK CONDITION A B C or BREAK CONDITION UBC command are ignored Time interval e Software breakpoints specified with the BREAK or BREAK SEQUENCE measurement modes 1 and 2 command are ignored Hardware break conditions specified with the BREAK CONDITION A B C command are ignored Conditions must be specified with the BREAK CONDITION UBC1 2 command All conditions specified with the TRACE CONDITION command are ignored Parallel mode cannot be entered Sequential break mode Software breakpoints specified with the BREAK or BREAK SEQUENCE command are ignored Conditions must be specified with the BREAK CONDITION UBC1 2 command Timeout break mode Software breakpoints specified with the BREAK or BREAK SEQUENCE command are ignored If break address gt is specified realtime emulation stops when the specified address is reached The instruction at the specified address is not executed This specification is valid for only the current GO command emulation BREAK_CONDITION_UBC2 command settings are invalid when a break address is specified Rev 1 0 09 00 page 252 of 423 HITACHI GO During user program execution program fetch addresses are displayed according to the time interval specified with the MON option in the EXECUTION_MODE command During GO command emulation pressing the SPACE key or RET key enters parallel mode If emulation
239. ealtime emulation Command Format e Execution GO A lt start address gt lt break address gt A lt mode gt RET lt start address gt Start address of realtime emulation or the word RESET break address Breakpoint address Break occurs before the instruction at the break address is executed mode Emulation mode R lt n gt Cycle reset mode n 1 to 12 N Temporarily invalidates break conditions I1 Time interval measurement mode 1 I2 Time interval measurement mode 2 SB BREAK CONDITION UBC sequential break mode TB Causes a break to occur at the timeout value specified with the TIME option of the PERFORMANCE ANALYSISI command Description e Execution Executes realtime emulation user program execution starting from the specified lt start address gt The following data can be specified as lt start address gt GO lt address gt RET Executes the program from the specified address RET When omitting the address the program executes from the address where the current PC indicates GO RESET RET After a RESET signal input to the SH7612 PC and SP are set to the values specified with the reset vector and program execution starts Rev 1 0 09 00 page 249 of 423 HITACHI GO According to the lt mode gt specification at GO command input the user program is executed in one of the following modes If no lt mode gt is specified normal emulation mode is assumed
240. easurement results in one of the following three formats If a subroutine name is specified the subroutine addresses and measurement results are displayed in numerical form or graph form Rev 1 0 09 00 page 282 of 423 HITACHI PERFORMANCE_ANALYSIS Execution time ratio displayed in graph form No option is specified PERFORMANCE_ANALYSIS RET NO NAME MODE RATE 0 10 20 30 40 50 60 70 80 90 100 1 SUBA D 10 0go a d 2 SUBB D200 Skk 3 SUBC B 20 0 Week 4 5 SUBD D15 0 eeeee lt ACCESS gt D 5 0 7 SUBE SC 30 0 lt CALL SUB gt 5 0 h TOTAL RUN TIME D 0000H 10M 008 000020US 000NS f a Subroutine number b Subroutine name up to 8 characters are displayed c Execution measurement mode Il Subroutine execution time measurement mode 1 12 Subroutine execution time measurement mode 2 13 Subroutine execution time measurement mode 3 AC Area access count measurement mode SC Subroutine call count measurement mode d Execution time ratio as a percentage e Execution time ratio in graph form in units of 2 asterisk rounded up f Total run time displayed as H hour M minutes S second US microsecond and NS nanosecond g Execution time ratio as a percentage and in graph form for area access h Execution time ratio as a percentage and in graph form for subroutine call Re
241. ed as follows e Channels 1 and 2 e Channels 3 and 4 e Channels 5 and 6 e Channels 7 and 8 Start address range End address range Figure 1 26 Time Measurement Mode 3 e Execution count measurement This is counted up every time the end address of the specified subroutine is passed e Execution time measurement The measurement starts from the program fetch cycles of the start address range and ends with the program fetch cycles of the end address range range Accordingly the execution time of a subroutine called during this period is included Rev 1 0 09 00 page 143 of 423 HITACHI Specified Count Access Range The access count from the subroutine specified by the start address and end address to the data in the user specification area is measured The combination of the channels is the same as that for time measurement mode 3 In this case this is measured in time measurement mode 1 Subroutine Call Count Measurement Mode The access count to a subroutine child is measured during subroutine parent execution The combination of the channels is the same as that for time measurement mode 3 Maximum Minimum Subroutine Time Detection Function This is specified in the time measurement mode 2 of PERFORMANCE ANALYSIS 1 2 3 4 This measures the maximum minimum execution time for a subroutine specified by the start address and end address Timeout Function This compares a measured value and a user specification time during user
242. ed in one bus cycle Only word data WD and a multiple of two can be specified as the data and address conditions respectively 32 bits must be specified as the data bus width Note that the data condition must be specified in combination with a specific address condition If no address condition is specified or if the address is masked the data condition will be satisfied when the address is a multiple of four Byte access Byte data is accessed in one bus cycle Only byte data D can be specified as the data condition Both even and odd address values can be specified as the address condition 32 bits must be specified as the data bus width Note that the data condition must be specified in combination with a specific address condition If no address condition is specified or if the address is masked the data condition will be satisfied when the address is a multiple of four Rev 1 0 09 00 page 207 of 423 HITACHI BREAK_CONDITION_A B C b Access to a 16 bit bus area e Longword access Longword data is accessed in two word access cycles Only word data WD and a multiple of two can be specified as the data and address conditions respectively 16 bits must be specified as the data bus width e Word access Word data is accessed in one bus cycle Only word data WD and a multiple of two can be specified as the data and address conditions respectively 16 bits must be specified as the data bus width e Byte access Byt
243. ed level NMI or NMI L The condition is satisfied when NMI is low NMI H The condition is satisfied when NMI is high External interrupt condition 2 The condition is satisfied when all of the IRL signals match the specified values Specify lt value gt as 1 byte data Each bit IRL lt value gt corresponds to an IRL number as follows 3 2 1 0 lt Bit xX x X lt Specified value Nou 3 2 1 0 lt IRL number x 0 Low level 1 High level The condition can be masked RES Searches for a bus cycle in which the RESET signal is low Time stamp Searches for the specified elapsed time TS lt elapsed time 1 gt A lt elapsed time 2 gt When only lt elapsed time 1 gt is specified searches for the time specified with lt elapsed time 1 gt When both lt elapsed time 1 gt and lt elapsed time 2 gt are specified searches for the time range specified with lt elapsed time 1 gt and lt elapsed time 2 gt elapsed time 1 gt hhh mm ss uuuuuu elapsed time 2 hhh mm ss uuuuuu hhh Hour mm Minute ss Second uuuuuu Microsecond Rev 1 0 09 00 page 339 of 423 HITACHI TRACE_SEARCH When an address or data condition is specified the emulator searches for a bus cycle where address bus and data bus values match the specified values respectively Note the following when specifying search conditions a Access to a 32 bit bus area e Longword access Longword data is ac
244. ee k k kok kk kk L COB 0 00 A0 00000000 M0 00000000 X0 00000000 Y0 00000000 A1G 00 A1 00000000 M1 00000000 X1 00000000 Y1 00000000 b lt address gt lt instruction mnemonic gt c MEMORY lt memory contents gt d lt cause of termination gt a Register information b Address and mnemonic of the executed instruction c Memory contents display d Cause of termination refer to table 7 24 Information a and c is displayed according to specifications made with the STEP_INFORMATION command The termination cause d is displayed only when the STEP command is completed Rev 1 0 09 00 page 299 of 423 HITACHI STEP Table 7 24 Causes of STEP Command Termination Message BREAK CONDITION UBC1 Termination Cause A break condition specified with the BREAK_CONDITION_UBC1 command was satisfied BREAK CONDITION An A break condition specified with the BREAK_CONDITION_An command was satisfied n 1 to 8 BREAK CONDITION Bn A break condition specified with the BREAK_CONDITION_Bn command was satisfied n 1 to 8 BREAK CONDITION Cn A break condition specified with the BREAK_CONDITION_Cn command was satisfied n 1 to 8 BREAK CONDITION Multiple break conditions specified with the BREAK_CONDITION_A A1 8 A1 to A8 commands were satisfied BREAK CONDITION Multiple break conditions specified with the BREAK CONDITION B B1 8 B1 to B8 commands were satis
245. efore the timer pins are valid even when user program execution has stopped The user can rewrite the timer registers with the MEMORY command 3 3 6 DMAC The DMAC performs data transfer between the memory internal or external and a peripheral device internal or external The DMAC of the SH7612 operates during the command input wait state as well as during emulation When transfer is requested the DMA transfer is performed 3 3 7 Hitachi User Debugging Interface Hitachi UDI The Hitachi user debugging interface Hitachi UDT incorporates a data transfer and interrupt request functions The H UDI performs serial transfer through the control of an external signal The E8000 operates using the H UDI function Therefore the H UDI cannot be used when the E8000 is used 3 3 8 Bus State Controller The SH7612 wait state controller has a programmable wait mode and a WAIT pin input mode While the programmable wait mode is valid when the emulation memory or user external memory is accessed input to the user WAIT pin is valid only when user external memory is accessed However the EXECUTION MODE command can be used to enable input to the user WAIT pin during emulation memory access cycles The refresh cycle controller operates continuously when the emulator is carrying out PSRAM DRAM SDRAM refresh control even during the command input wait state Rev 1 0 09 00 page 162 of 423 HITACHI 3 3 9 System Controller SYSC The system controll
246. enne 138 1 7 2 Subroutine Time Measurement and Number of Times Measurement 140 1 8 Trigger Output ssc oue ente tite e Ee Sesterce ee eee REESE 145 19 SH7612 Control and Status Check esses eene enne 146 1 10 Emulation Monitoring Function enne nemen nennen nennen 148 1 4 Assembly Function neg teen obiter REPERI 150 E EE 150 1 11 2 Input Format ene trt hee E REP ee rer rri righe 151 1 11 3 Disassembly ete eme SUB OUR qi p RU Om oie 153 Section 2 Differences between the SH7612 and the Emulator 155 section 3 H7612 Function Support ooo at e ett CA elie 157 3 1 Operating Mode Setting sorrise eerror REED EUER p REM RE 157 32 Memory Space net tessaher hee hep RIP peer 160 3 24 Inteinal VO Area ian teh RE nti 160 3 2 2 External Memory Area rente ere rt cipere ee pri eed 160 3 34 Other Punctioiis cte ann ii quendi 161 3 3 1 Low Power Mode Sleep and Standby sese 161 3 3 2 esee Ue eios mee Pie 161 3 3 3 Control Input Signals RES WAIT BREQ eese 161 3 3 4 Serial Communication Interface 162 3 3 5 16 Bit Free Running Timer eese nnne 162 3 350 DMAQ cse erae ee sud EAT t P a p ipee ER es 162 3 3 7 Hitachi User Debugging Interface Hitachi UDI eee 162 3 3
247. eot erbe n ee 36 3 3 1 PC Interface Board 1 38 3 3 2 Switch Settings of the PC Interface Board see 39 3 3 3 Installing the PC Interface Board sese 41 3 3 4 Connecting the E8000 Station to the PC Interface 42 3 3 5 Connecting to a Host Computer ssssessesesseeeeeeneeeneeneen eene 43 3 3 6 Connecting to a LAN Interface nennen 44 3 3 7 System Connection 1 ene 45 3 4 Operation Procedures of Interface Software IPW sese 50 Rev 1 0 09 00 page iii of xiv HITACHI 3 4 1 Installation and Initiation of Interface Software IPW 50 3 4 2 Interface Software IPW Settings nennen nennen 51 3 4 3 Debugging Support Functions rennen nee 55 3 5 Power On Procedures for Emulator eese nennen eene 57 3 5 1 Power On Procedures for LAN Interface 57 3 5 2 Power On Procedures for RS 232C Interface ssssseeeee 62 3 6 Emulator Monitor Commands essere nennen trennen nennen 63 3 6 1 Emulator Monitor Initiation sees nenne 63 3 62 64 3 0 3 liant eiie Go ee AE is oes 65 SOLE E 73 3 16 95 Tuuscniemenssne pecu end 74 3 7
248. er for example a watchdog timer generates and controls clock signals for all internal modules and external buses The watchdog timer stops counting during the command input wait state Therefore the frequency cannot be changed with emulator commands To change the frequency set the frequency modification register by using the user program Rev 1 0 09 00 page 163 of 423 HITACHI Rev 1 0 09 00 page 164 of 423 HITACHI Section 4 User System Interface The emulator is connected to the user system with the EV chip board Probe signal trace and break can be enabled by connecting the external probe to the user system The trigger output probe can output a low level pulse as an oscilloscope trigger signal For details refer to section 1 8 Trigger Output User System Interface Circuits The circuits that interface the SH7612 in the emulator to the user system include buffers and resistors as described below When connecting the emulator to the user system adjust the user system hardware compensating for FANIN FANOUT and propagation delays The AC timing values with the emulator connected are shown in table 4 1 Note The values with the emulator connected in table 4 1 are measurements for reference but are not guaranteed values Table 4 1 Bus Timing Bus Clock 30 MHz Item Values with Emulator Connected ns tAD 7 2 tBSD 7 2 tCSD 6 2 tNMIS 32 0 tRWD 6 1 tRSD 4 8 tRESS 19 8 tWDD 4 9 tWED
249. er any patents or other rights of any third party or Hitachi Figures Some figures in this user s manual may show items different from your actual system Limited Anticipation of Danger Hitachi cannot anticipate every possible circumstance that might involve a potential hazard The warnings in this user s manual and on the emulator product are therefore not all inclusive Therefore you must use the emulator product safely at your own risk Rev 1 0 09 00 page III of VI HITACHI SAFETY PAGE READ FIRST e READ this user s manual before using this emulator product e KEEP the user s manual handy for future reference Do not attempt to use the emulator product until you fully understand its mechanism DEFINITION OF SIGNAL WORDS DANGER indicates an imminently hazardous situation which if not avoided will result in DEATH or SERIOUS INJURY to you or other people WARNING indicates a potentially hazardous situation which if not avoided could result in DEATH or SERIOUS INJURY to you or other people CAUTION indicates a hazardous situation which if not avoided may result in minor or moderate injury to you or other people or may result in damage to the machine or loss of the user program It may also be used to alert against unsafe usage NOTE emphasizes essential information Rev 1 0 09 00 page IV of VI HITACHI N WARNING Observe the precautions listed below Failure to do so will result in a FIRE HAZARD and
250. es and must be re initiated 6 Enter S RET to re initiate the E8000 system program Rev 1 0 09 00 page 88 of 423 MODE C RET E8000 MD MD4 0 xx MD 00 _ E8000 MD MD4 0 xx MD 00 10 RET CONFIGURATION STORE Y N Y RET START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ S F L T S RET HITACHI 4 2 3 Allocating Standard Emulation Memory and Specifying Attributes To load the user program to memory and run the user program allocate standard emulation memory by the following procedures Operations 1 Enter MAP 1000000 1OFFFFF S RET to allocate standard emulation memory to addresses H 1000000 to H 10FFFFF 2 The message shown on the right which indicates that memory allocation has been completed is displayed 3 Enter MAP RET to display the attributes of all the memory areas Display Message MAP 1000000 10FFFFF S RET REMAINING EMULATION MEMORY S 3MB MAP RET 01000000 010FFFFF S 21000000 210FFFFF S X RAM AREA 1000E000 1000FFFF Y RAM AREA 1001E000 1001FFFF INTERNAL I O FFFF8000 FFFFBFFF FFFFFCOO REMAINING EMULATION MEMORY S 3MB Rev 1 0 09 00 page 89 of 423 HITACHI 4 2 4 Loading the User Program Connect the emulator to the host computer using the FTP server and load the user program by the following procedures This example assumes that in host computer HITACHI the user name is defined as E800
251. es and 4 3 Application Examples are based on the following user program These examples assume that the emulator is connected to the host computer by a LAN interface and is used with a TELNET connection ADDR CODE MNEMONIC OPERAND 01001000 E00A MOV 0A RO 01001002 E101 MOV 01 R1 01001004 E201 MOV 01 R2 01001006 D405 MOV L 0100101C R4 01001008 6323 MOV R2 R3 0100100A 321C ADD R1 R2 0100100C 2426 MOV L R2 R4 0100100E 6133 MOV R3 R1 01001010 7OFF ADD FF RO 01001012 8800 CMP EQ 00 RO 01001014 8BF8 BF 01001008 01001016 0009 NOP 01001018 AFFE BRA 01001018 0100101A 0009 NOP 0100101C OF10 DATA W 0100 0100101E 0000 DATA W FFFC Store the user program in the host computer before initiating the emulator and download it to the emulator In these examples the IP address is set to 128 1 1 1 CAUTION In these examples the IP address is set to 128 1 1 1 to 128 1 1 10 For the actual host computer an IP address available on the network connected to the emulator must be specified If an unavailable IP address is specified the network will have problems Rev 1 0 09 00 page 85 of 423 HITACHI 4 2 Basic Examples 4 2 1 Preparing for Connection of the LAN Host Computer The following host name and IP address are examples Specify the actual host computer name and IP address of the host computer Operations 1 Specify the host name and IP address of the host computer to which the emulator is to be connected by the LAN interfac
252. es for and displays trace information Command Format e Search and display TRACE SEARCH A condition A condition start bus cycle pointer gt lt end bus cycle pointer gt L RET lt condition gt Condition governing trace information to be searched for or displayed If this is omitted the number of bus cycles and the number of instructions in the trace buffer are displayed Specified when searching for trace information acquired before the trace or break condition has been satisfied This option is usually necessary except for displaying trace information during delays when a delay count condition is specified by the BREAK _ CONDITION B or TRACE CONDITION B command start bus cycle pointer Start pointer of bus cycle to be searched for or displayed end bus cycle pointer End pointer of bus cycle to be searched for or displayed If both start bus cycle pointer and end bus cycle pointer are omitted bus cycles are searched for or displayed according to the pointers specified with the TRACE DISPLAY MODE command L Displays the last bus cycle information to be searched for Description e Search and display Searches for information in the trace buffer under the specified conditions and displays all applicable bus cycle information If start bus cycle pointer and end bus cycle pointer are specified searches for and displays the bus cycle information between start bus cycle poin
253. es is specified When the P option is specified with PC a break occurs before program execution at the specified address while if the option is omitted a break occurs after program execution When PC is selected only the satisfaction count specification is valid When or YA is selected specify the address in words This condition can be masked Data condition D lt 1 byte value WD lt 2 byte value LD lt 4 byte value XD lt X bus data value YD lt Y bus data value The condition is satisfied when the data bus value matches the specified value When D WD or LD is specified the break condition is satisfied when the address is accessed in bytes words or longwords respectively In program fetch cycles the data condition is not satisfied irrespective of the data bus value When or YD is selected specify the data value in words Multiple data conditions cannot be specified This condition can be masked Read Write condition R Read W Write The condition is satisfied in a read cycle R is specified or a write cycle W is specified Access type DAT Execution cycle cycle Default All bus cycles described above including program fetch cycle The condition is satisfied when the bus cycle type matches the specified type Multiple access types cannot be specified either select one of the access types on the left or specify none Satisfaction count spec
254. es of other boards An overlap will cause incorrect operation H C0000 H C4000 H C8000 H CC000 H D0000 Setting at shipment H D4000 H D8000 H DC000 H E0000 H E4000 H E8000 H ECO00 H EFFFF Figure 3 10 Allocatable Memory Area of PC Interface Board Rev 1 0 09 00 page 39 of 423 HITACHI Switch Setting A rotary switch is installed on the PC interface board figure 3 11 The switch is used to set the memory area allocation Table 3 3 lists the switch setting states The switch setting at emulator shipment is No 4 memory area H D0000 to H D3FFF PC interface board Enlarged front view Rotary switch Figure 3 11 PC Interface Board Switch Table3 3 Switch Settings for Memory Areas Switch Switch Setting Memory Area Setting 0 H C0000 to H CSFFF 8 Memory Area H E0000 to H E3FFF Note When C to F of the switch are set memory areas cannot be allocated Set one of 0 to B Rev 1 0 09 00 page 40 of 423 HITACHI 1 H C4000 to H C7FFF 9 H E4000 to H E7FFF 2 H C8000 to H CBFFF A H E8000 to H EBFFF 3 H CCO000 to H CFFFF B H ECOO0 to H EFFFF 4 setting at shipment H D0000 to H D3FFF C Not used 5 H D4000 to H D7FFF D Not used 6 H D8000 to H DBFFF E Not used 7 H DCO000 to H DFFFF F Not used 3 3 3 Installing the PC Interface Board AN WARNING Always switch OFF the PC and peripheral devices connected to the PC before installing the PC interface board Failure to d
255. ess which is generally expressed in hexadecimal is displayed in four bytes in decimal For example when the IP address has been specified as H 80010101 represents hexadecimal the emulator will display the IP address as follows and wait for a new IP address input IP ADDRESS 128 1 1 1 _ Enter a new IP address to change the displayed IP address When changing the IP address with emulator monitor command L restart the emulator The host name and IP address of the emulator must be specified in the network database for the host computer Normally the network management tool of the host computer is used For details refer to the host computer user s manual 6 Define the subnet mask value when using the LAN board HS7000ELNO2H When the F command flash memory management tool initiation is entered while the emulator waits for an emulator monitor command the emulator displays prompt FM gt and waits for a flash memory management tool command refer to table 3 9 START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T F RET FM gt Next define the subnet mask value Rev 1 0 09 00 page 58 of 423 HITACHI FM SN subnet mask value gt C RET Enter Q RET to terminate the flash memory management tool FM Q RET Setthe routing information with the flash memory management tool command RTR when the LAN board HS7000ELNO2H is used to connect the host computer in
256. f bus cycles has been executed after the other specified condition is satisfied This condition can only be specified with the BREAK_CONDITION_B7 command HITACHI BREAK_CONDITION_A B C Table 7 7 Specifiable Conditions BREAK CONDITION 1 8 Item and Input Format Description Address condition When only address 1 is specified the condition is satisfied A lt address 1 gt lt address 2 gt when the address bus value matches the specified value When both lt address 1 gt and lt address 2 gt are specified the condition is satisfied when the address bus value is in the range from lt address 1 gt to lt address 2 gt This condition can be masked Access type DAT Execution cycle The condition is satisfied when the bus cycle type matches the specified type Multiple access types cannot be specified DMA DMA cycle either select one of the access types on the left or specify VCF Vector fetch cycle nong Default All bus cycles described above including program fetch cycle Address and data conditions are satisfied when address bus values and data bus values match the specified values Note the following when specifying break conditions a Access to a 32 bit bus area Longword access Longword data is accessed in one bus cycle Only longword data LD and a multiple of four can be specified as the data and address conditions respectively Word access Word data is access
257. f the E8000 station device control board and EV chip board Check all components after unpacking If any component is missing contact the sales office from which the emulator was purchased 1 4 1 E8000 Emulator Station Table 1 2 lists the E8000 station components Table 1 2 E8000 Station Components HS8000EST02H Classification Item Quantity Remarks Hardware E8000 station 1 Power supply control board and trace board are installed Trace cable Length 50 cm AC power cable UL cable or B5 cable Serial cable RS 232C interface Parallel cable Conforms to IEEE P1284 w Fuse Spare 3 A or T3 15A corresponding to CE marking Manual HS8000EST02H 1 HS8000ESTO2HE description notes 1 4 2 SH7612 Device Control Board and EV Chip Board Tables 1 3 and 1 4 list the device control board and EV chip board components For details refer to each user s manual Table 1 3 Device Control Board Components Classification Item Quantity Remarks Hardware Device control board 1 One board installed in the E8000 station External probe 1 Software 3 5 inch floppy disk 1 E8000 system program Manual HS7612EDD81H 1 HS7612EDD81HE description notes Rev 1 0 09 00 page 8 of 423 HITACHI Table 1 4 EV Chip Board Components Classification Item Quantity Remarks Hardware EV chip board 1 HS7612EBK81H connector or two HS7612EBH81H QFP boards to be installed in the user system Manual HS7612EBK8
258. fer Check the cable connection and the operating environment and re transfer the file INTFC ERROR NO INTERFACE BOARD The interface board is not inserted in the IBM PC expansion slot Check the DIP switch setting on the interface board and that the interface board is inserted in the expansion slot correctly and re transfer If the same error occurs again inform a Hitachi sales agency INTFC ERROR STOP COMMAND CHAIN Y N Automatic command input from the IBM PC file has been completed Enter Y to terminate command input enter N to continue command input INTFC ERROR SYNTAX ERROR An error exists in the IBM PC file name Refer to the debugger and IBM PC manuals and specify a correct file name INTFC ERROR TIMEOUT ERROR A timeout error has occurred during data transfer from the debugger Check the cable connection and re transfer Rev 1 0 09 00 page 399 of 423 HITACHI Rev 1 0 09 00 page 400 of 423 HITACHI Part Appendices Appendix Connectors A 1 Serial Connector Figure A 1 shows the serial connector pin alignment in the emulator station Table A 1 lists signal names and their usage Figure A 1 Serial Connector Pin Alignment at the Emulator Station Table A 1 Signal Names and Usage of Serial Connector Pin No Signal name Usage 1 Not connected 2 Receive Data RD Data receive line 3 Transmit Data TD Data transmit line 4 Data Terminal
259. fied BREAK CONDITION Multiple break conditions specified with the BREAK CONDITION C C1 8 C1 to C8 commands were satisfied BREAK KEY The BREAK key or CTRL C keys were pressed for forcible termination ILLEGAL INSTRUCTION A break instruction H 0000 was executed RESET BY E8000 The emulator forcibly terminates program execution with the RESET signal because an error has occurred in the user system STEP NORMAL END The specified number of steps were executed STOP ADDRESS The instruction at stop PC was executed MULTI BREAK Emulation stopped by the multi break If stop PC and display option are omitted instruction mnemonics and register information are displayed for each step executed STEP number of execution steps lt start address gt RET Instruction mnemonics and register information are also displayed for each step when stop PC is specified and single step emulation is executed until the instruction at stop PC is executed STEP number of execution steps lt start address gt stop PC RET Rev 1 0 09 00 page 300 of 423 HITACHI STEP If the J option is specified instruction mnemonics and register information are displayed Notes only for branch instructions and single step emulation is executed until the instruction at lt stop PC gt is executed If lt stop PC gt is set at the start address of an
260. for only the PERFORMANCE ANALYSIS command Specifiable range H 1 to H FFFF Subroutine entry address range start address of subroutine entry range end address of subroutine entry range Subroutine exit address range start address of subroutine exit range end address of subroutine exit range Address range of the area which is accessed by the subroutine start address of range end address of range Bus cycle type for the specified access area DAT Execution cycle DMA DMA cycle Default Address range of the called subroutine accessed by the calling subroutine All access cycles lt start address gt lt end address gt Initializes performance measurement information Displays specified subroutine addresses Displays subroutine execution time and execution count in numerical form If V is omitted display is in graph form Rev 1 0 09 00 page 279 of 423 HITACHI PERFORMANCE_ANALYSIS Description e Specification Measures the execution time and count of the specified subroutine during user program execution initiated with the GO command The following modes can be specified a Subroutine execution time measurement mode 1 Measures the execution time and count of the subroutine defined by lt start address gt and lt end address gt Measurement starts when an address within the range from the start address to the end address is prefetched halts when an address outside the specif
261. g the PC interface board PC interface board CI E8000 station PC interface cable LA Host computer Figure 2 9 System Configuration Using a PC Interface Board Rev 1 0 09 00 page 22 of 423 HITACHI Section 3 Preparation before Use 3 1 Emulator Preparation CAUTION Read the reference sections shaded in figure 3 1 and the following warnings before using the emulator Incorrect operation will damage the user system and the emulator The USER PROGRAM will be LOST Rev 1 0 09 00 page 23 of 423 HITACHI Unpack the emulator and prepare it for use as follows Unpack the emulator Reference Check the components against the component list Component list Connect the E8000 station and the device control board Connect the user system and the EV chip board Connect the E8000 station and the EV chip board Connect the external probe Sec 3 2 3 Select the clock Install the crystal oscillator Sec 3 2 4 Connect the system ground Sec 3 2 5 When the RS 232C interface When the PC interface cable or and bidirectional parallel When the LAN interface is used board is used interface cable is used Set the console Set the console Sec 33 Set the console interface switch interface switch interface switch Connect the LAN Set the PC interface interface cable board switch Connect the RS 232C Install the PC Sec 3 8 3
262. gnal trace Rev 1 0 09 00 page 130 of 423 HITACHI TS T2 TS Ti T2 1 T2 TS Tl External probe X undefined Figure 1 15 External Probe Signal Trace Example e External probe signal Trace information is sampled at rising edges in the T3 cycles of CLK figure 1 15 1 When the external probe signal changes between samplings it cannot be reflected in the trace data figure 1 15 2 When a sampling edge coincides with a change in the external probe signal the trace contents are undefined figure 1 15 3 e Clock number Three clock cycles are traced in bus cycle A Rev 1 0 09 00 page 131 of 423 HITACHI 1 5 2 Trace Condition Setting The user can specify the following five conditions with the TRACE_CONDITION_A B C commands For details refer to section 7 2 41 TRACE CONDITION Table 1 5 shows the maximum specifiable numbers in trace mode Free trace Subroutine trace Range trace Trace stop parallel mode Subroutine range trace Table 1 5 Maximum Specifiable Numbers in Trace Mode TRACE_ TRACE TRACE _ CONDITION_A CONDITION_B CONDITION_C Total Subroutine trace 8 8 16 Range trace 8 8 8 24 Subroutine range 4 4 trace Trace stop 8 8 8 24 Parallel mode Free Trace In free trace when the user program is executed as a result of the GO STEP or STEP OVER command tracing is carried out continuously for a maximum of the latest 131 070 b
263. he area other than the internal memory areas and areas CSO to CS4 2 Verification is not performed after save If the program must be verified use the LAN_ VERIFY command if necessary For details refer to section 9 3 11 LAN_VERIFY Example To save the memory contents in the address range from H 7000 to H 7FFF in the host computer as an S type load module file file name F11 S enter the following command line Before entering the LAN SAVE command connect the emulator to the host computer with the FTP command FTP HOST1 RET Username USER1 RET Password x RET login command success TP gt LSV 7000 7FFF F11 S RET SAVING ADDRESS 00007000 TOP ADDRESS 00007000 END ADDRESS 00007FFF FTP gt nj Rev 1 0 09 00 page 377 of 423 HITACHI LAN_VERIFY 9 3 11 LAN_VERIFY LV Verifies memory contents against the host computer file connected via the FTP interface Command Format e Verification LAN_VERIFY A lt offset gt lt load module type gt lt file name gt RET lt offset gt Value to be added to the load module address lt load module type gt Load module type R SYSROF type load module S S type load module H HEX type load module M Memory image file E ELF type load module Default SYSROF type load module file name File name in the host computer Description e Verification Verifies the file in the host computer connected via the FTP interface against dat
264. heck the operation status of the host computer Rev 1 0 09 00 page 394 of 423 HITACHI The E8000 system program outputs LAN I O error messages in the format below Table 10 3 lists the error messages with brief descriptions LAN I O ERROR E0xx socket library error nn lt error message gt xx Process in which error occurred see table 10 4 nn Error code lt error message gt Refer to table 10 3 If an error message other than that listed in table 10 3 is displayed refer to the description for the host computer error messages Table 10 3 LAN I O Error Messages Error No Error Message Description 01 not listen The socket cannot be created 02 Insufficient Buffer The internal buffer is insufficient 03 Socket not Support The requested function is not supported 04 Socket is Already The socket has already been connected 05 time out error A timeout error has occurred 06 Ip Address Nothing The IP address destination is undefined 07 Not Socket Connection The socket has not been connected 08 connection failire A connection failure has occurred 09 Illegal IP Address An illegal IP address has been specified 10 be Shutdowning The connection is being terminated 11 Not Socket Entry The socket information has not been defined 12 Socket is already The socket information has already been defined 13 HOSTS Name Nothing The host computer name does not exist 14 Soc
265. ied range is prefetched and restarts when an address within the specified range is prefetched again The subroutine execution count is incremented every time the subroutine end address is fetched The execution time of subroutines called from the specified subroutine is not included in the measurement results b Subroutine execution time measurement mode 2 Measures the execution time and count of the subroutine defined by lt start address gt and lt end address gt Measurement starts when the start address is prefetched and halts when the end address is prefetched The subroutine execution count is incremented every time the subroutine end address is fetched The execution time of subroutines called from the specified subroutine is included in the measurement results c Subroutine execution time measurement mode 3 Measures the execution time and count of the subroutine defined by lt start address range gt and lt end address range gt Measurement starts when an address in the start address range is prefetched and halts when an address in the end address range is prefetched The subroutine execution count is incremented every time lt end address range gt is passed d Area access count measurement mode Counts the number of times the subroutine defined by lt start address gt and lt end address gt accesses the range specified by lt accessed area address range gt The subroutine execution time is measured using subroutine execution
266. ification COUNT lt value gt value H 1 to H FFF Rev 1 0 09 00 page 214 of 423 This condition can be specified in combination with any of the address data read write and access type conditions The complete condition combination is satisfied when the other specified condition has been satisfied for the specified number of times HITACHI BREAK_CONDITION_UBC Table 7 11 Specifiable Conditions BREAK CONDITION UBC2 Item and Input Format Address condition A lt address gt PC lt address gt P Description The condition is satisfied when the address bus value matches the specified value When is selected the address bus in data access or program fetch cycles is specified and when is selected the address bus in program fetch cycles is specified When the P option is specified with a break occurs before program execution at the specified address while if the option is omitted a break occurs after program execution When is selected no other conditions can be specified This condition can be masked Read Write condition R Read W Write The condition is satisfied in a read cycle R is specified or a write cycle W is specified Access type DAT Execution cycle DMA DMA cycle Default All bus cycles described above including program fetch cycle The condition is satisfied when the bus cycle type matches the specified type Multiple access types
267. ified as required Rev 1 0 09 00 page 361 of 423 HITACHI 9 2 2 Data Transfer Data transfer is performed by connecting the emulator to the host computer via the FTP interface after the environmental settings have been completed In the FTP interface the optional LAN board supports only the client function Therefore the FTP command must be entered to the emulator and not the host computer to establish the FTP interface Transfer data using the following procedure Procedure 1 E8000 system program initiation Initiate the E8000 system program with the emulator monitor command S after confirming that the host computer to be connected has been defined with the emulator monitor flash memory management tool command LH 2 FTP connection Connect the emulator to the designated host computer with the FTP command using the format shown below Enter the host computer name defined with the emulator monitor flash memory management tool command LH In addition enter the user name and password FTP host computer name gt RET Username lt user name gt RET Password lt password gt RET login command success FTP gt 3 Transfer data using the LAN_LOAD LAN_SAVE or LAN_VERIFY command after the FTP interface is established For details refer to the corresponding command descriptions 9 2 3 Notes on FTP Interface Before turning off the emulator power the FTP interface must be terminated using the BYE command Otherwise th
268. ilable Cheapernet BNC T type connector with a characteristic impedance of 50 Q and a RG 58A U thin wire cable or its equivalent Table 3 7 shows a recommended BNC T type connector and thin wire cable Note Ifa connector or a cable with a characteristic impedance other than 50 Q is used the impedance mismatch will cause incorrect data transmission and reception LAN board pep m DCONT TRC ONT Cheapernet thin wire cable Cheapernet BNC T type connector T o 2 Np SE g 2 T SENSE MEN Workstation E8000 station rear panel Figure 3 15 Cheapernet Interface Table 3 7 Recommended BNC T Type Connector and Thin Wire Cable Item Product Type Manufacturer BNC T type connector HBN TA JPJ Hitachi Cable Ltd Thin wire cable HBN 3D2V LAN Hitachi Cable Ltd For setting up Cheapernet refer to the LAN board user s manual Rev 1 0 09 00 page 47 of 423 HITACHI RS 232C Interface Figure 3 16 shows the E8000 station connected to the host computer via RS 232C for a serial interface DCONT _TRC CONT LAN I n Nj N m F I Host computer RS 232C interface cable supplied E8000 station Figure 3 16 RS 232C Interface Rev 1 0 09 00 page 48 of 423 HITACHI Parallel Interface Figure 3 17 shows the E8000 station connected to a host computer via a parallel cable for a parallel interface When using the parallel interface connect not only the para
269. in tables 7 31 to 7 33 can be specified as lt condition gt and they can be combined by ANDing them Several conditions can be specified in any order Table 7 34 Specifiable Conditions TRACE CONDITION A Item and Input Format Address condition A lt address 1 gt lt address 2 gt Description When only lt address 1 gt is specified the condition is satisfied when the address bus value matches the specified value When both lt address 1 gt and lt address 2 gt are specified the condition is satisfied when the address bus value is in the range from lt address 1 gt to lt address 2 gt This condition can be masked Data condition D lt 1 byte value gt WD lt 2 byte value gt LD lt 4 byte value gt The condition is satisfied when the data bus value matches the specified value When D WD or LD is specified the condition is satisfied when the address is accessed in bytes words or longwords respectively In program fetch cycles the data condition is not satisfied irrespective of the data bus value This condition can be masked Read Write condition R Read W Write The condition is satisfied in a read cycle R is specified or a write cycle W is specified Access type DAT Execution cycle DMA DMA cycle VCF Vector fetch cycle Default All bus cycles described above including program fetch cycle The condition is satisfied when the bus cycle type matches the specified type
270. ing the device control board and EV chip board this emulator product can also be used for systems using other E8000 series microcomputers This emulator product must only be used for the above purpose Limited Applications This emulator product is not authorized for use in MEDICAL atomic energy aeronautical or space technology applications without consent of the appropriate officer of a Hitachi sales company Such use includes but is not limited to use in life support systems Buyers of this emulator product must notify the relevant Hitachi sales offices before planning to use the product in such applications Improvement Policy Hitachi Ltd including its subsidiaries hereafter collectively referred to as Hitachi pursues a policy of continuing improvement in design performance and safety of the emulator product Hitachi reserves the right to change wholly or partially the specifications design user s manual and other documentation at any time without notice Target User of the Emulator Product This emulator product should only be used by those who have carefully read and thoroughly understood the information and restrictions contained in the user s manual Do not attempt to use the emulator product until you fully understand its mechanism It is highly recommended that first time users be instructed by users that are well versed in the operation of the emulator product Rev 1 0 09 00 page of VI HITACHI LIMITED WARRAN
271. ins MD2 to MDO during operation If these pins are switched the operation is not guaranteed Table3 2 Setting and State of Operating Mode Pin Name Operating CKPREQ Mode MD2 MD1 MDO CKM EXTAL XTAL CKIO Mode 0 0 0 0 0 Clock input Open Output Hi Z 1 Crystal oscillation Mode 1 0 0 1 0 Clock input Open 1 Crystal oscillation Mode 2 0 1 0 0 Clock input Open 1 Crystal oscillation Mode 3 0 1 1 0 Clock input Open Hi Z 1 Crystal oscillation Mode 4 1 0 0 8 Open Clock input Mode 5 1 0 1 Mode 6 4 1 1 0 Notes Do not use MD2 to MDO pins in any combination other than those shown above 1 Operating modes 0 to 3 are not supported when CKPREQ CKM 1 2 In operating modes 4 to 6 a clock is input from the CKIO pin and an emulator internal clock cannot be used 3 In operating modes 4 to 6 the CKPREQ CKM pin functions as the clock pause request 4 High impedance Table 3 3 shows the selection of the CSO area bus width Table3 3 80 Bus Width Selection MD4 MD3 CS0 area Bus Width 0 0 8 bits 0 1 16 bits 1 0 32 bits 1 1 Setting prohibited In the emulator the operating mode previously set is saved in the configuration file on the flash memory of the E8000 station At initialization the emulator initiates the system with the operating mode specified with the MODE command Rev 1 0 09 00 page 159 of 423 HITACHI 3 2 Memory Space The SH7612 has a maximum of 160 Mbyte memor
272. ioa dente eee 100 4 3 4 Searching Trace Information sess 102 Part II Emulator Function Guide Section 1 Emulator Functions sss eerte 105 17 RES 105 L2 Specification nte ERROR ine nese hehehe aeter 105 1 3 Realtime Emu latiomn iere er re ERE EE E 113 Rev 1 0 09 00 page iv of xiv HITACHI 13210 Normal Mode eres dan RR 114 1 3 2 Cycle Reset Mode neg iR Ue PI ee BER eed 114 1 3 3 Parallel Mode ise 116 1 4 Break BEunclion eec cte eee e edic pi e e e p ee 118 1 4 E Hardware Break ena eterni 119 1 4 2 Software Break onsite bh Berean eee 126 1 4 3 gt Botced Break esee ek oh Reina BA ee nee ARE 129 T5 Realtime Trace Function eere o eI E 130 LXI Trace Taman Gs io E E utebare det 130 1 5 2 Trace Condition Setting nennen rennes 132 15 3 Trace Display ee 136 1 6 Single Step Function esses eere E E bnt nen trennen net inen entrent 136 16 1 Simngle Step ExecutiQn d om te eb eere ne eges 136 1 6 2 Setting Display Information nennen nennen eene 137 1 63 Termination of Single Step Function eese 137 1 7 Execution Time Measurement ccccccecsssscceessececeeneececeeececnesaeeecseeeeeecsneeeeseaeeeenseaeenens 138 1 7 1 Execution Time Measurement sess eene nennen enne ener
273. is 2 65 V or less The SH7612 is not operating correctly Displayed only when the user clock is selected RESET RES signal is low The SH7612 has been reset WAIT A XXxxxxxx WAIT signal is low The address bus value is displayed Not displayed during memory access command execution or refresh cycles TOUT A The SH7612 stops for 80 or longer The address value is displayed BREQ BREQ signal is low Note The time interval for this operating status display can be specified as 2 s 200 ms or no display by the MON option of the EXECUTION MODE command Default is 200 ms Rev 1 0 09 00 page 148 of 423 HITACHI User System Power and Clock Status The emulator monitors the user system power and clock status If the user system power is off or the clock stops when the SH7612 clock is set to USER with the CLOCK command the emulator executes the following operation according to the emulator status Notes 1 If the user system power is turned off Vcc is 2 65 V or lower this is detected before the clock stop is detected 2 Clock stop means that only the clock stops and the user system power remains on e During user program execution When the user system is turned off Vcc is 2 65 V or lower VCC DOWN is displayed When the power is turned on again the emulation restarts and current position of PC in the user program is displayed When the clock stops Vcc is 2 65 V or l
274. is command can be performed only in areas CSO to CS4 or the internal memory areas Example To perform line assembly from address H 1000 A 1000 RET DATA W 0000 0000 0000 0000 0000 0000 0000 0000 000 000 002 004 006 008 00C LDRS 4 LDRE 2 SETRC 0 128 NOP RET RET RET RET PADD X0 Y0 A0 PMULS A1 X0 MO MOVX W R4 X0 MOVY W R6 YO RET RET Rev 1 0 09 00 page 193 of 423 HITACHI BACKGROUND_INTERRUPT 7 2 5 BACKGROUND_INTERRUPT BI Sets and displays user interrupts in command input wait state Command Format e Setting BACKGROUND_INTERRUPT A E lt loop program address gt D RET e Display BACKGROUND_INTERRUPT RET E D User interrupt accepting mode in command input wait state E Enables user interrupts in command input wait state D Disables user interrupts in command input wait state default at emulator shipment lt loop program address gt Address of the loop program for accepting user interrupts When omitted the last address of internal Y RAM area 3 C Stores the settings as configuration information in emulator flash memory Description e Setting Enables user interrupts in command input wait state and sets the address of the loop program for accepting user interrupts If the above settings are reset when user interrupts have already been enabled even in the middle of the user interrupt processing the emula
275. is condition can be masked Data condition D lt 1 byte value gt NOT WD lt 2 byte value gt NOT LD lt 4 byte value gt NOT The condition is satisfied when the data bus value matches the specified value When D WD or LD is specified the break condition is satisfied when the address is accessed in bytes words or longwords respectively If the NOT option is specified the condition is satisfied when the data bus value does not match the specified value This condition can be masked Read Write condition R Read W Write The condition is satisfied in a read cycle R is specified or a write cycle W is specified Access type DAT Execution cycle DMA DMA cycle VCF Vector fetch cycle Default All bus cycles described above including program fetch cycle The condition is satisfied when the bus cycle type matches the specified type Multiple access types cannot be specified either select one of the access types on the left or specify none External probe condition PRB lt value gt The condition is satisfied when all of the emulator s external probe signals match the specified values Specify lt value gt as 1 byte data Each bit corresponds to a probe number as follows 3 2 1 X X X lt Bit lt Specified value x 4 3 2 1 lt Probe number 0 Low level 1 High level This condition be masked Rev 1 0 09 00 page 205 of 423 HITACHI BREAK_CONDI
276. is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this docu
277. is terminated register contents execution time and cause of termination are displayed in the following format PC 00005C60 SR 000000F0 000000000000 ITII00 a GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000FFE00 DSR200000000 t sk kk ect e kkk e kk kkk kkk k COB A0G 00 A0 00000000 0 00000000 X0 00000000 0 00000000 A1G 00 A1 00000000 M1 00000000 X1 00000000 Y1 00000000 I TIME D 0000H 00M 00S 000000US 000NS 00 0 E COUNT D 00000 b MAX D 0000H 00M 00S 000000US 000NS MIN D 0000H 00M 00S 000000US 000NS c d AVE D 0000H 00M 00S 000000US 000NS e RUN TIME D 0000H 00M 00S 000000US 000NS f lt cause of termination gt g a The register contents at emulation termination b In time interval measurement modes 1 and 2 execution time from the point when the BREAK_CONDITION_UBC2 condition is satisfied until the BREAK_CONDITION_ UBC condition is satisfied is displayed In only time interval measurement mode 2 the execution count during this period is also displayed c In time interval measurement modes 1 the maximum execution time from the point when the BREAK CONDITION UBC 2 condition is satisfied until the BREAK _ CONDITION condition is satisfied is displayed d In time interval measuremen
278. ister to PC XXXXXXXX _ H 0100FFFC 2 The emulator asks for the program 1001000 RET counter value Enter 1001000 RET as the program counter value 3 The emulator then asks for the SR xxxxxxxx RET status register value In this example other registers need not to be set or changed therefore enter RET to exit this interactive mode 4 Enter GO RET to execute the GO RET loaded program from the address pointed to by the PC While the PC 01001010 program is executed the current program counter value is displayed 5 Enter the BREAK key to BREAK terminate program execution PC 01001010 SR 000000F0 000000000000 GBR 00000000 VBR 00000000 MACH 00000000 MACL 0000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000FF 00000011 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 DSR O0000000 xxx KK e ke ke e e e e x x A0G 00 A0 00000000 M0 00000000 X0 00000000 Y0 0000 A1G 00 A1 00000000 M1 00000000 X1 00000000 Y1 0000 RUN TIME D 0000H 00M 008 000018US 000NS BREAK KEY Rev 1 0 09 00 page 91 of 423 HITACHI Operations Display Message 6 The contents of the program counter status register control registers general registers RO to R15 and DSP registers are displayed at GO command termination RUN TIME shows the duration of program execution from GO command execution to BREAK key entry BREAK KEY show
279. ket not Assign Connected The socket cannot be assigned 15 illegal port No The port number is invalid 16 initialized error An error has occurred during LAN board initialization Rev 1 0 09 00 page 395 of 423 HITACHI Table 10 3 LAN I O Error Messages cont Error No Error Message Description 17 Not Terminate The LAN board has not been terminated 18 terminate error A LAN board termination error has occurred 19 Not inialized The LAN board has not been initialized 20 Illeagal Borad An error has occurred in the LAN board 21 System Error A LAN board system error has occurred 22 Illegal Request An invalid request has been issued 23 Parameter Error The parameter data is invalid 24 Response Timeout Happend A response timeout error has occurred 25 Check Sum Error A checksum error has occurred 26 ICMP Error An ICMP error has occurred 27 ethernet address error An Ethernet address error has occurred 28 not HOST File The HOSTS information does not exist 30 illegal initialized The HOSTS initialization information is invalid 31 illegal My data Main station information is invalid 32 illega Other Party data Remote station information is invalid 33 remote Nothing Remote station has not been defined 34 transmission error A data transfer error has occurred 35 closing error A termination error has occurred FF unknown error An undefined error has occurred Rev 1 0 0
280. l correct system program Figure 5 1 Troubleshooting PAD Rev 1 0 09 00 page 177 of 423 HITACHI Internal system test at emulator system program System initiation passed deed Register break memory shared RAM System error defect EV chip board connected Connect correctly correctly CHECK command User system passed defect User system Without user connected System CHECK Emulator CHECK command command input command passed correctly passed System System defect defect System defect Correct data Correct protocol and transfer between baud rate for transfer emulator and between emulator host computer and host computer Host system Use correct connected and protocol and set up baud rate correctly Connect it correctly Figure 5 1 Troubleshooting PAD cont Rev 1 0 09 00 page 178 of 423 HITACHI Section 6 Command Input and Display 6 1 Command Syntax 6 1 1 Command Input Format The emulator command format is as follows lt command gt A lt parameter gt lt option gt RET A Space RET RET key Note that each command can be specified in abbreviated form to facilitate keyboard operations 6 1 2 Help Function emulator commands can be displayed by entering the HELP command Any command input format can be displayed by specifying the command name as a parameter of the HELP command e To
281. l be X ON X OFF control Changing the Host Computer Interface Settings The transfer rate data bit length stop bit length parity and control method can be changed with the console interface switch For the host computer connector pin assignments and signal names refer to Appendix A Connectors Rev 1 0 09 00 page 43 of 423 HITACHI 3 3 6 Connecting to a LAN Interface AN WARNING Always switch OFF the emulator and user system before connecting or disconnecting any CABLES Failure to do so will result in a FIRE HAZARD and will damage the user system and the emulator or will result in PERSONAL INJURY The USER PROGRAM will be LOST The LAN board for the emulator supports Ethernet 10 5 and Cheapernet 10BASE2 interfaces conforming to Ethernet specifications V 2 0 The LAN board communicates with a workstation according to the TCP IP protocol and the workstation transfers files and commands according to the FTP TELNET protocol The LAN board specifications at each layer of the OSI model are as follows Physical and Data Link Layers The LAN board communicates with Ethernet and Cheapernet Table 3 5 shows the Ethernet and Cheapernet specifications Table 3 5 Ethernet and Cheapernet Specifications Item Ethernet Cheapernet Transfer rate 10 Mbits second 10 Mbits second Maximum distance 500 m 185 m between segments Maximum network length 2500 m 925 m Maximum number of 100 30 nodes in one segment
282. le are sequentially executed Commands requiring further input such as the MEMORY command can be read from a file and executed Example File contents f 1000000 103ffff O w m 1000000 1 aaaaaaaa 55555555 12345678 d 1000000 1 Execution results 1000000 103ffff 0 1 m 1000000 1 01000000 00000000 aaaaaaaa 01000004 00000000 55555555 01000008 00000000 12345678 0100000C 00000000 d 1000000 1 ADDRESS D A T A gt lt ASCII CODE 01000000 AAAAAAAA 55555555 12345678 00000000 UUUU A4Vx 01000010 00000000 00000000 00000000 00000000 id 01000020 00000000 00000000 00000000 00000000 Llllll RII 1 Rev 1 0 09 00 55 of 423 The command file reading does not terminate until the end of the file is detected or the CTRL C keys are pressed If the CTRL C keys are pressed the command being executed is terminated and the message below is displayed According to the input reply command file reading is continued or terminated INTFC ERROR STOP COMMAND CHAIN Y N a RET a Y Terminate N Continue Logging When logging acquisition is specified not only are command inputs execution results and error messages afterwards the specification displayed on the console but they are output to the file specified with FILENAME Logging is specified with gt and characters when the emulator is in command input wait state Do not insert a space between gt and chara
283. les the trigger output remains low Note No pulse is output from the trigger output probe when a software break condition is satisfied In addition a low level pulse output timing and pulse width differ depending on each condition CLK Address TRIG when the user break controller condition is satisfied 5 2 ns 159 2 ns TRIG when the hardware break condition or trace condition 18 4 ns 53 2 ns is satisfied Three states External bus clock 30 MHz Figure 1 27 Pulse Output Timing Rev 1 0 09 00 page 145 of 423 HITACHI 1 9 SH7612 Control and Status Check The emulator is capable of switching the clock signal supplied to the SH7612 outputting strobe signals when the emulation memory is accessed checking normal operation and displaying the execution state This function is effective for debugging the user system hardware Clock Switching The emulation clock can be supplied from the user system clock hereafter referred to as the user clock the crystal oscillator installed on the emulator pod and the internal clock 15 MHz To switch the clock refer to section 7 2 11 CLOCK and note the following In addition refer to section 3 2 4 Selecting the Clock in part I E8000 Guide e When the clock is switched the emulator inputs a RES signal to the SH7612 This initializes the registers e When the user switches to the user clock and the user clock signal is not supplied an error message is displayed and the
284. llel interface cable but also the RS 232C cable It is impossible to use only the bidirectional parallel interface cable The parallel interface enables higher speed installation of the system program and higher speed load save or verification of the user program as compared with the RS 232C interface DCONT TRC CONT_LAN E DCONT 6 o i b mE 21 T Bidirectional parallel interface cable supplied NE CN Host computer RS 232C interface cable supplied E8000 station Figure 3 17 Bidirectional Parallel Interface Rev 1 0 09 00 page 49 of 423 HITACHI 3 4 Operation Procedures of Interface Software IPW Interface software IPW is used when the emulator is connected to the host computer via the RS 232C interface Interface software IPW runs on Microsoft Windows version 3 1 or Windows95 3 4 1 Installation and Initiation of Interface Software IPW Make a copy of file IPW EXE in the system disk to a folder The directory containing the copied folder will become the current directory Double clicking the IPW icon initiates interface software IPW and displays the IPW window shown in figure 3 18 n IP File F Setting S EMULATOR INTERFACE HS8000EIWOTSF V1 1 Copyright C Hitachi Ltd 1996 Licensed Material of Hitachi Ltd Figure 3 18 IPW Window Rev 1 0 09 00 page 50 of 423 HITACHI 3 4 2 Interface Software IPW Settings The procedures for operating interface software IPW are
285. llows REMAINING EMULATION MEMORY S xMB S xMB Standard emulation memory If there is not enough unused standard emulation memory to satisfy the specification data transfer is performed only for the memory area available and command execution terminates Contents of only areas CSO to CS4 and the internal memory areas can be transferred Refer to the MAP command for details on write protected area settings Rev 1 0 09 00 page 276 of 423 HITACHI Example MOVE_TO_RAM To allocate standard emulation memory to the address range from H O to H 3FFFF in the user system ROM area and transfer ROM contents MR 0 3FFFF S RET R EMAINING EMULATION M EMORY S 3MB HITACHI Rev 1 0 09 00 page 277 of 423 PERFORMANCE_ANALYSIS 7 2 30 PERFORMANCE ANALYSISI 8 PA 1 2 3 4 5 6 7 8 Specifies cancels Command Format e Specification e Cancellation e Initialization e Display initializes and displays performance measurement data PERFORMANCE_ANALYSIS 1 2 3 4 5 6 7 8 A lt subroutine name gt A lt start address gt A lt end address gt ATIME lt timeout value gt ACOUNT lt count value I1 RET Subroutine execution time measurement mode 1 PERFORMANCE ANALYSIS 1 2 3 4 5 6 7 8 A subroutine name gt A lt start address A end address ATIME timeout value ACOUNT lt count value I2 RET Subroutine execution time measurement mode 2 PERFORMANCE AN
286. ls refer to section 7 2 27 MODE Note An operating mode specified using the MODE command will be valid only after the emulator is re initiated Therefore the emulator must be reset after specifying an operating mode At this time emulator specifications before reset such as emulation memory attributes and breakpoint settings will not be saved Rev 1 0 09 00 page 157 of 423 HITACHI Table 3 1 Operating Mode Mode 0 SH7612 Operating Mode Selection Clock Description Source The PLL1 and PLL2 circuits operate The CKIO pin outputs a clock Crystal with the same phase as the LSI internal clock lo oscillator or The control bit of the frequency modification register FMR can switch external between operation and stop of the PLL1 and PLL2 circuits The CKIO Clock input pin can become the Hi Z state Mode 1 The PLL1 and PLL2 circuits operate The CKIO pin outputs an internal clock with a phase shift of 1 4 cycles behind the LSI internal system clock The control bit of the FMR can switch between operation and stop of the PLL1 and PLL2 circuits The CKIO pin can become the Hi Z state Mode 2 The PLL2 circuit operates The CKIO pin outputs a clock from the PLL2 circuit with the same frequency as an internal E clock The phases are not synchronized because the PLL1 circuit always stops The control bit of the FMR can switch between operation and stop of the PLL2 circuit
287. m EXECUTION_MODE UBC D RET e To enable UBC use by the user program EXECUTION_MODE UBC E RET Rev 1 0 09 00 page 244 of 423 HITACHI EXECUTION_MODE Notes 1 When UBC use is enabled the following functions cannot be used e BACKGROUND INTERRUPT command BREAK CONDITION UBC command e BREAK SEQUENCE command e STEP command e STEP OVER command e SBoption of GO command e Continuous GO command execution after termination by a software break 2 If conditions have already been set with BREAK CONDITION UBC command the UBC use setting cannot be performed Cancel the BREAK CONDITION UBC command settings before setting UBC use with the EXECUTION MODE command When the C option is specified the following message is displayed to confirm with the user whether to overwrite the existing configuration information in the emulator flash memory CONFIGURATION STORE OK Y N a RET a Y Stores the specifications as configuration information in the emulator flash memory Hereafter when the emulator is activated the saved specifications go into effect N Does not overwrite configuration information The existing specifications are valid Rev 1 0 09 00 page 245 of 423 HITACHI EXECUTION_MODE Specification interactive mode When all options are omitted the current values are displayed and the emulator enters the interactive mode Enter the required value for each item Enter RET for the ite
288. m not to be modified To exit the interactive mode enter a period In this case modifications before entering a period are valid EXECUTION MODE RET BREQ E TIME 1 6us TRGU D TRGB D MON 1 WAIT D CT D MB D UBC D BREQ D DISABLE E ENABLE RET Displays current value TIME 1 1 6us 2 406ns 3 20ns RET TRGU D DISABLE E ENABLE M MULTT RET TRGB A ALL 1 B 1 2 B2 3 B3 4 B4 5 B5 6 B6 7 B7 8 B8 D DISABLE RET MON 0 DISABLE 1 200ms 2 2s RET WAIT D DISABLE E ENABLE D RET Disables user wait CT D DISABLE E ENABLE RET MB D DISABLE E ENABLE RET UBC D DISABLE E ENABLE RET Examples 1 To enable the BREQ bus request signal inputs and store configuration information EM BREQ E C RET CONFIGURATION STORE OK Y N Y RET To display the specified values of the current emulation mode and modify them in interactive mode command execution can be terminated by entering a period EM RET BREQ E TIME 1 6us TRGU D TRGB D MON 1 WAIT D CT D MB D UBC D BREQ D DISABLE E ENABLE RET Input RET for no modification TIME 1 1 6us 2 406ns 3 20ns 1 RET Input 1 to set minimum measure time to 1 6 us TRGU D DISABLE E ENABLE M MULTI RET Command is terminated and new settings become valid Rev 1 0 09 00 page 246 of 423 HITACHI FILL 7 2 00 FILL Writes data to memory Command Format e Write FILLA lt start address gt A lt end address gt A lt nu
289. mand Gi TRACE command TRACE_SEARCH command As soon as the above command is terminated this command setting is validated and trace information acquisition starts In this case conditions that have been satisfied are all cleared Old trace information is also cleared At this time 8 TRACE CONDITION RESET is displayed Rev 1 0 09 00 page 328 of 423 HITACHI TRACE_CONDITION_A B C e Display Displays specified conditions as follows In addition to condition numbers character strings that were input for specifying conditions will be displayed as they were input If no trace condition is specified a blank is displayed TRACE_CONDITION_A RET A 1000 2000 R TCA2 S 5000 53FF ST TCA3 A 3000 4000 R TCA4 A 6000 7000 TCAS TCA6 TCA7 TCA8 e Cancellation Cancels conditions specified with the TRACE_CONDITION_A command TRACE CONDITION RET Note When conditions have already been set with the BREAK CONDITION command conditions cannot be set to the same channel number For example when conditions have already been set to BREAK CONDITION 1 no conditions can be set to CONDITION To set new conditions cancel previously set conditions When conditions have already been set with the BREAK CONDITION C or PERFORMANCE ANALYSIS command conditions cannot be set to the same channel number For example when conditions have already been set to BREAK
290. mber of bytes gt A lt data gt lt size gt AN RET lt start address gt Write start address lt end address gt Write end address lt number of bytes gt The number of bytes to be written lt data gt Data to be written Default is H 00 lt size gt Length of data to be written B 1 byte W 2 bytes L 4 bytes Default 1 byte N No verification Description e Write Writes data to the specified memory area Default value is H 00 After data is written it is also verified This command can therefore be used as a memory test If an error occurs the following message is displayed and processing is terminated FAILED AT xxxxxxxx WRITE READ zz z xxxxxxxx Error address yy y Write data hexadecimal and ASCII characters 77 7 Read data hexadecimal and ASCII characters Data can be written to only areas CSO to CS4 or the internal memory areas If Wis specified as lt size gt but the start address is odd the lowest bit is rounded down to the preceding even address If L is specified as lt size gt the lower bits are rounded down to become a multiple of four Writing never exceeds the specified lt end address gt Rev 1 0 09 00 page 247 of 423 HITACHI FILL Example To fill the entire area from addresses H O to H 6FFF with 1 byte data 00 F 0 6FFF 0 RET Rev 1 0 09 00 page 248 of 423 HITACHI GO 7 2 21 GO G Provides r
291. ment but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Compu
292. mnemonics and 7 2 4 specifies memory contents Disassembly DISASSEMBLE Disassembles memory contents 7 2 16 Execution time GO Measures GO command execution time 7 2 21 m remen Sa urement e Measures total run time e Measures execution time from BREAK_CONDITION_UBC2 condition satisfaction to BREAK_CONDITION_UBC1 condition satisfaction Test functions FILL Reads or writes the specified data to the 7 2 20 memory CHECK Tests SH7612 input signals 7 2 10 Command input Enables editing with cursor keys Copies immediately preceding line Copies operand of previous command RADIX Enables value input in binary octal 7 2 32 hexadecimal or ASCII characters Default can be specified Results display RESULT Displays emulation results 7 2 35 Rev 1 0 09 00 page 111 of 423 HITACHI Table 1 2 Command Type Command Others Emulation Functions cont Reference Function Section MOVE Transfers memory contents 7 2 28 MOVE TO RAM Memory to memory 7 2 29 e ROM user system memory to memory CONVERT Converts number display 7 2 13 e Displays in binary octal decimal hexadecimal or fixed point STATUS Displays emulator operating status 7 2 36 GO Monitors emulation 7 2 21 e Monitors emulation status at constant intervals and displays the emulation status RESET Inputs RES signal to SH7612 7 2 34 MODE Sets and displays the SH7612 operating 7 2 27 mode H
293. n the number of clock cycles CLK instead of time stamp 1 20 ns default at emulator shipment 2 1 6 us 3 52 us C Stores the settings as configuration information in the emulator flash memory Description e Specification Enables or disables trace information acquisition for DMA cycles e To enable trace information acquisition during DMA cycles TRACE MODE DMA E RET e To disable trace information acquisition during DMA cycles TRACE MODE DMA D RET Rev 1 0 09 00 page 334 of 423 HITACHI TRACE_MODE Enables or disables trace information acquisition for refresh cycles e To enable trace information acquisition during refresh cycles TRACE MODE REF E RET e To disable trace information acquisition during refresh cycles TRACE MODE REF D RET Specifies whether or not to generate a break when the trace buffer overflows e To generate a break when the trace buffer overflows TRACE_MODE OVFB E RET e To not generate a break when the trace buffer overflows TRACE_MODE OVFB D RET Specifies minimum time stamp unit e To acquire trace information on the number of clock cycles The time stamp is not acquired TRACE MODE 0 RET e To set the minimum time stamp unit to 20 ns TRACE MODE TIME I RET e To set the minimum time stamp unit to 1 6 us TRACE MODE TIME 2 RET e To set the minimum time stamp unit to 52 us TRACE MODE TIME 3 RET When the
294. nesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics all our customers Regarding the change of names mentioned in the document such as Hitachi Electric and Hitachi XX to Renesas Technology Corp The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003 These operations include microcomputer logic analog and discrete devices and memory chips other than DRAMs flash memory SRAMs etc Accordingly although Hitachi Hitachi Ltd Hitachi Semiconductors and other Hitachi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute any alteration to the contents of the document itself Renesas Technology Home Page http www renesas com Renesas Technology Corp Customer Support Dept April 1 2003 24 N SAS Renesas Technology Corp 434 NE SAS C 7 D m lt D c D SH7612 E8000 Emulator
295. ns set by the BREAK CONDITION B command are satisfied specifies whether a pulse is output from the trigger output pin of the emulator without a break 1 2 3 4 5 6 7 8 Outputs a trigger when the hardware break condition set by the specified channel of the BREAK CONDITION B command is satisfied without a break A Outputs a trigger when any hardware break condition set by the BREAK CONDITION B command is satisfied without a break D Break occurs but does not output a trigger default at emulator shipment Rev 1 0 09 00 page 241 of 423 HITACHI EXECUTION_MODE lt MON option gt Specifies time interval for execution status display 0 No display 1 Approximately 200 ms default at emulator shipment 2 Approximately 2 s WAIT option Specifies whether user wait is accepted E Enables user wait D Disables user wait default at emulator shipment CT option Specifies whether the cache access trace is enabled E Enables the cache access trace D Disables the cache access trace default at emulator shipment MB option Specifies whether the multi break is enabled E Enables the multi break D Disables the multi break default at emulator shipment UBC option Specifies whether UBC use by the user program is enabled E Enables UBC use D Disables UBC use default at emulator shipment C Stores the settings as configuration information in the emulator flash memory Description e Specification
296. nus one 0 H FFFFF S RET After allocation the size of the unused standard emulation memory is displayed REMAINING EMULATION MEMORY S xMB xMB Standard emulation memory When standard emulation memory is allocated to areas CSO to CS4 user system memory in the same space as the allocated area cannot be accessed correctly use memory in the user system specify U for the memory attribute cancel the write protection of standard emulation memory SW respecify S or U as the memory attribute Rev 1 0 09 00 page 264 of 423 HITACHI Display Displays the memory attribute of the area defined by lt start address gt and lt end address gt in the following format MAP lt start address gt lt end address gt RET XXXXXXXX XXXXXXXX V XXXXXXXX XXXXXXXX y a XXXXXXXX XXXXXXXX V XXXXXXXX XXXXXXXX y X RAM AREA XXXXXXXX XXXXXXXX b Y RAM AREA XXXXXXXX XXXXXXXX c INTERNAL I O xxxxxxxx XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX d REMAINING EMULATION MEMORY S xMB e a Address range and memory attribute Displays the addresses in both the cache and cache through areas to which standard emulation memory is allocated y Standard emulation memory attribute S Standard emulation memory in emulator SW Standard emulation memory in emulator with write protection b Internal X RAM address range c Internal Y RAM address range d Internal I O ad
297. o so will result in a FIRE HAZARD and will damage the PC interface board and peripheral devices or will result in PERSONAL INJURY Remove the cover of the PC and install the PC interface board in the ISA bus specification extension slot Tighten the screw after confirming that the PC interface cable can be connected to the board Interface cable PC case LS PC interface board P4 ISA bus specification extension slot Figure 3 12 Installing the PC Interface Board Rev 1 0 09 00 page 41 of 423 HITACHI 3 3 4 Connecting the E8000 Station to the PC Interface Board N WARNING Always switch OFF the emulator and user system before connecting or disconnecting any CABLES Failure to do so will result in a FIRE HAZARD and will damage the user system and the emulator or will result in PERSONAL INJURY The USER PROGRAM will be LOST Before using the emulator connect the E8000 station to the PC interface board with the PC interface cable supplied as shown in figure 3 13 TRC CONT LAN PC interface board PC interface cable E8000 station rear panel Figure 3 13 Connecting the E8000 Station to the PC Interface Board Rev 1 0 09 00 page 42 of 423 HITACHI 3 3 5 Connecting to a Host Computer AN WARNING Always switch OFF the emulator and user system before connecting or disconnecting any CABLES Failure to do so will result in a FIRE HAZARD and will damage the user system and the emulator or will result in PE
298. od 7 Enter the directory containing the INPUT SYSTEM DIRECTORY RET system file In this example A RET is entered 8 Enter Y RET to allow system LOAD E8000 SYSTEM FILE OK Y N Y RET program E8000 SYS to be loadedin INPUT FILE NAME E8000 SYS RET the emulator flash memory Then COMPLETED enter system program file name E8000 SYS Rev 1 0 09 00 page 79 of 423 HITACHI Operations 9 Enter Y RET to allow configuration file SHCNF761 SYS to be loaded in the emulator flash memory Then enter configuration file name SHCNF761 SYS 10 Enter Y RET to allow firmware file SHDCT761 SYS to be loaded in the emulator flash memory Then enter firmware file name SHDCT761 SYS 11 Enter N RET not to load the ITRON debugger 12 Enter N RET not to load the diagnostic program 13 Enter DIR RET to check whether the necessary files have been loaded 14 Enter Q RET to terminate the flash memory management tool 15 Installation is completed Rev 1 0 09 00 page 80 of 423 Display Message LOAD CONFIGURATION FILE OK Y N Y RET INPUT FILE NAME SHCNF761 SYS RET COMPLETED LOAD FIRMWARE FILE OK Y N Y RET INPUT FILE NAME SHDCT761 SYS RET COMPLETED LOAD ITRON DEBUGGER FILE OK Y N N RET LOAD DIAGNOSTIC FILE OK Y N N RET FM DIR RET FILE ID STATUS SYS OK CONF OK LAN NO FIRM OK TRON NO DIAG NO INI OK MON OK FM gt Q RET START E8000
299. of the board from lifting off the connector Alternately tighten the screws on both sides of the board Rev 1 0 09 00 page 25 of 423 HITACHI DCONT TRC CONT LAN Device control board TaTIVdvd I N m E8000 station rear panel Figure 3 2 Connecting the Device Control Board Rev 1 0 09 00 page 26 of 423 HITACHI 3 2 2 Connecting the EV Chip Board At shipment the EV chip board is packed separately from the E8000 station Use the following procedure to connect the EV chip board to the E8000 station or to disconnect them when moving the emulator N WARNING Always switch OFF the emulator and user system before connecting or disconnecting any CABLES Failure to do so will result in a FIRE HAZARD and will damage the user system and the emulator or will result in PERSONAL INJURY The USER PROGRAM will be LOST 1 Check that the emulator power switch is turned off Ensure that the power lamp on the left side of the E8000 station s front panel is not lit 2 Remove the AC power cable of the E8000 station from the outlet if the cable is connected to the outlet N WARNING When connecting the cable ensure that the upper A or lower B side of the cable does not lift off the connector Alternately tighten the screws on both sides of the cable while gradually pushing the cable toward the connector Failure to do so will result in a FIRE HAZARD damage the user system and emulator and
300. of the personal computer and the operating system Install copy the system disk to the personal computer connected to the emulator For details on the copy procedure refer to section 3 7 System Program Installation in Part I E8000 Guide Related Manuals HS7612EBK81H Manual HS7612EBH81H Manual Lan Board Manual Description Notes on Using the PC Interface Board HS6000EII01H SH Series C Compiler User s Manual SPARC SH Series Cross Assembler User s Manual SPARC H Series Linkage Editor User s Manual SPARC H Series Librarian User s Manual Integration Manager User s Manual Description Notes of Integration Manager SH7612 Definition File SH7612 E8000 Hitachi Debugging Interface User s Manual Notes 1 IBM is a registered trademark of International Business Machines Corporation 2 SPARC is a registered trademark of SPARC Intemational INC 3 Ethernet is a registered trademark of Xerox Corporation 4 Microsoft and Windows are registered trademarks of Microsoft Corporation Rev 1 0 09 00 page ii of xiv HITACHI Contents Part I E8000 Guide SECON T Uc tata etiaai hene todo tica eii ica A iet tb nud 3 I s ate pe oo ERU RI mn belle t e I PE Oei ette 3 1 2 Warnings 0 SERIO RU RII RO eie 6 13 Environmental Conditions e tee tice rp ipee tee n eerte 7 l4 Components ie cick Se AS i eet e A ee es a E 8 1 44 E8000 Emulator Station tee ck es eset omens 8 1 4 2 SH7612 Device Contr
301. ol Board and EV Chip Board sss 8 VA Bi ie Uem eram e EU ERES 9 Secti n 2 Components ecap oboe cM a 11 2 Emulator Hardware Components nennen nennen rennen ens 11 2 1 1 E8000 Station Components seen 12 2 1 2 Device Control Board Components nennen 15 2 1 3 EV Chip Board nennen nennen eene 16 2 2 Emulator 1 s 18 2 3 Syst m Configuration esee reete Ree Rete e Re eer d 20 2 3 1 System Configuration Using a LAN Interface sseseeeeeeee 20 2 3 2 System Configuration Using an RS 232C or Bidirectional Parallel Interface 21 2 3 3 System Configuration Using a PC Interface Board sss 22 Section 3 Preparation before tuiles 23 3 1 Emulator Preparation 5 ene ree e P De e ire IERI 23 3 2 Emulator Connection nece eene tae ee eee tpe ceste iets cite tete ete petet ione 25 3 2 1 Connecting the Device Control Board sese 25 3 2 2 Connecting the EV Chip Board esee nennen 27 3 2 3 Connecting the External Proben nenas 30 3 24 Selecting the Clock a eee ee eel 31 3 2 5 Connecting the System Ground 00 eee eene 34 3 3 3 System Connection
302. on H 0000 A breakpoint cannot be specified at this address 58 CANNOT SELECT EMULATOR An operating mode not supported with this CLOCK emulator was specified Check the operating mode 59 TOO MANY CHARACTERS Too many characters were specified Check the number of characters 60 ALL BREAKPOINT DELETED All software breakpoints specified with the BREAK or BREAK_SEQUENCE command were cancelled 61 CANNOT GET INTO PARALLEL The execution mode specified with the GO MODE command prevents the emulator from entering parallel mode Change the execution mode 62 LAN BOARD DISCONNECTION This command cannot be executed because the Rev 1 0 09 00 page 392 of 423 LAN board is not installed Install the optional LAN board and re enter the command HITACHI Table 10 1 Emulator Error Messages cont Error No 66 Error Message BACKGROUND INTERRUPT COMMAND STOPPED Description and Solution The BACKGROUND INTERRUPT command execution was terminated 67 LAN I O ERROR A LAN I O error occurred Refer to table 10 3 68 INVALID HOST NAME The specified host name is not defined in flash memory Define the host name with the emulator monitor command F flash memory management tool initiation 69 OUT OF CS AREA ADDRESS An attempt was made to allocate emulation memory to an area other than CSO to CS4 Check the specified address 71 MAPPING BOUND MUST BE IN 1MB UNITS Memory was allocated in 1 Mbyte units with th
303. on e Save Saves the specified memory contents in the specified load module type in a host computer file via the bidirectional parallel interface Use interface software IPW for the host computer An S type or HEX type load module can be saved An SYSROF type or ELF type load module cannot be saved Enter N before the command to request data receipt to the host computer N SAVE start address gt end address gt lt load module type gt lt file name RET When save is completed the start and end memory addresses are displayed as follows TOP ADDRESS start address gt END ADDRESS lt end address gt When the LF option is specified the emulator adds an LF code to the end of each record in addition to a CR code H OD in the S type or HEX type load module Rev 1 0 09 00 page 354 of 423 HITACHI SAVE Notes 1 Do not save data in the area other than the internal memory areas and areas CSO to CS4 2 Verification is not performed after save If the program must be verified use the VERIFY command For details refer to section 8 2 6 VERIFY Example To save memory contents in the address range from H 7000 to H 7FFF in host computer file F11 MOT in the S type load module format N SV 7000 7FFF F11 MOT RET TOP ADDRESS 00007000 END ADDRESS 00007FFF Rev 1 0 09 00 page 355 of 423 HITACHI VERIFY 8 2 6 VERIFY V Verifies memory contents against host
304. ons under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Re
305. oop program address is changed Rev 1 0 09 00 page 196 of 423 HITACHI BACKGROUND_INTERRUPT When one of the causes of termination listed in table 7 3 occurs during interrupt processing in command input wait state the interrupt processing stops there If an emulation command is executed in this state the following message is displayed after the emulation command execution In this case either change the interrupt processing program and enable user interrupts or disable user interrupts 66 STOPPED THE BACKGROUND INTERRUPT Do not use this command when using a system such as an OS that does not return from the user interrupt processing to the routine where the interrupt has occurred If used execution does not return to the loop program for accepting user interrupts even after the user interrupt processing has terminated Do not generate a reset exception when user interrupts are enabled If generated the user program is initiated and execution does not return to the loop program for accepting user interrupts During user interrupt processing in command input wait state the software breakpoints set with the BREAK or BREAK_SEQUENCE command and hardware break conditions become invalid During user interrupt processing in command input wait state no trace information is acquired Rev 1 0 09 00 page 197 of 423 HITACHI BACKGROUND_INTERRUPT Examples 1 To specify the executing addre
306. opyright C Hitachi Ltd 1995 Licensed Material of Hitachi Ltd TESTING RAM 0123 Rev 1 0 09 00 page 61 of 423 HITACHI 14 If no error occurs the emulator waits for emulator monitor command START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ Refer to section 3 6 1 Emulator Monitor Initiation for details on operations after emulator power on and section 3 8 E8000 System Program Initiation for details on emulator system initiation 3 5 2 Power On Procedures for RS 232C Interface Figure 3 24 shows the power on procedures when the RS 232C interface is used 1 Turn off to the right S7 and S8 in SW1 on the E8000 station rear panel 2 Run interface software IPW EXE on the host computer connected via the RS 232C interface 3 Power on the E8000 station Internal system test is executed 4 Initiation messages are displayed Test result OK 5 Emulator monitor command input wait state 5 Error message is displayed Figure 3 24 Power On Procedures for RS 232C Interface Rev 1 0 09 00 page 62 of 423 HITACHI Refer to section 3 6 1 Emulator Monitor Initiation for details on operations after emulator power on and section 3 8 E8000 System Program Initiation for details on emulator system initiation 3 6 Emulator Monitor Commands 3 6 1 Emulator Monitor Initiation The emulator supports the four monitor commands listed in table
307. or station is placed in a secure position so that it does not move and impose stress on the user interface during use Figure C 7 Examples of Securing the Emulator Station 2 Make sure the power supply is off Before connecting the EV chip board to the user system check that the emulator and the user system are off 3 Connect the Uvcc to the user system power The emulator monitors the Uvcc pin pins 6 11 19 26 34 42 50 58 73 86 99 107 111 117 125 138 151 155 and 166 for HS7612EBH81H and pin 51 on USER IF2 for HS7612EBK81H to determine whether the user system is on or off Accordingly after connecting the user system to the emulator be sure to supply power to the Uvcc pin Otherwise the emulator assumes that the user system is not connected Rev 1 0 09 00 page 421 of 423 HITACHI H 00000000 H 00000100 H 02000000 H 04000000 H 06000000 H 08000000 H 0A000000 H 1000E000 H 10010000 H 1001E000 H 10020000 H 20000000 H 22000000 H 24000000 H 26000000 H 28000000 H 2A000000 H 40000000 H 48000000 H 60000000 H 80000000 H C0000000 H C0001000 H FFFF8000 H FFFFCO00 H FFFFFCOO0 H FFFFFFFF Appendix D Memory Map Exception vector table 256 bytes CS0 cache area 32 Mbytes CS1 cache area 32 Mbytes CS2 cache area 32 Mbytes CS3 cache area 32 Mbytes CS4 cache area 32 Mbytes Internal X RAM 8 kbytes Internal Y RAM 8 kbytes Reserved CS0
308. ormally loaded on and NO for not loaded Example To display system file loading status FM gt DIR RET lt FILE ID gt lt STATUS gt SYS OK CONF OK LAN NO FIRM OK TRON NO DIAG OK INI OK MON OK FM Rev 1 0 09 00 page 66 of 423 HITACHI LH LH LH Defines the host name and IP address of the host computer Command Format e Definition LH RET Description e Definition Defines the host name and IP address of the host computer Enter the host name and IP address as follows after the specified number is entered and the emulator prompts them PLEASE SELECT NO 1 9 L E Q X definition number RET 01 HOSTNAME xxxxxx host name RET 01 IP ADDRESS xxx Xxx XXX XXX IP address RET e Display Entering L RET displays the list of the defined host computer e Initiation Entering E RET saves the new specifications in the emulator flash memory and initiates the LAN board Entering Q RET saves the new specifications in the emulator flash memory without initializing the LAN board and terminates LH command execution Entering X RET terminates LH command execution without saving the new specifications Rev 1 0 09 00 page 67 of 423 HITACHI LH Example To define the host name of the host computer as host and its IP address as 128 1 1 1 FM gt LH RET PLEASE SELECT NO 1 9 L E Q X 1 RET 01 HOST NAME xxxxxx host RET 01 IP ADDRESS xxx xxx xxx xxx 128 1 1 1
309. ound into a bundle Check for the number of cables bound into a bundle and the colors for connectors when connecting the cables Make sure the connector shapes and numbers are correctly matched when connecting trace cables to the station to EV chip interface connectors Failure to do so will damage the connectors Rev 1 0 09 00 page 28 of 423 HITACHI 4 Connect the trace cables to the station to EV chip board interface connectors CN1 CN2 and CN3 on the EV chip board Confirm that each trace cable connected to a connector on the E8000 station is also connected to its corresponding station to EV chip board interface connector on the EV chip board Connect the cables using the same method as in step 3 Figure 3 4 shows how to connect the trace cables to the EV chip board interface connectors CNS blue CN2 yellow Trace cable ON n Trace cable CN3 Trace cable CN2 Station to EV chip board Wa EEE interface connector CN1 x Station to EV chip board E interface connector CN3 Station to EV chip board User system interface connector CN2 Figure 3 4 Connecting Trace Cables to the EV Chip Board Note For the connection between the EV chip board and the user system refer to section 3 Connecting the EV Chip Board to the User System in the Evaluation Chip Board HS7612EBHS81H HS7612EBK81H Description Notes Rev 1 0 09 00 page 29 of 423 HITACHI 3 2 3 Connecting the External Probe
310. ower USER SYSTEM NOT READY NO CLOCK is displayed and the emulator system program stops To operate the emulator again restart the system program e During command input wait state When the user system is turned off Vcc is 2 65 V or lower USER SYSTEM NOT READY NO CLOCK is displayed and the SH7612 operating clock is switched to the internal 15 MHz clock and the emulator waits for command input A RES signal is input to the SH7612 and the internal registers are initialized USER SYSTEM NOT READY NO CLOCK is displayed after the user system has been turned off and one command has been executed When the clock stops Vcc is 2 65 V or lower USER SYSTEM NOT READY NO CLOCK is displayed and the emulator system terminates Restart the emulator in order to continue emulation Rev 1 0 09 00 page 149 of 423 HITACHI 1 11 Assembly Function 111 1 Overview The ASSEMBLE command enables line assembly as shown in figure 1 28 User memory Write to BN ASSEMBLE memory command gt Assembly language source input Figure 1 28 Assembly Function Line assembly Assembly language source is input from the console line by line Refer to section 7 2 4 ASSEMBLE for command initiation instructions Rev 1 0 09 00 page 150 of 423 HITACHI 1112 Input Format The basic instruction format is as follows instruction mnemonic gt A lt operand gt A lt comment gt RET lt instruction mnemonic gt lt operand gt
311. owing modes e Cycle reset mode R option of GO command e Time interval measurement mode or I2 option of GO command 1 4 Break Function The following four methods are useful to stop emulation The break function can be used regardless of the SH7612 s operating mode e Hardware break Caused by the SH7612 s signal status as specified e Software break Caused by a program counter e Forced break Caused by pressing the CTRL C keys or the BREAK key e Write protect guarded break Caused by writing to a write protected area or accessing guarded area Rev 1 0 09 00 page 118 of 423 HITACHI 1 4 1 Hardware Break A hardware break can be specified using the BREAK_CONDITION_UBC command or BREAK_CONDITION_A B C commands Specifiable break conditions are listed in table 1 4 The BREAK CONDITION UBC command uses the User Break Controller UBC in the SH7612 and therefore user programs using the UBC cannot be debugged Table 1 4 Specifiable Hardware Break Conditions BREAK BREAK BREAK BREAK BREAK CONDITION CONDITION CONDITION _ CONDITION _ CONDITION Condition UBC2 A 1 to 8 B 1 to 8 C 1 to 8 Address O O condition Datacondition condition O Read write O O O Bus cycle specification Probe condition O O interrupt condition Pass count O O O Delay count specification Sequential O break
312. pecify one before connection Rev 1 0 09 00 page 370 of 423 HITACHI Example To connect the emulator to host computer HOST via the FTP interface FTP HOST1 RET Username USER1 RET Password x x RET login command success gt Rev 1 0 09 00 page 371 of 423 HITACHI 9 3 7 LAN LAN Displays emulator IP address Command Format e Display LAN RET Description e Display Displays the emulator s internet IP address stored in the emulator in the following format LAN RET E8000 INTERNET ADDRESS xxx xxx xxx xxx a a Emulator IP address Specify the emulator IP address with the emulator monitor command L Example To display the emulator IP address LAN RET E8000 INTERNET ADDRESS 128 1 1 10 Rev 1 0 09 00 page 372 of 423 HITACHI LAN_HOST 9 3 8 LAN_HOST LH Displays the names and IP addresses of all defined host computers Command Format Display LAN_HOST RET Description e Display Displays the LAN host computer names and internet addresses defined in the emulator flash memory in the following format LAN_HOST RET NO HOSTNAME lt IPADDRESS gt NO lt HOST NAME gt IP ADDRESS gt 01 XXXXXX XXX XXX XXX XXx 02 XXXXXX XXX XXX XXX XXX 03 XXXXXX XXX XXX XXX Xxx 04 XXXXXX XXX XXX XXX XXX 05 XXXXXX XXX XXX xXx xxx 06 XXXXXX XXX XXX XXX XXX 07 XXXXXX XXX XXX XXX XXx 08 XXXXXX XXX XXX XXX X
313. pply refer to section 1 3 Environmental Conditions 6 When moving the emulator take care not to vibrate or otherwise damage it 7 After connecting the cable check that it is connected correctly For details refer to section 3 Preparation before Use 8 Supply power to the emulator and connected parts after connecting all cables Cables must not be connected or removed while the power is on 9 For details on differences between the SH7612 and the emulator refer to section 2 Differences between the SH7612 and the Emulator in Part II Emulator Function Guide Rev 1 0 09 00 page 6 of 423 HITACHI 1 3 Environmental Conditions CAUTION The following environmental conditions must be satisfied when using the emulator Failure to do so will damage the user system and the emulator The USER PROGRAM will be LOST Observe the conditions listed in table 1 1 when using the emulator Table 1 1 Environmental Conditions Specifications Temperature Operating 10 to 35 C Storage 10 to 50 C Humidity Operating 35 to 80 RH no condensation Storage 35 to 80 RH no condensation Vibration Operating 2 45 m s max Storage 4 9 m s max Transportation 14 7 m s max AC input power Voltage AC100 120 V 200 240 V 10 Frequency 50 60 Hz Power consumption 200 VA Ambient gases There must be no corrosive gases present Rev 1 0 09 00 page 7 of 423 HITACHI 14 Components The emulator consists o
314. r Memory corresponding to the allocated attributes can be accessed with user program or emulator commands Rev 1 0 09 00 page 160 of 423 HITACHI 3 3 Other Functions 3 3 1 Low Power Mode Sleep and Standby For reduced power consumption the SH7612 has sleep and standby modes The sleep and standby modes are switched using the SLEEP instruction These modes can be cleared with either the normal clearing cause or with the break condition satisfaction including BREAK or CTRL C key input and the program breaks Trace information is not acquired in the sleep and standby modes Notes 1 When restarting after a break the user program will restart at the instruction following the SLEEP instruction 2 During sleep mode if the user accesses or modifies the memory in parallel mode the sleep mode is cleared and the user program execution continues from the instruction following the SLEEP instruction 3 3 2 Interrupts During emulation the user can interrupt the SH7612 e When an interrupt is disabled by the BACKGROUND_INTERRUPT command If an interrupt occurs while the emulator is waiting for command input the interrupt is not processed However if an edge sensitive interrupt of internal and external interrupts occurs while the emulator is waiting for command input the emulator latches the interrupt and executes the interrupt processing routine when the GO command is entered e When an interrupt is enabled by the BACKGROUND_INTERR
315. r against the memory contents FTP HOST1 RET Username USER1 RET Password RET login command success FIP gt LV F11 ABS RET TOP ADDR ESS END ADDRI gt ESS VERIFYING ADDRESS 00000C00 00000000 00000FFF HITACHI Rev 1 0 09 00 page 379 of 423 LS 9 3 12 LS LS Displays the host computer directory connected via the FTP interface Command Format e Display LS A directory name RET directory name Name of host computer directory Default Current directory of the host computer Description e Display Displays the specified directory contents in the host computer connected via the FTP interface If directory name is omitted the current directory contents are displayed Note that the directory name must be specified according to the connected host computer format Example To display the contents of the host computer current directory FTP gt LS RET abc s XYZ FTP gt Rev 1 0 09 00 page 380 of 423 HITACHI 9 3 13 OPEN Connects the host computer to the FTP interface Command Format e FTP interface connection OPEN lt host name gt RET lt host name gt Name of the host computer to be connected via the FTP interface The host computer name must be already defined with the flash memory management tool Description e FTP interface connection Connects the emulator to the specified hos
316. r command format description RET Pressing the RET key Although italic and bold characters are used throughout this manual to indicate input it is not used in the command format parts of these descriptions HITACHI Rev 1 0 09 00 page 185 of 423 lt register gt 7 2 1 lt register gt lt register gt Modifies and displays register contents Command Format e Modification direct mode lt register gt A lt data gt RET e Modification interactive mode lt register gt RET lt register gt System register control register general register or DSP register to be modified or displayed System registers PC PR MACH MACL Control registers SR VBR RS RE MOD General registers R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP DSP registers DSR AOG AO A1G Al MO MI XO X1 YO Y1 data The value to be set in the specified register Description e Modification Direct mode Sets the specified value in the specified register SP can be specified instead of R15 MOD can be specified separately as MS and ME 16 bit unit each register data RET Interactive mode If no data is specified on the command line with register register modification is performed in interactive mode In this case the emulator displays the current register value and requests its modification Registers are processed in the following order and processing
317. r disconnecting any CABLES Failure to do so will result in a FIRE HAZARD and will damage the user system and the emulator or will result in PERSONAL INJURY The USER PROGRAM will be LOST System configuration examples are shown below Rev 1 0 09 00 page 45 of 423 HITACHI Ethernet Interface The LAN board of the emulator has a 15 pin D SUB connector for the Ethernet transceiver cables Figure 3 14 shows an example of the Ethernet system configuration Use commercially available Ethernet transceivers and transceiver cables Table 3 6 shows a recommended transceiver and transceiver cable Note When using the LAN interface refer to section 3 5 1 Power On Procedures for LAN Interface and set the IP address Ethernet transceivers Ethernet LAN board DCONT __TRC__CONT_LAN I 9 o S 1 Workstation E8000 station rear panel Figure 3 14 Ethernet Interface Table 3 6 Recommended Transceiver and Transceiver Cable Item Product Type Manufacturer Transceiver HBN 200 series Hitachi Cable Ltd Transceiver cable HBN TC 100 Hitachi Cable Ltd For setting up the Ethernet interface refer to the LAN board user s manual Rev 1 0 09 00 page 46 of 423 HITACHI Cheapernet Interface The LAN board of the emulator incorporates a transceiver and a BNC connector for a Cheapernet interface Figure 3 15 shows an example of the Cheapernet system configuration Use a commercially ava
318. rams via the parallel interface IPW EXE is a file containing interface software that runs on Microsoft Windows version 3 1 or Windows95 and must be installed to the host computer memory Rev 1 0 09 00 page 75 of 423 HITACHI 3 7 2 Installation To use the emulator the E8000 system program must be installed in the emulator flash memory Load the E8000 system program to flash memory with the system program writing file or with the flash memory management tool using the emulator monitor commands Automatic System Program Load by Bidirectional Parallel Interface If the emulator is connected to the host computer via the bidirectional parallel interface and the E8000 system disk is inserted in drive A of the host computer the E8000 system program can be automatically loaded with the system program writing file SETUP CC in the following procedures It takes approximately one minute Operations Display Message 1 Initiate IPW in the E8000 system floppy disk 2 Power on the emulator For details on the power on procedures refer to section 3 5 2 Power On Procedures for RS 232C Interface 3 Emulator monitor command prompt START E8000 S START E8000 F FLASH MEMORY TOOL L SET LAN PARAMETER T START DIAGNOSTIC TEST S F L T _ 4 Enter lt A SETUP CC RET inthe s F L T lt A SETUP CC RET monitor command input wait state 5 After the system program writing START E8000 file completes loading the system S START E8000 program th
319. re this symbol can be repeated Indicates a space Used only for command format description Pressing the RET key Although italic and bold characters are used throughout this manual to indicate input it is not used in the command format sections of these descriptions Rev 1 0 09 00 page 364 of 423 HITACHI ASC 9 3 1 ASC ASC Specifies the file type as ASCII Command Format e Setting ASC RET Description e Setting Specifies the file type as ASCII in the FTP interface To load an SYSROF type load module file binary must be specified with the BIN command Example To set the file type as ASCII in the FTP interface gt ASC RET asc command success FTP gt Rev 1 0 09 00 page 365 of 423 HITACHI BIN 9 3 2 BIN BIN Specifies the file type as binary Command Format e Setting BIN RET Description e Setting Specifies the file type as binary in the FTP interface This specification is required to transfer files with the LAN_LOAD LAN_SAVE or LAN_VERIFY command To load or verify an SYSROF type load module file binary must be specified with this command Otherwise a transfer error will occur At emulator initiation binary is the default setting Example To set the file type as binary in the FTP interface FTP gt BIN RET bin command success FTP gt Rev 1 0 09 00 page 366 of 423 HITACHI 9 3 3 BYE BYE Terminates the FTP interface
320. reset point are ignored during STEP and STEP OVER command execution Therefore the pass count is not updated during STEP and STEP OVER command execution Rev 1 0 09 00 page 219 of 423 HITACHI BREAK_SEQUENCE If the pass points have not been passed in the specified sequence break checking begins again from the first pass point When the specified reset point is passed break checking begins again at the first pass point even if the remaining pass points are then passed in the assigned sequence When pass points or a reset point are specified the emulator temporarily stops emulation and analyzes the pass sequence at each point Therefore realtime emulation is not performed When execution starts at the address set with the BREAK SEQUENCE command immediately after execution starts the BREAK CONDITION UBC2 command settings are invalidated Therefore even though a BREAK CONDITION UBC2 command setting is satisfied immediately after execution start GO command execution does not terminate Ifa pass point is set at a slot delayed branch instruction instead of terminating program execution a slot illegal instruction interrupt occurs Make sure not to set a pass point at a slot delayed branch instruction software breakpoint is set at an address in either a cache area or cache through area break will occur in both areas e Display Displays specified pass points and reset point as follows
321. s ASSEMBLE lt address gt RET XXXXXXXX lt disassemble display XXXXXXXX lt subcommand gt RET XXXXXXXx lt subcommand gt RET a b a Address When an odd address is specified it is rounded down to an even address b Subcommand Input the contents shown in table 7 2 Rev 1 0 09 00 page 192 of 423 HITACHI ASSEMBLE The subcommands listed in table 7 2 can be used with the ASSEMBLE command Table 7 2 Subcommand lt assembly language statement gt Subcommands for Line Assembly Description Assembles the input line statement into machine code and writes it to the displayed address address 1 gt A lt address 2 gt Disassembles instructions from lt address 1 gt to lt address 2 gt and displays them If lt address 2 gt is omitted the first 16 instructions from lt address 1 gt are displayed If only a slash is input the contents from the ASSEMBLE command start address to the current address 1 are disassembled RET only Increments the address odd address 1 even address 2 and re enters subcommand input wait state Decrements the address odd address 1 even address 2 and re enters subcommand input wait state Terminates the ASSEMBLE command Even if an odd address is specified machine codes are written to memory In that case the following warning message is displayed 82 0DD ADDRESS Line assembly with th
322. s If a break has occurred during user interrupt processing and the loop program has been stopped the register values at termination and the cause of termination are displayed in the following format BACKGROUND_INTERRUPT RET USER INTERRUPT x LOOP PROGRAM ADDRESS yyyyyyyy cause of termination X User interrupt accepting mode E User interrupts are enabled the loop program is being executed D Userinterrupts are disabled the loop program has been stopped S A break has occurred during user interrupt processing the loop program has been stopped yyyyyyyy Address of loop program for accepting user interrupts cause of termination Register values and the cause of termination listed in table 7 3 at loop program termination displayed only when S is selected above Rev 1 0 09 00 page 195 of 423 HITACHI BACKGROUND_INTERRUPT Display format is as follows PC 00005C60 SR 00000000 000000000000 00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000FFE00 5 00000000 ____ A0G 00 0 00000000 M0 00000000 X0 00000000 Y0 00000000 A1G 00 A1 00000000 M1 00000000 X1 00000000 Y1 00000000 lt cause of termination gt T
323. s executed the execution state display is interrupted Subroutine Step Execution When executing a JSR BSR or BSRF instruction the emulator treats the called subroutine as a single step All other instructions are executed one at a time This function is valid only in the user RAM or the emulation memory area 1 6 2 Setting Display Information The user can set the information displayed at each instruction using the STEP INFORMATION command For details refer to section 7 2 38 STEP INFORMATION 1 6 3 Termination of Single Step Function The single step function stops after executing a specified number of steps from the specified start address or the current PC address The user can stop execution by specifying a stop address However the specified address must be at the start of an instruction If the second byte of an instruction is specified not the start of an instruction the single step function will not stop and execution continues for the specified number of steps Rev 1 0 09 00 page 137 of 423 HITACHI 17 Execution Time Measurement 1 7 1 Execution Time Measurement GO to BREAK Time The user can measure the user program execution time by specifying with the GO command In this mode the emulator measures the total execution time from when the user program is started with the GO command to when it is stopped by a break Program execution starts Time measurement The break condition is O The break condition
324. s that execution has been terminated because the BREAK key was entered Rev 1 0 09 00 page 92 of 423 HITACHI 4 2 6 Setting a Software Breakpoint Execution of the GO command can be stopped immediately before executing a particular address by setting a software breakpoint by the following procedures Operations 1 Enter BREAK 1001010 RET to terminate the GO command immediately before executing the instruction at address H 1001010 Restart program execution from address H 1001000 This can be done in two ways one is to first set the program counter to H 1001000 then enter the GO command to execute the program and the other is to enter the start address directly The GO command execution terminates immediately before the instruction at address H 1001010 is executed The data shown on the right is displayed BREAKPOINT shows that the GO command execution was terminated due to a software breakpoint Display Message BREAK 1001010 RET PC 1001000 RET GO RET or GO 1001000 RET PC 01001010 SR 000000F0 000000000000 GBR 00000000 VBR 00000000 MACH 00000000 MACL 0000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000001 000000FF 00000011 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 DSR 200000000 X X RR RR RK RK KKK KK cOB A0G 00 0 00000000 0 00000000 x0 00000000 0 0000 A1G 00 1 00000000 1 00000000 1 00000000 1 0000 RUN TIME D 0000H 00M 00S 0000
325. s through which the data is accessed For bus lines through which no data is accessed asterisks are displayed d Memory area type Table 7 26 MA Display Display Description IO Internal I O area access INT Internal area access EXT CS0 to CS3 area access including reserved area access e Read write type Table 7 27 R W Display Display Description R Data read Data write f MCU status Table 7 28 STS Display Display Description PRG Instruction fetch cycle including PC relative data access cycle DAT Data access cycle except for PC relative data access cycle DMA Internal DMAC execution cycle VCF Vector fetch cycle REF Refresh cycle Rev 1 0 09 00 page 314 of 423 HITACHI g IRLO to IRL3 signal level IRL x3 x2 1 x0 x3 IRL3 signal status 0 Low level x2 IRL2 signal status 1 High level 1 IRL signal status x0 IRLO signal status h NMI signal level 0 low level 1 high level i RESET signal level 0 low level 1 high level j BREQ signal level 0 low level 1 high level k Vcc voltage Table 7 29 Voltage Display Display Description 0 Vcc voltage is 2 65 V or less the MCU is not operating correctly 1 Vcc voltage is more than 2 65 V D External probe signal level 0 low level 1 high level m Time stamp display Displayed only when time stamp display is enabled with the TIME option TIM
326. s to be delayed slightly Also the pull up resistors will change high impedance signals to high level signals Adjust the user system hardware accordingly Refer to section 4 User System Interface The user break controller UBC and Hitachi user debugging interface H UDI in SH7612 cannot be used with this emulator The emulator for the SH7612 can use an operating frequency of 66 MHz or lower Note however that the emulator cannot use an operating frequency higher than 66 MHz If the operating frequency is set to higher than 66 MHz correct emulation cannot be guaranteed Rev 1 0 09 00 page 155 of 423 HITACHI Rev 1 0 09 00 page 156 of 423 HITACHI Section 3 SH7612 Function Support The SH7612 has seven clock modes However operation using the crystal oscillator CKPREQ CKM 1 is not supported in operating modes 0 to 3 This section describes how the emulator supports the SH7612 functions Note The crystal oscillator bonded to the crystal oscillator terminals 0 and X1 on the evaluation chip board EV chip board is connected to an oscillator within the EV chip board to perform clock oscillation This clock source is input to the EXTAL pin of the SH7612 Note that the crystal oscillator cannot be directly connected to the EXTAL and XTAL pins of the SH7612 3 1 Operating Mode Setting The user selects the operating mode and CSO area bus width for the emulator with the MODE command as shown in table 3 1 For detai
327. se mask specification examples Example The following condition is satisfied when address 4000000 is the address condition and bit 0 is zero in the byte data condition TRACE CONDITION A H 4000000 D B 0 S RET Table 7 35 Mask Specifications TRACE CONDITION Radix Mask Unit Example Mask Position Allowed Condition Binary 1 bit B 01 1010 Bits 0 and 5 are masked Data D WD LD IRL or PRB Hexa 4 bits H F 50 Bits 15 to 8 are masked Data D WD LD IRL or decimal PRB Rev 1 0 09 00 page 327 of 423 HITACHI TRACE_CONDITION_A B C In parallel mode this command is executed as follows Parallel mode is entered by the RET key or the trace stop condition is satisfied e This command setting is invalid during parallel mode e No trace information is acquired e soon as parallel mode is terminated this command setting is validated and trace information acquisition starts In this case conditions that have been satisfied are all cleared and the conditions are rechecked from the beginning Old trace information is also cleared At this time SIITRACE CONDITION RESET is displayed Parallel mode is entered by the SPACE key e This command setting is valid e Trace information is acquired e During the following command execution this command setting is invalid and no trace information is acquired 1 A condition is newly set with the TRACE CONDITION com
328. sed in bytes words or longwords respectively This condition can be masked Read Write condition R Read W Write The condition is satisfied in a read cycle R is specified or a write cycle W is specified Access type DAT Execution cycle DMA DMA cycle VCF Vector fetch cycle REF Refresh cycle Default All bus cycles described above including program fetch cycle The condition is satisfied when the bus cycle type matches the specified type Multiple access types cannot be specified either select one of the access types on the left or specify none External probe condition PRB lt value gt Rev 1 0 09 00 page 338 of 423 The condition is satisfied when all of the emulator s external probe signals match the specified values Specify lt value gt as 1 byte data Each bit corresponds to a probe number as follows 3 2 1 0 Bit x x x x lt Specified value 4 3 2 1 lt Probe number x 0 Low level 1 High level This condition can be masked HITACHI TRACE_SEARCH Table 7 38 Specifiable Conditions TRACE_SEARCH cont Item and Input Format Memory type condition INT Internal area Internal I O area EXT External area CAC Cache Description Searches for a bus cycle in which the specified memory area type is accessed External interrupt condition 1 NMI L or NMI H The condition is satisfied when the NMI signal matches the specifi
329. sk in 1 bit or 4 bit units can be specified for address data IRL or PRB condition When a bit is masked the condition is satisfied irrespective of its bit value To implement the mask specify each digit to be masked at input as an asterisk Table 7 39 shows mask specification examples Example 1 To search for a bus cycle where bit 0 is zero in the byte data condition TRACE SEARCH A 4000000 D B Q RET Example 2 To search for a bus cycle where IRL2 is zero in the IRL condition IRL pins other than IRL2 are ignored TRACE SEARCH IRL B 0 RET Table 7 39 Mask Specifications TRACE SEARCH Radix Mask Unit Example Mask Position Allowed Condition Binary 1 bit B 01 1010 Bits O and 5 are masked Address data D WD LD IRL or PRB Hexa 4 bits H F 50 Bits 15 to 8 are masked Address data D WD LD decimal IRL or PRB The display contents are the same as the bus cycle display of the TRACE command However instruction mnemonics are not displayed no trace information satisfies the specified condition 45 NOT FOUND is displayed If there is no trace information in the trace buffer 39 BUFFER EMPTY is displayed Rev 1 0 09 00 page 341 of 423 HITACHI TRACE_SEARCH Examples 1 To search for bus cycles where data is written to addresses from H 1000000 to H 1000050 TS A 1000000 1000050 W RET BR AB DB RW ST IRL NMI RES VCC PRB
330. sked Data D WD LD IRL or PRB decimal Rev 1 0 09 00 page 209 of 423 HITACHI BREAK_CONDITION_A B C Ifa hardware break condition is satisfied emulation may stop after two or more instructions have been executed e Display Displays specified conditions The character string that was input for specifying conditions will be displayed as it was input If the break number is omitted all specified break conditions for that break type are displayed For BREAK_CONDITION_B1 B8 conditions satisfaction count since the previous break condition was satisfied is displayed For BREAK CONDITION B7 conditions delay count since the previous break condition was satisfied is displayed no break condition is specified a blank is displayed BREAK CONDITION B RET BCBI Bl break setting BCB2 B2 break setting BCB3 B3 break setting BCBA B4 break setting BCBS B5 break setting BCB6 B6 break setting BCB7 B7 break setting BCBS BS break setting Rev 1 0 09 00 page 210 of 423 HITACHI BREAK_CONDITION_A B C e Cancellation Cancels specified conditions When break numbers to 8 are omitted all break conditions are cancelled Cancels all conditions for the BREAK CONDITION A command BREAK CONDITION A RET Cancels BREAK CONDITION AI conditions BREAK CONDITION RET Note When conditions have already been set with the TR
331. ss count in area access count measurement mode or subroutine call count in subroutine call count measurement mode g Subroutine maximum execution time only for the PERFORMANCE_ANALYSIS 1 2 3 4 command in subroutine execution time measurement mode 2 I2 h Subroutine minimum execution time only for the PERFORMANCE_ANALYSIS 1 2 3 4 command in subroutine execution time measurement mode 2 I2 i Subroutine average execution time only for the PERFORMANCE_ANALYSIS 1 2 3 4 command j Total run time displayed as hour M minutes S second US microsecond and NS nanosecond Note According to the TIME option of the EXECUTION_MODE command the maximum measurable time is 488 124 or 6 hours where the minimum measurement time is 1 6 us 406 ns or 20 ns respectively When conditions have already been set with the BREAK_CONDITION_C or TRACE CONDITION C command conditions cannot be set to the same channel number For example when conditions have already been set to BREAK CONDITION or TRACE CONDITION no conditions can be set to PERFORMANCE ANALYSISI To set new conditions cancel previously set conditions Examples 1 To measure the execution time of subroutines SUBB H 5000 to H 7FEO and SUBD H 20100 to H 2FFFF and initialize the performance measurement data PA2 SUBB 5000 7FEO I2 RET PA7 SUBD 20100 2FFFF SC 30000 30060 RET PA I RET Rev 1 0 09 00 page 286 of 423 HITACHI PERFOR
332. ss of the loop program for accepting user interrupts to H FFFC and begin to accept user interrupts in command input wait state BI E FFFC RET 2 To display the current user interrupt accepting mode in command input wait state BI RET USER INTERRUPT S LOOP PROGRAM ADDRESS 0000FFFC PC 00005C60 SR 00000000 000000000000 00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 OO0FFEO0 DSR 200000000 X X X X XXX XXX kk COB A0G 00 A0 00000000 0 00000000 X0 00000000 0 00000000 A1G 00 A1 00000000 1 00000000 X1 00000000 1 00000000 ILLEGAL INSTRUCTION Rev 1 0 09 00 page 198 of 423 HITACHI 7 2 6 BREAK BREAK B Sets displays and cancels software breakpoints Command Format e Setting BREAKA lt software breakpoint to be set gt lt software breakpoint to be set gt RET e Display BREAK RET e Cancellation BREAK A lt software breakpoint to be cancelled gt lt software breakpoint to be cancelled gt RET software breakpoint to be set address A number of times gt address Software breakpoint address number of times How many times the specified software breakpoint is to be passed H 1 to H FFFF Default H 1
333. t computer via the FTP interface This command can also be used to change the host computer connected to the emulator To change the host computer first disconnect the current host computer using the CLOSE command and then connect the new host computer using this command FTP gt OPEN host name gt RET Username a RET Password b RET login command success FTP gt a Enter user name b Enter password Note A password must be specified before a host computer can be connected via the FTP interface If no password is specified specify one before connection Rev 1 0 09 00 page 381 of 423 HITACHI Example To disconnect the emulator from the current host computer and connect it to the new host computer HOSTI FTP CLOSE RET bye command success FTP gt OPEN HOST1 RET Username USER1 RET Password RET login command success FTP Rev 1 0 09 00 page 382 of 423 HITACHI PWD 9 3 14 PWD PWD Displays the current directory name of the host computer connected via the FTP interface Command Format e Display PWD RET Description e Display Displays the current directory name of the host computer connected via the FTP interface Example To display the current directory name of the host computer connected via the FTP interface FTP gt PWD RET usr e8000 FTP gt Rev 1 0 09 00 page 383 of 423 HITACHI ROUTER 93 15 ROUTER RTR
334. t modes 1 the minimum execution time from the point when the BREAK CONDITION UBC 2 condition is satisfied until the BREAK CONDITION UBC condition is satisfied is displayed Rev 1 0 09 00 page 253 of 423 HITACHI GO e In time interval measurement modes 1 the average execution time from the point when the BREAK CONDITION UBC2 condition is satisfied until the BREAK CONDITION UBC condition is satisfied is displayed Note The average execution time is obtained by dividing an execution time by the execution count Accordingly if emulation stops within the period from BCU2 condition satisfaction to BCU1 condition satisfaction a correct average execution time will not be displayed f User program execution time in decimal According to the TIME option of the MODE command the maximum measurable time is 488 124 or 6 hours where the minimum measurement time is 1 6 us 406 ns or 20 ns respectively If the p eriod exceeds the maximum measurable time it is displayed as g Cause of termination as listed in table 7 17 Rev 1 0 09 00 page 254 of 423 HITACHI Table 7 17 Message BREAK CONDITION UBC1 GO Causes of GO Command Termination Cause of Termination A break condition specified with the BREAK_CONDITION_UBC1 command was satisfied BREAK CONDITION UBC2 A break condition specified with the BREAK_CONDITION_UBC2 command was satisfied BREAK
335. tails on the PERFORMANCE_ANALYSIS command refer to section 7 2 30 PERFORMANCE_ANALYSIS1 8 Rev 1 0 09 00 page 140 of 423 HITACHI Time Measurement Mode 1 The execution time and count of the subroutine specified by the start address and end address e Execution count measurement This is counted up every time the end address of the specified subroutine is passed e Execution time measurement The measurement result does not include the execution time of the subroutine called by the specified subroutine between the start address and end address pod Start address m ime is measured End address Figure 1 24 Time Measurement Mode 1 Rev 1 0 09 00 page 141 of 423 HITACHI Time Measurement Mode 2 The execution time and count of the subroutine specified by the start address and end address e Execution count measurement This is counted up every time the end address of the specified subroutine is passed e Execution time measurement The measurement result includes the execution time of the subroutine called by the specified subroutine between the start address and end address P Start address mm ime is measured End address Figure 1 25 Time Measurement Mode 2 Rev 1 0 09 00 page 142 of 423 HITACHI Time Measurement Mode 3 The execution time and count of the subroutine specified by the start address range and end address range In this mode the combination of the specifiable channels is fix
336. ter and end bus cycle pointer Trace information is displayed in the same format as the bus cycle information display by the TRACE command no conditions are specified the number of bus cycles and instructions saved in the trace buffer are displayed TRACE SEARCH RET INSTRUCTION NUMBER D xxxxxx BUS CYCLE NUMBER D yyyyyy xxxxxx Number of instructions decimal yyyyyy Number of bus cycles decimal Rev 1 0 09 00 page 337 of 423 HITACHI TRACE_SEARCH If the L option is specified displays only the last bus cycle information to be searched for tems listed in table 7 38 can be specified for condition and they can be combined by ANDing them Table 7 38 Specifiable Conditions TRACE SEARCH Item and Input Format Address condition A lt address 1 gt lt address 2 gt Description When only lt address 1 gt is specified the condition is satisfied when the address bus value matches the specified value When both lt address 1 gt and lt address 2 gt are specified the condition is satisfied when the address bus value is in the range from lt address 1 gt to lt address 2 gt This condition can be masked Data condition D lt 1 byte value gt WD lt 2 byte value gt LD lt 4 byte value gt The condition is satisfied when the data bus value matches the specified value When D WD or LD is specified the condition is satisfied when the address is acces
337. ters office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfuncti
338. ther select one of the access types on the left or specify none External probe condition PRB lt value gt The condition is satisfied when all of the emulator s external probe signals match the specified values Specify lt value gt as 1 byte data Each bit corresponds to a probe number as follows 3 2 1 0 lt Bit xX x X lt Specified value 4 3 2 1 lt Probe number x 0 Low level 1 High level This condition can be masked Rev 1 0 09 00 page 323 of 423 HITACHI TRACE_CONDITION_A B C Table 7 32 Specifiable Conditions TRACE CONDITION B cont Item and Input Format External interrupt condition 1 NMI L or NMI H Description The condition is satisfied when the NMI signal matches the specified level NMI or NMI L The condition is satisfied when NMI is low NMI H The condition is satisfied when NMI is high External interrupt condition 2 IRL lt value gt The condition is satisfied when all of the IRL signals match the specified values Specify lt value gt as 1 byte data Each bit corresponds to an IRL number as follows 3 2 1 0 lt Bit x X lt Specified value 1 0 lt x 0 Low level x x 3 2 IRL number 1 High level The condition can be masked Satisfaction count specification COUNT lt value gt value H 1 to H FFFF The condition can be specified in combination with any of the address data read write access type extern
339. ting transfer rate can be switched Marked SW1 and SW2 9 Serial interface connector For RS 232C communication with a host PC Marked SERIAL 10 Station to EV chip board interface connector CN1 For trace cable 1 which connects the E8000 station to the EV chip board 11 Station to EV chip board interface connector CN2 For trace cable 2 which connects the E8000 station to the EV chip board 12 LAN board slot For installing the optional LAN board 13 Control board slot For installing the control board 14 Trace board slot For installing the trace board 15 Device control board slot For installing the device control board depends on the target device Rev 1 0 09 00 page 14 of 423 HITACHI 2 1 2 Device Control Board Components Id3Tivuvd zs N N m o o 100 120 AC200 240V 2A 50 60Hz Figure 2 4 Device Control Board 1 External probe connector CN4 For connecting to the external probe 2 Station to EV chip board interface connector CN3 For trace cable 3 which connects the E8000 station to the EV chip board 3 Device control board slot For installing the device control board depends on the target device Rev 1 0 09 00 page 15 of 423 HITACHI 2 1 3 EV Chip Board Components Pin 1 mark Bottom view a Station to EV chip board interface connectors Side view Figure 2 5 EV Chip Board HS7612EBH81H 1 1 Station to EV chip board interface connector CN3 For trace c
340. tion calling the subroutine are displayed Rev 1 0 09 00 page 308 of 423 HITACHI STEP_OVER Table 7 25 Causes of STEP_OVER Command Termination Message Termination Cause BREAK KEY The CTRL C keys were pressed for forcible termination ILLEGAL INSTRUCTION A break instruction H 0000 was executed ONE STEP END Single step execution was completed RESET BY E8000 The emulator forcibly terminates program execution with the RESET signal because an error occurs in the user system SUBROUTINE END The called subroutine has finished execution Notes 1 When a delayed branch instruction is executed with the STEP_OVER command execution stops at the instruction immediately following a delayed branch instruction Therefore two instruction mnemonics are displayed 2 Do not use this command when program execution may not return from a subroutine called by a BSR JSR BSRF or TRAPA instruction 3 Ifthe condition that UBC use is enabled is specified with the UBC option of the EXECUTION_MODE command the STEP_OVER command cannot be used If this is attempted the following error message is displayed and STEP_OVER command execution is terminated xik 8 UBC IS USED BY USER SYSTEM Example To execute the program one step at a time starting from the address given by the current PC and without displaying instructions within the called subroutine SO RET PC 00001002 SR 000000F0 000000000000 IIII00
341. tion using a LAN interface is shown in figure 2 7 Cheapernet Interface Ethernet Interface E8000 station station Workstation Workstation Figure 2 7 System Configuration Using a LAN Interface Cheapernet Interface This is achieved by connecting a coaxial cable referred to as the Cheapernet thin wire cable between the BNC connector on the LAN board and the workstation Ethernet Interface This is achieved by connecting transceivers and transceiver cables between the D SUB connector on the LAN board and the workstation Rev 1 0 09 00 page 20 of 423 HITACHI 2 3 2 System Configuration Using an RS 232C or Bidirectional Parallel Interface Using an RS 232C interface or a bidirectional parallel interface the E8000 station can be connected to a personal computer Figure 2 8 shows the system configuration using the RS 232C or bidirectional parallel interface RS 232C Interface Bidirectional Parallel Interface Host computer Host computer Figure 2 8 System Configuration Using an RS 232C or Bidirectional Parallel Interface Rev 1 0 09 00 page 21 of 423 HITACHI 2 3 3 System Configuration Using a PC Interface Board The E8000 station can be connected to a host computer via a PC interface board Install the PC interface board to the extension slot of the ISA bus specification in a PC and connect the interface cable supplied with the PC interface board to the E8000 station Figure 2 9 shows the system configuration usin
342. tions at addresses H 1000 and H 2000 have been executed in sequence Break condition 2 The break condition is satisfied Figure 1 13 Sequential Break Rev 1 0 09 00 page 128 of 423 HITACHI Break condition A break occurs when the instructions at addresses H 1000 and H 2000 have been executed in sequence Specification BREAK SEQUENCE 1000 2000 User program BREAK SEQUENCE 500 R Program flow 1000 No break occurs Break condition 1 Wait for break condition 2 500 No break occurs Searches for the condition Reset point Wait for break condition 1 from break condition 1 2000 No break occurs Break condition 2 Wait for break condition 1 1000 No break occurs Break condition 1 Wait for break condition 2 2000 A break occurs when the instructions Break condition 2 p 5 at addresses H 1000 and H 2000 have been executed in sequence Figure 1 14 Sequential Break Reset Point Specification Note When specifying the sequential break BREAK SEQUENCE the emulator firmware is activated every time the program passes the pass point or reset point As a result the program will not operate in realtime When the program passes the pass point or reset point the emulator executes the instruction at the address for one step then returns to program execution Accordingly the BREAK CONDITION UBC2 settings are invalid at pass point or reset point execution 1 4 3 Forced Break Pressing the CTR
343. to H FFFF Figure 1 19 shows the trace stop condition specification User program Program flow Trace memory Face Stop pz 131 070 bus condition is cycles satisfied Realtime emulation continues NUT No break occurs Figure 1 19 Trace Stop Condition Specification Subroutine Range Trace Trace information is acquired only when the instructions and operands are accessed in the specified subroutine under the specified condition The subroutine and condition can be specified with the CONDITION commands Rev 1 0 09 00 page 135 of 423 HITACHI 1 5 3 Trace Display The user can display trace information using the TRACE command There are three display formats as follows When branch instruction trace is specified with the TRACE_MODE command trace information for branch instruction cycles is displayed Instruction Display Only the executed instruction will be displayed in mnemonics from the trace information Bus Cycle Display Trace information is displayed in bus cycle units Search Display The emulator searches for specified trace information and displays all the corresponding bus cycles In this case use the TRACE_SEARCH command 1 6 Single Step Function In addition to realtime emulation effective debugging is facilitated by the single step function This function displays the following information every time a program instruction is executed
344. to table 10 2 5 INVALID DEVICE CONTROL The connected device control board is not BOARD supported by this E8000 system program Check the E8000 system program and device control board numbers 6 USER SYSTEM NOT READY _ The user clock or crystal oscillator clock was not input and therefore could not be selected The emulator internal clock was used instead Check if the clock signal is output correctly 8 UBC IS USED BY USER The command cannot be used because the UBC SYSTEM user break controller is open to the user system 9 INVALID OPTION The specified option is incorrect Check the specified option 10 FLASH MEMORY IS WRITE Flash memory is write protected Remove write PROTECTED protection 11 FLASH MEMORY WRITE An error occurred during write to flash memory ERROR 13 FILE NOT FOUND The configuration information specified to be restored with the CONFIGURATION command was not found in the emulator flash memory Rev 1 0 09 00 page 389 of 423 HITACHI Table 10 1 Emulator Error Messages cont Error No Error Message Description and Solution 15 INVALID FILE The specified file has invalid contents and cannot be read from or written to Check the contents of the specified file 20 SYNTAX ERROR The command syntax is incorrect Correct the syntax 21 INVALID COMMAND The specified command is invalid or this command cannot be executed in parallel mode Correctly enter the command 22 INVALID
345. tor forcibly terminates the processing and then initiates the loop program for accepting user interrupts again BACKGROUND_INTERRUPT E RET Enables user interrupts in command input wait state and sets the address of the loop program for accepting user interrupts The loop program must be stored in the RAM area If no address is specified the address specified before is used After setting the loop program execution starts BACKGROUND INTERRUPT E 0000FFFC RET Disables user interrupts in command input wait state BACKGROUND INTERRUPT D RET Rev 1 0 09 00 page 194 of 423 HITACHI BACKGROUND_INTERRUPT When the C option is specified the following message is displayed to confirm with the user whether to overwrite the existing configuration information in the emulator flash memory CONFIGURATION STORE OK Y N a RET a Y Stores the specifications as configuration information in emulator flash memory Hereafter when the emulator is activated the saved specifications go into effect N Does not overwrite configuration information The existing specifications are valid When user interrupts are enabled in command input wait state E is specified only commands usable in parallel mode and the BACKGROUND_INTERRUPT command can be executed Display Displays user interrupt accepting mode in command input wait state and the executing address of the loop program for accepting user interrupt
346. tudy trace information At each software breakpoint set with the BREAK command or at each pass point set with the BREAK SEQUENCE command the program halts at that address the emulator analyzes the pass count and pass point of the program and then the program continues When the memory access command processing in parallel mode occurs during this termination memory cannot be accessed At this time 78 EMULATOR BUSY is displayed and the command should be re input However when the interval of termination is too short the PC is not displayed the emulator does not enter parallel mode or commands may not be executed in parallel mode When the contents of a breakpoint set by the BREAK command have been modified by the user program during emulation that breakpoint will be cancelled at execution stop When the condition that UBC use is enabled is specified with the UBC option of the EXECUTION MODE command the following functions cannot be used a Software breakpoints e When restarting emulation from the breakpoint set with the BREAK command e When specifying the number of times a breakpoint is reached with the BREAK command e BREAK SEQUENCE command Under the above conditions when emulation cannot restart the following error message is displayed and the emulator enters the command input wait state 8 UBC IS USED BY USER SYSTEM b BREAK CONDITION sequential break mode c Emulation execution when bre
347. urement Mode 1 sese 138 Time Interval Measurement Mode 2 essseeeeeeeeeee eene 139 Time Measurement Mode 15 rentre mere eie 141 Time Measurement Mode 2 saiicta aeie iaa nennen enne entree 142 Time Measurement Mode 3 oo 143 Pulse Output Timing ette tee RE ER npe te te perte geh 145 Assembly E nctlOn eb eei e n e i e thecae pre e be 150 Basic Bus aereis ens ee Io dp REED e Seiad Ste ts 166 Control Signal Timing na iem e e PIE die A EE ge 167 User System Interface Circuits esses 168 Troubleshootimb PAD cette cei e ee lee e eee bue 177 Emulation Command Description Format eese 185 Display Range Specified by Pointers seen 312 Description Format of Host Computer Related 344 LAN Command Description Format seseseeeeeeeeneeneeeeenen nennen 363 Part HI Appendices Figure A 1 Figure A 2 Figure A 3 Figure A 4 Figure A 5 Figure B 1 Figure B 2 Serial Connector Pin Alignment at the Emulator 403 Parallel Connector Pin Alignment at the Emulator Station 404 LAN Connector Pin Alignment at the Emulator Station 406 Senal Interface Cable 1 2 erento ep Des
348. us cycles until a break condition is satisfied When no parameter is given with the TRACE CONDITION A B C commands the default is free trace Figure 1 16 illustrates the free trace operation Note 1 5 Realtime Trace Function Rev 1 0 09 00 page 132 of 423 HITACHI Only external bus information can be traced at realtime For details refer to section User program Program flow Trace memory Break condition is 131 070 satisfied bus cycles Figure 1 16 Free Trace Execution Subroutine Trace When a subroutine trace is specified the emulator acquires operand accesses and instructions between a specified start address and end address However when the specified subroutine calls another subroutine the called subroutine is not traced Figure 1 17 illustrates the operation of the subroutine trace Note Only external bus information can be traced at realtime For details refer to section 1 5 Realtime Trace Function Start address information is acquired Figure 1 17 Subroutine Trace Specification Rev 1 0 09 00 page 133 of 423 HITACHI Range Trace When a range trace is specified the emulator only traces at points where specified conditions are satisfied The following conditions can be specified e Address bus value within or outside a specified range e Read write condition e Access type program fetch cycle and program execution cycle Note Only external bus information
349. v 1 0 09 00 page 283 of 423 HITACHI PERFORMANCE_ANALYSIS Execution time ratio displayed in graph form Option A is specified PERFORMANCE ANALYSIS A RET NO NAME MODE ADDRESS 1 SUBA 00000100 00001FF0 TIME 2xxxH xxM xxS xxxxxxUS COUNT nnnnnnnn b 4 f g 2 SUBB 00005000 00007FF0 3 SUBC B 00010000 0001008F h 00020000 00020098 i 4 5 SUBE AC 00002030 0000207F lt ACCESS gt FFFFFF00 FFFFFF7F DAT 0 7 SUBD SC 00020100 0002FFFF lt CALL SUB gt 00030000 00030060 1 TOTAL RUN TIME D 0000H 10M 008 000020US 000NS m a Subroutine number b Subroutine name up to 8 characters are displayed c Time measurement mode Subroutine execution time measurement mode 1 I2 Subroutine execution time measurement mode 2 I3 Subroutine execution time measurement mode 3 AC Area access count measurement mode SC Subroutine call count measurement mode d Subroutine start address e Subroutine end address f Timeout value displayed only when the timeout value is set with the TIME option in mode I1 or I2 g Count value displayed only when the count value is set with the COUNT option in mode I1 or I2 h Start address range in subroutine execution time measurement mode 3 i End address range in subroutine execution time measurement mode 3 j Accessed area address range in area access count measurement mode Rev 1 0 09 00 page 284 of 423 HITAC
350. value lt display unit gt Size of display unit B 1 byte units W 2 byte units L 4 byte units XW 16 bit fixed point units XL 32 bit fixed point units Default 1 byte units Description e Display When B W or L is specified as display unit displays a memory dump of the specified area as follows ADDRESS DATA ASCII CODE XXXXXXXX on M XX b c a Address b Memory contents c Memory contents displayed as ASCII codes If there is no applicable ASCII code a period is displayed instead Rev 1 0 09 00 page 237 of 423 HITACHI DUMP If only the RET key is pressed after DUMP command execution has been terminated except for forcible termination the 256 bytes of data from the next address of the last dump are displayed When XW or XL is specified as lt display unit gt displays a fixed point memory dump of the specified area as follows lt ADDRESS gt lt HEX gt lt FIXED POINT gt XXXXXXXX XXXXXXXX X XXXXXXXXXX a b a Address b Memory contents of address a in hexadecimal c Memory contents of address a in fixed point units Note If a reserved area dump is displayed the contents will be undefined Examples 1 To display a memory dump from addresses H O to H 2F D 0 2F RET lt ADDRESS gt lt D A T A gt lt ASCII CODE 00000000 20 48 20 49 20 54 20 41 20 43 20 48 20 49 20 20 HITACHI 00000010 00 0
351. will damage the user system and the emulator product or will result in PERSONAL INJURY The USER PROGRAM will be LOST 1 Carefully handle the emulator product to prevent receiving an electric shock because the emulator product has a DC power supply Do not repair or remodel the emulator product by yourself for electric shock prevention and quality assurance Always switch OFF the emulator and user system before connecting or disconnecting any CABLES or PARTS Always before connecting make sure that pin 1 on both sides are correctly aligned Supply power according to the power specifications and do not apply an incorrect power voltage Use only the provided AC power cable Use only the specified type of fuse Rev 1 0 09 00 page V of VI HITACHI Warnings on Emulator Usage Warnings described below apply as long as you use this emulator Be sure to read and understand the warnings below before using this emulator Note that these are the main warnings not the complete list N WARNING Always switch OFF the emulator and user system before connecting or disconnecting any CABLES or PARTS Failure to do so will result in a FIRE HAZARD and will damage the user system and the emulator product or will result in PERSONAL INJURY The USER PROGRAM will be LOST N WARNING Place the emulator station and EV chip board so that the trace cables are not bent or twisted A bent or twisted cable will impose stress on the user
352. will result in PERSONAL INJURY The USER PROGRAM will be LOST E8000 station E8000 station N N 3 Connect the trace cables into the station to EV chip board interface connectors CN1 CN2 and CN3 on the E8000 station s rear panel Confirm that the shape of the trace cable plug matches that of the station to EV chip board interface connector before connecting Also note which trace cable is connected to which E8000 station connector so that the other end of the trace cable is connected to the matching connector number on the EV chip board After the connection is completed alternately tighten the screws on both sides of the trace cable to prevent the upper or lower side of the trace cable from lifting off the connector Figure 3 3 shows how to correctly connect the trace cables to the E8000 station connectors Rev 1 0 09 00 page 27 of 423 HITACHI CN1 red CN2 yellow CN3 blue Colors of the station to EV chip board interface connectors red yellow and blue seals on the panel CN1 red Colors of the screws on the trace cables CN2 yellow CNS blue Figure 3 3 Connecting Trace Cables to the E8000 Station Note At shipment the trace cable screws are colored to prevent an insertion error CN1 red CN2 yellow CN3 blue In addition trace cables CN2 and CN3 to be connected to the E8000 station are bound into a bundle and trace cables CN1 CN2 and CN3 to be connected to the EV chip board are b
353. witches are pushed to the left and the state becomes off when the switches are pushed to the right ON state ON state OFF state Side view of SW1 and SW2 ON OFF states Setting at shipment Figure 3 9 Console Interface Switches To change the console interface settings turn switches S1 to S8 on or off in the console interface switches SW1 and SW2 Table 3 1 lists the console interface settings and the corresponding setting states Rev 1 0 09 00 page 36 of 423 HITACHI Note Be sure to turn off the power supply before changing the settings of console interface switches SW1 and SW2 Table 3 1 Console Interface Settings Transfer Rate SW2 S3 S2 1 2400 BPS OFF OFF OFF 4800 BPS OFF OFF ON 9600 BPS OFF ON OFF Setting at shipment 19200 BPS OFF ON ON 38400 BPS ON OFF OFF Stop bit Length SW2 S4 1 bit OFF Setting at shipment 2 bits ON Bit Length SW2 S5 7 bits OFF 8 bits ON Setting at shipment Parity SW2 S6 None OFF Setting at shipment Parity ON Even odd Parity SW2 S7 1 bit OFF Setting at shipment 2 bits ON Note Effective only when there is a parity Flow Control Protocol SW2 S8 CTS RTS OFF X ON OFF ON Setting at shipment Automatic System Program Initiation Quit amp Warm Start SW1 S4 NO OFF Setting at shipment YES ON Rev 1 0 09 00 page 37 of 423 HITACHI Console LAN PC Interface SW1 57 S8 Console OFF
354. x WRITE yy y READ zz Z is displayed XXXXxxxx Address of error yy y Write data hexadecimal and ASCII characters zz z Read data hexadecimal and ASCII characters If areas other than the internal memory areas or areas CSO to CS4 are included in the destination transfer is performed to only the internal memory areas and areas CSO to CS4 Example To transfer data in the address range from H 101C to H 10FC to address H 1000 MV 101C 10FC 1000 RET Rev 1 0 09 00 page 275 of 423 HITACHI MOVE_TO_RAM 7 2 29 MR Moves contents of ROM to standard emulation memory Command Format e Movement MOVE_TO_RAMA lt start address gt A lt end address gt lt memory attribute gt RET lt start address gt Start address of the ROM area to be moved lt end address gt End address of the ROM area to be moved lt memory attribute gt Type of standard emulation memory to be allocated S Standard emulation memory SW Standard emulation memory with write protection Default Standard emulation memory S Description e Movement Use this command to temporarily modify ROM contents in the user system and execute the modified program Transfers user system ROM contents to the specified standard emulation memory area where data can be modified Data transfer to standard emulation memory is performed in 1 Mbyte units After data transfer the unused standard emulation memory area is displayed as fo
355. xecuted H 1 to H FFFFFFFF Default If stop PC and display option are specified H FFFFFFFF is assumed If not H 1 is assumed Start address of single step execution Default is the current PC address PC address when single step execution is terminated Default is number of execution steps Specification of instructions to be displayed J Displays instructions and register contents only when branch instructions are executed R Displays instructions and register contents only within the opening routine Default Displays instructions and register contents for all executed instructions Interrupt permission during STEP command execution HITACHI STEP Description e Single step Performs single step execution from lt start address gt to lt stop PC gt or from lt start address gt for lt number of execution steps gt The type of emulation performed described below depends on the specified parameters and option In addition register and memory contents address instruction mnemonic and termination cause are displayed in the following format PC 00001000 SR 000000F0 000000000000 IITI00 GBR 00000000 VBR 00000000 MACH 00000000 MACL 00000000 PR 00000000 RS 00000000 RE 00000000 MOD 00000000 RO 7 00000000 000000FF 00000011 00000000 00000000 00000000 00000000 00000000 R8 15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000FFE00 DSR200000000 k x z 2 k ze eee
356. y space in the CSO to CS4 areas Standard emulation memory 4 Mbytes can be set in 1 Mbyte units to the memory area The CSn area that is not set as emulation memory is set as user system memory For details refer to section 7 2 25 MAP e U User system memory e 5 Standard emulation memory The user can specify write protected and access prohibited areas as emulation memory Normally emulation memory and user memory should not be allocated to the same CS area concurrently If they are strobe signals RD CSn and WEn are not output in that CS area Access time of the emulation memory is ten clocks per bus cycle CPU internal clocks and WAIT count cannot be changed Write protected areas can be allocated to the emulation memory in units of 1 Mbyte or more e SW Write protected 32 1 Internal I O Area When the internal I O area is accessed the emulator accesses the SH7612 internal I O regardless of the memory attribute set with the MAP command The user can read from and write to the internal I O area with user program or emulator commands When writing to the internal I O area with an emulator command MEMORY the following warning message is displayed and the emulator starts writing without verifying 86 INTERNAL AREA However the user cannot write to the internal I O with the FILL command 3 2 2 External Memory Area The SH7612 external memory area can be allocated to all memory attributes supported by the emulato

SH7612 E8000 Emulator HS7612EDD81H User`s Manual

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