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DesignWare IP Family Quick Reference Guide

1. The dwcore_jpeg_codec data sheet is available at 377 Co dwcore_jpeg_codec x Qs Synthesizable JPEG CODEC DCTRam ZigRam0O ZigRam1 QMem HuffEnc ft Ff l pixout y v g TH dct ia zigzag Dy quant ip code eng m gt unstuff DS store addr gt decode H regctrl E din dout gt 4 A a JPEG CODEC HuffMin HuffBase HuffSymb http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_jpeg_codec pdf Synopsys Inc January 17 2005 DesignWare IP Family Chapter 6 DesignWare Star IP 6 DesignWare Star IP Design engineers who use the DesignWare Library have the ability to evaluate and design easily at their desktop using the following high performance high value IP cores from leading Star IP providers Component Name Component Description Component Type DW_IBM440 PowerPC 440 32 Bit Microprocessor Core Synthesizable RTL from IBM page 379 Verification Model DW_V850E Star V850E 32 Bit Microcontroller Core from Synthesizable RTL NEC Electronics page 381 Verification Model DW_C166S 16 Bit Microcontroller Subsystem from Synthesizable RTL Infineon page 383 Verification Model DW_TriCorel TriCore1 32 Bit Processor Core from Synthesizable RTL Infineon page 38
2. AXI AXI AXI AXI a Master Master Master Master lt APB A A A A ane APB maY Y Y Y S Monitor AXI Interconnect a A A A lt APB aK gt Slave v vV A 2 ae AXI AXI AXI to APB 4 lt T Slave Slave Bridge K D APB Slave v APB Monitor Using the DesignWare Verification Models for the AMBA 3 AXI Interface is available at http www synopsys com products designware docs 308 Synopsys Inc PRELIMINARY January 17 2005 DesignWare IP Family Board Verification IP Simulation models for Board Verification Board Verification IP Simulation models for Board Verification The DesignWare Library contains over 18 500 simulation models for ASIC SoC and Board verification For a complete search visit http www synopsys com ipdirectory Component Group Component Reference VMT Models Refer to DesignWare VMT Models on page 320 FlexModels Refer to DesignWare FlexModels on page 322 DesignWare Memory Models Refer to Memory Models on page 313 SmartModel Library Refer to DesignWare SmartModels on page 324 January 17 2005 Synopsys Inc 309 g m S O o e gt Ea DesignWare IP Family Ethernet 10 100 1G 10G Models Transceiver and Monitor Ethernet 10 100 1G 10G Models Transceiver and Monitor Transceiver ethernet_txrx_vmt Monitor ethern
3. DW_memctl DW_memcetl Static Dynamic Static i_memctl_ i_memctl_ 2 The DW_apb_ssi component i_ssil in the example subsystem can also communicate with an EEPROM as opposed to another DW_apb_ssi i_ssi2 290 Synopsys Inc January 17 2005 DesignWare IP Family Memory IP The following Memory IP are briefly described in this section Component Name Component Description Component Type DW_memctl Memory Controller page 292 Synthesizable RTL DW_rambist DesignWare Memory BIST solution page 294 Synthesizable RTL To view the complete DesignWare memory portfolio refer to the following http www synopsys com products designware memorycentral g m wo lt m gt 0 o N D D 5 January 17 2005 Synopsys Inc 291 DesignWare IP Family DW_memctl Memory Controller DW_memctl Memory Controller e Supports AHB data widths of 32 64 or 128 bits AHB address width of 32 bits e Supports pin based little or big endian modes of operation e Supports separate or shared memory address and or data buses between SDRAM and Static memories e Glueless connection to all JEDEC compliant SDRAM e Supports up to 16 SDRAM address bits e SDR SDRAM Mobile SDRAM and SyncFlash memory data widths 16 32 64 or 128 with 1 1 or 1 2 ratios with AHB data width DDR
4. Note that the num_cyc specification indicates the actual throughput of the device That is if a new input is driven before the num_cyc number of cycles are complete the results are undetermined Table 3 Synthesis Implementations Implementation Function License Feature Required cpa Carry propagate adder synthesis model DesignWare 136 Synopsys Inc January 17 2005 DesignWare IP Family N COs Datapath Trigonometric Overview Datapath Trigonometric Overview The trigonometric IP many of which are inferred are applicable to ASIC or FPGA designs These IP are high performance trigonometric implementations based on a fast carry look ahead architecture g m wn lt S gt D o N D gt D 5 January 17 2005 Synopsys Inc 137 DesignWare IP Family DW02 cos Combinational Cosine DW02 cos Combinational Cosine e Parameterized word length A Cos Table 1 Pin Description Pin Name Width Direction Function A A_width bit s Input Angle in binary COS cos_width bit s Output Cosine value of A Table 2 Parameter Description Parameter Values Description A_width 2 to 34 Word length of A cos_ width 2 to 34 Word length of COS Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare 138 Synops
5. Pin Name Width Direction Function A 3 to 512 bits Input Two s compliment integer number Z e f 1 bits Output Floating point number STATUS optional 8 bits Output Status flags RND optional 3 bits Input Rounding mode Table 2 Parameter Description Parameter Values Description e 3 to 31 bits Word length of biased exponent of floating point number A f 2 to 253 bits Word length of fraction field of floating point number A arch 0 Architecture implementation Table 3 Synthesis Implementations Implementation Name Function License Feature Required archO Synthesis model DesignWare January 17 2005 Synopsys Inc 123 dl a1qeziseyyAs IMA DesignWare DW_add_fp IP Family Floating Point Adder DW_add_fp Floating Point Adder Module Compiler Only e The precision format is parameterizable for either IEEE single double precision or a user defined custom format e Exponents can range from 3 to 31 bits e Significand or fractional part of the floating point number can range from 2 to 256 bits e Accuracy conforms to IEEE 754 Floating Point standard Table 1 Pin Description Pin Name Width Direction Function A e f 1 bits Input Input data B e f 1 bits Input Input data Z e f 1 bits Output Sum of A B STATUS optional 8 bits Output Status flags RND optional 3 bits Input Rounding mode
6. Control ee Instruction Queue Unit RCU Interface Syste Program Config Counter Multiplier 32x32 or General 16x16 Purpose Barrel Instruction Instr Interface VFB System Registers Data Cache Data Cache Interface Bus VDB Control Unit BCU VSB DMA Control Interrupt Interrupt Control Unit INTC System Standby Control Control Unit STBC Clock System me vontroller Po NPB NPB Reset V850E Star Block Diagram Also see the following web page for additional information http www synopsys com products designware starip nec_v850e html January 17 2005 Synopsys Inc 382 DesignWare IP Family DW_C166S C166S 16 Bit Microcontroller from Infineon DW_C166S C166S 16 Bit Microcontroller from Infineon RA The Infineon C166S is a highly configurable fully synthesizable microcontroller core based on the successful C166 microcontroller IC family and is 100 instruction set compatible Other features include the following e Four stage pipelined fully static 16 bit CPU n e CPU speed up to 100 MHz in 0 18 micron technology e Up to 16 MB addressable memory is space e Optional multiplier accumulator MAC unit e Integrated On Chip Debugging System OCDS e Most instructions execute in a single instruction cycle 2 CPU clock cycles e Multiple register banks with single instruction cycle context switching e 16x16 multiplication in 5 instruction cycles 32 16 division in 10 i
7. Parameter Values Description data_width 1 to 256 Width of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare 230 Synopsys Inc January 17 2005 DesignWare IP Family 100111001 RAM Memory Asynchronous RAMs Memory Asynchronous RAMs This section documents the various DesignWare Building Block IP memory asynchronous RAMs g m wo lt m gt D 2 N D 2 D 5 January 17 2005 Synopsys Inc 231 DesignWare IP Family 100111001 DW_ram_r_w_a_dff RAM Asynchronous Dual Port RAM Flip Flop Based 01101001 DW_ram_r w_a dff Asynchronous Dual Port RAM Flip Flop Based wr_addr e Parameterized word depth nd adak e Parameterized data width data_in data_out e Asynchronous static memory cs_n wr_n e Parameterized reset implementation f a f test_mode e High testability using DFT Compiler S test_clk Table 1 Pin Description Pin Name Width Direction Function rst_n 1 bit Input Reset active low cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low test_mode 1 bit Input Enables test_clk test_clk 1 bit Input Test clock to capture data during test_mode rd_addr ceil log depth bit s Input Read address bus wr_addr ce
8. Lem pummy Decoder a petault Master a Slave Read e Mux o gt AHB al AHB Master 1 lq 6 jaa z Slave 1 l a a l AHB gt AHB Master n lt 4 e TE Slave n Write A Mux A SS SSS g m S O o e gt Ea p Arbiter a lt q e Ww 4 AHB Monitor D a b Used when the Slave is being certified Used when the Master is being certified Dummy Master Default Slave Arbiter Decoder Write Mux and Read Mux are part of the AHB Bus VIP model The DesignWare AHB Verification IP Databook is available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 305 DesignWare IP Family DesignWare AMBA APB Models Master Slave Monitor DesignWare AMBA APB Models Master Slave Monitor All Models e Multiple command streams e Verilog VHDL or Vera testbenches e Configurable message formatting e Event driven testbenches APB Master apb_master_vmt e 1 16 Slaves e Data Address width 8 32 bits e Constrained random test transactions using random file memory or FIFO data e Internal or external data mux e Error injection capability APB Slave apb_slave_vmt Data Address width 8 32 bits Configurable memory fill patterns Big endian or little endian FIFO memory at any memory location APB Monitor apb_monitor_vmt e Transaction logging e Protocol checking e Incremental coverage
9. Table 2 Parameter Description Parameter Values Description e 3 to 31 bits Word length of biased exponent of floating point numbers A B and Z f 2 to 253 bits Word length of fraction field of floating point numbers A B and Z arch l0 Architecture implementation a The DW_add_fp component contains only one architecture therefore the arch parameter should be set to 0 Table 3 Synthesis Implementations Implementation Name Function License Feature Required arch0 Synthesis model DesignWare 124 Synopsys Inc January 17 2005 DesignWare IP Family DW_cmp_fp 2 4979 x 105 Floating Point Comparator DW_cmp_fp Floating Point Comparator Module Compiler Only e The precision format is parameterizable for either IEEE single double precision or a user defined custom format e Exponents can range from 3 to 31 bits e Significand or fractional part of the floating point number can range from 2 to 256 bits g m wn lt S gt D o N D gt D 5 e Accuracy conforms to IEEE 754 Floating Point standard Table 1 Pin Description Pin Name Width Direction Function A e f 1 bits Input Floating point number B e f 1 bits Input Floating point number ALTB 1 bit Output High when A is less than B AGTB 1 bit Output High when A is greater than B AEQB 1 bit Output High when A is equal to B ZO
10. Implementation Name Function License Feature Required csa Carry save array synthesis model DesignWare str Booth recoded Wallace tree synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b The csa implementation is only valid when the sum of A_width and B_width lt A8 bits as it has no area benefit beyond 48 bits January 17 2005 Synopsys Inc 93 DesignWare IP Family DW02_mult_5_ stage Five Stage Pipelined Multiplier DW02_mult_5 stage Five Stage Pipelined Multiplier e Parameterized word length e Unsigned and signed two s complement data operation Five stage pipelined architecture Automatic pipeline retiming e Inferable from Behavioral Compiler Table 1 Pin Description Pin Name Width Direction Function A A_width bit s Input Multiplier B B_width bit s Input Multiplicand TC 1 bit Input Two s complement 0 unsigned 1 signed CLK 1 bit Input Clock PRODUCT A_width B_width bit s Output Product A x B Table 2 Parameter Description Parameter Values Description A_width 21 Word length of A B_ width gt 1 For csa architecture A_width B_width lt A8 Word length
11. DesignWare IP Family a DW_fifo_s1_df Synchronous Single Clock FIFO with Dynamic Flags DW_fifo_s1_df Synchronous Single Clock FIFO with Dynamic Flags half_full almost_empty empty e FIFO error flag indicating underflow overflow and diag_n pointer corruption e Fully registered synchronous flag output ports push_req_n g data_i e D flip flop based memory array for high testability Ta D 3 pop_req_n data_out lt e All operations execute in a single clock cycle gt ae_level full p e FIFO empty half full and full flags af thresh 2 most_full N 2 5 error e Dynamically programmable almost full and almost gt clk rst_n empty flags e Parameterized word width e Parameterized word depth e Parameterized reset mode synchronous or asynchronous memory array initialized or not Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 or 2 synchronous if rst_mode 1 or 3 push_req_n 1 bit Input FIFO push request active low pop_req_n 1 bit Input FIFO pop request active low diag_n 1 bit Input Diagnostic control active low ae_level ceil logs depth bit s Input Almost empty level the number of words in the FIFO at or below which the almost_empty flag is active af_thresh ceil logs depth bit s Input Almost full threshold the number of words stored i
12. data_out_ gt 2 Default 16 Width of output data This parameter should also width satisfy the following equation data_out_width lt maximum feedback_width data_in_width frac_data_out_width max_coef_width 3 frac_coef_width frac_data_ 0 to data_out_width 1 Width of fraction portion of data_out out_width Default 4 feedback_width gt 2 Default 12 Width of feedback_data feedback_data is internal to the lt model gt max_coef_width gt 2 to 31 Default 8 Maximum coefficient word length frac_coef_width 0 to max_coef_width 4 Default 4 Width of the fraction portion of the coefficients saturation _mode 0 or 1 Default 0 Controls the mode of operation of the saturation output out_reg 0 or 1 Default 1 Controls whether data_out and saturation are registered Al _ coef range Default 0 Constant coefficient value Al range _gmax_coef_width 4d to qmax_coef_width d 4 A2_ coef range Default 0 Constant coefficient value A2 range _gmax_coef_width 4d to qmax_coef_width 4d 4 BO_coef range Default 0 Constant coefficient value BO range _gmax_coef_width 4d to qmax_coef_width 4d 4 B1_coef range Default 0 Constant coefficient value B1 range _gmax_coef_width d to qmax_coef_width d 4 B2_coef range Default 0 Constant coefficient value B2 range _gmax_coef_width 4d to qmax_coef_width 4d 4 Table 3 Synthesis Implementations
13. Pin Name Width Direction Function data width Input Counter load input up_dn 1 Input High for count up and low for count down load 1 Input Enable data load to counter active low cen 1 Input Count enable active high clk 1 Input Clock reset 1 Input Counter reset active low count_dec gwidth Output Binary decoded count value tercnt 1 Output Terminal count flag Table 2 Parameter Description Parameter Values Function width 21 Width of data input bus Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc g m 2 lt m gt D 2 N D 2 D 5 173 DesignWare IP Family DW_dpll_sd Digital Phase Locked Loop DW_dpll_sd Digital Phase Locked Loop e Parameterizable divisor ratio of reference clock to baud rate e Multichannel data recovery recovery of channels that accompany the locked channel e Stall input for power saving mode and or prescaler allowing one DW_dpll_sd to recover data at multiple rates e Squelch input for ignoring phase information when channel data is unknown or unconnected e Sampling window control to aid data recovery under harsh conditions data_in data_out jam window bit_ready squelch Stall clk_out clk e Parameterizable gain selection to meet a variety of application needs e Parame
14. Pin Name Width Direction Function rst_n 1 bit Input Reset active low cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low rdl_addr ceil logs depth bit Input Read1 address bus rd2_addr ceil logs depth bit Input Read2 address bus wr_addr ceil logs depth bit Input Write address bus data_in data_width bit Input Input data bus data_rdl_out data_width bit Output Output data bus for read1 data_rd2_out data_width bit Output Output data bus for read2 Table 2 Parameter Description Parameter Values Description data_width 1 to 256 Width of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width rst_mode Oor 1 Determines if the rst_n input is used 0 rst_n initializes the RAM 1 rst_n is not connected Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare 236 Synopsys Inc January 17 2005 DesignWare IP Family 100111001 RAM DW_ram_rw_a_dff 01101001 Asynchronous Single Port RAM Flip Flop Based DW_ram_rw_a_dff Asynchronous Single Port RAM Flip Flop Based e Parameterized word depth rw_addr data_in e Parameterized data width cs_n e Asynchronous static memory ween data_out j e Parameterized reset implementation test_mode e High testability using DFT Compiler Gee rst_n g m w
15. Inferable using a function call Table 1 Pin Description Pin Name Width Direction Function a num_inputs X width bit s Input Concatenated input data tc 1 bit Input Two s complement control min_max bit Input Minimum maximum control 0 minimum a 1 maximum a value width bit s Output Minimum maximum value index ceil log num_inputs bit s Output Index of minimum maximum input Table 2 Parameter Description Parameter Values Description width 21 Input word length num_inputs 22 Number of inputs Default 2 Table 3 Synthesis Implementations Implementation Name Function License Feature Required cla Carry lookahead tree synthesis model DesignWare clas Carry lookahead select tree synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide January 17 2005 Synopsys Inc 85 DesignWare IP Family DW02_mult Multiplier DW02_mult Multiplier e Parameterized word length A F TC e Unsigned and signed two s complement data operation X PRODUCT B Table 1 Pin Description Pin Name Wi
16. Table 2 Parameter Description Parameter Values Description width 22 Word length of a Default None num_stages 2 Number of pipeline stages Default 2 stall_mode Oor 1 Stall mode Default 1 0 non stallable 1 stallable rst mode 0to2 Reset mode Default 1 0 no reset 1 asynchronous reset 2 synchronous reset January 17 2005 Synopsys Inc 115 DesignWare IP Family DW_sqrt_pipe Stallable Pipelined square root Table 3 Synthesis Implementations Implementation Name Implementation License Feature Required str Pipelined str synthesis model DesignWare a One of rpl or cla implementation is selected based the constraints of the design 116 Synopsys Inc January 17 2005 DW01_sub Subtractor e Parameterized word length e Carry in and carry out signals DesignWare IP Family DW01_sub Subtractor is A Q o lt S DIFF F o 5 5 Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data B width bit s Input Input data CI 1 bit Input Carry in DIFF width bit s Output Difference of A B CI CO 1 bit Output Carry out Table 2 Parameter Description Parameter Values Description width gt 1 Word length of A B and DIFF Table 3 Synthesis Implementations
17. Table 2 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare or Test EEE STD 1149 1 252 Synopsys Inc January 17 2005 DesignWare IP Family DW_bc_4 Boundary Scan Cell Type BC_4 DW_bc 4 Boundary Scan Cell Type BC_4 gt capture_clk e IEEE Standard 1149 1 compliant data_in data_out g e Synchronous or asynchronous scan cells with respect to tck si D z lt e Supports the standard instructions EXTEST SAMPLE shift_dr PRELOAD and BYPASS Et capture_en S 5 D 5 Table 1 Pin Description Pin Name Width Direction Function capture_clk 1bit Input Clocks data into the capture stage capture_en 1 bit Input Enable for data clocked into the capture stage active low shift_dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo si l bit Input Serial path from the previous boundary scan cell data_in 1 bit Input Input data from system input pin SO 1 bit Output Serial path to the next boundary scan cell data_out l bit Output Output data Table 2 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare or Test EEE STD 1149 1 January 17 2005 Synopsys Inc 253 DesignWare IP Family DW_bc_5 Boundary Scan Cell Type BC_5 DW_bc_5 Boundary Scan C
18. af_level 1 to depth 1 Almost full level the number of empty memory locations in the FIFO at which the almost_full flag is active err_mode 0 to 2 Error mode Default 1 0 underflow overflow with pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode 0 to 3 Reset mode Default 1 0 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding memory 3 synchronous reset excluding memory byte_order 0 or 1 Order of send receive bytes or subword subword lt 8 bits gt Default 0 subword within a word 0 first byte is in most significant bits position 1 first byte is in the least significant bits position valid for data_in_width data_out_width January 17 2005 Synopsys Inc 187 DesignWare IP Family DW_asymfifo_s1_sf TEED Asymmetric I O Synchronous Single Clock FIFO with Static Flags Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cll Partial carry look ahead model DesignWare cl2 Full carry look ahead model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer
19. e Slave aliases up to 3 additional ports e Response through notification at the end of Read Write transactions January 17 2005 Synopsys Inc Monitor axi_monitor_vmt Full protocol checking for AXI interface protocol Up to 32 Master and 32 Slave ports Independent of interconnect support for shared buses Shared address shared data SASD Configurable data bus widths Configurable ID bus widths Master ID ports configurable from 1 to 8 bits Slave ID ports configurable from 1 to 13 bits Includes checks on channel handshake ordering Includes run time control of checkers Transaction logging for AXI Supports configurable coverage analysis and reporting Automated coverage g m S O D ot O gt Ea AXI Interconnect axi_interconnect_vmt Shared address shared data SASD Arbiter and Decoder on each channel bus Default Slave device supported Up to 32 Masters and 32 Slaves Configurable system address bus of 32 or 64 bits Configurable data bus up to 1024 bits All type of responses supported including burst and atomic access Unlimited memory map for each Slave Pipelined operation on each channel with input stage concept 307 DesignWare IP Family DesignWare VIP for AMBA 3 AXI Master Slave Monitor Interconnect
20. ethernet_txrx_vmt ethernet_monitor_vmt See page 310 C Transceiver model i2c_txrx_vmt See page 312 Serial ATA models sata_device_vmt sata_monitor_vmt See page 317 Serial Input Output UART Transceiver and Monitor models sio_txrx_vmt sio_monitor_vmt See page 318 Synopsys Inc January 17 2005 DesignWare IP Family Listing of FlexModels DesignWare FlexModels FlexModels are binary simulation models that represent the bus functionality of microprocessors cores digital signal processors and bus interfaces FlexModels utilize the industry standard SWIFT interface to communicate with simulators FlexModels have the following features e Built with a cycle accurate core and a controllable timing shell so that you can run the model in function only mode for higher performance or with timing mode enabled when you need to check delays You can switch between timing modes dynamically during simulation using simple commands in your testbench e Feature multiple different control mechanisms You can coordinate model behavior with simulation events synchronize different command processes and control several FlexModels simultaneously using a single command stream e Allow you to use different command sources You can send commands to FlexModels using processes in a Verilog or VHDL testbench a C program or a Vera testbench You can switch between the HDL or Vera testbench and a compiled C program as the source for c
21. 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode Oor 1 Reset mode Default 0 0 asynchronous reset 1 synchronous reset Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cll Partial carry look ahead model DesignWare cl2 Full carry look ahead model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide January 17 2005 Synopsys Inc 213 DesignWare IP Family DW_fifoctl_s2_sf TL Synchronous Dual Clock FIFO Controller with Static Flags DW_fifoctl_s2_sf Synchronous Dual Clock FIFO Controller with Static Flags e Fully registered synchronous flag output ports push_req_n o d i push_word_count e Single clock cycle push and pop operations DREM e Separate status flags for each clock system T Ik h e FIFO empty half full and full flags Aria push_af push_full e FIFO push error overflow and pop error underflow push_error flags pop_req_n rd_addr e Parameterized word depth pop_word_count pop_empty e Parameterized almost full and almost empty flag clk_pop pop_ae thresholds p pop_
22. DW_asymfifoctl_s1_sf Asymmetric I O Synchronous Single Clock FIFO Controller with Static Flags e Fully registered synchronous address and flag output data_out g ports push_req_n wr_addr wr_data o e All operations execute in a single clock cycle se w_en E r ata E d_add e FIFO empty half full and full flags pond 2 e Asymmetric input and output bit widths must be pop_req_n amful z y p p part_wd integer multiple relationship flush_n full 5 almost_full e Word integrity flag for daen half fuli data_in_width lt data_out_width almost_empty e Flushing out partial word for empty data_in_width lt data_out_width rst_n error e Parameterized byte order within a word e FIFO error flag indicating underflow overflow and pointer corruption e Parameterized word depth e Parameterized almost full and almost empty flags e Parameterized reset mode synchronous or asynchronous e Interfaces to common hard macro or compiled ASIC dual port synchronous RAMs Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 synchronous if rst_mode 1 push_req_n_ 1 bit Input FIFO push request active low flush_n 1 bit Input Flushes the partial word into memory fills in 0 s for data_in_width lt data_out_width only pop_req_n 1 bit Input FIFO pop request active low
23. Implementation Name Function License Feature Required rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none bk Brent Kung synthesis model DesignWare clf Fast carry look ahead synthesis model DesignWare csm Conditional sum synthesis model DesignWare rpcs Ripple carry select synthesis model DesignWare clsa MC inside DW carry look ahead select DesignWare csa MC inside DW carry select DesignWare fastcla MC inside DW fast carry look ahead DesignWare pprefix MC inside DW flexible parallel prefix DesignWare January 17 2005 Synopsys Inc 117 DesignWare IP Family DW01_sub Subtractor Table 3 Synthesis Implementations Implementation Name Function License Feature Required pparch Delay optimized flexible parallel prefix DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b The performance of the csm implementation is heavily dependent on the use of a high performance inverting 2 to 1 multiplexer in the technology library In such libraries the csm implementation exhibits a superior area delay product Although the csm implementation does not always surpass the delay performance of the clf implementation it is much lower i
24. Implementation Name Function License Required mult Multiplier synthesis model DesignWare vsum Vector sum synthesis model DesignWare January 17 2005 164 Synopsys Inc DesignWare IP Family E Logic Combinational Overview The combinational components consist of high performance logical components Most components in this category have multiple architectures for each function architecturally optimized for either performance or area to provide you with the best architecture for your design goals All components have a parameterized word length Logic Combinational Overview g m wn lt S gt D o N D gt D 5 January 17 2005 Synopsys Inc 165 DesignWare IP Family DW01_binenc Binary Encoder DW01_binenc Binary Encoder e Parameterized word length e Inferable using a function call Table 1 Pin Description ADDR Pin Name Width Direction Function A A_width Input Input data ADDR ADDR_width Output Binary encoded output data Table 2 Parameter Description Parameter Values Description A_width 21 Word length of input A ADDR_width gt ceil log gt A_width 1 Word length of output ADDR Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare cla Synthesis model DesignWare 166 Synopsys Inc January 17 20
25. January 17 2005 Index DW_ram_rw_a_dff 237 DW_ram_rw_a_lat 238 DW_ram_rw_s_dff 229 DW_ram_rw_s_lat 230 DW_rambist 294 DW_ shifter 109 DW_sart 114 DW_sqrt_pipe 115 DW_sqrt_seq 135 DW_square 111 DW_squarep 113 DW_stack 240 DW_stackctl 242 DW_tap 245 DW_tap_uc 247 DW_TriCorel 385 DW_V850E Star 381 DWO1_absval 52 DWOl1_add 53 DWO1_addsub 55 DWOl1_ash 59 DWO1_binenc 166 DWO1_bsh 62 DWO1_cmp2 63 DW01_cmp6 65 DWO1_csa 70 DWO1_dec 71 DWO1_decode 167 DWOl1_inc 78 DWOl1_incdec 80 DW01_mux_any 168 DWO1_prienc 169 DWOl1_satrnd 107 DWO1_sub 117 DW02_cos 138 DW02_mac 83 DW02_mult 86 DW02_mult_2_stage 90 DW02_mult_3_stage 92 DW02_mult_4_stage 93 DW02_mult_5_stage 94 DW02_mult_6_stage 96 Synopsys Inc 394 Index DW02_multp 88 DW02_prod_sum 101 DW02_prod_sum1 103 DW02_sin 139 DW02_sincos 140 DWO02_sum 119 DW02_tree 121 DW03_bictr_dento 171 DW03_bictr_decode 173 DW03_bictr_scnto 172 DW03_lIfsr_dento 176 DW03_lfsr_load 178 DW03_lfsr_scnto 177 DW03_lfsr_updn 179 DW03_pipe_reg 218 DW03_reg_s_pl 219 DW03_shftreg 222 DW03_updn_ctr 180 DW04_par_gen 148 DW04_shad_reg 220 DW8051 299 dwe_pcie_dualmode 350 dwc_pcie_endpoint 345 dwc_pcie_rootport 347 dwc_pcie_switchport 349 dweore_1394_avlink 372 dweore_1394_cphy 374 dwcore_ethernet 333 dwcore_ethernet_sub 335 dweore_gig_ethernet 337 dwcore_gig_ethernet_sub 339 dwcore_jpeg_codec 376 dwcore_pci 341 dwcore_pcie_phy 352 dweore_pcix 343 dwcore_sd_mmc_host 353 dwco
26. Pin Name Width Direction Function clk 1 bit Input Clock rst_n 1 bit Input Asynchronous reset active low init_rd_n 1 bit Input Synchronous initialization active low init_rd_val 1 bit Input Value of initial Running Disparity k_char bytes bit s Input Special character controls one control per byte to encode data_in bytes x 8 bit s Input Input data for encoding rd 1 bit Output Current Running Disparity before encoding data presented at data_in data_out bytes x 10 Output 8b10b encoded data bit s enable 1 bit Input Enables register clocking 152 Synopsys Inc January 17 2005 00900000 DesignWare IP Family Group DW_8b10b_enc 1010110001 8b10b Encoder Table 2 Parameter Description Parameter Value Description bytes 1 to 16 Number of bytes to encode Default 2 k28_5_only O or 1 Special character subset control parameter Default 0 0 for all special characters available 1 for only K28 5 available when k_char HIGH regardless of the value on data_in en_mode Oor 1 Enable control Default 0 0 the enable input port is not connected backward compatible with older components 1 when enable 0 the encoder is stalled g m wo lt m gt D 2 N D 2 D 5 init mode Oor1 Intialization mode for running disparity Default 0 0 during active init_rd_n input delay init_rd_val one clock cycle before applying it to data_in input in calculating data_ou
27. gt Hub Controller v Hub Functional State i Machine Hub Repeater Bowerand Hub Command Overcurrent Interpreter A Control Port State Port State Port State Port State Machine Machine Machine Machine Downstream Downstream Downstream Downstream ort 1 Port 2 Port 3 Port 4 v Y v y Transceiver Transceiver Transceiver Transceiver jan i 5 a ie USB The dwcore_usb1_hub data sheet is available at USB 010 MA http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_usb1_hub pdf January 17 2005 Synopsys Inc 360 DesignWare IP Family dwcore_usb1_hub 4 Qs Synthesizable USB 1 1 Hub Controller 361 Synopsys Inc January 17 2005 Co Es dwcore_usb2_hsotg Synthesizable USB 2 0 Hi Speed On the Go Controller Subsystem DesignWare IP Family dwcore_usb2_hsotg Synthesizable USB 2 0 Hi Speed On the Go Controller Subsystem The DesignWare USB 2 0 Hi Speed On The Go HS OTG Controller Subsystem performs as a standard Hi Speed Dual Role Device DRD operating as either a fully USB 2 0 Hi Speed compliant peripheral or an OTG host Features include the following January 17 2005 Hardware state machines maximize performance and minimize CPU interrupts Flexible parameters enable easy integration into low and high latency systems Transfer or transaction based processing of USB data is based on system requirements Configurable data bufferi
28. m wo lt m gt 0 2 N D D 5 DesignWare IP Family ly loy DW8051 Ce 8051 Microcontroller KS 128 or 256 bytes DW8051_core lo y gt tO out t1_out iram_bus t1 __ t2 DW8051_timer DW8051_timer2 Timers 0 and 1 Timer 2 lt _ t2ex optional t2_out DW8051_cpu sfr_bus le gt DW8051_ alu DW8051_ serial A txd0 ge alas or Serial Porto d0_in i DW8051_intr_1 optional gt rxd0_out gt DW8051_biu _intr_ DW8051_serial gt txd1 _ Serial Port 1 lt rxd1_in t optional rxd1_out interrupts DW8051_main_regs port_control mem_bus clk por_n rst_in_n rst_out_n test_mode_n idle_mode_n stop_mode_n DW8051_op_decoder i irom_bus 0 to 64 KB The DesignWare DW_8051 MacroCell Databook is available at J http www synopsys com products designware docs 300 Synopsys Inc January 17 2005 DesignWare IP Family Chapter 3 DesignWare Library Verification IP 3 DesignWare Library Verification IP Overview The following table identifies the various components that make up the DesignWare Library s Verification IP offering See page 309 for a listing of the Board Verification IP component groups Customers can also elect to license single DesignWare Verific
29. 2 N D D 5 DesignWare IP Family tit DW_fifoctl_s2_sf Synchronous Dual Clock FIFO Controller with Static Flags Table 2 Parameter Description Continued Parameter Values Description push_af_Ivl 1todepth 1 Almost full level for the push_af output port the number of Default 2 empty memory locations in the FIFO at which the push_af flag is active pop_ae_lvl 1ltodepth 1_ Almost empty level for the pop_ae output port the number Default 2 of words in the FIFO at or below which the pop_ae flag is active pop_af_lvl l to depth 1 Almost full level for the pop_af output port the number of Default 2 empty memory locations in the FIFO at which the pop_af flag is active err_mode Oor 1 Error mode Default 0 0 stays active until reset latched 1 active only as long as error condition exists unlatched push_syne 1 to3 Push flag synchronization mode Default 2 1 single register synchronization from pop pointer 2 double register 3 triple register pop_sync 1 to3 Pop flag synchronization mode Default 2 1 single register synchronization from push pointer 2 double register 3 triple register rst_mode Oor 1 Reset mode Default 0 0 asynchronous reset 1 synchronous reset tst_mode Oor 1 Test Mode Default 0 0 test input not connected 1 lock up latches inserted for scan test Table 3 Synthesis Implementations Implementation Name Funct
30. 2005 Synopsys Inc 259 DesignWare IP Family DW_bc_9 Boundary Scan Cell Type BC_9 260 Table 3 Simulation Models Model Function DW04 DW_bc_9_CFG_SIM Design unit name for VHDL simulation dw dw04 src DW_bc_9_sim vhd VHDL simulation model source code dw sim_ver DW_bc_9 v Verilog simulation model source code Synopsys Inc January 17 2005 DesignWare IP Family DW_bc_10 Boundary Scan Cell Type BC_10 DW_bc_10 Boundary Scan Cell Type BC_10 Last Revised Release DWF_0212 e IEEE Standard 1149 1 2001 compliant pin_input g i e Synchronous or asynchronous scan cells with respect to am data_out F tck so S hift_d e Supports the standard instructions EXTEST SAMPLE eee Q PRELOAD and BYPASS output_data 2 e Supports the optional instructions RUNBIST CLAMP and Ga HIGHZ update_en gt update_clk gt capture_clk Table 1 Pin Description Pin Name Width Direction Function capture_clk 1 bit Input Clocks data into the capture stage update_clk 1 bit Input Clocks data into the update stage capture_en 1 bit Input Enable for data clocked into the capture stage active low update_en 1 bit Input Enable for data clocked into the update stage active high shift_dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo mode 1 bit Input Det
31. 6 oesot ys srta nrar be dedhesnenednecdereeneenees 297 DW8051 SUSI Microcontgller se 1h6i46senesS keene h4seee seen sabes sheeee eae Ges 299 Chapter 3 DesignWare Library Verification IP cc ccc ccc cece eee eee eee 301 OVECVIEW bd cud ease rair eS oe se ERS Os BREE e SEES EAReee sores eA 301 Wer OI onc waded dd epee enendtsd shed cuns E E O E 303 DesignWare AMBA AHB Models Master Slave Monitor Bus Interconnect 0 0 cee eee eee 304 DesignWare AMBA APB Models 10 Synopsys Inc January 17 2005 DesignWare IP Family Contents Master Slave MOMOL 4 25 44 4444004 die S44 de hob awed Heed ea eo ode HES 306 DesignWare VIP for AMBA 3 AXI Master Slave Monitor Interconnect 0 0 eee 307 Board Verification IP Simulation models for Board Verification 0 00 ccc eee eee eee 309 Ethernet 10 100 1G 10G Models Transceiver and MORUOl ciuccacduhidwdsdeeeladedachdenekwcks ene bean 310 Ethernet Models RMI Iransceiver and HUD cs 6 065 peered koe ASAE OROSS CHEERS ERE ORES 311 VC Models Transceiver and MONIO sas 4 44 b exite aan eoerneG 4003 8 aaE Ver pee bees 312 Memory Models Simulation models of memory devices 544 ss bo ceeee ged esee seeds esa ees 313 PCI Express Models Transceiver an IGRI aid cas ded bdededecsadebechieaeke aks bee bean 314 PCI PCI X Bus Models Masten Slave and MONNOY s24uds ea cedaceeasenaeeeiebeud oeace Ea 316 Serial ATA Models PRELIMINARY Pee a Montor nn 5 tree dk
32. ASICs The interface has the following features supports 10 Mb s and 100 Mb s data rates single clock reference is sourced from the MAC to PHY or from an external source and independent 2 bit wide transmit and receive paths e enethub_fx This FlexModel is the BFM that supports hub functionality for the MII MII 100 and GMII Ethernet MAC The following types of operations are performed by the model acts as a common PHY for all MACs connected on its MII ports and propagates the transmitted data from the transmitting MAC to all the MACs in the g m S h system 8 e gt 5 HUB in full Ethernet FlexModels Duplex Mode Rx0 Rx1 nee rmiirs fx RMI rmiirs_ fx x Mil lt i l SN gt ee Tx0 Tx enethub_ fx The individual DesignWare FlexModel databooks can be found with each model at http www synopsys com products designware ipdir September 1 2004 Synopsys Inc 311 DesignWare IP Family I2C Models I Moni I2C Models Transceiver and Monitor i2c_txrx_vmt Model e Full I2C Master and Slave functionality Multiple command streams allow e Start repeat start and stop for all Slave and Master to operate possible transfers ERE E rr m i e Supports all IC clocking speeds nie a Roan a eee e 7b 10b configurable slave address e Configurable Slave FIFOs allows testing of varied bus traffic patterns e Bus accurate timing e Notifie
33. Contents DesignWare IP Family dwcore_gig_ethernet_sub Synthesizable Gigabit Ethernet Subsystem 22s2 02sce4e000eeeese0as 339 dwcore_pci Synthesizable Universal PCL Controller soos eke dent ese euncauticessiews 341 dwcore_pcix Synthesizable PCI X Controller and Test Environment 343 dwc_pcie_endpoint PCI Express Endpoint Synthesizable Core 242642 44405404056 40059 23445 345 dwc_pcie_rootport PCI Express Root Port Synthesizable Core lt 0 02cs2cnectssetsuasawecaves 347 dwc_pcie_switchport PCI Express Switch Port Synthesizable Core 6 22acscceeseGecneeeudet 349 dwc_pcie_dualmode PCI Express RC EP Dual Mode Synthesizable Core 0 350 dwcore_pcie_phy Pe ee PHY COE 6 ah os hse owe be eh oe Banden hee eaie eens 352 dwcore_sd_mmc_host Secure Digital SD and Multimedia Card MMC Host Controller 353 dwcore_usb1_device Synthesizable USB 1 1 Device Controll r c c2s4 x26 ooe50 e444 eexees bens 355 dwcore_usb1_host Syuthesizable USB 1 1 OHCI Host Controller 6c lt cscseoeciewcesosanes 357 dwcore_usb1_hub Synthesizable USB 1 1 Hub Controller 2c4ccccacusedistiauwaneted dnor 359 dwcore_usb2_hsotg Synthesizable USB 2 0 Hi Speed On the Go Controller Subsystem 362 dwcore_usb2_host Synthesizable USB 2 0 Host Controller ss issorercisisesrsissivsdridai 364 dwcore_usb2_device Synthesizable USB 2 0 Device Controller cccrcissniriiirescediisietisi 366 dwcore_usb2_phy USB 2 0 Trans
34. DesignPower DesignWare EPIC Formality HSPICE Hypermodel iN Phase InSpecs in Sync Leda MAST Meta Meta Software ModelAccess ModelTools NanoSim OpenVera PathMill Photolynx Physical Compiler PowerMill PrimeTime RailMill Raphael RapidScript Saber SiVL SmartLogic SNUG SolvNet Stream Driven Simulator Superlog System Compiler Testify TetraMAX TimeMill TMA VCS Vera and Virtual Stepper are registered trademarks of Synopsys Inc Trademarks abraCAD abraMAP Active Parasitics AFGen Apollo Apollo Il Apollo DPII Apollo GA ApolloGAIl Astro Astro Rail Astro Xtalk Aurora AvanTestchip AvanWaves BCView Behavioral Compiler BOA BRT Cedar ChipPlanner Circuit Analysis Columbia Columbia CE Comet 3D Cosmos CosmosEnterprise CosmosLE CosmosScope CosmosSE Cyclelink Davinci DC Expert DC Expert Plus DC Professional DC Ultra DC Ultra Plus Design Advisor Design Analyzer Design Vision DesignerHDL DesignTime DFM Workbench DFT Compiler Direct RTL Direct Silicon Access DW8051 DWPCI Dynamic Macromodeling Dynamic Model Switcher ECL Compiler ECO Compiler EDAnavigator Encore Encore PQ Evaccess ExpressModel Floorplan Manager Formal Model Checker FoundryModel FPGA Compiler Il FPGA Express Frame Compiler Galaxy Gatran HDL Advisor HDL Compiler Hercules Hercules Explorer Hercules ll Hierarchical Optimization Technology High Performance Option HotPlace HSPICE Link iN Tandem Integr
35. Inc January 17 2005 DesignWare IP Family Digital Signal Processing DSP Digital Signal Processing DSP This section documents the DSP components of the DesignWare Building Block IP Currently there are two digital FIR filter components designed for applications requiring programmable coefficients for either high speed or area efficient filtering g m wo lt m gt D 2 N D 2 D 5 January 17 2005 Synopsys Inc 155 DesignWare IP Family DW_fir High Speed Digital FIR Filter DW_fir High Speed Digital FIR Filter e High speed transposed canonical FIR filter architecture i coef_shift_en e Parameterized coefficient data and accumulator word lengths data_in coef_out e Parameterized filter order coef in e Serially loadable coefficients data_out i TERO init_acc_val e Cascadable architecture for easy partitioning gt clk rst_n Applications e 1 D FIR filtering e Matched filtering e Correlation e Pulse shaping e Adaptive filtering e Equalization Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock All internal registers are sensitive on the positive edge of clk and all setup and hold times are with respect to this edge of clk rst_n 1 bit Input Asynchronous reset active low Clears all coefficient and data values coef_shift_en 1 bit Input Enable coefficient shift loading at coef_in active high tc 1 bit Input Def
36. PCI Express PCI X PCI USB On the Go and more Microprocessor and DSP cores from industry leading Star IP providers Foundry Libraries Board verification IP Microcontrollers 8051 and 6811 A single license gives you access to all the IP in the library For more information on the DesignWare Library refer to the following http www synopsys com products designware dwlibrary html or call us at 1 877 4BEST IP For a detailed search of the available IP refer to the following 20 http www synopsys com products designware Synopsys Inc January 17 2005 DesignWare IP Family Chapter 1 Overview Building Block IP The DesignWare Building Block IP is a collection of over 140 technology independent high quality high performance IP Most of these IP elements include multiple implementations to provide a variety of performance and area tradeoff options Component groups for the Building Block IP are identified in the following table For more detail refer to Building Block IP on page 31 Component Group Description Component Type Datapath Arithmetic floating point trigonometric and Synthesizable RTL sequential math IP page 50 Data Integrity Data integrity IP such as CRC ECC 8b10b Synthesizable RTL page 141 Digital Signal FIR and IIR filters page 155 Synthesizable RTL Processing DSP Interface Debugger IP page 47 Synthesizable RTL Logic Combinational sequ
37. RMON Provides complete status for transmission and reception packets Highly programmable DMA engine to meet optimal bus performance Synopsys Inc Programmable descriptor based interrupt DMA architecture minimizes CPU overhead Supports programmable interrupt options for different operational conditions Includes two dual port RAM based FIFOs one for transmission and one for reception Optimized for switching routing network interface card and system on chip applications Supports Virtual LAN VLAN Detection Power management support Remote Wake up LAN and magic packets Synthesizable Verilog source code January 17 2005 DesignWare IP Family C Og dwcore_gig_ethernet_sub S Synthesizable Gigabit Ethernet Subsystem MAC DMA Controller MAC Transaction Media Access Controller GMAC MDC Layer MTL Host Interface lt gt Transmit ATI 4 MTI Transmit Master SS RGMII SGMII MHI RMIII K Receive ARI MRI Receive Control and Status one and Registers atus Registers Host Interface Slave MCI The dwcore_gig_ethernet_sub data sheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_gig_ethernet_sub pdf 010 MA January 17 2005 Synopsys
38. Two s complement input is converted into unsigned magnitude Output is unsigned positive Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock rst_n 1 bit Input Reset active low hold 1 bit Input Hold current operation 1 start 1 bit Input Start operation 1 A new operation is started by setting start 1 for one clock cycle a width bit s Input Radicand complete 1 bit Output Operation completed 1 root width 1 2 bit s Output Square root Table 2 Parameter Description Parameter Values Description width 26 Word length of a tc_mode O or 1 Two s complement control Default 0 0 unsigned 1 two s complement num_cyc 23 and lt width User defined number of clock cycles to produce a valid Default 3 result The real number of clock cycles depends on various parameters rst_mode Oor 1 Reset mode Default 0 0 asynchronous reset 1 synchronous reset January 17 2005 Synopsys Inc 135 DesignWare IP Family DW_sqrt_seq Sequential Square Root Table 2 Parameter Description Continued Parameter Values Description input_mode Oor 1 Registered inputs Default 1 0 no 1 yes output_mode Oor 1 Registered outputs Default 1 0 no 1 yes early_start Oor 1 Computation start Default 0 0 start computation in the second cycle 1 start computation in the first cycle
39. and decoding Scrambling o Command Legacy DMA Descrambling Legacy queued DMA Packet PIO e Native command queuing Register and First party DMA e Power management commands e Far end retimed loop back e Native command queuing Far end transmit only and e Issues informative messages Far end analog loop back BIST modes e OOB signal detection and transmission e Error injection detection Design Under Test SATA Host Internal Bus Bus Interface Link Layer Transport Layer SAPIS like I F The DesignWare SATA Verification IP User Manual is available at http www synopsys com products designware docs 317 Synopsys Inc January 17 2005 DesignWare IP Family Serial Input Output Interface Models Tranceiver and Monitor Serial Input Output Interface Models Tranceiver and Monitor SIO TxRx Model sio_txrx_vmt SIO Monitor Model e Full duplex operation sio_monitor_vmt e Fully configurable serial interface e Protocol checking e Both GPIO and SIO port interfaces e Transaction logging e Configurable receive FIFO depth e Watchpoint monitoring e Configurable internal baud clock e Configurable to match TxRx model e Programmable hardware flow control e Configurable internal baud clock e IrDA SIR infrared mode support e Programmable hardware flow control e Error generation injection capability e IrDA SIR infrared mode support e Parity generate check odd even none e Parity generation and checking space mar
40. ej Cc g PCI Parity p A Request FIFO E gt lt DMA Register 2 a a Q a Ea a Configuration Multiplexer Target Read g Fsi Be E FIFO a PCI Bus Target Write gt Register FIFO m gt Address FIFO gt Target State Goad Machine Address ecos Compare b bA The dwcore_pci data sheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_pci pdf 010 MA January 17 2005 Synopsys Inc 342 DesignWare IP Family dwcore_pcix Synthesizable PCI X Controller and Test Environment dwcore_pcix Synthesizable PCI X Controller and Test Environment C KN The Synopsys DesignWare PCI X Controller is a set of Verilog RTL synthesizable building blocks ASIC designers use to implement a complete PCI X interface PCI X is highly suitable in a wide range of applications such as SCSI Fibre Channel Gigabit Ethernet and graphics Other features include the following PCI X 1 0a compliant Dual Address Cycles DAC Host Bridge functionality Message Signaled Interrupts MSI PCI 2 3 compliant External EEPROM support 32 bit or 64 bit PCI X bus path Comprehensive Test Environment 64 bit application data path Device Under Test linkable to the test Supports 0 133 MHz PCI X bus ee Supports up to 32 outstanding delayed split transactions e RapidScript parameterized configuration for fast customization e Synthesizable Verilog source code 343 Synopsys Inc January 17 2005 DesignWar
41. o 5 empty error e Word integrity flag for gt clk rst_n data_in_width lt data_out_width e Flushing out partial word for data_in_width lt data_out_width e Parameterized byte or subword order within a word e FIFO error flag indicating underflow overflow and pointer corruption e Parameterized word depth e Parameterized almost full and almost empty flags e Parameterized reset mode synchronous or asynchronous memory array initialized or not January 17 2005 Synopsys Inc 185 DesignWare IP Family DW_asymfifo_s1_sf Asymmetric I O Synchronous Single Clock FIFO with Static Flags Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 synchronous if rst_mode 1 push_req_n 1 bit Input FIFO push request active low flush_n 1 bit Input Flushes the partial word into memory fills in 0 s for data_in_width lt data_out_width only pop_req_n 1 bit Input FIFO pop request active low diag_n 1 bit Input Diagnostic control active low for err_mode 0 NC for other err_mode values data_in data_in_width bit s Input FIFO data to push empty 1 bit Output FIFO empty output active high almost_empty 1 bit Output FIFO almost empty output active high asserted when FIFO level lt ae_level half_full 1 bit Output FIFO half ful
42. rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none clf Fast carry look ahead synthesis model DesignWare clsa MC inside DW carry look ahead select DesignWare csa MC inside DW carry select DesignWare fastcla gt MC inside DW fast carry look ahead DesignWare pprefix MC inside DW flexible parallel prefix DesignWare pparch Delay optimized flexible parallel prefix DesignWare 78 Synopsys Inc January 17 2005 DesignWare IP Family DW01_ inc Incrementer a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc_shell t variable dw_prefer_mc_inside must be set to true From the DC 2004 12 release onward the MC architectures are not available by default For more information refer to the DesignWare Building Block IP Users Guide c This delay optimized parallel prefix architecture is generated using Datapath generator technology DW gensh This is ON by default in the Design Compiler flow The DC variable synlib_
43. spi_miso_out_en spi_mosi_out_en spi_sck_out_en mem_bus interrupts DW_6811_spi optional sci_txd sci_rxd sci_txd_en sci_rxd_en irom_bus Internal ROM iROM OK 4K 8K 16K 32K or 64K DW_6811_sci optional ir stop_mode wait_mode test_addr The DesignWare DW_6811 MacroCell Databook is available at http www synopsys com products designware docs 298 Synopsys Inc January 17 2005 DesignWare IP Family Mac C DW8051 A 8051 Microcontroller DW8051 8051 Microcontroller e Compatible with industry standard 803x 805x o Standard 8051 instruction set o Optional full duplex serial ports selectable through parameters o Optional third timer selectable through parameter o Control signals for standard 803x 805x I O ports e High speed architecture o Four clocks per instruction cycle o 2 5X average improvement in instruction execution time over the standard 8051 o Runs greater than 300 MHz in 90 nanometer process technology o Wasted bus cycles eliminated o Dual data pointers January 17 2005 Synopsys Inc Parameterizable internal RAM address range Parameterizable internal ROM address range Simple integration of user defined peripherals through external Special Function Register SFR interface Enhanced memory interface with 16 bit address bus Variable length MOVX to access fast slow RAM peripherals Fully static synchronous design 299 g
44. timer_intr_flag_n timer_N_toggle The DesignWare DW_apb_timers Databook is available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 281 DesignWare IP Family DW_apb_uart APB Universal Asynchronous Receiver Transmitter DW_apb_uart APB Universal Asynchronous Receiver Transmitter Functionality based on the industry standard 16550 AMBA 2 0 compliant APB Interface with synthesis selectable prdata and pwdata bus widths 8 16 32 Synthesis selectable transmit and receive FIFO depths None 16 32 64 2048 Synthesis selectable internal RAM based on DesignWare D flip flop DW_ram_r_w_s_dff Synthesis selectable synchronous or asynchronous external Read Port RAM interface when external RAMs are selected Synthesis selectable asynchronous serial clock support pclk or pclk and sclk Synthesis selectable lock up latch insertion before clock boundary crossing in two clock implementations for test purposes Synthesis selectable 16750 compatible Programmable Auto Flow Control mode Auto CTS and Auto RTS Auto Flow Control significantly reduces software load and increases system performance by automatically controlling serial data flow Synthesis selectable Programmable Transmitter Holding Register THRE Interrupt mode This mode increases system performance by providing the host enough time to respond before the transmitter FIFO runs completely em
45. 1 single register synchronization from push pointer 2 double register 3 triple register rst_mode 0 or 3 Default 1 Reset mode 0 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding memory 3 synchronous reset excluding memory January 17 2005 Synopsys Inc 191 g wo lt m gt 0 o N D D 5 192 DesignWare IP Family DW_asymfifo_s2_sf Asymmetric Synchronous Dual Clock FIFO with Static Flags Table 2 Parameter Description Continued byte_order Oorl Parameter Values Description Default 0 Order of bytes or subword within a word 0 first byte is in most significant bits position 1 first byte is in the least significant bits position a Valid depth values include binary numbers from 8 to 256 i e 8 16 32 64 etc and all odd values between 8 and 256 Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare el2 Full carry look ahead model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide Synopsys Inc January 17 2005
46. 2005 Synopsys Inc 27 Chapter 1 Overview DesignWare Cores The DesignWare Cores shown in the following table provide system designers with silicon proven digital and analog connectivity IP DesignWare Cores are licensed individually on a fee per project business model DesignWare IP Family IP Directory Component Name Component Description Component Type Ethernet Cores dwcore_ethernet Ethernet MAC 10 100 Mbps Operation Synthesizable RTL page 333 dwcore_ethernet_sub Ethernet MAC Subsystem page 335 Synthesizable RTL dwcore_gig ethernet Gigabit Ethernet MAC 10 100 Mbps and Synthesizable RTL 1 Gbps Operation page 337 dwcore_gig_ethernet_sub Gigabit Ethernet MAC GMAC Subsystem Synthesizable RTL page 339 Flash Memory Controller Core dwcore_sd_mmc_host Secure Digital SD and Multimedia Card Synthesizable RTL MMC Host Controller page 353 IEEE 1394 Cores dwcore_1394_avlink TEEE 1394 AVLink page 372 Synthesizable RTL dweore_1394_cphy IEEE 1394 Cable PHY page 374 Synthesizable RTL JPEG Core dwcore_jpeg_codec JPEG CODEC page 376 Synthesizable RTL PCI Cores dwcore_pci 32 64 bit 33 66 MHz PCI Core page 341 Synthesizable RTL dwcore_pcix 32 64 bit 133 MHz PCI X Core page 343 Synthesizable RTL PCI Express Cores dwc_pcie_endpoint PCI Express Endpoint Core page 345 Synthesizable RTL dwc_pcie_rootport PCI Express Ro
47. 7 AM to 5 30 PM Pacific Time Mon Fri o Canada Call 1 650 584 4200 from 7 AM to 5 30 PM Pacific Time Mon Fri o All other countries Find other local support center telephone numbers at the following URL http www synopsys com support support_ctr Additional Information For additional Synopsys documentation refer to the following page http www synopsys com products designware docs For up to date information about the latest implementation IP and verification models visit the DesignWare home page http www synopsys com designware Comments To report errors or make suggestions please send e mail to support_center synopsys com To report an error that occurs on a specific page select the entire page including headers and footers and copy to the buffer Then paste the buffer to the body of your e mail message This will provide us with information to identify the source of the problem January 17 2005 Synopsys Inc 17 Preface DesignWare IP Family 18 Synopsys Inc January 17 2005 DesignWare IP Family Chapter 1 Overview 1 Overview Synopsys DesignWare IP the world s most widely used silicon proven IP provides designers with a broad portfolio of synthesizable implementation IP hardened PHYs and verification IP for ASIC SoC and FPGA designs The DesignWare family includes the following products e DesignWare Library on page 20 contains the principal ingredients for design and verifi
48. B_width 41 DesignWare or a Booth Wallace tree A_width B_width gt 41 synthesis model January 17 2005 Synopsys Inc 103 g m wo lt m gt D 2 N D 2 D 5 DesignWare IP Family DW02_prod_sum1 Multiplier Adder a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b In most cases the wall implementation generates both faster and smaller circuits for medium to large sized multipliers c In cases where A_width B_width 41 the nbw implementation generates a non Booth recoded Wallace tree multiplier For multipliers having products larger than 41 bits such as A_width B_width gt 41 the nbw implementation produces a Booth recoded multiplier identical to the wall implementation 104 Synopsys Inc January 17 2005 DW_prod_sum_pipe Stallable Pipelined Generalized Sum of Products e Parameterized word length e Unsigned and signed two s complement data operation DesignWare IP Family DW_prod_sum_pipe Stallable Pipelined Generalized Sum of Products e Parameterized number of pipeline stages e Parameterized stall mode stallable or non stallable e Parameterized reset mode no reset asynchronous or synchronous reset e Automatic pipeline r
49. Datapath technology 56 Synopsys Inc January 17 2005 DesignWare IP Family DW_addsub_dx Duplex Adder Subtractor with Saturation and Rounding DW _addsub dx Duplex Adder Subtractor with Saturation and Rounding e Selectable single full width Add Sub simplex or two smaller width Add Sub operations duplex e Selectable saturation mode e Selectable average mode e Selectable number system unsigned or twos complement g m wn lt S gt D o N D gt D 5 e Parameterized full word width e Parameterized partial word width allowing for asymmetric partial width operations e Carry out signals one for lower half and one for full and upper half that numerically extend the calculated sum maintaining full precision e Carry in signals one for full and lower half and one for upper half Table 1 Pin Description PinName Width Direction Function a width bit s Input Input data b width bit s Input Input data cil 1 bit Input Full or part1 carry input ci2 1 bit Input Part2 carry input addsub 1 bit Input Add subtract select input 0 performs add 1 performs subtract tc 1 bit Input Two s complement select active high sat 1 bit Input Saturation mode select active high avg 1 bit Input Average mode select active high dplx 1 bit Input Duplex mode select active high sum width bit s Output Output data January 17 2005 Synopsys I
50. Description Parameter Values Description data_in_width 21 Input data word length coef_width gt 1 Coefficient word length data_out_width gt 1 Accumulator word length order 2 to 256 FIR filter order a The parameter data_out_width is normally set to a value of coef_width data_in_width margin The value coef_width data_in_width accounts for the internal coefficient multiplications An appropriate margin must be included if the filter coefficients have a gain or are cascaded The value margin lt log2 order Table 3 Synthesis Implementations Implementation Name Function License Required str Structural synthesis model DesignWare January 17 2005 Synopsys Inc 157 DesignWare IP Family DW_fir_seq Sequential Digital FIR Filter DW_fir_seq Sequential Digital FIR Filter e Area efficient multi cycle implementation e Parameterized coefficient data and accumulator coef_shift_en run tc word lengths data_in start e Parameterized filter order coef_in hold e Serially loadable coefficients e Cascadable architecture for easy partitioning init_acc_val data_out Applications e 1 D FIR filtering e Matched filtering e Correlation e Pulse shaping e Adaptive filtering e Equalization Table 1 Pin Description Pin Name Size Direction Function clk 1 bit Input Clock All internal registers are sensitive to the positive edge
51. Inc 340 DesignWare IP Family dwcore_pci Synthesizable Universal PCI Controller dwcore_pci Synthesizable Universal PCI Controller C KN The Synopsys DesignWare PCI intellectual property IP products are Verilog RTL synthesizable modules that provide an interface between the application and the PCI bus Features include the following e PCI specification 2 3 compliant 15 application optimized PCI IP available in Verilog Silicon proven 33 MHz and 66 MHz performance 32 bit or 64 bit PCI bus path e 32 bit or 64 bit application data path Zero Latency Fast Back to Back transfers Zero Wait State Burst Mode transfers Support for Memory Read Line Multiple and Memory Write and Invalidate commands Dual Address cycles Loadable configuration space Universal configuration optimized for use in both Host Bridge and Add in Card designs Delayed Read support PCI power management support e PCI multifunction support 341 Synopsys Inc January 17 2005 DesignWare IP Family te dwcore_pci S Synthesizable Universal PCI Controller yN r n PCI Controller Multiplexer Master Write Register FIFO DE PCI ADout Register PCI Bus Master Read Output Register gt FIFO g Mux o O oO D Master e a
52. MCS MAC Management Counters MMC Address Check Book ACH MAC Block Flow Control Power Management Block PMT MII Management MIM PHY Interface The dwcore_ethernet data sheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_ethernet pdf 010 MA January 17 2005 Synopsys Inc 334 DesignWare IP Family dwcore_ethernet_sub Synthesizable Ethernet Subsystem dwcore_ ethernet sub Synthesizable Ethernet Subsystem The Synopsys DesignWare Ethernet Media Access Controller MAC Subsystem enables the host to communicate data using the Ethernet protocol IEEE 802 3 The subsystem is composed of three main layers the DMA the Transaction Layer Interface TLI and the Media Access Controller MAC The Synopsy Ethernet MAC Subsystem enables Ethernet functionality for switch NIC and system on chip applications Ethernet MAC implements more than the traditional functionality of standard MACs including a MAC Host Station Management Address Check and Control Status Register CSR blocks These additional blocks provide the higher level system functionality that is traditionally implemented in firmware or using separate products With these additional capabilities the Ethernet MAC simplifies the system implementation effort Features include the following e Compliant with IEEE 802 3 and e Uses descriptor based DMA 802 3u specif
53. Output FIFO error output active high part_wd 1 bit Output Partial word active high for data_in_width lt data_out_width only otherwise tied low data_out data_out_width bit s Output FIFO data to pop January 17 2005 Synopsys Inc 183 DesignWare IP Family DW_asymfifo_s1_df Asymmetric I O Synchronous Single Clock FIFO with Dynamic Flag Tit Table 2 Parameter Description Parameter Values Description data_in_width 1 to 256 Width of the data_in bus data_in_width must be in an integer multiple relationship with data_out_width That is either data_in_width K x data_out_width or data_out_width K x data_in_width where K is an integer data_out_width 1 to 256 Width of the data_out bus data_out_width must be in an integer multiple relationship with data_in_width That is either data_in_width K x data_out_width or data_out_width K x data_in_width where K is an integer depth 2 to 256 Number of memory elements used in the FIFO addr_width ceil log depth err_mode 0 to 2 Error mode Default 1 0 underflow overflow with pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode 0 to 3 Reset mode Default 1 0 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding memory 3 synchronous re
54. Overview e Highly configurable number of lanes e PCI Express is a high speed serial process rates for received packets and interface replacement for the older PCI completion packets transaction and PCI X parallel bus standards ordering rules packet payload sizes e The transceiver is fully bus functional symbol times between transmissions of and can verify PCI Express endpoints Ack Data Link layer packets number switches and root complex devices of SKIP symbols in a SKIP e The monitor provides detailed ordered set time out parameters etc transaction logging and coverage of the PCI Express Compliance Checklist Requester e Generates single word read and write Major Features transfers to memory I O and e Verification at PHY MAC interface of configuration space x1 x2 x4 x8 x12 x16 lanes e Generates block read and write e Full Link Training LTSSM support transfers to memory space e Protocol and compliance monitor e Generates message transfers which generates transaction and e Transmits raw request packets created symbol log files by user e Full Requester and Completer e Custom error injection functions e Automatic handling of completion e Multiple transfers initiated packets or optional handling of concurrently completion packets by testbench e Automatically generates flow control packets Completer e Automatically handles Transaction e Reads and writes internal address Data Link and Physical layer tasks spaces in respo
55. Parameterized byte order within a word e Word integrity flag for data_in_width lt data_out_width e Partial word flush for data_in_width lt data_out_width wr_data we_n wr_addr push_req_n Push_empty push_ae push_hf push_af push_full ram_full part_wd push_error data_in flush_n gt clk_push data_out rd_addr pop_empty pop_ae pop_hf pop_af pop_full pop_error rst_n pop_req_n gt clk_pop e Interfaces to common hard macro or compiled ASIC dual port synchronous RAMs Table 1 Pin Description Pin Name Width Direction Function clk_push 1 bit Input Input clock for push interface clk_pop 1 bit Input Input clock for pop interface rst_n 1 bit Input Reset input active low push_req_n 1 bit Input FIFO push request active low flush_n 1 bit Input Flushes the partial word into memory fills in 0 s for data_in_width lt data_out_width only pop_req_n 1 bit Input FIFO pop request active low data_in data_in_width bit s Input FIFO data to push rd_data max data_in_width Input RAM data input to FIFO controller data_out_width bit s 206 Synopsys Inc January 17 2005 Tit DesignWare IP Family DW_asymfifoctl_s2_sf Asymmetric Synchronous Dual Clock FIFO Controller with Static Flags Table 1 Pin Description Continued Pin Name Width Direction Function we_n 1 bit Output Write enable output for write port of RAM a
56. Parameterized full word width e Parameterized partial word width allowing for asymmetric partial width operations Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Input data b width bit s Input Input data tc 1 bit Input Two s complement control dplx 1 bit Input Duplex mode select active high product width x 2 bit s Output Product s Table 2 Parameter Description Parameter Values Description width gt 4a Word width of a and b pl_width 2 to width2 Word width of Part1 of duplex multiplier a Due to the limitation of memory addressing ranges of the computer operating system there is an upper limit for parameter width b For the best performance of DW_mult_dx p _width should be set in the range width 2 width 2 Table 3 Synthesis Implementations Implementation Name Function License Feature Required wall Booth recoded Wallace tree synthesis model DesignWare 98 Synopsys Inc January 17 2005 DW_mult_pipe Stallable Pipelined multiplier e Parameterized word length e Unsigned and signed two s complement pipelined multiplication e Parameterized number of pipeline stages e Parameterized stall mode stallable or non stallable e Parameterized reset mode no reset asynchronous or synchronous reset e Automatic pipeline retiming DesignWare IP Family DW_mult_p
57. Parameterized word length e Parameterized count to value a e Up down count control up_dn tercnt e Asynchronous reset cen e Loadable count register load e Terminal count flag gt clk reset e Counter enable Table 1 Pin Description Pin Name Width Direction Function data width Input Counter load input up_dn 1 bit Input High for count up and low for count down load 1 bit Input Enable data load to counter active low cen 1 bit Input Count enable active high clk 1 bit Input Clock reset 1 bit Input Counter reset active low count width Output Output count bus tercnt 1 bit Output Terminal count flag Table 2 Parameter Description Parameter Values Description width 1 to 30 Width of data and count count_to 1 to 2 idth 1 Count to value Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare 172 Synopsys Inc January 17 2005 ee DW03_bictr_decode Up Down Binary Counter with Output Decode e Up down count control Asynchronous reset Loadable count register Counter enable Terminal count flag DesignWare IP Family DW03_bictr_decode Up Down Binary Counter with Output Decode count_dec up_dn cen load y clk reset Table 1 Pin Description tercnt
58. The Go Models 1 1 2 0 OTG UTMI VMT page 320 usb_device_vmt and UTMI page 319 usb_monitor_vmt DesignWare Design Views of Star IP Microprocessors and DSP Core DW_IBM440 PowerPC 440 32 Bit Microprocessor Core from Compiled model IBM page 379 DW_V850E Star V850E 32 Bit Processor Core from NEC Compiled model page 381 DW_C166S 16 Bit Microcontroller Subsystem from Compiled model Infineon page 383 DW_TriCorel TriCore1 32 Bit Processor Core from Infineon Compiled model page 385 DW_MIPS4KE MIPS32 4KE 32 Bit Processor Core Family Compiled model from MIPS Technologies page 387 DW_CoolFlux CoolFlux 24 bit DSP Core from Philips Compiled model page 389 DesignWare Memory Access to the full suite of memory IP is made Memory Models available through DesignWare Memory Central a memory focused Web site that lets designers download DesignWare Memory IP and documentation Visit Memory Central at http www synopsys com products designware memorycentral SmartModel Library is a collection of over 3 000 binary behavioral SmartModels models of standard integrated circuits supporting more than 12 000 page 324 Synopsys Inc January 17 2005 DesignWare IP Famil Chapter 3 DesignWare Library Verification IP g y Verification Models The following datasheet pages are ordered alphabetically and briefly describe each Verification Model g m S O g e gt Ea January 17 2005 Synopsy
59. V850E1 instruction set Supports 32 bit and 16 bit instruction formats 64 MB linear address program memory space 4 GB linear address data memory space V850E1 CPU O O O Five stage pipeline 32 bit datapath Simultaneous transfer of instruction and data on separate buses Harvard architecture RISC architecture plus special instructions for saturation bit manipulation and multiply using integrated hardware multiplier 32 general purpose 32 bit registers e Instruction cache optional See the block diagram on the following page 381 Synopsys Inc Data cache optional Integrated 4 channel DMA optional e Integrated interrupt controller supporting 3 external non maskable interrupts NMIs and up to 64 external maskable interrupts Integrated run control unit optional Separate interfaces to internal ROM and RAM V850E System Bus VSB interface to high speed peripherals NEC Peripheral Bus NPB interface to low speed peripherals Legacy bus for backward compatibility with NEC internal designs Power management through HALT instruction and hardware or software generated stop mode implemented by standby control unit STBC e Fully synchronous design VSB to AHB bridge for integration into AMBA based systems January 17 2005 DesignWare IP Family 9p Ib DW_V850E Star V850E Microcontroller Core from NEC Electronics Run
60. Values Description width gt 1 Word length of a b c sum and carry Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare 70 Synopsys Inc January 17 2005 DesignWare IP Family DW01_dec Decrementer DW01_dec Decrementer e Parameterized word length g iz Ss gt D 2 N D o ye 3 Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data SUM width bit s Output Decremented A 1 Table 2 Parameter Description Parameter Values Description width 21 Word length of A and SUM Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none clf Fast carry look ahead synthesis model DesignWare clsa gt MC inside DW carry look ahead select DesignWare csa MC inside DW carry select DesignWare fastcla MC inside DW fast carry look ahead DesignWare pprefix MC inside DW flexible parallel prefix DesignWare pparch Delay optimized flexible parallel prefix DesignWare January 17 2005 Synopsys Inc 71 DesignWare IP Family DW01 dec Decrementer a During synthesis Design Compiler will select the appropriate architecture for your constraints
61. Width Direction Function clk 1 bit Input Clock input rst_n 1 bit Input Asynchronous reset input active low init_rd_n 1 bit Input Synchronous initialization control input active low init_rd_val 1 bit Input Value of initial Running Disparity data_in bytes x 10 bit s Input Input 8b 10b data for decoding error 1 bit Output Active high error flag indicating the presence of any type of error running disparity or coding in the information currently decoded on data_out rd 1 bit Output Current Running Disparity after decoding data presented at data_in to data_out k_char bytes bit s Output Special Character indicators one indicator per decoded byte data_out bytes x 8 bit s Output Decoded output data rd_err 1 bit Output Active high error flag indicating the presence of one or more Running Disparity errors in the information currently decoded on data_out code_err bit Output Active high error flag indicating the presence of a coding error in at least one byte of information currently decoded on data_out enable 1 bit Input Enables register clocking 150 Synopsys Inc January 17 2005 DesignWare IP Family 00000000 11111111 odin DW_8b10b_dec 8b10b Decoder OO 0100 1010110001 Table 2 Parameter Description Parameter Values Description bytes 1 to 16 Number of bytes to encode Default 2 k28_5_only 0 or 1 Special Character su
62. _apb_gpio gt DW _apb_uart z i_wdt i_ssi1 EE DW_apb_wdt EEPROM DW_apb_ ssi i_rtc testbench T Se loopback DW_apb_rtc connections DW_apb_ssi i_timer i_i2c1 26 BIM_1 DW_apb_timers 12C_BIM_ 2 DW_apb_i2c I2C_BIM_3 i i202 I ES DW_apb_i2c s slave 511 m master DW_amba_subsystem_SingleLayer v 2 DW_apb_ssi i_ssil can also communicate with an EEPROM as opposed to the other DW_apb_ssi i_ssi2 3 DW_memctl i_memctl connects to five external memories three SRAMs one SDRAM and one FLASH January 17 2005 Synopsys Inc 289 DesignWare IP Family DesignWare AMBA QuickStart Collection of example designs for AMBA subsystems testbench v Testbench Slave AHB Configuration BEM and Stimulus 126 BIM_1 Masters Slaves 12C_BIM_2 I2C_BIM_3 DW_apb_i2c1 i_i2c1 DW_apb_i2c1 i_i2c2 DW_apb_rap i_rap DW_apb_wat i_wdt AHB BFM APB po or DSM Monitor Generation DW_apb_ssi pe see aS i_ssit DW_apb_ssi i_ssi2 DW_apb_uart i_uart1 DW_apb_uart i_uart2 DW_apb_gpio i_gpio DW_apb_rtc i_rtc DW_apb_timers i_timers DW_apb_ictl i_ictl Slave s slave m master Slave BFM EEPROM Master E AHB2 Lite SIO_BIM see tests
63. active low tms 1 bit Input Test mode select tdi 1 bit Input Test data in SO 1 bit Input Serial data from boundary scan register and data registers bypass_sel 1 bit Input Selects the bypass register active high sentinel_val width 1 bit s Input User defined status bits device_id_sel 1 bit Input Selects the device identification register active high user_code_sel 1 bit Input Selects the user_code_val bus for input in to the device identification register active high user_code_val 32 bits Input 32 bit user defined code ver 4 bits Input 4 bit version number January 17 2005 Synopsys Inc 247 DesignWare IP Family DW_tap_uc TAP Controller with USERCODE support Table 1 Pin Description Continued Pin Name Width Direction Function ver_sel 1 bit Input Selects version from the parameter or the ver input port 0 version parameter 1 ver input port part_num 16 bits Input 16 bit part number part_num_sel 1 bit Input Selects part from the parameter or the part_num from the input port 0 part parameter 1 part_num input port mnfr_id 11 bits Input 11 bit JEDEC manufacturer s identity code mnfr_id 127 mnfr_id_sel 1 bit Input Selects man_num from the parameter or mnfr_id from the input port 0 man_num parameter 1 mnfr_id input port clock_dr 1 bit Output Clocks in data in asynchronous mode shift_dr 1 bit Output Enables shif
64. architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 90 Synopsys Inc January 17 2005 DesignWare IP Family DW02_mult_2_stage Two Stage Pipelined Multiplier b The csa implementation is only valid when the sum of A_width and B_width lt A8 bits as it has no area benefit beyond 48 bits g m wo lt m gt D 2 N D 2 D 5 January 17 2005 Synopsys Inc 91 DesignWare IP Family DW02_mult_3_stage Three Stage Pipelined Multiplier DW02_mult_3_stage Three Stage Pipelined Multiplier e Parameterized word length Automatic pipeline retiming Unsigned and signed two s complement data operation Three stage pipelined architecture Inferable from Behavioral Compiler Table 1 Pin Description Pin Name Width Direction Function A A_width bit s Input Multiplier B B_width bit s Input Multiplicand TC 1 bit Input Two s complement control 0 unsigned 1 signed CLK 1 bit Input Clock PRODUCT A_width B_width bit s Output Product A x B Table 2 Parameter Description Parameter Values Description A_width 21 Word length of A B_ width gt For csa architecture A_width B_width lt A8 Word length of B Table 3 Synthesis Implementations Implementation Name Function csa gt Carry save array synthesis model DesignWare s
65. connection through SmartModels listed in IP Directory Web site 324 Star IP Core DW_C166S 383 DW_CoolFlux 389 DW_IBM440 379 January 17 2005 Index DW_MIPS4KE 387 DW_TriCorel 385 DW_V850E Star 381 Star IP overview 378 SWIFT interface connection between SmartModels and simulators 324 Synopsys Common Licensing 16 Synthesizable IP See also DesignWare Library Synthesizable IP T TSMC Libraries 326 U USB On The Go Models 319 usb_device_vmt 319 usb_host_vmt 319 usb_monitor_vmt 319 y Verification IP for Bus and I O Standards listing 25 Verification IP overview 301 VMT Models overview 320 Synopsys Inc 396 Index DesignWare IP Family 397 Synopsys Inc January 17 2005
66. data DATA_TC 1 bit Input Data two s complement control 0 unsigned 1 signed SH SH_width bit s Input Shift control SH_TC 1 bit Input Shift two s complement control 0 unsigned 1 signed B A_width bit s Output Output data Table 2 Parameter Description Parameter Values Description A_width 22 Word length of A and B SH_width 21 Word length of SH Dependency The mx2 implementation limits the value to 31 or less January 17 2005 Synopsys Inc 59 DesignWare IP Family DW01_ash Arithmetic Shifter Table 3 Synthesis Implementations Implementation Name Function License Feature Required mx2 Implement using 2 1 multiplexers only none The mx2 implementation is only valid for SH_width values up to and including 31 mx2i Implement using 2 1 inverting multiplexers and DesignWare 2 1 multiplexers mx2n Implement using 2 1 non inverting DesignWare multiplexers mx4 Implement using 4 1 and 2 1 multiplexers DesignWare mx8 Implement using 8 1 4 1 and 2 1 multiplexers DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 60 Synopsys Inc January 17 2005 DW_bin2gray Binary to Gray Converter e Parameterized word length e Inferable usi
67. dwcore_pci 32 64 bit 33 66 MHz PCI Synthesizable RTL Core page 341 dwcore_pcix 32 64 bit 133 MHz PCI X Synthesizable RTL Core page 343 PCI Express Cores dwc_pcie_endpoint PCI Express Endpoint Core Synthesizable RTL page 345 dwc_pcie_rootport PCI Express Root Port Core Synthesizable RTL page 347 dwc_pcie_switchport PCI Express Switch Port Synthesizable RTL Core page 349 dwc_pcie_dualmode PCI Express Dual Mode Synthesizable RTL Core page 350 dwcore_pcie_phy PCI Express PHY Core Hard IP page 352 SATA Core dwc_sata_host SATA Host page 370 Synthesizable RTL USB Cores dwcore_usb1_device USB 1 1 Device Controller Synthesizable RTL page 355 dwcore_usb1_host USB 1 1 OHCI Host Synthesizable RTL Controller page 357 dwcore_usb1l_hub USB 1 1 Hub Controller Synthesizable RTL page 359 331 Synopsys Inc January 17 2005 DesignWare IP Family Chapter 5 DesignWare Cores IP Directory Component Name Component Description Component Type dwcore_usb2_host USB 2 0 Host Controller Synthesizable RTL UHOST2 page 364 dwcore_usb2_hsotg USB 2 0 Hi Speed On the Synthesizable RTL Go Controller Subsystem page 362 dwcore_usb2_device USB 2 0 Device Controller Synthesizable RTL page 366 dwcore_usb2_phy USB 2 0 PHY page 368 Hard IP January 17 2005 Synopsys Inc 332 010 MA DesignWare IP Family dwcore_ethernet Synthesizable Ethern
68. e f 1 bits Output Optional floating point output of e f 1 bits Z1 e f 1 bits Output Optional floating point output of e f 1 bits STATUSO optional 8 bits Output Status flags corresponding to Z0 STATUS1 optional 8 bits Output Status flags corresponding to Z1 MAX optional 1 bit Input Determines Min Max operation of ZO and Z1 Table 2 Parameter Description Parameter Values Description e 3 to 31 bits Word length of biased exponent field of floating point number A f 2 to 253 bits Word length of fraction field of floating point number A arch 9 Architecture implementation a This component contains only one architecture Therefore the arch parameter should be set to 0 Table 3 Synthesis Implementations Implementation Name Function License Feature Required archO Synthesis model DesignWare January 17 2005 Synopsys Inc 125 DesignWare IP Family DW_div_fp Floating Point Divider DW_div_fp Floating Point Divider Module Compiler Only e The precision format is parameterizable for either IEEE single double precision or a user defined custom format e Exponents can range from 3 to 31 bits e Significand and fractional part of the floating point number can range from 2 to 256 bits e Accuracy conforms to IEEE 754 Floating Point standard Table 1 Pin Description Pin Name Width Direction Function A e f 1 bits Input Dividend B
69. flexible integrated and feature rich design environment that allows you to select configure interconnect simulate and synthesize DesignWare AMBA synthesizable IP and verification IP VIP Connect also performs the following functions e Initializes the address map for the subsystem g m wo lt m gt 0 2 N D D 5 e Generates the top level subsystem RTL code e Provides and executes a subsystem testbench using your chosen simulator The testbench integrates the Synopsys AMBA Verification IP with your design and generates register ping stimulus in Verilog or C code for every slave in the design Connect allows you to include empty DesignWare AMBA master and slave RTL shells with configurable I O that you can manually replace with your own IP at a later stage by simply modifying a few files Because you add these placeholders in the Connect subsystem all DesignWare AMBA and non AMBA connections to other blocks or top level I O are easily and correctly made in the Connect subsystem DesignWare AMBA Connect comes packaged with the following set of design starting points to ease initial AMBA subsystem creation e AHB subsystem A single AHB block e Single layer simple A single AHB APB AMBA subsystem with a single memory controller interrupt controller general purpose I O and a UART e Multi layer interconnect matrix design A dual AHB AMBA subsystem with a single interconnect matrix sharing the memory c
70. for APB data bus widths of 8 16 and 32 bits e Component parameters for configurable software driver support e DMA handshaking interface compatible with the DW_ahb_dmac handshaking interface DW_apb_i2c APB Slave I2c Interface Master Slave DMA Controller Interface TX FIFO Interrupts RX FIFO RX Filter 2 Clock R C Generator ebug The DesignWare DW_apb_i2c Databook is available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 275 DesignWare IP Family DW_apb_ictl APB Interrupt Controller DW_apb _ictl APB Interrupt Controller e 2 to 64 IRQ normal interrupt sources e Priority filtering optional e to 8 FIQ fast interrupt sources e Masking optional e Scan mode optional e Vectored interrupts optional e Programmable interrupt priorities e Software interrupts after configuration Y Note DW_apb_ictl is an exact replacement for the original component DW_amba_ictl name change only DW_apb_ictl IRQ Generation Interrupt FIQ Registers Generation Vector Generation amp Masking The DesignWare DW_apb_ictl Databook is available at http www synopsys com products designware docs 276 Synopsys Inc January 17 2005 DW_apb_rap APB Remap and Pause e Configuration of APB data bus width 8 16 or 32 e Remap Control
71. instruction caches optional Synopsys Inc Data types boolean integer with saturation bit array signed fraction character double word signed unsigned integers IEEE 754 single precision floating point Data formats bit byte 8 bits half word 16 bits word 32 bits double word 64 bits Zero overhead loop Instruction types arithmetic address comparison address comparison logical MAC shift coprocessor bit logical branch bit field load store packed data system MMU specific instructions Addressing modes absolute circular bit reverse long amp short base offset base offset with pre amp post update Multiply amp Accumulate MAC instructions dual 16 x 16 16 x 32 32 x 32 On Chip Debug Support OCDS Levels 1 amp 2 Bi directional FPI to AHB bridge for integration into AMBA based systems January 17 2005 DesignWare IP Family 9 Id DW_TriCore1 TriCore1 32 Bit Processor Core from Infineon Program Tag Coprocessor Data Tag Interface Interface Interface Program Data Memory Memory Interface PMI CPU DMI Api Local Memory Memory Bus BIST Luh Interface Interface Interrupt Controller Interrupt Interface Clock Reset and Control FPI Bus Debug Interface Interface Also see the following web page for additional information http www synopsys com products designware starip infineon_tricore1 html January 17 2005 Synopsys Inc 386 DesignWare IP Family DW_M
72. integer multiple of data_out_width That is either data_in_width K x data_out_width or data_out_width K x data_in_width where K is an integer data_out_width 1 to 256 Width of the data_out bus data_out_width must be an integer multiple of data_in_width That is either data_in_width K x data_out_width or data_out_width K x data_in_width where K is an integer depth 4 to 256 Number of words that can be stored in FIFO push_ae_lvl 1 to depth 1 Almost empty level for the push_ae output port the number of words in the FIFO at or below which the push_ae flag is active push_af_lvl 1 to depth 1 Almost full level for the push_af output port the number of empty memory locations in the FIFO at which the push_af flag is active pop_ae_lvl 1 to depth 1 Almost empty level for the pop_ae output port the number of words in the FIFO at or below which the pop_ae flag is active pop_af_lvl 1 to depth 1 Almost full level for the pop_af output port the number of empty memory locations in the FIFO at which the pop_af flag is active err_mode 0 or 1 Error mode 0 stays active until reset latched 1 active only as long as error condition exists unlatched push_sync 1 to3 Push flag synchronization mode 1 single register synchronization from pop pointer 2 double register 3 triple register pop_sync 1 to3 Pop flag synchronization mode
73. logs depth bit s Input Read2 address bus wr_addr ceil logs depth bit s Input Write address bus data_in data_width bit s Input Input data bus data_rdl_out data_width bit s Output Output data bus for read1 data_rd2_out data_width bit s Output Output data bus for read2 Table 2 Parameter Description Parameter Values Description data_width 1 to 256 Width of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare 228 Synopsys Inc January 17 2005 100111001 RAN DesignWare IP Family DW_ram_rw_s_dff Synchronous Single Port Read Write RAM Flip Flop Based DW_ram_rw_s _dff Synchronous Single Port Read Write RAM Flip Flop Based g m wn lt gt D o N D gt D 5 e Parameterized word depth rw_addr e Parameterized data width data_in e Synchronous static memory data out e Parameterized reset mode asynchronous or synchronous e Inferable by Behavioral Compiler gt clk stn e High testability using DFT Compiler Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock rst_n 1 bit Input Reset active low cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active
74. low rw_addr ceil log depth bit s Input Address bus data_in data_width bit s Input Input data bus data_out data_width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data_width 1 to 256 Width of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width rst_mode Oor 1 Determines the reset methodology 0 rst_n asynchronously initializes the RAM 1 rst_n synchronously initializes the RAM Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc 229 DesignWare IP Family 100111001 DW_ram_rw_s lat RAM Synchronous Single Port Read Write RAM Latch Based 01101001 DW_ram_rw_s lat Synchronous Single Port Read Write RAM Latch Based e Parameterized word depth rw_addr e Parameterized data width data_in data_out e Synchronous static memory cs_n wr_n e Inferable from Behavioral Compiler Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low rw_addr ceil logs depth bit s Input Address bus data_in data_width bit s Input Input data bus data_out data_width bit s Output Output data bus Table 2 Parameter Description
75. of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc 225 DesignWare IP Family 100111001 DW_ram_2r_w_s dff RAM Synchronous Write Port Asynchronous Dual Read Port RAM Flip Flop Basq 001101001 DW_ram_2r_w_s_dff Synchronous Write Port Asynchronous Dual Read Port RAM Flip Flop Based e Parameterized word depth rd1_addr rd2_addr e Parameterized data width wr_addr data_in e Synchronous static memory data_rd1_out e Parameterized reset mode synchronous or asynchronous data_rd2_out e Inferable from Behavioral Compiler e High testability using DFT Compiler Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock rst_n 1 bit Input Reset active low cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low rdl_addr ceil log depth bit s Input Read1 address bus rd2_addr ceil log depth bit s Input Read2 address bus wr_addr ceil log depth bit s Input Write address bus data_in data_width bit s Input Input data bus data_rdl_out data_width bit s Output Output data bus for read1 data_rd2_out data_width bit s Output Output data bus for read2 Table 2 Param
76. port Ability to enable disable testing of individual memories Multiple controller scheduling Support for incomplete address space January 17 2005 DesignWare IP Family Ny I O A DW_rambist Ms Memory Built In Self Test Design for test Design for Verifiability e Configuration of shadow logic capture e simulation_mode signal to provide verification of very large configurations and to quickly check system level interconnection e Sample script for scan chain creation and connection part of example design e Integration with DFT Compiler BSD Compiler and TetraMax g m wo lt m gt 0 2 N D D 5 DW_rambist monitor_bus gt bist_mode gt clk clk_t simulation_mode J Controller oO DW_rambist_ctrl _ BIST I F_O 3 mode_reg_si en Capture_0 e shift_dr F parallel_dr 3 mode_reg_in E mbrun ss rst_n_a S debug_so fe debug_out_N T mode_reg_out 3 mode_reg_so o o lt x z z oO 3 O Z o lt n 3 P number of ports 0 lt P lt 3 Mode Register width 1 0 N Memory number 0 lt N lt 31 2 Address width 1 0 __ _ 1 conditional blocks 3 Number of Memories 1 0 gt conditional signals These signals are for simulation purposes and should be left unconnected at the system level More information on the DW_rambist MacroCell can be found at http www synopsys com products designw
77. reporting APB Monitor AAAAAA APB APB l l l l AHB APB Master 4 gt Ye AHB APB Bridge Slave 1 Slave 2 The DesignWare APB Verification IP Databook is available at http www synopsys com products designware docs 306 Synopsys Inc January 17 2005 DesignWare IP Family DesignWare VIP for AMBA 3 AXI Master Slave Monitor Interconnect DesignWare VIP for AMBA 3 AXI Master Slave Monitor Interconnect All Models AXI e Compliant with AXI 1 0 specification e Supports all AXI data address widths e Supports all protocol transfer types and e response types e e Supports constrained randomization of protocol attributes e e Checks for all protocol violations e e Logs transactions and reports on protocol coverage e e Configurable message formatting AXI Master axi_master_vmt Configurable outstanding transactions e Out of order transaction completion e Unaligned data transfers using byte e strobes e Constrained random transaction r generation limited to Vera control e Protected accesses e e Atomic access e Response through command and notification AXI Slave axi_slave_vmt e Configurable multiple transaction e Out of order completion R e Read interleaving a e Unaligned data transfers using byte i strobes e Constrained random transaction n generation K e Variable Slave response e Supports FIFO memory
78. reset excluding memory Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cl2 Full carry look ahead model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide January 17 2005 Synopsys Inc 241 DesignWare IP Family DW_stackctl Synchronous Single Clock Stack Controller DW_stackctl Synchronous Single Clock Stack Controller e Parameterized word width and depth wr_addr e Stack empty and full status flags push_req_n we_n pop_req_n rd_addr e Stack error flag indicating underflow and overflow e Fully registered synchronous address and flag output fuli ports empty Ik e All operations execute in a single clock cycle stay Smor e Parameterized reset mode synchronous or asynchronous e Interfaces with common hard macro or compiled ASIC dual port synchronous RAMs Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 synchronous if rst_mode 1 push_req_n 1 bit Input Stack pus
79. s Input Read2 address bus wr_addr ceil logs depth bit s Input Write address bus data_in data_width bit s Input Input data bus data_rd1_out data_width bit s Output Output data bus for read data_rd2_out data_width bit s Output Output data bus for read2 Table 2 Parameter Description Parameter Values Description data_width 1 to 256 Width of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width rst_mode Oor 1 Determines if the rst_n input is used 0 rst_n initializes the RAM 1 rst_n is not connected 234 Synopsys Inc January 17 2005 DesignWare IP Family 100111001 RAM DW_ram_2r_w_a_dff 01101001 Write Port Dual Read Port RAM Flip Flop Based Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare g m wo lt m gt D 2 N D 2 D 5 January 17 2005 Synopsys Inc 235 DesignWare IP Family 100111001 DW_ram_2r_w_a_lat RAM Write Port Dual Read Port RAM Latch Based 01101001 DW_ram_2r w_a lat Write Port Dual Read Port RAM Latch Based e Parameterized word depth rd1_addr rd2_addr e Parameterized data width wr_addr data_rd1_out e Asynchronous static memory data_in data_rd2_out e Parameterized reset implementation cs_n wr_n rst_n Table 1 Pin Description
80. shift and o De multiplexed external memory rotate interface Up to 18 maskable interrupt e Optional peripherals sources 17 maskable internal interrupts and 1 maskable o 16 bit timer external interrupt e Three Input Capture IC e Power saving STOP and channels WAIT modes e Four Output Compare OC channels o Standard 68HC11 instruction set e Simple integration of user defined One software selectable IC or peripherals through external Special a aanne Function Register SFR interface o 8 Bit pulse accumulator within SFR array space o COP watchdog timer system e Fully synchronous implementation o SPI synchronous serial port basic e Supports FPGA Compiler II or enhanced SPI or SPI o SCI UART basic or enhanced SCI or SCI o Up to 3 external reset interrupt sources o Up to 17 internal interrupt sources January 17 2005 Synopsys Inc 297 DesignWare IP Family Ma DW_6811 oly 6811 Microcontroller US timer_nocop timer_pai timer_ici ler i imer_i Le DW_6811_timer X timercied San optional TR timer_oc2 includes timer_oc3 pulse timer_oc4 iram_bus accumulator timer_oc5 and timer_oc1_en timer_oc2_en timer_oc3_en timer_oc4_en timer_oc5_en DW_6811_math COP watchdog DW_6811_cpu optional DW_6811_contro DW_6811_interrupt DW_6811_opdecoder DW_6811_biu sfr_bus DW_6811_alu spi_sck_in spi_sck_out spi_miso_in spi_miso_out spi_mosi_in spi_mosi_out spi_ss_n
81. to the DesignWare Building Block IP User Guide 188 Synopsys Inc January 17 2005 DesignWare IP Family vine DW_asymfifo_s2_sf Asymmetric Synchronous Dual Clock FIFO with Static Flags DW_asymfifo_s2_sf Asymmetric Synchronous Dual Clock FIFO with Static Flags e Parameterized asymmetric input and output bit data_in 9 idths must be integer multiple relationship puah mpy WI 8 P P push_req_n Push_ae a e Fully registered synchronous flag output ports push_ht flush_n push_af 7 e Separate status flags for each clock system push_full 2 gt clk_push ram_full D e FIFO empty half full and full flags part_wd e Parameterized almost full and almost empty flags panom y e FIFO push error overflow and pop error Gatgeoul underflow flags pop_req_n pop_empty pop_ae e D flip flop based memory array for high testability pop_hf gt clk_po e Single clock cycle push and pop operations al bee e Word integrity flag for pop_error data_in_width lt data_out_width rst_n e Partial word flush for data_in_width lt data_out_width e Parameterized byte order within a word e Parameterized reset mode synchronous or asynchronous memory array initialized or not Table 1 Pin Description Pin Name Width Direction Function clk_push 1 bit Input Input clock for push interface clk_pop 1 bit Input Input clock for pop interface rst_n 1 bit Input Reset input active low push_req_n 1 bi
82. 05 nt DW01 decode Decoder e Parameterized word length e Inferable using a function call Table 1 Pin Description DesignWare IP Family DW01_decode Decoder g m wn lt S gt D o N D gt D 5 Pin Name Width Direction Function A width Input Binary input data B qwidth Output Decoded output data Table 2 Parameter Description Parameter Values Description width 21 Word length of input A is width Word length of output B is 24 Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc 167 DesignWare IP Family DW01_mux_any Universal Multiplexer DW01_mux_any Universal Multiplexer e Parameterized word lengths e Saves coding time by eliminating the need to E MUX code muxes explicitly SEL e Increases design abstraction e Uses 8 to 1 muxes where possible Table 1 Pin Description Pin Name Width Direction Function A A_width Input Data input bus SEL SEL_width Input Select input MUX MUX_width Output Multiplexed data out Table 2 Parameter Description Parameter Values Description A_width gt 1 Word length of A SEL_width gt 1 Word length of SEL MUX_width 21 A SEL 1 x MUX_width 1 downto SEL MUX_width Table 3 Sy
83. 1 correct after N samples at a current phase such as N consecutive samples at 1 or N consecutive samples at 1 windows 1 to divisor 1 2 Number of sampling windows for the input serial data stream Default 1 Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple synthesis model DesignWare cla Carry look ahead architecture DesignWare synthesis model a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide January 17 2005 Synopsys Inc 175 DesignWare IP Family DW03_Ifsr_dcnto LFSR Counter with Dynamic Count to Flag DW03_Ifsr_dcnto LFSR Counter with Dynamic Count to Flag e Dynamically programmable count to value that indicates when the counter reaches a specified value data count count_to e High speed area efficient tercnt e Asynchronous reset e Terminal count reset S clk Table 1 Pin Description Pin Name Width Direction Function data width bit s Input Input data count_to width bit s Input Input count_to_bus load 1 bit Input Input load data to counter active low cen 1 bit Input Input count enable clk 1 bit Input Clock reset 1 bit Input Async
84. 1_df Asymmetric I O Synchronous Single Clock FIFO with Dynamic Flag Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock z rst_n 1 bit Input Reset input active low asynchronous if E rst_mode 0 synchronous if rst_mode 1 push_req_n 1 bit Input FIFO push request active low id flush_n 1 bit Input Flushes the partial word into memory fills in N 0 s for data_in_width lt data_out_width only z pop_req_n 1 bit Input FIFO pop request active low 5 diag_n 1 bit Input Diagnostic control active low for err_mode 0 NC for other err_mode values data_in data_in_width bit s Input FIFO data to push ae_level ceil logs depth bit s Input Almost empty level the number of words in the FIFO at or below which the almost_empty flag is active af_thresh ceil log depth bit s Input Almost full threshold the number of words stored in the FIFO at or above which the almost_full flag is active empty 1 bit Output FIFO empty output active high almost_empty 1 bit Output FIFO almost empty output active high asserted when FIFO level lt ae_level half_full 1 bit Output FIFO half full output active high almost_full 1 bit Output FIFO almost full output active high asserted when FIFO level af_thresh full 1 bit Output FIFO full output active high ram_full 1 bit Output RAM full output active high error 1 bit
85. 2 1 multiplexers mx4 Implement using 4 1 and 2 1 DesignWare multiplexers mx8 Implement using 8 1 4 1 and 2 1 DesignWare multiplexers a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 62 Synopsys Inc January 17 2005 DW01_cmp2 2 Function Comparator e Parameterized word length e Unsigned and signed two s complement data DesignWare IP Family 2 Function Comparator DW01_cmp2 operation Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data B width bit s Input Input data LEQ 1 bit Input Output condition control TC 1 bit Input Two s complement control 0 unsigned 1 signed LT_LE 1 bit Output Less than less than or equal output condition GE_GT 1 bit Output Greater than or equal greater than output condition Table 2 Parameter Description Parameter Values Description width 21 Word length of A and B January 17 2005 Synopsys Inc 63 g r wn lt gt D o N D S D 5 DesignWare IP Family DW01_cmp2 2 Function Comparator Table 3 Synthesis Implementations Implementation Name Function License Feature Requ
86. 2005 Synopsys Inc 336 DesignWare IP Family dwcore_gig_ethernet Synthesizable Gigabit Ethernet Core dwcore_gig_ethernet Synthesizable Gigabit Ethernet Core The Synopsys DesignWare Gigabit Ethernet Media Access Controller GMAC synthesizable Verilog RTL design provides all the necessary features to implement the Layer 2 protocol of the Ethernet standard Other features include the following 337 Collision detection and auto retransmission on collisions in Half Duplex mode CSMA CD protocol Preamble generation and removal Automatic 32 bit CRC generation and checking Supports multiple PHY interfaces TBI RGMII SGMII MII RMIT Configurable counters for remote monitoring RMON and Simple Network Management Protocol SNMP optional Complete status for transmission and reception frames Compliant with IEEE 802 3 802 3u and 802 3z specifications Supports 10 100 Mbps and 1 Gbps data transfers in Full Duplex and Half Duplex modes Supports rate selection 10 100 1000 Mbps rates post silicon Supports IEEE 802 3q Virtual LAN VLAN tagged frame detection TEEE 802 3z compliant GMII interface to an external GPHY Synopsys Inc IEEE 802 3z Physical Coding Sublayer PCS with Ten Bit Interface TBI that supports autonegotiation optional IEEE 802 3 compliant MII interface to an external Fast Ethernet PHY Supports CSMA CD protocol in Half Duplex mode Supports 1 Gbps frame bursting in Half Duplex m
87. 40 Microprocessor Core from Synthesizable RTL IBM page 379 Verification Model DW_V850E Star V850E Processor Core from NEC page 381 Synthesizable RTL Verification Model DW_C166S 16 bit Processor from Infineon page 383 Synthesizable RTL Verification Model DW_TriCorel TriCorel 32 Bit Processor Core from Infineon page 385 Synthesizable RTL Verification Model DW_MIPS4KE Processor Core Family from MIPS page 387 Synthesizable RTL Verification Model DW_CoolFlux CoolFlux 24 bit DSP Core from Philips page 389 Synthesizable RTL Verification Model a Verification models of these cores are included in the DesignWare Library and DesignWare Verification Library Synthesizable RTL of these cores are available through the Star IP Program Also visit the DesignWare Star IP web page at http www synopsys com products designware star_ip html 30 Synopsys Inc January 17 2005 DesignWare IP Family Chapter 2 DesignWare Library Synthesizable IP g 2 DesignWare Library Synthesizable IP This chapter briefly describes the DesignWare Library synthesizable IP in the following subsections e Building Block IP Datapath Data Integrity Test and more e AMBA Bus Fabric and Peripherals IP page 264 e Memory IP Memory BIST Memory Controller page 291 e Microcontrollers 6811 and 8051 page 296 Building Block IP The DesignWare Building Block IP f
88. 5 Verification Model DW_MIPS4KE MIPS32 4KE 32 Bit Processor Core Family Synthesizable RTL from MIPS Technologies page 387 Verification Model DW_CoolFlux CoolFlux 24 bit DSP Core from Philips Synthesizable RTL page 389 Verification Model a Verification models of these cores are included in the DesignWare Library Synthesizable RTL of these cores are available through the Star IP Program January 17 2005 Synopsys Inc 378 DesignWare IP Family No DW_IBM440 Ip IBM PowerPC 440 CPU Core DW_IBM440 IBM PowerPC 440 CPU Core The IBM PPC440x5 CPU core is a high performance low power engine that implements the flexible and powerful Book E Enhanced PowerPC Architecture Other features include the following 379 High performance dual issue superscalar 32 bit RISC CPU o Superscalar implementation of the full 32 bit Book E Enhanced PowerPC Architecture Seven stage highly pipelined micro architecture Dual instruction fetch decode and out of order issue Out of order dispatch execution and completion High accuracy dynamic branch prediction utilizing a Branch History Table BHT Three independent pipelines e Combined complex integer system and branch pipeline e Simple integer pipeline e Load store pipeline Single cycle multiply Single cycle multiply accumulate new DSP instruction set extensions Full support for both big and little endian byte order Extensive power management designed into core fo
89. AM active low empty 1 bit Output FIFO empty output active high almost_empty 1 bit Output FIFO almost empty output asserted when FIFO level lt ae_level active high half_full 1 bit Output FIFO half full output active high almost_full 1 bit Output FIFO almost full output asserted when FIFO level depth af_level active high full 1 bit Output FIFO full output active high error 1 bit Output FIFO error output active high 212 Synopsys Inc January 17 2005 DesignWare IP Family vine DW_fifoctl_s1_sf Synchronous SingleClock FIFO Controller with Static Flags Table 1 Pin Description Continued Pin Name Width Direction Function wr_addr ceil logs depth bit s Output Address output to write port of RAM rd_addr ceil log depth bit s Output Address output to read port of RAM z Hans 2 Table 2 Parameter Description lt gt Parameter Values Function a depth 2 to 224 Number of memory elements used in FIFO used to size X Default 4 the address ports J 5 ae_level 1 to depth 1 Almost empty level the number of words in the FIFO at Default 1 or below which the almost_empty flag is active af_level 1 todepth 1_ Almost full level the number of empty memory locations Default 1 in the FIFO at which the almost_full flag is active err_mode 0 to2 Error mode Default 0 0 underflow overflow and pointer latched checking
90. ASIC with a Link Layer controller CPHY is well suited for multimedia and mass storage applications requiring high bandwidth and is suitable for a wide range of applications from basic low cost devices 1 port to sophisticated high performance ASICs up to 16 ports Other features include the following e Complete IEEE 1394a support e Supports 100 200 400 Mbps bus speeds e Configurable number of ports 1 to 16 e Simple silicon proven interface to mixed signal analog circuitry e Supports suspend resume protocol January 17 2005 e Supports Link On LPS protocol Synopsys Inc RapidScript configuration utility for design customization Synthesis scripts Verilog source code Approximately 14K gates 3 port Proven in ASIC applications 374 010 MA DesignWare IP Family Co dwcore_1394_cphy x Qs Synthesizable IEEE 1394 Cable PHY CPHYSHELL 4 Low Speed Digital Block T CPHY o O Port g Controller S g PHY Link By Pal 2 Interface 4 gt Port D Controller b Controller at Link Port Mux 4 lt interface 2 _ Registers Port gt lee Controller 4 The dwcore_1394_cphy data sheet is available at 375 http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_1394_cphy pdf Synopsys Inc January 17 2005 Co Es dwcore_jpeg_codec Syn
91. Basic IP Library is included in your V HDL Compiler product Most IP in this category have multiple architectures for each function architecturally optimized for either performance or area This provides you with the best architecture for your design goals All IP have a parameterized word length g r wn lt S gt D o N D gt D 5 January 17 2005 Synopsys Inc 51 DesignWare IP Family DW01_absval Absolute Value DW01_absval Absolute Value e Parameterized word length A ABSVAL Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data ABSVAL width bit s Output Absolute value of A Table 2 Parameter Description Parameter Values Function width 21 Word length of A and ABSVAL Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none clf Fast carry look ahead synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 52 Synopsys Inc January 17 2005 DesignWare IP Family DW01_add Adder DW01_add Adder e Pa
92. Cells and I Os are available to DesignWare Library licensees at no additional cost z TI e c gt Q lt oy o D 77 TSMC Libraries are developed by TSMC and process tuned to TSMC s semiconductor technologies Each logic and I O cell is validated in silicon and meets the company s rigorous library quality criteria TSMC libraries are in production in multiple customer designs Table 1 on page 327 shows the TSMC Standard I O categories Table 2 on page 328 shows the TSMC Standard Cell categories For more information about the TSMC Libraries visit http www synopsys com products designware tsmc html January 17 2005 Synopsys Inc 326 Chapter 4 DesignWare Foundry Libraries DesignWare IP Family Table 1 TSMC Standard I O Categories Technology Process Core Voltage I O Voltage Configuration Library Name 90nm General Purpose 1 0V 2 5V Staggered TPDN90G2 1 8V Staggered TPDN90G18 3 3V Staggered TPDN90G3 130nm General Purpose 1 2V HVT 2 5V 3 3V tol Staggered TPZO013G2 3 3V 5V tol Staggered TPZ013G3 1 2V 2 5V Linear TPDO13N2 3 3V Linear TPDO13N3 Low Voltage 1 0V HVT 2 5V 3 3V tol Staggered TPZO013LG2 1 0V HVT 3 3V 5V tol Staggered TPZO013LG3 1 0V OD 2 5V 3 3V tol Staggered TPZ013LODG2 1 0V OD 3 3V 5V tol Staggered TPZO013LODG3 Low Power 1 5V 2 5V Linear TPDO13LPN2 3 3V Linear TPDO13LPN3 150nm General Purp
93. Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b The performance of the csm implementation is heavily dependent on the use of a high performance inverting 2 to 1 multiplexer in the technology library In such libraries the csm implementation exhibits a superior area delay product Although the csm implementation does not always surpass the delay performance of the clf implementation it is much lower in area c This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc_shell t variable dw_prefer_mc_inside must be set to true From the DC 2004 12 release onward the MC architectures are not available by default For more information refer to the DesignWare Building Block IP Users Guide d This delay optimized parallel prefix architecture is generated using Datapath generator 54 technology DW gensh This is ON by default in the Design Compiler flow The DC variable synlib_enable_dpgen must be set to true the default to make use of this Datapath technology Synopsys Inc January 17 2005 DesignWare IP Family DW01_addsub Adder Subtractor DW01_addsub Adder Subtractor e Parameterized word le
94. Function a a_width bit s Input Multiplier b_width bit s Input Multiplicand tc 1 bit Input Two s complement 0 unsigned 1 signed out0 out_width bit s Output Partial product of a x b outl out_width bit s Output Partial product of a x b Table 2 Parameter Description Parameter Values Description a_width 21 Word length of a b_width gt 1 Word length of b out_width 2 a_width b_width 2 Word length of outO and out1 Table 3 Synthesis Implementations Implementation Name Function License Feature Required wall Booth recoded Wallace tree synthesis DesignWare model gt nbw Either a non Booth A_width B_width 41 DesignWare or a Booth Wallace tree A_width B_width gt 41 synthesis model a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 88 Synopsys Inc January 17 2005 DesignWare IP Family DW02_multp Partial Product Multiplier b In most cases the wall implementation generates both faster and smaller circuits for medium to large sized multipliers c In cases where A_width B_width lt 41 the nbw implementation generates a non Booth recoded Wallace tree multiplier For multipliers having products large
95. However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b This delay optimized parallel prefix architecture is generated using Datapath generator technology DW gensh This is ON by default in the Design Compiler flow The DC variable synlib_enable_dpgen must be set to true the default to make use of this Datapath technology c This delay optimized parallel prefix architecture is generated using Datapath generator technology DW gensh This is ON by default in the Design Compiler flow The DC variable synlib_enable_dpgen must be set to true the default to make use of this Datapath technology 72 Synopsys Inc January 17 2005 DW_div Combinational Divider e Parameterized word lengths e Unsigned and signed two s complement data operation e Remainder or modulus as second output DesignWare IP Family DW_div Combinational Divider quotient ja remainder jam divide_by_0 g m wo lt m gt D 2 N D D 5 Table 1 Pin Description Pin Name Width Direction Function a a_width bit s Input Dividend b b_width bit s Input Divisor quotient a_width bit s Output Quotient remainder b_width bit s Output Remainder modulus divide_by_0 1 bit Output Indicates if b equals 0 Table 2 Para
96. I Express specification including the latest errata Architecture supports x1 x2 x4 x8 and x16 2 5Gbps lane configurations Available in 32 64 or 128 bit datapath widths Modular design base core with additional support modules Implementation supports 125MHz and 250MHz Type 0 configuration space PIPE 8 bit 16 bit support Ultra low transmit and receive latency Configurable retry buffer size Configurable outstanding request supports up to 32 lookup entries without RAM beyond 32 entries with RAM Very high accessible bandwidth Lane reversal and polarity inversion TX RX Configurable multi VCs multi traffic class support e Configurable multi function support 345 Packet sizes configurable max payload size 128B to 4KB and max request size up to 4KB Synopsys Inc Supports bypass cut through and store and forward request queues with PCIe credit management as well as configurable for infinite credits for all type of traffic Configurable ECRC generation and check Complete Link Training LTSSM Beacon and wake up mechanism Full PCI PM software and ASPM Full Advanced PCI Express Error Reporting All in band messages supported for EP Legacy MSI and MSI X interrupt support Configurable EP filtering rules for posted non posted and completion traffic Configurable BAR filtering IO filtering configuration filtering and completion lookup timeout for EP e Support for two application cl
97. IPS4KE MIPS32 4KE Processor Core Family from MIPS Technologies DW_MIPS4KE MIPS32 4KE Processor Core Family from MIPS Technologies San The highly configurable MIPS32 4KE family represents the next generation of 32 bit MIPS cores Features include the following e 32 bit address and data paths e Five stage pipelined CPU Compatible with standard MIPS32 instruction set with optional support for MIPS16 instructions User defined instructions optional e Configurable instruction and data cache sizes MIPS R4000 style Privileged Resource Architecture Synchronous system EC bus interface Memory management unit o Translation lookaside buffer TLB in 4KEc configuration o Fixed address mapping in 4KEm and 4KEp configurations Synopsys Inc e Scratchpad RAM support optional e Coprocessor 2 interface optional Multiply divide unit o High performance implementation in 4KEc and 4KEm configurations o Area efficient implementation in 4KEp configuration Power management Enhanced JTAG EJTAG debug support Support for a variety of third party development and debugging tools the current list of support tools is available at http www mips com EC to AHB bridge for integration into AMBA based systems January 17 2005 COP2 I F COP2 I F Logic DesignWare IP Family DW_MIPS4KE MIPS32 4KE Processor Core Family from MIPS Technologies Data Cache System I F Execution Cac
98. O g m wn lt S gt D o N D gt D 5 Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset active low not used if parameter rst_mode 0 en 1 bit Input Load enable used only if parameter stall_mode 1 0 stall 1 load a a_width bit s Input Dividend b a_width bit s Input Divisor quotient a_width bit s Output Quotient a b remainder b_width bit s Output Remainder Table 2 Parameter Description Parameter Values Description a_width 22 Word length of a Default None b_width gt 2 lt a width Word length of b Default None tc_mode Oor 1 Two s complement control Default 0 0 unsigned 1 signed January 17 2005 Synopsys Inc 75 DesignWare IP Family DW_div_pipe Stallable Pipelined Divider Table 2 Parameter Description Continued Parameter Values Description rem_mode Oor1 Default 1 Remainder output control 0 modulus 1 remainder num_stages 2 Number of pipeline stages Default 2 stall mode Oor 1 Stall mode Default 1 0 non stallable 1 stallable rst_mode 0 to 2 Default 1 Reset mode 0 no reset 1 asynchronous reset 2 synchronous reset Table 3 Synthesis Implementations Implementation Name Implementation License Feature Required str Pipelined str synthesis model Desi
99. Parameter Values Description width 1 to 256 Defines the width of the input bus par_type Oor 1 Defines the type of parity a The upper bound of the legal range is a guideline to ensure reasonable compile times Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare 148 Synopsys Inc January 17 2005 0000000 DesignWare IP Family odin 1010110001 Data Integrity Coding Group Overview Data Integrity Coding Group Overview The Coding Group consists of a set of IP that encode and or decode data for use in data communications and data storage applications Currently the 8B 10B coding scheme used in standard data communication and networking protocols such as Gigabit Ethernet and Fiber Channel is embodied in the Coding Group IP g m wn lt S gt D o N D gt D 5 January 17 2005 Synopsys Inc 149 DesignWare IP Family 00000000 oding DW_8b10b_dec 8b10b Decoder 1010110001 DW 8b10b dec 8b10b Decoder e Configurable data width data_in data_out e Configurable simplified Special Character indicator ee k_char flags for protocols requiring only the K28 5 special j ae rd character init_rd_n See enable rd_err code_err e Synchronous initialization of Running Disparity with design specified value e All outputs registered Table 1 Pin Description Pin Name
100. Port RAM Flip Flop Based 224 DW_ram_r_w_s _lat Synchronous Write Port Asynchronous Read Port RAM Latch Based 225 DW_ram_2r_w_s_dff Synchronous Write Port Asynchronous Dual Read Port RAM Flip Flop Based 226 DW_ram_2r_w_s_lat Synchronous Write Port Asynchronous Dual Read Port RAM Latch Based 228 DW_ram_rw_s_dff Synchronous Single Port Read Write RAM Flip Flop Based 229 DW_ram_rw_s_lat Synchronous Single Port Read Write RAM Latch Based 230 Memoty Asynchrongus RAMS c2 44c4edesied eee 46555585 ees tpi sees 231 DW_ram_r_w_a _dff Asynchronous Dual Port RAM Flip Flop Based 04 232 DW_ram_r_w_a_lat Asynchronous Dual Port RAM Latch Based 0 0 0008 233 DW_ram_2r_w_a_dff Write Port Dual Read Port RAM Flip Flop Based 4 234 8 Synopsys Inc January 17 2005 DesignWare IP Family Contents DW_ram_2r_w_a_lat Write Port Dual Read Port RAM Latch Based 000000000 236 DW_ram_rw_a_dff Asynchronous Single Port RAM Flip Flop Based 04 237 DW_ram_rw_a_lat Asynchronous Single Port RAM Latch Based 0 0 238 Memory Stacks crasivan dense banteans ed s 66 cibau seas nk tunes baeius 239 DW_stack Synchronous Smele Clock Stack c cs esisaveseiewocs sadiewdanwasawe 240 DW_stackctl Synchronous Single Clock Stack Controller 0000 242
101. RP and HNP USB On The Go Verification IP USB Host USB Hub USB Host OF USB Device USB OTG Device USB Device USB Monitor The DesignWare USB On The Go Verification IP User Manual is available at http www synopsys com products designware docs 319 Synopsys Inc January 17 2005 DesignWare IP Family DesignWare VMT Models VMT Verification Modeling Technology models are bus functional models and monitors that can be instantiated in Vera or HDL testbenches All VMT models have a common command interface style that allows you to easily integrate standard bus protocol devices into your system testbenches All VMT models support these features e Multiple command streams Switch command control conditionally or unconditionally Execute Master Host and Slave Device command streams Stop command execution until new command streams are loaded e Verilog VHDL or Vera testbenches or Native Testbench VMT models run on these simulators Synopsys VCS and VCS MX MTI Verilog Cadence NC Verilog MTI VHDL and Cadence NC VHDL e Configurable message formatting Enable or disable o Message types Errors Warnings Timing X handling Notes Protocol o Message logs Simulator transcript window and or log files o Message features Building blocks of message content g m S O g e gt 5 e Event driven testbenches Waits for an event from the model and blocks comma
102. S Secure Digital SD and Multimedia Card MMC Host Controller clk _ y BIU CIU Regulators Interrupts SDIO 3 Power status Interrupt Switches Control Power Interrupt Pullup Control Card detect ket amp Debounce MUX write goce APB AHB ES Control De MUX z protect Interface fa Unit alg lt 5 Interface _ gt gt TEE card Unit 2 2 tect protec F gt Command o Registers n Path e DMA eee Control als Cards Interface z B optional DIWA FIFO Data O celk 4 gt Interface c ontrol Path ccmd Control ae Control cdata RAM 1 a Interface RA j celk_in_drv optional FIFO Clock cclk_in_sample RAM Control cclk_in optional Note The card_detect and write protect signals are from the SD MMC card socket and not from the SD MMC card The DesignWare DW_sd_mmc datasheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file gt DWC_sd_mmce pdf January 17 2005 Synopsys Inc 354 010 MA DesignWare IP Family dwcore_usb1_device Synthesizable USB 1 1 Device Controller dwcore_usb1 device Synthesizable USB 1 1 Device Controller C KN The Synopsys DesignWare USB Device Controller UDC is a set of synthesizable building blocks for implementing a com
103. SDRAMs memory data width 8 16 32 or 64 with 1 2 or 1 4 ratios with the AHB data width Programmable row and column address bit widths Supports 2K to 64K rows 256 to 32K columns and 2 to 16 banks Supports up to 8 chip selects with a maximum of 4 GB of address space per chip select Supports asynchronous SRAMs page mode FLASHes and ROMs Supports up to three sets of timing registers Supports external READY handshake pin to interface non SRAM type device Note Does not generate split retry or error responses on the AHB bus Also see the block diagram on the following page 292 Synopsys Inc January 17 2005 DesignWare IP Family DW_memctl Memory Controller DW_memctl MacroCell g Address Decoder PP lt gt O o SDRAM Controller SDRAM N State Machine Interface g D Host 2 Interface Z Unit HIU Static memory Controller Static State Machine Memory Interface Control Registers Refresh Unit The DesignWare DW_memctl MacroCell Databook is available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 293 DesignWare IP Family DW_rambist Memory Built In Self Test DW_rambist Memory Built In Self Test Interfaces 8 e IEEE 1149 1 TAP controller interface e Two clock interface one for a slower TAP I F second for at speed BIST execution e Optional MUX block that supports either embedded multip
104. SYNDB 36 generated during DC compilation The new implementation is capable of producing any of the original architectures automatically based on user constraints January 17 2005 Synopsys Inc 211 DesignWare IP Family DW_fifoctl_s1_sf eine Synchronous SingleClock FIFO Controller with Static Flags DW_fifoctl_s1_sf Synchronous SingleClock FIFO Controller with Static Flags e Fully registered synchronous address and flag output push_regq_n mesa ports we_n pop_req_n rd_addr e All operations execute in a single clock cycle diag_n full e FIFO empty half full and full flags almost_full half_full almost_empty empty rst_n error e FIFO error flag indicating underflow overflow and pointer corruption e Parameterized word depth e Parameterized almost full and almost empty flags e Parameterized reset mode synchronous or asynchronous e Interfaces to common hard macro or compiled ASIC dual port synchronous RAMs Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 synchronous if rst_mode 1 push_req_n 1 bit Input FIFO push request active low pop_req_n 1 bit Input FIFO pop request active low diag_n 1 bit Input Diagnostic control for err_mode 0 NC for other err_mode values active low we_n 1 bit Output Write enable output for write port of R
105. SYNOPSYS DesignWare IP Family Reference Guide DesignWare IP Family Copyright Notice and Proprietary Information Copyright 2005 Synopsys Inc All rights reserved This software and documentation contain confidential and proprietary information that is the property of Synopsys Inc The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement No part of the software and documentation may be reproduced transmitted or translated in any form or by any means electronic mechanical manual optical or otherwise without prior written permission of Synopsys Inc or as expressly provided by the license agreement Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America Disclosure to nationals of other countries contrary to United States law is prohibited It is the reader s responsibility to determine the applicable regulations and to comply with them Disclaimer SYNOPSYS INC AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Registered Trademarks Synopsys AMPS Arcadia C Level Design C2HDL C2V C2VHDL Cadabra Calaveras Algorithm CATS COSSAP CSim DelayMill Design Compiler
106. Test ee er re ee ee ee re 244 DW_tap TAP Controller posses ceiebacceaeibsseeade beaters eaecnseebascess 245 DW_tap_uc TAP Controller with USERCODE support lt 44 e sibscdenseensiwacabus 247 DW_bc_1 may Scan Cell Type BC 1 cheetah ee cha pee case ners ees ews 250 DW_bc_2 Boundary scan Cell Type BC 2 ck ose ha cae ee oS hoes 8 RS 4a weer nee bees 251 DW_bc_3 Boundary Scan Cell Type BC 3 cedesea cence eoneedesee cheudee es e885 292 DW_bc_4 Boundary Scan Cell Type BC 4 ccbccceecitodeesiudedsesianwanbes ones 253 DW_bc_5 Boundary Scan Cell Type BOS cov acedacdeadet os cease eadeusseeeeseas 254 DW_bc_7 onary Scan Cell Type BU 7 gk cs ewe chen eeh bh ieee btereree iss 255 DW_bc_8 Pouudary Scan Coll Type BC S 2 obs c oa hh hi eek et bead iS Hib ens 257 DW_bc_9 Boundary Sean Cell Type BC ce ceded evi desss hes eee sees eee ees 239 DW_bc_10 Boundary Scan Cell Type BC 10 ce cineeicgoteesdneedaesiagoteeesades 261 GTECH Library CE 93 oe he ee he oe Os hens EE R a6 263 AMBA Bus Fabric and Peripherals IP sc cccscccevseedesess oe theeeeseceeeca es 264 DW_ahb Advanced High Performance Bus 244 o 4060asceas densa eae iened bee cea 266 DW_ahb_dmac AHB Central Direct Memory Access DMA Controller 268 DW_ahb_eh2h Banged AHB t AHB Bridge oc 6 aceon bie io 5 bee dens ineins shee 269 DW_ahb_icm AHB Multi layer Interconnection Matrix 0e eee e sees eeees 271 DW_ahb _ictl January 17 2005 Synopsys Inc 9 Contents Design
107. USB 1 1 Hub Controller The Synopsys DesignWare USB Hub UH01 is a set of synthesizable building blocks that ASIC FPGA designers use to implement a complete USB Hub The RapidScript utility enables designers to easily configure the device by setting the number of downstream ports The Synopsys UHO1 product consists of the Hub Repeater and the Hub Controller The Hub Repeater is responsible for connectivity setup and tear down and supports exception handling such as bus fault detection recovery and connect disconnect detection The Hub Controller provides the mechanism for host to hub communication Hub specific status and control commands permit the host to configure a hub and to monitor and control its individual downstream ports Other features include the following e Silicon proven e Downstream device connect e USB 1 1 compliant disconnect detection e Verilog source code e Supports suspend resume for power e Supports low speed and full speed en a devices on downstream ports e Supports one interrupt endpoint in e Integrated DPLL for clock and data paca fo endpoint 0 recovery e Approximately 12K gates for four ports 359 Synopsys Inc January 17 2005 DesignWare IP Family C Og dwcore_usb1_hub S Synthesizable USB 1 1 Hub Controller a ie Transceiver A UHO1 Hub Root Port Frame Timer
108. Used to switch the DW_ahb address decoder from boot mode to normal mode operation e Pause Mode Used to put the DW_ahb s arbiter into low power pause mode DesignWare IP Family DW_apb_rap APB Remap and Pause In pause mode the dummy master is granted the AHB bus until an interrupt occurs Reset Status Register Keeps track of status from up to eight separate system reset signals g m wn lt S gt D o N D D 5 Identification Code Register Implements a configurable read only ID register DW_apb_rap scan_mode sys_resets Registers remap_n por_reset_n irq_n fig_n Remap irq Pause fiq prdata pclk APB Interface pwrite __ penable gt pause Optional signals The DesignWare DW_apb_rap Databook is available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 277 DesignWare IP Family DW_apb_rtc APB Real Time Clock DW_apb_rtc APB Real Time Clock e APB slave interface with read write coherency for registers e Incrementing counter and comparator for interrupt generation e Free running pclk e User defined parameters O O O O O 0 APB data bus width Counter width Clock relationship between bus clock and counter clock Interrupt polarity level Interrupt clock domain location Counter enable mo
109. VHDL U1 DWO2 mult generic map A width gt inst_A width B width gt inst_B width port map A gt inst_A B gt inst_B TC gt inst_TC PRODUCT gt inst PRODUCT g m wn lt S gt D o N D D z Currently FPGA Compiler II does not support inference of DesignWare Building Block IP Synthesizing DesignWare Building Block IP in FPGA Compiler Il FPGA Compiler II versions 3 2 and later automatically select the implementation for the chosen FPGA technology It understands and takes advantage of vendor specific architectures to provide the best quality of results QoR for most DesignWare Building Block IP Note that some DesignWare Building Block IP are implemented using generic gates but improvement in QoR can be expected in future releases Simulating DesignWare Building Block IP FPGA Compiler II has the ability to generate synthesized netlists in Verilog and VHDL Just right click on the optimized chip select Export Netlist and then select Verilog or VHDL as the desired output format The netlists generated are structural netlists which can be simulated with VCS or VSS Technical Support or Further Information For further information on using DesignWare in FPGA Compiler II e Visit our Web site at http www synopsys com products fpga fpga_solution html e e mail the Synopsys Support Center at support_center synopsys com e Call 800 245 8005 toll free in the United States January 17 2005 Syn
110. W02_mac Dp ACCOMM cdsha sie es darii io 4464009405404 40s oe oS 83 4 Synopsys Inc January 17 2005 DesignWare IP Family Contents DW_minmax Minimum Maximum Value 4 is 6 eared dee pee se ERAS ESN Es ee 6G REEwae 85 DW02_mult se ar ee eee ee 86 DW02_multp Pitta Product MUlpiit ois ceeaceunsd ener edtegneeddee is ovusdeuetansa 88 DW02_mult_2_stage Two Stage Pipelined Multipliet 2244 4cees2ss0c5404s54esesgeoaseeess teas 90 DW02_mult_3_stage Three Stage Pipelined Multiplier g2is 402nbeadivedadetsestenasigeineose 92 DW02_mult_4_stage FourStage Pipelined Multiplier 2 oscce gs eees eesti besaeee eho sac ges gece 93 DW02_mult_5_stage Fiv Stage Pipelined Multiplier 4 icaccsacceaercacceadeeasbeancenscees 94 DW02_mult_6_stage Six Stage Pipehned Mulnipher ossecicssci creci iicirrtien i dait Enee senss 96 DW_mult_dx Daplis DONDU oe ea ne ee eG Bee 6 ee es 98 DW_mult_pipe Stallable Tee MUIUPHEF on os oe eh nee bce we sawe eres ENI eeeawes 99 DW02_prod_sum Generdlized Sum Of Products lt so 0640548 opexdeees noe rieta endeeoseeed 101 DW02_prod_sum1 MulipherAdder 2 455 cers aessseoroeeeetedsescatedindesuwdees sages 103 DW_prod_sum_pipe Stallable Pipelined Generalized Sum of Products 0000 105 DWO1_satrnd Arithmetic Saturation and Rounding Logic w sics ci eeeeeatiwvsinetieas 107 DW_shifter Combined Arithmetic and Barrel Shifter 5 42c2ce si bdcieedecndaeesabas 109 DW_square TC SN ia 4 a 4 a a ee 111 DW_
111. Ware IP Family AHB ei SE oc dain ote ba a ea a es aie DW_apb Advanced Peripheral BUS os 0G osee eases Hoo hese RESO Oe KH ee a 213 DW_apb_gpio APB General Purpose Programmable I O 0022 c eee ee eee 274 DW_apb_i2c BE Ie ire coe ore os E E PENTAS ET T ATE E Zlo DW_apb_ictl APB Umer er virrei di he a ea ea ees 276 DW_apb_rap AFB Remap and Pause os oe Knee bh iolee pasar eds eos ie gee Hues beee esses 211 DW_apb_rtc APE Real Time Clock ac oxcseencsoudet os eessaee oo 64S5eeneseee ene Ses 278 DW_apb_ssi APB Synchronous Serial Interface 26 h2nhsdeesisivdaad eens vad sas dears 219 DW_apb_timers APB Programmable Timers 240sc00scen eeu adsbed oeecs waddew seen cues 281 DW_apb_uart APB Universal Asynchronous Receiver Transmitter 000 282 DW_ahb_h2h Pr AHB Bridge go pede shia betwee pbt sari EEEL EDNER tes 284 DW_apb_wdt APB ele TiS scene needed aes ea heen eo ees 286 DesignWare AMBA Connect Design environment for AMBA synthesizable and verification IP 287 DesignWare AMBA QuickStart Collection of example designs for AMBA subsystems 288 PAO geeks 4 een 9h b Hee oS 45 5234 bk Kee oa heed Re eh OS oS Ms 291 DW_memctl Memory LOURGIE ccacsavdse oc eetetee seer eases cee shag seers one 54 292 DW_rambist Memory Built In Self TeSt ci cock cuatagedhecsees de eoshesbaset asiain 294 Micr processors Microcontrollers 4 codn 5 55455494242 586 55 4S4H 98S 4s eked eHes 296 DW_6811 GS Li COCR
112. _asymfifo_s2_sf Asymmetric Synchronous Dual Clock FIFO with Static Flags 189 DW_fifo_sl_df Synchronous Single Clock FIFO with Dynamic Flags 193 DW_fifo_sl_sf Synchronous Single Clock FIFO with Static Flags 0 195 January 17 2005 Synopsys Inc 7 Contents DesignWare IP Family DW_fifo_s2_sf Synchronous Dual Clock FIFO with Static Flags 0 197 DW_asymfifoctl_s1_df Asymmetric I O Synchronous Single Clock FIFO Controller with Dynamic Flags 200 DW_asymfifoctl_s1_sf Asymmetric I O Synchronous Single Clock FIFO Controller with Static Flags 203 DW_asymfifoctl_s2_sf Asymmetric Synchronous Dual Clock FIFO Controller with Static Flags 206 DW_fifoctl_sl_df DW_fifoctl_s1_sf Synchronous SingleClock FIFO Controller with Static Flags 212 DW_fifoctl_s2_ sf Synchronous Dual Clock FIFO Controller with Static Flags 214 ay Cnt ose he cide oot ne bea best A Gate EE teense 217 DW03_pipe_reg Pipe RG eaor a ode slut ee ao eee eee Lees 218 DW03_reg_s_pl Register with Synchronous Enable Reset 10 1014 sees ssosewescene bens 219 DW04_shad_reg Shadow and MW Resister oo5 on odes oe cedeeee seer seeesseneeeue ees 220 DW03_shftreg DIME PO 42365624 cucedeo cnet ses sears hess obersees ceeekenaedas 222 Memory Synchronous RAMS g1i05 2 45 dee bh tren tr Eu ER EREL R aS 223 DW_ram_r_w_s_dff Synchronous Write Port Asynchronous Read
113. _master_vmt DesignWare AMBA APB Models page 306 Verification apb_monitor_vmt apb_slave_vmt axi_master_vmt DesignWare VIP for AMBA 3 AXI page 307 Verification axi_slave_vmt axi_monitor_vmt axi_interconnect_vmt ethernet_txrx_vmt 10 100 1G 10G Ethernet Models page 310 Verification ethernet_monitor_vmt enethub_fx Ethernet RMI Transceiver and Hub page 311 Verification rmiirs_ fx i2c_txrx_vmt PC Bi Directional Two Wire Bus page 312 Verification pcie_txrx_vmt PCI Express 1 00a page 314 Verification pcie_monitor_vmt pcimaster_fx PCI 2 3 and PCI X 2 0 Simulation Models and Test Verification pcislave_fx Suite page 316 pcimonitor_fx sata_device_vmt Serial ATA Models PRELIMINARY page 317 Verification sata_monitor_vmt sio_txrx_vmt Serial Input Output Interface Models page 318 Verification sio_monitor_vmt usb_host_vmt USB On The Go Models 1 1 2 0 OTG UTMI and Verification usb_device_vmt UTMI Low Pin Interface ULPI page 319 usb_monitor_vmt January 17 2005 Synopsys Inc 25 Chapter 1 Overview DesignWare IP Family Board Verification IP The DesignWare Library contains over 18 500 simulation models for ASIC SoC and Board verification For a complete search visit http www synopsys com ipdirectory Component Group Component Reference VMT Models Refer to DesignWare VMT Models on page 320 FlexModels Refer to DesignWare FlexModels on page 322 DesignWare Memor
114. _reg_s_ pl Register with Synchronous Enable Reset DW03_reg_s pl Register with Synchronous Enable Reset d e Parameterizable data width z e Parameterized reset to any constant value enable a lt e Multiple synthesis implementations gt clk gt reset_N 2 2 D o ae v Table 1 Pin Description Pin Name Width Direction Function d width bit s Input Input data bus clk 1 bit Input Clock reset_N 1 bit Input Synchronous reset enable 1 bit Input Enables all operations q width bi s Output Output data bus Table 2 Parameter Description Parameter Values Description width 1 to 31 Width of d and q buses Default 8 reset_value 0 to 2 4th_1 when width 31 Resets to a constant 0 when width 32 Default 0 Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Single bit flip flops synthesis model DesignWare mbstr Multiple bit flip flops synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide January 17 2005 Synopsys Inc 219 DesignWare IP Family DW04_shad_reg Shadow and Multibit Register DW04_shad_reg Shadow and Multibit Registe
115. ad eee GED eS eee Renae ede een 317 Serial Input Output Interface Models Traneceiver and MOMOL 6 0 444 lt 444004 084 ti IRENI ESNEA RENTE RE T RETS 318 USB On The Go Models Host Device and Monitor 22 4 cee e605 044 hh se eee discri dds eh di 319 Das ir a VMT Mode ok ek Shawne kbs bye hs oon be CO eee State e noes 320 Design wate PICsMOGG lt 2165cc5cseGhchotaserrgetessscbeteeeiheee ies sane 322 Leoz ol FENO raea a e 8S a eG 8S es 322 Design Ware Smart Odes ks oh id aie eel be oo 6 OE G60 S OES es hE SOA ds ORES 324 Sinan vViodel Features 4 45 6 4 45 5 4 44 r inn RITEN IESU ERTS ERA ETAR ARa 324 SmanModel Types vacdkdeibndebgeetsadesautanedcsudereeeawdawsebae cen 324 SmartModel Timing Definitions sssesssrssesessssessereresersrene 325 Specie Model Irn gecdi donc e be teeisthiddeeseuntedhs O ER 325 Chapter 4 DesignWare Foundry Libraries ccc ccccccccccccccnccccnccees 326 TON LDA ci btn dda eh da take eed ante wee ehe kee dteeda OEE eta 326 Toe TAMNNIES 2c bas E Keke banks eben enki eee keds pews E E 329 Chapter 5 Desin yare COTES aememean erie ar ane gra area ane eg marae hearer era er cpom ara R 330 dwcore_ethernet Synthesizable Ethernet Core 5 cece ice gadwaeG nde ace eaeeusseusseas 333 dwcore_ethernet_sub Synthesizable Ethernet Subsystem 25s bac ce wsdbaand enka dan dewed baeeued 335 dwcore_gig_ethernet Synthesizable Gigabit Ethernet Core s ccrccricinsoceirierssceniisdatani 337 January 17 2005 Synopsys Inc 11
116. ag i is active pop_ae_lvl 1 todepthd Almost empty level for the pop_ae output port the number of Default 2 words in the FIFO at or below which the pop_ae flag is active pop_af_Ivl 1 to depth Almost full level for the pop_af output port the number of Default 2 mpty memory locations in the FIFO at which the pop_af flag f is active 198 Synopsys Inc January 17 2005 Tit DesignWare IP Family DW_fifo_s2_sf Synchronous Dual Clock FIFO with Static Flags Table 2 Parameter Description Continued g m wo lt m gt 0 o N D D 5 Parameter Values Description err_mode Oor 1 Error mode Default 0 0 stays active until reset latched 1 active only as long as error condition exists unlatched push_syne 1 to3 Push flag synchronization mode Default 2 1 single register synchronization from pop pointer 2 double register 3 triple register pop_sync 1 to3 Pop flag synchronization mode Default 2 1 single register synchronization from push pointer 2 double register 3 triple register rst_mode 0 to 3 Reset mode Default 0 0 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding memory 3 synchronous reset excluding memory Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cl2 Full
117. ample designs for AMBA subsystems built with DesignWare AMBA On chip Bus components The QuickStart example designs are static non reconfigurable examples of complete subsystems that use DesignWare AMBA IIP and VIP components Star IP Microprocessor and DSP Cores Component Name Component Description Component Type DW_IBM440 PowerPC 440 32 Bit Microprocessor Core Synthesizable RTL from IBM page 379 Verification Model DW_V850E Star V850E 32 Bit Microcontroller Core from NEC Synthesizable RTL Electronics page 381 Verification Model DW_C166S 16 Bit Microcontroller Subsystem from Synthesizable RTL Infineon page 383 Verification Model DW_TriCorel TriCore1 32 Bit Processor Core from Infineon Synthesizable RTL page 385 Verification Model DW_MIPS4KE MIPS32 4KE 32 Bit Processor Core Family Synthesizable RTL from MIPS Technologies page 387 Verification Model DW_CoolFlux CoolFlux 24 bit DSP Core from Philips Synthesizable RTL page 389 Verification Model a Verification models of these cores are included in the DesignWare Library and the DesignWare Verification Library Synthesizable RTL of these cores are available through the Star IP Program For more information visit http www synopsys com designware star_ip html January 17 2005 Synopsys Inc 23 Chapter 1 Overview DesignWare IP Family Microcontrollers Component Name Componen
118. an cell Table 2 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare or Test IEEE STD 1149 1 250 Synopsys Inc January 17 2005 DW_bc_2 Boundary Scan Cell Type BC_2 e IEEE Standard 1149 1 compliant e Synchronous or asynchronous scan cells with respect to tck si e Supports the standard instructions EXTEST SAMPLE PRELOAD and BYPASS e Supports the optional instructions INTEST RUNBIST CLAMP and HIGHZ DesignWare IP Family DW_bc_2 Boundary Scan Cell Type BC_2 data_in data_out so mode shift_dr capture_en update_en g m 7 lt m gt D 2 N D D 5 gt update_clk gt capture_clk Table 1 Pin Description Pin Name Width Direction Function capture_clk 1 bit Input Clocks data into the capture stage update_clk 1 bit Input Clocks data into the update stage capture_en 1 bit Input Enable for data clocked into the capture stage active low update_en 1 bit Input Enable for data clocked into the update stage active high shift_dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo mode 1 bit Input Determines whether data_out is controlled by the boundary scan cell or by the data_in signal si l bit Input Serial path from the previous boundary scan cell data_in l bit I
119. and packages gtech src_ver Verilog For more information about the GTECH IP refer to the DesignWare GTECH Libraries Databook g m wn lt S gt D o N D D z January 17 2005 Synopsys Inc 263 DesignWare IP Family AMBA Bus Fabric and Peripherals IP AMBA is a standard bus architecture system developed by ARM for rapid development of processor driven systems AMBA also allows a number of bus peripherals and resources to be connected in a consistent way The following Synopsys DesignWare AMBA 2 0 compliant components are briefly described in this section Table 1 Alphabetical List of the DesignWare AMBA Synthesizable IP Name and Page Description DW_ahb page 266 Advanced High performance Bus AHB DW_ahb_dmac page 268 AHB Central Direct Memory Access DMA Controller DW_ahb_eh2h page 269 Enhanced AHB to AHB Bridge DW_ahb_h2h page 284 AHB to AHB Bridge DW_ahb_icm page 271 AMBA AHB Multi layer Interconnection Matrix DW_ahb_ictl page 272 AHB Interrupt Controller DW_apb page 273 Advanced Peripheral Bus APB DW_apb_gpio page 274 General Purpose Programmable I O DW_apb_ictl page 276 APB Interrupt Controller DW_apb_i2c page 275 APB I C Interface DW_apb_rap page 277 Remap and Pause DW_apb_rtc page 278 APB Real Time Clock DW_apb_ssi page 279 APB Synchronous Serial Interface DW_apb_timers page 281 Programmable Timers DW_apb_uart page 282 Uni
120. ange from 3 to 31 bits e Significand or fractional part of the floating point number can range from 2 to 256 bits e Accuracy conforms to IEEE 754 Floating Point standard Table 1 Pin Description Pin Name Width Direction Function A e f 1 bits Input Multiplier B e f 1 bits Input Multiplicand Z e f 1 bits Output Product of A x B STATUS optional 8 bits Output Status flags RND optional 3 bits Input Rounding mode Table 2 Parameter Description Parameter Values Description e 3 to 31 bits Word length of biased exponent of floating point numbers A B and Z f 2 to 253 bits Word length of fraction field of floating point numbers A B and Z arch 0 Architecture implementation a This component contains only one architecture therfore the arch parameter should be set to 0 Table 3 Synthesis Implementations Implementation Name Function License Feature Required arch0 Synthesis model DesignWare 128 Synopsys Inc January 17 2005 DesignWare IP Family DW_flt2i_fp 2 4979 x 105 Floating Point to Integer Converter DW fit2i_fp Floating Point to Integer Converter Module Compiler Only e The precision format is parameterizable for either IEEE single double precision or a user defined custom format e Exponents can range from 3 to 31 bits a FETAI e Significand or fractional part of the floating point number can STATUS
121. arameter Values Description width 21 Input word length Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cla Carry lookahead synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 82 Synopsys Inc January 17 2005 DesignWare IP Family DW02_mac Multiplier Accumulator DW02 mac Multiplier Accumulator e Parameterized word length g e Unsigned and signed two s complement data operation B MAC a c gt TC B N D o o Table 1 Pin Description a Pin Name Width Direction Function A A_width bit s Input Multiplier B B_width bit s Input Multiplicand C A_width B_width bit s Input Addend TC l bit Input Two s complement control 0 unsigned 1 signed MAC A_width B_width bit s Output MAC result A x B C Table 2 Parameter Description Parameter Values Description A_width gt 1 Word length of A B_ width gt 1 Word length of B Table 3 Synthesis Implementations Implementation Name Function License Feature Required acsmult Area opt
122. are docs ds i DW_rambist_ds pdf January 17 2005 Synopsys Inc 295 DesignWare IP Family Microprocessors Microcontrollers The components detailed in this section contain a page reference in the following table Component Name Component Description DW_IBM440 PowerPC 440 Microprocessor Core from IBM page 379 DW_V850E Star V850E Processor Core from NEC page 381 DW_C166S 16 bit Processor from Infineon page 383 DW_TriCorel TriCore1 32 Bit Processor Core from Infineon page 385 DW_MIPS4KE Processor Core Family from MIPS page 387 DW_6811 8 bit Microcontroller page 297 DW8051 8 bit Microcontroller page 299 a Synthesizable RTL of the processor cores are available through the Star IP Program For more information on this program visit http www synopsys com designware 296 Synopsys Inc January 17 2005 DesignWare IP Family Mac Os DW_6811 Us 6811 Microcontroller DW_6811 6811 Microcontroller e Compatibility with industry standard e A BIU unit to provide control signals 68HC11 microcontroller for memory and I O ports o 8 bit CPU with 8 bit 16 bit ALU o Programmable memory map for e Two 8 bit accumulators that internal RAM iRAM and SFR g m wn lt S gt D o N D D z can be concatenated to provide altay spaces 16 bit addition 16 bit o Parameterized internal ROM subtraction 16 x 16 division 8 GROM size x 8 multiplication
123. as DW03_bictr_dcnto Seta Up Down Binary Counter with Dynamic Count to Flag DW03_bictr_dcnto Up Down Binary Counter with Dynamic Count to Flag e Parameterized word length d ata f count e Terminal count flag for count to comparison count_to e Pin programmable count to value up_dn terent e Up down count control cen e Asynchronous reset load clk reset g 7 lt m gt D 2 N D D 5 e Synchronous counter load e Synchronous count enable Table 1 Pin Description Pin Name Width Direction Function data width Input Counter load input count_to width Input Count compare input up_dn 1 Input High for count up and low for count down load 1 Input Enable data load to counter active low cen 1 Input Count enable active high clk 1 Input Clock reset 1 Input Counter reset active low count width Output Output count bus tercnt 1 Output Terminal count flag active high Table 2 Parameter Description Parameter Values Description width 21 Width of data input bus Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc 171 DesignWare IP Family DW03_bictr_scnto 4 fox Up Down Binary Counter with Static Count to Flag DW03_bictr_scnto Up Down Binary Counter with Static Count to Flag e
124. ation IP suites out of the DesignWare Verification Library Component Name Component Description Model Technology DesignWare Bus amp I O Standards ahb_bus_vmt ahb_master_vmt ahb_monitor_vmt ahb_slave_vmt DesignWare AMBA AHB Models page 304 VMT page 320 apb_master_vmt apb_monitor_vmt apb_slave_vmt DesignWare AMBA APB Models page 306 VMT page 320 axi_master_vmt axi_slave_vmt axi_monitor_vmt axi_interconnect_vmt DesignWare VIP for AMBA 3 AXI page 307 VMT page 320 ethernet_txrx_vmt ethernet_monitor_vmt 10 100 1G 10G Ethernet Models page 310 VMT page 320 enethub_fx rmiirs_ fx Ethernet RMI Transceiver and Hub page 311 FlexModels page 322 i2c_txrx_vmt PC Bi Directional Two Wire Bus page 312 VMT page 320 January 17 2005 Synopsys Inc 301 g m S O o e gt Ea Chapter 3 DesignWare Library Verification IP DesignWare IP Family different devices pcie_txrx_vmt PCI Express 1 00a page 314 VMT page 320 pcie_monitor_vmt pcimaster_fx PCI PCI X Simulation Models and Test Suite FlexModels page 322 pcislave_fx page 316 pcimonitor_fx sata_device_vmt Serial ATA Models PRELIMINARY VMT page 320 sata_monitor_vmt page 317 sio_txrx_vmt Serial Input Output Interface Models page 318 VMT page 320 sio_monitor_vmt usb_host_vmt USB On
125. ation Name Function License Feature Required rpl Ripple synthesis model DesignWare cla Carry look ahead synthesis model DesignWare Synopsys Inc January 17 2005 DesignWare IP Family Application Specific Interface Overview Application Specific Interface Overview The Interface IP consist of the DW_debugger IP g m wn lt S gt D o N D gt D 5 January 17 2005 Synopsys Inc 47 DesignWare IP Family DW_debugger On Chip ASCII Debugger DW_debugger On Chip ASCII Debugger e Low gate count rd_bits wr_bits e Parameterized data widths rxd xd Xi div_bypass_mode gt clk reset _N Table 1 Pin Description Pin Name Width Direction Function clk l bit Input Clock reset_N 1 bit Input Synchronous reset active low rd_bits rd_bits_width bit s Input Input data bus rxd 1 bit Input Receive data wr_bits wr_bits_width bit s Output Output data bus txd 1 bit Output Transmit data div_bypass_mode 1 bit Input Clock Divider Bypass Control active high Table 2 Parameter Description Parameter Values Description rd_bits_width 8 to 2048 Width of rd_bits Default 8 wr_bits_width 8 to 2048 Width of wr_bits Default 8 clk_freq 21 must be a whole Clock rate in MHz number Default 1 baud_rate 300 600 1200 2400 Sets the baud rate of the UART 4800 9600 or 19200 Default 19200 mark_parity Oor 1 Set
126. ation can be followed by an addition without a carry propagation before the addition Similarly in product of sums an addition can be followed by a multiplication without a carry propagation before the multiplication The same techniques are also applied to reduce the number of carry propagations in magnitude comparisons of complete sum of products Resource and common subexpression sharing allow for further area savings The datapath generators then perform a constraint and technology driven synthesis of the extracted sum of product and product of sum blocks Enhanced algorithms are used to construct optimized adder reduction trees and carry propagate adders to meet the given timing constraints with minimal area requirements for the specified technology and conditions A smart generation feature selects the best among alternative implementation variants Special datapath library cells are automatically used where available and beneficial Optimized structures are generated for special arithmetic operations like constant multiplication or squaring 50 Synopsys Inc January 17 2005 DesignWare IP Family ee Datapath Arithmetic Overview Datapath Arithmetic Overview The Datapath arithmetic DesignWare Building Block IP many of which are inferred are applicable to ASIC or FPGA designs These IP are high performance arithmetic implementations based on a fast carry look ahead architecture to augment those in the Basic IP Library The
127. ator Interactive Waveform Viewer i Virtual Stepper Jupiter Jupiter DP JupiterXT JupiterXT ASIC JVXtreme Liberty Libra Passport Library Compiler Libra Visa LRC Magellan Mars Mars Rail Mars Xtalk Medici Metacapture Metacircuit Metamanager Metamixsim Milkyway ModelSource Module Compiler MS 3200 MS 3400 Nova Product Family Nova ExploreRTL Nova Trans Nova VeriLint Nova VHDLlint Optimum Silicon Orion_ec Parasitic View Passport Planet Planet PL Planet RTL Polaris Polaris CBS Polaris MT Power Compiler PowerCODE PowerGate ProFPGA Progen Prospector Proteus OPC Protocol Compiler PSMGen Raphael NES RoadRunner RTL Analyzer Saturn ScanBand Schematic Compiler Scirocco Scirocco i Shadow Debugger Silicon Blueprint Silicon Early Access SinglePass SoC Smart Extraction SmartLicense SmartModel Library Softwire Source Level Design Star Star DC Star MS Star MTB Star Power Star Rail Star RC Star RCXT Star Sim Star SimXT Star Time Star XP SWIFT Taurus Taurus Device Taurus Layout Taurus Lithography Taurus OPC Taurus Process Taurus Topography Taurus Visual Taurus Workbench TimeSlice TimeTracker Timing Annotator TopoPlace TopoRoute Trace On Demand True Hspice TSUPREM 4 TymeWare VCS Express VCSi Venus Verification Portal VFormal VHDL Compiler VHDL System Simulator VirSim and VMC are trademarks of Synopsys Inc Service Marks s MAP in SVP Caf and TAP in are service marks of Syno
128. ble For more details please refer to the DesignWare Building Block IP User Guide January 17 2005 Synopsys Inc 243 DesignWare IP Family Test JTAG Overview Test JTAG Overview The JTAG IP consist of a set of boundary scan IP The boundary scan IP include a parameterized Test Access Port TAP controller DW_tap plus a set of boundary scan cells that you can use to implement a custom IEEE 1149 1 boundary scan test solution for your ASIC 244 Synopsys Inc January 17 2005 DesignWare IP Family DW_tap TAP Controller DW_tap TAP Controller e JEEE Standard 1149 1 compliant clock_dr g hift_d e Synchronous or asynchronous registers with respect faite a m lt to tck tck sync_update_dr e Supports the standard instructions EXTEST tms tdo 2 SAMPLE PRELOAD and BYPASS tdi tdo_en 2 e Supports the optional instructions IDCODE on sync capturg en 5 INTEST RUNBIST CLAMP and HIGHZ bypass_sel tap_state tinel_val e Optional use of device identification register and sa extest IDCODE instruction Sampad instructi e Parameterized instruction register width ison i Table 1 Pin Description Pin Name Width Direction Function tck 1 bit Input Test clock trst_n 1 bit Input Test reset active low tms 1 bit Input Test mode select tdi 1 bit Input Test data in so l bit Input Serial data from boundary scan register and data regis
129. ble flag logic may be statically or dynamically programmed When statically programmed the threshold comparison value is hardwired at synthesis compile time When dynamically programmed it may be changed during FIFO operation January 17 2005 Synopsys Inc 181 g m wn lt S gt D o N D D z DesignWare IP Family DW_asymfifo_s1_df TEED Asymmetric I O Synchronous Single Clock FIFO with Dynamic Flag DW_asymfifo_s1_df Asymmetric I O Synchronous Single Clock FIFO with Dynamic Flag e Fully registered synchronous flag output ports yee eae data_out ata_in e D flip flop based memory array for high testability sense ram_full e All operations execute in a single clock cycle aiae a u e FIFO empty half full and full flags af_thresh almost_full e Parameterized asymmetric input and output bit widths flush_n half_full must be integer multiple relationship diag n almost empty e Word integrity flag for empty data_in_width lt data_out_width Ss clk eti error e Flushing out partial word for data_in_width lt data_out_width e Parameterized byte or subword order within a word e FIFO error flag indicating underflow overflow and pointer corruption e Parameterized word depth e Dynamically programmable almost full and almost empty flags e Parameterized reset mode synchronous or asynchronous memory array initialized or not 182 Synopsys Inc January 17 2005 DesignWare IP Family vine DW_asymfifo_s
130. bset control parameter 2 Default 0 0 for all special characters decoded 1 for only K28 5 decoded when k_char HIGH implies K28 5 O all other special characters indicate an error X en_mode Oor 1 Enable control Default 0 0 the enable input port is not connected backward compatible 2 with older components 1 when enable 0 the decoder is stalled init mode Qorl Initialization mode for running disparity Default O O during active init_rd_n input delay init_rd_val one clock cycle before applying it to data_in input in calculating data_out backward compatible with older components 1 during active init_rd_n input directly apply init_rd_val to data_in input with no clock cycle delay in calculating data_out Table 3 Synthesis Implementations Implementation Name Function License Feature Required rtl Synthesis model DesignWare January 17 2005 Synopsys Inc 151 DesignWare IP Family 00000000 oding DW_8b10b_enc Q 0100 1010110001 8b10b Encoder DW _ 8b10b enc 8b10b Encoder e Configurable data width data_in data_out e Configurable simplified Special Character control for k_char protocols requiring only the K28 5 special character init_rd_val init_rd_n enable gt clk e Synchronous initialization of Running Disparity with design specified value rst_n e All outputs registered Table 1 Pin Description
131. capabilities The DesignWare Memory Models all have built in memory debug utilities The debug utilities can be controlled from a VHDL Verilog Vera or SystemC testbench The verification engineer has access to memory load dump peek poke and trace commands g m S O o e gt 5 Debugging the memory model content interactively during run time simulation reduces the effort required to debug memory subsystems The DesignWare MemScope allows users to view and modify all the memory model data as well as monitoring the transaction types taking place on the selected models The MemScope connects directly to the DesignWare Memory Model technology core and not through the simulator This results in no simulation performance degradation even with the MemScope connected The memory transaction history can be viewed dynamically during simulation or in a post processing fashion The address and data fields can be searched to locate selected values quickly The memory model content can be viewed or modified dynamically during the simulation The data contents can be saved to a file for use as a pre load file in subsequent simulations The Memory Model documentation is available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 313 DesignWare IP Family PCI Express Models Transceiver and Monitor PCI Express Models Transceiver and Monitor pcie_txrx_vmt pcie_monitor_vmt Models
132. carry look ahead model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the Design Ware Building Block IP User Guide January 17 2005 Synopsys Inc 199 DesignWare IP Family DW_asymfifoctl_s1_df Asymmetric I O Synchronous Single Clock FIFO Controller with Dynamic F DW_asymfifoctl_s1_df Asymmetric I O Synchronous Single Clock FIFO Controller with Dynamic Flags Tit e Fully registered synchronous address and flag output push_req_n data_out ports data_in weaadr rd_data wr_data e All operations execute in a single clock cycle w_en e FIFO empty half full and full flags e Asymmetric input and output bit widths must be integer multiple relationship e Word integrity flag for data_in_width lt data_out_width e Flushing out partial word for data_in_width lt data_out_width e Parameterized byte order within a word pop_req_n rd_addr ae_level ram_full af_thresh part_wd full almost_full half_full flush_n diag_n almost_empty empty clk rst_n error e FIFO error flag indicating underflow overflow and pointer corruption e Parameterized word depth e Dynamically programmable almost full and almost empty flags e Parameterized reset mode synchronous or asynchronous e Interfaces
133. cation including high speed datapath components AMBA On Chip Bus memory portfolio verification models of standard bus and I Os foundry libraries popular Star IP cores and board verification IP e DesignWare Verification Library on page 26 is a subset of the DesignWare Library and contains reusable pre verified verification IP of the industry s most popular bus and interface standards such as AMBA PCI Express PCI X PCI USB On the Go Ethernet I7C and thousands of memory models e DesignWare Cores on page 28 silicon proven digital and analog standards based connectivity IP such as PCI Express PCI X PCI USB 2 0 On the Go OTG USB 2 0 PHY USB 1 1 and Ethernet e DesignWare Star IP on page 30 high performance high value cores from leading Star IP providers such as IBM Infineon Technologies MIPS Technologies NEC and Philips January 17 2005 Synopsys Inc 19 Chapter 1 Overview DesignWare IP Family DesignWare Library The DesignWare Library provides designers with a comprehensive collection of synthesizable IP verification IP and foundry libraries The library contains the following principal ingredients for ASIC SoC and FPGA design and verification Building Block IP Datapath Data Integrity DSP Test and more AMBA Bus Fabric Peripherals and Verification IP Memory portfolio memory controller memory BIST memory models and more Verification models of popular bus and I O Standards
134. ceiver Macrocell Interface PHY ssusicisesisisisesieridas 368 dwc_sata_host Sed ATA FIOM sorroikarb bess kESbaes keel bees KOSS 25694 eR TERET SRR 370 dwcore_1394_avlink Synthesizable IEEE 1394 AVLINk sosescs pou ceeeeeeeeseee dtes to reaa 372 dwcore_1394_cphy Synthesizable IEEE 1394 Cable PHY s issceesdeaseadeknndewes bao euas 374 dwcore_jpeg_codec Syntheszable JPEG CODEC octiniergsiririr itini e Enea 376 Chapter 6 DesignWare Star IP ssiiriresorireristr atana nna err anr An Sense vades 378 DW_IBM440 IBM Powa PC S30 CPU CHE 226 ch45s6eectodaeddatediossauns ae sd cece 379 12 Synopsys Inc January 17 2005 DesignWare IP Family Contents DW_V850E Star V850E Microcontroller Core from NEC Electronics 00005 381 DW_C166S C166S 16 Bit Microcontroller from Infineon 0 0 0c eee 383 DW_TriCorel TriCore1 32 Bit Processor Core from Infineon 0 000 eee 385 DW_MIPS4KE MIPS32 4KE Processor Core Family from MIPS Technologies 387 DW_CoolFlux CoolFlux 24 bit DSP Core from Philips lt cs0cc2csseeusetsuornwecaves 389 DIES 54554 AGN Seb E EEE hs Sh eee eee 392 January 17 2005 Synopsys Inc 13 Contents DesignWare IP Family 14 Synopsys Inc January 17 2005 DesignWare IP Family About This Manual Preface Preface This manual is a brief overview of the DesignWare Family of synthesizable and verification IP For detailed product information refer to individual product databooks a
135. cient values data_in A1_coef saturation A2_coef e Parameterized coefficient widths BO_coef B1_coef B2_coef data_out Applications e 1 D filtering e Matched filtering e Correlation e Pulse shaping e Equalization 160 Synopsys Inc January 17 2005 DesignWare IP Family DW_iir_dce High Speed Digital IIR Filter with Dynamic Coefficients Table 1 Signal Description Name Width VO Description clk 1 bit In Clock signal All registers are sensitive on the positive z edge of clk and all setup and hold times are with respect rc to this edge of clk L rst_n 1 bit In Asynchronous reset active low Clears all registers init_n 1 bit In Synchronous active low signal to clear all registers S enable 1 bit In Active high signal to enable all registers a D Al_coef max_coef_width bit s In Two s complement value of coefficient A1 5 A2_coef max_coef_width bit s In Two s complement value of coefficient A2 BO_coef max_coef_width bit s In Two s complement value of coefficient BO Bl_coef max_coef_width bit s In Two s complement value of coefficient B1 B2_coef max_coef_width bit s In Two s complement value of coefficient B2 data_in data_in_width bit s In Input data data_out data_out_width bit s Out Accumulated sum of products of the IIR filter saturation 1 bit Out Used
136. cludes logic to enable parking when no clients Pens EA no logic for parking park_index 0 to m4 Index of the client used for parking Default 0 output_mode Oor 1 output_mode 1 includes registers at the outputs Default 1 output_mode 0 contains no output registers Table 3 Synthesis Implementations Implementation Name Function License Feature Required cla Carry look ahead synthesis model DesignWare clas Carry look ahead select synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 42 Synopsys Inc January 17 2005 DesignWare IP Family DW_arbiter_fcfs Arbiter with First Come First Served Priority Scheme DW_arbiter_fcfs Arbiter with First Come First Served Priority Scheme e Parameterizable number of clients request 0 mask grant e Programmable mask for all clients lock grant_index D lt e Park feature default grant when no requests are pending O e Lock feature ability to lock the currently granted client N granted o e Registered unregistered outputs o 5 Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n l bit Input Active low input reset re
137. connectivity IP Provided as heavily annotated synthesizable RTL source code or in GDS format these cores enable you to design innovative cost effective systems on chip and embedded systems DesignWare Cores are licensed individually on a fee per project business model The following table identifies the DesignWare Cores offering IP Directory Component Name Component Description Component Type Ethernet Cores dwcore_ethernet Ethernet MAC 10 100 Synthesizable RTL Mbps Operation page 333 dwcore_ethernet_sub Ethernet MAC Subsystem Synthesizable RTL page 335 dwcore_gig_ethernet Gigabit Ethernet MAC Synthesizable RTL 10 100 Mbps and 1 Gbps Operation page 337 dwcore_gig_ethernet_sub Gigabit Ethernet MAC Synthesizable RTL GMAC Subsystem page 339 Flash Memory Controller Core 010 MA dwcore_sd_mmc_host Secure Digital SD and Synthesizable RTL Multimedia Card MMC Host Controller page 353 January 17 2005 Synopsys Inc 330 Chapter 5 DesignWare Cores DesignWare IP Family IP Directory Component Name Component Description Component Type IEEE 1394 Cores dwcore_1394_avlink TEEE 1394 AVLink Synthesizable RTL page 372 dwcore_1394_cphy TEEE 1394 Cable PHY Synthesizable RTL page 374 JPEG Core dwcore_jpeg_codec JPEG CODEC page 376 Synthesizable RTL PCI Cores
138. cription Parameter Values Description data_width 1to 256 Width of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width rst_mode Oor 1 Determines the reset methodology 0 rst_n asynchronously initializes the RAM 1 rst_n synchronously initializes the RAM Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare Synopsys Inc January 17 2005 100111001 DesignWare IP Family DW_ram_r_w_s lat Synchronous Write Port Asynchronous Read Port RAM Latch Based DW_ram_r_w_s lat Synchronous Write Port Asynchronous Read Port RAM Latch Based RAN rd_addr wr_addr e Parameterized word depth e Parameterized data width daan e Synchronous static memory Da data_out e Inferable from Behavioral Compiler wr_n g wo lt m gt D 2 N D D 5 Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low rd_addr ceil logy depth bit s Input Read address bus wr_addr ceil log depth bit s Input Write address bus data_in data_width bit s Input Input data bus data_out data_width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data_width 1 to 256 Width
139. cted based on the constraints of the design Synopsys Inc January 17 2005 DW01_satrnd Arithmetic Saturation and Rounding Logic e Parameterized word length e Dynamically or statically configurable e Arithmetic saturation clipping or wrap around for MSB truncation e Round to nearest logic for LSB truncation e Signed and unsigned data operation DesignWare IP Family DW01_satrnd Arithmetic Saturation and Rounding Logic din tc Table 1 Pin Description dout g m wo lt m gt D 2 N D 2 D 5 Pin Name Width Direction Function din width bit s Input Input data tc 1 bit Input Two s complement control 0 unsigned 1 signed sat 1 bit Input Saturation enable 0 no saturation 1 enable saturation rnd 1 bit Input Rounding enable 0 no rounding 1 enable rounding OV 1 bit Output Overflow status dout msb_out sb_out 1 bit s Output Output data Table 2 Parameter Description Parameter Values Description width 22 Word length of din Default 16 msb_out width 1 2 msb_out gt lsb_out dout MSB position after Default 15 truncation of din MSBs Isb_out msb_out gt lsb_out 0 dout LSB position after Default 0 truncation of din LSBs January 17 2005 Synopsys Inc 107 DesignWare IP Family DW01_satrnd Arithmetic Saturation and Rounding Logic 108 Table 3 Synthesis Implementations Im
140. ctive low push_empty 1 bit Output FIFO empty output flag synchronous to clk_push active high push_ae 1 bit Output FIFO almost empty output flag synchronous to clk_push active high determined by push_ae_lvl parameter push_hf 1 bit Output FIFO half full output flag synchronous to clk_push active high g m 7 lt m gt 0 2 N D D 5 push_af l bit Output FIFO almost full output flag synchronous to clk_push active high determined by push_af_lvl parameter push_full l bit Output FIFO s RAM full output flag including the input buffer of FIFO controller for data_in_width lt data_out_width synchronous to clk_push active high ram_full 1 bit Output FIFO s RAM excluding the input buffer of FIFO controller for data_in_width lt data_out_width full output flag synchronous to clk_push active high part_wd 1 bit Output Partial word accumulated in the input buffer synchronous to clk_push active high for data_in_width lt data_out_width only otherwise tied low push_error 1 bit Output FIFO push error overrun output flag synchronous to clk_push active high pop_empty 1 bit Output FIFO empty output flag synchronous to clk_pop active high pop_ae 1 bit Output FIFO almost empty output flag synchronous to clk_pop active high determined by pop_ae_lvl parameter pop_hf 1 b
141. ctive low init_n 1 bit Input Reset synchronous active low load_n 1 bit Input Enable data load to counter active low data width bit s Input Counter load input cen 1 bit Input Count enable active high count width bit s Output Gray coded counter output Table 2 Parameter Description Parameter Values Description width 21 Word length of counter Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cla Carry lookahead synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide January 17 2005 Synopsys Inc 69 DesignWare IP Family DW01_csa Carry Save Adder DW01_csa Carry Save Adder e Parameterized word length e Carry in and carry out signals Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Input data b width bit s Input Input data c width bit s Input Input data ci 1 bit Input Carry in carry width bit s Output Carry output data sum width bit s Output Sum output data co 1 bit Output Carry out Table 2 Parameter Description Parameter
142. d e AHB slave e Supports up to 16 APB slaves e Supports big and little endian AHB systems e Supports little endian APB slaves DesignWare IP Family DW_apb Advanced Peripheral Bus e Supports 32 64 128 256 AHB data buses e Supports 8 16 and 32 bit APB data buses e Supports single and burst AHB transfers g m wo lt m gt 0 o N D D 5 e Supports synchronous hclk pclk hclk is an integer multiple of pelk e The AHB slave side does not support SPLIT RETRY or ERROR responses Configurable w DW apb Slave Ports up to 16 lt gt Slave 0 Address AHB Slave Decoder AHB lt gt Interface Read Data MUX lt gt Slavej_ j upto15 The DesignWare DW_apb Databook is available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 273 DesignWare IP Family DW_apb_gpio APB General Purpose Programmable I O DW_apb_gpio APB General Purpose Programmable I O e Up to 128 independently configurable e Independently controllable port bits pins If more than 128 pins are e Configurable interrupt mode for Port required another DW_apb_gpio A should bota stontatad e Configurable debounce logic with an e Up to four ports A to D which are external slow clock to debounce separately configurable interrupts e Separate data registers and data e Option to generate single or multiple direction registers for each port interr
143. d for parking Default 0 output_mode 0 or 1 output_mode 1 includes registers at the outputs Default 1 output_mode 0 contains no output registers Table 3 Synthesis Implementations Implementation Name Function License Feature Required rtl Synthesis Model DesignWare a The implementation rtl replaces the obsolete implementations cla and clas Information messages listing implementation replacements S YNDB 37 may be generated by DC at compile time Existing designs that specify an obsolete implementation cla or clas will automatically have that implementation replaced by the new superseding implementation rtl noted by an information message SYNDB 36 generated during DC compilation The new implementation is capable of producing either of the original architectures automatically based on user constraints 40 Synopsys Inc January 17 2005 DesignWare IP Family DW_arbiter_dp Arbiter with Dynamic Priority Scheme DW_arbiter_dp Arbiter with Dynamic Priority Scheme e Parameterizable number of clients request s mask grant e Programmable mask for all clients lock grant index 9 e Park feature default grant when no requests are priory S i O pending cik locked N e Lock feature ability to lock the currently granted client granted arked e Registered unregistered outputs rs
144. de Counter wrap mode e Some uses of the DW_apb_trtc are o Real time clock used with software for keeping track of time o Long term exact chronometer When clocked with a 1 Hz clock it can keep track of time from now up to 136 years in the future o Alarm function generates an interrupt after a programmed number of cycles o Long time base counter clocked with a very slow clock signal DW_apb_rtc APB Interface Register Block Read Write Coherency Counter Synchronization Interrupt Generation Up Counter The DesignWare DW_apb_rtc Databook is available at http www synopsys com products designware docs 278 Synopsys Inc January 17 2005 DW_apb _ ssi APB Synchronous Serial Interface e AMBA APB interface Allows for easy integration into an AMBA System on Chip SoC implementation e Scalable APB data bus width Supports APB data bus widths of 8 16 and 32 bits e Serial master or serial slave operation Enables serial communication with serial master or serial slave peripheral devices e DMA Controller Interface Enables the DW_apb_ssi to interface to a DMA controller over the AMBA bus using a handshaking interface for transfer requests e Independent masking of interrupts Master collision transmit FIFO overflow transmit FIFO empty receive FIFO full receive FIFO underfl
145. der Stuffer and Hold Transmitters FS FS LS e Transceiver MUX Single Ended USB 1 1 Receivers Transceiver gt O oO 2 Analog Block Digital Block amp Transceiver Block amp USB 2 PHY Macro The dwcore_usb2_phy data sheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_usb2_phy pdf 369 Synopsys Inc January 17 2005 DesignWare IP Family C Og dwc_sata_host S Serial ATA Host dwc_sata host Serial ATA Host The DesignWare SATA Host intellectual property IP is designed for use in system on chip SoC solutions The IP uses the popular AHB standard for a host interface and a configurable PHY link interface to support a number of industry PHYs Synopsys provides a large set of parameters to enable the IP s integration in systems with different requirements By leveraging these parameters the DWC SATA Host can optimize gate count and reduce time to market Features e Provides hooks for DMA integration e Compliant with Serial ATA 1 0a e Data scrambling from the transport SATA II and SATA 2 0 ee EEY e Supports 1 5Gbps and 3 0Gbps data e Supports ATAPI 1 7 throughput e Supports Power down mode Power e Integrates SATA link layer and manag eniin transport layer logic e Supports CRC detection and generation e Highly Configurable Lightweight AHB slave interface to system bus e Highly Configurable PHY Link Interface o Variable data bus w
146. dex DW_add_fp 124 DW_addsub_dx 57 DW_ahb 266 DW_ahb_dmac 268 DW_ahb_eh2h 269 DW_ahb_h2h 284 DW_ahb_icm 271 DW_ahb_ictl 272 DW_apb 273 DW_apb_gpio 274 DW_apb_i2c 275 DW_apb_ictl 276 DW_apb_rap 277 DW_apb_rtc 278 DW_apb_ssi 279 DW_apb_timers 281 DW_apb_uart 282 DW_apb_wdt 286 DW_arbiter_2t 39 DW_arbiter_dp 41 DW_arbiter_fcfs 43 DW_arbiter_sp 45 DW_asymfifo_s1_df 182 DW_asymfifo_s1_sf 185 DW_asymfifo_s2_sf 189 DW_asymfifoctl_s1_df 200 DW_asymfifoctl_s1_sf 203 DW_asymfifoctl_s2_sf 206 DW_bc_1 250 DW_bc_10 261 DW_bc_2 251 DW_bc_3 252 DW_bc_4 253 DW_bc_5 254 DW_bc_7 255 DW_bc_8 257 DW_bc_9 259 DW_bin2gray 61 DW_C166S 383 DW_cmp_dx 67 DW_cmp_fp 125 DW_cntr_gray 69 Synopsys Inc 393 DesignWare IP Family DW_CoolFlux 389 DW_crc_p 142 DW _crc_s 144 DW_debugger 48 DW_div 73 DW_div_fp 126 DW_div_pipe 75 DW_div_seq 131 DW_dpll_sd 174 DW_ecc 146 DW_fifo_sl_df 193 DW_fifo_sl_sf 195 DW_fifo_s2_sf 197 DW_fifoctl_s1_df 210 DW_fifoctl_sl_sf 212 DW_fifoctl_s2_sf 214 DW_fir 156 DW_fir_seq 158 DW_flt2i_fp 129 DW_gray2bin 77 DW_hsata 370 DW_i2flt_fp 123 DW_IBM440 379 DW_iir_dc 160 DW_iir_sc 163 DW_inc_gray 82 DW_memctl 292 DW_minmax 85 DW_MIPS4KE 387 DW_mult_dx 98 DW_mult_fp 128 DW_mult_pipe 99 DW_amult_seq 133 DW_prod_sum_pipe 105 DW_ram_2r_ w_a_dff 234 DW_ram_2r_w_a_lat 236 DW_ram_2r_w_s_dff 226 DW_ram_2r_w_s_ lat 228 DW_ram_r_w_a_dff 232 DW_ram_r_w_a_lat 233 DW_ram_r_w_s_dff 224 DW_ram_r_w_s_lat 225
147. diag_n 1 bit Input Diagnostic control active low for err_mode 0 NC for other err_mode values data_in data_in_width bit s Input FIFO data to push January 17 2005 Synopsys Inc 203 DesignWare IP Family DW_asymfifoctl_s1_sf Asymmetric I O Synchronous Single Clock FIFO Controller with Static Flag tit Table 1 Pin Description Continued Pin Name Width Direction Function rd_data max data_in_width Input RAM data input to FIFO controller data_out_width bit s w_en 1 bit Output Write enable output for write port of RAM active low empty 1 bit Output FIFO empty output active high almost_empty 1 bit Output FIFO almost empty output active high asserted when FIFO level lt ae_level half_full 1 bit Output FIFO half full output active high almost_full 1 bit Output FIFO almost full output active high asserted when FIFO level depth af_level full 1 bit Output FIFO full output active high ram_full 1 bit Output RAM full output active high error 1 bit Output FIFO error output active high part_wd 1 bit Output Partial word active high for data_in_width lt data_out_width only otherwise tied low wr_data max data_in_width Output FIFO controller output data to RAM data_out_width bit s wr_addr ceil logs depth bit s Output Address output to write port of RAM rd_addr ceil logs depth bit s Output Address output to read po
148. dth K x data_in_width where K is an integer data_out_width 1 to 256 Width of the data_out bus data_out_width must be in an integer multiple relationship with data_in_width That is either data_in_width K x data_out_width or data_out_width K x data_in_width where K is an integer depth 4 to 224 Number of words that can be stored in FIFO push_ae_lvl 1 to depth 1 Almost empty level for the push_ae output port the number of words in the FIFO at or below which the push_ae flag is active push_af_lvl 1 to depth 1 Almost full level for the push_af output port the number of empty memory locations in the FIFO at which the push_af flag is active pop_ae_lvl 1 to depth 1 Almost empty level for the pop_ae output port the number of words in the FIFO at or below which the pop_ae flag is active pop_af_lvl 1 to depth 1 Almost full level for the pop_af output port the number of empty memory locations in the FIFO at which the pop_af flag is active err_mode Oor 1 Error mode 0 stays active until reset latched 1 active only as long as error condition exists unlatched 208 Synopsys Inc January 17 2005 Tit DesignWare IP Family DW_asymfifoctl_s2_sf Asymmetric Synchronous Dual Clock FIFO Controller with Static Flags Table 2 Parameter Description Continued Parameter Values Description push_sync 1 to3 Push flag sync
149. dth Direction Function A A_width bit s Input Multiplier B B_width bit s Input Multiplicand TC 1 bit Input Two s complement control 0 unsigned 1 signed PRODUCT A_width B_width bit s Output Product A x B Table 2 Parameter Description Parameter Values Description A_width 21 Word length of A B_width 21 Word length of B Table 3 Synthesis Implementations Implementation Name Function License Feature Required csa Carry save array synthesis model none nbw Either a non Booth A_width B_width 1 DesignWare or a Booth Wallace tree A_width B_width gt 41 synthesis model wall Booth recoded Wallace tree synthesis DesignWare model mcearch MC inside DW Wallace tree DesignWare csmult MC inside DW flexible Booth Wallace DesignWare pparch Delay optimized flexible Booth Wallace DesignWare 86 Synopsys Inc January 17 2005 DesignWare IP Family DW02_mult Multiplier a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b In cases where A_width B_width lt A1 the nbw implementation generates a non Booth recoded Wallace tree multiplier For multipliers having products larger than 41 bits such as A_width B_width gt 41 the nbw implementation produces a Booth recoded multiplier identical to t
150. e init_n draining e Parameterized register initialization all ones or all Id_crc_n drain_done zeroes erc_in crc_ok e Parameterized inverted insertion of generated CRC drain omer e Parameterized bit and byte ordering enable ae gt clk e Loadable CRC value for use in context switching of ded interspersed blocks Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock input rst_n 1 bit Input Asynchronous reset input active low init_n 1 bit Input Synchronous initialization control input active low enable 1 bit Input Enable control input for all operations other than reset and initialization active high drain 1 bit Input Drains control input active high Id_crc_n 1 bit Input eee CRC register load control input active ow data_in data_width bit s Input Input data crc_in poly_size bit s Input Input CRC value to be loaded into the CRC register as commanded by the Id_crc_n control input draining 1 bit Output Indicates that the CRC register is draining inserting the CRC into the data stream drain_done bit Output Indicates that the CRC register has finished draining crc_ok 1 bit Output Indicates a correct residual CRC value active high data_out data_width bit s Output Output data crc_out poly_size bit s Output Provides constant monitoring of the CRC register 144 Synopsys Inc January 17 2005 Des
151. e IP Family The dwcore_pcix data sheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_pcix pdf January 17 2005 Synopsys Inc as 5 dwcore_pcix Synthesizable PCI X Controller and Test Environment sE Address Data Input Block ve A J y i TA Defer Split lt lt Table Target Target State a gt Controller gt a gt Bd EEPROM ii Controller lt gt Optional g 4g 2 i Master Configuration Register _ J5 E E Controller Eoo w x z O i T l Power Management Controller lt a Optional d gt lt gt Master Master State Message lt gt Machine Master aeaee Signaled Defer Split 4 lt gt Interrupt Table Controller Optional e Address Data Output Block sa 344 010 MA DesignWare IP Family dwc_pcie_endpoint PCI Express Endpoint Synthesizable Core dwc_pcie_endpoint PCI Express Endpoint Synthesizable Core The DesignWare Endpoint EP PCI Express Core is a synthesizable endpoint solution that can be configured to address multiple applications ranging from server and desktop systems to mobile devices Other features include the following Designed according to the 1 0a PC
152. e counter counts If a timeout occurs the DW_apb_wdt can perform one of the following operations o Generate a system reset o First generate an interrupt and if this is not cleared by the service routine by the time a second timeout occurs then generate a system reset DW_apb_wdt Programmable timeout range period The option of hard coding this value during configuration is available to reduce the register requirements Optional dual programmable timeout period used when the duration waited for the first kick is different than that required for subsequent kicks The option of hard coding these values is available Programmable and hard coded reset pulse length Prevention of accidental restart of the DW_apb_wdt counter Prevention of accidental disabling of the DW_apb_wdt Optional support for Pause mode with the use of external pause enable signal Test mode signal to decrease the time required during functional test APB Register Interface Block Interrupt amp System Reset Control The DesignWare DW_apb_i2c Databook is available at 286 http www synopsys com products designware docs Synopsys Inc January 17 2005 DesignWare IP Family DesignWare AMBA Connect Design environment for AMBA synthesizable and verification IP DesignWare AMBA Connect Design environment for AMBA synthesizable and verification IP DesignWare AMBA Connect is a highly
153. e f 1 bits Input Divisor Z e f 1 bits Output Quotient of A B STATUS optional 8 bits Output Status flags RND optional 3 bits Input Rounding mode Table 2 Parameter Description Parameter Values Description e 3 to 31 bits Word length of biased exponent of floating point numbers A B and Z f 2 to 253 bits Word length of fraction field of floating point numbers A B and Z arch 1 2 and3 Architecture implementation 1 MC_divider architecture 1 producing 1 bit per iteration 2 MC_divider ROM based architecture producing 1 bit per iteration 3 MC_divider architecture 3 producing 2 bits per iteration Divider operands can be of any width for arch 1 and arch 3 but should be less than 10 bits for arch 2 For details see divide function of Module Compiler reference manual 126 Synopsys Inc January 17 2005 DesignWare IP Family DW_div_fp 2 4979 x 105 Floating Point Divider Table 3 Synthesis Implementations Implementation Name Function License Feature Required arch0 Synthesis model DesignWare g m wn lt S gt D o N D gt D 5 January 17 2005 Synopsys Inc 127 DesignWare IP Family DW_mult_fp Floating Point Multiplier DW_mult_fp Floating Point Multiplier Module Compiler Only e The precision format is parameterizable for either IEEE single double precision or a user defined custom format e Exponents can r
154. efer to the DesignWare Building Block IP Users Guide This area and delay optimized Booth Wallace architecture is generated using Datapath generator technology DW gensh This is ON by default in Design Compiler flow The DC variable synlib_enable_dpgen must be set to true the default to make use of this Datapath technology Synopsys Inc January 17 2005 DW02_prod_sum1 Multiplier Adder e Parameterized number of inputs DesignWare IP Family DW02_prod_sum1 Multiplier Adder TC e Parameterized word length a B SUM C Table 1 Pin Description Pin Name Width Direction Function A A_width bit s Input Input data B B_width bit s Input Input data C SUM_width bit s Input Input data TC 1 bit Input Two s complement 0 unsigned 1 signed SUM SUM_width bit s Output Sum of products Table 2 Parameter Description Parameter Values Description A_width gt 1 Word length of A B_width gt 18 Word length of B SUM_width 21 Word length of C and output SUM a For nbw implementation A_width B_width 36 Due to concern of implementation selection run time a limitation is set for A_width and B_width Table 3 Synthesis Implementations Implementation Name Function License Feature Required csa Carry save array synthesis model DesignWare wall Booth recoded Wallace tree synthesis DesignWare model nbw Either a non Booth A_width
155. egistered or un registered inputs and outputs quotient remainder divide_by_0 complete clk Table 1 Pin Description g wo lt m gt D 2 N D D 5 Pin Name Width Direction Function clk l bit Input Clock rst_n 1 bit Input Reset active low hold 1 bit Input Hold current operation 1 start 1 bit Input Start operation 1 A new operation is started by setting start 1 for one clock cycle a a_width bit s Input Dividend b b_width bit s Input Divisor complete 1 bit Output Operation completed 1 divide_by_0 1 bit Output Indicates if b equals O quotient a_width bit s Output Quotient remainder b_width bit s Output Remainder Table 2 Parameter Description Parameter Values Description a_width 23 Word length of a b_width 23 and lt a_width Word length of b tc_mode Oor 1 Two s complement control Default 0 0 unsigned 1 two s complement num_cyc 23 and lt a_width User defined number of clock cycles to produce a valid Default 3 result The real number of clock cycles depends on various parameters January 17 2005 Synopsys Inc 131 DesignWare IP Family DW_div_seq Sequential Divider Table 2 Parameter Description Continued Parameter Values Description rst_mode O or 1 Reset mode Default 0 0 as
156. ell Type BC_5 e IEEE Standard 1149 1 compliant data_in data_out e Synchronous or asynchronous scan cells with respect to tck intest f mode e Supports the standard instructions EXTEST SAMPLE shift di PRELOAD and BYPASS 3 capture_en e Supports the optional instructions INTEST RUNBIST update_en CLAMP and HIGHZ update_clk gt capture_clk Table 1 Pin Description Pin Name Width Direction Function capture_clk 1 bit Input Clocks data into the capture stage update_clk 1 bit Input Clocks data into the update stage capture_en 1 bit Input Enable for data clocked into the capture stage active low update_en 1 bit Input Enable for data clocked into the update stage active high shift_dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo mode 1 bit Input Determines whether data_out is controlled by the boundary scan cell or by the data_in signal intest 1 bit Input INTEST instruction signal si l bit Input Serial path from the previous boundary scan cell data_in l bit Input Input data from system input pin data_out l bit Output Output data SO l bit Output Serial path to the next boundary scan cell Table 2 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare or Test EEE STD 1149 1 254 Synopsys Inc Jan
157. ementation Name Function License Feature Required csa Carry save array synthesis model DesignWare clsa gt MC inside DW carry look ahead select DesignWare fastcla gt MC inside DW fast carry look ahead DesignWare mccsa MC inside DW carry select DesignWare pprefix MC inside DW flexible parallel prefix DesignWare ripple MC inside DW ripple carry DesignWare rpl Ripple carry synthesis model DesignWare wall Wallace tree synthesis model DesignWare pparch Delay optimized flexible parallel prefix DesignWare apparch Area optimized flexible parallel prefix DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same January 17 2005 Synopsys Inc 119 DesignWare IP Family DW02 sum Vector Adder DesignWare part To use this architecture during synthesis the dc_shell t variable dw_prefer_mc_inside must be set to true From the DC 2004 12 release onward the MC architectures are not available by default For more information refer to the DesignWare Building Block IP Users Guide c These area and delay o
158. empty output active high almost_empty 1 bit Output FIFO almost empty output active high asserted when FIFO level lt ae_level half_full 1 bit Output FIFO half full output active high almost_full 1 bit Output FIFO almost full output active high asserted when FIFO level af_thresh full 1 bit Output FIFO full output active high ram_full 1 bit Output RAM full output active high error 1 bit Output FIFO error output active high part_wd 1 bit Output Partial word active high for data_in_width lt data_out_width only otherwise tied low wr_data max data_in_width Output FIFO controller output data to RAM data_out_width bit s wr_addr ceil logs depth bit s Output Address output to write port of RAM rd_addr ceil log depth bit s Output Address output to read port of RAM data_out data_out_width bit s Output FIFO data to pop January 17 2005 Synopsys Inc 201 DesignWare IP Family DW_asynmfifoctl_s1_df Asymmetric I O Synchronous Single Clock FIFO Controller with Dynamic F Tit Table 2 Parameter Description Parameter Values Description data_in_width 1 to 256 Width of the data_in bus data_in_width must be in an integer multiple relationship with data_out_width That is either data_in_width K x data_out_width or data_out_width K x data_in_width where K is an integer data_out_width 1 to 256 Width of the data_out bus data_out_width must be in an in
159. enable_dpgen must be set to true the default to make use of this Datapath technology g m wo lt m gt D 2 N D 2 D 5 January 17 2005 Synopsys Inc 79 DesignWare IP Family DW01_incdec Incrementer Decrementer DW01_incdec Incrementer Decrementer e Parameterized word length Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data INC_DEC Input Increment control 0 increment A 1 1 decrement A 1 SUM width bit s Output Increment A 1 or decrement A 1 Table 2 Parameter Description Parameter Values Function width 21 Word length of A and SUM Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none clf Fast carry look ahead synthesis model DesignWare clsa MC inside DW carry look ahead select DesignWare csa MC inside DW carry select DesignWare fastcla MC inside DW fast carry look ahead DesignWare pprefix MC inside DW flexible parallel prefix DesignWare pparch Delay optimized flexible parallel prefix DesignWare 80 Synopsys Inc January 17 2005 DesignWare IP Family DW01_incdec Incrementer Decrementer a During synthesis Design Compiler will select the appropriate architecture for your constraints H
160. ential and control IP page 38 Synthesizable RTL Memory Registers FIFO synchronous and asynchronous Synthesizable RTL RAM and stack IP page 217 Test JTAG IP such as boundary scan TAP controller Synthesizable RTL page 244 GTECH Technology independent IP library to aid users in Synthesizable RTL developing technology independent parts page 263 January 17 2005 Synopsys Inc 21 Chapter 1 Overview DesignWare IP Family AMBA On Chip Bus AMBA is a standard bus architecture system developed by ARM for rapid development of processor driven systems The AMBA standard also allows a number of bus peripherals and resources to be connected in a consistent way The following Synopsys DesignWare AMBA components are AMBA 2 0 compliant Component Name DesignWare AMBA 2 0 Component Description Component Type DW_ahb AHB bus arbitration decode and control logic Synthesizable RTL page 266 DW_ahb_dmac AHB Central Direct Memory Access DMA Synthesizable RTL Controller page 268 DW_ahb_h2h AHB to AHB Bridge page 284 Synthesizable RTL DW_ahb_icm AHB Multi layer Interconnection Matrix Synthesizable RTL page 271 DW_ahb_ictl AHB Interrupt Controller page 272 Synthesizable RTL DW_apb APB bus decode and bridge page 273 Synthesizable RTL DW_apb_gpio APB General Purpose I O GPIO page 274 Synthesizable RTL DW_apb_ictl APB Interrupt Con
161. ermines whether data_out is controlled by the boundary scan cell or by the data_in signal si l bit Input Serial path from the previous boundary scan cell pin_input 1 bit Input IC system input pin output_data 1 bit Input IC output logic signal data_out 1 bit Output Output data SO 1 bit Output Serial path to the next boundary scan cell Table 2 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare or Test EEE STD 1149 1 January 17 2005 Synopsys Inc 261 DesignWare IP Family DW_bc_10 Boundary Scan Cell Type BC_10 262 Table 3 Simulation Models Model Function DW04 DW_bc_10_CFG_SIM Design unit name for VHDL simulation dw dw04 src DW_bc_10_sim vhd VHDL simulation model source code dw sim_ver DW_bc_10 v Verilog simulation model source code Synopsys Inc January 17 2005 DesignWare IP Family GTECH Library Overview GTECH Library Overview Synopsys provides the GTECH technology independent library to aid users in developing technology independent parts Also DesignWare IP often use these cells for their implementation This generic technology library called gtech db contains common logic elements gtech db can be found under the Synopsys root directory in libraries syn Simulation models are located under the Synopsys root directory in packages gtech sre VHDL
162. es The library features models of devices from the world s leading semiconductor manufacturers including microprocessors controllers peripherals memories and general purpose logic SmartModels connect to logic simulators through the SWIFT interface which is integrated with over 30 commercial simulators including Synopsys VCS and Scirocco Cadence Verilog XL and Mentor Graphics QuickSim II Instead of simulating devices at the gate level SmartModels represent integrated circuits and system buses as black boxes that accept input stimulus and respond with appropriate output behavior Such behavioral models are distributed in object code form because they provide improved performance over gate level models while at the same time protecting the proprietary designs created by semiconductor vendors All SmartModels and model datasheets are listed in the IP Directory which you can find on the Web at http www synopsys com products designware ipditr g m S O o e gt 5 SmartModel Features e Support for Windows allowing you to view and change internal register values e Consistent SWIFT interface across most simulators e Simulation efficient behavorial level models e Industry standard as well as configurable timing behavior SmartModel Types There are two basic types of SmartModels e Full functional Models FFMs simulate the complete range of device behavior e Bus Functional Models BFMs s
163. esis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare or Test IEEE STD 1149 1 January 17 2005 Synopsys Inc 249 DesignWare IP Family DW_bc_1 Boundary Scan Cell Type BC_1 DW_bc_1 Boundary Scan Cell Type BC_1 e IEEE Standard 1149 1 compliant data_in data_out i j SO e Synchronous or asynchronous scan cells with respect to tck SI mode e Supports the standard instructions EXTEST SAMPLE shift dr PRELOAD and BYPASS 7 e Supports the optional instructions INTEST RUNBIST CLAMP and HIGHZ capture_en update_en gt update_clk gt capture_clk Table 1 Pin Description Pin Name Width Direction Function capture_clk 1 bit Input Clocks data into the capture stage update_clk 1 bit Input Clocks data into the update stage capture_en 1 bit Input Enable for data clocked into the capture stage active low update_en_ 1 bit Input Enable for data clocked into the update stage active high shift_dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo mode 1 bit Input Determines whether data_out is controlled by the boundary scan cell or by the data_in signal Si 1 bit Input Serial path from the previous boundary scan cell data_in 1 bit Input Input data data_out 1 bit Output Output data so 1 bit Output Serial path to the next boundary sc
164. et Core dwcore_ethernet Synthesizable Ethernet Core The Synopsys DesignWare Ethernet Media Access Controller MAC includes the MAC and the MAC test environment The Ethernet MAC is in a synthesizable Verilog RTL code that provides all the necessary features to implement the layer 2 protocol of the Ethernet standard Features include the following Compliant with IEEE 802 3 and 802 3u specifications Supports 10 100 Mbps data transfer rates IEEE 802 3 Media Independent Interface MII Reduced Media Independent Interface RMIT and General Purpose Serial Interface Supports Full and Half Duplex operations Support for control frames in Full Duplex mode IEEE 802 3x Configurable counters for remote monitoring RMON Virtual LAN VLAN support e Wake on S B Wake on LAN and 333 magic packets Synopsys Inc Collision detection in Half Duplex mode CSMA CD protocol Preamble generation and removal Automatic 32 bit CRC generation and checking Complete status for transmission and reception packets Optimized for switching routing network interface card and system on chip applications RapidScript utility for fast RMON customization Virtual Component Interface VCI Available in Verilog Application integration support Approximately 12K gates January 17 2005 DesignWare IP Family Cc Og dwcore_ethernet S Synthesizable Ethernet Core Application Interface MAC Host Block MAC CSR Block MHT
165. et_monitor_vmt e Interfaces for 10 100 1G and 10G e Protocol checking for supported frame MII SMII GMII XGMII XAUT types and errors e Half and full duplex MAC operation e Transaction logging for frames fault Multiple frame types MAC VLAN tagged control and jumbo User defined frame content Flow control with pause frames Adjusts IPG for effective data rate Frame error generation and recognition Code error generation injection Link fault support Robust command set control Ethernet VIP Monitor_1 Rx Monitor_16 Tx_direction Rx_direction Ms OE Co iy Bin Port Tx MII SMII GMII XGMII XAUI Port 2 Port Rx MII SMII GMII XGMII XAUI MII SMII GMII XGMII XAUI messaging and cycle level bus activity Configurable to match TxRx model Watchpoint monitoring Cumulative simulation coverage Dynamic start stop Command set control Port 1 Port Rx Port Tx The DesignWare Ethernet Verification IP User Manual is available at http www synopsys com products designware docs 310 Synopsys Inc September 1 2004 DesignWare IP Family Ethernet Models RMII Transceiver and Hub Ethernet Models RMII Transceiver and Hub The Synopys Ethernet FlexModel set consists of two models and system testbenches in Vera Verilog C and VHDL e rmiirs_fx The RMII interface is a low pin count MII interface intended for use between the ethernet PHY and switch or repeater
166. eter Description Parameter Values Description data_width 1 to 256 Width of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width rst_mode Oor 1 Determines the reset methodology 0 rst_n asynchronously initializes the RAM 1 rst_n synchronously initializes the RAM 226 Synopsys Inc January 17 2005 DesignWare IP Family 100111001 RAM DW_ram_2r_w_s_dff 01101001 Synchronous Write Port Asynchronous Dual Read Port RAM Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare g m wo lt m gt D 2 N D 2 D 5 January 17 2005 Synopsys Inc 227 DesignWare IP Family 100111001 DW_ram_2r_w_s lat RAM Synchronous Write Port Asynchronous Dual Read Port RAM Latch Based 201101001 DW_ram_2r_w_s lat Synchronous Write Port Asynchronous Dual Read Port RAM Latch Based e Parameterized word depth rd1_addr rd2_addr e Parameterized data width taddi e Synchronous static memory data_in cs_n wr_n data_rd2_out data_rd1_out e Inferable from Behavioral Compiler Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low rdl_addr ceil logs depth bit Input Read1 address bus rd2_addr ceil
167. etiming Table 1 Pin Description rst_n a gil b gt aix bi tc sum en g m wo lt m gt D 2 N D 2 D 5 Pin Name Width Direction Function clk 1 bit Input rst_n 1 bit Input Reset active low not used if parameter en 1 bit Input Load enable used only if parameter tc 1 bit Input Two s complement control a a_width X num_inputs bit s Input Concatenated input data vector b b_width X num_inputs bit s Input Concatenated input data vector sum sum_width bit s Output Pipelined data summation January 17 2005 Synopsys Inc 105 DesignWare IP Family DW_prod_sum_pipe Stallable Pipelined Generalized Sum of Products Table 2 Parameter Description Parameter Values Description a_width gt 1 Word length of a Default None b_width 21 Word length of b Default None num_inputs gt 1 Number of inputs Default 2 num_stages 2 Number of pipeline stages Default 2 stall_mode 0or 1 Stall mode Default 1 0 non stallable 1 stallable rst_mode 0 to 2 Reset mode Default 1 0 no reset 1 asynchronous reset 2 synchronous reset sum_width 2 1 Word length of sum Default None Table 3 Synthesis Implementations Implementation Name Implementation License Feature Required a Pipelined str synthesis model DesignWare 106 a One of csa wall or nbw implementation is sele
168. ev ciGoss sus Seuss Sees Sess 5 31 DW0l1_absval Absolu Val cccckas boned ae cekhesdedansssdudacheeasienes 644 dunks 52 DWO1_add POU 2 45 hounds end bene Gn se peas AT ETETE E EEATT 53 DW01_addsub Aider lhe seort ee ee ee ee ee oe eee 39 DW_addsub_dx Duplex Adder Subtractor with Saturation and Rounding 57 DW0l1_ash PIS EF ersen r aa A A a ea es 59 DW_bin2gray Binary to Gray COVE os he 8 6 oho 54 64 kde SSG 4 piire he heina bees kE 61 DWO1_bsh Panel Pel ee ee ee ee eee eee ee ee er rer ee re ee er ree 62 DWO01_cmp2 2 Ubon COMPO pn ded bee eeakekgxcened ban deade bu adewed anria 63 DWO0O1_cmp6 Cerin Comparator bide tea ees bokeh kha ees EETA ee ea 65 DW_cmp_dx Puplex ns 5 se a a a aa 67 DW_cntr_gray Bary ON i no sh vanu ee bbe dees eRieiee eennel sanded Cones neees 69 DWO1_csa ctl AVG AOE isos set ce oeseebae re wh eseee sees Sages shes eee n esse 70 DW0O1_dec be os ee eee ee eee ee ee ea ee ee ee ee ey ee a4 DW_div Combinational DIVET 224504 ncs oad yee dese ene een dee naeuede des eeass T DW_div_pipe Stallable Pipelined DPIvidef lt i4s si esteuegi ened dleeecheoaeeidesG esas T3 DW_gray2bin ary ary Cn na 5s koa eh ottur ENIGEEN ERES Oe Knee baa af DWOL_ inc Fe cots Mae nee me ie ee EEEE TEE ter ee er enn a rere en ne ree arene re 78 DWO1_incdec Incrementer Decrem ni t 21626cc545n60cceocneesedoaredecnwiaess A 80 DW_inc_gray Gray lacrementel 44 93 ce encee se duaneeediiadsGus phone en diweseene sued 82 D
169. ftware Transfer EST release of DesignWare Building Block IP from the following location http www synopsys com designware dwest If you prefer you may also send an email to dw_EST synopsys com with EST in subject line In that email send the following information in the body of the message in the following format lt Site Id gt lt Synopsys Release gt For example if your site id is 555 and you want to install the EST for use with the 2003 03 version of the Synopsys Synthesis CD write the following two fields in the body of the message separated by a few blank spaces 555 2003 03 Setting Up DesignWare Building Block IP in DC Include the following lines in your synopsys_dc setup file and ensure that you have a valid DesignWare Library license target library your _library db synthetic library dw _foundation sldb link library target library synthetic library search path search path synopsys root dw sim ver synopsys root libraries syn your library path synlib wait for design license DesignWare 32 Synopsys Inc January 17 2005 DesignWare IP Family Chapter 2 DesignWare Library Synthesizable IP Accessing DesignWare Building Block IP in DC You can access DesignWare Building Block IP either by operator or functional inference or by instantiating the component directly The example below shows how to access these IP Verilog assign PROD IN1 IN2 Operator I
170. gnWare a One of rpl cla or cl2 implementation is selected based the constraints of the design 76 Synopsys Inc January 17 2005 DW_gray2bin Gray to Binary Converter e Parameterized word length e Inferable using a function call Table 1 Pin Description DesignWare IP Family DW_gray2bin Gray to Binary Converter g m wn lt S gt D o N D gt D 5 Pin Name Width Direction Function g width bit s Input Gray coded input data b width bit s Output Binary coded output data Table 2 Parameter Description Parameter Values Description width 21 Input word length Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cla Carry lookahead synthesis model DesignWare January 17 2005 Synopsys Inc 77 DesignWare IP Family DW01 inc Incrementer DW01 inc Incrementer e Parameterized word length Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data SUM width bit s Output Increment A 1 Table 2 Parameter Description Parameter Values Description width 21 Word length of A and SUM Table 3 Synthesis Implementations Implementation Name Function License Feature Required
171. gtl 1 bit Output Part1 greater than output condition lt2 l bit Output Full width or part2 less than output condition eq2 1 bit Output Full width or part2 equal output condition gt2 1 bit Output Full width or part2 greater than output condition Table 2 Parameter Description Parameter Values Description width 24 Word width of a and b pl_width 2 to width2 Word width of part of duplex compare Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare bk Brent Kung synthesis model DesignWare January 17 2005 Synopsys Inc 67 DesignWare IP Family DW_cmp_dx Duplex Comparator a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 68 Synopsys Inc January 17 2005 DesignWare IP Family DW_cntr_gray Gray Code Counter DW_cntr_gray Gray Code Counter e Gray encoded output data count e Asynchronous and synchronous reset e Count enable g m wo lt m gt D 2 N D D 5 Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock rst_n 1 bit Input Reset asynchronous a
172. h Delay optimized flexible parallel prefix DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b The performance of the csm implementation is heavily dependent on the use of a high performance inverting 2 to 1 MUX in the technology library In such libraries the csm implementation exhibits a superior area delay product Although the csm implementation does not always surpass the delay performance of the clf implementation it is much lower in area c This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc_shell t variable dw_prefer_mc_inside must be set to true From the DC 2004 12 release onward the MC architectures are not available by default For more information refer to the DesignWare Building Block IP Users Guide d This delay optimized parallel prefix architecture is generated using Datapath generator technology DW gensh This is ON by default in the Design Compiler flow The DC variable synlib_enable_dpgen must be set to true the default to make use of this
173. h Static Coefficients e High speed direct form vector sum architecture e High speed transposed form multiplier architecture enable init_n e Parameterized input output and feedback data data_in saturation widths data_out rst_n e Parameterized coefficient values and widths gt clk e Parameterized fraction widths and saturation mode Applications e 1 D filtering e Matched filtering e Correlation e Pulse shaping e Equalization Table 1 Signal Description Name Width VO Description clk 1 bit Input Clock signal All internal registers are sensitive on the positive edge of clk and all setup and hold times are with respect to this edge of clk rst_n 1 bit Input Synchronous reset active low Clears all registers init_n 1 bit Input Synchronous active low signal to clear all registers enable 1 bit Input Active high signal to enable all registers data_in data_in_width bit s Input Input data data_out data_out_width bit s Output Accumulated sum of products of the IIR filter saturation 1 bit Output Used to indicate the output data or feedback data is in saturation January 17 2005 Synopsys Inc 163 dl a1qezisayyAs IMA DesignWare IP Family DW _iir_ sc High Speed Digital IIR Filter with Static Coefficients Table 2 Parameter Description Parameter Values Description data_in_ width gt 2 Default 8 Input data word length
174. h request active low pop_req_n 1 bit Input Stack pop request active low we_n 1 bit Output Write enable for RAM write port active low empty 1 bit Output Stack empty flag active high full 1 bit Output Stack full flag active high error 1 bit Output Stack error output active high wr_addr ceil log depth bit s Output Address output to write port of RAM rd_addr ceil logs depth bit s Output Address output to read port of RAM 242 Synopsys Inc January 17 2005 DesignWare IP Family DW_stackctl Synchronous Single Clock Stack Controller Table 2 Parameter Description Parameter Values Function depth 2 to 224 Number of memory elements in the stack used to Default None 912 the address ports g err_mode Oor 1 Error mode a Default 0 0 underflow overflow error hold until reset 1 underflow overflow error hold until next clock a rst_mode 0 or 1 Reset mode N Default 0 0 asynchronous reset 5 1 synchronous reset Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cl2 Full carry look ahead model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this ta
175. hapter 1 Overview pcie_txrx_vmt PCI Express 1 00a page 314 Verification Model pcie_monitor_vmt pcimaster_fx PCI PCI X Simulation Model and Test Suite Verification Models pcislave_fx page 316 pcimonitor_fx usb_host_vmt USB On The Go Models 1 1 2 0 OTG UTMI Verification Model usb_device_vmt and UTMI page 319 usb_monitor_vmt sio_txrxvmt Serial Input Output Interface Models page 318 Verification Models sio_monitor_vmt DesignWare Design Views of Star IP Cores DW_IBM440 PowerPC 440 Microprocessor Core from IBM Verification Model page 379 DW_V850E Star V850E Processor Core from NEC page 381 Verification Model DW_C166S 16 bit Processor Core from Infineon page 383 Verification Model DW_TriCorel TriCore1 32 Bit Processor Core from Infineon Verification Model page 385 DW_MIPS4KE 32 bit Processor Core Family from MIPS Verification Model page 387 DW_CoolFlux CoolFlux 24 bit DSP Core from Philips page 389 Verification Model DesignWare Memory Access to the full suite of memory IP is made available through DesignWare Memory Central a memory focused Web site that lets designers download DesignWare Memory IP and documentation Visit Memory Central at http www synopsys com products designware memorycentral Also visit the DesignWare Verification Library web page at http www synopsys com products designware dwverificationlibrary html January 17
176. he Instruction Unit Controller Cache seule ee I F Register ISPRAM I F gt EC I F Bus Interface EJTAG I F Unit gt Trace Control EJTAG Trace I F Block DW_MIPS4KE Block Diagram Also see the following web page for additional information gt http www synopsys com products designware starip mips_4ke html January 17 2005 Synopsys Inc 388 DesignWare IP Family DW_CoolFlux CoolFlux 24 bit DSP Core from Philips DW_CoolFlux CoolFlux 24 bit DSP Core from Philips RA Phillips CoolFlux DSP is a synthesizable 24 bit DSP Core for ultra low power applications like portable audio encoding decoding sound enhancement and noise suppression The core targets specific applications such as headsets hearing instruments and portable audio players The Philips CoolFlux DSP is designed with a highly efficient ILP optimizing C compiler The compiler can exploit all the parallelism in the core and generates very efficient code both from a cycle and code density perspective Other features include the following e Ultra low power consumption o lt 0 1mW MHz 1 2V 0 13u CMOS o lt 0 2m W MHz 1 8V 0 18u CMOS e Highly optimizing C compiler e Minimal core size 43K gates excluding debug interface 4 5k gates e Small memory footprint e Performance worst case commercial conditions o 175 MHz 0 13u CMOS o 135 MHz 0 184 CMOS gt 1000 MOPs e Extensive software library for audi
177. he RapidScript utility builds the core and test environment in source code for the targeted application Other features include the following Certified High Speed USB 2 0 Device Controller Supports 480 Mbps 12 Mbps and 1 5 Mbps devices Supports USB 2 0 Transceiver Macrocell Interface UTMI e Verilog source code Interfaces to any application bus Supports Virtual Component Interface VCD to application logic Optional support for AHB and DMA engine Programmable number of endpoints e Flexible endpoint configuration with Windows 98 ME 2000 XP Host Class Drivers e Process independent and portable January 17 2005 Fully synchronous design Synopsys Inc Microprocessor and tool independent Backward compliance with USB 1 1 Specification Supports up to 16 configurations 16 interfaces per configuration and 16 alternate settings per interface Easy endpoint configuration Supports chirp sequences Supports Ping protocol Suspend resume logic provided Supports UTMI compliant transceiver and Philips ISP1501 Peripheral Transceiver Get Descriptor command can be decoded by the application Supports vendor specific commands Maintains address pointer for Endpoint 0 transaction 366 010 MA DesignWare IP Family dwcore_usb2_device 4 Qs Synthesizable USB 2 0 Device Controller VCI Application Control VCI State Status Block Machine rr Suspend Synchronization Block Resume Block S
178. he legal range is a guideline to ensure reasonable compile times Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc 177 DesignWare IP Family DW03_Ifsr_load fox LFSR Counter with Loadable Input DW03_Ifsr_load LFSR Counter with Loadable Input e Parameterized word length e Loadable counter registers e High speed area efficient e Asynchronous reset e Terminal count Table 1 Pin Description Pin Name Width Direction Function data width bit s Input Input data load 1 bit Input Input load data to counter active low cen 1 bit Input Input count enable clk 1 bit Input Clock reset 1 bit Input Asynchronous reset active low count width bit s Output Output count bus Table 2 Parameter Description Parameter Values Description width 1 to 50 Word length of counter a The upper bound of the legal range is a guideline to ensure reasonable compile times Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare 178 Synopsys Inc January 17 2005 ee DW03_Ifsr_updn LFSR Up Down Counter e High speed area efficient Asynchronous reset Terminal count flag Pseudorandom sequence generat
179. he start of processing of a data_in sample hold 1 bit Output Handshake signal that indicates processing has been completed for the current data_in sample and the filter is ready to process the next sample data_out data_out_width Output The accumulated sum of products from the FIR bit s convolution plus the init_acc_val input order 1 init_acc_val n 1 data_in n i 1 coef i i 0 Table 2 Parameter Description Parameter Values Description data_in_width gt 1 Input data word length coef_width gt 1 Coefficient word length data_out_width gt 1 Accumulator word length order 2 to 256 FIR filter order a The parameter data_out_width is normally set to a value of coef_width data_in_width margin The value coef_width data_in_width accounts for the internal coefficient multiplications An appropriate margin must be included if the filter coefficients have a gain or are cascaded The value margin lt log2 order Table 3 Synthesis Implementations Implementation Name Function License Required str Structural synthesis model DesignWare January 17 2005 Synopsys Inc 159 g m wo lt m gt D 2 N D D 5 DesignWare IP Family DW_iir_dc High Speed Digital IIR Filter with Dynamic Coefficients DW_iir_dc High Speed Digital IIR Filter with Dynamic Coefficients e High speed transposed form multiplier architecture i l enable init_n e Variable coeffi
180. he wall implementation c In most cases the wall implementation generates faster and smaller circuits for medium to large sized multipliers g m wo lt m gt D 2 N D 2 D 5 d Automatically selects Booth recoding or non Booth recoding depending on constraints e This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc_shell t variable dw_prefer_mc_inside must be set to true From the DC 2004 12 release onward the MC architectures are not available by default For more information refer to the DesignWare Building Block IP Users Guide f This delay optimized Booth Wallace architecture is generated using Datapath generator technology DW gensh This is ON by default in Design Compiler flow The DC variable synlib_enable_dpgen must be set to true the default to make use of this Datapath technology January 17 2005 Synopsys Inc 87 DesignWare IP Family DW02_multp Partial Product Multiplier DW02_multp Partial Product Multiplier e Parameterized word lengths e Parameterized sign extension of partial product outputs for use in summing products e Unsigned and signed two s complement data operation Table 1 Pin Description Pin Name Width Direction
181. hesis Implementations Implementation Function License Feature Required pparch Delay optimized flexible Booth Wallace DesignWare aparch Area optimized flexible Booth Wallace DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints 102 However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide In most cases the wall implementation generates both faster and smaller circuits for medium to large sized multipliers In cases where A_width B_width lt A1 the nbw implementation generates a non Booth recoded Wallace tree multiplier For multipliers having products larger than 41 bits such as A_width B_width gt 41 the nbw implementation produces a Booth recoded multiplier identical to the wall implementation Automatically chooses Booth recoded or non Booth recoded architectures depending on constraints This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc_shell t variable dw_prefer_mc_inside must be set to true From the DC 2004 12 release onward the MC architectures are not available by default For more information r
182. hesizable IP Details about inference and instantiation in VHDL and Verilog are in the following directory SYNOPS YS dw examples Synthesizing DesignWare Building Block IP in DC FPGA DC FPGA automatically selects the best implementation for combinational DesignWare Building Block IP You can also force DC FPGA to select the implementation of your choice either by adding Synopsys Compiler directives or by using the following commands dc_shell gt set dont use standard sldb DW01 add rpl dc_shell gt set implementation clf add 68 g m wo lt m gt D 2 N D 2 D 5 Simulating DesignWare Building Block IP Synopsys VCS simulator uses the default setup file while simulating DesignWare Building Block IP Use the following options to simulate DesignWare Building Block IP with a Verilog simulator y SSYNOPSYS dw sim ver libext v January 17 2005 Synopsys Inc 35 Chapter 2 DesignWare Library Synthesizable IP DesignWare IP Family Building Block IP in FPGA Compiler II QuickStart The following topics provide the basic information to get started using the DesignWare Building Block IP with FPGA Compiler II Updating FPGA Compiler Il FPGA Compiler II versions 3 2 and later support instantiated DesignWare Building Block IP Install the latest release of FPGA Compiler II to get the best performance as well as access to the latest FPGA technologies FPGA Compiler II customers who are on active maintenance will automa
183. hi pop_af e Interfaces to common hard macro or compiled ASIC pop_full dual port synchronous RAMs test sea Table 1 Pin Description Pin Name Width Direction Function clk_push 1 bit Input Input clock for push interface clk_pop 1 bit Input Input clock for pop interface rst_n 1 bit Input Reset input active low push_req_n 1 bit Input FIFO push request active low pop_req_n 1 bit Input FIFO pop request active low we_n 1 bit Output Write enable output for write port of RAM active low push_empty 1 bit Output FIFO empty output flag synchronous to clk_push active high push_ae l bit Output FIFO almost empty output flag synchronous to clk_push active high determined by push_ae_lvl parameter push_hf l bit Output FIFO half full output flag synchronous to clk_push active high push_af l bit Output FIFO almost full output flag synchronous to clk_push active high determined by push_af_lvl parameter 214 Synopsys Inc January 17 2005 Tit DesignWare IP Family DW _fifoctl s2 sf Synchronous Dual Clock FIFO Controller with Static Flags Table 1 Pin Description Continued Pin Name Width Direction Function push_full l bit Output FIFO full output flag synchronous to clk_push active high push_error 1 bit Output FIFO push error overrun output flag synchronous to clk_push active high pop_empty 1 bit Output FIFO empty output flag synchronous to clk_
184. hronization mode 1 single register synchronization from pop pointer g 2 double register 3 triple register 77 lt pop_sync 1 to3 Pop flag synchronization mode 1 single register synchronization from push pointer 2 2 double register D 3 triple register rst_mode Oor 1 Reset mode v 0 asynchronous reset 1 synchronous reset byte_order Oor 1 Order of bytes or subword within a word Default 0 0 first byte is in most significant bits position 1 first byte is in the least significant bits position Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cl2 Full carry look ahead model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide January 17 2005 Synopsys Inc 209 DesignWare IP Family DW_fifoctl_s1_df DW _fifoctl_s1_df Synchronous Single Clock FIFO Controller with Dynamic Flags e Fully registered synchronous address and flag output ports e All operations execute in a single clock cycle e FIFO empty half full and full flags e FIFO error flag indicating underflow overflow and pointer corruption e Dynamically programmable almost full and almost empty f
185. hronous reset active low count width bit s Output Output count bus tercnt 1 bit Output Output terminal count Table 2 Parameter Description Parameter Legal Range Description width 1 to 50 Word length of counter a The upper bound of the legal range is a guideline to ensure reasonable compile times Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model Design Ware Synopsys Inc January 17 2005 DesignWare IP Family DW03_Ifsr_scnto LFSR Counter with Static Count to Flag E DW03_lfsr_scnto LFSR Counter with Static Count to Flag e Asynchronous reset e Parameterized count to value to indicate when the counter g reaches a specified value N e Parameterized word length E D e High speed area efficient 2 5 p 5 e Terminal count flag Table 1 Pin Description Pin Name Width Direction Function data width bit s Input Input data load 1 bit Input Input load active low cen 1 bit Input Input count enable clk 1 bit Input Clock reset 1 Input Asynchronous reset active low count width bit s Output Output count bus tercnt 1 bit Output Output terminal count Table 2 Parameter Description Parameter Values Function width 2 to 50 Word length of counter count_to 1 to 2Width 2 count_to bus a The upper bound of t
186. ications architecture for minimum CPU e Supports 10 100 Mbps transfer rates intervention e IEEE 802 3 Media Independent Supports programmable interrupt Interface MII RMII and Serial options for different operational Interface conditions e Supports Full and Half duplex e Includes two dual port FIFOs one for operations transmission and one for reception e Optimized for switching routing network interface card and system on chip applications e Power management supports remote wake up LAN and magic packets e Virtual LAN VLAN support e RapidScript utility for fast RMON customization e Generic 32 bit single channel DMA engine e Available with a PVCI or AHB Interface e Available in Verilog e HomePNA 2 0 support with specific HPNA PHYs 335 Synopsys Inc January 17 2005 DesignWare IP Family Og dwcore_ethernet_sub S Synthesizable Ethernet Subsystem Host RX RX IF Engine W F FIFO AHB to VCI V V V V V P 2 Bridge C C C C C Ethernet H Optional MAC Y used only for AHB Host TX TX Buffer I F Engine I F Control Host Bus AHB DMA Controller Transaction Layer Ethernet MAC Subsystem The dwcore_ethernet_sub data sheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_ethernet_sub pdf 010 MA January 17
187. idth o 8B 10B encoding optional o Data alignment optional O OOB detection generation optional 010 MA January 17 2005 Synopsys Inc 370 DesignWare IP Family dwc_sata_host On Os Serial ATA Host Rx Clock Tx Clock Domain PHY Rx Domain Data amp Ta A Control In X AHB a Datapath Rx FIFO DS FIEO Slave I F PHY Tx Data Link Tx Datapath Weta Ext DMA Interface 5 INTRQ Link PHY Transport FIS ATA Initialization lt Control Construct SATA Control amp OOB Synch Decompose Registers Link Layer The DesignWare dwc_sata_host data sheet is available at http www synopsys com products designware docs ds c dwc_sata_host pdf 371 Synopsys Inc January 17 2005 C KY dwcore_1394_avlink Synthesizable IEEE 1394 AVLink DesignWare IP Family dwcore_1394_avlink Synthesizable IEEE 1394 AVLink The Synopsys DesignWare IEEE 1394 AVLink intellectual property IP is a set of highly configurable blocks that implements complete 1394 interface functions tailored to support audio visual AV oriented IEC 61883 applications Configured through our RapidScript utility this device can also be optimized to act as a generic 1394 device controller Therefore AVLink can be effectively used in a wide range of applications such as digital still cameras video conferencing cameras printer
188. ients In band and out of band access to configuration space registers and external user application registers with local bus controller e Supports external or internal transmit priority arbiter January 17 2005 DesignWare IP Family Og dwc_pcie_endpoint S PCI Express Endpoint Synthesizable Core e Supports expansion ROM e Hot plug support More information is available at http www synopsys com products designware pciexpress html 010 MA January 17 2005 Synopsys Inc 346 DesignWare IP Family dwc_pcie_rootport PCI Express Root Port Synthesizable Core dwc_pcie_rootport PCI Express Root Port Synthesizable Core The DesignWare Root Port RC PCI Express Core is a synthesizable RC solution that can be configured to address multiple applications ranging from server and desktop systems to mobile devices Other features include the following 347 Compliant with PCI Express 1 0a Specification Modular design base CXPL core with additional support modules Architecture supports x1 x2 x4 x8 and x16 2 5Gbps lane configurations Available in 32 64 or 128 bit datapath widths Implementation supports 125MHz and 250MHz Type 1 configuration space PIPE 8 bit 16 bit support Ultra low transmit and receive latency Configurable retry buffer size Configurable outstanding request support up to 32 lookup entries without RAM beyond 32 entries with RAM Very high accessible bandwidth Lane
189. ignWare IP Family DW _cre_s i Universal Synchronous Clocked CRC Generator Checker Table 2 Parameter Description Parameter Values Description data_width 1 to poly_size Width of data_in and data_out also the number of bits per clock Default 16 z poly_size 2 to 64 Size of the CRC polynomial a Default 16 E crce_cfg 0 to7 CRC initialization and insertion configuration a Default 7 X bit_order 0to3 Bit and byte order configuration o Default 3 3 poly_coefO 1 to 65535 Polynomial coefficients 0 through 15 Default 4129 poly_coefl 0 to 65535 Polynomial coefficients 16 through 31 Default 0 poly_coef2 0 to 65535 Polynomial coefficients 32 through 47 Default 0 poly_coef3 0 to 65535 Polynomial coefficients 48 through 63 Default 0 a The data_width value must be chosen such that poly_size is a multiple of data_width b The poly_coefO0 value must be an odd number since all primitive polynomials include the coefficient 1 which is equivalent to x c CCITT CRC16 polynomial is X 6 ex X5 1 thus poly_coef0 2 25 1 4129 Table 3 Synthesis Implementations Implementation Name Implementation License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc 145 DesignWare IP Family DW_ecc Error Checking and Correction DW ecc Error Checking and Correction e Parameteri
190. il log depth bit s Input Write address bus data_in data_width bit s Input Input data bus data_out data_width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data_width 1 to 256 Width of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width rst_mode Oor 1 Determines if the rst_n input is used 0 rst_n initializes the RAM 1 rst_n is not connected Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare 232 Synopsys Inc January 17 2005 DesignWare IP Family 100111001 RAM DW_ram_r_w_a_lat 01101001 Asynchronous Dual Port RAM Latch Based DW_ram_r_w_a lat Asynchronous Dual Port RAM Latch Based wr_addr rd_addr data_in e Parameterized word depth e Parameterized data width e Asynchronous static memory e Parameterized reset implementation g m wo lt m gt D 2 N D D 5 Table 1 Pin Description Pin Name Width Direction Function rst_n 1 bit Input Reset active low cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low rd_addr ceil log depth bit s Input Read address bus wr_addr ceil log depth bit s Input Write address bus data_in data_width bit s Input Input data bus data_ou
191. ilog source code 364 010 MA DesignWare IP Family Co PCI Bus dwcore_usb2_host 4 Qs Synthesizable USB 2 0 Host Controller UHOST2 Subsystem PCI Controller with AHB VCI PCI to AHB AHB nl VCI VCI N 22 USB Target Bridge Decoder m 52 Device AHB VCI USB 2 0 S Initiator EHCI g Transaction LN S gt qam Host USB Controller Controller bw Sa Device with AHB 5 VCI PCI DER Controller E 7 DA Device with Asynch C x a ontrol 3 7 E FIFO and Status 5 2 Interface Registers E D n ar x O O NI USB 1 1 OHCI gt m m Host Controller I with AHB VCI lt O gt Initiator AHB VCl Target g Transaction Controller AHB 2 USB 1 1 OHCI VCI m Host Controller Arbiter I with AHB VCI a gt The dwcore_usb2_host data sheet is available at 365 http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_usb2_host pdf Synopsys Inc January 17 2005 Co as 5 dwcore_usb2 device Synthesizable USB 2 0 Device Controller DesignWare IP Family dwcore_usb2_device Synthesizable USB 2 0 Device Controller The USB 2 0 Device Controller UDC20 features industry standard interfaces that easily integrate the USB 2 0 transceiver and application logic T
192. imized flexible synthesis model DesignWare csa Carry save array synthesis model DesignWare csmult Delay optimized flexible synthesis DesignWare model wall Booth recoded Wallace tree synthesis DesignWare model pparch Delay optimized flexible Booth Wallace DesignWare apparch Area optimized flexible Booth Wallace DesignWare January 17 2005 Synopsys Inc 83 DesignWare IP Family DW02_mac Multiplier Accumulator a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b This area and delay optimized Booth Wallace architecture is generated using Datapath generator technology DW gensh This is ON by default in Design Compiler flow The DC variable synlib_enable_dpgen must be set to true the default to make use of this Datapath technology 84 Synopsys Inc January 17 2005 DesignWare IP Family DW_minmax Minimum Maximum Value DW_minmax Minimum Maximum Value e Parameterized number of inputs a ee e Parameterized word length iE min_max index e Unsigned and signed two s complement data operation e Dynamically selectable mode minimum or maximum g m wo lt m gt D 2 N D 2 D 5 e Additional output gives an index of the minimum or maximum input
193. imulate all device bus cycles FlexModels are a type of BFM in the SmartModel Library which you can control using Verilog VHDL Vera or C For some devices more than one type of model may be available but these are exceptions not the general rule For detailed information about a specific SmartModel including FlexModels refer to the model s datasheet For an overview of the FlexModels see DesignWare FlexModels on page 322 January 17 2005 Synopsys Inc 324 SmartModel Timing Definitions DesignWare IP Family SmartModel Timing Definitions All SmartModels have at least one timing version To see what timing versions are available for a particular model use the Browser tool to display a list of timing versions for that model If you need a timing version that is not supplied with the library or if you want to back annotate customized delays into the model s simulation you can create a custom timing version as described in User Defined Timing in the Smartmodel Library User s Manual Specific Model Information SmartModel datasheets provide specific user information about each model in the library The model datasheets supplement but do not duplicate the manufacturer s datasheets for the hardware parts In general the model datasheets describe Supported hardware IP and devices Bibliographic sources used to develop the model specific vendor databooks or datasheets How to configure and operate the m
194. ines data_in and coef_in values as two s complement or unsigned If low the data_in and coef_in values are unsigned if high they are two s complement 156 Synopsys Inc January 17 2005 DesignWare IP Family DW_fir High Speed Digital FIR Filter Table 1 Pin Description Pin Name Width Direction Function data_in data_in_width Input Input data bit s Z coef_in coef_width Input Serial coefficient coef_shift_en port This port is m bit s enabled when the coef_shift_en pin is set high A rising 2 edge of clk loads the coefficient data at coef_in into the gt first internal coefficient register and shifts all other coefficients in the internal registers one location to the N right z init_acc_val data_out_width Input Initial accumulated sum value If unused this pin is 5 bit s tied to low 000 000 that is when the FIR filter is implemented with a single DW_fir component When several DW_fir components are cascaded the data_out of the previous stage is connected to the init_acc_val port of the next data_out data_out_width Output Accumulated sum of products of the FIR filter bit s coef_out coef_width Output Serial coefficient output port When the coef_shift_en bit s pin is high and coefficients are being loaded serially the coefficient data in the last internal coefficient register is output through the coef_out port Table 2 Parameter
195. ion License Feature Required rpl Ripple Carry synthesis model DesignWare cl2 Full Carry lookahead model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 216 Synopsys Inc January 17 2005 DesignWare IP Family Memory Registers Memory Registers This section documents the various memory registers found in the library of DesignWare Building Block IP g m wn lt S gt D o N D gt D 5 January 17 2005 Synopsys Inc 217 DesignWare IP Family DW03_pipe_reg Pipeline Register DW03_pipe_reg Pipeline Register 218 e Parameterized data width and depth Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data bus clk 1 bit Input Clock B width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description depth 21 Depth of registers width 21 Width of A and B buses Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare Synopsys Inc January 17 2005 DesignWare IP Family DW03
196. ion Name Function License Feature Required wall Wallace tree synthesis model DesignWare mearch MC inside DW Wallace tree DesignWare pparch Delay optimized flexible Booth Wallace DesignWare apparch Area optimized flexible Booth Wallace DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b Automatically chooses Booth recoding or non Booth recoding architecture depending on constraints January 17 2005 Synopsys Inc 111 DesignWare IP Family DW_square Integer Squarer c This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc_shell t variable dw_prefer_mc_inside must be set to true From the DC 2004 12 release onward the MC architectures are not available by default For more information refer to the DesignWare Building Block IP Users Guide d These area and delay optimized Booth Wallace architectures are generated using Datapath generator technology DW gensh This is ON by default in Design Compiler flow The DC variable synlib_enable_dpgen must be set to tr
197. ipe Stallable Pipelined multiplier Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset active low not used if parameter rst_mode 0 en 1 bit Input Load enable used only if parameter stall_mode 1 0 stall 1 load tc 1 bit Input Two s complement control 0 unsigned 1 signed a a_width bit s Input Multiplier b b_width bit s Input Multiplicand product a_width b_width bit s Output Product a x b January 17 2005 Synopsys Inc 99 g m wn lt S gt D o N D D 5 DesignWare IP Family DW_mult_pipe Stallable Pipelined multiplier Table 2 Parameter Description Parameter Values Description a_width 21 Word length of a Default None b_width gt 1 Word length of b Default None num_stages 2 Number of pipeline stages Default 2 stall_mode Oor 1 Stall mode Default 1 0 non stallable 1 stallable rst mode 0to2 Reset mode Default 1 0 no reset 1 asynchronous reset 2 synchronous reset Table 3 Synthesis Implementations Implementation Name Implementation License Feature Required str Pipelined str synthesis model DesignWare a One of csa wall or nbw implementation is selected based on the constraints of the design 100 Synopsys Inc January 17 2005 DesignWare IP Family DW02_
198. irectory where your product must be installed Vertical rule Choice among alternatives as in the following syntax example effort_level low medium high Square brackets Enclose optional parameters pinli pin2 pinwN In this example you must enter at least one pin name pin but others are optional pin2 pinN TopMenu gt SubMenu Pulldown menu paths such as File gt Save As Synopsys Common Licensing SCL You can find general SCL information on the Web at http www synopsys com keys 16 Synopsys Inc January 17 2005 DesignWare IP Family Preface Getting Help If you have a question about using Synopsys products please consult product documentation that is installed on your network or located at the root level of your Synopsys product CD ROM if available You can also access documentation for DesignWare products on the Web e Product documentation for many DesignWare products http www synopsys com products designware docs e Datasheets for individual DesignWare IP components located using Search for IP http www synopsys com designware You can also contact the Synopsys Support Center in the following ways Open a call to your local support center using this page http www synopsys com support support html e Send an e mail message to support_center synopsys com e Telephone your local support center o United States Call 1 800 245 8005 from
199. ired rpl Ripple carry synthesis model none bk Brent Kung synthesis model DesignWare cla Carry look ahead synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 64 Synopsys Inc January 17 2005 DesignWare IP Family DW01_cmp6 6 Function Comparator DW01_cmp6 6 Function Comparator e Parameterized word length e Unsigned and signed two s complement data comparison g m wn lt S gt D o N D D 5 Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data B width bit s Input Input data TC 1 bit Input Two s complement control 0 unsigned 1 signed LT 1 bit Output Less than output condition GT 1 bit Output Greater than output condition EQ 1 bit Output Equal output condition LE 1 bit Output Less than or equal output condition GE 1 bit Output Greater than or equal output condition NE 1 bit Output Not equal output condition Table 2 Parameter Description Parameter Values Description width 21 Word length of A and B Table 3 Synthesis Implementations Implementation Name Function License Feature Required
200. is available at http www synopsys com products designware docs 268 Synopsys Inc January 17 2005 DesignWare IP Family DW_ahb_eh2h Enhanced AHB to AHB Bridge DW_ahb eh2h Enhanced AHB to AHB Bridge Clocks AHB Master interface e Asynchronous or synchronous clocks e Data width 32 64 128 or 256 bits z any clock ratio e Address width 32 or 64 bits in e Fully registered outputs e Big or little endian E e Optional pipeline stages to reduce e Lock and bus request generation a logic levels on bus inputs e SINGLE INCR burst type generation X for writes D AHB Slave interface e Any burst type generation for reads v e Data width 32 64 128 or 256 bits e Downsizing of wider transfers Address width 32 or 64 bits Write operations e Big or little endian e Zero or two wait states OKAY e Configurable depth write buffer response e Buffered writes always HPROT is e ERROR response don t care e No RETRY response e SPLIT response on write buffer full e SPLIT response e Maximum of two wait states on e HSPLIT generation non sequential access e Handling of multiple outstanding split e Zero wait states full bandwidth on transactions sequential access e Multiple HSELs e Zero BUSY cycles full bandwidth e HREADY low alternative to SPLIT secondary burst generation response operation mode poner op Read operations SONWATE MENACE Configurable depth read buffer Pre fetched reads Non prefetched reads SPLIT response on no
201. it Output FIFO half full output flag synchronous to clk_pop active high pop_af 1 bit Output FIFO almost full output flag synchronous to clk_pop active high determined by pop_af_lvl parameter January 17 2005 Synopsys Inc 207 DesignWare P Family DW_asymfifoctl_s2_sf TL Asymmetric Synchronous Dual Clock FIFO Controller with Static Flags Table 1 Pin Description Continued Pin Name Width Direction Function pop_full 1 bit Output FIFO s RAM full output flag excluding the input buffer of FIFO controller for case data_in_width lt data_out_width synchronous to clk_pop active high pop_error 1 bit Output FIFO pop error underrun output flag synchronous to clk_pop active high wr_data max data_in_width Output FIFO controller output data to RAM data_out_width bit s wr_addr ceil logs depth bit s Output Address output to write port of RAM rd_addr ceil logs depth bit s Output Address output to read port of RAM data_out data_out_width bit s Output FIFO data to pop a As perceived by the push interface b As perceived by the pop interface Table 2 Parameter Description Parameter Values Description data_in_width 1 to 256 Width of the data_in bus data_in_width must be in an integer multiple relationship with data_out_width That is either data_in_width K x data_out_width or data_out_wi
202. it Input Clock PRODUCT A_width B_width bit s Output Product A x B Table 2 Parameter Description Parameter Values Description A_width 21 Word length of A B_width 2 1 For csa architecture A_width B_width 48 Word length of B Table 3 Synthesis Implementations Implementation Name Function csa Carry save array synthesis model DesignWare str Booth recoded Wallace tree synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 96 Synopsys Inc January 17 2005 License Feature Required DesignWare IP Family DW02_mult_6_stage Six Stage Pipelined Multiplier b The csa implementation is only valid when the sum of A_width and B_width lt 8 bits as it has no area benefit beyond 48 bits g m wo lt m gt D 2 N D D 5 January 17 2005 Synopsys Inc 97 DesignWare IP Family DW_mult_dx Duplex Multiplier DW_mult_dx Duplex Multiplier e Selectable single full width multiplier simplex or two parallel smaller width multiplier duplex operations e Area and delay are similar to those of the DW02_mult wallace architecture e Selectable number system unsigned or two s complement e
203. itchport PCI Express Switch Port Synthesizable Core The DesignWare Switch Port SW PCI Express Core is a synthesizable SW solution that can be configured to address multiple applications ranging from server and desktop systems to mobile devices Other features include the following Compliant with PCI Express 1 0a Specification Modular Design base CXPL core with additional support modules Architecture supports x1 x2 x4 x8 x16 2 5 Gbps lane configurations Available in 32 64 or 128 bit datapath widths 125MHz or 250MHz operation Type 1 configuration space register support e PIPE 8 bit 16 bit support Configurable upstream and downstream port e Ultra low transmit and receive latency e Configurable retry buffer size Bypass cut through and store forward configurable transmit and receive queue Configurable multi single transmit and receive queue structure More information is available at 349 Pre fetch memory space support Transaction filtering and routing look up Full PCI bridge to bridge support Configurable VC TC mapping Lane reversal and polarity inversion TX RX Configurable multi VCs multi traffic class support Packet sizes configurable maximum payload size 128B to 4KB and Max request size up to 4KB Complete Switch Port upstream or downstream link training LTSSM Full PCI PM software and ASPM support Full Advanced PCI Express Error Reporting Full PCI Express message forwa
204. izable IEEE 1394 AVLink Isochronous TX VCIF TX_AV IBUF ITX_VCIF TXIP gt Isochronous ITF RX VCIF RX_IIP _ gt IRX_VCIF 4 _IRF_ RX_AV a Asynchronous TX VCIF ABUF gt ATX_VCIF gt gt Asynchronous tst lt CSs CS ATX_Req RX VCIF gt lt ____ ARX_VCIF ATX_Res Host BO ARX VCIF ____ HOST_VCIF e gt Isochronous Control i gt The dweore_1394_avlink data sheet is available at AV1394Link Link Layer Core TX RET CRC PHY Monitor RX i y Control and Status Unit pegs et CSRs Control PHY Link IF http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_1394_avlink pdf 373 Synopsys Inc January 17 2005 C KN dwcore_1394_cphy Synthesizable IEEE 1394 Cable PHY DesignWare IP Family dwcore_1394_cphy Synthesizable IEEE 1394 Cable PHY The Synopsys industry proven DesignWare 1394 Cable Physical Layer CPHY enables devices to interface with the 1394 serial bus The 1394 CPHY is a synthesizable RTL design that provides all the necessary features to implement the complete IEEE 1394a specification for the digital portion of the cable PHY CPHY can be combined with an analog PHY and used in a stand alone ASIC or it can be integrated into an
205. k e Command set control e Robust command set control g m S O o e gt 5 sin a c sout sout c gt sin cts_n a l rts_n rts_n ll cts_n l DW_apb_uart sio_txrx_vmt or DUT lic a ieee gpo n Se gpi n gt sclk presetn T i g rst n C sio_monitor_vmt The DesignWare SIO Verification IP Databook is available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 318 DesignWare IP Family USB On The Go Models Host Device and Monitor USB On The Go Models Host Device and Monitor USB Host Model usb_host_vmt USB Device Model e 1 1 2 0 OTG UTMI UTMIG and usb_device_vmt ULPI e 1 1 2 0 OTG UTMI UTMI and e High full and low speeds ULPI e Operation at packet and transaction e Configures to Non OTG SRP Host levels only SRP Peripheral only Dual Role e USB signaling with programmable OTG A Dual Role OTG B timers e Operation at packet and transaction e Suspend resume reset signaling levels e Error generation capabilities e High full and low speeds e Programmable inter packet and e Programmable response for endpoints end to end delays e Packet error injection detection e Suspend resume reset signaling USB Monitor Model e Supports SRP and HNP usb_monitor_vmt e 1 1 2 0 OTG UTMI UTMI and ULPI Protocol checking Transaction logging Coverage monitoring Supports S
206. l Slave with without lock control Layer release scheme Baseline arbitration scheme O O CO 0 0O External arbitration priority control DW_ahb Layer 1 DW_ahb 4 lt gt Layer N N DW_ahb_icm4 gt 7 DW_ahb Slave The DesignWare DW_ahb_icm Databook is available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 271 DesignWare IP Family DW_ahb_ictl AHB Interrupt Controller DW_ahb_ictl AHB Interrupt Controller e 2 to 64 IRQ normal interrupt sources e to 8 FIQ fast interrupt sources optional e Vectored interrupts optional e Software interrupts e Component parameters for configurable software driver support e AMBA Compliance Tool ACT certification Priority filtering optional Masking Scan mode optional Programmable interrupt priorities after configuration Encoded parameters e Note Does not support split transfers DW_ahb_ictl Generation IRQ Interrupt Registers Generation FIQ Masking Vector Generation amp The DesignWare DW_ahb_ictl Databook is available at http www synopsys com products designware docs 272 Synopsys Inc January 17 2005 DW_apb Advanced Peripheral Bus e Compliance with the AMBA Specification Rev 2 0 APB Bridge and APB bus functionality incorporate
207. l output active high almost_full 1 bit Output FIFO almost full output active high asserted when FIFO level depth af_level full 1 bit Output FIFO full output active high ram_full 1 bit Output RAM full output active high error 1 bit Output FIFO error output active high part_wd 1 bit Output Partial word active high for data_in_width lt data_out_width only otherwise tied low data_out data_out_width bit s Output FIFO data to pop 186 Synopsys Inc January 17 2005 DesignWare IP Family vine DW_asymfifo_s1_sf Asymmetric I O Synchronous Single Clock FIFO with Static Flags Table 2 Parameter Description Parameter Values Description data_in_width 1 to 256 Width of the data_in bus data_in_width must be in an integer multiple relationship with data_out_width That is either data_in_width K x data_out_width or data_out_width K x data_in_width where K is an integer data_out_width 1 to 256 Width of the data_out bus data_out_width must be in an integer multiple relationship with data_in_width That is either data_in_width K x data_out_width or data_out_width K x data_in_width where K is an integer g m wo lt m gt D 2 N D D 5 depth 2 to 256 Number of memory elements used in the FIFO addr_width ceil logz depth ae_level 1 to depth 1 Almost empty level the number of words in the FIFO at or below which the almost_empty flag is active
208. lags e Parameterized word depth wr_addr push_req_n pop_req_n weet rd_addr ae_level af_thresh full almost_full half_full almost_empty empty error diag_n rst_n e Parameterized reset mode synchronous or asynchronous e Interfaces to common hard macro or compiled ASIC dual port synchronous RAMs Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 synchronous if rst_mode 1 push_req_n 1 bit Input FIFO push request active low pop_req_n 1 bit Input FIFO pop request active low diag_n 1 bit Input Diagnostic control for err_mode 0 NC for other err_mode values active low ae_level ceil logs depth bit s Input Almost empty level the number of words in the FIFO at or below which the almost_empty flag is active 210 Synopsys Inc January 17 2005 Tit DesignWare IP Family DW_fifoctl_s1_df Table 1 Pin Description Pin Name Width Direction Function af_thresh ceil log depth bit s Input Almost full threshold the number of words stored in the FIFO at or above which the almost_full flag is active we_n 1 bit Output Write enable output for write port of RAM active low empty 1 bit Output FIFO empty output active high almost_empty bit Output FIFO almost empty output active high g m 7 lt
209. lexers inside the memories or user specified multiplexers Io 1O Can Default sequence or run time selection of individual test Improved test execution time through reduced memory read write cycles each access to synchronous memory occurs in one clock cycle Configuration of Mode Register reset value to provide easy power up tests Higher speed clock frequency e Flexible configuration for embedded Supported Memories MUX block providing a better interface to memory control signals with different widths and polarities e Error Diagnostics e Pause on first and subsequent failures e mode serial debugging e Failing address and data may be scanned out for examination Synchronous and asynchronous SRAM Asymmetrical pipelining support up to four stages Support for 32 memories per BIST controller Highly configurable memory interface to suit most types of memories e Quick debug mode continue on Supported Memory Configurations failures mode failing addresses not J recorded e Parallel debug port to observe the failing memory data bits BIST Tests e User choice of March LR 14n March C 10n and MATS 6n e Custom user defined patterns option e Optional SRAM retention test Sn delay auto pause mechanism e Selection of background and complement background data patterns 294 Synopsys Inc True at speed testing of memories in parallel Memory array test via single port and multi
210. ll operations execute in a single clock cycle e D flip flop based memory array for high testability e Parameterized reset mode synchronous or asynchronous Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 or 2 synchronous if rst_mode 1 or 3 push_req_n 1 bit Input Stack push request active low pop_req_n 1 bit Input Stack pop request active low data_in data_width bit s Input Stack push data empty 1 bit Output Stack empty flag active high full 1 bit Output Stack full flag active high error 1 bit Output Stack error output active high data_out data_width bit s Output Stack pop data 240 Synopsys Inc January 17 2005 DesignWare IP Family DW_stack Synchronous Single Clock Stack Table 2 Parameter Description Parameter Values Description width 1 to 256 Width of data_in and data_out buses Default None Z depth 2 to 256 Depth in words of memory array m wo Default None lt err_mode Oor 1 Error mode a Default 0 0 underflow overflow error hold until reset N 1 underflow overflow error hold until next clock z rst_mode 0 to3 Reset mode 5 Default 0 0 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding memory 3 synchronous
211. lt 0 sync_mode Oorl Determines whether the bypass device identification and Default 0 instruction registers are synchronous with respect to tck 0 asynchronous synchronous Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare or Test EEE STD 1149 1 246 Synopsys Inc January 17 2005 DesignWare IP Family DW_tap_uc TAP Controller with USERCODE support DW_tap_uc TAP Controller with USERCODE support e IEEE Standard 1149 1 compliant tek clock_dr tms shift_dr tdi update_dr so sync_update_dr e Synchronous or asynchronous registers with respect to tck e Provides interface to supports the standard TEEE 1149 1 and optional instructions bypass_sel tdo sentinel_val tdo_en device_id_sel g m wo lt m gt D 2 N D 2 D 5 e Optional use of device identification register and IDCODE instruction and support of user_code_sel tap_state USERCODE instruction user_code_val e User defined opcode for IDCODE eee eee f instructions e Parameterized instruction register width part_num F part_num_sel e External interface to program device mnfr_id identification register mnfr_id_sel trst_n Table 1 Pin Description Pin Name Width Direction Function tck 1 bit Input Test clock trst_n 1 bit Input Test reset
212. ly C Og dwcore_usb2_host S Synthesizable USB 2 0 Host Controller dwcore_usb2_host Synthesizable USB 2 0 Host Controller The Synopsys DesignWare USB Host Controller UHOST2 is a set of synthesizable building blocks that ASIC FPGA designers use to implement a complete USB 2 0 host for 480 Mbps operation The UHOST2 can be customized and optimized as a stand alone host chip or as an integrated ASIC for applications such as game consoles set top boxes PCs PDAs and telecommunications equipment In addition the design can be easily processed in most technologies and can be easily bridged to any industry standard bus and includes both the PCI and ARM AHB interfaces The application interface screens USB host controller design complexities making it easy to integrate the UHOST2 device to customer target applications Other features include the following e USB 2 0 EHCI and OHCI e Simple application interface facilitates specification compliant bridging the controller to other system buses e High speed 480 Mbps full speed January 17 2005 12 Mbps and low speed 1 5 Mbps capability e Configurable root hub supporting up to 15 downstream ports with 1 1 or 2 0 speed capability e Choice of micro frame or frame caching of data structures EHCI Synopsys Inc PCI and AHB interfaces available Approximately 130K gates for a typical two port implementation Compatible with the Synopsys High Speed Certified USB 2 0 PHY Ver
213. m gt 0 2 N D D 5 half _full 1 bit Output FIFO half full output active high almost_full 1 bit Output FIFO almost full output active high full 1 bit Output FIFO full output active high error 1 bit Output FIFO error output active high wr_addr ceil log depth bit s Output Address output to write port of RAM rd_addr ceil log depth bit s Output Address output to read port of RAM Table 2 Parameter Description Parameter Values Description depth 2 to 224 Number of memory elements used in FIFO used to size the address ports err_mode 0 to 2 Error mode Default 0 0 underflow overflow and pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode Oor 1 Reset mode Default 0 0 asynchronous reset 1 synchronous reset Table 3 Synthesis Implementations Implementation Name Function License Feature Required rt Synthesis Model DesignWare a The implementation rtl replaces the obsolete implementations rpl c11 and c12 Information messages listing implementation replacements SYNDB 37 may be generated by DC at compile time Existing designs that specify an obsolete implementation rpl c11 and cl2 will automatically have that implementation replaced by the new superseding implementation rtl noted by an information message
214. meout FIFO Detection Control Character MEM_MODE Timeout THA Level Syne Baud Clock Module Generator RX Character FIFO pe Timeout er sout Control Clear MEM_MODE Data Sync IX RBR Module x sir_out_n Transmit f Data Sync a all sin EP r External or External or Module RX Internal Internal sir_in RX Memory TX Memory Receive Data Sync aos Serial Interface Parameter pelk Selected sclk Cross Clock opi Taek Lockup Latches The DesignWare DW_apb_uart Databook is available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 283 DesignWare IP Family DW_ahb_h2h AHB to AHB Bridge DW_ahb_h2h AHB to AHB Bridge System Level Configurable asynchronous or synchronous clocks any clock ratio Four clocking modes for synchronous clock configurations two with and two without clock enables Low gate count implementation minimum configuration below 2K gates Sub optimal throughput performance non buffered architecture High clock speed operations fully registered outputs operating frequency more than 300 MHz AHB Master Interface Configurable AHB address width 32 or 64 bits Configurable AHB data width 32 64 128 or 256 bits Configurable endianness HLOCK generation HBUSREQ generation HTRANS generation of IDLE or NSEQ bus cycles Non pipelined transfers address phase always followed by IDLE cycles until data phase completes HBURST fi
215. meter Description Parameter Values Description a_width gt 2 Word length of a Default None b_width gt 2 lt a_width Word length of b Default None tc_mode Oor 1 Two complement control Default 0 rem_mode Oor 1 Remainder output control Default 1 January 17 2005 Synopsys Inc 73 DesignWare IP Family DW_div Combinational Divider Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Restoring ripple carry synthesis model DesignWare cla Restoring carry look ahead synthesis DesignWare model cla2 Restoring carry look ahead 2 way DesignWare overlapped synthesis model a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 74 Synopsys Inc January 17 2005 DW_div_p ipe Stallable Pipelined Divider e Parameterized word length e Parameterized unsigned and signed data operation e Parameterized number of pipeline stages e Parameterized stall mode stallable or non stallable e Parameterized reset mode no reset asynchronous or synchronous reset e Automatic pipeline retiming DesignWare IP Family DW_div_pipe Stallable Pipelined Divider Table 1 Pin Description quotient remainder divide_by_0
216. mode1 data_out a tck mode2 99 E gt e Supports the standard instructions EXTEST INTEST shift_dr Q SAMPLE PRELOAD and BYPASS output_data D e Supports the optional instructions RUNBIST CLAMP and ei HIGHZ update_en gt update_clk gt capture_clk Table 1 Pin Description Pin Name Width Direction Function capture_clk 1 bit Input Clocks data into the capture stage update_clk 1 bit Input Clocks data into the update stage capture_en 1 bit Input Enable for data clocked into the capture stage active low update_en 1 bit Input Enable for data clocked into the update stage active high shift_dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo model 1 bit Input Determines whether data_out is controlled by the boundary scan cell or by the data_in signal mode2 1 bit Input Determines whether data_out is controlled by the boundary scan cell or by the data_in signal si l bit Input Serial path from the previous boundary scan cell pin_input l bit Input IC system input pin output_data 1bit Input IC output logic signal data_out l bit Output Output data SO 1 bit Output Serial path to the next boundary scan cell Table 2 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare or Test IEEE STD 1149 1 January 17
217. mplementation Name Function License Feature Required str Synthesis model DesignWare 222 Synopsys Inc January 17 2005 DesignWare IP Family 100111001 RAM Memory Synchronous RAMs Memory Synchronous RAMs This section documents the various DesignWare Building Block IP memory synchronous RAMs g m wo lt m gt D 2 N D 2 D 5 January 17 2005 Synopsys Inc 223 DesignWare IP Family 100111001 DW_ram_r_w_s dff Synchronous Write Port Asynchronous Read Port RAM Flip Flop Based RAN DW_ram_r_w_s dff Synchronous Write Port Asynchronous Read Port RAM Flip Flop Based rd_addr wr_addr e Parameterized word depth e Parameterized data width asain e Synchronous static memory data_out j e Parameterized reset mode synchronous or asynchronous cs_n e Inferable from Behavioral Compiler wey gt clk rst_n e High testability using DFT Compiler Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock rst_n 1 bit Input Reset active low cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low rd_addr ceil log depth bit s Input Read address bus wr_addr ceil log depth bit s Input Write address bus data_in data_width bit s Input Input data bus data_out data_width bit s Output Output data bus Table 2 Parameter Des
218. n lt S gt D o N D gt D 5 Table 1 Pin Description Pin Name Width Direction Function rst_n 1 bit Input Reset active low cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low test_mode 1 bit Input Enables test_clk test_clk 1 bit Input Test clock to capture data during test_mode rw_addr ceil log depth bit s Input Address bus data_in data_width bit s Input Input data bus data_out data_width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data_width 1 to 256 Width of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width rst_mode Oor 1 Determines if the rst_n input is used 0 rst_n initializes the RAM 1 rst_n is not connected Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc 237 DesignWare IP Family 100111001 RAN DW_ram_rw_a_lat Asynchronous Single Port RAM Latch Based DW_ram_rw_a lat Asynchronous Single Port RAM Latch Based e Parameterized word depth rw_addr e Parameterized data width data_in data_out e Asynchronous static memory cs_n e Parameterized reset implementation wr_n rst_n Table 1 Pin Description Pin Name Width Di
219. n width 22 Word length of a tc_mode Oorl Two s complement control Default 0 0 unsigned 1 signed Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Restoring ripple carry synthesis model DesignWare cla Restoring carry lookahead synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 114 Synopsys Inc January 17 2005 DesignWare IP Family DW_sqrt_pipe Stallable Pipelined square root DW_sart_pipe Stallable Pipelined square root e Parameterized word length e Unsigned and signed two s complement data operation e Parameterized number of pipeline stages e Parameterized stall mode stallable or non stallable e Parameterized reset mode no reset asynchronous or synchronous reset g m wo lt m gt D 2 N D 2 D 5 e Automatic pipeline retiming Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset active low not used if parameter rst_mode 0 en 1 bit Input Load enable used only if parameter stall_mode 1 0 stall 1 load a width bit s Input Radicand root width 1 2 bit s Output Square root
220. n area c This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc_shell variable dw_prefer_mc_inside must be set to true From the DC 2004 12 release onward the MC architectures are not available by default For more information refer to the DesignWare Building Block IP Users Guide d This delay optimized parallel prefix architecture is generated using Datapath generator technology DW gensh This is ON by default in the Design Compiler flow The DC variable synlib_enable_dpgen must be set to true the default to make use of this Datapath technology 118 Synopsys Inc January 17 2005 DesignWare IP Family DW02_sum Vector Adder DW02_sum Vector Adder e Parameterized number of inputs INPUT SUM g e Parameterized word length a e Multiple synthesis implementations N Table 1 Pin Description gt Pin Name Width Direction Function 3 INPUT num_inputs X input_width bit s Input Concatenated input data SUM input_width bit s Output Sum Table 2 Parameter Description Parameter Values Description num_inputs 21 Number of inputs input_width 21 Word length of inputs and sum Table 3 Synthesis Implementations Impl
221. n high end ASICs The functions mainly deal with arithmetic operations in floating point format format conversions and comparison functions The main features of this library are as follows The format of the floating point numbers that determines the precision of the number that it represents is parametrizable The user can select the precision based on either IEEE single or double precision or custom format defined by you The parameter range for exponents is from 3 to 31 bits The parameter range for the significand or the fractional part of the floating point number is from 2 bits to 256 bits The parameter range for integers is from 3 to 512 bits Accuracy conforms to the definitions in the IEEE 754 Floating Point standard Download instructions for the Floating Point components can be found at the following web address 122 http www synopsys com products designware dwest Synopsys Inc January 17 2005 DesignWare IP Family DW_i2flt_fp 2 4979 x 105 Integer to Floating Point Converter DW_i2flt_fp Integer to Floating Point Converter Module Compiler Only e The precision format is parameterizable for either IEEE single double precision or a user defined custom format e Exponents can range from 3 to 31 bits A I2FLT e Significand or fractional part of the floating point number can STATUS range from 2 to 256 bits RND e Accuracy conforms to IEEE 754 Floating Point standard Table 1 Pin Description
222. n sequential non yet prefetched access e Input sstall pin to qualify an address Zero wait states full bandwidth on phase for HREADY low operation prefetched read data mode e Output sflush pin to monitor the flushing operation on the read buffer e Interrupt signal on write errors e Interrupt status clear registers Sideband signals January 17 2005 Synopsys Inc 269 DesignWare IP Family DW_ahb_eh2h Enhanced AHB to AHB Bridge Write Buffer Primary AHB Secondary AHB Read Buffer sHCLK mHCLK The DesignWare DW_ahb_eh2h Databook is available at http www synopsys com products designware docs 270 Synopsys Inc January 17 2005 DW_ahb_ icm AHB Multi layer Interconnection Matrix e Layer arbitration and master multiplexing e Input stage address and control holding registers for each layer e Mapping of slave response onto correct layer e Returning of splits onto the correct layer e Common clock and reset shared amongst all layers DesignWare IP Family DW_ahb_icm AHB Multi layer Interconnection Matrix e User defined parameters o AMBA Lite o AHB address bus width same width on all layers o AHB data bus width same width on each layer g m wo lt m gt 0 o N D D 5 o AHB master layers up to 4 o Split or non split capable slave o Slave with without multiple select lines o Slave with without protection control Slave with without burst contro
223. n the FIFO at or above which the almost_full flag is active data_in width bit s Input FIFO data to push empty 1 bit Output FIFO empty output active high almost_empty 1 bit Output FIFO almost empty output active high half_full 1 bit Output FIFO half full output active high January 17 2005 Synopsys Inc 193 DesignWare IP Family DW_fifo_s1_df Synchronous Single Clock FIFO with Dynamic Flags Table 1 Pin Description Continued Pin Name Width Direction Function almost_full 1 bit Output FIFO almost full output active high full 1 bit Output FIFO full output active high error 1 bit Output FIFO error output active high data_out width bit s Output FIFO data to pop Table 2 Parameter Description Parameter Values Description width 1 to 256 Width of data_in and data_out buses Default 8 depth 2 to 256 Number of memory elements used in FIFO Default 4 err_mode 0 to 2 Error mode Default 0 0 underflow overflow and pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst mode 0to3 Reset mode Default 0 0 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding memory 3 synchronous reset excluding memory Table 3 Synthesis Implementations Implementation Name Function rtl Synthesi
224. nal for the output enable output_data 1 bit Input IC output logic signal ic_input 1 bit Output IC input logic signal data_out 1 bit Output Output data SO 1 bit Output Serial path to the next boundary scan cell January 17 2005 Synopsys Inc 255 DesignWare IP Family DW_bc_7 Boundary Scan Cell Type BC_7 Table 2 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare or Test EEE STD 1149 1 256 Synopsys Inc January 17 2005 DW bc 8 Boundary Scan Cell Type BC_8 Last Revised Release DWF_0212 e IEEE Standard 1149 1 2001 compliant e Synchronous or asynchronous scan cells with respect to tck e Supports the standard instructions EXTEST SAMPLE PRELOAD and BYPASS e Supports the optional instructions RUNBIST CLAMP and DesignWare IP Family DW_bc_8 Boundary Scan Cell Type BC_8 pin_input si ic_input data_out so mode shift_dr control_out output_data o capture_en g m wo lt m gt D 2 N D 2 D 5 HIGHZ update_en update_clk gt capture_clk Table 1 Pin Description Pin Name Width Direction Function capture_clk 1 bit Input Clocks data into the capture stage update_clk 1 bit Input Clocks data into the update stage capture_en 1 bit Input Enable for data clocked into the capture stage active low update_en 1 bit Inp
225. nc 57 DesignWare IP Family DW_addsub_dx Duplex Adder Subtractor with Saturation and Rounding Table 1 Pin Description Continued Pin Name Width Direction Function col 1 bit Output Part1 carry output co2 1 bit Output Full width or part2 carry output Table 2 Parameter Description Parameter Values Description width gt 4 Word width of a b and sum pl_width 2 to width2 Word width of part1 of duplex Add Sub Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple Carry Synthesis Model DesignWare rpcs Ripple Carry Select Synthesis Model DesignWare csm Conditional Sum Synthesis Model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 58 Synopsys Inc January 17 2005 DesignWare IP Family DW01_ash Arithmetic Shifter DW01_ash Arithmetic Shifter e Parameterized word length A z e Parameterized shift coefficient width DATA TC B a lt e Inferable using a function call SH z D o nii i Table 1 Pin Description Pin Name Width Direction Function A A_width bit s Input Input
226. nd manuals mentioned in the following chapters Manual Overview This manual contains the following chapters Preface Chapter 1 Overview Chapter 2 DesignWare Library Synthesizable IP Chapter 3 DesignWare Library Verification IP Chapter 5 DesignWare Cores Chapter 6 DesignWare Star IP January 17 2005 Describes the manual and typographical conventions and symbols tells how to get technical assistance Contains an overview and general description of the DesignWare Library product offering Contains a brief description of each DesignWare Library Synthesizable IP Describes the available DesignWare Library verification models Contains a brief description of each DesignWare Core Contains a brief description of each DesignWare Star IP core Synopsys Inc 15 Preface DesignWare IP Family Typographical and Symbol Conventions Table 1 lists the conventions that are used throughout this document Table 1 Documentation Conventions Convention Description and Example Represents the UNIX prompt Bold User input text entered by the user ed LMC HOME hdl Monospace System generated text prompts messages files reports No Mismatches 66 Vectors processed 66 Possible Italic or Italic Variables for which you supply a specific value As a command line example setenv LMC HOME prod dir In body text In the previous example prod_dir is the d
227. nds until the event happens Events can be individual model messages groups of messages or message types or boolean combinations Triggering events can be enabled or disabled at any time Some VMT models support additional features Consult model feature lists in this quick reference or model datasheets for supported features e Multiple command channels Simultaneously send and receive data full duplex operation e Constrained random test Configure testbenches to execute transactions transaction sequences or transaction choice sets weighted by any configurable parameter Provide file or random payloads for those transactions January 17 2005 Synopsys Inc 320 DesignWare IP Family The following list identifies VMT models supporting major verification IP solutions 321 DesignWare AMBA Advanced High Performance Bus AHB models ahb_act_monitor_vmt ahb_bus_vmt ahb_master_vmt ahb_monitor_vmt ahb_slave_vmt See page 304 DesignWare AMBA Advanced Peripheral Bus APB models apb_master_vmt apb_monitor_vmt apb_slave_vmt See page 306 DesignWare AXI models axi_master_vmt axi_slave_vmt axi_monitor_vmt axi_interconnect_vmt See page 307 PCI Express Transceiver and Monitor models pcie_txrx_vmt pcie_monitor_vmt See page 314 USB On The_Go Host Device and Monitor models usb_host_vmt usb_device_vmt usb_monitor_vmt See page 319 Ethernet 10 100 1G 10G Transceiver and Monitor models
228. nes desea es ceesdeedeees 137 DW02_cos AOU Cosine 2 4 ox dene ecs ous 56 oe eb roas hon eeoa EET sex 138 DWO2_ sin SO I got cee henee etude eehs bees eb eee ted hed ceRense ds cue 139 DW02_sincos Combinational Sine Cosine 24uh lt d4ese4satewsteucteadebuetenseswndes 140 ass Se a ares or ee age nay ener er ce ane eee ire or ILRI EAS 141 DW_crc_p Universal Parallel Combinational CRC Generator Checker 142 DW_crc_s Universal Synchronous Clocked CRC Generator Checker 144 DW_ecc Error Checking and Correction 4 444 s beewedbeadiendeeyebeees endieas 146 DW04_par_gen Panty Generator and Checker 2 341 e cases xsd e dee eesGeeeiedes Lees 148 Data Integrity Coding Group Overview 0 cee eee eee eee 149 DW_8b10b_dec BOlOW DEQUG 244ecteudeeberceabetuneeekedbautecdteinn tuaed basckes 150 DW_8b10b_enc We PUCOUE fo abes ociedeeetincameeeeledake tdadaees EE E S 152 DW_8b10b_unbal p10b Coding Balance Predictor osrcesiirssteritusired ridete iiki 154 Digital Signal Processing DSP cirirccisreiiiverciciiticriiettisikiinti 153 DW_fir High Speed Digital FIR Piller 44401046445 554666502404 4454040404b0e200 156 6 Synopsys Inc January 17 2005 DesignWare IP Family Contents DW_fir_seq pequential Digital FIR Piller 2i4 s4deeseadeea dd ewasoaed ouesee seeuasus 158 DW _iir_dc High Speed Digital IIR Filter with Dynamic Coefficients 160 DW_iir_sc High Speed Digital IIR Filter with S
229. nference assign PROD DWF mult tc IN1 IN2 Function Inference DWO2 mult 8 8 Ul A B TC PRODUCT Instantiation Details about inference and instantiation in VHDL and Verilog are in the following directory SYNOPS YS dw examples g m wn lt S gt D o N D gt D 5 Synthesizing DesignWare Building Block IP in DC Design Compiler automatically selects the best implementation for combinational DesignWare Building Block IP You can also force Design Compiler to select the implementation of your choice either by adding Synopsys Compiler directives or by using the following commands dc _ shell gt set dont use standard sldb DW01 add rpl dc shell gt set implementation clf add 68 Simulating DesignWare Building Block IP Synopsys VCS simulator uses the default setup file while simulating DesignWare Building Block IP Use the following options to simulate DesignWare Building Block IP with a Verilog simulator y SSYNOPSYS dw sim ver libext v January 17 2005 Synopsys Inc 33 Chapter 2 DesignWare Library Synthesizable IP DesignWare IP Family Building Block IP in DC FPGA QuickStart The following topics provide the basic information to get started using the DesignWare Building Block IP with DC FPGA Updating Building Block IP for DC FPGA To get the latest version and receive the best performance install the Electronic Software Transfer EST release of DesignWare Building Block IP from the follo
230. ng a function call Table 1 Pin Description DesignWare IP Family DW_bin2gray Binary to Gray Converter Pin Name Width Direction Function g m wo lt m gt 0 o N D 2 D 5 b width bit s Input Binary coded input data width bit s Output Gray coded output data Table 2 Parameter Description Parameter Values Description width 21 Input word length Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc 61 DesignWare IP Family DW01_bsh Barrel Shifter DW01_bsh Barrel Shifter e Parameterized data and shift coefficient word lengths a B e Inferable using a function call oe Table 1 Pin Description Pin Name Width Direction Function A A_width Input Input data SH SH_width Input Shift control B A_width Output Shifted data out Table 2 Parameter Description Parameter Values Description A_width 21 Word length of A and B SH_width lt ceil log5 A_width for mx2 mx2i Word length of SH gt 1 for mx4 mx8 Table 3 Synthesis Implementations Implementation Name Function License Feature Required mx2 Implement using 2 1 multiplexers only DesignWare mx2i Implement using 2 1 inverting DesignWare multiplexers and
231. ng options fine tune performance area trade offs Buffer and descriptor pre fetching maximizes host throughput Firmware selectable endpoint configurations enable post silicon application changes and the flexibility of one chip design for multiple applications Synopsys Inc Quality IP is tested through extensive Constrained Random Verification AMBA High Performance Bus AHB interface enables rapid integration into ARM based designs UTMI Level 3 enables rapid integration with compatible PHYs Hi Speed 480 Mbps Full Speed 12 Mbps and Low Speed 1 5 Mbps operation is compliant to the USB OTG Supplement Supports all OTG features including Host Negotiation Protocol and Session Request Protocol Verilog Source RTL 362 010 MA DesignWare IP Family dwcore_usb2_hsotg Synthesizable USB 2 0 Hi Speed On the Go Controller Subsystem AHB Application Bus AHB Slave Interface Interrupt AHB Master Interface Descriptor Prefetch Buffer Single Port Ram DPB RAM Interface Transaction DWC_HSOTG AIU D DWC_HSOTG aes Sideband ignals CSR metie DWC_HSOTG MAC Data RAM Interface UTMI UTMI PHY Data Port RAM The dwcore_usb2_hsotg data sheet is available at http www synopsys com products designware docs ds c dwc_usb2_hsotg html 363 Synopsys Inc January 17 2005 DesignWare IP Fami
232. ngine RBU Destination Receive RPE Address Filter Flow DAF gt Controller FRX MAC Control i Interface MCI Control and Status Registers CSR Station Management lt gt Agent Management Counters SMA Optional The dwcore_gig_ethernet data sheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_gig_ethernet pdf 010 MA January 17 2005 Synopsys Inc 338 DesignWare IP Family dwcore_gig_ethernet_sub Synthesizable Gigabit Ethernet Subsystem dwcore_gig_ethernet_sub Synthesizable Gigabit Ethernet Subsystem The Synopsys DesignWare Gigabit Ethernet MAC GMAC Subsystem enables the host to communicate data using the Gigabit Ethernet protocol IEEE 802 3 The GMAC Subsystem is composed of three main layers the Gigabit Ethernet Media Access Controller GMAC the MAC Transaction Layer MTL and the MAC DMA Controller MDC Other features include the following 339 Compliant with IEEE 802 3z and 802 3u specifications Supports 10 100 Mbps and 1 Gbps data transfer rates IEEE 802 3z Gigabit Media Independent Interface GMI TEEE 802 3z Physical Coding Sublayer PCS with Ten Bit Interface TBI that supports autonegotiation optional Supports Full and Half Duplex operations in all speed modes Generates and accepts Control Frames in Full Duplex Mode IEEE 802 3x Includes configurable counters for statistical network management support
233. ngth e Carry in and carry out signals g m wn lt S gt D o N D gt D 5 Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data B width bit s Input Input data CI 1 bit Input Carry borrow in ADD_SUB _ 1 bit Input Addition subtraction control SUM width bit s Output Sum A B CI or difference A B CI CO 1 bit Output Carry borrow out Table 2 Parameter Description Parameter Values Description width gt 1 Word length of A B and SUM Table 3 Synthesis Implementations Implementation Name Implementation License Feature Required rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none bk Brent Kung architecture synthesis model DesignWare clf Fast carry look ahead synthesis model DesignWare csm Conditional sum synthesis model DesignWare rpcs Ripple carry select architecture DesignWare clsa MC inside DW carry look ahead select DesignWare January 17 2005 Synopsys Inc 55 DesignWare IP Family DW01_addsub Adder Subtractor Table 3 Synthesis Implementations Continued Implementation Name Implementation License Feature Required csa MC inside DW carry select DesignWare fastcla MC inside DW fast carry look ahead DesignWare pprefix MC inside DW flexible parallel prefix DesignWare pparc
234. nous or asynchronous memory array initialized or not Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 or 2 synchronous if rst_mode 1 or 3 push_req_n 1 bit Input FIFO push request active low pop_req_n 1 bit Input FIFO pop request active low diag_n 1 bit Input Diagnostic control active low data_in width bit s Input FIFO data to push empty 1 bit Output FIFO empty output active high almost_empty 1 bit Output FIFO almost empty output active high half_full 1 bit Output FIFO half full output active high almost_full 1 bit Output FIFO almost full output active high full 1 bit Output FIFO full output active high error 1 bit Output FIFO error output active high data_out width bit s Output FIFO data to pop January 17 2005 Synopsys Inc 195 DesignWare IP Family DW_fifo_s1_sf Synchronous Single Clock FIFO with Static Flags Table 2 Parameter Description Parameter Values Function width 1 to 256 Width of the data_in and data_out buses Default 8 depth 2 to 256 Number of memory elements used in FIFO Default 4 addr_width ceil log depth ae_level 1 to depth 1 Almost empty level the number of words in the FIFO at Default 1 or below which the almost_empty flag is active af_level 1 to depth 1 Almost full level the number of empty memory location
235. nput Counter load enable active low cen 1 bit Input Counter enable active high clk 1 bit Input Clock reset 1 bit Input Asynchronous counter reset active low count width bit s Output Output count bus tercnt 1 bit Output Terminal count flag Table 2 Parameter Description Parameter Value Function width 21 Width of count output bus Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cla Carry look ahead synthesis model DesignWare clf Fast carry look ahead synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 180 Synopsys Inc January 17 2005 DesignWare IP Family Tit Memory FIFO Overview The FIFOs in this category address a broad array of design requirements FIFOs which include dual port RAM memory arrays are offered for both synchronous and asynchronous interfaces The memory arrays are offered in two configurations latch based to minimize area and D flip flop based to maximize testability These two configurations also offer flexibility when working under design constraints such as a requirement that no latches be employed Flip flop based designs em
236. nput Input data data_out l bit Output Output data SO 1 bit Output Serial path to the next boundary scan cell Table 2 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare or Test EEE STD 1149 1 January 17 2005 Synopsys Inc 251 DesignWare IP Family DW_bc_3 Boundary Scan Cell Type BC_3 DW_bc_3 Boundary Scan Cell Type BC_3 e IEEE Standard 1149 1 compliant data_in data_out e Synchronous or asynchronous scan cells with respect to tck si 20 mode e Supports the standard instructions EXTEST SAMPLE md PRELOAD and BYPASS e Supports the optional instructions INTEST RUNBIST CLAMP and HIGHZ gt capture_clk q capture_en Table 1 Pin Description Pin Name Width Direction Function capture_clk 1 bit Input Clocks data into the capture stage capture_en bit Input Enable for data clocked into capture stage active low shift_dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo mode 1 bit Input Determines whether data_out is controlled by the boundary scan cell or by the data_in signal si 1 bit Input Serial path from the previous boundary scan cell data_in 1 bit Input Input data from system input pin data_out 1 bit Output Output data to IC logic SO 1 bit Output Serial path to the next boundary scan cell
237. nse to link requests e Requester and Completer operate e Allows modification and review of concurrently using independent internal address spaces with zero cycle command channels commands e Power management support e Allows configuration of address ranges for internal memory and I O spaces e Returns raw request packets e Transmits raw completion packets e Creates completion packets for incoming requests e Notifies testbench of significant events 314 Synopsys Inc January 17 2005 DesignWare IP Family PCI Express Models Transceiver and Monitor Monitor e Provides coverage of PCI Express compliance checklist Coverage reports show checks passed checks failed and checks not hit e Logging of PCI Express transactions Configurable to show start time stop time direction packet type sequence credits and many other packet attributes e Records coverage for TLP types g rc S m TESTBENCH pcie_txrx_vmt new_buffer 1e_ 9 na read write mem Write stops Queue here eee Q I posted mi Requester Completer V i in L ff L _ T Queue Que
238. nstruction cycles e e Multiple high bandwidth internal data buses also available externally XBus Local Memory bus Dual Port RAM bus PDBus e Up to 112 interrupt nodes 15 of which are used for internal interrupts 383 Synopsys Inc 16 level 8 group level interrupt priority Up to 16 interrupt driven peripheral event controller PEC channels Power reduction modes Programmable watchdog timer e Debug interface that supports hardware software and external breakpoints and provides access to internal registers and memory through a JTAG module Support for a wide variety of third party development and debugging tools the current list of support tools is available at http www infineon com Asynchronous synchronous serial channel ASC High speed synchronous serial channel SSC General purpose timer block GPT12E Ports I O module that provides programmable external bus or general purpose I O port functionality LM to AHB bridge for integration into AMBA based systems January 17 2005 S DesignWare IP Family ap Ip DW_C166S C166S 16 Bit Microcontroller from Infineon PAD interface External Bus Dedicated Pins Memory Interrupt Requests d PDBus Local Memory gt e Peripherals LM66 Interfaces Control Debug Signals System Control JTAG Module Clock Interface Clock Generation Unit C166S Core S
239. nthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare 168 Synopsys Inc January 17 2005 DesignWare IP Family iis DW01_prienc Priority Encoder DW01_prienc Priority Encoder e Parameterized word length g e Inferable using a function call D lt gt D Table 1 Pin Description N Pin Name Width Direction Function A A_width Input Input data v INDEX INDEX _width Output Binary encoded output data Table 2 Parameter Description Parameter Values Description A_width 21 Word length of input A INDEX _width 2 ceil logs A_width 1 Word length of output INDEX Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare cla Synthesis model DesignWare January 17 2005 Synopsys Inc 169 DesignWare IP Family Logic Sequential Overview The sequential components consist of high performance counters many with either dynamic or static count to flags Components in this category have multiple architectures for each function architecturally optimized for either performance or area to provide you with the best architecture for your design goals All components have a parameterized word length 170 Synopsys Inc January 17 2005 DesignWare IP Family
240. o Chapter 4 DesignWare Foundry Libraries DesignWare IP Family Table 2 TSMC Standard Cell Categories Continued Technology Process Feature Library Name 130nm General Nominal VT TCB0O13GHP Patpa Low VT TCB013GHPLVT High VT TCB013GHPHVT Low Voltage Nominal VT TCBO13LVHP High VT TCBO13LVHPHVT Over Drive 1 2V TCB0O13LVHPOD Over Drive 1 2V High VT TCBO13LVHPODHVT Low Power Nominal VT TCB013LPHP Low VT TCB0O13LPHPLVT 150nm General Nominal VT TCBOISGHD Purpose Low Voltage Nominal VT TCBOISLVHD Tower Libraries The 0 18 micron Tower library is a set of technology aggressive high performance and high density foundation intellectual property IP specifically targeted for manufacture of IC designs at Tower Semiconductor Ltd Library components include standard cells I Os and memory compilers All are handcrafted to Tower Semiconductor s 0 18 micron process design rules The library has been extensively silicon validated to ensure maximum performance and reliability The libraries support an open electronic design automation EDA environment The DesignWare Library 0 18 micron Tower library is an ideal solution for both all digital integrated circuit and mixed signal designs 329 Synopsys Inc January 17 2005 DesignWare IP Family Chapter 5 DesignWare Cores 5 DesignWare Cores DesignWare Cores provide system designers with silicon proven digital and analog
241. o decoding and advanced sound enhancement algorithms e Dual Harvard architecture e Full 24 bit data paths 389 Synopsys Inc Two 24 x 24 bit signed multipliers Three ALUs Four 56 bit accumulators Extensive addressing modes with modulo protection bit reversal Saturation and rounding units RISC instruction set suitable for control as well as DSP Highly efficient stack support e Zero overhead loops nested up to 4 levels 64 Kwords address space each for P X Y IO DMA ports for program and data memories e Three maskable low latency interrupts Extensive power management support stop restart instructions JTAG based Joint Test Action Group IEEE 1149 1 std test interface debug port January 17 2005 DesignWare IP Family 9p i DW_CoolFlux CoolFlux 24 bit DSP Core from Philips Program X Data Y Data Memory Memory Memory 32 46 A24 16 A24 416 L Program X Address Y Address Control Generation Generation Operand Registers X Y Multiplier X ALU 0 Multiplier Y ALU X ALU Y Accumulator Registers A B Rounding Saturation Data Computation i fi t t 7 Interrupts JTAG DMA 1 0 Also see the following web page for additional information http www synopsys com products designware starip philips_coolflux html January 17 2005 Synops
242. ode Supports IEEE 802 3 flow control for Full Duplex operation Automatic Pause Frame generation in Full Duplex mode Back pressure support in Half Duplex mode Supports magic packet and wake on LAN frame detection Ethernet frame statistic support for Management Information Base MIB Options for automatic pad stripping Supports jumbo frames Supports internal loopback on the GMII MII interface for debugging Supports a variety of flexible address filtering modes Separate 32 bit status returned for transmit and receive frames January 17 2005 DesignWare IP Family Cc Ofo dwcore_gig_ethernet S Synthesizable Gigabit Ethernet Core Media Access Controller Transmit CRC Generator MAC Frame CTX Transmit man n Controller Ti it Protocol Interface TFC fae Engine MTI Transmit k Flow Controller TPE Bus FTX Interface lt gt lt gt Unit gt TBU la Transmit Scheduler Power STX P gt Management a GMII MII z TBI Block CRC MAC poa k Checker i RX Receive Controller CE i Interface x RFC i A MRI Receive i gt Intetece W i I Receive ni Has z
243. ode and PCI X mode Each system testbench uses two g m S O o e gt Ea PCI system level testbench HDL control cimaster_fx C or Vera command stream gt P i control file Design Under SSS Test HDL control cislave_ fx C or Vera command stream gt P 2 control file HDL control cimonitor_fx C or Vera command stream gt P control file bus trace output file The individual DesignWare FlexModel databooks are available with each model at http www synopsys com products designware ipdir January 17 2005 Synopsys Inc 316 DesignWare IP Family Serial ATA Models PRELIMINARY Device and Monitor Serial ATA Models PRELIMINARY Device and Monitor Device sata_device_vmt Monitor sata_monitor_vmt e Gen 1 and Gen 2 support e Gen 1 and Gen 2 support e SATA PHY Interface Differential e Snoops bus information NRZ serial stream e Protocol coverage e Transfer support includes e Checks the validity of the following o PIO aspects for the corresponding layers o First party DMA o Physical Serialization o Legacy and Legacy Queued DMA Deserialization SERDES o Non Data and PACKET command Out of band signaling transfers o Link Framing CRC 8B 10B e Power on sequencing and speed encoding scrambling running negotiation disparity e CRC computation 8B 10B encoding o Transport FIS sequencing
244. odel Any timing parameters that differ from the vendor specifications How to program the device if applicable or otherwise use it in simulation Differences between the model and the corresponding hardware device Models are partitioned by function including Processors VLSI Programmables Memories Standards Buses General Purpose SmartModel datasheets have standard sections that apply to all models and model specific sections whose contents depend on the model type 325 Synopsys Inc January 17 2005 DesignWare IP Family Chapter 4 DesignWare Foundry Libraries g 4 DesignWare Foundry Libraries This chapter briefly describes the DesignWare Foundry Libraries Synopsys is teaming with foundry leaders to provide DesignWare Library licensees access to standard cells memories and I Os optimized for their process technologies starting with 0 15 0 13 micron and 90 nm Each library is delivered in a set of front end and back end views The front end views enable a complete evaluation of the libraries all the way through layout and complete verification The back end views include the GDSII data and tech files necessary for tape out TSMC Libraries TSMC and Synopsys offer a complete path from RTL to GDSII by ensuring a tight integration of the TSMC Libraries and the Synopsys Galaxy platform through the TSMC Reference Flow 5 0 Both the front end and back end views of the TSMC 0 15 0 13 micron and Nexsys 90 nanometer Standard
245. of B Table 3 Synthesis Implementations Implementation Name Function csa Carry save array synthesis model DesignWare str Booth recoded Wallace tree synthesis model DesignWare License Feature Required a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 94 Synopsys Inc January 17 2005 DesignWare IP Family DW02_mult_5_ stage Five Stage Pipelined Multiplier b The csa implementation is only valid when the sum of A_width and B_width lt 8 bits as it has no area benefit beyond 48 bits g m wo lt m gt D 2 N D 2 D 5 January 17 2005 Synopsys Inc 95 DesignWare IP Family DW02_mult_6_stage Six Stage Pipelined Multiplier DW02_mult_6 stage Six Stage Pipelined Multiplier e Parameterized word length e Unsigned and signed two s complement data operation Six stage pipelined architecture Automatic pipeline retiming e Inferable from Behavioral Compiler Table 1 Pin Description Pin Name Width Direction Function A A_width bit s Input Multiplier B B_width bit s Input Multiplicand TC 1 bit Input Two s complement 0 unsigned 1 signed CLK 1 b
246. of clk rst_n 1 bit Input Asynchronous reset active low coef_shift_en 1 bit Input Enable coefficient shift loading at coef_in active high This signal is synchronous to the positive edge of clk tc 1 bit Input Defines data_in and coef_in values as two s complement or unsigned When low the data_in and coef_in values are unsigned When high the data_in and coef_in values are two s complement run 1 bit Input Handshake signal that initiates the processing of a data sample on the data_in port This signal is synchronous to the positive edge of clk 158 Synopsys Inc January 17 2005 DesignWare IP Family DW_fir_seq Sequential Digital FIR Filter Table 1 Pin Description Pin Name Size Direction Function data_in data_in_width Input Input data bit s coef_in coef_width Input Serial coefficient load port This port is enabled when bit s the coef_shift_en pin is set high A rising edge of clk loads the coefficient data at coef_in into the first internal coefficient register and shifts all other coefficients in the internal registers one location to the right init_acc_val_ data_out_width Input Initial accumulated value for the convolution sum of bit s products Normally set to zero 000 000 start 1 bit Output Handshake signal generated by synchronizing the run input with clk It acknowledges the run signal and indicates t
247. ommands g m S O o e gt 5 Listing of FlexModels Table 1 lists the FlexModels that are available including a brief description Table 1 Listing of FlexModels Model Name Vendor Description Bus Models enethub_fx Ethernet Emulates the protocol of Ethernet Hub at the pin and bus cycle levels handles data routing from TX to RX rmiis_fx Ethernet Interface between MII and reduced RMII interface pcimaster_fx PCI PCI X Emulates the protocol of PCI PCI X initiators at the pin and bus cycle levels Initiates read and write cycles pcislave_fx PCI PCI X Responds to cycles initiated by the pcimaster_fx model or by the user s PCI master device pcimonitor_fx PCI PCI X Monitors logs and arbitrates activity on the PCI or PCI X bus Support Models sync8_fx Synopsys 8 bit synchronization model January 17 2005 Synopsys Inc 322 Listing of FlexModels DesignWare IP Family More information on these models is available from the following Web page http www synopsys com products designware dwverificationlibrary html The FlexModel User s Manual is available at http www synopsys com products designware docs 323 Synopsys Inc January 17 2005 DesignWare IP Family SmartModel Features DesignWare SmartModels The SmartModel Library is a collection of over 3 000 binary behavioral models of standard integrated circuits supporting more than 12 000 different devic
248. ontroller interrupt controller general purpose I O UART Synchronous Serial I O I2C and a dual master DMA e Multi layer Bridge A variant of the multi layer design with a bridge replacing the interconnect matrix DesignWare AMBA Connect also offers two QuickStart examples which are described in the topic titled DesignWare AMBA QuickStart on page 288 For more information about using DesignWare AMBA Connect refer to the DesignWare AMBA Connect Databook available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 287 DesignWare IP Family DesignWare AMBA QuickStart Collection of example designs for AMBA subsystems DesignWare AMBA QuickStart Collection of example designs for AMBA subsystems DesignWare AMBA QuickStart is a collection of example designs for AMBA subsystems built with DesignWare AMBA On chip Bus synthesizable IP and verification IP components The QuickStart demonstrates the following e How the DesignWare AMBA On Chip Bus components and peripherals synthesizable IP integrate together e How to initialize and program using C or Verilog BFM commands the synthesizable component blocks to perform basic operating functions e How the DesignWare AMBA verification models and synthesizable components work together e How to connect and use a microprocessor model within a DesignWare AMBA subsystem QuickStart currently includes two example designs e QuickSta
249. ook is available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 267 DesignWare IP Family DW_ahb_dmac AHB Central Direct Memory Access DMA Controller DW_ahb dmac AHB Central Direct Memory Access DMA Controller e AMBA 2 0 compliant e AHB slave interface used to program the DW_ahb_dmac e AHB master interface s o Up to four independent AHB master interfaces that allows e Up to four simultaneous DMA transfers e Masters that can be on different AMBA layers multi layer support e Source and destination that can be on different AMBA layers pseudo fly by performance o Configurable data bus width up to 256 bits for each AHB master interface o Configurable endianness for master interfaces DMA Hardware Request I F Master I F e Channels o Up to eight channels one per source and destination pair o Unidirectional channels data transfers in one direction only o Programmable channel priority e Transfers o Support for memory to memory memory to peripheral peripheral to memory and peripheral to peripheral DMA transfers o DW_ahb_dmac to or from APB peripherals through the APB bridge e Configurable identification register e Component parameters for configurable software driver support e Encoded parameters e AMBA Compliance Tool ACT certification Channel 0 AHB Slave I F The DesignWare DW_ahb_dmac Databook
250. opsys Inc 37 DesignWare IP Family Application Specific Control Logic Application Specific Control Logic The Control Logic IP consist of a family of arbiters The arbiter components are distinguished from each other primarily by the arbitration scheme they embody The components DW_arbiter_sp and DW_arbiter_dp are based on the static fixed priority scheme and dynamically programmable priority scheme respectively Each of these components has multiple architectural implementations optimized for timing or area The number of clients connected to the arbiter is parametrizable from 2 to 32 Other features like parking and locking are available through parameter selection 38 Synopsys Inc January 17 2005 DesignWare IP Family DW_arbiter_ 2t Two Tier Arbiter with Dynamic Fair Among Equal Scheme DW_arbiter_2t Two Tier Arbiter with Dynamic Fair Among Equal Scheme e Parameterizable number of clients g request e Programmable mask for all clients mack grant D tind 5 e Park feature default grant when no requests are pending oe ty See F o e Lock feature ability to lock the currently granted client N locked oF e Registered unregistered outputs m granted o parked a rst_n Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Active low input reset request n bit s Input Input request from clients priority nx p_width In
251. or Up down count control DesignWare IP Family DW03_Ifsr_updn LFSR Up Down Counter tercnt clk reset Table 1 Pin Description Pin Name Width Direction Function updn 1 bit Input Input high for count up and low for count down 1 bit Input Input count enable 1 bit Input Clock reset 1 bit Input Asynchronous reset active low count width bit s Output Output count bus tercnt 1 bit Output Output terminal count Table 2 Parameter Description Parameter Values Description width 2 to 50 Word length of counter a The upper bound of the legal range is a guideline to ensure reasonable compile times Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc g rc 7 lt m gt 0 2 N D 2 D 5 DesignWare IP Family DW03_updn_ctr fox Up Down Counter DW03_updn_ctr Up Down Counter e Up down count control e Asynchronous reset e Loadable count register e Counter enable e Terminal count flag clk reset e Multiple synthesis implementations Table 1 Pin Description Pin Name Width Direction Function data width bit s Input Input data bus up_dn 1 bit Input Count up up_dn 1 or count down up_dn 0 load 1 bit I
252. ormally called Foundation Library is a collection of reusable intellectual property blocks that are tightly integrated into the Synopsys synthesis environment Using DesignWare Building Block IP allows transparent high level optimization of performance during synthesis With the large number of parts available design reuse is enabled and significant productivity gains are possible This library contains high performance implementations of Basic Library IP plus many IP that implement more advanced arithmetic and sequential logic functions The DesignWare Building Block IP consists of e Basic Library A set of IP bundled with HDL Compiler that implements several common arithmetic and logic functions e Logic Combinational and Sequential IP e Math Arithmetic and Trigonometric IP e Digital Signal Processing DSP IP FIR and IIR filters January 17 2005 Synopsys Inc 31 g m wo lt m gt 0 2 N D D 5 Chapter 2 DesignWare Library Synthesizable IP DesignWare IP Family e Memory Registers FIFOs and FIFO Controllers Synchronous and Asynchronous RAMs and Stack IP e Application Specific Data Integrity Interface JTAG IP and others Building Block IP for DC QuickStart The following topics provide the basic information for you to get started using the DesignWare Building Block IP Updating Building Block IP for DC To get the latest version and receive the best performance install the Electronic So
253. orrected or uncorrected data from chkin When gen 0 and synd_sel 1 chkout is the error syndrome value 146 Synopsys Inc January 17 2005 R DesignWare IP Family DW_ecc Error Checking and Correction Table 2 Parameter Description g m wo lt m gt 0 o N D 2 D 5 Parameter Values Description width 8 to 502 Width of input and output data buses chkbits 5to 10 Width of check bits input and output buses calculated from width synd_sel O or 1 Selects function of chkout when gen 0 If synd_sel 0 and gen 0 then chkout is the corrected or uncorrected data from chkin If synd_sel 1 and gen 0 then chkout is the error syndrome value Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc 147 DesignWare IP Family DW04_par_gen Parity Generator and Checker DW04_par_gen Parity Generator and Checker e Generates parity for given input data e Supports even and odd parity selectable via a parameter e Supports variable word widths e Inferable using a function call Table 1 Pin Description Pin Name Width Direction Function datain width bit s Input Input data word to check or generate parity parity 1 bit Output Generated parity Table 2 Parameter Description
254. ose 1 5V 3 3V 5V tol Staggered TPZ015G Low Voltage 1 2V 3 3V 5V tol Staggered TPZO1ISLG 327 Synopsys Inc January 17 2005 DesignWare IP Family Chapter 4 DesignWare Foundry Libraries Table 2 TSMC Standard Cell Categories Technology Process Feature Library Name 90nm General Nominal VT TCBN90G Purpose G aw Vr TCBN9OGLVT High VT TCBN9OGHVT Over Drive TCBN90GOD Over Drive Low VT TCBN90GODLVT Over Drive High VT TCBN90GODHVT High Performance Library Nominal TCBN9OGHP VT High Performance Library Low VT TCBN9OGHPLVT High Performance Library High VT TCBN9OGHPHVT High Performance Library Over TCBN90GHPOD drive Nominal VT High Performance Library Over TCBN90GHPODLVT drive Low VT High Performance Library Over TCBN90GHPODHVT drive High VT High High Performance Library Nominal TCBN9OGTHP Performance VT St High Performance Library Low VT TCBN9OGTHPLVT High Performance Library High VT TCBN9OGTHPHVT Low Nominal VT TCBN9OLP eS EE Low VT TCBNOOLPLVT High VT TCBN9OLPHVT Ultra High VT TCBN9OLPUHVT High Performance Library Nominal TCBN9OLPHP VT High Performance Library Low VT TCBN9OLPHPLVT High Performance Library High VT TCBN9OLPHPHVT High Performance Library Ultra TCBN9OLPHPUHVT High VT January 17 2005 Synopsys Inc 328 z m o 5 2 Q lt T roy g 9 D
255. ot Port Core page 347 Synthesizable RTL dwc_pcie_switchport PCI Express Switch Port Core page 349 Synthesizable RTL dwc_pcie_dualmode PCI Express Dual Mode Core page 350 Synthesizable RTL Synopsys Inc January 17 2005 DesignWare IP Family Chapter 1 Overview dwcore_pcie_phy PCI Express PHY Core page 352 Hard IP SATA Core dwc_sata_host SATA Host page 370 Synthesizable RTL USB Cores dwcore_usb1_device USB 1 1 Device Controller page 355 Synthesizable RTL dwcore_usb1_host USB 1 1 OHCI Host Controller page 357 Synthesizable RTL dwcore_usb1_hub USB 1 1 Hub Controller page 359 Synthesizable RTL dwcore_usb2_host USB 2 0 Host Controller UHOST 2 page 364 Synthesizable RTL dwcore_usb2_hsotg USB 2 0 Hi Speed On the Go Controller Synthesizable RTL Subsystem page 362 dwcore_usb2_device USB 2 0 Device Controller page 366 Synthesizable RTL dwcore_usb2_phy USB 2 0 PHY page 368 Hard IP Also visit the DesignWare Cores web page at http www synopsys com products designware dwcores html January 17 2005 Synopsys Inc Chapter 1 Overview DesignWare Star IP Synopsys offers DesignWare Library users the ability to evaluate and design easily at their desktop using the following high performance high value IP cores from leading DesignWare IP Family Star IP providers Component Name Component Description Component Type DW_IBM440 PowerPC 4
256. ous reset byte_order Oor 1 Order of bytes or subword subword lt 8 bits gt subword within Default 0 a word 0 first byte is in most significant bits position 1 first byte is in the least significant bits position Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cll Partial carry look ahead model DesignWare cl2 Full carry look ahead model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide January 17 2005 Synopsys Inc 205 DesignWare IP Family DW_asymfifoctl_s2_sf Asymmetric Synchronous Dual Clock FIFO Controller with Static Flags DW_asymfifoctl_s2_sf Asymmetric Synchronous Dual Clock FIFO Controller with Static Flags e Parameterized asymmetric input and output bit widths must be integer multiple relationship e Parameterized word depth e Fully registered synchronous flag output ports e Separate status flags for each clock domain e FIFO empty half full and full flags e Parameterized almost full and almost empty flags e FIFO push error overflow and pop error underflow flags e Single clock cycle push and pop operations e
257. ow and receive FIFO overflow interrupts can all be masked independently e Multi master contention detection Informs the processor of multiple serial master accesses on the serial bus e Bypass of meta stability flip flops for synchronous clocks When the APB clock pclk and the DW_apb_ssi serial clock ssi_clk are synchronous meta stable flip flops are not used when transferring control signals across these clock domains January 17 2005 e Programmable features Synopsys Inc DesignWare IP Family DW_apb_ssi APB Synchronous Serial Interface o Serial interface operation Choice of Motorola SPI Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire g m wo lt m gt 0 2 N D D 5 o Clock bit rate Dynamic control of serial bit rate of data transfer used in only serial master mode o Data Item size 4 to 16 bits Item size of each data transfer under control of programmer e Configurable features o FIFO depth Configurable depth of transmit and receive FIFO buffers from 2 to 256 words deep FIFO width fixed at 16 bits o Number of slave select outputs When operating as serial master 1 to 16 serial slave select output signals can be generated o Hardware software slave select Dedicated hardware slave select lines or software control for targeting serial slave device o Combined or individual interrupt lines o Interr
258. owever you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b This architecture is specially generated using Module Compiler technology It is normally used as a replacement for rather than in conjunction with the HDL architectures available for the same DesignWare part To use this architecture during synthesis the dc_shell t variable dw_prefer_mc_inside must be set to true From the DC 2004 12 release onward the MC architectures are not available by default For more information refer to the DesignWare Building Block IP Users Guide c This delay optimized parallel prefix architecture is generated using Datapath generator technology DW gensh This is ON by default in the Design Compiler flow The DC variable synlib_enable_dpgen must be set to true the default to make use of this Datapath technology g m wo lt m gt D 2 N D 2 D 5 January 17 2005 Synopsys Inc 81 DesignWare IP Family DW_inc_gray Gray Incrementer DW_inc_gray Gray Incrementer e Parameterized word length e Inferable using a function call Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Gray coded input data ci 1 bit Input Carry in Z width bit s Output Gray coded output data Table 2 Parameter Description P
259. peed Enumeration Block Protocol Management Command Bridge Laver Layer Protocol x Parallel Serial Interface Interface Engine Engine PIE SIE PHY Macrocell Transceiver The dwcore_usb2_device data sheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_usb2_device pdf 367 Synopsys Inc January 17 2005 Co dwcore_usb2_phy USB 2 0 Transceiver Macrocell Interface PHY DesignWare IP Family dwcore_usb2_phy USB 2 0 Transceiver Macrocell Interface PHY The USB 2 PHY includes all the required logical geometric and physical design files to implement USB 2 0 capability in a System on Chip SOC design and fabricate the design in the designated foundry The initial foundry process for the USB 2 PHY is the 0 18 micron CMOS digital logic process Alternatively design services are available for porting the USB 2 PHY to other semiconductor processes The USB 2 PHY integrates high speed mixed signal custom CMOS circuitry compliant with the UTMI Specification version 1 04 supports the USB 2 0 480 Mbps protocol and data rate and is backward compatible to the USB 1 1 legacy protocol at 1 5 Mbps and 12 Mbps Other features include the following January 17 2005 Complete mixed signal physical layer PHY for single chip USB 2 0 applications USB 2 0 Transceiver Macrocell Interface UTMI Specification compliant 8 bit interface at 60 MHz operation and 16 bit interface at 30 MHz opera
260. plementation Name Function License Feature Required str Synthesis model DesignWare Synopsys Inc January 17 2005 DesignWare IP Family DW_shifter Combined Arithmetic and Barrel Shifter DW_ shifter Combined Arithmetic and Barrel Shifter e Dynamically selectable arithmetic or barrel shift mode data_in Parameterized input control inverted and non inverted logic data_tc Parameterized padded logic value control for arithmetic shift sh data_out only sh_tc Parameterized data and shift coefficient word lengths See Inferable using a function call support for inv_mode 0 only Table 1 Pin Description Pin Name Width Direction Function data_in data_width bit s Input Input data data_tc 1 bit Input Two s complement control on data_in 0 unsigned data_in 1 signed data_in sh sh_width bit s Input Shift control sh_te 1 bit Input Two s complement control on sh 0 unsigned sh 1 signed sh sh_mode 1 bit Input Arithmetic or barrel shift mode 0 barrel shift mode 1 arithmetic shift mode data_out data_width bit s Output Output data Table 2 Parameter Description Parameter Values Description data_width gt 2 Word length of data_in and data_out sh_width 1 to ceil logy data_width 1 Word length of sh inv_mode 0 to3 logic mode Default 0 0 normal input 0 padding in output 1 normal input 1 padding in out
261. plete USB device interface Features include the following 32 bit Virtual Component Interface VCI Maintains address pointer for endpoint 0 transactions Silicon proven e USB 1 1 compliant 355 AHB Interface and DMA Engine options Standard register set specification available Applications supported include pointing devices scanners cameras faxes printers speakers monitor Verilog source code Synopsys Inc Supports low speed and full speed devices Programmable number of endpoints Easily configurable endpoint organization Supports up to 15 configurations up to 15 interfaces per configuration and up to 15 alternate settings per interface Supports all USB standard commands Easy to add Vendor Class commands Suspend resume logic provided Approximately 12K gates for 5 physical endpoints January 17 2005 DesignWare IP Family On dwcore_usb1_device S Synthesizable USB 1 1 Device Controller Transceiver n Function Interface Logic Block 4 E EPINFO Block The dwcore_usb1_device data sheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_usb1_device pdf 010 MA January 17 2005 Synopsys Inc 356 DesignWare IP Family dwcore_usb1_host Synthesizable USB 1 1 OHCI Host Controller dwcore_usb1_host Synthesizable USB 1 1 OHCI Host Controller C KN The Synopsys DesignWare USB 1 1 Host Controller OHCI Synthesizable IP i
262. ploy no clock gating to minimize skew and maximize performance All FIFOs employ a FIFO RAM controller architecture in which there is no extended fall through time required before reading contents just written Memory FIFO Overview Also offered are FIFO Controllers without the RAM array They consist of control and flag logic and an interface to common ASIC dual port RAMs Choosing between the two is typically based on the required size of the FIFO For shallow FIFOs less than 256 bits synchronous or asynchronous FIFOs are available which include both memory and control in a single macro These macros can be programmed via word width depth and level almost full flag parameters For larger applications greater than 256 bits you can use the asynchronous FIFO Controller with a diffused or metal programmable RAM See Figure 1 Technology independent FIFO FIFO Controller to be used with a that includes control and memory technology specific vendor supplied RAM Synthetic Designs FIFO Synthetic Designs includes control and memory FIFO RAM Controller Controller Diffused Latch or or Metal Programmable Flip Flop RAM Based RAM on chip or off chip eFor shallow FIFOs lt 256 bits For large FIFOs gt 256 bits Self contained RAM storage array elnterfaces to dual port static RAMs Figure 1 Memory FIFOs and FIFO Controllers All FIFOs and Controllers support full empty and programmable flag logic Programma
263. pop active high Pop_ae l bit Output FIFO almost empty output flag synchronous to clk_pop active high determined by pop_ae_lvl parameter pop_ht l bit Output FIFO half full output flag synchronous to clk_pop active high pop_af l bit Output FIFO almost full output flag synchronous to clk_pop active high determined by pop_af_lvl parameter pop_full l bit Output FIFO full output flag synchronous to clk_pop active high pop_error 1 bit Output FIFO pop error underrun output flag synchronous to clk_pop active high wr_addr ceil log depth bit s Output Address output to write port of RAM rd_addr ceil log depth bit s Output Address output to read port of RAM push_word_count ceil logs depth 1 bit s Output Words in FIFO as perceived by the push pop interface pop_word_count ceil logy depth 1 bit s Output Words in FIFO as perceived by the push pop interface test 1 bit Input Active high test input control for inserting scan test lock up latches a As perceived by the push interface b As perceived by the pop interface Table 2 Parameter Description Parameter Values Description depth 4 to 274 Number of words that can be stored in FIFO Default 8 push_ae_lvl 1todepth 1 Almost empty level for the push_ae output port the number Default 2 ao in the FIFO at or below which the push_ae flag is January 17 2005 Synopsys Inc 215 g 7 lt m gt D
264. prod_sum Generalized Sum of Products DW02_prod_sum Generalized Sum of Products e Parameterized number of inputs TC g e Parameterized word length a r SUM 2 2 N D o Table 1 Pin Description a Pin Name Width Direction Function A A_width x num_inputs bit s Input Concatenated input data B B_width x num_inputs bit s Input Concatenated input data TC 1 bit Input Two s complement 0 unsigned 1 signed SUM SUM_width bit s Output Sum of products Table 2 Parameter Description Parameter Values Description A_width 21 Word length of A B_width gt 18 Word length of B num_inputs 21 Number of inputs SUM_width 21 Word length of SUM a For nbw implementation A_width B_width 36 Due to concern of implementation selection run time a limitation is set for A_width and B_width Table 3 Synthesis Implementations Implementation Function License Feature Required csa Carry save array synthesis model DesignWare wall Booth recoded Wallace tree synthesis model DesignWare nbw Either a non Booth A_width B_width 41 or a DesignWare Booth Wallace tree A_width B_width gt 41 synthesis model mearch MC inside DW Wallace tree DesignWare csmult MC inside DW flexible Booth Wallace DesignWare January 17 2005 Synopsys Inc 101 DesignWare IP Family DW02_prod_sum Generalized Sum of Products Table 3 Synt
265. psys Inc SystemC is a trademark of the Open SystemC Initiative and is used under license AMBA is a trademark of ARM Limited ARM is a registered trademark of ARM Limited All other product or company names may be trademarks of their respective owners 2 Synopsys Inc January 17 2005 DesignWare IP Family Contents Contents PrO 6 6 64 KO KES ROSALES OES ABER KHR OS KDEAHHA EEEE REESS 15 About This Manual 5 hk kak eres bo cee Fee oo ee ee ees 15 Manual OVERVIEW cacedeoeccotsonseeeeseee Heen eee oe shes es sh bx eee eee eos 15 Typographical and Symbol Conventions 2 46444 2c0ee4e08seneseeseeaes eves 16 Synopsys Common Licensing SCL iiccicccacciegadeadisaedecedhoetsaseceacaws 16 Creme GUE 45453516 eee n EGOS OOS Se ee 17 Additonal WS seas cede ent Ep oes whe ene anes eeieeeeee as 17 COMMENT icdienckded owns bendeesicbeoteretibedees 4aeedhess aeadies sence 17 Chapter 1 OVERVIEW isk k ced owen cena eden ensds keds es ek suns ene tit een ewe enaee ne 19 DesignWare LIMAY ccd hed eadebabatedadhe eee di haetea aden hendeban tags 20 Pi Bs 2a bed oe oo eb She a ee 21 SMBA MA MPE ssorreiercierietiisiyat bnn etr OE EEEN 22 Star IP Microprocessor and DSP Cores ccc csscesadagessdasneesneateeat ates 23 DCIS sigsiresrigsrredio dee 4h EN ASELA 24 Momay IP sccirieadririiei aibe a a peAa 24 Pondi y LIDET pikes chase nidi cee ESTERI EENIEDER SE IRRI ERD 24 Verification IP for Bus and VO Standards 4 204s 04scee see eane 25 Powmd Vernicahon IP i565 ce
266. ptimized parallel prefix architectures are generated using Datapath generator technology DW gensh This is ON by default in the Design Compiler flow The DC variable synlib_enable_dpgen must be set to true the default to make use of this Datapath technology 120 Synopsys Inc January 17 2005 DW02 tree Wallace Tree Compressor DesignWare IP Family DW0O2 tree Wallace Tree Compressor e Parameterized word length g o lt S gt o N a Table 1 Pin Description o Pin Name Width Direction Function 2 INPUT num_inputs x input_width bit s Input Input vector OUTO input_width bit s Output Partial sum OUTI input_width bit s Output Partial sum Table 2 Parameter Description Parameter Values Description num_inputs 21 Number of inputs input_width gt 1 Word length of OUTO and OUT1 Table 3 Synthesis Implementations Implementation Name Function License Feature Required wallace Wallace tree synthesis model DesignWare January 17 2005 Synopsys Inc 121 DesignWare IP Family Datapath Floating Point Overview Datapath Floating Point Overview gt Note The Floating Point IP are designed specifically for Module Compiler and do not work with Design Compiler The Floating Point components comprise a library of functions used to synthesize floating point computational circuits i
267. ption Parameter Values Description width 1 to 5122 Defines the width of the system and shadow registers and the input and output buses bld_shad_reg Oor1 Defines whether to build both the system and shadow registers bld_shad_reg 1 or just the system register bld_shad_reg 0 a The upper bound of the legal range is a guideline to ensure reasonable compile times 220 Synopsys Inc January 17 2005 DesignWare IP Family DW04_shad_reg Shadow and Multibit Register Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare g wn lt S gt D o N D gt D 5 January 17 2005 Synopsys Inc 221 DesignWare IP Family DW03_shftreg Shift Register DW03_shftreg Shift Register e Parameterized word length e Active low shift enable e Active low load enable Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Clock s_in 1 bit Input Serial shift input p_in length bit s Input Parallel input shift_n 1 bit Input Shift enable active low load_n 1 bit Input Parallel load enable active low p_out length bit s Output Shift register parallel output Table 2 Parameter Description Parameter Values Description length 21 Length of shifter Table 3 Synthesis Implementations I
268. pty and allowing the software to completely fill the FIFO each transmission sequence Synthesis selectable IrDA SIR mode support with up to 115 2 Kbaud data rate Programmable FIFO disabling External memory read enable signals for RAM wake up when external RAMs are selected Support for any serial data baud rate subject to the serial clock frequency as follows baud rate serial clock frequency 16 divisor Modem and status lines are independently controlled Extended diagnostic Loopback mode allows testing more Modem Control and Auto Flow Control features Also see the block diagram on the following page 282 Synopsys Inc January 17 2005 DW_apb_uart Two Clock Domains Note Generalized internal diagram not all signals are shown here DesignWare IP Family DW_apb_uart APB Universal Asynchronous Receiver Transmitter g Modem Status J Level Sync L Module aa Modem Registers yp Status and o APB Control N Interface a Serial Cntrl Control Reg Sync Z E E yt Uv and S Module Shadow statue Character Registers Timeout T Level Sync jag Character TX Module Ti
269. put 2 inverted input 0 padding in output 3 inverted input 1 padding in output a Inverted input refers to sh sh_tc and data_tc pins only January 17 2005 Synopsys Inc g m wo lt m gt 0 2 N D 2 D 5 109 DesignWare IP Family DW_ shifter Combined Arithmetic and Barrel Shifter Table 3 Synthesis Implementations Implementation Name Function License Feature Required mx2 Implement using 2 1 multiplexers only DesignWare mx2i Implement using 2 1 inverting DesignWare multiplexers and 2 1 multiplexers mx4 Implement using 4 1 and 2 1 DesignWare multiplexers mx8 Implement using 8 1 4 1 and 2 1 DesignWare multiplexers 110 Synopsys Inc January 17 2005 DW_square Integer Squarer e Parameterized word length e Unsigned and signed two s complement data operation DesignWare IP Family DW_square Integer Squarer a Z tc op lt gt X lt square z o N D g D a 2 5 Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Input data tc 1 bit Input Two s complement control 0 unsigned 1 signed square 2 x width bit s Output Product of a x a Table 2 Parameter Description Parameter Values Description width 21 Word length of a Table 3 Synthesis Implementations Implementat
270. put Priority vector from the clients of the arbiter bit s lock n bit s Input Active high signal to lock the grant to the current request By setting lock i 1 the arbiter is locked to the request i if it is currently granted For lock i 0 the lock on the arbiter is removed mask n bit s Input Active high input to mask specific clients By setting mask i 1 request i is masked For mask i 0 the mask on the request i is removed parked 1 bit Output Flag to indicate that there are no requesting clients and the grant of resources has defaulted to park_index granted 1 bit Output Flag to indicate that arbiter has issued a grant to one of the clients locked 1 bit Output Flags that the arbiter is locked by a client grant n bit s Output Grant output grant_index ceil logyn bit s Output Index of the requesting client that has been currently granted or the client designated by park_index in park_mode January 17 2005 Synopsys Inc 39 DesignWare IP Family DW_arbiter_2t Two Tier Arbiter with Dynamic Fair Among Equal Scheme Table 2 Parameter Description Parameter Values Description n 2 to 32 Number of arbiter clients Default 4 p_width 1 to5 Width of the priority vector of each client Default 2 park_mode 0or 1 park mode 1 includes logic to enable parking when no clients are Pea Saeed contains no logic for parking park_index 0 ton Index of the client use
271. put_mode includes registers at the outputs Default 1 output_mode 0 contains no output registers Table 3 Synthesis Implementations Implementation Name Function License Feature Required cla Carry look ahead synthesis model DesignWare clas Carry look ahead select synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 44 Synopsys Inc January 17 2005 DesignWare IP Family DW_arbiter_sp Arbiter with Static Priority Scheme DW_arbiter_sp Arbiter with Static Priority Scheme request mask lock e Parameterizable number of clients grant e Programmable mask for all clients grant_index e Park feature default grant to a client when no requests are pending granted e Lock feature ability to lock the currently granted client e Registered unregistered outputs parked Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Active low input reset request n bit s Input Input request from clients lock n bit s Input Active high signal to lock input By setting lock i 1 the arbiter is locked to the request i if it is cur
272. quest n bit s Input Input request from clients lock n bit s Input Active high signal to lock the grant to the current request By setting lock i 1 the arbiter is locked to the request 7 if it is currently granted For lock i 0 the lock on the arbiter is removed mask n bit s Input Active high input to mask specific clients By setting mask i 1 request z is masked For mask i 0 the mask on the request i is removed parked 1 bit Output Flag to indicate that there are no requesting clients and the grant of resources has defaulted to park_index granted 1 bit Output Flag to indicate that arbiter has issued a grant to one of the clients locked 1 bit Output Flags that the arbiter is locked by a client grant n bit s Output Grant output grant_index ceil log sn bit s Output Index of the requesting client that has been currently granted or the client designated by park_index in park_mode January 17 2005 Synopsys Inc 43 DesignWare IP Family DW_arbiter_fcfs Arbiter with First Come First Served Priority Scheme Table 2 Parameter Description Parameter Values Description n 2 to 32 Number of arbiter clients Default 4 park_mode 0or 1 park mode 1 includes logic to enable parking when no clients are Default 1 requesting and efau park_mode 0 contains no logic for parking park_index O ton Index of the client used for parking Default 0 output_mode 0 or 1 out
273. r e Captures the state of system registers dynamically during datain SyS_out system operation f SI shad_out e Serial access on shadow register to scan out the state of captured data e Constructed with multibit flip flop cells where possible can be used as a simple non shadowed multibit register e Parameterized width and number of registers one or two Table 1 Pin Description Pin Name Width Direction Function datain width bit s Input Data input driving the input to the system register sys_clk 1 bit Input Clock that samples the system register positive edge triggered shad_clk 1 bit Input Signal that clocks the output of the system register into the shadow register positive edge triggered reset 1 bit Input Asynchronous reset signal that clears the system and shadow registers SI 1 bit Input Serial scan input clocked by shad_clk when SE is high SE 1 bit Input Serial scan enable signal active high Enables scan only on the shadow register sys_out width bit s Output Output of the system register shad_out width bit s Output Parallel output of the shadow register that lags the system register by one cycle SO 1 bit Output Serial scan output from shadow register When SE is low represents the state of the MSB of the shadow register When SE is high each successive bit is shifted up one and SI is clocked into the LSB Table 2 Parameter Descri
274. r maximum performance power efficiency Separate 32 KB instruction and data caches Memory Management Unit with separate instruction and data micro TLB s Extensive hardware debug facilities incorporated into the IEEE 1149 1 JTAG port Timer facilities o 64 bit time base o Decrementer with auto reload capability o Fixed interval timer FIT o Watchdog timer with critical interrupt and or auto reset Multiple core interfaces defined by IBM s CoreConnect on chip system architecture o Processor local bus PLB interfaces o Auxiliary Processor Unit APU Port o Device Control Register DCR interface for independent access to on chip control registers JTAG Debug Reset and Trace interfaces Clock and power management CPM interface External interrupt controller EIC interface PLB to AHB bridge for integration into AMBA based systems O O O 0 O O O O 0 Synopsys Inc January 17 2005 DesignWare IP Family S lay lp DW_IBM440 IBM PowerPC 440 CPU Core a eo E rig DMA OCM Memory LCD OPB Bridge Controller Controller Controller Controller Bridge o 7 7 df Processor Local Bus PLB gt 2C Instr
275. r set during configuration of component Optional arbiter slave interface Optional internal decoder Programmable arbitration scheme Weighted token Programmable or fixed priority Fair Among Equals Arbitration for up to 15 masters Individual grant signals for each Support for split burst and locked transfers Optional support for early burst termination Configurable support for termination of undefined length bursts by masters of equal or higher priority Configurable or programmable priority assignments to masters Disabling of masters and protection against self disable Optional support for AMBA memory remap feature Optional support for pausing of the system immediately or when bus is IDLE Contiguous and non contiguous memory allocation options for slaves External debug mode signals giving visibility Also see the block diagram on the following page 266 Synopsys Inc January 17 2005 DesignWare IP Family DW_ahb Advanced High Performance Bus DW_ahb Parameterizable Parameterizable Master Ports Arbiter Slave Ports 0 m 2 Master 1 lt gt lt gt Slave 1 Q N 9 z o 5 Master 2 lt gt Slave2 Address and control MUX Write data MUX Master i lt gt Slave j Read data MUX i upto15 j upto15 Decoder internal The DesignWare DW_ahb Datab
276. r than 41 bits such as A_width B_width gt 41 the nbw implementation produces a Booth recoded multiplier identical to the wall implementation g m wo lt m gt D 2 N D 2 D 5 January 17 2005 Synopsys Inc 89 DesignWare IP Family DW02_mult_2_stage Two Stage Pipelined Multiplier DW02_mult_2 stage Two Stage Pipelined Multiplier e Parameterized word length e Unsigned and signed two s complement data operation e Two stage pipelined architecture e Automatic pipeline retiming e Inferable from Behavioral Compiler Table 1 Pin Description Pin Name Width Direction Function A A_width bit s Input Multiplier B B_width bit s Input Multiplicand TC 1 bit Input Two s complement control 0 unsigned 1 signed CLK 1 bit Input Clock PRODUCT A_width B_width bit s Output Product A x B Table 2 Parameter Description Parameter Values Description A_width 21 Word length of A B_width 2 For csa architecture A_width B_width 48 Word length of B Table 3 Synthesis Implementations Implementation Name Function License Feature Required csa gt Carry save array synthesis model DesignWare str Booth recoded Wallace tree synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the
277. rameterized word depth pusn_tu N push_error e Separate status flags for each clock system o pop_req_n data_out ae e FIFO empty half full and full flags pop_word_count pop_empty e Parameterized almost full and almost empty flag gt clk_pop Sap ste thresholds pop_hf e FIFO push error overflow and pop error underflow dhe pop_tu flags pop_error rst_n Table 1 Pin Description Pin Name Width Direction Function clk_push 1 bit Input Input clock for push interface clk_pop 1 bit Input Input clock for pop interface rst_n 1 bit Input Reset input active low push_req_n 1 bit Input FIFO push request active low pop_req_n 1 bit Input FIFO pop request active low data_in width bit s Input FIFO data to push push_empty 1 bit Output FIFO empty output flag synchronous to clk_push active ply Pp 8 SY push high push_ae l bit Output FIFO almost empty output flag synchronous to clk_push active high determined by push_ae_lvl parameter push_hf l bit Output FIFO half full output flag synchronous to clk_push active high push_af l bit Output FIFO almost full output flag synchronous to clk_push active high determined by push_af_lvl parameter push_full 1 bit Output FIFO full output flag synchronous to clk_push active high push_error bit Output FIFO push error overrun output flag synchronous to clk_push active high January 17 2005 Synopsys Inc 197 DesignWare IP Family DW_fifo_s2_sf Synchronou
278. rameterized word length e Carry in and carry out signals e Module Compiler Architectures g r wn lt S gt D o N D gt D 5 Table 1 Pin Description Pin Name Width Direction Function A width bit s Input Input data B width bit s Input Input data CI l bit Input Carry in SUM width bit s Output Sum of A B CD CO l bit Output Carry out Table 2 Parameter Description Parameter Values Description width gt 1 Word length of A B and SUM January 17 2005 Synopsys Inc 53 DesignWare IP Family DW01_add Adder Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model none cla Carry look ahead synthesis model none clf Fast carry look ahead synthesis model DesignWare bk Brent Kung architecture synthesis model DesignWare csm Conditional sum synthesis model DesignWare rpcs Ripple carry select architecture DesignWare clsa MC inside DW carry look ahead select DesignWare csat MC inside DW carry select DesignWare fastcla MC inside DW fast carry look ahead DesignWare pprefix MC inside DW flexible parallel prefix DesignWare pparch Delay optimized flexible parallel prefix DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force
279. range from 2 to 256 bits di a1qezisayyAs IMA e Accuracy conforms to IEEE 754 Floating Point standard Table 1 Pin Description Pin Name Width Direction Function A e f 1 bits Input Floating point number Z 3 to 512 bits Output Two s complement integer number STATUS optional 8 bits Output Status flags RND optional 3 bits Input Rounding mode Table 2 Parameter Description Parameter Values Description e 3 to 31 bits Word length of biased exponent of floating point number A f 2 to 253 bits Word length of fraction field of floating point number A arch 0 Architecture implementation a This component contains only one architecture Therefore the arch parameter should be set to 0 Table 3 Synthesis Implementations Implementation Name Function License Feature Required arch0 Synthesis model DesignWare January 17 2005 Synopsys Inc 129 DesignWare IP Family D Datapath Sequential Overview Datapath Sequential Overview This section documents the various Datapath Sequential IP found in the DesignWare Building Block IP 130 Synopsys Inc January 17 2005 DesignWare IP Family DW_div_seq Sequential Divider DW_div_seq Sequential Divider e Parameterized word length e Parameterized number of clock cycles e Unsigned and signed two s complement data division e R
280. rding and processing http www synopsys com products designware pciexpress html Synopsys Inc January 17 2005 C KY dwc_pcie_dualmode PCI Express RC EP Dual Mode Synthesizable Core DesignWare IP Family dwc_pcie_dualmode PCI Express RC EP Dual Mode Synthesizable Core The DesignWare RC EP Dual Mode PCI Express Core is a synthesizable solution that can be configured to address multiple applications ranging from server and desktop systems to mobile devices Other features include the following Compliant with PCI Express 1 0a Specification Modular design base core with additional support modules Architecture supports x1 x2 x4 x8 and x16 2 5Gbps lane configurations Available in 32 64 or 128 bit datapath widths Implementation supports 125MHz and 250MHz Dynamically configured Type 0 and 1 configuration space PIPE 8 bit 16 bit support Ultra low transmit and receive latency Configurable retry buffer size Configurable outstanding request support up to 32 lookup entries without RAM beyond 32 entries with RAM e Very high accessible bandwidth January 17 2005 Lane reversal and polarity inversion TX RX Configurable multi VCs multi traffic class support Configurable multi function support Packet sizes configurable max payload size 128B to 4KB and max request size up to 4KB Synopsys Inc Supports bypass cut through and store and forward request queues with PCIe credit managemen
281. re_usb1_device 355 dwcore_usb1_host 357 dwcore_usb1_hub 359 dwcore_usb2_device 366 dwcore_usb2_host 364 dwcore_usb2_hsotg 362 395 DesignWare IP Family dwcore_usb2_phy 368 DWMM See also DesignWare Memory Models DWMM See also Memory IP E enethub_fx 311 ethernet_monitor_vmt 310 ethernet_txrx_vmt 310 F FlexModels 322 Foundation Library See also Building Block IP Foundry Libraries See also DesignWare Foundry Libraries FPGA Compiler II 36 G GTECH Library Overview 263 I I2C Models 312 i2c_txrx_vmt 312 Interfaces SWIFT connection for SmartModels IP Synthesizable See also DesignWare Library Synthesizable IP L Licensing for Synopsys products 16 M Memory IP 291 Memory IP listing 24 Memory Models See also DesignWare Memory Models Microprocessors Microcontroller Cores Synopsys Inc January 17 2005 DesignWare IP Family Microprocessors Microcontroller Cores listing 23 24 Models behavioral 324 FlexModels 322 SmartModel behavioral simulation 324 VMT 320 Module Compiler 122 P PCI PCI X Bus Verification Models 316 PCI Express Models 314 pcie_txrx_vmt 314 pcimaster_fx 316 pcimonitor_fx 316 pcislave_fx 316 Q QuickStart features 287 288 QuickStart AMBA 288 R rmiirs_fx 311 S sata_device_vmt 317 sata_monitor_vmt 317 SCL 16 Serial ATA Models 317 Serial Input Output Interface Models 318 sio_monitor_vmt 318 sio_txrx_vmt 318 SmartModel Library SWIFT interface
282. rection Function rst_n 1 bit Input Reset active low cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low rw_addr ceil logs depth bit s Input Address bus data_in data_width bit s Input Input data bus data_out data_width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data_width 1 to 256 Width of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width rst_mode Oorl Determines if the rst_n input is used 0 rst_n initializes the RAM 1 rst_n is not connected Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare 238 Synopsys Inc January 17 2005 DesignWare IP Family Memory Stacks Memory Stacks This section documents the various DesignWare Building Block IP memory stacks g m wo lt m gt D 2 N D 2 D 5 January 17 2005 Synopsys Inc 239 DesignWare IP Family DW_stack Synchronous Single Clock Stack DW_stack Synchronous Single Clock Stack e Parameterized word width and depth data_in data_out e Stack empty and full status flags push reqzn ai e Stack error flag indicating underflow and overflow pop_req_n empty e Fully registered synchronous flag output ports error e A
283. rently granted For lock i 0 the lock on the arbiter is removed mask n bit s Input Active high input to mask specific clients By setting mask i 1 request i is masked For mask i 0 the mask on the request i is removed parked 1 bit Output Flag to indicate that there are no requesting clients and the grant of resources has defaulted to park_index granted 1 bit Output Flag to indicate that arbiter has issued a grant to one of the clients locked 1 bit Output Flags that the arbiter is locked by a client grant n bit s Output Grant output grant_index logyn bit s Output Index of the requesting client that has been currently issued the grant or the client designated by park_index in park_mode January 17 2005 Synopsys Inc 45 g rc 2 lt m gt D 2 N D 2 D 5 DesignWare IP Family 46 DW_arbiter_sp Arbiter with Static Priority Scheme Table 2 Parameter Description Parameter Values Description n 2 to 32 Number of arbiter clients Default 4 park_mode 0Oor 1 park mode 1 includes logic to enable parking when no Default 1 clients are requesting and park_mode 0 contains no logic for parking park_index 0 ton Index of the client used for parking Default 0 output_mode 0 or 1 output_mode includes registers at the outputs Default 1 output_mode 0 contains no output registers Table 3 Synthesis Implementations Implement
284. reversal and polarity inversion TX RX Configurable multi VCs multi traffic class support Packet sizes configurable max payload size 128B to 4KB and max request size up to 4KB Synopsys Inc Supports bypass cut through and store and forward request queues with PCIe credit management as well as configurable for infinite credits for all type of traffic Configurable ECRC generation and check Complete Root Port link training LTSSM Beacon and wake up mechanism Full Root Port PCI PM software and ASPM Full Advanced PCI Express Error Reporting All in band messages supported for RC Legacy MSI and MSI X interrupt support Configurable RC filtering rules for posted non posted and completion traffic Configurable BAR filtering IO filtering configuration filtering and completion lookup timeout for RC e Support for two application clients e In band and out of band access to configuration space registers and external user application registers with local bus controller January 17 2005 DesignWare IP Family C Ofo dwc_pcie_rootport S PCI Express Root Port Synthesizable Core e Supports external or internal transmit priority arbiter e Hot plug support More information is available at http www synopsys com products designware pciexpress html 010 MA January 17 2005 Synopsys Inc 348 DesignWare IP Family dwc_pcie_switchport PCI Express Switch Port Synthesizable Core dwc_pcie_sw
285. rpl Ripple carry synthesis model none bk Brent Kung synthesis model DesignWare cla Carry look ahead synthesis model DesignWare January 17 2005 Synopsys Inc 65 DesignWare IP Family DW01_cmp6 6 Function Comparator a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 66 Synopsys Inc January 17 2005 DW_cmp_dx Duplex Comparator Selectable single full width Compare or two smaller width Compare operations duplex Selectable number system unsigned or two s complement Parameterized full word width Parameterized partial word width allowing for asymmetric partial width operations Separate flags for Less Than Equal To and Greater Than Two sets of flags for duplex operation DesignWare IP Family DW_cmp_dx Duplex Comparator g r wn lt S gt D o N D D 5 Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Input data b width bit s Input Input data tc 1 bit Input Two s complement control dplx 1 bit Input Duplex mode select active high Itl 1 bit Output Part1 less than output condition eql 1 bit Output Part1 equal output condition
286. rt of RAM data_out data_out_width bit s Output FIFO data to pop 204 Synopsys Inc January 17 2005 DesignWare IP Family vine DW_asymfifoctl_s1_sf Asymmetric I O Synchronous Single Clock FIFO Controller with Static Table 2 Parameter Description Parameter Values Description data_in_width 1 to 256 Width of the data_in bus Values for data_in_width must be in an integer multiple relationship with data_out_width That is z either data_in_width K x data_out_width or data_out_width rc K x data_in_width where K is an integer L data_out_width 1 to 256 Width of the data_out bus data_out_width must be in an integer multiple relationship with data_in_width That is either O data_in_width K x data_out_width or data_out_width K N x data_in_width where K is an integer depth 2 to 224 Number of memory elements used in the FIFO 5 addr_width ceil log gt depth ae_level 1 to depth 1 Almost empty level the number of words in the FIFO at or below which the almost_empty flag is active af_level 1 to depth 1 Almost full level the number of empty memory locations in the FIFO at which the almost_full flag is active err_mode 0 to 2 Error mode Default 1 0 underflow overflow with pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode Oor 1 Reset mode Default 1 0 asynchronous reset 1 synchron
287. rt_SingleLayer This is a single layer subsystem This subsystem is an enhanced version of the QuickStart example that was included in the DesignWare AMBA 2004 05 release e QuickStart_MultiLayer This is a multi layer subsystem with DMA PCI USB ICM AHB bridge and other peripheral components The QuickStart_SingleLayer and QuickStart_MultiLayer subsystems include pre configured instances of DesignWare AMBA Bus IP and peripheral components as shown in the following figures respectively For more information about using DesignWare AMBA QuickStart refer to the DesignWare AMBA QuickStart_SingleLayer Guide and the DesignWare AMBA QuickStart_MultiLayer Guide which are available at http www synopsys com products designware docs 288 Synopsys Inc January 17 2005 DesignWare IP Family DesignWare AMBA QuickStart Collection of example designs for AMBA subsystems Testbench Clock AHB testbench v Configuration Generation Monitor and Stimulus z g i_intr2 i_memctl k memory y 0 AHB Master DW_ahb_ictl DW_memctl SRAM 2 BFM MyExtAhbMstr1 s3 intregs L SRAM mi mO sO o AHB Slave Pe 25 SDRAM gt BFM V APB Monitor Se i_remap DW b APB Slave MyExtApbSlv apb_rap BFM i_intr1 i_uart1 SIO BIM DW_apb_ictl DW_apb_uart see tests i_gpio I I i_uart2 DW
288. s Default 1 in the FIFO at which the almost_full flag is active err_mode 0 to2 Error mode Default 0 0 underflow overflow and pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode 0 to3 Reset mode Default 0 0 asynchronous reset including memory 1 synchronous reset including memory 2 asynchronous reset excluding memory 3 synchronous reset excluding memory Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cll Partial carry look ahead model DesignWare cl2 Full carry look ahead model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 196 Synopsys Inc January 17 2005 DesignWare IP Family vine DW _fifo_s2 sf Synchronous Dual Clock FIFO with Static Flags DW_fifo_s2_sf Synchronous Dual Clock FIFO with Static Flags push_word_count e Fully registered synchronous flag output ports asian a g e Single clock cycle push and pop operations push_req_n Push_ae a j push_hf lt e Parameterized word width push_af gt gt clk_push h full HA e Pa
289. s Dual Clock FIFO with Static Flags Tit Table 1 Pin Description Continued Pin Name Width Direction Function pop_empty 1 bit Output FIFO empty p output flag synchronous to clk_pop active high pop_ae l bit Output FIFO almost empty output flag synchronous to clk_pop active high determined by pop_ae_lvl parameter pop_hf l bit Output FIFO half full output flag synchronous to clk_pop active high pop_af l bit Output FIFO almost full output flag synchronous to clk_pop active high determined by pop_af_lvl parameter pop_full l bit Output FIFO full output flag synchronous to clk_pop active high pop_error 1 bit Output FIFO pop error underrun output flag synchronous to clk_pop active high data_out width bit s Output FIFO data to pop a As perceived by the push interface b As perceived by the pop interface Table 2 Parameter Description Parameter Values Description width 1 to 256 Width of the data_in and data_out buses Default 8 depth 4 to 256 Number of words that can be stored in FIFO Default 8 push_ae_lvl 1 to depth Almost empty level for the push_ae output port the number of Default 2 words in the FIFO at or below which the push_ae flag is active push_af_lvl 1 to deptht Almost full level for the push_af output port the number of Default 2 mpty memory locations in the FIFO at which the push_af fl
290. s Inc 303 DesignWare IP Family DesignWare AMBA AHB Models Master Slave Monitor Bus Interconnect DesignWare AMBA AHB Models Master Slave Monitor Bus Interconnect All Models AHB Bus Interconnect e Multiple command streams ahb_bus_vmt e Verilog VHDL or Vera testbenches Up to 15 Masters and 15 Slaves e Configurable message formatting Unlimited Slave memory maps e Event driven testbenches Priority based arbitration algorithm All types of Master transfers All types of Slave responses Configurable early burst termination and undefined length burst termination AHB Master ahb_master_vmt e Data width 8 1024 bits e Single or burst transfers e Burst rebuild capability e Constrained random test transactions using random file memory or FIFO data e Compare with expected data AHB Slave ahb_slave_vmt e OK Error Retry or Split responses Programmable wait states Configurable memory fill patterns FIFO memory at any memory location Constrained random test transactions using random file memory or FIFO data AHB Monitor ahb_monitor_vmt e Cycle based or transaction based event monitoring e Protocol checking e Incremental coverage reporting 304 Synopsys Inc January 17 2005 DesignWare IP Family DesignWare AMBA AHB Models Master Slave Monitor Bus Interconnect
291. s scanners digital audio devices electronic musical instruments digital VCRs VTRs and storage devices Other features include the following Silicon proven IEEE 1394 Link Layer Controller for both audio visual A V and non A V applications Support for common isochronous packet CIP headers time stamping and padded zeros for A V data transactions TEEE 1394 1995 and 1394a 2000 specification compliance IEC 61883 requirement for A V data streaming compliance Supports 100 200 400 Mbps data rates Full link layer implementation e Asynchronous isochronous and PHY January 17 2005 packet transmit and receive operations Cycle master and node controller capability Automatic isochronous resource manager detection Automatic acknowledge packet generation for received asynchronous packets Automatic 32 bit CRC generation and error detection interface Flexible 32 bit Virtual Component Interface VCI for host Asynchronous and isochronous FIFO interface with burst and non burst access modes Multi speed concatenated isochronous packet support Configurable number of isochronous transmit receive channels Status reporting by extensive maskable interrupt register set Supports inbound and outbound single phase retry protocol RapidScript custom IP configuration e Verilog source code Synopsys Inc Optional 1394 verification environment 372 010 MA DesignWare IP Family dwcore_1394_avlink Synthes
292. s Model DesignWare a The implementation rtl replaces the obsolete implementations rpl c11 and c12 tit License Feature Required Information messages listing implementation replacements SYNDB 37 may be generated by DC at compile time Existing designs that specify an obsolete implementation rpl cl1 and cl2 will automatically have that implementation replaced by the new superseding implementation rtl noted by an information message S YNDB 36 generated during DC compilation The new implementation is capable of producing any of the original architectures automatically based on user constraints 194 Synopsys Inc January 17 2005 Tit DesignWare IP Family DW_fifo_s1_sf Synchronous Single Clock FIFO with Static Flags DW_fifo_s1_sf Synchronous Single Clock FIFO with Static Flags e Fully registered synchronous flag output ports ac g e D flip flop based memory array for high testability Sinks a pop_req_n data_out lt e All operations execute in a single clock cycle full e FIFO empty half full and full flags almost_full N half_full fex e FIFO error flag indicating underflow overflow and diag_n almost_empty o pointer corruption empty x e Parameterized word width clk rtn emor e Parameterized word depth e Parameterized almost full and almost empty flags e Parameterized reset mode synchro
293. s a set of synthesizable building blocks that ASIC FPGA designers use to implement a complete USB OHCI Host Controller function Features include the following Silicon proven USB 1 1 compliant VCI AHB or Native interface Compatible with Open HCI 1 0 specification Verilog source code e Supports low speed and full speed devices e Configurable root hub supporting up to 15 downstream ports 357 Synopsys Inc Configuration data stored in Port Configurable Block Single 48 MHz input clock Simple application interface facilitates bridging the host to other system bus such as PCI and the integration of the controller with chipsets and microcontrollers Integrated DPLL Support for SMI interrupts Approximately 25K gates with 2 ports January 17 2005 DesignWare IP Family C Ofo dwcore_usb1_host S Synthesizable USB 1 1 OHCI Host Controller yN RCFG_RegData 32 APP_SADR oe Control APP_SData 3 List Processor Block ED amp TD Regs HCI Bus S o DF_Data 8 DF_Data 8 8 6 8 Ext FIFO Status lt HCF_Data FIFO_Data lt a go XT oO The dwcore_usb1_host data sheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwcore_usb1_host pdf 010 MA January 17 2005 Synopsys Inc 358 DesignWare IP Family dwcore_usb1_hub Synthesizable USB 1 1 Hub Controller dwcore_usb1_hub Synthesizable
294. s acne se eotsheos 6 6445e4s hOG Shoe 646s eRe aG 26 Danone Yornificaton LIMAY gd dh bd plc deed cee degs se bdedensdende gees bad 26 CI Ee ok bo E E one esssG ounce sreoin es FR653005006R se E 28 Desci n eA IP a2 cd nade eo eeeee a aa ee 30 Chapter 2 DesignWare Library pea La ee a gla eee eva arene arr vere Cem ireti ar gentry renner arar eGA 31 Pee INGER cictadscekeeuiisgsseentadese i seudeteddddieeeeeeensi ees 31 Building Block IP for DC QuickStart 22 4ccchbadeasibieieedeeastedar aece ns 32 Building Block IP in DC FPGA QuickStart sds icc cde ereeceeeetaeeeetesees 34 Building Block IP in FPGA Compiler I QuickStart 000 36 Application Specific Control Logic 2 2 cscciscieeivedindetievrsaeosiuediaaas 38 DW_arbiter_2t Two Tier Arbiter with Dynamic Fair Among Equal Scheme 39 DW_arbiter_dp Arbiter with Dynamic Priority Scheme 1 42 c62ccsacteceseesieasebavewane 4 DW_arbiter_fcfs Arbiter with First Come First Served Priority Scheme 04 43 DW_arbiter_sp Arbiter with Static Priority Scheme 66 ieun Ghee dda dine caw see sed dabiewes 45 January 17 2005 Synopsys Inc 3 Contents DesignWare IP Family Application Speciii Intetiace Overview 144254644 440544 6s sdses we deedeeees 47 DW_debugger i i eee nso 55s bo vet ws eaw ee EREEREER ESEE ENE EN 48 Datapath Generator OVeryieWw ocean del esceueo suede eset useedeceesdens ices 50 Datapath Arithmetic Overview lt i65e eos choses
295. s the fixed value of the parity bit from Default 1 the UART transmitter 48 Synopsys Inc January 17 2005 DesignWare IP Family DW_debugger On Chip ASCII Debugger Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare g m wo lt m gt D 2 N D 2 D 5 January 17 2005 Synopsys Inc 49 DesignWare IP Family Datapath Generator Overview Datapath Generator Overview The new datapath generators improve the quality of synthesized datapaths in two steps 1 By using more sophisticated extraction and partitioning of datapaths from RTL code 2 By improved synthesis of the extracted datapaths The following figure shows the flow for datapath synthesis After the RTL code is analyzed and elaborated by the Presto Verilog VHDL Compiler the datapath portions of the RTL are extracted by DC Ultra and then synthesized by the datapath generators in the DesignWare Library RTL Verilog VHDL Presto Verilog VHDL Compiler unmapped db DC Ultra Datapath Extraction DesignWare Library Datapath Generator Logic Optimization mapped db DC Ultra partitions datapaths that are extracted from RTL into large sum of product and product of sum blocks This reduces the number of expensive carry propagations to a minimum resulting in faster and smaller circuits In sum of products a multiplic
296. s the testbench of significant events such as transactions warnings and protocol errors SDA SCL Clock Slave Master Tx Rx FIFO FIFO x y y pushd_slave_tx_fifo read pop_slave_rx_fifo write Test Bench The DesignWare PC Verification IP Databook is available at http www synopsys com products designware docs 312 Synopsys Inc January 17 2005 DesignWare IP Family Memory Models Simulation models of memory devices Memory Models Simulation models of memory devices DesignWare Memory Models are pre verified simulation models of memory devices The DesignWare Memory Models are built on top of the Synopsys memory model technology thus ensuring model accuracy quality and reliability With thousands of pre verified memory models to choose from supporting over 30 memory vendors it s very easy to find a match to a systems memory requirement The models integrate with the simulator through the de facto industry standard SWIFT interface which is supported by all Synopsys simulators and by all other major simulator vendors Smarter verification is achieved by using the models debugging utilities You can search through the thousands of memory models using the memory model search capabilities offered as part of DesignWare Memory Central at http www synopsys com memorycentral DesignWare Memory Models provide the following
297. set excluding memory byte_order Oor 1 Order of send receive bytes or subword subword 8 bits subword Default 0 Within a word 0 first byte is in most significant bits position 1 first byte is in the least significant bits position valid for data_in_width data_out_width Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cll Partial carry look ahead model DesignWare cl2 Full carry look ahead model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 184 Synopsys Inc January 17 2005 DesignWare IP Family vine DW_asymfifo_s1_sf Asymmetric I O Synchronous Single Clock FIFO with Static Flags DW_asymfifo_s1_sf Asymmetric I O Synchronous Single Clock FIFO with Static Flags half_full e Parameterized asymmetric input and output bit widths diag n almost_empty must be integer multiple relationship e Fully registered synchronous flag output ports push_req_n data_out g data_i e D flip flop based memory array for high testability Sa ram_full a a m pop_req_n part wd lt e All operations execute in a single clock cycle z F flush_n full O e FIFO empty half full and full flags almost_full N
298. squarep Partial Product Integer Sguarter lt 2 cnciiestcget heed keeinesiadoesees ceed 113 DW_sart Ori Sguare ROO ooo ep eesaeec yee eeee eoase ee needeeeie ees 114 DW_sqrt_pipe Stallable Pipelined square fO01 4 452664 s4e ened eas dendebkan dened bas chats 115 DWO1_sub PUIG a con cena eS wenech bd thee eekseets Ghd ed wets cedseanesias 117 DW02_sum Umi aa ee eee eee see ee ee me ee er eee ere ee were ae 119 DW02_tree Wallace Tee Ue bho 6 se irar PERRA REER EPAI ESRAS SN 121 Datapath Floating Point Overview 22 0 6 06 cscs eden cece nennen 122 January 17 2005 Synopsys Inc 5 Contents DesignWare IP Family DW_1i2flt_fp Integer to Floating Point Converter lt 4 sa s64seseess0isbeee4e9eedee05 123 DW_add_fp Pia OO OE 5 been cheba Le een Se erase 124 DW_cmp_fp Floanne Point Une IE 2 be eeccececdin eter dcanioeedededesdeeeetsaud 125 DW_div_fp Pinte Pom et sg ogo oa Se 2 2rd heen e4sene aes 126 DW_mult_fp Pinging Point Moltiplief sockccctenas kes iadadeset ened isn ik nienn iea 128 DW_flt2i_fp Floating Point to Integer Converter ccess eckecee ee seers ecsaeosades 129 Datapath Seguential CVI 6 wks so eae Ki bw Cede ee henwdsd ss eew newer es 130 DW_div_seq See Ee hd HS ha AG 4H ON E E E 131 DW_mult_seq PHL Al MuUlUpIEr 2 253525ees cease nue has 6 400 34604e0055606 0808 133 DW_sqrt_seq Seguential Square ROG oc cs 6as oe ds bes OOS ENN S444 CORSO ds RRS eR 135 Datapath Trigonometrie Overview as vssh es eeeses
299. synchronous to clk_push for data_in_width lt data_out_width only otherwise tied low active high push_error 1 bit Output FIFO push error overrun output flag synchronous to clk_push active high pop_empty 1 bit Output FIFO empty output flag synchronous to clk_pop active high pop_ae 1 bit Output FIFO almost empty output flag synchronous to clk_pop determined by pop_ae_lvl parameter active high pop_hf 1 bit Output FIFO half full output flag synchronous to clk_pop active high pop_af 1 bit Output FIFO almost full output flag synchronous to clk_pop determined by pop_af_lvl parameter active high pop_full 1 bit Output FIFO s RAM full output flag excluding the input buffer of FIFO for case data_in_width lt data_out_width synchronous to clk_pop active high pop_error 1 bit Output FIFO pop error underrun output flag synchronous to clk_pop active high data_out data_out_width bit s Output FIFO data to pop 190 Synopsys Inc January 17 2005 DesignWare IP Family tit a As perceived by the push interface DW_asymfifo_s2_sf Asymmetric Synchronous Dual Clock FIFO with Static Flags b As perceived by the pop interface Table 2 Parameter Description Parameter Values Description data_in_width 1 to 256 Width of the data_in bus data_in_ width must in an
300. sys Inc January 17 2005 DesignWare IP Family R N Data Integrity Data Integrity This section documents the various DesignWare Building Block IP data integrity components g m wn lt S gt D o N D gt D 5 January 17 2005 Synopsys Inc 141 DesignWare IP Family DW_crc_p Universal Parallel Combinational CRC Generator Checker DW_crc_p Universal Parallel Combinational CRC Generator Checker Parameterized arbitrary polynomial up to 64 bit Parameterized data width up to 512 bits Parameterized initial CRC value all ones or all zeroes Parameterized inversion of generated CRC Parameterized bit and byte ordering Table 1 Pin Description Pin Name Width Direction Function data_in data_width bit s Input Input data used for both generating and checking for valid CRC crc_in poly_size bit s Input Input CRC value used to check a record not used when generating CRC from data_in crc_ok 1 bit Output Indicates a correct residual CRC value active high crc_out poly_size bit s Output Provides the CRC check bits to be appended to the input data to form a valid record data_in and crc_in Table 2 Parameter Description Parameter Values Description data_width 1 to 512 Width of data_in i e the amount of data that CRC Default 16 will be calculated upon poly_size 2 to 64 Size of the CRC polynomial and thus
301. t backward compatible with older components 1 during active init_rd_n input directly apply init_rd_val to data_in input with no clock cycle delay in calculating data_out Table 3 Synthesis Implementations Implementation Function License Feature Required rtl Synthesis model DesignWare January 17 2005 Synopsys Inc 153 DesignWare IP Family 00000000 oding DW_8b10b_unbal DW_8b10b_unbal 8b10b Coding Balance Predictor e Independent of Running Disparity data_in e Higher speed than a full encoder k_char ae e Predicts balance for both data and special characters Table 1 Pin Description Pin Name Width Direction Function k_char l bit Input Special character control input LOW for data characters HIGH for special characters data_in 8 bits Input Input for 8 bit data character to be encoded unbal l bit Output Unbalanced code character indicator LOW for balanced HIGH for unbalanced Table 2 Parameter Description Parameter Values Description k28_5_mode 0 or 1 Special Character subset control parameter Default 0 0 for all special characters available 1 for only K28 5 available when k_char HIGH regardless of the value on data_in Table 3 Synthesis Implementations Implementation Name Function License Feature Required rtl Synthesis model DesignWare 154 Synopsys
302. t as well as configurable for infinite credits for all type of traffic Configurable ECRC generation and check Complete upstream and downstream Link Training LTSSM Beacon and wake up mechanism Full upstream and downstream PCI PM software and ASPM Full Advanced PCI Express Error Reporting All in band messages supported for Endpoint and Root Port Legacy MSI and MSI X interrupt support Configurable RC and EP filtering rules for posted non posted and completion traffics Configurable BAR filtering IO filtering configuration filtering and completion lookup timeout for EP Support for two application clients In band and out of band access to configuration space registers and external user application registers with local bus controller 350 010 MA DesignWare IP Family dwc_pcie_dualmode Ne Qs PCI Express RC EP Dual Mode Synthesizable Core e Supports external or internal transmit priority arbiter e Supports expansion ROM e Hot plug removal legacy and native support More information is available at http www synopsys com products designware pciexpress html 351 Synopsys Inc January 17 2005 DesignWare IP Family OF 5 dwcore_pcie_phy PCI Express PHY Core dwcore_pcie_phy PCI Express PHY Core The DesignWare PCI Express PCI E PHY is a complete mixed signal semiconductor intellectual property IP solution designed for integration in both upstream and downstream applications Industry s
303. t Description Component Type DW_6811 8 Bit Microcontroller page 297 Synthesizable RTL DW8051 8 Bit Microcontroller page 299 Synthesizable RTL Memory IP Component Name Component Description Component Type Memory Models DesignWare contains thousands of pre verified Verification Models memory models with over 10 000 devices from more than 25 vendors page 313 DW_memctl DesignWare Memory Controller page 292 Synthesizable RTL DW_rambist DesignWare Memory BIST solution page 294 Synthesizable RTL DW Memory Building DesignWare Building Block IP contains many Synthesizable RTL Block IP memory related IP page 217 To view the complete DesignWare memory portfolio refer to the following http www synopsys com memorycentral Foundry Libraries Synopsys is teaming with foundry leaders to provide DesignWare Library licensees access to standard cells and I Os optimized for their process technologies starting with 0 15 0 13 micron and 90 nm Each library includes a complete set of front end and back end views The current offering includes the TSMC Libraries described on page 326 24 Synopsys Inc January 17 2005 DesignWare IP Family Chapter 1 Overview Verification IP for Bus and I O Standards Component Name Component Description Type ahb_bus_vmt DesignWare AMBA AHB Models page 304 Verification ahb_master_vmt ahb_monitor_vmt ahb_slave_vmt apb
304. t Input FIFO push request active low flush_n 1 bit Input Flushes the partial word into memory fills in 0 s for empty bits for data_in_width lt data_out_width only active low pop_req_n 1 bit Input FIFO pop request active low data_in data_in_width bit s Input FIFO data to push January 17 2005 Synopsys Inc 189 DesignWare IP Family DW_asymfifo_s2_sf Asymmetric Synchronous Dual Clock FIFO with Static Flags tit Table 1 Pin Description Continued Pin Name Width Direction Function push_empty 1 bit Output FIFO empty output flag synchronous to clk_push active high push_ae 1 bit Output FIFO almost empty output flag synchronous to clk_push determined by push_ae_lvl parameter active high push_hf 1 bit Output FIFO half full output flag synchronous to clk_push active high push_af 1 bit Output FIFO almost full output flag synchronous to clk_push determined by push_af_lvl parameter active high push_full 1 bit Output FIFO s RAM full output flag including the input buffer of FIFO for data_in_width lt data_out_width synchronous to clk_push active high ram_full 1 bit Output FIFO s RAM excluding the input buffer of FIFO for data_in_width lt data_out_width full output flag synchronous to clk_push active high part_wd 1 bit Output Partial word accumulated in the input buffer
305. t data_width bit s Output Output data bus Table 2 Parameter Description Parameter Values Description data_width 1 to 256 Width of data_in and data_out buses depth 2 to 256 Number of words in the memory array address width rst_mode Oor 1 Determines if the rst_n input is used O rst_n initializes the RAM l rst_n is not connected Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc 233 DesignWare IP Family 100111001 DW_ram_2r_w_a_dff RAM Write Port Dual Read Port RAM Flip Flop Based 01101001 DW_ram_2r_w_a_dff Write Port Dual Read Port RAM Flip Flop Based e Parameterized word depth rd1_addr A rd2_addr e Parameterized data width wr_addr e Asynchronous static memory data_in gata_rd1_out 3 cs_n e Parameterized reset implementation wrn Gata_td2_out e High testability using DFT Compiler test miedo gt test_clk rst_n Table 1 Pin Description Pin Name Width Direction Function rst_n 1 bit Input Reset active low cs_n 1 bit Input Chip select active low wr_n 1 bit Input Write enable active low test_mode 1 bit Input Enables test_clk test_clk 1 bit Input Test clock to capture data during test_mode rdl_addr ceil log depth bit s Input Read1 address bus rd2_addr ceil log depth bit
306. t_n p W Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Input reset active low request n bit s Input Input request from clients priority n ceil logsn bit s Input Priority vector from the clients of the arbiter lock n bit s Input Signal to lock the grant to the current request By setting lock i 1 the arbiter is locked to the request i if it is currently granted For lock i 0 the lock on the arbiter is removed mask n bit s Input Input to mask specific clients By setting mask i 1 request 7 is masked For mask i 0 the mask on the request i is removed parked 1 bit Output Flag to indicate that there are no requesting clients and the grant of resources has defaulted to client designated by park_index granted 1 bit Output Flag to indicate that the arbiter has issued a grant to one of the requesting clients locked 1 bit Output Flag to indicate that the arbiter is locked by a client grant n bit s Output Grant output grant_index log n bit s Output Index of the requesting client that has been currently granted or the client designated by park_index in park_mode January 17 2005 Synopsys Inc 41 DesignWare IP Family DW_arbiter_dp Arbiter with Dynamic Priority Scheme Table 2 Parameter Description Parameter Values Description n 2 to 32 Number of arbiter clients Default 4 park_mode O or 1 park mode 1 in
307. tandard PIPE interface and validated compatibility with the DesignWare PCI E Endpoint Controller enable easy integration of PCI E into a variety of applications ranging from server and desktop systems to mobile devices Other features include the following e Supports a wide range of e Supports all power down states for configurations including 1 0v amp 1 2v highly efficient operation core supplies and 2 5v amp 3 3v I O e Full support for beaconing receiver supplies detection and electrical idle e Supports a wide range of PCI E bus e Reliable link operation across channel widths up to x16 support manufacturing operation e Fully compliant with PCI E 1 0a and BER lt 10 18 1 0a Errata and PIPE interface to ensure interoperability and ease of integration with higher protocol levels More information is available at http www synopsys com products designware docs ds c DWC_pcie_phy htm1 010 MA January 17 2005 Synopsys Inc 352 DesignWare IP Family dwcore_sd_mmc_host Secure Digital SD and Multimedia Card MMC Host Controller dwcore_sd_mmc_host Secure Digital SD and Multimedia Card MMC Host Controller Bus Interface Features Supports AMBA AHB or APB interface Supports 16 32 or 64 bit data widths e Supports optional external DMA controllers for data transfers Does not generate split retry or error responses on the AMBA AHB bus Supports pin based little endian or big endian modes of AHB opera
308. tatic Coefficients 163 Logic Combinational OvervieW 2240icchccheiencdeaad east eakianse bastun 165 DW0O1_binenc Binary Bier 64h odeee ese kieane ke oo ieehes Geese ease de eee beas 166 DW01_decode Decodor ee ee ee ee ee eee ee ee ee eer eee re 167 DW01_mux_any Universal Malper sc te oenndesbaivass EEIE RI ER VERA EDN E LEN 168 DWO1_prienc POENE ag aes oe a ee ee 169 Logic eguental Oyemniew ech oe dG epee she beh ee ee ede ee hee dou ke 170 DW03_bictr_dcnto Up Down Binary Counter with Dynamic Count to Flag 171 DWO03_bictr_scnto Up Down Binary Counter with Static Count to Flag 0 0 172 DW03_bictr_decode Up Down Binary Counter with Output Decode 0 0 0 0 unen 173 DW_dpll_sd Digital Phase Locked Loop 2 62226424402s8eieesdudedsesisuweneee ages 174 DW03_Ifsr_dcnto LFSR Counter with Dynamic Count to Flag 0 0 000 ee eee 176 DW03_lfsr_scnto LFSR Counter with Static Count to Flag ss i 6s6i45 si ensase tiene des diced 177 DW03_lIfsr_load LFSR Counter with Loadable Input 6nn5 a0 hiSe eee bese weseaentewisd bes 178 DW03_Ifsr_updn LFSR ae os da aa a a a es 179 DW03_updn_ctr pow Ce 5 24 0455 0504085i0604 cG08 bes kE aeo hea ae a SS 180 ii FIRI ee 3 heen She eG ed ee 181 DW_asymfifo_s1_df Asymmetric I O Synchronous Single Clock FIFO with Dynamic Flag 182 DW_asymfifo_s1_sf Asymmetric I O Synchronous Single Clock FIFO with Static Flags 185 DW
309. teger multiple relationship with data_in_width That is either data_in_width K x data_out_width or data_out_width K x data_in_width where K is an integer depth 2 to 274 Number of memory elements used in the FIFO addr_width ceil log gt depth err_mode 0 to 2 Error mode Default 1 0 underflow overflow with pointer latched checking 1 underflow overflow latched checking 2 underflow overflow unlatched checking rst_mode Oor 1 Reset mode Default 1 0 asynchronous reset 1 synchronous reset byte_order Oor 1 Order of bytes or subword Default 0 subword lt 8 bits gt subword within a word 0 first byte is in most significant bits position 1 first byte is in the least significant bits position Table 3 Synthesis Implementations Implementation Name Function License Feature Required rpl Ripple carry synthesis model DesignWare cll Partial carry look ahead model DesignWare cl2 Full carry look ahead model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide 202 Synopsys Inc January 17 2005 DesignWare IP Family vine DW_asymfifoctl_s1_sf Asymmetric I O Synchronous Single Clock FIFO Controller with Static
310. terizable filter controls phase correction reactiveness from minor phase errors Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Reference clock rst_n 1 bit Input Asynchronous reset active low stall 1 bit Input Stalls everything except synchronizer active high squelch 1 bit Input Turns off phase detection When high no phase correction is carried out leaving DPLL free running active high window ceil log2 windows Input Sampling window selector data_in width bit s Input Serial input data stream clk_out 1 bit Output Recovered Clock bit_ready 1 bit Output Output data ready flag data_out width bit s Output Recovered output data stream a The minimum value must be 1 174 Synopsys Inc January 17 2005 E DesignWare IP Family DW_dpll_sd Digital Phase Locked Loop Table 2 Parameter Description Parameter Values Description width 1 to 16 Number of input serial channels Default 1 z divisor 4 to 256 Determines the number of samples per input clock cycle m Default 4 2 gain 1 to2 Phase correction factor for the absolute value of clock phase a Default 1 error greater than I1 N 1 50 phase correction z 2 100 phase correction 5 filter 0 to 8 Phase correction control for 1 clock phase error region Default 2 0 no correction 1 always correct For integer N gt
311. ters bypass_sel l bit Input Selects the bypass register active high sentinel_val width 1 bit s Input User defined status bits clock_dr 1 bit Output Clocks in data in asynchronous mode shift_dr 1 bit Output Enables shifting of data in both synchronous and asynchronous mode update_dr 1 bit Output Enables updating data in asynchronous mode tdo 1 bit Output Test data out tdo_en 1 bit Output Enable for tdo output buffer tap_state 16 bits Output Current state of the TAP finite state machine extest 1 bit Output EXTEST decoded instruction samp_load 1 bit Output SAMPLE PRELOAD decoded instruction instructions width bit s Output Instruction register output January 17 2005 Synopsys Inc 245 DesignWare IP Family DW_tap TAP Controller Table 1 Pin Description Continued Pin Name Width Direction Function sync_capture_en 1 bit Output Enable for synchronous capture sync_update_dr 1 bit Output Enables updating new data in synchronous_mode Table 2 Parameter Description Parameter Values Description width 2 to 32 Width of instruction register Default None id Oor 1 Determines whether the device identification register is Default 0 present 0 not present 1 present version 0 to 15 4 bit version number Default 0 part 0 to 65535 16 bit part number Default 0 man_num 0 to 2047 11 bit JEDEC manufacturer identity code man_num 127 Defau
312. the width of Default 16 crc_in and crc_out crce_cfg 0 to7 CRC initialization and insertion configuration Default 7 bit_order 0 to3 Bit and byte order configuration Default 3 poly_coef0 1 to 65535 Polynomial coefficients 0 through 15 Default 4129 poly_coefl 0 to 65535 Polynomial coefficients 16 through 31 Default 0 142 Synopsys Inc January 17 2005 DesignWare IP Family 1 01 DW_crc_p Universal Parallel Combinational CRC Generator Checker Table 2 Parameter Description Continued Parameter Values Description poly_coef2 0 to 65535 Polynomial coefficients 32 through 47 Default 0 poly_coef3 0 to 65535 Polynomial coefficients 48 through 63 Default 0 a poly_coefO must be an odd number since all primitive polynomials include the coefficient 1 which is equivalent to x b CCITT CRC16 polynomial is X16 X12 X5 1 thus poly_coef0 212 25 1 4129 g m wo lt m gt D 2 N D 2 D 5 Table 3 Synthesis Implementations Implementation Name Implementation License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc 143 DesignWare IP Family DW_crc_s Universal Synchronous Clocked CRC Generator Checker DW cre s Universal Synchronous Clocked CRC Generator Checker e Parameterized arbitrary polynomial up to 64 bit data_in data_out e Parameterized data width up to polynomial siz
313. thesizable JPEG CODEC DesignWare IP Family dwcore_jpeg_codec Synthesizable JPEG CODEC The Synopsys DesignWare JPEG CODEC is part of an SoC based multimedia solution that enables fast and simple image compression and decompression The simplicity of the design allows for easy SoC integration high speed operation and suitability for multimedia and color printing applications Individual Encoder and Decoder products are available from Synopsys Other JPEG CODEC features include the following 100 baseline ISO IEC 10918 1 JPEG compliant Verified in hardware e 8 bit channel pixel depths January 17 2005 Up to four programmable quantization tables Single clock Huffman coding and decoding Fully programmable Huffman tables two AC and two DC Fully programmable Minimum Coded Unit MCU Encoding decoding support non simultaneous Single clock per pixel encoding and decoding according to the JPEG baseline algorithm Hardware support for restart marker insertion Synopsys Inc Support for single grayscale components Support for up to four channels of component color Internal register interface Fully synchronous design Available as fully functional and synthesizable VHDL or Verilog Includes testbench Simple external interface Four channel interface Low gate count total gate count is 35K gates Stallable design 376 010 MA DesignWare IP Family dec
314. tically receive CDs for the latest major release or from any Synopsys sales office or at the following location http www synopsys com products fpga Setting Up DesignWare Building Block IP in FPGA Compiler Il DesignWare Building Block IP components are automatically installed by default during the installation of FPGA Compiler II versions 3 2 and later You can choose to not install DesignWare Building Block IP by unchecking DesignWare in the FPGA Vendors dialog box during installation Otherwise there is nothing equivalent to the synopsys_dc setup file for Design Compiler to modify License Requirement FPGA Compiler II versions 3 2 to 3 3 require a valid DesignWare Library license in order to implement all DesignWare Building Block IP Beginning in FPGA Compiler II version 3 5 DesignWare Building Block basic IP can be implemented without the requirement of a DesignWare Library license The basic IP include the following DWO1_cmp2 DWO1_cmp6 DWOl1_absval DWO1_add DWO1_sub DWOl1_addsub DWOIL_inc DWO1_dec DWO1_incdec DWO2_mult 36 Synopsys Inc January 17 2005 DesignWare IP Family Chapter 2 DesignWare Library Synthesizable IP Accessing DesignWare Building Block IP in FPGA Compiler Il You can access DesignWare Building Block IP in FPGA Compiler II versions 3 2 and later by direct instantiation For example In Verilog DWO2 mult inst_A width inst _B width U1 A inst_A B inst_B TC inst TC PRODUCT inst PRODUCT In
315. ting of data in both synchronous and asynchronous mode update_dr 1 bit Output Enables updating data in asynchronous mode tdo 1 bit Output Test data out tdo_en 1 bit Output Enable for tdo output buffer tap_state 16 bits Output Current state of the TAP finite state machine instructions width bit s Output Instruction register output sync_capture_en 1 bit Output Enable for synchronous capture sync_update_dr 1 bit Output Enables updating new data in synchronous_mode Table 2 Parameter Description Parameter Values Description width 2 to 32 Width of instruction register Default None id O or 1 Determines whether the device identification register is Default 0 present 0 not present 1 present idcode_opcode 1 tg 2Wwidth 1 Opcode for IDCODE Default 1 version 0 to 15 4 bit version number Default 0 248 Synopsys Inc January 17 2005 DesignWare IP Family DW_tap_uc TAP Controller with USERCODE support Table 2 Parameter Description Continued Parameter Values Description part 0 to 65535 16 bit part number Default 0 man_num 0 to 2047 11 bit JEDEC manufacturer identity code man_num 127 Default 0 sync_mode O or 1 Determines whether the bypass device identification and Default 0 instruction registers are synchronous with respect to tck 0 asynchronous synchronous g 2 lt m gt 0 2 N D 2 D 5 Table 3 Synth
316. tion Supports separate clocks for bus interface and card interface Supports multiple or combined single FIFO for transmit and receive operations Supports from 4 to 4096 configurable FIFO depths FIFO controller shipped with a flip flop based single clock dual port synchronous read and synchronous write RAM Supports FIFO over run and under run prevention by stopping card clock Verification Environment Features 353 AMBA SD memory SDIO and MMC bus functional models BFMs and AHB monitors Constrained random and directed tests Configurable and self checking testbench and test suites in Vera Synopsys Inc C KN Card Interface Features Can be configured as MMC only controller or SD_MMC controller Supports 1 to 30 MMC cards or 1 to 16 SD cards Supports 1 bit 4 bit and 8 bit cards Supports CRC generation and error detection Supports programmable baud rate Provides ON or OFF clock control Supports power management and power switch Supports host pull up control Supports card detection and initialization Supports write protection Supports 1 bit and 4 bit SDIO interrupts Supports SDIO suspend resume and read wait Supports 1 to 65 535 byte block size Example Linux Demonstration Features DW_sd_mmc controller specific host driver APIs DW_sd_mmc controller independent SD MMC protocol specific bus driver APIs January 17 2005 DesignWare IP Family C Og dwcore_sd_mmc_host
317. tion chip Compatible with the Synopsys USB 2 0 Device and Host components USB 2 0 Device automatic switching between full and high speed modes Host Device automatic switching between full high and low speed modes Synopsys Inc Designed for minimal power dissipation for low power and bus powered devices Low power design enables host enumeration of an unpowered device Sea wall and decoupling structures reduce on chip noise Suspend Resume and Remote Wake up mode support USB 2 0 test mode support Additional built in analog testability features USB Implementers Forum certified 368 010 MA DesignWare IP Family dwcore_usb2_phy 4 Qs USB 2 0 Transceiver Macrocell Interface PHY Bias Test SYNC Bit Interface Detector Unstuffer Crystal I i Osc P HS FS LS HS NRZI Rx Shift XO Receivers gt HS DLL Decoder and Hold PLL I Squelch Elasticity Disconnect Buffer pecole tate Clock Buffers Mache Common x U Block Fi teat Control l y ransmitter Logi Local Bias gt FS DPLL 2J l FS v D D D D Transmit Pull up State Pull down Machine Logic HS NRZI Bit Tx Shift HS FS LS Enco
318. to common hard macro or compiled ASIC dual port synchronous RAMs Table 1 Pin Description Pin Name Width Direction Function clk 1 bit Input Input clock rst_n 1 bit Input Reset input active low asynchronous if rst_mode 0 synchronous if rst_mode 1 push_req_n 1 bit Input FIFO push request active low flush_n 1 bit Input Flushes the partial word into memory fills in 0 s for data_in_width lt data_out_width only pop_req_n 1 bit Input FIFO pop request active low diag_n 1 bit Input Diagnostic control active low for err_mode 0 NC for other err_mode values data_in data_in_width bit s Input FIFO data to push 200 Synopsys Inc January 17 2005 Tit DesignWare IP Family DW_asymfifoctl_s1_df Asymmetric I O Synchronous Single Clock FIFO Controller with Table 1 Pin Description Continued Pin Name Width Direction Function rd_data max data_in_width Input RAM data input to FIFO controller data_out_width bit s ae_level ceil log depth bit s Input Almost empty level the number of words in the FIFO at or below which the almost o _empty flag is active E af_thresh ceil log depth bit s Input Almost full threshold the number of words a stored in the FIFO at or above which the N almost_full flag is active w_en 1 bit Output Write enable output for write port of RAM 5 active low empty 1 bit Output FIFO
319. to indicate the output data or feedback data is in saturation Table 2 Parameter Description Parameter Values Description data_in_ gt 2 Default 8 Input data word length width data_out_ 22 Default 16 Width of output data This parameter should also satisfy width the following equation data_out_width lt maximum feedback_width data_in_width frac_data_out_width max_coef_width 3 frac_coef_width frac_data_ O to data_out_width Width of fraction portion of data_out out_width Default 4 feedback_ 2 2 Default 12 Width of feedback_data feedback_data is internal to the width lt model gt max_coef_ 2 2 Default 8 Maximum coefficient word length width frac_coef_ 0 to max_coef_width 1 Width of the fraction portion of the coefficients width Default 4 saturation_ 0 or 1 Default 0 Controls the mode of operation of the saturation output mode out_reg 0 or 1 Default 1 Controls whether data_out and saturation are registered January 17 2005 Synopsys Inc 161 DesignWare IP Family DW_iir_dc High Speed Digital IIR Filter with Dynamic Coefficients Table 3 Synthesis Implementations Implementation Name Function License Required mult Structural synthesis model DesignWare 162 Synopsys Inc January 17 2005 DesignWare IP Family DW_iir_sc High Speed Digital IIR Filter with Static Coefficients DW_liir_sc High Speed Digital IIR Filter wit
320. tr Booth recoded Wallace tree synthesis model DesignWare a During synthesis Design Compiler will select the appropriate architecture for your constraints However you may force Design Compiler to use one of the architectures described in this table For more details please refer to the DesignWare Building Block IP User Guide b The csa implementation is only valid when the sum of A_width and B_width lt A8 bits as it has no area benefit beyond 48 bits 92 Synopsys Inc January 17 2005 License Feature Required DesignWare IP Family DW02_mult_4_stage Four Stage Pipelined Multiplier DW02_mult_4 stage Four Stage Pipelined Multiplier e Inferable from Behavioral Compiler e Parameterized word length g e Unsigned and signed two s complement data operation a e Four stage pipelined architecture e Automatic pipeline retiming N o v Table 1 Pin Description Pin Name Width Direction Function A A_width bit s Input Multiplier B B_width bit s Input Multiplicand TC 1 bit Input Two s complement control 0 unsigned 1 signed CLK 1 bit Input Clock PRODUCT A_width B_width bit s Output Product A x B Table 2 Parameter Description Parameter Values Description A_ width gt 1 Word length of A B_ width gt For csa architecture A_width B_width lt A8 Word length of B Table 3 Synthesis Implementations
321. troller page 276 Synthesizable RTL DW_apb_rap APB Remap amp Pause page 277 Synthesizable RTL DW_apb_rtc APB Real Time Clock page 278 Synthesizable RTL DW_apb_ssi APB Synchronous Serial Interface page 279 Synthesizable RTL DW_apb_timers APB Timer page 281 Synthesizable RTL DW_apb_uart APB UART page 282 Synthesizable RTL DW_apb_wadt APB Watch Dog Timer page 286 Synthesizable RTL DW_memctl Memory Controller page 292 Synthesizable RTL ahb_bus_vmt AHB Bus Interconnect page 304 Verification Models ahb_master_vmt AHB Master page 304 ahb_monitor_vmt AHB Monitor page 304 ahb_slave_vmt AHB Slave page 304 apb_master_vmt APB Master page 306 Verification Models apb_monitor_vmt APB Monitor page 306 apb_slave_vmt APB Slave page 306 22 Synopsys Inc January 17 2005 DesignWare IP Family Chapter 1 Overview Component Name DesignWare AMBA 2 0 Component Description Component Type axi_master_vmt axi_slave_vmt axi_monitor_vmt axi_interconnect_vmt DesignWare VIP for AMBA 3 AXI page 307 Verification Models DesignWare AMBA Connect DesignWare AMBA Connect page 287 is a highly flexible integrated and feature rich design environment that allows you to select configure interconnect simulate and synthesize DesignWare AMBA synthesizable IP and verification IP VIP DesignWare AMBA QuickStart The DesignWare AMBA QuickStart page 288 is a collection of ex
322. uary 17 2005 DW_bc_7 Boundary Scan Cell Type BC_7 e IEEE Standard 1149 1 compliant e Synchronous or asynchronous scan cells with respect to tck e Supports the standard instructions EXTEST SAMPLE PRELOAD and BYPASS e Supports the optional instructions INTEST RUNBIST CLAMP and HIGHZ DesignWare IP Family DW_bc_7 Boundary Scan Cell Type BC_7 shift_dr mode1 ic_input mode2 data_out si so pin_input control_out g m wo lt m gt D 2 N D D 5 output_data capture_en update_en update_clk capture_clk Table 1 Pin Description Pin Name Width Direction Function capture_clk 1 bit Input Clocks data into the capture stage update_clk 1 bit Input Clocks data into the update stage capture_en bit Input Enable for data clocked into the capture stage active low update_en 1 bit Input Enable for data clocked into the update stage active high shift_dr 1 bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo model 1 bit Input Determines whether data_out is controlled by the boundary scan cell or by the output_data signal mode2 1 bit Input Determines whether ic_input is controlled by the boundary scan cell or by the pin_input signal Si 1 bit Input Serial path from the previous boundary scan cell pin_input 1 bit Input IC system input pin control_out 1 bit Input Control sig
323. ubsystem Clock Control Enable Block Generator gt Clock Enables C166S Subsystem Block Diagram Also see the following web page for additional information http www synopsys com products designware starip infineon_c166s html January 17 2005 Synopsys Inc 384 DesignWare IP Family DW_TriCore1 TriCore1 32 Bit Processor Core from Infineon DW_TriCore1 TriCore1 32 Bit Processor Core from Infineon RA Infineon s TriCore is the first unified MCU DSP architecture in a single core This core is ideally suited to SoC applications that require both microcontroller and DSP functionality together with high performance low cost and minimal power consumption TriCore meets the needs of automotive industrial mass storage and communications applications where TriCore based ASSP silicon devices from Infineon are already successful Other features include the following 32 bit load Store Harvard Architecture e 4 GB address range e General Purpose Register Set GPRS 385 o Sixteen 32 bit data registers Dx o Sixteen 32 bit address registers Ax o Three 32 bit status amp program counter registers PSW PC PCXI Shadow registers for fast context switching Automatic context save on entry and restore on exit for subroutine interrupt amp trap Two memory protection register sets Instruction formats 16 bit and 32 bit Byte amp bit addressing Saturation integer arithmetic Packed data Data and
324. uction Cache Data Cache PLB With Parity With Parity PLB ies Floating I ii I Point n MN oO Unit I Cache Controller p 4 entry with gt Load Store Queues a Program FPU oT parity a 5 lt gt Vo or EBU Y D Cache Controller Auxiliary Instruction Unit Branch Unit aK DCR Bus 2 Processor nstruction Uni Target gt le Unit Address BHT is T Slee APU Dispatch Dispatch Cache Trace og 2 I p3 Y D 4 Firewire Interrupt GPR and Z Integer File Integer ay gt Load Timers 5 vA Gait ae amp gt SmartCard O MAC Clock and OPB Pi Mgmt 4 gt Master PowerPC 440 CPU OPB Slave DesignWare IBM PowerPC 440 CPU Block Diagram Also see the following web page for additional information http www synopsys com products designware starip ibm_powerpc html January 17 2005 Synopsys Inc 380 DesignWare IP Family DW_V850E Star V850E Microcontroller Core from NEC Electronics DW_V850E Star V850E Microcontroller Core from NEC Electronics RA The NEC V850E is a highly configurable fully synthesizable RISC architecture microcontroller The V850E core is ideal for applications that require high performance low cost and minimum power consumption In addition the excellent processing horsepower of this 32 bit processor is perfect for new applications that need more than a 16 bit processor can provide Other features include the following Fully compatible with
325. ue the default to make use of this Datapath technology 112 Synopsys Inc January 17 2005 DW_squarep Partial Product Integer Squarer e Parameterized word lengths e Unsigned and signed two s complement data DesignWare IP Family DW_squarep Partial Product Integer Squarer g m 2 operation lt gt D 2 N D o 5 Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Multiplier tc 1 bit Input Two s complement control 0 unsigned 1 signed out0 width x 2 Output Partial product of a x a bit s out 1 width x 2 Output Partial product of a x a bit s Table 2 Parameter Description Parameter Values Description width 21 Word length of signal a Table 3 Synthesis Implementations Implementation Name Function License Feature Required Wallace tree synthesis mode DesignWare January 17 2005 Synopsys Inc 113 DesignWare IP Family DW_saqrt Combinational Square Root DW_sart Combinational Square Root e Parameterized word length e Unsigned and signed two s complement square root computation Table 1 Pin Description Pin Name Width Direction Function a width bit s Input Radicand root int width 1 2 bit s Output Square root Table 2 Parameter Description Parameter Values Descriptio
326. ue Mem lAck r Ack Queue I Queue TL Link PHY I PHY Link TL Rx ees Tx Results Queue L P T Queue Buffer iF MH a M4 E v viv PCI Express Monitor pcie_monitor_vmt TL Header Data LL Seq Header Data CRC Transaction and Symbol PHY STP Seq Header Data CRC END Log Files The DesignWare PCI Express Verification IP Databook 1s available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 315 DesignWare IP Family PCI PCI X Bus Models Master Slave and Monitor PCI PCI X Bus Models Master Slave and Monitor The Synopsys PCI PCI X FlexModel set consists of three separate PCI PCI X FlexModels and a set of system level testbenches The models support the PCI 2 3 and the PCI X 1 0 and 2 0 specifications e pcimaster_fx Performs timing violation checks and emulates the protocol of PCI PCI X initiators at the pin and bus cycle levels Initiates read and write cycles In PCI X mode pcimaster_fx can function as a target for split transactions e pcislave_fx Responds to cycles initiated by the pcimaster_fx model or by the user s PCI master device In PCI X mode the pcislave_fx also functions as an initiator for split transactions e pcimonitor_fx Monitors logs and arbitrates activity on the PCI or PCI X bus e PCI and PCI X system testbenches Provides ready to use example testbenches for both conventional PCI m
327. upt polarity Selects serial clock phase of SPI format directly after reset 279 DesignWare IP Family DW_apb_ssi APB Synchronous Serial Interface DW_apb_ssi Transmit FIFO Shift APB Interface Control Control Logic Receive FIFO Control Register Block Interrupt Transmit Logic FIFO Memory DMA Interface Receive FIFO Clock FSM Control The DesignWare DW_apb_ssi Databook 1s available at http www synopsys com products designware docs 280 Synopsys Inc January 17 2005 DesignWare IP Family DW_apb_timers APB Programmable Timers DW_apb_timers APB Programmable Timers e Up to eight programmable timers e Configurable option for a single or Z e Configurable timer width 8 to 32 bits combined interrupt output flag 7 e Support for two operation modes e Configurable option to have read write E free running and user defined count coherency registers for each timer H e Support for independent clocking of e Configurable option to include timer X timers toggle output which toggles each time A counter reloads e Configurable polarity for each individual interrupt DW_apb_timers pclk ___ presetn APB psel Interface paddrf timer_N_clk timer_N_resetn scan_mode __ gt timer_en gt timer_intr gt timer_intr_n timer_intr_flag
328. upts e Configurable hardware and software e GPIO Component Type register control for each port or for each bit of each port e GPIO Component Version register ae e Configurable reset values on output e Separate auxiliary data input data amp P orts output and data control for each I O in P Hardware Control mode DW_apb_gpio External Data j gt Port N xpins 0 t interface j gt Interface AuxData p a Interrupt Interrupts Detection The DesignWare DW_apb_gpio Databook is available at http www synopsys com products designware docs 274 Synopsys Inc January 17 2005 DesignWare IP Family DW_apb_i2c APB I C Interface DW_apb_i2c APB I C Interface e Two wire C serial interface e Ignores CBUS addresses an older z e Three speeds ancestor of I7C that used to share the a 2 Ss o Standard mode 100 Kb s IC bus o Fast mode 400 Kb s e Transmit and receive buffers g o High speed mode 3 4 Mb s e Interrupt or polled mode operation a apposen gynnan e Handles Bit and Byte waiting at all bus 5 e Master or slave I7C operation speeds e Supports multi Master operation bus e Simple software interface consistent arbitration with DesignWare APB peripherals e 7 or 10 bit addressing e Digital filter for the received SDA and e 7 or 10 bit combined format transfers SCL lines e Slave bulk transfer mode e Support
329. ut Enable for data clocked into the update stage active high shift_dr l bit Input Enables the boundary scan chain to shift data one stage toward its serial output tdo mode 1 bit Input Determines whether data_out is controlled by the boundary scan cell or by the data_in signal si l bit Input Serial path from the previous boundary scan cell pin_input 1 bit Input IC system input pin output_data 1 bit Input IC output logic signal ic_input l bit Output Connected to IC input logic data_out l bit Output Output data SO 1 bit Output Serial path to the next boundary scan cell January 17 2005 Synopsys Inc 257 DesignWare IP Family DW_bc_8 Boundary Scan Cell Type BC_8 Table 2 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model or Test IEEE STD 1149 1 258 Table 3 Simulation Models Model Function DW04 DW_BC_8_CFG_SIM Design unit name for VHDL simulation dw dw04 src DW_bc_8_sim vhd VHDL simulation model source code dw sim_ver DW_bc_8 v Verilog simulation model source code Synopsys Inc January 17 2005 DesignWare IP Family DW_bc_9 Boundary Scan Cell Type BC_9 DW_bc_9 Boundary Scan Cell Type BC_9 Last Revised Release DWF_0212 e IEEE Standard 1149 1 2001 compliant pin_input l o si e Synchronous or asynchronous scan cells with respect to
330. versal Asynchronous Receiver Transmitter DW_apb_wdt page 286 APB Watch Dog Timer A brief introduction to the AMBA On Chip Bus can be found at the following location http www synopsys com products designware dw_amba html DesignWare AMBA Connect DesignWare AMBA Connect page 287 is a highly flexible integrated and feature rich design environment that allows you to select configure interconnect simulate and synthesize DesignWare AMBA synthesizable IP and verification IP VIP 264 Synopsys Inc January 17 2005 DesignWare IP Family DesignWare AMBA QuickStart The DesignWare AMBA QuickStart page 288 is a collection of example designs for AMBA subsystems built with DesignWare AMBA On chip Bus components The QuickStart example designs are static non reconfigurable examples of complete subsystems that use DesignWare AMBA IIP and VIP components g m wo lt m gt 0 o N D D 5 January 17 2005 Synopsys Inc 265 DesignWare IP Family DW_ahb Advanced High Performance Bus DW_ahb Advanced High Performance Bus Compliance with the AMBA Specification Rev 2 0 Configuration of AMBA Lite system e Configuration of up to 15 masters in a non AMBA Lite system Configuration of up to 15 slaves e Configuration of data bus width of up to 256 bits System address width of 32 or 64 bits Configuration of system endianness big or little endian can be controlled by external input o
331. w 322 DesignWare Foundation Library See also Building Block IP DesignWare Foundry Libraries 326 DesignWare GTECH Library 263 DesignWare Hard IP dwcore_pcie_phy 352 DesignWare IP Family overview 19 DesignWare Library Synthesizable IP 31 AMBA On chip Bus Logic and Peripherals 264 Building Block IP 31 DW_6811 297 DW_ahb 266 DW_ahb_dmac 268 DW_ahb_eh2h 269 DW_ahb_h2h 284 DW_ahb_icm 271 DW_ahb_ictl 272 DW_apb 273 DW_apb_gpio 274 DW_apb_i2c 275 Synopsys Inc 392 DesignWare IP Family DW_apb_ictl 276 DW_apb_rap 277 DW_apb_rtc 278 DW_apb_ssi 279 DW_apb_timers 281 DW_apb_uart 282 DW_apb_wadt 286 DW_memctl 292 DW_rambist 294 DW8051 299 Memory IP 291 DesignWare Library Verification IP overview 301 DesignWare Memory Models features 313 overview 313 DesignWare Silicon Libraries TSMC Libraries 326 DesignWare Star IP overview 378 DesignWare Synthesizable Core dwe_pcie_dualmode 350 dwc_pcie_endpoint 345 dwc_pcie_rootport 347 dwc_pcie_switchport 349 dweore_1394_avlink 372 dweore_1394_cphy 374 dwcore_ethernet 333 dwcore_ethernet_sub 335 dwcore_gig_ethernet 337 dwcore_gig_ethernet_sub 339 dwcore_jpeg_codec 376 dwcore_pci 341 dweore_pcix 343 dwcore_usb1_device 355 dwcore_usb1_host 357 dwcore_usb1_hub 359 dwcore_usb2_device 366 dwcore_usb2_host 364 dwcore_usb2_hsotg 362 DesignWare VMT Models overview 320 DSP Library Overview 263 DW_6811 297 DW_8b10b_dec 150 DW_8b10b_enc 152 DW_8b10b_unbal 154 January 17 2005 In
332. width 23 Word length of b tc_mode Oor 1 Two s complement control Default 0 0 unsigned 1 two s complement num_cyc 23 and lt a_width User defined number of clock cycles to produce a valid Default 3 result The real number of clock cycles depends on various parameters rst_mode Oor 1 Reset mode Default 0 0 asynchronous reset 1 synchronous reset January 17 2005 Synopsys Inc 133 DesignWare IP Family DW_mult_seq Sequential Multiplier Table 2 Parameter Description Continued Parameter Values Description input_mode Oor 1 Registered inputs Default 1 0 no 1 yes output_mode Oor 1 Registered outputs Default 1 0 no 1 yes early_start 0 or 1 Computation start Default 0 0 start computation in the second cycle 1 start computation in the first cycle Table 3 Synthesis Implementations Implementation Function License Feature Required cpa Carry propagate adder synthesis model DesignWare 134 Synopsys Inc January 17 2005 DesignWare IP Family DW_sqrt_seq Sequential Square Root DW_sart_seq Sequential Square Root e Parameterized word length e Parameterized number of clock cycles e Unsigned and signed two s complement square roots e Registered or un registered inputs and outputs g m 7 lt m gt 0 2 N D 2 D 5 Note that data input is taken as absolute value
333. wing location http www synopsys com designware dwest If you prefer you may also send an email to dw_EST synopsys com with EST in subject line In that email send the following information in the body of the message in the following format lt Site Id gt lt Synopsys Release gt For example if your site id is 555 and you want to install the EST for use with the 2003 03 version of the Synopsys Synthesis CD write the following two fields in the body of the message separated by a few blank spaces 555 2003 03 Setting Up DesignWare Building Block IP for DC FPGA Include the following lines in your synopsys_dc setup file and ensure that you have a valid DesignWare Library license target library your library db synthetic library dw foundation sldb tmg sldb link library target library synthetic library search path search path synopsys root dw sim ver synopsys root libraries syn your library path Accessing DesignWare Building Block IP in DC FPGA You can access DesignWare Building Block IP either by operator or functional inference or by instantiating the component directly The example below shows how to access these IP Verilog assign PROD IN1 IN2 Operator Inference assign PROD DWF mult tc IN1 IN2 Function Inference DWO2 mult 8 8 Ul A B TC PRODUCT Instantiation 34 Synopsys Inc January 17 2005 DesignWare IP Family Chapter 2 DesignWare Library Synt
334. xed to SINGLE e All other AHB control signals 284 forwarded unchanged AHB Lite configuration to remove redundant logic Deadlock detection Synopsys Inc AHB Slave Interface Deadlock protection SPLIT response generation after deadlock detection at the master interface Bus held off HREADY low until the secondary transfer data phase completes and is acknowledged back from the master interface SPLIT response from secondary forwarded back to primary as RETRY Component ID code retrievable from read data bus Support for locked transfers any HTRANS through HMASTLOCK IDLE and BUSY non locked cycles ignored January 17 2005 DesignWare IP Family DW_ahb_h2h AHB to AHB Bridge DW_ahb_h2h g m w lt m gt 0 o N D D 5 AHB bus secondary AHB bus En primary e The DesignWare DW_ahb_h2h Databook is available at http www synopsys com products designware docs January 17 2005 Synopsys Inc 285 DesignWare IP Family DW_apb_wdt APB Watchdog Timer DW_apb_wdt APB Watchdog Timer AMBA APB interface used to allow easy integration into AMBA System on Chip SoC implementations Configurable APB data bus widths of 8 16 and 32 bits Configurable watchdog counter width of 16 to 32 bits Counter counts down from a pre set value to zero to indicate the occurrence of a timeout Optional external clock enable signal to control the rate at which th
335. y Models Refer to Memory Models on page 313 SmartModel Library Refer to DesignWare SmartModels on page 324 DesignWare Verification Library The DesignWare Verification Library a subset of the DesignWare Library contains reusable pre verified verification IP of the industry s most popular bus and interface standards Design Views for Star IP cores and thousands of memory models The following table identifies the various components that make up this library Component Name Component Description Component Type DesignWare Bus amp I O Standards ahb_bus_vmt ahb_master_vmt ahb_monitor_vmt ahb_slave_vmt DesignWare AMBA AHB Models AHB Bus Interconnect AHB Master AHB Monitor and AHB Slave page 304 Verification Models apb_master_vmt apb_monitor_vmt apb_slave_vmt DesignWare AMBA APB Models APB Master APB Monitor and APB Slave page 306 Verification Models axi_master_vmt axi_slave_vmt axi_monitor_vmt axi_interconnect_vmt DesignWare VIP for AMBA 3 AXI page 307 Verification Model ethernet_txrx_vmt ethernet_monitor_vmt 10 100 1G 10G Gigabit Ethernet Models page 310 Verification Models enethub_fx rmiirs_ fx Ethernet RMII Tranceiver and Hub page 311 Verification Models i2c_txrx_vmt PC Bi Directional Two Wire Bus Verification Model 26 Synopsys Inc January 17 2005 DesignWare IP Family C
336. ynchronous reset 1 synchronous reset input_mode O or 1 Registered inputs Default 1 0 no 1 yes output_mode Oor 1 Registered outputs Default 1 0 no 1 yes early_start Oor 1 Computation start Default 0 0 start computation in the second cycle 1 start computation in the first cycle Table 3 Synthesis Implementations Implementation Function License Feature Required cpa Carry propagate adder synthesis model DesignWare 132 Synopsys Inc January 17 2005 DW_mult_seq Sequential Multiplier e Parameterized word length e Parameterized number of clock cycles e Unsigned and signed two s complement data multiplication e Registered or un registered inputs and outputs DesignWare IP Family DW_mult_seq Sequential Multiplier g 7 lt m gt D 2 N D D 5 Table 1 Pin Description Pin Name Width Direction Function clk l bit Input Clock rst_n 1 bit Input Reset active low hold 1 bit Input Hold current operation 1 start 1 bit Input Start operation 1 A new operation is started again by making start 1 for one clock cycle a a_width bit s Input Multiplier b b_width bit s Input Multiplicand complete 1 bit Output Operation completed 1 product a_width b_width bit s Output Product a x b Table 2 Parameter Description Parameter Values Description a_width 23 and lt b_width Word length of a b_
337. ys Inc 390 DesignWare IP Family No DW_CoolFlux d IA CoolFlux 24 bit DSP Core from Philips 391 Synopsys Inc January 17 2005 DesignWare IP Family Index Index Numerics 10 Gigabit Ethernet Models 310 A ahb_bus_vmt 304 ahb_master_vmt 304 ahb_monitor_vmt 304 ahb_slave_vmt 304 AMBA AHB Models 304 AMBA APB Models 306 AMBA Connect 287 AMBA On Chip Bus IP listing 22 AMBA QuickStart 288 apb_master_vmt 306 apb_monitor_vmt 306 apb_slave_vmt 306 axi_interconnect_vmt 307 axi_master_vmt 307 axi_monitor_vmt 307 axi_slave_vmt 307 B Board Verification IP listing 26 Building Block IP application specific control logic 38 application specific interface 47 data integrity 141 data integrity coding overview 149 datapath arithmetic overview 51 datapath floating point overview 122 datapath sequential 130 datapath trigonometric overview 137 datapath generator overview 50 DSP 155 logic combinational overview 165 logic sequential overview 170 memory asynchronous RAMs 231 memory FIFO overview 181 memory registers 217 January 17 2005 memory stacks 239 overview 31 test JTAG overview 244 C Cores overview 330 D datapath generator overview 50 Design Compiler 33 35 DesignWare AMBA Connect 287 DesignWare Building Block IP See also Building Block IP DesignWare Core dwcore_usb2_phy 368 DesignWare Cores overview 330 DesignWare FlexModels listing 322 DesignWare FlexModels overvie
338. ys Inc January 17 2005 R DW02_sin Combinational Sine DesignWare IP Family DW02_sin Combinational Sine e Parameterized word length A SIN g o lt gt D Table 1 Pin Description N Pin Name Width Direction Function A A_width bit s Input Angle in binary E SIN sin_width bit s Output Sine value of A Table 2 Parameter Description Parameter Values Description A_ width 2 to 34 Word length of A sin_width 2 to 34 Word length of SIN Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare January 17 2005 Synopsys Inc 139 DesignWare IP Family DW02_sincos Combinational Sine Cosine DW02 sincos Combinational Sine Cosine e Parameterized word length SIN_COS A WAVE Table 1 Pin Description Pin Name Width Direction Function A A_width bit s Input Angle in binary SIN_COS 1 bit Input sine SIN_COS 0 or cosine SIN_COS 1 WAVE wave_width bit s Output sine or cosine value of A Table 2 Parameter Description Parameter Values Function A_width 2to34 Word length of A wave_width 2 to 34 _ Word length of WAVE Table 3 Synthesis Implementations Implementation Name Function License Feature Required str Synthesis model DesignWare 140 Synop
339. zed word width e Generates check bits for new data written and corrects corrupt data for read and read modify write cycles e Supports scrubbing e Flags to indicate if an error was detected and if the error is not correctable e Flow through architecture for speed and flexibility gen err_detect correct_n err_multpl datain dataout chkin chkout e Error syndrome output for error logging Table 1 Pin Description Pin Name Width Direction Function gen 1 bit Input Suppresses correction in write mode gen 1 and generates check bits Enables correction when in read mode gen 0 and correct_n is asserted low correct_n 1 bit Input Enables correction of correctable words active low datain width bits Input Input data word to check check mode or data from which check bits are generated generate mode chkin chkbits bits Input Check bits input for error analysis on read err_detect 1 bit Output Indicates that an error has been detected active high Location of error is specified by the error syndrome err_multpl 1 bit Output Indicates that the error detected is a multiple bit error and therefore uncorrectable dataout width bits Output Output data May be corrected if an error is detected and correct_n is asserted chkout chkbits bits Output When gen 1 chkout contains the check bits generated from datain When gen 0 and synd_sel 0 chkout is the c

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