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VPC3+S User Manual

1. only Bit Position A J Address Designation 7 6 5 4 3 2 0 04H E Status Reg Intel WD State DP State g S 3 v 7 0 e i e 182 2 S 9 See below 1 0 1 0 oc a a O for coding Bit Position Address Designation 15 14 13 12 11 10 9 8 05H Status Reg Intel VPC3 Release Baud Rate 15 8 See below 3 2 1 0 3 2 1 0 for coding 32 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 ASIC Interface 5 Status Register Low Byte Address 04H Intel bit 7 6 WD State 1 0 State of the Watchdog State Machine r 00 00 BAUD_SEARCH state 01 BAUD_CONTROL state 10 DP_CONTROL state 11 Not possible bit 5 4 DP_State 1 0 State of the DP State Machine r 00 00 WAIT PRM state 01 WAIT CFG state 10 DATA EXCH state 11 Not possible bit 3 Reserved r 0 bit 2 Diag_Flag Status of the Diagnosis Buffer ro 0 The Diagnosis Buffer had been fetched by the DP Master 1 The Diagnosis Buffer had not been fetched by the DP Master yet bit 1 Reserved r 0 bit O Offline Passive Idle Offline Passive ldle state r 0 0 VPC3 S is in Offline 1 VPC3 S is in Passive Idle Figure 5 6 Status Register Low Byte Status Register High Byte Address 05H Intel bit 15 12 VPC3 Release 3 0 Release number for VPC3 r 1110 1110 bit 11 8 Baud Rate 3 0 The baud rate found by VPC3 S 1
2. No Parameter MIN MAX Unit 1 ALE pulsewidth 10 ns 2 ALE J to XRD J 20 ns 3 Address to ALE 4 setuptime 10 ns 4 Address holdtime after ALE 4 0 ns 5 XRD to data valid 83 ns 6 XRD pulsewidth 105 ns 7 XRDTtoALET 10 ns 8 address AB7 0 holdtime after XRD XWR f 0 ns 9 data holdtime after XRD T 3 12 ns 10 XRD XWR cycletime 155 ns 11 ALE J to XWR Y 20 ns 12 XWR pulsewidth 83 ns 13 data setuptime to XWR f 10 ns 14 XWR f to ALE T 10 ns 15 data holdtime after XWR f 0 ns Figure 10 10 Timing Synchronous Intel Mode VPC3 S User Manual Revision 1 06 115 Copyright O profichip GmbH 2012 10 Operational Specifications 10 6 3 Timing in the Asynchronous Intel Mode In the asynchronous Intel mode the VPC3 S acts like a memory with ready logic The access time depends on the type of access The request for an access to the VPC3 S is generated from the falling edge of the read signal XRD or the rising edge of the write signal XWR The VPC3 S generates the Ready signal synchronously to the system clock The Ready signal gets inactive when the read or the write signal is deactivated The data bus is switched to Tristate with XRD 1 DB7 0 24 XRD XCS XREADY normal XREADY early Le 02 gt Figure 10 11 Asynchronous Intel Mode READ XWR 1 116 Revision 1 06 VPC3 S User Manual Copyright profichip G
3. Ball Pin c SLAP MA BGA QFP Signal Name In Out Description Source Destination AB8 Address Bus 8 A1 48 S CPU SPI SCK I2C SCK SPI Serial Clock I2C Serial Clock XREADY XDTACK READY DTACK for external CPU A2 47 S O CPU SPI MISO 12C SDA SPI Master In Slave Out I2C Serial Data A3 GND A4 VCC Era AB3 Address Bus 3 CPU 12C_SA3 I2C Slave Address 3 Configuration Pin AB2 Address Bus 2 CPU A6 37 l2C SA2 I2C Slave Address 2 Configuration Pin Bi f AB7 IS Address Bus 7 CPU SPI_MOSI SPI Master Out Slave In Configuration Pin UP AB5 Address Bus 5 CPU I2C SA5 I2C Slave Address 5 Configuration Pin AB9 Address Bus 9 CPU B3 44 SPI CPHA SPI Clock Phase Configuration Pin UN AB4 Address Bus 4 CPU 12C_SA4 I2C Slave Address 4 Configuration Pin TART AB1 Address Bus 1 CPU I2C_SA1 I2C Slave Address 1 Configuration Pin TE ABO Address Bus 0 CPU I2C SAO I2C Slave Address 0 Configuration Pin XCS AB11 Chip Select Address Bus 11 C1 3 CPU SPI XSS SPI Slave Select es 5 AB10 Address Bus 10 CPU SPI CPOL SPI Clock Polarity Configuration Pin AB6 Address Bus 6 CPU C3 45 12C_SA6 I2C Slave Address 6 Configuration Pin C4 40 SYNC O Synchronization Pulse CPU Motion Control C5 35 ALE AS AB11 Address Latch Enable Address Strobe CPU Address Bus 11 C6 34 XRD R W Read Read Write CPU D1 18 VCC D2 5 XTESTO Test Pin 0 to be connected to VCC Test Pin Divide
4. SCK SDA IN SDA OUT Figure 10 23 Timing Diagram I2C Interface Mode Symbol Parameter MIN MAX Unit f sck Clock Frequency SCK 6 MHz t Low Clock Pulse Width Low 83 ns t HIGH Clock Pulse Width High 83 ns t AA Clock Low to Data Out Valid 76 ns t H STA Start Condition Hold Time 21 ns tssta Start Condition Set up Time 21 ns t H DAT Data In Hold Time 10 ns t S DAT Data In Set up Time 10 ns tssto Stop Condition Set up Time 21 ns t pH Data Out Hold Time 21 ns Figure 10 24 Timing I2C Interface Mode VPC3 S User Manual Revision 1 06 125 Copyright O profichip GmbH 2012 10 Operational Specifications 10 7 Package Specifications 10 7 1 LFBGA48 BOTTOM VIEW EIS 9 b n X 6 5 4 5 2 1 O0 000 O OIO O O O 010 0 O O OJOOO OO 010 O TI O 1m O ww gt al SIDE VIEW Figure 10 25 LFBGA48 Package Drawing 126 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Operational Specifications 10 TOP VIEW PIN A1 CORNER zonmo0 gt Total Thickness Substrate Thickness Ball Diameter Package Edge Tolerance ewe ee o TE mmn Te x Et 4 000 Edge Ball Center to Center y s560 Figure 10 26 LFBGA48 Package Dimensions and Tolerances VPC3 S User Manual Revision 1 06 127 Copyright profichip GmbH 2012 10 Operational Specifications 10 7 2 LQFP48 DA D A JAN 36 25 OTRO 7 37
5. Bit Position A Byte Designation 7 6 5 4 3 2 1 0 Seconds 2 0 since 1 1 1900 0 00 00 0 or since 7 2 2036 6 28 16 if value lt Ox9dff4400 Clock_Value_ 7 Fraction Part of Seconds 2 0 Time Event Base is 1 2 Seconds Seconds 2 0 since 1 1 1900 0 00 00 8 or since 7 2 2036 6 28 16 if value Ox9dff4400 Clock Value 15 Fraction Part of Seconds 2 0 previous TE Base is 1 2 Seconds t D 16 C CV Clock_Value_Status1 8 5 17 ANH SWT CR z SYF Clock Value Status2 2 ao o o Figure 7 28 Format of Clock Value Processing Sequence The Clock Sync Interval is a time for monitoring and has to be written into the Clock Sync Buffer by the user The Time Receiver state machine in the VPC3 S is started after this write access The value for Clock Sync Interval is locked until the next LEAVE MASTER or a new parameterization occurs In addition it can be unlocked if the user set the Stop Clock Sync in Command byte VPC3 S User Manual Revision 1 06 81 Copyright O profichip GmbH 2012 7 PROFIBUS DP Extensions Following to a clock synchronization sequence the Clock Sync interrupt will be asserted Further information is contained in the Status byte If an overflow of the Receive Delay Timer occurs the Status byte will be cleared The VPC3 S cannot write new data to the Clock Sync Buffer until the user has acknowledged the Clock S
6. I I A5 38 l2C_SA3 I2C Slave Address VCC or GND I A6 37 l2C SA2 VCC or GND B5 39 I2C SA1 VCC or GND B6 36 I2C SAO VCC or GND A1 48 2C SCK I S Serial Clock CPU SCK A2 47 l2C SDA I S O Serial Data Line CPU SDA Figure 3 9 Interface Configuration I2C Mode VPC3 S User Manual Revision 1 06 17 Copyright O profichip GmbH 2012 3 Pin Description Notes 18 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 4 1 Memory Organization A Overview The internal Control Parameters are located in the first 21 addresses The latches registers either come from the internal controller or influence the controller Certain cells are read or write only The internal working cells which are not accessible by the user are located in RAM at the same address locations The Organizational Parameters are located in RAM beginning with address 16H The entire buffer structure for tne DP SAPs is based on these pa rameters In addition general parameter data Station Address Ident Number etc and status information Global Control command etc are also stored in these cells Corresponding to the parameter setting of the Organizational Parameters the user generated buffers are located beginning with address 40H All buffers or lists must begin at segment addresses 8 bytes segmentation for 2K Byte mode 16 bytes segmentation for 4
7. XREADY 80286 Buscontr DB 15 0 DB 7 0 82288 82244 AB 23 0 AES GND RD WR IE driver control logic DEEE EM address cs EPROM RAM TSEPROM decoder 64kB 32kB Figure 8 22 80286 System X86 Mode 104 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Hardware Interface 8 8 1 6 Application with 80C32 2K Byte RAM Mode VPC3 48MHz 22R CLK DIVIDER connect to VDD or GND CLKOUT GND XINT MOT XDATAEX LED for Data Exchange CHE RESET XREADYo VDD 9 xcs X INT 9 4 1 gt VDD MODE zn VDD lt 4 XTESTO R 4k7 VDD XTESTI TXD RS485 gt Luc XRD ALE RXD C XRD HT XWR RTS RS485 uC XWR AB8 XCTS aGND ABO ABO apy STR ns ES UN ABT AB3 DB 1 ADB BR and Be EE 485 pB3 A3 AB 14 AB6 DB 4 ADB 4 AB 15 ABT DBS ADB 5 GND mx ABS DB 6 Fr AB g 15 OND e AB9 DB 7 lt ac GND m AB 10 DB 0 7 TxD tristate external pull up resistor required iC gt Figure 8 23 80C32 Application in 2K Byte mode The internal chipselect is activated when the address inputs AB 10 3 of the VPC3 S are set to O In the example above the start address of the VPC3 S is set to 1000H Processor VPC3 address
8. 16 328 Evo nn 17 326 J20 Moden 17 4 Memory Organization 19 41 OW GIVIOW nenne 19 4 2 Control Parameters Latches Registers 21 4 3 Organizational Parameters RAM 23 8 11 25 5 1 Mode Registers RTT 25 5 14 1 Mode Register Da 25 5 1 2 Mode Register 1 nee 27 5 1 3 Mode Register 2 29 5 1 4 Mode Register 3 31 5 2 Status REMISE ns en eee eee sen reer 32 5 3 Interrupt Controller a 34 5 3 1 Interrupt Request Register 35 5 3 2 Interrupt Acknowledge Mask Register 38 5 4 Watchdog EE IER oo OT 38 5 4 1 Automatic Baud Rate Identification 39 5 4 2 Baud Rate Monitor ios nine 39 5 4 3 Response Time Monitoring 39 6 PROFIBUS DP Interface 41 6 1 DP Buffer Structure eene roter mr cibum n Ext Et kid rna nds 41 6 2 Description of the DP Services 44 6 2 1 Set Slave Add SAP 55 44 p 22 oL Pim SAP 6T csvset coe ci able a e ieee 45 6 2 3 CHK Clg SAP 82 nenne 49 6 2 4 Slave Diag SAP 60 50 6 2 5 Write Read Data Data Exchange Default SAP 52 6 2 6 Global Control SAP BB neun 56 p 27 AD Input GAP Beh 57 6 2 8 BD Output SAP 57 eost nennen 57 6 2 9 Get Cfg SAP 59 unnnennennssnanennnnnnssnnnesnnnannnnarnnnnnnnnnn 58 VPC3 S User Manual Revision 1 06 3 Copyright profichip GmbH 2012
9. bit 1 0 Ind_U_Buffer Indicated User Buffer 01 Dout Buf Ptr1 10 Dout Buf Ptr2 11 Dout Buf Ptr3 Figure 6 13 Coding of Next Dout Buf Cmd The user must clear the U buffer during initialization so that defined cleared data can be sent for a RD Output telegram before the first data cycle Reading Inputs The VPC3 S sends the input data from the D buffer Prior to sending the VPC3 S fetches the Din Buffer from N to D If no new buffer is present in N there is no change The user makes the new data available in U With the New Din Buffer Cmd the buffer changes from U to N If the user s preparation cycle time is shorter than the bus cycle time not all new input data are sent but just the most current At a 12 Mbit s baud rate it is more likely however that the user s preparation cycle time is larger than the bus cycle time Then the VPC3 S sends the same data several times in succession Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 PROFIBUS DP Extensions 6 During start up the VPC3 S does not go to DATA EXCH before all parameter telegrams and configuration telegrams have been acknowledged If Diag Freeze Mode 1 there is no buffer change prior to sending The user can read the status of the state machine cell with the following codings for the four states Nil Dout Buf Ptri Dout Buf Ptr2 and Dout Buf Ptr3 The pointer for the current data is in the
10. Dest Slot Number o o j o oc AJOIN Offset Data Area c eo Sample Length um further link entries 120 Figure 7 9 Format of the Structured Prm Data with DXB Subscribertable specific link is grey scaled The user must copy the link entries of DXB Linktable or DXB Subscribertable without Dest Slot Number and Offset Data Area into the DXB Link Buf and set R Len DXB Link Buf Also the user must enter the default status message in DXB Status Buf with the received links and write the appropriate values to R Len DXB Status Buf After that the parameterization interrupt can be acknowledged Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 PROFIBUS DP Extensions 7 Bit Position Byte Designation 7 6 5 4 3 2 1 0 0 0 0 Block Length Header Byte 1 1 0 0 0 0 0 1 1 Status Type 2 0 0 0 0 0 0 0 Slot Number 3 0 0 0 0 0 0 0 Status Specifier 4 Publisher Addr Link Link_ Data_ 2 Status Error D Exist Jue 6 further link entries 61 Link Status bit 7 Link Status 1 active valid data receipt during last monitoring period 0 not active no valid data receipt during last monitoring period DEFAULT bit 6 Link Error 0 no faulty Broadcast data receipt DEFAULT 1 wrong length error occurred during reception bit 0 Data Exist 0 no correct Broadc
11. DP Master PROFIBUS DP Slave Request to acyclic SAP gt fill Indication Buffer lt short acknowledgement SC Polling telegram to acyclic SAP gt process data lt short acknowledgement SC update Response Buffer Polling telegram to acyclic SAP gt lt Response from acyclic Figure 7 5 acyclic communication sequence VPC3 S Firmware set Request_SA Request_SSA set INUSE in Control of Ind_Buf write data in Ind_Buf clear INUSE and set USER and IND in Control of Ind_Buf set FDL Ind interrupt clear FDL Ind interrupt search for Ind Buf with IND 1 read Ind Buf clear IND in Control of Ind Buf write Response in Resp Buf set RESP in Control of Resp Buf check on RESP 1 read Resp Buf clear RESP and USER in Control of Resp Buf set Response Sent set Poll End Ind interrupt clear Poll End Ind interrupt search for SAP with Response Sent 1 clear Response Sent Figure 7 6 FDL Interface of VPC3 S e g same Buffer for Indication and Response 7 2 2 Diagnosis Model The format of the device related diagnosis data depends on the GSD keyword DPV1 Slave in the GSD If DPV1 Slave 1 alarm and status messages are used in diagnosis telegrams Status messages are required by the Data eXchange Broadcast service for example Alarm Ack is used as the other acyclic services VPC3 S User Manual Revision 1 06 63 Copyright O profichip GmbH 2012 7 PROFIBUS DP Extensions 7 3 P
12. 10 reserved SYNC 9 8 Number of SYNC 11 Number of SYNC 7 0 12 An i5 ley Time Base us 48 16 reserved Teu 9 8 Tru Input_Time 17 Teu 1 7 0 Time Base Tsync 18 reserved Tri o 9 8 Teu o Output_Time 19 Tp11_ o 7 0 Time Base Tsync 20 0 255 E limit VPC3 S User Manual Revision 1 06 77 Copyright profichip GmbH 2012 7 PROFIBUS DP Extensions 78 PLL Buffer GC Clock Hit r 0 GC clock Hit The VPC3 has received a valid SYNCH telegram during the tolerance window GC Clock Detect r 0 GC Clock Detect Last SYNC signal coincides with the expected SYNCH telegram GC Clock Errror r 0 GC Clock Error PLL detects Synchronization Errors and has to be resynchronized PLL synched r 0 PLL synched PLL is synchronized with the DP Masters SYNCH Out Clock Detect r 0 Out Clock Detect Last SYNC signal coincides with the instant in time of the setpoint transfer In Clock Detect r 0 In Clock Detect Last SYNC signal coincides with the instant in time of the actual value acquisition PLL Start PLL Start rw 0 0 PLL is stopped 1 PLL is started SYNC Enable SYNC Enable rw 0 0 SYNC signal is not enabled 1 SYNC signal is send to DATAEXCH_N SYNC_Mode SYNC_Mode rw 0 0 SYNC signal not synchronized to SYNCH telegram 1 SYNC signal synchronized to SYNCH telegram Enable GC Clock rw 0 Enable GC Clock 0 gene
13. Set Slave Address Buffer Parameter Buffer Figure 6 1 DP_SAP Buffer Structure The VPC3 S first stores the parameter telegrams Set_Slave_Add and Set_ Ext_ Prm and the configuration telegram Chk_Cfg in Aux Buffer 1 or Aux Buffer 2 If the telegrams are error free data is exchanged with the corresponding target buffer Set Slave Add Buffer Parameter Buffer and Config Buffer Each of the buffers to be exchanged must have the same length In the R Aux Buf Sel parameter cell see Figure 6 2 the user defines which Aux buffers are to be used for the telegrams mentioned Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 PROFIBUS DP Extensions 6 above The Aux Buffer 1 must always be available Aux Buffer 2 is optional If the data profiles of these DP telegrams are very different for example the length of the Set Prm telegram is significantly larger than the length of the other telegrams it is suggested to make an Aux Buffer 2 available R Aux Buf Sel Set Prm 1 for this telegram The other telegrams are then read via Aux Buffer 1 R_ Aux Buf Sel Set Slave Adr 0 Chk Cfg 0 If the buffers are too small the VPC3 S responds with no resources RR Bit Position A Address Designation 7 6 5 4 3 2 1 0 2AH R Aux Buf Sel 8 lt B E 9 9 o Te o l See below 33 for coding 00 a R Aux Buf Sel Address 2AH bit 7 3 Don t Care
14. Table of Contents 7 PROFIBUS DP Extensions 59 7 1 Set Ext Prm SAP 53 SAP 61 59 72 PROFIBUS DP V sense ee 60 7 2 1 Acyclic Communication Relationships 60 7 2 2 Diagnosis ol iiri idi ee ee 63 73 PROFIBUS DP V2 nase 64 7 3 1 DXB Data eXchange Broadcast 64 7 3 2 soM Isochronous Mode sese 70 732 1 ISOM PIL none 74 7 3 3 CS Clock Synchronization sese 80 8 Hardware Interface 87 8 1 Universal Processor Bus Interface ssssssssss 87 OMNES UL c 87 8 1 2 Parallel Interface Modes essssseeesssss 88 8 1 3 SPI Interface Mode 91 8 1 4 12C Interface Mode eoi a 97 8 1 5 Application Examples Principles 103 8 1 6 Application with 80C32 2K Byte RAM Mode 105 8 1 7 Application with 80C32 4K Byte RAM Mode 106 8 1 8 Application with 80C165 nnssssessnnssssnnnnnnnnennnnnnnn 107 8 2 Dual Port RAM Controller 107 8 3 UAR Tc 108 BA ASIC Tettau 108 9 PROFIBUS Interface 109 91 Pin Assignment ies tht Xen a 109 9 2 Example for the RS485 Interface sssssessssss 110 10 Oper
15. The PLL shall handle following issues The jitter of the SYNCH telegrams has to be smoothed by the PLL If the jitter exceeds a certain limit the PLL will recognize a loss of the synchronization SYNCH telegrams lost due to bus disturbances have to be compensated Phase shifts due to line delay between the different DP slaves may be compensated Generation of a SYNC clock in every slave cycle The slave application cycle time must be an integer part of DP cycle time Reset Global Control clock SYNC clock Top gt T n Jitter lt 1 us Jitter lt 100 ns Parameter gt Status occurence of Global_Control ok l Bari DP Cycle Top I gt tolerance window error error delayed missing Tsyne Sync_PW_Reg 4 a SYNC GC Clock Hit GC Clock Detect behaviour in case of Enable In Clock 1 Enable Out Clock 1 Enable GC Clock 1 Number of SYNC 3 Tpu 3 Ty o 2 SYNC GC Clock Detect Out Clock Detect In Clock Detect Figure 7 20 SYNC clock and status signals of PLL To enable the IsoM PLL in the VPC3 S bit PLL Supported in Mode Registe
16. ADB7 0 The lower address bits AB7 0 are stored with the ALE signal in an in ternal address latch The internal CS decoder is activated VPC3 S generates its own CS signal from the address lines AB10 3 The VPC3 S selects the relevant address window from the AB2 0 signals A11 from the microcontroller must be connected to XCS pin BGA_C1 QFP_3 in 4K Byte mode as this is the additional address bus signal in this mode In 2K Byte mode this pin is not used and should be pulled to VDD Asynchronous Intel Mode In this mode various 16 8 bit microcontroller series like Intel s x86 Siemens 80C16x or compatible series from other manufacturers can be used Asynchronous bus timing with evaluation of the XREADY signal 8 bit non multiplexed bus DB7 0 AB10 0 AB11 0 in 4K Byte mode VPC3 S User Manual Revision 1 06 89 Copyright profichip GmbH 2012 8 Hardware Interface 90 The internal VPC3 S address decoder is disabled the XCS input is used instead External address decoding is always necessary External chip select logic is necessary if not present in the microcon troller A11 from the microcontroller must be connected to ALE AS pin BGA C5 QFP 35 in 4K Byte mode as this is the additional address bus signal in this mode In 2K Byte mode this pin is not used and should be pulled to GND Asynchronous Motorola Mode Motorola microcontrollers like the HC16 and HC916 can be used in this mode When using HC
17. Copyright profichip GmbH 2012 PROFIBUS DP Extensions 6 Structure of the Set_Slave_Add Telegram The net data are stored as follows in the SSA buffer Bit Position p A Byte Designation 7 6 5 4 3 2 1 0 0 New_Slave_Address 1 Ident_Number_High 2 Ident_Number_Low 3 No_Add_Chg 4 Rem_Slave_Data additional application 243 specific data Figure 6 4 Structure of the Set Slave Add Telegram 6 2 2 Set Prm SAP 61 Parameter Data Structure The VPC3 S evaluates the first seven data bytes without User_Prm_Data or the first eight data bytes with User_Prm_Data The first seven bytes are specified according to the standard The eighth byte is used for VPC3 S specific characteristics The additional bytes are available to the application If a PROFIBUS DP extension shall be used the bytes 7 9 are called DPV1 Status and must be coded as described in section 7 PROFIBUS DP Extensions Generally it is recommended to start the User Prm Data first with byte 10 VPC3 S User Manual Revision 1 06 45 Copyright O profichip GmbH 2012 6 PROFIBUS DP Extensions Bit Position i Byte Designation 7 6 5 4 3 2 1 0 TD TD TD J oe s 18 8 8 0 9 ol N 9 o 5 Station Status o70 20 c0 9 97 a o o no co gt oo o o Sc lSceioc lic c cc cc 1 WD Fact 1 2 WD Fact 2 3 minTs
18. N state Bit Position Address Designation 7 6 5 4 3 2 1 0 08H F U N D Din Buffer SM Din Buffer SM Address 08H bit 7 6 F Assignment of the F Buffer 00 Nil 01 Din Buf Ptr1 10 Din Buf Ptr2 11 Din Buf Ptr3 bit 5 4 U Assignment of the U Buffer 00 Nil 01 Din_Buf_Ptr1 10 Din Buf Ptr2 11 Din Buf Ptr3 bit 3 2 N Assignment of the N Buffer 00 Nil 01 Din_Buf_Ptr1 10 Din Buf Ptr2 11 Din Buf Ptr3 bit 1 0 D Assignment of the D Buffer 00 Nil 01 Din_Buf_Ptr1 10 Din Buf Ptr2 11 Din Buf Ptr3 Figure 6 14 Din Buffer Management VPC3 S User Manual Revision 1 06 55 Copyright O profichip GmbH 2012 6 PROFIBUS DP Extensions Bit Position Address Designation 7 6 5 4 3 2 1 0 09H 0 0 0 0 0 0 U U New Din Buf Cmd 0 1 Din_Buf_Ptr1 1 0 Din_Buf_Ptr2 1 1 Din_Buf_Ptr3 Figure 6 15 Coding of New_Din_Buf_Cmd User Watchdog Timer After start up DATA EXCH state it is possible that the VPC3 S continually answers Data Exchange telegrams without the user fetching the received Dout Buffers or making new Din Buffers available If the user processor hangs up the DP Master would not receive this information Therefore a User Watchdog Timer is implemented in the VPC3 S This User WD Timer is an internal 16 bit RAM cell that is started from a user paramete
19. These events can be individually enabled via a mask register Acknowledgement takes place by means of the acknowl edge register The VPC3 S has a common interrupt output The integrated Watchdog Timer is operated in three different states BAUD SEARCH BAUD CONTROL and DP CONTROL The Micro Sequencer MS controls the entire process It contains the DP Slave state machine DP SM The integrated 4K Byte RAM that operates as a Dual Port RAM contains procedure specific parameters buffer pointer buffer lengths Station Address etc and the data buffers In the UART the parallel data flow is converted into the serial data flow and vice versa The VPC3 S is capable of automatically identifying the baud rates 9 6 Kbit s 12 Mbit s The Idle Timer directly controls the bus times on the serial bus line The IsoM PLL provides high precision synchronization mechanisms as defined in the PROFIBUS DPV2 protocol extension 8 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Pin Description 3 3 1 Pinout The VPC3 S is available in two package versions LFBGA48 or LQFP48 Several pins are sharing different functions Which pin function actually applies depends on the interface mode selected by the configuration pins Four parallel interface modes as well as I2C and SPI mode with con figurable clock phase and clock polarity are supported Please see the following chapters for details 1 2 3 4 5 6 oeooees 000006
20. XDATAEXCH O Push Pull 8mA 50pF CLKOUT O Push Pull 8mA 50pF Figure 10 4 Ratings for the Output Drivers 10 5 DC Electrical Characteristics Parameter Symbol MIN TYP MAX Unit DC supply voltage VCC 3 00 3 30 3 60 V Input voltage LOW level Vit 0 8 V Input voltage HIGH level Vin 2 0 V Output voltage LOW level VoL 0 4 V Output voltage HIGH level Von 2 4 V Deom a threshold voltage VE 13 id b ka voltage WT 19 bs ii Input LOW current li 1 1 uA Input HIGH current lia 1 1 uA Tri state leakage current loz 10 1 10 uA Output current LOW level 8mA cell lo 8 mA Output current HIGH level 8mA cell lon 8 mA Figure 10 5 DC Specification of I O Drivers for 3 3V Operation Notes The VPC3 S is equipped with 5V tolerant inputs 112 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 10 6 Timing Characteristics Operational Specifications 10 All signals beginning with X are low active All timing values are based on the capacitive loads specified in the table above 10 6 1 System Bus Interface Clock Clock frequency is 48 MHz Distortion of the clock signal is permissible up to a ratio of 30 70 at the threshold levels 0 9 V and 2 1 V Parameter Symbol MIN MAX Unit Clock period T 20 83 20 83 Clock high time Tcu 6 25 14 6 ns Clock low time Tot 6 25 14 6 ns Clock rise time Tor 4 ns Clock fall
21. and a fixed assignment If the CPU is clocked by the VPC3 S the output clock pulse CLKOUT 2 4 must be 4 times larger than the E Clock That is a clock pulse sig nal must be present at the CLK input that is at least 10 times larger than the desired system clock pulse E Clock The Divider Pin must be connected to 0 divider 4 This results in an E Clock of 3 MHz AB11 must be connected to ALE AS pin BGA C5 QFP 35 in 4K Byte mode as this is the additional address bus signal in this mode In 2K Byte mode this pin is not used and should be pulled to GND Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Hardware Interface 8 8 1 3 SPI Interface Mode The VPC3 S is designed to interface directly with the Serial Peripheral Interface SPI port of many of today s popular microcontroller families It may also interface with microcontrollers that do not have a built in SPI port by using discrete I O lines programmed to match the SPI protocol The SPI mode allows a duplex synchronous serial communication between the CPU and peripheral devices The CPU is always master while the VPC3 S is always slave in this configuration Four associated SPI port pins are dedicated to the SPI function as Slave Select SPI XSS Serial Clock SPI SCK Master Out Slave In SPI MOSI Master In Slave Out SPI MISO The clock phase control bit SPI CPHA and the clock polarity control bit SPI CPOL select one of four possible cl
22. whereby the access times depend on the type of access The request for an access of the VPC3 S is generated from the falling edge of the AS signal in addition XCS 0 R W 1 The request for a write access is generated from the rising edge of the AS signal in addition XCS2 0 RWz 0 AB10 0 DB7 0 AS RW XCS XDTACK normal XDTACK early re 50 re 6 gt Figure 10 17 Asynchronous Motorola Mode READ E CLOCK 0 120 Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 Operational Specifications 10 AB10 0 DB7 0 AS XCS XDTACK normal XDTACK early Le 60 gt Figure 10 18 Asynchronous Motorola Mode WRITE VPC3 S User Manual Revision 1 06 121 Copyright profichip GmbH 2012 10 Operational Specifications No Parameter MIN MAX Unit 43 address setuptime to AS 4 0 ns 44 AS J to data valid 83 ns 45 AS pulsewidth read access 115 ns 46 R Wisetuptime to AS 4 10 ns 47 XCS Y setuptime to AS 4 5 ns 48 AS to XDTACK J Normal Ready 125 ns 49 AS to XDTACK J Early Ready 104 ns 50 last AS J to XCS 4 93 ns 51 AS cycletime 125 ns 52 address holdtime after AS T 0 ns 53 Data holdtime after AS T 3 12 ns 54 AS inactive time 10 ns 55 R_W holdtime after AS T 10 ns 56 XCS holdtime after AS T 0
23. 46 47 CPOL 0 JLI LI LJ LJ LiJ LJ LJ LJ LI LI LJ LJ LJ LI L L MOSI don t care Data Byte 2 Data Byte 3 iisa BHO ROBO OO i i Figure 8 8 READ ARRAY Sequence WRITE BYTE Sequence The VPC3 S is selected by pulling XSS low The 8 bit WRITE BYTE instruction is transmitted to the device followed by the 16 bit address with the four MSBs of the address being don t care bits in case of 2 kB RAM mode the five MSBs of the address are don t care After the correct WRITE BYTE instruction and address are sent the data byte is shifted in on the MOSI pin Once 8 SCK clock pulses are received the sampled data byte is written to the selected address Providing more SCK clock pulses does not affect the VPC3 S The write operation is terminated by raising the XSS pin XSS 0 d 2 3 4 5 6 T 8 9 10 1 20 21 22 23 24 25 26 27 28 29 30 31 SCK CPOL 0 LY LI LI LI LI LI LI LI LI LI LU LI Le Instruction 16 bit Address Data In MOSI AAGDUEDODUDOODOLIOUDOODOUDDDODGO EST ITBedance MISO Figure 8 9 WRITE BYTE Sequence 96 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Hardware Interface 8 WRITE ARRAY Sequence The WRITE ARRAY sequence is similar to the WRITE BYTE sequence unless more than one data byte is transferred After the reception of every data byte the internal destination address is auto incremented by 1 When the highest address is reached 0x7FF in case of 2 k
24. Extensions 6 In order to use Sync and Freeze these functions must be enabled in the Mode Register 0 Bit Position A Address Designation 7 6 5 4 3 2 1 0 3CH R_GC_ a 5 5 P 3 en Command 5 N a o Z Z o o gt by 5 o See below D e o t for coding cr a a 2 LL 2 O oc R_GC_Command Address 3CH bit 7 6 Reserved bit 5 Sync The output data transferred with a Data_Exchange telegram is changed from D to N The following transferred output data is kept in D until the next Sync command is given bit 4 Unsync The Unsync command cancels the Sync command bit 3 Freeze The input data is fetched from N to D and frozen New input data is not fetched again until the DP Master sends the next Freeze command bit 2 Unfreeze The Unfreeze command cancels the Freeze command bit 1 Clear_Data With this command the output data is deleted in D and is changed to N bit 0 Reserved Figure 6 16 Format of the Global Control Telegram 6 2 7 RD_Input SAP 56 The VPC3 S fetches the input data like it does for the Data Exchange telegram available Prior to sending N is shifted to D if new input data are in N For Diag Freeze Mode 1 there is no buffer change 6 2 8 RD Output SAP 57 The VPC3 S fetches the output data from the Dout Buffer in U The user must pres
25. IO Data Bus 4 CPU G6 25 DB3 IO Data Bus 3 CPU H1 13 TXD O Transmit Data external pull up resistor required PB Interface H2 14 RTS O Request To Send PB Interface H3 42 VCC H4 43 GND H5 23 DB6 IO Data Bus 6 CPU H6 24 DB5 IO Data Bus 7 CPU Figure 3 3 Pin Assignment Notes All signals beginning with X are LOW active VCC 3 3 V OV The assignment of AB11 depends on the parallel interface mode selected All unused inputs must be connected to GND Input Levels I S LVTTL LVTTL Schmitt Trigger 12 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Pin Description 3 The following chapters are describing the different processor interface modes supported by the VPC3 S For every interface mode the settings of the configuration pins and the signals necessary to communicate with the microcontroller are listed Common signals for all interface types like clock divider interrupt and PROFIBUS interface signals are not explicitly listed in this overview 3 2 1 Asynchronous Intel Mode In Asynchronous Intel Mode the data and address busses are separate non multiplexed Address line 11 is to be connected to pin BGA C5 QFP 35 of the VPC3 S XREADY mechanism is supported Ball Pin Signal Name In Out Description Connect to BGA QFP E3 9 SERMODE I 0 Par
26. TT TT lp gt gt Sm E 48 c 3 PIN 1 IDENTIFIER w SEATING PLANE e SECTION A A Figure 10 27 LQFP48 Package Drawing 128 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Operational Specifications 10 Symbol Dimensions in mm MIN NOM MAX A 1 60 Ay 0 05 0 15 A2 1 35 1 40 1 45 b 0 17 0 22 0 27 bi 0 17 0 20 0 23 C 0 09 0 20 Ci 0 09 0 16 D 9 00 BSC D 7 00 BSC E 9 00 BSC Ei 7 00 BSC 0 50 BSC 0 45 0 60 0 75 L4 1 00 REF R4 0 08 R2 0 08 0 20 S 0 20 0 3 5 7 O4 0 Oo 12 TYP O3 12 TYP Figure 10 28 LQFP48 Package Dimensions and Tolerances VPC3 S User Manual Revision 1 06 129 Copyright O profichip GmbH 2012 10 Operational Specifications 10 8 Processing Instructions Generally ESD protective measures must be maintained for all electronic components The VPC3 S is a cracking endangered component that must be handled properly Profichip products are tested and classified for moisture sensitivity according to the procedures outlined by JEDEC The VPC3 S is classified as moisture sensitivity level MSL 3 In order to minimize any potential risk caused by moisture trapped inside non hermetic packages it is a general recommendation to perform a drying process before soldering 10 9 Ordering Information Version Order Code Package Temperatur
27. Time period of 2 Tcs expired after reception of ro Time Event Status Set Time bit 0 The VPC3 D has received a valid Clock Value telegram and made the ro data available in the Clock Sync Buffer Command Reserved bit 7 3 r 00000 Command Clock Value Check Ena bit A 0 don t evaluate Clock_Value_previous_TE NE 1 check Clock_Value_previous_TE with local variable Time_Last_Rcvd Command Ignore_Cyclic_State_Machine bit 0 Clock Synchronization stops after the receiption of a new Set Prm or us a LEAVE MASTER 1 Clock Synchronization continues until the user set Stop_Clock_Sync Command Stop_Clock_Sync bit 0 Stop the Clock Synchronization in order to write a new Tos without a w 0 previous Set_Prm or LEAVE MASTER The Bit is cleared by the Time_Receiver State Machine Clock_Value_ C Sign of CV 0 add correction value to Time a 1 substract correction value to Time Clock Value CV Correction Value Sel 0 2 0 min r 00000 1 31 30 930 min Clock_Value_ Reserved Status1 bit 1 0 r 00 VPC3 S User Manual Revision 1 06 83 7 PROFIBUS DP Extensions Clock_Sync Buffer Clock Value ANH Announcment Hour is 0 no change planned within the next hour E 1 a change of SWT will occur within the next hour Clock Value SWT Summertime Status 0 Winter Time bit 6 1 Summer Time r 0 Clock Value Reserved Status2 bit 5 r 0 Clock Value CR Accuracy St
28. WD_Timeout baudrate detected aan A WD On 0 WD_DP_CONTROL_Timeout or DP_CONTROL Figure 5 12 Watchdog State Machine WD SM 38 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 ASIC Interface 5 5 4 1 Automatic Baud Rate Identification The VPC3 S starts searching for the transmission rate using the highest baud rate If no SD1 telegram SD2 telegram or SD3 telegram was received completely and without errors during the monitoring time the search continues using the next lower baud rate After identifying the correct baud rate the VPC3 S switches to the BAUD CONTROL state and observes the baud rate The monitoring time can be parameterized WD BAUD CONTROL Val The watchdog uses a clock of 100 Hz 10 ms Each telegram to its own Station Address received with no errors resets the Watchdog If the timer expires the VPC3 S switches to the BAUD SEARCH state again 5 4 2 Baud Rate Monitoring The detected baud rate is permanently monitored in BAUD CONTROL The Watchdog is triggered by each error free telegram to its own Station Address The monitoring time results from multiplying twice WD BAUD CONTROL Val user sets this parameter by the time base 10 ms If the timer expires WD SM again goes to BAUD SEARCH If the user uses the DP protocol DP Mode 1 see Mode Register 0 the watchdog is used for
29. are enabled with DPV1_Enable in the Set_Prm telegram Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 PROFIBUS DP Extensions 7 Bit Position Byte Designation 7 6 5 4 3 2 1 0 e 0 Se SAP_Number SAP_Number o o ee 1 Request_SA 2 Request_SSAP 3 Service_Supported 4 Ind Buf Ptr O 5 Ind Buf Pti 1 6 Resp Buf Ptr SAP List entry Byte 0 Response Sent Response Buffer sent 0 no Response sent 1 Response sent SAP Number 0 51 Byte 1 Request SA The source address of a request is compared with this value At differences the VPC3 S response with no service activated RS The default value for this entry is 7FH Byte 2 Request SSAP The source SAP of a request is compared with this value At differences the VPC3 S response with no service activated RS The default value for this entry is 7FH Byte 3 Service Supported Indicates the permitted FDL service 00 all FDL services allowed Byte 4 Ind Buf Ptr 0 pointer to Indication Buffer 0 Byte 5 Ind Buf Ptr 1 pointer to Indication Buffer 1 Byte 6 Resp Buf Ptr pointer to Response Buffer Figure 7 3 SAP List entry In addition an Indication and Response Buffer are needed Each buffer consists of a 4 byte header for the buffer management and a data block of configurable length VPC3 S User Manual Revision 1 06 61 Copyrig
30. current output data from N The buffer changes from N to U with the Next Dout Buffer Cmd so that the current data can be transmitted to the application by a RD Output request from a DP Master Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 PROFIBUS DP Extensions 6 If the users evaluation cycle time is shorter than the bus cycle time the user does not find any new buffers with the next Next Dout Buffer Cmd in N Therefore the buffer exchange is omitted At a 12 Mbit s baud rate it is more likely however that the user s evaluation cycle time is larger than the bus cycle time This makes new output data available in N several times before the user fetches the next buffer It is guaranteed however that the user receives the data last received For power on LEAVE MASTER and the Global Control telegram with Clear Data 1 the VPC3 S deletes the D buffer and then shifts it to N This also takes place during power up entering the WAIT PRM state If the user fetches this buffer he receives U Buffer Cleared during the Next Dout Buffer Cmd If the user is supposed to enlarge the output data buffer after the Chk Cfg telegram the user must delete this deviation in the N buffer himself possible only during the start up phase in the WAIT CFG state If Diag Sync Mode 1 the D buffer is filled but not exchanged with the Data Exchange telegram It is exchanged at the next Sync or Unsync command
31. in Time of the 17 Actual Value Acquistion Time Base Taase 10 To 18 Se 0 2 1 Instant in Time of the 19 setpoint transfer Time Base Tpase 10 20 Tpx 0 2 7 1 Data_Exchange Time 23 Time Base 1 12 us 24 Teu w 1 2 1 Default 12 PLL Window 25 Time Base 1 12 us 26 TPL p 0 2 1 Default 0 PLL Delay Time 27 Time Base 1 12 us Figure 7 22 Format of Structured_Prm_Data with IsoM Parameter The following input parameters have to be calculated by firmware SYNC cycle time T T T we DP _ DP n Number _ of _ SYNC 1 start value of PLL window First Window Z Tj nl Ty n2 with nl 21 n2 gt 0 0003 76 Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 PROFIBUS DP Extensions 7 The base address of the PLL Buffer depends on the memory mode 2K Byte mode 7COH 4K Byte mode FCOH Bit Position Byte Designation 7 6 5 4 3 2 1 0 E x x x x 83 39 2 85 8 38 0 reserved 58 O8 SE O5 OT Status iQ o IIo 1 gO E 2 5 O 2 ix iS iS 8 8 5 o98 o9 o9 gt amp 3 1 reserved mo er o el Command o N TPLL w 2 f PLL_Window 1 29 1 Default 12 1 3 Time Base us 12 TPLL p 4 T PLL Delay Time 0 2 1 Default 0 1 5 Time Base us 12 Tsyne 6 E SYNC Cycle Time 1 24 9 Time Base us 48 Number of
32. may take place in the Offline State only like Mode Register 0 Bit Position Address 7 6 5 4 3 2 1 0 Designation 12H x Mode Reg 3 a S 17 0 28 8 Reserved LENA t _ zu JE 6 E S a S c x Q aon u a D Mode Register 3 Address 12H bit 7 Reserved w 0 bit 6 w 0 Reserved DIS Reserved w 0 bit 4 Reserved w 0 bit 3 PLL_Supported Enables IsoM PLL w 0 0 PLL is disabled 1 PLLis enabled For use of PLL SYNC_Ena must be set bit 2 En Chk SSAP Evaluation of Source Address Extension w 0 0 VPC3 accept any value of S SAP 1 VPC3 only process the received telegram if the S_SAP match to the default values presented by the IEC 61158 bit 1 DX_Int_Mode_2 Mode of DX_out interrupt w 0 0 DX Out interrupt is generated after each Data_Exch telegram 1 DX Out interrupt is only generated if received data is not equal to current data in DX Out buffer of user bit O GC Int Mode Ext extend GC Int Mode works only if GC Int Mode 0 w 0 0 GC Interrupt is only generated if changed GC telegram is received 1 GC Interrupt is only generated if GC telegram with changed Control_Command is received Figure 5 5 Coding of Mode Register 3 VPC3 S User Manual Revision 1 06 31 Copyright profichip GmbH 2012 5 ASIC Interface 5 2 Status Register The Status Register shows the current VPC3 S status and can be read
33. minTspn time OCH Mode Reg2 7 0 Mode Register 2 ODH Sync_PW_Reg 7 0 Sync Pulse Width Register Control_Command value for DER Control Command Reg n comparison with SYNCH telegram Group Select value for comparison OFH Group_Select_Reg 7 0 with SYNCH telegram 10H Reserved 11H 12H Mode Reg3 7 0 Mode Register 3 13H 14H Reserved 15H Figure 4 3 Assignment of the Internal Parameter Latches for WRITE Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 4 3 Organizational Parameters RAM The user stores the organizational parameters in the RAM under the specified addresses These parameters can be written and read Memory Organization 4 Address Intel Mot Name Bit No Significance 16H R TS Adr Setup Station Address of the VPC3 S 174 SAP tis Pr in nr 18H 19H R User WD Value 7 0 In DP Mode an internal 16 bit watchdog 19H 18H R User WD Value 15 8 timer monitors the user 1AH R Len Dout Buf Length of the 3 Dout Buf 1BH R Dout Buf Ptr Segment base address of Dout_Buf 1 1CH R Dout Buf Ptr2 Segment base address of Dout Buf 2 1DH R Dout Buf Ptr3 Segment base address of Dout Buf 3 1EH R Len Din Buf Length of the 3 Din Buf 1FH R Din Buf Ptr1 Segment base address of Din Buf 1 20H R Din Buf Ptr2 Segment base address of Din Buf 2 21H R Din Buf Ptr3 Segment base address of Din Buf 3 22H R Len D
34. mode READ BYTE Sequence The device is selected by pulling XSS low The 8 bit READ BYTE instruction is transmitted to the VPC3 S followed by the 16 bit address with the four MSBs of the address being don t care bits in case of 2 kB RAM mode the five MSBs of the address are don t care After the correct READ BYTE instruction and address are sent the data byte stored in the memory at the selected address is shifted out on the MISO pin After additional 8 SCK pulses the complete data byte has sent and no more valid data bits are shifted out on the MISO pin There is no auto increment mechanism for this instruction The read operation is terminated by raising the XSS pin Figure 8 7 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Hardware Interface 8 Note When reading from the Control Parameter memory address 0x000 to address 0x015 only the READ BYTE instruction may be used Otherwise an unintended read operation to the subsequent memory location will occur leading to an unpredictable behavior of the VPC3 S XSS 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31 SCK CPOL 0 en Instruction 16 bit Address we eff EERE M 3 Data Out High Impedance ww 80000000 Figure 8 7 READ BYTE Sequence READ ARRAY Sequence The device is selected by pulling XSS low The 8 bit READ BYTE instruc tion is transmitted to the VPC3 S followed by the 16 bit address with the fou
35. the DP CONTROL state after a Set Prm telegram was received with an enabled response time monitoring WD On 1 The watchdog timer remains in the baud rate monitoring state when the master monitoring is disabled WD On 0 The DP SM is not reset when the timer expires in the state BAUD CONTROL That is the DP Slave remains in the DATA EXCH state for example 5 4 3 Response Time Monitoring The DP CONTROL state serves as the response time monitoring of the DP Master Diag Master Add The used monitoring time results from multiplying both watchdog factors and then multiplying this result with the time base 1 ms or 10 ms Two WD Base WD Fact 1 WD Fact 2 See byte 7 of the Set Prm telegram The user can load the two watchdog factors WD Fact 1 and WD Fact 2 and the time base that represents a measurement for the monitoring time via the Set Prm telegram with any value between 1 and 255 EXCEPTION The WD Fact 1 WD Fact 2 1 setting is not allowed The circuit does not check this setting A monitoring time between 2 ms and 650 s independent of the baud rate can be implemented with the allowed watchdog factors VPC3 S User Manual Revision 1 06 39 Copyright O profichip GmbH 2012 5 ASIC Interface If the monitoring time expires the VPC3 S goes to BAUD CONTROL state again and generates the WD DP CONTROL Timeout interrupt In addition the DP State Machine is reset that is it generates the reset states of the buf
36. 0 MOSI 12C_A5 CPHA I2C A4 I2C A1 I2C AO S Figure 3 1 VPC3 S LFBGA48 Pinout TOP VIEW VPC3 S User Manual Revision 1 06 9 Copyright profichip GmbH 2012 3 Pin Description 36 ABO I2C SA0 35 ALE AS ABt1 34 XRD R_W 33 MODE 32 XWR E_CLOCK AB11 TE ao 29 XTEST1 28 Mor xiNT CET os I vec TES veo C TA oes AB2 12C_SA2 37 124 DBS AB3 12C_SA3 38 23 Be AB1 12C_SA1 39 22 DB4 SYNC 40 21 DB2 AB4 12C_SA4 41 20 DB7 vec 2T Te sw en 23 T vec AB9 SPI CPHA 44 17 J INT AB6 12C_SA6 45 16 xcrs AB5 12C_SA5 46 15 Rxp XREADY DTACK SPI_MISO 12C_SDA 47 ta RTS Mee soe scx EL TE mo DIVIDER a xresto 5T vec T on 7T c xour s SERMODE 9 eu oT XDATAEXCH 11 reser 2 o 9 o 8 z o a az z 5 57 Komm o 2 m lt D lt lt n O x Figure 3 2 VPC3 S LQFP48 Pinout TOP VIEW Details about package outlines and dimensions are listed in section 10 7 10 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Pin Description 3 3 2 Pin Assignment Overview
37. 0 010 Offset 4 bit 11 0 Physical address 12 bit 20 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Memory Organization 4 4 2 Control Parameters Latches Registers These cells can be either read only or write only In the Motorola Mode the VPC3 S carries out address swapping for an access to the address locations OOH 07H word registers That is the VPC3 S internally generates an even address from an odd address and vice versa Address Intel Mot Name Bit No Significance Read Access 00H 01H _ Int Req Reg 7 0 01H 00H Int Req Reg 15 8 Interrupt Controller Register 02H 03H Int Reg 7 0 03H 02H Int Reg 15 8 04H 05H Status Reg 7 0 Status Register 05H 04H Status Reg 15 8 06H 07H Mode Reg 0 7 0 Mode Register 0 07H 06H Mode Reg 0 15 8 Buffer assignment of the Dan BIBEBUNE SM 7 0 DP_Din_Buffer_State_Machine The user makes a new DP Din_Buf 09H New_Din_Buffer_Cmd 1 0 available inthe N state Buffer assignment of the CAM Dout_Buffer_SM 70 DP Dout Buffer State Machine The user fetches the last DP OBH Next_Dout_Buffer_Cmd 3 0 Dout Buf from the N state Buffer assignment for the OCH Diag_Buffer_SM 3 0 DP Diag Buffer State Machine ODH New Diag Buffer Cmd 1 0 The user makes a new DP Diag_Buf available to the VPC3 S The user positively acknowledges OEH User_Prm_Data_Okay 1 0 the user parameter setti
38. 1 DXBout Buf Ptr1 10 DXBout Buf Ptr2 11 DXBout Buf Ptr3 bit 5 4 U Assignment of the U Buffer 00 Nil 01 DXBout Buf Ptr1 10 DXBout Buf Ptr2 11 DXBout Buf Ptr3 bit 3 2 N Assignment of the N Buffer 00 Nil 01 DXBout Buf Ptr1 10 DXBout Buf Ptr2 11 DXBout Buf Ptr3 bit 1 0 D Assignment of the D Buffer 00 Nil 01 DXBout Buf Ptr1 10 DXBout Buf Ptr2 11 DXBout Buf Ptr3 Figure 7 12 DXBout Buffer Management 68 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 PROFIBUS DP Extensions 7 Bit Position R A Address Designation 7 6 5 4 3 2 1 0 13H 0 0 0 0 0 Next_DXBout_ Buf_Cmd gt ob 2 8 See coding 5 v5 below am m Next DXBout Buf Cmd Address 0BH bit 7 3 Don t care Read as 0 bit 2 State_U_Buffer State of the User Buffer 0 no new U buffer 1 new U buffer bit 1 0 Ind_U_Buffer Indicated User Buffer 01 DXBout Buf Ptr1 10 DXBout Buf Ptr2 11 DXBout Buf Ptr3 Figure 7 13 Coding of Next DXBout Buf Cmd Monitoring After receiving the DXB data the Link Status in DXB Status Buf of the corresponding Publisher is updated In case of an error the bit Link Error is set If the processing is finished without errors the bit Data Exist is set In state DATA EXCH the links are monitored in intervals defined by the parameterized watchdog time After the monito
39. 11 types with a multiplexed bus the address signals AB7 0 must be generated from the DB7 0 signals externally Asynchronous bus timing with evaluation of the XREADY signal 8 bit non multiplexed bus DB7 0 AB11 0 in 4K Byte mode The internal VPC3 S address decoder is disabled the XCS input is used instead Chip select logic is available and programmable in all microcontrollers mentioned above AB11 must be connected to XWR E CLOCK pin BGA D5 QFP 32 in 4K Byte mode as this is the additional address bus signal in this mode In 2K Byte mode this pin is not used and should be pulled to GND Synchronous Motorola Mode Motorola microcontrollers like the HC11 types K N M F1 or the HC16 and HC916 types with programmable E Clock timing can be used in this mode When using HC11 types with a multiplexed bus the address signals AB7 0 must be generated from the DB7 0 signals externally Synchronous bus timing without evaluation of the XREADY signal 8 bit non multiplexed bus DB7 0 AB10 0 AB11 0 in 4K Byte mode The internal VPC3 S address decoder is disabled the XCS input is used instead For microcontrollers with chip select logic K F1 HC16 and HC916 the chip select signals are programmable regarding address range pri ority polarity and window width in the write cycle or read cycle For microcontrollers without chip select logic N and M and others an external chip select logic is required This means additional hardware
40. 111 0000 12 00 Mbit s 0001 6 00 Mbit s 0010 3 00 Mbit s 0011 1 50 Mbit s 0100 500 00 Kbit s 0101 187 50 Kbit s 0110 93 75 Kbit s 0111 45 45 Kbit s 1000 19 20 Kbit s 1001 9 60 Kbit s 1111 after reset and during baud rate search Rest not possible Figure 5 7 Status Register High Byte VPC3 S User Manual Revision 1 06 33 Copyright O profichip GmbH 2012 5 ASIC Interface 5 3 34 Interrupt Controller The processor is informed about indication messages and various error events via the interrupt controller Up to a total of 16 events are stored in the interrupt controller The events are summed up to a common interrupt output The controller does not have a prioritization level and does not provide an interrupt vector not 8259A compatible The controller consists of an Interrupt Request Register IRR an Interrupt Mask Register IMR an Interrupt Register IR and an Interrupt Acknowl edge Register IAR uP uP uP uP INT_POL Figure 5 8 Block Diagram of Interrupt Controller Each event is stored in the IRR Individual events can be suppressed via the IMR The input in the IRR is independent of the interrupt masks Events that are not masked in the IMR set the corresponding IR bit and generate the X INT interrupt via a sum network The user can set each event in the IRR for debugging Each interrupt event that was processed by the microcontroller must be deleted via th
41. 5 g 9 E el 7 0 o5 s s S459 239 yelda gt amp 9 DE OE See below for o5 5 5 a S Q 26 26 coding Co d o ul on ao ao Bit Position p Address 15 14 13 12 11 10 9 8 Designation 07H E m E Mode Reg 0 Intel G ED 15 WS Le la Bs esp E Le m mud gt E 5 Of AS KSIF 5 S2 ve Z E Jo Io 2 See below for o amp oS9 o l 5 loo co f o 2 o9 o5 oon oc Og a coding cc LNI lanla gt DMm um a If Spec Clear Mode 1 Fail Safe Mode the VPC3 S will accept Data Exchange telegrams without any output data data unit length 0 in the state DATA EXCH The reaction to the outputs can be parameterized in the parameterization telegram When a large number of parameters have to be transmitted from the DP Master to the DP Slave the Aux Buffer 1 2 must have the same length as the Parameter Buffer Sometimes this could reach the limit of the available memory in the VPC3 S When Spec Prm Buf Mode 1 the parameterization data are processed directly in this special buffer and the Aux Buffers can be held compact VPC3 S User Manual Revision 1 06 25 Copyright O profichip GmbH 2012 5 ASIC Interface Mode Register 0 Low Byte Address 06H Intel bit 7 Freeze_Supported Freeze_Mode support rw 0 0 Freeze Mode is not supported 1 Freeze Mode is supported bit 6 Sync Supported Sync Mode support rw 0 0 Sync Mode is not supporte
42. AB 10 7 pun Ec Figure 8 26 Internal Chipselect Generation in Synchronous Intel Mode 4K Byte RAM 106 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Hardware Interface 8 8 1 8 Application with 80C165 VPC3 22R CLK DIVIDER connect to VDD or GND CLKOUT GND o XINT MOT XDATAEX LED for Data Exchange nC RESET XREADY6 1 gt uc XCS X INT u gt GND MODE un VDD 4 9 XTESTO R 4k7 VDD XTESTI TXD RS485 gt RXD Lu AAT XRD RTS RS485 AE m a XCTS aGND ABO ABI AB 1 AB2 apo ee BBC AB 3 DB 1 DE AB4 And past PB ABS 485 DB3 DB5 ABO AB 6 DB4 p Re BE AB7 DB5 OR AB8 ne De ABI AB9 DB 7 p PR AB 10 AB 10 ABI ALE AB 11 DB 0 7 qc gt AB 0 11 TxD tristate external pull up resistor required c Figure 8 27 80C165 Application 8 2 Dual Port RAM Controller The internal 4K Byte RAM of the VPC3 S is a single port RAM An integrated Dual Port RAM controller however permits an almost simultaneous access of both ports bus interface and microsequencer interface When there is a simultaneous access of both ports the bus interface has priority This guarantees the shortest possible access time If the VPC3 S is connected to a microcontroller with an asynchronous in
43. B RAM mode or OxFFF in 4 kB mode the address counter rolls over to address 0x000 allowing the write cycle to be continued indefinitely The write operation is terminated by raising the XSS pin XSS 20 21 22 23 24 25 26 27 28 29 30 31 CPOL 0 eocces 16 bit Address Data Byte 1 s COE P 3 x psp peg ssp ess 8008080050000 High Impedance MISSO __ _ c XSS 32 33 34 35 36 37 38 39 140 41 42 43 44 45 46 47 CPOL 0 LY LI LI LI LI LU LI LI LI LI LI LI LI LI LI Le Data Byte 2 Data Byte 3 uon BDDUDDUDUDOSODODOOUE High Impedance MISO Data Byte n Figure 8 10 WRITE ARRAY Sequence 8 1 4 12C Interface Mode The VPC3 S supports a bidirectional 2 wire bus and data transmission protocol A device that sends data onto the bus is defined as transmitter while a device receiving data is defined as a receiver The bus has to be controlled by a master device which generates the Serial Clock SCK controls the bus access and generates the Start and Stop conditions while the VPC3 S works as slave Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated The data on the SDA line must be stable during the HIGH period of the clock The HIGH or LOW state of the data line can only change when the clock signal on the SCK line is LOW Figure 8 11 One clock pulse is generated for each data bit transferred VPC3
44. CK line with data being latched on odd numbered edges and shifted on even numbered edges Data reception is double buffered Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI Data Register after the last bit is shifted in CPHA 1 Transfer Format Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin the second edge clocks data into the system In this format the first SCK edge is issued by setting the CPHA bit at the beginning of the 8 cycle transfer operation The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay This first edge commands the slave to transfer its first data bit to the serial data input pin of the master A half SCK cycle later the second edge appears on the SCK pin This is the latching edge for both the master and slave When the third edge occurs the value previously latched from the serial data input pin is shifted into the SPI shift register After this edge the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave Transfer SCK Edge Nr SCK CPOL 0 SCK CPOL 1 SAMPLE MOSI MISO MOSI MISO XSS Figure 8 5 SPI Transfer Format CPHA 1 VPC3 S User Manual Revision 1 06 93 Copyright O profichip GmbH 2012 8 Hardware Interface 94 This process c
45. Command Figure 7 17 SYNC signal and interrupts for synchronization modes picture only shows the effects by reception of telegrams time between telegrams is not equal Isochronous Mode To enable the Isochronous Mode in the VPC3 S bit SYNC Ena in Mode Register 2 must be set Additionally the Spec Clear Mode in Mode Register 0 must be set The polarity of the SYNC signal can be adjusted with the SYNC Pol bit The register Sync PW contains a multiplicator with the base of 1 12 us to adjust the SYNC pulse width Settings in the Set Prm telegram are shown below The Structured Prm Data block IsoM Structure Type 4 is also required for the application If it is sent by Set Prm telegram the bit Prm Structure must be set VPC3 S User Manual Revision 1 06 71 Copyright O profichip GmbH 2012 7 PROFIBUS DP Extensions 72 Bit Position 5 Byte Designation 7 6 5 4 3 e 7 I g 8 0 oc E Station Status o N c o gt o a re 1 WD Fact 1 2 WD Fact 2 3 minTspr 4 Ident_Number_High 5 Ident_Number_Low e Il co 6 al Group_Ident 3 O n 2 7 b DPV1 Status 1 T LL 8 DPV1 Status 2 1 o 9 c DPV1 Status 3 o 2 10 User_Prm_Data 246 Figure 7 18 Format of Set_Prm telegram for IsoM Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 PROFIBUS DP Extensions 7 DP Slave in an IsoM network To enable cyclic sy
46. D Operation 102 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Hardware Interface 8 8 1 5 Application Examples Principles Clock Generator 48MHz DIVIDER Y CLK wa eem Clockdivider BD PI XRD RTS gt INTO 14 X INT DB 7 0 TxD J Port 0 A D 7 0 p 80C 32 B DB 7 0 RxD Address Latch C501 ALE ress Latc AB 7 0 VPC3 N 1K Port 2 AB 1 5 8 0000 0XXX Decoder T GND ABB AB9 AB10 VPC3 Mode Reset Reset 1K HK IK 3K 3 o GND VDD Figure 8 20 Low Cost System with 80C32 Clock Generator 48 MHz DIVIDER i sd Kdivid neo iocKdivide CLK WR gt XWR ee RD i iat RTS INTO j4 X INT TxD DB 7 0 80C 32 Data RxD I DB 7 0 20 16 MHz ALE I lAddress Latch XCTS LM Address VPC3 l Porto A D 7 0 Latch aS Port2 AB 15 8 0000 0XXX GND PSEN AB 15 0 ABB AB9 Reset AB10 VPC3 Mode Reset Address EPROM RAM Decoder ina 64kB 32kB f i 1K HK IK a 4 mee RD WR GND VDD Figure 8 21 80C32 System with External Memory VPC3 S User Manual Revision 1 06 103 Copyright profichip GmbH 2012 8 Hardware Interface 12 24 MHz Clockgenerator 48 MHz N XWR XRD X INT
47. Isochronous Mode Each SYNCH telegram causes an impulse on the SYNC output and a New GC Command interrupt In this mode the IsoM PLL can be used for compensation of jitter and loss of synchroni zation Simple Sync Mode A Data Exchange telegram no longer causes a DX Out interrupt immediately rather the event is stored in a flag By a following SYNCH message reception the DX Out interrupt and a synchronization signal are generated at the same time Additionally a New GC Command interrupt is produced as the SYNCH telegram behaves like a regular Global Control telegram to the DP state machine If no Data Exchange telegram precedes the SYNCH telegram only the New GC Command interrupt is generated Bit Position Byte Designation 7 6 5 4 3 2 1 0 0 0 0 0 Control Command Group 8 1 Group_ Select Figure 7 16 IsoM SYNCH telegram Each Global_Control is compared with the values that can be adjusted in Control Command Reg 0Eh and Group Select Reg OFh If the values are equal a SYNCH telegram will be detected Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 PROFIBUS DP Extensions 7 Data_Ex SYNCH SYNCH Data_Ex GC SYNCH telegrams IsoM SYNC DX Out New GC Command Simple Sync Mode SYNC DX Out New GC
48. K Byte mode Address Function 000H Control Parameters latches registers 21 bytes Iniermel wording cale 015H 016H Organizational Parameters 42 bytes O3FH 040H DP buffers Data in 3 Data out 3 Diagnosis data 2 Parameter data 1 Configuration data 2 Auxiliary buffers 2 SSA buffer 1 DP V1 buffer SAP List 1 Indication Response buffers DP V2 buffer DXB out 3 DXB buffers 2 CS buffer 1 7FFH FFFH PLL buffer 1 kkk Figure 4 1 Memory Table Data in means input data from DP Slave to DP Master Data out means output data from DP Master to DP Slave Number of buffers depends on the entries in the SAP List DXB out means input data from another DP Slave slave to slave communication VPC3 S User Manual Revision 1 06 19 Copyright O profichip GmbH 2012 4 Memory Organization Internal VPC3 S RAM 2K 4K Byte Segment 0 Segment 1 Segment 2 8 16 bit segment addresses pointer to the buffers Segment 254 Segment 255 Building of the physical buffer address 2K Byte Mode 7 0 Segment base address 8 bit 0 0 0 0 0 Offset 3 bit 10 0 Physical address 11 bit 4K Byte Mode 7 0 Segment base address 8 bit 01
49. M and writing the address in the RAM cell R TS Adr There must be a non volatile memory available for example an external EEPROM to support this service It must be possible to store the Station Address and the Real No Add Change True FFH parameter in this EEPROM After each restart caused by a power failure the user must read these values from the EEPROM again and write them to the R TS Adr und R Real No Add Change RAM registers If SAP55 is enabled and the Set Slave Add telegram is received correctly the VPC3 S enters the pure data in the Aux Buffer 1 2 exchanges the Aux Buffer 1 2 for the Set Slave Add Buffer stores the entered data length in R Len SSA Data generates the New SSA Data interrupt and internally stores the New Slave Add as Station Address and the No Add Chg as Real No Add Chg The user does not need to transfer this changed parameter to the VPC3 S again After reading the buffer the user generates the SSA Buffer Free Cmd read operation on address 14H This makes the VPC3 S ready again to receive another Set Slave Add telegram for example from a different DP Master The VPC3 S reacts automatically to errors Bit Position P 2 Address Designation 7 6 5 4 3 2 1 0 SSA_Buf_ 14H 0 0 0 0 0 0 0 0 Free_Cmd SSA_Buf_Free_Cmd Address 14H bit 7 0 Don t care Read as 0 Figure 6 3 Coding of SSA_Buffer_Free_ Command Revision 1 06 VPC3 S User Manual
50. P Slave for IsoM set PLL Support receive Set Ext Prm set New Ext Prm Data interrupt acknowledge New Ext Prm Data interrupt configure PLL receive SYNCH telegrams set PLL Start synchronization of PLL to GC clock gt set hit display set Sync Enable release clock on SYNC pin Figure 7 25 Start up of PLL grey scaled task omitted if SYNC Modez0 VPC3 S User Manual Revision 1 06 79 Copyright O profichip GmbH 2012 7 PROFIBUS DP Extensions 7 3 3 CS Clock Synchronization 80 The Clock Synchronization mechanism synchronizes the time between devices on a PROFIBUS segment A time master is a DP Master The scheme used is a backwards time based correction The knowledge of when a special timer event message was broadcasted is subsequently used to calculate appropriate clock adjustments The synchronized time can be used for time stamp mechanism Time Master Output Time Event Clock Value gt t Time Receiver Input Time_Event Clock_Value gt t Time Receiver Application gt t je gt 44 tsp tor tho Tz i 1 2 3 4 1 Time Event 2 Clock Sync Interrupt 3 read access Receive Delay Time 4 update system timer Figure 7 26 clock synchronization mechanism The clock synchronization sequence consists of two messages broad casted by the time master When the first message called Time Event is received the VPC3 S s
51. ROFIBUS DP V2 7 3 1 64 DXB Data eXchange Broadcast The DXB mechanism enables a fast slave to slave communication A DP Slave that holds input data significant for other DP Slaves works as a Publisher The Publisher can handle a special kind of Data Exchange request from the DP Master and sends its answer as a broadcast telegram Other DP Slaves which are parameterized as Subscribers can monitor this telegram A link is opened to the Publisher if the address of the Publisher is registered in the linktable of the Subscriber If the link has been established correctly the Subscriber can receive the input data from the Publisher DP Master Classi lt b IT Dout Din Request FC 7 Response DA 127 Data Exchange with Data Exchange with E m Data DP Master Class 1 DP Master Class a irem a Dout Din Dout Din DXBout DP Slave Publisher DP Slave Subscriber pu Figure 7 7 Overview DXB The VPC3 S can handle a maximum of 29 links simultaneously Publisher A Publisher is activated with Publisher Enable 1 in DPV1 Status 1 The time minTspr must be set to Tip 37 tpi 2 Tser Tour All Data Exchange telegrams containing the function code 7 Send and Request Data Multicast are responded with destination address 127 If Publisher mode is not enabled these requests are ignored Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 PROFIBUS DP Extens
52. Read as 0 bit 2 Set Slave Adr Set Slave Address 0 Aux Buffer 1 1 Aux Buffer 2 bit 1 Chk Cfg Check Configuration 0 Aux Buffer 1 1 Aux Buffer 2 bit O Set Prm Set Extended Parameter 0 Aux Buffer 1 1 Aux Buffer 2 Figure 6 2 Aux Buffer Management The user makes the configuration data Get Cfg available in the Read Config Buffer for reading The Read Config Buffer must have the same length as the Config Buffer The RD Input telegram is serviced from the Din buffer in the D state and the RD Output telegram is serviced from the Dout Buffer in the U state All buffer pointers are 8 bit segment addresses because the VPC3 S have only 8 bit address registers internally For a RAM access VPC3 S adds an 8 bit offset address to the segment address shifted by 4 bits result 12 bit physical address in case of 4K Byte RAM or shifted by 3 bits result 11 bit physical address in case of 2K Byte RAM With regard to the buffer start addresses this specification results either in a 16 byte or in an 8 byte granularity VPC3 S User Manual Revision 1 06 43 Copyright O profichip GmbH 2012 6 PROFIBUS DP Extensions 6 2 Description of the DP Services 6 2 1 44 Set Slave Add SAP 55 Sequence for the Set Slave Add service The user can disable this service by setting R SSA Puf Ptr 00H The Station Address must then be determined for example by reading a DIP switch or an EEPRO
53. S User Manual Revision 1 06 97 Copyright O profichip GmbH 2012 8 Hardware Interface SDA SCK by data line change stable of data data valid allowed Figure 8 11 Bit Transfer on the I2C bus All transactions begin with a START S and can be terminated by a STOP P condition A HIGH to LOW transition on the SDA line while SCK is HIGH defines a START condition A LOW to HIGH transition on the SDA line while SCK is HIGH defines a STOP condition START condition STOP condition Figure 8 12 START and STOP condition START and STOP conditions are always generated by the master The bus is considered to be busy after the START condition The bus is considered to be free again a certain time after the STOP condition Every byte sent on the SDA line must be 8 bits long The number of bytes that can be transmitted per transfer is unrestricted Each byte has to be followed by an Acknowledge bit Data is transferred with the Most Significant Bit MSB first l l DUM Gene x A X X XX 7 XX Eu S E 1 1 1 MSB uo acknowledgement acknowledgement jl Sr l signal from slave signal from slave I I I I SCK iSorsgr 1 2 7 8 9 1 2 8108 9 I SrorP sers Se Weer ete ACK ACK START or byte complete clock line held LOW STOP or repeated START interrupt within slave while interrupts are serviced repeated START condition condition Figure 8 13 Data Transfer on the I2C Bus 98 Revision 1 06 VPC3 S User Manual Copyright profich
54. Status Segment base address of the 38H R DXB Status Buf Ptr DXB Status Buf This parameter specifies whether the 39H R Real No Add Change Station Address may be changed again later The user sets the parameters for the SAN R_Ident_Low Ident Number Low value The user sets the parameters for the San R_laent_High Ident Number High value The Control Command of Global Control 3CH R GC Command last received If parameters are set for the Spec Prm Buffer Mode see Mode SER R_Len_Spec_Prm_Buf Register 0 this cell defines the length of the Prm_Buf 3EH R DXBout Buf Ptr2 Segment base address of DXBout_Buf 2 3FH R DXBout Buf Ptr3 Segment base address of DXBout_Buf 3 Figure 4 4 Assignment of the Organizational Parameters Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 ASIC Interface 5 5 1 Mode Registers In the VPC3 S parameter bits that access the controller directly or which the controller directly sets are combined in three Mode Registers 0 1 2 and 3 5 1 1 Mode Register 0 Setting parameters for Mode Register 0 may take place in the Offline state only for example after power on The VPC3 S may not exit the Offline state until Mode Register 0 all Control and Organizational Parameters are loaded START VPC3 1 in Mode Register 1 Bit Position Address 7 6 5 4 3 2 1 0 Designation 06H Mode Reg 0 Intel x nte E g
55. VPC3 S User Manual Revision 1 06 A profichip automation in silicon Liability Exclusion We have tested the contents of this document regarding agreement with the hardware and software described Nevertheless there may be deviations and we do not guarantee complete agreement The data in the document is tested periodically however Required corrections are included in subsequent versions We gratefully accept suggestions for improvements Copyright Copyright profichip GmbH 2009 2012 All Rights Reserved Unless permission has been expressly granted passing on this document or copying it or using and sharing its content are not allowed Offenders will be held liable All rights reserved in the event a patent is granted or a utility model or design is registered This document is subject to technical changes Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Table of Contents 1 MITDEUEBBN ae 5 2 Functional Description 7 ANE U m 7 3 Pin Besefplen an ner 9 OMM 9 3 2 Pin Assignment Overview seesem 11 3 2 1 Asynchronous Intel Mode 13 3 2 2 Synchronous Intel Mode 14 3 2 3 Asynchronous Motorola Mode ssss 15 3 2 4 Synchronous Motorola Mode
56. XBout Buf Length of the 3 DXBout Buf 23H R DXBout Buf Ptr1 Segment base address of DXBout_Buf 1 24H R Len Diag Buf1 Length of Diag Buf 1 25H R Len Diag Buf2 Length of Diag_Buf 2 26H R Diag Buf Ptr1 Segment base address of Diag Buf 1 27H R Diag Buf Ptr2 Segment base address of Diag Buf 2 Length of Aux Buf 1 and the 28H R Len Cntrl Bufi See example Read_Cfg_Buf Length of Aux_Buf 2 and the 29H R Len Cntrl Buf2 e nno PCIE example Read_Cfg_Buf Bit array defines the assignment of the 2AH R_Aux_Buf_Sel Aux_Buf 1 and 2 to the control buffers SSA_Buf Prm_Buf Cfg_Buf 2BH R Aux Buf Ptr1 Segment base address of Aux Buf 1 2CH R Aux Buf Ptr2 Segment base address of Aux Buf 2 aDH f Len SSA Dat ae zen R SSA But Pr ah 2FH R_Len_Prm_Data Length of the input data in the Prm_Buf VPC3 S User Manual Revision 1 06 23 Copyright profichip GmbH 2012 4 Memory Organization 24 Address Intel Mot Name Bit No Significance 30H R Prm Buf Ptr Segment base address of the Prm_Buf 31H R Len Cfg Data Length of the input data in the Cfg_Buf 32H R Cfg Buf Ptr Segment base address of the Cfg Buf 33H R Len Read Cfg Data Length of the input data in the Read Cfg Buf Segment base address of the 34H R Read Cfg Buf Ptr Read Cfg Buf 35H R Len DXB Link Buf Length of the DXB Linktable Segment base address of the 36H R DXB Link Buf Ptr DXB Link Buf 37H R Len DXB Status Buf Length of the DXB
57. allel Interface GND E4 28 MOT XINT l 0 Intel Format GND D4 33 MODE 0 Asynchronous Interface Mode GND C5 35 AB11 I Address Lines Bit 11 CPU Address Bus 11 C2 2 AB10 B3 44 AB9 A1 48 ABS S Bi 1 AB7 S C3 45 AB6 B2 46 ABS Address Lines Bits 10 0 yn ress Bus 10 0 B4 41 AB4 A5 38 AB3 A6 37 AB2 l B5 39 AB1 B6 36 ABO G4 20 DB7 IO H5 23 DB6 IO H6 24 DB5 IO G5 22 DB4 IO Data Bus 7 0 CPU Data Bus 7 0 G6 25 DB3 IO F4 21 DB2 IO F6 27 DB1 IO F5 26 DBO IO C1 3 XCS Chip Select Signal active low CPU Chip Select D5 32 XWR Write Signal active low CPU Write C6 34 XRD Read Signal active low CPU Read VPC3 S User Manual Copyright O profichip GmbH 2012 Figure 3 4 Interface Configuration Asynchronous Intel Mode Revision 1 06 13 3 Pin Description 3 2 2 Synchronous Intel Mode In Synchronous Intel Mode the lower 8 bits of the address lines are multiplexed with the 8 bit data bus DB 7 0 The upper address lines bits 10 to 8 need to be connected to the AB 2 0 inputs of the VPC3 S Address line 11 is to be connected to pin BGA C1 QFP 3 of the VPC3 S XREADY mechanism is not supported in this interface mode E En Signal Name In Out Descrip
58. an be used for parameterization This service is only available in state WAIT CFG after the reception of a Set_Prm telegram and before the reception of a Chk_Cfg telegram The new Set_Ext_Prm telegram simply consists of Structured_Prm_Data blocks The new service uses the same buffer handling as described by Set_Prm By means of the New_Ext_Prm_Data interrupt the user can recognize which kind of telegram is entered in the Parameter Buffer Additional the SAP 53 must be activated by Set_Ext_Prm_Supported bit in Mode Register 0 The Aux Buffer for the Set_Ext_Prm is the same as the one for Set_Prm and has to be different from the Chk_Cfg Aux Buffer Furthermore the Spec_Prm_Buf_Mode in Mode Register 0 must not be used together with SAP 53 7 2 PROFIBUS DP V1 7 2 1 60 Acyclic Communication Relationships The VPC3 S supports acyclic communication as described in the DP V1 specification Therefore a memory area is required which contains all SAPs needed for the communication The user must do the initialization of this area SAP List in Offline state Each entry in the SAP List consists of 7 bytes The pointer at address 17H contains the segment base address of the first element of the SAP List The last element in the list is always indicated with FFH If the SAP List shall not be used the first entry must be FFH so the pointer at address 17H must point to a segment base address location that contains FFH The new communication features
59. are supposed to be present simultaneously during start up the user must maintain the Set Prm and then the Chk_Cfg acknowledgement sequence Bit Position Address Designation 7 6 5 4 3 2 1 0 User Cf 10H 0 0 0 0 0 0 y U a Data_Okay 0 0 User_Cfg_Finished 0 1 Cfg Conflict 1 1 Not Allowed Bit Position Address Designation 7 6 5 4 3 2 1 0 User Cf uH oj ol ooj ol o U U zie Data Not Okay 0 0 User Cfg Finished 0 Cfg Conflict 1 1 Not Allowed Figure 6 8 Coding of User Cfg Not Okay Cmd 6 2 4 Slave Diag SAP 60 50 Diagnosis Processing Sequence Two buffers are available for diagnosis These two buffers can have different lengths One Diagnosis Buffer which is sent on a diagnosis request is always assigned to the VPC3 S The user can pre process new diagnosis data in the other buffer parallel If the new diagnosis data are to be sent the user issues the New Diag Cmd to make the request to exchange the Diagnosis Buffers The user receives confirmation of the buffer exchange with the Diag_Buffer_Changed interrupt When the buffers are exchanged the internal Diag_Flag is also set For an activated Diag Flag the VPC3 S responds during the next Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 PROFIBUS DP Extensions 6 Data_Exchange with high priority response data That signals the DP Master that
60. ast data receipt during current monitoring period DEFAULT 1 error free reception of Broadcast data during current monitoring period Figure 7 10 DXB Link Status Buf specific link is grey scaled Processing Sequence The VPC3 S processes DXBout Buffers like the Dout Buffers The only difference is that the DXBout Buffers are not cleared by the VPC3 S The VPC3 S writes the received and filtered broadcast data in the D buffer The buffer contains also the Publisher Address and the Sample Length After error free receipt the VPC3 S shifts the newly filled buffer from D to N In addition the DXBout interrupt is generated The user now fetches the current output data from N The buffer changes from N to U with the Next DXBout Buffer Cmd VPC3 S User Manual Revision 1 06 67 Copyright O profichip GmbH 2012 7 PROFIBUS DP Extensions Bit Position Byte Designation 7 6 5 4 3 0 0 Publisher_Addr 1 Sample_Length 2 Sample_Data 246 Figure 7 11 DXBout Buffer When reading the Next_DXBout_buffer_Cmd the user gets the information which buffer U buffer is assigned to the user after the change or whether a change has taken place at all Bit Position Address 7 6 5 4 3 Designation 12H F U D DXBout_Buffer_SM DXBout Buffer SM Address OAH bit 7 6 F Assignment of the F Buffer 00 Nil 0
61. ational Specifications 111 10 1 Absolute Maximum Ratings 111 10 2 Recommended Operating Conditions 111 10 3 General DC Characteristics 111 10 4 Ratings for the Output Drivers 112 10 5 DC Electrical Characteristics 112 10 6 Timing Charatleristies ee pe Os su a xu Ere UEEUE 113 10 6 1 System Bus Interface ere ens 113 10 6 2 Timing in the Synchronous Intel Mode 114 10 6 3 Timing in the Asynchronous Intel Mode 116 10 6 4 Timing in the Synchronous Motorola Mode 118 10 6 5 Timing in the Asynchronous Motorola Mode 120 10 6 6 Timing in SPI Interface Mode 123 10 6 7 Timing in I2C Interface Mode 125 10 7 Package Specifications uun444444444nnnnnnnnnnnnnnnnnnnnnnnn 126 DUvANBIIII I 126 1072 LOFERS m 128 10 8 Processing Instr ctonss aaeene ee 130 10 9 Ordering Information ann 130 Revision History ee 131 4 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Introduction 1 Profichip s VPC3 S is a communication chip with 8 Bit parallel processor interface for intelligent PROFIBUS DP Slave applications Alternatively an SPI or IC interface can be used to communicate with the chip The VPC3 S handles the message and a
62. atus2 0 21ms bit 4 3 1 10 ms r 00 2 100 ms 3 1s Clock_Value_ Reserved Status2 bit 2 1 r 00 Clock Value SYF Synchronisation Active Status 0 Clock Value Time Event is synchronized x 1 Clock Value Time Event is not synchronized r 0 Clock Value Time Event Same format as defined in IEC 61158 6 is used Value is stored with the most significant byte at the lowest address No address swapping is done for Intel format r 0 Receive Delay Time Value is stored with the most significant byte in address 12 No address swapping is done for Intel format r 0 Clock Value previous TE Same format as defined in IEC 61158 6 is used Value is stored with the most significant byte at the lowest address No address swapping is done for Intel format rw 0 Clock Sync Interval Value is stored with the most significant byte in address 24 No address swapping is done for Intel format Figure 7 29 Format of the Clock Sync Buffer 84 VPC3 S User Manual Copyright O profichip GmbH 2012 Revision 1 06 PROFIBUS DP Extensions 7 VPC3 S Firmware set CS_Supported reception of Set_ Ext_ Prm set New_ Ext_ Prm_Data interrupt acknowledge interrupt write Clock Sync Interval to CS Buffer reception of Time Event start Receive Delay Timer reception of Clock Value set Clock Sync interrupt read CS Status IF Set Time 1 THEN stop Receive Delay Timer read CS Buffer update system time END IF acknowledge int
63. ccess to the VPC3 S is derived from the rising edge of the E Clock in addition XCS 0 R W 1 The request for a write access is derived from the falling edge of the E Clock in addition XCS 0 RW 0 re Sr gt E_CLOCK AB10 0 DB7 0 data valid R_W 7 Le XCS 38 Figure 10 14 Synchronous Motorola Mode READ AS 1 118 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Operational Specifications 10 e sr gt E CLOCK 33 37 ARI ee 41 22 DB7 0 data valid RW Dec 352 XCS 36 40 Figure 10 15 Synchronous Motorola Mode WRITE AS 1 No Parameter MIN MAX Unit 31 E Clock pulse width 136 7 ns 33 Address setuptime A10 0 to E Clock f 10 ns 37 Address holdtime after E Clock 4 0 ns 32 E Clock f to Data valid 83 ns 38 Data holdtime after E Clock 4 3 12 ns 35 R W setuptime to E Clock T 10 ns 39 R W holdtime after E Clock 4 5 ns 36 XCS setuptime to E Clock f 0 ns 40 XCS holdtime after E Clock 4 0 ns 41 Data setuptime to E Clock 4 10 ns 42 Data holdtime after E Clock 4 0 ns Figure 10 16 Timing Synchronous Motorola Mode VPC3 S User Manual Revision 1 06 119 Copyright O profichip GmbH 2012 10 Operational Specifications 10 6 5 Timing in the Asynchronous Motorola Mode In the asynchronous Motorola mode the VPC3 S acts like a memory with Ready logic
64. ct byte position of the 16 bit data bus during reading or the least significant address bit is not connected and the 80286 must read word accesses and evaluate only the lower byte Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Hardware Interface 8 Name On Type Comments DB 7 0 VO Tristate High resistance during RESET AB 10 0 AB 10 has a pull down resistor MODE Configuration syn async interface XWR E_CLOCK Intel Write Sync Motorola E Clk AB11 AB11 Asynchronous Motorola Mode XRD R_W Intel Read Motorola Read Write XCS Chip Select AB11 AB11 Synchronous Intel Mode ALE AS Intel Motorola Address Latch Enable AB11 AB11 Async Intel Sync Motorola Mode DIVIDER Scaling factor 2 4 for CLKOUT 2 4 X INT O Push Pull Polarity programmable XRDY XDTACK O Push Pull Intel Motorola Ready Signal CLK 48 MHz XINT MOT Setting Intel Motorola CLKOUT2 4 O Push Pull 24 12 MHz RESET Schmitt Trigger Minimum of 4 clock cycles Figure 8 2 Microprocessor Bus Signals Due to compatibility reasons to existing competitive chips the XRDY XDTACK output of the VPC3 S has push pull characteristic no tristate Synchronous Intel Mode In this mode Intel CPUs like 80C51 52 32 and compatible processor series from several manufacturers can be used Synchronous bus timing without evaluation of the XREADY signal 8 bit multiplexed bus
65. d 1 Sync_ Mode is supported bit 5 Early_Rdy Early Ready rw 0 0 Normal Ready Ready is generated when data is valid write or when data has been accepted read 1 Ready is generated one clock pulse earlier bit 4 INT_Pol Interrupt Polarity rw 0 0 The interrupt output is low active 1 The interrupt output is high active bit 3 CS_Supported Enable Clock Synchronization rw 0 0 Clock Synchronization is disabled default 1 Clock Synchronization is enabled bit 2 WD Base Watchdog Time Base rw 0 0 Watchdog time base is 10 ms default state 1 Watchdog time base is 1 ms bit 1 Dis Stop Control Disable Stopbit Control rw 0 0 Stop bit monitoring is enabled 1 Stop bit monitoring is switched off Set_Prm telegram overwrites this memory cell in the DP_Mode Refer to the user specific data bit 0 Dis Start Control Disable Startbit Control rw 0 0 Monitoring the following start bit is enabled 1 Monitoring the following start bit is switched off Set_Prm telegram overwrites this memory cell in the DP_Mode Refer to the user specific data Figure 5 1 Coding of Mode Register 0 Low Byte 26 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 ASIC Interface 5 Mode Register 0 High Byte Address 07H Intel bit 15 Reserved rw 0 bit 14 PrmCmd_Supported PrmCmd support for redundancy rw 0 0 PrmCmd is not supported 1 PrmCmd is suppor
66. ddress identification the data security sequences and the protocol processing for PROFIBUS DP In ad dition the acyclic communication and alarm messages described in DP V1 extension are supported Furthermore the slave to slave communication Data eXchange Broadcast DXB and the Isochronous Bus Mode IsoM described in DP V2 extension are also provided For high precision syn chronized motion control applications the chip is equipped with an HW PLL for IsoM Automatic recognition and support of data transmissions rates up to 12 Mbit s the integration of the complete PROFIBUS DP protocol 4K Byte communication RAM and the configurable processor interface are features to create high performance PROFIBUS DP Slave applications The device is to be operated with 3 3V single supply voltage All inputs are 5V tolerant Profichips VPC3 S is another member of profichips successful VPC3 family It is software compatible to other VPC3 series devices however it offers some unique features like serial processor interfaces IsoM PLL and a very small package As there are also simple devices in the automation engineering area such as switches or thermo elements that do not require a microcontroller for data preprocessing profichip offers a DP Slave ASIC with 32 direct in put output bits The VPCLS2 handles the entire data traffic independently No additional microprocessor or firmware is necessary The VPCLS2 is compatible to existing chips Furt
67. e IAR except for New_ Ext_ Prm_Data and New_Cfg_ Data A logical 1 must be written on the specific bit position If a new event and an acknowledge from the previous event are present at the IRR at the same time the event remains stored If the microcontroller enables a mask subsequently it must be ensured that no prior IRR input is present To be on the safe side the position in the IRR must be deleted prior to the enabling of the mask Before leaving the interrupt routine the microprocessor must set the end of interrupt bit EOI 1 in Mode Register 1 The interrupt output is switched to inactive with this edge change If another event occurs the interrupt output is not activated again until the interrupt inactive time of at least 1 us or 1 ms expires This interrupt inactive time can be set via EOI Time Base in Mode Register 0 This makes it possible to enter the interrupt routine again when an edge triggered interrupt input is used Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 ASIC Interface 5 The polarity of the interrupt output is parameterized via the Int_Pol bit in Mode Register 0 After hardware reset the output is low active 5 3 1 Interrupt Request Register Bit Position Address 7 6 5 4 3 2 1 0 Designation 00H 5 Int Req Reg Intel 9 7 0 E T SE L TENE 5 4 o i GIg o See below 5 zo c E O 8 gx amp gt for c
68. e Range Notes Part Number Industrial VPC3 S BGA48 PALF2009 LFBGA48 40 C to 85 C Industrial VPC3 S QFP48 PALF2012 LQFP48 40 C to 85 C 130 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Revision History Version Date Page Remarks V1 00 01 04 2009 First release V1 01 10 08 2009 29 Description of GC Int Mode Ext in Mode Register 3 corrected 72 77 Some hints for configuration of PLL added 96 Name of I2C clock changed from SCL to SCK 111 Current consumption and thermal resistance added V1 02 25 05 2010 92 SPI instruction WRITE ARRAY added to Figure 8 6 95 Instruction coding in Figure 8 10 WRITE ARRAY Sequence corrected V1 03 28 05 2010 122 Timing table for SPI interface mode corrected MIN MAX values swapped 123 Timing table for I2C interface mode corrected MIN MAX values swapped V1 04 10 10 2012 10 17 Pin assignment of LQFP48 package version added 111 Thermal resistance of LQFP48 package added 128 129 LQFP48 package drawing added 130 Processing instructions revised and ordering information added V1 05 18 02 2014 10 11 AB11 pin 3 added to pinout figure and pin assignment table 130 Part number added to ordering information V1 06 18 07 2014 13 16 Notes regarding external pull up on TXD added 89 90 Modification of signal names 105 107 Modification of figure 8 23 8 24 8 25 8 26 8 27 9 2 109 110 VPC3 S User Man
69. e next byte transmitted by the master is the high order byte of the address and will be written into the Address Pointer of the VPC3 S The next byte is the Least Significant Address Byte After receiving another Acknowledge signal from the VPC3 S the master device will transmit the data byte to be written into the addressed memory location The VPC3 S acknowledges again and the master either generates a STOP condition or transfers more data bytes to the VPC3 S Upon receipt of each data byte the VPC3 S generates an Acknowledge signal and the internal Address Pointer is incremented by 1 When the highest address is reached 0x7FF in case of 2 kB RAM mode or OxFFF in 4 kB mode the address counter rolls over to address 0x000 allowing the write sequence to be continued indefinitely The write operation is terminated by receiving a STOP condition from the master Address High Byte Address Low Byte Data Byte 0 Data Byte n 17 gt 0 100 ou zjelsle gt lz1 Je tisser PP A A c Figure 8 16 I2C WRITE Sequence READ Operations Read operations are initiated in the same way as write operations with the exception that the R W bit of the control byte is set to 1 There are three basic types of read operations current address read random read and sequential read Current Address READ Operation The VPC3 S contains an address counter that maintains the address of the last byte accessed internally incremented by 1 The
70. e set to OOH for this purpose The DP SAP Buffer Structure is shown in Figure 6 1 The user configures all buffers length and buffer start in the Offline state During operation the buffer configuration must not be changed except for the length of the Dout Din Buffers The user may still adapt these buffers in the WAIT CFG state after the con figuration telegram Chk Cfg Only the same configuration may be accepted in the DATA EXCH state The buffer structure is divided into the data buffers Diagnosis Buffers and the control buffers Both the output data and the input data have three buffers available with the same length These buffers are working as changing buffers One buffer is assigned to the data transfer D and one buffer is assigned to the user U The third buffer is either in a next state N or a free state F One of the two states is always unoccupied For diagnosis two Diagnosis Buffers that can have different lengths are available One Diagnosis Buffer D is always assigned to the VPC3 S for sending The other Diagnosis Buffer U belongs to the user for preprocessing new diagnosis data VPC3 S User Manual Revision 1 06 41 Copyright O profichip GmbH 2012 6 PROFIBUS DP Extensions 42 Be N U Dout Buffer 4 D N changed N U changed by VPC3 by User N 1 U Din Buffer lt gt Diagnosis U Buffer Read_Config Buffer A changed by User Config Buffer
71. errupt Figure 7 30 communication scheme VPC3 S User Manual Revision 1 06 85 Copyright O profichip GmbH 2012 7 PROFIBUS DP Extensions Notes 86 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 8 1 8 1 1 Hardware Interface 8 Universal Processor Bus Interface Overview The VPC3 S can be interfaced by using either a parallel 8 bit data interface or an SPI or I2C interface In parallel mode the VPC3 S provides an 8 bit data interface with an 11 bit address bus The VPC3 S supports all 8 bit processors and micro controllers based on the 80C51 52 80C32 from Intel the Motorola HC1 1 family as well as 8 16 bit processors or microcontrollers from the Siemens 80C166 family X86 from Intel and the HC16 and HC916 family from Motorola Because the data formats from Intel and Motorola are different VPC3 S automatically carries out byte swapping for accesses to the following 16 bit registers Interrupt Register Status Register and Mode Register 0 and the 16 bit RAM cell R User WD Value This makes it possible for a Motorola processor to read the 16 bit value correctly Reading or writing takes place as usual through two accesses 8 bit data bus Four SPI modes are supported which differ in clock polarity and clock phase In these interface modes the VPC3 S acts like a memory device with serial SPI interface connected to the CPU The chip needs to be selected by pulling the Slave Select p
72. et the output data with 0 during start up so that no invalid data can be sent here If there is a buffer change from N to U through the VPC3 S User Manual Revision 1 06 57 Copyright O profichip GmbH 2012 6 PROFIBUS DP Extensions Next Dout Buffer Cmd between the first call up and the repetition the new output data is sent during the repetition 6 2 9 Get Cfg SAP 59 58 The user makes the configuration data available in the Read Config Buffer For a change in the configuration after the Chk Cfg telegram the user writes the changed data in the Config Buffer sets En Change Cfg buffer 1 see Mode Register 1 and the VPC3 S then exchanges the Config Buffer for the Read Config Buffer If there is a change in the configuration data during operation for example for a modular DP systems the user must return with Go Offline command see Mode Register 1 to WAIT PRM Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 7 1 PROFIBUS DP Extensions Set_ Ext_ Prm SAP 53 SAP 61 The PROFIBUS DP extensions require three bytes to implement the new parameterization function The bits of the Spec User Prm Byte are included Bit Position Byte Designation 7 6 5 4 3 2 1 0 0 p DPV1 Status 1 DPV1 Enable Fail Safe Publisher Enable Reserved Reserved WD Base Dis Sto Control Dis Start Control Specific Alarm Enable g Alarm g Mode DPV1 Sta
73. exchange or whether both buffers are currently assigned to the VPC3 S No Buffer Diag Buf1 Diag Buf2 VPC3 S User Manual Revision 1 06 51 Copyright profichip GmbH 2012 6 PROFIBUS DP Extensions Bit Position Address Designation 7 6 5 4 3 2 1 0 New_Dia ODH 0 0 0 0 0 0 U U i om Buffer Cmd 0 O No Buffer 0 1 Diag Buf1 1 0 Diag Buf2 Figure 6 10 Coding of New Diag Cmd Bit Position i i Byte Designation 7 e s ae ls Paya g D D gt G o a i Oo 0 g A a E E al no 1 2 3 4 5 E Ext Diag Data user input n max 243 Figure 6 11 Format of the Diagnosis Buffer The Ext Diag Data must be entered into the buffers after the VPC3 S internal diagnosis data Three different formats are possible here device related ID related and port related If PROFIBUS DP extensions shall be used the device related diagnosis is substituted by alarm and status messages In addition to the Ext_Diag_Data the buffer length also includes the VPC3 S diagnosis bytes R Len Diag Buf 1 R Len Diag Buf 2 6 2 5 Write Read Data Data Exchange Default SAP 52 Writing Outputs The VPC3 S writes the received output data in the D buffer After an error free receipt the VPC3 S shifts the newly filled buffer from D to N In addition the DX Out interrupt is generated The user now fetches the
74. fer management This operation mode is recommended for the most applications If another DP Master takes over the VPC3 S the Watchdog State Machine either branches to BAUD CONTROL WD On 0 or to DP CONTROL WD On 1 40 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 PROFIBUS DP Extensions 6 6 1 DP Buffer Structure The DP Mode is enabled in the VPC3 S with DP Mode 1 see Mode Register 0 In this mode the following SAPs are permanently reserved Default SAP Write and Read data Data Exchange SAP 53 Sending extended parameter setting data Set Ext Prm SAP 55 Changing the Station Address Set Slave Add SAP 56 Reading the inputs RD Input SAP 57 Reading the outputs RD Output SAP 58 Control commands to the DP Slave Global Control SAP 59 Reading configuration data Get Cfg SAP 60 Reading diagnosis information Slave Diag SAP 61 Sending parameter setting data Set Prm SAP 62 Checking configuration data Chk Cfg The DP Slave protocol is completely integrated in the VPC3 S and is handled independently The user must correspondingly parameterize the ASIC and process and acknowledge received messages All SAPs are always enabled except the Default SAP SAP 56 SAP 57 and SAP 58 The remaining SAPs are not enabled until the DP SM goes into the DATA EXCH state The user can disable SAP 55 to not permit changing the Station Address The corresponding buffer pointer R SSA Buf Ptr must b
75. ffline state rw 0 1 After the current request ends VPC3 S goes to the Offline state and sets Go Offline to 0 again bit 1 EOI End of Interrupt rw 0 1 VPC3 S disables the interrupt output and sets EOI to 0 again bit O Start_VPC3 Exiting the Offline state rw 0 1 VPC3 S exits offline and goes to Passive Idle In addition the Idle Timer and Watchdog Timer are started and Go Offline 0 is set Figure 5 3 Coding of Mode Register 1 28 Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 ASIC Interface 5 5 1 3 Mode Register 2 Setting parameters for Mode Register 2 may take place in the Offline State only like Mode Register 0 Bit Position 3 Address 7 6 5 4 3 2 1 0 Designation 0 0 0 0 0 0 1 Reset Value OCH Mode Reg 2 3 o TD o 7 0 9 lal Z c 8 i gt 8 i o SD AT o GO o oo al sal og csl 16 o E 5c amp m o E x xl d o i Z 77 a Oo zoo VPC3 S User Manual Revision 1 06 29 Copyright O profichip GmbH 2012 5 ASIC Interface Mode Register 2 Address 0CH bit 7 4KB Mode size of internal RAM w 0 0 2K Byte RAM default 1 4K Byte RAM bit 6 No_Check_Prm_Reserved disables checking of the reserved bits in w 0 DPV1_Status_2 3 of Set_Prm telegram 0 reserved bits of a Set_Prm telegram are checked default 1 reserved bits of a Set_Prm telegram are not checked bi
76. fline bit Clock Sync used if CS Supportedz1 The VPC3 D has received a Clock Value telegram or an error occurs Further differentiation is made in the Clock Sync Buffer Figure 5 9 Interrupt Request Register Low Byte Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 ASIC Interface 5 Interrupt Request Register 0 High Byte Address 01H Intel bit 15 rw 0 FDL Ind The VPC3 S has received an acyclic service request and made the data available in an Indication Buffer bit 14 rw 0 Poll End Ind The VPC3 S have send the response to an acyclic service bit 13 rw 0 DX_Out The VPC3 S have received a Data_Exchange telegram and made the new output data available in the N buffer bit 12 rw 0 Diag_Buffer_Changed Due to the request made by New_Diag_Cmd the VPC3 S exchanged the Diagnosis Buffers and made the old buffer available to the user again bit 11 rw 0 New_Prm_Data The VPC3 S have received a Set_Prm telegram and made the data available in the Parameter Buffer bit 10 rw 0 New_Cfg_Data The VPC3 S have received a Chk_Cfg telegram and made the data available in the Config Buffer bit 9 rw 0 New_SSA Data The VPC3 S have received a Set_Slave Add telegram and made the data available in the Set Slave Add Buffer bit 8 rw 0 New_GC Command The VPC3 S have received a Global_Control telegram and stored the Cont
77. fore all buffers must be located at the beginning of a segment If the VPC3 S carries out a DP communication it automatically sets up all DP SAPs The various telegram information is made available to the user in separate data buffers for example parameter and configuration data Three buffers are provided for data communication three for output data and three for input data As one buffer is always available for communica tion no resource problems can occur For optimal diagnosis support the VPC3 S offers two Diagnosis Buffers The user enters the updated diagnosis data into these buffers One Diagnosis Buffer is always assigned to the VPC3 S The Bus Interface Unit is a parameterizable synchronous asynchronous 8 bit parallel interface for various Intel and Motorola microcontrollers pro cessors The user can directly access the internal 2K 4K Byte RAM or the parameter latches and control registers via the 11 12 bit address bus Alternatively serial standard protocols like SPI or I C can be used to access the VPC3 S Procedure specific parameters Station Address control bits etc must be transferred to the Parameter Registers and to the Mode Registers after power on VPC3 S User Manual Revision 1 06 7 Copyright O profichip GmbH 2012 2 Functional Description The MAC status can be observed at any time in the Status Register Various events e g various indications error events etc are entered in the Interrupt Controller
78. he connected processor microcontroller This is a synchronous or asynchronous 8 bit interface with an 11 bit 12 bit in 4K Byte mode address bus The interface is configurable via 2 pins XINT MOT MODE The connected processor family bus control signals such as XWR XRD or R W and the data format is specified with the XINT MOT pin Synchronous or asynchronous bus timing is specified with the MODE pin SERMODE XINT MOT MODE Processor Interface Mode 0 0 1 Synchronous Intel mode 0 0 0 Asynchronous Intel mode 0 1 0 Asynchronous Motorola mode 0 1 1 Synchronous Motorola mode Figure 8 1 Configuration of the parallel Processor Interface Modes Examples of various Intel system configurations are given in subsequent sections The internal address latch and the integrated decoder must be used in the synchronous Intel mode One figure shows the minimum con figuration of a system with the VPC3 S where the chip is connected to an EPROM version of the controller Only a clock generator is necessary as an additional device in this configuration If a controller is to be used without an integrated program memory the addresses must be latched for the external memory Notes If the VPC3 S is connected to an 80286 or similar processor it must be taken into consideration that the processor carries out word accesses That is either a swapper is necessary that switches the characters out of the VPC3 S at the corre
79. he pin names A and B on the plug connector refer to the signal names in the RS485 standard and not the pin names of driver ICs Keep the wires from driver to connector as short as possible Note TXD is tristate output and requires external pull up resistor for correct operation with common line drivers VPC3 S User Manual Revision 1 06 109 Copyright O profichip GmbH 2012 9 PROFIBUS Interface 9 2 Example for the RS485 Interface To minimize the capacity of the bus lines the user should avoid additional capacities The typical capacity of a bus station should be 15 25 pF SWIKLD SUBD_BUS resi VCC IS0 GND 150 R2 102 330R VCC_150 ap LE vec rs H 6 L Ic2 R R D D GND_ISO 74AHCT1 G00 R39 1K 5 VCC ISO GND 1S0 VCC 1S0 VCC IS0 GNDI GND2 R40 Lo 470R VPC3 you nua amp Notice TXD tristate pull up resistor required Figure 9 2 Example for the RS485 Interface 110 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Operational Specifications 10 10 1 Absolute Maximum Ratings Copyright profichip GmbH 2012 Parameter Symbol Limits Unit DC supply voltage VCC 0 3 to 3 9 V Input voltage Vi 0 3 to 5 5 V Output v
80. her information about our products or current and future projects is available on our web page http www profichip com VPC3 S User Manual Revision 1 06 5 Copyright O profichip GmbH 2012 1 Introduction Notes 6 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Functional Description 2 2 1 Overview The VPC3 S makes a cost optimized design of intelligent PROFIBUS DP Slave applications possible Due to the very flexible processor interface the VPC3 S supports a broad range of processor types and families Please check the corresponding chapters of this manual for details Here are just some common examples Intel 80031 80C51 80X86 and their derivates Siemens 80C166 165 167 Motorola HC11 HC16 and HC916 types ARM all ARM derivates with parallel SPI or I C interface The VPC3 S handles the physical layer 1 and the data link layer 2 of the ISO OSI reference model excluding the analog RS485 drivers The integrated 4K Byte Dual Port RAM serves as an interface between the VPC3 S and the software application In case of using 2K Byte the entire memory is divided into 256 segments with 8 bytes each Otherwise in the 4K Byte mode the segment base addresses starts at multiple of 16 Addressing by the user is done directly however the internal Micro Sequencer MS addresses the RAM by means of the so called base pointer The base pointer can be positioned at the beginning of a segment in the memory There
81. ht O profichip GmbH 2012 7 PROFIBUS DP Extensions Bit Position i Byte Designation 7 6 5 4 3 2 1 0 LU 0 AT m D Control a LLI 5 zZ oc z 1 Max Length 2 Length 3 Function Code SAP List entry Byte 0 Control bits for buffer management USER buffer assigned to user IND indication data included in buffer RESP response data included in buffer INUSE buffer assigned to VPC3 S Byte 1 Max Length length of buffer Byte 2 Length length of data included in buffer Byte 3 Function Code function code of the telegram Figure 7 4 Buffer Header Processing Sequence A received telegram is compared with the values in the SAP List If this check is positive the telegram is stored in an Indication Buffer with the INUSE bit set In case of any deviations the VPC3 S responses with no service activated RS or if no free buffer is available with no resource RR After finishing the processing of the incoming telegram the INUSE bit is reset and the bits USER and IND are set by VPC3 S Now the FDL Ind interrupt is generated Polling telegrams do not produce interrupts The RESP bit indicates response data provided by the user in the Response Buffer The Poll End Ind interrupt is set after the Response Buffer is sent Also bits RESP and USER are cleared 62 Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 PROFIBUS DP Extensions 7
82. ht O profichip GmbH 2012 6 PROFIBUS DP Extensions 48 Parameter Data Processing Sequence In the case of a positive validation of more than seven data bytes the VPC3 S carries out the following reaction The VPC3 S exchanges Aux Buffer 1 2 all data bytes are entered here for the Parameter Buffer stores the input data length in R Len Prm Data and triggers the New Prm Data interrupt The user must then check the User Prm Data and either reply with User Prm Data Okay Cmd or with User Prm Data Not Okay Cmd The entire telegram is entered in this buffer The user parameter data are stored beginning with data byte 8 or with byte 10 if DPV1 Status bytes used The user response User Prm Data Okay Cmd or User Prm Data Not Okay Cmd clears the New Prm Data interrupt The user cannot acknowledge the New Prm Data interrupt in the IAR register With the User Prm Data Not Okay Cmd message relevant diagnosis bits are set and the DP SM branches to WAIT PRM The User Prm Data Okay and User Prm Data Not Okay acknow ledgements are read accesses to defined registers with the relevant signals e User Prm Finished No additional parameter telegram is present e Prm Conflict An additional parameter telegram is present processing again e Not Allowed Access not permitted in the current bus state Bit Position 3 Address Designation 7 6 5 4 3 2 1 0 User Prm OEH 0 0 0 0 0 0 y y mM Data Okay 0 0 Use
83. ice slave devices that are not selected do not interfere with SPI bus activities The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format The CPHA clock phase control bit selects one of two fundamentally different transmission formats Clock phase and polarity should be identical for the master SPI device and the communicating slave device CPHA z 0 Transfer Format The first edge on the SCK line is used to clock the first data bit of the slave into the master and the first data bit of the master into the slave In some peripherals the first bit of the slave s data is available at the slave s data out pin as soon as the slave is selected In this format the first SCK edge is issued a half cycle after SS has become low A half SCK cycle later the second edge appears on the SCK line When this second edge occurs the value previously latched from the serial data input pin is shifted into the shift register Transfer SCK Edge Nr SCK CPOL 0 SCK CPOL 1 SAMPLE MOSI MISO MOSI MISO XSS Figure 8 4 SPI Transfer Format CPHA 0 92 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Hardware Interface 8 After this second edge the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave This process continues for a total of 16 edges on the S
84. in SPI XSS low before receiving clock pulses via SPI SCK pin from the CPU Depending on the OP code received the VPC3 S carries out a read or write operation starting at the specified address inside the internal memory Serial data is shifted in via SPI MOSI pin and shifted out via SPI MISO pin In I2C mode the VPC3 S can be connected to an I2C network by using the pins I2C SCK and I2C SDA In this mode the VPC3 S acts like a memory device with serial I2C interface connected to the CPU The chip supports slave mode only and the desired slave address can be selected by using the pins I2C_A 6 0 Upon reception of the correct slave address and depending on the status of the R W bit the VPC3 S carries out a read or write operation starting at the specified address inside the internal memory The Bus Interface Unit BIU and the Dual Port RAM Controller DPC that controls accesses to the internal RAM belong to the processor interface of the VPC3 S The VPC3 S is supplied with a clock pulse rate of 48MHz In addition a clock divider is integrated The clock pulse is divided by 2 Pin DIVIDER 1 or 4 Pin DIVIDER 0 and applied to the pin CLKOUT This allows the connection of a slower controller without additional expenditures in a low cost application VPC3 S User Manual Revision 1 06 87 Copyright O profichip GmbH 2012 8 Hardware Interface 8 1 2 Parallel Interface Modes 88 The Bus Interface Unit BIU is the interface to t
85. interfaced like an SPI compatible memory device Depending on the setting of CPOL and CPHA four different SPI modes can be selected All unused inputs including DB 7 0 must be connected to GND Ball Pin Signal Name In Out Description Connect to BGA QFP E3 9 SERMODE 1 Serial Interface VCC E4 28 MOT XINT 0 not used in this mode GND D4 33 MODE 0 SPI Mode GND C2 2 SPI CPOL Clock Polarity VCC or GND B3 44 SPI CPHA Clock Phase VCC or GND C1 3 SPI XSS Slave Select Signal active low CPU Slave Select A1 48 SPI SCK S Serial Clock CPU SCK B1 1 SPI MOSI Master Out Slave In Serial Data Input CPU MOSI A2 47 SPI MISO O Master In Slave Out Serial Data Output CPU MISO Figure 3 8 Interface Configuration SPI Mode 3 2 6 12C Mode The VPC3 S can be interfaced like an I2C compatible memory device The VPC3 S is always in slave mode master mode is not supported The slave address can be configured by using the AB 6 0 inputs All unused inputs including DB 7 0 must be connected to GND Ball Pin BGA QFP Signal Name In Out Description Connect to E3 9 SERMODE 1 Serial Interface VCC E4 28 MOT XINT I 0 not used in this mode GND D4 33 MODE 1 I2C Mode VCC C3 45 12C_SA6 VCC or GND B2 46 12C_SA5 VCC or GND B4 41 12C_SA4 VCC or GND
86. ion is selected The next two bytes received define the address of the first data byte Figure 8 15 In case of the 4 kB RAM mode is selected only A11 to AO are used the upper four address bits are don t care bits in case of 2 kB RAM mode the upper five address bits are don t care The upper address bits MSB are transferred first followed by the Less Significant bits LSB Following the Start condition the VPC3 S monitors the SDA line checking the control byte transmitted and upon receiving appropriate Slave Address bits the device outputs an Acknowledge signal on the SDA line Depending on the state of the R W bit the VPC3 S will select a read or write operation Control Byte Address High Byte Address Low Byte SA6 SA5 SA4 SA3 SA2 SA1 SAO R W X X X X At1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO Slave Address Figure 8 15 Address Sequence Bit Assignments VPC3 S User Manual Revision 1 06 99 Copyright profichip GmbH 2012 8 Hardware Interface Control Byte WRITE Sequence Following the START condition from the master Slave Address 6 bits and the R W bit which is a logic low are clocked onto the bus by the master transmitter This indicates to the addressed slave receiver that the address high byte will follow once it has generated an Acknowledge bit during the ninth clock cycle Therefore th
87. ion is reported several diagnosis bits are changed and the VPC3 S branches to state WAIT PRM For a correct configuration the transition to DATA EXCH takes place immediately if trigger counters for the parameter telegrams and configuration telegrams are at 0 When entering into DATA EXCH the VPC3 S also generates the Go Leave DATA EXCH Interrupt If the received configuration data from the Config Buffer is supposed to result in a change to the Read Config Buffer contains the data for the Get Cfg telegram the user have to make the new Read Config data available in the Read Config Buffer before the User Cfg Data Okay Cmd acknowledgement that is the user has to copy the new configuration data into the Read Config Buffer During acknowledgement the user receives information about whether there is a conflict or not If another Chk Cfg telegram was supposed to be VPC3 S User Manual Revision 1 06 49 Copyright O profichip GmbH 2012 6 PROFIBUS DP Extensions received in the meantime the user receives the Cfg Conflict signal during the positive or negative acknowledgement of the first Chk Cfg telegram Then the user must repeat the validation because the VPC3 S have made a new Config Buffer available The User Cfg Data Okay Cmd and User Cfg Data Not Okay Cmd acknowledgements are read accesses to defined memory cells with the relevant Not Allowed User Cfg Finished or Cfg Conflict signals If the New Prm Data and New Cfg Data
88. ions 7 Subscriber A Subscriber requires information about the links to its Publishers These settings are contained in a DXB Linktable or DXB Subscribertable and transferred via the Structured_Prm_Data in a Set_Prm or Set_Ext_Prm telegram Each Structured Prm Data is treated like the User Prm Data and therefore to be evaluated by the user From the received data the user has to generate DXB Link Buf and DXB Status Buf entries The watch dog must be enabled to make use of the monitoring mechanism The user must check this Bit Position Byte Designation 7 6 5 4 3 2 1 0 0 Structured Length k _ Structure_Type Slot Number Reserved O oioj o OoOj o o o o o o Oo o o o Oo OTO JOJ GJO OJO Oj o o E Version Publisher Addr Publisher Length Sample Offset Sample Length OI III AJOJN further link entries E me eo Figure 7 8 Format of the Structured Prm Data with DXB Linktable specific link is grey scaled VPC3 S User Manual Revision 1 06 65 Copyright O profichip GmbH 2012 7 PROFIBUS DP Extensions 66 Bit Position k Byte Designation 7 6 5 4 3 2 1 0 0 Structured Length 1 1 1 Structure Type Slot Number ojo Reserved O o o o Oloj oj o O o o o O o o o O o o o D O O OoO o o 1 Version Publisher Addr Publisher Length Sample Offset
89. ip GmbH 2012 Hardware Interface 8 Each receiving device when addressed is obliged to generate an Acknowledge after the reception of each byte The master device must generate an extra clock pulse which is associated with this Acknowledge bit The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse Of course setup and hold times must be taken into account During reads a master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave In this case the slave VPC3 S will leave the data line high to enable the master to generate the Stop condition A control byte is the first byte received following the Start condition from the master device Figure 8 14 The control byte consists of a seven bit Slave Address SA 6 0 to select which device is accessed The Slave Address bits in the control byte must correspond to the logic levels on the I2C SA 6 0 pins for the VPC3 S to respond Read Write Bit m SA6 SA5 SA4 SA3 SA2 SA1 sao Rack Slave Address START Condition Acknowledge Bit Figure 8 14 Control Byte Format S The last bit of the control byte defines the operation to be performed When set to a 1 a read operation is selected When set to a 0 a write operat
90. latch 11 7 AB 10 8 internal address CS 1 AB 15 11 all bits decoder internal chip zero select Figure 8 24 Internal Chipselect Generation in Synchronous Intel Mode 2K Byte RAM VPC3 S User Manual Revision 1 06 105 Copyright O profichip GmbH 2012 8 Hardware Interface 8 1 7 Application with 80C32 4K Byte RAM Mode VPC3 48MHz 22R CLK DIVIDER connect to VDD or GND CLKOUT GND o XINT MOT XDATAEX LED for Data Exchange Cac RESET XREADY9 X INT 9 C gt VDD MODE VDD VDD 5 XTESTO R 4k7 VDD 9 XTESTI TXD R5485 gt uc ALE RXD 885 c XRD XRD lt XWR AR RTS R5485 gt EX m XCTS aGND ABO T Ani ADB 0 AB 10 ABI ux ADBO ABII 4XCS ABII DHL R AB 13 7 ABA DBS ADB 3 ABT ABA DB4 R a ABS DBS ADB6 GND u AB 7 DB 6 NEN AB 8 15 GND m AB8 DB 7 uc GND AB 9 GND s AB 10 DB 0 7 Qc gt TxD tristate external pull up resistor required Figure 8 25 80C32 Application in 4K Byte mode The internal chipselect is activated when the address inputs AB 10 3 of the VPC3 S are set to O In the example above the start address of the VPC3 S is set to 2000H Q address latch AB 2 0 12 XCS ABII Processor VPC3 AB 10 8 AB 11 internal address AB 6 3 cs 1 decoder
91. mbH 2012 valid AB10 0 DB7 0 Operational Specifications 10 XWR XCS XREADY normal XREADY early Figure 10 12 Asynchronous Intel Mode WRITE XRD 1 No Parameter MIN MAX Unit 16 address setuptime to XRD XWR 4 0 ns 17 XRD i to data valid 83 ns 18 XRD pulsewidth 105 ns 19 XCS J setuptime to XRD XWR 4 0 ns 20 XRD J to XREADY J Normal Ready 125 ns 21 XRD J to XREADY Early Ready 104 ns 22 XRD XWR cycletime 125 ns 23 address holdtime after XRD XWR T 0 ns 24 data holdtime after XRD T 3 12 ns 25 read write inactive time 10 ns 26 XCS holdtime after XRD XWR T 0 ns 27 XREADY holdtime after XRD XWR 3 15 ns 28 data setuptime to XWR f 10 ns 29 XWR pulsewidth 83 ns 30 data holdtime after XWR f 0 ns Figure 10 13 Timing Asynchronous Intel Mode VPC3 S User Manual Revision 1 06 117 Copyright O profichip GmbH 2012 10 Operational Specifications 10 6 4 Timing in the Synchronous Motorola Mode If the CPU is clocked by the VPC3 S the output clock pulse CLKOUT 2 4 must be 4 times larger than the E_Clock That is a clock pulse signal must be present at the CLK input that is at least 10 times larger than the desired system clock pulse E Clock The Divider Pin must be connected to 0 divider 4 This results in an E Clock of 3 MHz The request for a read a
92. mple to set START VPC3 write a 1 to address 08H in order to reset this bit write a 1 to address 09H VPC3 S User Manual Revision 1 06 27 Copyright O profichip GmbH 2012 5 ASIC Interface Bit Position p 2 Address Designation 7 6 5 4 3 2 1 0 08H ui Mode Reg_1_S o gt d D D ale 7 0 9 Z s5 Zu if OM IE co N o oc o 24 o o o oo cgo o O rau ra c ceD5 uo 5 S uoo 09H w Mode Reg_1_R O5 7 0 TD D a cec fam en g g 3 Jul 9 9 Io sa 9 8 See below D da c as o O HF amp di or r2 uo 2z o Ep gt OP coadng Mode Register 1 Set Address 08H bit 7 Reserved rw 0 bit 6 Reserved rw 0 bit 5 Res User WD Resetting the User WD Timer rw 0 1 VPC3 S sets the User WD Timer to the parameterized value User WD Value After this action VPC3 S sets Res User WD to 0 bit 4 En Change Cfg Buffer Enabling buffer exchange Config Buffer for rw 0 Read_Config Buffer 0 With User_Cfg_Data_Okay_Cmd the Config Buffer may not be exchanged for the Read_Config Buffer 1 With User_Cfg_Data_Okay_Cmd the Config Buffer must be exchanged for the Read_Config Buffer bit 3 User_LEAVE MASTER Request to the DP_SM to go to WAIT PRM rw 0 1 The user causes the DP SM to go to WAIT PRM After this action VPC3 sets User LEAVE MASTER to 0 again bit 2 Go Offline Going into the O
93. nchronization via the Simple Sync Mode the bit DX Int Port in Mode Register 2 has to be set Bit SYNC Ena must not be set The settings of the pulse polarity are adjusted like described in the IsoM section For the parameterization telegram the DP format is used Though the DPV1 Status bytes 1 3 could be used as User Prm Data it is generally recommended starting the User Prm Data at byte 10 Bit Position Byte Designation 7 6 5 4 3 2 1 0 le WI E Uu oo E S of 2 y Tr 2s 0 TET JET Station_ Status o O 5 N 20 s9z2 3 oz n0 gt 25 gt Qu wn 1 WD Fact 1 2 WD Fact 2 3 minTspr 4 Ident_Number_High 5 Ident_Number_Low n eo 6 a Group_Ident 3 O 7 DPV1 Status 1 8 DPV1 Status 2 9 DPV1 Status 3 10 User Prm Data 246 Figure 7 19 Format of Set Prm for DP Slave using isochronous cycles In opposite to IsoM the first DX Out interrupt is generated after the receipt of a SYNCH telegram If no Data Exchange telegram had been received before a SYNCH occurred no synchronization signal is generated For this mechanism the interrupt controller is used Hence no signal will be generated if the mask for DX Out in the IMR is set Since the synchronization signal is now the DX Out interrupt it remains active until the interrupt is acknowledged VPC3 S User Manual Revision 1 06 73 Copyright O profichip GmbH 2012 7 PROFIBUS DP Extensions 7 3 2 1 ISOM PLL
94. nd address busses are separate non multiplexed When using HC11 types with a multiplexed bus the address signals AB 7 0 must be generated from the DB 7 0 signals externally Address line 11 is to be connected to pin BGA D5 QFP32 of the VPC3 S XDTACK mechanism is supported pa EN Signal Name In Out Description Connect to E3 9 SERMODE 0 Parallel Interface GND E4 28 MOT XINT 1 Motorola Format VCC D4 33 MODE 0 Asynchronous Interface Mode GND D5 32 AB11 I Address Lines Bit 11 CPU Address Bus 11 C2 2 AB10 B3 44 AB9 A1 48 AB8 S Bi 1 AB7 S C3 45 AB6 B2 46 ABS Address Lines Bits 10 0 He ress Bus 10 0 B4 41 AB4 A5 38 AB3 A6 37 AB2 B5 39 AB1 Be 36 ABO G4 20 DB7 IO H5 23 DB6 IO H6 24 DB5 IO G5 22 DB4 IO Data Bus 7 0 CPU Data Bus 7 0 G6 25 DB3 IO F4 21 DB2 IO F6 27 DB1 IO F5 26 DBO IO C1 3 XCS Chip Select Signal active low CPU Chip Select C5 35 AS Address Strobe active low CPU Address Strobe C6 34 RW Read Write Signal 1 Read CPU Read Write Figure 3 6 Interface Configuration Asynchronous Motorola Mode VPC3 S User Manual Revision 1 06 15 Copyright profichip GmbH 2012 3 Pin Description 3 2 4 Synchronous Motorola Mode In Synchronous M
95. new diagnosis data are present at the DP Slave The DP Master then fetches the new diagnosis data with a Slave Diag telegram Then the Diag Flag is cleared again However if the user signals Diag Stat Diag 1 that is static diagnosis see the structure of the Diagnosis Buffer the Diag Flag still remains activated after the relevant DP Master has fetched the diagnosis The user can poll the Diag Flag in the Status Register to find out whether the DP Master has already fetched the diagnosis data before the old data is exchanged for the new data According to IEC 61158 Static Diagnosis should only be used during start up Status coding for the diagnosis buffers is stored in the Diag Buffer SM control parameter The user can read this cell with the possible codings for both buffers User VPC3 or VPC3 Send Mode Bit Position Address Designation 7 6 5 4 3 2 1 0 OCH 0 0 0 0 Diag Buf2 Diag_Buf1 Diag Buffer SM Diag Buffer SM Address OCH bit 7 4 Don t care Read as 0 bit 3 2 Diag Buf2 Assignment of Diagnosis Buffer 2 00 Nil 01 User 10 VPC3 11 VPC3_Send_Mode bit 1 0 Diag Buf1 Assignment of Diagnosis Buffer 1 00 Nil 01 User 10 VPC3 11 VPC3 Send Mode Figure 6 9 Diagnosis Buffer Assignment The New Diag Cmd is also a read access to a defined control parameter indicating which Diagnosis Buffer belongs to the user after the
96. ng data of a Set Ext Prm telegram The user negatively acknowledges OFH User_Prm_Data_Not_Okay 1 0 the user parameter setting data of a Set_ Ext_ Prm telegram The user positively acknowledges 10H User_Cfg_Data_Okay 1 0 the configuration data of a Chk Cfg telegram The user negatively acknowledges 11H User_Cfg_Data_Not_Okay 1 0 the configuration data of a Chk Cfg telegram Buffer assignment of the ten DXBout BUE SM 79 DXBout Buffer State Machine The user fetches the last 13H Next DXBout Buffer Cmd 2 0 DXBout Buf from the N state The user has fetched the data from 14H SSA_Buffer_Free_Cmd the SSA_Buf and enables the buffer again 15H Mode Reg 1 7 0 Figure 4 2 Assignment of the Internal Parameter Latches for READ VPC3 S User Manual Revision 1 06 21 Copyright O profichip GmbH 2012 4 Memory Organization 22 Address Intel Mot Name Bit No Significance Write Access 00H 01H Int Req Reg 7 0 01H 00H Int Req_Reg 15 8 02H 03H Int Ack Reg 7 0 Interrupt Controller Register 03H 02H Int Ack Reg 15 8 04H 05H Int Mask Reg 7 0 05H 04H Int Mask Reg 15 8 06H 07H Mode RegO 7 0 Setting parameters for individual bits 07H 06H Mode RegO 15 8 08H Mode Reg1 S 7 0 09H Mode Reg1 R 7 0 Square root value for OAH WD_BAUD_CONTROL_Val 7 0 baud rate monitoring OBH minTspa Val 7 0
97. ns 57 XDTACK holdtime after AS T 3 15 ns 58 Data setuptime to AS f 10 ns 59 AS pulsewidth write access 83 ns 60 Data holdtime after AS T 0 ns Figure 10 19 Timing Asynchronous Motorola Mode 122 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Operational Specifications 10 10 6 6 Timing in SPI Interface Mode XSS SCK CPOL 0 SCK CPOL 1 HIGH IMP HIGH IMPEDANCE MISO vs LLL ON KYLIE XL Figure 10 20 Timing Diagram SPI Interface Mode CPHA 0 XSS SCK CPOL 0 SCK CPOL 1 MISO HIGH IMP VALID OUT ts l tus vos DUDEN KK LZ Figure 10 21 Timing Diagram SPI Interface Mode CPHA 1 VPC3 S User Manual Revision 1 06 123 Copyright O profichip GmbH 2012 10 Operational Specifications Symbol Parameter MIN MAX Unit f sck Clock Frequency SCK 6 MHz tiowsck Clock Pulse Width Low 83 ns tH ch sck Clock Pulse Width High 83 ns ts xss XSS Setup Time 83 ns t v so Clock to Data Out Valid 76 ns t uso Data Out Hold Time 21 ns tssi Data In Set up Time 10 ns t usi Data In Hold Time 10 ns to sso Output Disable Time 83 ns tHenxss XSS Inactive High Time 83 ns Figure 10 22 Timing SPI Interface Mode 124 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Operational Specifications 10 10 6 7 Timing in I2C Interface Mode
98. nt to the address location following the one that was just read S T A Control Byte Address High Byte Address Low Byte R Control Byte Data Byte 1 I l Tl ot S T A R TI v vo u AO AND o AO ANP Oz Figure 8 18 I2C Random READ Operation Sequential READ Operation Sequential reads are initiated in the same way as a random read except that once the VPC3 S transmits the first data byte the master issues an acknowledge as opposed to the Stop condition used in a random read This acknowledge directs the VPC3 S to transmit the next sequentially addressed data byte Figure 8 19 Following the final byte transmitted to the master the master will NOT generate an acknowledge but will generate a STOP condition To provide sequential reads the VPC3 S contains an internal Address Pointer which is incremented by 1 upon completion of each operation This Address Pointer allows the entire memory contents to be serially read during one operation The internal VPC3 S User Manual Revision 1 06 101 Copyright profichip GmbH 2012 8 Hardware Interface Address Pointer will automatically roll over from address OxFFF Ox7FF in 2 kB mode to address 0x000 if the master acknowledges the byte received from address OxFFF Ox7FF S T S R Control Byte x Data Byte n E Data Byte n 1 Data Byte n x o s Felisite Fresh nje sjers ahe or o c C c 0 K K K A C K Figure 8 19 I2C Sequential REA
99. ock formats to be used by the SPI system The CPOL bit simply selects a non inverted or inverted clock The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges SPI CPHA 0 or on even numbered SCK edges SPI CPHA 1 The main element of the SPI system is the SPI Data Register The 8 bit data register in the master and the 8 bit data register in the slave are linked by the MOSI and MISO pins to form a distributed 16 bit register When a data transfer operation is performed this 16 bit register is serially shifted eight bit positions by the SCK clock from the master so data is exchanged between the master and the slave MASTER SPI CPU SLAVE SPI VPC3 S uma et pm SHIFT REGISTER Me BAUDRATE GENERATOR Figure 8 3 SPI Master Slave Transfer Block Diagram VPC3 S User Manual Revision 1 06 91 Copyright profichip GmbH 2012 8 Hardware Interface Data written to the master SPI Data Register becomes the output data for the slave and data read from the master SPI Data Register after a transfer operation is the input data from the slave Transmission Formats During an SPI transmission data is transmitted shifted out serially and re ceived shifted in serially simultaneously The serial clock SCK synchro nizes shifting and sampling of the information on the two serial data lines The slave select line allows selection of an individual slave SPI dev
100. oding O GE CSS x one Ex 1Z D amp O x E xe 33 258 23 S amp lt 2 a za au 5o so malo oao zo Bit Position Address 15 14 13 12 11 10 9 8 Designation 01H g Int Req Reg Intel m lt o 15 8 ou e 5g E 2 Ja los m gt ma ac O P og E I O a Sizs zs zs se See below O x SE OB amp OB for coding LL a oa aozalzai zai zo VPC3 S User Manual Revision 1 06 35 Copyright profichip GmbH 2012 5 ASIC Interface 36 Interrupt Request Register Low Byte Address 00H Intel bit 7 DXB_Out rw 0 VPC3 S has received a DXB telegram and made the new output data available in the N buffer bit 6 New_Ext_Prm_Data rw 0 The VPC3 S has received a Set Ext Prm telegram and made the data available in the Parameter Buffer bit 5 DXB Link Error rw 0 The Watchdog cycle is elapsed and at least one Publisher Subscriber connection breaks down bit 4 User_Timer_Clock rw 0 The time base for the User Timer Clocks is run out 1 10ms bit 3 WD DP CONTROL Timeout rw 0 The watchdog timer expired in the DP CONTROL state bit 2 Baud Rate Detect rw 0 The VPC3 S has left the BAUD SEARCH state and found a baud rate bit 1 Go Leave DATA EXCH rw 0 The DP_SM has entered or exited the DATA EXCH state bit O MAC_Reset used if CS_Supported 0 rw 0 After processing the current request the VPC3 D has entered the Offline state by setting the Go Of
101. oltage Vo 0 3 to VCC 0 3 V DC output current lo See Figure 10 4 mA Storage temperature Tstore 40 to 150 C Figure 10 1 Absolute Maximum Ratings 10 2 Recommended Operating Conditions Parameter Symbol MIN MAX Unit DC supply voltage VCC 3 00 3 6 V Static supply current Le 100 uA Circuit ground GND 0 V Input voltage Vi 5 50 V Input voltage HIGH level Vin 2 00 5 50 V Input voltage LOW level Vit 0 8 V Output voltage Vo 0 VCC V Ambient temperature TA 40 485 C Static Ipp current is exclusively of input output drive requirements and is measured with the clock stopped and all inputs tied to VCC or GND Figure 10 2 Recommended Operating Conditions 10 3 General DC Characteristics Parameter Symbol MIN TYP MAX Unit Input LOW current lit 1 1 uA Input HIGH current lH 1 1 uA Tri state leakage current loz 10 10 HA Current consumption 3 3V lA 30 mA Input capacitance Cin 5 pF Output capacitance Cour 5 pF Bi directional buffer capacitance Ci pF Thermal Resist BGA48 Oya 43 6 K W Thermal Resist QFP48 Osa 72 2 K W Figure 10 3 General DC Characteristics VPC3 S User Manual Revision 1 06 111 10 Operational Specifications 10 4 Ratings for the Output Drivers Signal Direction dm Driver Strength ie De DB 0 7 1 0 Tristate 8mA 50pF RTS O Push Pull 8mA 50pF TXD O Tristate 8mA 50pF INT O Push Pull 8mA 50pF XREADY XDTACK O Push Pull SPI_MISO O Push Pull 8mA 50pF l2C SDA 1 0 Tristate
102. ontinues for a total of 16 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges Data reception is double buffered data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI Data Register after the last bit is shifted in Principles of Operation The VPC3 S contains an 8 bit instruction register and a 16 bit address register The device is accessed via the MOSI pin with data being clocked in on the configured edge of SCK The XSS pin must be held low for the entire operation The first byte received during a valid SPI transfer is interpreted as SPI instruction Figure 8 6 lists the supported instruction bytes and formats for the device operation All instructions addresses and data are transferred MSB first LSB last Instruction Instruction Name Format Description READ BYTE 0001 001 1 Read a single data byte from selected address READ ARRAY 0000 0011 Read several data bytes beginning at selected address with auto increment WRITE BYTE 0001 0010 Write a single data byte to selected address Write several data bytes beginning at selected address with auto increment WRITE ARRAY 0000 0010 Figure 8 6 SPI Instruction Set Note In SPI interface mode all internal addresses are interpreted in Intel format Motorola format byte swapping for certain addresses is not supported in SPI
103. or DP in order to increase the permissible distortion of the stop bit 8 4 ASIC Test 108 All output pins and I O pins can be switched to the high resistance state via the XTESTO test pin An additional XTEST1 input is provided to test the chip on automatic test devices not in the target hardware environment Pin Name Value Function GND All outputs high resistance D2 XTESTO VCC Normal VPC3 function GND Various test modes E5 XTEST1 VCC Normal VPC3 function Figure 8 28 Test Ports Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 PROFIBUS Interface 9 9 1 Pin Assignment The data transmission is performed in RS485 operating mode i e physical RS485 The VPC3 S is connected via the following signals to the galvanically isolated interface drivers Signal Name Input Output Function RTS Output Request to send TXD Output Sending data tristate output pull up resistor required RXD Input Receiving data Figure 9 1 PROFIBUS Signals The PROFIBUS interface is a 9 way sub D plug connector with the following pin assignment Pin 1 Free Pin 2 Free Pin 3 B line Pin 4 Request to send RTS Pin 5 Ground 5V M 5 Pin 6 Potential 5V floating P5 Pin 7 Free Pin 8 A line Pin 9 Free The cable shield must be connected to the plug connector housing The free pins are described as optional in IEC 61158 2 CAUTION T
104. otorola Mode the data and address busses are separate non multiplexed When using HC11 types with a multiplexed bus the address signals AB 7 0 must be generated from the DB 7 0 signals externally Address line 11 is to be connected to pin BGA C5 QFP 35 of the VPC3 S XDTACK mechanism is not supported Pin BGA QFP Signal Name In Out Description Connect to E3 9 SERMODE 0 Parallel Interface GND E4 28 MOT XINT 1 Motorola Format VCC D4 33 MODE 1 Synchronous Interface Mode VCC C5 35 AB11 Address Lines Bit 11 CPU Address Bus 11 C2 2 AB10 B3 44 AB9 A1 48 AB8 S Bi 1 AB7 S C3 45 AB6 B2 46 ABS Address Lines Bits 10 0 Fi ress Bus 10 0 B4 41 AB4 A5 38 AB3 A6 37 AB2 B5 39 AB1 Be 36 ABO G4 20 DB7 IO H5 23 DB6 IO H6 24 DB5 IO G5 22 DB4 IO Data Bus 7 0 CPU Data Bus 7 0 G6 25 DB3 IO F4 21 DB2 IO F6 27 DB1 IO F5 26 DBO IO C1 3 XCS Chip Select Signal active low CPU Chip Select D5 32 E CLOCK E Clock CPU E Clock C6 34 RW I Read Write Signal 1 Read CPU Read Write Figure 3 7 Interface Configuration Synchronous Motorola Mode 16 Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 Pin Description 3 3 2 5 SPI Mode The VPC3 S can be
105. pr 4 Ident_Number_High 5 Ident_Number_Low 6 Group Ident io oo D a c 7 S 2 2 5 2 0 0 a 2 5 3 5 Spec User Prm Byte Q c ot l Ez 1 DPV1 Status 1 ow 8 zu QO 2o6 26 L ja 50 50 8 DPV1 Status 2 9 DPV1 Status 3 10 User Prm Data 243 Figure 6 5 Format of the Set Prm Telegram 46 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 PROFIBUS DP Extensions 6 Spec User Prm Byte DPV1 Status 1 bit 7 DPV1 Enable 0 DP V1 extensions disabled default 1 DP V1 extensions enabled bit 6 Fail Safe 0 Fail Safe mode disabled default 1 Fail Safe mode enabled bit 5 Publisher Enable 0 Publisher function disabled default 1 Publisher function enabled bit 4 3 Reserved To be parameterized with 0 bit 2 WD_Base Watchdog Time Base 0 Watchdog time base is 10 ms default 1 Watchdog time base is 1 ms bit 1 Dis_Stop_Control Disable Stop bit Control 0 Stop bit monitoring in the receiver is enabled default 1 Stop bit monitoring in the receiver is disabled bit 0 Dis_Start_Control Disable Start bit Control 0 Start bit monitoring in the receiver is enabled default 1 Start bit monitoring in the receiver is disabled Figure 6 6 Spec User Prm Byte DPV1 Status 1 It is recommended not to use the DPV1 Status bytes bytes 7 9 for user parameter data VPC3 S User Manual Revision 1 06 47 Copyrig
106. r 3 must be set and the lsoM must be parameterized A Structured Prm Data block for IsoM in the parameter telegram contains the configuration values for the PLL 74 Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 PROFIBUS DP Extensions 7 The PLL can be used in Isochronous Mode only not in Simple Sync Mode The user has to take care that the value of SYNC PW Reg matches the SYNC cycle time which could be smaller than the DP cycle time now If E limit is reached a SYNC clock is generated too Direction Parameter Description OUT Global Control clock indicates arriving SYNCH telegram PLL start start and stop of PLL SYNC mode SYNC clock synchronized to Global Control clock SYNC enable enable SYNC clock after successful synchronization specific clock enable enable only clockO input or output clock SYNC cycle time Tsync period of SYNC clock cycle shall be an integer part of DP cycle time ratio of DP cycle to SYNC cycle n number of SYNC clock cycles per Top E limit number of acceptable synchronization errors input time Tpi 1 point in time for actual value acquisition output time Tei o point in time for setpoint transfer PLL window TpL1 w half the width of the tolerance window First Window start value of PLL window PLL delay time Teu p SYNC clock delay of the generated SYNC clock to compensate pha
107. r MSBs of the address being don t care bits in case of 2 kB RAM mode the five MSBs of the address are don t care After the correct READ ARRAY instruction and address are sent the data byte stored in the memory at the selected address is shifted out on the MISO pin After additional 8 SCK pulses the complete first data byte has been sent The data byte stored in the memory at the next address can be read sequentially by continuing to provide clock pulses The internal Ad dress Pointer is automatically incremented to the next higher address after each byte of data is shifted out When the highest address is reached Ox7FF in case of 2 kB RAM mode or OxFFF in 4 kB mode the address counter rolls over to address 0x000 allowing the read cycle to be continued indefinitely The read operation is terminated by raising the XSS pin Figure 8 8 Note The SPI instruction READ ARRAY may not be used when reading from the Control Parameter memory address 0x000 to address 0x015 Otherwise due to the auto increment mechanism of the READ ARRAY instruction an unintended read operation to the subsequent memory loca tion will occur leading to an unpredictable behavior of the VPC3 S VPC3 S User Manual Revision 1 06 95 Copyright O profichip GmbH 2012 8 Hardware Interface XSS 22 23 24 25 26 27 28 29 30 31 SCK CPOL 0 16 bit Address MOSI High Impedance MISO XSS 32 33 34 35 36 37 38 39 40 41 42 43 4 45
108. r Prm Finished 0 1 Prm Conflict 1 1 Not Allowed Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 PROFIBUS DP Extensions 6 Bit Position Address Designation 7 6 5 4 3 2 1 0 User_Prm OFH 0 0 0 0 0 0 U U EE Data Not Okay 0 0 User Prm Finished 0 1 Prm Conflict 1 1 Not Allowed Figure 6 7 Coding of User Prm Not Okay Cmd If another Set Prm telegram is supposed to be received in the meantime the signal Prm Conflict is returned for the positive or negative acknowledgement of the first Set Prm telegram Then the user must repeat the validation because the VPC3 S has made a new Parameter Buffer available 6 2 3 Chk_Cfg SAP 62 The user checks the correctness of the configuration data After receiving an error free Chk Cfg telegram the VPC3 S exchanges the Aux Buffer 1 2 all data bytes are entered here for the Config Buffer stores the input data length in R Len Cfg Data and generates the New Cfg Data interrupt Then the user has to check the User Config Data and either respond with User Cfg Data Okay Cmd or with User Cfg Data Not Okay Cmd The pure data is entered in the buffer in the format of the standard The user response User Cfg Data Okay Cmd or the User Cfg Data Not Okay Cmd response clears the New Cfg Data interrupt The user cannot acknowledge the New Cfg Data in the IAR register If an incorrect configurat
109. r setting for CLKOUT 0 12 MHz D3 4 DIVIDER 4 24 MHz Configuration Pin 0 Asynchronous Mode Parallel Interface Mode 1 Synchronous Mode Parallel Interface Mode D4 33 MODE Configuration Pin 0 SPI Serial Interface Mode 1 I2C Serial Interface Mode VPC3 S User Manual Copyright O profichip GmbH 2012 Revision 1 06 11 3 Pin Description pall gin Signal Name In Out Description Source Destination D5 32 XWR E_CLOCK AB11 Write E Clock Motorola Address Bus 11 CPU D6 19 GND E1 31 GND E2 8 CLKOUT O Clock Output 12 MHZ or 24 MHz CPU System Es 9 SERMODE B c EM Configuration Pin E4 28 monat EU ICE Configuration Pin E5 29 XTEST1 Test Pin 1 to be connected to VCC Test Pin E6 30 VCC F1 10 CLK KS System Clock 48 MHz System F2 11 XDATAEXCH O Indicates state Data Exchange for PROFIBUS DP LED F3 16 XCTS Clear To Send for FSK Modem PB Interface F4 21 DB2 IO Data Bus 2 CPU F5 26 DBO IO Data Bus 0 CPU F6 27 DB1 IO Data Bus 1 CPU G1 12 RESET I S Master Reset connect to port pin of CPU CPU G2 15 RXD Receive Data PB Interface G3 17 INT O Interrupt CPU IRQ Controller G4 20 DB7 IO Data Bus 7 CPU G5 22 DB4
110. rate no SYNC signal coincides with the expected SYNCH telegram 1 generate SYNC signal coincides with the expected SYNCH telegram Enable Out Clock rw 0 Enable Out_Clock 0 generate no SYNC signal at To 1 generate SYNC signal at To Enable In Clock rw 0 Enable In Clock 0 generate no SYNC signal at Ti 1 generate SYNC signal at T Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 PROFIBUS DP Extensions 7 Number of SYNC Number of SYNC rw 0 Number of SYNC cycles per DP cycle Number of SYNC 1 TPLL 1 Input Time rw 0 Number of SYNC cycles from start of DP cycle up to Ti TPLL_O Output_Time rw 0 Number of SYNC cycles from start of DP cycle up to To E limit E limit rw 0 Number of acceptable synchronization errors during time interval Figure 7 23 Format of the PLL_Buffer T in the Structured_Prm_Data block is the period of time between actual value acquisition and the start of new DP cycle whereas Tp is the period of time from the start of DP cycle to the point of data acquisition start of setpoint actual value start of DP cycle transfer acquisition DP cycle To ToLo Tu i T Top Figure 7 24 configuration of Tp _o and Tpit If none of the Enable xx Clock bits is set the PLL generates a SYNC clock after every expiration of the slave application cycle Tsync VPC3 S Firmware configure D
111. refore if the previous read access was to address n n is any legal address the next current address read operation would access data from address n 1 Upon receipt of the control byte with R W bit set to 1 the VPC3 S issues an acknowledge and transmits the 8 bit data byte The master will not acknowledge the transfer but does generate a STOP condition and the VPC3 S discontinues transmission Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Hardware Interface 8 S T Control Byte Data Byte n O P o Oz Figure 8 17 I2C Current Address READ Operation Random READ Operation Random read operations allow the master to access any memory location in a random manner To perform this type of read operation the byte address must first be set This is accomplished by sending the byte address to the VPC3 S as part of a write operation R W bit set to 0 Once the byte address is sent the master generates a START condition following the acknowledge This terminates the write operation but not before the internal Address Pointer is set The master issues the control byte again but with the R W bit set to a 1 The VPC3 S will then issue an acknowledge and transmit the 8 bit data byte The master will not acknowledge the transfer but does generate a Stop condition which causes the VPC3 S to discontinue transmission Figure 8 17 After a random Read command the internal address counter will poi
112. ring time runs out the VPC3 S evaluates the Link Status of each Publisher and updates the bit Link Status The timer restarts again automatically Link Link Data Event Status Error Exist valid DXB data receipt 0 1 faulty DXB data receipt 0 1 0 WD Time elapsed AND Data Exist 1 1 0 0 WD Time elapsed AND Link Error 1 0 0 0 Figure 7 14 Link Status handling To enable the monitoring of Publisher Subscriber links the watchdog timer must be enabled in the Set Prm telegram The user must check this VPC3 S User Manual Revision 1 06 69 Copyright O profichip GmbH 2012 7 PROFIBUS DP Extensions 7 3 2 70 IsoM Isochronous Mode The IsoM synchronizes DP Master DP Slave and DP Cycle The isochro nous cycle time starts with the transmission of the SYNCH telegram by the IsoM master If the ISoM support of the VPC3 S is enabled a synchroniza tion signal at Pin C4 SYNO is generated by each reception of a SYNCH telegram The SYNCH telegram is a special coded Global Control request SYNCHI Cyclic Cyclic Acyclic Acyclic Spare SYNCH mesage Service Service Service Service Token Time mesage Cyclic pa Acyclic Part Part Cycle Time Typ Figure 7 15 Telegram sequences in IsoM with one DP Master Class 1 Two operation modes for cyclic synchronization are available in the VPC3 S 1
113. rized value R User WD Value and is decremented by the VPC3 S with each received Data Exchange telegram If the timer reaches the value 0000H the VPC3 S goes to the WAIT PRM state and the DP SM carries out a LEAVE MASTER The user must cyclically set this timer to its start value Therefore Res User WD 1 must be set in Mode Register 1 Upon receipt of the next Data Exchange telegram the VPC3 S again loads the User WD Timer to the parameterized value R User WD Value and sets Res User WD 0 Mode Register 1 During power up the user must also set Res User WD 1 so that the User WD Timer is set to its parameterized value 6 2 6 Global Control SAP 58 56 The VPC3 S processes the Global Control telegrams like already described The first byte of a valid Global Control is stored in the R GC Command RAM cel The second telegram byte Group Select is processed internally The interrupt behavior regarding to the reception of a Global Control telegram can be configured via bit 8 of Mode Register 2 The VPC3 S either generates the New GC Control interrupt after each receipt of a Global Control telegram default or just in case if the Global Control differs from the previous one The R GC Command RAM cell is not initialized by the VPC3 S Therefore the cell has to be preset with 00H during power up The user can read and evaluate this cell Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 PROFIBUS DP
114. rol Command in the R GC Command RAM cell Figure 5 10 Interrupt Request Register High Byte VPC3 S User Manual Revision 1 06 37 Copyright O profichip GmbH 2012 5 ASIC Interface 5 3 2 Interrupt Acknowledge Mask Register The other interrupt controller registers are assigned in the bit positions like the Interrupt Request Register Address Register Reset state Assignment 02H 03H Interrupt Readable only All bits Register IR cleared 04H 05H Interrupt Writeable can All bits set 1 Mask is set and the Mask be changed interrupt is disabled Register during operation 0 Mask is cleared and the IMR interrupt is enabled 02H 03H Interrupt Writeable can All bits 1 Interrupt is Acknowledge be changed cleared acknowledged and the IRR Register during operation bit is cleared IAR 0 IRR bit remains unchanged Figure 5 11 Interrupt Acknowledge Mask Register The New Ext Prm Data New Cfg Data interrupts cannot be acknowledged via the Interrupt Acknowledge Register The relevant state machines clear these interrupts through the user acknowledgements for example User Prm Data Okay etc 5 4 Watchdog Timer The VPC3 S is able to identify the baud rate automatically The state ma chine is in the BAUD SEARCH state after each RESET and also after the Watchdog WD Timer has expired in the BAUD CONTROL state BAUD SEARCH x
115. se shifts between slaves due to the runtimes of SYNCH telegram output clock of the PLL SYNCH error synchronization errors detected resynchronization necessary PLL synchronized PLL is synchronized with the DP Masters SYNCH hit display SYNCH telegram arrived within tolerance window SYNC clock coincides with the expected FRS display Global Control clock input clock display SYNC clock designated for actual value acquisition output clock display SYNC clock designated for setpoint transfer Figure 7 21 Inputs and outputs of the PLL VPC3 S User Manual Revision 1 06 Copyright O profichip GmbH 2012 75 7 PROFIBUS DP Extensions Bit Position Byte Designation 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 0 Structured Length 1 0 0 0 0 0 1 0 0 Structure Type 2 0 0 0 0 0 0 0 0 Slot Number 3 0 0 0 0 0 0 0 0 Reserved 4 0 0 0 0 0 0 0 1 Version 5 375 750 1500 3000 6000 12000 sd ime Base for Tpp 8 31 25 us 62 5 us 125 us 250 us 500 us 1000 us Time Base 1 12 us 1 01 Top DP Cycle Time 10 Note GSD Spezifikation Top max 32 ms Time Base Tee Tuapc 11 1 14 Master Application ii Cycle Time Time Base Top 12 375 750 1500 3000 6000 12000 Tease jo Time Base of Ti To 15 31 25 us 62 5 us 125 us 250 us 500 us 1000 us Time Base 1 12 us Ti 16 0 2 5 1 Instant
116. sent by Global Control telegram Bit Position Address Designation 7 6 5 4 3 2 1 0 OAH F U N D Dout_Buffer_SM Dout Buffer SM Address 0AH bit 7 6 F Assignment of the F Buffer 00 Nil 01 Dout Buf Ptr1 10 Dout Buf Ptr2 11 Dout Buf Ptr3 bit 5 4 U Assignment of the U Buffer 00 Nil 01 Dout Buf Ptr1 10 Dout Buf Ptr2 11 Dout Buf Ptr3 bit 3 2 N Assignment of the N Buffer 00 Nil 01 Dout Buf Ptr1 10 Dout Buf Ptr2 11 Dout Buf Ptr3 bit 1 0 D Assignment of the D Buffer 00 Nil 01 Dout Buf Ptr1 10 Dout Buf Ptr2 11 Dout Buf Ptr3 Figure 6 12 Dout Buffer Management VPC3 S User Manual Revision 1 06 53 Copyright O profichip GmbH 2012 6 PROFIBUS DP Extensions 54 When reading the Next Dout Buffer Cmd the user gets the information which buffer U buffer belongs to the user after the change or whether a change has taken place at all Bit Position Address Designation 7 6 5 4 3 2 1 0 OBH 0 0 0 0 Next_Dout_ Buf_Cmd TD 2 2 g o5 gt See coding 2 85 D 5 below D20 0m m Next Dout Buf Cmd Address OBH bit 7 4 Don t care Read as 0 bit 3 U Buffer Cleared User Buffer Cleared Flag 0 U buffer contains data 1 U buffer is cleared bit 2 State U Buffer State of the User Buffer 0 no new U buffer 1 new U buffer
117. t 5 SYNC Pol polarity of SYNC pulse for Isochronous Mode only w 0 0 negative polarity of SYNC pulse default 1 positive polarity of SYNC pulse bit 4 SYNC_Ena enables generation of SYNC pulse for Isochronous Mode only w 0 0 SYNC pulse generation is disabled default 1 SYNC pulse generation is enabled bit 3 DX Int Port Port mode for DX Out interrupt ignored if SYNC_Ena set w 0 0 DX_ Out interrupt is not assigned to port DATAEXCH default 1 DX Out Interrupt synchronized to SYNCH telegram is assigned to port DATAEXCH bit 2 DX Int Mode Mode of DX out interrupt w 0 0 DX Out interrupt is only generated if Len_Dout_Buf is unequal 0 default 1 DX_Out interrupt is generated after every Data_Exchange telegram bit 1 No_Check_GC_Reserved Disables checking of the reserved bits in w 0 Global_Control telegram 0 reserved bits of a Global_Control telegram are checked default 1 reserved bits of a Global Control telegram are not checked bit O GC_Int_Mode Controls generation of New_GC_Command interrupt w 1 0 New GC Command interrupt is only generated if a changed Global Control telegram is received 1 New GC Command interrupt is generated after every Global Control telegram default Figure 5 4 Coding of Mode Register 2 30 Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 ASIC Interface 5 5 1 4 Mode Register 3 Setting parameters for Mode Register 3
118. tarts the receive delay timer tap The time master then sends a second message called Clock Value which contains the actual time when the Time Event was sent plus the send delay time tsp By receiption of the second message the Clock Sync interrupt will be generated To achieve the most accuracy the receive delay timer is running until the user reads the Clock Sync Buffer The VPC3 S only synchronizes the received telegrams the system time management is done by the user The user has also to account for the time after the receive delay timer has been read till the update of the system time tpp process delay time The time for transmission delay tor CS Delay Time and the Clock_Sync_Interval are communicated to the VPC3 S by a Structured_Prm_Data block The CS_Delay_Time is used by the user to calculate the system time ts Clock Value Time Event tor tap tpp Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 PROFIBUS DP Extensions 7 Bit Position A 1 Byte Designation 7 6 5 4 3 2 1 0 0 Structured Length 1 0 0 0 0 1 0 0 0 Structure Type 0 0 0 0 0 0 0 0 Slot Number Reserved AJOJN o o o o o o o o Clock Sync Interval 5 Time Base 10 ms Seconds 2 0 CS Delay Time Fraction Part of Seconds 2 0 13 db can be omitted Base is 1 2 Seconds Figure 7 27 Format of Structured Prm Data with Time AR
119. ted bit 13 Spec_Clear Mode Special Clear Mode Fail Safe Mode rw 0 0 No special clear mode 1 Special clear mode VPC3 S will accept data telegrams with data unit 0 bit 12 Spec Prm Buf Mode Special Parameter Buffer Mode rw 0 0 No Special Parameter Buffer 1 Special Parameter Buffer mode Parameterization data will be stored directly in the Special Parameter Buffer bit 11 Set_Ext_Prm_Supported Set_Ext_Prm telegram support rw 0 0 SAP 53 is deactivated 1 SAP 53 is activated bit 10 User Time Base Timebase of the cyclical User Time Clock Interrupt rw 0 0 The User Time Clock Interrupt occurs every 1 ms 1 The User Time Clock Interrupt occurs every 10 ms bit 9 EOI Time Base End of Interrupt Timebase rw 0 0 The interrupt inactive time is at least 1 us long 1 The interrupt inactive time is at least 1 ms long bit 8 DP Mode DP Mode enable rw 0 0 DP_Mode is disabled 1 DP Mode is enabled VPC3 S sets up all DP SAPs default configuration Figure 5 2 Coding of Mode Register 0 High Byte 5 1 2 Mode Register 1 Some control bits must be changed during operation These control bits are combined in Mode Register 1 and can be set independently of each other Mode Reg 1 S or can be reset independently of each other Mode Reg 1 HR Separate addresses are used for setting and resetting A logical T must be written to the bit position to be set or reset For exa
120. terface the controller can evaluate the Ready signal VPC3 S User Manual Revision 1 06 107 Copyright O profichip GmbH 2012 8 Hardware Interface 8 3 UART The transmitter converts the parallel data structure into a serial data flow Signal Request to Send RTS is generated before the first character The XCTS input is available for connecting a modem After RTS active the transmitter must hold back the first telegram character until the modem acti vates XCTS XCTS is checked again after each character The receiver converts the serial data flow into the parallel data structure and scans the serial data flow with the four fold transmission speed Stop bit testing can be switched off for test purposes Dis Stop Control 1 in Mode Register 0 or Set Prm telegram for DP One requirement of the PROFIBUS protocol is that no rest states are permitted between the telegram characters The VPCS3 S transmitter ensures that this specification is maintained The synchronization of the receiver starts with the falling edge of the start bit The start bit is checked again in the middle of the bit time for low level The data bits the parity and the stop bit are also scanned in the middle of the bit time To compensate for the synchronization error a repeater gen erates a 25 distortion of the stop bit at a four fold scan rate In this case the VPC3 should be parameterized with Dis Start Control 1 in Mode Register 0 or Set Prm telegram f
121. time Tcr 4 ns Figure 10 6 Clock Timing Note The VPC3 S is equipped with 5V tolerant inputs Interrupt After acknowledging an interrupt with EOI the interrupt output of the VPC3 S is deactivated for at least 1 us or 1 ms depending on the bit EOI Time Base in Mode Register O Parameter MIN MAX Unit Interrupt inactive time EOI Timebase 0 1 1 us Interrupt inactive time EOI Timebase 1 1 1 ms Figure 10 7 End of Interrupt Timing Reset VPC3 S requires a minimum reset phase of 100 ns at power on VPC3 S User Manual Revision 1 06 113 Copyright O profichip GmbH 2012 10 Operational Specifications 10 6 2 Timing in the Synchronous Intel Mode In the synchronous Intel mode the VPC3 S latches the least significant addresses with the falling edge of ALE At the same time the VPC3 S expects the most significant address bits on the address bus An internal chipselect signal is generated from the most significant address bits The request for an access to the VPC3 S is generated from the falling edge of the read signal XRD and from the rising edge of the write signal XWR ALE AB10 0 DB7 0 address XRD ALE AB10 0 DB7 0 XWR Figure 10 9 Synchronous Intel Mode WRITE XRD 1 114 Revision 1 06 VPC3 S User Manual Copyright O profichip GmbH 2012 Operational Specifications 10
122. tion Connect to E3 9 SERMODE 0 Parallel Interface GND E4 28 MOT XINT 0 Intel Format GND D4 33 MODE I 1 Synchronous Interface Mode VCC C1 3 AB11 l Address Bit 11 CPU Address Bus 11 A6 37 AB2 Address Bit 10 CPU Address Bus 10 B5 39 AB1 Address Bit 9 CPU Address Bus 9 B6 36 ABO Address Bit 8 CPU Address Bus 8 G4 20 DB7 IO H5 23 DB6 IO H6 24 DB5 IO Data Bus 7 0 CPU Data Address GS 22 DB4 IO multiplexed with lower address bits 7 0 Bus 7 0 G6 25 DB3 IO ALE used to latch the lower address bits F4 21 DB2 IO F6 27 DB1 IO F5 26 DBO IO C2 2 AB10 B3 44 AB9 Use one inverted A1 48 AB8 S CPU Address Line for In Synchronous Intel Mode these inputs are used to generating the Bi 1 AB7 S generate the internal Chip Select signal VPC3 S Chip Select C3 45 AB6 signal Chip Select is active if all inputs are 0 B2 46 ABS Connect all other B4 41 AB4 inputs to GND A5 38 AB3 Address Latch Enable C5 35 ALE I The lower address bits 7 0 are latched with the falling CPU ALE edge of ALE D5 32 XWR Write Signal active low CPU Write C6 34 XRD Read Signal active low CPU Read Figure 3 5 Interface Configuration Synchronous Intel Mode 14 Revision 1 06 VPC3 S User Manual Copyright profichip GmbH 2012 Pin Description 3 3 2 3 Asynchronous Motorola Mode In Asynchronous Motorola Mode the data a
123. tus 2 Enable Update Alarm Manufacturer Status Alarm Enable Chk Cf Enable _ Diagnostic Alarm Process Alarm Enable Pull Plu Enable q 0 Alarm Mode DPV1 Status 3 o PrmCmd eo IsoM Re Prm_ Structure 10 User_Prm_Data 243 Figure 7 1 Set_Prm with DPV1_Status bytes If the extensions are used the bit Spec Clear Mode in Mode Register 0 serves as Fail_Safe_required Therefore it is used for a comparison with the bit Fail_Safe in parameter telegram Whether the DP Master supports the Fail_Safe mode or not is indicated by the telegram bit If the DP Slave requires Fail_Safe but the DP Master doesn t the Prm_Fault bit is set If the VPC3 S should be used for DXB IsoM or redundancy mode the parameterization data must be packed in a Structured_Prm_Data block to distinguish between the User_Prm_Data The bit Prm_Structure indicates this If redundancy should be supported the PrmCmd_Supported bit in Mode Register 0 must be set VPC3 S User Manual Revision 1 06 59 Copyright profichip GmbH 2012 7 PROFIBUS DP Extensions Bit Position Byte Designation y 7 6 5 4 3 2 1 0 B 0 Structured Length 1 Structure Typ 2 Slot Number 3 Reserved 4 User_Prm_Data 243 Figure 7 2 Format of the Structured_Prm_Data block Additional to the Set_Prm telegram SAP 61 a Set_Ext_Prm SAP 53 telegram c
124. ual Copyright O profichip GmbH 2012 Revision 1 06 131 profichip GmbH Einsteinstrasse 6 91074 Herzogenaurach profichip Phone 49 9132 744 200 m Fax 49 9132 744 2164 automation in silicon www profichip com
125. ync interrupt Hence to ensure no new data overwrites the buffer the user should read out the buffer before acknowledging the interrupt The base address of the Clock_Sync Buffer depends on the memory mode 2K Byte mode 7EOH 4K Byte mode FEOH Bit Position A Byte Designation 7 6 5 4 3 2 1 0 o 5 5 E 0 reserved S Status e 2 gt o O 12 ge se e zsu lss se gt oO oO o an 1 reserved is i Command xol La AlO S ic o 2 9 o 55 2 C CV reserved Clock Value Status1 TD 3 ANH SWT 9 CR reserved SYF Clock Value Status2 Seconds 2 1 0 since 1 1 1900 0 00 00 4 or since 7 2 2036 6 28 16 if value lt 9DFF4400H Clock_Value_ 11 Fraction Part of Seconds 2 1 0 Time_Event Base is 1 2 Seconds 12 2741 20 Receive_Delay_Time 15 Time Base 1 us Seconds 2 1 0 since 1 1 1900 0 00 00 16 or since 7 2 2036 6 28 16 if value lt 9DFF4400H Clock_Value_ 23 Fraction Part of Seconds 2 1 0 previous_TE Base is 1 2 Seconds 24 29 1 0 Clock_Sync_Interval 25 Time Base 10 ms nn 82 Revision 1 06 Copyright VPC3 S User Manual profichip GmbH 2012 PROFIBUS DP Extensions 7 Clock_Sync Buffer Copyright profichip GmbH 2012 Status Reserved bit 7 2 r 000000 Status Clock_Sync_Violation bit 1 Wrong telegram or

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