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MRU User Manual - Digalog Systems, Inc.

1. Visual BASIC Declaration Public Sub mrirgNum RetData As Integer ByVal Group As Integer Call mrirgNum RetData Group Where RetData Return value containing the first interrupt number Group 0 to 15 The UUT s group number EXAMPLES Const UUT_GROUP 0 Const WORDWISE 2 Const ENABLE IRQ 1 Dim Interrupt As Integer Initialize the UUT s stack address and then enable the interrupts Call mrLoadStackPtr UUT_GROUP amp HFF80 Call mrIrqEnable UUT_GROUP ENABLE_IRQ Do some other things Check what interrupt was received Call mrirqNum Interrupt UUT_GROUP MsgBox First interrupt was amp CStr Interrupt Series 2040 Test System Page 59 MRU User Manual V1 5 mr J um p Executes a jump to a product routine that was previously loaded with the mrLoad call The product routine must be loaded at the address Address The product routine must jump back to the monitor at a specific address supplied by the writer of the monitor The argument Timeout is the time that the function waits in milliseconds for the product routine to jump back to the emulation monitor after executing its code If Timeout is zero the function returns immediately and leaves the product routine in control of the UUT The only way to regain control in this case is to reboot the UUT using the mrBoot command or load and execute a boot RAM product routine Visual BASIC Declaration Public Sub mrJump R
2. Parameter Names section O High Low and then enter the desired Initialization Fi Byte Order nitialization File 68020 INZ value in the text box below If Data Bits no items appear in the Parameter Names section the monitor does not have any special considerations associated with it Active ROM Chip Select Level OHigh Low The polarity and duration of BOOT ADDRESS Hexidecimal the reset signal that the MRU board drives the product with Processo 1 can be set usi ng the Product Handles configuration items not in the editor Reset controls If the duration Series 2040 Test System Page 21 MRU User Manual V1 5 is not known the Learn Valid Reset option can be executed This utility will determine the minimum reset duration needed from 500 up to 500 mS Next the active level of the UUT s ROM chip select level can be selected in the Active ROM Chip Select Level section There are two available options active high and active low It should be set to the same level as UUT processor s ROM chip select level This needs to be initialized so the LFA can be properly set up to correctly pass read and write data from the UUT to the MRU board The Byte Order section shows which MRU board number is assigned to which UUT boot ROM data byte It is used for informational purposes only This information can not be changed by the user Due to software limitations the least significant data by
3. SW2 Logic Family 0 Undefined 1 3 Volt 2 5 Volt 3 Undefined 4 Undefined JP1 Install if the UUT needs the reset line to be pulled down while inactive and it is not done by the UUT JP2 Install if the UUT needs the reset line to be pulled up while inactive and it is not done by the UUT JP3 JP4 JP5 Unused Do NOT install JP6 Install if the UUT uses a 32 pin DIP socket adaptor On DIP style LFAs only P1 Logic Family Adaptor Connector Series 2040 Test System Page 99 MRU User Manual V1 5 P2 Logic Family Adaptor Connector Continued SIGNAL SIGNAL CZ N CE Brae fe enel rans Je eat E fena CO EN o fens le a as EE Sense nme In P3 Power Connector 1 VCC From UUT Digital 5V Power Supply 2 GND From the UUT Digital 5V Return MRU Interface Ground 3 GND From the UUT Digital 5V Return MRU Interface Ground 4 VCC From the UUT Digital 5V Return MRU Interface Ground Page 100 Series 2040 Test System UUT Interface Wirewrap Field Wirewrap version P4 P A PI AI UDO cl GND A2 upi c2 cND A3 uD2 C3 GND A4 UD3 CA GND AS UD4 C5 GND Ap UDS Cp GND A7 UD6 C7 GND A8 UD7 CH GND A9 UAO CO GND A10 UAI C10 GND All UA2 cu GND Al2 UA3 C12 GND A13 UA4 C13 GND Al4 UAS C14 GND A15 UA6 C15 GND A16 UAT c16 GND A17 UA8 C17 GND A18 UA9 C18 GND A19 UAI0 C19 GND A20 UAII C20 GND A21 UAI2 C21 GND A22 UA13 C
4. golden log file which contains the signal behavior of a properly working product can be any log file just like the sample log file and will overlay the sample log file when loaded Any discrepancies between the two log files will then appear in red and be easily noticed The Help menu option provides access to the help file via its Contents and Search for Help on submenu items The Timebase field contains the timebase used for logging this data and is extracted from the log file Various timebases accommodated by the MRU board are asynchronous clocks periods of 20 40 80 100 200 and 400 nano seconds product bus cycles and an external signal The Timebase field will contain the clock period value the phrase Bus Cycle or the word Unknown respectively The Signal field contains the name of the signal whose waveform the mouse pointer is currently positioned over Depending on the timebase selected the Time field contains the time division index the bus cycle index or the log sample index of the mouse pointer s current position The Sample data and Sample address fields contain the hexadecimal values of the data and address signals respectively in the sample file whose timebase index the mouse pointer is currently positioned over The Golden data and Golden address fields contain the hexadecimal values of the data and address
5. PIN aach ler Jaen Je sms Page 108 Series 2040 Test System MRU User Manual V1 5 Series 2040 Test System Page 109 MRU User Manual V1 5 DIGALOG MRU ERROR CODES 105 001 MRU Monitor does not support this command 105 002 MRU Invalid cycle size for this monitor 105 003 MRU RAMTEST VERIFY Failed the UUT RAM test 105 004 MRU UUT exception error 105 005 MRU Product Routine Area not available 105 006 MRU Too many locations to be copied 105 007 MRU Too mant bytes to download 105 037 MRU Out of MRU RAM 105 038 MRU Interrupts have not been enabled 105 041 MRU The UUT had an interrupt 105 042 MRU Invalid Logic Analyzer Mode 105 044 MRU Invalid Logic Analyzer address 105 046 MRU MRU Firmware exception 105 048 MRU Stack pointer has not been initialized 105 049 MRU Stack already loaded 105 070 MRU Unknown command requested by host PC 105 128 MRU Invalid Trigger Matrix Channel Channel exceeded the MAX_CHAN number 105 129 MRU Invalid Testhead slot Slot number exceeds the MAX_Slot number 105 130 MRU Invalid Trigger Matrix signal Signal exceeded MAX_SIG 105 132 MRU Invalid Trigger Matrix slot Slot without trigger matrix hardware 105 133 MRU Error opening configuration file 105 193 MRU Firmware did not set FDRDY Error is in GetByte 105 195 MRU Firmware has not cleared HDRDY by reading the previous data Error is in r_putByte Error reading
6. ByVal DataNibble As Integer Call mrSend Group DataNibble Where Group 0 to 15 The UUT s group number DataNibble amp HO to amp H07 Data to be written EXAMPLES Const UUT_GROUP 0 Set bit 1 in the UUT status register Call mrSend UUT_GROUP amp H02 Page 78 Series 2040 Test System MRU User Manual V1 5 mrSetCode Sets the function code lines of the UUT for all subsequent emulation reads and writes ReadCode is the function code that the UUT processor uses when reading data WriteCode is the function code used when writing data This command is only available for processors that support function codes such as the Motorola 680xx series Visual BASIC Declaration Public Sub mrSetCode ByVal Group As Integer ByVal ReadCode As Long ByVal WriteCode As Long Call meSetCode Group ReadCode WriteCode Where Group 0 to 15 The UUT s group number ReadCode Any valid UUT function code setting WriteCode Any valid UUT function code setting EXAMPLES Definitions Const UUT_GROUP 0 Const BYTEWISE 1 68K function codes Const USER DATA amp H1 0001 Const SUPERVISOR_DATA amp H5 0101 Dim Address As Long location of the byte to modify Dim DataByte As Long holder for the byte data Address amp H5D040100 amp Modify a byte in the Supervisor Data Space Call mrSetCode UUT_GROUP SUPERVISOR_DATA SUPERVISOR_DATA Call mrRead DataByte UUT_GROUP BYTEWISE Addr
7. Therefore the monitor would read two bytes at address 0x3B00 to get the REGISTER VECTOR and two bytes at address 0x3B02 to get the RAM VECTOR The monitor must be able to interpret the data generated by the Special Considerations section of the configuration editor An example of a special consideration would be a processor that has a watchdog timer that cannot be disabled by the initialization code because the timer s address resides in a relocatable register In this case the monitor must handle the resetting of the watchdog before it times out Therefore the monitor code must be informed Page 36 Series 2040 Test System MRU User Manual V1 5 by the user as to where the register is located so that it can disable the watch dog timer on boot up This can be accomplished by placing the address of the relocatable register in the boot RAM space for the monitor to fetch at the proper time The address of the relocatable register is automatically placed in the boot RAM space by the mrBoot functional call However the value of the relocatable register must be specified by the user from within the Monitor Specific Considerations editor which is part of the MRU Configuration Editor When the configuration is saved the value of the relocatable register is saved to this project s mru ini file Which is then read by the mrConfig functional call and then available to the mrBoot functional call NOTE To p
8. e g 3 Volts 5 Volts and the upper four bits representing the type of LFA to UUT connection e g wirewrap DIP To see what each of the four bits represent see the Logic Family Adapter Card section NOTE The LFA must be powered up before executing this call After executing this call the UUT will have to be re booted to get control of the monitor again Visual BASIC Declaration Public Sub mrReadLFAid IdVal As Integer ByVal GroupAndBdNum As Integer all mrReadLFAid IdVal GroupAndBdNum Where IdVal The returned LFA ID GroupAndBdNum 0x00 to OxFF This parameter represents the group number and board number of the MRU board connected to the LFA card to be identified The lowest nibble is the board number within the group and the second nibble is the group number Thus 0x12 would be board 2 of group 1 EXAMPLES Const LFA Board 0 The UUT s group number Dim IdVal As Integer Read the ID of the LFA associated with the MRU board LFA BOARD Call mrReadLFAid IdVal LFA_Board Series 2040 Test System Page 73 MRU User Manual V1 5 mrReadLogicData Reads the existing samples from the logic analyzer and stores them in the file FileName The samples are retrieved starting at logic analyzer memory address 0x0000 and continues sequentially until one of three events occur First it returns the number of samples given by the parameter MaxReturnSamples if the number of samples actually store
9. 1 2 or 4 The size in bytes of the read write cycle to use Address Valid UUT I O address to read from EXAMPLES Const UUT_GROUP 0 Const BYTEWISE 1 Dim DataByte As Long Fetch what is at I O address OxOa Call mrIn DataByte UUT_GROUP BYTEWISE amp HA amp MsgBox I O address OxOa contains amp CStr DataByte Series 2040 Test System Page 57 MRU User Manual V1 5 mrirgEnable Enables or disables the UUT s maskable interrupt Before enabling the interrupts the UUT s stack pointer must have been initialized by using the mrLoadStackPtr call The mrlrqNum call is used to retrieve the first interrupt number from the UUT Visual BASIC Declaration Public Sub mrirqEnable ByVal Group As Integer ByVal Enable As Integer Call mrIrqEnable Group Enable Where Group 0 to 15 The UUT s group number Enable 0 Disable interrupts 1 Enable interrupts EXAMPLES Const UUT_GROUP 0 Const ENABLE_INTERRUPT 1 Enable the UUT to save the interrupt number so it can then be returned Call mrIrgEnable UUT_GROUP ENABLE INTERRUPT Page 58 Series 2040 Test System MRU User Manual V1 5 mrirqNum Returns the number of the first UUT interrupt since interrupts were enabled using the call mrlrqEnable The stack pointer for the UUT must have been initialized by using the mrLoadStackPtr call Since mrLoadStackPtr needs UUT RAM the UUT must have its own RAM to store an interrupt number
10. 2040 Test System Page 97 MRU User Manual V1 5 LOGIC FAMILY ADAPTER CARD WIREWRAP VERSION SHOWN Ed paca lt SI Stu P1 P2 Si Sin u a S R4 S gt Description The Logic Family Adapter Card LFA pod is used to connect to the ROM address space of the unit under test UUT The LFA card has to match the logic family type e g 3 Volt 5 Volt of the UUT Therefore there will be a different LFA card for each family type In addition each LFA type can have one of several different methods of connecting to the UUT There currently are two methods of connecting to the UUT wirewrap and DIP socket adaptor The LFA card has a serial communication link to the MC68331 microcontroller on the MRU board This serial link is used to test the integrity of the data address and control line connections between the MRU board and the LFA board Switches and Jumpers SW1 UUT Connection Method Undefined Wirewrap 28 pin DIP socket adaptor 32 pin DIP socket adaptor WN CH Page 98 Series 2040 Test System MRU User Manual V1 5
11. Flag As Integer Call mrTMTrigEn PrevState Group Flag Where PrevState 0 Previous state disabled 1 Previous state enabled Group 0 to 15 The UUT s group number Flag 0 Disable the FuncTrig signal 1 Enable the FuncTrig signal EXAMPLES Const UUT GROUP 0 Dim PrevState As Integer Disable function trigger output from the UUT Call mrTMTrigEn PrevState UUT_GROUP 0 Series 2040 Test System Page 81 MRU User Manual V1 5 mrWaitTrig Waits Timeout milliseconds for a low pulse from a preselected trigger matrix line to be detected on either the InO or In1 signal line The pulse is latched when it is detected and remains latched until it is reset If Timeout is reached and if the latched signal has not been detected by the end of the waiting period a timeout error is returned When the latched signal line is detected no error is returned The fact that it is latched means that the MRU cannot distinguish between a pulse which occurred after this command was given or before the command was given Therefore to detect a pulse that occurred after this command the latch must first be reset by calling this function with a Timeout of zero This will not cause a timeout error Visual BASIC Declaration Public Sub mrWaitTrig ByVal Group As Integer ByVal Signal As Integer ByVal Timeout As Long Call mrWaitTrig Group Signal Timeout Where Group 0 to 15 The UUT s group number Signal 0 I
12. Manual V1 5 Data Cables P1 MRU Interface Cable 1 Interface Board to LFA Card PIN SIGNAL PIN SIGNAL CERN 10 PD4 11 12 Pps 15 16 PD7 17 18 _ PAo 19 20 _ PA1 21 22 _ PA2 23 24 PA3 25 26 pad 27 28 PAS 29 30 PA6 31 32 PAT 33 34 pA8 Page 104 Series 2040 Test System MRU User Manual V1 5 P2 MRU Interface Cable 2 Interface Board to LFA Card PIN SIGNAL PIN SIGNAL ROMVCC Sense n LA O gt 5 7 ND ES En En 7 En 3 Series 2040 Test System Page 105 MRU User Manual V1 5 P4 UUT Interface SS Field PIN SIGNAL Al GND A2 GND A3 GND A4 GND A7 GND gt 8 GND A9 UAO GND A10 UAL C10 GND GND UA3 GND A13 UA4 GND Al4 UAS GND ais UAG GND UA7 ND UAS UA9 A UA10 N c20 All A12 A16 A17 A18 a 00 819 8 9 J A19 A20 Q Uo H EEE 5 S EIEIEIEIEIEIE O19 lt Q Z J A23 Q Z J 6 24 Q Z J A25 Q Z J A26 SET Q Z g 3 27 TS Q Z J A28 OGWTS A29 OGSTRT A30 OGSTOP A31 UBUSQUAL A32 N EEN Q Z J orere ZIZIZ DIO Q g Q Z Page 106 Series 2040 Test System MRU User Manual V1 5 28 32 Pin DIP Connectors PIN SIGNAL PIN SIGNAL s forso fe noros beer pasar fo fox Kl jo Install JP 6 at Pin 9 for a 32 Pin Socket Series 2040 Test System Page 107 MRU User Manual V1 5 Wirewrap Field SIGNAL PIN SIGNAL
13. NLocations Where Group 0 to 15 The UUT s group number DataSize 1 2 or 4 The size in bytes of the write cycle to use Dest Any valid UUT RAM address FillData amp HO to amp HFFFFFFFF Depends on the DataSize parameter NLocations Number of valid UUT RAM locations for the given data bus width EXAMPLES Const UUT_GROUP 0 Const BYTEWISE 1 Const WORDWISE 2 Fill the bottom 1K Bytes of UUT RAM with zeros Call mrFilllUUT_GROUP BYTEWISE amp H000 amp H0 1024 amp Fill a 4K Byte section of word mode only memory with a test pattern Call mrFill UUT_GROUPWORDWISE amp HE8000000 amp H5A5A 2 1024 amp Page 56 Series 2040 Test System MRU User Manual V1 5 mrin Reads data from UUT I O space at the address Source The parameter DataSize specifies the size of the read cycle to use This command is only available for processors that have an I O space If the FuncTrig trigger signal has been is enabled by using the mrTMTrigEn call then this command will produce a low pulse on the FuncTrig signal line connected to a preselected trigger matrix line just before the data is read Visual BASIC Declaration Public Sub mrIn RetData As Long ByVal Group As Integer ByVal DataSize As Integer ByVal Address As Long Call mrIn RetData Group DataSize Address Where RetData Return value containing the I O space input data Group 0 to 15 The UUT s group number DataSize
14. NOT USED NOT USED NOT USED P3 Analog Motherboard Connector Al A16 Not used B1 B16 Not used C1 C16 Not used P4 Debug Terminal Connector 1 TX1TOUT 2 RXTIN 3 GND Series 2040 Test System Page 91 P5 DOS MC68331 Debugger Cable Connector MRU User Manual V1 5 H s Ja j uni a E Or mi E Dz z ee on A s a a EI albi i s ls a GE iz eil eil EL I si Beem s Is x w e m w feci a SR B E E H E d EE EST ER Besa BE Beem iB Been Bi en ER Boa Be D H s IS amp 5 E DI Lal GJ JH LL il pel il eil ell ge Pi m a a n Ei gei q EE pa Y eil HH een Se Z s h El Gei GEH GK ea ii el ell A a m mm ca am Z i g E DE D EJ DREI A Z air mi H a a coli ME 5 a cath cal a an ol E z m mr z e Z diel Sg JNE sE ll wll BEER nm H 20 o KEN ce D o 4 A Series 2040 Test System MRU Board Part Number 0000 5356 Page 92 MRU User Manual V1 5 MRU Board
15. Patchboard Interface PIN SIGNAL SIGNAL PIN TPBI PDO BPBI PDO TPB2 PDI PD1 TPB3 PD2 PD2 TPB4 PD3 PD3 TPBS PD4 PD4 TPB6 PDS PD5 Se TPB8 PD7 PD7 TPB9 PAO PAO TPB10 PAI PA1 PA2 PA2 PA3 PA3 PA4 PA4 B TPBI11 TPB12 PAS PAS PA6 PA6 PA7 PA7 PA8 PA8 PA9 PA9 PA10 PA10 PAII PA11 PA12 PA12 PA13 PA13 SDATAOUT SCLK ROMCS ROMCS PWTS PWTS ROMOE TPB16 TPB17 TPB18 TPB19 TPB20 TPB21 TPB22 TPB23 TPB24 TPB25 PODSENSE TESTMD TPB29 NRESETMD BPB29 XPRNTMD TPB30 NLOGSTRT BPB30 NLOGSTOP XLOGWTS BPB31 XLOGWTS BUSQUAL BPB32 GND BUSQUAL BPB33 GND ROMVCC BPB34 SDATAIN Sense Series 2040 Test System Page 93 TPB31 TPB32 TPB33 TPB34 MRU User Manual V1 5 MEMORY REPLACEMENT UNIT INTERFACE CARD BPBIO Copa P p P P 3P36 P BEN P 3PB18 8PBI E pa PBN P P 8P817 BPB27 Description The Memory Replacement Unit Interface Card provides the means to connect the Logic Family Adapter LFA to the tester The Interface Card plugs directly onto the Patchboard The Patchboard is the base of the test fixture The connection to the LFA is made with two 2 34 pin data cables and one 1 fo
16. already connected to a different TMBus channel the connection will be broken Passing a negative number for the Channel parameter will break the connection between the signal selected and the Trigger Matrix Bus The signal is selected by cross referencing the signal name to the number that represents it for that particular board type and then inserting it into the Sig parameter Visual BASIC Declaration Public Sub TMSetIn ByVal Channel As Integer ByVal Slot As Integer ByVal Sig As Integer Call TMSetIn Channel Slot Sig Where Channel E 0 to 7 TMBus channel to connect disconnect to from Slot 1 to 23 The Testhead slot containing the board Sig 0 Out 0 1 Out 1 2 FuncTrig 3 ResetTrig 4 UUTTrigOut These are the only Trigger Matrix input signals available on the MRU Board EXAMPLES Const BREAKIT 5 Channel 5 Slot 22 Sig 0 Call TMSetln Charinel Slot Sig usarne connects input signal EE 0 of board in slot 22 to TMBus channel 5 Call TMSetIn BREAKIT Slot Sig disconnects input signal 0 of board in slot 22 pila li lai iaia from TMBus channel 5 Page 26 Series 2040 Test System MRU User Manual V1 5 TMSetOut The TMSetOut function is used to make or break Trigger Matrix connections to the outputs of boards containing Trigger Matrix hardware To avoid conflicting sources no two outputs from Testhead boards will be allowed to drive a single Trigger Matrix Bus cha
17. amp amp HFEA5 amp Series 2040 Test System Page 83 MRU User Manual V1 5 MAINTENANCE Calibration No calibration is necessary for the MRU Testhead board Selftest The Software distributed with the MRU Board includes a Selftest Executive called MRUExec This utility allows the user to perform self tests on the MRU Board Selftest Programs The MRU Testhead board comes with a series of Selftest routines to verify the functionality of the circuitry on the board These tests are listed below with a brief description of what each test does Page 84 MRU de f Tests the registers on the MRU board that can be written to and read from A walking bit test is performed on each register A Turbo Selftest Assembly is not required MRU_mem_f Tests the 32Kx8 Boot RAM and the 32Kx8 Product Routine RAM on the MRU board A walking bit test is performed on each memory chip Then 0x55 and OxAA are written and tested at each address location A Turbo Selftest Assembly is not required MRULogMem Tests the 32Kx32 Logic Analyzer memory on the MRU board A walking bit test is performed on each memory chip Then 0x55 and OxAA are written and tested at each address location A Turbo Selftest Assembly is not required MRULogFull Checks if the Logic Analyzer s hardware on the MRU correctly sets the bit that signals its memory is full It also checks if this bit can be cleared A Turbo Selftest Assembly is not required MRU_gnd_f C
18. be executed by the monitor When a value is specified as 8 bit it means that the size of the value is always 8 bits Command 1 Read Reads a value from the location specified by the primary address Data value 1 8 bit specifies the size of the bus access in bytes If the bus access size is illegal for the UUT processor the monitor returns the error code ERR_CYCLE SIZE The monitor must support at a minimum byte read access The value read or an error is returned Command 2 Write Writes a value to the location specified by the primary address Data value 1 8 bit specifies the size of the bus access in bytes If the bus access size is illegal for the UUT processor the monitor returns the error code ERR CYCLE SIZE The monitor must support at a minimum byte read ac cess The value to write is supplied by Date Value 2 The command returns a zero or an error Command 3 Copy Copies a block of UUT memory The primary address specifies the start of the source block The secondary address specifies the start of the destination block Data Value 1 8 bit specifies the size of the bus access in bytes Data Value 2 specifies the number of locations to copy The command returns a zero or an error Command 4 Fill Writes a value to a block of UUT memory The primary address specifies the start of the block Data Value 1 8 bit specifies the size of the bus access in bytes Data Value 2 specifies the number of loc
19. bit processor the tester requirements would be two MRU boards Likewise a thirty two bit processor would require four MRU boards Each MRU board has an eight switch dip package that is used to assign this board to a UUT ROM data byte and which processor group it is assigned to The processor group is needed when one UUT has more than one processor on it The lower nibble is used to distinguish which data byte it is assigned to and the upper nibble is used to distinguish which processor group it is assigned to Within each processor group MRU board number 0 must be assigned to the least significant ROM data byte The assignment of the processor group number is up to the user SW1 8 SWI 7 SWI 6 SWI 5 SWI 4 SWI 3 SWI 2 Example This configuration would signify board two zero inclusive of group one zero inclusive or the MRU board responsible for data bits sixteen through twenty three on the second processor All configuration concerns listed below are contained in a file named mru ini located in the Projects MRU directory This information is entered through the MRU Configuration Editor Each configuration concern is also available for each processor when multiple processors are present Reset Type The reset type specifies the reset signal as active high or active low This signal is generated on the MRU controlled LFA pod board Reset Time The reset time specifies the duration of the reset signal that is generated on the
20. eegenen ele 81 PDI DU E srt cai leali 82 MIAMI cana olii de bibione 83 Mantenne Lorena een 84 Calibidioriara EE nnee 84 SEINE eene ane ee 84 KE 84 Logic Family Adapter TES senen reeet aan 85 AWT enen alle 87 Memory Replacement Unit MRU ue 87 Ree WE 87 MRU Interconnect ett 88 Switches and jumpers iii alinea 89 Connector Pin Definitions seeen 90 P5 DOS MC68331 Debugger Cable Connector 92 MRU Board Part Number 0000 5356 92 MRU Board Patchboard Interface eee 93 Memory Replacement Unit Interface Card 94 Do on riali 94 Connector pin GU entente ed 95 Logic Family Adapter Card Wirewrap version shown 98 CADIER PRO neben dee 103 Error GOOSE menten entree ian niee online eben 109 DIGALOG MRU ERROR CODES watten nende ionen ea 110 Page 4 Series 2040 Test System MRU User Manual V1 5 Memory Replacement Unit Revision V1 5 Series 2040 Test System Page 5 MRU User Manual V1 5 a roagrvdor WW IW WD HOLdvay A Iw 21901 D stk OTIOOe CO N Wu HAZATYNV Vv 21901 3 O 4 L VaHv Jo XT N 1VNDIS e yaaya lo N IT S S 3 H a a Y LN VaHv DO 3NILNOU odi n VI Londoud Y a WOH 1V207 NYHDOHd HOLINOW N D eu 3009 elen NOLLVZITWILINI ADA MRU Block Diagram Series 2040 Test S
21. must be a 0 or 1 Invalid MRU WaitTrig Sig The signal must be a 0 or 1 Invalid MRU FunCode Setting Illegal function code setting for UUT processor 105 232 MRU Invalid MRU UUT Fill Bytes The UUT cannot fill this many bytes 105 233 MRU Invalid MRU UUT Fill Data Invalid data for the given data size 105 234 MRU Invalid MRU IO Addr Illegal MRU UO address 105 235 MRU Illegal IRQ enable flag 105 238 MRU Illegal numbber of UUT RAM locations to test 105 244 MRU SPI getChar timed out 105 246 MRU SPI putChar timed out AN ZN AN ZZZ a i Sn SS 105 247 MRU Could not determine the Logic WTS delay 105 249 MRU No samples stored in the Logic Analyzer 105 250 MRU Could not determine the ReadBack WTS delay 105 252 MRU Could not find a time for the UUT reset pulse 105 253 MRU Not enough UUT RAM to perform the copy 105 254 MRU Too many bytes for the CRC Series 2040 Test System Page 111 MRU User Manual V1 5 Page 112 Series 2040 Test System
22. pass Fr data to from the LFA The UUT itself FR is not tested in fact it is recom mended that the UUT be discon nected from the LFA during this test However the LFA needs to be pow ered up for this utility to work So the power cable must be connected and the power supply used to power up the LFA must be turned on and set to 5 0 volts The setting and turning on of the power supply must be done from another program Rasdl F This program has the ability to perform three tests on the LFA They are Read LFA Identification Test LFA Communication and LFA Data Read Test These tests are described on the next page Series 2040 Test System Page 85 MRU User Manual V1 5 Page 86 Read LFA Identification This test reads the LFA s ID The ID consists of the 8 position DIP switch used to represent the LFA s logic family type i e 3 volt 5 volt and the type of LFA to UUT connection i e wirewrap DIP The test simply calls the mrReadLFAid functional call using the given MRU group and board number The user selects the group and board number to be used The upper four bits switch 2 represent the logic family type and the lower four bits switch 1 represent the LFA to UUT connection method The ID value read is shown both graphically and as a hexadecimal number Test LFA Communication Test the ability of the LFA to drive the data address and control lines from the LFA to the MRU s Logic Analyzer Thirty four differe
23. sources to capture the various signal states after reset The results can then be viewed to check for various anomalies such as short circuited or stuck at signal conditions illegal opcodes and incorrect branching destinations Edit project code D When this option is selected from the MRUMAN menu the Ze program opens Visual BASIC It will open the vbp file with the Tan pan same name as the project in this case it will open example vbp in the Digalog Projects Example MRU directory example project If no vbp file exists in that directory Visual BASIC opens the standard blank Project1 vbp When VB code for the Example project is stored it should also be stored in this directory Configuration The MRU Configuration editor manages the necessary information describ ing the product s configuration and the various files needed to control and interact with the product during testing The first step to create a configuration for the current project is to double click on the text field labeled CPU File and select the CPU configuration file that matches your product This file describes the possible bus width options specifies the monitor and default initialization files and alerts the user to set up any additional or special CPU related considerations such as the address location of a particular relocatable CPU register that the monitor might use The monitor file is a boot up program that has been written in the native Pa
24. user through the Special Considerations option of the Configuration Editor In the example below the special consideration called REGISTER VECTOR is assigned to handle a maximum of two bytes The user can then enter a maximum of two bytes for this option in the Special Considerations option The two bytes entered by the user would be the address where their product has the processor s registers located The Special Consideration data is written to the MRU s boot RAM address given by MONITOR PARAM _ADDR when the mrConfig functional call is executed The monitor can then read this data at the given MRU boot RAM address GENERAL MONITOR_FILE c digalog include mon68020 bin BUS WIDTH 1 BIG ENDIAN TRUE BOOT HI LO _FLAG LOW EXCEPT VEC ADDR 000 EXCEPT VEC SIZE 4 EXCEPT VEC NUM 256 MONITOR PARAM ADDR 800 INITIALIZATION ADDR 400 MONITOR_ADDR 000 MAX_INIT_SIZE 40 START_IO_ADDR END_IO_ADDR MONITOR PARAM NAMES REGISTER VECTOR 2 Page 32 Series 2040 Test System MRU User Manual V1 5 MONITOR _FILE Specifies the full path to the monitor file associated with this cpu file The monitors are usually kept in the digalog include directory BUS_WIDTH Specifies the width in bytes of the boot ROM s data bus for this processor The valid numbers are 1 2 4 and 8 BIG_ENDIAN Specifies if this processor uses big endian i e Motorola or little endian i e Intel format For a big endian processor this
25. 22 GND A23 e C23 GND A24 UROMCS C24 GND A25 UROMOE c25 GND A26 URESET C26 GND A27 UWTS C27 GND A28 UXLOGWTS C28 GND A29 UXLOGSTRT C29 GND A30 UXLOGSTOP C30 GND A31 UBUSQUAL C31 GND A32 GND C32 GND Series 2040 Test System MRU User Manual V1 5 Page 101 MRU User Manual V1 5 P4 28 32 Pin Dip Connector DIP Version SIGNAL SIGNAL i Noruse 2 nor usen aerer Nor use SC koruse s oe aerer Nor use o quos fo fone Install JP 6 at Pin 9 for a 32 Pin Socket 7 foose e Fer Pescher Gomm ker DEER ve br Page 102 Series 2040 Test System MRU User Manual V1 5 Cables Data Cables There are two 34 pin data cables per LFA card The data cables connect the data address and control lines from the Interface card to the LFA card Wirewrap UUT Interface Lines If the LFA card uses the wirewrap method to connect to the UUT there will be 64 wirewrap lines per LFA card These lines connect the data address and control lines from the LFA card to the UUT Each signal pin has a ground pin adjacent to it for using twisted pair wiring 28 32 pin DIP Socket Adaptors If the LFA card uses the DIP method to connect to the UUT there will be a 34 pin connector and a twenty pin wirewrap connector per LFA card These connectors and wirewrap lines connect the data address and control lines from the LFA card to the UUT Series 2040 Test System Page 103 MRU User
26. Configures the MRU boards as specified in the project s MRU configuration file The mrConfig call must be executed before any other MRU functional calls since all other calls will depend upon configuration dependent informa tion such as byte order data size and CPU type Use the MRU Configuration Editor to construct the projects mru ini file and then use that file name in the mrConfig call Visual BASIC Declaration Public Sub mrConfig ByVal FileName As String Call mrConfig Filename Where FileName The full path to the project s configuration file EXAMPLES Dim FileName As String Configure all MRU boards for the EXAMPLE project FileName C DIGALOG PROJECTS EXAMPLE MRU MRU INI Call mrConfig FileName Series 2040 Test System Page 53 MRU User Manual V1 5 mrCo Copies NLocations of data from the UUT memory starting at the address Source to the UUT memory at address Dest Depending upon the UUT processor and its monitor any of the UUT s read write cycles should be adequate for the copy operation For example on a processor with a bus width of 16 bits read write operations can use either byte or word cycles and DataSize equals one or two bytes respectively If the FuncTrig trigger matrix signal has been enabled by using the mrTMTrigEn call then this command will produce a low pulse on the FuncTrig signal line connected to a preselected trigger matri
27. F Call Mux 0 1 10 Call AMS vret 1 1 0 0 The previous code writes a hex FF to an 8 bit Digital to Analog Converter DAC located on the UUT at hex address 1000 The output of the DAC is connected to channel 0 of the Relay Multiplexer RMUX The Mux call connects RMUX channel 0 to the Amplitude Measurement Systems AMS signal 1 Sig1 with a 20 Volt range The AMS call measures the Voltage on signal 1 and returns it in vret The analog functional calls are fully explained in the analog programming manual Once the test is running from Visual BASIC the engineer can convert UUT processor intensive tests such as memory testing and ADC calibration into product routines Product routines are written in the native language of the processor and can be downloaded and executed within the UUT s memory This speeds up testing even more by eliminating the time overhead that is required for the functional calls in the Visual BASIC test program to communicate with the monitor Instead of receiving commands one at a time from the VB test program functional calls and returning a status reply for each command s execution the monitor simply downloads the product routine executes it and returns one response Page 8 Series 2040 Test System MRU User Manual V1 5 Product Routines Product routines are routines that are written in the native language usually assembly language of the processor and downloaded to the UUT for it to execute The ro
28. MRU User Manual V1 5 Series 2040 Test Systems MRU User Manual Part Number 4200 0172 Version 1 5 Series 2040 Test System Page 1 MRU User Manual V1 5 Table Of Contents Memory Replacement Unitaria 5 MRU Block Desmo 6 SOFIMARE recon 7 DESCRIPTION OF THE DEVELOPMENT CYCLE 7 Product ROUUNES E 9 Using a Product Routine nemende etende 10 Using the Trigger Matrix with a Product Routine 11 Trigger Matrix EE 12 OVERVIEW OF MRUMAN S PROJECT UTILITIES cc ceeeeeeeeees 14 File MEN serene neden eee ia ade etn 14 NK Menterne elkeen nende 14 Tester Resources Manager es ER durende 15 RTL EE 16 KORAN ZEN aided ed 17 Edit project EE 20 Config ra ee ieee eed edet 20 MRU Selftest E 22 SETUP OF MRU PRIOR TO TESTING gite 23 BOARD CCRN 23 Board Number ar lare 23 Reset A EO 23 Reset Eeer 23 CPU E 24 Byte Orden lai 24 Monitor Ee 24 Initialization GI 24 Active ROM Chip Select Level 24 DOOE AGE alare 25 TRIGGER MATRIX FUNCTIONS 3 cipria 25 El EE 26 RER 27 GIST neee reale 28 EXTERNAL CONTROLS RER 30 WRITING A MONITOR PROGRAM eee 31 Monitor epu EE 31 MONITOR PILE E 33 BIS WW MD EN 33 BIG SENDIAN RE 33 Page 2 Series 2040 Test System MRU User Manual V1 5 BOOT MIO EE 33 EXCEPT VEC ADDR ormatie 33 EXCEPT MEC SIZE ran eenn ennen eeens 33 EXCEPT WEG REN eet 33 MONITOR PARAM ADDR ser 33 INSTIALIZATIOIN ANDER EE 34 MONTOR TEE 34 EE EE 34 START ADDR t
29. MRU controlled LFA pod board Series 2040 Test System Page 23 MRU User Manual V1 5 The bus width specifies the configuration of the MRU boards required to emulate the ROM devices For example if a single 16 bit processor is selected the data bus width is sixteen bits and therefore creates a system requirement of two MRU boards Software determines that the two MRU boards are for the same processor and executes accordingly This value is part of the cpu file and cannot be edited from this dialog CPU File This file contains all CPU specific configuration concerns such as bus width high or low boot processor name of the monitor file etc Byte Order The byte order is the significance arrangement of the CPU data bus For example the Motorola 680xx family of processors uses Big Endian MSB at lowest address while the Intel 80x86 family uses Little Endian LSB at lowest address It is used for informational purposes only This information can not be changed by the user Due to software limitations the least significant data byte is always assigned to MRU board 0 Monitor File This file is downloaded into the ROM space of the product RAM on the MRU board and is responsible for accepting and acting upon commands given to it to allow the test engineer to fully interact with and test the product The monitor file to be used can not be changed by the user It is specified within the CPU file The CPU file is generated by the writ
30. MRU project a message box is displayed prompting the user to create one For the purposes of this discussion a project named Example could be created by selecting Create from the File menu and entering the name Example in the resulting inputbox This also creates a subdirectory called Digalog Projects Example MRU where MRU project specific files are stored Project Menu MRUMAN DS Once the project is selected or created it must be properly configured All project specific information can be entered or edited using options from the Project menu These options include Tester Resources Direct execution MRU Logic Analyzer Edit project code Configuration and Selftest Tester Resources Direct execution MRU Logic Analyzer Edit project code Configuration SelfTest Page 14 Series 2040 Test System MRU User Manual V1 5 Tester Resources Manager The Tester Resource Manager is used to track and manage the tester resources including all the boards in the Testhead and the UUT power supplies Information about these resources can be automatically generated or manually defined and are used to generate a Patchboard Interface Map and define the pin locations of these resources at the Patchboard This information can be saved to the Registry and can be used by other Digalog System s applications Specifically the software is capable of printing out a Patchboard Map containing Patchboard pin mnemonics b
31. N MROUT An active low transition pulse is generated on the ResetTrig line just prior to negating the UUT reset line The time between each of these signals will be a few microseconds The active low pulse on ResetTrig will occur automatically whenever the mrBoot or mrReset functional call is executed Using this signal allows a Testhead board to be triggered whenever the UUT is booted or reset Page 12 Series 2040 Test System MRU User Manual V1 5 An active low transition pulse is generated on the UUTTrigOut line when a product routine executing in the UUT processor reads from the Trigger Matrix Pulse offset within the flag area of the boot ROM space The following are the 6 input triggers with the corresponding signal number used in the TMSetIn trigger matrix functional call Signal Name Number men TMLogWTS TMLogS TRT TMLogSTOP When the MRU board detects a rising signal edge on the In0 or In1 line it is latched and can be checked for with the functional call mrWaitTrig The mrWaitTrig functional call then clears the latch before it returns If a pulse has been latched before mrWaitTrig is called or its TimeOut parameter is zero it will clear the latch and return immediately The UUTTrigIn line is connected to the tester status register which can be read by a product routine executing in the UUT processor This allows a product routine to wait for some trigger from another Testhead board The address of the tester stat
32. S CLOCKS LFA Pod interface controls and clocks UD x UUT data lines zero to seven eight to fifteen sixteen to twenty three etc dependent on MRU board number UA x UUT address lines zero to thirteen UROMVCC product VCC monitoring signal UROMCS product ROM chip select signal monitored and used for emulation control UBUSQUAL product signal logically or d with UROMCS to define the valid and inactive regions of a bus cycle UROMOE product ROM output enable monitored and used for emulation control URESET product ROM reset signal generated by MRU and used for emulation control UWTS product ROM write strobe signal monitored and used for emulation control UXLOGWTS externally generated write strobe used to capture logic analyzer data samples UXLOGSTRT externally generated software generated signal used to arm logic analyzer UXLOGSTOP externally generated software generated signal used to disarm logic analyzer GND product ground used to match LFA pod ground and to shield signals in twisted pair wiring Page 30 Series 2040 Test System MRU User Manual V1 5 WRITING A MONITOR PROGRAM The monitor program accepts commands to read and write any location in the UUT processor s address map The test engineer uses Visual BASIC to send commands to the MRU board The MRU breaks the command into lower level commands to be executed by the monitor This allows the UUT to be tested without
33. T s I O space Only the least significant DataSize bytes of OutData is written This command is only available for processors that have an I O space If the FuncTrig trigger matrix signal has been is enabled by using the mrTMTrigEn call then this command will produce a low pulse on the FuncTrig signal line connected to a preselected trigger matrix line just before the data is written Visual BASIC Declaration Public Sub mrOut ByVal Group As Integer ByVal DataSize As Integer ByVal Dest As Long ByVal OutData As Long Call mrOut Group DataSize Dest OutData Where Group 0 to 15 The UUT s group number DataSize 1 2 or 4 The size in bytes of the write cycle to use Dest Valid UUT I O address to write to OutData amp HO to amp HFFFFFFFF Data to be written out EXAMPLES Const UUT_GROUP 0 Const BYTEWISE 1 Have the product write a zero to port 3 Call mrOut UUT_GROUP BYTEWISE amp H3 amp amp HO amp Page 68 Series 2040 Test System MRU User Manual V1 5 mrPrReset Resets the UUT so that a previously loaded boot RAM product routine or monitor can be started It then waits for data to be returned The argument Timeout gives the time to wait in milliseconds A timeout of zero instructs the call to not wait for return data An MRU communication error is returned if Timeout is reached before the product routine returns data Visual BASIC Declaration Public Sub mrPrReset RetD
34. a 2 byte word Error writing a 2 byte word Error reading a 4 byte word Error writing a 4 byte word Error opening the file to hold the temporary except vectors Full path to golden samples file is too long Could not open golden samples file in LearnLogicWtsDelay Bad Data Size Only 1 2 4 or 8 bytes allowed Byte readback test failed Short readback test failed Long readback test failed MRU board not present No MRU boards found Illegal MRU group number Given MRU group not configured Bad name access to the CPU file Bad name access to the INIT file Invalid reset action Invalid auxLine level Invalid Logic Analyzer write strobe signal 105 197 105 199 105 201 105 205 105 206 105 207 105 208 105 209 105 210 105 211 105 212 105 213 105 214 105 215 105 216 105 217 105 218 105 220 105 221 105 223 MRU MRU MRU MRU MRU MRU MRU MRU MRU MRU MRU MRU MRU MRU MRU MRU MRU MRU MRU MRU ZN gt ZN ZN AN ZN AN ZN 2222222 IR SS SS SS SS SSS SSS SS SS Page 110 Series 2040 Test System MRU User Manual V1 5 105 224 105 225 105 226 105 227 105 228 105 229 105 230 105 231 MRU MRU MRU MRU MRU MRU MRU MRU Invalid Logic Analyzer write strobe delay File path to monitor file too long Invalid MRU RAM Addr Illegal MRU RAM address Illegal MRU RamTest Timeout Invalid MRU TMPulse Sig The signal must be a 0 or 1 Invalid MRU TrigEn Flag The flag parameter
35. arting address argument Upon completion of the routine the processor returns back to the next monitor instruction by utilizing the address that it saved on the stack The mrJump causes the processor to immediately begin executing the code at the given product routine starting address argument Upon completion of the routine a jump instruction must be executed to jump to the section of the monitor that sends a return value back to the user It then resumes waiting for the next command instruction from the MRU All Digalog written monitors are explicitly documented in this respect for the test engineer to easily write product routines that properly jump back into the monitor upon their completion One advantage of the mrJump functional call over the mrCall functional call is that it can be used even if there is no UUT RAM available or before the UUT RAM has been tested because mrJump does not require a stack To return a value to the VB test program the product routine loads it into the UUT processor register specified in the monitor documentation for that processor When the product routine returns to the monitor the monitor passes the value in this UUT processor register to the mrJump functional call in the test program The size of the return value depends on the size of the UUT processor register If more than one value needs to be returned to the test program the product routine can write those values to an accessible tested area of UUT RAM T
36. ata As Long ByVal Group As Integer ByVal DataSize As Integer ByVal Timeout As Long Call mrPrReset RetData Group DataSize Timeout Where RetData Return value from the product routine Group 0 to 15 The UUT s group number DataSize 1 2 or 4 The size in bytes of the return data Timeout 0 Do not wait for the product routine to return data 1 to 60000 Time in milliseconds to wait for return data EXAMPLES Const UUT GROUP 0 Const LONGWISE 4 Const RESET PULSE 0 Dim FileName As String Dim RetData As Long On Error GoTo PrResetErr Load the file into product routine RAM FileName C DIGALOG PROJECTS EXAMPLE MRU PRTEST BIN Call mrLoad UUT_GROUPLONGWISE amp HO amp FileName Reset the UUT and wait one second for return data Call mrPrReset RetData UUT_GROUPLONGWISE 1000 amp Display the return data MsgBox The Product Routine returned amp CStr RetData Exit Sub Handle the error that can occur if product routine does not respond within one second PrResetErr MsgBox The Product Routine did not complete Exit Sub Series 2040 Test System Page 69 MRU User Manual V1 5 mrRamTest Tests NLocations of UUT RAM starting at the address Start If there is a failure FailAddr will hold the address at which the test failed Expect will be the byte value expected and Actual will be the byte value which was actually read at FailAddr A failure is
37. ations to fill Data Value 3 specifies the value used to fill the block The command returns a zero or an error Command 5 Ram Test Tests a block of UUT RAM The primary address specifies the start of the block Data Value 2 specifies the number of locations to test The testing method is left up to the discretion of the monitor programmer ERR RAM VERIFY is returned on an error Only one byte of actual and expected data is returned Finally the four byte address is returned Series 2040 Test System Page 45 MRU User Manual V1 5 Command 6 IRQNum Bit 0 of the ErrFlag IRQ Enabled is checked by the MRU This bit when asserted high signifies that an exception has occurred and the exception number was stored The activated ISR stores the exception number at the memory location pointed to by the exception number address contained in the communication area The exception number will be initialized to a specific value by the monitor when the stack pointer is initialized This function checks the current value against the initialized value to detect if an exception has indeed occurred The command returns the exception number or NO_ERROR to the MRU via the protocol previously defined This feature allows the test engineer to ascertain if an interrupt occurs in response to a particular stimulus of the product Command 7 In Reads a byte from the I O space of the UUT processor The primary address specifies the location to read fr
38. b mrBoot ByVal Group As Integer Call mrBoot Group Where Group 0 to 15 The UUT s group number EXAMPLES Const DASH CONTROLLER 0 a 68040 Const IGNITION CONTROL 1 a 68HC11 Dim FileName As String Configure all MRU boards for the EXAMPLE project FileName C DIGALOG PROJECTS EXAMPLE MRU MRU INI Call mrConfig FileName Load the monitors into both UUTs Call mrBoot DASH_ CONTROLLER Call mrBoot IGNITION_CONTROL As a side note its always wise to use constants or even variables for your arguments rather than magic numbers Code is then clearer and maintenance becomes much easier Page 50 Series 2040 Test System MRU User Manual V1 5 mrCall Calls a microprocessor specific product routine previously loaded at the address CodeAddr The address can be in Product Routine RAM Boot RAM or UUT RAM The function will wait Timeout milliseconds for the product routine to execute and then return to the emulation monitor A Timeout of zero causes the function to return immediately leaving the product routine in control of the UUT The only way to then regain control is to reboot the UUT or load and run a boot RAM product routine Since this function directs the monitor to save its program counter s contents to the stack to be used when returning back from the product routine the UUT must have its own RAM and the stack pointer must have been previously initialized by cal
39. butes oe mese sur ate rest Oo von eeermmm resto poos Sierre Re ny ono ever te Rear Jam _ ponor Fe tase avr Jam _ 402 Dabs tags Ayr Jam _ NOTE The offset of 0 is actually 8K below the top of memory Use of the Error Flag offset signals the MRU that an error has occurred and that it should request the error code number from the monitor The flag is generated by a read access within the flag area with address bit A7 asserted high on MRU board 0 Page 40 Series 2040 Test System MRU User Manual V1 5 Communication Area Located at offset Ox7CO above the product Routine Area the following parameter locations are defined as indicated Data Type Primary Address Secondary Address 4 Data Value 1 Data Value 2 Data Value 3 Data Value 5 0 Data Value 6 8 Command Number Flag Byte 57 Data Value 4 32 Exception Address 58 Flag Byte Bit 0 IRQ Enabled Flag O interrupt exception number capturing disabled 1 interrupt exception number capturing enabled This bit is used by the interrupt service routines to determine whether to save or discard the exception number when an exception occurs This bit will only be asserted by the firmware if a valid stack pointer has already been loaded Bit 1 Stack Enabled Flag 0 invalid stack pointer 1 valid stack pointer This bit is used to verify proper use of the mrCall functional call to check if a valid stack exists and to signal what a
40. ct address to read from for the application The address must map to board 0 if the application has a UUT bus wider than 8 bits The UUTTrigOut line is connected to hardware addressed at the Trigger Matrix Pulse offset within the address map By reading from this location a falling logic 1 to logic 0 pulse is delivered to the connected trigger matrix line Consult the Address Offset Map of the MRU as seen from UUT processor to determine the exact address to read from for your application The address must map to board 0 if the application has a UUT data bus wider than 8 bits Series 2040 Test System Page 11 MRU User Manual V1 5 Trigger Matrix Connections The MRU board has 5 output triggers and 6 input triggers that can be connected to the trigger matrix The following are the 5 output triggers with the corresponding signal number used in the TMSetOut trigger matrix functional call Signal Name Number An active low transition logic 1 to logic 0 pulse is generated on either the OutO or Out1 line by the functional call mrTMPulse and can be used to trigger some other action on another board in the Testhead configured to sense the corresponding signal An active low transition pulse is generated on the FuncTrig line when the auto trig mode has been enabled with the mrTMTrigEn functional call AND one of the following functional calls is executed in the test program MRCOPY MRFILL MRREAD MRWRITE MRI
41. ction to take when servicing an interrupt Series 2040 Test System Page 41 MRU User Manual V1 5 Exception Number Address The initial stack pointer value is written here by the MRU when the Load Stack Pointer command is given The monitor reserves this initial stack location for storage of an exception number if one should occur The stack then actually starts one location above or below depending on the stack s direction from the initial stack pointer All information in the communication area conforms to the byte ordering of the UUT processor Addressing of the communication area by the monitor must take into account the bus width To address Data Value 1 on a single byte machine an offset of seven bytes would be added to the Data Value 1 location Tester Status Register Bits 0 2 Unassigned These bits may be used by a product routine to receive commands from the test program Bit 3 Command ready Flag 0 No command ready 1 Command ready This bit is used to signal the monitor program that a command has been loaded into the communication area Bit 4 Trigger Matrix In O Pulse received No pulse received This bit is used to signal the UUT that a pulse was received on the trigger matrix bus Bit 5 Product Routine Area Access Flag 0 UUT does not have access 1 UUT has access This bit is used to determine if the UUT has access to the product routine and communication area The MRU places the command
42. d exceeds MaxReturnSamples Second it returns all 32 768 samples of the logic analyzer s memory if it is full and MaxReturnSamples is 32768 Third it returns only the samples stored since the logic analyzer was last enabled and the number of samples is fewer than MaxReturnSamples The number of samples actually returned is placed in the return variable SamplesRead Visual BASIC Declaration Public Sub mrReadLogicData SamplesRead As Long ByVal Group As Integer ByVal FileName As String ByVal MaxReturnSamples As Long Call mrReadLogicData SamplesRead Group FileName MaxReturnSamples Where SamplesRead The number of samples read from the logic analyzer s memory Group 0 to 15 The UUT s group number Filename File to store the samples in MaxReturnSamples 1 to 32768 Maximum number of samples to return EXAMPLES Const UUT GROUP 0 Dim FileName As String Dim SamplesRead As Long Read a maximum of 1000 samples and store them in the file given by FileName FileName C DIGALOG PROJECTS EXAMPLE MRU LOGIC LOG Call mrReadLogicData SamplesRead UUT_ GROUP FileName 1000 amp Page 74 Series 2040 Test System MRU User Manual V1 5 mrReceive Waits for a product routine to finish and then reads its return data value RetData The argument Timeout specifies in milliseconds the time to wait for the product routine to finish A timeout of zero means to check for the prod
43. detected by comparing the actual data to the expected If they are different a failure has occurred To finish testing the UUT RAM after a failure this command must be executed again using FailAddr 1 as the address Start and NLocations will be the original NLocations value minus the number of tested addresses NOTE The actual RAM test will vary due to the fact that the test is actually done by the monitor and that there may be processor limitations e g not enough registers that prevent a more extensive RAM test If a more extensive RAM test is desired it may have to be implemented using the functional calls mrRead and mrWrite Visual BASIC Declaration Public Sub mrRamTest FailAddr As Long Expect As Integer Actual As Integer ByVal Group As Integer ByVal Start As Long ByVal NLocations As Long ByVal Timeout As Long Where FailAddr Failed address Expect Test data written Actual Data actually read Group 0 to 15 The UUT s group number Start Valid UUT RAM address NLocations Number of UUT RAM locations to test Timeout 1 to 60 000 Time in milliseconds to wait for the test to finish Page 70 Series 2040 Test System EXAMPLES Dim FailAddr As Long Dim Expected As Integer Dim Actual As Integer Test the bottom 16K Bytes of the UUT RAM on MRU Group 0 Call mrRamTest FailAddr Expect Actual 0 amp H0 amp 1024 16 50 Check for a failure If Expect lt gt Ac
44. e Logic Analyzer s address mrLogicModeEnable Enable disable the Logic Analyzer mrLoadStackPtr Initialize the UUT s stack to one of its RAM addresses mrOut Write data to the UUT I O space mrPrReset Reset the UUT and wait for return data mrRamTest Test a section of UUT RAM mrRead Read data from UUT memory mrReadLFAid Reads the LFA s ID mrReadLogicData Read the stored data from the Logic Analyzer mrReceive Fetch the return value of a product routine mrReset Control the state of the UUT s reset line mrSelectLogicWts Select one of eight Logic Analyzer write strobes mrSend Write to the UUT status byte mrSetCode Set UUT function code lines mrTMPulse Output a low pulse on Out0 or Out1 mrTMTrigEn Enable disable the FuncTrig signal mrWaitTrig Wait for a preselected signal on the Trigger matrix mrWrite Write data to UUT RAM Series 2040 Test System Page 49 MRU User Manual V1 5 mrBoot Loads the emulation monitor into the UUT boot RAM space on the MRU board and then boots up the UUT via its reset line After the UUT is reset the monitor is in control of the UUT The test engineer can then use the UUT s own processor to test itself and its associated hardware The name and location of the monitor program is contained in the cpu file for the given project The cpu file to use for the project is selected from the configuration editor Visual BASIC Declaration Public Su
45. e monitor location were a product routine will jump to after a mrJump command must also be given by the writer of the monitor And since this location can not change the location of the monitor must not change INITIALIZATION ADDR Specifies the address where the software will automatically place the monitor s initialization code within the MRU s boot space MONITOR ADDR Specifies the address where the software will automatically place the monitor s code within the MRU s boot space MAX_INIT_SIZE Specifies the maximum size for the initialization code Since the writer of the monitor maps where the monitor initialization code and special consider ation information goes and since the user can add to the initialization code the maximum space this code can take in the boot space must be specified so these three items do not overwrite each other START_IO_ADDR Specifies the starting I O space address for the processor This element is only valid for processors that have an I O space END_IO_ADDR Specifies the ending I O space address for the processor This element is only valid for processors that have an I O space Handling exceptions The monitor must be written so it can handle exceptions Fatal and nonfatal interrupt service routines ISRs need to be handled differently The nonfatal ISRs first need to check if the UUT s stack pointer has been initialized by the mrLoadStackPtr function If the stack has been ini
46. eName C DIGALOG PROJECTS EXAMPLE MRU FIRM BIN Call mrLoad UUT GROUP BYTEWISE amp HO amp FileName Now reset the product Call mrPrReset RetData UUT_GROUP BYTEWISE 0 Test out firmware without burning EPROMS Series 2040 Test System Page 63 MRU User Manual V1 5 mrLoadimm Writes the parameter ImmData into memory at the address Dest This address value can be located in boot RAM product routine RAM or UUT RAM The DataSize argument specifies the number of bytes in ImmData that are going be written starting with the least significant byte Visual BASIC Declaration Public Sub mrLoadlmm ByVal Group As Integer ByVal DataSize As Integer ByVal Dest As Long ByVal ImmData As Long Call mrLoadimm Group DataSize Dest ImmData Where Group 0 to 15 The UUT s group number DataSize 1 2 or 4 The size in bytes of the read write cycle to use Dest Valid boot RAM product routine RAM or UUT RAM address ImmData amp HO to amp HFFFFFFFF The data to be written depending on the size of the Read Write cycle EXAMPLES Const UUT_GROUP 0 Const WORDWISE 2 Change one vector in the boot memory Call mrLoadimm UUT_GROUP WORDWISE amp H00000004 amp amp H17D3 amp Page 64 Series 2040 Test System MRU User Manual V1 5 mrLoadLogicMemoryAddr Sets the logic analyzer s memory to address the argument Address The logic analyzer will be disabled before its address
47. ea resource The purpose of the signal area is to provide a communication path from the monitor back to the MRU Because the monitor only has readable access to the ROM space it cannot write data to be returned to the MRU Thus another method is used the signal area resource The signal area resource is only available on MRU board 0 Board 0 is always connected to the least significant byte of the UUT data bus The MRU loads the 256 locations of the signal area resource with the signal values 0 255 in sequential order The monitor or product routines can use this section to communicate data back to the MRU To use the signal area resource lookup table the executing code performs a read access at the location containing the number that it wants to transfer back to the MRU The value at that location is latched for the MRU to read and a flag is set in the flag area to notify the MRU that a signal value has been latched Addressing of the signal area locations must take into account the width of the data bus in the same way as the communication area must be addressed Series 2040 Test System Page 39 MRU User Manual V1 5 ADDRESS OFFSET MAP of MRU as seen from UUT processor Low Boot Processor 8 bit data bus Start End Description Attributes cl Deemno ul kamera vum femore Jeum _ el frese su Regier Jeu _ vue emo ts amer Mode ren om our Dae tg amer ite Team _ High Boot Processor 8 bit data bus Start End Description Attri
48. ecific to the processor the monitor is written for The cpu file is read when the mrConfig functional call is executed The information contained in the cpu file is then used to setup the MRU hardware and software for the processor it was created for The listing on the next page shows the elements that must be in the file with example settings for each element Following the listing is a description of each element The section titled GENERAL must be in every cpu file All of the elements must be initialized except the two dealing with a processors I O space These two elements are only valid for processors that have an I O space Series 2040 Test System Page 31 MRU User Manual V1 5 The section titled MONITOR PARAM NAMES is optional This section deals with processor options see the Special Considerations option in the configuration editor that are not dealt with in the GENERAL section of the cpu file or are not part of the configuration editor An example of an option that would have to be handled in this section is the location of a processors s registers if they can be relocated within the processor s memory map First the writer of the monitor assigns a name to each element they place under the IMONITOR PARAM NAMES section Then each element is initialized to the number of bytes needed to be reserved in the MRU boot RAM to store the element s value the value will be assigned by the
49. element is set to TRUE and for a little endian processor this element is set to FALSE BOOT_HI_LO_FLAG Specifies if this processor is a high or low boot For a high boot processor the valid entry is HIGH and for a low boot processor the valid entry is LOW EXCEPT_VEC_ADDR Specifies the address location within the MRU s 4K boot space of the first exception vector This element will only be used by projects with low boot processors that have had their boot space re mapped If the boot space is re mapped the exception vectors will have to be rewritten to correspond to the new location EXCEPT_VEC_SIZE Specifies the size in bytes of each exception vector This information is needed so the software knows how to rewrite the exception vectors to the MRU s boot space for the various combinations of exception vector bytes and number of MRU boards for a given project EXCEPT_VEC_NUM Specifies the number of exception vectors for this processor MONITOR_PARAM_ADDR Specifies the address where the software will automatically place the monitor s special consideration information within the MRU s boot space This is one of three boot space addresses that must be specified by the writer of the monitor The other two are INITIALIZATION ADDR and MONITOR ADDR The addresses were to load these three items must be given by the writer of the Series 2040 Test System Page 33 MRU User Manual V1 5 monitor because th
50. eply loop to be jumped to must be given by the writer of the monitor In addition any data being returned from the product routine must be stored in a UUT processor register specified by the writer of the monitor Command 11 Call Calls a product routine with a Jump to Subroutine instruction The primary address specifies the address to jump to When the Jump to Subroutine instruction is executed the UUT s processor automatically places the address to return to on the stack Therefore when the product routine does its Re turn from Subroutine instruction it retrieves the return address from the stack This return address will be the next instruction in the call command after the Jump to Subroutine instruction In addition any data being returned from the product routine must be stored in a UUT processor register specified by the writer of the monitor When code execution returns to the call com mand it should jump to the reply loop so the product routine data can be returned to the MRU Command 12 Download Downloads a maximum of 32 bytes of product routine at a time The primary address specifies the location to start downloading to Data value 2 8 bit specifies the number of data values being passed in the 32 byte block If this value is greater than 32 then the error ERR BLOCK SIZE is passed back to the MRU If it is 32 or less then that number of bytes are copied from the block to t
51. er of the monitor and the two files must go together Initialization File This project specific file contains processor setup routines that are executed by the processor immediately following its reset mode but prior to execution of the monitor program Active ROM Chip Select Level Used to select the active state of the UUT s ROM chip select signal This needs to be initialized so the LFA can be properly set up to correctly pass read and write data from the UUT to the MRU board Page 24 Series 2040 Test System MRU User Manual V1 5 Boot Address This is only used for cases where the boot space on a low boot processor has been re mapped to another location The location of the re mapped boot space is needed so the exception vectors in the monitor can be changed to their new location If a high boot processor is configured or the boot space is not re mapped this field should be zero TRIGGER MATRIX FUNCTIONS The following pages contain the description of the functional calls that are used with the trigger matrix feature located on the MRU card Syntax for Visual BASIC is provided Series 2040 Test System Page 25 MRU User Manual V1 5 TMSetIn The TMSetIn function is used to make or break Trigger Matrix connections to the inputs of boards containing Trigger Matrix hardware Due to hardware restrictions an input to a board cannot be connected to more than one Trigger Matrix channel at a time If the selected input signal is
52. ess Call mrWrite UUT_GROUP BYTEWISE Address DataByte And amp H5A amp Then switch back to the User Data Space for normal operation Call mrSetCode UUT_GROUP USER_DATA USER_DATA Series 2040 Test System Page 79 MRU User Manual V1 5 mrTMPulse Outputs a low pulse on the given signal line to the trigger matrix By using the trigger matrix functional calls the Outx signal selected by the parameter Signal can be routed to one of the trigger matrix output signals This pulse can be used to trigger another card in the Testhead Visual BASIC Declaration Public Sub mrTMPulse ByVal Group As Integer ByVal Signal As Integer Call mrTMPulse Group Signal Where Group 0 to 15 The UUT s group number Signal 0 Out0 trigger matrix signal line 1 Out1 trigger matrix signal line EXAMPLES Const UUT_GROUP 0 Const OUT1 1 Have the MRU board send a low pulse on the Out1 signal line Call mrTMPulse UUT_GROUP OUT1 Page 80 Series 2040 Test System MRU User Manual V1 5 mrTMTrigEn Enables or disables the FuncTrig signal line based on the value of Flag When enabled a low pulse is sent on the preselected trigger matrix line when any of these commands are executed mrCopy mrFill mrRead mrWrite mrin and mrOut The function returns the previous state of the enable flag in PrevState Visual BASIC Declaration Public Sub mrTMTrigEn PrevState As Integer ByVal Group As Integer
53. etData as Long ByVal Group As Integer ByVal Address As Long ByVal Timeout As Long Call mrJump RetData Group Address Timeout Where RetData Return value containing data from the product Group 0 to 15 The UUT s group number Address Any valid address for a product routine to be placed Timeout 0 Do not wait for the product routine to return 1 to 60000 Time in milliseconds to wait for the product routine to return EXAMPLES Dim RetData As Long Dim FileName as String Const UUT_GROUP 0 Const DataSize 1 Const PR ADDR amp H1000 Load the burn in code FileName C DIGALOG PROJECTS EXAMPLE MRU BURNIN BIN Call mrLoad UUT GROUP DataSize PR_ADDR FileName Jump to the burn in code don t wait for return data Call mrJump RetData UUT_GROUP PR_ADDR 0O Page 60 Series 2040 Test System MRU User Manual V1 5 Wait 65 seconds Call Idle 65000 Reboot the monitor for the post burn in checkout Call mrBoot UUT Series 2040 Test System Page 61 MRU User Manual V1 5 mrLfaDisconnect Disables all of the LFA boards for the UUT whose group number is in the argument Group so that the LFA data address and control lines are not driven from the UUT to the MRU board Before disconnecting the LFAs the UUT is placed in the reset state and it is left as such The LFAs are automatically enabled within the mrBoot Visual BASIC Declaration Public Sub mrLfaDisconnect ByVal G
54. ge 20 Series 2040 Test System MRU User Manual V1 5 language of the product and performs whatever commands are given to it by the MRU board in order to execute the desired functional call The next step is to double click on the text field labeled Initialization File and then select the monitor initialization file to be used for this project The initialization file contains code that is executed by the product after being reset but before the monitor is run It may include instructions to disable a watchdog timer to disable the maskable interrupts or to specify the behavior of programmable I O pins H the selected monitor handles special considerations hit the command button called Monitor Specific Considerations to bring up the configuration editor that allows the user to initialize these options The writer of the monitor must specify the special considerations the monitor handles The name of the special considerations and the MRU board s Boot RAM storage space in bytes needed for these special considerations are entered by the writer of the monitor into the processor s cpu file under the heading MONITOR PARAM NAMES This data is read when the d digalog projects example mru mru ini Monitor Specific De Help Considerations editor is selected When the Monitor CPU File Product Reset Specific Considerations editor ms is displayed the user can click ee on one of the items in the Achvelavel
55. having to program test routines in the native language of the UUT s processor The MRU also accepts commands to download data to any space in the UUT s address map This data could be machine language product routines which the monitor can be instructed to execute The monitor will be downloaded to the memory location given by the MONITOR ADDR entry in the project s CPU file This location is specified by the author of the monitor program When the UUT boots up the first code that is executed is the initialization file A default initialization file is supplied by Digalog The test engineer can add code to this file that is specific to the UUT The initialization code is used to set up registers enable disable watchdogs and anything else that must be setup either due to time or order of execution restrictions This code might also be needed to setup the UUT to be able to execute the monitor from the MRU board The initialization code is always executed prior to the monitor even if the only function of the initialization code is to jump to the monitor The initialization file will be downloaded to the memory location given by the INITIALIZATION_ADDR entry in the project s CPU file This location is also specified by the author of the monitor program Monitor cpu file Each monitor must be accompanied with a second file This file must have a cpu file name extension The cpu file will contain configuration type information sp
56. he VB test program then uses mrRead to retrieve the values from the UUT RAM area Page 10 Series 2040 Test System MRU User Manual V1 5 The product routine returns to the monitor in one of two ways depending on how it was called If it was called by mrJump it must execute a jump instruction to the mrJump return address in the monitor which was specified in the monitor documentation If it was called by mrCall it must execute a return from subroutine instruction to return to the monitor The second method requires accessible tested UUT RAM and a valid stack pointer address Using the Trigger Matrix with a Product Routine The product routine can be synchronized with other boards in the Testhead by using the trigger matrix Two signals are provided for connection to the trigger matrix the UUTTrigIn signal for input from the trigger matrix and the UUTTrigOut signal for output to the trigger matrix The UUTTrigIn line is latched and connected to bit 4 of the tester status register This bit is high or at logic 1 when no pulse has been received on the trigger matrix line that it is connected to The bit goes low or to logic 0 when a rising logic 0 to logic 1 pulse is detected on the connected trigger matrix line The bit remains low until the product routine reads from the ResetTM offset within the flag area Consult the Address Offset Map of the MRU as seen from UUT processor to determine the exa
57. he digital motherboard The output signals can be used to signal other boards that the MRU has performed or started to perform a certain function The input signals can be used to signal the MRU that another board has finished or started a certain function A second advanced feature of the MRU is the Logic Analyzer The Logic Analyzer can be used to record the data address and control signals of the UUT The Logic Analyzer can be started and stopped by signals coming through the Trigger Matrix bus and the LFA board from the UUT One use of the Logic Analyzer is to record the boot sequence of the UUT and then compare it to a known good sequence This allows the user to determine the point at where the boot up process fails Series 2040 Test System Page 87 MRU User Manual V1 5 9G 9 0000 DOUM SE posulse JOSUUODIO4UI ou tT eee DI t fe kE Boon teen hok Sp CED i ay 4591 r JPM 0965 0000 I 12338111 E Dee SJ pipog OSUUOTIB U Tr 8 ol 9EG 0000 dDd did 1 KEE SI PJioog SODLSIU AID 216807 04 punolS Li ge Ze EE Se p Ze 905 0000 2E d d SCH DO ik seljddns Jemod INN E GER L WOI SBDYOA a 7905 0000 ADI 1 MOd MRU Interconnect Series 2040 Test System Page 88 MRU User Manual V1 5 Switches and Jumpers SW1 1 through SW1 4 select the MRU board number SW1 4 SW1 3 SW1 2 SW1 1 Board Number or on Jom orr Jor o orr Joer or orerejyel
58. he engineer must also select the proper logic family adapter board LFA pod to match the logic family of the address and data bus interface chips on the UUT Then the test engineer configures the system using the configuration manager When the UUT is connected to the MRU system and power is supplied to the UUT the test engineer can use the MRU s logic analyzer to check if the system can boot The Direct Execution mode permits the engineer to boot up and reset the UUT as well as interactively issue commands to the monitor Once the monitor is booted the engineer can use the various Direct Execution mode Series 2040 Test System Page 7 MRU User Manual V1 5 commands such as mrWrite and mrRead to access the hardware on the UUT to verify preliminary operation The commands used to verify the operation can be incorporated into a Visual BASIC test program to automate and to speed up hardware testing After the engineer is satisfied with the basic operation of the UUT the Visual Basic environment can be entered Using Visual Basic the engineer can write test code to test the UUT The MRU functional calls can be used with the analog functional calls to test hardware on the UUT The following example Visual BASIC code shows the ease with which the tests can be implemented Dim vret as Double Call Power UUT O 5 0 1 5 Call mrConfig C DIGALOG PROJECTS EXAMPLE MRU MRU INI Call mrBoot 0 Call mrWrite 0 1 amp H1000 amp HF
59. he given address If the product routine being downloaded is greater than 32 bytes the MRU will successively call this command until the entire product routine is downloaded The MRU will handle incrementing the address to download to for successive blocks of data being downloaded Therefore the monitor code can treat each call to the download command as a separate call and just download the given number of bytes to the given address The command returns a zero or an error Series 2040 Test System Page 47 MRU User Manual V1 5 Command 13 SetFCode Sets the read and function code lines Not all processors support function codes If the processor does not support function codes then the error number ERR UNSP COMMAND should be returned If the function codes are supported the primary address location will contain the read address and the secondary address location will contain the write address When finished the command returns a zero or an error Command 14 IrqEnable Enables or disables the processor s maskable interrupts Bit 0 of the FlagByte in the communication area is checked to see if interrupts are being enabled or disabled The bit is high if interrupts are being enabled and low if they are being disabled If interrupts are being enabled the monitor must execute any instructions needed to enable maskable interrupts The monitor must also initialize the exception number location set by the Load Stack Pointer functio
60. hecks the level of the ground connection which is coming from the MRU board The MRU s ground line is routed to SIG5 on the MRU Selftest board which is then routed to the AMS board The level of the MRU s ground is then measured and checked against a min and max value A Turbo Selftest Assembly is required Series 2040 Test System MRU User Manual V1 5 MRU_com_f Tests the MRU to Patchboard to Selftest connection Data is written serially to the MRU Selftest board which then directs it back to the MRU s logic analyzer Logic analyzer samples are then taken and then checked against the data that was written serially A Turbo Selftest Assembly is required MRU_id_f Tests the ability of the MRU to read an LFA s ID The MRU Selftest board is used in place of the LFA A Turbo Selftest Assembly is required MRU_tmsig_f Tests the functionality of the Trigger Matrix on the MRU board Each of the six inputs are verified that they can be connected to each of the six outputs on each of the eight Trigger Matrix busses It is verified that only one output has an output pulse for each test A Turbo Selftest Assembly is not required Logic Family Adapter Test In addition to the selftest routines fhe Cep included in the Selftest Executive Se Sei there is a program called Logic Family nn Adapter Test that can be used to test man wl L a a all se an LFA This utility allows the user to ALE pae test the ability of the MRU to
61. interrupt number just like in nonfatal ISR handling before returning the exception error Series 2040 Test System Page 35 MRU User Manual V1 5 Handling special considerations Since the configuration editor cannot account for every configurable option of every existing and future processor the monitor must be able to handle these special options These options are defined by the writer of the monitor and entered into the cpu file for the processor the monitor is being written for The first value that needs to be defined and entered is the Boot RAM address where the MRU firmware will place the parameters for the special considerations This address is assigned to the MONITOR PARAM ADDR entry within the IGENERAL section of the cpu file Care must be taken so the required data space for these parameters is not placed within the initialization code or the monitor itself Next to be entered is the name of each option and the number of bytes that each will occupy in the Boot RAM of MRU board 0 only The parameter names are entered under the section titled MONITOR PARAM NAMES in the cpu file This is an example of the Special Consideration additions needed to be made to the cpu file GENERAL MONITOR_PARAM_ADDR 0x3B00 MONITOR_PARAM_NAMES REGISTER VECTOR 2 RAM_VECTOR 2 In this example four bytes 2 bytes for each special consideration are re served at address 0x3B00 in the boot RAM space
62. irectory The Direct Execution mode enables the user to interactively execute any MRU functional call This mode provides direct immediate feedback to the user as an aid in troubleshooting the hardware interfacing and in streamlining the building process of each test program After a MRU functional call is entered into the single line text entry box at the bottom of the screen the results of its execution appear in the upper portion of the screen following the output of the previously executed functional call for the user to easily follow This history code can then be printed out to use as a reference for code development later on in the Visual BASIC programming environment Direct Execution File Edit Subroutine Macro mrReset 989 1 Adjusting the UUT reset state mnrLoad 9 1 amp HB Exanple Loading file data into memory arLfaDisconnect mrLfaDisconnect group It also features the ability to create and process macros which are short user definable names used to represent the MRU functional calls and includes their parameter lists These macros can be saved to a file and later retrieved Page 16 Series 2040 Test System MRU User Manual V1 5 Under the File menu option the choices for loading and saving macro files for printing out the history code Aa e z A g mBoot and for terminating this application are mrCall available mrConfig mrCopy Under the Edit menu option the ae choices f
63. is set Therefore the mrLogicModeEnable function must be given after this call to enable the logic analyzer Visual BASIC Declaration Public Sub mrLoadLogicMemoryAddr ByVal Group As Integer ByVal Address As Long Call mrLoadLogicMemoryAddr Group Address Where Group 0 to 15 The UUT s group number Address 0x0 to OxFFFF Valid logic analyzer memory address EXAMPLES Const UUT_GROUP 0 Set the logic analyzer s memory address counter to amp H100 Call mrLoadLogicMemoryAddr UUT_GROUP amp H100 amp Series 2040 Test System Page 65 MRU User Manual V1 5 mrLogicModeEnable Enables or disables the logic analyzer based on the value of the parameter Mode When disabled the logic analyzer cannot store samples When enabled the logic analyzer can store samples as long as the UUT is booted and the hardware is set up to clock the logic analyzer s memory from an internal signal external signal or one of the six asynchronous clocks available An alternative method of enabling the logic analyzer is to use a signal from the trigger matrix Signals from the trigger matrix have the ability to enable TMLogsStrt and disable TMLogStop the logic analyzer Visual BASIC Declaration Public Sub mrLogicModeEnable ByVal Group As Integer ByVal Mode As Integer Call mrLogicModeEnable Group Mode Where Group 0 to 15 The UUT s group number Mode 0 Disable the logic analyzer 1 Enable the logic analyze
64. ling the mrLoadStackPtr function Visual BASIC Declaration Public Sub mrCall RetData as Long ByVal Group As Integer ByVal CodeAddr As Long ByVal Timeout As Long Call mrCall RetData Group CodeAddr Timeout Where RetData Value returned from the product routine Group 0 to 15 The UUT s group number CodeAddr Any valid address in product routine RAM boot RAM or UUT RAM Timeout 0 Do not wait for return data 1 to 60000 Time in milliseconds to wait for the product routine to finish EXAMPLES Const DATA_SIZE 1 Byte wide data bus Const UUT_GROUP 0 Just one UUT Dim i As Integer burn in run counter variable Dim FileName As String Dim CfgFileName As String Dim RetData As Long configure the MRU boards for the current project CfgFileName C DIGALOG PROJECTS EXAMPLE MRU MRU INI Call mrConfig CfgFileName Series 2040 Test System Page 51 MRU User Manual V1 5 Load the raw binary burn in code into the UUT memory Call mrLoad UUT GROUP DATA _SIZE amp H00000100 amp FileName Call the routine for burn in 2 hours of 1 minute executions On Error GoTo BurnError Fori 1 To 2 60 Call mrCall RetData UUT_GROUP amp H00000100 amp 60000 If RetData lt gt NO_ERROR Then Error O invoke error handler Endlf Next i MsgBox GOOD Exit Sub BurnError MsgBox BAD Exit Sub Page 52 Series 2040 Test System MRU User Manual V1 5 mrConfig
65. ment Unit MRU Description The Memory Replacement Unit MRU board can replace the unit under test s UUT ROM space The user can then direct the MRU to test the operation of the UUT s microprocessor and any of its associated circuitry The MRU board has an embedded 32 bit Motorola MC68331 microcontroller The MC68331 has 256Kb ROM and 256Kb expandable to 1Mb RAM The MRU board also has 32Kb RAM of Program Routine Memory This is to facilitate the proper placement of the 2Kb program routine memory within the memory map of a low or high boot UUT processor The UUT has read write access to this memory This memory is used to store and execute user written programs that test the UUT at speed The UUT can also pass test data back to the MRU through this memory via the signal area resource These programs must be compiled in the UUT microprocessor s native language There also is 32Kb Boot RAM memory This is to facilitate the proper placement of the 4Kb boot memory within the memory map of a low or high boot UUT processor This memory is mapped into the UUT s boot space and replaces the UUT s boot ROM The monitor or user written routines can be loaded into this space and then executed by rebooting the UUT s microprocessor One advanced feature of the MRU is the Trigger Matrix The Trigger Matrix has five inputs and six outputs that can be connected to eight bus lines These bus lines are connected to other boards in the tester via t
66. mmand number from the communication area and check if it is within the range of valid commands It should then either report an error or jump to a routine to handle the command It must jump to the routine instead of executing any type of subroutine call that utilizes the stack because the UUT RAM may not have been tested yet This also requires all variable storage to be done in the UUT processor s registers or internal processor RAM if available Data is returned to the MRU through the signal area resource The protocol to do this is as follows 1 If an error is being returned set the error flag by doing a read access at the Error Flag offset 2 Wait for bit 7 of the tester status register to be a 1 This signifies that the previous signal value has been read by the MRU 3 Send the number of bytes being returned by doing a read access at corresponding offset in the signal area resource i e offset 1 for one byte offset 2 for two bytes etc 4 Wait for bit 7 of the tester status register to be a 1 This signifies that the byte count value has been read by the MRU 5 Send the value by doing a read access at the corresponding offset in the signal area resource i e offset 0 for value 0 offset 1 for value 1 or offset Oxff for value Oxff 6 If more than one byte is being sent repeat steps 4 amp 5 Page 44 Series 2040 Test System MRU User Manual V1 5 The following is a description of the commands that can
67. mrReset ByVal Group As Integer ByVal Action As Integer Call mrReset Group Action Where Group 0 to 15 The UUT s group number Action 1 Bring the UUT out of the reset state RELEASE 0 Toggle the reset line PULSE 1 Put the UUT into the reset state SUSPEND EXAMPLES Const UUT_GROUP 0 Const LONGWISE 4 Const RESET_PULSE 0 Dim FileName As String Load the file into the boot memory FileName C DIGALOG PROJECTS EXAMPLE MRU BOOT BIN Call mrLoad UUT _GROUP LONGWISE amp HO FileName Toggle the reset line to reset the UUT Call mrReset UUT_GROUP RESET_PULSE Page 76 Series 2040 Test System MRU User Manual V1 5 mrSelectLogicWts Selects one of the eight possible logic analyzer write strobes The selected write strobe is used to write the current UUT data address and control lines to the logic analyzer s memory on its falling edge and then increment the address counters to the next address Visual BASIC Declaration Public Sub mrSelectLogicWts ByVal Group As Integer ByVal Signal As Integer Call mrSelectLogicWts Group Signal Where Group 0 to 15 The UUT s group number Signal 0 Internal signal VROMCS or UWTS The internal write strobe is determined by the falling edge of UROMCS UBUSQUAL or by the rising edge of UWTS whichever occurs first This strobe saves the current address data and control signal levels into the logic analyzer memory 1 External signal
68. n with a number that is not a valid exception for this processor i e load the location with 256 if the maximum exception number is 255 This is done so the IRQNum function can determine if an interrupt has occurred will read a valid exception number or did not occur will read the invalid exception number The command returns a zero or an error Page 48 Series 2040 Test System MRU User Manual V1 5 MONITOR ERROR DEFINITIONS NO ERROR 0 ERR_UNSUP_ COMMAND 1 ERR CYCLE SIZE 2 ERR RAM VERIFY 3 ERR_EXCEPTION 4 ERR_PRA_NOT_AVAIL 5 ERR_DATA_CNT 6 ERR BLOCK SIZE 7 MRU FUNCTIONAL CALLS IN VISUAL BASIC Brief Summary mrBoot Load the monitor into the UUT boot memory and boot it mrCall Call a product routine previously loaded into UUT or MRU RAM mrConfig Configure the software and the MRU boards mrCopy Duplicate a section of UUT memory mrCRC Calculates a 16 bit cyclic redundancy check CRC value on a section of UUT RAM mrFill Fill a section of UUT memory with data mrin Read data from UUT I O space mrlrqEnable Enable the maskable UUT interrupts mrirqNum Get the first occurring UUT IRQ number since they were enabled mrJump Jump to a previously loaded product routine in UUT or MRU memory mrLfaDisconnect Disconnect the LFA pod from the UUT mrLoad Load binary data into UUT or MRU memory mrLoadImm Write immediate data to UUT or MRU memory mrLoadLogicMemoryAddr Set th
69. nO trigger matrix signal line 1 In1 trigger matrix signal line Timeout 0 Reset the possibly latched signal 1 to 60000 Time in milliseconds to wait for the low pulse EXAMPLES Const UUT GROUP 0 Const IN1 1 Wait up to 200 mS for a low pulse on the IN1 signal line Call mrWaitTrig UUT_GROUP IN1 200 amp Page 82 Series 2040 Test System MRU User Manual V1 5 mrWrite Writes the argument WriteData to the UUT s address Dest The write cycle can use bytes words or longwords Only the least significant DataSize bytes of WriteData are written If the FuncTrig trigger signal has been is enabled by using the mrTMTrigEn call then this command will produce a low pulse on the FuncTrig signal line connected to a preselected trigger matrix line just before the write cycle is executed Visual BASIC Declaration Public Sub mrWrite ByVal Group As Integer ByVal DataSize As Integer ByVal Dest As Long ByVal WriteData As Long Call mrWrite Group DataSize Dest WriteData Where Group 0 to 15 The UUT s group number DataSize 1 2 or 4 The size in bytes of the read write cycle to use Dest Any valid UUT address WriteData amp HO to amp HFFFFFFFE Data to be written depending on the size of the write cycle used EXAMPLES Const UUT GROUP 0 Const WORDWISE 2 Write an integer timing constant into a routine already present Call mrWrite UUT_GROUPWORDWISE amp HE346
70. nd booted Test execution results can be returned to the monitor in several ways The product routine can place a return value in one of the processor s registers The product routine then returns back to the monitor Next the monitor transfers the result back to the VB functional call The product routine also could place one or more return values in the UUT s RAM The approach used depends on the processor s architecture and the implementation of the monitor All Digalog written monitors are explicitly documented in this respect for the test engineer to easily write product routines that properly pass information back to the monitor upon their completion Series 2040 Test System Page 9 MRU User Manual V1 5 Using a Product Routine The product routine is downloaded to the product routine area using mrLoad All locations in the product routine area are acceptable for use except for the monitor communication area which exists in the topmost 64 ocations The product routine can be written to utilize parameters located in a non code area of the product routine area or in an accessible area of the UUT s RAM The VB test program uses mrLoadImm to load the parameters into the proper memory area The product routine is executed by calling mrJump or mrCall in the test program The mrCall causes the processor to save the address of the next monitor instruction to the stack and then begin executing the code at the given product routine st
71. nnel at one time If the selected input signal is already connected to a different TMBus channel the connection will be broken Passing a negative number for the Channel parameter will break the connection between the signal selected and the Trigger Matrix Bus The signal is selected by cross referencing the signal name to the number that represents it for that particular board type and then inserting it into the Sig parameter Visual BASIC Declaration Public Sub TMSetOut ByVal Channel As Integer ByVal Slot As Integer ByVal Sig As Integer Call TMSetOut Channel Slot Sig Where Channel 0 to 7 TMBus channel to connect disconnect to from Slot 1 to 23 The Testhead slot containing the board Sig 0 InOTrig 1 In Trig 2 UUTTrigIn 3 TMLogWTS 4 TMLogSTRT 5 TMLogSTOP These are the only Trigger Matrix output signals available on the MRU Board EXAMPLES Const BREAKIT 5 Channel 5 Slot 22 Sig 0 Call TMSetOut Channel Slot Sig connects outputsignal 0 of board in slot 22 ER EE E EEEE dirla E to TMBus channel 5 Call TMSetOut BREAKIT Slot Sig disconnects output signal 0 of board in slot 22 from E E shes cussdadoosdssesa EENS Ehe TMBus channel 5 Series 2040 Test System Page 27 MRU User Manual V1 5 ClearTM ClearTM breaks all input and output connections of every Testhead board from a specific Trigger Matrix Bus channel This function works well to clear the way for
72. nt patterns of data are sent to the LFA using the MRU s serial port The LFA then drives this data back to the MRU s Logic Analyzer The Logic Analyzer is then used to read the data The written and read data are then compared The results window shows each test result and the number of passes and failures are displayed The data patterns used are each bit in the 32 bit long data pattern are set high separately 0x00000000 and OxFFFFFFFF It should be noted that bits 14 and 15 0x0000C000 will always be high and bit 18 0x00040000 will always be low These three bits are not used on the Logic Analyzer LFA Data Read Test Tests the ability of the MRU board to drive the data lines to the LFA A known data byte is written to a given address within the MRU s Boot RAM This address is then serially written to the LFA The LFA latches the address and drives it back to the MRU board The LFA should now be able to read the data byte The LFA then latches this byte and the MRU reads it back using its serial port All 13 address lines used to address the MRU s Boot RAM are individually tested a total of 14 different addresses At each address each data bit is set high individually and tested a total of 9 different test patterns This adds up to a total of 126 separate tests The results window shows each test result and the number of passes and failures are displayed Series 2040 Test System MRU User Manual V1 5 HARDWARE Memory Replace
73. number and parameters in the communication area and then switches access to the UUT If the monitor attempts to access the area without Page 42 Series 2040 Test System MRU User Manual V1 5 permission it will not retrieve the correct data Bit 6 Monitor Program Space Access Flag MRU Boot RAM 0 UUT does not have access 1 UUT has access This bit is used to determine if the UUT can access the monitor program area RAM on the MRU board The MRU loads the monitor switches access to the UUT and resets the UUT to boot the monitor Bit 7 Signal Ready Flag O MRU has not read the latched signal value 1 MRU has read the latched signal value This bit is used to determine if the MRU has read the previous signal value Command Description The monitor program must handle the following set of commands Any commands that are unsupported for the processor must return the error code ERR_UNSUP_COMMAND Command Description Writes a location in the UUT I O space Series 2040 Test System Page 43 MRU User Manual V1 5 All commands must return a value to the MRU This value can be data as in a Read command a zero byte to signify success or a nonzero byte with the error flag set to signify an error Once the monitor has finished with any initializations it should enter a main loop where it checks bit 3 of the tester status register A value of 1 signifies that a command is in the communication area The monitor should get the co
74. oeloe ett t Z O Z SW1 5 through SW1 8 select the group number that the MRU board is a member of SW1 8 SW1 7 SW1 6 SWI 5 Group Number oo ZZ Note ON means the switch is closed o ofo o o ZIzIiz z z CC o oo on Jm Jom li jor Jon Jom j _ jor Jor for e jor jor fom 7 O Z Series 2040 Test System Page 89 MRU User Manual V1 5 JP1 JP2 Reserved Default setting JP2 only JP3 JP4 Reserved Default setting JP4 only JP5 Selects the size of the MRU s MC68331 boot ROM If the jumper is between pins 1 2 the size is 512K If the jumper is between pins 2 3 the size is 128K Default JP6 Selects the physical size of the MRU board s MC68331 RAM For 32 pin DIP chips jumper pins 1 2 For 28 pin DIP chips jumper pins 2 3 Default JP7 Reserved Default setting jumper pins 1 2 Connector Pin Definitions P1 Digital Motherboard Connector 1 NAME SIGNAL NAME SIGNAL NAME SIGNAL e fror je sores Jee les notusen po NOT USED NOT USED C7 NorusED B7 NOT USED NOT USED oes NOT USED A8 amp NOT USED NOT USED NOT USED NOT USED Page 90 Series 2040 Test System MRU User Manual V1 5 P2 Digital Motherboard Connector 2 NAME SIGNAL SIGNAL NAME SIGNAL ENC CC CN Cn er rorum e foso Je Songs foo Lo In porso fe Jr ir zi fes fas Nor use fas eme e orelelelele ZIZIZIZ Z OIII E IE Q S Q JE cs JI CEE jes es jer cs c Ja
75. om The command returns a zero or an error Command 8 Out Writes a byte to the I O space of the UUT processor The primary address specifies the location to write to Data value 1 specifies the value to write The command returns a zero or an error Command 9 LoadSP Loads the stack pointer register The stack address specifies the value to load into the stack register Bit 1 of the flag byte will be set by the MRU to signify that the stack is valid The monitor must then adjust the stack pointer to allocate enough storage to accommodate all of the possible exception numbers plus one For example if the processor is capable of generating 256 exceptions at least two bytes must be allocated for the exception number storage because the exception number must be initialized to an unused value e g 256 When the IRQNum command interrogates the monitor as to whether an exception has occurred or not the monitor will be able to compare the currently stored exception value to the unused value to determine if an exception has occurred The command returns a zero or an error Page 46 Series 2040 Test System MRU User Manual V1 5 Command 10 Jump Jumps to a product routine to start executing it The primary address specifies the address to jump to The product routine must jump back to the reply loop in the monitor The reply loop is the section of the monitor where data is returned to the MRU The starting address of the r
76. or removing copying inserting man and erasing selected sections of the miRQEnable entered functional call are available as mare I h g d mrJump well as the options to create delete mil faDisconnect and clear all macros mrLoad mrLoadimm A mrLoadStackPtr The Subroutine menu option lists all n u of the MRU functional calls to choose mPrReset from and presents the parameter list mRamTest mRead usage below the text field once a call dre has been chosen from the list The mReceive user can also enter the functional call miReset via the keyboard but no parameter eet list information will be provided In mrTMPulse this case the section on functional mrTMTrigEn calls in this manual will have to be WAR had mriWrite consulted Logic Analyzer LoadLogicM emoryAddr LogicM odeEnable The Macro menu option lists the ReadLogicdata SelectLogicWts available macros to choose from for SetLogicWisDelay immediate execution Logic Analyzer The Logic Analyzer utility graphically displays the signal levels KASE that were read by an MRU board s logic analyzer circuitry and SES saved to a log file If the system is configured for multiple MRU boards the signal levels from each MRU board are written to the same log file Since the MRU Logic Analyzer utility can only display eight data lines at a time in addition to the address and control lines to load a multiple MRU board log file it will invoke itself automaticall
77. programming Trigger Matrix connections to a TMBus channel of unknown status Visual BASIC Declaration Public Sub ClearTM ByVal Channel As Integer Call ClearTM Channel Where Channel 0 to 7 The TMBus channel to be cleared EXAMPLES Dim Channel As Integer Channel 0 Call ClearTM Channel ee clear all connections to TMBus channel 0 Page 28 Series 2040 Test System MRU User Manual V1 5 Trigger matrix interface controls and clocks Out 0 software generated trigger output created by MRU firmware from functional call mrTMPulse Out 1 software generated trigger output created by MRU firmware from functional call mrTMPulse FuncTrig software generated trigger output created by MRU firmware during execution of certain functional calls ResetTrig software generated trigger output created by MRU firmware during product reset UUTTrigOut product generated trigger output lasting one UUT bus cycle In 0 software monitored trigger input via functional call mrWaitTrig In 1 software monitored trigger input via functional call mrWaitTrig UUTTrigIn UUT monitored input trigger TMLogWTS Trigger Matrix input signal used to capture logic analyzer data samples TMLogSTRT Trigger Matrix input signal used to arm the logic analyzer TMLogSTOP Trigger Matrix input signal used to disarm the logic analyzer Series 2040 Test System Page 29 MRU User Manual V1 5 EXTERNAL CONTROL
78. r EXAMPLES Const UUT GROUP 0 Const ENABLE LOGIC_MODE 1 Enables the MRU s logic analyzer for group 0 Call mrLogicModeEnable UUT_GROUP ENABLE_LOGIC_MODE Page 66 Series 2040 Test System MRU User Manual V1 5 mrLoadStackPtr Initializes the UUT s stack pointer so that it can be used for product routine execution and interrupt handling The stack address is given by the parameter StackAddr and must be a valid UUT RAM address The RAM location given by StackAddr is actually reserved for storing an exception number for when interrupts have been enabled by using the mrIrqEnable command After being initialized to this address the stack pointer is offset by one or more address locations in order to set aside enough space to accommodate the largest possible exception number plus one This call must be executed before the command mrCall is used If the UUT does not have its own RAM this function cannot be used Visual BASIC Declaration Public Sub mrLoadStackPtr ByVal Group As Integer ByVal StackAddr As Long Call mrLoadStackPtr Group StackAddr Where Group 0 to 15 The UUT s group number StackAddr Any valid UUT RAM address location EXAMPLES Const UUT_GROUP 0 Initialize the UUT stack pointer Call mrLoadStackPtr UUT_GROUP amp H1050 amp Series 2040 Test System Page 67 MRU User Manual V1 5 mrOut Writes the parameter OutData to the address Dest in the UU
79. roperly fetch the data on a UUT with a 16 bit data bus the monitor needs to fetch each data byte separately using a byte wide operation and then concantenate the bytes together to form the proper value Thus the first byte is located at address MONITOR PARAM ADDR and the second at MONITOR PARAM ADDR 2 For a 32 bit data bus each byte is located 4 addresses away from the previous one The resources available to the monitor consist of the processor s registers 4K location boot ROM space 2K 64 location product routine area 256 location signal area resource and a 64 location communication area Al sizes are given in locations which is bytes if the data bus width is 8 bits words if the data bus width is 16 bits or long words if the data bus width is 32 bits NOTE Even though the communication area can be byte wide word wide or longword wide depending on the data bus width its data is stored contiguously in the boot RAM of MRU board 0 only To fetch a word using a word wide data bus requires two byte wide read operations specifying two addresses not adjacent to each other but having a difference of two For a longword wide architecture adjacent data bytes in the communication area have addresses that differ by four Thus the monitor must take the CPU s data bus architecture into account when retrieving words and long words from the communication area Series 2040 Test System Page 37 MRU User Manual V1 5 Offset map for a lo
80. roup As Integer Call mrLfaDisconnect Group Where Group 0 to 15 The UUT s group number EXAMPLES Const UUT_GROUP 0 Disable the LFA data lines between the UUT and the MRU boards Call mrLfaDisconnect UUT_GROUP Page 62 Series 2040 Test System MRU User Manual V1 5 mrLoad Loads the product routine or any binary data in the file FileName into UUT or MRU RAM beginning at the address Dest This call can be used to load code into boot RAM Product Routine RAM and UUT RAM If Dest specifies UUT RAM the various UUT write cycles can be sized according to the DataSize argument For product routine RAM and boot RAM the DataSize argument provides the size of the UUT s data bus This is needed so that the call knows how many MRU boards make up the data bus and how to write the product routine to the different MRU boards Visual BASIC Declaration Public Sub mrLoad ByVal Group As Integer ByVal DataSize As Integer ByVal Dest As Long ByVal FileName As String Call mrLoad Group DataSize Dest FileName Where Group 0 to 15 The UUT s group number DataSize 1 2 or 4 The size in bytes of the write cycle to use Dest Valid boot RAM product routine RAM or UUT RAM address FileName Full path to a valid binary file name EXAMPLES Const UUT GROUP 0 Const BYTEWISE 1 Dim RetData As Long Dim FileName As String Load the latest version of the firmware into the boot memory Fil
81. signals respectively in the golden file whose timebase index the mouse pointer is currently positioned over The Cycles to Shift field is used to specify how many cycles the sample data or golden data is to be shifted when the lt lt or gt gt command button associated with the Cycles to Shift field is selected The need to shift the sample data or golden data occurs when the two batches of samples do not start on the same cycle By shifting one of the sample sets both of the sample sets can be aligned to the same cycle When either of the sample sets are shifted up to the right the invalid signal state shown on the leftmost portion of the Logic Analyzer will not show up as being high or low Instead it will be Series 2040 Test System Page 19 MRU User Manual V1 5 displayed as being filled in The signal state is invalid because it is not an actual sample taken The Block information and manipulation controls are located below the Time field A block consists of 512 samples of the monitored signals Incrementing up and down through the blocks is performed using the gt gt and lt lt command buttons respectively The block index and the corresponding timebase index range for the currently visible waveform are also displayed The Logic Analyzer utility can be used to troubleshoot the boot up sequence of an uncommunicative product by enabling one of the asynchronous clock
82. tData Group DataSize Source NLocations Where RetData The return variable containing the CRC calculation Group 0 to 15 The UUT s group number DataSize 1 2 or 4 Size of the read cycle to use Source Valid UUT RAM address for the base address of the source data NLocations Valid number of UUT RAM locations for the given data bus width EXAMPLES Const UUT_GROUP 0 Const EACH BYTE 1 Dim ByteCRC As Integer Check 128 words two bytes each starting at 0x100 Call mrCRC ByteCRC UUT_GROUP EACH_BYTE amp H100 amp 256 amp Show the results MsgBox ByteCRC amp CStr ByteCRC Series 2040 Test System Page 55 MRU User Manual V1 5 mrFill Fills NLocations of UUT memory starting at the address Dest with the value FillData The type of write cycle to be used as indicated by the parameter DataSize determines how much of FillData is used A byte wide write cycle only uses the least significant byte If the FuncTrig trigger matrix signal has been enabled by using the mrTMTrigEn call then this command will produce a low pulse on the FuncTrig signal line connected to a preselected trigger matrix line just before the fill operation begins on the UUT Visual BASIC Declaration Public Sub mrFill ByVal Group As Integer ByVal DataSize As Integer ByVal Dest As Long ByVal FillData As Long ByVal NLocations As Long Call mrFill Group DataSize Dest FillData
83. te edentate 34 END EE E 34 Handling e EE 34 Handlmg special consideration i ui 36 Offset map for a low boot processor nnen 38 Offset map for a high boot processor nennen 38 Description of signal area resource vennen 39 ADDRESS OFFSET MAP of MRU as seen from UUT processor40 Low Boot Processor 8 bit data bus 40 High Boot Processor 8 bit data bus 40 Ree TE 41 Flag BAE enteren nt deeman 41 Exception Number Address ee 42 Jester Status Registers sonate eneen enen deed 42 Command Description 43 Monitor ERROR definitions ssisversivatiessectedsavtivasievtarecvnn taneveans 49 MRU Functional Calls in Visual BASIC 49 Brief SUMIMALY niente eenen 49 ROTTS OO neet E Ee 50 MICA 51 Kl cea 53 DER EEN ee ee 54 MERO sele Aa 55 DE rile 56 el natens heee sedens edna dsten 57 GERED Ra ea 58 idee Ier WE 59 898 RONA PERE OR RR E E A RARE IEEE 60 Hal PAL SCOMMOCE area 62 HNO WE 63 at BE aah eten AEN 64 Series 2040 Test System Page 3 MRU User Manual V1 5 D Etude 65 mrLogicModeEnable ninssnerendenee doden moed 66 mrkoadStackPtr sr eege 67 PRO UES Sansa leleine 68 IEE TRGB CU rn saatn eersel ban Vaden oid 69 mrRAMTESE onice 70 MIR riale 72 mrReadLFA D 73 mrReadLogicData nnen enk eene did 74 IRENE tn te daneen ire 75 RAK RESCE EE 76 IMISCICCILO RIM Saar 77 MS alia 78 ae rela 79 DEE aerden ene 80 RETIN
84. te is always assigned to MRU board 0 Finally the boot address is entered This is only used for cases where the boot space on a low boot processor has been re mapped to another location The location of the re mapped boot space is needed so the exception vectors within the monitor can be changed to their new location If a high boot processor is configured or the boot space is not re mapped this field should be zero If the product contains more than one processor then the Processors field will have to be incremented When this field is incremented another processor tab will appear next to the first one Proc 1 The new processor tab will then have to be selected and the configuration data for the new processor will have to be entered When all of the information has been entered the configuration file should be saved using either the Save or Save As operation under the File menu option MRU Selftest Executive The MRU Selftest Executive provides the means to functionally test all of the MRU boards in the Testhead For a description of the Selftest programs see the Selftest Programs section of this manual Page 22 Series 2040 Test System MRU User Manual V1 5 SETUP OF MRU PRIOR TO TESTING BOARD CONFIGURATION Board Number Each Memory Replacement Unit MRU Testhead board is responsible for 8 bits of data bus ROM emulation on a product Therefore if the product contains a sixteen
85. tialized bit 1 of the Flag Byte in the Communication Area will be set If the stack has not been initialized or there is no UUT RAM the ISR cannot return by way of a return from interrupt instruction because there is no valid return address In this case the ISR should just jump to the monitor s command loop and wait for the next instruction If the stack has been initialized the nonfatal ISR needs to Page 34 Series 2040 Test System MRU User Manual V1 5 check if interrupts are expected by the mrIrqEnable function ISRs are expected if bit 0 of the Flag Byte in the Communication Area is set If they are not expected the return from interrupt instruction should be executed If interrupts are expected the exception number needs to be stored at the UUT RAM address that is specified in the exception address location in the Communication Area see the description of the Communication Area below The exception number can then later be retrieved by the mrirqNum functional call Once the exception number has been stored the return from interrupt instruction can be executed to resume monitor or product routine execution Fatal interrupts need to be handled differently Since the state of the UUT cannot be guaranteed after a fatal interrupt the user should be notified of the fatal interrupt by returning the monitor s ERR_EXCEPTION error If the UUT s stack has been initialized the fatal ISR can save the
86. tual Then MsgBox UUT RAM Failed at amp CStr FailAddr End If Series 2040 Test System MRU User Manual V1 5 Page 71 MRU User Manual V1 5 mrRead Reads data from UUT memory at the address Address and returns the result in the return variable RetData using a read cycle corresponding to the data width DataSize If the FuncTrig trigger matrix signal has been is enabled by using the mrTMTrigEn call then this command will produce a low pulse on the FuncTrig signal line connected to a preselected trigger matrix line just before the read operation is executed Visual BASIC Declaration Public Sub mrRead RetData As Long ByVal Group As Integer ByVal DataSize As Integer ByVal Address As Long Call mrRead RetData Group DataSize Address Where RetData Return data read from UUT RAM boot Ram or Product Routine RAM Group 0 to 15 The UUT s group number DataSize 1 2 or 4 The size in bytes of the read cycle to use Address Valid UUT memory address EXAMPLES Const UUT GROUP 0 Const BYTEWISE 1 Dim DataByte As Long Find out what s in UUT RAM at address 0x3000 Call mrRead DataByte UUT_GROUP BYTEWISE amp H3000 amp MsgBox Address 0x3000 contains amp CStr DataByte Page 72 Series 2040 Test System MRU User Manual V1 5 mrReadLFAid Reads an LFA s ID The returned value is a byte wide value with the lower four bits representing the LFA s logic family type
87. uct routine return data only once before returning Visual BASIC Declaration Public Sub mrReceive RetData As Long ByVal Group As Integer ByVal DataSize As Integer ByVal Timeout As Long Call mrReceive RetData Group DataSize Timeout Where RetData Return value containing the data sent from the product routine Group 0 to 15 The UUT s group number DataSize 1 2 or 4 The size in bytes of the return data Timeout 0 Checks only once for data to be returned from the product routine 1 to 60000 Time in milliseconds to wait for the return data EXAMPLES Const UUT_GROUP 0 Const BYTEWISE 1 Const LONGWISE 4 Dim RetCode As Long Dim FileName As String FileName C DIGALOG PROJECTS EXAMPLE MRU QWIKTEST BIN Load and start the product routine but do not wait for return data Call mrLoad UUT_GROUP BYTEWISE amp HO amp FileName Call mrJump RetData UUT_GROUP amp H0 amp 0 amp Retrieve and display the return data Call mrReceive RetData UUT_GROUP LONGWISE 15000 amp MsgBox Return code amp CStr RetData Series 2040 Test System Page 75 MRU User Manual V1 5 mrReset Used to control the state of the UUT s reset line There are three ways to use this function One is to place the UUT into the reset state SUSPEND The second is to bring the UUT out of reset RELEASE The third is to perform a full reset by toggling the reset line PULSE Visual BASIC Declaration Public Sub
88. ur pin ground connection cable Page 94 Series 2040 Test System MRU User Manual V1 5 Connector pin outs P1 Interface Board Connector 1 SIGNAL PIN SIGNAL e e e ee fe feor p fe ro EEN CNE mo ps Series 2040 Test System Page 95 MRU User Manual V1 5 P2 Interface Board Connector 2 Se ROMCS PWTS 0 NXLOGSTOP a XLOGWTS XLOGWTS TESTMD BUSQUAL BUSQUAL ROMVCC Sense P3 Interface Board Connector 3 1 N C 2 N C 3 Ground 4 Ground Page 96 Series 2040 Test System MRU User Manual V1 5 Interface to Patchboard Connector PIN SIGNAL PIN SIGNAL TPB1 PDO BPBI PDO TPB2 PDI BPB2 PDI TPB3 PD2 BPB3 PD2 TPB4 PD3 BPB4 PD3 TPBS PD4 BPBS PD4 TPB6 PDS BPB6 PD5 TPB7 PD6 BPB7 PD6 TPB8 PD7 BPB8 PD7 TPB9 PAO BPB9 PAO TPB10 PAI BPB10 PAI TPBI1 PA2 BPB11 PA2 TPB12 PA3 BPB12 PA3 TPB13 PA4 BPB13 PA4 TPB14 PAS BPB14 PAS TPB15 PAG BPB15 PA6 TPB16 PA7 BPB16 PA7 TPB17 PA8 BPB17 PA8 TPB18 PA9 BPB18 PA9 TPB19 PA10 BPB19 PA10 TPB20 PAII BPB20 PAII TPB21 PA12 BPB21 PA12 TPB22 PA13 PA13 TPB23 SDATAOUT SCLK TPB24 ROMCS ROMCS TPB25 PWTS PWTS TPB26 ROMOE BPB26 ROMOE TPB27 PODSENSE BPB27 PRESET TPB28 TESTMD BPB28 RESETLVL TPB29 NRESETMD BPB29 XPRNTMD TPB30 NLOGSTRT BPB30 NLOGSTOP TPB31 XLOGWTS BPB31 XLOGWTS TPB32 BUSQUAL BPB32 GND TPB33 BUSQUAL BPB33 GND ROMVCC Sense TPB34 BPB34 SDATAIN Series
89. us register is given in the Address Offset Map of MRU as seen from UUT Processor section of this manual The TMLogWTS line is connected to the logic analyzer memory and is used as a clock to capture the state of the address control and data lines connected to the UUT boot ROM socket The TMLogSTRT and TMLogSTOP lines are connected to the enable logic of the logic analyzer memory and are used to start and stop capturing of the address control and data lines connected to the UUT boot ROM socket Series 2040 Test System Page 13 MRU User Manual V1 5 OVERVIEW OF MRUMAN S PROJECT UTILITIES The MRUMAN program provides a starting point for project US development It also serves as a launch pad for the Tester Resources Manager the Direct Execution mode the MRU MRUMAN Logic Analyzer utility the MRU Configuration editor the Visual Basic program development environment and the MRU Selftest Executive When the program is executed the screen to the right is displayed showing the projects available in the Digalog Projects directory If none of the projects File Project Help in this directory is a MRU project an appropriate message box is displayed File Menu The MRUMAN File menu contains selections to Create a project Delete a project Reread the project list or Exit the program An existing project can only be selected by clicking on it with the mouse If the project directory selected does not contain a
90. utines are useful for doing tests that must run at the full speed of the UUT processor and for testing large sections of memory which would otherwise require a lot of time just to transfer data between the tester and the monitor The product routines can be written in C if there is accessible tested and sufficient read write memory for the stack because C language routines require the use of a valid stack pointer The MRU system itself provides approximately 2K of product routine memory space Larger product routines will have to be downloaded into UUT read write memory The product routine area is provided for product routines to be downloaded into and executed from This area is 2K locations in size where the size of each location is determined by the bus size of the boot ROM space For example on an 8 bit bus there are 2K bytes and on a 16 bit bus there are 2K words or Ak bytes Sixty four 64 locations at the top of the product routine area are reserved for passing commands and parameters to the monitor Product routines can also be downloaded to the UUT s RAM This allows the use of larger product routines limited only by the size of the UUT RAM However this memory must first be tested to assure proper code execution In addition the product routines can be downloaded into the monitor space thereby overwriting the monitor This is not recommended since none of the monitor functions will be available until the monitor is reloaded a
91. via the Patchboard 20 nS asynchronous clock 40 nS asynchronous clock 80 nS asynchronous clock 100 nS asynchronous clock 200 nS asynchronous clock 7 400 nS asynchronous clock NOTE 1 Ifthe Internal Signal mode is selected and the signal UROMCS does not toggle at the end of each successive ROM addressed read cycle then another read cycle only UUT low active signal which does toggle at the end of each cycle must be connected to the UBUSQUAL pin to produce the necessary falling edge Il DUI ES WN NOTE 2 The actual clocking signal driving the logic analyzer is derived from the leading falling edge of the UROMCS UBUSQUAL signal or from the trailing rising edge of the UWTS signal whichever comes first It is recommended that the UWTS signal be active only during ROM based ACCESSES EXAMPLES Const UUT_GROUP 0 Route the UUT s own ROM chip select line to clock the samples into the logic analyzer s memory Call mrSelectLogicWts UUT_GROUP O Series 2040 Test System Page 77 MRU User Manual V1 5 mrSend Writes the least significant 3 bits of the parameter DataNibble to the least significant 3 bits of the UUT status register Since product routines can read this register this can be useful for conveying information to a currently executing product routine which may be awaiting additional information from the test program Visual BASIC Declaration Public Sub mrSend ByVal Group As Integer
92. w boot processor Offset Section EN EN CE 0x1000 2K Product Routine Area EN En Offset map for a high boot processor Offset Section seg Jer Ser EN EE NOTE The offset of 0 is actually 8K below the top of memory The MRU board maps into an 8K location region of the boot ROM space The 8K region is located either at the top of memory or at the bottom depend ing on whether the UUT processor boots from high or low memory The monitor has a 4K location space allocated to it out of the 8K region This 4K space holds the initialization code the monitor code various startup param eters and the vector table The remaining 4K space of the 8K region is mapped into a 2K location prod uct routine area a 256 location signal area resource a 256 location flag area and an MRU status register The MRU uses the top 64 address locations in the product routine area to pass commands and parameters to the monitor The Page 38 Series 2040 Test System MRU User Manual V1 5 256 location signal area resource is used by the monitor to pass values back to the firmware The 256 location flag area is used to trigger events on the trigger matrix bus and signal errors to the MRU The MRU status register is used to inform the monitor that a command is in the communication area and that the MRU has released its control of the product routine area for the monitor to now be able to fetch its next instruction Description of signal ar
93. x line just before the copy operation is executed Visual BASIC Declaration Public Sub mrCopy ByVal Group As Integer ByVal DataSize As Integer ByVal Source As Long ByVal Dest As Long ByVal NLocations As Long Call mrCopy Group DataSize Source Dest NLocations Where Group 0 to 15 The UUT s group number DataSize 1 2 4 The size in bytes of the read write cycle to use Source Any valid UUT RAM address for the base address of the source data Dest Any valid UUT RAM address for the base address of the destination data NLocations Valid number of UUT RAM locations for the given data bus width EXAMPLES Const UUT_GROUP 0 Const BYTEWISE 1 Const WORDWISE 2 Copy 128 words from 0x100 to 0x400 Call mrCopy UUT_GROUP WORDWISE amp H100 amp amp H400 amp 128 amp Copy 128 bytes from 0x600 to 0x800 Call mrCopy UUT_GROUP BYTEWISE amp H600 amp amp H800 amp 128 amp Page 54 Series 2040 Test System MRU User Manual V1 5 mrCRC Calculates a 16 bit cyclic redundancy check CRC value by using the CRC 16 polynomial with a divisor of X Si X 1 starting at the address Source and continuing for NLocations The read address is incremented by DataSize bytes for each appropriately sized read cycle Visual BASIC Declaration Public Sub mrCRC RetData As Integer ByVal Group As Integer ByVal DataSize As Integer ByVal Source As Long ByVal NLocations As Long Call mrCRC Re
94. y and repeatedly to show all of the data Series 2040 Test System Page 17 MRU User Manual V1 5 lines For example when a 16 bit product is monitored there will be two MRU Logic Analyzer utilities with one displaying DO D7 and the other D8 D15 The address and control signals display the same values in each utility invocation The control signals that are monitored consist of Name Description ROM CS The ROM chip select ROM OE The ROM output enable PRESET Product Reset controlled by MRU This utility also features golden log file comparison and hexadecimal representation of the data and address lines It also continuously updates the information fields displaying the signal name the signal levels and the time index to reflect the current position of the mouse pointer within each log file Logic Analyzer File Golden Help Timebase Signal _Ext Log Start Cycles to Shift H Time Sample data address _3FFF In Block H Golden data L address IT lt p gt Ip Samples Ons gt 204 4 us Bus Qualify Ext Log Stop The actions listed under the File menu option operate on the user selectable sample log file which is plotted in red upon being loaded The actions listed under the Golden menu option operate on the user selectable Page 18 Series 2040 Test System MRU User Manual V1 5 golden log file which is plotted in blue upon being loaded The
95. y either automatically interrogating the tester for its resources or by asking the programmer to define the tester s resources When the configuration is performed manually it allows the programmer to configure additional resources beyond what the tester physically contains In this manner a programmer has the additional resources and dialogs to generate programs and fixtures for any tester Tester Resource MANager c digalog include resource ini File Options Help Pond Adie didi ker ker ag oe kee bus ha ken GM oe ech Row 3 NEGO beer Gau GE Daz GC TIN RO MET nnn 617 28 2 Gi SCH a oat ein Di HL Ar gi 0A3 AGND DAG AGND DA18 ba prs Den Posi S01 A3 JAGND AGND paz JW AT AGND Dam eere moete he am Ro Mo mow I0 NEGT MU GH GH SE Row 13 POS GC Ser GC DA23 SEI EE Ska bere E Row 15 NEG2 Me il ee be fan pp _ SEH Row17 IL Me ve e beet se s ILR pa EN CC Jai vo Iran Series 2040 Test System Page 15 MRU User Manual V1 5 Direct Execution Located under the Project menu The Direct execution utility Direct provides direct execution of MRU functional calls functional call Execution parameter list examples drop down menu access to functional calls and macro definition and execution capabilities When invoked by MRUMAN Direct Execution accepts the path to the currently selected MRU project All macros developed will then be saved in the projects MRU subd
96. ystem Page 6 MRU User Manual V1 5 SOFTWARE DESCRIPTION OF THE DEVELOPMENT CYCLE The development cycle starts with determining how the UUT can be tested with the MRU system The MRU requires the following conditions e The processor can boot from external ROM e The boot ROM chips are at least 8K bytes e The ROM access time is greater than 100 nanoseconds e Any ROM memory caching can be disabled e The boot ROM data path is less than or equal to 64 bits Data fetches are allowed from boot ROM space e The boot ROM can be removed or disabled The test engineer must first determine if the processor on the UUT is supported by the MRU system If the processor is not supported a custom monitor will need to be written See the section on how to write a monitor The number of MRU boards needed must then be determined Each 8 bits of the boot ROM data bus will require an MRU board Next the test engineer must determine how the MRU system will be connected to the UUT There are generally two ways of connecting to the UUT The first method involves removing the boot ROM chips and plugging the MRU cables into the boot ROM sockets The second method uses a bed of nails fixture with wire wrapping of the connections If the second approach is used the boot ROM chips do not have to be removed if they can be either disabled or re mapped to another location in the processor memory space before boot up In addition to the connection method t

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