Home

View/Open - Calhoun: The NPS

1. 4 eee eeeee cesso seses seo to east so stas ene enean ene sn asas en atae 20 LSPECHICA OS ii Tc M Isi 29 PA Vir iiri OA eem E M 29 D MASTER SLAVE PARALLELING cciinnsicincn sinaloa irlanda 33 PENCON AAA nn A AN 33 No e etr 35 Y nip A ae eesoaues 37 VC PROGRAMMING ISSUE Sinn cia 39 A INTRODUCTION ins is 39 B C INTERFACE REQUIREMENTS sishsccscatesiscesccstseictassstiatasdescocsststcesentessssesdesteves edvsbacsedsicescassesnsbaccuseosas 40 C PROBLEMS WITH IMPLEMENTATION IN EXISTING CODE occcccconacornonconccnnononneracacconcacosananonas 41 VLARCEP CONTRO rr A A aa 45 A BASIC ARCP INVERTER OPERATION cssscssssssscscessosssssossosersesnasssscesnssacsessncacssncsecssceccascesssscaseas 45 B OPEN LOOF CONTRO Lin uiae eh cb pa DAE RE RIO ROS SE Eve eER pEe Boc I verha REI E aer ONE va ceni in ent 46 C CLOSED LOOP CONTRO L iiieeseesesssas xetotd qievehbesius ete tius a iia 51 iN ig er ivdestasstnvecanceade E EAA E AEA EEEE EE E AES 51 ZAPNE NON id 54 VILCONCEUS ON Si ca 55 A SUMMARY OF RESEARCH WORK c sccsssssssssesssssssonsssecsenscnscncseccesssnssssocesssnccansensosnscsansencseseess 55 B NOTABLE CONCLUSIONS siria ri eeen Da eaae da dora ERA o ERE E Ea Ca BERN Pe PEE e HEU 56 C RECOMMENDATIONS FOR FUTURE WORK sssosscssssssscnsscnsenssssscensssnsssntesnsonsenecsnsenssensssnesoscons 56 APPENDIX A SOFTWARE ACCESS AND DOS COMMANDS ccsccsssssssssese
2. UPDATE SLAVE DUTY CYCLE 2 444 44444 44 k FF EX LDF AR3 d R4 R4 Dss d1 gt master dutycycle ADDF AR3 Vd inta R4 RA Dss dl Vd int LDF AR3 tms oaci RO RO kp GUI value oaci MPYF AR3 Vdiffa RO RO kp iomaster ioslave ADDF RO R4 R4 Dss d1 Vdint kp i0master 1oslave T Master Duty integ ki io err kp io err EN Limit the duty cycle HiLim0 CMPF max R4 BLE LoLim0 LDF max R4 LoLim0 CMPF min R4 BGT Samed LDF min R4 Same0 NOP LDI AR3 tms_swp R7 FLOAT R7 MPYF R7 R4 SUBF R4 R7 R7 duty tms swp R4 tms_swp Ss Here R7 1 d to compensate for the PEBB EPLD inversion 86 FIX R7 paran Write the Slave Duty to B phase CTC S1 o kk kkk LDI Oct phaseb ARO Pointer for phase B counter STI R7 ARO 2 Store LSB of counter 2 LSH 08H R7 f STI R7 AR0 2 Store MSB of counter 2 eT E ER a a RA ACERA Overtem undervoltage protection L R_sw Gen I O word bit0 overtemp slave bitl overtemp master bit2 control voltage slave bit3 control voltage master LDI d output ARO set pointer to Gen I O STI ARO RO RO gen_I O word AND 000fH RO smask all but 4 Isbs LDI cmd_ad R4 Jump target if needed for shutdown CMPI OfH RO see if word is good BNE R4 Shuts down Bucks ENEE FERRE NOR NORIORUE OE ORO IOIOIOOR RETEST SE GEOE EOIGOIOIOIOE IOR SER ORG ESTE RES POP ARO POPF RO POP RO POPF RI POP RI f POPF R2 POP R2 POPF R3 POP R3
3. NAVAL POSTGRADUATE SCHOOL MONTEREY CALIFORNIA THESIS USING THE PEBB UNIVERSAL CONTROLLER TO MODIFY CONTROL ALGORITHMS FOR DC TO DC CONVERTERS AND IMPLEMENT CLOSED LOOP CONTROL OF ARCP INVERTERS by David L Floodeen September 1998 Thesis Co Advisors John G Ciezki Robert W Ashton Approved for public release distribution is unlimited DTIC QUALITY INSPECTED 4 80 11 18601 REPORT DOCUMENTATION PAGE Public reporting burden for this collection of information is estimated to average 1 hour per response including the time for reviewing instruction searching existing data sources gathering and maintaining the data needed and completing and reviewing the collection of information Send comments regarding this burden estimate or any other aspect of this collection of information including suggestions for reducing this burden to Washington Headquarters Services Directorate for Information Operations and Reports 1215 Jefferson Davis Highway Suite 1204 Arlington VA 22202 4302 and to the Office of Management and Budget Paperwork Reduction Project 0704 0188 Washington DC 20503 l AGENCY USE ONLY Leave blank 2 REPORT DATE 3 REPORT TYPE AND DATES COVERED September 1998 Master s Thesis 4 TITLE AND SUBTITLE USING THE PEBB UNIVERSAL CONTROLLER TO 5 FUNDING NUMBERS MODIFY CONTROL ALGORITHMS FOR DC TO DC CONVERTERS AND IMPLEMENT CLOSED LOOP CONTROL OF ARCP INVERTERS 6 AUTHOR S David L F
4. init LDI 0 DP Point the DP register to page 0 LDI 00H ST Clear and enable cache and disable OVM 1800h LDI 0000H IE Clear all interrupts LDI ctrl ARO Load peripheral bus memory mapped reg LDI xbus RO STI R0 AR0 60H Init expansion bus control reg LDI g pbus RO STI RO ARO 64H _ Init primary bus control reg LDI stck SP Initialize the stack pointer CALL init_ct Init counter timer LDI d output ARO LDI 00FFH RO i STI RO ARO LDI Act port ARO Pointer for counter timer control register LDI greset out RO STI RO ARO Disable all output 97 LDI QctlARO LDI Oblk1 AR3 Sratch pad memory area LDI dp mem ARA Top of dual port memory LDI ObIk0 ARS Sratch pad memory area LDI sram AR7 Top of the look up table LDI dp_cint IRO Clear dual port memory interrupt LDI AR4 IRO RO LDI 000H R0 Clear sram memory RPTS 2047 STI RO AR4 1 LDI gdp mem ARA Top of dual port memory LDI 0000H IF Clear all flags LDI 0008H IE Enable interrupt 3 dual port memory OR 02000H ST Global interrupt enable begin NOP NOP NOP BR begin read cmd LDI AR4 1 RO Check command AND 00FFH RO Clear all other bits CMPI 01EH RO BHS stopinit Ignore command if command 23 LDI cmd adjRl ADDI RI RO BNZ R0 stopinit RETS i x startcemd BR cmdO Off BR cmd Test Mode ARCP CONTROL BR cmdO AC to DC control BR cmdO Motor Control
5. POPF R4 a POP R4 POPF R5 POP R5 POPF R6 POP R6 POPF R7 POP R7 POP IRI POP ST gt ANDN mask intO IF Clear interrupt 0 RETI Return and enable interrupt LY NN EN AENA ej gt ee e rr a ee ee E er M ee ee e ET A Ee EE Tiel SSAA A Se IPod t eee isr1 SSCM MASTER UNIT interrupt service rountine BOOT Sect isrl 7 BOOT Named Section isrl NOP 3 EPROM ANDN mask intl IF Clear interrupt 1 RETI Return and enable interrupt nini ma OR CPE TE SS SP Rl AEG SS A isr2 Phase C interrupt service rountine BOOT Sect isr2 BOOT Named Section isr2 NOP 3 EPROM 87 ANDN mask_int2 1F Clear interrupt 2 RETI Not Used M MM i i is nt a M P T rn M P M e T MX M M e AP ee ee ee irs3 Dual port memory interrupt service rountine ak BOOT sect isr3 z BOOT Named Section isr3 NOP EPROM PUSH ST Save registers PUSH DP PUSH IRI PUSH R7 PUSHF R7 PUSH R6 PUSHF R6 PUSH R5 PUSHF R5 PUSH R4 PUSHF R4 PUSH R3 PUSHF R3 PUSH R2 1 PUSHF R2 PUSH RI PUSHF R1 PUSH RO PUSHF RO LDI gdp cintIRO LDI AR4 IRO RO Clear interrupt CALL read cmd ANDN mask_int3 IF Clear interrupt 3 POPF RO a POP RO POPF Rl POP RI P
6. Controller Memory DSP i 32K X 32 SRAM i i l l i I a e u s u A O A ee UU O O O s mo ee A o um a oJ e Local Display 8 1MUX UO OO 00D CO CO QU O OO O a a m a D e e e D A E A AX A E A i AMA GUA AO GARE D AGER IA E GU iia rs c eum ia dli HERES D FARA HRSG dejen cilium O A RH Gia KE A Prim aet Figure 2 1 PEBB Universal Controller Block Diagram Ref 5 Input to the Universal Controller comes from a host PC using the RS232 serial port on the back of the PC Output from the Universal Controller is converted to optical gate control signals by optical transmitters on the I O board These signals are then sent out as control signals to modify switch operation This provides a level of isolation between the Universal Controller and the high power units being controlled C PRIMARY COMPONENTS 1 CPU Board The CPU board is built around the Texas Instrument TMS320C30 which as stated earlier is discussed in the next chapter The microprocessor is supported by the Texas Instrument TI 8751 microcontroller and a memory section Figure 2 2 shows the primary components of the Universal Controller CPU board microcontroller dual port memory TMS320C30 Figure 2 2 CPU Board of the Universal Controller Ref 3 The microcontroller is able to communicate both in serial or parallel modes Any one of its 32 I O pins can be addressed as an input an o
7. Forward BR cmd0 Motor Control Reverse BR cmdO Actuator Control Open BR cmdO Actuator Control Close BR cmd Actuator Control Open BR cmdO Actuator Control Close BR cmdO DC to DC Boost BR cmd0 AC to DC Control BR cmdO BR cmd0 BR cmdO BR cmdO BR cmdO BR cmdO BR cmd0 BR cmd0 BR cmd0 98 BR cmdO BR cmdO BR cmd0 j BR cmd0 BR cmdO BR cmd0 BR cmd0 Stepx BR cmd0 AC output voltage BR cmdO Boost time BR cmd0 Set current boost limit BR cmd0 BR cmdO RETS Turning off ARCP cmdo0 LDI 08H IE Disable interrupts 0 1 2 LDI ct_port ARO Pointer for counter timer control register LDI clear_main RO STI RO ARO Disable all output STI RO AR3 tms_outputb LDI 030H RO wait20 SUBIOIH RO BNZ wait20 LDI greset out RO STI RO ARO Disable all counter timer output CALL init ct LDI 00H RO STI RO AR4 1 LDI dp intIRO STI RO ARA IRO LDI d output ARO LDI OFFFH RO STI RO ARO LDI gct port ARO Pointer for counter timer control register LDI greset out RO STI RO ARO Disable all output RETS Test Mode cmdi LDI OSH IE Disable interrupts 0 1 2 LDI Act port ARO Pointer for counter timer control register LDI clear main RO STI RO ARO Disable all output LDI 030H RO waitl1 SUBI O1H RO BNZ waitll i LDI greset out RO STI RO ARO Disable
8. data sram word 0080000H Beginning address of SRAM bikO word 0809800H Beginning address of RAM block 0 bik1 word 0809C00H Beginning address of RAM block 1 stck word 0809F00H __ Beginning of stack ctrl word 0808000H Pointer for peripheral bus memory map xbus word 0000048H Xpansion bus 2 wait states external RDY not in use 88 pbus word 0000428H Primary bus 1M bank compare 1 wait states external RDY not in use timOctl word 00003CIH Internal timer 0 1111000001 301 1100000001 timOprd word 0000064H 40Hl 10us timlctl word 00003C1H Internal timer 1 1111000001 301 1100000001 timiprd word 0004E20H 40H1 2ms wait4t word 0000100H dp mem word 0100000H Pointer for dual port memory command reg dp int word 00003FEH Pointer for setting interrupt flag dp cint word 00003FFH Pointer for clearing interrupt flag 93 dp cmd set dp oaci set dp acv set dp bdly set dp btime set dp dci set dp odci set dp dcv set dp dt set dp of set dp swf set dp aci set dp blk set dp acs set dp dcs set dp step set dp delay set dp swp set dp stepx set dp ta set dp tb set dp kc set dp kcb set dp bt set dp bi set dp mode set 0000032H tms cmd set tms oaci set tms acv set tms bdly set tms btime set tms dci set tms odci set tms dcv set tms dt set tms of set tms swf set tms aci set tms blk set tms acs set tms dcs
9. The file may now be changed as desired The arrow keys on the keyboard will move the cursor Any command that is present may be changed or any executable DOS command can be added to or deleted from the file For instance npsbuck asm located in the first line of the batch file could be changed to a different filename thus allowing different assembly language files to be assembled During the course of this research it became helpful to write program code on a different computer save the file on a floppy disk and assemble the code as discussed in Reference 3 In DOS the a drive is usually the floppy disk drive To access this drive the command a is used This command can be used in conjunction with other commands to add flexibility to the batch file For instance if line one of npsbuck bat is changed to read asm30 a npsbuck asm c l q The assembler will now assemble the program npsbuck asm that is located on the floppy disk in the a drive Another example using the a command is to add the line copy npsbuck out a to the bottom of the batch file npsbuck bat This would copy the output file created by the assembler linker to the floppy disk located in drive a 63 The a command can be used outside of a batch file as well C DSPTOOLS gt copy a npsbuck asm This command will copy the file named npsbuck asm from the floppy disk in drive a to the current working sub directory dsptools Know
10. Variables Y Iste Y Y O O es es Pointer Regist r Variables Table 5 1 Register Use and Preservation Conventions Ref 9 This table shows the convention that must be followed when interfacing assembly language modules into C code According to Reference 9 the called function is 41 responsible for preserving the contents of any used registers In other words when C code calls an assembly language function the called assembly language function is responsible for saving and restoring any uen it modifies Reference 9 further states that the C compiler must be free to modify registers as needed to accomplish program requirements which means that the compiler will choose which registers to save and restore based on Table 5 1 This issue is at the heart of the programming dilemma Instead of inserting assembly functions into C code the previously stated programming plan intended to insert C code functions into an existing assembly language program The problem this created is explained shortly To further aggravate the situation the register convention of the assembly code does NOT follow that stated by Reference 9 For example C code uses AR3 as the frame pointer for the program code but AR3 is used as a pointer to scratch pad memory and not the current working frame in the assembly code Also the assembly code uses general registers RO R7 for all types of uses not just those specified by Table 5 1 The problems cr
11. ct port init ct cmd10 isr_mode cmd1 ct phasea word 0804200H __ Phase A timer ct phaseb word 0804300H _ Phase B timer init_ct init_swct isrl ct_phasec word 0804400H Phase C timer init_ct init_swct isr2 d output word 0804500H General purpurse D O port init cmd1 d input word 0804600H General purpurse digital input port inputcs word 0804900H Input voltage and current ADC init acs word 0804a00H Phase a output V amp I ADC isrl isr2 bcs word 0804b00H Phase b output V amp I ADC isrO isr2 ccs word 0804c00H Phase c output V amp I ADC isr0 isr1 dac 1 word 0804700H Digital to Analog converter 1 dac 2 word 0804800H Digital to Analog converter 2 cmd ad int startcmd read cmd mode ad int mode cmd x isr_mode mask intO set 0000001H J Setexternal interrupt 0 isrO mask intl set 0000002H Setexternal interrupt 1 isr1 mask int2 set 0000004H Set external interrupt 2 isr2 78 mask int3 set mask timerO set 0000100H mask timerl set 0000200H mask dac set clear main word 0004444H reset out word O00ffffH 0000008H 0000800H Set external interrupt 3 isr3 Set internal timer 0 interrupt Set internal timer 1 interrupt allow 2 s comp numbers in dac cmd10 isr_mode cmd1 init cmd10 isr_mode cmd1 Define default values L R_sw oaci word 300 acv word 120 bdly word 10 btime word 4 dci word 10 odci word 200 Vref word
12. the program waits for an interrupt from the host PC When the interrupt interrupt 3 is received the control values are loaded in from the PC the Universal Controller initialization is completed and the program waits for phase interrupts to start controlling the system When not processing an interrupt the program is in a No Operation NOP loop waiting for the next interrupt It continues this operation until it receives an interrupt from the PC to shut down the system This defines remote operation For local operation the Universal Controller reads the reference voltage from the front panel potentiometers uses this Vref to calculate the changes to the duty cycle and therefore control the system In order to start up the system in Local mode a table of default control values had to be loaded into memory Then when starting up in Local mode this table would be read instead of the control values from the host PC As previously mentioned switching from one mode to the other needed to cause a shut down of the system and a restart in the proper mode Now that the modes of operation have been defined the algorithm dictating how the Universal Controller monitors the L R switch position and transitions between modes must be discussed It was determined that the interrupt decae of the control program would have to be changed The Universal controller needed to check the L R switch position on initial power up and monitor 1ts position throughout the
13. AND iL master MSB 82 LDI LDI LDI LDI LDI NOP iL slave MSB NOP LDI LDI LDI LDI LDI NOP AR3 AR7 READ io slave LSB AND io master MSB NOP NOP dolo Drocess and Accumulate Data AR4 R6 A2Dfltr R6 R7 R6 Vinput LSB R7 iL_slave MSB ADDF R6 RO RO Vinput 2 ARS R6 A2Dfltr R6 R7 R67 Voutput LSB R7 io slave MSB ADDF R6 R1 RI Voutput 2 AR6 R6 A2Dfltr R6 R7 R6 iL_slave LSB R7 iL master MSB ADDF R6 R2 R2 iL slave 2 ADDF R7 R3 R3 iL_master 1 AR7 R6 A2Dfltr R6 R7 R6 io_slave LSB R7 io master MSB ADDF R6 R4 R4 iout slave 2 ADDF R7 R5 R5 jout master 1 sk ok ok ok oc ok ok oe ale ok ode ale ale ok o ale ale ok ok ale ale ok ok ok ok ok ale ok oe ok ok oe ok ale ok oe ok ade ok ae oc ok ade ke ok oe ale ade ok ade ok oe ok ok ale ade ok oe EEE EE E EE E E E EE E EE LDI ARO AR4 READ Vinput LSB AND NOP NOP LDI ARI AR5 READ Voutput LSB AND io slave MSB NOP LDI AR2 AR6 READ iL_slave LSB AND iL_master MSB NOP NOP AR3 AR7 READ io slave LSB AND io master MSB NOP NOP Jaiak Process and Accumulate Data AR4 R6 A2Dfltr R6 R7 R6 Vinput LSB R7 iL_slave MSB ADDF R6 RO RO Vinput 2 ARS R6 A2Dfltr R6 R7 R6 Voutput LSB R7 io slave MSB ADDF R6 R1 R1 Voutput 2 AR6 R6 A2Dfltr R6 R7 R6 iL slave LSB R7 iL master MSB ADDF R6 R2 R2 iL slave 2 ADDF R7 R3 R3 iL_master 1 ART R6 A2Dfl
14. ARO D RO AND O000FFH RO Clear all other higher bits LDI ARO D R1 LSH 0008H R1 AND 00f00H R1 a OR RLRO CMPI R2 R0 BGT checkout LDI AR3 tms_swp RO STI RO ARO 2 Store LSB of counter 2 LSH 0008H RO STI RO ARO 2 Store MSB of counter 2 LDI gct phasea ARO Pointer for phase a counter LDI AR3 tms btime R1 STI R1 ARO 0 Store LSB of counter 0 LDI AR3 tms_bdly R1 ADDI AR3 tms_btime R1 STI R1 ARO 1 Store LSB of counter 1 LDI AR3 tms ta RI SII RL ARO 2 Store LSB of counter 2 LSH 08H R1 STI R1 ARO 2 Store MSB of counter 2 LDI gct phaseb ARO Pointer for phase b counter LDI AR3 tms_btime R1 STI R1 ARO 0 Store LSB of counter 0 LDI AR3 tms_bdly R1 ADDI AR3 tms_btime R1 STI RL ARO 1 Store LSB of counter 1 LDI AR3 tms_ta R1 STI RL ARO 2 Store LSB of counter 2 LSH 08H R1 SII R1 ARO 2 Store MSB of counter 2 104 LDI gct phasec ARO Pointer for phase c counter LDI AR3 tms btime R1 STI R1 ARO 0 Store LSB of counter 0 LDI AR3 tms bdly R1 ADDI AR3 tms_btime R1 STI R1 ARO 1 Store LSB of counter 1 LDI AR3 tms_ta R1 STI R1 AR0 2 LSH 08H R1 STI R1 AROQ LDI STI Store LSB of counter 2 Store MSB of counter 2 AR3 tms_btime RO RO AR3 tms_tboost RETS isr mode LDI AR3 tms_mode RO LDI gmode adjRl ADDI
15. LDI 010bH IE Enable interrupts 0 1 3 8 LDI 0030bH IE Enable interrupts 0 1 3 8 9 LDI 01H RO STI RO AR4 1 LDI gdp int IRO STI RO AR4 IRO RETS save setup LDI tblsize RC Init loop counter RPTB save dp LDI AR4 1 RO Start at the top of the dual port memory AND OffH RO Mask out all higher bits LSH 08H R0 Rotate 8 bits to the left LDI AR4 1 R1 GetLSB AND OffH R1 OR RO RI save dp STI R1 AR3 1 Save 32 bit data in internal RAM LDI dp_mem AR4 Reset AR4 LDI blk1 AR3 Reset AR3 LDI AR3 tms swf Rl BZ init _ Reset if switching frequency is 0 LDI swp constRO Determine switching period CALL divi STI RO AR3 tms swp my change to code to have interupt 1 2 way thru cycle LDI 02H R1 sold code LDI 003H R CALL divi ADDI 10H RO SII RO AR3 tms_swp_120 LDI AR3 tms_swp RO LDI RO RI Determine ta LSH 1H RO LDI AR3 tms btime R2 SUBI R2 R0 STI RO AR3 tms ta LDI AR3 tms_dt RO Determine tb LSH 01H RO SUBI RO R1 LSH 1H R1 f FLOAT R1 RND RI STF RI1 AR3 tms_ tb LDI AR3 tms_of RO Determine stepx LDI AR3 tms blk RI 72 MPYI R1 RO BZ init i LDI AR3 tms_swf R1 CALL divi STI R0 AR3 tms_stepx LDI AR3 tms_btime R1 STI R1 AR3 tms_tboost LDI AR3 tms_oaci R2 FLOAT R2 MPYF en6 R2 STF R2 AR3 tms_oaci STF R2 AR3 tms ilmin RETS A init swct LDI gct swfreg ARO Pointer for switchin
16. MSB of the SRC and converts the two values into 32bit integer format Storing the LSB integer in the SRC register and Storing the MSB integer in the MSB register LDI SRC MSB LSH 04H MSB ASH 14H MSB FLOAT MSB LSH 14H SRC ASH 14H SRC FLOAT SRC endm sh Puro dub 400 45 DA clin Gago do pm UAE VIE ee RP PR ld le dio up ly YD Se D mi o el UD ADS O RA An m um que US US GS O CU ee GU SU UA LL UD O O n 65 text init NOP LDI 0 DP EPROM Point the DP register to page 0 Boot LDI 08H DP Boot Init DP register LDI 00H ST Clear and enable cache and disable OVM 1800h LDI 0000H IE Clear all interrupts LDI Qctrl ARO Load peripheral bus memory mapped reg LDI xbus RO STI RO ARO 60H Init expansion bus control reg LDI gpbus RO STI RO ARO 64H Init primary bus control reg LDI stck SP Initialize the stack pointer CALL init ct Init counter timer CALL init values load default value table L R_sw LDI gd output ARO LDI 00FFH RO STI RO ARO LDI ct_port ARO Pointer for counter timer control register LDI Oreset_out RO STI RO ARO Disable all output LDI ctrl ARO LDI blk1 AR3 Sratch pad memory area LDI dp mem ARA Top of dual port memory LDI blk0 AR5 Sratch pad memory area LDI sram AR7 Top of the look up table LDI dp cin IRO Clear dual port memory interrupt LDI AR4 IRO RO LDI 000H RO Clear sram memory RPTS 204
17. Modes and Types 19 An addressing mode is a grouping of instructions based on the syntax used when writing code An addressing type is a grouping of instructions based on how data is accessed from memory or registers Chapter 5 of Reference 8 provides a complete and thorough description of each mode and type of addressing Not every type of addressing is available in every mode For instance the Three Operand Addressing Mode allows only register addressing and indirect addressing because of the fields available in the instruction word Examples of each mode and type of addressing can be found in decidi B the code Circular addressing plays a very important role in the implementation of the control algorithms discussed in Chapter VI and will be covered in more detail there D PROGRAM DEVELOPMENT AND SUPPORT Texas Instruments provides an excellent support system for the TMS320C30 microprocessor user Numerous resources are available to aid in the design implementation and debugging processes Figure 3 1 shows the TMS320C3x development environment supported by products from Texas Instruments Software tools availabl include an Assembler Linker allowing programming in assembly language an ANSI C Compiler so C source code may also be used and a TMS320C3x Simulator to allow for source code debugging of programs The TMS320C3x Simulator was used extensively during the coding portions of this thesis to test code prior to EPROM progr
18. RO LDI gd output ARO LDI OFFFH RO STI RO ARO LDI gct port ARO Pointer for counter timer control register LDI greset out RO STI RO FARO Disable all output RETS DC to DC Buck Converter cmd10 LDI 08H IE Disable interrupts 0 1 2 LDI ct_port ARO Pointer for counter timer control register LDI gclear main RO STI RO ARO Disable all output LDI 030H RO wait210 SUBI 01H RO BNZ wait210 LDI reset_out RO STI RO ARO Disable all counter timer output CALL init ct CALL save_setup Save data in 32 bit format CALL init swct Init switching frequency counters LDI AR3 tms swp RO FLOAT RO LDF gmax R MPYF RO R STF R1 AR3 UMAX MPYF Qmin RO STF RO AR3 UMIN LDI AR3 tms_ Vref RO FLOAT RO RND RO i STF RO AR3 tms_Vref 69 x Calc limit for Voltage error integrator LDI AR3 tms aci Rl FLOAT RI MPYF en2 R1 scale input to percent MPYF 5 0 R1 RND R1 STF R1 AR3 tms_aci AE Calc limit for Current error integrator LDI AR3 tms dci Rl1 FLOAT RI MPYF en2 R1 Scale input to percent RND Rl STF R1 AR3 tms dci start up ramp function xk LDI AR3 tms_step RO STI RO AR3 stopfreq LDI 000H RO STI RO AR3 tms_stepx Startup LDI AR3 stopfreq RO FLOAT RO a CALL FPINV MPYF AR3 tms_Vref RO RND RO STF RO AR3 vperfreq LDF 0000 RO STF RO AR
19. RO STI RO ARO LDI Qwait4t RO SUBI 01H RO BNZ wait31 LDI ct_port ARO Pointer for counter timer control register LDI allon RO STI RO ARO Enable all counter timer output STI RO AR3 tms outputb LDI 0209H IE Enable interrupts 0 3 9 LDI 01H RO STI RO AR4 1 LDI dp_int IRO STI RO AR4 IRO RETS Initialize counter timer init ct LDI ct_port ARO Pointer for counter timer control register LDI OOffH RO STI RO ARO Disable all counter timer output LDI gct swfreg ARO Pointer for switching frequency timer 1 LDI 0034H RO Mode 2 rate generator 00110100B STI RO ARO 3 LDI 0074H RO 01110100B STI RO AROG LDI 00b4H RO 10110100B STI RO AROG LDI ct_phasea ARO Pointer for phase a counter LDI 0012H RO Mode 1 hardware retriggerable one shoot 00010010B STI RO ARO 3 LDI 0052H RO Mode 1 R W LSB 01010010B STI RO ARO 3 LDI 00b2H RO Mode 1 R W LSB amp MSB 10110010B STI RO AROG LDI Act phaseb ARO Pointer for phase b counter LDI 0012H RO Mode 1 hardware retriggerable R W LSB 00010010B STI RO AROG LDI 0052H RO Mode 1 R W LSB 01010010B STI R0 AR0 3 LDI 00b2H RO Mode 1 R W LSB amp MSB 10110010B STI RO AROG LDI gct phasec ARO Pointer for phase c counter LDI 0012H RO Mode 1 hardware retriggerable R W LSB 00010010B 101 STI RO ARO 3 LDI 0052H RO Mo
20. Universal Controller s counter timers the same way it did for the buck choppers only with 120 degree displacement between phases This phase difference is created in part by offsetting the phase interrupts that are used to calculate the control signal duty cycles The code that actually performs this function can be found in the init swct subroutine listed in Appendix C 46 switching frequency timer C T1 Counter en n 1 t m qunppumy Figure 6 2 Three Phase Interrupt Initialization Ref 3 The switching period count is calculated from the switching frequency from the host PC and loaded into one of the switching frequency timers This same count is then loaded into the next phase counter after being delayed by 2 3 of the period and into the last counter after another similar delay This ultimately produces a 120 degree a between phase interrupts The duty cycle count for the primary switches is based on sine triangle pulse width modulation PWM In PWM a sine wave at the desired output frequency of the inverter is superimposed on a fixed amplitude triangular wave at the desired switching frequency of the inverter Each phase will have a bo sinusoidal control signal with the respective signals 120 degrees out of phase When the sine wave is greater than the triangle waveform the upper switch for the given inverter leg is gated When the sine wave 15 less than the triangle waveform the lower switch is gated This crea
21. closed loop control algorithm for the ARCP inverter is encoded and recommendations for future research are outlined vi TABLE OF CONTENTS LINTRODUCTUO Nini A coins 1 A DC ZONAL ELECTRICAL DISTRIBUTION sccccsssssecsessssnssonesnsccescesnescssesscoacseesosscsensenscsecsoes 1 Be RESEARCH B 26 AAA nn M 3 IL UNIVERSAL CONTROLLER isssisccscasssnicsdssnississessssiisscosesvitcassasvenseassodscanacuspecbincienssateeussedasesesseansoses seseguasoss 7 As INTRODUCTION Ite 7 B GENERAL DESCRIPTION riiin aaa eNA Or EAT a nA SEE 8 C PRIMARY COMPONEN TS ai ria 9 ASIA NOn 9 Di MI A O 11 D OPERATIONAL OVERVIEW ua ia 14 IL TMS3S20CS0 ARCHITECTURE sosiaa aaee anaa Ssa aa e ap OaE A SEEE a 17 A INTRODUC HON ii ii 17 B ARCHITECTURE 00 TCR 17 ADDRESS MODE Sidi 19 D PROGRAM DEVELOPMENT AND SUPPORT s scsssosscsssssssscsosscsscssessnsorssessocseressssessecsecsessceneseoss 20 IV BUCK CHOPPER APPLICATIONS cossis aaa aara draba aaa a aiaa osaa aoaaa aain 23 AcINTRODUC TION a debia 23 B PROTECTION GIRCULES ore eiii 25 1 24 volt Control Power Low Over Temperature e essesesorcesesessosoosocsossesssososssoeessesssvouososossosos nd 25 2 Over Current Sense and Shutdown eee Ie ee eee eurer eere tet eses toot asserere enses eene tene en aenea 26 C LOCAL REMOTE SWITCH MODIFICATION
22. set tms step set tms delay set tms swp set tms stepx set tms ta set tms tb set tms kc set tms kcb set tms bt set tms bi set tms mode set 0000000H 0000002H 0000004H 0000006H 0000008H 000000aH 000000ch 000000eH 0000010H 0000012H 0000014H 0000016H 0000018H 00000 1aH 000001cH 000001eH 0000020H 0000022H 0000024H 0000026H 0000028H 000002aH 000002cH 000002eH 0000030H 0000000H 0000001H 0000002H 0000003H 0000004H 0000005H 0000006h 0000007H 0000008H 0000009H 000000aH 000000bH 000000cH 000000dH 000000eH 000000fH 0000010H 0000011H 0000012H 0000013H 0000014H 0000015H 0000016H 0000017H 0000018H 0000019H Command register Ac trip current level Ac voltage Boost delay Boost time Dc current Dc trip current level Dc voltage Deadtime Ac frequency Switching frequency Ac current Block size c sensor Dc sensor Step Delay Switching period Step ta constant tb constant gt gt 3 Mode Command register Ac trip current level Ac voltage Boost delay Boost time Dc current Dc trip current level Dc voltage Deadtime Ac frequency Switching frequency Ac current Block size Ac sensor Dc sensor Step Delay Switching period Step ta constant tb constant gt gt Mode 94 tms swp 120 set 000001aH tms cos set 000001bH offset for pointer to cos i
23. the existing program to C is investigated and reported on in Chapter V NSWC engineers encoded an open loop control algorithm for the SSIM an ARCP inverter Closed loop control is desirable because it can reduce or eliminate changes that would occur in output voltages caused by changes in the load or input voltage Ref 4 Chapter VI of this thesis contains a description of the current open loop operation of the ARCP and the implementation of one proposed closed loop control algorithm Finally Chapter VII contains a summary of research work completed notable conclusions and recommendations for future work II UNIVERSAL CONTROLLER A INTRODUCTION Digital control algorithms have proven more flexible than analog ones Changes to digital controllers can be made relatively easily via software modifications Analog changes require the removal and replacement of actual components This can be very time consuming and expensive Also depending on component tolerances the accuracy of the analog implementation may be less than acceptable Digital algorithms on the other hand can be modified by changing numbers in software then reloading the new program Any size change can be accommodated with the proper scaling and accuracy can be achieved by fine tuning the changes in the software Closed loop control algorithms can be very I O intensive The ARCP for example has six 6 primary switches that require control signals to t
24. the operating program for the Universal Controller The static RAM or SRAM is made up of four IDT71256SA fast 32K x 8 bit CMOS chips Again these chips are connected in parallel to an address decoder to provide a 32 bit data word similar to the EPROMs The SRAM is primarily used for 10 data storage It stores values such as the sin look up table used by the ARCP program for calculating the control signals The final type of memory is the 1K x 8 bit high speed dual port static RAM It is connected between the microcontroller and the microprocessor This memory is used to store information sent to the Universal Controller from the host PC until it is needed or until it can be loaded into the SRAM This information includes but is not limited to command information that directs which algorithm to run maximum and minimum currents and voltages reference information used by the control algorithm and the control constants needed by the control equations Because the Universal Controller communicates serially with the host PC access to this information is delayed a relatively long time Using the microcontroller to direct this interface and load this information into the dual port memory for later use by the microprocessor greatly accelerates this process A more in depth discussion of the specifics of the Universal Controller s memory is available in Chapter III of Reference 3 2 VO Board The I O Board of the Universal Controller can
25. tms_btime R1 STI RL ARO 0 Store LSB of counter 0 LDI AR3 tms_bdly R1 ADDI AR3 tms_btime R1 STI R1 ARO 1 Store LSB of counter 1 LDI AR3 tms_ta R1 STI R1 ARO 2 Store LSB of counter 2 LSH 08H R1 STI R1 ARO 2 Store MSB of counter 2 LDI AR3 tms btime RO STI RO AR3 tms_tboost RETS LDI AR3 tms mode RO LDI gmode ad R1 ADDI R1 RO BNZ RO RETS d BR modeO Stop BR modeO Test Mode BR mode0 DC to AC Mode BR modeO Motor Control Mode Forward BR modeO Motor Control Mode Reverse BR mode0 Actuator Control Mode Open BR mode0 Actuator Control Mode Close BR mode0 Linear Actuator Mode Open BR modeO Linear Actuator Mode Close BR mode9 DC to DC Boost Mode BR modelO DC to DC Buck Mode BR mode0 Stop BR modeO Stop LDI O8H IE Disable interrupts 0 1 2 LDI Oct port ARO Pointer for counter timer control register LDI clear main RO STI RO ARO Disable all output LDI 030H RO wait30 SUBI O1H RO BNZ wait30 LDI greset out RO STI RO ARO Disable all counter timer output AND 08H IF Clear all pending interrupts 0 1 2 LDI 00H RO 74 STI RO AR4 1 LDI gdp int IRO STI RO ARA IRO RETS Return test mode9 LDI AR3 tms_kc R7 4 RETS DC to DC Buck Converter model0 LDF AR3 tms Vref RO RO Vref LDF AR3 Vin_inv R1 R1 1 Vin LDF AR3 Vout R2 R2 Vout LDF A
26. to maintain stability Equations 4 7 and 4 8 show the control equations implemented using the Master Slave scheme 34 D Des My Vor Vne hn f Vi V at h ia 612 ia i 4 7 Dus Dus k is inn Jat key s i 4 8 where D ase Master Buck duty cycle D steady state duty cycle h voltage gain V voltage out from Buck one e reference voltage h voltage integrator gain h current gain i Buck one inductor current i Buck two inductor current i Buck one output current i Buck two output current k proportional gain Die Slave Buck duty cycle k current integrator gain 2 Application To implement the Master Slave algorithm as efficiently as possible much of the previous control code and interrupt was retained Much of the code was written by Mr Roger Cooley an engineer for NSWC in Annapolis MD with modifications made at Naval Postgraduate School to allow testing on the 20 kW units in the Power Systems Laboratory Figure 4 4 documents the program flow for controlling two 2 buck choppers Ref 3 The two bucks are controlled by the phase interrupts routed through PLD A and PLD B The interrupts occur 180 degrees out of phase or 29 every 25 msec allowing the Universal Controller to monitor and control one 1 buck chopper at a time i PLD B interrupt MA PLDA wait for interrupt routine E sample voltages sample voltages and currents load a
27. two primary reasons that the C programming language was chosen to lil the control algorithms for the Universal Controller First the C language being a high level language is more compact and more readable than assembly language Closed loop control algorithms with PI controllers use equations that involve relatively complex mathematical computations The assembly code used to implement these equations is also complex and oftentimes difficult to decipher Several lines of assembly code are required to do mathematical operations performed by a single line of C code The second reason to use C was a matter of convenience An ANSI C compiler is supplied with the TMS320C30 microprocessor This is a full featured optimizing compiler that translates ANSI C programs into assembly language source code Ref 9 The compiler allows for the interlacing of assembly language instructions into C code and also allows assembly modules to call C modules and vice versa Implementing C code was going to be done in steps in order to provide a measure of testability on existing systems The current assembly code is quite extensive To prevent reinventing the wheel the plan was to write only the control algorithm for the buck chopper in C code leaving as much of the remaining code intact as possible This would save a significant amount of time in coding because the majority of the existing program used for initializing the system could be used as an assembly mod
28. 3 tms Vref LDI ctrl ARO Load peripheral bus memory mapped reg LDI AR3 tms_delay RO MPYI 064H RO STI RO ARO 28H LDI tim0ctl RO STI RO ARO 20H Init internal timer 0 voltage and current scaling LDI AR3 tms dcs RO FLOAT RO MPYF invl lbits RO 3 RND RO STF RO AR3 tms put LDI AR3 tms acs RO FLOAT RO MPYF Qginvlibits RO RND RO STF RO AR3 tms PT define hi hn hv and T 2 LDI AR3 tms swf d RO fsw FLOAT RO MPYF 2 0 RO IR 2 fsw 2 fsamp CALL FPINV a Tswp 2 70 s ok kale ale ok ade ok oe ole ade ale ade ale oe ale ole oe ale ade ale ale ae ale ole ale ole ae ok de ok ade ale ak ale oe ale ade oe K ad ale oe k k Ok ale k k k k OverCurrent Trip Code STF RO AR3 tau_2 Store T 2 PES ETL oko ok k k SESE ESE ade ale ok ok ade k SES ES ale ade ale ade TT TT k 3k K k K ale a ad ale ade ale ade ale k ok LDI AR3 tms_bi Rl FLOAT Rl MPYF en4 R1 MPYF RO RI i RND RI STF RL AR3 K slave j gt K T 2 LDI AR3 tms kc Rl FLOAT RI f MPYF en4 RI hn MPYF RI1 RO RND RO STF RO AR3 hn jor gt hn T 2 LDI AR3 tms kcb RO FLOAT RO MPYF en4 RO RND R0 STF R0O AR3 hv j gt hv LDI AR3 tms_bt RO FLOAT RO MPYF en4 RO RND RO f STF R0 AR3 hi soen gt hi LDF 0 0 RO 2 STF RO AR3 Vdiffa Initialize V diff STF R0 AR3 Vd_inta Initialize Vd_int STF RO AR3 Vdiffb Initiali
29. 43 dt word 14 of word 60 swf word 20000 aci word 10 blk word 2000 acs word 50 des word 500 step word 50 delay word 10000 ke word 17333 keb word 9 bt word 105 bi word 2 L R posit word 00H command word 10 mode word 10 Define constants swp const word 10000000 save setup invllbits float 0 00048828125 cmd10 isr0 cmd1 mil float 0 001 init pid en7 float 0 0000001 en6 float 0 000001 en5 float 0 00001 en4 float 0 0001 en3 float 0 001 en2 float 0 01 enl float 0 1 AVE float 0 2 max float 0 95 min float 0 05 eK ok ok ok ole oe ok ok ke ok ok ok ok 2 oe ok oe ok ale ole oe ok al k ok ook k k ode OK ade ade ale ae ale k ale k x OverCurrent Trip Code 79 full float 116 0 limit float 58 0 sk ak sk ale ade ade ole ole ade ESS SSL EST LE SESS TS ae ale ok oe ale ESET ak k oe o e k k e x BOOT cmd usect dualport 10000h BOOT cmd usect dualport 10000h EPROM ctio usect xbus 2000h lookup usect ram1 400h varible usect ram2 400h ppe iaaa US FR A A A edicit EA ip isr0 SSCM SLAVE UNIT interrupt service rountine x BOOT sect isr0 BOOT Named Section isr0 NOP 3 EPROM PUSH ST Save registers PUSH IRI PUSH R7 PUSHF R7 4 PUSH R6 PUSHF R6 PUSH R5 PUSHF R5 PUSH R4 PUSHF R4 PUSH R3 PUSHF R3 PUSH R2 PUSHF R2 i PUSH RI PUSHF R1 i PUSH RO PUSHF RO PUSH ARO PUS
30. 6 RO RO Vinput 2 81 LD ARS R6 A2Dfltr R6 R7 R6 Voutput LSB R7 io slave MSB ADDF R6 R1 R17 Voutput 2 LDI AR6 R6 A2Dfltr R6 R7 R6 iL_slave LSB R7 iL master MSB ADDF R6 R2 R2 iL_ slave 2 ADDF R7 R3 R3 iL_master 1 LDI AR7 R6 A2Dfltr R6 R7 R6 i0_slave LSB R7 io master MSB ADDF R6 R4 R4 iout slave 2 ADDF R7 R5 R5 jout master 1 MR ee ER sek kc ook ajajaja jad fala ja OIG OR GOR OR oe ak oko xke soe mR I kk kok kok LDI ARO AR4 READ Vinput LSB AND iL slave MSB NOP NOP LDI ARI ARS READ Voutput LSB AND io slave MSB NOP NOP LDI AR2 AR6 READ iL_slave LSB AND iL master MSB NOP NOP LDI AR3 AR7 READ io slave LSB AND io master MSB NOP NOP EEEE kk Process and Accumulate Data LDI AR4 R6 A2Dfltr R6 R7 R67 Vinput LSB R7 iL slave MSB ADDF R6 RO RO Vinput 2 LDI ARS R6 A2Dfltr R6 R7 R6 Voutput LSB R7 io slave MSB ADDF R6 R1 R17 Voutput 2 LDI AR6 R6 A2Dfltr R6 R7 R6 iL_slave LSB R7 iL master MSB ADDF R6 R2 R2 iL slave 2 ADDF R7 R3 R3 iL master 1 LDI AR7 R6 A2Dfltr R6 R7 R6 io slave LSB R7 io master MSB ADDF R6 R4 R4 tout_slave 2 ADDF R7 RS R5 iout master 1 A oe ek ok OR ROR RRR ROR OR IORI Rk soe xeokoxeexeokeoke eek iL_slave MSB NOP LDI ARO AR4 READ Vinput LSB AND NOP NOP LDI ARLARS READ Voutput LSB AND io slave MSB NOP LDI AR2 AR6 READ iL slave LSB
31. 7 STI RO AR4 1 LDI dp mem ARA Top of dual port memory LDI 0000H IF Clear all flags LDI 0200H IE Enable interrupt 9 internal timer 1 L R sw OR 02000H ST Global interrupt enable begin NOP NOP NOP NOP BR begin Initialize counter timer mt ct LDI ct_port ARO Pointer for counter timer control register LDI 00ffH RO STI RO ARO Disable all counter timer output LDI ct_swfreg ARO_ Pointer for switching frequency timer 1 LDI 0034H RO Mode 2 rate generator 00110100B STI RO ARO 3 66 LDI 0074H RO 01110100B STI RO ARO 3 LDI 00b4H RO 10110100B STI RO ARO 3 LDI Oct phasea ARO Pointer for phase a counter LDI 0012H RO Mode 1 hardware retriggerable one shoot 00010010B STI RO ARO 3 LDI 0052H RO Mode 1 R W LSB 01010010B STI RO ARO 3 LDI 00b2H RO Mode 1 R W LSB amp MSB 10110010B STI RO ARO 3 LDI Oct phaseb ARO Pointer for phase b counter LDI 0012H RO Mode 1 hardware retriggerable R W LSB 00010010B STI RO ARO 3 LDI 0052H R0 Mode 1 R W LSB 01010010B STI RO F AROG LDI 00b2H RO Mode 1 R W LSB amp MSB 10110010B STI RO ARO 3 LDI gct phasec ARO Pointer for phase c counter LDI 0012H RO Mode 1 hardware retriggerable R W LSB 00010010B STI RO ARO 3 LDI 0052H RO Mode 1 R W LSB 01010010B STI RO ARO 3 LDI 00b2H RO Mode 1 R W LSB amp MSB 10110010B STI RO AR
32. FFFH RO MPYI AR3 tms_odci RO LDI AR3 tms dcs R1 CALL divi 2 LDI gdac 2 ARO STI RO ARO RETS sine tbl this routine generates a SINE lookup table with length equals to the value stored in dp blk memory location sine tbl LDI AR3 tms_blk RC Get size of lookup table LDI RC RO SUBI 0001H RC BLS init Reset if size is too small FLOAT RO CALL FPINV l blk LDF gtwo pLRl Store 2 pi value MPYF R1 RO 1 bIk 2 pi RND RO LDF RO R6 Save the result LDF 0 0 R7 RPTB save_tbl MPYF3 R6 R7 RO l blk count 2 pi CALL SIN RND RO ADDF 1 0 R7 Increment count save tbl STF RO AR7 1 Save data into lookup table LDI sram AR7 Restore lookup table pointer RETS init swct LDI gct swfreg ARO Pointer for switching frequency timer 1 LDI AR3 tms_swp RO STI RO ARO 0 Store LSB of counter 0 LSH 08H RO STI RO ARO 0 Store MSB of counter 0 NOP NOP NOP LDI AR3 tms swp 120 R2 103 checkout0 LDI 0000H RO STI RO ARO 3 Latch command LDI ARO 0O RO AND 000FFH RO Clear all other higher bits LDI ARO O R1 LSH 0008H R1 AND 00f00H R1 OR RI1 RO CMPI R2 RO BGT checkoutO LDI AR3 tms_swp RO SII RO ARO 1 Store LSB of counter 1 LSH 0008H RO STI RO ARO I Store MSB of counter 1 NOP NOP NOP LDI AR3 tms_ swp 120 R2 checkout1 LDI 0040H RO i STI R0 AR0 3 Latch command LDI
33. H ARI PUSH AR2 E PUSH AR3 PUSH AR4 PUSH ARS PUSH AR6 PUSH AR7 LDI 0AOH R7 wait00 SUBI 01H R7 BNZ wait00 LDI Qinputcs ARO Pointer for DC ADC LDI Qacs ARI LDI bcs AR2 LDI ccs AR3 80 LDI ARO RO start conversion NOP NOP LDI ARLRI NOP NOP LDI AR2 R2 NOP NOP LDI AR3 R3 NOP NOP LDI 00FH R7 wait SUBI 01H R7 BNZ wait0 STORE SAMPLED VOLTAGES AND CURRENTS LDI ARO RO READ Vinput LSB AND iL slave MSB NOP NOP LDI ARLIRI READ Voutput LSB AND io slave MSB NOP NOP LDI AR2 R2 READ iL slave LSB AND iL master MSB NOP NOP LDI AR3 RA READ io slave LSB AND io master MSB NOP NOP A2Dfltr RO R7 RO Vinput LSB R7 iL slave MSB A2Dfltr R1 R7 R1 Voutput LSB R7 io slave MSB A2Dfltr R2 R3 R2 iL_slave LSB R3 iL master MSB A2Dfltr R4 RS R4 io_slave LSB R5 io master MSB sk ok ook oko ofc ok ok ok ade ale a af ok ok ad oe oe ale ale ok al ok oko oe ok ok okc ok ale ale ad ade oe ok oe oe ok ok okc ok ok ad ok ok okc al ade ok ok oec oe oe oe ok ok ok al E ae EE E E E E E E E E E E LDI ARO AR4 READ Vinput LSB AND iL_slave MSB NOP NOP LDI ARI ARS READ Voutput LSB AND io slave MSB NOP NOP LDI ARZ AR READ iL slave LSB AND iL master MSB NOP NOP LDI AR3 AR7 READ io_slave LSB AND io master MSB NOP NOP Nooo Process and Accumulate Data LDI AR4 R6 A2Dfltr R6 R7 R6 Vinput LSB R7 iL_slave MSB ADDF R
34. O mask all but 4 Isbs LDI cmd_ad R4 Jump target if needed for shutdown CMPI OfH RO see if word is good BNE R4 Shuts down Bucks Interrupt subroutine O was selected as the place to add the protection code because 1srO will run in both local or remote mode Local and remote modes of operation are explained in a later section The third protection circuit code over current sense and shutdown was placed in isrO for the same reason 2 Over Current Sense and Shutdown The over current sense and shutdown code was designed to monitor the average over current and shut down the system whenever the average over current exceeded 150 of rated current The problem caused by over current is that the heat that builds up in the solid state switches has no time to dissipate As the average over current increases the operating temperature of the device rises and eventually the component fails But when the heat has a chance to dissipate indicated by when the average over current decreases the components have a chance to recover and system shutdown is not required The average over current was calculated by integrating the over current over time This was accomplished by encoding the following equation i iy 116 dt 4 2 over current_average 116 out where 116 represents 10096 rated current in amps 26 The actual encoding of the integral required ien steps to accomplish The integration was to be performed using the trapezoidal in
35. OG LDI Octrl ARO Pointer for counter timer control register L R sw LDI gtimlprd RO load internal timer period L R sw STI RO ARO 38H L R sw LDI timlctl RO _ init timerl L R sw STI RO ARO 30H L R sw RETS init values LDI oaci AR3 tms_oaci load all front panel values for L R sw LDI gacv AR3 tms acv XL R sw LDI bdly AR3 tms_bdly X L R sw LDI gbtime AR3 tms btime L R sw LDI gdci AR3 tms dci XL R sw LDI odci AR3 tms_odci L R sw LDI Vref AR3 tms Vref L R sw LDI dt AR3 tms dt XL R sw LDI 2of AR3 tms of XL R sw LDI gswf AR3 tms swf XL R sw LDI gaci AR3 tms aci XL R sw LDI gblk AR3 tms blk L R sw LDI acs AR3 tms_acs L R_sw LDI dcs AR3 tms_des L R_sw LDI step AR3 tms_ step L R_sw LDI delay AR3 tms delay L R_sw LDI kc AR3 tms_ kc L R sw LDI kcb AR3 tms_kcb XL R sw LDI gbt AR3 tms bt L R sw LDI bi AR3 tms_bi L R sw 67 LDI L_R_posit AR3 L_R_posit need to init switch posit 0 remote LDI command AR3 command L R_sw LDI mode AR tms_mode XL R sw RETS read cmd modified for L R sw operation read cmd LDI AR3 L R posit RO read switch posit L R sw CMPI 0000H RO see if in remote L R sw BEQ ck cmd jf in remote go to ck cmd L R sw LDI AR3 command RO ifin local load command 10 L R sw addr LDI gcmd ad R p
36. OPF R2 POP R2 POPF R3 POP R3 POPF R4 POP R4 POPF R5 POP R5 POPF R6 POP R6 POPF R7 POP R7 POP IR POP DP POP ST NOP 88 RETI Return and enable interrupt e aay aman gay sae ee ee ee EE CA SE TS eS TS LS SS SS et it ei timer0 Startup timer BOOT sect time0 BOOT Named Section timed NOP EPROM PUSH RO PUSHF RO PUSH ARO LDI AR3 tms stepx RO ADDI 01H RO STI RO AR3 tms_stepx CMPI AR3 stopfreq RO BLE looptimer0 LDI 000H RO LDI ctri ARO STI R0 AR0 20H Clear counter ANDN mask timer0 IE Disable timer interrupt POP ARO POPF RO POP RO RETI looptimer0 LDF AR3 vperfreq RO ADDF AR3 tms_Vref RO RND RO f STF R0 AR3 tms_Vref POP ARO f POPF RO timer 100ms Timer BOOD sect timel BOOT Named Section timel NOP P EPROM PUSH ST PUSH DP PUSH IRI PUSH R7 PUSHF R7 PUSH R6 PUSHF R6 PUSH R6 PUSHF RS PUSH R4 PUSHF R4 PUSH R3 PUSHF R3 PUSH R2 89 PUSHF R2 PUSH RI gt PUSHF RI PUSH RO PUSHF RO PUSH ARO LDI AR3 L R posit R1 get previous L R posit LDI gd output ARO set pointer to Gen I O STI ARO RO RO gen I O word AND 0010H RO mask all but L R sw posit bit4 CMPI 00H RO if 0 in remote BEQ remote local LDI 303H IE disables int3 in loca mode CMP RO R see if sw same as last interrupt BEQ update vref if in local update vr
37. OTECTION CIRCUITS 1 24 volt Control Power Low Over Temperature Self protection requirements were established by personnel at NSWC for SSCM control operation These requirements consisted of a 24 volt control power low shutdown an over temperature shutdown and an over current sense and shutdown These changes needed to be incorporated in software In the cases of 24 volt low and over temperature these changes merely consisted of reading a status words in from an external sense board that monitored these conditions and comparing the result to a word that corresponds to an admissible condition The output from the sense board is connected to a general purpose I O jack labeled connector JP 1 on the Universal Controller Table 4 1 Protection Circuit Bit Assignments Table 4 1 shows the bit assignments used for the general purpose I O connector on the Universal Controller Memory address location 804500h d output is associated with the general I O port and was used to test for errors Only the four 4 least o bits needed to be checked so the rest were masked out Since the requirement was for any one of the fault conditions to shut down the bucks only one compare was 25 needed All four bits were tested at once If any one of them indicated an error the system was shut down The following code was added to interrupt subroutine 0 isr0 LDI Ad output ARO set pointer to Gen I O STI ARO RO sRO gen I O word AND 000fH R
38. R3 Vdiff R3 R3 Vdiff n 1 LDF AR3 iL R6 R6 iL SUBF AR3 iout R6 R6 iL iout MPYF AR3 hi R6 R6 hi iL iout MPYF3 RO RI RA R4 Dss Vref Vin s STF R4 AR3 Dss e SUBF3 RO R2 R5 RS Vdiff n Vout Vref ADDF R5 R3 FR3 Vdiff n Vdiff n 1 MPYF AR3 hn R3 R3 Vd int KcT 2 Vdiff n Vdiff n 1 ADDF AR3 Vd int R3 R3 Vd int n Vd int Vd int n 1 jM Limit the Integrator LDF R3 R7 R7 temp Vd int n ABSF R7 CMPF AR3 tms_aci R7 CMPf abs Vd int n Iac BLE NoLim10 Limit reached stop increasing LDF AR3 Vd int R3 R3 Vd int old NoLim10 NOP LDF AR3 Dss R4 restore Dss to R4 SUBF R3 R4 R4 D Dss Vd int SUBF R6 R4 R4 Dss Vd int hi iL iout LDF AR3 hv R6 R6 hv MPYF R5 R6 R6 hv Vout Vref SUBF R6 R4 R4 Dss Vd int hi iL iout hv Vout Vref jM Limit the duty cycle HiLim CMPF max R4 BLE LoLim LDF max R4 LoLim CMPF min R4 BGT Same LDF min R4 Same NOP EN Store Master Dutycycle STF R4 AR3 d d Dss dl LDI AR3 tms_swp R7 FLOAT R7 MPYF R7 R4 SUBF R4 R7 a Here R7 1 d to compensate for the PEBB EPLD inversion STF R7 AR3 count e FIX R7 RETS Return EPROM ONLY Sect vecs Named section reset word init RS loads address init to PC intO word isrO INTO loads address intO to PC intl word isrl INTI loads address int to PC int word isr2 INT2 loads address int2 to PC int3 word isr3 INT3 loads add
39. RI RO BNZ RO RETS k mode_cmd BR mode0 Stop BR model Test Mode ARCP Open loop BR modeO DC to AC Mode BR modeO Motor Control Mode Forward BR modeO Motor Control Mode Reverse BR mode0 Actuator Control Mode Open BR modeO Actuator Control Mode Close BR modeO Linear Actuator Mode Open BR mode0 Linear Actuator Mode Close BR modeO DC to DC Boost Mode BR mode0 DC to DC Buck Mode BR modeO Stop BR mode0 Stop mode0 LDI 08H IE Disable interrupts 0 1 2 LDI Oct port ARO Pointer for counter timer control register LDI clear main RO STI RO ARO Disable all output LDI 030H RO wait30 SUBI 01H RO BNZ wait30 LDI reset_out RO STI RO ARO Disable all counter timer output AND 08H IF Clear all pending interrupts 0 1 2 LDI 00H RO STI RO AR4 1 LDI dp int RO STI RO AR4 IRO RETS Return model MPYF AR3 tms tb R7 105 FIX R7 ADDI AR3 tms_ta R7 RETS Return timer0 Motor startup timer time0 PUSH RO PUSHF RO PUSH ARO LDI AR3 tms_stepx RO ADDI 01H RO STI RO AR3 tms stepx CMPI AR3 stopfreq RO BLT looptimerO LDI 000H RO LDI ctrl ARO STI RO ARO 20H Clear counter ANDN mask timerO IE Disable timer interrupt POP ARO POPF RO POP RO RETI looptimer0 LDF AR3 vperfreq RO ADDF AR3 tms_acv RO RND RO STF RO AR3 tms_acv POP ARO POPF RO q POP RO RETI t
40. RO RO Clear interrupt CALL read cmd a ANDN mask int3 IF Clear interrupt 3 POPF RO POP RO POPF Rl POP Ri gt POPF R2 POP R2 POPF R3 POP R3 POPF R4 POP R4 POPF R5 POP R5 POPF R6 POP R6 POPF R7 POP R7 POP IRI POP DP POP ST RETI Return and enable interrupt end 111 112 LIST OF REFERENCES Dade T B Advanced Electric Propulsion Power Generation and Power Distribution Naval Engineers Journal Vol 106 No 2 pp 83 92 March 1994 Oberley M J The Operation and Interaction of the Auxiliary Resonant Commutated Pole Converter in a Shipboard DC Power Distribution Network Master s Thesis Naval Postgraduate School Monterey CA 1996 Hanson R J Implementing Closed loop Control Algorithms for DC to DC Converters and ARCP Inverters Using the Universal Controller Electrical Engineer Thesis Naval Postgraduate School Monterey CA June 1997 _ Fisher M J Power Electronics PWS Kent Publishing Company Boston 1991 NSWC CDAD Schematics Code 813 Annapolis 1995 Intel AP 70 Using the INTEL MCS 51 Boolean Processing Capabilities Intel Corporation 1998 MAXIM MAX120 MAX122 Data Sheet Sunnyvale CA 1994 Texas Instruments TMS320C3x User s Guide Texas Instruments Inc 1994 Texas Instruments TMS320 Floating Point DSP Optimizing Compiler Texas Instruments Inc 1991 10 Texas Instrument
41. TMS320C30 microprocessor was discussed in Chapter III The architecture powerful instruction m and paralleling hardware give the microprocessor exceptional speed and the ability to handle the tasking of the Universal Controller Some of this tasking was covered in Chapter IV NSWC personnel specified additional software features that had to be incorporated in the assembly language program governing the operation of the buck choppers In Chapter IV the over current under voltage and over temperature protection schemes were introduced and added to the control code This chapter also covered modifications needed to provide for Local Remote switch operation as well as encoding a Master Slave paralleling algorithm Improving the readability of the control 55 algorithms was addressed in Chapter V together with assessing the possibility of using C code The several problems that were associated with trying to inject C modules into the assembly code were discussed Finally Chapter VI covered the control of the ARCP inverter Basic open loop operation was discussed and one closed loop control algorithm was described and encoded B NOTABLE CONCLUSIONS The Universal Controller is very flexible Modifications to the control algorithms can be made but the assembly language program is quite lengthy and complex With no user s manual and little documentation available a significant amount of time is required to understand the code well enough to make ch
42. Vd int set 0000021H integral of Vdiff hn set 0000022H hv set 0000023H hi set 0000024H iL set 0000025H iout set 0000026H Vdiffa set 0000027H Vdiffb set 0000028H Vd_inta set 0000029H Vd_intb set 000002aH Vout set 000002fH DC input model0 Vin inv set 0000030H DUTY set 0000031H vperfreq set 0000033H Volt per frequency ratio 77 stopfreq set 0000034H Target frequecy stopvolt set 0000035H Target voltage tms invdv set 0000036H init cmd10 cmd1 s Dss set 0000037h d set 0000038h count set 0000039h e tms tboost set 000003aH save setup init swct isrO isrl isr2 cmd28 tms acscale set 000003bH tms dcscale set 000003cH cmd10 init cmd1 tms outputb set 000003eH cmdl0 cmdl tms ilmin set 000003fH save setup cmd29 tblsize set 000001aH Setup table size save setup K slave set 0000040H IL slave set 0000041H iL master set 0000042H io slave set 0000043H io master set 0000044H_ Vin set 0000045H ak ok ak He kc okc ak ak ok ok ok ok ok ok ae oe oe ok ok a k ak oe k oe oe oe oe oe ak de a ek xe OverCurrent Trip Code trip m set 0000046H trip s set 0000047H io m 116 set 0000048H io s 116 set 0000049H tau_2 set 000004aH PEE ESSE LSS ET TESS ole ale oe ok ok ale oe oe ok k oe oe oe oe k k kk k k k x ct swfreg word 0804000H Switching freq timer init ct init swct ct port word 0804100H Timer control register
43. a front panel Local mode or from the host PC Remote mode was hard wired in The system needed to be able to be initialized and run in either local mode or remote mode and switched from one mode to the other during operation When switched from mode to mode during operation the system needs to shut down and restart in the new mode of operation because switching from one mode to the other would not be a bumpless transition Two 2 voltage potentiometers were also connected to the front panel They provided a course and fine adjustment for the reference voltage when the units were operating in Local mode Software changes were required to enable operation of the front panel 2 Application In order to enable the front panel the TMS320C30 had to be able to recognize and monitor the position of the L R switch Bit 5 of the general purpose I O port used previously by the protection circuits was used to carry the L R switch position The reference voltage potentiometer signals were added together and sent as one input to the general purpose I O port This voltage was sent to an onboard A D converter to create a voltage word usable by the Universal Controller Once the TMS320C30 could access this information changes to the software were made so it could process this information 29 The normal program flow for the buck chopper control program was discussed in Chapter 2 As mentioned there after initialization of the microprocessor
44. age DC voltage out Figure 4 2 illustrates the affect that the duty cycle of the switch has on one average DC voltage out Figure 4 2 Average DC Voltage from a Buck Chopper Ref 3 23 For continuous inductor current the ideal steady state relationship is given by Vine Dek 4 1 where D steady state duty cycle t T E input voltage Further details on buck chopper operation are listed in Reference 3 Previous research developed a closed loop control algorithm for the SSCM The Universal Controller has enough I O capability to simultaneously control 2 buck choppers Reference 3 details single and dual buck chopper control System integrators at NSWC required some modifications to the software control that involved incorporating additional features not currently available This chapter addresses the added under voltage over temperature and over current protection algorithms and documents the changes to the assembly code provided in Reference 3 The next section describes how these changes were implemented Another added feature was the Local Remote switch Section C of this chapter outlines the changes to the interrupt structure and the code required to allow operation of an L R switch Finally the buck choppers must be capable of operating in parallel and sharing the load proportionately Section D addresses this issue and describes the changes made to implement a Master Slave type control algorithm 24 B PR
45. all counter timer output CALL init ct LDI sram AR7 _ Reset pointer for phase a CALL save setup Save data in 32 bit format 99 CALL set_oc CALL init swct Init switching frequency counters CALL sine_tbl Generate a SINE lookup table LDI AR3 tms a RO FLOAT RO MPYF gsqr2 RO RND RO STF RO AR3 tms_ T LDF AR3 tms_invdv RO CALL FPINV LDI AR3 tms swp R1 FLOAT Rl LDF half R2 MPYF3 R1 R2 R3 R3 T 2 RND R3 STF R3 AR3 T 2 store T 2 for use in integrating MPYF RLRO MPYF half RO RND RO STF RO AR3 tms_dtset LDF AR3 tms_tb RO STF RO AR3 dmax NEGF RO STF RO AR3 dmin LDF 0 5 R0 STF RO AR3 INA STF RO AR3 INB STF RO AR3 INC LDF Qzero RO a STF RO AR3 iq_int STF RO AR3 id_int STF RO AR3 igq STF RO AR2 idd initialize these to zero LDI AR3 tms acs RO FLOAT RO MPYF inv 1bits RO RND RO STF R0O AR3 tms acscal LDI AR3 tms_dcs RO FLOAT RO E MPYF inv1 1bits RO RND RO STF RO AR3 tms_ descale LDI AR3 tms_bik RO LDI O4H RI CALL divi LDI RO R1 STI RO AR3 tms_cos Reset pointer for cos function LD AR3 tms_blk BK 100 wait31 LDI ctrl ARO Load peripheral bus memory mapped reg LDI Otimiprd RO 10ms STI R0 ARO 38H LDI timictl RO STI R0 ARO 30H Init internal timer 1 LDI d_output ARO LDI 00FEH
46. amming All three of these software products are loaded on PCP WR 8 located in Bullard 114 Appendix A contains an explanation of how to access and run the Assembler Linker and Compiler by using DOS commands 20 and batch files Further information concerning the specific features provided by these products is available in their respective reference manuals Ref 9 and Ref 10 which are also located in Bullard 114 The TMS320C3x Simulator is described in Reference 11 Included in this manual are installation instructions and an operational tutorial that proved quite helpful Assembler Macro Source Source Files C Source Files C Compiler armo oo x Assembler Archiver Macro Libraries A d Dimma aat ymae DI mm other object libraries xecutable Object COFF Format 1 Converter x EPROM Simulator TMS320C30 Programmer Figure 3 1 Development Support for the TMS320C3x Ref 8 Other software products available and shown on Figure 3 1 are an Object Format Converter used to convert executable code into a format compatible with PLD programming and an EPROM Programmer to do the actual programming of PLDs 21 Again these products are loaded on PCPWR 8 in Bullard 114 Use of the Object Format Converter is addressed in Appendix A of this thesis and a complete description of how to use the EPROM Programmer can be found in Appendix C of Reference 3 Also available from Texas Instruments but
47. anges to the control algorithms C code algorithms would be easier to read and modify but extensive rework of the existing program would be required to allow the interlacing of C code modules with the assembly code Closed loop control of the ARCP is achievable with the Universal Controller allowing fast accurate response to system perturbations C RECOMMENDATIONS FOR FUTURE WORK Further work in the area of paralleling buck choppers is needed The problems associated with the original droop method and the differential cross current in the Master Slave algorithm leave the door open Bi the development of an algorithm that would allow control of multiple bucks in parallel yet be able to ensure proper load sharing Possible areas of investigation include current share wire or frequency injection controlling Research needs to be done to refine the closed loop ARCP inverter algorithm including the possible move to a more specialized control card or even a commercial 56 control card that may not be as I O capable or flexible as the Universal Controller but may allow different programming schemes Another possibility would be to develop a new control program scheme that is not interrupt driven and that can be implemented in C C visual C or some other high level language or even possibly completely rewriting the existing program in C The U S Navy is looking for ways to save money and at the same time upgrade operational capabili
48. be divided into two main functional parts an analog to digital interface portion and a counter timer portion Figure 2 3 shows the key components of the y O board of the Universal Controller The analog to digital interface part consists of 11 A D converters used to convert voltage and current signals into digital words that be used by the microprocessor The counter timer portion of the I O board is made up of 4 counter timer chips that contain 3 counters each and are used for various timing applications needed for control algorithm implementation 11 12 optical transmite E ej a INTO INT1 INT2 PLD PLD PLD Figure 2 3 I O Board of the Universal Controller Ref 3 The analog to digital interface is made up of 11 Maxim 500kbps A D converters Ten of these 12 bit converters are used to convert sensed voltages and currents that are imported to the control board from the SSCMs or SSIM One is reserved for conversions of on board values needed for different types of operation Five memory locations are reserved for the A D converters Since the TMS320C30 uses 32 bit words two 2 12 bit A D words can be stored in each location Initiating a read of an A D converter s memory location will read the value of the last conversion and initiate a new one The first read is always discarded because it is the result of a previous or time late data sample The second read represents a more real time sample of th
49. calculations One important difference i note is that only one interrupt was needed for closed loop control instead of the three used for open loop operation This involved making a slight change to the interrupt structure Interrupt Subroutines 1 and 2 were completely eliminated so as to not disrupt operation of the now longer Interrupt Subroutine O The 120 degree difference between phases 1s maintained by sampling the currents of two phases and then using those two samples to calculate what all three duty counts should be when separated by the proper phase difference The ARCP code in its entirety is enclosed as Appendix C 54 VII CONCLUSIONS A SUMMARY OF RESEARCH WORK The PEBB Universal Controller is a digital controller designed to handle the extensive 1 O requirements needed to implement closed loop control of buck chopper converters and ARCP inverters It provides great flexibility and 1s a valuable tool 1n the Navy s efforts to implement a DC ZEDS scheme The focus of this research was to expand the operational capabilities of the buck chopper converter control algorithm and to implement closed loop ud of the ARCP inverter In Chapter II the PEBB nives Controller operation and architecture were investigated The exceptional I O capability of the Universal Controller was dla was the architecture of the CPU board Basic program operation was outlined in order to set the stage for subsequent modifications The Texas Instrument
50. de 1 R W LSB 01010010B STI R0 AR0 3 LDI 00b2H RO Mode 1 R W LSB amp MSB 10110010B STI R0 AR0 3 RETS save setup LDI tblsize RC Init loop counter save dp RPTB save dp LDI AR4 l RO Start at the top of the dual port memory AND OffH RO Mask out all higher bits LSH 08H RO Rotate 8 bits to the left LDI AR4 1 RI GetLSB AND OffH R1 OR ROjRI STI R1 AR3 1 Save 32 bit data in internal RAM LDI dp_mem AR4 Reset ARA LDI bik1 AR3 Reset AR3 LDI AR3 tms swf R1 BZ init Reset if switching frequency is 0 LDI gswp constRO Determine switching period CALL divi SII RO AR3 tms_swp LDI 003H RI CALL divi f MPYI 02H RO ADDI 10H RO STI RO AR3 tms swp 120 LDI AR3 tms_swp RO LDI RO RI Determine ta LSH 1H RO LDI AR3 tms btime R2 j SUBI R2 RO STI RO AR3 tms ta LDI AR3 tms_dt RO Determine tb LSH 01H RO SUBI RO RI LSH 1H R1 FLOAT Ri RND Ri STF R1 AR3 tms_tb LDI AR3 tms_of RO Determine stepx LDI AR3 tms_blk R1 MPYI R1 RO a BZ init LDI AR3 tms swf Rl CALL divi STI RO AR3 tms_stepx LDI AR3 tms_btime R1 STI RI1 AR3 tms_tboost LDI AR3 tms oaci R2 FLOAT R2 STF R2 AR3 tms_ilmin 102 RETS i set overcurrent reference values set oc LDI OFFFH RO MPYI AR3 tms oaci RO LDI AR3 tms acs R1 CALL divi LDI dac 1 ARO STI RO ARO LDI O
51. e desired data and is saved for computations Each conversion takes 2 6 usec which is considerably slower than the 60 nsec instruction execution time for the microprocessor To allow for complete conversions there is a wait loop or delay time programmed into the code 12 following each A D read Specifics on data step size digital word selectivity of the A D converters can be found in Reference 6 Four 4 Harris 82C54 counter timers are located on the I O board Each 82C54 contains 3 counters that can be set up in various modes of operation for use by the Universal Controller The first counter timer 1s operated in a rate generator mode This counter timer functions as the switching frequency timer The desired switching frequency is programmed from the PC and converted to a count based on the clock speed and then loaded into the counter Ref 3 The other two counters located on the same chip are loaded with the same switching frequency count only delayed either by 120 degrees or 180 degrees of switching period depending on the application At a 20 Khz switching frequency 120 degrees of delay equates to 16 7 msec and 180 degrees of delay is 25 msec of difference between the first counter and the next These counters will generate interrupts with the proper phase shifts needed by the Cave Controller to initiate sampling and run the control igors The other three 3 Harris counter timers are used as hardware retriggerable one shots Adjusti
52. e present sw posit for later call cmdO sto shutdown bucks End int ANDN mask timerl IF RESET timer interrupt Flag POP ARO POPF RO POP RO POPF RI POP RI POPF R2 POP R2 POPF R3 POP R3 POPF R4 POP R4 POPF R5 POP R5 POPF R6 POP R6 POPF R7 POP R7 POP IR POP DP POP ST RETI end 91 92 APPENDIX C ARCP CLOSED LOOP CONTROL CODE xk ak ale ale ale a ok al ade ale al ok ade ole ale ale ale ok ade okc ade ade ade ade ade ad ae al oke ade ale ale ok ale ale ale ale ale ole al E EEE E E E E E E le al E E E ok NPS POWER LAB TMS320C30 CONTROL CODE BY TUAN DUONG NSWC MODIFIED FOR CLOSED LOOP CONTROL OF THE ARCP BY DAVID FLOODEEN sk sk ok ok oe ole ok ok oe ale ale ole ok ok ok ok ok ale ade ok ade ok ok oe oe ok ok ale ade ok ok ale ok ade ok ad k ale al ok ade k ok oe oe k ale ade oe ke ok k k de al k kk k X X KF X title PEBB global reset init global intO intl int2 int3 global tint0 global isr0 isr1 isr2 isr3 global time0 global SIN FPINV divi x sect vecs Named section reset word init RS loads address init to PC int word isrO INTO loads address int0 to PC intl word isrl INT1 loads address intl to PC int2 word isr2 INT2 loads address int2 to PC int3 word isr3 INT3 loads address int3 to PC space 4 Reserved space tint0 word time0 Timer 0 interrupt processing tint word timel Timer 1 interrupt processing space 33 Reserved space
53. e quantities Table 6 1 Closed Loop Control Algorithm Annotation The first step of closed loop control was to sample two 2 phase currents i and ij This will exploit the fact that for a three wire wye connected AC load the sum of the three instantaneous phase currents is zero The two 2 phase currents were then transformed into the synchronous reference frame To make this transformation easier to follow it was performed in steps gee the measured quantities were transformed into the stationary reference frame using the following diffeomorphic relationship ap Le fi tal e a Eak m Once in the stationary reference frame the following transformation is applied placing the quantities into the synchronous reference frame i n cos amp n sin amp n i n eral 6 3 i sin 9 n cos amp n 5 n Here 6 is the electrical angle of the measured quantities The values of sin and cos 6 are found using the sine look up table described in the previous section As mentioned then a pointer was set for the sine and double circular addressing was used 52 for the cosine as before Once i and i are calculated they are anpa to commanded values entered from the host PC i7 and i7 This produced i and i as shown by Equation 6 4 and 6 5 ka i n zin 6 4 ia i7 n n 6 5 The values i and 1 4 are next applied to a PI controller to calculate control voltages V
54. e set 0000004H Boost time save setup init swct tms dci set 0000005H Dccurrent tms odci set 0000006h De trip current level set oc tms Vref set 0000007H Dc voltage tms dt set 0000008H Deadtime save setup tms of set 0000009H Ac frequency save setup tms swf set 000000aH Switching frequency save setup tms aci set 000000bH Ac current tms blk set 000000cH Block size cmdl0 save_ setup sine_tbl cmd1 tms acs set 000000dH current sensor tms dcs set 000000eH voltage sensor set_oc cmd10 cmdl tms step set 000000fH Step tms delay set OO00010H Delay tms swp set 0000011H J Switching period init cmd10 save_setup init_swet cmd1 tms stepx set 0000012H Step cmd10 save_setup isr0 isr isr2 cmd26 tms ta set 0000013H taconst init swct modelO save setup model tms tb set 0000014H tb const init cmd10 save_setup mode10 cmd1 model tms kc set 0000015H Ginit_pid mode10 tms kcb set 0000016H tms bt set 0000017H init pid model0 tms bi set 0000018H init pid model0 tms mode set 0000019H Mode isr mode cmd27 tms swp 120 set 000001aH tms command set 000001bH init swct save setup command L R sw L R posit set 000001cH Local remote sw posit L R sw Vref desired set 000001dH front panel desired Vref L R_sw timel UMIN set 000001eH init pid model0 UMAX set 000001fH init pid model0 Vdiff set 0000020H Vout Vref
55. eated by inserting C code into assembly language programs that do not follow the stated register convention stem from the fact that the C programming language was designed to operate independently of system architecture Ref 12 The compiler chooses which registers to assign values to often based on some type of least cost algorithm The compiler s algorithm decides which registers to save and restore at the time the program is compiled The C language does not have provisions for mandating which registers are stored and which are not This means that the calling assembly program would know which registers the C module would save and restore based on Table 5 1 but not which registers the C module would use or modify 42 The first attempt at calling a C function from the assembly code failed because of this problem Running the program on the TMS320C30 simulator showed an extensive amount of data that the assembly code was storing in registers for later use was being over written by the C code To try and work around this register saving problem the code was modified so that the calling assembly function saved all the registers before calling the C module and restored them after the return from the C module This created a problem with the passing of variables from assembly to C and back again When all the registers were saved qnd restored each time a C module was called the parameter passing ability from assembly to C was lost I
56. ed to be able to connect two 2 100 kW units together in parallel to create a single 200 kW unit Reference 3 33 contains an algorithm for paralleling two 2 buck cheaper based on decreasing the reference voltage specified by a unit as the unit output current increases droop The droop method worked but wasn t accurate enough for the 200 kW parallel application Personnel at NSWC wanted current sharing accuracy greater than that attainable through the droop method and wanted to eliminate the droop or sag produced in the voltage as load increased To correct this problem a Master Slave control algorithm was developed The basic premise behind the Master Slave algorithm was to use a modified multi loop feedback with a steady state DC term a Proportional plus Integral PI controller on the voltage and a Proportional term on the current to calculate a duty cycle for the Master buck chopper Input and output voltage can be established at one node because the buck choppers are in parallel V in V out V in 2 Y out 2 4 3 4 4 However the individual inductor currents must be summed and the individual output currents must be summed to establish base inductor and output currents jj 1 1 4 5 m bl lout 4 6 The Slave buck chopper duty cycle then mimics the Master s An Integral term is added to remove current error between the Master and the Slave and a proportional term is added
57. ef and end int if sw is now in L from R shutdown and restart in local mode STIRO AR3 L_R posit save current sw posit call cmdO sto shutdown unit restart call read cmd sto restart BR End int update vref LDF RO AR3 tms_Vref get Vref from memory LDI gadcl cs ARO pointer to ADC for front panel LDI ARO RI loads old data inits new read NOP NOP nops for delay LDI ARO RI read in new Vref from front panel A2Dfltr R1 R7 to extract front panel voltage if needed MPYF AR3 tms_descale R1 scale the word to make actual voltage STF R1 AR3 Vref_ desired store front panel as desired Vref SUBF3 RO R1 R2 R2 R1 RO V_desired Vref CMPF 10 0 R2 see if greater than 10V increase BLE no step step LDI 00H AR3 tms stepx set counter to zero MPYF en1 R2 R2 voltage difference 10 FIX R2 make R2 an integer LDI R2 AR3 stopfreq use R2 as number of steps required LDF 10 0 AR vperfreq 10v is the step size LDI Zctrl ARO f LDI Otim1prd RO load 100ms period STI RO AR0 28H load in timer0 LDI timOctrl RO STI R0 ARO 30H init timerO for step BR End int no step LDF R1 AR3 tms_Vref if no step req d save front panel as Vref BR End int remote LDI 30bH IE enable intr 0 1 3 8 9 CMP RO RI see if previous sw posit matches present 90 BEQ End_int if still in remote end intr if sw changed from local and now in remote shutdown and wait for PC command STI RO AR3 L R posit stor
58. entire operation of the program It could no longer just wait for an interrupt from the PC This created two 2 different start up scenarios that had to be accounted for in the code either start up in Local mode or start up in Remote mode The Universal Controller needed to be able to 30 recognize a switch change from Local to Remote or vice versa An internal timer interrupt was set up to check switch position The previous switch position was saved to provide the ability to compare current position sw n with the previous position sw n 1 This created four 4 possible run time scenarios that also needed to be programmed into the code 1 Switch previously in Local stays in Local 2 Switch previously in Local switched to Remote 3 Switch previously in Remote stays in Remote 4 Switch previously in Remote switched to Local The interrupt structure and program flow were changed to cover all of the possible scenarios Figure 4 3 shows a block diagram of the modified program flow allowing for L R switch operation The code is enclosed as a portion of Appendix B On initial power up the program initializes the microprocessor and then checks the position of the L R switch If in Remote the program functions exactly as it did before It waits for an interrupt 3 from the PC continues the initialization process and waits for phase interrupts If the switch was in Local when checked the program jumps to a routine that l
59. es it the speed to execute up to 50 MFLOPS Ref 8 Many functions that are often done with software are performed in hardware by the C30 This architecture allows a high level of parallelism to support pipelining which increases speed The TMS320C30 supports mih addressing modes Six different types of addressing are available in five different modes This gives the C30 the large amount of versatility needed to implement complex control algorithms Texas Instruments provides several support programs with extensive documentation to aid in system development using the TMS320C30 It is this high speed architecture the flexible addressing modes and the extensive support systems that makes the TMS320C30 ideal bi use 1n the PEBB Universal Controller B ARCHITECTURE The TMS320C30 uses a register based architecture It consists of 12 control registers 8 extended precision registers also called accumulators and 8 auxiliary registers This register system give the C30 the flexibility to handle complex tasks using registers for storage By decreasing the number of times the CPU needs to access 17 memory the overall speed of the system is increased The TMS320C30 also contains two auxiliary register arithmetic units ARAU that are used strictly for address calculations The ARAUs can generate two 2 different addresses in a single clock cycle Ref 8 They are used to calculate complex addresses such as addresses with displacement or addresses
60. f and the lower switch on Both switches conducting at the same time would cause catastrophic failure of the unit The ARCP inverter used in this research has circuitry onboard that controls this situation The dead time referred to in tms tb is used to prevent the duty cycle limits of 596 to 9596 from being exceeded Sine theta is determined by the use of a look up table loaded into scratch pad memory and by using the circular addressing mode of the microprocessor A detailed explanation of circular addressing can be found in Reference 8 Below is an example of an instruction that uses circular addressing LDF AR7 IR1 R7 Basically an auxiliary register is used as a pointer to the look up table and an index register is used as a step size index The step size tells the pointer how far to step or index after reading the current value of the table In this case the value of the sine table that pointer AR7 is pointing to is loaded into R7 then the pointer is indexed by the 49 amount in IR1 If the end of the table is reached the pointer circles around and starts at the beginning of the table again The three phases are kept 120 degrees apart by using three 3 different pointers one for each phase and a double circular addressing scheme for the Phase B and C pointers that keeps them tied 120 degrees out of phase with the Phase A pointer Below is the code for the double circular addressing scheme used for one of the Phase B or C interrup
61. g frequency timer 1 LDI AR3 tms_swp RO LDI AR3 tms_swp Rl STI R0 ARO 0 Store LSB of counter 0 STI RL ARO 1 Store LSB of counter 1 LSH 08H RO LSH 08H R1 STI RO ARO 0 Store MSB of counter 0 STI R1 ARO 1 Store MSB of counter 1 NOP NOP NOP LDI AR3 tms_swp_120 R2 checkout LDI 0040H R0 STI RO AROG Latch command LDI ARO l RO AND 000FFH RO Clear all other higher bits LDI ARO D RI l LSH 0008H R1 AND 00f00H R1 OR RLRO CMPI R2 R0 BGT checkout LDI AR3 tms_swp RO STI RO AROQ Store LSB of counter 2 LSH 0008H RO STI RO ARO 2 Store MSB of counter 2 LDI ct_phasea ARO Pointer for phase a counter LDI AR3 tms_btime R1 STI RL ARO 0 Store LSB of counter 0 LDI AR3 tms_bdly R1 ADDI AR3 tms_btime R1 STI R1 ARO 1 Store LSB of counter 1 LDI AR3 tms _ ta R1 STI R1 ARO 2 Store LSB of counter 2 LSH 08H R1 STI R1 ARO 2 Store MSB of counter 2 LDI Oct phaseb ARO Pointer for phase b counter LDI AR3 tms_btime R1 73 isr_mode mode cm modeo STI R1 ARO 0 Store LSB of counter 0 LDI AR3 tms_bdly RI ADDI AR3 tms_btime R1 STI R1 ARO0 1 Store LSB of counter 1 LDI AR3 tms_ta Rl STI R1 ARO 2 Store LSB of counter 2 LSH 08H R1 STI R1 ARO 2 Store MSB of counter 2 LDI gct phasec ARO Pointer for phase c counter LDI AR3
62. graduate School Monterey California 93943 5121 David Lo PIOOdGeti o eoo aci 2 137 Moreell Circle Monterey California 93940 115
63. hat called C modules ended up longer and more complex than the original assembly code The final program still lost register information that prevented it from running properly when switching from assembly code to the C environment and balas It was decided the assembly language program would have to be rewritten to allow the interface with C code modules Extensive changes in the use of the registers by the assembly code would have to be made The time required to do this proved too great for this thesis research Another option would be to write the entire program in C This would require extensive research of the TMS320C30 s online C run time libraries and a thorough understanding of the C programming language Then C modules could be written to initialize the microprocessor provide the required interrupt structure and initialize the Universal Controller counter timers as needed for control algorithm implementation This also proved too time consuming for this research effort The decision was made to implement the closed loop ARCP inverter algorithm in assembly language VI ARCP CONTROL A BASIC ARCP INVERTER OPERATION The topology and operation of an Auxiliary Resonant Commutated Pole ARCP inverter is described in Reference 13 An operational unit was designed by individuals at the Applied Research Laboratory Penn State University and delivered to the Power Systems Laboratory at NPS It is designed to convert DC voltage int
64. imerl Discharging circuit timel PUSH RO PUSHF RO PUSH ARO LDI gd output ARO LDI OFFH RO SII RO ARO a LDI 000H RO LDI ctrl ARO SII R0 AR0 30H Clear counter ANDN mask_timer E Disable timer interrupt POP ARO POPF RO POP RO RETI jrs0 Phase A interrupt service routine isrO for closed loop control of ARCP resonant converter written by David Floodeen 106 isr0 PUSH ST Save registers PUSH IRI PUSH R7 PUSHF R7 PUSH R6 PUSHF R6 PUSH RS PUSHF R5 PUSH R4 PUSHF R4 PUSH R3 a PUSHF R3 PUSH R2 PUSHF R2 PUSH Rl PUSHF RI PUSH R0 PUSHF RO PUSH ARO LDI Qacs ARO Pointer for phase a A D converter LDI bcs AR2 Pointer for phase b A D converter LDI ARO RO initiate a new conversion don t use these values they are time late LDI AR2 R1 LDI 00cH R2 delay loop to allow time for the slower A D converters wait SUBI 0O1H R2 BNZ wait READ and STORE SAMPLED CURRENTS LDI ARO RO READ Va AND ia LDI AR2 R2 Read Vb and ib Get ja and ib Assuming ia is msb of A D word as in Tuan s code LSH 04H RO ASH __ 14H RO i FLOAT RO RO ia LSH 04H R2 ASH 14H R2 FLOAT R2 R2 ijb x ok ok ole ale ole ole ale OK ale ale This section scales the A D current using a scaling factor to make them actual currents Final output of this section RO ja R2 1b assuming tms acscale is set to the c
65. ke Windows with its graphical user interface DOS relies on a series of commands entered at command prompt to govern operation Below is an example of a DOS command prompt 59 CA gt The C refers to which drive is the current working drive and the backslash Y with no other directories after it indicates that the computer is working in the root directory The C drive is usually the computer s hard drive or primary memory storage Commands usually letters or short words typed from a keyboard directly after the command prompt direct the computer s operations For the purposes of this Appendix the command prompt is shown with each command discussed Commands entered by the user are in boldface and are directly related to using the support programs required for this thesis After applying power to the computer PCPWR3 the system boots up and the command prompt appears on the scr en To obtain a listing of directories present on the C drive type dir and press enter CA gt dir The screen will scroll through a listing of all files and sub directories located in the root directory On PCPWRS the list is too long to fit on the screen To view the list one page at a time type C gt dir p This will display the entire listing one page at atime The files consist of a filename followed by an extension For example on the file npsbuck asm npsbuck is the filename and asm is the extension DOS filenames are
66. ledge of DOS is invaluable for performing research involving the Universal Controller The most helpful commands have been discussed in this Appendix A more thorough explanation of the workings of DOS and DOS commands is contained in Reference 17 an MSDOS 6 User s Guide 64 APPENDIX B BUCK CHOPPER CONTROL CODE oleada ad ode ke ad ale ale de ale a ode ale al ok ade ade oe ode okc ak oke ad ST SESS ETS ole e de ade ode ole ade E E E E E E E ad ad ad ale ale ae ad ale ale NPS POWER LAB TMS320C30 SSCM CONTROL CODE BY RON HANSON MODIFIED FOR PARALLEL OPERATION BY BOB ASHTON NPS Theoretical ROGER COOLEY NSWC Coding Single Interupt Zero phase difference OVER CURRENT UNDER VOLTAGE OVER TEMP LOCAL REMOTE SWITCH OPERATION BY DAVID FLOODEEN Y 4 NX X XX Y Y F He KH X Y EF sk ok ok ok ade ok ale ade oke ok ok Ak ale ok ad ade ok ok ade al ale ale oke ok ok oK ade ale ale ak o ade ade ad de ale ak al ae ok oe 3k 3k k k ak dd k OK e a a OK KO oe title BUCK global init Joe cee nee nnn een e nen n nnn nnn en EPROM Config global reset global int0 intl int2 int3 global tintO global isr0 isr1 isr2 isr3 global time0 nens END EPROM global SIN FPINV FDIV divi menm dii ae di db m inb un eB Hi UR Que quu apu qn ipo eq up Us E ut IE B ji qum UV VD VE VA UP CUP TP VUE UOCE VP GUI VU VU DV V OV UD UU UD OD D OD UO C UD UU UR A2Dfltr macro SRC MSB Takes two 12bit values in b0 b11 LSB and b16 27
67. limited to eight 8 characters and can be either upper of lower case DOS is not case sensitive Extensions are used to define the file type Table A 1 lists the DOS extensions most used in this thesis work and the meaning of each extension 60 Eten Meaning o obj output file produced by converting an object file into the format needed to program EPROMS command file used to link format information to the assembly code for inclusion in the object code batch file of executable instructions Table A 1 DOS Extensions Assembly language code that 1s to be assembled must have the filename extension asm and C language code that 1s to be compliled must have the filename extension c This code may be written using any text editor the user is familiar with as long as it is saved with the proper extension As described in Reference 3 the C compiler and the Assembly language assembler are loaded on PCPWRS in the DSPTOOLS sub directory on drive C To switch computer operation to this sub directory type CHA gt cd dsptools The cd stands for change directory and the command prompt will change to indicate the new working directory CADSPTOOLS gt The user is now ready to run the batch file npsbuck bat as described in Reference 3 61 C BATCH FILES Batch files are files that consist of a series of executable DOS commands To run a batch file the user simply needs t
68. loodeen 7 PERFORMING ORGANIZATION NAME S AND ADDRESS ES Naval Postgraduate School ORGANIZATION Monterey CA 93943 5000 REPORT NUMBER SPONSORING MONITORING AGENCY NAME S AND ADDRESS ES 10 SPONSORING MONITORING AGENCY REPORT NUMBER SUPPLEMENTARY NOTES The views expressed in this thesis are those of the author and do not reflect the official policy or position of the Department of Defense or the U S Government 12a DISTRIBUTION AVAILABILITY STATEMENT 12b DISTRIBUTION CODE Approved for public release distribution is unlimited 13 ABSTRACT maximum 200 words The objective of this thesis is two fold The first goal is to expand the operational capabilities of the Ship s Service Converter Module control algorithm for a DC to DC converter using the Universal Controller The second goal is to investigate the use of the Universal Controller to implement a closed loop control algorithm for an Auxiliary Resonant Commutated Pole ARCP power inverter These power electronic devices are central to the development of a DC Zonal Electric Distribution System DC ZEDS that is scheduled for application in the twenty first century surface combatant SC 21 The development of appropriate control algorithms is a key element to this design process The Universal Controller is a digital controller that was developed by personnel at the Naval Surface Warfare Center NSWC Annapolis Maryland The basic operation of the Universal Controller and the Texas In
69. n order for the C code to use any values with which to make any calculations the values first had to be saved in memory locations accessible to the C module upon which they could then be modified by the C code and finally saved back in memory prior to returning to the assembly code This complex scheme of saving all parameters in memory then saving all registers on the stack prior to calling C code then restoring all registers from the stack and finally changing those values modified in memory proved more complex than just using the original assembly code When this code was run on the simulator data was still being lost due to a memory issue caused by the hardware Some of the values needed by the C code had to be read from the A D converters on the Universal Controller As stated earlier these A D converters have memory locations assigned to them and conversions are initiated by reading these locations However the memory map used by the TMS320C30 and therefore used by the compiler identified these locations as illegal memory locations and would not allow C memory 43 pointers to be assigned to them In order to initiate conversions of the required input data the microprocessor had to be forced to read these locations with assembly code After several weeks of trying to work around the register saving problem and the variable passing problem it was decided to abandon the C code The final program written in assembly language t
70. n sin table tms 23 set 000001cH tms fractor set 000001dH UMIN set 00000leH UMAX set 000001fH INA set 0000020H INB set 0000021H INC set 0000022H iq int set 0000023H __ running total of iq integral id int set 0000024H _ running total of id integral iqq set 0000025H _ difference between iqe and ige idd set 0000026H difference between ide and ide T2 se 0000027H tau 2 for use in integrating tms ige set 0000028H commanded value iqe tms ide set 0000029H commanded value ide Kpq set 000002aH constant for closed loop Kiq set 000002bH constant for closed loop Kpd set 000002cH constant for closed loop Kid set 000002dH constant for closed loop c vl set 000002eH di set 000002fH DC input d v set 0000030H_ x i set 0000031H J Xtravandi ADC x v set 0000032H vperfreq set 0000033H Volt per frequency ratio stopfreq set 0000034H Target frequecy stopvolt set 0000035H Target voltage tms invdv set 0000036H tms dtset set 0000037H dmax set 0000038H i dmin set 0000039H tms_tboost set 000003aH tms_acscale set 000003bH tms dcscale set 000003cH f tms intbits set 000003dH tms outputb set 000003eH tms ilmin set 000003fH tblsize set 000001aH Setup table size ports word 0804500H Pointer for i o ports ct swfreg word 0804000H Switching frequency timer ct port word 0804100H __ Timer contr
71. nal timer interrupt sqrt2 float 1 414213562373 sqrt3 float 1 73205080757 sqrt3 3 float 0 57735026919 sqrt23 3 float 1 15470053838 half float 0 5 half12 float 2048 invllbits float 0 00048828125 tenu float mil bi umax umin float acdcconst float acdchalf float acdcmax float acdcmin float Zero ave Set Set tbmax tbmin float 0 float 0 2 float 0 05 0 05 0 009765625 0 00048828125 0 00001 0001 1 0 1 0 float 0 0 float 0 2 40 10 gt gt 3 gt gt 96 LOU cmd usect dualport 10000h ctio usect xbus 2000h lookup usect ram1 400h varible usect ram2 400h text ST CPU status register IE CPU DMA interrupt enable flags IF CPU interrupt flags IOF I O flags x 9S Y HF The status register has the following arrangement Bits 31 14 131211109 876543210 Function Resrv GIE CC CE CF Res RM OVM LUF LV UF N ZV C RO RI R2 R3 R4 R5 Saved during interrupt 0 1 2 R6 Saved during interrupts 0 1 2 R7 Saved during interrrupts 0 1 2 ARO ARI AR2 AR3 POINTER FOR INTERNAL MEMORY BLOCK 1 do not change AR4 POINTER FOR DUAL PORT MEMORY do not change ARS POINTER FOR INTERNAL MEMORY BLOCK 0 do not change AR6 POINTER FOR SINEWAVE LOOKUP TABLE do not change AR7 POINTER FOR SINEWAVE LOOKUP TABLE do not change TRO IR1 Saved during interrupts 0 1 2
72. nd currents load previous Vd2 n 1 previous Vd1 n 1 and Vdint2 n 1 and Vdint1 n 1 calculate duty cycie load duty cycle een jM c counter 2 register CALL mode10 CALL mode10 store Vd2 n and store Vd1 n and Vdint2 n return from interrupt Vdint1fn clear interrupt clear interrupt Figure 4 4 Program Flow for Dual Buck Chopper Operation Ref 3 The actual designation of which buck would be the Master and which would be the Slave is purely arbitrary Interrupt subroutine O was modified to control the Slave and interrupt subroutine 1 was modified for the Master The actual encoding of the algorithm the integration etc was performed as it was in Reference 3 The program flow was changed as illustrated in by Figure 4 5 36 PLD A interrupt routine PLD B interrupt routine wait for interrupt Master pie vollag and currents load terms needed for sample voltages and currents load terms needed for integration mode10 integration Vd2 n 1 and int calculate Master duty cycle update Slave duty CALL mode10 cycle as needed load Master duty cycle into C T3 s counter 2 register load Slave duty cycle into C T2 s counter 2 register check duty clycle for proper range store terms needed for future integration clear interrupt store Vd2 n and Vdint2 n return from interrupt clear interrupt Figure 4 5 Master Slave Modified Pr
73. nd in Chapter 5 of Reference 3 The next step was to close the loop on the control algorithm C CLOSED LOOP CONTROL 1 Theory Closed loop control as mentioned earlier is a method of controlling a system that uses a portion of the output fed back to modify system operation This is done to reduce or eliminate transients and steady state inaccuracies caused by a changing load or changing inputs Closed loop control can be accomplished by using either a current control mode or a voltage control mode The current control mode was selected in this case because the ARCP inverter already has sensors in place that provide scaled measurements of the system currents The current control mode allows the inherent limiting of the current flowing through the semiconductor switches Control signals for the ARCP inverter can be established b regulating either stationary reference frame quantities or synchronous reference frame quantities As discussed 1n Reference 2 using commanded quantities in the synchronous reference frame are preferred over the stationary reference frame because the steady state commanded values are DC levels in the synchronous reference frame In other words when operating in the synchronous reference frame and in a steady state no perturbations present the error term produced by a PI controller will be zero The annotation for the control algorithm is shown in Table 6 1 51 Superscript s stationary reference fram
74. ng the count in these three 3 counters changes the duty cycle of the controlled solid state switches The duty counts calculated by the control equations are loaded into these counters The output pulses of these three counters go to optical transmitters via three 3 PALs that convert the timer outputs into the necessary control signals for the SSCMs or SSIM switches Further details on the actual loading of these counter timers and count calculation details can be found in Reference 7 13 D OPERATIONAL OVERVIEW The process of operating the Universal Controller can be divided into several steps The EPROMS are programmed loaded into the Universal Controller CPU board and power is applied The next step is to load the operation and control values from the host PC and begin operation Once the program is running phase interrupts generated by the switching frequency timer will run the control algorithms The Universal Controller will continue operating in this interrupt driven mode until the unit is shut down Operation begins with loading the operating code for the microprocessor onto the EPROM s To do this the code is assembled linked converted to the proper format and burned into the PLDs The assembler is loaded on PCPWRP 8 located in Bullard Hall room 114 This is an older PC that uses DOS 3 x as an operating system This machine is still used to assemble the code because it also has the ALL 03A Universal Programmer and Teste
75. nitialized 0 assumming T 2 T 2 is calculated already LDF RO R2 RO R2 iqq ADDF AR3 iqq R2 R2 iqq n 1 iqq n STF RO AR3 iqq store iqq for next time MPYF AR3 T 2 R2 R2 T Z iqq n 1 iqq n ADDF AR3 iq int R2 R2 iq int n 1 T 2 iqq n 1 iqq n 108 STF MPYF MPYF ADDF LDF ADDF STF MPYF ADDF STF MPYF MPYF ADDF MPYF3 R2 R7 RO MPYF3 R3 R6 R1 ADDF MPYF3 R3 R7 RI MPYF3 R2 R6 R4 SUBF LDF MPYF MPYF MPYF LDF SUBF3 SUBF SUBF3 SUBF MPYF ADDF FIX MPYF ADDF FIX MPYF ADDF FIX R2 AR3 iq int store iq int for next time AR3 Kiq R2 AR3 Kpq RO RO R2 R2 Vqe R1 R3 R1 R3 idd AR3 idd R3 R3 idd n 1 idd n R1 AR3 idd store idd for next time AR3 T_2 R3 R3 T 2 idd n 1 idd n AR3 id_int R3 R3 id int n 1 4 T 2 idd n 1 cidd n R3 AR3 id int store id int for next time AR3 Kid R3 AR3 Kpd R1 R1 R3 R3 Vde This section transforms Vqe and Vde to Vqs and Vds RO Vqe cos theta R1 Vde sin theta R1 RO RO Vqs R1 Vde cos theta R4 Vge sin theta RA RI R1 Vds FThis section transforms Vqs and Vds to Va Vb Vc assumes half 5 sqrt3 1 7320508 zero 0 0 RO R3 Vqs R0 R3 Va half RO R0 5Vqs half R1 R1 5Vds sqrt3 R1 R1 root3 Vds 2 zero R2 R2 0 0 RO R2 R4 R4 5Vqs R1 R4 R4 5Vqs root3 Vds 2 Vb R3 R2 R5 RS Va R4 R5 RS Va Vb Vc This section calculates new d
76. not shown in Figure 3 1 is an XDS Emulator This is a hardware device that allows full speed program execution of TMS320C3x programs The Power Systems Lab at the Naval Postgraduate School NPS does not have this piece of hardware so it will not be discussed in detail here As has been shown numerous resources are available from Texas Instruments to aid in the development of a TMS320C3x system The C30 has a flexible instruction set with many addressing modes to allow flexibility in programming control algorithms The architecture utilizes extensive paralleling to provide the speed needed for DSP control algorithms The utilization of these characteristics as applied to buck chopper control is discussed in the next chapter 22 IV BUCK CHOPPER APPLICATIONS A INTRODUCTION A major component of the DC ZEDS system is the Ships Service Conair Module The SSCM is a feedback controlled buck chopper used to step down a DC voltage to a lower level Figure 4 1 shows a basic schematic of a buck chopper A buck chopper uses an electronic switch to chop an input DC voltage and an LC filter to eliminate the high frequency components to produce a lower average DC value Figure 4 1 Buck Chopper Basic Schematic Ref 3 In present Navy shipboard designs the electronic switch is an Insulated Gate Bipolar Transistor IGBT Control signals applied to the gate of the electronic switch change the duty cycle of the switch and change the aver
77. o three phase 34 AC using auxiliary semiconductor devices to implement soft switching Below is a circuit block diagram of one phase of the ARCP inverter LIFTS Current Out Sink pper Gale C ment ri dad ane a Detection aps E Circuitry 4 Tis DU E Control Figure 6 1 ARCP Inverter Circuit Block Diagram Ref 14 The inverter has two primary switches and two auxiliary switches for each phase The inverter operates by applying a changing control signal to the gates of these electronic switches Each phase has two main drive circuits and two auxiliary switch drive circuits Control signals from the Universal Controller act as inputs to the main drive circuits via 45 optical links An inner control loop on each phase senses the direction of current flow and controls the operation of the auxiliary switches Ref 13 During half the cycle the pump drive circuit turns on the lower auxiliary switch and the inverter sources current During the other half cycle the sink pump circuit is operating the upper auxiliary switch and the inverter is a current sink Onboard controls which may be overridden dictate the firing of the auxiliary devices If the auxiliary device controls are not overridden control of the unit can be accomplished by merely controlling the signal sent to the six 6 main electronic switches and will be discussed below B OPEN LOOP CONTROL The open loop control program provided by NSWC initializes the
78. o type the name of the file For example to run the batch file that assembles the file npsbuck asm the user must type C DSPTOOLS gt npsbuck As outlined in Reference 3 Appendix C the input filename is required to be npsbuck asm A listing of the actual batch file explains why this is the case To view the batch file the following command is entered at the command prompt C DSPTOOLS gt type npsbuck bat The batch file will then be displayed on the screen asm30 npsbuck asm s l q Ink30 npsbuck obj npsbuck cmd hex30 I npsbuck The first command assembles the file named npsbuck asm The letters after the filename are different options available with the assembler and are defined in Reference 8 For instance the l tells the assembler to create a listing file and the q suppresses the banner and all progress information during assembly Ref 8 The second command links the object file produced by the assembler with the command file named npsbuck cmd The final command converts the object code into the proper hex format necessary to program an EPROM The specifics of each instruction and their various options are described in Reference 8 62 Batch files are very versatile They can be written to perform a myriad of functions To edit a batch file use the DOS command edit The following 1s typed at the command prompt C DSPTOOLS gt edit npsbuck bat An onscreen editor will appear with the contents of the batch file displayed
79. oads the default table into memory and then continues the program waiting for interrupts When an interrupt is received if it is a phase interrupt i e intO the program runs the appropriate control algorithm encoded in the interrupt subroutine as before Only if the interrupt is from the internal timer does the code change again 31 Initialize the Microprocessor Local Remote Check Local Remote Wait for interrupt from switch PC Load Default values from memory and continue When interrupt 3 is received load control values from PC and continue Wait for an interrupt Check type of interrupt Phase Interrupt Perform control algorithm L R Switch Interrupt from internal timer 1 Check Switch Position Check previous position Check previous position Remote Remote Remote Local Local Remote Local Local Shut down Restart in Local Update Vref Shut down RETI wait for command from PC Ramp if needed RETI Figure 4 3 Program Flow with Local Remote Switch When an interrupt is received from the internal timer the timer 1 subroutine takes over First it reads the previous switch position from memory then gets the current switch position Zero 0 1s used for remote and one 1 for Local mode From 32 there it branches to the appropriate section based on current switch position Once in the appropriate section of code ei
80. odules as long as the variables used by the C compiler are prefaced with an underscore _ in the assembly code For example a variable used by C code called newcount eh to be listed as newcount in the assembly language code and defined in the dss section of the source code This rule applies to all constants variables and module names called by the C code This is because the C 40 compiler automatically prefaces all variable names called by a C function with an underscore _ so for the two codes to work together this convention must be followed This naming convention was easily complied with by simply changing variable names in the assembly code If any of the variables were overlooked it became evident during the linking process when unknown variable errors surfaced Further editing then allowed for error free compiling and linking The second requirement for interfacing code the register usage variable passing convention proved more difficult to implement E PROBLEMS WITH IMPLEMENTATION IN EXISTING CODE In order for C code modules and assembly modules to communicate strict register conventions must be followed Ref 9 Table 5 1 summarizes the C compiler s register use and preservation conventions Register Use by Compiler Preserved by Call RO Scalar Return Values Nod R1 R3 Integer and Floating Point Expressions R4 R5 Integer Register Variables Yes N N Y R6 R7 Floating Point Register Y
81. ogram Flow 3 Findings The Master Slave control algorithm performed satisfactorily on the 20 kW buck dopa nits in the Power Systems Laboratory Room 100A in Bullard Hall However when tested on the 100 kW units at NSWC a problem was discovered It was found that a circulating current due to the 180 degree phase shift was running from one buck to the other and was causing an error in the current readings measured during the 37 two 2 different phase interrupt subroutines As the total load current increased this differential current also increased and disrupted the proper current sharing desired by the two 2 units Mr Roger Cooley changed the program to read all values and perform all duty cycle calculations for both the Master and the Slave buck choppers during one phase interrupt This zero phase difference design and code improved the performance of the Master Slave algorithm This code is also listed in Appendix B Thus far all the programs for the control algorithms run by the Universal Controller have been written in assembly language These programs are quite lengthy and complex A high level language such as C would increase readability of the code and reduce the time required for other researchers to understand the program operation The next phase of this research dealt with investigating the use of C language programs for the Universal Controller 38 V C PROGRAMMING ISSUES A INTRODUCTION There are
82. ointer for command address L R sw ADDI R1 RO XL R sw BNZ RO XL R sw stopinit RETS XL R sw ck cmd LDI AR4 1 RO Check command from the PC L R sw AND OOFFH RO Clear all other bits L R sw CMPI 01EH RO XL R sw BHS stopinit Ignore command if command gt 30 L R sw BR addr L R_sw sk de ok ok ode ok ade ade ale ok ale ade ale aj de SLES ESE SS ale ale ale ok ale ade ole ak ale startemd BR cmdO Off BR cmdO Test Mode BR cmdO AC to DC control BR cmdO Motor Control Forward BR cmdO Motor Control Reverse BR cmdO Actuator Control Open BR cmdO Actuator Control Close BR cmd0 Actuator Control Open BR cmdO Actuator Control Close BR cmdlO DC to DC Boost BR cmdl0 DC to DC Buck BR cmd0 BR cmdO BR cmd0 BR cmdO BR cmd0 BR cmdO BR cmd0 BR cmd0 BR cmd0 BR cmd0 BR cmdO BR cmdO BR cmdO BR cmdO BR cmd0 3 BR cmd0 Stepx BR cmd AC output voltage BR cmd0 Boost time BR cmdO Set current boost limit 68 BR cmdO BR cmdO RETS Turning off ARCP cmdO LDI OSH IE _ Disable interrupts 0 1 2 LDI ct_port ARO _ Pointer for counter timer control register LDI clear main RO STI RO ARO Disable all output STI RO AR3 tms_outputb LDI 030H RO wait20 SUBI O1 H RO BNZ wait20 LDI greset out RO STI RO ARO Disable all counter timer output CALL init_ct LDI 00H RO STI RO AR4A 1 LDI dp int RO STI RO AR4
83. ol register ct phasea word 0804200H _ Phase A timer ct phaseb word 0804300H _ PhaseB timer ct phasec word 0804400H Phase C timer d output word 0804500H General purpurse digital output port d input word 0804600H General purpurse digital input port dac 1 word 0804700H Digitalto Analog converter 1 dac 2 word 0804800H Digitalto Analog converter 2 inputcs word 0804900H Input voltage and current ADC acs word 0804a00H Phase a output voltage and current ADC bes word 0804b00H Phase b output voltage and current ADC 95 ccs word 0804c00H adcl_cs word 0804d00H adc2_cs word 0804e00H cmd ad int startemd x mode ad intmode cmd mask _int0 set 0000001H mask intl set 0000002H mask int2 set 0000004H mask int3 set 0000008H mask timerO set 0000100H mask timerl set 0000200H x clear main word 0004444H reset out word OO0ffffH allon set 0000000H a on set 0000000H a a3 set 0000001H a a4 set 0000002H b on set 0000000H b a3 set 0000004H b a4 set 0000008H c on set 0000000H c a3 set 0000010H c a4 Set 0000020H Define constants one pi two pi float Swp const word 10000000 we woe gt float 3 14159263590 6 28318530718 Phase c output voltage and current ADC ADC 1 ADC 2 3 Set external interrupt 0 Set external interrupt 1 Set external interrupt 2 Set external interrupt 3 Set internal timer 0 interrupt Set inter
84. ower is stepped down using Ship s Service Converter Modules SSCMs that act as buffers for the zones The power is then further stepped down using more SSCMs or converted back to AC using Ship s Service Inverter Modules SSIMs DC power distribution can increase survivability by speeding up the fault detection and switching process and because DC ZEDS requires significantly less cabling and essentially no transformers it is projected to produce large savings in both the weight and the cost of next generation ships Ref 1 The SSCMs are actually buck chopper converters that are used to step down and regulate the DC voltage entering the zone The SSIMs are Auxiliary Resonant Commutated Pole ARCP inverters that convert the DC into three phase 30 AC Ref 2 Both SSCMs and SSIMs require feedback control and monitoring to be useful in a DC ZEDS environment because the systems must be stable and allow for fast transient response in the dynamic environment aboard U S Navy ships Digital control has proven to be more flexible due to the ability to modify the control algorithm with simple software changes vice the extensive hardware changes required in analog systems For DC ZEDS to be successtul effective control algorithms for SSCMs and SSIMs must be developed B RESEARCH FOCUS The focus of this thesis is on using the Power Electronic Building Blocks PEBB Universal Controller developed by the engineers at Naval Surface Warfare Cen
85. p and V7 The PI controller equations are given as follows V sn Kulin Ka findi 6 6 Vj lt Ky iu Ka findi 67 The control voltages are now inverse transformed to the stationary reference frame using the following Dc A These stationary reference frame control voltages V p and V p are then converted to the three different phase control voltages or abc quantities Var War 6 9 Lopes Ba Vip E g PI EN d PI 6 10 Nur Var Vip 6 1 1 Finally the phase control voltages are used to calculate the new duty counts needed to produce the desired three phase 3 AC voltages The equations for 53 calculating duty count are listed below This is the same method used in the open loop operation Equation 6 1 except the phase control voltages are used in place of tb The new duty counts are then loaded into the appropriate counter timers to produce the control signals sent to the ARCP inverter dutycount V p sin0 tms_ta 6 12 dutycount V y sin tms_ta 6 13 dutycount V p sin tms ta 6 14 2 Application The code used to implement the closed loop control algorithm is enclosed as interrupt subroutine 0 of Appendix C Many of the techniques used in previous applications were used in this code The same trapezoidal integration scheme was used for calculating the integrals needed by the PI controller and circular addressing with a sine wave look up table was used for angle
86. r SUBF R4 R5 RS Vdiff n io master io slave LDF AR3 Vin RO CALL FPINV RND RO STF RO AR3 Vin inv STORE 1 Vin LDF AR3 Vdiffa R3 Prepare for Trapzd integration STF R3 AR3 Vdiff by loading old n 1 values into Vdiff LDF AR3 Vd inta RO and Vd int STF RO AR3 Vd int j TRAPZD INTEGRATION from Mode 10 Routine LDF AR3 Vdiff R3 R3 Vdiff n 1 ADDF RS5 R3 R3 Vdiff n Vdiff n 1 85 MPYF AR3 K_slave R3 R3 Vd int K T72 Vdiff n V diff n 1 ADDF AR3 Vd_int R3 R3 Vd int n Vd int Vd int n 1 no Limit the Integrator LDF R3 R7 R7 temp Vd int n ABSF R7 CMPF AR3 tms_dci R7 abs Vd int n Idc BLE NoLim0 Limit reached stop increasing LDF AR3 Vd_int R3 R3 Vd int old NoLim0 NOP RS Save Integ quantities for next time RND R5 STF R5 AR3 Vdiffa RND R3 STF R3 AR3 Vd inta rn Get Master DutyCycle xk ok ak okc ok od ak ak ak ala oe ke ole oe ale k k k k e ov k o oe x x LDF AR3 Vdiffb RO STF R0 AR3 Vdiff LDF AR3 Vd intb RO STF RO AR3 Vd int CALL isr mode EN Save Integ quantities for next time RND R5 STF R5 AR3 Vdiffb RND R3 STF R3 AR3 Vd intb j Write the Master Duty to A phase CTC S1 LDI Act phasea ARO Pointer for phase A counter STI R7 ARO Q Store LSB of counter 2 LSH 08H R7 STI R7 ARO 2 Store MSB of counter 2 p
87. r attached to it which programs the WSI PLDs This allows the code to be assembled and loaded onto the PLDs all on the same system To make the task of programming chips easier batch files have been created A batch file is a DOS file that contains a listing of executable instructions To use a batch file simply type the name of the file and it will execute the necessary instructions Appendix A contains a listing of DOS commands and instructions for creating modifying and using batch files to assemble the code and load the executable object file onto PLDs Once the code is loaded the four 4 PLDs are inserted into the four 4 PROM slots Fig 2 2 as U5 U6 U8 andU9 on the CPU board Then when power is applied to the Universal Controller the software program initializes the microprocessor the 14 memory map the counter timers and the interrupt structure and then waits for a unit on interrupt interrupt 3 in the code from the host PC Reference 3 describes in detail the operation of the host PC and associated software Figure 2 4 illustrates the program flow The unit on interrupt starts the operation of the control algorithms The front panel values are read and loaded into the dual port memory the counter timers C Ts are loaded the rest of the interrupts are enabled and the unit then waits for a phase interrupt to occur Initialize the microprocessor memory and counter timers Wait for an in
88. ral STF R7 AR3 trip m Stores trip m n for next pass 84 LDI cmd_ad R5 Jump target if needed for shutdown LDF limit R6 R6 58 0 integral limit SUBF R6 R7 BNN R5 Shuts down Bucks BR iokm Branch to output current okay clrtripm LDF 0 0 R5 STF R5 AR3 trip m Resets integral if negative iokm LDF AR3 io_master R5 Resets R5 to jo master LDF full R7 R7 116 0 SUBF R7 R4 R4 io slave n 116 0 LDF AR3 io s 116 R7 R7 i0_slave n 1 116 0 STF R4 AR3 io s 116 Saveio slave n for next pass ADDF R4 R7 R7 Sum of n and n 1 LDF AR3 tau 2 RA R4 T 2 MPYF R4 R7 R7 T 2 n n LDF AR3 trip_s R4 R4 previous integral total ADDF R4 R7 R7 Total integral value BN clrtrips Assuring non negative integral STF R7 AR3 trip s Stores trip s n for next pass LDI cmd_ad R4 Jump target if needed for shutdown LDF limit R6 R6 58 0 integral limit SUBF R6 R7 BNN R4 Shuts down Bucks BR ioks Branch to output current okay clrtrips LDF 0 0 R4 STF R4 AR3 trip s Resets integral if negative ioks LDF AR3 io slave RA Resets R4 to io slave Mea kc ale ole ok ke ok ale ok ok ok ale ade ale ale ok ade ok oe ale ale oko oe ok oe oe ok ok ok ok ke oe k ok k ke ke k oe KK ADDF3 R4 R5 RO RND RO STF RO AR3 iout STORE THE TOTAL OUTPUT CURRENT iout ADDF3 R2 R3 RO RND RO STF RO AR3 iL STORE THE TOTAL Inductor CURRENT iL ES Calculate gt Iout_erro
89. ress int3 to PC space 4 Reserved space tint0 word timeO Timer 0 interrupt processing tinti word timel Timer 1 interrupt processing Space 34 Reserved space end EPROM data sram word 0080000H EPROM Beginning of SRAM init cmd BOOT sam word 0084000H BOOT Beginning of Sin Table blkO word 0809800H Beginning address of RAM block 0 init blkl word 0809C00H Beginning address of RAM block 1 init save setup stek word 0809F00H Beginning of stack init ctr word 0808000H Pointer for peripheral bus memory map init cmd10 cmd1 xbus word 0000048H Xpansion bus 2 wait states external init RDY not in use 88 pbus word 0000428H Primary bus 1M bank compare wait init States external RDY not in use timOctl word 3 00003CIH Internal timer 0 1111000001 301 1100000001 timlctl word 00003C1H Internal timer 1 1111000001 301 1100000001 timlprd word 007A120H 7A120H 500000d 10MHz 50 duty 50ms 2 100ms wait4t word 0000100H cmd10 cmd1 dp mem word 0100000H Pointer for dual port memory command reg init save setup dp int word 00003FEH Pointer for setting interrupt flag cmd10 isr mode cmdl dp cint word 00003FFH Pointer for clearing interrupt flag init 76 tms oaci set 0000001H _ Ac trip current level save setup set_oc cmd29 tms acv set 0000002H test tms bdly set 0000003H Boost delay init swct tms btim
90. s TMS320 Floating Point DSP Assembly Language Tools Texas Instruments Inc 1991 11 Texas Instruments TMS320C3X C Source Debugger Texas Instruments Inc 1993 12 Deitel H M Deitel P J C How to Program Prentice Hall Inc 1994 13 DeDoncker R W Lyons J P The Auxiliary resonant Commutated Pole Converter JEEE IAS Annual Meeting Proceedings 1990 pp 1228 1235 14 Mayer J S Salberta F High Frequency Power Electronic Converter For Propulsion Applications Final Technical Report Department of Electrical Engineering and the Applied Research Laboratory Penn State University University Park PA 113 15 Microsoft MS DOS 6 User s Manual Microsoft Corporation 1993 114 INITIAL DISTRIBUTION LIST Defense Technical Information Center at 2 8725 John J Kingman Rd STE 0944 Fort Belvoir Virginia 22060 6218 Dudley Knox LIDEAEV scort ia 2 Naval Postgraduate School 411 Dyer Rd Monterey California 93943 5101 Chairman Code BG uio o eto aerea ea Sa cid 1 Department of Electrical and Computer Engineering Naval Postgraduate School Monterey California 93943 5121 JohmCiezki Code ECON nestor tdo 3 Department of Electrical and Computer Engineering Naval Postgraduate School Monterey California 93943 5121 Robert Ashton Code EC AD oooooccooocccnnononanacacccnoncanccccnoos 3 Department of Electrical and Computer Engineering Naval Post
91. scsscscssscrsncsncesssesesscescseces 59 A PROGRAM DEVELOPMENT SOFTWARE TOOLG scsscsssssssosssssesssccocessscsenseracseccerseseevesnceesees 59 Vu B DOS COMMANDS siii raid ARA EEEa E A n Ea iOS eee 59 C BAICH FILES Deer 62 APPENDIX B BUCK CHOPPER CONTROL CODE csssscossssssesssscossnscossnorsssossnesnsnsssecsecsssecssosensnasens 65 APPENDIX C ARCP CLOSED LOOP CONTROL CODE reseosssesecsssesecosseseeeoasesseseososssosossooesssosssoseas 93 LIST OF REFERENC ES crannan a ESG 113 INITIAL DISTRIBUTION LIST vicioso dais 115 Vill I INTRODUCTION A DC ZONAL ELECTRICAL DISTRIBUTION Downsizing is a reality in the military of today The United States Navy is continually tasked with finding ways to meet operational commitments as well as satisfy the research and development requirements needed to continually upgrade capabilities One area the Navy is investigating is the use of a DC power distribution system for the next generation of ships The project is referred to as DC Zonal Electrical Distribution System DC ZEDS Ref 1 Figure 1 1 shows a simplified block diagram of a proposed DC ZEDS system Zone DC Auctioneer SIBD DC BUS Power distribution under this system is accomplished by rectifying AC into DC as soon as it is generated The ship is divided into zones and the DC power is routed to these zones on two primary DC busses Port DC bus and Stbd DC bus Upon entering the zone the DC p
92. sily be written to take advantage of this 18 parallel architecture Simultaneous use of the single cycle ALU Barrel shifter and parallel multiplier are possible in software Ref 8 The registers the ALU and the parallel multiplier are all supported by an extensive 32 bit internal bus structure designed to allow a great deal of instruction overlap in execution This bus structure is what enables the parallel instruction set In addition to two 2 ARAU address buses and two 2 separate data busses that connect CPU registers to memory another set of separate address and data busses are used for peripherals and yet another for Direct Memory Access DMA It is this extensive bus structure supporting the large amount of paralleling hardware and the flexible register system that makes the TMS320C30 well suited for use in the Universal Controller C ADDRESS MODES Much of the flexibility of the TMS320C30 comes from the instruction set that supports it This instruction set is quite powerful due in part to the numerous addressing modes available for use The C30 supports five 5 different addressing modes and six 6 types of addressing Table 3 1 shows a listing of the different addressing modes and types used by the TMS320C30 Six Addressing Types Register Addressing Direct Addressing Indirect Addressing Short Immediate Addressing Long Immediate Addressing po PC Relarive Addressing Table 3 1 TMS320C30 Addressing
93. strument TMS320C30 microprocessor architecture are described with emphasis placed on the system control algorithms 8 PERFORMING Previous studies have encoded and successfully tested a closed loop control algorithm for a DC to DC converter In this research endeavor this control algorithm is expanded to include various protection circuits and a Master Slave paralleling scheme Finally a closed loop control algorithm for the ARCP inverter is encoded and recommendations for future research are outlined SUBJECT TERMS dc to dc buck converter auxiliary resonant commutated pole 15 NUMBER OF inverter universal controller closed loop control of power inverters texas PAGES 124 instruments tms320c30 16 PRICE CODE SECURITY CLASSIFICA 18 SECURITY CLASSIFI 19 SECURITY CLASSIFICA 20 LIMITATION OF TION OF REPORT CATION OF THIS PAGE TION OF ABSTRACT ABSTRACT Unclassified Unclassified Unclassified UL NSN 7540 01 280 5500 Standard Form 298 Rev 2 89 Prescribed by ANSI Std 239 18 298 102 11 Approved for public release distribution is unlimited USING THE PEBB UNIVERSAL CONTROLLER TO MODIFY CONTROL ALGORITHMS FOR DC TO DC CONVERTERS AND IMPLEMENT CLOSED LOOP CONTROL OF ARCP INVERTERS David L Floodeen Lieutenant Commander United States Navy B S E E San Diego State University 1987 Submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING from
94. tegration method as explained in Reference 3 Several lines of code and some new variables and constants had to be inserted to implement the integration digitally The first step in encoding the over current sense and shut down code was to create a variable named T 2 that is equal to one half the switching period This value is calculated in the cmd 10 subroutine of the buck chopper code provided in Reference 3 but was not saved for later use The following line of code was inserted to accomplish this STF RO AR3 au 2 Store T 2 After saving T 2 several other variables and constants needed to be created Table 4 2 contains a listing of the added constants and variables and their initial values AR RN MINI E ARE ed Table 4 2 Added Variables for Over Current Sense and Shut Down The constant full represents 100 of rated current while limit represents the maximum amount of average over current allowed The terms io m 116 and o s 116 are used to store the output over current or i 116 0 for the master and out 27 slave buck choppers respectively The Riemann sums or average over currents for the master and the slave are stored in trip_m and trip s The final step involved encoding the integral Appendix B contains the entire code for the buck choppers with the over current sense and shut down portion inserted in isrO Since the code for the master and the slave functions exactl
95. ter NSWC to expand the operational capabilities of the SSCM control algorithm and to implement a closed loop control algorithm for the SSIM The PEBB Universal Controller is a two card digital controller designed to handle the extensive Input Output I O requirements needed to control both buck chopper converters and ARCP inverters Closed loop control for a typical ARCP inverter requires the conversion of as many as 10 voltage and current signals and the generation of as many as 12 different control signals These control signals are used to gate on and off the electronic switches and modify the duty cycle The Universal Controller has no user s manual Previous research Ref 3 documented in part how the Universal Controller works and how to implement control algorithms using it Chapter II of this thesis documents in greater detail the actual operation of the Universal Controller The Universal Controller is based on the Texas Instrument TMS320C30 microprocessor This is a general purpose microprocessor designed for DSP applications Chapter III delves into the architecture of this chip and how it gives flexibility to the Universal Controller Previous Ref 3 has included the encoding and successful testing of a closed loop control algorithm for the SSCM the buck chopper Several additional operational features were desired by NSWC Over current protection under voltage protection over temperature protection and the ability to operate
96. terrupt from the PC Load constants from host PC load C Ts enable interrupts Wait for an interrupt Run the apropropriate interrupt subroutine to implement the control algorithm Figure 2 4 Program Flow for the Universal Controller 15 Interrupts drive the system The interrupts occur with the correct phase relationship and at the proper sampling rate determined by the switching frequency loaded in from the host PC The interrupt subroutines sample the required voltages and currents the microprocessor manipulates the data and calculates the duty cycle changes needed to produce the proper outputs The counts loaded into the counters timers that control the switching period of the IGBTs are modified The outputs of these counters produce the control signals that are converted to optical signals and sent out to the SSCMs or SSIM Again all of these actions are controlled by the program run by the TMS320C30 microprocessor The architecture of the TMS320C30 is discussed in the next chapter 16 Ill TMS320C30 ARCHITECTURE A INTRODUCTION The TMS320C30 is the heart of the Universal Controller It is a high speed general purpose microprocessor produced by Texas Instruments It has an architecture instruction set and support system conducive to real time digital signal processing DSP and ideal for application as the center piece of the Universal Controller The TMS320C30 has a 60 nsec single cycle execution time that giv
97. tes a voltage across the lower switch as illustrated in Figure 6 3 The pattern basically may be viewed as a varying duty cycle applied to the devices in the inverter leg The amplitude of the 47 sinusoidal control signal directly dictates the amplitude of the resulting phase voltage Again the switching period of the control signal is determined by the switching frequency entered from the host PC WY time gt time gt Figure 6 3 Sine Triangle Pulse Width Modulation Ref 2 Figure 6 3 shows that as the amplitude of the sine wave approaches its maximum value the duty cycle of the primary switch approaches its maximum When the sine wave Is at a zero value the duty cycle is at 50 and decreases to a minimum at the maximum negative value of the sine wave Equation 6 1 shows the assembly language formula that actually implements this type of modulation and calculates the duty count 48 dutycount tms_tb R7 tms ta 6 1 where R7 value read from a sine wave lookup table tms ta sweep period 2 tms tb sweep period 2 dead time 2 Using ta and tb in this manner has the affect of shifting the sine wave output up so the minimum is at or near zero This is required for implementation because it is impossible to load a negative count or have a negative duty cycle Dead time is used to ensure proper switch operation Dead time usually refers to the time between turning the top switch of
98. the NAVAL POSTGRADUATE SCHOOL September 1998 Author David L Floodeen Approved by Thesis Co Advisor Department of Electrical and Computer Engineering 111 iv ABSTRACT The objective of this thesis is two fold The first goal is to expand the operational capabilities of the Ship s Service Converter Module control algorithm for a DC to DC converter using the Universal Controller The second goal is to investigate the use of the Universal Controller to implement a closed loop control algorithm for an Auxiliary Resonant Commutated Pole ARCP power inverter These power electronic devices are central to the development of a DC Zonal Electric Distribution System DC ZEDS that is scheduled for application in the twenty first century surface combatant SC 21 The of appropriate control algorithms is a key element to this design process The Universal Controller is a digital controller that was developed by personnel the Naval Surface Warfare Center NSWC Annapolis Maryland The basic operation of the Universal Controller and the Texas Instrument TMS320C30 microprocessor architecture are described with emphasis placed on the system control algorithms Previous studies have encoded and successfully tested a closed loop control algorithm for a DC to DC converter In this research endeavor this control algorithm is expanded to include various protection circuits and a Master Slave paralleling scheme Finally a
99. the bucks from a remote front panel were all desired features that were not incorporated in the original 3 buck control code Chapter IV of this thesis contains a discussion of the theory and changes required to implement these features The present SSCM closed loop control algorithm implementation Ref 3 allowed for individual control of multiple buck choppers Problems developed when trying to operate these units in parallel at Power Paragen Inc Anaheim CA One buck had a tendency to take over and try to supply the entire load while the other unit floated at no load The changes made to operate bi buck chopper converters in a Master Slave configuration that provides the proper current sharing required for successful parallel operation are documented and discussed in Chapter IV as well The TMS320C30 has the ability to be programmed in both assembly language and C Closed loop control algorithms use complex mathematical functions to calculate the desired control signals The current encoded control algorithms are written in assembly language This code is lengthy and very complex Great benefits would be derived from using C code functions to implement the control algorithms C code being a high level language uses instructions that more closely resemble common mathematical statements Using C would greatly improve the readability of the software which would in turn facilitate easier modifications The possibility of converting parts of
100. ther Local or Remote it compares the current switch position with the previous switch position to determine which of the four 4 run time scenarios the system is in The bottom of Figure 4 3 shows a brief synopsis of what is done for each of the four 4 cases If in Local and previously in Local the program updates Vref by reading in the front panel voltage initiates a ramp up function if Vref changed by more than 10 volts stores the new Vref and returns from interrupt If in Local and previously was in Remote the program branches to the cmd 0 subroutine and shuts down the system It then starts back up in bos If in Remote and previously in Remote the program merely returns from interrupt Finally if in T and previously in Local the program branches to cmd 0 again to shut down the system and restarts waiting for an interrupt 3 from the PC to run in Remote mode By using the TMS320C30 s internal timer 1 to generate interrupts to check L R switch position throughout operation of the and then changing the interrupt structure to look for this interrupt Local Remote switch operation was encoded into the Universal Controller code The only modification left to add for this thesis research involved encoding a Master Slave algorithm for parallel operation of the buck choppers D MASTER SLAVE PARALLELING 1 Theory The final requirement from NSWC was to investigate and develop a paralleling algorithm that did not require droop NSWC personnel want
101. ties DC ZEDS research is one way of meeting these goals The flexibility of the Universal Controller makes it a key component in the DC ZEDS system and one worthy of further research and development 57 58 APPENDIX A SOFTWARE ACCESS AND DOS COMMANDS A PROGRAM DEVELOPMENT SOFTWARE TOOLS In addition to the assembly programs discussed in this thesis several software programs are required for implementation of this research Appendix C of Reference 3 contains a detailed description of several support programs and their use The programs are stored on PCPWR7 in Bullard Hall Room 114 and are installed in various computers throughout the Power Systems Laboratory Reference 3 outlines how to install and use the Host PC software and how to install or burn code on the EPROMS used by the Universal Controller The Host PC software is written in C and designed for use in a Windows 3 1 operating environment The software required to install code on the Universal Controller s EPROMs is loaded on PCPWRS also located in Bullard Hall Room 114 This is a DOS based system Batch files control much of the software on this system therefore a working knowledge of DOS commands ind batch files is required This Appendix assumes the reader has a basic knowledge of computers and the use of Windows but that the reader has had little exposure to DOS B DOS COMMANDS DOS is the precursor to Windows as an operating system for computers Unli
102. tr R6 R7 R6 io_slave LSB R7 io master MSB ADDF R6 R4 R4 jout_slave 2 83 ADDF R7 R5 RS jiout master 1 Al added ok ok oe oe ke ad oe oe od ae ae dd oe ook ok ae ale ok ok oke ok ok ok oe a e oke ok okc ok e de de ok oke ke oe oko ok ok ae ok okc ok ok kok e xke ke koe ae ke ok ok ok ad x POP AR7 POP AR6 POP ARS POP AR4 POP AR3 POP AR2 POP ARI da Calculate System Voltages MPYF AVE RO MPYF AR3 tms dcscale RO RND RO STF RO AR3 Vin STORE Input voltage Vin MPYF QAVERI MPYF AR3 tms dcscale R 1 RND R STF R1 AR3 V out STORE Output voltage Vout MPYF AVE R2 MPYF AR3 tms_acscale R2 RND R2 STF R2 AR3 iL slave MPYF AVE R3 MPYF AR3 tms_acscale R3 RND R3 STF R3 AR3 iL master MPYF AVE R4 MPYF AR3 tms_acscale R4 RND R4 STF RA AR3 io slave MPYF QAVE R5 MPYF AR3 tms_acscale R5 RND R5 STF R5 AR3 io_master 3k kk dde k k ale ake ak ake ale oc ak ake ae okc ole od ade ale ak ale ad ale ad okc k okcoke okc k ak ak ad ok oe k a ok k OverCurrent Trip Code LDF full R7 R7 116 0 SUBF R7 RS R5 i0_master n 116 0 LDF AR3 io m 116 R7 R7 io_master n 1 116 0 STF R5 AR3 io_m_116 Save io_master n for next pass ADDF RS5S R7 R7 Sum of n and n LDF AR3 tau 2 R5 R5 T 2 MPYF R5 R7 R7 T 2 n n 1 LDF AR3 trip_m RS RS previous integral total ADDF RS5 R7 R7 Total integral value BN clrtripm Assuring non negative integ
103. ts The only difference between the Phase B and Phase C scheme is the value of IR1 For Phase B it is equivalent to 120 degree displacement and for Phase C it provides a 240 degree displacement LDI AR7 AR6 LDF AR6 IR1 R7 LDF AROTT IBL S RI Recall from above that AR7 is the Phase A pointer to the sine table The first line of code copies this pointer to AR6 so that when indexing is done AR7 is not changed AR7 should only increment during the Phase A interrupt Line one of the code prevents AR7 from indexing during the Phase B or Phase C interrupt The next line is a regular circular addressing instruction It loads R7 with the value pointed to by AR6 which in this case equals the current Phase A sine value AR6 is then incremented the appropriate 120 or 240 degrees The circular addressing instruction is then used again to load the desired sine table value with the proper phase displacement into R7 for use in Equation 6 1 This double circular scheme is what allows the duty count for each of the three phases to be calculated during different interrupt subroutines in the program yet remain exactly 120 degrees apart 50 Finally using Equation 6 1 the new duty count is calculated for each phase and loaded in the corresponding counter timers This produces the required modulation signal which is then exported to the primary switches providing open loop operation Further details about open loop operation of the ARCP can be fou
104. ule that called the control algorithm in C The 39 new C code control algorithm could be compared to the already tested assembly language one the buck chopper closed loop control algorithm in Reference 3 to ensure operability and yet provide the flexibility desired for future modifications Then once the code was tested and working on the buck chopper system in the Power Systems Lab the closed loop algorithm for the ARCP inverter would be written in C When completed it would be inserted into the existing program that runs the inverter in open loop mode This approach would avoid the need to write complicated assembly code for the ARCP closed loop algorithm and provide a readable modifiable closed loop algorithm To write C modules that could talk to the existing assembly code several requirements had to be met B C INTERFACE REQUIREMENTS The TMS320C30 supports interlacing assembly language and C code with its onboard C compiler It facilitates the writing of modules both in C and assembly language compiling them both in a single step and linking them together to form one executable object code The two types of code will work together as long as some very specific rules are followed These rules are outlined in Reference 9 pages 4 10 through 4 25 and deal with variable naming and module calling conventions as well as proper register usage and parameter passing schemes used by the C compiler Assembly code modules can call C m
105. urn on and off the solid state gates Also 3 phase power control implies 3 different phase current and voltage measurements that need to be sampled and manipulated Finding an appropriate digital controller that can handle this many I O signals is challenging For this reason the engineers at NSWC designed the Power Electronic Building Block PEBB Universal Controller here in referred to as simply the Universal Controller PEBB is a generic term for solid state switching equipment being developed for Department of Defense DOD systems and Universal Controller implies that this controller is designed to handle a myriad of applications in addition to those discussed in this thesis B GENERAL DESCRIPTION The PEBB Universal Controller is comprised of two basic parts a CPU board and an I O board Figure 2 1 shows a block diagram of the Universal Controller The CPU board is based on the Texas Instruments TMS320C30 DSP microprocessor chip which will be covered in greater detail in Chapter III The CPU board also contains three 3 different types of memory and a microcontroller that directs the interface with the host PC The I O board contains the Analog to Digital A D converters that provide the analog input to the Universal Controller and has several counter timers used to generate interrupts and modify the output control signals from the board DIP SW l CPU Board i 32K X 32 1 EPROM i bo TMS320C30
106. urrent scaling word calculated by Ron Hanson MPYF AR3 tms_acscale RO RND RO RO ia STF R0O AR3 ia STORE ia 107 MPYF AR3 tms_acscale R2 RND R2 R2 ib STF R2 AR3 ib STORE ib This section reads sin theta and cos theta from the lookup table assuming tms cos is block size 4 vice tms 13 or tms 23 LDI AR3 tms_stepx IR1 LDF AR7 IRI R6 R6 sin theta LDI AR3 tms cos IRI SUBI AR3 tms_stepx IR subtract step to compensate for previous increment LDI AR7 AR6 suse AR6 to not further increment AR7 LDF AR6 IR1 R7 sread twice to get desired value in R7 LDF AR6 IR1 R7 R7 cos theta This section converts ia and ib to iqs and ids then to iqe and ide assumes sqrt3 3 root3 3 sqrt23 3 2root3 3 LDF RO RI RO iqs ia Rl MPYF saqrt3_3 R1 R1 r00t3 3 1a MPYF Asqrt23 3 R2 R2 2ro0t3 3 ib SUBF R2 R1 R1 ids root3 3 ia 2root3 3 ib MPYF3 R7 RO R2 R2 1iqs cos theta MPYF3 R6 R1 R3 R3 ids sin theta SUBF R3 R2 R2 iqe iqs cos theta ids sin theta MPYF3 R6 R0 R3 R3 iqs sin theta MPYF3 R7 R1 R4 R4 1ids cos theta ADDF R4 R3 R3 ide iqs sin theta ids cos theta This section calculates iqq and idd LDF AR3 tms_iqe RO SUBF R2 R0 RO iqq iqe ige LDF AR3 tms_ide R1 SUBF R3 RI R1 idd ide ide Integrate using trapazoidal method to calculate iq int and id int and calculates Vqe and Vde assumming iq int id int iqq idd i
107. used in the circular addressing mode which are discussed in a later chapter Being able to separately and simultaneously calculate memory addresses allows a great deal of pipelining Pipelining is the overlapping of instructions being executed by the microprocessor which greatly increases speed of operation In the case of memory access using ARAUS to calculate memory addresses frees up the ALU to perform other tasking while the C30 is reading from or writing to memory An added benefit of using ARAUs comes from freeing the other microprocessor registers which would normally be used for memory address calculations to be used as needed elsewhere in the program In addition to the flexible register system the TMS320C30 has other pieces of hardware that add to its overall speed The C30 has a full function ALU that performs dd on 32 bit integers and 40 bit floating point data in a single clock cycle There is also a Barrel shifter capable of performing up to 32 bit shifts in a single cycle which adds great flexibility for bit manipulation instructions Finally the TMS320C30 has a parallel floating point integer multiplier This multiplier allows floating point operations to be performed in parallel with ALU operations The inputs to the multiplier are two 2 32 bit floating point numbers and the result is a 40 bit floating point number Ref 8 The instruction set of the TMS320C30 is written to support parallel instruction execution so programs can ea
108. utput or both Ref 6 This is what gives the TI 8751 the flexibility to communicate serially with the host PC and yet read from and write to the dual port memory in parallel The TI 8751 microcontroller also contains 4K bytes of Erasable Programmable Read Only Memory EPROM on chip This is used to hold the interface program supplied by NSWC A copy of this code is located on PCPWR 7 a personal computer located in Bullard Hall room 114 This code is what controls the interface between the Universal Controller and the host PC It contains the memory map and instructions used for loading front panel information from the PC into the Universal Controller on start up and it also directs the interrupts generated by the host PC used to initiate and terminate operation of the controller The second major portion of the CPU board is the memory section The memory section can be divided into three parts The three types of memory located on the Universal Controller are 32K of EPROM 32K of Static Random Access Memory SRAM and 1K x 8 bit high speed dual port static RAM The EPROM part of memory is made by connecting four WSI WS57C256F 32K x 8 bit chips in parallel Since the EPROMS have an 8 bit data word and the TMS320C30 uses a 32 bit data bus an address decoder 1s connected to the four WSI EPROMS This allows simultaneous access to the four memory chips and provides a 32 bit data word for the CPU The EPROM memory is used primarily for storage of
109. uty_counta b c R6 R3 R3 Va sin theta AR3 tms ta R3 R3 R3 dutycount a R6 R4 R4 Vb sin theta AR3 tms_ta R4 R4 R4 dutycount b R6 R5 R5 Vc sin theta AR3 tms ta R5 R5 R5 dutycount c 109 This section loads new duty counta b c LDI Oct phasea ARO STI R3 ARO 2 stores Isb of counter LSH 08H R3 STI R3 ARO 2 stores msb of counter LDI Qct phaseb ARO STI R4 ARO 2 stores lsb of counter LSH 08H R4 STI R4 ARO 2 stores msb of counter LDI Qct phasec ARO STI R5 AROQ stores lsb of counter LSH 08H R5 STI R5 AR0 2 stores msb of counter This section clears the interupt and the stack ANDN mask intO IF Clear interrupt 0 POP ARO POPF RO 3 POP RO POPF RI i POP Rl POPF R2 POP R2 POPF R3 POP R3 POPF R4 POP R4 POPF R5 i POP R5 POPF R6 POP R6 POPF R7 POP R7 POP IR1 POP ST RETI Return and enable interrupt jsr1 Phase B interrupt service rountine isrl NOP RETI Return interrupt not used isr2 Phase C interrupt service rountine isr2 NOP RETI Return interrupt not used irs3 Dual port memory interrupt service rountine 110 x isr3 PUSH ST Save registers PUSH DP PUSH IR1 a PUSH R7 PUSHF R7 PUSH R6 PUSHF R6 PUSH R5 PUSHF R5 PUSH R4 PUSHF R4 PUSH R3 PUSHF R3 PUSH R2 1 PUSHF R2 PUSH RI PUSHF RI x PUSH RO PUSHF RO LDI gdp cintIRO LDI ARA I
110. y the same only the code for the master is outlined here First the value of full is loaded into the microprocessor s general register seven R7 then it is subtracted from the output current of the master This creates the value of io m 116 n which is stored for use in the next cycleas io m 116 n 1 Next the previous value of io m 116 is added to the current value and multiplied by T 2 The result represents the change in the average over current for this small portion of time This integral change is added to the previous total to produce the Riemann sum If the sum is negative the sum is reset to zero which assures a non negative integral The sum is stored for use during the next cycle and then compared to the limit If the limit is exceeded the subroutine branches to the cmd 0 subroutine which shuts down the system If the limit is not exceeded the subroutine exits this portion of code and resumes normal operation After coding the protection circuits the next change provides for a Local Remote L R switch for system control and a front panel potentiometer adjustment for reference voltage in Local mode 28 C LOCAL REMOTE SWITCH MODIFICATION 1 Specifications System integrators at NSWC requested that the buck choppers be equipped with some sort of front panel hard wired controls to aid in troubleshooting and maintenance A Local Remote L R switch that can select control of the buck choppers from either
111. ze Vdiff STF RO AR3 Vd intb Initialize Vd int sk 2K ade ole ade ale ok ok ok ok ade ale ade ale ale ade ade ale ade ok ok ale ok ok ale ade ale ok ale ok ale ok ok ok ale ale ade ok ok ale ok ade ale ale ak k k ok xx OverCurrent Trip Code STF RO AR3 io m 116 Initialize io m 116 STF RO AR3 io s 116 Initialize io s 116 STF RO AR3 trip m Initialize trip m STF RO AR3 trip s Initialize trip s sk sk ok ok ke ok ke ok ok ok ke oko ok ade ale EE E E EE EE EEE EE EZ E E Z E E EET EE E EE E EEE ak ok ak ak ak ak ake ake ak ke ak akak 3k ak 3k ak ak 3k a 3 3k ak ake ak 3k EE k K KK k k EEE pulse by pulse Limit to the DAC LDF AR3 tms acscale RO acscale is used as current scalefactor CALL FPINV Generate scalefactor for DC OC Limit LDI AR3 tms_odci R1 Read in DC OverCurrent Limit FLOAT RI MPYF RI RO Scale Threshold Limit Value RND RO FIX RO RO amps to counts scalefactor XOR mask dac RO LDI gdac l1 ARO STI RO ARO Write CurrentLimit to dac 1 LDI dac_2 AR0 STI RO ARO write CurrentLimit to dac 2 71 ie ENT LDF 0 0 RO STF RO AR3 d _ initialize Master dutycycle 3k ode de ale ale ole ole ok ke ok k oe o ook ok ok ade k k ok de ok ade ade ade ae oe o ale al ale ae al oe ale ade ale c o OK a LDI Act port ARO Pointer for counter timer control register LDI 00300H RO 1100000 disable phase C STI RO ARO Enable all counter timer output STI RO AR3 tms_outputb s

View/Open - Calhoun: The NPS

Contents

Download Pdf Manuals

Related Search

Related Contents