RL78/G1E Group Low-Power Control of Analog Block
Contents
1. Address F0162H F0163H After reset 0000H R W Set value 000 H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a ap Set value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remark Write 1 to this bit only when starting serial communication 4 Ports a Port mode registers Select the Pmn pin I O mode m 0 to 2 4 6 7 14 15 n 0 to 7 Address FFF20H After reset FFH R W Set value 9FH Symbol 7 6 5 4 3 2 1 0 PMO 1 PMO06 PMO05 PM04 PM0O3 PM02 PMO1 PMO0O Set value 1 0 0 1 1 1 1 1 Address FFF21H After reset FFH R W Set value BFH Symbol 7 6 5 4 3 2 1 0 PM1 1 PM16 PM15 PM14 PM13 PM12 PM11 PM10 Set value 1 0 1 1 1 1 1 1 Address FFF22H After reset FFH R W Set value 1FH Symbol 7 6 5 4 3 2 1 0 PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 Set value 0 0 0 1 1 1 1 1 Address FFF24H After reset FFH R W Set value F7H Symbol 7 6 5 4 3 2 1 0 PM4 1 1 1 1 PM43 PM42 PM41 PM40 Set value 1 1 1 1 0 1 1 1 Address FFF26H After reset FFH R W Set value FOH Symbol 7 6 5 4 3 2 1 0 PM6 1 1 1 1 PM63 PM62 PM61 PM60 Set value 1 1 1 1 0 0 0 0 Address FFF27H After reset FFH R W Set value 02H Symbol 7 6 5 4 3 2 1 0 PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 Set value 0 0 0 0 0 0 1 0 Address FFF2EH After reset FFH R W Set value FDH Symbol 7 6 5 4 3 2 1 0 PM14 1 1 1 1 1 1 PM141 PM140 Set value 1 1 1 1 1 1 0 1 RO1AN1128EJ0110 Rev 1 10 RENESAS Page 21 of 38 Sep 30 20132. Remark Write 1 to this bit during timer operation to stop the timer operation b Timer clock selection register 0 TPSO Specify 32 MHz fctx 32 MHz as the CK00 operation clock and 4 MHz fcx 32 MHz as the CKO1 operation clock Address F01B6H F01B7H After reset 0000H R W Set value 0030H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPSO o ro ro a ro ra al o op op AW WA O oO oo Ca Ca oo o gt o gt am faam ama a e ap rap ap ap ap ap rap ap ap ap ap ap oc oc oc oc oc oc oc oc oc oc oc oc A a A a A A a A A a A a Set value 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 c Timer mode registers 1 and 3 TMRO1 TMRO3 Set timer mode registers 1 and 3 as follows e Set the operation clock of channel 1 fmcx to operation clock CKO1 set by TPSO e Set the operation clock of channel 3 fycx to operation clock CKO0 set by TPSO e Set the count clock of channels 3 and 1 frc_x to operation clock fick specified by the CKSOn0 and CKSOn1 n to 3 bits e Specify that channels 3 and 1 are used as 8 bit timers not 16 bit timers e Specify only software trigger start is valid other trigger sources are unselected as the start trigger and capture trigger for channels 3 and 1 e Specify the interval timer as the operation mode of channels 3 and 1 e Specify timer interrupt is no
3. RL78 G1E Group Address FFF2FH Symbol PM15 Set value Low Power Control of Analog Block Intermittent Operation b Port registers Address FFFOOH Symbol PO Set value Address FFF01H Symbol P1 Set value Address FFF02H Symbol P2 Set value Address FFF04H Symbol P4 Set value Address FFF07H Symbol P7 Set value Address FFFODH Symbol P13 Set value Address FFFOEH Symbol P14 After reset FFH R W Set value EOH 7 6 5 4 3 2 1 0 1 1 1 PM154 PM153 PM152 PM151 PM150 1 1 1 0 0 0 0 0 Control the Pmn pin output data m 0 to 2 4 7 13 14 n 0 to 5 and 7 After reset 00H R W Set value 00H 7 6 5 4 3 2 1 0 0 0 0 P04 P03 P02 P01 POO 0 0 0 0 0 0 0 0 After reset 00H R W Set value 00H 7 6 5 4 3 2 1 0 0 0 P15 P14 P13 P12 P11 P10 0 0 0 0 0 0 0 0 After reset 00H R W Set value 00H 7 6 5 4 3 2 1 0 0 0 0 P24 P23 P22 P21 P20 0 0 0 0 0 0 0 0 After reset 00H R W Set value 00H 7 6 5 4 3 2 1 0 0 0 0 0 0 P42 P41 P40 0 0 0 0 0 0 0 0 After reset 00H R W Set value 0 H 7 6 5 4 3 2 1 0 0 0 0 0 P73 P72 P71 P70 0 0 0 0 1 0 1 After reset Undefined R W Set value 01H 7 6 5 4 3 2 1 0 P137 0 0 0 0 0 0 P130 0 0 0 0 0 0 0 1 After reset 00H R W Set valu
4. b User option byte 000C1H 010C1H Set the LVD operation mode to reset mode and the LVD detection level Vivi when the voltage is rising to 4 06 V and when the voltage is falling to 3 98 V Address 000C1H 010C1H Set value 73H Symbol 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOCO 1 LVIS1 LVISO LVIMDS1 LVIMDSO Set value 0 1 1 1 0 0 1 1 c User option byte 000C2H 010C2H Set the flash operation mode to HS high speed main mode and select 32 MHz as the high speed on chip oscillator frequency Address 000C2H 010C2H Set value E8H Symbol 7 6 5 4 3 2 1 0 CMODE1 CMODEO 1 0 FRQSEL FRQSEL FRQSEL FRQSEL 3 2 1 0 Set value 1 1 1 0 1 0 0 0 d On chip debug option byte Q00C3H 010C3H Enable on chip debugging and specify that the flash memory data is erased if security ID authorization fails Address 000C3H 010C3H Set value 84H Symbol 7 6 5 4 3 2 1 0 OCDENS 0 0 0 0 1 0 OCDERS ET D Set value 1 0 0 0 0 1 0 0 RO1AN1128EJ0110 Rev 1 10 RENESAS Page 17 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 2 Clock generator a Clock operation mode control register CMC Set the operation mode of the high speed system clock pin to input port Address FFFAOQH After reset 00H R W Set value 10H Symbol 7 6 5 4 3 2 1 0 CMC EXCLK OSCSEL 0 0 0 0 0 AMPH Set v
5. 11 Start TAUO Ch1 counter operation start function R_TAUO_Channe Ll stop TAUO Ch1 counter operation stop function R_TAUO_Channe 13_Start TAUO Ch3 counter operation start function R_TAUO_Channe 13_Stop TAUO Ch3 counter operation stop function r_cg_timer_user c r_tau0_channe 11_interrupt TAUO Ch1 interrupt service function TAUO_WAIT_lus 1 us unit wait function RO1AN1128EJ0110 Rev 1 10 Sep 30 2013 tENESAS Page 27 of 38 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 6 5 Function Specifications The specifications of the major functions used in this application note are described below For details about using the SPI to communicate with the analog block see Sample Code for Performing SPI Communication with Analog Block ROIANII30E 1 main function Declaration void main void Overview Main routine function Parameters None Return value None Description e Initializes the variable output voltage regulator in the analog block Initializes timer array unit 0 in the microcontroller block Executes processing to make the system wait for the output of the variable output voltage regulator in the analog block to stabilize Initializes the A D converter in the microcontroller block Initializes the circuits configurable amplifier Ch1 and D A converter Ch1 in the analog block Starts counting usi
6. For on chip debugging lt gt P130 outputs a high level RL78 G1E R5F10FMx Figure 4 1 Hardware Configuration Caution This circuit diagram is simplified to show an overview of the circuit connections When designing an actual circuit connect pins appropriately so as to satisfy the electrical specifications Connect unused input only ports individually to Vpp or Vss via a resistor R01AN1128EJ0110 Rev 1 10 RENESAS Page 5 of 38 Sep 30 2013 RL78 G1E Group 4 2 Circuits Used Low Power Control of Analog Block Intermittent Operation Table 4 1 shows the RL78 G1E R5FIOFMx peripheral circuits used in this application note and their applications Table 4 1 RL78 G1E R5F10FMx Peripheral Circuits and Their Applications RL78 G1E R5F10FMx Peripheral Application Circuit x Configurable amplifier Used as a transimpedance amplifier that converts the output current 2 from a sensor photodiode to a single ended voltage and amplifies it o D A converter Generates a bias voltage for the configurable amplifier used as a g transimpedance amplifier lt Variable output voltage Generates the power supply voltage for the A D converter regulator SPI Controls SPI communication with the microcontroller block of the RL78 G1E R5F10FMx x A D converter Converts the voltage output from the configurable amplifier used as a 2 transimpedance amplifier to a
7. block via the SPI Figure 1 1 Control Flow RO1AN1128EJ0110 Rev 1 10 RENESAS Page 3 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 2 Conditions for Verifying Operation The operation of the sample code shown in this application note has been verified under the conditions shown below Table 2 1 Conditions for Verifying Operation Item Description Microcontroller used RL78 G1E R5F10FME Operating frequency High speed on chip oscillator high speed OCO clock 32 MHz CPU peripheral hardware clock 32 MHz Operating voltage Vbo DVpp AVpp1 AVppze AV pps 5 0 V AV pp 3 3 V LVD detection voltage Vivin 4 06 V when rising 3 98 V when falling External devices used Photodiode BS520E0F made by Sharp Corporation Integrated development CubeSuite V1 01 01 31 Jan 2012 made by Renesas Electronics environment C compiler CA78KOR V1 30 made by Renesas Electronics 3 Related Application Notes Related application notes are shown below Also refer to these documents when using this application note E RL78 G13 Low Power Operation RO1AN0465E Application Note RL78 G1E Example Measurement Using a Current Sensor R01AN1055E Application Note E RL78 GI1E Sample Code for Performing SPI Communication with Analog Block RO1AN1130E Application Note RO1AN1128EJ0110 Rev 1 10 RENESAS Page 4 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block I
8. OOH R W Set value H Symbol 7 6 5 4 3 2 1 0 PC1 DAC4OF DAC3OF DAC2OF DAC1OF 0 AMP30F AMP2OF AMP10OF Set value 0 0 0 0 0 0 Remark Write 1 to this bit to enable operation of configurable amplifier Ch1 and D A converter Ch1 and 0 to stop operation 10 Power control register 2 PC2 Enable operation of the variable output voltage regulator and reference voltage generator Address 12H After reset OOH R W Set value 02H Symbol 7 6 5 4 3 2 1 0 PC2 0 0 0 GAINOF LPFOF HPFOF LDOOF TEMPOF Set value 0 0 0 0 0 0 1 0 RO1AN1128EJ0110 Rev 1 10 RENESAS Page 16 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 6 3 Settings of Microcontroller Block Registers The register settings specified for the microcontroller block of the RL78 G1E R5F10FMx are shown below This section omits descriptions of the SPI control registers not used in this application note They are used with their default values Caution For how to specify the microcontroller block register settings see the RL78 GIE Hardware User s Manual 1 User option bytes a User option byte OOOCOH 010C0H Disable operation of the watchdog timer counter Address 000COH 010COH Set value EEH Symbol 7 6 5 4 3 2 1 0 WDTINT WINDOW WINDOW WDTON WDCS2 WDCS1 WDCSO WDSTBY 1 0 ON Set value 1 1 1 0 1 1 1 0
9. Block Intermittent Operation Table 5 2 Settling Time of Configurable Amplifier Used as Transimpedance Amplifier 40 C lt Ty lt 85 C AVpp AVpp2 AVpp3 DVpp 5 0 V AMPIOF AMP20F AMP30F 1 Parameter Symbol Conditions Ratings Unit MIN TYP MAX Settling time Ts High speed mode 9 HS CC1 CCO 0 0 Feedback resistance 20 kQ 5 4 3 D A converter settling time When operation of the D A converter is started by setting DACnOF n 1 to 4 to 1 in power control register 1 PC1 after having been stopped by setting DACnOF n 1 to 4 to 0 in PC1 a settling time tsgr is required for the output of the D A converter to stabilize The settling time of the D A converter is measured from the end of SPI command the data that changes the setting of the DACnOF n 1 to 4 bit from 0 to 1 is latched until the output voltage from the D A converter DACn_OUT n 1 to 4 is within 1 0 of the final output voltage The required settling time of the D A converter is shown in Table 5 3 below based on the electrical specifications described in the RL78 G1E Hardware User s Manual Table 5 3 D A Converter Settling Time 40 C lt T4 lt 85 C AVpp AVpp2 AVpp3 DVpp 5 0 V DACIOF DAC20F DAC30F DAC4OF 1 Parameter Symbol Conditions Ratings Unit MIN TYP MAX Settling time tset 100 Us RO1AN1128EJ0110 Rev 1 10 RENESAS Page 11
10. Chl lt l gt Set VRT1 to 0 and VRTO to 0 in the DAC reference voltage control register DACRC to specify AVpp X 5 10 as the upper limit of the reference voltage VRT for the D A converter lt 2 gt Set VRB1 to 0 and VRBO to 0 in the DAC reference voltage control register DACRC to specify AGND1 as the lower limit of the reference voltage VRB for the D A converter lt 3 gt Specify the analog voltage to be output to DAC control register 1 DACIC e In this application note D A converter Ch1 is used to generate a bias voltage for configurable amplifier Ch1 used as a transimpedance amplifier Set the DACIC register to 19H to specify 0 49 V as the voltage output from the DAC1_OUT pin Note that the value set to the DACIC register is a reference value The user needs to evaluate the system to determine the actual values e DAC1_OUT reference voltage upper limit reference voltage lower limit x 2 x m 255 2 x reference voltage lower limit AVpp X 5 10 AGND1 x 2 x 25 255 2 x AGND1 5 x 5 10 0 x 2 x 25 255 2 x 0 0 49 V AVpp1 5 V AGNDI 0 V m DACIC register value 25 19H lt 4 gt Set DACIOF to 1 in power control register 1 PC1 to enable operation of D A converter Chl By executing the above steps D A converter Ch1 starts operating Follow the procedure below to stop D A converter Ch1 lt l gt Set DACIOF to 0 in power control register 1 PC1 to stop operation of D A conver
11. OO ccc vsiet te vo cd ocd pase da aa bedava tree paca dane th ab bebe wie treess ad lexdgcasstaces ai stedevaat ees ddeveeeansdec sa iteevesaes 6 5 Features of the Analog BlOCK vicic cccciccsccccecesccceeeessseedeessceedescacchteesscenceesaceeteeescendeesaccnteessceneteessceeeeeecenteesee 7 5 1 Procedure for Setting the Variable Output Voltage ReQulator ccccceeeeececeeeeseeeeeneeeeeeeees 7 5 2 Procedure for Setting the Configurable Amplifiers cccccccecceeeeeeeeeeeeeeeeeeeseneeeseaeeeseaneneaeees 8 5 3 Procedure for Setting the D A Converter cccccceesceceeeeeceeeeeeaeeeeeeeeceaeeeeaaeeseaeeseeeeseaeessaeeneneees 9 5 4 Analog Block Settling Timme c cccccccescceceeeeeeeeeeeeeeeceaeeeeaaeseeeeeceaeeseaaeseeaeeseneeesaeeeeaaeseeneeeeaeee 10 5 4 1 Settling time of the variable output voltage reQulator cecceeeeeeeeeeeeeeeeeeseeeeseeeteeeeeaes 10 5 4 2 Settling time of the configurable amplifier used as transimpedance amplifier 10 5 4 3 D A converter Settling time cece eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaaeeessaaeaeseeaaeeeseegeneeseesenaees 11 6 SOWA E 5 aisiecs see eel lecaperactsacnpadeceeneesuatleigehpve lt Tea dia utes stdin daara a di adgacdaveusivagialdacduen MastalevadaaiAseatetenent 12 6 1 Timing Chatt possesens ee saed ohbennesceniyseha cdo ana lat weeaed slonaeasceuie ss okquasalidbsledeewagesan shee secede 12 6 2 Settings of Analog Block Registers 0 c cccesc
12. Starts operation of the TAUO Ch1 counter me gt RSF10FMx_Analog _Start Analog block operation start function Has communication No Starts operation of configurable amplifier Ch1 and D A converter Ch1 in the RL78 G1E with the analog block finished RSF10FMx successfully Yes 1 us unit wait function TAUO_WAIT_lus 100 Makes the system wait for the settling time of configurable amplifier Ch1 and D A converter Ch1 at least 100 ps A D conversion control function Controls A D conversion of the voltage voltage stepped down by using a resistor divider output from configurable amplifier Ch1 used as a transimpedance amplifier ADC_Control le R5F10FMx_Analog Stop Analog block operation stop function Flas communication No Stops operation of configurable amplifier Ch1 and D A converter Ch1 in the RL78 G1E with the analog block finished R5F10FMx successfully J Yes HALT The CPU enters HALT mode Figure 6 5 Flowchart for main Function RO1AN1128EJ0110 Rev 1 10 RENESAS Page 33 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 4 Analog block LDO initialization function R5F10FMx_LDO_Enable RSF1 OFMx_ LDO_Enable SPI_ControlRegis ter Write SPI control register write function Writes data to the SPI control register in the RL78 G1E
13. TAUOEN Set value 0 0 1 0 1 0 1 3 Serial array unit 1 a Serial mode register 11 SMR11 Specify the operation clock specified by the SPS1 register CK10 as the operation clock for channel 1 fmcx the divided operation clock fycx specified by the CKS11 bit as the transfer clock for channel 1 frcr CSI mode as the channel 1 operation mode and the transfer end interrupt or buffer empty interrupt as the channel 1 interrupt source Address F0152H F0153H After reset 0020H R W Set value 002 H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 O O dp 7 Set value 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 i Remark Switch the transfer end interrupt 0 and buffer empty interrupt 1 by using software b Serial communication operation setting register 11 SCR11 Specify transmission reception as the channel 1 operation mode Type 1 as the data and clock phase in CSI mode MSB first as the data transfer order and 8 bits as the transfer data length Address F015AH FO15BH After reset 0087H R W Set value C007H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scR11 _ I l Tie Ne Z wlmwl al e amp lol lsglsSleleole Slel 4 Fl a s IEEE z a Set value 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 c Serial data register 11 SDR11 Specify fmcg 32 as the transfer clock generated b
14. TDRO3 Set value 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 e Timer channel start register 0 TSO Specify that the trigger to start operation of channel 1 and channel 3 is the setting of the TEO1 and TEO3 bits to 1 enabling counting Address Symbol TSO Set value F01B2H F01B3H After reset 0000H R W Set value 000 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 n 5 o Te lt op a x o o o o o I o I o P D P D P D P D 2 SE FlJ FITFJFJFI FE eee 0 0 0 0 0 0 0 0 0 0 0 0 i 0 i 0 RO1AN1128EJ0110 Rev 1 10 Sep 30 2013 Remark Write 1 to this bit only when starting the timer tENESAS Page 26 of 38 RL78 G1E Group 6 4 Functions Table 6 1 Functions Low Power Control of Analog Block Intermittent Operation File Name Function Name Overview main c main main function R5F10FMx_LDO_ Enable Analog block LDO initialization function R5F10FMx_Analog_Init Analog block initialization function R5F10FMx_Analog_Start Analog block operation start function R5F10FMx_Analog_Stop Analog block operation stop function r_systeminit c R_Systeminit MCU initialization function hdwinit System initialization function r CG _COG R_CGC_Create Clock generator initialization function f G9 port c R_PORT_Create Port initialization f
15. connected to the AMP1_OUT pin in the analog block via a resistor divider P130 Output P130 is an output only pin in the microcontroller block This pin is connected to the ARESET pin in the analog block and is used to control the analog reset feature of the analog block RO1AN1128EJ0110 Rev 1 10 RENESAS Page 6 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 5 Features of the Analog Block See 6 2 Settings of Analog Block Registers on p 14 for details 5 1 Procedure for Setting the Variable Output Voltage Regulator The variable output voltage regulator incorporated in the RL78 G1E R5FIOFMx is a series regulator which outputs the variable voltage from 2 0 to 3 3 V by a 0 1 V step with the setting of control registers In this application note the output voltage from the variable output voltage regulator is set to be 3 3 V and is used as the power supply voltage of the A D converter Figure 5 1 shows the connection between the variable output voltage regulator in the analog block and the A D converter in the microcontroller block incorporated in the RL78 G1E RSF10FMx RL78 G1E R5F10FMx Analog block BGR_OUT Reference voltage generator 777 3 3 V Typ _LDO_OUT le Variable output voltage regulator Microcontroller block AVop gt Set the LDO_OUT pin output to 3 3 V T
16. of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 6 Software 6 1 Timing Chart In this application note configurable amplifier Ch1 used as a transimpedance amplifier and D A converter Ch1 are used It is therefore necessary to program the system to wait for at least 100 us between when the AMP1OF and DACIOF bits are set to 1 in the PC1 register and the start of A D conversion to accord with the D A converter s settling time which is the longer of the two A timing chart showing the intermittent operation described in this application note is shown below i 10 ms lt TAUO Ch1 INTTMO1 4 t HALT i Normal CPU status mode Normal operation mode HALT mode operation j mode Po TAUO Ch3 100 us oe measured oa 1 AMP10F Operating settling time i i y i iy Status of configurable Operation l Operating Operation stood amplifier Ch1 stopped output stable P PP L DAC1OF i Operating output stable i y 1 1i i Status of D A Operation l i Operation stopped converter Ch1 stopped i P PP H JL l oa i a H j Operating settling time A D converter b 4 ADCS po lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt b gt lt 6 gt lt i gt Remark INTTMO01 Interrupt triggered by the completion of counting by channel 1 of timer array unit 0 or captu
17. produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products e Before changing from one product to another i e to one with a different part number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different part numbers implement a system evaluation test for each of the products Notice 1 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 2 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 3 Renesas Electronics does not assum
18. subsequent figures C Start hdwinit System initialization function The relevant option byte is referenced before the initial setup function is called main main function Ct Figure 6 2 Overview of Processing Flow 1 System initialization function hdwinit C hdwinit DI Disables interrupts R_Systeminit MCU initialization function Initializes the MCU described in this application note EI Enables interrupts C return D Figure 6 3 Flowchart for hdwinit Function RO1AN1128EJ0110 Rev 1 10 RENESAS Page 31 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 2 MCU initialization function R_Systeminit C R_Systeminit PIOR 0x00U Initializes peripheral I O redirect R_PORT_Create Port initialization function Initializes the ports described in this application note R_CGC_Create Clock generator initialization function Initializes the clock generator described in this application note R_SAU1_Create SAUT initialization function Initializes the 3 wire serial I O CSI21 of channel 1 of serial array unit 1 described in this application note CRCOCTL 0x00U Initializes the flash memory CRC calculation unit IAWCTL 0x00U Initializes the illegal memory acces
19. the control flow used in this application note Microcontroller block of Analog block of RL78 G1E R5F10FMx RL78 G1E R5F10FMx y f Both the microcontroller block and the HALT state Operation stopped 4 analog block are in the low power state Me INTTMO1 c The microcontroller block enters the normal interrupt 5 v On contro y operation state in response to an interrupt request Normal operation gt Operation starts lt The microcontroller block sends a SPI a command to the analog block to start i y operating Wait for settling time Settling time Wait for 100 ps ite A a Out Ji sabie f The analog block output stabilizes after E eee y P the settling time has elapsed A D conversion starts Y A D conversion ends PESEE ESETE O ff control y Once A D conversion has finished the 4 Operation stops lt microcontoller sends a SPI command to the 10 ms HALT state l analog block to stop operating cycle i Both the microcontroller block and the i i i analog block are in the low power state INTTMO14 c The microcontroller block enters the normal interrupt 5 v On contro i operation state triggered by an interrupt request Normal operation gt Operation starts lt The analog block starts operating based on i i communication from the microcontroller v M
20. to initialize the clock generator Calls the R_SAU1_Create function to initialize the 3 wire serial I O CSI21 of channel 1 in serial array unit 1 7 System initialization function hdwinit Declaration void hdwinit void Overview System initialization function Parameters None Return value None Description e Disables interrupts e Calls the R_Systeminit function to initialize the MCU e Enables interrupts 8 A D conversion control function ADC_Control Declaration void ADC_Control void Overview A D conversion control function Parameters None Return value None Description Controls A D conversion of the voltage output from the configurable amplifier Ch1 voltage stepped down by using a resistor divider RO1AN1128EJ0110 Rev 1 10 Sep 30 2013 RENESAS Page 29 of 38 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 9 1 us unit wait function TAUO_WAIT_lus Declaration void TAUO_WAIT_lus uint32_t wait_lus Overview 1 us unit wait function Parameters uint32_t wait_lus 1 us counter Return value None Description e Calls the R_LTAUO_Channe13_Stop function to stop counting using channel 3 in timer array unit 0 e Calls the R_LTAUO_Channe13_Start function to start counting using channel 3 in timer array unit 0 e Decrements the value of the wait_lus parameter for the interval of channe
21. value capacitor is connected to the LDO_OUT pin and a 0 1 pF recommended value capacitor is connected to the BGR_OUT pin 5 4 2 Settling time of the configurable amplifier used as transimpedance amplifier When operation of the configurable amplifier is started by setting AMPnOF n 1 to 3 to 1 in power control register 1 PC1 after having been stopped by setting AMPnOF n 1 to 3 to 0 in PC1 a settling time Ts is required for the output of the amplifier to stabilize The settling time of the configurable amplifier used as a non inverting amplifier is measured from the end of SPI command the data that changes the setting of the AMPnOF n to 3 bit from 0 to 1 is latched until the output voltage from the configurable amplifier AMPn_OUT n 1 to 3 is within 0 1 of the final output voltage Figure 5 3 shows the settling time CS SCLK Ts AMPn_OUT n 1 to 3 Data that changes AMPnOF n 1 to 3 from 0 to 1 is latched Figure 5 3 Settling Time of Configurable Amplifier Used as Transimpedance Amplifier The required settling time of the configurable amplifier when used as a transimpedance amplifier is shown in Table 5 2 below based on the electrical specifications described in the RL78 GIE Hardware User s Manual RO1AN1128EJ0110 Rev 1 10 RENESAS Page 10 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog
22. C Set the operating mode of configurable amplifier Ch1 to high speed mode Address 09H After reset OOH R W Set value 00H Symbol 7 6 5 4 3 2 1 0 AOMC 0 0 0 0 0 0 CC1 CCO Set value 0 0 0 0 0 0 0 0 6 LDO control register L DOC Set the output voltage of the variable output voltage regulator to 3 3 V Typ Address OBH After reset ODH R W Set value ODH Symbol 7 6 5 4 3 2 1 0 LDOC 0 0 0 0 LDO3 LDO2 LDO1 LDOO Set value 0 0 0 0 1 1 0 1 7 DAC reference voltage control register DACRC Set the upper VRT and lower VRB limits of the reference voltage for the D A converter to AVpp X 5 10 and AGND1 respectively Address OCH After reset OOH R W Set value 00H Symbol 7 6 5 4 3 2 1 0 DACRC 0 0 0 0 VRT1 VRTO VRB1 VRBO Set value 0 0 0 0 0 0 0 0 8 DAC control register 1 DAC1C Set the analog voltage to be output to the DAC1_OUT pin to 0 49 V Address ODH After reset 80H R W Set value 19H Symbol 7 6 5 4 3 2 1 0 DAC1C DAC17 DAC16 DAC15 DAC14 DAC13 DAC12 DAC11 DAC10 Set value 0 0 0 1 1 0 0 1 RO1AN1128EJ0110 Rev 1 10 RENESAS Page 15 of 38 Sep 30 2013 RL78 G1E Group 9 Power control register 1 PC1 Enable or stop operation of configurable amplifier Chl and D A converter Chl Low Power Control of Analog Block Intermittent Operation Address 11H After reset
23. Centre No 18 Jin Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2013 Renesas Electronics Corporation All rights reserved Colophon 2 2
24. N10 MPX1 a Pom k AMP1OF 4 a 5 SW11 1 MPXIN11 D g y T 3 sSw01 1 L ee t L AMP1_OUT L MPXIN20 P Lies MPXIN21 5 oO e E SW12 1 SW13 1 PX2 D A converter Ch1 DAC1_OUT MREFIN1 DAGI MPX21 1 LDO_OUT MPX20 0 3 3 V Typ Microcontroller bock opaa AVop 2kQ AVes A D converter i ANIE 3 kQ TA ho Resistor divider Steps down the 5 V AMP1_OUT amplitude signal to a 3 V amplitude signal Figure 5 2 Connection Between Configurable Amplifier Ch1 and Photodiode and Between Configurable Amplifier Ch1 and A D Converter Follow the procedure below to start configurable amplifier Ch1 used as a transimpedance amplifier lt l gt Set SW11 to 1 SW12 to 1 and SW13 to 1 in configuration register 1 CONFIG1 to specify that configurable amplifier Ch1 is used as a transimpedance amplifier lt 2 gt Set MPX11 to 0 and MPX10 to 0 in MPX setting register 1 MPX1 to specify the MPXIN10 pin as the source of inverted input to configurable amplifier Ch1 lt 3 gt Set MPX21 to 1 and MPX20 to 0 in MPX setting register 1 MPX1 to specify the D A converter Ch1 output signal or the VREFIN pin as the source of non inverted input to configurable amplifier Ch1 lt 4 gt Set CC1 to 0 and CCO to 0 in the AMP operation mode control register AOMC to specify high speed mode as the operation mode of configurable amplifier channels Ch1 to Ch3 lt 5 gt Set AMP14 to 0 AMP13 to 1 AMP12 to 1 AMP11 to 1 and AMP10 to 1 in gain
25. R5F10FMx LDOC 0BH ODH PC2 12H 02H Has communication No with the analog block finished successfully Returns 0 if writing the SPI control register was completed successfully and 1 if an error occurred Yes C return 0 return 1 Figure 6 6 Flowchart for R5F10FMx_LDO_Enable Function 5 Analog block initialization function R5F10FMx_Analog_Init on OFMx_Analog_Init es SPI control register write function ire Writes data to the SPI control register in the RL78 G1E R5F10FMx CONFIG1 00H 70H CONFIG2 01H 02H MPX1 03H 20H GC1 06H OFH AOMC 09H 00H Has communication ee ee with the analog block finished a DAGIO ODM H successfully E f Returns 0 if writing the SPI control register was completed successfully Yes and 1 if an error occurred C return 0 D C return 1 D Figure 6 7 Flowchart for R5F10FMx_Analog_Init Function R01AN1128EJ0110 Rev 1 10 RENESAS Page 34 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 6 Analog block operation start function RSF10FMx_Analog_Start ssriorixAnatog stare A SPI_ControlRegis ter Write SPI control register write function Writes data to the SPI control register in the RL78 G1E R5F10FMx PC1 11H 11H las communication No
26. RENESAS APPLICATION NOTE RL78 G1 E Group RO1AN1128EJ0110 Rev 1 10 Low Power Control of Analog Block Intermittent Operation Sep 70 2018 Introduction This application note describes how to apply the low power control for the sensor measurement by using the stanby function HALT mode of the microcontroller block and the power off function of the analog block incorporated in the RL78 G1E R5F10FMx Operation Verified Devices RL78 G1E R5F10FMx x C D or E When this application note is applied to other microcontrollers make the necessary changes according to the specifications of the microcontroller and verify them thoroughly RO1AN1128EJ0110 Rev 1 10 RENESAS Page 1 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation Contents Te Specifications sssini ands epi cca ps vised inea Soap cade ean gsaccy ss acaba deanca va ic abet acters E a decedes Gewese Soe gtesaere 3 2 Conditions for Verifying Operation cceceececececeeeeeeeeeeeeeeeceeeeeceaeeeeaaeseeaeeseaeeeseaaeeeeeeeseaeeesaaeseeaaeeeneeseaees 4 3 Related Application Notes cccccceceesesceceeeeeeeeeeeneeeeeeaeeeseeaaesesaaeeeseageeesaaeeeseeaaeeeseeeaaeeeseeeeeeeeeeenees 4 Ac THAW ack A a suhed A 5 4 1 Hardware Configuration Example ccccccseeeeeeeeceeeeeeeaeeeeaeeseeeeeseaeeesaaesseaeeseeeesaaeessaeeeeneeenaees 5 4 2 PUNCUONS USS osis an aa E E E ceeds lan exeestan test an aceessan acct a 6 4 3 PPV WS
27. a aa aa aa aa aa aa ao A a oO oO A oO A Set value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f Serial output register 1 SO1 Set the serial clock output of channel 1 to 1 and the serial data output to 0 Address F0168H F0169H After reset OFOFH R W Set value 0301H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ro ro ro ro ro ro Q Q ro ro ro ro ro ro Q Q O O Set value 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 g Serial output enable register 1 SOE1 Specify whether to enable the serial output of channel during serial communication Address FO16AH FO16BH After reset 0000H R W Set value 000 H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SOE1 SOE11 o SOE10 o Set value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remark Write 1 to this bit to start serial communication and 0 to stop serial communication RO1AN1128EJ0110 Rev 1 10 RENESAS Page 20 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation h Serial channel start register 1 SS1 Specify that the trigger to start operation of channel 1 is clear the SE11 bit to 1 and enter the communication wait status
28. alue 0 0 0 1 0 0 0 0 b Clock operation status control register CSC Set the operation mode of the high speed system clock in input port mode to input port and the operation mode of the high speed on chip oscillator to high speed on chip oscillator operating Address FFFA1H After reset COH R W Set value COH Symbol 7 6 5 4 3 2 1 0 CSC MSTOP 1 0 0 0 0 0 HIOSTOP Set value 1 1 0 0 0 0 0 0 c System clock control register CKC Select the high speed on chip oscillator clock fmam as the main system clock fim Address FFFA4H After reset OOH R W Set value 00H Symbol 7 6 5 4 3 2 1 0 CKC CLS 0 MCS MCMO 0 0 0 0 Set value 0 0 0 0 0 0 0 0 d Operation speed mode control register OSMC Select the low speed on chip oscillator clock as the interval timer operation clock Address FOOF3H After reset OOH R W Set value 10H Symbol 7 6 5 4 3 2 1 0 OSMC 0 0 0 WUTMM 0 0 0 0 CKO Set value 0 0 0 1 0 0 0 0 RO1AN1128EJ0110 Rev 1 10 RENESAS Page 18 of 38 Sep 30 2013 RL78 G1E e Group Peripheral enable register 0 PERO Enable the input clock supply to the A D converter serial array unit 1 and timer array unit 0 Low Power Control of Analog Block Intermittent Operation Address FOOFOH After reset 00H R W Set value 29H Symbol 7 6 5 4 3 2 0 PERO RTCEN 0 ADCEN 0 SAU1EN SAUOEN
29. control register 1 GC1 to specify 640 kQ as the feedback resistance Typ of configurable amplifier Chl used as a transimpedance amplifier lt 6 gt Set SWO1 to 1 in configuration register 2 CONFIG2 to turn on SWO1 lt 7 gt Set AMPIOF to 1 in power control register 1 PC1 to enable operation of configurable amplifier Ch1 By executing the above steps configurable amplifier Ch1 used as a transimpedance amplifier starts operating RO1AN1128EJ0110 Rev 1 10 RENESAS Page 8 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation Follow the procedure below to stop configurable amplifier Ch1 used as a transimpedance amplifier lt l gt Set AMPIOF to 0 in power control register 1 PC1 to stop operation of configurable amplifier Ch1 By executing the above step configurable amplifier Ch1 used as a transimpedance amplifier stops operating In this application note the operation of configurable amplifier Ch1 used as a transimpedance amplifier is stopped after its output voltage which is a voltage that has been stepped down by using a resistor divider has been A D converted by the A D converter in the microcontroller block 5 3 Procedure for Setting the D A Converter In this application note D A converter Ch1 in the analog block is used to generate a bias voltage for configurable amplifier Ch1 used as a transimpedance amplifier Follow the procedure below to start D A converter
30. digital value s High speed on chip oscillator Generates the 32 MHz clock used as the main system clock 5 high speed OCO Serial array unit 1 channel 1 Controls SPI communication with the analog block by using the 3 wire S serial I O CS121 I O ports Controls the reset of the analog block and the chip select signal CS used to control SPI communication with the analog block Timer array unit 0 channel 1 The timer to generate the signal which cancels the HALT mode Timer array unit 0 channel 3 The timer to generate the settling time that the system must wait until the output of configurable amplifier Ch1 used as a transimpedance amplifier and the D A converter stabilizes 4 3 Pins Used Table 4 2 shows the RL78 G1E RS5FIOFMx pins used in this application note and their features Table 4 2 RL78 G1E R5F10FMx Pins Used and Their Features Pin Name 1 0 Description MPXIN10 Input This is an inverted input pin of the configurable amplifier Ch1 used as a transimpedance amplifier in the analog block This pin is connected to the sensor Photodiode AMP1_OUT Output This is an output pin of the configurable amplifier Ch1 used as a transimpedance amplifier in the analog block This pin is connected to the ANI2 pin of the A D converter in the microcontroller block via a resistor divider ANI2 Input This is an analog input pin of the A D converter in the microcontroller block This pin is
31. e 00H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 P140 0 0 0 0 0 0 0 0 Set value Remark Write 0 or 1 to switch the output level according to the status RO1AN1128EJ0110 Rev 1 10 Sep 30 2013 tENESAS Page 22 of 38 RL78 G1E Group c Port mode control register 7 PMC7 Specify whether the P70 pin is used as a digital I O pin or an analog input pin Address FFF67H Symbol PMC7 Set value After reset FFH Set value FEH Low Power Control of Analog Block Intermittent Operation 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PMC70 1 1 1 1 1 1 1 0 5 A D converter a A D converter mode register 0 ADMO Enable A D conversion specify select as the A D conversion channel selection mode enable operation of the A D voltage comparator and set the A D conversion time to 54 us 12 bit A D conversion no stabilization wait hardware trigger no wait mode AVpp 2 7 to 3 6 V fork 32 MHz Address FFF30H Symbol ADMO Set value After reset 00H R W Set value 1H 7 6 5 4 3 2 1 0 ADCS ADMD FR2 FR1 FRO LV1 LVO ADCE j 0 0 0 0 0 0 1 Remark Write 1 to this bit only when starting A D conversion b A D converter mode register 1 ADM1 Specify software trigger mode as the A D conversion trigger mode and one shot conversion mode as the A D conversion operation mode Address FFF32H Symbol ADM1 Set val
32. e any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others 4 You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product 5 Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a di
33. e microcontroller block so the variable output voltage regulator is never stopped once they start operating RO1AN1128EJ0110 Rev 1 10 RENESAS Page 7 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 5 2 Procedure for Setting the Configurable Amplifiers A configurable amplifier can change its circuit configuration and its circuit features and characteristics with the setting of control registers included in the analog block In this application note the configurable amplifier Ch1 is connected to the photodiode and is used as a transimpedance amplifier to convert an output current from the photodiode to a single ended voltage The output pin AMP1_OUT of the configurable amplifier Ch1 is connected to the analog input pin ANI2 of the A D converter outside the packages Figure 5 2 shows the connection among the photodiode the configurable amplifier Chl and the A D converter RL78 G1E R5F10FMx GeNaorn Analog block 5 0V AV Hees Feedback resistance of transimpedance AVpp1 lt amplifier 640 kQ Typ AGND1 Photodiode ee i ii Nee onfigurable amplifier MPXI
34. eceeeeceeeeeeeeeeeeeeseaeeeseaeeseaaeseneeeseaeeesaeeeeeeseeeees 14 6 3 Settings of Microcontroller Block Registers cccsceceeeeeeeeeeeeeeeeeeeeeeeaeeesaaeeeeneeseeeesaaeeneneeee 17 6 4 FUNCUONS sctetiveieca tance dean R E een A 27 6 5 FUNCTION Specifications iii ccieccesacevesic cade secete sake cotensnseeeeedh cadeated ea ede naianei idrarda aa aaaea 28 6 6 RAM Variable Searsin dentine niaivdlieav ai nanan 30 6 7 FIOWCNAMNS i ccccicechassselecaentebensateniaiiadead ate peau S EEAO nated aa AEAEE RA 31 6 8 Source Files and Changes Applied to the Code Output from the Code Generator 36 RO1AN1128EJ0110 Rev 1 10 RENESAS Page 2 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 1 Specifications This application note describes the example of the low power control introducing the intermittent operation to the sensor measurement with the RL78 GIE RSF1OFMx In this application note using the example of the system to measure the illuminance with the photodiode BS520E0F made by Sharp Corporation connected to the RL78 GIE R5FIOFMx it is explained how to shift the microcontroller block and the analog block incorporated in the RL78 G1E R5F10FMx from the normal operation mode to the stanby mode how to make a comeback to the normal operation mode and how to use the CPU peripheral function the analog peripheral function after a comeback Figure 1 1 shows an overview of
35. ed Pins in the manual 2 Processing at Power on e The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses e Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals e After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal
36. ent of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations 10 Itis the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics CENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesa
37. er Ch1 output voltage Enables D A converter Ch1 and configurable amplifier Ch1 RO1AN1128EJ0110 Rev 1 10 RENESAS Page 28 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 4 Analog block operation start function RSF10FMx_Analog_Start Declaration static uinu8_t R5F10FMx_Analog_Start void Overview Analog block operation start function Parameters None Return value 0 Successful 1 Communication with the analog block failed Description e Starts operation of the circuits in the analog block Enables D A converter Ch1 and configurable amplifier Ch1 5 Analog block operation stop function R5F10FMx_Analog_Stop Declaration static uinu8_t R5F10FMx_Analog_Stop void Overview Analog block operation stop function Parameters None Return value 0 Successful 1 Communication with the analog block failed Description e Stops operation of the circuits in the analog block Stops operation of D A converter Ch1 and configurable amplifier Ch1 6 MCU initialization function R_Systeminit Declaration void R_Systeminit void Overview MCU initialization function Parameters None Return value None Description e Initializes the peripheral hardware in the MCU used in this application note Calls the R_LPORT_Create function to initialize the ports Calls the R_CGC_Create function
38. fy the SPI control register settings see the RL78 G1E Hardware User s Manual Address 00H After reset OOH R W Set value 70H 7 6 5 4 3 2 1 0 0 SW11 SW12 SW13 0 SW21 SW22 SW23 0 1 1 1 0 0 0 0 2 Configuration register 2 CONFIG2 Turn on the output switches of configurable amplifier Ch1 Address 01H After reset OOH R W Set value 02H 7 6 5 4 3 2 1 0 0 SW31 SW32 SW33 0 Swo2 Swot Swoo0 0 0 0 0 0 0 1 0 Set value 3 MPX setting register 1 MPX1 Specify the MPXIN10 pin as the source of inverted input to configurable amplifier Ch1 and the D A converter Chl output signal or the VREFIN1 pin as the source of non inverted input to configurable amplifier Ch1 Symbol MPX1 Address 03H After reset OOH R W Set value 20H 7 6 5 4 3 2 1 0 MPX11 MPX10 MPX21 MPX20 MPX31 MPX30 MPX41 MPX40 0 0 1 0 0 0 0 0 Set value 4 Gain control register 1 GC1 Set the feedback resistance of configurable amplifier Ch1 used as a transimpedance amplifier to 640 KQ Typ Address 06H After reset OOH R W Set value OFH Symbol 7 6 5 4 3 2 1 0 GC1 0 0 0 AMPG14 AMPG13 AMPG12 AMPG11 AMPG10 Set value 0 0 0 0 1 1 1 1 RO1AN1128EJ0110 Rev 1 10 RENESAS Page 14 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 5 AMP operation mode control register AOM
39. ifferences between the RL78 G1A R5FIOELE and RL78 G1E R5FIOFME see the RL78 G1E Hardware User s Manual Table 6 3 Source Files and Changes Applied to the Code Output from the Code Generator 1 2 File Name Description Changes Applied to the Code Output by the Code Generator Item Description r_main c Output by the code generator r_systeminit c Output by the R_systeminit e Commented out code generator function R_ADC_Create e Commented out R_TAUO_Create E CJ Cgc uc Output by the R_CGC_Create e Changed the value set to CMC code generator function aie e Commented out XSTOP e Commented out CSS r_cg_cgc_user c Output by the z code generator r_cg_port c Output by the R_PORT_Create e Commented out P6 code generator function e Commented out P12 e Commented out P15 e Commented out PMC4 e Changed the value set to ADPC sr r_cg_port_user c Output by the code generator r_cg_serial c Output by the R_CS1I21_Create e Commented out SO1 code generator function e Commented out S01 amp r_cg_serial_user c Output by the r_csi21_callback e Added processing code generator _receiveend function r_cg_adc c Output by the R_ADC_Create function e Commented out PM2 code generator e Commented out PM15 e Commented out PM12 e Commented out PMC3 e Commented out PM3 r_cg_adc_use
40. l 3 in timer array unit 0 1 us until the value becomes 0 6 6 RAM Variables Table 6 2 RAM Variables Data Type Variable Name Description Function That Uses This Variable volatile gp_csi21_rx_address_ Address of CSI21 R_CSI21_Send_Receive uint8_t reception buffer y_csi2l_interrupt volatile g_csi21_rx_length Number of bytes None uint16_t received at CSI21 volatile g_csi21_rx_count CSI21 received byte None uintl6_t counter volatile gp_csi21_tx_address Address of CS121 R_CSI21_Send_Receive uint8_t transmission buffer r_csi2l_interrupt volatile g_csi21_send_length_ Number of bytes R_CSI21_Send_Receive uintl6_t transmitted from r_csi2l1_interrupt csl21 volatile g_csi21_tx_count CSI21 transmitted byte R_CSI21_Send_Receive uintl6_t counter r_csi21_interrupt static _ad_buffer Stores the A D r_adc_interrupt uint1l6_t conversion result ADC_Get_AD_Buffer_Value static g_csi21_overrun_flag CSI21 overrun flag R_CSI21_Send_Receive uint8_t r_csi21_callback_error SPI_ControlRegister_Read SPI_ControlRegister_Write RO1AN1128EJ0110 Rev 1 10 Sep 30 2013 tENESAS Page 30 of 38 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 6 7 Flowcharts Figure 6 2 shows an overview of the processing flow used in this application note Flowcharts for the major functions are shown in the
41. ment safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you 8 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations 9 Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the developm
42. nd which is counted by using the interval timer of channel 3 of timer array unit 0 in the microcontroller block Once the 100 us wait time has elapsed the A D converter in the microcontroller block enters software trigger mode and A D conversion of the data input from the ANI2 pin is started by setting the ADCS bit to 1 in A D converter mode register 0 ADMO lt 4 gt When the A D converter in the microcontroller block finishes A D converting the data the conversion result is read out lt 5 gt Operation of configurable amplifier Chl used as a transimpedance amplifier and D A converter Ch1 in the analog block is stopped via CSI21 in the microcontroller block by setting the AMP1OF and DACIOF bits to 0 in the PCI register lt 6 gt The microcontroller block enters HALT mode RO1AN1128EJ0110 Rev 1 10 RENESAS Page 13 of 38 Sep 30 2013 RL78 G1E Group 6 2 Settings of Analog Block Registers Low Power Control of Analog Block Intermittent Operation This section describes the settings of the SPI control registers in the analog block of the RL78 G1E RS5FIOFMx used in this application note This section omits descriptions of the SPI control registers not used in this application note They are used with their default values Caution 1 Configuration register 1 CONFIG1 Set all the switches of configurable amplifier Ch1 to transimpedance amplifier mode Symbol CONFIG1 Set value Symbol CONFIG2 For how to speci
43. nesas com Inquiries http www renesas com contact RO1AN1128EJ0110 Rev 1 10 Sep 30 2013 Low Power Control of Analog Block Intermittent Operation tENESAS Page 38 of 38 Revision Record Description Rev Date Page Summary 1 00 Sep 30 2012 First edition issued 1 10 Sep 30 2013 Some descriptions are modified All trademarks and registered trademarks are the property of their respective owners A 1 General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins e Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unus
44. ng channel 1 in timer array unit 0 in the microcontroller block Starts operation of the circuits configurable amplifier Ch1 and D A converter Ch1 in the analog block Waits for the 100 us settling time Controls A D conversion performed by the A D converter in the microcontroller block Stops operation of the circuits configurable amplifier Ch1 and D A converter Ch1 in the analog block e Shifts the microcontroller block to HALT mode 2 Analog block LDO initialization function R5F10FMx_LDO_Enable Declaration static uinu8_t R5F10FMx_LDO Enable void Overview Analog block LDO initialization function Parameters None Return value 0 Successful 1 Communication with the analog block failed Description e Initializes the variable output voltage regulator in the analog block Sets the variable output voltage regulator voltage to 3 3 V and enables the variable output voltage regulator and the reference voltage generator 3 Analog block initialization function R5F10FMx_Analog_Init Declaration static uinu8_t R5F10FMx_Analog_Init void Overview Analog block initialization function Parameters None Return value 0 Successful 1 Communication with the analog block failed Description e Initializes the circuits in the analog block Configures configurable amplifier CH1 used as a transimpedance amplifier as shown in this application note Sets the D A convert
45. ntermittent Operation 4 Hardware 4 1 Hardware Configuration Example Figure 4 1 shows an example of the hardware configuration described in this application note 5 0 V MPXIN10 m AVpp1 AVope2 AVops AGND1 We Sensor photodiode AGND2 AGND3 nf Analog AGND4 block UL 5 0 V AMP1_OUT DVpp DGND ARESET DGND LDO_OUT DGND DGND a BGR_OUT G 50V J E P70 SCLK a P71 SDO SPI communication E EL P72 SDI P73 CS 5 0 V A D converter power supply 3 3 V AVpp Vop EEN EET SEE AVss REGC l me Vss L 2ko Measured voltage subject oja to A D conversion ANI2 _ 1 i V7 l Analog block reset control P130 Nlicroconitrolier j block i 3kQ 77 50V Note 1 Because the A D converter supply voltage is 3 3 L Te V the output of the AMP1_OUT pin 0 to 5 V is Resistor divider stepped down to 0 to 3 V by using a resistor divider RESET Note 2 The analog block is reset via the P130 pin output f TOOLO After the reset of the microcontroller block ends
46. r c Output by the r_adc_interrupt e Added processing code generator function r_cg_timer c Output by the R_TAUO_Create e Commented out TOMO amp code generator function e Commented out TOLO amp e Commented out TOO amp e Commented out TOEO amp r_cg_timer_user c Output by the code generator r_cg_macrodriver h Output by the code generator RO1AN1128EJ0110 Rev 1 10 RENESAS Page 36 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation Table 6 4 Source Files and Changes Applied to the Code Output from the Code Generator 2 2 File Name Description Changes Applied to the Code Output by the Code Generator Item r_cg_userdefine h Output by the e Added the typedef and code generator define statements r_cg_cgc h Output by the e Added the extern statement code generator r_cg_port h Output by the e Added the extern statement code generator r_cg_serial h Output by the e Added the extern statement code generator r_cg_adc h Output by the e Added the extern statement code generator r_cg_timer h Output by the e Added the extern statement code generator led c LCD module control led h Header file for tede e R01AN1128EJ0110 Rev 1 10 RENESAS Page 37 of 38 Sep 30 2013 RL78 G1E Group Website and Support Renesas Electronics Website http www re
47. re interrupt AMP10OF _ Bit 0 of power control register 1 PC1 Controls the operation of configurable amplifier Ch1 0 Stop operation of configurable amplifier Ch1 1 Enable operation of configurable amplifier Ch1 DAC1OF Bit 4 of power control register 1 PC1 Controls the operation of D A converter Ch1 0 Stop operation of D A converter Ch1 1 Enable operation of D A converter Ch1 ADCS Bit 7 of A D converter mode register 0 ADMO 0 Stop conversion When read Conversion stopped or in the standby status 1 Enable conversion When read Conversion in progress software trigger mode Figure 6 1 Timing Chart for Intermittent Operation RO1AN1128EJ0110 Rev 1 10 RENESAS Page 12 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation lt l gt The microcontroller block exits the HALT mode upon occurrence of the interrupt request triggered by the completion of counting by channel 1 of timer array unit 0 INTTMO01 lt 2 gt Operation of configurable amplifier Chl used as a transimpedance amplifier and D A converter Ch1 in the analog block is started via the 3 wire serial I O of channel 1 of serial array unit 1 CSI21 in the microcontroller block by setting the AMP1OF and DACIOF bits to 1 in the PC1 register lt 3 gt The system waits for 100 us which is the settling time of configurable amplifier Ch1 used as a transimpedance amplifier and D A converter Ch in the analog block a
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50. s detection RAM guard and SFR guard features C return D Figure 6 4 Flowchart for R_Systeminit Function R01AN1128EJ0110 Rev 1 10 RENESAS Sep 30 2013 Page 32 of 38 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 3 main function main C main 14 s R5F10FMx_LDO _Enable Analog block LDO initialization function Has communication No Initializes the variable output voltage regulator incorporated in the RL78 G1E with the analog block finished R5F10FMx successfully if Yes DIO Disables interrupts TAUO initialization function Pee Initializes timer array unit 0 in the RL78 G1E R5F10FMx 1 us unit wait function Executes processing to make the system wait 5 ms for the output of the variable output voltage regulator in the analog block to stabilize TAUO_WAIT_1lus 5000 R_ADC_Create ADC initialization function _ Initializes the A D converter incorporated in the RL78 G1E R5F10FMx Enables interrupts EI 14 y R5F10FMx_Analog _Init Analog block initialization function a immuniation E Initializes configurable amplifier Ch1 and D A converter Ch1 las col o with the analog block finished incorporated in the RL78 G1E R5F10FMx successfully yar Yes Fg TAUO Ch1 counter operation start function
51. t generated when counting is started timer output does not change either as the count start and interrupt setting for channels 3 and 1 Address F0192H F0193H After reset 0000H R W Set value 8000H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENEE ee es ee ell ojal z e o o o o o _ bl k mog k apg q 2 2 slel2 2 2 2 8 c co sis eig OIIO O oO o op o O O Ss Set value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RO1AN1128EJ0110 Rev 1 10 RENESAS Page 25 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation Address F0196H F0197H After reset 0000H R W Set value 0000H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMRO3 gt ro rs D a f O f O E e ee ee de E e a e fh Oo 6 olll lololo Ss 5 Set value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d Timer data registers 1 and 3 TDRO1 TDRO3 Specify the interval in the interval mode of channels 1 and 3 of timer array unit 0 Address FFF1AH FFF1BH After reset 0000H R W Set value 9C3FH Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TDRO1 Set value 1 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 Address FFF66H FFF67H After reset 0000H R W Set value 001FH Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
52. ter Ch1 By executing the above step D A converter Ch1 stops operating In this application note the operation of configurable amplifier Ch1 used as a transimpedance amplifier is stopped after its output voltage which is a voltage that has been stepped down by using a resistor divider has been A D converted by the A D converter in the microcontroller block Due to this the operation of D A converter is also stopped RO1AN1128EJ0110 Rev 1 10 RENESAS Page 9 of 38 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 5 4 Analog Block Settling Time 5 4 1 Settling time of the variable output voltage regulator When operation of the variable output voltage regulator is started by setting LDOOF to 1 in power control register 2 PC2 after having been stopped by setting LDOOF to 0 in PC2 a settling time tser is required for the output of the variable output voltage regulator to stabilize The required settling time of the variable output voltage regulator is shown in Table 5 1 below based on the electrical specifications described in the RL78 GIE Hardware User s Manual Table 5 1 Settling Time of Variable Output Voltage Regulator 40 C lt Ta lt 85 C AVpp1 AVpp2 AVpp3 DVpp 5 0 V LDOOF 1 Parameter Symbol Conditions Ratings Unit MIN TYP MAX Settling time tset 5 ms Caution The rating in Table 5 1 applies to when a 4 7 uF recommended
53. ue After reset 00H R W Set value 20H 7 6 5 4 3 2 1 0 ADTMD1 ADTMDO ADSCM 0 0 0 ADTRS1 ADTRSO 0 0 1 0 0 0 0 0 c A D converter mode register 2 ADM2 Specify AVpp as the positive reference voltage supply of the A D converter AVss as the negative reference voltage supply of the A D converter the generation of an interrupt signal INTAD if the conversion result upper lower limit check results in ADLL register value lt ADCR register value lt ADUL register value disable the SNOOZE mode and set the A D conversion resolution to 12 bits Address F0010H After reset OOH R W Set value 00H Symbol 7 6 5 4 3 2 1 0 ADM2 ADREFP1 ADREFPO ADREFM 0 ADRCK AWC 0 ADTYP Set value 0 0 0 0 0 0 0 0 RO1AN1128EJ0110 Rev 1 10 RENESAS Page 23 of 38 Sep 30 2013 RL78 G1E Group d Conversion result comparison upper limit setting register ADUL Set the A D conversion result comparison upper limit to FFH Low Power Control of Analog Block Intermittent Operation Address F0011H After reset FFH R W Set value FFH Symbol 7 6 5 4 3 2 1 0 ADUL ADUL7 ADUL6 ADUL5 ADUL4 ADUL3 ADUL2 ADUL1 ADULO Set value 1 1 1 1 1 1 1 1 e Conversion result comparison lower limit setting register ADLL Set the A D conversion result comparison lower limit to OOH Address F0012H After reset OOH R W Set
54. unction r_cg_serial c R_SAU1_Create SAU1 initialization function R_CSI21_Create CSI21 initialization function R_CSI21_Start CSl21 operation start function R_CSI21_Stop CSI21 operation stop function R_CSI21_Send_Receive CSI21 transmission reception function r_cg_serial_user c r_csi21_interrupt INTCS121 interrupt service function r_csi21_callback_receiveend CSI21 reception completion function r_csi21_callback_error CSI21 error handling function SPI_ControlRegister_Read SPI control register read function SPI_ControlRegister_Write SPI control register write function SPI_ControlRegister_Write_ SPI control register write verify function Verify SPI_ControlRegister_Read_ SPI control register bit read function Bit SPI_ControlRegister_Write_ SPI control register bit write function Bit SPI_ControlRegister_Write_ SPI control register bit write verify function Verify_Bit Ecg ader R_ADC_Create ADC initialization function R_ADC_Start ADC operation start function R_ADC_Stop ADC operation stop function R_ADC_Set_OperationOn ADC comparator operation enable function R_ADC_Set_Operationoff ADC comparator operation stop function R_ADC_Get_Result A D conversion result read function r_cg_adc_user c ADC_Control A D conversion control function r_cg_timer c R_TAUO_Create TAUO initialization function R_TAUO_Channe
55. value 00H Symbol 7 6 5 4 3 2 1 0 ADLL ADLL7 ADLL6 ADLL5 ADLL4 ADLL3 ADLL2 ADLL1 ADLLO Set value 0 0 0 0 0 0 0 0 f Analog input channel specification register ADS Specify ANI2 as the A D conversion channel in select mode ADMD 0 Address FFF31H After reset 00H R W Set value 02H Symbol 7 6 5 4 3 2 1 0 ADS ADISS 0 0 ADS4 ADS3 ADS2 ADS1 ADSO Set value 0 0 0 0 0 0 1 0 g A D port configuration register ADPC Specify analog input not digital I O as the I O mode of the P24 ANI4 P23 ANI3 P22 ANI2 P21 ANI1 and P20 ANIO pins Address F0076H After reset OOH R W Set value 00H Symbol 7 6 5 4 3 2 1 0 ADPC 0 0 0 0 0 ADPC2 ADPC1 ADPCO Set value 0 0 0 0 0 0 0 0 RO1AN1128EJ0110 Rev 1 10 RENESAS Sep 30 2013 Page 24 of 38 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation 6 Timer array unit 0 a Timer channel stop register 0 TTO Specify no trigger operation as the trigger to stop operation of channel 3 and operation is stopped stop trigger is generated as that of channel 1 Address F01B4H F01B5H After reset 0000H R W Set value 000 H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTO E sSslelegel al ls al e o gt j e gt je gt jojJj Tjo Tj oJ J ee ell e elf e lll Fe E E FlrRI rF _rR rR rR Pe ITB Set value 0 0 0 0 0 0 0 0 0 0 0 0 i 0 0
56. with the analog block finished successfully Returns 0 if writing the SPI control register was completed successfully and 1 if an error occurred C return 0 D C return 1 Figure 6 8 Flowchart for RSF10FMx_ Analog_Start Function 7 Analog block operation stop function R5F10FMx_Analog_Stop Forro anatoa stor SPI_ControlRegis ter Write SPI control register write function Writes data to the SPI control register in the RL78 G1E R5F10FMx PC1 11H 00H Has communication No with the analog block finished successfully Returns 0 if writing the SPI control register was completed successfully Yes and 1 if an error occurred C return 0 C return 1 Figure 6 9 Flowchart for R5F10FMx_Analog_ Stop Function RO1AN1128EJ0110 Rev 1 10 RENESAS Page 35 of 38 Sep 30 2013 RL78 G1E Group 6 8 Generator Low Power Control of Analog Block Intermittent Operation Source Files and Changes Applied to the Code Output from the Code The sample code used in this application note was created based on the code for the RL78 G1A group R5FIOELE output by the code generator of CubeSuite The output file has been modified to apply the differences between the RL78 G1A RSFIOELE and RL78 G1E RSFIOFME such as incorporated registers Table 6 3 and Table 6 4 show the changes applied to the code output by the code generator For details about the d
57. y dividing the operation clock fmcg The lower 8 bits bits 7 to 0 function as a transmission reception buffer register Address FFF4AH FFF4BH After reset 0000H R W Set value 1E H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDR11 Set value 0 0 0 1 1 1 1 0 x x x Remark Functions as a transmission reception buffer register RENESAS Page 19 of 38 R01AN1128EJ0110 Rev 1 10 Sep 30 2013 RL78 G1E Group Low Power Control of Analog Block Intermittent Operation d Serial channel stop register 1 ST1 Specify whether the trigger to stop operation of channel 1 is the no trigger operation or clear the SE11 bit to 0 to stop the communication operation Address F0164H FO165H After reset 0000H R W Set value 000 H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST1 o dp 09 Set value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ig 0 Remark Write 1 to this bit only when finishing serial communication e Serial clock select register 1 SPS1 Specify 32 MHz when fc x 32 MHz as the operation clock CK10 Address F0166H F0167H After reset 0000H R W Set value 0000H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPS1 ro a o ra a o oO oO on on o o o o o o o o D D D D D D D D aa a
58. yp and connect it to the A D converter AVbo pin of the A D converter AVss R Figure 5 1 Connection Between Variable Output Voltage Regulator and A D Converter Follow the procedure below to start the variable output voltage regulator LDO_OUT 3 3 V Typ and reference voltage generator in the analog block of the RL78 G1E R5F10FMx lt l gt Set LDO3 to 1 LDO2 to 1 LDO1 to 0 and LDOO to 1 in the LDO control register LDOC to specify 3 3 V Typ as the voltage output from the variable output voltage regulator lt 2 gt Set LDOOF to 1 in power control register 2 PC2 to enable operation of the variable output voltage regulator and reference voltage generator By executing the above steps the variable output voltage regulator and reference voltage generator start operating and 3 3 V Typ is output from the LDO_OUT pin Follow the procedure below to stop the variable output voltage regulator and reference voltage generator lt l gt Set LDOOF to 0 in power control register 2 PC2 to stop operation of the variable output voltage regulator and reference voltage generator By executing the above step the variable output voltage regulator and reference voltage generator stop operating and 0 V is output from the LDO_OUT pin In this application note the output voltage from the variable output voltage regulator in the analog block is used as the power supply voltage of the A D converter in th
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