MPC5553DEMO
Contents
1. NEXUS Port The NEXUS port provides a more powerful and higher speed development port for high end tools The port connector is an AMP 38 pin Mictor style part number 767053 1 NEXUS Port Signal Pin Signal NXS1 TP 1 2 NXS2 TP NXS3 TP 3 4 NXS4 TP MDO9 5 6 CLKOUT BOOTCFG1 7 8 MDO8 B RESET 9 10 11 12 43 3V MDO10 13 14 RDY B 15 16 MDO7 B TMS 17 18 MDO6 B TDI 19 20 MDO5 B 21 22 MDO4 MDO 11 23 24 MDO3 ERSTOUT 25 26 MDO2 NXS27 TP 27 28 MDO1 V 31 32 EVTO 33 34 MCKO B VSTBY 37 38 Notes 1 signals are buffered 2 NXSxx TP signals are not connected to the MPC5553 and provide Test Pad on the board 3 NXSxx signal TP is also connected to the ROBUST Nexus connector 4 Signals followed by a symbol are active logic low 17 MPC5553DEMO 09 06 05 ROBUST Port The ROBUST port connector location is provided for user expansion This port provides the ROBUST Nexus 51 pin location that applies the GLENAIR MR7580 51P2BNU connector ROBUST Port Pin Signal Pin Signal Pin Signal 1 V 19 MDOO 36 GND 2 V 20 GND 37 MDO4 3 VSTBY1 21 MCKO 38 GND 4 NXS35 TP 22 GND 39 MDO5 5 TDO 23 EVTO 40 GND 6 B RDY 24 GND 41 MDO6 7 B RESET 25 MSEOO 42 GND 8 B_ 3 3V 26 MDO9 43 MDO7 9 B EVII 22. 7 6 G1 A23 G2 A2 G3 2 64 TPU_A21 2 5 H1 A20 2 TPUA1 TPU A17 9 8 J1 TPU A16 J2 A1 J3 TPU_A1 J4 TPU_A13 5 4 K1 TPU A12 K2 A1 A1 K4 TPU A9 1 0 L1 TPU A8 L2 TPU A7 TPU A6 L4 TPU A5 M1 TPU A4 M2 TPU 2 M4 TPU 1 N1 BDIP TEA TPU AO 4 TCRCLK P1 CS3 P2 CS2 P3 CS1 P4 CS0 R1 WES H2 WE2 WE1 WEO T1 3 3 TSIZO T3 RD_WR_ T4 3 3V U1 A16 U2 75121 03 TA U4 3 3V V1 A18 V2 A17 V3 TS V4 A8 W1 20 W2 A19 W3 AQ W4 A10 Y1 A22 Y2 A21 11 Y4 3 3V 1 A24 AA2 A23 A13 AA4 A12 AB1 3 3V AB2 A25 A15 A14 A26 AC2 A27 A31 4 GND AD1 A28 AD2 A30 ADS GND AD4 VDD AE1 A29 AE2 GND AES VDD 4 CRS AF1 GND AF2 VDD AF3 TX AF4 TX ER A22 05 HEADER PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL A22 MDO11 B22 MDO7 C22 MDO3 D22 5 A21 GPIO205 B21 MDO10 C21 MDO6 021 MDO2 A20 B20 x C20 MDO9 D20 MDO5 A19 B19 x C19 x 019 x A18 x 18 x C18 x 018 x A17 x B17 x C17 x D17 x A16 ETRIG1 B16 ETRIGO C16 x D16 x A15 AN15 B15 AN14 C15 AN13 D15 AN12 A14 VSSA 14 VSSA C14 VDDAO 014 5V A13 AN35 B13 AN32 C13 AN33 D13 AN34 A12 AN28 B12 1 C12 AN30 D12 AN29 11 27 11 26 11 25
3. MPC5553DEMO Development Board for the Freescale MPC5553 OPTIONS and CONNECTIONS Axiom Manufacturing 2813 Industrial Lane e Garland TX 75041 Email Sales Gaxman com Web http www axman com MPC5553DEMO 09 06 05 CONFIG SWITCH tee eee dese te o Foe dene tee re street te Poet pe ed Feeder tere d eed 4 5 dieses re eR Ie 4 SWITCH it coves uu PWR POWER JACK musici CMM VSTBY SWITCH AND vane ANALOG SW1 SW4 PUsH SWITCHES SHEAKEBAND SPERO rp ere Lim n NE JT 0 00 TS ETHERNET PORTS 412 420 costes zy tees rates sated ats sean Peau d bte Sc cate naaa NEA LES I E E os 9 DNKOSPD amd ACT eov GA EEA LA 9 NIME CRY NS IL MM ER 9 JI CONNECIOT M H K 9 COM 1 JP2 Option SEL Option LIN J1 8 Option ed NEGLI MM T 12 Option RR ettet eie ee EORR let tM e EAS UMEN EIS 12 JP6 Option JP7 Option 413 LIN PWR Option s LIN JI
4. 011 24 10 23 10 AN22 C10 010 AN6_DAN3 9 9 X C9 AN7 DAN3 09 AN2_DAN1 A8 AN5 AND2 B8 AN4_AND2 C8 1 D8 AN18 A7 AN1 ANDO B7 ANO 0 C7 21 D7 10 A6 AN16 B6 AN20 C6 VSSA 06 AN9 5 VDDA1 B5 AN19 C5 17 05 AN38 19 MPC5553DEMO 09 06 05 23 AF26 HEADER PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL A23 MDO8 A24 VDD A25 3 3V A26 GND B23 MDO4 B24 MDOO B25 GND B26 3 3V C23 MDO1 C24 GND C25 3 3V C26 VDD D23 GND D24 3 3V D25 TCK D26 TDI E23 3 3V E24 TMS E25 TDO E26 TEST F23 MSEOO F24 JCOMP F25 EVTI F26 EVTO G23 MSEO1 G24 MCKO G25 GPIO204 G26 X H23 RDY H24 GPIO203 H25 X H26 X J23 5V J24 X J25 X J26 X K23 X K24 X K25 X K26 X L23 X L24 X L25 X L26 X M23 M24 x M25 x M26 SIN_B N23 SOUT B N24 PCS B3 N25 PCS BO N26 PCS B1 P23 SIN D P24 PCS B4 25 SCK B P26 PCS B2 R23 PCS B5 R24 PCS C5 R25 PCS C2 R26 PCS C1 T23 PCS B2 T24 PCS D2 T25 SCK D T26 5 023 SOUT D U24 TXDA U25 PCS B3 U26 3 3V V23 CNTX C V24 RXDA V25 RSTOUT V26 RSTCFG W23 RXDB W24 CNRX C W25 TXDB W26 RESET Y23 WKPCFG Y24 1 25 GND Y26 GND AA23 5V AA24 PLLCFG1 25 BOOTCFGO AA26 x EXTAL AB23 VDD AB24 x VRCCTL AB25 PLLCFGO 26 XTAL AC23 GND AC
5. 3 install a 1 space 3 pin header and a jumper shunt option With the jumper installed on JP8 pins 1 and 2 the PHY will be included in the JTAG scan the 2 device NOTE JP8 function is disabled on the Revision B DEMO board do not apply J 1 Connector J1 provides the RJ45 style Ethernet 10 100TX port connection The connector has an integrated transformer for network connection MPC5553DEMO 09 06 05 J1 connection Pin Signal TX termination TX Termination RX RX Termination RX Termination COM 1 Port COM 1 is a standard RS232 type serial port configured for direct connection to a PC COM Port with a straight through type 9 pin serial cable Option JP2 provides MPC5553 SCI channel A signal connections when installed Optional RTS and CTS hardware flow control connection pads are provided for the user to apply MPC5553 I O ports and software to enhance operation J P2 Option The JP2 Option provides MPC5553 RXDA and TXDA signals to the COM 1 transceiver connections This allows the user to apply the provided communication transceiver with the SCI A channel or to apply the associated to other purposes JP2 position 1 installed enables the TXDA output and position 2 enables the RXDA input on COM 1 1 1 1 X The COM 1 port is a Female socket type DB9 connector TXD 2 616 RXD 3 7 Pins 1 4 6 connected for status null to host 4
6. VDC 12VDC typical 4 Volts 2mm center MPC5553DEMO 09 06 05 POWER Port Power Port provides access to the main power supplies and Power Oak optional supplies The V connections provided at pins 1 and 2 should be applied for an output voltage source only not for input supply PINE SIGNAL DESCRIPTION Ground VSS VSTBY MPC5553 VSTBY supply See VSTBY switch option 5VA MPC5553 Analog suppl Ground YSS JJ 24 Ground VSS 24 Note Pins 14 16 18 20 and 22 not connected FUSE F1 Input power is limited by fuse F1 An 5x20mm type 1A slow blow type fuse is applied to protect the DEMO board for overload conditions VSTBY Switch RV3 and CT7 The VSTBY SWITCH provides enabling and disabling the VSTBY operation of the MPC5553 internal RAM Switch in the OFF position disables the VSTBY operation and the VSTBY pin is connected to VSS Ground Switch in the ON position applies the VKAM standby voltage from the Power Oak supply to the VSTBY pin Potentiometer RV3 provides adjustment of the VSTBY voltage from 75 to 1 25 volts The factory setting for RV3 is VSTBY 1 0 volts and switch is ON Cut away option CT7 allows the user to isolate the VSTBY pin of the MPC5553 from the switch With CT7 open the user must apply external battery or ground to the VSTBY position on the Power Port connector or I O header ring MPC5553DEMO 09 06 05 ANALOG Supplies MPC5553
7. and an active low Fault signal will be provided to MPC5553 EMIOS10 signal pin SW3 UP and SW4 Down User switches SW3 and SWA provide the motor speed UP and DOWN input signals when the MOTOR EN option is installed Both switches are active low SW3 UP signal is provided to the MPC5553 EMIOSS signal pin SW4 DOWN signal is provided to the MPC5553 EMIOS9 signal pin TPU Port The PORT provides an organized I O port for the MPC5553 signals MPC5553 Signal TPU Port MPC5553 Signal 3 3V 1 2 5V ETPU_A16 3 4 x ETPU_A17 5 6 x ETPU_A18 7 8 ETPU_AO ETPU_A19 9 10 ETPU A1 ETPU A20 11 12 ETPU A2 ETPU A21 13 14 ETPU ETPU 22 15 16 ETPU A4 ETPU A23 17 18 ETPU A5 ETPU A24 19 20 ETPU A6 ETPU A25 21 22 ETPU A7 ETPU A26 23 24 ETPU A8 ETPU A27 25 26 ETPU A9 ETPU A28 27 28 ETPU A10 ETPU A29 29 30 ETPU A11 ETPU A30 31 32 ETPU A12 ETPU_A31 33 34 ETPU A13 GND 35 36 ETPU A14 TCRCLK A 37 38 ETPU A15 GND 39 40 GND 15 MPC5553DEMO 09 06 05 DEVELOPMENT PORTS The MPC5553DEMO board provides 1 JTAG and 2 NEXUS type development ports Only one of the development ports should be applied due to common signals used on the ports The development port input and power signals are buffered by a CBTLV3861 device This buffer provides a bi directional 5 ohms series resistance on the input signals wh
8. 14 8 RTS OUT GND 5 919 Pins 7 and 8 maybe applied by CTS and RTS pads to MPC5553 I O RTS signal active output level is logic 0 User should place port applied at logic low 0 to enable the RTS signal and reception of bytes if applied User should apply a logic high signal under software control inform host or connected RS232 device to STOP transmitting stop sending incoming bytes CTS signal active input is level is logic 0 User should apply software to detect a logic high signal or rising edge on applied I O port and STOP transmitting bytes to the host or connected device to implement hardware flow control Detection of a logic low input indicates the host is ready to receive bytes and the user may transmit DB9 connector pin locations are provided access pads behind the connector on the DEMO board User may isolate the connection pads by cutting the associated circuit trace on the bottom of the board 10 MPC5553DEMO 09 06 05 CAN Port The CAN Port provides 9 pin connector with the Power Oak CAN transceiver interface to the MPC5553 CAN channels The CAN SEL option locations select the CAN channel is applied to the transceiver and CAN Port User may apply more than one MPC5553 CAN channel to the port if open drain TX output type is applied on the associated CAN channel transmit pins CAN SEL Option The CAN SEL option header allows selection of the MPC5553 CAN channels applied to the Power Oak transceiver and CAN Port If mor
9. 24 VDD 25 VRC33 AC26 x VDDSYN AD23 NC2 AD24 GND AD25 VDD AD26 3 3V AE23 3 3V AE24 CLKOUT AE25 GND AE26 VDD AF23 PCS C4 AF24 3 3V AF25 ENGCLK AF26 GND 22 AF5 HEADER PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL AC22 NC11 AD22 3 3V AE22 CNRX_A AF22 PCS C3 AC21 3 3V AD21 CNTX_A AE21 EMIOS23 AF21 EMIOS2 0 AC20 5V AD20 EMIOS22 AE20 EMIOS19 AF20 EMIOS1 8 AC19 EMIOS21 AD19 EMIOS17 AE19 EMIOS16 AF19 EMIOS1 4 AC18 EMIOS12 AD18 EMIOS15 AE18 EMIOS13 AF18 EMIOS1 1 AC17 EMIOS8 AD17 EMIOS10 AE17 EMIOS9 AF17 EMIOS7 AC16 EMIOS2 AD16 EMIOS6 AE16 55 AF16 EMIOS4 AC15 D14 AD15 EMIOS3 AE15 EMIOS1 AF15 EMOSO AC14 D12 AD14 015 AE14 MDIO AF14 BB AC13 3 3V AD13 D13 AE13 MDC AF13 D7 AC12 010 AD12 D11 AE12 OE AF12 D5 AC11 D8 AD11 D9 AE11 D6 AF11 3 3V AC10 RXD3 AD10 GPIO207 AE10 D4 AF10 D3 AC9 RXD2 AD9 3 3V AE9 D2 AF9 D1 AC8 3 3V AD8 RXD1 AE8 DO AF8 GPIO206 TXD1 AD7 TXD2 AE7 TXD3 AF7 RXDO AC6 TX AD6 RX DV AE6 RX ER AF6 TXDO AC5 VDD AD5 COL AE5 RX_CLK AF5 3 3V Note Indicated as AF22 AF5 on DEMO board 20
10. 5VA analog supply is provided by the Power Oak VPP regulator output Individual noise filters are applied to the 5VA supply to derive the VDDA1 and VDDA2 supplies to the MPC5553 VRH reference supply is provided by 5VA default with the VRH EN option jumper installed External VRH reference may be applied by removing the VRH EN option jumper and applying reference voltage at header ring I O pin A9 or pin 1 of the option header The analog ground supply is also noise filtered and provided to the MPC5553 VSSA pins VRL is provided by option VRL EN which is a cut away type option The QADC digital supply is provided 5 by option CT9 An optional connection to 3 3V for the QADC is provided by CT10 CT9 must be opened to install CT10 for 3 3V operation See the MPC5553 user manual for more details on operating the QADC at 3 2 V and limitations of the VDDA and VRH supplies The Power Oak may be set via the SPI control port to provide a 3 3 analog supply on the VPP output Refer to the MC33394 user manual for details USER Components The DEMO board provides an External clock option X1 8 LED indicators an 8 position DIP switch 4 push switches a speaker with amplifier and 2 user potentiometers These devices are accessed via the USER LED USER SWITCH and USER DEV I O headers DEMO board user may apply the devices to the MPC5553 I O header signals to evaluate operation or assist in code development X1 CLOCK Oscillator The X1 socket is p
11. 7 MDO1 44 GND 10 GND 28 GND 45 MDO8 11 B JCOMP 29 MDO2 46 GND 12 GND 30 GND 47 MDO10 13 TMS 31 MDO3 48 GND 14 GND 32 GND 49 MDO 1 1 15 TDI 33 NXS29 TP 50 GND 16 GND 34 GND 51 JP1 pin 2 17 35 MSEO 1 18 GND Notes 1 529 and NXS35 signals are also connected to the NEXUS connector 2 Signals followed by a symbol are active logic low J P1 Option JP1 provides signal selection for the Robust Nexus connector pin 51 Position 1 2 provides the signal and position 2 3 provides the ERSTOUT signal 1 2 3 Robust pin 51 ERSTOUT 1 2 3 Robust pin 51 1 MPC5553 I O HEADER RING 5553 I O signals are provided by the I O header ring The header ring consists of 1 inch grid pins organized in 4 rows for each side of the MPC5553 device Each row reflects the corresponding location of the MPC5553 device BGA package ball ring Signals indicated are the DEMO board primary function 18 09 06 05 MPC5553DEMO A1 HEADER PIN SIGNAL PIN SIGNAL PIN SIGNAL SIGNAL A1 GND A2 VSTBY AN37 A4 AN11 B1 VDD B2 GND B3 AN36 B4 ANS39 C1 3 3V C2 VDD C3 GND C4 8 D1 TPU A30 D2 D3 VDD 04 GND 1 E1 TPU A28 E2 TPU A2 ES 5V 4 VDD 9 F1 A24 F2 2 F3 TPU A2 F4 5V
12. CONNECIOT 13 ROR T 13 MOTOR_EN Option UNI 3 Port we HALL ENCODER Port RUN STOP Switch RV4 FAULT Adjust and Fault Indicator RR RUMP ERE 15 SW3_UP and SW4 Down 15 TPU PORT m n 15 DEVELOPMENT PORTS NEXUS POPE T ROBUST Port Option AT AFA HEADER ier meteo Pre E 19 A22 D HEADER EUR 19 A29S ARO HEADER kidera AR A E nii einen irt he T DEP TA Eee DEEP EE e EET RR Tae eed 20 22 de 20 MPC5553DEMO 09 06 05 Cautionary Notes 1 Electrostatic Discharge ESD prevention measures should be applied whenever handling this product ESD damage is not a warranty repair item 2 Axiom Manufacturing reserves the right to make changes without further notice to any products to improve reliability function or design Axiom Manufacturing does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under patent rights or the rights of others 3 EMC Information on the MPC5553DEMO board a This product as shippe
13. HDN input connection pad This pad maybe connected to a 5553 output signal to disable the amplifier with a logic high signal of 3 3V or 5V MPC5553DEMO Ports J1 10 100TX Ethernet Port MPC5553 signals 016 D31 are applied as the FEC module I O port for Ethernet 10 100TX support provided at J1 FEC signals are applied to U11 DP83848 10 100TX PHY device The J1 port provides AUTO MDIX cable connection detection for standard cross over or straight through type Ethernet CAT5E cables Three Ethernet status indicators are provided for Link Speed and Activity The PHY device may also be included in the JTAG scan signals by option JP8 Default configuration is PHY not included the scan LNK SPD and ACT Indicators Ethernet status is provided by the LNK Link status SPD 10 or 100 speed status and ACT transmit status indicators All three indicators present Green for the active condition as follows LNK ON for Ethernet network link detected No link detected if off SPD ON for 100TX operation 10TX operation if off ACT ON for MPC5553 transmit activity Off indicates idle The status indicator operation can be modified by MAC PHY commands Refer to the DP83848 and MPC5553 user manual for operation details J P8J TAG Scan Option JP8 is hardwired to exclude the U11 PHY device from the JTAG scan from the JTAG Port To include the device in the JATG scan the user should cut the hardwired trace between JP8 pins 2 and
14. M_CT 9 10 Common 2 4 6 8 X TPU_A13 PWM_CB 11 12 GROUND VSS GROUND VSS GROUND GROUND 13 14 x X 15 16 VSSA ANALOG GND 17 18 ANALOG GND VSSA X 19 20 x AN16 VS DCB 21 22 15 DCB AN17 AN18 IS A 23 24 ISB AN19 AN20 IS C 25 26 x x 27 28 TPU_A15 BRAKE 29 30 x X 31 32 X 33 34 ZX A TPU A5 TPU A6 ZX B 35 36 ZX C TPU A7 X 37 38 BEMF A AN21 AN22 BEMF_B 39 40 BEMF_C AN23 HALL ENCODER Port The Hall encoder port is provided for motor position feedback signals from the UNI 3 motor application development boards HALL HALL MPC5553 Signal Port Signal 1 5V 5V VDDH 2 GROUND VSS GROUND 3 H_1 TPU_A1 4 H2 TPU A2 5 H3 TPU AS3 6 H4 TPU A4 X H CLK TCRCLK A H CLK is derived by logic from the H 1 4 signals 14 MPC5553DEMO 09 06 05 RUN STOP Switch The RUN STOP switch is connected to the MPC5553 EMIOS11 signal pin The switch provides a motor run or stop condition input for the motor control application RV4 FAULT Adjust and Fault Indicator RV4 Fault Adjustment is provided to set the applied motor over current fault condition The IS DCB current sense input from the UNI port is compared by 016 with the RV4 setting to determine if an over current condition exists If the IS DCB input signal is greater than the RV4 setting the Fault condition becomes active The FAULT indicator will light
15. d from the factory with associated power supplies and cables has been tested and meets with requirements of CE and the FCC as a CLASS A product o This product is designed and intended for use as development platform for hardware or software in an educational or professional laboratory C In a domestic environment this product may cause radio interference in which case the user may be required to take adequate prevention measures 2 Attaching additional wiring to this product or modifying the products operation from the factory default as shipped may effect its performance and also cause interference with other apparatus in the immediate vicinity If such interference is detected suitable mitigating measures should be taken Terminology This development board applies option selection jumpers Terminology for application of the option jumpers is as follows Jumper on in or installed jumper is a plastic shunt that fits across 2 pins and the shunt is installed so that the 2 pins are connected with the shunt Jumper off out or idle jumper or shunt is installed so that only 1 pin holds the shunt no 2 pins are connected or jumper is removed It is recommended that the jumpers be idled by installing on 1 pin so they will not be lost This development board applies hardwired option selections EN and CUTAWAY 1 16 These option selections apply a circuit trace between the option pads to complete a default connec
16. e SRAM supports 4 word BURST mode access also 1 2 3 RAM_CS CS1 1 2 3 RAM CS CS0 MPC5553DEMO 09 06 05 POWER Supply This section covers the MPC5553DEMO board power supplies and options The primary power supply is the MC33394 Power Oak device configured to support the MPC5553 device The 5553 regulator provides the VDD 1 5V supply in the default configuration and CT4 Open CT2 and closed Power Oak 1 5V supply may be applied by optional configuration to provide the VDD 1 5V supply CT1 and 4 closed CT2 and CT3 open Power On Reset is provided to the MPC5553 by the Power Oak PORESETB output by default SO option closed The Power Oak HRESETB signal may be applied instead by S1 closed and 0 open Power Oak controls are provided by MPC5553 QSPIA These signals maybe isolated for other applications by opening options S2 S5 ON OFF Switch The ON OFF toggle switch provides ignition on and off control to the MC33394 Power Oak supply The Power Oak device will enable and disable the main power supplies With the switch in the ON position all power indicators should light Inspect input power connection and source and fuse F1 if power indication does not occur PWR Power Jack The Power Jack provides the default power input to the board The jack accepts a standard 2 0 2 1mm center barrel plug connector positive voltage center to provide the VIN supply of 6 to 24
17. e that one transmit channel is applied transmit pins must apply the open drain output feature Note that the MPC5553 only provides CAN channels A and C channel B support is provided for MPC5554 POSITION MPC5553 CAN SIGNAL CNTX A channel A TX out DEFAULT enabled CNRX A channel A RX in DEFAULT enabled 6 C chamelCRXin Following is the DB9S connection reference CAN PORT 1 1 X CAN port has a Female socket type DB9 0 2 6 GND 3 7 414 8 8 515 99 CAN HI and CAN LO signals are terminated together with 120 ohms R68 DB9 connector pin locations are provided access pads behind the connector on the DEMO board for additional user application 11 MPC5553DEMO 09 06 05 LIN J1 The LIN J1 port provides a Master Mode LIN network connection The MPC5553 device provides a LIN Master type node on the LIN Network A LIN physical layer transceiver U7 MC33661 or similar is provided between the MPC5553 device and the LIN network connector Refer to the MC33661 data sheet for complete details of transceiver operation The following diagram represents the LIN connection MPC5553 MC33661 The LIN interface provides optional features of slew rate control network supply and wake up option See the JP5 JP6 JP7 and options following Option MPC5553 I O signal GPIO205 provides LIN transceiver U7 enable control EN pin Software cont
18. en powered on The buffer also provides signal isolation when powered off NOTE Proper power sequencing must be performed when a development port is applied cable connected Development port application power sequence 1 MPC5553DEMO board ON OFF switch is OFF and no power is applied to the PWR connector 2 Connect development port cable to the desired MPC5553DEMO board development port 3 Apply power to the MPC5553DEMO board PWR connector and turn ON OFF switch ON 4 If power is removed or the ON OFF switch is turned off remove development cable from board connector and re apply from step 1 of this procedure J TAG Port The JTAG port provides a Freescale standard JTAG connection to the MPC5553 connector is a standard 2x7 1 inch pin space keyed pin header Example compatible cables include the OCDEMON NP JTAG ONCE Wiggler and the P amp E Microcomputer Systems CABPPCNEXUS Host software must be applied to operate the cables JTAG Port Signal Pin Pin Signal B TDI 1 2 GND TDO 3 4 GND B TCK 5 6 GND JTG7 TP 7 8 JTG8 TP B RESET 9 10 B TMS 3 3V 11 12 GND B RDY 13 14 B JCOMP Notes 1 B_ signals are buffered 2 JTGx signals are not connected to the MPC5553 and provide a Test Pad on the board 3 Signals followed by a symbol are active logic low 4 See the J1 Ethernet section about JP8 and the PHY device JTAG 16 MPC5553DEMO 09 06 05
19. ith 10K ohm resistors when the switch position in the off position Switch positions placed in the ON position will provide a 3 3V output to the connector USER DEV User DEV provides access to the 4 push switches SW1 SW4 speaker and 2 user potentiometers RV1 and RV2 PIN amp USER COMPONENT CONNECTION SW1 out de bounced CMOS drive 0 or 3 3V active low SW1 out de bounced Open Drain output active low 10K ohm pull up to 3 3V Suitable for IRQ input signal drive SW out active low 10K ohm pull up to 3 3V 6 SPEAKER amp input 0 to 5Vpp volume adjust with SPKR VOL 8 2 0 5Vadjstment O SW1 5 4 Push Switches The push switches provide momentary active low input for user applications SW1 has additional features of being de bounced for no glitch operation and push pull output on pin 1 or open drain output on pin 2 Typical user application would be to provide program control or menu selection input UP and 5 4 Down are also provided for the UNI Port motor control operation when the MOTOR EN option is installed MPC5553DEMO 09 06 05 SPEAKER and SPKR VOL The speaker and amplifier provide user applications with a method to generate sound effects from a MPC5553 output Frequency range of the amplifier input is 300Hz to 10Khz The SPKR VOL potentiometer allows user adjustment of the sound effect volume from the speaker The amplifier also provides a S
20. not overload the F1 fuse and verify only one source is applied on the network LIN J 1 Connector The LIN J1 network connector provides a standard pin configuration with a network option position on pin 2 Front view looking into connector from outside of board edge Mating connector Molex 39 01 2040 with 39 00 0039 pins LIN Signal V Output JP5 Option JP4 Ground UNL 3 Motor Control Port The UNI Motor Control Port is provided for easy application of the Freescale UNI 3 Motor control application boards and motors Many of the MPC5553 signals are applied for the UNI 3 motor control application so the user should review application carefully UNI 3 port operation is enabled by the MOTOR EN option jumper installation 13 MPC5553DEMO 09 06 05 MOTOR EN Option This option controls the connection of the MPC5553 I O ports to the UNI 3 and HALL ENCODER motor control ports When installed signal buffers 013 and U15 are enabled to apply MPC5553 for motor control UN 3 Port The UNI 3 port is the primary motor control I O port for application of the UNI motor control development boards Following are the signal assignments MPC5553 Signal UNI 3Signal UNI 3Port UNI 3 Signal MPC5553 Signal TPU A8 PWM AT 1 2 Common 4 6 8 10 x TPU A9 PWM AB 3 4 Common 2 6 8 10 x TPU_A10 PWM_BT 5 6 Common 2 4 8 10 x TPU_A11 PWM_BB 7 8 Common 2 4 6 10 x TPU_A12 PW
21. rol of the EN pin allows the user to set the slew rate control of the transceiver User applications should configure the GPIO205 pin for output to operate the LIN transceiver If 205 is needed for other purposes the CT8 option maybe cut to isolate the signal from the LIN transceiver and JP4 installed to provide an enable to the transceiver Refer to the MC33361 data sheet for further details of operation J P4 Option Installation of JP4 applies a pull up resistor on the LIN transceiver enable pin MPC5553 GPIO205 may still control the transceiver enable operation when is installed J P5 Option JP5 selects the MPC5553 SCI RXDB signal input to be from the LIN transceiver For LIN operation JP5 must be installed J P6 Option JP6 is wired closed by default and not populated JP6 provides the MPC5553 TXDB signal to the LIN transceiver User may cut the JP6 wire trace to isolate the TXDB signal 12 MPC5553DEMO 09 06 05 J P7 Option LIN J1 connector pin 2 may be configured for different network requirements by JP7 JP7 open will disconnect LIN J1 pin 2 from the DEMO board 1 2 3 LIN J1 pin 2 Ground VSS 1 2 3 LIN J1 pin 2 Transceiver WAKE pin LIN PWR Option Installation of the LIN PWR option applies MPC5553DEMO V input voltage for LIN network power to LIN J1 pin 3 This connection allows the DEMO board to operate as a LIN master node to power remote LIN slave nodes User should use caution to
22. rovided to install standard 5V compatible CAN type clock oscillators so that alternate clock source or frequencies maybe applied to the MPC5553 User should refer to the MPC5553 device user manual for information on frequency selection and clocking configuration X1 clock signal is provided to the MPC5553 by option pad set CT16 being closed by 0 ohm resistor or mod wire application CUT AWAY option CT5 must be opened to remove the Y1 crystal from the EXTAL signal or problems may occur with operation User should review the 5553 user guide for proper PLLCFGO and PLLCFG1 CONFIG Switch 4 and 5 option settings if an external clock is applied RV1 and RV2 User Potentiometers The User Potentiometers provide an adjustable linear voltage output from 0 to 5V The voltage signal may be applied to an MPC5553 analog input port for user application MPC5553DEMO 09 06 05 USER LED User LED header provides access to the user LED 1 to 8 Connector pin 1 to 8 organization is provided in a one to one method to the individual indicators LED 1 to 8 The LED indicators are buffered for minimal drive current requirement 300ua Indicators will turn on with a logic high or 2 5 to 5V input at the respective connector pin USER Switch User Switch provides access to the user 8 position DIP Switch Connector pin 1 to 8 organization is provided in a one to one organization to the individual DIP switch positions 1 to 8 The switch connections are pulled low w
23. tion This type connection places an equivalent Jumper Installed type option The circuit trace between the option pads maybe cut with a razor blade or similar type knife to isolate the default connection provided Applying the default connection again can be performed by instaling the option post pins and shunt jumper or by applying a wire between the option pads MPC5553DEMO 09 06 05 MPC5553DEMO Configuration CONFIG Switch The CONFIG switch provides reset configuration options for the MPC5553 device Configuration options are enabled by position 1 of the switch Switch positions 2 6 OFF provide an active low output condition to the respective configuration signal Switch position ON will provide an active high signal condition 6 WKPCFG ON default Refer to Freescale MPC5553 Documentation 1 OFF default Refer to Freescale MPC5553 Documentation BOOTCFGO ON default Refer to Freescale MPC5553 Documentation 1 CONFIG enable OFFz default ON enables the RCON configuration to be applied from the switch settings SRAM SEL Option MPC5553DEMO board provides a 256K x 18 synchronous SRAM U2 on the 16 bit data bus 00 015 SRAM bits 16 17 are not applied SRAM SEL provides selection of the 0 or CS1 chip selects to access the external SRAM U2 on the DEMO board Chip select configuration should be set for 0 wait states 512K byte memory range WE signals Write Enable Th
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MPC5553DEMO