EVBUM2281 - KAI-11002 Imager Board User`s Manual
Contents
1. RIGHT RCLK RCLK V2 DRIVER 1 SHOT DRIVER CCD SENSOR FDG vi EF gt DRIVER CKT HiL POT TIMING H1A H2A H1B H2B DRIVERS ADJUST DRIVER DRIVER DRIVER DRIVER LVDS TO TTL BUFFERS 15V REGULATOR 15V REGULATOR J1 BOARD INTERFACE CONNECTOR Figure 1 KAl 11002 Imager Board Block Diagram LINEARITY 100000 10000 1000 E MEASURED m 100 10 DEVIATION FROM FIT d 1 lt D 0 1 0 01 INTEGRATION TIME SECONDS Figure 2 Measured Performance Linearity http onsemi com 6 Noise A D counts EVBUM2281 D Photon Transfer 100 X Slope el Adu 18 82 electrons Noise floor 1 49 counts 28 electrons 10 LVSAT 63386 electrons LXX LX x VSAT 69126 electrons 1 10 100 1000 10000 100000 Signal Mean Electrons Figure 3 Measured Performance Dynamic Range and Noise Floor http onsemi com 7 EVBUM2281 D CONNECTOR ASSIGNMENTS AND PINOUTS SMB Connectors J2 and J3 The emitter follower buffered CCD_VOUT signals are 75 should be used to connect the imager board to the driven from the Imager Board via the SMB connectors J2 Timing Generator Board to match the series and terminating and J3 Coaxial cable with a characteristic impedance of resisto2. VPLUS and VMINUS supplies onto the Substrate voltage This creates the necessary potential to clear all charge from the photodiodes thereby acting as an electronic shutter to control exposure CCD Bias Voltages The CCD bias voltages are set by potentiometers buffered by operational amplifiers configured as voltage followers The bias voltages are de coupled at the CCD pin Emitter Follower The VOUT CCD signals are buffered using bipolar junction transistors in the emitter follower configuration These circuits also provide the necessary 5 mA current sink for the CCD output circuits CCD Image Sensor This evaluation board supports the KAI 11002 Image Sensor Line Drivers The buffered VOUT CCD signals are AC coupled and driven from the Imager Board by operational amplifiers in a non inverting configuration The operational amplifiers are configured to have a gain of 2 to correctly drive 75 Q video coaxial cabling from the SMB connectors http onsemi com 2 EVBUM2281 D OPERATIONAL SETTINGS The Imager board is configured to operate the KAI 11002 were correct at the time of this document s publication but Image Sensors under the following operating conditions may be subject to change refer to the KAI 11002 device specification DC Bias Voltages The following voltages are fixed or adjusted with a potentiometer as noted The nominal values listed in Table 3 Table 3 DC BIAS VOLTAGES Left Output Amplifier Supply VD
3. the board INPUT REQUIREMENTS Table 1 POWER REQUIREMENTS ee L Ss a eee eee Table 2 SIGNAL LEVEL REQUIREMENTS mam fa H2B T g e H P 0 1 V1 4 0 weg 9 weg weg merwarg 9 Semiconductor Components Industries LLC 2014 October 2014 Rev 2 0 0 0 0 2 al m P EZA op sw Ce 5 1 4 9 21 18 ws Publication Order Number EVBUM2281 D EVBUM2281 D ARCHITECTURE OVERVIEW The following sections describe the functional blocks of the KAI 11002 Imager Board Refer to Figure 1 Power Filtering and Regulation Power is supplied to the Imager Board via the J1 interface connector The power supplies are de coupled and filtered with ferrite beads and capacitors to suppress noise Voltage regulators are used to create the 15 V and 15 V supplies from the VPLUS and VMINUS supplies LVDS Receivers TTL Buffers LVDS timing signals are input to the Imager Board via the J1 interface connector These signals are shifted to TTL levels before being sent to the CCD clock drivers CCD Pixel Rate Clock Drivers H1 H2 amp Reset Clocks The pixel rate CCD clock drivers utilize two fast switching transistors that are designed to translate TTL level input clock signals to the voltage l
4. DL 15 0 Right Output Amplifier Supply VDDR 15 0 Reset Drain VRD s 12 0 ESD Protection ESD Substrate VSUB 8 5 Output Gate Left VOGL 7 5 Output Gate Right VOGR 7 5 Ground P well GND 1 Ifthe CCD is to be operated in single output mode only VOUT LEFT the unused output amplifier supply can be tied to ground to conserve power by not populating R71 R72 and C76 and by replacing C75 with a 0 Q resistor 2 The Output Gate signals VOGL and VOGR may be controlled independently or by installing R28 and R33 and removing R29 may be set to the same potential controlled by R11 3 The Min and Max voltages in the table indicate the imager board potentiometer adjustable voltage range These values may exceed the specified CCD operating conditions See the KAI 11002 device specification for details Clock Voltages Table 4 were correct at the time of this document s The following clock voltage levels are fixed or adjusted publication but may be subject to change refer to the with a potentiometer as noted The nominal values listed in KAI 4011 KAI 4021 KAI 04022 device specification Table 4 CLOCK VOLTAGES 7 Sims te Nam Usi rotorene Weis Horizontal CCD Clock Phase 1A H1A CCD xe pere sur nur e 2 me 5 Horizontal CCD Clock Phase 1B H1B CCD EN a EN 2 me HCCD Last Gate Clock Phase 1L H1L CCD Du pup oe ee pa pp e Ho
5. EVBUM2281 D KAI 11002 Imager Board User s Manual Description The KAI 11002 Imager Evaluation Board referred to in this document as the Imager Board is designed to be used as part of a two board set in conjunction with a Timing Generator Board ON Semiconductor offers an Imager Board Timing Generator Board package that has been designed and configured to operate with the KAI 11002 Image Sensor The Timing Generator Board generates the timing signals necessary to operate the CCD and provides the power required by the Imager Board The timing signals in LVDS format and the power are provided to the Imager Board via the interface connector J1 In addition the Timing Generator Board performs the processing and digitization of the analog video output of the Imager Board The KAI 11002 Imager Board has been designed to operate the KAI 11002 with the specified performance at ON Semiconductor www onsemi com EVAL BOARD USER S MANUAL 30 MHz pixel clocking rate and nominal operating conditions See the KAI 11002 performance specifications for details For testing and characterization purposes the KAI 11002 Imager Board provides the ability to adjust many of the CCD bias voltages and CCD clock level voltages by adjusting potentiometers on the board The Imager Board provides the means to modify other device operating parameters CCD reset clock pulse width VSS bias voltage by populating components differently on
6. Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2281 D
7. The One Shot can be configured to provide a RESET CCD clock signal with a pulse width from 5 ns to 15 ns CCD VCLK Drivers The vertical clock VCLK drivers consist of MOSFET driver IC s These drivers are designed to translate the TTL level clock signals to the voltage levels required by the CCD The high middle and low voltage levels of the vertical clocks are set by potentiometers buffered by operational amplifiers configured as voltage followers The current sources for these voltage levels are high current up to 600 mA transistors The V2 CCD high level clock voltage is switched from V MID to V HIGH once per frame to transfer the charge from the photodiodes to the vertical CCDs See Table 6 and Table 7 for vertical clocking voltage level options CCD FDG Voltages The Fast Dump Gate FDG driver is a transistor that will switch the voltage on the FDG pin of the CCD from FDG LOW to FDG HIGH during Fast Dump Gate operation When not in operation or when the Fast Dump Gate feature is not being utilized the FDG pin of the CCD is held at FDG LOW The FDG HIGH and FDG LOW voltage levels of the FDG driver are set by resistor divider circuits and are buffered by operational amplifiers configured as voltage followers VES Circuit The quiescent CCD substrate voltage VSUB is set by a potentiometer For electronic shutter operation the VES signal drives a transistor amplifier circuit which AC couples the voltage difference between the
8. ers including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT American Technical Support 800 282 9855 Toll Free Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe
9. evels required by the CCD The high and low voltage levels of the CCD clocks are set by potentiometers buffered by operational amplifiers configured as voltage followers For the H1A and H2A clock drivers which require larger amounts of drive current due to the larger capacitive load presented by the CCD the current source of the high and low voltage levels is a high current up to 600 mA transistor configured as an emitter follower For better current drive capability an extra pair of transistors may be populated in parallel For the other clock drivers H1L RESET that have much smaller loads the drive current is supplied by the buffer op amp itself Because the H1 and H2 clock rails are adjusted independently the H1B and H2B clock driver voltage rails are selected by using four jumpers 1 4 In single output mode the H1B and H2B rails are connected to the H1A and H2A rails respectively In dual output mode the H1B and H2B rails should be connected to the H2A and rails respectively See Table 5 for details H1L CCD Timing Adjustment Potentiometers Minor timing adjustments can be made to the HIL CCD right and left clock positions using the delay adjust potentiometers R180 and R181 Each potentiometer along with a capacitor forms an RC network that acts to delay the position of the H1L clock with respect to the H1A clock Reset Clock One Shot The pulse width of the RESET CCD clock is set by a programmable One Shot
10. n Board Kit may at their discretion make changes to the Timing Generator Board firmware ON Semiconductor can only support firmware developed by and supplied by ON Semiconductor Changes to the firmware are at the risk of the customer E mail info truesenseimaging com ON Semiconductor reserves the right to change any information contained herein without notice All information furnished by ON Semiconductor is believed to be accurate ON Semiconductor and the ON are registered trademarks of Semiconductor Components Industries LLC SCILLC or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating paramet
11. ocking mode only See Table 6 and Table 7 Vertical Clocking Modes Not applicable for all devices see KAI 11002 device specifications 10 H1B and H2B high and low clock voltages are connected either to H1A High and Low or H2A high and low depending on the output mode of operation See Table 5 COND Table 5 HCLK JUMPER SETTINGS Jumper Setting Clock Level Voltage Set To Notes E1 100 H2B LOW H1A LOW Default E1 20UT H2B LOW H2A LOW Four level vertical clocking mode only Not applicable for all devices see device specifications http onsemi com 4 EVBUM2281 D Table 7 V2 VERTICAL CLOCKING MODES 15V 0 1 1 Four level vertical clocking mode only Not applicable for all devices see device specifications 15V 1 1 1 Four level vertical clocking mode only Not applicable for all devices see device specifications Reset Clock Pulse Width The pulse width of RESET_CCD is set by configuring can be tied high or low to achieve the desired pulse width by P 2 0 the inputs to the programmable one shot P 2 0 populating the resistors R161 164 accordingly Table 8 RESET CLOCK PULSE WIDTH http onsemi com 5 EVBUM2281 D BLOCK DIAGRAM AND PERFORMANCE DATA J2 J3 SMB SMB LINE EMITTER EMITTER __ LINE DRIVER FOLLOWER FOLLOWER DRIVER V V3RD DRIVER VOUT LEFT VOUT
12. rizontal CCD Clock Phase 2A H2A_CCD gt pev o2 pu p ome Connected to CCD pins 8 9 and 13 H1SL H1BL and H1SR Connected to CCD pin 12 H1BR H1L Left connected to CCD pin 5 H1BINL H1L Right connected to CCD pin 16 H1BINR Connected to CCD pins 7 10 and 14 H2SL H2BL and H2SR Connected to CCD pin 11 H2BR Four level vertical clocking mode only See Table 6 and Table 7 Vertical Clocking Modes Not applicable for all devices see KAI 11002 device specifications 10 H1B and H2B high and low clock voltages are connected either to H1A High and Low or H2A high and low depending on the output mode of operation See Table 5 lt lt lt lt lt lt lt lt lt lt NDO OA http onsemi com 3 EVBUM2281 D Table 4 CLOCK VOLTAGES Besson Sis ise Mm Nom Wax Uni Nores uw p o9 T 1 m p T m Par 3 8 T Fast Dump Clock pedro 2200 ag 2 uS gu Connected to CCD pins 8 9 and 13 H1SL H1BL and H1SR Connected to CCD pin 12 H1BR H1L Left connected to CCD pin 5 H1BINL H1L Right connected to CCD pin 16 H1BINR Connected to CCD pins 7 10 and 14 H2SL H2BL and H2SR Connected to CCD pin 11 H2BR Four level vertical cl
13. rs used on these boards Table 9 J1 INTERFACE CONNECTOR PIN ASSIGNMENTS Pin Signal Pin Signal 1 N C N C AGND V3RD 11 13 s 7 19 21 23 VES AGND AGND ooo 25 27 29 31 V2 1 R V AGND AGND 2 jme ea m 26 28 30 32 56 58 60 62 64 BET RN REPETI IGNES ft SET AGND H2A AGND 3 5 7 9 1 495 51 53 2 3 3 3 3 4 4 4 4 4 C 55 57 AGND 59 AMP_ENABLE 61 5 V_MTR VMINUS_MTR N C AGND AMP_ENABLE 5 V_MTR 63 N C N C AGND AGND 5 V_MTR 5 V_MTR N C N C C AGND VPLUS MTR N VPLUS MTR C 65 67 n E 75 77 3 9 C 7 http onsemi com 8 EVBUM2281 D Warnings and Advisories Ordering Information ON Semiconductor is not responsible for customer Please address all inquiries and purchase orders to damage to the Imager Board or Imager Board electronics The customer assumes responsibility and care must be taken Truesense Imaging Inc when probing modifying or integrating the 1964 Lake Avenue ON Semiconductor Evaluation Board Kits Rochester New York 14615 Phone 585 784 5500 When programming the Timing Board the Imager Board must be disconnected from the Timing Board before power is applied If the Imager Board is connected to the Timing Board during the reprogramming of the Altera PLD damage to the Imager Board will occur Purchasers of an Evaluatio
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