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A13 User Manual V1.30 - linux

1. 700MHz gt CONTROL LOGIC e RGB LA 2vyU 1 DATA DMA OUTO Async FIFOI e FA v FORMATTER 444 El HV TIMING OUT2 Fr 3 Channel CPU TIMING To FIFO Flag BASIC 2 amp TIMING es mM lt gt crock GENERATOR e GC LVDS TIMING x OUT CEU Gamma TV TIMING Async FIFO2 GENERATOR Figure 29 1 LCD TV Timing Controller Block Diagram 29 2 TCON Register List Module Name Base Address TCON 0x01C0C000 Register Name Offset Description TCON GCTL REG 0x0000 TCON Global Control Register TCON GINTO REG 0x0004 TCON Global Interrupt RegisterO TCON GINT1 REG 0x0008 TCON Giobal Interrupt Register1 TCONO FRM CTL REG 0x0010 TCON FRM Control Register TCONO FRM SEEDO REG 0x0014 TCON FRM Seed RegisterO TCONO FRM SEED1 REG 0x0018 TCON FRM Seed Register1 TCONO FRM SEED2 REG 0x001C TCON FRM Seed Register2 TCONO FRM SEED3 REG 0x0020 TCON FRM Seed Register3 TCONO FRM SEED4 REG 0x0024 TCON FRM Seed Register4 TCONO FRM _SEED5 REG 0x0028 TCON FRM Seed Register5 TCONO FRM TABO REG 0x002C TCON FRM Table Register0 TCONO_FRM_TAB1_REG 0x0030 TCON FRM Table Register1 TCONO_FRM_TAB2_REG 0x0034 TCON FRM Table Register2 TCONO FRM TAB3 REG 0x0038 TCON FRM Table Register3 TCONO CTL REG 0x
2. Technology 26 5 2 CCIR656 Header Decode Decode F V H P3 P2 P1 PO Field 1 start of active video SAV 0 0 0 0 0 0 0 Field 1 end of active video EAV 0 0 1 1 1 0 1 Field 1 SAV digital blanking 0 1 0 1 0 1 1 Field 1 EAV digital blanking 0 1 1 0 1 1 0 Field 2 SAV 1 0 0 0 1 1 1 Field 2 EAV 1 0 1 1 0 1 0 Field 2 SAV digital blanking 1 1 0 1 1 0 0 Field 2 EAV digital blanking 1 1 1 0 0 0 1 26 6 CSI Timing Diagram vsync nirames n 1 frame hsyne if Loo active data firstline data gt ff lastline data Vref Positive Href Positive Ven ff H n frame ff n 1 frame le n lines rh m lines hsync W H H e vertical stat line n vertical active line length m Vertical Size Setting j n clock zk m clocks gt hsyne _ ff H _ active data X x X X iS A A A X fo active in rising piet ge SVV q KEE heer evecare AAAA horizontal start clock n horizontal active clocks length m Horizontal Size Setting and Pixel Clock Timing Href positive A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 275 Allwinner Technology 27 Display Engine Front End DEFE 27 1 Overview The Display Engine Front End DEFE performs image capture driver video graphic scale format conversion and color space conversion It is composed of DMA controller input controller scaler color space conversion and output controller as show in figure 27 1 The DEF
3. 5 3 4 PMU AXI Clock Range Register Offset 0x20 Register Name PMU AXI AUTO SWT REGO Bit regain EE Description rite Hex 31 27 26 16 RAW 0x0 AXI CLK LEVEL1 AXICLK level 1 15 11 10 RW Wee AXI CLK LEVELO AXICLK level 0 5 3 5 PMU AXI Clock Range Register1 Offset 0x24 Register Name PMU AXI AUTO SWT REG1 f Read W Default SE Bit Description rite Hex 31 27 AXI CLK LEVE3 SC e ae AXICLK level 3 15 11 AXI CLK LEVEL2 e EE hii AXICLK level 2 5 3 6 PMU DVFS Control Register 3 Offset 0x18 Register Name PMU DVFS CTRL REG3 f Read W Default D Bit i Description rite Hex 31 0 5 3 7 PMU DVFS TimeOut Control Register Default 0x00000027 Offset 0x1C Register Name PMU DVFS TIMEOUT CTRL REG Read W Default WE Bit Description rite Hex 31 6 DVFS TIMEOUT DVFS operate on TWI timeout cycles in TWI peripheral clock 0 1 cycle 5 0 R W 0x27 fa 0x27 40 cycles 0x3F 64 cycles A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 34 5 3 8 Allwinner Technology PMU IRQ En Register Offset 0x40 Register Name PMU IRQ EN REG Bit Read W rite Default Hex Description 31 13 12 RW Ox0 VOLT DET ERR IRQ EN Voltage Detect Error IRQ Enable 0 Disable 1 Enable 11 RW Ox0 DVFS CLK SWTH ERR IRQ EN DVFS Clock Switch Operation
4. Register Name PD CFG1 Offset 0x70 Default Value 0x0000 0000 Bit Read Write Default Description 31 PD15 Select 000 Input 001 Output 010 LCD_D15 011 ERXERR 100 101 30 28 R W 0 110 111 27 PD14 Select 000 Input 001 Output 010 LCD D14 011 ERXCK 100 101 26 24 R W 0 110 111 23 PD13 Select 000 Input 001 Output 010 LCD D13 011 ERXD3 100 101 22 20 R W 0 110 111 19 PD12 Select 000 Input 001 Output 010 LCD_D12 011 ERXD2 100 101 18 16 R W 0 110 111 15 PD11 Select 000 Input 001 Output 010 LCD_D11 011 ERXD1 100 101 14 12 R W 0 110 111 11 PD10 Select 000 Input 001 Output 010 LCD_D10 011 ERXDO 100 101 10 8 R W 0 110 111 7 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 377 Allwinner Technology 6 4 R W 0 3 2 0 R W 0 33 4 21 PD Configure Register 2 Register Name PD CFG2 Offset 0x74 Default Value 0x0000 0000 Bit Read Write Default Description 31 PD23 Select 000 Input 001 Output 010 LCD D23 011 ETXEN 100 101 30 28 R W 0 110 111 27 PD22 Select 000 Input 001 Output 010 LCD_D22 011 ETXD3 100 101 26 24 R W 0 110 111 23 PD21 Select 000 Input 001 Output 010 LCD_D21 011 ETXD2 100
5. DEFEO 0x01E00000 Register Name Offset Description DEFE EN REG 0x0000 DEFE Module Enable Register DEFE FRM CTRL REG 0x0004 DEFE Frame Process Control Register DEFE BYPASS REG 0x0008 DEFE CSC By Pass Register DEFE AGTH SEL REG 0x000C DEFE Algorithm Selection Register DEFE LINT CTRL REG 0x0010 DEFE Line Interrupt Control Register DEFE BUF ADDRO REG 0x0020 DEFE Input Channel 0 Buffer Address Register DEFE BUF ADDR1 REG 0x0024 DEFE Input Channel 1 Buffer Address Register DEFE BUF ADDR1 REG 0x0028 DEFE Input Channel 2 Buffer Address Register DEFE FIELD CTRL REG 0x002C DEFE Field Sequence Register DEFE TB OFFO REG 0x0030 DEFE Channel 0 Tile Based Offset Register DEFE TB OFF1 REG 0x0034 DEFE Channel 1 Tile Based Offset Register DEFE TB OFF2 REG 0x0038 DEFE Channel 2 Tile Based Offset Register DEFE LINESTRDO REG 0x0040 DEFE Channel 0 Line Stride Register DEFE LINESTRD1 REG 0x0044 DEFE Channel 1 Line Stride Register DEFE LINESTRD2 REG 0x0048 DEFE Channel 2 Line Stride Register DEFE INPUT FMT REG 0x004C DEFE Input Format Register DEFE_WB_ADDRO_REG 0x0050 DEFE Channel 3 Write Back Address Register DEFE OUTPUT FMT REG 0x005C DEFE Output Format Register DEFE INT EN REG 0x0060 DEFE Interrupt Enable Register DEFE INT STATUS REG 0x0064 DEFE Interrupt Status Register DEFE STATUS REG 0x0068 DEFE Status Register DEFE CSC COEF00 REG 0x0070 DEFE CSC Coefficient 00 Register DEFE CSC COEFO1 REG 0x0074 DEFE CSC Coefficient 01 Register D
6. Reserved This bit is reserved for future use and should return a value of zero when read R W 0 Port Reset 1 Port is in Reset 0 Port is not in Reset Default value 0 When software writes a one to this bit from a zero the bus reset sequence as defined in the USB Specification Revision 2 0 is started Software writes a zero to this bit to terminate the bus reset sequence Software must keep this bit at a one long enough to ensure the reset sequence as specified in the USB Specification Revision 2 0 completes Notes when software writes this bit to a one it must also write a zero to the Port Enable bit Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero The bit status will not read as a zero until after the reset has completed If the port is in high speed mode after reset is complete the host controller will automatically enable this port e g set the Port Enable bit to a one host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero For example if the port detects that the attached device is high speed during reset then the host controller must have the port in the enabled state with 2ms of software writing this bit to a zero The HC Halted bit in the USBSTS register should be a zero before software attempts to use this
7. Module Name Base Address CSI 0x01C00900 Register Name Offset Description CSI EN REG 0x0000 CSI Enable Register CSI CFG REG 0x0004 CSI Configuration Register CSI CPT CTRL REG 0x0008 CSI Capture Control Register CSI FIFO0 BUF A ADDR REG 0x0010 CSI FIFOO Buffer A Register CSI FIFO0 BUF B ADDR REG 0x0014 CSI FIFOO Buffer B Register CSI FIFO1 BUF A ADDR REG 0x0018 CSI FIFO1 Buffer A Register CSI FIFO1 BUF B ADDR REG 0x001C CSI FIFO1 Buffer B Register CSI BUF CTRL REG 0x0028 CSI Buffer Contrl Register A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 267 Allwinner Technology CSI STA REG 0x002C CSI Status Register CSI INT EN REG 0x0030 CSI Interrupt Enable Register CSI INT STA REG 0x0034 CSI Interrupt Status Register CSI WIN CTRL W REG 0x0040 CSI Window Width Control Register CSI WIN CTRL H REG 0x0044 CSI Window Height Control Register CSI BUF LEN REG 0x0048 CSI Buffer Length Register 26 4 CSI Register Description 26 4 1 CSI Enable Register Name CSI EN REG Default Value 0X00000000 Offset 0X0000 Read Default He Bit Description Write D P 31 01 Reserved EN CSI Enable R W 0 ve 0 Reset and disable 1 Enable 26 4 2 CSI Configuration Register Register Name CSI CFG REG ffset Add 0X0004 m Si lee Default Value 0X00000000 Read Wr Default Bi
8. ADC_REF 24 KEY_DOWN_IRQ gt moles 26 HOLD_KEY_IRQ Control Logic x ADC_REF SSP 525 24 3 LRADC Register List Module Name Base Address LRADC 0x01C22800 Register Name Offset Description LRADC_CTRL 0x00 LRADC Control Register LRADC_INTC 0x04 LRADC Interrupt Control Register LRADC_INTS 0x08 LRADC Interrupt Status Register LRADC_DATAO 0x0c LRADC Data Register 0 LRADC_DATA1 0x10 LRADC Data Register 1 24 4 LRADC Register Description 24 4 1 LRADC Control Register Offset 0x00 Register Name LRADC_CTRL Bit Read Default Description Write Hex 31 24 RW 0x1 FIRST_CONCERT_DLY ADC First Convert Delay setting ADC conversion is delayed by n samples 23 22 RW 0x0 ADC_CHAN_SELECT ADC channel select 00 ADCO channel 01 ADC1 channel 1x ADCO amp ADC1 channel 21 20 19 16 RW 0x0 CONTINUE_TIME_SELECT Continue Mode time select one of 8 N 1 sample as a valuable sample data A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 247 Allwinner Technology 15 14 13 12 R W 0x0 KEY_MODE_SELECT Key Mode Select 00 Normal Mode 01 Single Mode 10 Continue Mode R W 0x1 LEVELA B CNT Level A to Level B time threshold select judge ADC convert value in level A to level B in n 1 samples RW 0x1 LRADC_HOL
9. 23 4 8 ADC RX DATA Register Register Name AC_ADC_RXDATA Offset 0x24 Default Value 0x0000 0000 Bit Read Write Default Description RX DATA RX Sample Host can get one sample by reading this register The left channel 31 0 R 0x0 sample data is first and then the right channel sample 23 4 9 ADC Analog Control Register Offset 0x28 Register Name AC_PA_ADC_ACTRL Bit R W Default Description 31 R W 0x0 ADCREN ADC Right Channel Enable 0 Disable 1 Enable 30 R W 0x0 ADCLEN ADC Left Channel Enable 0 Disable 1 Enable 29 R W 0x0 PREG1EN MIC1 pre amplifier Enable A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 242 Allwinner Technology 0 Disable 1 Enable 28 RW Ox0 PREG2EN MIC2 pre amplifier Enable 0 Disable 1 Enable 27 RW Ox0 VMICEN VMIC pin voltage enable 0 disable 1 enable 26 25 R W 0x2 PREG1 MIC1 pre amplifier Gain Control 00 0dB 01 35dB 10 38dB 11 41dB 24 23 R W 0x2 PREG2 MIC2 pre amplifier Gain Control 00 0dB 01 35dB 10 38dB 11 41dB 22 20 R W 0x3 ADCG ADC Input Gain Control 000 4 5dB 001 3dB 010 1 5dB 011 0dB 100 1 5dB 101 3dB 110 4 5dB 111 6dB 19 17 RW 0x2 ADCIS ADC input source select 000 left select LINEINL right select LINEINR or b
10. Technology PLL3x1 LCD CH1 CLK2 ee PLL7x1 CLK OUT CLK IN M ee M 1 16 PLE3x2 LCD CH1 CLK1 CLK_OUT CLK_IN M PLL7x2 Me OSC24M CSI CLK CSI CLK OUT PLL3x1 CLK OUT CLK IN M M 1 32 PLL7x1 PLL3x2 PLL7x2 VE CLK OUT PLLA VE CLK Lech AUDIOCODEC CLK OUT PLL2 AUDIOCODEC CLK AVS CLK OUT OSC24M AVS CLK OSC24M MBUS CLK Max 300MHz CLK_OUT CLK_IN M N MBUS CLK OUT PLL6 Lk M 1 16 N 1 2 4 8 PLL5 Figure6 3 Bus Clock Generation Part 2 6 3 CCM Register List Module Name Base Address CCM 0x01C20000 Register Name Offset Description PLL1 CFG REG 0x0000 PLL1 Control PLL1 TUN REG 0x0004 PLL1 Tuning A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 51 Allwinner Technology PLL2 CFG REG 0x0008 PLL2 Control PLL2 TUN REG 0x000C PLL2 Tuning PLL3 CFG REG 0x0010 PLL3 Control 0x0014 PLL4 CFG REG 0x0018 PLL4 Control 0x001C PLL5 CFG REG 0x0020 PLL5 Control PLL5 TUN REG 0x0024 PLL5 Tuning PLL6 CFG REG 0x0028 PLL6 Control 0x002C PLL6 Tuning PLL7_CFG_REG 0x0030 0x0034 PLL1_TUN2_REG 0x0038 PLL1 Tuning2 PLL5_TUN2_REG 0x003C PLL5 Tuning2 0x004C OSC24M_CFG_REG 0x0050 OSC24M control CPU AHB APBO CFG REG 0x0054 CPU AHB And APBO Divide Ratio APB1 CLK DIV REG 0x0058 APB1 Clock D
11. 23 0 R W BC Burst Counter In master mode this field specifies the total burst number when SMC is 1 0 0 burst 1 1 burst N N bursts 18 4 10 SPI Transmit Counter Register Offset 0x24 Register Name SPI TC Default Value 0x0000 0000 Bit Read Write Default Description 31 24 23 0 R W WTC Write Transmit Counter In master mode this field specifies the burst number that should be sent to TXFIFO before automatically sending dummy burst when SMC is 1 For saving bus bandwidth the dummy burst all zero bits or all one bits is sent by SPI Controller automatically 0 0 burst 1 1 burst N N bursts 18 4 11 SPI FIFO Status Register Offset 0x28 Register Name SPI FIFO STA Default Value 0x0000 0000 Bit Read Write Default Description A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 174 Allwinner Technology 31 25 TXFIFO Counter 0 0 byte in TXFIFO 1 1 byte in TXFIFO 63 63 bytes in TXFIFO 22 16 R 0x0 64 64 bytes in TXFIFO These bits indicate the number of words in TXFIFO 15 7 RXFIFO Counter 0 0 byte in RXFIFO 1 1 byte in RXFIFO 63 63 bytes in RXFIFO 6 0 R 0x0 64 64 bytes in RXFIFO These bits indicate the number of words in RXFIFO 18 5 SPI Special Requirement 18 5 1 SPI Pin
12. 33 2 Port Configuration Table PIO Multiplex Function Select Name MO MI M2 M3 M4 M5 M6 PBO Input Output TWIO SCK PB1 Input Output TWIO SDA PB2 Input Output PWM EINT16 PB3 Input Output IR TX EINT 17 PB4 Input Output IR RX EINT18 PB10 Input Output SPI CSI EINT24 PB15 Input Output TWI1_SCK PB16 Input Output TWI1_SDA PB17 Input Output TWI2_SCK PB18 Input Output TWD SDA PCO Input Output NWE SPIO_MOSI PCI Input Output NALE SPIO MISO PC2 Input Output NCLE SPIO_CLK PC3 Input Output NCEI SPIO_CSO PC4 Input Output NCEO DCS Input Output NRE PC6 Input Output NRBO SDC2 CMD PC7 Input Output NRB1 SDC2_CLK DCH Input Output NDQO SDC2 DO PC9 Input Output NDQI SDC2 DI PC10 Input Output NDQ2 SDC2 D2 PC11 Input Output NDQ3 SDC2 D3 PC12 Input Output NDQ4 SDC2 D4 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 366 Allwinner Technology PC13 Input Output NDQ5 SDC2 D5 PC14 Input Output NDQ6 SDC2 D6 PC15 Input Output NDQ7 SDC2 D7 PC19 Input Output NDQS UART2 RX UART3 RTS PD2 Input Output LCD D2 UART2 TX PD3 Input Output LCD D3 UART2 RX
13. A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 55 Allwinner Technology The PLL3 output range is 27MHz 381MHz 30 27 26 24 RW 0x0 23 21 20 16 RW 0x10 PLL3_MODE_SEL 15 R W 0x1 PLL3 mode select 0 fractional mode 1 integer mode PLL3_FUNC_SET 14 R W 0x1 PLL3 fractional setting 0 270MHz 1 297MHz 13 12 8 RW 0x10 7 PLL3 FACTOR M 6 0 R W 0x63 PLL3 Factor M The range is from 9 to 127 6 4 6 PLL4 VE Default 0x21081000 Offset 0x18 Register Name PLL4 CFG_REG Read W Default EE Bit Description rite Hex PLL4_Enable 0 Disable 1 Enable 31 RW oki The PLL4 opur 24MHZ N K M P The PLL4 output is for the VE Note the output 24MHZ N K clock must be in the range of 240MHz 2GHz if the bypass is disabled PLL4 OUT BYPASS EN PLL4 Output Bypass Enable mae hu 0 Disable 1 Enable If the bypass is enabled the PLL4 output is 24MHz 29 25 RW 0x10 d 24 20 RM 0x10 19 R W 0x1 18 e PLL4 OUT EXT DIV P 17 16 RW 0x0 PLL4 Output external divider P The range is 1 2 4 8 15 13 PLL4 FACTOR N 12 8 R W 0x10 PLL4 Factor N Factor 0 N 0 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 56 Allwinner
14. A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 388 Allwinner Technology 33 4 53 PG Pull Register 0 Register Name PG_PULLO Offset OxF4 Default Value 0x0000 0000 Bit Read Write Default Description 31 28 PG n Pull up down Select n 0 13 2i 1 2i 00 Pull up down disable 01 Pull up i 0 13 RW 0x0 10 Pull down 11 Reserved 33 4 54 PG Pull Register 1 Register Name PG_PULL1 Offset OxF8 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 55 PIO Interrupt Configure Register 0 Register Name PIO INT CFGO Offset 0x200 Default Value 0x0000 0000 Bit Read Write Default Description External INTn Mode n 0 7 0x0 Positive Edge 0x1 Negative Edge 0x2 High Level 0x3 Low Level 4i 3 4i 0x4 Double Edge Positive Negative i 0 7 R W 0 Others Reserved 33 4 56 PIO Interrupt Configure Register 1 Register Name PIO_INT_CFG1 Offset 0x204 Default Value 0x0000 0000 Bit Read Write Default Description External INTn Mode n 8 15 0x0 Positive Edge 0x1 Negative Edge 0x2 High Level 0x3 Low Level 4i 3 4i 0x4 Double Edge Positive Negative i 0 7 R W 0 Others Reserved 33 4 57 PIO Interrupt Configure Register 2 Register Name PIO INT CFG2 Offset 0x208 Default Value 0x0000 00
15. 17 16 R W 0x0 15 SCLK1_GATING Gating Special Clock 1 0 Clock is OFF 1 Clock is ON This special clock 1 Special Clock 1 Source 14 12 11 SCLK1 SRC SEL Special Clock 1 Source Select 0 Special Clock 2 1 Special Clock 2 divide by 2 R W 0x0 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 73 Allwinner Technology 10 4 CLK_DIV_RATIO_M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 35 CSI Clock Default 0x00000000 Offset 0x134 Register Name CSI CFG REG f Read W Default Bit Description rite Hex SCLK_GATING Gating Special Clock 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M CSI_RST 30 R W 0x0 CSI Reset 0 reset valid 1 reset invalid 29 27 CLK_SRC_SEL Clock Source Select 000 OSC24M 001 PLL3 1X 010 PLL7 1X 26 24 RW 0x0 ott 100 101 PLL3 2X 110 PLL7 2X 111 23 18 17 16 15 5 CLK DIV RATIO M 4 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 32 6 4 36 VE Clock Default 0x00000000 Offset 0x13C Register Name VE_CFG_REG f Read W Default SE Bit Description rite Hex SCLK_GATING Gating the Special clock for
16. 32 3 3 SID Root Key 2 Register Register Name SID RKEY2 Offset 0x08 Default Value 0xXXXX XXXX Bit Read Write Default Description 31 0 R D Security root key 95 64 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 364 Allwinner Technology 32 3 4 SID Root Key 3 Register Register Name SID RKEY3 Offset 0x0c Default Value 0xXXXX XXXX Bit Read Write Default Description 31 0 R D Security root key 127 96 32 3 5 SID Program Control Register Register Name SID PCTL Offset 0x44 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 Program index 7 4 R W 0 The index value of 32 bits electrical fuses hardware macrocell 3 1 Software program start Write 1 to start software program and automatically clear to 0 0 R W 0 after program A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 365 Allwinner Technology 33 Port Controller 33 1 Overview The chip has 6 ports for multi functional input out pins They are These ports can be easily configured by software for various system configurations Port B PB 10input output port Port C PC 17 input output port Port D PD 22 input output port Port E PE 12 input output port Port F PF 6 input output port Port G PG 9 input output port
17. Offset 0x28 Register Name DEFE BUF ADDR2 REG f Read W Default Ge Bit Description rite Hex BUF ADDR DEFE frame buffer address 31 0 R W 0x0 In tile based type The address is the start address of the line in the first tile used to A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 287 Allwinner Technology generate output frame In non tile based type The address is the start address of the first line 27 5 9 DEFE FIELD CTRL REG Offset 0x2C Register Name DEFE FIELD CTRL REG Read W Default i Bit Description rite Hex 31 13 FIELD LOOP MOD 12 R W 0x0 Field loop mode 0 the last field 1 the full frame 11 VALID FIELD CNT 10 8 R W 0x0 Valid field counter bit the valid value this value 1 FIELD_CNT 7 0 R W 0x0 Field counter each bit specify a field to display 0 top field 1 bottom field 27 5 10 DEFE_TB_OFF0_REG Offset 0x30 Register Name DEFE TB OFFO REG Read W Default a Bit Description rite Hex 31 21 X_OFFSET1 20 16 RW 0x0 T S The x offset of the bottom right point in the end tile 15 13 Y_OFFSETO 12 R 0x0 7 S d i The y offset of the top left point in the first tile 7 5 X_OFFSETO 4 R S d Ge The x offset of the top left point in the first tile 27 5 11 DEFE TB OFF1 REG Offs
18. 27 5 37 DEFE CHO OUTSIZE REG Offset 0x104 Register Name DEFE CHO OUTSIZE REG Read W Default SE Bit Description rite Hex 31 29 OUT_HEIGHT 28 16 RW 0x0 Output layer Y G component height The output layer height The value of these bits add 1 15 13 OUT_WIDTH Output layer Y G component width 12 0 R W 0x0 The output layer width The value of these bits add 1 When line buffer result selection is horizontal filtered result the maximum width is 2048 27 5 38 DEFE CHO HORZFACT REG Offset 0x108 Register Name DEFE CHO HORZFACT REG Read W Default Bit Description rite Hex 31 24 FACTOR_INT 23 16 R W 0x0 The integer part of the horizontal scaling ratio the horizontal scaling ratio input width output width 150 RW oxo FACTOR_FRAC The fractional part of the horizontal scaling ratio A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 298 Allwinner Technology the horizontal scaling ratio input width output width 27 5 39 DEFE CHO VERTFACT REG Offset 0x10C Register Name DEFE_CHO_VERTFACT_REG Read W Default Bit Description rite Hex 31 24 FACTOR INT 23 16 RW 0x0 The integer part of the vertical scaling ratio the vertical scaling ratio input height output height FACTOR_FRAC 15 0 R W 0x0 The f
19. Technology Read W Default a Bit Description rite Hex SCLK_GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 00 OSC24M 25 24 RW 0x0 01 PLL6 10 PLL5 11 23 18 CLK_DIV RATIO N 17 16 R W Ox0 Clock pre divide ratio n The select clock source is pre divided by 2 The divider is 1 2 4 8 15 4 CLK DIV RATIO M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 26 SPIO Clock Default 0x00000000 Offset 0xA0 Register Name SPI 0 SCLK CFG REG Read W Default SS Bit Description rite Hex SCLK_GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 00 OSC24M 25 24 RW 0x0 01 PLL6 10 PLL5 11 23 18 CLK_DIV_RATIO_N 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 The divider is 1 2 4 8 15 4 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 68 Allwinner Technology CLK DIV RATIO M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider i
20. Technology Factor 1 N 1 Factor 2 N 2 Factor 31 N 31 7 6 PLL4 FACTOR K 5 4 R W 0x0 PLL4 Factor K K Factor 1 The range is from 1 to 4 3 2 PLL4 FACTOR M 1 0 R W 0x0 PLL4 Factor M M Factor 1 The range is from 1 to 4 6 4 7 PLL5 DDR Default 0x11049280 Offset 0x20 Register Name PLL5_CFG_REG f Read W Default SE Bit i Description rite Hex PLL5 Enable 0 Disable 1 Enable The PLL5 output for DDR 24MHZ N K M 31 R W 0x0 The PLL5 output for other module 24MHZ N K P The PLL5 output is for the DDR Note the output 24MHZ N K clock must be in the range of 240MHz 2GHz if the bypass is disabled PLL5 OUT BYPASS EN PLL5 Output Bypass Enable EN RW 190 o Disable 1 Enable If the bypass is enabled the PLL6 output is 24MHz 29 RW ER DDR CLK OUT EN DDR clock output en 28 25 RW 0x8 24 20 RW 0x10 19 R W 0x0 18 R W 0x1 PLL5 OUT EXT DIV P 17 16 RW 0x0 PLL5 Output External Divider P The range is 1 2 4 8 15 13 RW 0x4 PLL5_FACTOR_N PLL5 Factor N Factor 0 N 0 12 8 R W 0x12 Factor Kat Factor 2 N 2 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 57 Allwinner Technology Factor 31 N 31 LDO EN S Ge LDO Enable 6 PLL5 FACTOR K 5 4 R W 0x0 PLL5 Factor K K Factor 1 The range is from 1 to 4 PLL5 FACTOR Mi
21. 14 4 3 Normal DMA Configuration Register Default 0x00000000 N 0 7 rrrrrrrennnnrr 14 4 4 Normal DMA Source Address Register Default Ox00000000 14 4 5 Normal DMA Destination Address Register Default 0Ox00000000 14 4 6 Normal DMA Byte Counter Register Default 0x00000000 srrrnrrrnvnnnvrrrnrnnnvnnnn 14 4 7 Dedicated DMA Configuration Register Default 0x00000000 ranrrrnvnrnvrrnnrnenn 14 4 8 Dedicated DMA Source Start Address Register N 0 7 14 4 9 Dedicated DMA Destination Start Address Register N 0 7 14 4 10 Dedicated DMA Byte Counter Register N O 14 4 11 Dedicated DMA Parameter Register 15 NAND Flash se sisicssiccsvcscictssensioususnevetssanctecsvonsdebassusdsesvensvereducaetsvensusdsuevsvetsnessuedsdcasvsusvonsiensvoucdsievensuesseeves 15 1 ONE ee 15 2 NEG Block Diagrai 2 ain 153 NEC Timing Daga SSSR ee R En NS Ne NE en EE 15 4 NFC Operation UNE en 16 SD MMC Controller E 16 1 NE ee 16 2 SD MMC Timing Re E 17 Two Wire Interface synes SELEN 17 1 NE 17 2 TWITIMNG Diagram E 17 3 TWI Controller Register list un Ne 17 4 TWI Controller Register Description sco tected cn deeded ied de eee ceed A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 9 Allwinner Technology 17 4 1 TWI Slave Address E 156 17 4 2 T
22. 30 28 RW 0 27 26 24 R W 0 23 22 20 R W 0 19 PG4 Select 000 Input 001 Output 010 SDC1 CLK 011 100 UART1 RX 101 18 16 R W 0 110 EINT4 111 15 PG3 Select 000 Input 001 Output 010 SDC1 CMD 011 100 UART1_TX 101 14 12 R W 0 110 EINT3 111 11 PG2 Select 000 Input 001 Reserved 10 8 RW 0 010 GPS MAG 011 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 386 Allwinner Technology 100 101 110 EINT2 111 7 PG1 Select 000 Input 001 Reserved 010 GPS_SIGN 011 100 101 6 4 R W 0 110 EINT1 111 3 PGO Select 000 Input 001 Reserved 010 GPS_CLK 011 100 101 2 0 R W 0 110 EINTO 111 33 4 47 PG Configure Register 1 Register Name PG CFGi1 Offset OxDC Default Value 0x0000 0000 Bit Read Write Default Description 31 24 23 22 20 R W 0 19 PG12 Select 000 Input 001 Output 010 SPI1_MISO 011 UART3_RTS 100 101 18 16 R W 0 110 EINT12 111 15 PG11 Select 000 Input 001 Output 010 SPI1 MOSI 011 UART3 CTS 100 101 14 12 R W 0 110 EINT11 111 11 PG10 Select 000 Input 001 Output 010 SPI1_CLK 011 UART3_RX 100 101 10 8 R W 0 110 EINT10 111 7 PG9 Select 6 4 R W 0 000 Input 001 Output A13 User Manual V1 3 Cop
23. Offset 0x84 Register Name DEFE CSC COEF11 REG f Read W Default EE Bit Description rite Hex 31 13 COEF 12 0 R W 0x0 the U R coefficient the value equals to coefficient 2 27 5 28 DEFE CSC COEF12 REG Offset 0x88 Register Name DEFE CSC COEF12 REG i Read W Default Bit Description rite Hex 31 13 COEF 12 0 R W 0x0 the U R coefficient the value equals to coefficient 2 27 5 29 DEFE CSC COEF13 REG Offset Ox8C Register Name DEFE CSC COEF13 REG Read W Default Bit Description rite Hex 31 14 CONT 13 00 R W 0x0 the U R constant the value equals to coefficient 2 27 5 30 DEFE_CSC_COEF20 REG Offset 0x90 Register Name DEFE_CSC_COEF20_REG i Read W Default D Bit Description rite Hex 31 13 12 0 R W 0x0 Se SC the V B coefficient A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 296 Allwinner Technology the value equals to coefficient 2 27 5 31 DEFE CSC COEF21 REG Offset 0x94 Register Name DEFE CSC COEF21 REG Read W Default Bit Description rite Hex 31 13 COEF 12 0 R W 0x0 the V B coefficient the value equals to coefficient 2 27 5 32 DEFE CSC COEF22 REG Offset 0x98 Register Name DEFE CSC COEF22 REG f Read W Default Wi
24. 3 0 R N PORTS This field specifies the number of physical downstream ports implemented on this host controller The value of this field determines how many port registers are addressable in the Operational Register Space Valid values are in the range of 0x1 to OxOf This field is always 1 22 5 4 EHCI Host Control Capability Parameter Register Register Name HCCPARAMS Offset 0x08 Default Value Implementation Dependent Bit Read Write Default Description Reserved 31 16 0 These bits are reserved and should be set to zero EHCI Extended Capabilities Pointer EECP This optional field indicates the existence of a capabilities list A value of 00b indicates no extended capabilities are implemented A non zero value in this register indicates the offset in PCI 15 18 R 0 configuration space of the first EHCI extended capabiliby The A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 201 Allwinner Technology pointer value must be 40h or greater if implemented to maintain to consistency of the PCI header defined for this calss of device The value of this field is always 00b 7 4 Isochronous Scheduling Threshold This field indicates relative to the current position of the executing host controller where software can reliably update the isochronous schedule When bit 7 is zero the value of the least significant 3 bits in
25. 13 4 16 Interrupt Enable Register 2 Default 0x00000000 Offset 0x48 Register Name INTC_EN_REG2 Read W Default ON Bit i Description rite Hex INT_SRC_EN2 Int t Source 95 64 Enable Bits 31 0 R W 0x0 hekke 9 l Dee 0 Corresponding interrupt is disabled 1 Corresponding interrupt is enabled 13 4 17 Interrupt Mask Register 0 Default 0x00000000 Offset 0x50 Register Name INTC MASK REGO Read W Default eech Bit Description rite Hex INT_MASKO Interrupt Source 31 0 Mask Bits No effect 310 RW Jox 2 No efect 1 interrupt is masked If interrupt is enabled and the interrupt occurred the interrupt pending bit will be set whether the corresponding interrupt mask bit is set 13 4 18 Interrupt Mask Register 1 Default 0x00000000 Offset 0x54 Register Name INTC_MASK_REG1 Read W Default Bit Description rite Hex INT MASK1 Interrupt Source 63 32 Mask Bits No effect 310 Rw Lo Feed 1 interrupt is masked If interrupt is enabled and the interrupt occurred the interrupt pending bit will be set whether the corresponding interrupt mask bit is set 13 4 19 Interrupt Mask Register 2 Default 0x00000000 Offset 0x58 Register Name INTC_MASK_REG2 Read W Default De Bit Description rite Hex 31 0 RAV 0x0 INT MASK2 D Interrupt Source 95 64 Mask Bits A13 User Manual V1 3
26. Technology 7 3 2 SRAM Configuration Register 1 Default 0x00001000 Offset 0x04 Register Name SRAM CFG REG1 Read W Default D Bit Description rite Hex 31 RW 0x0 30 18 17 RW 0x0 16 R W 0x0 15 14 RW 0x0 13 SRAM_C3_MAP 19 RW d SRAM C3 map config 0 map to CPU BIST 1 map to ISP 11 6 d i SRAM_A3_A4_ MAP SRAM Area A3 A4 Configuration by AHB 5 4 R W 0x0 00 map to CPU DMA 01 10 11 3 1 SRAM_D MAP 0 RW 0x0 SRAM D Area Config 0 map to CPU DMA 1 map to USB DRD A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved Allwinner Technology 8 CPU Control 8 1 CPU Register List Module Name Base Address CPU CTL 0x01C23400 Register Name Offset Description CPU CTRL REG 0x0020 CPU Control Register 8 2 CPU Control Register Description 8 2 1 CPU Control Register Default 0x00000002 Offset 0x20 Register Name CPU CTRL REG f Read W Default W Bit Description rite Hex 31 9 H 8 R W 0x0 ATUN CPU ID Option 7 2 R W 0x1 CP15 WRITE DISABLE Disable write access to certain CP 15 registers 0 R W 0x0 0 enable 1 disable A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 80 Allwinner Technology 9 SDRAM Controller 9 1 Overview The SDRAM Controller DRAMG provides a simple flexible burst optimiz
27. 0x0 PortSuspendStatusChange This bit is set when the full resume sequence has been completed This sequence includes the 20 s resume pulse LS EOP and 3 ms resychronization delay The HCD writes a 1 to clear this bit Writing a 0 has no effect This bit is also cleared when ResetStatusChange is set A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 229 Allwinner Technology 0 resume is not completed 1 resume completed PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared Changes from HCD writes do not set this bit The HCD writes a 1 to clear this bit Writing a O has no effect 0 no change in PortEnableStatus 17 RW RW 0x0 1 change in PortEnableStatus ConnectStatusChange This bit is set whenever a connect or disconnect event occurs The HCD writes a 1 to clear this bit Writing a 0 has no effect If CurrentConnectStatus is cleared when a SetPortReset SetPortEnable or SetPortSuspend write occurs this bit is set to force the driver to re evaluate the connection status since these writes should not occur if the port is disconnected 0 no change in PortEnableStatus 1 change in PortEnableStatus Note If the DeviceRemovable NDP bit is set this bit is set only after a Root Hub reset to inform the system that the device is 16 RW RW 0x0
28. 11 0 RW HBP horizontal back porch Thbp HBP 1 Thdclk 29 3 25 TCON1 BASIC4 REG Offset OxOA4 Register Name TCON1 basic timing register4 Read W Default i Bit f Description rite Hex 31 28 VT 28 16 R W 0 horizontal total time in HD line Tvt VT 2 Th 15 12 VBP 11 0 R W 0 horizontal back porch in HD line Tvbp VBP 1 Th 29 3 26 TCON1 BASIC5 REG Offset 0Ox0A8 Register Name TCON1 basic timing register5 Read W Default Bit i Description rite Hex 31 26 HSPW 2546 RW 0 horizontal Sync Pulse Width in dclk Thspw HSPW 1 Tdclk Note HT gt HSPW 1 15 10 VSPW 9 0 RW 0 vertical Sync Pulse Width in lines Tvspw VSPW 1 Th Note VT 2 gt VSPW 1 29 3 27 TCON1 IO POL REG Offset OxOFO Register Name TCON1 IO polarity register i Read W Default KR Bit Description rite Hex 31 28 103_Inv 27 R W 0 0 not invert 1 invert 102 Inv 26 R W 0 0 not invert 1 invert A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 346 Allwinner Technology IO Inv 25 R W 0 0 not invert 1 invert 100_Inv 24 R W 0 0 not invert 1 invert Data Inv TCON1 output port D 23 0 polarity control with independent i I 53 0 RAW 0 bit contro Os norma
29. Allwinner Technology Owner bit USB Error Interrupt USBERRINT The Host Controller sets this bit to 1 when completion of USB transaction results in an error condition e g error counter underflow If the TD on which the error interrupt occurred also had its IOC bit set both 1 R WC 0 This bit and USBINT bit are set USB Interrupt USBINT The Host Controller sets this bit to a one on the completion of a USB transaction which results in the retirement of a Transfer Descriptor that had its IOC bit set The Host Controller also sets this bit to 1 when a short packet is detected actual number of bytes received was less than the expected 0 R WC 0 number of bytes 22 5 8 EHCI USB Interrupt Enable Register Register Name USBINTR Offset 0x18 Default Value 0x00000000 Bit Read Write Default Description Reserved 31 6 0 These bits are reserved and should be zero Interrupt on Async Advance Enable When this bit is 1 and the Interrupt on Async Advance bit in the USBSTS register is 1 the host controller will issue an interrupt at the next interrupt threshold The interrupt is acknowledged by 5 R W 0 software clearing the Interrupt on Async Advance bit Host System Error Enable When this bit is 1 and the Host System Error Status bit in the USBSTS register is 1 the host controller will issue an interrupt The interrupt is acknowledged by software clearing the Host 4 R W 0 System Erro
30. Note the active cycles should be no larger than the period cycles A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 84 Allwinner Technology 11 Asynchronic Timer 11 1 Overview The chip implements 6 async timers Timer 0 1 2 can take their inputs from the PLL6 6 or OSC24M They provide the operating system s scheduler interrupt It is designed to offer maximum accuracy and efficient management even for systems with long or short response time They provide 32 bit programmable overflow counter and work in auto reload mode or no reload mode The watch dog is used to resume controller operation by generating a general reset or an interrupt request when it is disturbed by malfunctions such as noise sand system errors It features a down counter that allows a watchdog period of up to 16 seconds Timer 3 is used for OS to generate a periodic interrupt 11 2 ASYNC Timer Register List Module Name Base Address ASYNC Timer 0x01C20C00 Register Name Offset Description ASYNG TMR IRQ EN REG 0x0000 Timer IRQ Enable ASYNC TMR IRQ STAS REG 0x0004 Timer Status ASYNC TMRO CTRL REG 0x0010 Timer 0 Control ASYNG TMRO INTV VALUE REG 0x0014 Timer 0 Interval Value ASYNG TMRO CURNT VALUE REG 0x0018 Timer 0 Current Value ASYNG TMR1 CTRL REG 0x0020 Timer 1 Control ASYNG TMR1 INTV VALUE REG 0x0024 Timer 1 Interval Value ASYNG
31. Bit Read Write Default Description 31 8 7 6 RT RCVR Trigger This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated In auto flow control mode it is used to determine when the ris n signal is de asserted It also determines when the dma rx req n signal is asserted in certain modes of operation 00 1 character in the FIFO 01 FIFO 14 full 10 FIFO 2 full 11 FIFO 2 less than full 5 4 TFT TX Empty Trigger Writes have no effect when THRE MODE USER Disabled This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active It also determines when the dma tx req n signal is asserted when in certain modes of operation 00 FIFO empty 01 2 characters in the FIFO 10 FIFO full 11 FIFO L full DMAM DMA Mode 0 Mode 0 1 Mode 1 XFIFOR XMIT FIFO Reset This resets the control portion of the transmit FIFO and treats the FIFO as empty This also de asserts the DMA TX request It is self clearing It is not necessary to clear this bit RFIFOR RCVR FIFO Reset This resets the control portion of the receive FIFO and treats the FIFO as empty This also de asserts the DMA RX request It is self clearing It is not necessary to clear this bit FIFOE Enable FIFOs This enables disables the transmit XMIT and receive RCVR F
32. Copyright O 2013 Allwinner Technology All Rights Reserved 165 Allwinner Technology SPI BC 0x20 SPI Burst Counter Register SPI TC 0x24 Spi Transmit Counter Register SPI FIFO STA 0x28 SPI FIFO Status Register 18 4 SPI Register Description 18 4 1 SPI RX Data Register Register Name SPI RXDATA Offset 0x00 Default Value 0x0000 0000 Bit Read Write Default Description Receive Data In 8 bits SPI bus width this register can be accessed in byte half word or word unit by AHB In byte accessing method if there are words in RXFIFO the top word is returned and the RXFIFO depth is decreased by 1 In half word accessing method the two SPI bursts are returned and the RXFIFO depth decreases by 2 In word accessing method the four SPI bursts are returned and the 31 0 R 0 RXFIFO depth decreases by 4 18 4 2 SPI TX Data Register Register Name SPI TXDATA Offset 0x04 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 W 0 Transmit Data 18 4 3 SPI Control Register Register Name SPI CTL Offset 0x08 Default Value 0x0002 001C Bit Read Write Default Description 31 20 Master Sample Data Control Set this bit to 1 to make the internal read sample point with a delay of half cycle of SPI_CLK It is used in high speed read 19 R W 0 operation to reduce the error caused by the time delay of SPI CLK propagating b
33. NFC_CE A NFC_WE d w t14 NFC_RE ff NFC_ALE e t16 NFC_RB S NFC_IOx cmd d 0 d 1 fan Figure15 8 Waiting R B Ready Diagram NFC CLE NFC CEH p t17 gt NFC_RE NFC_ALE f f NFC_WE f f f en UR Wer We NFC_RB NFC_IOx cmd am X a0 fan Figure15 9 WE High to RE Low Timing Diagram NFC_CLE NFC_CE NFC_WE AE NFC_RE NFC_ALE NFC_RB NFC_IOx d 0 d Xdad n 1 05h coli col2 EOh Figure15 10 RE High to WE Low Timing Diagram A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 149 Allwinner Technology NFC_CLE NFC_CE T19 gt NFC_WE NFC_RE NFC_ALE NFC_RB NFC_IOx addr2 X addr3 d 0 d 1 d 2 X d n 1 Figure15 11 Address to Data Loading Timing Diagram Timing Cycle List ID Parameter Timing Notes T1 NFC_CLE setup time T T2 NFC_CLE hold time T T3 NFC_CE setup time T T4 NFC_CE hold time T T5 NFC_WE pulse T width T6 NFC_WE hold time T T7 NFC_ALE setup time T T8 Data setup time T T9 Data hold time T T10 Ready to NFC_RE 3T low T11 NFC_ALE hold time T T12 NFC_RE pulse width T T13 NFC REt hold time T T14 Read cycle time 2T T15 Write cycle
34. PWM Channel 0 pulse output start 0 no effect 1 output 1 pulse The pulse width should be according to the period 0 register 15 0 and the pulse state should be according to the active state After the pulse is finished the bit will be cleared automatically RW Ox0 PWM_CHANNELO MODE 0 cycle mode 1 pulse mode RW Ox0 SCLK CHO GATING Gating the Special Clock for PWMO 0 mask 1 pass R W 0x0 PWM_CHO_ACT_STA PWM Channel 0 Active State 0 Low Level 1 High Level R W 0x0 PWM_CHO EN PWM Channel 0 Enable 0 Disable 1 Enable 3 0 RW Ox0 PWM_CHO_PRESCAL PWM Channel 0 Prescalar These bits should be setting before the PWM Channel 0 clock gate on 0000 120 0001 180 0010 240 0011 360 0100 480 0101 0110 0111 1000 12k 1001 24k 1010 36k 1011 48k 1100 72k 1101 1110 1111 1 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 83 10 3 2 Allwinner Technology PWM Channel 0 Period Register Offset 0x204 Register Name PWM CHO PERIOD REG Bit Read W rite Default Hex Description 31 16 R W PWM ENT CYC Number of the entire cycles in the PWM clock 0 1 cycle 1 2 cycles N N 1 cycles 15 0 RW PWM ACT CYC Number of the active cycles in the PWM clock 0 0 cycle 1 1 cycles N N cycles
35. RW Ox0 NDMA7 HF IRQ PEND Normal DMA 7 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 13 RW Ox0 NDMA6 END IRQ PEND A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 135 Allwinner Technology Normal DMA 6 End Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear 12 RW Ox0 NDMA6 HF IRQ PEND Normal DMA 6 Half Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear 11 R W 0x0 NDMA5_END_IRQ_PEND Normal DMA 5 End Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear 10 R W 0x0 NDMA5_HF_IRQ_PEND Normal DMA 5 Half Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear R W 0x0 NDMA4_END_IRQ_PEND Normal DMA 4 End Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear R W 0x0 NDMA4_HF_IRQ_PEND Normal DMA 4 Half Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear R W 0x0 NDMA3_END_IRQ_PEND Normal DMA 3 End Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear R W 0x0 NDMA3 HF IRQ PEND Normal DMA 3 Half Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the b
36. SE ER PLL5 Factor M1 PLL5 FACTOR M 1 0 R W 0x0 PLL5 Factor M M Factor 1 The range is from 1 to 4 6 4 8 PLL5 Tuning Default 0x14880000 Offset 0x24 Register Name PLL5_TUN_REG l Read W Default a Bit Description rite Hex 31 0 6 4 9 PLL6 Default 0x21009931 Offset 0x28 Register Name PLL6 CFG REG Read W Default a Bit Description rite Hex PLL6_Enable 0 Disable 1 Enable 31 RAW 0x0 Output 24MHZ N K M 2 Note the output 24MHZ N K clock must be in the range of 240MHz 3GHz if the bypass is disabled Its default is 1200MHz PLL6 BYPASS EN PLL6 Output Bypass Enable RW 190 o Disable 1 Enable If the bypass is enabled the PLL6 output is 24MHz 29 13 PLL6_FACTOR_N PLL6 Factor N Factor 0 N 0 12 8 RW 0x19 Factor 1 N 1 Factor 2 N 2 Factor 31 N 31 7 6 PLL6 damping factor control 1 0 5 4 J PLL6 FACTOR K PLL6 Factor K K Factor 1 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 58 Allwinner Technology The range is from 1 to 4 3 2 PLL6_FACTOR_M 1 0 R W Ox1 PLL6 Factor M M Factor 1 The range is from 1 to 4 6 4 10 PLL7 Default 0x0010D063 Offset 0x30 Register Name PLL7_CFG_REG Read W Default ae Bit Description rite Hex PLL7_Enable 0 Disable 1 Enable 31 R W 0x0 In the
37. ennen 68 6 4 27 SPI1 Clock Default 0x00000000 enne 69 6 4 28 SPI2 Clock Default Ox00000000 nne 69 6 4 29 IR Clock Default 0Ox00000000 nne 70 6 4 30 USB Clock Default 0x00000000 Us 70 6 4 31 DRAM CLK Default 0x00000000 nne 71 6 4 32 DE BE Clock Default 0x00000000 rerrnrrerrnrnrrrnvnnrrnverrnrnrrrnnnnrrrverrnnnerrnnerrrnnerennnn 72 6 4 33 DE FE Clock Default OxOOO0O0OO0O0 72 6 4 34 LCD CH1 Clock Default 0x00000000 rrnrrrrnrnnrnnvenrnrnrrrnrnnrrnrerrnnrrrnrnnrrnrerrnnnernnn 73 6 4 35 CSI Clock Default 0x00000000 2 74 6 4 36 VE Clock Default OsOOOO0O0O0O0 cecececeeeeeeeeeeeeeeeeeeeeeeeeeeeeseaeeeeeaeesseeesseeeesaeees 74 6 4 37 Audio Codec Clock Default 0Ox00000000 75 6 4 38 AVS Clock Default 0x00000000 ss 75 6 4 39 Mali 400 Clock Register Default 0x00000000 ccceceseeeeeeeeeneeeeeeeeteneeesseeeens 75 6 4 40 MBUS Clock Control Default 0x00000000 eeececeecceeeeeeeneeeeeeeeeeeeeesneeessaeeeees 76 6 4 41 IEP Clock Control Default 0x00000000 rrnrrrrrnrnrrrnverrnrnrrrnrnrrrnrerrnnerrnrerrrnnerennnn 76 T System KREE geseet Eege 78 EE e 78 7 2 System Control Register List ss 78 7 3 System Control Register Description 78 7 3 1 SRAM Configuration Register 0 Default 0x lt 7FFFFFFF mrrrnrenrnnrrnrnnrrrrnnrrrverrnnnenn 78 7 3
38. the value equals to coefficient 2 9 Register Name DEBE OCBCOEF REG 28 5 36 DEBE Output Color B Constant Register Offset Ox9FC Register Name DEBE OCBCONS REG Read Wr Default ae Bit Description ite Hex OC_BCONS the B constant the value equals to coefficient 2 28 5 37 DE HWC Pattern Memory Block Function 1bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P09 P08 PO7 P06 POS P04 P03 P02 P01 POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 2bpp A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 328 Allwinner Technology Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P15 P14 P13 P12 P11 P10 P09 P08 P07 P06 P05 P04 P03 P02 PO1 POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 O1 00 4bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PO7 PO6 PO5 PO4 P03 P02 PO1 P00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 O1 00 8bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P3 P2 P1 PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Offset DE HW cursor pattern memory block 0x4800 0x4BFF Read Wr Default Bit ES r Sieg Description ite Hex Hardware cursor pixel patt
39. 24 R W 0x0 DDMA4_HF_IRQ_EN Dedicated DMA 4 Half Transfer Interrupt Enable 0 Disable 1 Enable 23 R W 0x0 DDMA3 END IRQ EN Dedicated DMA 3 End Transfer Interrupt Enable 0 Disable 1 Enable 22 R W 0x0 DDMA3_HF_IRQ_EN Dedicated DMA 3 Half Transfer Interrupt Enable 0 Disable 1 Enable 21 R W 0x0 DDMA2 END IRQ EN Dedicated DMA 2 End Transfer Interrupt Enable 0 Disable 1 Enable 20 R W 0x0 DDMA2_HF_IRQ_EN Dedicated DMA 2 Half Transfer Interrupt Enable 0 Disable 1 Enable 19 R W 0x0 DDMA1_END_IRQ_EN Dedicated DMA 1 End Transfer Interrupt Enable 0 Disable 1 Enable 18 R W 0x0 DDMA1 HF IRQ EN Dedicated DMA 1 Half Transfer Interrupt Enable 0 Disable 1 Enable A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved Allwinner Technology DDMAO_END IRQ EN 17 R W 0x0 Dedicated DMA 0 End Transfer Interrupt Enable 0 Disable 1 Enable DDMAO HF IRQ EN 16 R W 0x0 Dedicated DMA 0 Half Transfer Interrupt Enable 0 Disable 1 Enable NDMA7_END_IRQ_EN 15 R W 0x0 Normal DMA 7 End Transfer Interrupt Enable 0 Disable 1 Enable NDMA7_HF_IRQ_EN 14 R W 0x0 Normal DMA 7 Half Transfer Interrupt Enable 0 Disable 1 Enable NDMA6_END_IRQ_EN 13 R W 0x0 Normal DMA 6 End Transfer Interrupt Enable 0 Disable 1 Enable NDMA6_HF_IRQ_EN 12 R W 0x0
40. 5 3 18 PMU VF Table Register 2 Offset 0x88 Register Name PMU VF TABLE REG2 Bit pr Pee Description rite Hex 31 11 CPU MAX FREQ 080 10 0 R W X CPU max frequency if cpuvdd 0 8v unit MHz This register can only be written if the DVFS function is disabled 5 3 19 PMU VF Table Register 3 Offset Ox8C Register Name PMU VF TABLE REG3 Read W Default EN Bit Description rite Hex 31 11 CPU MAX FREQ 085 10 0 R W X CPU max frequency if cpuvdd 0 85v unit MHz This register can only be written if the DVFS function is disabled 5 3 20 PMU VF Table Register 4 Offset 0x90 Register Name PMU_VF_TABLE_REG4 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 39 Allwinner Technology Read W Default Bit Description rite Hex 31 11 CPU MAX FREQ 090 10 0 R W X CPU max frequency if vddcpu 0 9v unit MHz This register can only be written if the DVFS function is disabled 5 3 21 PMU VF Table Register 5 Offset 0x94 Register Name PMU VF TABLE REG5 Read W Default SE Bit Description rite Hex 31 11 CPU MAX FREQ 095 10 0 R W D CPU max frequency if cpuvdd 0 95v unit MHz This register can only be written if the DVFS function is disabled 5 3 22 PMU VF Table Register 6 Offset 0x98 Register Name PMU_VF_TABLE_REG6 Read W De
41. Copyright 2013 Allwinner Technology All Rights Reserved 112 Allwinner Technology 0 No effect 1 interrupt is masked If interrupt is enabled and the interrupt occurred the interrupt pending bit will be set whether the corresponding interrupt mask bit is set 13 4 20 Interrupt Response Register 0 Default 0x00000000 Offset 0x60 Register Name INTC RESP REGO Read W Default SCH Bit Description rite Hex INT_RESPO Interrupt Source 31 0 response bit 31 0 R W 0x0 l Ek If the corresponding bit is set the interrupt with the lower or the same priority level is masked 13 4 21 Interrupt Response Register 1 Default 0x00000000 Offset 0x64 Register Name INTC RESP REG1 Read W Default o Bit f Description rite Hex INT_RESP1 Interrupt Source 63 32 response bit 31 0 RW 0x0 G If the corresponding bit is set the interrupt with the lower or the same priority level is masked 13 4 22 Interrupt Response Register 2 Default 0x00000000 Offset 0x68 Register Name INTC RESP REG2 Read W Default a Bit Description rite Hex INT RESP2 31 0 RAW CR Interrupt Source 25 64 response pit If the corresponding bit is set the interrupt with the lower or the same priority level is masked 13 4 23 Interrupt Fast Forcing Register 0 Default 0x00000000 Offset 0x70 Register Name INTC_FORCE
42. Copyright 2013 Allwinner Technology All Rights Reserved 217 Allwinner Reserved OwershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC When set HC will set the OwnershipChange field in HcinterruptStatus After the changeover this bit is cleared and remains so until the next request from OS HCD BulkIListFilled This bit is used to indicate whether there are any TDs on the Bulk list It is set by HCD whenever it adds a TD to an ED in the Bulk list When HC begins to process the head of the Bulk list it checks BLF As long as BulkListFilled is 0 HC will not start processing the Bulk list If BulkListFilled is 1 HC will start processing the Bulk list and will set BF to 0 If HC finds a TD on the list then HC will set BulkListFilled to 1 causing the Bulk list processing to continue If no TD is found on the Bulk list and if HCD does not set BulkListFilled then BulkListFilled will still be 0 when HC completes processing the Bulk list and Bulk list processing will stop ControlListFilled This bit is used to indicate whether there are any TDs on the Control list It is set by HCD whenever it adds a TD to an ED in the Control list When HC begins to process the head of the Control list it checks CLF As long as ControlListFilled is 0 HC will not start processing the Control list If CF is 1 HC will start processing the Control list and will set ControlListFilled to 0 If HC
43. Offset 0x58 Register Name PC_DAT A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 374 Allwinner Technology Default Value 0x0000 0000 Bit Read Write Default Description 31 20 If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If the port is configured as functional pin the undefined 19 0 R W 0 value will be read 33 4 15 PC Multi Driving Register 0 Register Name PC DRVO Offset 0x5C Default Value 0x5555 5555 Bit Read Write Default Description PC n Multi Driving Select n 0 15 2i 1 2i 00 Level 0 01 Level 1 i 0 15 RW Ox1 10 Level 2 11 Level 3 33 4 16 PC Multi Driving Register 1 Register Name PC DRV1 Offset 0x60 Default Value 0x0000 0055 Bit Read Write Default Description 31 8 PC n Multi Driving Select n 16 19 2i 1 2i 00 Level 0 01 Level 1 i 0 3 R W 0x1 10 Level 2 11 Level 3 33 4 17 PC Pull Register 0 Register Name PC_PULLO Offset 0x64 Default Value 0x0000 5140 Bit Read Write Default Description PC n Pull up down Select n 0 15 2i 1 2i 00 Pull up down disable 01 Pull up i 0 15 RW 0x0000 5140 10 Pull down 11 Reserved 33 4 18
44. SIN SOUT S Stop gt 3 16 Bit Time gt 3 16 Bit Time SIR OUT gt 3 16 Bit Time SIR IN Figure 19 2 Serial IrDA Data Format 19 3 UART Register List There are 4 UART controllers that can be configured as Serial IrDA Module Name Base Address UARTO 0x01C28000 UART1 0x01C28400 UART2 0x01C28800 UART3 0x01C28C00 Register Name Offset Description UART_RBR 0x00 UART Receive Buffer Register UART_THR 0x00 UART Transmit Holding Register UART_DLL 0x00 UART Divisor Latch Low Register UART_DLH 0x04 UART Divisor Latch High Register UART_IER 0x04 UART Interrupt Enable Register UART_IIR 0x08 UART Interrupt Identity Register UART_FCR 0x08 UART FIFO Control Register UART_LCR 0x0C UART Line Control Register UART_MCR 0x10 UART Modem Control Register UART_LSR 0x14 UART Line Status Register UART_MSR 0x18 UART Modem Status Register UART_SCH Ox1C UART Scratch Register UART USR 0x7C UART Status Register UART_TFL 0x80 UART Transmit FIFO Level UART_RFL 0x84 UART_RFL UART_HALT OxA4 UART Halt TX Register 19 4 UART Register Description 19 4 1 UART Receiver Buffer Register Register Name UART_RBR Offset 0x00 Default Value 0x0000 0000 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 177 Allwinner Technology Bit Read Write Default Descripti
45. frame buffer data Output color ao RO GO Bo 8bpp a R1 G1 B1 as RS G5 B5 038 R38 G38 B38 5 38 133 28 On Rn Gn Bn 0433 R133 G133 B133 028 R28 G28 B28 0254 R254 G254 B254 0255 R255 G255 B255 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 330 Allwinner Technology 28 5 40 Internal Frame Buffer Mode In internal frame buffer mode the RAM array is used as an on chip frame buffer each pixel in the RAM array is used to select one of the palette 32 bit colors 1bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P09 P08 PO7 P06 P05 P04 PO3 P02 PO1 POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 2bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P15 P14 P13 P12 P11 P10 P09 P08 P07 P06 P05 P04 P03 P02 P01 POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 4bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P07 P06 P05 P04 P03 P02 PO1 POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 8bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P3
46. 0 Reserved 19 16 0 These bits are reserved and should be set to zero Number of Companion Controller N CC 15 12 R 0 This field indicates the number of companion controllers A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 200 Allwinner Technology associated with this USB2 0 host controller A zero in this field indicates there are no companion host controllers And a value larger than zero in this field indicates there are companion USB1 1 host controller s This field will always be 0 Number of Port per Companion Controller N PCC This field indicates the number of ports supported per companion host controller host controller It is used to indicate the port routing configuration to system software This field will always fix with 0 Port Routing Rules This field indicates the method used by this implementation for how all ports are mapped to companion controllers The value of this field has the following interpretation Value Meaning The first N PCC ports are routed to the lowest numbered function companion host controller the next N PCC port are routed to the next lowest function companion controller and so on The port routing is explicitly enumerated by the first 1 N PORTS elements of the HCSP PORTTOUTE array This field will always be 0 6 4 Reserved These bits are reserved and should be set to zero
47. 0 mask 1 pass BDRD AHB GATING 0 RW 0x0 Ge G Gating AHB Clock for USB DRD 0 mask 1 pass 6 4 18 AHB Module Clock Gating Register 1 Default 0x00000000 Offset 0x64 Register Name AHB_GATING_REG1 Bit Read Default Description A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 63 Allwinner Technology Write Hex 31 21 20 R W 0x0 Gating AHB Clock for Mali 400 0 mask 1 pass IEP_AHB_GATING 19 R W 0x0 Gating AHB Clock for IEP 0 mask 1 pass 18 15 FE AHB GATING 14 RW 0x0 Gating AHB Clock for DE FE 0 mask 1 pass 13 BE_AHB_GATING 12 RW 0x0 x Gating AHB Clock for DE BE 0 mask 1 pass 11 R W 0x0 10 9 AHB GATING 8 RW 0x0 CSL G 2 Gating AHB Clock for CSI 0 mask 1 pass 7 5 LCD AHB GATING 4 RW 0x0 x Gating AHB Clock for LCD 0 mask 1 pass 3 2 R W 0x0 1 VE_AHB_GATING 0 R W 0x0 F a Gating AHB Clock for VE 0 mask 1 pass 6 4 19 APBO Module Clock Gating Default 0x00000000 Offset 0x68 Register Name APBO_GATING_REG Bit meee ieee Description Write Hex 31 11 10 R W 0x0 9 7 6 RW oxo IR_APB_GATING Gating APB Clock for IR 0 mask 1 pass PIO_APB_GATING SC Ge Gating APB Clock for PIO 0 mas
48. 0X00C0 Register Name IMGEHC_CSCYGCOFF_REG R U component 0X00C4 B V component 0X00C8 Read Wr Default TR Bit Description ite Hex A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 355 Allwinner Technology Ox4a7 CSC_YG_COFF Oxie6f the Y G coefficient Oxicbf the value equals to coefficient 2 9 30 2 17 CSC Y G Constant Register Offset OXOOCC Register Name IMGEHC_CSCYGCON_REG Read Wr Default gt Bit Description ite Hex CSC YG CON 13 00 RW 0x877 the Y G constant the value equals to coefficient 2 30 2 18 CSC U R Coefficient Register Offset G Y component 0X00D0 R U component 0X00D4 B V component 0X00D8 Read Wr Default SE Bit Description ite Hex CSC_UR_COFF 12 00 RW the U R coefficient the value equals to coefficient 2 30 2 19 CSC U R Constant Register Offset OXOODC Register Name IMGEHC_CSCURCON_REG Read Wr Default SC Bit Description ite Hex CSC_UR_CON 13 00 RW 0x3211 the U R constant the value equals to coefficient 2 30 2 20 CSC V B Coefficient Register Offset G Y component 0X00E0 R U component 0X00E4 Register Name IMGEHC_CSCURCOFF_REG Register Name IMGEHC_CSCVBCOFF_REG B V component 0X00E8 Read Wr Default en Bit Description ite Hex A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 356 Allwinner Technology CSC_VB_COFF the
49. 0x0000 0000 Bit Read Write Default Description 31 0 R 0 32 bits TX FIFO for Output 31 5 Security System Clock Requirement Clock Name Description Requirement A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 362 Allwinner Technology ahb cik AHB bus clock gt 24MHz ss cik SS serial clock lt 150MHz A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 363 Allwinner Technology 32 Security ID 32 1 Overview There is one on chip 128 bit EFUS for security application It can also be used as root key or for other purposes It features 128 bit electrical fuses for root key 32 2 Security ID Register List Module Name Base Address SID 0x01c23800 Register Name Offset Description SID RKEYO 0x00 Root Key 31 0 SID RKEY1 0x04 Root Key 63 32 SID_RKEY2 0x08 Root Key 95 64 SID RKEY3 0x0c Root Key 127 96 32 3 Security ID Register Description 32 3 1 SID Root Key 0 Register Register Name SID RKEYO Offset 0x00 Default Value 0xXXXX XXXX Bit Read Write Default Description 31 0 R D Securiy root key 31 0 32 3 2 SID Root Key 1 Register Register Name SID RKEY1 Offset 0x04 Default Value 0xXXXX XXXX Bit Read Write Default Description 31 0 R D Security root key 63 32
50. 0x00000000 eee eee eeeeeeeneeeeeneeeeeeee 113 13 4 22 Interrupt Response Register 2 Default 0x00000000 ee eee eeeeeteneeeteneeeeeee 113 13 4 23 Interrupt Fast Forcing Register 0 Default 0x00000000 ee eee eeeeeeeeteeeeeeee 113 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 8 Allwinner Technology 13 4 24 Interrupt Fast Forcing Register 1 Default 0x00000000 eerrnrrrnnnrnnrrnnnrrnrrnnnnrrnnn 13 4 25 Interrupt Fast Forcing Register 2 Default 0x00000000 errnrrrvnnrnnrrvnnrnnrrnnnnvnnnn 13 4 26 Interrupt Source Priority 0 Register Default 0Ox00000000 13 4 27 Interrupt Source Priority 1 Register Default 0Ox00000000 13 4 28 Interrupt Source Priority 2 Register Default 0Ox00000000 13 4 29 Interrupt Source Priority 3 Register Default 0Ox00000000 13 4 30 Interrupt Source Priority 4 Register Default 0Ox00000000 13 4 31 Interrupt Source Priority 5 Register Default 0Ox00000000 14 2 Ee le 14 3 DMA Register List iii 14 4 DMA Register Description sue ean die ai ele es nn nes 14 4 1 DMA IRQ Enable Register Default 0x00000000 rrrrnrvrrnnrnrrnrrerrnnnnrrnrnrrnnnerenn 14 4 2 DMA IRQ Pending Status Register Default 0Ox00000000
51. 1 AV a In the only layer B area R R b AV b R bg 1 AV bi G G b AV b G bg 1 AV bi B B b AV_b B bg 1 AV bi In the overlapping area If the priority of layer A is higher than layer B R R a AV a R b AV b R bg 1 AV b 1 AV a G G_a AV_a G b AV b G bg 1 AV b 1 AV a B Ba AVa B b AV b B bg 1 AV b 1 AV a If the priority of layer A is lower than layer B R R a AV a R bg 1 AV a 1 AV b R b AV b G G a AV a G bg 1 AV a 1 AV b G b AV b B B a AV a B bg 1 AV a 1 AV b Bb AV b 28 3 2 Color Key Matching Condition Input Color Output Color DR Color Color Key Matching MUX gt Color Key Theory Block In display engine the process of color key will be done in Alpha Blender1 block Only 2 channels can process color key at the same coordinate of screen If both channels are set into color key mode the higher priority channel will match another channel See the following diagram A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 306 Allwinner Technology Layer A Layer B Screen Back Ground Color Matching Area The alpha value of layer A AV The alpha value of layer A AV b The RGB value of layer A R a G a B a The RGB value of layer B R b G b B b The RGB value of Background color H bg G bg B bg In none matching area As same as normal alpha blending process In matching area If priority of layer A gt p
52. 2N CLK_IN 16 256 STYLUS UP DEBOUCE EN Stylus Up De bounce Function Select 0 Disable 1 Enable Ox0 TOUCH PAN CALI EN Touch Panel Calibration 1 start Calibration it is clear to 0 after calibration TP DUAL EN Touch Panel Double Point Enable 0 Disable 1 Enable TP MODE EN Tp Mode Function Enable 0 Disable 1 Enable 0x0 0x1 0x0 R W 9 R W 8 7 R W 0x0 6 5 R W 0x0 4 R W 3 R W 2 0 R W TP_ADC_SELECT Touch Panel and ADC Select 0 TP 1 ADC ADC_CHAN_SELECT Analog input channel Select In Normal mode 000 X1 channel 001 X2 Channel 010 Y1 Channel 011 Y2 Channel 1xx 4 channel robin round FIFO Access Mode based on this setting Selecting one channel FIFO will access that channel data Selecting four channels FIFO will access each channel data in successive turn first is X1 data A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 261 Allwinner Technology 25 6 3 TP Control Register 2 Offset 0x08 Register Name TP_CNT2 Bit Read W rite Default Hex Description 31 28 RW 0x8 TP_SENSITIVE_ADJUST Internal Pull up Resistor Control 0000 least sensitive 0011 1111 most sensitive Note Used to adjust sensitivity of pen down detection 27 26 R W 0x0 TP_MODE_SELECT TP Mode Select 00 FIFO store X Y data with Z filter 01 FIFO store X Y AX AY da
53. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P07 P06 P05 P04 P03 P02 P01 POO P15 P14 P13 P12 P11 P10 PO9 P08 P23 P22 P21 P20 P19 P18 P17 P16 P31 P30 P29 P28 P27 P26 P25 P24 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POO P01 P02 P03 P04 P05 P06 PO7 P08 PO9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Mono or Internal Frame Buffer 2 Bpp Or Palette 2 Bpp Mode FBF 0001 PS 00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P15 P14 P13 P12 P11 P10 P09 P08 P07 P06 P05 P04 P03 P02 P01 POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P12 P13 P14 P15 P08 P09 P10 P11 P04 P05 P06 P07 POO PO1 PO2 P03 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 10 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P03 P02 PO1 POO P07 P06 P05 P04 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 318 Allwinner Technology P11 P10 P09 P08 P15 P14 P13 P12 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 11 Bit 31 3
54. Allwinner Technology This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 00 OSC24M 25 24 RW 0x0 01 PLL6 10 PLL5 11 23 18 CLK DIV RATIO N 17 16 R W Ox0 Clock pre divide ratio n The select clock source is pre divided by 2n The divider is 1 2 4 8 15 4 CLK DIV RATIO M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 24 SD2 Clock Default 0x00000000 Offset 0x90 Register Name SD2 SCLK CFG REG Read W Default DE Bit f Description rite Hex SCLK_GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK SRC SEL Clock Source Select 00 OSC24M 25 24 RW 0x0 01 PLL6 10 PLL5 11 23 18 CLK DIV RATIO N 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 CLK DIV RATIO M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 25 SS Clock Default 0x00000000 Offset 0x9C Register Name SS_SCLK_CFG_REG A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 67 Allwinner
55. Copyright 2013 Allwinner Technology All Rights Reserved Allwinner Technology e gt S gt EE gt UV00 31 ko EI YUV420 d Z a E a _ 4 rd lt UV00 a BEG UVOIL A La e E UV10 UV11 ja La _ Lat d E gt YUV411 Tile Based Planar Mode Y component The mapping of Y component is the same in YUV422 YUV420 and YUV411 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 281 Allwinner Technology I y D Y U or V component The mapping of V component is the same as U component YUV422 YUV420 YUV411 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 282 Allwinner Technology 27 4 DEFE Register List Module Name Base Address
56. G U component coefficient U U G component coefficient G G V component coefficient V U B component coefficient B G constant U constant B V B Y component coefficient Y V R component coefficient R B U component coefficient U V G component coefficient G B V component coefficient V V B component coefficient B B constant V constant 27 3 6 DEFE Source Input Formats Copyright 2013 Allwinner Technology All Rights Reserved Line JH Line XX E e 81 855 i XX REX e a D D S gt US DR REX X RR BAR AKBAR KA e X vian Om S YUV YCbCr 4 2 2 formatting YUV YCbCr 4 4 4 formatting Line KA M X Line XX X O O O O AAA A A RXXX x EE EE 9 O O O O oO OO B Ge X Y Sample O UV CbCr Sample X Y Sample O UV CbCr Sample 27 3 7 Image Data Memory Mapping The DEFE not only supports the sequence non tile based format input data but also the tile based format input data The tile based format data is valid for YUV422 YUV420 and YUV411 when input data mode is planar or UV combined mode In different conditions the tile based format memory mapping can refer to the following Tile Based UV Combined Mode Y component mapping The mapping of Y component is the same in YUV422 YUV420 and YUV411 UV component mapping YUV422
57. PC Pull Register 1 Register Name PC PULL Offset 0x68 Default Value 0x0000 0016 Bit Read Write Default Description 31 8 PC n Pull up down Select n 16 19 2i 1 2i 00 Pull up down disable 01 Pull up i 0 3 R W 0x16 10 Pull down 11 Reserved A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 375 Allwinner Technology 33 4 19 PD Configure Register 0 Register Name PD CFGO Offset 0x6C Default Value 0x0000 0000 Bit Read Write Default Description 31 PD7 Select 000 Input 001 Output 010 LCD D7 011 ECOL 100 101 30 28 R W 0 110 111 27 PD6 Select 000 Input 001 Output 010 LCD_D6 011 ECRS 100 101 26 24 R W 0 110 111 23 PD5 Select 000 Input 001 Output 010 LCD_D5 011 UART2_RTS 100 101 22 20 R W 0 110 111 19 PD4 Select 000 Input 001 Output 010 LCD_D4 011 UART2_CTS 100 101 18 16 R W 0 110 111 15 PD3 Select 000 Input 001 Output 010 LCD_D3 011 UART2_RX 100 101 14 12 R W 0 110 111 11 PD2 Select 000 Input 001 Output 010 LCD_D2 011 UART2_TX 100 101 10 8 R W 0 110 111 7 6 4 R W 0 3 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 376 Allwinner Technology 20 RW o 33 4 20 PD Configure Register 1
58. RPE 1 R W 0 Receiver Packet End Flag A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 194 Allwinner Technology 0 STO was not detected In CIR mode one CIR symbol is receiving or not detected 1 STO field or packet abort symbol 7 60000 000 and 8 b0000 0000 for MIR and FIR is detected In CIR mode one CIR symbol is received This bit is cleared by writing a 1 ROI Receiver FIFO Overrun 0 Receiver FIFO not overrun 1 Receiver FIFO overrun 0 R W 0 This bit is cleared by writing a 1 20 3 6 CIR Configure Register Register Name IR CIR Offset 0x34 Default Value 0x0000 1828 Bit Read Write Default Description 31 16 ITHR Idle Threshold for CIR The Receiver uses it to decide whether the CIR command has been received If there is no CIR signal on the air the receiver is staying in IDLE status One active pulse will bring the receiver from IDLE status to Receiving status After the CIR is end the inputting signal will keep the specified level high or low level for a long time The receiver can use this idle signal duration to decide that it has received the CIR command The corresponding flag is asserted If the corresponding interrupt is enabled the interrupt line is asserted to CPU When the duration of signal keeps one status high or low level for the specified duration ITHR 1 128 sample cik this mean
59. Read W Default Bit Description rite Hex 31 25 24 0 RW 0 Pixel Seed Value Note avoid set it to 0 Offset 0x020 0x028 Register Name TCON FRM line seed register Read W Default Bit g Z Description 31 25 12 0 R W 0 Pingo value Note avoid set it to 0 29 3 6 TCONO FRM TAB REG Offset 0x02C 0x038 Register Name TCON FRM table register Bit pe perau Description rite Hex 127 0 R W 0 Frm_Table Value 29 3 7 TCONO CTL REG Offset 0x040 Register Name TCONO control register i Read W Default bat Bit f Description rite Hex TCONO En 0 disable 31 R W 0 1 enable Note It executes at the beginning of the first blank line of TCONO timing 30 26 TCONO IF 25 24 RW 0 00 HV Sync DE 01 8080 I F A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 338 Allwinner Technology 10 TTL I F 11 reserved TCONO_RG_Swap 23 R W 0 0 default 1 swap RED and BLUE data at FIFO1 TCONO_Test_Value 22 R W 0 O all Os t all 1s TCONO_FIFO1_Rst 21 R W 0 Write 1 and then 0 at this bit will reset FIFO 1 Note 1 holding time must be more than 1 DCLK TCONO Interlace En 20 RW 0 O disable 1 enable NOTE this flag is valid only when TCONO_EN 1 19 9 TCONO_State_Delay 8 4 R W 0 STA delay NOTE valid only whe
60. Read W Default SC Bit Description rite Hex 31 13 AA KEY FIELD 12 1 R W 0x333 J WDOG_RESTART 0 R W X Watchdog Restart 0 No effect 1 Restart the Watchdog 11 3 25 Watchdog Mode Register Default 0x00000000 Offset 0x94 Register Name WDOG MODE REG Read W Default Bit Description rite Hex A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 97 Allwinner Technology 31 RW WDOG TEST MODE 0 normal mode 1 test mode 30 7 6 3 RW Ox0 WDOG INTV VALUE Watchdog Interval Value Watchdog clock source is OSC24M If the OSC24M is turned off the watchdog will not work 0000 0 5sec 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1sec 2sec 3sec 4sec 5sec 6sec 8sec 10sec 12sec 14sec 16sec 1110 1111 RW Ox0 WDOG RST EN Watchdog Reset Enable 0 No effect on the resets 1 Enables the Watchdog to activate the system reset R W 0x0 WDOG EN Watchdog Enable 0 No effect 1 Enable the Watchdog 11 3 26 64 bit Counter Low Register Default 0x00000000 Offset OxA4 Register Name COUNTER64 LOW REG Read W Default SC Bit Description rite Hex CONT64_LO 31 0 R W 0x0 64 bit Counter 31 0 11 3 27 64 bit Counter High Register Default 0x000000
61. Select the pre scale of timer 4 clock source 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 3 2 R W 0x1 TMR4_CLK_SRC Timer 4 Clock Source 00 01 OSC24M 10 External CLKINO 11 RW Ox0 TMR4 RELOAD Timer 4 Reload 0 No effect 1 Reload timer 0 Interval value After the bit is set it can not be written again before its cleared automatically RW Ox0 TMR4_EN Timer 4 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note 1 If the clock source is External CLKIN the interval value register is not used the current value register is an up counter that counting from 0 2 The time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 11 3 15 ASYNC Timer 4 Interval Value Register Offset 0x54 Register Na
62. set to zero the baud clock is disabled and no serial communications occur Also once the DLH is set at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting 7 0 R W 0 or receiving data 19 4 5 UART Interrupt Enable Register Register Name UART_IER Offset 0x04 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 PTIME Programmable THRE Interrupt Mode Enable This is used to enable disable the generation of THRE Interrupt 0 Disable 7 R W 1 Enable 6 4 EDSSI Enable Modem Status Interrupt This is used to enable disable the generation of Modem Status Interrupt This is the fourth highest priority interrupt 3 R W 0 0 Disable A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 179 Allwinner Technology 1 Enable RW ELSI Enable Receiver Line Status Interrupt This is used to enable disable the generation of Receiver Line Status Interrupt This is the highest priority interrupt 0 Disable 1 Enable R W ETBEI Enable Transmit Holding Register Empty Interrupt This is used to enable disable the generation of Transmitter Holding Register Empty Interrupt This is the third highest priority interrupt 0 Disable 1 Enable R W ERBFI Enable Received Data Available Interrupt This is used to enable disable the generation of Received Data Available In
63. 0 output low level 1 output high level TWI SCL line state control enable When this bit is set the state of TWI_SCL is controlled by the value of bit 3 0 disable TWI SCL line control mode 1 enable TWI SCL line control mode 1 RW TWI SDA line state control bit When line control mode is enabled bit 0 set value of this bit decides the output level of TWI SDA A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 161 Allwinner Technology 0 output low level 1 output high level TWI SDA line state control enable When this bit is set the state of TWI SDA is controlled by the value of bit 1 0 disable TWI SDA line control mode 0 RM 0 1 enable TWI SDA line control mode 17 4 10 TWI DVFS Control Register Register Name WI DVFSCR Offset 0x24 Default Value 0x0000 0000 Bit Read Write Default Description 31 2 CPU and DVFS BUSY set priority select 0 CPU has higher priority 2 R W 0 1 DVFS has higher priority 1 R W 0 CPU Busy set 0 R W 0 DVFS Busy set Notes This register is only implemented in TWIO 17 5 TWI Controller Special Requirement 17 5 1 TWI Pin List Port Name Width Direction Description TWI_SCL 1 IN OUT TWI Clock line TWI_SDA_ 1 IN OUT TWI Serial Data line 17 5 2 TWI Controller Operation There are four operation modes on the two wire
64. 0 No resume K state detected driven on port Default value 0 This functionality defined for manipulating this bit depends on the value of the Suspend bit For example if the port is not suspend and software transitions this bit to a one then the effects on the bus are undefined Software sets this bit to a 1 drive resume signaling The Host Controller sets this bit to a 1 if a J to K transition is detected while the port is in the Suspend state When this bit transitions to a one because a J to K transition is detected the Port Change Detect bit in the USBSTS register is also set to a one If software sets this bit to a one the host controller must not set the Port Change Detect bit Note that when the EHCI controller owns the port the resume sequence follows the defined sequence documented in the USB Specification Revision 2 0 The resume signaling Full speed K is driven on the port as long as this remains a one Software must A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 213 Allwinner Technology appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed Writing a zero from one causes the port to return high speed mode forcing the bus below the port into a high speed idle This bit will remain a one until the port has switched to high speed idle The host controller must complete this transition within 2 milliseconds of so
65. 0 Control Register Default Ox00000004 87 11 3 4 ASYNC Timer 0 Interval Value Register 2424442 88 11 3 5 ASYNC Timer 0 Current Value Register 8eme 88 11 3 6 ASYNC Timer 1 Control Register Default Ox00000004 89 11 3 7 ASYNE Timer 1 Interval Value ET 90 11 3 8 ASYNC Timer 1 Current Value Register 90 11 3 9 ASYNC Timer 2 Control Register Default Ox00000004 90 11 3 10 ASYNC Timer 2 Interval Value Register 91 11 3 11 ASYNC Timer 2 Current Value Register rrrrnnnnnrnvnnnvvnnvnnrnvnnnrvnnrnnnnvnnnvnnnrnnrnnnnnvnenn 91 11 3 12 ASYNC Timer 3 Control Register Default Ox00000000 91 11 313 ASYNE Timer 3 Interval Value Laastad 92 11 3 14 ASYNC Timer 4 Control Register Default Ox00000004 92 11 3 15 ASYNC Timer 4 Interval Value Register 93 11 3 16 ASYNG Timer 4 Current Value Register 210 Nine 94 11 3 17 ASYNC Timer 5 Control Register Default Ox00000004 94 11 3 18 ASYNC Timer 5 Interval Value Register rrrrnnnnnvnnnrnonrnnrnnnnnrnnnrnnrnnnnnrnnnrnnrnnnrnnnenne 95 11 3 19 ASYNC Timer 5 Current Value Register rrrnnnnnnrnvnnnvvnnnnnnnvnnnrnnnvnnnnvnnnvnnnvnnnnnnnnrnenn 95 11 3 20 AVS Counter Control Regi
66. 0 current value is a 56 bit down counter from interval value to 0 The current value register is a 56 bit register When read or write the current value the Low register should be read or written first A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 104 Allwinner Technology 13 Interrupt Controller 13 1 Overview The interrupt controller features Control the nIRQ and FIQ of a RISC Processor Support 96 interrupt sources 4 Level Priority Controller External Sources of Edge sensitive or Level sensitive The 4 level Priority Controller allows users to define the priority of each interrupt source so higher priority interrupts can be serviced even if a lower priority interrupt is being treated 13 2 Interrupt Source The interrupt source 0 is always located at FIQ The interrupt sources 1 to 63 are located at System Interrupt and user peripheral Interrupt Source SRC Vector FIQ Description External Non Mask Interrupt External NMI 0 0x0000 yes 1 ower deg battery VDD VDDIO VDD18 VDD25 brownout detect 1 0x0004 UART 1 2 0x0008 UART 1 interrupt 3 0x000C UART 3 4 0x0010 UART 3 interrupt IR 5 0x0014 IR O interrupt 6 0x0018 TWI O 7 0x001C TWI 0 interrupt TWI 1 8 0x0020 TWI 1 interrupt TWI 2 9 0x0024 TWI 2 interrupt SPI 0 10 0x0028 SPI 0 interrupt SPI 1 11 0x002C SPI 1 interrupt SPI 2 12 0x0030 SPI 2 interr
67. 0x0 Scanning Mode selection 0 non interlace 1 interlace 11 DATA_MOD Input data mode selection 000 non tile based planar data 001 interleaved data vr SS ES 010 non tile based UV combined data 100 tile based planar data 110 tile based UV combined data other reserved 7 DATA_FMT 6 4 RW 0x0 Input component data format In non tile based planar data mode 000 YUV 4 4 4 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 290 Allwinner Technology 001 YUV 4 2 2 010 YUV 4 2 0 011 YUV 4 1 1 100 CSI RGB data 101 RGB888 Other Reserved In interleaved data mode 000 YUV 4 4 4 001 YUV 4 2 2 101 ARGB8888 Other reserved In non tile based UV combined data mode 001 YUV 4 2 2 010 YUV 4 2 0 011 YUV 4 1 1 Other reserved In tile based planar data mode 001 YUV 4 2 2 010 YUV 4 2 0 011 YUV 4 1 1 Other Reserved In tile based UV combined data mode 001 YUV 4 2 2 010 YUV 4 2 0 011 YUV 4 1 1 Other reserved 3 2 1 0 R W 0x0 DATA_PS Pixel sequence In interleaved YUV422 data mode 00 Y1VOYOUO 01 VOY1U0YO 10 Y1U0YOVO 11 UOY1VOYO In interleaved YUV444 data mode 00 VUYA 01 AYUV Other reserved In UV combined data mode UV component 00 V1U1VOUO 01 U1V1UOVO Other reserved In interleaved ARGB8888 data mode 00 BGRA A13 User Manual V1 3 Copyright 2013 Allwinn
68. 0x0154 Mali400 Gating Special Clock 0x0158 MBUS SCLK CFG REG 0x015C MBUS Gating Clock IEP SCLK CFG REG 0x0160 IEP Gating Clock 6 4 CCM Register Description 6 4 1 PLL1 Core Default 0x21005000 Offset 0x00 Register Name PLL1_CFG_REG Read W Default us Bit l Description rite Hex PLL1_Enable 0 Disable 1 Enable The PLL1 output 24MHZ N K M P 31 R W 0x0 The PLL1 output is for the CORECLK Note the output 24MHZ N K clock must be in the range of 240MHz 2GHz if the bypass is disabled Its default is 384MHz 30 18 17 16 RW 0x0 PLL1 OUT EXT DIVP A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 53 Allwinner Technology PLL1 Output external divider P The range is 1 2 4 8 15 13 PLL1 FACTOR N PLL1 Factor N Factor 0 N 0 12 8 R W 0x10 Factor 1 N 1 Factor 2 N 2 Factor 31 N 31 7 6 PLL1_FACTOR_K 5 4 R W 0x0 PLL1 Factor K K Factor 1 The range is from 1 to 4 3 R W 0x0 2 R W 0x0 PLL1 FACTOR M 1 0 R W 0x0 PLL1 Factor M M Factor 1 The range is from 1 to 4 6 4 2 PLL1 Tuning Default 0x0A101000 Offset 0x04 Register Name PLL1 TUN REG Read W Default Bit Description rite Hex 31 28 27 R W Ox1 26 R W 0x0 25 23 RW 0x4 22 16 RW 0x10 15 R W 0x0 14 8 R W 0x10 7 R W
69. 0x01C2 2000 0x01C2 23FF 1K IIS 0x01C2 2400 0x01C2 27FF 1K LRADC 0x01C2 2800 0x01C2 2BFF 1K Audio Codec 0x01C2 2C00 0x01C2 2FFF 1K KEYPAD 0x01C2 3000 0x01C2 33FF CPU Control 0x01C2 3400 0x01C2 37FF 1K SID 0x01C2 3800 0x01C2 3BFF 1K 0x01C2 3C00 0x01C2 3FFF 1K A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 27 Allwinner Technology 0x01C2 4000 0x01C2 43FF 1K 0x01C2 4400 0x01C2 47FF 1K 0x01C2 4800 0x01C2 4BFF 1K 0x01C2 4C00 0x01C2 4FFF 1K TP 0x01C2 5000 0x01C2 53FF 1K PMU 0x01C2 5400 0x01C2 57FF 1K 0x01C2 5800 0x01C2 5BFF 1K 0x01C2 5C00 0x01C2 5FFF 1K 0x01C2 6000 0x01C2 63FF 1K 0x01C2 6400 0x01C2 67FF 1K 0x01C2 6800 0x01C2 6BFF 1K 0x01C2 6C00 0x01C2 6FFF 1K 0x01C2 7000 0x01C2 73FF 1K 0x01C2 7400 0x01C2 77FF 1K 0x01C2 7800 0x01C2 7BFF 1K 0x01C2 7C00 0x01C2 7FFF 1K 0x01C2 8000 0x01C2 83FF 1K UART 1 0x01C2 8400 0x01C2 87FF 1K 0x01C2 8800 0x01C2 8BFF 1K UART 3 0x01C2 8C00 0x01C2 8FFF 1K 0x01C2 9000 0x01C2 93FF 1K 0x01C2 9400 0x01C2 97FF 1K 0x01C2 9800 0x01C2 9BFF 1K 0x01C2 9C00 0x01C2 9FFF 1K 0x01C2 A000 0x01C2 A3FF 1K 0x01C2 A300 0x01C2 A7FF 1K 0x01C2 A800 0x01C2 ABFF 1K TWIO 0x01C2 AC00 0x01C2 AFFF 1K TWI 1 0x01C2 B000 0x01C2 B
70. 1 Clock is ON IEP CLOCK BE Clock IEP RST 30 R W 0x0 IEP Reset 0 reset valid 1 reset invalid 29 0 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 77 Allwinner Technology 7 System Control 7 1 Overview The chip embeds a high speed SRAM which is split into five areas Its Memory Mapping is detailed in the following table Area Address Size Bytes A1 0x00000000 0x00003FFF 16K A2 0x00004000 0x00007FFF 16K A3 0x00008000 0x0000B3FF 13K A4 0x0000B400 0x0000BFFF 3K C1 0x01D00000 0x01D7FFFF VE C3 0x01DC0000 0x01DCFFFF ISP NAND 2K D USB 0x00010000 0x00010FFF 4K CPU I Cache 32K CPU D Cache 32K CPU L2 Cache 128K 7 2 System Control Register List Module Name Base Address SRAM 0x01C00000 Register Name Offset Description SRAM CFG REGO 0x0000 SRAM Configuration SRAM CFG REG1 0x0004 SRAM Control 7 3 System Control Register Description 7 3 1 SRAM Configuration Register 0 Default 0x7FFFFFFF Offset 0x00 Register Name SRAM_CFG_REGO Bit Read Default H Description Write ex 31 SRAM C1 MAP SRAM Area C1 50K Bytes Configuration by AHB 0 map to CPU DMA 1 map to VE 30 0 RW Ox7fffffff A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 78 Allwinner
71. 1 Timer 1 Interval Value reached interrupt enable STMRO INT EN 0 RAW 0x0 Sync Timer 0 Interrupt Enable 0 No effect 1 Timer 0 Interval Value reached interrupt enable A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 100 12 3 2 Allwinner Technology Sync Timer IRQ Status Register Default 0x00000000 Offset 0x04 Register Name SYNC TMR IRQ STAS REG Bit Read W rite Default Hex Description 31 2 R W 0x0 STMR1_IRQ_PEND Sync Timer 1 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 1 interval value is reached R W 0x0 STMRO IRQ PEND Sync Timer 0 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 0 interval value is reached 12 3 3 Sync Timer 0 Control Register Default 0x00000004 Offset 0x10 Register Name SYNC TMRO CTRL REG Bit Read W rite Default Hex Description 31 RW Ox0 SYNC_TMRO TEST Sync timer0 test mode In test mode the low register should be set to 0x1 the high register will down count The counter needs to be reloaded 0 normal mode 1 test mode 30 8 R W 0x0 STMRO MODE Sync Timer0 mode 0 Continuous mode When reaches the internal value the timer will not be disabled automatically 1 Single mode When reaches the internal value the timer will be disable
72. 101 22 20 R W 0 110 111 19 PD20 Select 000 Input 001 Output 010 LCD_D20 011 ETXD1 100 101 18 16 R W 0 110 111 15 PD19 Select 000 Input 001 Output 010 LCD_D19 011 ETXDO 100 101 14 12 R W 0 110 111 11 PD18 Select 000 Input 001 Output 010 LCD_D18 011 ERXDV 10 8 R W 0 100 101 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 378 Allwinner Technology 110 111 7 6 4 R W 0 3 2 0 RW 0 33 4 22 PD Configure Register 3 Register Name PD CFG3 Offset 0x78 Default Value 0x0000 0000 Bit Read Write Default Description 31 16 15 PD27 Select 000 Input 001 Output 010 LCD_VSYNC 011 EMDIO 100 101 14 12 RW 0 110 11157 11 PD26 Select 000 Input 001 Output 010 LCD HSYNG 011 EMDC 100 101 10 8 RW 0 110 111 7 PD25 Select 000 Input 001 Output 010 LCD DE 011 ETXERR 100 101 6 4 RW 0 110 111 3 PD24 Select 000 Input 001 Output 010 LCD CLK 011 ETXCK 100 101 2 0 R W 0 110 111 33 4 23 PD Data Register Register Name PD DAT Offset 0x7C Default Value 0x0000 0000 Bit Read Write Default Description 31 28 If the port is configured as input the corresponding bit is the pin 27 0 R W 0 state If the port is configured
73. 110 64 111 128 3 2 R W 0x1 TMR5_CLK_SRC Timer 5 Clock Source 00 01 OSC24M 10 External CLKIN1 11 7 Ox0 TMR5 RELOAD Timer 5 Reload 0 No effect 1 Reload timer 0 Interval value A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 94 Allwinner Technology After the bit is set it can not be written again before its cleared automatically TMR5 EN Timer 5 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 0 RAW 0x0 If the current counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note 1 If the clock source is External CLKIN the interval value register is not used the current value register is an up counter that counting from 0 2 The time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 11 3 18 ASYNC Timer 5 Interval Value Register Offset 0x
74. 190 Allwinner Technology Default Value 0x0000 0000 Bit Read Write Default Description 31 7 Transmit FIFO Level 6 0 R 0 This indicates the number of data entries in the transmit FIFO 19 4 15 UART Receive FIFO Level Register Register Name UART RFL Offset 0x84 Default Value 0x0000 0000 Bit Read Write Default Description 31 7 Receive FIFO Level 6 0 R 0 This indicates the number of data entries in the receive FIFO 19 4 16 UART Halt TX Register Offset OxA4 Register Name UART HALT Default Value 0x0000 0000 Bit Read Write Default Description 31 6 SIR Receiver Pulse Polarity Invert 0 Not invert receiver signal 1 Invert receiver signal SIR Transmit Pulse Polarity Invert 0 Not invert transmit pulse 1 Invert transmit pulse 0 R W Halt TX This register is use to halt transmissions for testing so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled 0 Halt TX disabled 1 Halt TX enabled Note If FIFOs are not enabled the setting of the halt TX register has no effect on operation 19 5 UART Special Requirement 19 5 1 IrDA Inverted Signals When the UART is working in IrDA mode MCR 6 1 if HALT 4 is set to 1 the signal is inverted before transferring to pin SOUT and if HALT 5 is set to 1 the si
75. 2 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved Allwinner Technology 27 5 53 DEFE CH1 VERTCOEF REGN N 0 31 Offset 0x700 N 4 Register Name DEFE CH1 VERTCOEF REGN Read W Default Kee Bit Description rite Hex TAP3 31 24 RW 0x0 Vertical tap3 coefficient The value equals to coefficient 2 TAP2 23 16 RW 0x0 Vertical tap2 coefficient The value equals to coefficient 29 TAP1 15 8 R W 0x0 Vertical tap1 coefficient The value equals to coefficient 2 TAPO 7 0 R W 0x0 Vertical tap0 coefficient The value equals to coefficient 2 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 303 Allwinner Technology 28 Display Engine Back End DEBE 28 1 Overview The Display Engine Back End DEBE features A13 User Manual V1 3 4 moveable amp size adjustable layers Layer size up to 8192 8192 pixels Support Alpha blending Support color key Support write back function Support 1 2 4 8 bpp mono palette Support 16 24 32 bpp color external frame buffer 5 6 5 1 5 5 5 0 8 8 8 8 8 8 8 8 8 8 4 4 4 4 Support on chip SRAM 256 entry 32 bpp palette 1 2 4 8 bpp internal frame buffer support Gamma correction Support hardware cursor 32x32 8 bpp 64x64 2 bpp 64x32 4 bpp 32x64 4 bpp Support YUV input channel Output color correction
76. 23 Priority Set priority level for IRQ bit 23 15 14 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ22 PRIO IRQ 22 Priority Set priority level for IRQ bit 22 13 12 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ21_PRIO IRQ 21 Priority 11 10 R W 0x0 Set priority level for IRQ bit 21 Level 0x0 level 0 lowest priority Level 0x1 level 1 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 118 Allwinner Technology Offset 0x84 Register Name INTC SRC PRIO REG1 Level 0x1 level 2 Level 0x1 level 3 highest priority 9 8 R W 0x0 IRQ20_PRIO IRQ 20 Priority Set priority level for IRQ bit 20 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 7 6 RW Ox0 IRQ19 PRIO IRQ 19 Priority Set priority level for IRQ bit 19 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 5 4 RW Ox0 IRQ18 PRIO IRQ 18 Priority Set priority level for IRQ bit 18 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 3 2 RW Ox0 IRQ17_PRIO IRQ 17
77. 29 3 32 TOCONT FILL BEGIN REG was tanins 348 RC NS EE EN ren nr eee nee Pee nr omeer arom nnn sete nT ere ner Ernrrrr rere 349 EN e RT ER E oe ee ne ee eee eee 349 TER 350 SE NNN 350 30 2 IEP ee ER le re 350 30 2 1 General Control Register sc a a dada nude 350 30 2 2 DRC Size REN 350 30 2 3 Ree Oe EE 351 30 2 4 DRC External LGC Start Address Register vunnet 351 30 2 5 DRCG Setting SIS USM 1 sean nan en nn ee 351 30 2 6 DRC Window Position DEER gege 2 4 224 0 0 ne 352 30 2 7 DRC Window Position Register 2e Rene 352 30 2 8 DRC Write Back Control Register nt 353 30 2 9 DRC Write Back Address RediSi r 1 353 30 2 10 DRC Write Back Buffer Line Width Register 354 30 2 11 Luminance Histogram Control Regist r eee 354 30 2 12 Luminance Histogram Threshold Setting Register 0 354 30 2 13 Luminance Histogram Threshold Setting Register 1 354 30 2 14 Luminance Histogram Statistics Lum Recording Hegieter 355 30 2 15 Luminance Histogram Statistics Counter Recording Register rrrrnrnnnrnnnvnnrnrnenn 355 30 2 16 CSC Y G Coefficient Register tienne tnt tnt 355 30 2 17 MANNEN cs geen een nee ene nor ee nP amen nnn nD ten eee ner ErnCEn Tene 356 30 2 18 CSC U R CoBtici ent ASOISIE Ten aces cet coe en ne 356 30 2 19 CSC U R Constant Regisiehnn to 356 30 2 20 CSC V B Coefficient Regisiel 1s 356 30 2 21 CSC V B Constant E E 357 30 2 22 RENN aeeeemee een ere meen re mr aerey Seeeer reer vene re
78. 49 0x00C4 PMU interrupt 50 0x00C8 51 0x00CC 52 0x00D0 VE 53 0x00D4 VE interrupt SS 54 0x00D8 Security System interrupt 55 0x00DC 56 0x00E0 57 Ox00E4 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 106 Allwinner Technology Interrupt Source SRC Vector FIQ Description 58 0x00E8 59 Ox00EC 60 0x00F0 61 0x00F4 62 0x00F8 63 Ox00FC 64 0x100 65 0x104 PLE on non secure transfers interrupt PLE PERFMU 66 0x108 PLE on secur transfer interrupt PLE error interrupt Performance monitor interrupt Timer 4 67 0x010C Timer 4 interrupt Timer 5 68 0x0110 Timer 5 interrupt GPU GP 69 0x0114 GPU GPMMU 70 0x0118 GPU PPO 71 0x011C GPU PPMMUO 72 0x0120 GPU PMU 73 0x0124 GPU RSVO 74 0x0128 GPU RSV1 75 0x012C GPU RSV2 76 0x0130 GPU RSV3 77 0x0134 GPU RSV4 78 0x0138 GPU RSV5 79 0x013C GPU RSV6 80 0x0140 81 0x0144 Sync timer 0 82 0x0148 Sync timer 1 83 0x014C 13 3 Interrupt Register List Module Name Base Address INTC 0x01C20400 Register Name Offset Description INTC_VECTOR REG 0x0000 Interrupt Vector INTC BASE ADDR REG 0x0004 Interrupt Base Address INC PROTEC REG 0x0008 Interrupt Protection INTC_NMII CTRL REG 0x000C Interrupt Control INTC_IRQ_PEND_REGO 0x0010 Interrupt IRQ Pending 0 Status
79. 7 SS IVO 0x24 Security Initialization Vector 0 SS IV1 0x28 Security Initialization Vector 1 SS IV7 0x40 Security Initialization Vector 7 SS_FCSR 0x44 Security FIFO Control Status Register SS_ICSR 0x48 Security Interrupt Control Status Register SS_MDO 0x4C SHA1 MD5 Message Digest 0 PRNG Data0 SS_MD1 0x50 SHA1 MD5 Message Digest 1 PRNG Data1 SS_MD2 0x54 SHA1 MD5 Message Digest 2 PRNG Data2 SS_MD3 0x58 SHA1 MD5 Message Digest 3 PRNG Data3 SS_MD4 0x5C SHA1 MD5 Message Digest 4 PRNG Data4 SS_RXFIFO 0x200 RX FIFO input port SS_TXFIFO 0x204 TX FIFO output port 31 4 Security System Register Description 31 4 1 Security System Control Register Offset 0x00 Register Name SS_CTL Default Value 0x0000 0000 Bit Read Write Default Description 31 28 27 24 R W AES DES 3DES key select 0 Select input SS_KEYx Normal Mode 1 Select SID RKEYx from Security ID 2 Reserved 3 10 Select internal Key n n from 0 to 7 Others Reserved 18 16 R Reserved 15 R W PRNG generator mode 0 One shot mode 1 Continue mode 14 R W IV Steady of SHA 1 MD5 constants 0 Constants 1 Arbitrary IV Notes It is only used for SHA 1 MD5 engine If the number of IV word is beyond of 4 Counter 0 register is used for IV4 13 12 R W SS Operation Mode 00 Electronic Code Book ECB mode 01 Cipher Block Chaining CBC mode 10 11 Reserved 11 10 A13 User Manual V
80. A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 107 Allwinner Technology INTC_IRQ PEND REG1 0x0014 Interrupt IRQ Pending 1 Status INTC IRQ PEND REG2 0x0018 Interrupt IRQ Pending 2 Status 0x001C INTC FIQ PEND REGO 0x0020 Interrupt FIQ Pending 0 Status INTC FIQ PEND REG 0x0024 Interrupt FIQ Pending 1 Status INTC FIQ PEND REG2 0x0028 Interrupt FIQ Pending 2 Status 0x002C INTC SEL REGO 0x0030 Interrupt Select 0 INTC SEL REG1 0x0034 Interrupt Select 1 INTC SEL REG2 0x0038 Interrupt Select 2 0x003C INTC EN REGO 0x0040 Interrupt Enable 0 INTC EN REG 0x0044 Interrupt Enable 1 INTC EN REG2 0x0048 Interrupt Enable 2 0x004C INTC_MASK_REGO 0x0050 Interrupt Mask 0 INTC_MASK_REG1 0x0054 Interrupt Mask 1 INTC MASK REG2 0x0058 Interrupt Mask 2 0x005C INTC_RESP_REGO 0x0060 Interrupt Response 0 INTC RESP REG1 0x0064 Interrupt Response 1 INTC RESP REG2 0x0068 Interrupt Response 2 0x006C INTC FORCE REGO 0x0070 Interrupt Fast Forcing 0 INTC FORGE REG 0x0074 Interrupt Fast Forcing 1 INTC FORGE REG2 0x0078 Interrupt Fast Forcing 2 0x007C INTC_SRC_PRIO_REGO 0x0080 Interrupt Source Priority 0 INTC_SRC_PRIO_REG1 0x0084 Interrupt Source Priority 1 INTC_SRC_PRIO_REG2 0x0088 Interrupt Source Priority 2 INTC_SRC_PRIO_REG3 0x008C Interrupt Source Priority 3 INTC_SRC_PRIO_REG4 0x0090 Interr
81. APB clock input For 400kHz full speed 2Wire CLK_N 2 CLK_M 2 FO 48M 212 12Mhz F1 F0 10 2 1 0 4Mhz For 100Khz standard speed 2Wire CLK_N 2 CLK_M 11 F0 48M 2 2 12Mhz F1 F0 10 11 1 0 1Mhz A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 160 Allwinner Technology 17 4 7 TWI Soft Reset Register Register Name TWI_SRST Offset 0x18 Default Value 0x0000 0000 Bit Read Write Default Description 31 1 Soft Reset Write 1 to this bit to reset the TWI and clear to 0 when complete 0 R W 0 Soft Reset operation 17 4 8 TWI Enhance Feature Register Register Name TWI EFR Offset 0x1C Default Value 0x0000 0000 Bit Read Write Default Description 31 2 i Data Byte follow Read Command Control No Data Byte to be written after read command Only 1 byte data to be written after read command 2 bytes data can be written after read command 0 1 R W 0 3 bytes data can be written after read command 17 4 9 TWI Line Control Register Offset 0x20 Register Name TWI LCR Default Value 0x0000 003a Bit Read Write Default Description 31 6 Current state of TWI SCL 0 low 1 high Current state of TWI SDA 0 low 1 high TWI_SCL line state control bit When line control mode is enabled bit 2 set value of this bit decide the output level of TWI SCL
82. AXI Clock 00 1 01 2 10 4 11 8 3 2 1 0 R W 0x0 AXI_CLK_DIV_RATIO A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 61 Allwinner Technology AXI Clock divide ratio AXI Clock source is CPU clock 00 1 01 2 10 3 11 4 6 4 15 APB1 Clock Divide Ratio Default 0x00000000 Offset 0x58 Register Name APB1 CLK DIV REG Bit Al keg Description Write Hex 31 26 APB1_CLK_SRC_SEL APB1 Clock Source Select 00 OSC24M 01 PLL6 set to 1 2GHz 25 24 RM 0x0 10 32KHz 11 This clock is used for some special module apbcik TWI UART and SCR Because these modules need special clock rate even if the apbclk changes 23 18 CLK_RAT_N 17 16 RW 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 5 CLK RAT M 4 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 32 6 4 16 AXI Module Clock Gating Default 0x00000000 Offset 0x5C Register Name AXI_GATING_REG Read Default AE Bit Write Mek Description 31 1 0 RW oxo DRAM ANLCGATING Gating AXI Clock for SDRAM 0 mask 1 pass 6 4 17 AHB Module Clock Gating Register 0 Default 0x00000000 Offset 0x60 Register Name AHB_GATING_REGO Bit eae SEH Description Writ
83. Bit i Description rite Hex 31 13 COEF 12 0 R W 0x0 the V B coefficient the value equals to coefficient 2 27 5 33 DEFE CSC COEF23 REG Offset Ox9C Register Name DEFE CSC COEF23 REG Bit PERUN SE Description rite Hex 31 14 CONT 13 00 R W 0x0 the V B constant the value equals to coefficient 2 27 5 34 DEFE WB LINESTRD EN REG Offset OxDO Register Name DEFE WB LINESTRD EN REG Read W Default SC Bit f Description rite Hex 31 1 EN Wri ER 0 RW oxo me back line stride enable 0 disable 1 enable 27 5 35 DEFE_WB_LINESTRDO REG Offset 0xD4 Register Name DEFE WB LINESTRDO REG Bit Read W rite Default Hex Description A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 297 Allwinner Technology 31 0 R W 0x0 LINE_STRD Ch3 write back line stride 27 5 36 DEFE CHO INSIZE REG Offset 0x100 Register Name DEFE CHO INSIZE REG Read W Default ar Bit Description rite Hex 31 29 IN HEIGHT 28 16 RW 0x0 Input image Y G component height Input image height The value of these bits add 1 15 13 IN WIDTH Input image Y G component width 12 0 R W 0x0 The image width The value of these bits add 1 When line buffer result selection is original data the maximum width is 2048
84. Copyright 2013 Allwinner Technology All Rights Reserved 304 28 2 DEBE Block Diagram AHB B U Sse Intelligent Ext DMA Controller H W Cursor pattern buffer Normal YUV Palette Gamma Internal frame buffer Controller FEI CT Is SC PIPE 1 FIFO les Alpha Alpha Color yl S S Blender 1 Blender 0 Correction Ox PIPE 0 FIFO A gt JOE I ore Write back channel DEFE DEBE Figure 28 1 Display Engine Block Diagram 28 3 DEBE Description 28 3 1 Alpha Blending Alpha blending is a convex combination of two colors allowing for transparency effects in computer graphics The value of alpha in the color code ranges from 0 0 to 1 0 where 0 0 represents a fully transparent color and 1 0 represents a fully opaque color In the display engine If setting the alpha register value ARV OB xxxxxxxx 8 bit value Then the alpha value AV ARV 256 Layer A Layer B Screen Back Ground Color Overlapping Area In the above diagram layer A and layer B are not in same channel The alpha value of layer A AV a The alpha value of layer A AV_b The RGB value of layer A R a G a B a Copyright 2013 Allwinner Technology All Rights Reserved Allwinner Technology The RGB value of layer B R b G b B b The RGB value of Background color R_bg G_bg B_bg In the only layer A area R R a AV a R bg 1 AV a G G a AV a G bg 1 AV a B B a AV_a B bg
85. Copyright O 2013 Allwinner Technology All Rights Reserved 284 Allwinner Technology rite Hex 31 1 R W 0x0 EN DEFE enable 0 Disable 1 Enable When DEFE enable bit is disabled the clock of DEFE module will be disabled If this bit transits from 0 to 1 the frame process control register and the interrupt enable register will be initialized to default value and the state machine of the module is reset 27 5 2 DEFE_FRM_CTRL_REG Offset 0x4 Register Name DEFE_FRM_CTRL_REG Bit Read W rite Default Hex Description 31 24 23 R W COEF_ACCESS_CTRL Fir coef ram access control 0 CPU doesn t access fir coef ram 1 CPU will access fir coef ram This bit will be set to 1 before CPU accesses fir coef ram 22 17 16 R W 0x0 FRM_START Frame start amp reset control 0 reset 1 start If the bit is written to zero the whole state machine and data paths of DEFE module will be reset When the bit is written to 1 DEFE will start a new frame process 15 12 11 R W 0x0 OUT_CTRL DEFE output control 0 enable DEFE output to DEBE 1 disable DEFE output to DEBE If DEFE write back function is enabled DEFE output to DEBE isn t recommended 10 3 R W 0x0 WB_EN Write back enable 0 Disable 1 Enable If output to DEBE is enabled the writin
86. DEBE eesesvvvenvvvevenevneneveeneveenenennenevesnennenenennenenneneneunennnneneneeneneenenennenense 304 281 e EE 304 28 2 DEBE Block Diagram sise 305 203 DEBE D SCrIPIONE ER erm nett eee tee peter eter ene ee ee re 305 28 3 1 Aloha BICNGING c 1 ir hn anh ee 305 28 3 2 CR EE een ee EE EE EEE ee 306 28 3 3 PIPE see 307 28 4 DEBE Ke ET EEN 307 28 5 DEBE Register Descriptions ein eee eee ase eel nei ends en erie 309 28 5 1 DEBE Mode Control ee 309 28 5 2 DE Back Color Control Eet eieiei EEN Ee 310 28 5 3 DE Back Display Size Setting Register rrarrnnnnvnnnvvnnrnnnnvnnnrnnnrnnnnnnnnrnnnrnnrnnnrnvnenn 310 28 5 4 DE Layer Ee E 310 28 5 5 DE Layer Coordinate Control Register aerer ere 311 28 5 6 DE Layer Frame Buffer Line Width Register 311 28 5 7 DE Layer Frame Buffer Low 32 Bit Address Register 312 28 5 8 DE Layer Frame Buffer High 4 Bit Address Register 312 28 5 9 DE Register Buffer Control Register 312 28 5 10 DE Color Key MAX REESEN AE 313 28 5 11 DE Golbr Key MIN Register Lusmaeneanansdnmmdnnnindmndddambdndsdntddetssndder 313 28 5 12 DE Color Key Configuration Register sas NS RSR 314 28 5 13 DE Layer Attribute Control Register 314 28 5 14 DE Layer Attribute Control Register ss 316 28 5 15 Pixels Sequence AIRE eee er mee eee 317 28 5 16 DE HWC Coordinate Control Register nas 320 28 5 17 DE HWC Frame Buffer Format Register 2228 321 28 5 18 DEBE Write Back Control Register nuasmsiseimmsinnt
87. Data Available Pending bit 8 R W 0 0 No TX FIFO pending A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 361 Allwinner Technology 1 TX FIFO pending Notes Write 1 to clear or automatically clear if interrupt condition fails 7 5 R W DRQ Enable 0 Disable DRQ CPU polling mode 1 Enable DRQ DMA mode R W RX FIFO Empty Interrupt Enable 0 Disable 1 Enable Notes If it is set to 1 when the number of empty room is no smaller than gt the preset threshold the interrupt is triggered and the correspond flag is set R W TX FIFO Data Available Interrupt Enable 0 Disable 1 Enable Notes If it is set to 1 when available data number is no smaller than gt the preset threshold the interrupt is triggered and the correspond flag is set 31 4 6 Security System Message Digest n Register Offset Ox4C 4 n Register Name SS MD n Default Value 0x0000 0000 Bit Read Write Default Description 31 0 R 0 SHA1 MD5 Message digest MD n for SHA1 MD5 n 0 4 31 4 7 Security System RX FIFO Register Offset 0x200 Register Name SS_RX Default Value 0x0000 0000 Bit Read Write Default Description 31 0 W 0 32 bits RX FIFO for Input 31 4 8 Security System TX FIFO Register Offset 0x204 Register Name SS TX Default Value
88. Default 0x11049280 remets 57 6 4 8 PLL5 Tuning Default 04880000 2 2 2 ts nn knhnhineneihnknknkhnnnheenkak 58 6 4 9 PLL6 Default EIN Nede 58 6 4 10 PLL7 Default HUNN cc 59 6 4 11 PLL1 Tuning2 Default 0x00000000 iscsi ot 59 6 4 12 PLL5 Tuning2 Default AT RENE 60 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 5 Allwinner Technology 6 4 13 OSC24M Default 0x00138013 enee 60 6 4 14 CPU AHB APBO Clock Ratio Default OsO0O0O 00101 61 6 4 15 APB1 Clock Divide Ratio Default Ox00000000 62 6 4 16 AXI Module Clock Gating Default 0x00000000 rrrrrnrvrrrnrnnrrnverenrnrrrnnnnrrnrerennnernn 62 6 4 17 AHB Module Clock Gating Register 0 Default 0Ox00000000 62 6 4 18 AHB Module Clock Gating Register 1 Default 0Ox00000000 63 6 4 19 APBO Module Clock Gating Default 0x00000000 rrrrrrrrnrnrrrrrerrnrnrrrrnrrrnrerrnnnern 64 6 4 20 APB1 Module Clock Gating Default 0x00000000 rrnrrrrenrnrrnnverrnrnrrrnrnnrrrrerrnnnernn 65 6 4 21 NAND Clock Default 0x00000000 Us 65 6 4 22 SDO Clock Default 0x00000000 VU 66 6 4 23 SD1 Clock Default 0x00000000 VU 66 6 4 24 SD2 Clock Default 0x00000000 VU 67 6 4 25 SS Clock Default 0x00000000 a a E AE E 67 6 4 26 SPIO Clock Default Ox00000000
89. Disable interrupt generation due to Scheduling Overrun 22 6 7 HcHCCA Register Offset 0x418 Register Name HcHCCA Default Value 0x0 Read Write Bit HCD HC Default Description HCCA 31 8 This is the base address of the Host Controller Communication Area This area is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and 31 8 RW R 0x0 the Host Controller Driver HCCA 7 0 The alignment restriction in HcHCCA register is evaluated by examining the number of zeros in the lower order bits The minimum alignment is 256 bytes therefore bits 0 through 7 must 7 0 R R 0x0 always return 0 when read 22 6 8 HcPeriodCurrentED Register Offset 0x41c Register Name HcPeriodCurrentED PCED Default Value 0x0 Bit Read Write HCD HC Default Description A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 221 Allwinner Technology 31 4 RW Ox0 PCED 31 4 This is used by HC to point to the head of one of the Periodec list which will be processed in the current Frame The content of this register is updated by HC after a periodic ED has been processed HCD may read the content in determining which ED is currently being processed at the time of reading 3 0 R R Ox0 PCED 3 0 Because the general
90. Enable 28 27 26 25 R W 0x0 DDMA DST DATA WIDTH DMA Destination Data Width 00 8 bit 01 16 bit 10 32 bit 11 24 23 RW Ox0 DDMA DST BST LEN DMA Destination Burst Length 00 1 01 4 10 8 11 22 21 R W 0x0 DDMA_ADDR_MODE DMA Destination Address Mode DMA Source Address Mode 0x0 Linear Mode 0x1 IO Mode 0x2 Horizontal Page Mode 0x3 Vertical Page Mode 20 16 R W 0x0 DDMA_DST_DRQ_SEL Dedicated DMA Destination DRQ Type 0x0 SRAM memory 0x1 SDRAM memory 0x2 0x3 NAND Flash Controller NFC 0x4 USBO 0x5 0x6 0x7 0x8 SPI1 TX 0x9 OxA Security System TX A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 141 Allwinner Technology OxB OxC OxD OxE TCONO OXF 0x10 Ox11 Ox12 AEN Ox14 Ox15 Ox16 Ox17 AEN 0x19 Ox1A SPIO TX Ox1B Ox1C SPI2 TX Ox1D Ox1E Ox1F BC_MODE_SEL BC mode select 15 R W 0x0 0 normal mode the value read back equals to the value that is written 1 remain mode the value read back equals to the remain counter to be transferred 14 11 DDMA SRC DATA WIDTH DMA Source Data Width 00 8 bit 01 16 bit 10 32 bit 11 10 9 R W 0x0 DDMA SRC BST LEN DMA Source Burst Length 00 1 01 4 10 8 11 8 7 R W 0x0 DDMA_SRC_AD
91. Enabled LAY2 EN Layer2 Enable Disable 0 Disabled 1 Enabled LAY1 EN Layer1 Enable Disable 0 Disabled 1 Enabled LAYO EN A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 309 Allwinner Technology Layer0 Enable Disable 0 Disabled 1 Enabled START_CTL Normal output channel Start amp Reset control 0 reset 1 start DEBE_EN DEBE enable disable 0 disable 1 enable Offset 0x804 Register Name DEBE_BACKCOLOR_REG Read Default e lal peee o Leen Red Red screen background color value BK GREEN Green Green screen background color value BK BLUE Blue Blue screen background color value 28 5 3 DE Back Display Size sea Register DIS HEIGHT Display height The real display height The value of these bits add 1 DIS_WIDTH Display width The real display width The value of these bits add 1 Layer 0 0x810 Register Name DEBE_LAYSIZE_REG Layer 1 0x814 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 310 Allwinner Technology Layer 2 0x818 Layer 3 0x81C Read Wr Default S Bit Description ite Hex LAY HEIGHT 28 16 R W UDF Layer Height The Layer Height The value of these bits add 1 LAY_WIDTH Layer Width The Layer Width The value of these bits add 1 28 5 5 DE Layer Coordinate Control Register Layer 0 0x820 Layer 1 0x824 Register Name DEBE_LAYCOOR_REG Layer 2 0x828 Layer 3 0x82C L
92. Error IRQ Enable 0 Disable 1 Enable 10 RW Ox0 DVFS VOLT CHANGE ERR EN DVFS Voltage Change Error Enable 0 Disable 1 Enable R W 0x0 DVFS_SPD_DET_ERR_IRQ_EN DVFS Speed Detect Error IRQ Enable 0 Disable 1 Enable 8 5 R W 0x0 VOLT_DET_FIN_IRQ_EN Voltage Detect Finished IRQ Enable 0 Disable 1 Enable R W 0x0 DVFS CLK SWT FIN IRQ EN DVFS Clock Switch Operation Finished IRQ Enable 0 Disable 1 Enable RW Ox0 DVFS VOLT CHANGE FIN EN DVFS Voltage Change Finished Enable 0 Disable 1 Enable R W 0x0 DVFS_SPD_DET_FIN_IRQ_EN DVFS Speed Detect Finished IRQ Enable 0 Disable 1 Enable R W 0x0 DVFS_FIN_IRQ_EN DVFS Finished IRQ Enable 0 Disable 1 Enable A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 35 5 3 9 Allwinner Technology PMU IRQ Status Register Offset 0x44 Register Name PMU IRQ STATUS REG Bit Read W rite Default Hex Description 31 13 12 RW Ox0 VOLT DET ERR IRQ PEND Voltage Detect Error IRQ Pending 0 No effect 1 Pending Set one to this bit will clear it 11 RW Ox0 DVFS CLK SWT ERR IRQ PEND DVFS Clock Switch Operation Error IRQ Pending 0 No effect 1 Pending Set one to this bit will clear it 10 RW Ox0 DVFS VOLT CHANGE ERR PEND D
93. FIFO Data Available Trigger Level Interrupt and DMA request trigger level for TP or Auxiliary ADC Trigger Level TXTL 1 R W 0x0 TP_DATA_DRQ_EN TP FIFO Data Available DRQ Enable 0 Disable 1 Enable R W 0x0 TP_FIFO_FLUSH TP FIFO Flush Write 1 to flush TX FIFO self clear to 0 R W 0x0 TP_UP_IRQ_EN Touch Panel Last Touch Stylus Up IRQ Enable 0 Disable 1 Enable R W 0x0 TP DOWN IRQ EN Touch Panel First Touch Stylus Down IRQ Enable 0 Disable 1 Enable A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 263 Allwinner Technology 25 6 6 TP Interrupt amp FIFO Status Register Offset 0x14 Register Name TP_FIFOCS Bit Read W rite Default Hex Description 31 19 18 R W 0x0 17 R W 0x0 FIFO OVERRUN PENDING TP FIFO Over Run IRQ pending 0 No Pending IRQ 1 FIFO Overrun Pending IRQ Write 1 to clear this interrupt or automatic clear if interrupt condition fails 16 R W 0x0 FIFO_DATA_PENDING TP FIFO Data Available pending Bit 0 NO Pending IRQ 1 FIFO Available Pending IRQ Write 1 to clear this interrupt or automatic clear if interrupt condition fails 15 13 12 8 R Ox0 RXA CNT TP FIFO available Sample Word Counter Ox0 TP IDLE FLG Touch Panel Idle Flag 0 idle 1 not idl
94. H 263 MPEG 1 2 4 etc gt Up to 1920x1080 30fps Video Encoding gt Support encoding in H 264 MP format gt Up to 720p 30fps Display Processing Ability Four moveable and size adjustable layers Support multi format image input A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 22 Allwinner Technology Support image enhancement processor Support Alpha blending anti flicker Support Hardware cursor Support output color correction luminance hue saturation etc Display Output Ability Flexible LCD interface CPU Sync RGB Image Input Ability CMOS sensor interface CSI Memory 16 bit SDRAM controller gt Support DDR2 SDRAM and DDR3 SDRAM gt Memory Capacity up to 512MB 8 bit NAND Flash Controller with 2 CE and 2 RB signals gt Support SLC MLC TLC DDR NAND gt 64 bit ECC External Peripherals One USB 2 0 Dual Role Device DRD controller for general application and one USB EHCI OHCI controller for host application Two high speed memory controllers supporting SD version 3 0 and eMMC version 4 3 Four UARTs all with Infrared data Association IrDA Three SPI controllers master slave mode Three Two Wire Interfaces TWI IR controller supporting CIR remoter 6 bit LRADC for line control Internal 4 wire touch panel controller with pressure sensor and 2 point touch Internal 24 bit Audio Codec for 2 Ch headphone and 1 Ch microphone PWM
95. LAY_BRSWAPEN B R channel swap 0 RGB Follow the bit 11 8 RGB 1 BGR Swap the B R channel in the data format LAY_FBPS PS Pixels Sequence See the follow table Pixels Sequence 28 5 15 Pixels Sequence Table DE layer attribute control register1 11 08 FBF frame buffer format DE layer attribute control register1 01 00 PS pixels sequence A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 317 Allwinner Technology Mono or Internal Frame Buffer 1 Bpp Or Palette 1 Bpp Mode FBF 0000 PS 00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P09 P08 P07 P06 P05 P04 P03 P02 P01 POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P24 P25 P26 P27 P28 P29 P30 P31 P16 P17 P18 P19 P20 P21 P22 P23 P08 P09 P10 P11 P12 P13 P14 P15 POO PO1 P02 P03 P04 P05 P06 P07 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 10 Bit
96. Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ72 PRIO IRQ 72 Priority Set priority level for IRQ bit 72 17 16 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ71 PRIO IRQ 71 Priority Set priority level for IRQ bit 71 15 14 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ70_PRIO IRQ 70 Priority 13 12 RW 0x0 Set priority level for IRQ bit 70 Level 0x0 level 0 lowest priority Level 0x1 level 1 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 126 Allwinner Technology Offset 0x90 Register Name INTC SRC PRIO REG4 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ69 PRIO IRQ 69 Priority Set priority level for IRQ bit 69 11 10 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ68_PRIO IRQ 68 Priority Set priority level for IRQ bit 68 9 8 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ67_PRIO IRQ 67 Priority Set priority level for IRQ bit 67 7 6 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3
97. List The direction of SPI pin is different in two work modes Master Mode and Slave Mode Port Name Width Direction M Direction S Description SPI SCLK 1 OUT IN SPI Clock SPI MOSI 1 OUT IN SPI Master Output Slave Input Data Signal SPI MISO 1 IN OUT SPI Master Input Slave Output Data Signal SPI CS 1 0 2 OUT IN SPI Chip Select Signal 18 5 2 SPI Module Clock Source and Frequency The SPI module uses two clock sources AHB CLK and SPI CLK The SPI SCLK can in the range from 3KHz to 100MHz and AHB_CLK gt 2x SPI SCLK Clock Name Description Requirement AHB CLK AHB Bus Clock as the clock source of SPI AHB CLK gt 2xSPI SCLK module SPI CLK SPI Serial Input Clock A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 175 Allwinner Technology 19 UART 19 1 Overview The UART is used for serial communication with a peripheral modem data carrier equipment DCE or data set Data is written from a master CPU over the APB bus to the UART and it is converted to serial form and transmitted to the destination device Serial data is also received by the UART and stored for the master CPU to read back The UART contains registers to control the character length baud rate parity generation checking and interrupt generation Although there is only one interrupt output signal from the UART there are several prioritized interru
98. P2 P1 PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ffset Offset DE on chip SRAM block 0x4000 0x57FF Bit Read Wr Default ite Hex Internal frame buffer pixel pattern 31 00 R W UDF f f Specify the color displayed for each of the internal frame buffer pixels 28 5 41 Address Pipe0 0x5000 0x53FF Pipe1 0x5400 0x57FF Read Wr Default ite Hex Internal Frame Buffer Mode Palette Table Pipe palette table A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 331 Allwinner Technology 15 08 Green value EE The SE figure shows the RAM array used for internal frame buffer mode and the corresponding colors output Output color On chip SRAM array 2bpp mode oi R2 G2 B2 Internal frame buffer bit7 bit0 av RO Go BO Palette table 3 2 0 2 a2 R2 G2 B2 Color0 ao RO GO BO a3 R3 G3 B3 Color1 al RI G1 B1 a2 R2 G2 B2 1 3 2 2 oi R2 Go B 3 3 0 1 a3 R3 G3 B3 Color254 254 R254 G254 B254 oi Ri o BI Color255 255 R255 G255 B255 On chip SRAM for internal an RI 1 B1 frame buffer ao RO GO BO a3 R3 G3 B3 a3 R3 G3 B3 28 5 42 Gamma Correction Mode Offset 0x4400 0x47FF DE on chip SRAM block Read Wr Default Bit i Description ite Hex 31 24 RW UDF as Inn Alpha channel intensity 23 16 R W UDF jects Inn Red channel intensity 15 08 RW
99. Priority Set priority level for IRQ bit 17 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 1 0 R W 0x0 IRQ16_PRIO IRQ 16 Priority Set priority level for IRQ bit 16 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 13 4 28 Interrupt Source Priority 2 Register Default 0x00000000 Offset 0x88 Register Name INTC_SRC_PRIO_REG2 Read W Default DE Bit Description rite Hex 31 30 R W 0x0 IRQ47 PRIO A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 119 Allwinner Technology Offset 0x88 Register Name INTC SRC PRIO REG2 IRQ 47 Priority Set priority level for IRQ bit 47 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ46_PRIO IRQ 46 Priority Set priority level for IRQ bit 46 29 28 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ45_PRIO IRQ 45 Priority Set priority level for IRQ bit 45 27 26 RW 0x0 Level 0x0 level 0 lowest priority Leveli 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ44_PRIO IRQ 44 Priority Set priority level for IRQ bit 44 25 24 RW 0x0 Le
100. R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 29 IR Clock Default 0x00000000 Offset OxBO Register Name IR SCLK CFG REG Read W Default Bit Description rite Hex SCLK_GATING Gating Special Clock Max Clock 100MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 00 OSC24M 25 24 RW 0x0 01 PLL6 10 PLL5 11 23 18 CLK DIV RATIO 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 The divider is 1 2 4 8 15 4 CLK DIV RATIO M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 30 USB Clock Default 0x00000000 Offset OxCC Register Name USBPHY_CFG_REG Read W Default SC Bit Description rite Hex 31 10 USBPHY1_CLK_GATING Gating Special Clock for USB PHY1 S Ge 0 Clock is OFF 1 Clock is ON A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 70 Allwinner Technology USBPHYO_CLK GATING Gating Special Clock for USB PHYO RAW 90 9 Clock is OFF 1 Clock is ON 7 OHCI SCLK GATING Gating Special Clock for OHCI i D M RTL ilo Gieek is OFF 1 Clock is ON 5 4 3 2
101. R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ80 PRIO IRQ 80 Priority Set priority level for IRQ bit 80 1 0 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 130 Allwinner Technology 14 DMA 14 1 Overview There are two kinds of DMA in the chip One is Normal DMA NDMA with 8 channels and the other is Dedicated DMA DDMA with 8 channels For NDMA only one channel can be active and the sequence is in accordance with the priority level For DDMA at most 8 channels can be active at the same time if their source or destination does not conflict 14 2 DMA Description DMA can support 8 bit 16 bit 32 bit data width The data width of Source and Destination can be different but the address should be aligned 14 3 DMA Register List Module Name Base Address DMA 0x01C02000 Register Name Offset Description DMA IRQ EN REG 0x0000 DMA IRQ Enable DMA IRQ PEND STAS REG 0x0004 DMA IRQ Pending Status N I DMA fi i NDMA_CTRL_REG 0x100 N 0x20 E SA CANON N 0 1 2 3 4 5 6 7 NDMA SRC ADDR REG 0x100 N 0x20 4 Normal DMA Source Address NDMA DEST ADDR REG 0x100 N 0x20 8 Normal DMA Destination Address NDMA_BC_REG 0
102. Register Offset 0x54 Register Name PORTSC A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 210 Allwinner Technology Default Value 0x00002000 w PPC set to one 0x00003000 w PPC set to a zero Bit Read Write Default Description Reserved These bits are reserved for future use and should return a value of 31 22 0 zero when read Wake on Disconnect Enable WKDSCNNT EI Writing this bit to a one enables the port to be sensitive to device disconnects as wake up events This field is zero if Port Power is zero 21 R W 0 The default value in this field is 0 Wake on Connect Enable WKCNNT E Writing this bit to a one enable the port to be sensitive to device connects as wake up events This field is zero if Port Power is zero 20 R W 0 The default value in this field is 0 Port Test Control The value in this field specifies the test mode of the port The encoding of the test mode bits are as follow Bits Test Mode 0000b The port is NOT operating in a test mode 0001b Test J STATE 0010b Test K_STATE 0011b Test SEO NAK 0100b Test Packet 0101b Test FORCE ENABLE 0110b 1111b Reserved 19 16 R W 0 The default value in this field is O000b Reserved These bits are reserved for future use and should return a value of 15 14 RM 0 zero when read Port Owner This bit unconditio
103. Register Offset 0x18 Register Name SYNC TMRO INTV HI REG Bit Read W rite Default Hex Description 31 24 23 0 R W X STMRO INTV VALUE HI Sync Timer 0 Interval Value 55 32 Note the interval value register is a 56 bit register When read or write the interval value the Low register should be read or write first And the High register should be written after the Low register 12 3 6 Sync Timer 0 Current Value Lo Register Offset 0x1C Register Name SYNC TMRO CURNT LOW REG Read W Default EE Bit Description rite Hex 31 0 RW i SIMRO CUR_VALUE_LOW Sync Timer 0 Current Value 31 0 12 3 7 Sync Timer 0 Current Value Hi Register Offset 0x20 Register Name SYNC_TMRO_CURNT_HI_REG f Read W Default ae Bit i Description rite Hex A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 102 Allwinner Technology 31 24 STMRO CUR VALUE HI 23 0 R W Sync Timer 0 Current Value 55 32 Note 1 Timer 0 current value is a 56 bit down counter from interval value to 0 2 The current value register is a 56 bit register When read or write the current value the Low register should be read or write first 12 3 8 Sync Timer 1 Control Register Default 0x00000004 Offset 0x30 Register Name SYNC TMR1 CTRL REG Bit Re
104. TD length is 16 bytes the memory structure for the TD must be aligned to a 16 byte boundary So the lower bits in the PCED through bit 0 to bit 3 must be zero in this field 22 6 9 HcControlHeadED Register Offset 0x420 Register Name HcControlHeadED CHED Default Value 0x0 Bit Read Write HCD HC Default Description 31 4 RW Ox0 EHCD 31 4 The HcControlHeadED register contains the physical address of the first Endpoint Descriptor of the Control list HC traverse the Control list starting with the HcControlHeadED pointer The content is loaded from HCCA during the initialization of HC 3 0 R R 0x0 EHCD 3 0 Because the general TD length is 16 bytes the memory structure for the TD must be aligned to a 16 byte boundary So the lower bits in the PCED through bit 0 to bit 3 must be zero in this field 22 6 10 HcControlCurrentED Register Offset 0x424 Register Name HcControlCurrentED CCED Default Value 0x0 Bit Read Write HCD HC Default Description 31 4 R W R W 0x0 CCED 31 4 The pointer is advanced to the next ED after serving the present one HC will continue processing the list from where it left off in the last Frame When it reaches the end of the Control list HC checks the ControlListFilled of in HcCommandStatus If set it copies the content of HcControlHeadED to HcControlCurrentED and clears the bit If
105. TMR1 CURNT VALUE REG 0x0028 Timer 1 Current Value ASYNC TMR2 CTRL REG 0x0030 Timer 2 Control ASYNG TMR2 INTV VALUE REG 0x0034 Timer 2 Interval Value ASYNG TMR2 CURNT VALUE REG 0x0038 Timer 2 Current Value ASYNGC TMR3 CTRL REG 0x0040 Timer 3 Control ASYNGC TMR3 INTV VALUE REG 0x0044 Timer 3 Interval Value ASYNGC TMR4 CTRL REG 0x0050 Timer 4 Control ASYNG TMR4 INTV VALUE REG 0x0054 Timer 4 Interval Value ASYNG TMR4 CURNT VALUE REG 0x0058 Timer 4 Current Value ASYNG TMR5 CTRL REG 0x0060 Timer 5 Control ASYNGC TMR5 INTV VALUE REG 0x0064 Timer 5 Interval Value ASYNG TMR5 CURNT VALUE REG 0x0068 Timer 5 Current Value A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 85 Allwinner Technology AVS CNT CTL REG 0x0080 AVS Control Register AVS CNTO REG 0x0084 AVS Counter 0 Register AVS CNT1 REG 0x0088 AVS Counter 1 Register AVS CNT DIVISOR REG 0x008C AVS Divisor WDOG CTRL REG 0x0090 Watchdog Control WDOG MODE REG 0x0094 Watchdog Mode COUNTER64 CTRL REG 0x00A0 64 bit Counter control COUNTER64_LOW_REG 0x00A4 64 bit Counter low COUNTER64_HI_REG 0x00A8 64 bit Counter high CPU_CFG_REG 0x0140 CPU configuration register 11 3 ASYNC Timer Register Description 11 3 1 ASYNC Timer IRQ Enable Register Default 0x00000000 Offset 0x00 Register Name ASYNC_TMR_IRQ_EN_ REG Bit EE EEN Description rite Hex 31 9 WDOG INT EN 8 R
106. TS CLK 011 CSI PCLK 100 SPI2_CSO 101 110 EINT14 111 33 4 29 PE Configure Register 1 Register Name PE_CFG1 Offset 0x94 Default Value 0x0000 0000 Bit Read Write Default Description 31 16 15 PE11 Select 000 Input 001 Output 010 TS D7 011 CSI D7 100 UART1 RX 101 14 12 R W 0 110 111 11 PE10 Select 000 Input 001 Output 010 TS_D6 011 CSI D 100 UART1 TX 101 10 8 R W 0 110 111 7 PE9 Select 000 Input 001 Output 010 TS_D5 011 CSI_D5 100 SDC2_CLK 101 6 4 R W 0 110 111 3 PE8 Select 000 Input 001 Output 010 TS D4 011 CSI D4 100 SDC2 CMD 101 2 0 R W 0 110 111 33 4 30 PE Configure Register 2 Register Name PE CFG2 Offset 0x98 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 31 PE Configure Register 3 Offset 0x90C Register Name PE CFG3 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 382 Allwinner Technology Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 32 PE Data Register Register Name PE DAT Offset OxA0 Default Value 0x0000 0000 Bit Read Write Default Description 31 12 If the port is configured as input the corresponding bit is the pin state If the port is conf
107. VE 0 mask 1 pass 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock is PLL4 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 74 Allwinner Technology 25 24 30 20 19 16 15 1 VE_RST 0 R W 0x0 VE Reset 0 reset valid 1 reset invalid 6 4 37 Audio Codec Clock Default 0x00000000 Offset 0x140 Register Name AUDIO_CODEC_SCLK_CFG_REG Read W Default Ee Bit i Description rite Hex SCLK GATING Gating Special Clock 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock PLL2 output 30 0 6 4 38 AVS Clock Default 0x00000000 Offset 0x144 Register Name AVS_SCLK_CFG_REG Bit near ES Description rite Hex SCLK GATING Gating Special Clock 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock OSC24M 30 0 6 4 39 Mali 400 Clock Register Default 0x00000000 Offset 0x154 Register Name MALI CLOCK CFG REG Read W Default a Bit Description rite Hex SCLK_GATING Gating Special Clock Max Clock 381MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M MALI400_RST 30 R W 0x0 Mali400 Reset 0 reset valid 1 reset invalid 29 27 26 24 RW 0x0 CLK_SRC_SEL A13 User Manual V1 3 Copyright 2013 Allwinner Technology All R
108. W Bit rite Default Hex Description 31 30 RW Ox0 IRQ15 PRIO IRQ 15 Priority Set priority level for IRQ bit 15 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 29 28 RW Ox0 IRQ14 PRIO IRQ 14 Priority Set priority level for IRQ bit 14 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 27 26 RW Ox0 IRQ13_PRIO IRQ 13 Priority A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 114 Allwinner Technology Offset 0x80 Register Name INTC SRC PRIO REGO Set priority level for IRQ bit 13 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x2 level 2 Level 0x3 level 3 highest priority IRQ12_PRIO IRQ 12 Priority Set priority level for IRQ bit 12 25 24 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x2 level 2 Level3 0x3 level 3 highest priority IRQ11 PRIO IRQ 11 Priority Set priority level for IRQ bit 11 23 22 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x2 level 2 Level 0x3 level 3 highest priority IRQ10 PRIO IRQ 10 Priority Set priority level for IRQ bit 10 21 20 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x2 level 2 Le
109. and Y switches for the Z1 and Z2 measurements and store the results in the Z1 and Z2 result registers The touch resistance RTOUCH can then be calculated using the following equation Rroucx Rxptate x Xposition 4096 x Z2 Z1 1 1 MEASURE MEASURE X POSITION Z1 POSITION A Y 1 D X oO Q x r a ka TOUCH gt i H i TOUCH H CI Sp ziposition OS T VE P STTION Nay kar Z2 POSITION 3 3 3 O X Y X QY 4 MEAS RE Z2 POSITION Figure25 12 Pressure Measurement Block Diagram Second Method The second method requires the user to know the resistance of the X plate and Y plate tablets Three touch screen conversions are required a measurement of the X position Xposition the Y position Yposition and the Z1 position The following equation also calculates the touch resistance Rroucu Rrouc RxpLaTe x Xposition 4096 x 4096 21 1 Rypuate 1 Yrosition 4096 2 25 4 7 Pen Down Detection with Programmable Sensitivity Pen down detection is used as an interrupt to the host Rira is an internal pull up resistor with a programmable value of 6 96 kQ default 48kQ The PENIRQ output is pulled high by an internal pull up the Y driver is on and connected to GND and the PENIRQ output is connected to the X input When the panel is touched the X input is pulled to ground through the touch screen and the PENIRQ output goes low because of the curren
110. at odd lines of the panel line 1 3 5 7 00 R G B 01 B gt R G 10 G B R 11 R gt G B 25 24 RW RGB888 SM1 Serial RGB888 mode Output sequence at even lines of the panel line 2 4 6 8 00 R gt G B 01 B gt R G 10 G B R 11 R gt G B 23 22 R W YUV_SM serial YUV mode Output sequence 2 pixel pair of every scan line 00 YUYV 01 YVYU 10 UYVY 11 VYUY 21 20 R W YUV EAV SAV F line delay 0 F toggle right after active video line 1 delay 2 line CCIR NTSC 2 delay 3 line CCIR PAL 3 reserved A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 341 Allwinner Technology 19 0 29 3 14 TCONO CPU IF REG Offset 0x060 Register Name TCONO cpu panel interface register Bit Read W rite Default Hex Description 31 29 R W CPU_MOD 000 18bit 256K mode 001 16bit mode 010 16bit mode1 011 16bit mode2 100 16bit mode3 101 9bit mode 110 8bit 256K mode 111 8bit 65K mode 28 R W AUTO auto Transfer Mode If it s 1 all valid data during this frame is written to panel Note This bit is sampled by Vsync 27 R W FLUSH direct transfer mode If it s enabled FIFO1 is irrelevant to the HV timing and pixels data keeps being transferred unless the input FIFO is empty Data output rate control by DCLK 26 R W DA pin A1 value in 8080 mode auto fla
111. attached 15 10 r Lo Reserved read LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port When set a Low Speed device is attached to this port When cleared a Full Speed device is attached to this port This field is valid only when the CurrentConnectStatus is set 0 full speed device attached 1 low speed device attached write ClearPortPower The HCD clears the PortPowerStatus bit by writing a 1 to this bit 9 RW RW Writing a 0 has no effect read PortPowerStatus This bit reflects the port s power status irrelevant of the type of power switching implemented This bit is cleared if an overcurrent condition is detected HCD sets this bit by writing SetPortPower or SetGlobalPower HCD clears this bit by writing ClearPortPower or ClearGlobalPower Which power control switches are enabled is determined by PowerSwitchingMode and PortPortControlMask NumberDownstreamPort In global switching mode PowerSwitchingMode 0 only 8 RW RW Ox1 Set ClearGlobalPower controls A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 230 Allwinner Technology this bit In per port power switching PowerSwitchingMode 1 if the PortPowerControlMask NDP bit for the port is set only Set ClearPortPower commands are enabled If the mask is not set only Set ClearGlobalPower commands are enabled When port
112. bit The host controller may hold Port A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 212 Allwinner Technology Reset asserted to a one when the HC Halted bit is a one This field is zero if Port Power is zero Suspend Port Enabled Bit and Suspend bit of this register define the port states as follows Bits Port Enables Port State Suspend Ox Disable 10 Enable 11 Suspend When in suspend state downstream propagation of data is blocked on this port except for port reset The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1 In the suspend state the port is sensitive to resume detection Not that the bit status does not change until the port is suspend and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB A write of zero to this bit is ignored by the host controller The host controller will unconditionally set this bit to a zero when Software sets the Force Port Resume bit to a zero from a one Software sets the Port Reset bit to a one from a zero If host software sets this bit to a one when the port is not enabled i e Port enabled bit is a zero the results are undefined This field is zero if Port Power is zero The default value in this field is 0 Force Port Resume 1 Resume detected driven on port
113. ener artery er arene ye ar veneer Merrery 357 30 2 23 DRC Intensity COemiCient lt c ccs ER RE AE ee 357 30224 DRC Luminance Gain Coefficient entres Ra 357 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 18 Allwinner Technology 91 Security SYSLOM EN 358 S EE EE are ery PE a PRE ree Tearyn 358 31 2 Security System Block DATA SR SN 358 31 3 Security System Register ASE accede lee eee 358 314 Security System Register Description aie ee ee dd 359 31 4 1 Security System Control Registered 359 31 4 2 Security System Key In Register msmmiriniieiinamiihuabevbumbvktketnbnddkatndatnknknn 360 31 4 3 Security System MAJ Register seatecccdcnddnnadanssencccendans nandansibanctendteastenctaantandsendsunddaniiate 360 31 4 4 Security System FIFO Control Status Register 361 31 4 5 Security System Interrupt Control Status Register 361 31 4 6 Security System Message Digest n Register 362 31 4 7 Security System RX FIFO Register eege 362 31 4 8 Security System TX FIFO Register sn nn An an ee eek at 362 31 5 Security System Clock Requirement ss 362 32 S c rity ID DEE 364 EE ee 364 32 2 SEN ID Register List daesenendn 364 32 3 Security ID Register DESenplon iaannmemiannennnnikeiteinenietnijenhenlvnim tin tient 364 32 3 1 SID Root Key e 364 32 3 2 SID R st Key 1 REJSE aa 364 32 3 3 SID Root Key 2 Register usann kakene 364 32 3 4 SID Root K
114. finds a TD on the list then HC will set ControlListFilled to 1 causing the Control list processing to continue If no TD is found on the Control list and if the HCD does not set ControlListFilled then ControlListFilled will still be 0 when HC completes processing the Control list and Control list processing will stop Technology 15 4 0x0 3 RW RW oxo 2 RW RW oxo 1 RW RW oxo 0 RW R E oxo HostControllerReset This bit is by HCD to initiate a software reset of HC Regardless of the functional state of HC it moves to the USBSuspend state in which most of the operational registers are reset except those stated otherwise e g the InteruptRouting field of HcControl and no Host bus accesses are allowed This bit is cleared by HC upon the completion of the reset operation The reset operation must be completed within 10 ms This bit when set should not cause a reset to the Root Hub and no subsequent reset signaling should be asserted to its downstream ports 22 6 4 HcinterruptStatus Register Offset 0x40c Register Name HcinterruptStatus A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 218 Allwinner Technology Default Value 0x00 Read Write Bit HCD HC Default Description 31 7 0x0 Reserved RootHubStatusChange 0x0 This bit is set when the content of HcRhStatus or the content of 6 RW RW 0x
115. integer mode The PLL7 output 3MHz M In the fractional mode the PLL7 output is select by bit 14 The PLL7 output range is 27MHz 381 MHz 30 16 PLL7_MODE_SEL 15 R W 0x1 PLL7 mode select 0 fractional mode 1 integer mode PLL7_FRAC_SET 14 R W 0x1 PLL7 fractional setting 0 270MHz 1 297MHz 13 7 PLL7_FACTOR_M 6 0 R W 0x63 PLL7 Factor M The range is from 9 to 127 6 4 11 PLL1 Tuning2 Default 0x00000000 Offset 0x38 Register Name PLL1 TUNG REG Read W Default or Bit Description rite Hex SIG_DELT_PAT_EN 31 R W 0x0 Sigma delta pattern enable SPR_FREQ_MODE Spread Frequency Mode 00 DC 0 30 29 RW 0x0 01 DC 1 10 Triangular 11 awmode WAVE STEP 28 20 RW 0x0 Wave step 19 FREQ 18 17 RW 0x0 Frequency A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 59 Allwinner Technology 00 31 5KHz 01 32KHz 10 32 5KHz 11 33KHz 16 0 R W 0x0 we poe Wave Bottom 6 4 12 PLL5 Tuning2 Default 0x00000000 Offset Ox3C Register Name PLL5 TUN2 REG Read W Default Bit i Description rite Hex SIG_DELT_PAT_EN 31 R W 0x0 Sigma delta pattern enable SPR_FREQ_MODE Spread Frequency Mode 00 DC 0 30 29 RW 0x0 01 DC 1 10 Triangular 11 awmode WAVE STEP 28 20 RW 0x0 Wave step 19 FREQ Frequency 00 31 5KHz 18 17 RW 0x0 01 3
116. is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note Time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 11 3 10 ASYNC Timer 2 Interval Value Register Offset 0x34 Register Name ASYNG TMR2 INTV VALUE REG f Read W Default SS Bit Description rite Hex 31 0 RW TMR2_INTV_VALUE Timer 2 Interval Value Note The value setting should consider the system clock and the timer clock source 11 3 11 ASYNC Timer 2 Current Value Register Offset 0x38 Register Name ASYNC TMR2 CURNT VALUE REG Read W Default EE Bit Description rite Hex TMR2 CUR VALUE 1 R 7 SE d i Timer 2 Current Value Note Timer current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale 11 3 12 ASYNC Timer 3 Control Register Default 0x00000000 Offset 0x40 Register Name ASYNC_TMR3_CTRL_REG Bit Read W Default Description A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 91 Allwinner Technology rite Hex 31 8 RW Ox0 TMR3 CLK SRC Timer 3 Cl
117. not set it does nothing HCD is allowed to modify this register only when the ControlListEnable of HcControl is cleared When set HCD only reads the instantaneous value of this register Initially this is set to zero to indicate the end of the Control list 3 0 0x0 CCED 3 0 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 222 Allwinner Technology Because the general TD length is 16 bytes the memory structure for the TD must be aligned to a 16 byte boundary So the lower bits in the PCED bit 0 to bit 3 must be zero in this field 22 6 11 HcBulkHeadED Register Offset 0x428 Register Name HcBulkHeadED BHED Default Value 0x0 Read Write Bit HCD HC Default Description BHED 31 4 The HcBulkHeadED register contains the physical address of the first Endpoint Descriptor of the Bulk list HC traverses the Bulk list starting with the HcBulkHeadED pointer The content is loaded 31 4 RW R 0x0 from HCCA during the initialization of HC BHEDJ3 0 Because the general TD length is 16 bytes the memory structure for the TD must be aligned to a 16 byte boundary So the lower bits 3 0 R R 0x0 in the PCED bit 0 to bit 3 must be zero in this field 22 6 12 HcBulkCurrentED Register Offset 0x42c Register Name HcBulkCurrentED BCED Default Value 0x00 Bit Read Write HCD HC Defaul
118. refer to relative Specifications listed below Physical Layer Specification Ver3 00 Final 2009 04 16 SDIO Specification Ver2 00 Consumer Electronics Advanced Transport Architecture CE ATA version 1 1 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 153 Allwinner Technology Multimedia Cards MMC version 4 2 JEDEC Standard JESD84 44 Embedded Multimedia Card eMMC Card Product Standard A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 154 Allwinner Technology 17 Two Wire Interface 17 1 Overview This Two Wire Interface TWI controller is an interface between CPU host and the serial 2 Wire bus which supports all standard 2 Wire transfer including Slave and Master The communication to the 2 Wire bus is carried out on byte wise basis using interrupt or polled handshaking This 2 Wire Controller can be operated in standard mode 100K bps or fast mode up to 400K bps Multiple Masters and 10 bit addressing Mode are supported for this specified application General Call Addressing is supported in Slave mode The 2 Wire Controller features Software programmable for Slave or Master Support Repeated START signal Support Multi master systems Support 10 bit addressing with 2 Wire bus Perform arbitration and clock synchronization Own address and General Call address detection Interrupt on address detection Support sp
119. set by hardware when a change has occurred to the OverCurrentindicator field of this register The HCD clears this bit 17 RW R 0 by writing a 1 Writing a 0 has no effect read LocalPowerStartusChange The Root Hub does not support the local power status features thus this bit is always read as 0 write SetGlobalPower In global power mode PowerSwitchingMode 0 this bit is written to 1 to turn on power to all ports clear PortPowerStatus In per port power mode it sets PortPowerStatus only on ports whose 16 RW IR 0x0 PortPowerControlMask bit is not set Writing a 0 has no effect read DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt 0 ConnectStatusChange is not a remote wakeup event 1 ConnectStatusChange is a remote wakeup event write SetRemoteWakeupEnable 15 RW R 0x0 Writing a 1 sets DeviceRemoveWakeupEnable Writing a 0 has A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 228 Allwinner Technology no effect 14 2 Reserved OverCurrentindicator This bit reports overcurrent conditions when the global reporting is implemented When set an overcurrent condition exists When cleared all power operations are normal If per port overcurrent protection is implemented this bit is always 1 R R W 0
120. the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index Values mean Bits Meaning 00b 1024 elements 4096bytes Default value 01b 512 elements 2048byts 10b 256 elements 1024bytes For resource constrained condition 11b reserved 3 2 R W or R 0 The default value is 00b Host Controller Reset This control bit is used by software to reset the host controller The effects of this on Root Hub registers are similar to a Chip Hardware Reset When software writes a one to this bit the Host Controller resets its internal pipelines timers counters state machines etc to their initial value Any transaction currently in progress on USB is immediately terminated A USB reset is not driven on downstream ports 1 R W 0 All operational registers including port registers and port state A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 205 Allwinner Technology machines are set to their initial values Port ownership reverts to the companion host controller s Software must reinitialize the host controller as described in Section 4 1 of the CHEI Specification in order to return the host controller to an operational state This bit is set to zero by the Host Controller when the reset process is complete Software cannot terminate the reset process early by writing a zero to this register Software should not set this bit to a one when the
121. to 0x3 and is W R Otherwise it defaults to zero and is R It contains a count of the number of successive transactions the host controller is allowed to execute from a high speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule Valid value are 0x1 to 0x3 Software must not write a zero to this bit when Park Mode Enable is a one as it will result in undefined behavior Light Host Controller Reset OPTIONAL This control bit is not required If implemented it allows the driver to reset the EHCI controller without affecting the state of the ports or relationship to the companion host controllers For example the PORSTC registers should not be reset to their default values and the CF bit setting should not go to zero retaining port ownership relationships A host software read of this bit as zero indicates the Light Host Controller Reset has completed and it si safe for software to re initialize the host controller A host software read of this bit as a one indicates the Light Host Technology 10 0 9 8 R W or R 0 7 RW 0 6 R W 0 Interrupt on Async Advance Doorbell This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule Soft Ware must write a 1 to this bit to ring the doorbell When the host controller has evicted all appropriate cached schedule state it sets the Interrupt on Async
122. wire I F Dual touch detect Touch pressure measurement Support program set threshold Sampling frequency 2MHz max Single ended conversion of touch screen inputs and ratiometric conversion of touch screen inputs TACQ up to 262ms Median and averaging filter to reduce noise Pen down detection with programmable sensitivity Support X Y change 25 2 Typical Application Circuit X MN MA AA Figure 25 1 TP Typical Application Circuit A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 252 Allwinner Technology 25 3 Clock Tree and ADC Time 25 3 1 Clock Tree PRESCALER 00 2 HOSC24M 01 3 10 6 11 1 CLK IN AUDIO PLL Figure 25 2 TP Clock Tree 25 3 2 A D Convertion Time When the clock source is 24MHz and the prescaler value is 6 total 12 bit conversion time is CLK IN 24MHz 6 4MHz Conversion Time 1 4MHz 13Cycles 3 25us Touch acquire time divider is 16 TACQ 16 16 1 4us 64us FS_TIME Based on TACQ and Touch Mode When touch is in dual and pressure measurement mode TACQ is the FS_TIME must be no less than 6 TACQ Conversion Time FS_TIME gt M TACQ Conversion Time Conversion Time DATA GV 1 DATA DAT GY2 DATA Lg ZI DATA gg Z2 DATA Wax FS TIME p g
123. 0 IRQ93_PRIO IRQ 93 Priority Set priority level for IRQ bit 93 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 25 24 R W 0x0 IRQ92_PRIO IRQ 92 Priority Set priority level for IRQ bit 92 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 23 22 R W 0x0 IRQ91 PRIO IRQ 91 Priority Set priority level for IRQ bit 91 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 21 20 R W 0x0 IRQ90_PRIO IRQ 90 Priority A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 128 Allwinner Technology Offset 0x94 Register Name INTC SRC PRIO REG5 Set priority level for IRQ bit 90 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ89 PRIO IRQ 89 Priority Set priority level for IRQ bit 89 19 18 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ88_PRIO IRQ 88 Priority Set priority level for IRQ bit 88 17 16 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ87_RPIO IRQ 87
124. 0 11 RAV 0x0 10 Pull down 11 Reserved 33 4 28 PE Configure Register 0 Register Name PE CFGO Offset 0x90 Default Value 0x0000 0000 Bit Read Write Default Description 31 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 380 Allwinner Technology PE7 Select 000 Input 001 Output 010 TS D3 011 CSI D3 100 SDC2 D3 101 30 28 R W 0 110 111 27 PE6 Select 000 Input 001 Output 010 TS D2 011 CSI D2 100 SDC2 D2 101 26 24 R W 0 110 111 23 PE5 Select 000 Input 001 Output 010 TS_D1 011 CSI Di 100 SDC2 Di 101 22 20 R W 0 110 111 19 PE4 Select 000 Input 001 Output 010 TS DO 011 CSI DO 100 SDC2 DO 101 18 16 R W 0 110 111 15 PE3 Select 000 Input 001 Output 010 TS_DVLD 011 CSI_VSYNC 100 SPI2_MISO 101 14 12 R W 0 110 111 11 PE2 Select 000 Input 001 Reserved 010 TS_SYNC 011 CSI_HSYNC 100 SPI2 MOSI 101 10 8 R W 0 110 111 7 PE1 Select 000 Input 001 Reserved 010 TS_ERR 011 CSI MCLK 100 SPI2 CLK 101 6 4 R W 0 110 EINT15 111 3 4 2 0 R W 0 PEO Select A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 381 Allwinner Technology 000 Input 001 Reserved 010
125. 0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POO P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Mono 4 bpp or palette 4 bpp mode FBF 0010 PS 00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P07 P06 P05 P04 P03 P02 PO1 POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P06 P07 P04 P05 P02 P03 POO PO1 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 0 PS 10 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PO1 POO P03 P02 P05 P04 P07 P06 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POO PO1 P02 P03 P04 P05 P06 P07 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Mono 8 bpp mode or palette 8 bpp mode FBF 0011 PS 00 11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P3 P2 P1 PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 01 10 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 319 Allwinner Technology Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PO P1 P2 P3 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Color 16 bpp mode FBF 0100 or 0101 or 0110 or 0111 or 1000 PS 00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P1 PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 01 Bit 31 30 29 28 27 26 25 24 23
126. 00 Offset OxA8 Register Name COUNTER64 HI REG Read W Default Bit Description rite Hex 31 0 R W 0x0 CONT64_HI A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 98 Allwinner Technology 64 bit Counter 63 32 11 3 28 64 bit Counter Control Register Default 0x00000000 Offset OxAO Register Name COUNTER64 CTRL REG Read W Bit N rite Default Hex Description 31 3 2 RW Ox0 CONT64 CLK SRC SEL 64 bit Counter Clock Source Select 0 OSC24M 1 PLL6 6 Ox0 CONT64 RLATCH EN 64 bit Counter Read Latch Enable 0 no effect 1 to latch the 64 bit Counter to the Low Hi registers and it will change to zero after the registers are latched Ox0 CONT64 CLR EN 64 bit Counter Clear Enable 0 no effect 1 to clear the 64 bit Counter Low Hi registers and it will change to zero after the registers are cleared 11 3 29 CPU Config Register Default 0x00000000 Offset 0x13C Register Name CPU CFG REG Read W Bit rite Default Hex Description 31 2 0x0 L1_INVALID_RST_EN Enable L1 data cache invalidation at reset For L1 data cache the cycles are up to 512 CPU clock cycles 0 enable 1 disable 0x0 L2_INVALID_RST_EN Enable L2 data cache invalidation at reset For L1 data cache the cycle
127. 00 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 389 Bit Allwinner Technology Read Write Default Description 4i 3 4 i 0 7 R W External INTn Mode n 16 23 0x0 Positive Edge 0x1 Negative Edge 0x2 High Level 0x3 Low Level 0x4 Double Edge Positive Negative Others Reserved 33 4 58 PIO Interrupt Configure Register 3 Offset 0x20C Register Name PIO INT CFG3 Default Value 0x0000 0000 Bit Read Write Default Description 4i 3 4 i 0 7 RW External INTn Mode n 24 31 0x0 Positive Edge 0x1 Negative Edge 0x2 High Level 0x3 Low Level 0x4 Double Edge Positive Negative Others Reserved 33 4 59 PIO Interrupt Control Register Offset 0x210 Register Name PIO_INT_CTL Default Value 0x0000 0000 Bit Read Write Default Description External INTn Enable n 0 31 n 0 Disable n 0 31 RAW 0 1 Enable 33 4 60 PIO Interrupt Status Register Offset 0x214 Register Name PIO_INT_STATUS Default Value 0x0000 0000 Bit Read Write Default Description External INTn Pending Bit n 0 31 0 No IRQ pending n 1 IRQ pending n 0 31 RW 0 Write 1 to clear 33 4 61 PIO Interrupt Debounce Register Offset 0x218 Register Name PIO_INT_DEB Default Value 0x0000 0000 Bit Read Wr
128. 00 0x01C0 3FFF 4K 0x01C0 4000 0x01C0 4FFF 4K A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved Allwinner Technology SPI 0 0x01C0 5000 0x01C0 5FFF 4K SPI 1 0x01C0 6000 0x01C0 6FFF 4K 0x01C0 7000 0x01C0 7FFF 4K 0x01C0 8000 0x01C0 8FFF 4K CSI 0x01C0 9000 0x01C0 9FFF 4K 0x01C0 A000 0x01C0 AFFF EMAC 0x01C0 B000 0x01C0 BFFF LCD 0x01C0 C000 0x01C0 CFFF 4K 0x01C0 D000 0x01C0 DFFF 4K VE 0x01C0 E000 0x01C0 EFFF 4K SD MMC 0 0x01C0 FO00 0x01C0 FFFF 4K SD MMC 1 0x01C1 0000 0x01C1 OFFF 4K SD MMC 2 0x01C1 1000 0x01C1 1FFF 4K 0x01C1 2000 0x01C1 2FFF 4K USB DRD 0x01C1 3000 0x01C1 3FFF 4K USB HCI 0x01C1 4000 0x01C1 4FFF 4K SS 0x01C1 5000 0x01C1 5FFF 4K 0x01C1 6000 0x01C1 6FFF SPI 2 0x01C1 7000 0x01C1 7FFF 4K 0x01C1 8000 0x01C1 8FFF 4K 0x01C1 9000 0x01C1 9FFF 4K 0x01C1 A000 0x01C1 AFFF 4K 0x01C1 B000 0x01C1 BFFF 4K 0x01C1 C000 0x01C1 CFFF 4K 0x01C1 D000 0x01C1 DFFF 4K 0x01C1 E000 0x01C1 EFFF 4K 0x01C1 FO00 0x01C1 FFFF 4K CCM 0x01C2 0000 0x01C2 03FF 1K INTC 0x01C2 0400 0x01C2 07FF 1K PIO 0x01C2 0800 0x01C2 OBFF 1K Timer 0x01C2 0C00 0x01C2 OFFF 1K 0x01C2 1000 0x01C2 13FF 1K 0x01C2 1400 0x01C2 17FF 1K IR 0x01C2 1800 0x01C2 1BFF 1K 0x01C2 1C00 0x01C2 1FFF 1K
129. 000 0000 Bit Read Write Default Description 31 8 Scratch Register This register is used by programmers as a temporary storage 7 0 R W 0 space It has no defined purpose in the UART 19 4 13 UART Status Register Offset Ox7C Register Name UART_USR Default Value 0x0000 0006 Bit Read Write Default Description 31 5 RFF Receive FIFO Full This is used to indicate that the receive FIFO is completely full 0 Receive FIFO not full 1 Receive FIFO Full This bit is cleared when the RX FIFO is no longer full RFNE Receive FIFO Not Empty This is used to indicate that the receive FIFO contains one or more entries 0 Receive FIFO is empty 1 Receive FIFO is not empty This bit is cleared when the RX FIFO is empty TFE Transmit FIFO Empty This is used to indicate that the transmit FIFO is completely empty 0 Transmit FIFO is not empty 1 Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty TFNF Transmit FIFO Not Full This is used to indicate that the transmit FIFO is not full 0 Transmit FIFO is full 1 Transmit FIFO is not full This bit is cleared when the TX FIFO is full R BUSY UART Busy Bit 0 Idle or inactive 1 Busy 19 4 14 UART Transmit FIFO Level Register Offset 0x80 Register Name UART_TFL A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved
130. 0040 TCONO Control Register A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 334 Allwinner Technology TCONO DCLK REG 0x0044 TCONO Data Clock Register TCONO BASICO REG 0x0048 TCONO Basic Timing RegisterO TCONO BASIC1 REG 0x004C TCONO Basic Timing Register1 TCONO BASIC2 REG 0x0050 TCONO Basic Timing Register2 TCONO BASIC3 REG 0x0054 TCONO Basic Timing Register3 TCONO HV IF REG 0x0058 TCONO Hv Panel Interface Register TCONO CPU IF REG 0x0060 TCONO CPU Panel Interface Register TCONO CPU WR REG 0x0064 TCONO CPU Panel Write Data Register TCONO CPU RDO REG 0x0068 TCONO CPU Panel Read Data RegisterO TCONO CPU RD1 REG 0x006C TCONO CPU Panel Read Data Register1 TCONO IO POL REG 0x0088 TCONO IO Polarity Register TCONO IO TRI REG 0x008C TCONO IO Control Register TCON1 CTL REG 0x0090 TCON1 Control Register TCON1 BASICO REG 0x0094 TCON1 Basic Timing RegisterO TCON1 BASIC1 REG 0x0098 TCON1 Basic Timing Register1 TCON1_BASIC2_REG 0x009C TCON1 Basic Timing Register2 TCON1 BASIC3 REG 0x00A0 TCON1 Basic Timing Register3 TCON1_BASIC4_REG Ox00A4 TCON1 Basic Timing Register4 TCON1_BASIC5_ REG 0x00A8 TCON1 Basic Timing Register5 TCON1 IO POL REG 0x00FO TCON1 IO Polarity Register TCON1_IO TRI REG 0x00F4 TCON1 10 Control Register TCON CEU CTL REG 0x0100 TCON CEU Control Register TCON CEU CO
131. 01 22 20 R W 0x4 110 111 19 PF4 Select 000 Input 001 Output 010 SDCO D3 011 UARTO RX 100 101 18 16 R W 0x0 110 111 15 PF3 Select 000 Input 001 Output 010 SDCO CMD 011 JTAG DO1 100 101 14 12 R W 0x4 110 111 11 PF2 Select 000 Input 001 Output 010 SDCO CLK 011 UARTO TX 100 101 10 8 R W 0 110 111 7 PF1 Select 000 Input 001 Output 010 SDCO DO 011 JTAG Di 100 101 6 4 R W 0x4 110 111 3 PFO Select 000 Input 001 Output 010 SDCO D1 011 JTAG MS1 100 101 2 0 R W 0x4 110 111 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 384 Allwinner Technology 33 4 38 PF Configure Register 1 Register Name PF CFG1 Offset 0xB8 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 39 PF Configure Register 2 Register Name PE CFG2 Offset 0xBC Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 40 PF Configure Register 3 Register Name PE CFG3 Offset OxCO Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 41 PF Data Register Register Name PF_DAT Offset OxC4 Default Value 0x0000 0000 Bit Read Write Default Description 31 6 If the port is configured as input t
132. 0x0 AVS CNTO EN Audio Video Sync Counter 1 Enable Disable The counter source is OSC24M 0 Disable 1 Enable 11 3 21 AVS Counter 0 Register Default 0x00000000 Offset 0x84 Register Name AVS CNTO REG Bit Read Write Default Description 31 0 RW Ox0 AVS_CNTO Counter 0 for Audio Video Sync Application The high 32 bits of the internal 33 bits 90KHZ counter register The initial value of the internal 33 bits counter register can be set by software The LSB bit of the 33 bits counter register should be zero when the initial value is updated It will count from the initial value The initial value can be updated at any time It can also be paused by setting AVS CNTO PS to 1 When it is paused the counter won t increase 11 3 22 AVS Counter 1 Register Default 0x00000000 Offset 0x88 Register Name AVS CNT1 REG Read Default Bit em Description Write AVS_CNT1 Counter 1 for Audio Video Sync Application 31 0 RW ove me high 32 bits of the internal son 90KHzZ counter register The initial value of the internal 33 bits counter register can be set by software The LSB bit of the 33 bits counter register should be zero when the initial value is updated It will count from the initial value A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 96 Allwinner Technology The initial value can be updated at a
133. 0x0 6 0 R 0x0 6 4 3 PLL2 Audio Default 0x08100010 Offset 0x08 Register Name PLL2 CFG REG Read W Default teg Bit Description rite Hex PLL2_Enable 0 Disable 1 Enable 31 R W 0x0 The PLL2 is for Audio PLL2 Output 24MHz N PLL2 PRE DIV PLL2 POST DIV 1X 48 N PreDiv PostDiv 2 not 50 duty A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 54 Allwinner Technology 2X 48 N PreDiv 4 8X 4 50 duty 4X 48 N PreDiv 2 8X 2 50 duty 8X 48 N PreDiv not 50 duty 30 PLL2 POST DIV PLL2 post divider 3 0 29 26 RW 0x2 0000 0x1 1111 0x10 25 21 R W 0x0 20 16 RW 0x10 15 PLL2 Factor N PLL2 Factor N Factor 0 N 1 14 8 R W 0x0 Factor 1 N 1 Factor 0x7F N 0x7F 7 5 PLL2 PRE DIV PLL2 pre divider 4 0 4 0 R W 0x10 00000 0x1 11111 0x20 6 4 4 PLL2 Tuning Default 0x00000000 Offset OxOC Register Name PLL2 TUN REG Read W Default Bit Description rite Hex 31 R W 0x0 30 29 RW 0x0 28 20 RW 0x0 19 18 17 RW 0x0 16 0 R W 0x0 6 4 5 PLL3 Video Default 0x0010D063 Offset 0x10 Register Name PLL3 CFG REG f Read W Default ae Bit Description rite Hex PLL3_Enable 0 Disable 1 Enable S Ge In the integer mode The PLL3 output 3MHz M In the fractional mode the PLL3 output is select by bit 14
134. 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 29 28 RW Ox0 IRQ78 PRIO IRQ 78 Priority Set priority level for IRQ bit 78 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 27 26 RW Ox0 IRQ77 PRIO IRQ 77 Priority Set priority level for IRQ bit 77 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 25 24 RW Ox0 IRQ76_PRIO IRQ 76 Priority Set priority level for IRQ bit 76 Level 0x0 level 0 lowest priority A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 125 Allwinner Technology Offset 0x90 Register Name INTC SRC PRIO REG4 Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ75 PRIO IRQ 75 Priority Set priority level for IRQ bit 75 23 22 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ74 PRIO IRQ 74 Priority Set priority level for IRQ bit 74 21 20 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ73_PRIO IRQ 73 Priority Set priority level for IRQ bit 73 19 18 RAW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1
135. 1 any of HcRhPortStatus NumberofDownstreamPort has changed FrameNumberOverflow This bit is set when the MSb of HcFmNumber bit 15 changes value from 0 to 1 or from 1 to 0 and after HccaFrameNumber has 5 RW RW 0x0 been updated UnrecoverableError This bit is set when HC detects a system error not related to USB HC should not proceed with any processing nor signaling before the system error has been corrected HCD clears this bit after HC 4 RW R W 0x0 has been reset ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling It is the transition from no resume signaling to resume signaling causing this bit to be set This bit is 3 HAN RW 0x0 not set when HCD sets the USBRseume state StartofFrame This bit is set by HC at each start of frame and after the update of HccaFrameNumber HC also generates a SOF token at the same 2 RW RW 0x0 time WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead Further updates of the HccaDoneHead will not occur until this bit has been cleared HCD should only clear this bit 1 RW RW 0x0 after it has saved the content of HccaDoneHead SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be 0 RW RW 0x0 Incremented 22 6 5 Hcinterr
136. 1 3 Copyright 2013 Allwinner Technology All Rights Reserved 359 Allwinner Technology 9 8 RW 0 Key Size for AES 00 128 bits 01 192 bits 10 256 bits 11 Reserved SS Operation Direction 0 Encryption 1 Decryption SS Method 000 AES 001 DES 010 Triple DES 3DES 011 SHA 1 100 MD5 101 PRNG Others Reserved SHA 1 MD5 Data End bit Write 1 to tell SHA 1 MD5 engine that the text data ends If there is some data in FIFO the engine will fetch these data and process them After finishing message digest this bit is cleared to 0 by hardware and message digest can be read out from digest registers Notes It is only used for SHA 1 MD5 engine PRNG start bit In PRNG one shot mode write 1 to start PRNG After generating one group random data 5 words this bit is cleared to 0 by hardware 0 R W 0 SS Enable A disable on this bit overrides any other block and flushes all FIFOs 0 Disable 1 Enable 31 4 2 Security System Key n Register Offset 0x04 4 n Register Name SS_KEY n Default Value 0x0000 0000 Bit Read Write Default Description 31 0 RW 0 Key n Input Value n 0 7 PRNG Seed n n 0 5 31 4 3 Security System IV n Register Offset 0x24 4 n Register Name SS Win Default Value 0x0000 0000 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All R
137. 101 30 28 R W 0 110 111 27 PC14 Select 000 Input 001 Output 010 NDQ6 011 SDC2_D6 100 101 26 24 R W 0 110 111 23 PC13 Select 000 Input 001 Output 010 NDQ5 011 SDC2_D5 100 101 22 20 R W 0 110 111 19 PC12 Select 000 Input 001 Output 010 NDQ4 011 SDC2_D4 100 101 18 16 R W 0 110 111 15 PC11 Select 1412 RW 0 000 Input 001 Output A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 373 Allwinner Technology 010 NDQ3 011 SDC2 D3 100 101 110 111 11 PC10 Select 000 Input 001 Output 010 NDQ2 011 SDC2 D2 100 101 10 8 R W 0 110 111 7 PC9 Select 000 Input 001 Output 010 NDQ1 011 SDC2_D1 100 101 6 4 R W 0 110 111 3 PC8 Select 000 Input 001 Output 010 NDQO 011 SDC2 DO 100 101 2 0 R W 0 110 111 33 4 12 PC Configure Register 2 Register Name PC CFG2 Offset 0x50 Default Value 0x0000 0000 Bit Read Write Default Description 31 16 15 PC19 Select 000 Input 001 Output 010 NDQS 011 100 UART3_RTS 101 14 12 RW 0 110 111 11 0 33 4 13 PC Configure Register 3 Register Name PC_CFG3 Offset 0x54 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 14 PC Data Register
138. 11 R W 0x0 TMRO RELOAD Timer 0 Reload 0 No effect 1 Reload timer 0 Interval value After the bit is set it can not be written again before its cleared automatically R W 0x0 TMRO EN Timer 0 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcycles the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note Time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 11 3 4 ASYNC Timer 0 Interval Value Register Offset 0x14 Register Name ASYNC_TMRO_INTV_VALUE_REG f Read W Default e Bit Description rite Hex TMRO_INTV_ VALUE 31 0 R W x Timer 0 Interval Value Note The value setting should consider the system clock and the timer clock source 11 3 5 ASYNC Timer 0 Current Value Register Offset 0x18 Register Name ASYNC_TMRO_CURNT_VALUE_REG Read W Default ee Bit Description ri
139. 11 R W TXFIFO 1 4 Empty DMA Request Enable 0 Disable 1 Enable 10 R W TXFIFO Not Full DMA Request Enable When enabled if more than one free room for burst DMA request is asserted otherwise it s de asserted 0 Disable 1 Enable R W TXFIFO Half Empty DMA Request Enable 0 Disable 1 Enable R W TXFIFO Empty DMA Request Enable 0 Disable 1 Enable R W RXFIFO 3 4 Full DMA Request Enable This bit enables disables the RXFIFO 3 4 Full DMA Request 0 Disable 1 Enable A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 172 Allwinner Technology RXFIFO 1 4 Full DMA Request Enable This bit enables disables the RXFIFO 1 4 Full DMA Request 0 Disable 3 R W 0 1 Enable RXFIFO Full DMA Request Enable This bit enables disables the RXFIFO Half Full DMA Request 0 Disable 2 R W 0 1 Enable RXFIFO Half Full DMA Request Enable This bit enables disables the RXFIFO Half Full DMA Request 0 Disable 1 R W 0 1 Enable RXFIFO Ready Request Enable This bit enables disables the RXFIFO Ready DMA Request when one or more than one words in RXFIFO 0 Disable 0 R W 0 1 Enable 18 4 7 SPI Wait Clock Register Offset 0x18 Register Name SPI WAIT Default Value 0x0000 0000 Bit Read Write Default Description 31 16 15 0 R W WCC Wait Clock Counter In Maste
140. 13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 20 Allwinner Technology 33 4 56 PIO Interrupt Configure Register en tn ne 389 33 4 57 PIO Interrupt Configure Res 389 33 4 58 PIO Interrupt Configure Register dsl hasta harhersharhesshnnannhnhententannhsntntss 390 33 4 59 PIO Interrupt Control Register 4asuantesetnnttesbnmjanindbnsisebeisdddis nttde 390 33 4 60 PIO Interrupt Status Register SR EN Se 390 33 4 61 PIO Interrupt Debounce Register mvh ak 390 ET 392 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 21 Allwinner Technology 1 Overview The A13 processor is an ARM Cortex A8 based tablet processor that is even more competitive for Android tablets with higher performance ManyCore Lite lower power consumption and lower total system cost As the brains of Android 4 0 3 A13 makes multitasking smoother apps loading more quickly and anything you touch responds instantly What s more important A13 is available in eLQFP176 package with Audio Codec and 2 Points R TP integrated 1 1 Features CPU e ARM Cortex V A8 Core ARMv7 Instruction set plus Thumb 2 Instruction Set 32KB Instruction Cache and 32KB Data Cache e 256KB L2 Cache e NEON SIMD Coprocessor Jazelle RCT Acceleration GPU 3D Graphic Engine Support Open GL ES 1 1 2 0 and Open VG 1 1 VPU Video Decoding FULL HD gt Support popular video formats including VP6 8 AVS H 264
141. 159 Allwinner Technology received ACK transmitted 0x80 Data byte received after slave address received ACK transmitted 0x88 Data byte received after slave address received not ACK transmitted 0x90 Data byte received after General Call received ACK transmitted 0x98 Data byte received after General Call received not ACK transmitted OxAO STOP or repeated START condition received in slave mode OxA8 Slave address Read bit received ACK transmitted OxBO Arbitration lost in address as master slave address Read bit received ACK transmitted 0xB8 Data byte transmitted in slave mode ACK received OxCO Data byte transmitted in slave mode ACK not received OxC8 Last byte transmitted in slave mode ACK received OxDO Second Address byte Write bit transmitted ACK received OxD8 Second Address byte Write bit transmitted ACK not received OxF8 No relevant status information INT_FLAG 0 Others Reserved 17 4 6 TWI Clock Register Offset 0x14 Register Name TWI_CCR Default Value 0x0000 0000 Bit Read Write Default Description 31 7 6 3 R W 0 CLK_M 2 0 RW CLK_N The two wire bus is sampled by the TWI at the frequency defined by FO Fsamp F 0 Fin 24CLK_N The TWI OSCL output frequency in master mode is F1 10 F1 FO CLK_M 1 Foscl F1 10 Fin 2 CLK_N CLK_M 1 10 For Example Fin 48Mhz
142. 2 SRAM Configuration Register 1 Default 0Ox00001000 79 8 ei OR lte E 80 Bts PU e LA ae ea a aca ae bee a Ea aaa 80 8 2 CPU Control Register Description ss 80 8 2 1 CPU Control Register Default 0x00000002 80 9 SDRAM Controller isciiicscssiiccstsscscesissctcccisseissetsscicestesedcsodsscdetesecescsstestdcasdessdecadsssiscetescdeeathea saeieucdisedsseecies 81 GEET 81 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 6 Allwinner Technology 10 EN EE NN MR dassies lssdsess aedes sises saada istes saod aassis uasi 82 10 1 Overview 00 cece cccccccccccceeeeeeeeeeeceaeeeeaeeeseaeeesaeessaaeeseaeeeceaeessaeeeseaeeeseaeessaeesseesseaeesseeeeseteeessaeess 82 10 2 PWM Register Listir r RSR RTS nu 82 10 3 PWM Register DESCIDUlOM EEN 82 10 3 1 PWM Control Register Default 0x00000000 rrrrrrnrrrrnvnrrrnrnrrrnrerrrnrrrnrerrrrnerrnnnn 82 10 3 2 PWM Channel 0 Period Papeete 84 TL Asynchronic LI issescasscssisescsescaserscasnsasssccssaresadensessacusedesscusesasosdsevasedscenduscheusssacesavisasencsssacossasescusatasoaes 85 ENEE 85 11 2 ASYNE Timer Register NS te ipa ace ancora encod eee ee 85 11 3 ASYNC Timer Register Deppen 86 11 3 1 ASYNC Timer IRQ Enable Register Default 0x00000000 rrrrrrrnrrrrrnrnrrrrverennnernn 86 11 3 2 ASYNC Timer IRQ Status Register Default 0Ox00000000 86 11 3 3 ASYNC Timer
143. 20 10 0 R W X CPU max frequency if cpuvdd 1 2v unit MHz This register can only be written if the DVFS function is disabled 5 3 27 PMU VF Table Register 11 Offset OxAC Register Name PMU VF TABLE REG11 Read W Default SCH Bit Description rite Hex 31 11 CPU_MAX_FREQ_125 10 0 R W D CPU max frequency if cpuvdd 1 25v unit MHz This register can only be written if the DVFS function is disabled 5 3 28 PMU VF Table Register 12 Offset OxBO Register Name PMU VF TABLE REG12 Read W Default o Bit f Description rite Hex 31 11 CPU_MAX_FREQ_130 10 0 R W X CPU max frequency if cpuvdd 1 3v unit MHz This register can only be written if the DVFS function is disabled 5 3 29 PMU VF Table Register 13 Offset 0xB4 Register Name PMU_VF_TABLE_REG13 Read W Default a Bit Description rite Hex 31 11 10 0 RW x PMR CPU max frequency if cpuvdd 1 35v unit MHz A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 41 Allwinner Technology This register can only be written if the DVFS function is disabled 5 3 30 PMU VF Table Register 14 Offset 0xB8 Register Name PMU VF TABLE REG14 Read W Default Bit Description rite Hex 31 11 l CPU MAX FREQ 140 10 0 R W X CPU max frequency if cpuvdd 1 4v unit MHz Th
144. 22 21 20 19 18 17 16 PO P1 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 10 11 Invalid Color 24 bpp or 32 bpp mode FBF 1001 or 1010 PS 00 01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 400 The bytes sequence is ARGB PS 10 11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 The bytes sequence is BGRA 28 5 16 DE HWC Coordinate Control Register Offset 0x8D8 Register Name DEBE HWCCTL REG Read Wr Default Ne Bit Description ite Hex A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 320 Allwinner Technology Hardware cursor Y coordinate 15 0 R W UDF MODE Hardware cursor X coordinate 28 5 17 DE HWC Frame Buffer Format Register Offset 0x8E0 Register Name DEBE_HWCFBCTL_REG Read Wr Default KC Bit Description ite Hex HWC_YCOOROFF Y coordinate offset The hardware cursor is 32 32 2 bpp pattern this value represent the start position of the cursor in Y coordinate HWC_XCOOROFF X coordinate offset The hardware cursor is 32 32 2 bpp pattern this value represent the start position of the cursor in X coordinate HWC_YSIZE Y size control 00 32pixels per line 01 64pixels per line Other reserved HWC_XSIZE X size control 00 32pixels per row 01 64pixels per row Other reserved HWC_FBFMT Pixels
145. 25 23 R W 0x3 FM Input to output mixer Gain Control From 4 5dB to 6dB 1 5dB step default is 0dB MICG 22 20 R W 0x3 MIC gain stage to output mixer Gain Control From 4 5dB to 6dB 1 5dB step default is 0dB LLNS Left LINEIN gain stage to left output MP mute 19 R W 0x0 0 mute 1 Not mute When LNRDF is 0 left select LINEINL When LNRDF is 1 left select LINEINL LINEINR RLNS Right LINEIN gain stage to right output MP mute 18 R W 0x0 0 mute 1 Not mute When LNRDF is 0 right select LINEINR When LNRDF is 1 right select LINEINL LINEINR LFMS Left FM to left output MP mute O mute 1 Not mute 17 R W 0x0 RFMS right FM to right output MP mute 0 mute 1 Not mute 16 R W 0x0 LDACLMIXS Left DAC to left output mixer Mute 0 Mute 1 Not mute 15 R W 0x0 RDACRMIXS Right DAC to right output mixer Mute 0 Mute 1 Not mute 14 R W 0x0 LDACRMIXS Left DAC to right output mixer Mute 0 Mute 1 Not mute 13 R W 0x0 MIC LS MIC to output mixer left channel mute 0 mute 1 Not mute 12 R W 0x0 11 R W 0x0 MIC RS A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 239 Allwinner Technology MIC to output mixer right channel mute 0 mute 1 Not mute 10 R W 0x0 9 R W 0x0 DACPAS DAC to PA Mute 8 R W 0x0 0 Mute 1 Not mute MIXPAS 7 RW pg Output Mixer to PA mu
146. 2KHz 10 32 5KHz 11 33KHz 16 0 R W 0x0 Wide Wave Bottom 6 4 13 OSC24M Default 0x00138013 Offset 0x50 Register Name OSC24M CFG REG Read W Default SEN Bit f Description rite Hex 31 24 RW 0x0 23 18 PLL IN PWR SEL 17 R W 0x1 PLL Input Power Select 0 2 5v 1 3 3v LDO EN 16 R W 0x1 LDO Enable 0 Disable 1 Enable 15 R W 0x1 PLL_BIAS_EN A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 60 Allwinner Technology PLL Bias Enable 0 disable 1 enable 14 2 R W 0x1 OSC24M GSM OSC24M GSM R W 0x1 OSC24M_EN OSC24M Enable 0 Disable 1 Enable 6 4 14 CPU AHB APBO Clock Ratio Default 0x00010010 Offset 0x54 Register Name CPU AHB APBO CFG REG Bit Read W rite Default Hex Description 31 18 17 16 RW 0x1 CPU_CLK_SRC_SEL CPU Clock Source Select 00 32KHz OSC Internal 01 OSC24M 10 PLL1 11 200MHz source from the PLL6 If the clock source is changed at most to wait for 8 present running clock cycles 15 10 9 8 RW Ox0 APBO CLK RATIO APBO Clock divide ratio APBO clock source is AHB2 clock 00 2 01 2 10 4 11 8 7 6 RW Ox0 AHB CLK SRC SEL 00 AXI 01 CPUCLK 10 PLL6 2 11 5 4 R W 0x1 AHB_CLK_DIV_RATIO AHB Clock divide ratio AHB clock source is
147. 32 PMU VF Table Register er 42 5 3 33 PMU VF Table EC 42 5 3 34 PMU VF Table Register 8 EES 42 5 3 35 PMU VF Table Valid Register sr 43 5 3 36 PMU VF Table Index Register 43 5 3 37 PMU VF Table Range Registern its 44 5 3 38 PMU Speed Factor Register 0 D 44 5 3 39 PMU Speed Factor ROIS sed dmdedsdddeinteden 45 5 3 40 PMU Speed Factor Register ds eee 45 5 3 41 CPU Idle Counter Low Register Default 0x00000000 46 5 3 42 CPU Idle Counter High Register Default 0x00000000 rrrrrrrrrenrnrrrrvnrrrrverrnnnrrnn 46 5 3 43 CPU Idle Control Register Default OsO00O0O000O0 47 5 3 44 CPU Idle Status Register Default 0x00000000 rrrrrnrvrrrrverrrrverrnnnrrrnrrrrrrrerrnnnernn 47 6 Clock Control Module COM sicsccssscsssissssisvioesscesnsnsssevessssvesassasesaassavevssesasnbsvesvsssssesntesvoscsdeunssesdeswsnbenes 48 6i EEN 48 627 Clock Tee Diane i ec a ec wre ee dee 49 6 3 GCM Register E 51 6 4 CCM Register e E le niin kite Gln ten nn 53 6 4 1 PLLA Gore Default 0x21005000 saci cictescasitnsinanauindcnessienddanadendionsdasdleesatenstuactundeauatendes 53 6 4 2 PLL1 Tuning Default 0x0A101000 E 54 6 4 3 PLL2 Audio Default 0x08100010 eanet hakka ss 54 6 4 4 PLL2 Tuning Default 0x00000000 segesegegeigeedE ege aide dei een 55 6 4 5 PLL3 Video Default 0x0010D063 ESS tect eeeceeetteeteecttateneeeeeeataias 55 6 4 6 PLL4 VE Default TOG TODO eect 56 6 4 7 PLL5 DDR
148. 38 PMU Speed Fa ctor Register 0 Offset OxEO Register Name PMU_SPEED_FACTOR_REGO Read W Bit i rite Default Hex Description 31 R W 0x0 SPD DET EN Speed Detect Enable 0 Disable 1 Enable 30 RW Ox0 SPD DET MODE Speed Detect Mode 0 single mode 1 continuous mode 29 28 RW Ox0 SPD DET SPDUP FACTOR Speed Detect Speed Up Factor Set these bits to non zero value can speed up the scan operation 00 lowest 11 fastest 27 17 Ox0 SPD DET SCN FIN Speed Detect Scan Finished 0 no effect 1 scan finished 15 8 R Ox0 SPD DET FACTOR Speed Detect Factor 1 This number indicates the delay length equivalent to input clock period x2 7 0 R Ox0 SPD DET FACTORO Speed Detect Factor 0 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 44 Allwinner Technology This number indicates the delay length equivalent to input clock period x1 5 3 39 PMU Speed Factor Register 1 Offset 0xE4 Register Name PMU_SPEED_FACTOR_REG1 Bit Read W rite Default Hex Description 31 R W 0x0 SPD DET EN Speed Detect Enable 0 Disable 1 Enable 30 R W 0x0 SPD_DET_MODE Speed Detect Mode 0 single mode 1 continuous mode 29 28 R W 0x0 SPD_DET_SPDUP_FACTOR Speed Detect Speed Up Factor Set these bits to n
149. 3FF 1K 0x01C2 B400 0x01C2 B7FF 1K 0x01C2 B800 0x01C2 BBFF 1K 0x01C2 BCO0 0x01C2 BFFF 1K 0x01C2 C000 0x01C2 C3FF 1K 0x01C2 C400 0x01C2 C7FF 1K 0x01C2 C800 0x01C2 CBFF 1K 0x01C2 CCO0 0x01C2 CFFF 1K 0x01C3 0000 0x01C3 FFFF 64K Mali 400 0x01C4 0000 0x01C4 FFFF 64K Sync Timer 0x01C6 0000 0x01C6 OFFF 4K SRAM C 0x01D0 0000 0x01DF FFFF Module SRAM DE FE 0x01E0 0000 0x01E1 FFFF 128K 0x01E2 0000 0x01E3 FFFF 128K DE BE 0x01E6 0000 0x01E6 FFFF 64K A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 28 Allwinner Technology IEP 0x01E7 0000 0x01E7 FFFF GAK 0x01E4 0000 0x01E5 FFFF 128K i 0x01E8 0000 0x01E9 FFFF 198K 0x01EA 0000 0x01EB FFFF 128K 0x3F50 0000 0x3F50 FFFF GET DDR I DDR lli 0x4000 0000 0xBFFF FFFF 2G BROM OxFFFF 0000 0xFFFF 7FFF 32K A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 29 Allwinner Technology 4 Boot System 4 1 Overview With one 32KB ROM the A13 supports five boot methods The system can boot sequencially from NAND Flash SPI NOR Flash SD Card and USB However if the external boot select pin BSP which is pulled up by an internal 50K resistor in normal state is checked by boot code to be on low level state after system power on the system will directly jump to boot from USB 4 2 Boot Diagram Power e state of BSP Yes
150. 5 HcinterruptEnable Register 219 22 6 6 HcinterruptDisable Register 220 22 6 7 HeHGCCA Register ESS a a a a a e anaa SE 221 22 6 8 HePeriodGurrentED Fe 221 22 6 9 aleet Ee ER 222 22 6 10 HcControlCurrentED Regisbr usuniete aime 222 22 6 11 HcBulkHeadED Register sn 223 22612 HeBulkCurrentED Register ass sus tintin titi tente 223 22 6 13 HcDoneHead Register sisi 223 22 6 14 HcFminterval Register sise 224 22 6 15 HcFmRemaining Register An 224 22 60 16 HeEFMNumber Register enterrer eens 225 22 6 17 Tee ein d 225 22 6 18 HcLSThreshold ReGISIBT nn tintin 226 22 6 19 HcRhDescriptorA Register 226 22 6 20 HcRhDescriptorB Register 227 22 6 21 HcRhStatus VNU cd tn ec ct cde teed tree deeeceees 228 22 6 22 HeRhPortStatus Register tenctaiatets 229 22 1 USB Host Special Requirement ess 233 23 AUNG e 234 2 DAN EE 234 23 2 Audio Lee Block TN 234 23 3 Audio Codec Register eege 235 23 4 Audio Codec Register Description 235 23 4 1 DAC Digital Part Control Fees Ee 235 23 4 2 DAG FIFO Control Register aac i cauaa na anaana kaa Eaa 236 23 4 3 DAC FIFO Status USN EE 237 23 4 4 DAC TX DATA RER EE 238 23 4 5 DAC Analog Control RegiISten cet el el ae 238 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 12 Allwinner Technology 23 4 6 ADC FIFO EE 240 23 4 7 EE 241 23 4 8 ADC BA DATA REgIStEr cscs Se ca nt nts atk ath ne dates 242 23 4 9 ADC Analog Control PEGI Ste La
151. 5 6 3 TP Control Register 2 4 eee ee 262 25 6 4 Median Filter Control Register i menenanunnnnieisiveinenjeivve hen eien 262 25 6 5 TP Interrupt amp FIFO Control Reiser nan 263 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 13 Allwinner Technology 25 6 6 TP Interrupt amp FIFO Status Eesbech 264 25 6 7 C mmon REN WEE 264 25 6 8 TP Data LE 265 25 6 9 TP Port IO Configure Register acetic anced accel heise cecal aiaced ana Recetas 265 25 610 IP Port Data Register tein hee inictohsioieh EENS 266 26 vs eege 267 ERR 267 260 2 091 B K Hegra ser ennan aaraa Eanna Eae ale Zak Geli data ints date NEEE ENRE 267 26 3 CSI Register ILE er Eoee EEEE e E E EEEE EEEE EET TE EES 267 EN TE NN 268 26 4 1 ETE 268 26 4 2 Eee E 268 26 4 3 CSI Capture Control Register session disent 270 26 4 4 CSI FIFOO0 Eupen eebe 270 26 4 5 CSI FIFOO Buffer Ee 270 26 4 6 CSI FIFO1 Buffer A R GISISrE cee ec 271 26 4 7 CSI FIFOT Buffer E Fiegetet eebe eebe keete 271 26 4 8 CSI Buffer Control SS a cect rec cae ces ces ec cence ce 271 26 4 9 CSSS RER Cee ere emt ee ee nro ere cena ar aoe 271 26 4 10 CSI Interrupt Enable P tten 272 26411 CSI Interrupt Status Register sees 273 26 4 12 CSI Window Width Control Register ss 273 26 4 13 CSI Window Height Control Register eegegegeegecegetegegegeegegegeegegegeegegegieggegetegeefeg 274 26 4 14 CSI Buffer Length Register sn RER ER NT ek 274 OU s s aa 274 26 5 1 Heade
152. 52 9 8 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ51 PRIO IRQ 51 Priority Set priority level for IRQ bit 51 7 6 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ50 PRIO IRQ 50 Priority Set priority level for IRQ bit 50 5 4 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 3 2 R W 0x0 IRQ49_PRIO A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 124 Allwinner Technology Offset 0x8C Register Name INTC_SRC_PRIO_REG3 IRQ 49 Priority Set priority level for IRQ bit 49 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ48_PRIO IRQ 48 Priority Set priority level for IRQ bit 48 1 0 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 13 4 30 Interrupt Source Priority 4 Register Default 0x00000000 Offset 0x90 Register Name INTC SRC PRIO REG4 Bit Read W rite Default Hex Description 31 30 R W 0x0 IRQ79_PRIO IRQ 79 Priority Set priority level for IRQ bit 79 Level 0x0 level 0 lowest priority Level
153. 54 Allwinner Technology 25 4 2 Single ended Mode When the TP Control Register 0 Biti2 ADC Mode Select is high the controller is in the measurement mode of AUX Temp the internal ADC reference voltage source is the single ended mode using the AVCC reference source as the ADC reference voltage application of the principle of single ended mode shown in Figure 28 8 ei a iG mr ANN REF mMm ANA AAA 2 Figure 25 8 Simplified Diagram of Single Ended Reference 25 4 3 Differential Mode When the TP Control Register 0 Biti2 ADC Mode Select is low the controller is in the measurement mode of X Y Z the internal ADC reference voltage source is the differential mode shown in Figure 28 9 The advantage of differential mode REF and REF input directly to the Y Y which can eliminate measurement error because of the switch on resistance The disadvantage is that both the ample or conversion process the driver needs to be on relative to single ended mode the power consumption increases AVCC REF t IN REF Converter REF AA Figure25 9 Simplified Diagram of Differential Reference A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 255 25 4 4 Single Touch Detection The principle of operation is illustrated below For an X co ordinate measurement the X pin is internally switched to AVCC a
154. 58 Priority Set priority level for IRQ bit 58 21 20 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ57_PRIO IRQ 57 Priority Set priority level for IRQ bit 57 19 18 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ56 PRIO IRQ 56 Priority Set priority level for IRQ bit 56 17 16 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 123 Allwinner Technology Offset 0x8C Register Name INTC_SRC_PRIO_REG3 IRQ55_PRIO IRQ 55 Priority Set priority level for IRQ bit 55 15 14 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ54 PRIO IRQ 54 Priority Set priority level for IRQ bit 54 13 12 RW 0x0 Level 0x0 level 0 lowest priority Leveli 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ53 PRIO IRQ 53 Priority Set priority level for IRQ bit 53 11 10 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ52_PRIO IRQ 52 Priority Set priority level for IRQ bit
155. 64 Register Name ASYNC_TMR5_INTV_VALUE_REG Read W Default E Bit Description rite Hex 31 0 RW TMR5 INTV VALUE i Timer 5 Interval Value Note the value setting should consider the system clock and the timer clock source 11 3 19 ASYNC Timer 5 Current Value Register Offset 0x68 Register Name ASYNC TMR5 CURNT VALUE REG Read W Default SC Bit Description rite Hex TMR5 CUR VALUE 1 R e SC Ge d t Timer 5 Current Value Note 1 Timer 1 current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale 2 Before timer 5 is enabled its current value register needs to be written with zero 11 3 20 AVS Counter Control Register Default 0x00000000 Offset 0x80 Register Name AVS CNT CTL REG Read Bit Default Description Write S EN 31 10 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 95 Allwinner Technology Ox0 AVS CNT1 PS Audio Video Sync Counter 1 Pause Control 0 Not pause 1 Pause Counter 1 R W 0x0 AVS CNTO PS Audio Video Sync Counter 0 Pause Control 0 Not pause 1 Pause Counter 0 7 2 R W 0x0 AVS CNT1 EN Audio Video Sync Counter 1 Enable Disable The counter source is OSC24M 0 Disable 1 Enable R W
156. A O_HcRhDesriptorB 0x44c OHCI Root Hub Descriptor Register B O_HcRhStatus 0x450 OHCI Root Hub Status Register O_HcRhPortStatus 0x454 OHCI Root Hub Port Status Register 22 5 EHCI Register Description 22 5 1 EHCI Identification Register Register Name CAPLENGTH Offset 0x00 Default Value Implementation Dependent Bit Read Write Default Description CAPLENGTH The value in these bits indicates an offset to add to register base to 7 0 R 0x10 find the beginning of the Operational Register Space 22 5 2 EHCI Host Interface Version Number Register Register Name HCIVERSION Offset 0x02 Default Value 0x0100 Bit Read Write Default Description HCIVERSION This is a 16 bits register containing a BCD encoding of the EHCI revision number supported by this host controller The most significant byte of this register represents a major revision and the 15 0 R 0x0100 least significant byte is the minor revision 22 5 3 EHCI Host Control Structural Parameter Register Register Name HCSPARAMS Offset 0x04 Default Value Implementation Dependent Bit Read Write Default Description Reserved 31 24 0 These bits are reserved and should be set to zero Debug Port Number This register identifies which of the host controller ports is the debug port The value is the port number one based of the debug port 23 20 R 0 This field will always be
157. ALID_REG Bit Read W rite Default Hex Description 31 16 RW Ox0 15 6 RW 0x1 VF_TABLE_18_VALID PMU V F Table Register 18 valid 0 valid 1 invalid RW 0x1 VF TABLE 17 VALID PMU V F Table Register 17 valid 0 valid 1 invalid R W 0x1 VF_TABLE_16_VALID PMU V F Table Register 16 valid 0 valid 1 invalid R W 0x1 VF_TABLE_15_VALID PMU V F Table Register 15 valid 0 valid 1 invalid R W 0x0 VF TABLE 14 VALID PMU V F Table Register 14 valid 0 valid 1 invalid R W 0x0 VF_TABLE_13_VALID PMU V F Table Register 13 valid 0 valid 1 invalid 5 3 36 PMU VF Table Index Register Offset OxDO Register Name PMU VF TABLE INDEX REG Bit Read W rite Default Hex Description 31 2 1 0 RW Ox0 VF TABLE IDX PMU V F Table Index 00 01 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 43 Allwinner Technology 10 11 5 3 37 PMU VF Table Range Register Offset OxD4 Register Name PMU VF TABLE RANGE REG Read W Default Dr Bit Description rite Hex 31 24 2346 RW oxo VF TABLE RNG2 PMU V F Table Range 2 158 RW gan VF TABLE RNG1 PMU V F Table Range 1 70 RW oxo VF_TABLE_RNGO PMU V F Table Range 0 5 3
158. AY_YCOOR Y coordinate Y is the left top y coordinate of layer on screen in pixels The Y represents the two s complement LAY_XCOOR X coordinate X is left top x coordinate of the layer on screen in pixels The X represents the two s complement Setting the layer0 layer3 the coordinate left top on screen control information 28 5 6 DE Layer Frame Buffer Line Width Register Layer 0 0x840 Layer 1 0x844 Register Name DEBE_LAYLINEWIDTH_REG Layer 2 0x848 Layer 3 0x84C Read Wr Default Bit Description ite Hex 34 0 RW UDF LAY_LINEWIDTH Layer frame buffer line width in bits A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 311 Allwinner Technology Note If the layer is selected by video channel or YUV channel the setting of this register will be ignored 28 5 7 DE Layer Frame Buffer Low 32 Bit Address Register Offset Layer 0 0x850 Layer 1 0x854 Register Name DEBE LAYFB L32ADD REG Layer 2 0x858 Layer 3 0x85C Read Wr Default BS Bit Description ite Hex LAYFB_L32ADD Buffer start Address Layer Frame start Buffer Address in bit Note If the layer is selected by video channel or YUV channel the setting of this register will be ignored 28 5 8 DE Layer Frame Buffer High 4 Bit Address Register Offset 0x860 Register Name DEBE_LAYFB_H4ADD_REG Read Wr Default un Bit Description ite Hex LAY3FB_H4ADD 27 24 RW UDF Layer3 elen le La
159. Address 14 4 5 Normal DMA Destination Address Register Default 0x00000000 Offset 0x100 N 0x20 0x8 N 0 1 2 3 4 5 6 7 Register Name NDMA DEST ADDR REG Read W Default SED Bit Description rite Hex 31 0 RW NDMA_DST_ADDR Normal DMA Destination Address 14 4 6 Normal DMA Byte Counter Register Default 0x00000000 Offset 0x100 N 0x20 0xC N 0 1 2 3 4 5 6 7 Register Name NDMA BC REG i Read W Default SC Bit Description rite Hex 31 24 23 0 RW S NDMA BC Normal DMA Byte Counter Note If ByteCounter 0 DMA will transfer no byte The maximum value is 128k 14 4 7 Dedicated DMA Configuration Register Default 0x00000000 Offset 0x300 N 0x20 N 0 1 2 3 4 5 6 7 Register Name DDMA CFG REG Read Defaul Bi D it Write Hex escription DDMA_LOAD DMA Loading 31 R W 0x0 If set to 1 DMA will start and load the DMA registers to the shadow registers The bit will hold on until the DMA finishes It will be cleared A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 140 Allwinner Technology automatically Set 0 to the bit will stop the corresponding DMA channel and reset its state machine 30 Ox0 DDMA BSY STA DMA Busy Status 0 DMA idle 1 DMA busy 29 RW Ox0 DDMA CONTI MODE EN DMA Continuous Mode Enable 0 Disable 1
160. Advance status bit in the USBSTS if the Interrupt on Async Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold The host controller sets this bit to a zero after it has set the Interrupt on Async Advance status bit in the USBSTS register to a one Software should not write a one to this bit when the asynchronous schedule is disabled Doing so will yield undefined results A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 204 Allwinner Technology Asynchronous Schedule Enable This bit controls whether the host controller skips processing the Asynchronous Schedule Values mean Bit Meaning Value 0 Do not process the Asynchronous Schedule 1 Use the ASYNLISTADDR register to access the Asynchronous Schedule 5 R W 0 The default value of this field is Ob Periodic Schedule Enable This bit controls whether the host controller skips processing the Periodic Schedule Values mean Bit Meaning Value 0 Do not process the Periodic Schedule 1 Use the PERIODICLISTBASE register to access the Periodic Schedule 4 R W 0 The default value of this field is Ob Frame List Size This field is R W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one This field specifies the size of the Frame list The size
161. Allwinner Technology A13 User Manual V1 3 2013 03 26 Copyright O 2013 Allwinner Technology All Rights Reserved Allwinner Technology Revision History Version Date Author Description V1 0 2012 04 16 Initial version V1 1 2012 10 25 Modify SDRAM NAND module descriptions V1 2 2013 1 8 Modify NAND USB DRD SD MMC V1 3 2013 3 26 Modify Audio Codec register description A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved Allwinner Technology Technical Items NO Abbreviation Full Name Description 1 ARM Cortex A8 amp ARM Cortex A8 amp A processor core designed by ARM Holdings implementing the ARM v7 instruction set architecture 2 Mali 400 Mali 400 A 2D 3D graphic processor unit designed by ARM Holdings 3 SDRAM Synchronous Dynamic Random Access Memory Dynamic random access memory DRAM that is synchronized with the system bus 4 PWM Pulse Width Modulator A commonly used technique for controlling power to inertial electrical devices made practical by modern electronic power switches 5 SPI Serial Peripheral Interface A synchronous serial data link standard named by Motorola that operates in full duplex mode Devices communicate in master slave mode where the master device initiates the data frame 6 UART Universal Asynchronous Receiver Transmitter used for serial communicatio
162. C SS DAC 63 STEP VOLUME From 0dB to 624B MIXEN DACPAS Figure23 1 Audio Codec Block Diagram A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 234 Allwinner Technology 23 3 Audio Codec Register List Module Name Base Address Audio Codec 0x01C22C00 Register Name Offset Description AC DAG DPC 0x00 DAC Digital Part Control Register AC_DAC_FIFOC 0x04 DAC FIFO Control Register AC_DAC_FIFOS 0x08 DAC FIFO Status Register AC_DAC_TXDATA Ox0C DAC TX Data Register AC DAG AGTL 0x10 DAC Analog Control Register AC_ADC_FIFOC Ox1C ADC FIFO Control Register AG ADG FIFOS 0x20 ADC FIFO Status Register AG ADC RXDATA 0x24 ADC RX Data Register AC_ADC AGTL 0x28 ADC Analog Control Register AG DAC CNT 0x30 DAC TX FIFO Counter Register AC_ADC_CNT 0x34 ADC RX FIFO Counter Register 23 4 Audio Codec Register Description 23 4 1 DAC Digital Part Control Register Offset 0x00 Register Name AC_DAC_DPC Bit Read Write Default Description EN_DA 31 RAW geg BAG Digital Part Enable 0 Disable 1 Enable 30 29 MODQU Internal DAC Quantization Levels 28 25 RW 0x0 Levels 7 21 4MODQU 3 0 128 Default levels 7 21 128 1 15 DWA DWA Function Disable 0 Enable 1 Disable 24 R W 0x0 23 19 HPF_EN High Pass Filter Enable 0 Disable 1 Enable 18 R W 0x0 DVOL 17 12 R W 0x0 Digita
163. DR_MODE DMA Source Address Mode 6 5 R W 0x0 0x0 Linear Mode 0x1 IO Mode 0x2 Horizontal Page Mode A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 142 Allwinner Technology 0x3 Vertical Page Mode 4 0 RW Ox0 14 4 8 DDMA SRC DRQ TYPE Dedicated DMA Source DRQ Type 0x0 SRAM memory 0x1 SDRAM memory 0x2 0x3 NAND Flash Controller NFC 0x4 USBO 0x5 0x6 Ox7 0x8 0x9 SPI1 RX OxA OxB Security System RX OxC OxD OxE OXF 0x10 Ox11 Ox12 AEN Ox14 Ox15 Ox16 Ox17 AEN 0x19 Ox1A 0x1B SPIO RX Ox1G 0x1D SPI2 RX Ox1E Ox1F Dedicated DMA Source Start Address Register N 0 7 Offset 0x300 N 0x20 0x4 N 0 1 2 3 4 5 6 7 Register Name DDMA SRC ADDR REG Bit Read W rite Default Hex Description 31 0 R W X DDMA SRC START ADDR Dedicated DMA Source Start Address A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 143 14 4 9 Allwinner Technology Dedicated DMA Destination Start Address Register N 0 7 Offset 0x300 N 0x20 0x8 N 0 1 2 3 4 5 6 7 Register Name DDMA_DEST_ADDR_REG Read W Default hd Bit Description rite Hex 31 0 RW POMA DST O TARTZADDR Dedicated DMA Destination Start Address 14 4 10 Dedica
164. D_EN LRADC Sample hold Enable 0 Disable 1 Enable 5 4 R W 0x2 LEVELB_VOL Level B Corresponding Data Value setting the real voltage value 00 0x3C 1 9v 01 0x39 1 8v 10 0x36 1 7v 11 0x33 1 6v 3 2 R W 0x2 LRADC_SAMPLE_RATE LRADC Sample Rate 00 250 Hz 01 125 Hz 10 62 5 Hz 11 32 25 Hz R W 0x0 LRADC EN LRADC enable 0 Disable 1 Enable 24 4 2 LRADC Interrupt Control Register Offset 0x04 Register Name LRADC_INTC Bit Read W rite Default Hex Description 31 16 12 R W 0x0 ADC1_KEYUP_IRQ_EN ADC 1 Key Up IRQ Enable 0 Disable 1 Enable 11 R W 0x0 ADC1_ALRDY_HOLD_IRQ_EN ADC 1 Already Hold Key IRQ Enable 0 Disable A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 248 Allwinner Technology 1 Enable 10 R W 0x0 ADC 1 Hold Key IRQ Enable 0 Disable 1 Enable R W 0x0 ADC1 KEYIRQ EN ADC 1 Key IRQ Enable 0 Disable 1 Enable RW Ox0 ADC1 DATA IRQ EN ADC 1 DATA IRQ Enable 0 Disable 1 Enable RW Ox0 ADCO KEYUP IRQ EN ADC 0 Key Up IRQ Enable 0 Disable 1 Enable RW Ox0 ADCO ALRDY HOLD IRQ EN ADC 0 Already Hold IRQ Enable 0 Disable 1 Enable RW Ox0 ADCO HOLD IRQ EN ADC 0 Hold Key IRQ Enable 0 Disable 1 Enable R
165. E INT STATUS REG ua 27521 DEFE STATUS REENEN er DEFE GSG EN NE 275230 DEFE CSO GOEFOL REG ee 27 5 24 DEFE CSC GUERRE REG aed 271525 DEFE CSO GJEFOS REG vvs ene DEFE CSC GOEFTO REG SE es Eai kaakkoa E 271527 DEFE CSC GOEFN BEG Suit tane fied DEFE CSG COEFI2 REG wicca 27529 DEFE CSC GOEFIS REG vasse 21500 DEFE CSC GOEF20 REG eegen 5 DEFE EE Ee Pre DEFE CSC GUERRE Ee 27533 DEFE CSC GOES REG aan 27 5 34 DEFE WEB LINESTED EN R GNE iat tati niet eda 27535 DEFE WB LINESTROD Eegeregie eege 21506 DEFE CHO INSIZE REG aan 21537 DEFE EREECHEN 27 5 38 EE GN a FACILES ee en er nn ee enn PAPEETE rrr 27509 DEFE CHO VERTFAGT RES eu uns 27 5 40 DERE CHO AORZPHASE MECS ee 27541 DEFE CHO VERTPHASED REG vasse 27 5 42 DERE GO VERTPHASEL REG uansett 27 5 43 DEFE CHI INSIZE REG Gansetssnninndndsndininitioniseienisnvnitnninite A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved Allwinner Technology 21 044 DERE CAL OUTSISE Eege 300 27585 DEFE CH HORZFACT FE Fv 300 21 540 DEFE CH1 VERTFAGT REG 215 nn nees 300 27 5 47 DEFE CHI EE RE ttes 301 27 5 48 DEFE CHI VERTPHASED REG eee 301 27 549 DEFE CHI VERTPHASET REG siennes nakne 301 27 5 50 DEFE CHO H RZCOEFO REGN N 0 91 5 Le 301 27 5 51 DEFE CHO VERTCOEF RECN NEO nt nues 302 27 5 52 DEFE CHI H RZGOERD REGN N 0 231 sje 302 27553 DEFE CHI VERTCGOEF REGN N 0 231 Lunar 303 28 Display Engine Back End
166. E features Output scan type interlace progressive Input format YUV444 YUV422 YUV420 YUV411 RGB Direct display output format RGB Write back output format RGB YUV444 YUV420 YUV422 YUV411 3 channel scaling pipelines for scaling up down Programmable source image size from 8x4 to 8192x8192 resolution Programmable destination image size from 8x4 to 8192x8192 resolution 4 tap scale filter in horizontal and vertical direction 32 Programmable coefficients for each tap Color space conversion between YUV and RGB Support direct display and write back to memory 27 2 DEFE Block Diagram Aa bd d Register file EE scaler rz CSC m gt SE display Figure 27 1 DEFE Block Diagram 27 3 DEFE Description DEFE supports scaling or resizing of planar or interleaved video component data Resizing or scaling the image means generating a new image that is larger or smaller than the original The new image will have a larger or smaller number of pixels in the horizontal and or vertical directions than the original image Filtering provides image enhancement and scaler provides high quality 4 tap in A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 276 Allwinner Technology horizontal and 4 tap in vertical filtering of YUV or RGB data 27 3 1 Re Sampling Up sampling is the process of inserting new data samples between original d
167. EBE U R constant register DEBE VBCOEF REG 0x970 0x978 DEBE V B coefficient register DEBE VBCONS REG 0x97C DEBE V B constant register DEBE_OCCTL_REG 0x9C0 DEBE output color control register DEBE_OCRCOEF_REG 0x9D0 0x9D8 DEBE output color R coefficient register DEBE_OCRCONS_REG Ox9DC DEBE output color R constant register DEBE OCGCOEF REG Ox9E0 0x9E8 DEBE output color G coefficient register DEBE_OCGCONS_REG Ox9EC DEBE output color G constant register A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 308 Allwinner Technology DEBE OCBCOEF REG 0x9F0 0x9F8 DEBE output color B coefficient register DEBE OCBCONS REG Ox9FC DEBE output color B constant register Memories 0x4400 0x47FF Gamma table 0x4800 0x4BFF DE HWC pattern memory block 0x4C00 0x4FFF DE HWC color palette table 0x5000 0x53FF Piped palette table 0x5400 0x57FF Pipe1 palette table 28 5 DEBE Register Description 28 5 1 DEBE Mode Control Register Offset 0x800 Register Name DEBE MODCTL REG Read Wr Default GA Bit Description ite Hex LINE_SEL 29 R W l DE Start top bottom line selection in interlace mode ITLMOD EN Interlace mode enable HWC EN Hardware cursor enabled disabled control 0 Disabled 1 Enabled Hardware cursor has the highest priority in the alpha blender0 the alpha value of cursor will be selected LAY3 EN Layer3 Enable Disable 0 Disabled 1
168. EFE CSC COEF02 REG 0x0078 DEFE CSC Coefficient 02 Register A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 283 Allwinner Technology DEFE CSC COEFO3 REG 0x007C DEFE CSC Coefficient 03 Register DEFE CSC COEF10 REG 0x0080 DEFE CSC Coefficient 10 Register DEFE CSC COEF11 REG 0x0084 DEFE CSC Coefficient 11 Register DEFE CSC COEF12 REG 0x0088 DEFE CSC Coefficient 12 Register DEFE CSC COEF13 REG 0x008C DEFE CSC Coefficient 13 Register DEFE_CSC_COEF20_REG 0x0090 DEFE CSC Coefficient 20 Register DEFE_CSC_COEF21_REG 0x0094 DEFE CSC Coefficient 21 Register DEFE_CSC_COEF22_REG 0x0098 DEFE CSC Coefficient 22 Register DEFE CSC COEF23 REG 0x009C DEFE CSC Coefficient 23 Register DEFE WB LINESTRD EN REG 0x00D0 DEFE Write Back Line Stride Enable Register DEFE WB LINESTRDO REG 0x00D4 DEFE Write Back Channel 3 Line Stride Register DEFE CHO INSIZE REG 0x0100 DEFE Channel 0 Input Size Register DEFE CHO OUTSIZE REG 0x0104 DEFE Channel 0 Output Size Register DEFE CHO HORZFACT REG 0x0108 DEFE Channel 0 Horizontal Factor Register DEFE CHO VERTFACT REG 0x010C DEFE Channel 0 Vertical factor Register DEFE CHO HORZPHASE REG 0x0110 DEFE Channel 0 Horizontal Initial Phase Register DEFE CHO VERTPHASEO REG 0x0114 DEFE Channel 0 Vertical Initial Phase 0 Register DEFE_CHO_VERTPHASE1_REG 0x0118 DEFE Channel 0 Vertical Initial Pha
169. EFO REG 0x0110 TCON CEU Coefficient RegisterO TCON_CEU_COEF1_REG 0x0114 TCON CEU Coefficient Register1 TCON_CEU_COEF2_REG 0x0118 TCON CEU Coefficient Register2 TCON_CEU_COEF3_REG 0x011C TCON CEU Coefficient Register3 TCON_CEU_COEF4_REG 0x0120 TCON CEU Coefficient Register4 TCON_CEU_COEF5_REG 0x0124 TCON CEU Coefficient Register5 TCON CEU COEF6 REG 0x0128 TCON CEU Coefficient Register6 TCON CEU COEF7 REG 0x012C TCON CEU Coefficient Register7 TCON CEU COEF8 REG 0x0130 TCON CEU Coefficient Register8 TCON CEU COEF9 REG 0x0134 TCON CEU Coefficient Register9 TCON CEU COEF10 REG 0x0138 TCON CEU Coefficient Register10 TCON CEU COEF11 REG 0x013C TCON CEU Coefficient Register11 TCON CEU COEF12 REG 0x0140 TCON CEU Coefficient Register12 TCON CEU COEF13 REG 0x0144 TCON CEU Coefficient Register13 TCON CEU COEF14 REG 0x0148 TCON CEU Coefficient Register14 TCON1 FILL CTL REG 0x0300 TCON1 Fill Data Control Register TCON1_ FILL BEGINO REG 0x0304 TCON1 Fill Data Begin RegisterO TCON1_ FILL ENDO REG 0x0308 TCON1 Fill Data End Register0 TCON1_ FILL DATAO REG 0x030C TCON1 Fill Data Value RegisterO TCON1 FILL BEGIN REG 0x0310 TCON1 Fill Data Begin Register A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved Allwinner Technology TCON1 FILL END1 REG 0x0314 TCON1 Fill Data End Register1 TCON1_ FILL_DATA1_REG 0x0318 TCON1 Fill Data Value Register1 TCON1_ FILL_BEGIN2_REG 0x031C TCON1 Fill Data Begin Register2 TC
170. Enable R W TX FIFO Empty Interrupt Enable 0 Disable 1 Enable R W RXFIFO under run Interrupt Enable 0 Disable 1 Enable R W RX FIFO Overflow Interrupt Enable 0 Disable 1 Enable R W RXFIFO 3 4 Full Interrupt Enable 0 Disable 1 Enable R W RX FIFO 1 4 Full Interrupt Enable 0 Disable 1 Enable R W RX FIFO Full Interrupt Enable A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 169 Allwinner Technology 0 Disable 1 Enable R W RX FIFO Half Full Interrupt Enable 0 Disable 1 Enable R W RX FIFO Ready Interrupt Enable 0 Disable 1 Enable 18 4 5 SPI Interrupt Status Register Offset 0x10 Register Name SPI_INT_STA Default Value 0x0000 1B00 Bit Read Write Default Description 31 Clear interrupt busy flag 0 clearing interrupt is done 1 clearing interrupt is busy 30 24 23 20 19 18 TITI IJIIJISIJIeS 17 RW SSI SS Invalid Interrupt When SSI is 1 it indicates that SS has changed from valid state to invalid state Writing 1 to this bit clears it 16 RW TC Transfer Completed In master mode when SMC is 1 it indicates that all bursts specified by BC have been exchanged In other condition When set this bit indicates that all the data in TXFIFO has been loaded in the Shift register and the S
171. FO Empty Pending Interrupt 0 No Pending IRQ 1 FIFO Empty Pending Interrupt Write 1 to clear this interrupt or automatic clear if interrupt condition fails 3 R W 0x1 TXU INT TX FIFO Under run Pending Interrupt 2 R W 0x0 0 No Pending Interrupt 1 FIFO Under run Pending Interrupt Write 1 to clear this interrupt TXO INT TX FIFO Overrun Pending Interrupt 1 R W 0x0 0 No Pending Interrupt 1 FIFO Overrun Pending Interrupt Write 1 to clear this interrupt 0 23 4 4 DAC TX DATA Register Offset OxC Register Name AC DAC TXDATA Bit Read Write Default Description TX DATA Transmitting left right channel sample data should be written this register one by one The left channel sample data is first and then 31 0 W 0x0 the right channel sample 23 4 5 DAC Analog Control Register Offset 0x10 Register Name AC_DAC_ACTRL Bit R W Default Description DACAREN Internal DAC Analog Right channel Enable 0 Disable 1 Enable DACALEN Internal DAC Analog Left channel Enable 0 Disable 1 Enable MIXEN Analog Output Mixer Enable 0 Disable 1 Enable 31 R W 0x0 30 R W 0x0 29 R W 0x0 28 27 26 R W 0x1 LNG A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 238 Allwinner Technology Line in gain stage to output mixer Gain Control 0 1 5dB 1 0dB FMG
172. HC Halted bit in the USBSTS register is a zero Attempting to reset an actively running host controller will result in undefined behavior 0 RW Run Stop When set to a 1 the Host Controller proceeds with execution of the schedule When set to 0 the Host Controller completes the current and any actively pipelined transactions on the USB and then halts The Host Controller must halt within 16 micro frames after software clears this bit The HC Halted bit indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state Software must not write a one to this field unless the Host Controller is in the Halt State The default value is 0x0 22 5 7 EHCI USB Status Register Offset 0x14 Register Name USBSTS Default Value 0x00001000 Bit Read Write Default Description 31 16 Reserved These bits are reserved and should be set to zero 15 R Asynchronous Schedule Status The bit reports the current real status of Asynchronous Schedule If this bit is a zero then the status of the Asynchronous Schedule is disabled If this bit is a one then the status of the Asynchronous Schedule is enabled The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register When this bit and the Asynchronous Schedule Enable bit are the same valu
173. I Frame List Base Address Register E_ASYNCLISTADDR 0x028 EHCI Next Asynchronous List Address Register E CONFIGFLAG 0x050 EHCI Configured Flag Register E PORTSC 0x054 EHCI Port Status Control Register OHCI Control and Status Partition Register O HcRevision 0x400 OHCI Revision Register O HcControl 0x404 OHCI Control Register O HcCommandStatus 0x408 OHCI Command Status Register O HelnterruptStatus 0x40c OHCI Interrupt Status Register O HcinterruptEnable 0x410 OHCI Interrupt Enable Register O HelnterruptDisable 0x414 OHCI Interrupt Disable Register OHCI Memory Pointer Partition Register O_HcHCCA 0x418 OHCI HCCA Base O_HcPeriodCurrentED 0x41c OHCI Period Current ED Base O_HcControlHeadED 0x420 OHCI Control Head ED Base O HcControlCurrentED 0x424 OHCI Control Current ED Base O_HcBulkHeadED 0x428 OHCI Bulk Head ED Base O_HcBulkCurrentED 0x42c OHCI Bulk Current ED Base O_HcDoneHead 0x430 OHCI Done Head Base OHCI Frame Counter Partition Register O_HcFmInterval 0x434 OHCI Frame Interval Register O HcFmRemaining 0x438 OHCI Frame Remaining Register O HcFmNumber 0x43c OHCI Frame Number Register A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 199 Allwinner Technology O_HcPerioddicStart 0x440 OHCI Periodic Start Register O_HcLSThreshold 0x444 OHCI LS Threshold Register OHCI Root Hub Partition Register O_HcRhDescriptorA 0x448 OHCI Root Hub Descriptor Register
174. IFOs Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 182 Allwinner Technology 19 4 8 UART Line Control Register Register Name UART LCR Offset 0xOC Default Value 0x0000 0000 Bit Read Write Default Description 31 8 DLAB Divisor Latch Access Bit It is writeable only when UART is not busy USR 0 is zero and always readable This bit is used to enable reading and writing of the Divisor Latch register DLL and DLH to set the baud rate of the UART This bit must be cleared after initial baud rate setup in order to access other registers 0 Select RX Buffer Register RBR TX Holding Register THR and Interrupt Enable Register IER 1 Select Divisor Latch LS Register DLL and Divisor Latch MS 7 R W 0 Register DLM BC Break Control Bit This is used to cause a break condition to be transmitted to the receiving device If set to one the serial output is forced to the spacing logic 0 state When not in Loopback Mode as determined by MCR 4 the sout line is forced low until the Break bit is cleared If SIR MODE Enabled and active MCRI 6 set to one the sir_out_n line is continuously pulsed When in Loopback Mode the break condition is internally looped back to the receiver and the 6 R W 0 sir_out_n line is forced low 5 EPS Even Pari
175. L3 25 24 RW 0x0 01 PLL 10 PLL5 11 23 18 17 16 15 4 CLK_DIV_RATIO_M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 33 DE FE Clock Default 0x00000000 Offset 0x10C Register Name FE_CFG_REG Read W Default De Bit i Description rite Hex SCLK_GATING Gating Special Clock 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M 30 R W 0x0 FE_RST A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 72 Allwinner Technology DE FE Reset O reset valid 1 reset invalid 29 26 25 24 CLK SRC SEL Clock Source Select 00 PLL3 01 PLL7 10 PLL5 11 R W 0x0 23 18 17 16 15 4 I 3 0 CLK DIV RATIO M R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 34 LCD CH1 Clock Default 0x00000000 Offset 0x12C Register Name LCD_CH1_CFG_REG Bit Read W Default Description rite Hex H 31 SCLK2_GATING Gating Special Clock 2 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock 2 Special Clock 2 Source Divider M 30 26 25 24 SCLK2_SRC_SEL Special Clock 2 Source Select 00 PLL3 1X 01 PLL7 1X 10 PLL3 2X 11 PLL7 2X R W 0x0 23 18
176. LUE luminance statistical value 31 08 When frame done interrupt flag come value is ready and will last until next frame done For raw data value G gt gt 1 R G gt gt 8 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 271 Allwinner Technology For yuv422 value Y gt gt 8 VIDEO CAP ON Video capture in progress Indicates the CSI is capturing video image data multiple frames The bit is set at the start of the first frame after enabling video capture When software disables video capture it clears itself after the last pixel of the current frame is captured STILL CPT ON Still capture in progress Indicates the CSI is capturing still image data single frame The bit is set at the start of the first frame after enabling still frame capture It is self cleared after the last pixel of the first frame is captured For CCIR656 interface if the output format is frame planar YCbCr 420 mode the frame end means the field2 end and the other frame end means filed end 26 4 10 CSI Interrupt Enable Register Offset Address 0X0030 Register Name CSI INT EN REG Default Value 0X00000000 Read Wr Default De Bit Description ite Hex VSYNC_FLAG vsync flag The bit is set when vsync come And at this time load the buffer address for the coming frame So after this irq comes change the buffer address could only affect next frame Hblank FIFO overflow The bit is set when 3 FIFOs still ov
177. Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ37_PRIO IRQ 37 Priority Set priority level for IRQ bit 37 11 10 R W 0x0 Level 0x0 level 0 lowest priority Leveli 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ36 PRIO IRQ 36 Priority Set priority level for IRQ bit 36 9 8 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ35_PRIO 7 6 R W 0x0 IRQ 35 Priority Set priority level for IRQ bit 35 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 121 Allwinner Technology Offset 0x88 Register Name INTC SRC PRIO REG2 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ34 PRIO IRQ 34 Priority Set priority level for IRQ bit 34 5 4 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ33 PRIO IRQ 33 Priority Set priority level for IRQ bit 33 3 2 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ32_PRIO IRQ 32 Priority Set priority level for IRQ bit 32 1 0 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 hig
178. Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved Allwinner Technology PF2 Input Output SDCO_CLK UARTO TX PF3 Input Output SDCO CMD JTAG_DOI PF4 Input Output SDCO D3 UARTO RX PF5 Input Output SDCO D2 JTAG CK1 PGO Input Output GPS CLK EINTO PG1 Input Output GPS_SIG EINT1 PG2 Input Output GPS MAG EINT2 PG3 Input Output SDC1 CMD MS BS UARTI1 TX EINT3 PG4 Input Output SDC1 CLK MS CLK UARTI1 RX EINT4 PG9 Input Output SPIL CSO UART3 TX EINT9 PG10 Input Output SPIL CLK UART3 RX EINT10 PG11 Input Output SPIL MOSI UART3_CTS EINT11 PG12 Input Output SPIL MISO UART3 RTS EINT12 33 3 Port Register List Module Name Base Address PIO 0x01C20800 Register Name Offset Description Pn CFGO n 0x24 0x00 Port n Configure Register 0 n from 0 to 6 Pn CFG1 n 0x24 0x04 Port n Configure Register 1 n from 0 to 6 Pn_CFG2 n 0x24 0x08 Port n Configure Register 2 n from 0 to 6 Pn_CFG3 n 0x24 0x0C Port n Configure Register 3 n from 0 to 6 Pn_DAT n 0x24 0x10 Port n Data Register n from 0 to 6 Pn_DRVO n 0x24 0x14 Port n Multi Driving Register 0 n from 0 to 6 Pn_DRV1 n 0x24 0x18 Port n Multi Driving Register 1 n from 0 to 6 Pn_PULO n 0x24 0x1C Port n Pull Register 0 n from 0 to 6 Pn PUL1 n 0x24 0x20 Port n Pull Register 1 n from 0 to 6 PI
179. Normal DMA 6 Half Transfer Interrupt Enable 0 Disable 1 Enable NDMA5_END_IRQ_EN 11 R W 0x0 Normal DMA 5 End Transfer Interrupt Enable 0 Disable 1 Enable NDMA5_HF_IRQ_EN 10 R W 0x0 Normal DMA 5 Half Transfer Interrupt Enable 0 Disable 1 Enable NDMA4 END IRQ EN 9 R W 0x0 Normal DMA 4 End Transfer Interrupt Enable 0 Disable 1 Enable NDMA4 HF IRQ EN 8 R W 0x0 Normal DMA 4 Half Transfer Interrupt Enable 0 Disable 1 Enable NDMA3_END_IRQ_EN 7 R W 0x0 Normal DMA 3 End Transfer Interrupt Enable 0 Disable 1 Enable NDMA3_HF_IRQ_EN 6 R W 0x0 Normal DMA 3 Half Transfer Interrupt Enable 0 Disable 1 Enable NDMA2_END_IRQ_EN 5 R W 0x0 Normal DMA 2 End Transfer Interrupt Enable 0 Disable 1 Enable NDMA2_HF_IRQ_EN 4 R W 0x0 Normal DMA 2 Half Transfer Interrupt Enable 0 Disable 1 Enable NDMA1_END_IRQ_EN 3 R W 0x0 S Normal DMA 1 End Transfer Interrupt Enable A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 133 Allwinner Technology 0 Disable 1 Enable R W 0x0 NDMA1_HF_IRQ_EN Normal DMA 1 Half Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMAO END IRQ EN Normal DMA 0 End Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMAO HF IRQ EN Normal DMA 0 Half Transfer Interrupt Enable 0 Disable 1 Enable 14 4 2 DMA IRQ Pen
180. O INT CFGO 0x200 PIO Interrrupt Configure Register 0 PIO INT CFG1 0x204 PIO Interrrupt Configure Register 1 PIO INT CFG2 0x208 PIO Interrrupt Configure Register 2 PIO INT CFG3 0x20C PIO Interrrupt Configure Register 3 PIO_INT_CTL 0x210 PIO Interrupt Control Register PIO_INT_STA 0x214 PIO Interrupt Status Register PIO_INT_DEB 0x218 PIO Interrupt Debounce Register 33 4 Port Register Description 33 4 1 PB Configure Register 0 Register Name PB CFGO Offset 0x24 Default Value 0x0000 0000 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 368 Allwinner Technology Bit Read Write Default Description 31 30 28 RW 0 27 26 24 R W 0 23 22 20 R W 0 19 PB4 Select 000 Input 001 Output 010 IR RX 011 100 101 18 16 R W 0 110 EINT18 111 15 PB3 Select 000 Input 001 Output 010 IR_TX 011 100 101 14 12 R W 0 110 EINT17 111 11 PB2 Select 000 Input 001 Output 010 PWM 011 100 101 10 8 R W 0 110 EINT16 111 7 PB1 Select 000 Input 001 Output 010 TWIO SDA 011 100 101 6 4 R W 0 110 111 3 PBO Select 000 Input 001 Output 010 TWIO SCK 011 100 101 2 0 R W 0 110 111 33 4 2 PB Configure Register 1 Register Name PB CFG1 Offset 0x28 Default Value 0x0000 0000 Bit Read Write Default Desc
181. ON1 FILL END2 REG 0x0320 TCON1 Fill Data End Register2 TCON1_ FILL_DATA2_REG 0x0324 TCON1 Fill Data Value Register2 TCON1 GAMMA TABLE REG 0x400 0x7FF TCON1 Gama Table Register 29 3 TCON Register Description 29 3 1 TCON GCTL REG Offset 0x000 Register Name TCON global control register f Read W Default DE Bit Description rite Hex TCON_En 31 RAW 0 0 disable 1 enable When it s disabled the module will be reset to idle state TCON_Gamma_En 30 R W 0 0 disable 1 enable 29 1 IO Map Sel 0 TCONO i SS e 1 TCON1 Note This bit determines which IO INV IO TRI is valid 29 3 2 TCON GINTO REG Offset 0x004 Register Name TCON global interrupt registerO f Read W Default KE Bit Description rite Hex TCONO Vb Int En 31 R W 0 0 disable 1 enable TCON1 Vb Int En 30 R W 0 0 disable 1 enable TCONO Line Int En 29 R W 0 0 disable 1 enable TCON1 Line Int En 28 R W 0 0 disable 1 enable 27 16 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 336 Allwinner Technology TCONO Vb Int Flag 15 R W 0 Asserted during vertical no display period every frame Write 0 to clear it TCON1 Vb Int Flag 14 R W 0 Asserted during vertical no display period every frame Write 0 to clear it TCONO Line Int Flag 13 RW 0 tri
182. Ox00000000 110 13 4 7 Interrupt IRQ Pending Register 2 Default 0Ox00000000 110 13 4 8 Interrupt FIQ Pending Clear Register 0 Default 0x00000000 eee 110 13 4 9 Interrupt FIQ Pending Clear Register 1 Default 0x00000000 s 110 13 4 10 Interrupt FIQ Pending Clear Register 2 Default 0x00000000 eee 110 13 4 11 Interrupt Select Register 0 Default 0x00000000 eee eeeeeeeeeeeeeeeeeeeeeeeeeeeeeenees 111 13 4 12 Interrupt Select Register 1 Default 0x00000000 rrrrrnvrrnrnnnvnnnnrnrnrnrnverrnrrrnrnrnvennn 111 13 4 13 Interrupt Select Register 2 Default 0x00000000 rrrnvvrnnrnnnvnnnnrnnnrnnnvenrnrnrnrnrnvnnnn 111 13 4 14 Interrupt Enable Register 0 Default 0x00000000 rrrnvrrnnnrvnrrvrnrenrrnrrnrnnrrrerenvnnenn 111 13 4 15 Interrupt Enable Register 1 Default 0x00000000 errnvrnnnnrvnrnvrnnenvrnnnnrnnrrernnenvnnenn 111 13 4 16 Interrupt Enable Register 2 Default 0x00000000 eerrnnvrvvnnrnnrrnnnrnnrrnnnrrnrrnnnnennnn 112 13 4 17 Interrupt Mask Register 0 Default Ox00000000 112 13 4 18 Interrupt Mask Register 1 Default Ox00000000 112 13 4 19 Interrupt Mask Register 2 Default Ox00000000 112 13 4 20 Interrupt Response Register 0 Default 0x00000000 eee eeeeteteeeeeteeeeeee 113 13 4 21 Interrupt Response Register 1 Default
183. PD4 Input Output LCD D4 UART2 CIS PD5 Input Output LCD D5 UART2 RTS PD6 Input Output LCD D6 ECRS PD7 Input Output LCD D7 ECOL PD8 Input Output LCD_D8 PD9 Input Output LCD D9 PD10 Input Output LCD D10 ERXDO PD 11 Input Output LCD DI ERXD1 PD12 Input Output LCD_D12 ERXD2 PD13 Input Output LCD D13 ERXD3 PD14 Input Output LCD D14 ERXCK PD15 Input Output LCD D15 ERXERR PD18 Input Output LCD DIS ERXDV PD19 Input Output LCD D19 ETXDO PD20 Input Output LCD D20 ETXD1 PD21 Input Output LCD D21 ETXD2 PD22 Input Output LCD D22 ETXD3 PD23 Input Output LCD D23 ETXEN PD24 Input Output LCD CLK ETXCK PD25 Input Output LCD DE ETXERR PD26 Input Output LCD HSYNC EMDC PD27 Input Output LCD VSYNC EMDIO PEO Input Output TS CLK CSL PCLK SPR CS0 EINT14 PE1 Input Output TS ERR CSI MCLK SPI CLK EINT15 PE2 Input Output TS_SYNC CSI HSYNC SPI2 MOSI PE3 Input Output TS DVLD CSL VSYNC SPIR MISO PE4 Input Output TS DO CSL DO SDC2 DO PES Input Output TS_D1 CSL DI SDC2 DI PE6 Input Output TS D2 CSI D2 SDC2_D2 PE7 Input Output TS_D3 CSI_D3 SDC2_D3 PES Input Output TS D4 CSI D4 SDC2 CMD PE9 Input Output TS_DS CSL DS SDC2_CLK PE10 Input Output TS_D6 CSI D6 UARTI_TX PE11 Input Output TS D7 CSL Di UARTI1 RX PFO Input Output SDCO DI JTAG MS PF1 Input Output SDCO DO JTAG_DII A13 User
184. Priority Set priority level for IRQ bit 87 15 14 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ86_RPIO IRQ 86 Priority Set priority level for IRQ bit 86 13 12 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ85_PRIO IRQ 85 Priority Set priority level for IRQ bit 85 11 10 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ84_PRIO 9 8 R W 0x0 IRQ 84 Priority Set priority level for IRQ bit 84 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 129 Allwinner Technology Offset 0x94 Register Name INTC SRC PRIO REG5 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ83 PRIO IRQ 83 Priority Set priority level for IRQ bit 83 7 6 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ82_PRIO IRQ 82 Priority Set priority level for IRQ bit 82 5 4 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ81 PRIO IRQ 81 Priority Set priority level for IRQ bit 81 3 2
185. REG Read Wr Default or Bit Description ite Hex CKR MATCH Red Match Rule 00 always match 01 always match 10 match if Color Min lt Color lt Color Max 11 match if Color gt Color Max or Color lt Color Min CKG MATCH Green Match Rule 00 always match 01 always match 10 match if Color Min lt Color lt Color Max 11 match if Color gt Color Max or Color lt Color Min CKB MATCH Blue Match Rule 00 always match 01 always match 10 match if Color Min lt Color lt Color Max 11 match if Color gt Color Max or Color lt Color Min 28 5 13 DE Layer Attribute Control Register Offset Layer0 0x890 Layer1 0x894 Register Name DEBE_ATTCTL_REGO Layer2 0x898 Layer3 0x89C Read Wr Default Aa Bit Description ite Hex LAY GLBALPHA 31 24 RW UDF Alpha value Alpha value is used for this layer LAY WORKMOD Layer working mode selection 00 normal mode Non Index mode 1 pal l 23 22 RW UDE 0 pa ette mode Index mode 10 internal frame buffer mode 11 gamma correction Except the normal mode if the other working mode is selected the on A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 314 Allwinner Technology A13 User Manual V1 3 chip SRAM will be enabled PREMUL 0 normal input layer 1 pre multiply input layer Other reserved CKEN Color key Mode 00 disabled color key 01 The layer color key matches another channel pixel data i
186. RW 0 Start_Delay This is for DE1 and DE2 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 344 Allwinner Technology 29 3 21 TCON1 BASICO REG Offset 0x094 Register Name TCON1 basic timing register0 Read W Default JE Bit Description rite Hex 31 27 TCON1 XI R di av 9 source width is X 1 15 12 TCON1 YI 11 0 R W 0 7 source height is Y 1 29 3 22 TCON1 BASIC1 REG Offset 0x098 Register Name TCON1 basic timing register1 Read W Default Bit rite Z Description 31 27 LS XO SC e width is LS_XO 1 15 12 LS YO 11 0 RW lo width is LS YO 1 Note this version LS YO TCON1 YI 29 3 23 TCON1 BASIC2 REG Offset 0x09C Register Name TCON1 basic timing register2 Read W Default Bit Description rite Hex 31 27 TCON1 XO So ra width is TCON1_XO 1 15 12 TCON1 YO 11 0 R W 0 height is TCON1_YO 1 29 3 24 TCON1 BASIC3 REG Offset 0Ox0A0 Register Name TCON1 basic timing register3 i Read W Default Bit Description rite Hex 31 28 HT 28 16 R W 0 horizontal total time Thcycle HT 1 Thdclk 15 12 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 345 Allwinner Technology
187. SM MODE Clock Change Smooth Mode 0 Divide mode 1 Gating mode Ox0 SM EN Smooth enable 0 Disable 1 Enable Ox0 CLK SWTH EN Clock switch enable 0 Disable 1 Enable Ox0 VOLT CHANGE EN Voltage change enable 0 Disable 1 Enable Ox0 SPD DET EN Speed detect enable 0 Disable 1 Enable 3 1 Ox0 DVFS EN PMU DVFS Enable 0 Disable 1 Enable 5 3 2 PMU DVFS Control Register 1 Default 0x00001010 Offset 0x04 Register Name PMU DVFS CTRL REG1 f Read W Default CH Bit Description rite Hex 31 24 PLL STAB TIME 23 8 R W 0x10 SS g PLL stable time 70 RW 60 SE Smooth interval value 5 3 3 PMU DVFS Control Register 2 Offset 0x0C Register Name PMU DVFS CTRL REG2 Read W Default Bit i Description rite Hex 31 1 j VOLT_SET_EN Voltage Set Enable 0 RW di It will be auto cleared after the voltage setting command is sent successfully Set this bit to 1 will start the voltage setting set the CPUVDD register value to the external PMU IC through the TWI interface Note This bit can not be set to one if the VoltageChangeEnable bit in the DVFS Ctrl register 0 is set A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 33 to 1 Allwinner Technology
188. TH Input image U R component width 12 0 R W 0x0 The image width The value of these bits add 1 When line buffer result selection is original data the maximum width is 2048 27 5 44 DEFE CH1 OUTSIZE REG Offset 0x204 Register Name DEFE CH OUTSIZE REG Read W Default SCH Bit f Description rite Hex 31 29 OUT_HEIGHT 28 16 RW 0x0 Output layer U R component height The output layer height The value of these bits add 1 15 13 OUT WIDTH Output layer U R component width 12 0 R W 0x0 The output layer width The value of these bits add 1 When line buffer result selection is horizontal filtered result the maximum width is 2048 27 5 45 DEFE_CH1_HORZFACT_REG Offset 0x208 Register Name DEFE_CH1_HORZFACT_REG Read W Default Bit Description rite Hex 31 24 FACTOR INT 23 16 RW 0x0 The integer part of the horizontal scaling ratio the horizontal scaling ratio input width output width FACTOR_FRAC 15 0 R W 0x0 The fractional part of the horizontal scaling ratio the horizontal scaling ratio input width output width 27 5 46 DEFE_CH1_VERTFACT_REG Offset 0x20C Register Name DEFE_CH1_VERTFACT_REG Bit Read W Default Description A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 300 Allwinner Technology
189. UART mode SIR MODE Disabled it is set whenever the serial input sin is held in a logic 0 state for longer than the sum of start time data bits parity stop bits If in infrared mode SIR MODE Enabled it is set whenever the serial input sir in is continuously pulsed to logic 0 for longer than the sum of start time data bits parity stop bits A break condition on serial input causes one and only one character consisting of all zeros to be received by the UART In the FIFO mode the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO Reading the LSR clears the BI bit In the non FIFO mode the BI indication occurs immediately 4 R 0 and persists until the LSR is read FE Framing Error 3 R 0 This is used to indicate the occurrence of a framing error in the A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 186 Allwinner Technology receiver A framing error occurs when the receiver does not detect a valid STOP bit in the received data In the FIFO mode since the framing error is associated with a character received it is revealed when the character with the framing error is at the top of the FIFO When a framing error occurs the UART tries to resynchronize It does this by assuming that the error occurs due to the start bit of the next character and then continues receiving t
190. UDF Green channel intensity 07 00 RW UDF Blue channel intensity In gamma correction mode the RAM array is used for gamma correction each pixel s alpha red green and blue color component is treated as an index into the SRAM array The corresponding Alpha red green or blue channel intensity value at that index is used in the actual color The following figure shows the RAM array used for gamma correction and the corresponding colors output A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 332 Allwinner Technology On chip SRAM array Inputting external frame buffer data av RO GO BO Output color OI R1 G1 B1 D 5 R38 G133 B28 0254 R254 G254 B254 0255 R255 G255 B255 On chip SRAM for gamma correction 28 6 Display Engine Memory Mapping Base Address BEO 0x01e60000 Offset 0x0000 Reserved 0x07FF 0x0800 Registers OxODFF 0x0E00 Reserved Ox3FFF 0x4000 Reserved 0x43FF 0x4400 Gamma Table 0x47FF 0x4800 HWC Memory Ox4BFF Bi 0x4C00 HWC Palette Table Ox4FFF 0x5000 PIPEO Palette Table 0x53FF 0x5400 PIPE1 Palette Table Ox57FF 0x5800 Reserved OxFFFF A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 333 Allwinner Technology 29 TCON 29 1 TCON Block Diagram MAX
191. USBPHY1 RST CTRL 1 RW 0x0 USB PHY1 iia Control 0 Reset valid 1 Reset invalid USBPHYO RST CTRL 0 RW oxo USB PHYO Bor Control 0 Reset valid 1 Reset invalid 6 4 31 DRAM CLK Default 0x00000000 Offset 0x100 Register Name DRAM_SCLK_CFG_REG Read W Default D Bit Description rite Hex 31 RW oxo EN Gating DRAM Clock for IEP 0 mask 1 pass 30 29 RW oxo ACE DOLK GATING Gating DRAM Clock for ACE 0 mask 1 pass 28 27 26 RW p PRD GATING Gating DRAM Clock for DE BE 0 mask 1 pass 25 RW o PE DELK GATING Gating DRAM Clock for DE_FE 0 mask 1 pass 24 23 16 15 14 7 6 5 R W 0x0 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 71 Allwinner Technology 4 3 R W 0x0 2 CSI DCLK GATING 1 R Ge Gating DRAM Clock for CSI 0 mask 1 pass VE DCLK GATING 2 deier Ge Gating DRAM Clock for VE 0 mask 1 pass 6 4 32 DE BE Clock Default 0x00000000 Offset 0x104 Register Name BE CFG REG Read W Default oe Bit i Description rite Hex SCLK GATING Gating Special Clock 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M BE_RST 30 R W 0x0 DE BE Reset 0 reset valid 1 reset invalid 29 26 CLK_SRC_SEL Clock Source Select 00 PL
192. V B coefficient the value equals to coefficient 2 9 30 2 21 CSC V B Constant Register Offset OXOOEC Register Name IMGEHC_CSCVBCON_REG Read Wr Default SC Bit Description ite Hex CSC VB CON 13 00 R V Ox2eb1 the V B constant the value equals to coefficient 2 30 2 22 DRC Spatial Coefficient Offset OXOOFO 0X00F8 Register Name IMGEHC_DRCSPACOFF Read Wr Default EES Bit Description ite Hex map p OoOo ae RW o Sits unsigned spatial coeficiertdaa 508 aw o 8 bis unsigned spatarcoeticient data 0700 aw o0 8 bis unsigned spatarcoeticient data 30 2 23 DRC Intensity Coefficient Offset 0X0100 OX01FC Register Name IMGEHC_DRCINTCOFF f Read Wr Default DE Bit Description ite Hex 2 RW o bis unsigned EE ER ag aw o 8 bis unsigned intensity coeficentdata SSSSSOSC S ang aw o 8 bis unsigned intensity coeficientdata SSSSSOSOSCS 0700 aw o0 8 bis unsigned intensity coeficentdata 30 2 24 DRC Luminance Gain Coefficient Offset 0X0200 0X03FC Register Name IMGEHC_DRCLGCOFF Read Wr Default SE Bit Description ite Hex 16bits luminance gain coefficient unsigned data 31 16 RW The high 5 bits is the integer part The low 11 bits is the decimal part 16bits luminance gain coefficient unsigned data 15 00 RW The high 5 bits is the integer part The low 11 bits is the decimal part A13 User Manual V1 3 Copyright 2013 Allwinner Technolog
193. VFS Voltage Change Error Pending 0 No effect 1 Pending Set one to this bit will clear it R W 0x0 DVFS_SPD_DET_ERR_IRQ_PEND DVFS Speed Detect Error IRQ Pending 0 No effect 1 Pending Set one to this bit will clear it 8 5 R W 0x0 VOLT_DET_FIN_IRQ_PEND Voltage Detect Finished IRQ Pending 0 No effect 1 Pending Set one to this bit will clear it R W 0x0 DVFS_CLK_SWT_FIN_IRQ_PEND DVFS Clock Switch Operation Finished IRQ Pending 0 No effect 1 Pending Set one to this bit will clear it R W 0x0 DVFS VOLT CHANGE FIN PEND DVFS Voltage Change Finished Pending 0 No effect 1 Pending Set one to this bit will clear it R W 0x0 DVFS_SPD_DET_FIN_IRQ_PEND DVFS Speed Detect Finished IRQ Pending 0 No effect 1 Pending Set one to this bit will clear it R W 0x0 DVFS_FIN_IRQ_PEND DVFS Finished IRQ Pending 0 No effect 1 Pending Set one to this bit will clear it A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 36 Allwinner Technology 5 3 10 PMU Status Register Offset 0x48 Register Name PMU STATUS REG Read W Default SE Bit 8 Description rite Hex 31 1 DVFS BUSY DVFS Busy 0 R W 0x0 0 no effect 1 DVFS is busy 5 3 11 PMU CPUVDD DCDC Control Register Addres
194. W Ox0 ADCO KEYDOWN EN ADC 0 Key Down Enable 0 Disable 1 Enable RW Ox0 ADCO DATA IRQ EN ADC 0 Data IRQ Enable 0 Disable 1 Enable 24 4 3 LRADC Interrupt Status Register Offset 0x08 Register Name LRADC INT Bit Read W Default Description rite Hex 31 8 12 0x0 ADC1_KEYUP_PENDING ADC 1 Key up pending Bit When general key pull up it the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 249 Allwinner Technology Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable 11 R W 0x0 ADC1_ALRDY_HOLD_PENDING ADC 1 Already Hold Pending Bit When hold key pull down and pull the general key down if the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled 10 R W 0x0 ADC1_HOLDKEY_PENDING ADC 1 Hold Key pending Bit When Hold key pull down the status bit is set and the interrupt line is set if the corresponding interrupt is enabled 0 NO IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable R W 0x0 ADC1_KEYDOWN_IRQ_PENDING ADC 1 Key Down IRQ Pending Bit When General key pull down the stat
195. W 0x0 Watchdog Interrupt Enable 0 No effect 1 watchdog Interval Value reached interrupt enable 7 6 TMR5 INT EN 5 R W 0x0 Timer 5 Interrupt Enable 0 No effect 1 Timer 5 Interval Value reached interrupt enable TMR4_INT_EN 4 R W 0x0 Timer 4 Interrupt Enable 0 No effect 1 Timer 4 Interval Value reached interrupt enable TMR3_INT_EN 3 R W 0x0 Timer 3 Interrupt Enable 0 No effect 1 Timer 3 Interval Value reached interrupt enable TMR2_INT_EN 2 R W 0x0 Timer 2 Interrupt Enable 0 No effect 1 Timer 2 Interval Value reached interrupt enable TMR1_INT_EN 1 R W 0x0 Timer 1 Interrupt Enable 0 No effect 1 Timer 1 Interval Value reached interrupt enable TMRO_INT_EN 0 R W 0x0 Timer 0 Interrupt Enable 0 No effect 1 Timer 0 Interval Value reached interrupt enable 11 3 2 ASYNC Timer IRQ Status Register Default 0x00000000 Offset 0x04 Register Name ASYNC_TMR_IRQ_STAS_REG A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 86 Allwinner Technology Read W Default Bit Description rite Hex 31 9 WDOG_IRQ_PEND 8 R W 0x0 Watchdog IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending Watchdog counter value is reached 7 6 TMR5 IRQ PEND 5 R W 0x0 Timer 5 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 5 counter valu
196. WART Register E 177 19 4 UART Register Descriptions star nn nn sante 177 19 4 1 UART Receiver Buffer Register An 177 19 4 2 UART Transmit Holding Register 178 19 4 3 UART Divisor Latch Low Register 178 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 10 Allwinner Technology 19 4 4 UART Divisor Latch High Register 179 19 4 5 VART Interrupt Enable Register An 179 19 4 6 UART Interrupt Identity Register 180 19 4 7 UART FIFO Control Register etset 181 19 4 8 UART Line Control Eeer 183 19 4 9 UART Modem Control Register LS SSL LR Rs 184 19 4 10 UART Line Status FEE Gundersens 185 19 4 11 UART Modem Status Register uunnamnmeneunetemtetnumenieeuenekneensletejedsknse 188 19 412 UART SGEN Register eege Ee 189 19413 UART Status e 190 19 4 14 UART Transmit FIFO Level Register 190 19 4 15 UART Receive FIFO Level Register 191 19416 UART Halt TX Register sereine Re ea e EEEE ia 191 19 5 UART Special PENE 191 19 5 1 fal FS 9 angela tere TE NER 191 20 CIR E E ann 192 20 1 e 192 20 2 GIR Register Det eene 192 20 3 CIR ele E nnns rasoaa dninni aE 192 20 3 1 CIR Control Register ee 192 20 3 2 CIR Receiver Re Ce 193 20 3 3 CIR Receiver FIFO Register ebe eise ten lan tn het aan tannins EE ie 193 20 3 4 CIR Receiver Interrupt Control Regist
197. WI Extend Address Register ennn 157 17 4 3 TL D t e IEC PRE amaaa naea araa a a aaea e aa aasa aa a araa a aana 157 17 4 4 TWI Control PGI EEE EEE ETE 157 17 4 5 TWI Status E E 159 17 4 6 TWI Clock Ee 160 17 4 7 TWI Soft Reset POS EE renee hep APIS PE emne Ein Aes 161 17 4 8 TWI Enhance Feature Register A 161 17 4 9 TWI Line Control US ua 161 124410 TYLDVPS Control reene 162 17 5 TWI Controller Special Requirement ss 162 17 5 1 TYPENE 162 17 5 2 TWI Controller Te nie RU Rte 162 UE ME 164 TO VE 164 18 2 SPI Timing Diagram su veeesesmsetentnenidsindemmdedndarndedadaedadededetsdedsdekedndedndedesendadedete 164 18 3 SPI Register lst ee 165 18 4 SPI Register Description E 166 18 4 1 SPI RA D ta Registi eorne eer 166 18 4 2 SPI TX Data e EE 166 18 4 3 SPIL FER ET ae 166 18 4 4 SPI Interrupt Control Register L nasnmanmsnsinininsamiinnaiianntanddnnntenedantendsenddenddnnedeee 168 18 4 5 SPI Interrupt Status Register NU 170 18 4 6 SPI DMA Control ROSE eebe keete 172 18 4 7 SPIWa it Clock FE EE 173 18 4 8 SPI Clock Control ss e Re ee ire ere mrt ener rereerie er renerreeee 173 18 4 9 SPI Burst Counter EE 174 18 4 10 SPI Transmit Counter Register umesamisk 174 18 4 11 SPI FIFO Status EE eet see enh anenee en ek 174 185 EC E 175 18 5 1 SPF LS hud 175 18 5 2 SPI Module Clock Source and Fr qu enev s ue atusudein 175 19 UART E 176 ER ESTE EEE 176 19 2 UART Timing Diagram sisi orren ern r nrs e etre 176 19 30
198. Window Width Control Register Register Name CSI WIN CTRL W REG fiset A 0X004 EE Default Value 0X00000000 Read Wr Default SC Bit Description ite Hex A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 273 Allwinner Technology ACTIVE LEN 28 16 RW 500 Horizontal pixel clock length Valid pixel clocks of a line ACTIVE_START 12 00 RW Horizontal pixel clock start Pixel data is valid from this clock 26 4 13 CSI Window Height Control Register Offset Address 0X0044 Register Name CSI WIN CTRL H REG er Default Value 0X00000000 Read Wr Default Kee Bit Description ite Hex pap p feme 28 16 0x1E0 ee Vertical line mea Aen Valid line number of a frame 12 00 RW Beni o Vertical line start data is valid from this line 26 4 14 CSI Buffer Length Register Register Name CSI BUF LEN REG ffset 0X0048 7 7 Read Wr Default a Bit Description ite Hex BUFF_LEN 12 00 R W 0x280 Buffer Length Buffer length of a line Unit is byte 26 5 CCIR656 Format 26 5 1 Header Data Bit Definition Data Bit First Word 0xFF REH ee Fourth Word CS D 7 MSB 1 0 0 1 CS Die 1 0 0 F CS DE 1 0 0 V CS D 4 1 0 0 H CS D 3 1 0 0 P3 CS D2 1 0 0 P2 CS D 1 1 0 0 P1 CS D 0 1 0 0 PO A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 274 Allwinner
199. YLINEWIDTH REG 0x840 0x84C DE layer frame buffer line width register DEBE_LAYFB_L32ADD_REG 0x850 0x85C DE layer frame buffer low 32 bit address register DE layer frame buffer high 4 bit address DEBE LAYFB H4ADD REG 0x860 register DEBE REGBUFFCTL REG 0x870 DE Register buffer control register DEBE CKMAX REG 0x880 DE color key MAX register DEBE CKMIN REG 0x884 DE color key MIN register DEBE CKCFG REG 0x888 DE color key configuration register DEBE ATTCTL REGO 0x890 0x89C DE layer attribute control registerO DEBE_ATTCTL_REG1 Ox8A0 0x8AC DE layer attribute control register DEBE HWCCTL REG 0x8D8 DE HWC coordinate control register DEBE HWCFBCTL REG Ox8E0 DE HWC frame buffer format register DEBE WBCTL REG Ox8F0 DEBE write back control register DEBE WBADD REG Ox8F4 DEBE write back address register DEBE i k ffer li idth DEBE_WBLINEWIDTH_REG 0x8F8 ME eee ee register DEBE i YUV ch l l DEBE_IYUVCTL_REG 0x920 Ek V K Channel conte register DEBE_IYUVADD_REG 0x930 0x938 DEBE YUV channel frame buffer address register DEBE_IYUVLINEWIDTH_REG 0x940 0x948 DEBE YUV channel buffer line width register DEBE_YGCOEF_REG 0x950 0x958 DEBE Y G coefficient register DEBE_YGCONS_REG 0x95C DEBE Y G constant register DEBE_URCOEF_REG 0x960 0x968 DEBE U R coefficient register DEBE URCONS REG 0x96C D
200. YUYV 09 08 RW 2 01 YVYU 10 UYVY 11 VYUY VSYNC_POL Vref polarity 0 negative 1 positive This register is not applied to CCIR656 interface HSYNC_POL Href polarity 0 negative 1 positive This register is not applied to CCIR656 interface A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 269 Allwinner Technology PCLK POL Data clock type 0 active in falling edge 1 active in rising edge 00 RW 0 26 4 3 CSI Capture Control Register GA Address 0Y0006 Register Name CSI CPT CTRL REG ER Default Value 0X00000000 Read Wr Default De Bit Description ite Hex VIDEO_CAP_CTRL Video capture control Capture the video image data stream 0 Disable video capture If video capture is in progress the CSI stops capturing image data at the end of the current frame and all of the current frame data is written to output FIFO 1 Enable video capture The CSI starts capturing image data at the start of the next frame STILL_CAP_CTRL Still capture control Capture a single still image frame 0 Disable still capture 1 Enable still capture The CSI module starts capturing image data at the start of the next frame The CSI module captures only one frame of image data This bit is self cleared and always reads as a 0 26 4 4 CSI FIFOO Buffer A Register ET Register Name CSI FIFOO BUF A ADDR REG SS Default Value 0X00000000 Read Wr Default SC Bit Descr
201. _REGO f Read W Default D Bit l Description rite Hex INT FFO Enables the fast forcing feature on the corresponding interrupt source 31 0 31 0 W 0x0 0 No effect 1 Forcing the corresponding interrupt Setting this bit can be valid only when the corresponding interrupt enable bit is set A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 113 Allwinner Technology 13 4 24 Interrupt Fast Forcing Register 1 Default 0x00000000 Offset 0x74 Register Name INTC FORCE REG1 Read W Bit rite Default Hex Description 31 0 W 0x0 INT_FF1 Enables the fast forcing feature on the corresponding interrupt source 63 32 0 No effect 1 Forcing the corresponding interrupt Setting this bit can be valid only when the corresponding interrupt enable bit is set 13 4 25 Interrupt Fast Forcing Register 2 Default 0x00000000 Offset 0x78 Register Name INTC_FORCE_REG2 Read W Bit rite Default Hex Description 31 0 W 0x0 INT_FF2 Enables the fast forcing feature on the corresponding interrupt source 95 64 0 No effect 1 Forcing the corresponding interrupt Setting this bit can be valid only when the corresponding interrupt enable bit is set 13 4 26 Interrupt Source Priority 0 Register Default 0x00000000 Offset 0x80 Register Name INTC_SRC_PRIO_REGO Read
202. acent pixels and the fractional part to choose the filter coefficients which generate the output value from the adjacent pixels This could be done by generating the output pixel X and Y numbers and dividing each by its associated scale factor A line may start and or end at the edge of the input image In this case you should use mirroring data shown in follow figure 6 E D eng N Mirroring data TO TI T2 T3 Start of a line SS New data position Xo 7 Xoo DS Xoi Xo Yn kal TO EE dg New data position qd a E a End of a column Mirroring data ERT 24 The scaler uses a 16 bit integer and a16 bit fractional value for the X and Y increment values This allows a fractional value resolution of 1 64K Only the most significant 5 bits of the fractional value are used by the filter coefficient RAMs 27 3 3 Scaling Filter New pixels are generated by interpolation or filtering of the original pixels Interpolation is the weighted average of the input pixels adjacent to the output pixel Filtering extends interpolation to include input pixels beyond the input pair adjacent to the output pixel The number of pixels used to generate the output defines the filter type Interpolation is a 2 tap filter A tap is equivalent to an original un scaled pixel of data A 4 tap filter would use the two pixels to the left and the two pixels to the right of the output pixel Following is the scaling algorithm A13 User Man
203. ad W rite Default Hex Description 31 RW Ox0 SYNC_TMR1_TEST Sync timer1 test mode In test mode the low register should be set to 0x1 the high register will down count The counter needs to be reloaded 0 normal mode 1 test mode 30 8 R W 0x0 STMR1_MODE Sync Timer1 mode 0 Continuous mode When reaches the internal value the timer will not be disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically Sync Timer 1 Clock Source is fixed to AHBCLK 6 4 R W 0x0 STMR1 CLK SRC Select the pre scale of the sync timer 1 clock source 000 1 001 2 010 4 011 8 100 16 101 110 111 3 2 R W 0x0 STMR1_RELOAD Sync Timer 1 Reload 0 No effect 1 Reload timer 1 Interval value R W 0x0 STMR1_EN Sync Timer 1 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 103 Allwinner Technology If the current counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be mod
204. als to coefficient 2 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 301 Allwinner Technology TAP2 23 16 RW 0x0 Horizontal tap2 coefficient The value equals to coefficient 2 TAP1 15 8 R W 0x0 Horizontal tap1 coefficient The value equals to coefficient 29 TAPO 7 0 R W 0x0 Horizontal tap0 coefficient The value equals to coefficient 2 27 5 51 DEFE_CHO_VERTCOEF_REGN N 0 31 Offset 0x500 N 4 Register Name DEFE CHO VERTCOEF REGN Read W Default Bit Description rite Hex TAP3 31 24 RW 0x0 Vertical tap3 coefficient The value equals to coefficient 2 TAP2 23 16 RW 0x0 Vertical tap2 coefficient The value equals to coefficient 2 TAP1 15 8 R W 0x0 Vertical tap1 coefficient The value equals to coefficient 2 TAPO 7 0 R W 0x0 Vertical tap0 coefficient The value equals to coefficient 2 27 5 52 DEFE_CH1_ HORZCOEFO REGN N 0 31 Offset 0x600 N 4 Register Name DEFE CH HORZCOEFO REGN Read W Default Bit Description rite Hex TAP3 31 24 RW 0x0 Horizontal tap3 coefficient The value equals to coefficient 2 TAP2 23 16 RW 0x0 Horizontal tap2 coefficient The value equals to coefficient 29 TAP1 15 8 R W 0x0 Horizontal tap1 coefficient The value equals to coefficient 29 TAPO 7 0 R W 0x0 Horizontal tap0 coefficient The value equals to coefficient
205. annel 2 0x938 Read Wr Default SC Bit i Description ite Hex IYUV ADD 31 0 RM UDF Buffer Address Frame buffer address in BYTE 28 5 23 DEBE YUV Channel Butter Line Width Register Offset Channel 0 0x940 Channel 1 0x944 Channel 2 0x948 Read Wr Default Ss Bit i Description ite Hex Register Name DEBE_IYUVADD_REG Register Name DEBE_IYUVLINEWIDTH_REG IYUV_LINEWIDTH Line width 31 0 R W UDF The width is the distance from the start of one line to the start of the next line Description in bits YUV to RGB conversion algorithm formula R R Y component coefficient Y R U component coefficient U R V component coefficient V R constant G G Y component coefficient Y G U component coefficient U G V component coefficient V G constant A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 324 Allwinner Technology B B Y component coefficient Y B U component coefficient U B V component coefficient V B constant 28 5 24 DEBE Y G Coefficient Register Offset G Y component 0x950 R U component 0x954 B V component 0x958 Read Wr Default Bit Description ite Hex Register Name DEBE YGCOEF REG IYUV YGCOEF the Y G coefficient the value equals to coefficient 2 9 28 5 25 DEBE Y G Constant Register Offset 0x95C Register Name DEBE YGCONS REG Read Wr Defaul
206. ary and sent a SOF but before HC reads the first ED in that Frame After writing to HCCA HC will 15 0 R R W 0x0 set the StartofFrame in HclnterruptStatus 22 6 17 HcPeriodicStart Register Offset 0x440 Register Name HcPeriodicStatus Default Value 0x0 Read Write Bit HCD HC Default Description 31 14 Reserved 13 0 R W 0x0 PeriodicStart After hardware reset this field is cleared This is then set by HCD during the HC initialization The value is calculated roughly as 10 off from HcFminterval A typical value will be Ox2A3F When HcFmRemaining reaches the value specified processing of the periodic lists will have priority over Control Bulk processing HC will therefore start processing the Interrupt list after completing the current Control or Bulk transaction that is in progress A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 225 Allwinner Technology 22 6 18 HcLSThreshold Register Offset 0x444 Register Name HcLSThreshold Default Value 0x0628 Read Write Bit HCD HC Default Description 31 12 Reserved LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction The transaction is started only if FrameRemaining 3 this field The value is calculated by 11 0 RW R 0x0628 HCD with the consideratio
207. as output the pin state is the same A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 379 Allwinner Technology as the corresponding bit The read bit value is the value setup by software If the port is configured as functional pin the undefined value will be read 33 4 24 PD Multi Driving Register 0 Register Name PD DRVO Offset 0x80 Default Value 0x5555 5555 Bit Read Write Default Description PD n Multi Driving Select n 0 15 2i 1 2i 00 Level 0 01 Level 1 i 0 15 RAV Ox1 10 Level 2 11 Level 3 33 4 25 PD Multi Driving Register 1 Register Name PD_DRV1 Offset 0x84 Default Value 0x0055 5555 Bit Read Write Default Description 31 24 PD n Multi Driving Select n 16 27 2i 1 2i 00 Level 0 01 Level 1 i 0 11 RW 0x1 10 Level 2 11 Level 3 33 4 26 PD Pull Register 0 Register Name PD_PULLO Offset 0x88 Default Value 0x0000 0000 Bit Read Write Default Description PD n Pull up down Select n 0 15 2i 1 2i 00 Pull up down disable 01 Pull up i 0 15 RW 0x0 10 Pull down 11 Reserved 33 4 27 PD Pull Register 1 Register Name PD_PULL1 Offset 0x8C Default Value 0x0000 0000 Bit Read Write Default Description 31 24 PD n Pull up down Select n 16 27 2i 1 2i 00 Pull up down disable 01 Pull up enable i
208. assumed to be the last byte After this byte is transmitted the TWI will enter state C8h then return to the idle state Status code F8h when INT_FLAG is cleared The TWI will not respond as a slave unless A_ACK is set 1 0 17 4 5 TWI Status Register Offset 0x10 Register Name TWI_STAT Default Value 0x0000 00F8 Bit Read Write Default Description 31 8 7 0 OxF8 Status Information Byte Code Status 0x00 Bus error 0x08 START condition transmitted 0x10 Repeated START condition transmitted 0x18 Address Write bit transmitted ACK received 0x20 Address Write bit transmitted ACK not received 0x28 Data byte transmitted in master mode ACK received 0x30 Data byte transmitted in master mode ACK not received 0x38 Arbitration lost in address or data byte 0x40 Address Read bit transmitted ACK received 0x48 Address Read bit transmitted ACK not received 0x50 Data byte received in master mode ACK transmitted 0x58 Data byte received in master mode not ACK transmitted 0x60 Slave address Write bit received ACK transmitted 0x68 Arbitration lost in address as master slave address Write bit received ACK transmitted 0x70 General Call address received ACK transmitted 0x78 Arbitration lost in address as master General Call address A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved
209. at the peripheral transmits and receives The number of bit that may be selected areas follows 00 5 bits 01 6 bits 10 7 bits 11 8 bits 19 4 9 UART Modem Control Register Offset 0x10 Register Name UART_MCR Default Value 0x0000 0000 Bit Read Write Default Description 31 7 SIRE SIR Mode Enable 0 IrDA SIR Mode disabled 1 IrDA SIR Mode enabled AFCE Auto Flow Control Enable When FIFOs are enabled and the Auto Flow Control Enable AFCE bit is set Auto Flow Control features are enabled 0 Auto Flow Control Mode disabled 1 Auto Flow Control Mode enabled LOOP Loop Back Mode 0 Normal Mode 1 Loop Back Mode This is used to put the UART into a diagnostic mode for test purposes H operating in UART mode SIR MODE Enabled or not active MCR 6 set to zero data on the sout line is held high A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 184 Allwinner Technology while serial data output is looped back to the sin line internally In this mode all the interrupts are fully functional Also in loopback mode the modem control inputs dsr n cts_n ri n dcd_n are disconnected and the modem control outputs dir n rts n out n out2 n are looped back to the inputs internally If operating in infrared mode SIR MODE Enabled AND active MCR 6 set to one data on the sir out n line
210. ata samples to increase the sampling rate Down sampling is the process of reducing the sampling rate by removing or throwing away original data samples In order to generate the output pixels one first needs to relate the output grid to the input grid Scaling is a pixel transformation in which an array of output pixels is generated from an array of input pixels The value of each pixel on the output pixel grid is calculated from the values of its adjacent pixels on the input grid To find these adjacent pixels the output grid needs to be overlaid on the input grid and the starting pixels XOYO of the two grids are alignd To identify the adjacent input pixels for a given output pixel the output pixel X pixel number along the output line and Y pixel line number within window should be divided by their corresponding scaling factors Xout Xin horizontal scaling factor where horizontal scaling factor input length output length Yout Yin vertical scaling factor where vertical scaling factor input height output height Note that the resulting Xin and Yin values will be real numbers because the output pixels will usually fall between the input pixels The fractional portion indicates the fractional distance to the next pixel To calculate the output pixel value you use the value for the nearest pixel to the left and above and combine it with the value of the other adjacent pixel s For example horizontal interpolation uses th
211. back error status de R oxo 0 valid write back 1 un valid write back This bit is cleared through writing 0 to reset start bit in frame control register COEF_ACCESS_STATUS Fir coef access status 0 scaler module can access fir coef RAM 11 R 0x0 1 CPU can access fir coef ram This bit must be 1 before CPU accesses fir coef RAM When this bit is 1 scaler module will fetch 0x00004000 from RAM 10 6 LCD_FIELD 6 R oxo LCD field status 0 top field 1 bottom field DRAM STATUS Access dram status 4 R 0x0 0 idle 1 busy This flag indicates whether DEFE is accessing dram 3 CFG_PENDING Register configuration pending 0 no pending 2 R 0x0 1 configuration pending This bit indicates the registers for the next frame has been configured This bit will be set when configuration ready bit is set and this bit will be cleared when a new frame process begins WB_STATUS Write back process status 0 write back end or write back disable 1 R 0x0 1 write back in process This flag indicates that a full frame has not been written back to memory The bit will be set when write back enable bit is set and be cleared when write back process ends A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 294 Allwinner Technology FRM_BUSY Frame busy 0 R 0x0 This flag indicates that the frame is being processed The bit will be set when frame process reset amp start is set and be
212. bit is cleared automatically writing a 0 to this bit has no effect INT_FLAG Interrupt Flag INT_FLAG is automatically set to 1 when any of 28 out of the possible 29 states is entered see STAT Register below The only state that does not set INT_FLAG is state F8h If the INT_EN bit is set the interrupt line goes high when IFLG is set to 1 If the TWI is operating in slave mode data transfer is suspended when INT_FLAG is set and the low period of the two wire bus clock line SCL is stretched until 0 is written to INT FLAG The 2 wire clock line is then released and the interrupt line goes low A_ACK Assert Acknowledge When A_ACK is set to 1 an Acknowledge low level on SDA will A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 158 Allwinner Technology be sent during the acknowledge clock pulse on the two wire bus if 1 Either the whole of a matching 7 bit slave address or the first or the second byte of a matching 10 bit slave address has been received 2 The general call address has been received and the GCE bit in the ADDR register is set to 1 3 data byte has been received in master or slave mode When A_ACK is 0 a Not Acknowledge high level on SDA will be sent when a data byte is received in master or slave mode If A_ACK is cleared to 0 in slave transmitter mode the byte in the DATA register is
213. bus which dictates the communications method Master Transmit Master Receive Slave Transmit and Slave Receive In general CPU host controls TWI by writing commands and data to its registers The TWI interrupts the CPU host for the attention each time a byte transfer is done or a START STOP condition is detected The CPU host can also poll the status register for current status if the interrupt mechanism is not disabled by the CPU host When the CPU host wants to start a bus transfer it initiates a bus START to enter the master mode by setting IM_STA bit in the 2WIRE_CNTR register to high before it must be low The TWI will assert INT line and INT_FLAG to indicate a completion for the START condition and each consequent byte transfer At each interrupt the micro processor needs to check the 2WIRE_STAT register for current status A transfer has to be concluded with STOP condition by setting M_STP bit high In Slave Mode the TWI also constantly samples the bus and look for its own slave address during addressing cycles Once a match is found it is addressed and interrupts the CPU host with the corresponding status Upon request the CPU host should read the status read write 2WIRE_DATA data register and set the 2WIRE_CNTR control register After each byte transfer a slave device always halt the operation of remote master by holding the next low pulse on SCL line until the microprocessor responds to the status of previous byte transfer or START condit
214. ce Low Resolution Analog to A module which can transfer analo 15 LRADC esoe 3 DR A Digital Converter signal to digital signal The hardware block that interfaces with different image sensor interfaces and 16 CSI CMOS Sensor Interface g provides a standard output that can be used for subsequent image processing A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 3 Allwinner Technology Table of Contents Revision History seesesevvenvnreneveenenenneneneeneneenenenneneneensnennenennenenennenenneneneeneneenenennenensenenennenennenenevneneenenenneneneeneneenee 1 Technical RE 2 SLET EE NN MM iisa 22 NNER gt NM SE 22 2 Pin Description seseseevesvnrenvveeneneunenenevnennenenenneneneenenennenennenenevnennenenenneneneenenennenennenenennennenenenseneneeneveenenenee 25 21 Pin Plat ment Fables sans nant A RAR RAR hehehe eben 25 22 PinDbeial DESCrPION merere s e a e E a ec E e 25 ONE TT 26 3 1 Functional Block Diagram sise 26 3 22 Memory Mapping RER RM RER RIRE ARR EE 26 4 Boot System E 30 A Ee ee 30 42 gt 916 9B e E 30 5 UE 31 SN st eee 31 5 2 PMU Register Listen amenant ae EES 31 5 3 PMU Register Description ss 32 5 3 1 PMU DVFS Control Register E 32 5 3 2 PMU DVFS Control Register 1 Default OsO00O0O 1 0101 33 5 3 3 PMU DVFS Control Register acc nae end 33 5 3 4 PMU AXI Clock Range FEE E 34 5 3 5 PMU AXI Clock Range Register E 34 5 3 6 PMU DVFS Contr
215. chnology 10 Pull down 11 Reserved 33 4 10 PC Configure Register 0 Register Name PC CFGO Offset 0x48 Default Value 0x0000 0000 Bit Read Write Default Description 31 PC7 Select 000 Input 001 Output 010 NRB1 011 SDC2_CLK 100 101 30 28 R W 0 110 111 27 PC6 Select 000 Input 001 Output 010 NRBO 011 SDC2 CMD 100 101 26 24 R W 0 110 111 23 PC5 Select 000 Input 001 Output 010 NRE 011 100 101 22 20 R W 0 110 111 19 PC4 Select 000 Input 001 Output 010 NCEO 011 100 101 18 16 R W 0 110 111 15 PC3 Select 000 Input 001 Output 010 NCE1 011 SPIO_CSO 100 101 14 12 R W 0 110 111 11 PC2 Select 000 Input 001 Output 010 NCLE 011 SPIO_CLK 100 101 10 8 R W 0 110 111 7 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 372 Allwinner Technology PC1 Select 000 Input 001 Output O10 NALE 011 SPIO_MISO 100 101 6 4 R W 0 110 111 3 PCO Select 000 Input 001 Output 010 NWE 011 SPIO_MOSI 100 101 2 0 R W 0 110 111 33 4 11 PC Configure Register 1 Register Name PC_CFG1 Offset 0x4C Default Value 0x0000 0000 Bit Read Write Default Description 31 PC15 Select 000 Input 001 Output 010 NDQ7 011 SDC2 D7 100
216. cleared when frame process is reset or disabled 27 5 22 DEFE_CSC_COEF00 REG Offset 0x70 Register Name DEFE_CSC_COEF00_REG Read W Default Bit Description rite Hex 31 13 COEF 12 0 R W 0x0 the Y G coefficient the value equals to coefficient 2 27 5 23 DEFE CSC COEFO1 REG Offset 0x74 Register Name DEFE CSC COEFO1 REG Read W Default Ke Bit i Description rite Hex 31 13 COEF 12 0 R W 0x0 the Y G coefficient the value equals to coefficient 2 27 5 24 DEFE_CSC_COEF02_REG Offset 0x78 Register Name DEFE_CSC_COEF02_REG Read W Default Kar Bit f Description rite Hex 31 13 COEF 12 0 R W 0x0 the Y G coefficient the value equals to coefficient 2 27 5 25 DEFE_CSC_COEF03 REG Offset Ox7C Register Name DEFE_CSC_COEF03_REG Read W Default SC Bit Description rite Hex 31 14 CONT 13 0 R W 0x0 the Y G constant the value equals to coefficient 2 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 295 Allwinner Technology 27 5 26 DEFE CSC COEF10 REG Offset 0x80 Register Name DEFE CSC COEF10 REG Read W Default echt Bit i Description rite Hex 31 13 COEF 12 0 R W 0x0 the U R coefficient the value equals to coefficient 2 27 5 27 DEFE CSC COEF11 REG
217. controller System Peripherals A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 23 Allwinner Technology e 8 channels normal DMA and 8 channels dedicated DMA Internal 48K SRAM on chip 6 asynchronic timers 2 synchronic timers 1 watchdog and 2 AVS counters Security System Crypto Engine Support DES 3DES AES encryption and decryption Support SHA 1 MD5 message digest 160 bit hardware PRNG with 192 bit seed 128 bit EFUSE chip ID Package eLQFP176 package A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 24 Allwinner Technology 2 Pin Description 2 1 Pin Placement Table Refer to A13 Datasheet for details 2 2 Pin Detail Description Refer to A13 Datasheet for details A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 25 Allwinner Technology 3 Architecture 3 1 Functional Block Diagram t AN 4 Figure3 1 A13 Block Diagram 3 2 Memory Mapping Module Address Size Bytes SRAM A1 0x0000 0000 0x0000 3FFF 16K SRAM A2 0x0000 4000 0x0000 7FFF 16K SRAM A3 0x0000 8000 0x0000 B3FF 13K SRAM A4 0x0000 B400 0x0000 BFFF 3K SRAM NAND 2K SRAM D 0x0001 0000 0x0001 OFFF 4K SRAM Controller 0x01C0 0000 0x01C0 OFFF 4K DRAM Controller 0x01C0 1000 0x01C0 1FFF 4K DMA 0x01C0 2000 0x01C0 2FFF 4K NFC 0x01C0 30
218. d and the loading is done the bit will be cleared automatically DRC DB EN DRC double buffer function enable control 0 disable 1 enable LGC Luminance Gain Coefficient 30 2 4 DRC External LGC Start Address Register Offset 0X0014 Register Name IMGEHC_DRCLGC_STAADD_REG f Read Wr Default Wi Bit Description ite Hex 31 00 RW PRE EGG STAND Start address in byte Double buffered register of DRC double buffer function is controlled by DRC DB EN and DRC_DBRDY_CTL bits 30 2 5 DRC Setting Register Offset 0X0018 Register Name IMGEHC DRC SET REG HEGE Poa Description ORG GAN AUTOLSAD BIS Only valid when the module is enabled and MOD is DRC mode or the bit is ignored If the auto load function is enabled the DRC luminance gain coefficient will be auto loaded from the external appointed memory address when the SYNC signal LCD SYNC signal is coming A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 351 Allwinner Technology otherwise ignore the auto load function About the calculating way of the external appointed memory address refer to the DRC external LGC start address register 0 Enable the auto load function 1 Disable the auto load function am ew ow ERR DRC_LGC_ABSLUMPERVAL 1508 08 Abs luminance percent value foo fr krem O EN DRC ADJUST EN 01 R W 0x00 0 disable 1 enable DRC_LGC_ABSLUMSHF RW 0x00 Abs oranan shift bits 0 shift 8bits 1 shif
219. d automatically Timer 0 Clock Source is fixed to AHBCLK 6 4 RW Ox0 STMRO CLK Select the pre scale of the sync timer 0 clock source 000 1 001 2 010 4 011 8 100 16 101 110 111 R W 0x0 STMRO_RELOAD A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 101 Allwinner Technology Sync Timer 0 Reload 0 No effect 1 Reload timer 0 Interval value R W 0x0 STMRO EN Sync Timer 0 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time 12 3 4 Sync Timer 0 Interval Value Low Register Offset 0x14 Register Name SYNC TMRO INTV LO REG Bit Read W rite Default Hex Description 31 0 RW X STMRO INTV VALUE LO Sync Timer 0 Interval Value 31 0 12 3 5 Sync Timer 0 Interval Value High
220. defined Note Writes must be Dword Writes 22 5 11 EHCI Current Asynchronous List Address Register Register Name ASYNCLISTADDR Offset 0x28 Default Value Undefined Bit Read Write Default Description Link Pointer LP This field contains the address of the next asynchronous queue head to be executed These bits correspond to memory address signals 31 5 31 5 R W respectively Reserved These bits are reserved and their value has no effect on operation Bits in this field cannot be modified by system software and will 4 0 always return a zero when read Note Write must be DWord Writes 22 5 12 EHCI Configure Flag Register Register Name CONFIGFLAG Offset 0x50 Default Value 0x00000000 Bit Read Write Default Description Reserved 31 1 0 These bits are reserved and should be set to zero Configure Flag CF Host software sets this bit as the last action in its process of configuring the Host Controller This bit controls the default port routing control logic as follow Value Meaning 0 Port routing control logic default routs each port to an implementation dependent classic host controller 1 Port routing control logic default routs all ports to this host controller 0 R W 0 The default value of this field is 0 Note This register is not use in the normal implementation 22 5 13 EHCI Port Status and Control
221. dicListEnable This bit is set to enable the processing of periodic list in the next Frame If cleared by HCD processing of the periodic list does not occur after the next SOF HC must check this bit before it starts processing the list 1 0 R W R 0x0 ControlBulkServiceRatio This specifies the service ratio between Control and Bulk EDs Before processing any of the nonperiodic lists HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed in determining whether to continue serving another Control ED or switching to Bulk EDs The internal count will be retained when crossing the frame boundary In case of reset HCD is responsible for restoring this value CBSR No of Control EDs Over Bulk EDs Served 0 1 1 1 2 1 2 3 1 3 4 1 The default value is 0x0 22 6 3 HcCommandStatus Register Offset 0x408 Register Name HcCommandStatus Default Value 0x0 Read Write Bit HCD HC Default Description 31 18 0x0 Reserved SchedulingOverrunCount These bits are incremented on each scheduling overrun error It is initialized to 00b and wraps around at 11b This will be incremented when a scheduling overrun is detected even if SchedulingOverrun in HclnterruptStatus has already been set This is used by HCD to 17 16 R R W 0x0 monitor any persistent scheduling problem A13 User Manual V1 3
222. dicates the number of micro frames a host controller can hold a set of isochronous data structures one or more before flushing the state When bit 7 is a one then host software assumes the host controller may cache an isochronous data structure for an entire frame Reserved These bits are reserved and should be set to zero Asynchronous Schedule Park Capability If this bit is set to a one then the host controller supports the park feature for high speed queue heads in the Asynchronous Schedule The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register Programmable Frame List Flag If this bit is set to a zero then system software must use a frame list length of 1024 elements with this host controller The USBCMD register Frame List Size field is a read only register and should be set to Zero If set to 1 then system software can specify and use the frame list in the USBCMD register Frame List Size field to cofigure the host controller The frame list must always aligned on a 4K page boundary This requirement ensures that the frame list is always physically contiguous R Reserved These bits are reserved for future use and should return a value of zero when read 22 5 5 EHCI Companion Port Route Description Register Name HCSP PORTROUTE Offset O
223. ding Status Register Default 0x00000000 Offset 0x04 Register Name DMA IRQ PEND STAS REG Bit Read W rite Default Hex Description 31 RW Ox0 DDMA7 END IRQ PEND Dedicated DMA 7 End Transfer Interrupt Pending clearit 0 No effect 1 Pending Set 1 to the bit will 30 RW Ox0 DDMA7 HF IRQ PEND Dedicated DMA 7 Half Transfer Interrupt Pending clear it 0 No effect 1 Pending Set 1 to the bit will 29 R W 0x0 DDMA6 END IRQ PEND Dedicated DMA 6 End Transfer Interrupt Pending clear it 0 No effect 1 Pending Set 1 to the bit will 28 RW Ox0 DDMA6 HF IRQ PEND Dedicated DMA 6 Half Transfer Interrupt Pending clear it 0 No effect 1 Pending Set 1 to the bit will 27 RW Ox0 DDMA5 END IRQ PEND Dedicated DMA 5 End Transfer Interrupt Pending clear it 0 No effect 1 Pending Set 1 to the bit will 26 RW Ox0 DDMA5 HF IRQ PEND Dedicated DMA 5 Half Transfer Interrupt Pending clear it 0 No effect 1 Pending Set 1 to the bit will 25 R W 0x0 DDMA4_END_IRQ_PEND Dedicated DMA 4 End Transfer Interrupt Pending clear it 0 No effect 1 Pending Set 1 to the bit will 24 R W 0x0 DDMA4_HF_IRQ_PEND A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 134 Allwinner Technology Dedicated DMA 4 Ha
224. dle mode and this bit is set the ccu will auto switch the CPU clock divide ratio from 8 to 1 with 4 steps 6 3 CPU IDLE CNT EN CPU idle counter enable 2 R W 0x0 0 disable 1 enable CPU IDLE RL EN 1 RW oxo CPU idle Counter Read Latch Enable 0 no effect 1 to latch the idle Counter to the Low Hi registers and it will change to zero after the registers are latched CPU_IDLE_CNT_CLR_EN 0 RW 0x0 CPU idle Counter Clear Enable 0 no effect 1 to clear the idle Counter Low Hi registers and it will change to zero after the registers are cleared 5 3 44 CPU Idle Status Register Default 0x00000000 Offset OxFC Register Name CPU IDLE STATUS REG f Read W Default Bit Description rite Hex 31 1 CPU_IDLE_STA CPU idle exit finished pending 0 R W 0x0 0 no effect 1 idle exit finished Set 1 to this bit will clear it A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 47 Allwinner Technology 6 Clock Control Module CCM 6 1 Overvi ew The Clock Control Module CCM is made up of 7 PLLs a Main Oscillator and an on chip RC Oscillator The 24 MHz crystal is mandatory and to generate input clock source for PLLs and main digital blocks In order to provide high performance low power consumption and user friendly interfaces the chip includes several clock domains CPU clock AHB clock APB clock and special clock See details in the follow
225. ds to the first bit received from the two wire bus If GCE is set to 1 the TWI will also recognize the general call address 00h For 10 bit addressing When the address received starts with 11110b the TWI recognizes this as the first part of a 10 bit address and if the next two bits match ADDR 2 1 i e SLAX9 and SLAX8 of the device s extended address it sends an ACK The device does not generate an interrupt at this point If the next byte of the address matches the XADDR register SLAX7 SLAXO the TWI generates an interrupt and goes into slave mode 17 4 2 TWI Extend Address Register Register Name TWI XADDR Offset 0x04 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 SLAX Extend Slave Address 7 0 R W 0 SLAX 7 0 17 4 3 TWI Data Register Register Name 2WIRE_DATA Offset 0x08 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 7 0 R W 0 Data byte for transmitting or receiving 17 4 4 TWI Control Register Register Name TWI CNTR Offset 0xOC Default Value 0x0000 0000 Bit Read Write Default Description 31 8 INT EN Interrupt Enable 1 b0 The interrupt line always low 7 R W 0 1 b1 The interrupt line will go high when INT FLAG is set 6 R W 0 BUS EN A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 157 All
226. duling Overrun 22 6 6 HcinterruptDisable Register Offset 0x414 Register Name HcinterruptDisable Register Default Value 0x0 Read Write Bit HCD HC Default Description MasterInterruptEnable A written 0 to this field is ignored by HC A 1 written to this field disables interrupt generation due events specified in the other bits 31 RW R 0x0 of this register This field is set after a hardware or software reset 30 7 0x00 Reserved RootHubStatusChange Interrupt Disable 0 Ignore 6 RW R 0x0 1 Disable interrupt generation due to Root Hub Status A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 220 Allwinner Technology Change FrameNumberOverflow Interrupt Disable 0 Ignore 1 Disable interrupt generation due to Frame Number Over 5 RW IR 0x0 Flow UnrecoverableError Interrupt Disable 0 Ignore 4 RW R 0x0 1 Disable interrupt generation due to Unrecoverable Error ResumeDetected Interrupt Disable 0 Ignore 3 RW R 0x0 1 Disable interrupt generation due to Resume Detected StartofFrame Interrupt Disable 0 Ignore 2 RW R 0x0 1 Disable interrupt generation due to Start of Flame WritebackDoneHead Interrupt Disable 0 Ignore 1 Disable interrupt generation due to Write back Done 1 RW R 0x0 Head SchedulingOverrun Interrupt Disable 0 Ignore 0 RAW R 0x0 1
227. e 0x0 TP_UP_PENDING Touch Panel Last Touch Stylus Up IRQ Pending bit 0 No IRQ 1 IRQ Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable 0x0 TP_DOWN_PENDING Touch Panel First Touch Stylus Down IRQ Pending bit 0 No IRQ 1 IRQ Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable 25 6 7 Common Data Register Offset 0x1c Register Name TP_CDAT Bit Read W Default Description A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 264 Allwinner Technology rite Hex 31 12 11 0 R W 0x0 TP_CDAT TP Common Data 25 6 8 TP Data Register Offset 0x24 Register Name TP_DATA Bit Read W Default Description rite Hex 31 12 7 11 0 R 0x0 TP_DATA Touch Panel X Y data or Auxiliary analog input data 25 6 9 TP Port IO Configure Register Offset 0x28 Register Name TP_IO_CONFIG Bit Read W Default Description rite Hex 31 15 14 12 RW 0x2 TY_N_SELECT TY_N Port Function Select 000 Input 001 Output 010 TP_YN 011 100 101 110 111 11 10 8 R W 0x2 TY_P_SELECT TY_P Port Function Select 000 Input 001 Output 010 TP_YP 011 100 101 110 111 7 6 4 R W 0x2 TX_N_SELECT TX_P Por
228. e Hex 31 29 28 R W 0x0 STIMER_AHB_GATING A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 62 Allwinner Technology Gating AHB Clock for Sync timer 0 mask 1 pass 27 26 R W 0x0 25 23 PI2_AHB l 22 R W 0x0 S om NG Gating AHB Clock for SPI2 0 mask 1 pass DI AHB GATING 21 R W 0x0 SPH G a Gating AHB Clock for SPI1 0 mask 1 pass SPIO AHB GATING 20 RW 0x0 Gating AHB Clock for SPIO 0 mask 1 pass 19 18 R W 0x0 17 R W 0x0 16 15 SDRAM_AHB_GATING 14 R W 0x0 Gating AHB Clock for SDRAM 0 mask 1 pass NAND_AHB_GATING 13 R W 0x0 Gating AHB Clock for NAND 0 mask 1 pass 12 R W 0x0 11 SD2_AHB_GATING 10 R W 0x0 S Gating AHB Clock for SD MMC2 0 mask 1 pass SD1 AHB GATING 9 R W 0x0 x Gating AHB Clock for SD MMC1 0 mask 1 pass SDO AHB GATING 8 R W 0x0 IW Gating AHB Clock for SD MMCO 0 mask 1 pass BIST_AHB_GATING 7 R W 0x0 S J G Gating AHB Clock for BIST 0 mask 1 pass DMA_AHB_GATING 6 R W 0x0 f Gating AHB Clock for DMA 0 mask 1 pass SS_AHB_GATING 5 R W 0x0 7 Gating AHB Clock for SS 0 mask 1 pass 4 3 OHCI_AHB_GATING 2 R W 0x0 x Gating AHB Clock for USB OHCI 0 mask 1 pass 1 RW ER ENG Gating AHB Clock for USB EHCI
229. e starting pixel to the left interpolated with the next pixel to the right with the fractional value used to determine the weighting for the interpolation 27 3 2 Quantizing The new position is forced to be at a location n 32 in H and V relative to the position of the original pixel grid Line TapO Tap1 Tap2 Tap3 ee O O O O 0 7 15 23 31 Line n O X Pixel Location Line n2 O Horizontal quantizing Tap3 Line n3 O O Vertical quantizing The relation between each output pixel location the input pixel grid is X location of output pixel XO of input line output pixel number X Scale Factor Y location of output pixel YO of input window output line number Y scale factor The X and Y locations may not be integer values which depend on the scale factor The resulting X and Y pixel locations can be separated into an integer and a fractional part The integer part of the X and Y location selects the pixel and line number closest to the output pixel respectively The A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 277 Allwinner Technology fractional part gives the fractional distance of the output pixel to the next X and Y input pixel values These fractional parts are the a and values shown in scaling algorithm diagram To perform scaling the X and Y locations of the output pixel relating to the input pixel grid must be generated This includes both the integer part to locate the adj
230. e the Asynchronous Schedule is either enabled 1 or disabled 0 14 R Periodic Schedule Status The bit reports the current real status of the Periodic Schedule If this bit is a zero then the status of the Periodic Schedule is disabled If this bit is a one then the status of the Periodic Schedule A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 206 Allwinner Technology is enabled The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register When this bit and the Periodic Schedule Enable bit are the same value the Periodic Schedule is either enabled 1 or disabled 0 13 Reclamation This is a read only status bit which is used to detect an empty asynchronous schedule 12 HC Halted This bit is a zero whenever the Run Stop bit is a one The Host Controller Sets this bit to one after it has stopped executing as a result of the Run Stop bit being set to 0 either by software or by the Host Controller Hardware e g internal error The default value is 1 11 6 Reserved These bits are reserved and should be set to zero R WC 0 Interrupt on Async Advance System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt
231. e and SCL signal line on the 2 Wire serial bus ER ee ket 11C3 WE WE CR SCU if Figure 17 1 TWI Timing Diagram 17 3 TWI Controller Register List Module Name Base Address TWIO 0x01C2AC00 TWI1 0x01C2B000 TWI2 0x01C2B400 Register Name Offset Description TWI ADDR 0x0000 TWI Slave address TWI XADDR 0x0004 TWI Extended slave address TWI DATA 0x0008 TWI Data byte TWI CNTR 0x000C TWI Control register TWI STAT 0x0010 TWI Status register TWI CCR 0x0014 TWI Clock control register TWI SRST 0x0018 TWI Software reset TWI EFR 0x001C TWI Enhance Feature register TWI LCR 0x0020 TWI Line Control register 17 4 TWI Controller Register Description 17 4 1 TWI Slave Address Register Register Name TWI ADDR Offset 0x00 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 SLA Slave address 7 bit addressing SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLAO 7 1 R W 0 10 bit addressing A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 156 Allwinner Technology 1 1 1 1 0 SLAX 9 8 GCE General call address enable 0 Disable 0 R W 0 1 Enable Note For 7 bit addressing SLA6 SLAO is the 7 bit address of TWI in slave mode When TWI receives this address after a START condition it will generate an interrupt and enter slave mode SLA6 correspon
232. e ee eee ee ee eee 380 33421 GR RER Ee Ee WEE 380 33 4 28 PE Configure Register ss A 380 35420 PE Configure Register Tausen 382 33 4 30 PE Configure Register eebe eebe feinen eebe eben Dee 382 33 4 31 PE Configure Register 3 eee ereree er ere nee re me aenrey Meeeer ree reNt tr ener artery er ere re are tre ferrer re 382 33492 PE Data Register ti cies ee ed ete 383 33 4 33 PE Multi Driving Register 0 0 2 aa eesti pint iibei neath 383 33 4 34 PE Multi Driving Register 1 383 33 4 35 PE Pull Register O0 sisi 383 33 4 36 PE Pull Register 1 scsi eee os de ee eee 383 393497 PF Configure Register ds nee te 384 33 4 38 PF Configure Register Es sn nn ie 2 2 385 33 4 39 PF Configure E 385 33 4 40 PF Configure Register ss Re ent ne 385 33441 PF Data e ET 385 33 4 42 PF Multi Driving Register O0 ss 385 33 4 43 PF Multi Driving Register 1 385 33 4 44 PF Pull Register 0er ited tide edie 386 33 4 45 PF Pull Register E 386 33 4 46 PG Configure Register rcs cs ace acai la nett een hevet tat nt iat ies 386 33 4 47 PG Configure Register Uses en ne nn Ce ec icetateting 387 33 4 48 PG Configure Register sun ni ne Ne 388 23449 PG Configure Register dns en RL A ae 388 3394 50 FEN tc te eer Sc ete te rece eee 388 33 4 51 PE Multi Driving Register ds ed du 388 33 4 52 PG Multi Driving Register Le ee 388 33 4 53 PE PURES ISO E 389 Bate PG PUN REF este see 389 33 4 55 PIO Interrupt Configure Register 0 ss 389 A
233. e is reached TMR4_IRQ_PEND 4 R W 0x0 Timer 4 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 4 counter value is reached TMR3_IRQ_PEND 3 R W 0x0 Timer 3 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 3 counter value is reached TMR2_IRQ_PEND 2 R W 0x0 Timer 2 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 2 counter value is reached TMR1 IRQ PEND 1 R W 0x0 Timer 1 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 1 interval value is reached TMRO_IRQ_PEND 0 R W 0x0 Timer 0 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 0 interval value is reached 11 3 3 ASYNC Timer 0 Control Register Default 0x00000004 Offset 0x10 Register Name ASYNC_TMRO_CTRL_REG Bit se Pen Description rite Hex 31 8 TMRO MODE Timer0 mode 7 RW 0x0 0 Cartuns mode ANEN reaches the internal value the timer will not be disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically TMRO CLK PRES Select the pre scale of timer 0 clock source 000 1 6 4 RW 0x0 001 2 010 4 011 8 100 16 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 87 Allwinner Technology 101 32 110 64 111 128 3 2 RW 0x1 TMRO CLK SRC Timer 0 Clock Source 00 01 OSC24M 10 PLL6 6
234. e line penler algorithm select 0 horizontal filtered result 1 original data 7 0 27 5 5 DEFE LINT CTRL REG Offset 0x10 Register Name DEFE_LINT_CTRL_REG Bit Read W Default Description A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 286 Allwinner Technology rite Hex 31 28 27 16 R 0x0 CURRENT_LINE FIELD_SEL 15 RW oxo Field select 0 each field 1 end field field counter in reg0x2c 14 13 TRIG_LINE 12 0 R W 0x0 PUR Trigger line number of line interrupt 27 5 6 _DEFE_BUF_ADDRO_REG Offset 0x20 Register Name DEFE_BUF_ADDRO_REG Read W Bit rite Default Hex Description 31 0 R W 0x0 BUF_ADDR DEFE frame buffer address In tile based type The address is the start address of the line in the first tile used to generate output frame In non tile based type The address is the start address of the first line 27 5 7 DEFE_BUF_ADDR1_REG Offset 0x24 Register Name DEFE BUF ADDR1 REG Read W Bit rite Default Hex Description 31 0 R W 0x0 BUF_ADDR DEFE frame buffer address In tile based type The address is the start address of the line in the first tile used to generate output frame In non tile based type The address is the start address of the first line 27 5 8 DEFE_BUF_ADDR2_REG
235. echnology All Rights Reserved 226 Allwinner Technology should always read write 0 PowerSwitchingMode This bit is used to specify how the power switching of the Root Hub ports is controlled It is implementation specific This field is only valid when the NoPowerSwitching field is cleared 0 All ports are powered at the same time 1 Each port is powered individually This mode allows port power to be controlled by either the global switch or per port switch If the PortPowerControlMask bit is set the port responds only to port power commands Set ClearPortPower If the port mask is cleared then the port is controlled only by the global power switch 9 RW R 1 Set ClearGlobalPower NoPowerSwithcing These bits are used to specify whether power switching is supported or ports are always powered It is implementation specific When this bit is cleared the PowerSwitchingMode specifies global or per port switching 0 Ports are power switched 1 Ports are always powered on when the HC is powered 8 RW R 0 on NumberDownstreamPorts These bits specify the number of downstream ports supported by the Root Hub It is implementation specific The minimum number 7 0 R R 0x01 of ports is 1 22 6 20 HcRhDescriptorB Register Register Name HcRhDescriptorB Register Offset 0x44c Default Value Read Write Bit HCD HC Default Description PortPowerCon
236. ed by the CPU the CPU should also modify this to be the same in the PMU 5 3 15 PMU 32KHz CPUVDD Minimum Value Default 0x0000000C Offset 0x5C Register Name PMU_32KHZ_CPUVDD_MIN_REG Bit Read W rite Default Hex Description 31 8 7 0 R W Oxc CPUVDD 32KHZ MIN VALUE PMU CPUVDD Default Value 0x00 0 70v 0x02 0 75v 0x04 0 80v 0x06 0 85v 0x08 0 90v Ox0A 0 95v 0x0C 1 00v Ox0E 1 05v 0x10 1 10v 0x12 1 15v 0x14 1 20v 0x16 1 25v 0x18 1 30v Ox1A 1 35v 0x1C 1 40v A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 38 Allwinner Technology Ox1E 1 45v 0x20 1 50v 0x22 1 55v 0x24 1 60v 5 3 16 PMU VF Table Register 0 Offset 0x80 Register Name PMU VF TABLE REGO Read W Default SCH Bit i Description rite Hex 31 11 CPU MAX FREQ 070 10 0 R W X CPU max frequency if cpuvdd 0 7v unit MHz This register can only be written if the DVFS function is disabled 5 3 17 PMU VF Table Register 1 Offset 0x84 Register Name PMU VF TABLE REG1 Read W Default SC Bit f Description rite Hex 31 11 CPU_MAX_FREQ_075 10 0 R W D CPU max frequency if cpuvdd 0 75v unit MHz This register can only be written if the DVFS function is disabled
237. ed interface to all industy standard double data rate Il DDR2 ordinary SDRAM and Double data rate Ill DDR3 ordinary SDRAM It supports up to a 512MB memory address space The DRAMC automatically handles memory management initialization and refresh operations It gives the host CPU a simple command interface hiding details of the required address page and burst handling procedures All memory parameters are runtime configurable including timing memory setting SDRAM type and Extended Mode Register settings The DRAMC includes following features Support DDR2 SDRAM and DDR3 SDRAM Support different memory device power voltage of 1 5V and 1 8V Support memory capacity up to 512MB 15 address lines and 3 bank address lines Data IO size can up to 16 bit for DDR2 and DDR3 Automatically generate initialization and refresh sequences Runtime configurable parameters setting for application flexibility Clock frequency can be chosen for different applications Priority of transferring through multiple ports is programmable Support random read or write operation A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 81 Allwinner Technology 10 PWM 10 1 Overview The output of the PWM is a toggling signal whose frequency and duty cycle can be modulated by its programmable registers Each channel has a dedicated internal 16 bit up counter If the counter reaches the value stored in the channel period register
238. ed to test X X Y Y and record AX X X AY Y Y if AX or AY great than threshold as a dual touch thus as a single touch i MEASURE A X Position TOUCH MW 7 X POSITION WV JW i O X O MEASURE v X Position Figure25 11 Dual Touch X Position Measurements Copyright 2013 Allwinner Technology All Rights Reserved Allwinner Technology 25 4 6 Touch Pressure Measurement The pressure applied to the touch screen by a pen or finger to filter unavailable can also be also be measurement with the controller using some simple calculations The contact resistance between the X and Y plates is measured providing a good indication of the size of the depressed area and therefore the applied pressure The area of the spot that is touched is proportional to the size of the object touching it The size of this resistance Rtouch can be calculated using two different methods First Method The first method requires the user to know the total resistance of the X plate tablet RX Three touch screen conversions are required measurement of the X position XPOSITION Y input measurement of the X input with the excitation voltage applied to Y and X Z1 measurement and measurement of the Y input with the excitation voltage applied to Y and X Z2 measurement These three measurements are illustrated in Figure 4 The controller have two special ADC channel settings that configure the X
239. eed up to 400K bits s fast mode Support operation from a wide range of input clock frequencies 17 2 TWI Timing Diagram Data are always transferred 1 In unit of byte 8 bit 2 Each byte followed by an acknowledge bit 3 Unlimited number of byte in each data transfer 4 Data are transferred in serial with MSB first 5 The receiver will hold SCL low to force the transmitter to enter a wait state while it is waiting for responses from the microprocessor after every byte transfer Acknowledge is indispensible in data transfer and related acknowledge clock pulse is generated by the master After sending a byte the transmitter will release the SDA line and one of the following two cases will occur a The SDA is pulled down by the receiver and an acknowledge signal is sent back b The SDA is left high and a not acknowledge signal is sent back When the slave receiver doesn t acknowledge the slave address because of resource deficiency the SDA will be left high for master to generate a STOP condition to abort the transfer A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 155 Allwinner Technology When the slave receiver acknowledges the slave address but not ready to receive more during a data transfer the SDA will be left high for the master to generate a STOP condition to abort the transfer The following diagram provides an illustration to the relation between SDA signal lin
240. egister can only be accessed in privileged mode 13 4 4 NMI Interrupt Control Register Default 0x00000000 Offset 0x0C Register Name INTCNMI CTRL REG Read W Default ee Bit l Description rite Hex 31 2 NMI_SRC_TYPE External NMI Interrupt Source Type 10 RW oxo 00 Low level sensitive 01 Negative edge trigged 10 High level sensitive 11 Positive edge sensitive 13 4 5 Interrupt IRQ Pending Register 0 Default 0x00000000 Offset 0x10 Register Name INTC_IRQ_PEND_REGO Read W Bit rite Default Hex Description A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 109 Allwinner Technology INT IRQ SRC PENDO 31 0 R oxo Interrupt IRQ Source 31 eil Fending Clear Bit 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 13 4 6 Interrupt IRQ Pending Register 1 Default 0x00000000 Offset 0x14 Register Name INTC PEND REG1 Read W Default SCH Bit f Description rite Hex INT IRQ SRC PEND1 Interrupt IRQ Source 63 32 Pending Clear Bit 31 0 R 0x0 E i 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 13 4 7 Interrupt IRQ Pending Register 2 Default 0x00000000 Offset 0x18 Register Name INTC PEND REG2 Read W Default i Bit Description ri
241. ent input signal 0 no overcurrent condition 1 overcurrent condition detected write ClearSuspendStatus The HCD writes a 1 to initiate a resume Writing a 0 has no effect A resume is initiated only if PortSuspendStatus is set R W R W 0x0 read PortSuspendStatus This bit indicates the port is suspended or in the resume sequence A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 231 Allwinner Technology It is set by a SetSuspendState write and cleared when PortSuspendStatusChange is set at the end of the resume interval This bit cannot be set if CurrentConnectStatus is cleared This bit is also cleared when PortResetStatusChange is set at the end of the port reset or when the HC is placed in the USBRESUME state If an upstream resume is in progress it should propagate to the HC 0 port is not suspended 1 port is suspended write SetPortSuspend The HCD sets the PortSuspendStatus bit by writing a 1 to this bit Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortSuspendStatus instead it sets ConnectStatusChange This informs the driver that it attempted to suspend a disconnected port read PortEnableStatus This bit indicates whether the port is enabled or disabled The Root Hub may clear this bit when an overcurrent condition disconnect event switched
242. er 193 20 3 5 CIR Receiver Status Feet geseet 194 20 3 6 CIR Configure Registers asin ae 195 21 USB DRD Controller sisesisisscistosstusessinicesietsisintesniniadenvisssvessiaistesstataintsisarintelainisiuisinisiataseiniaiaustsiaisinvinian 197 Can Ne 197 21 2 USB DRD Timing Diagrann 197 22 USB RSE T T E E AE 198 SE PER EE EEE EEE 198 22 2 USB Host Block HEN seen 198 22 3 USB Host Timing Dig ae ee endEege 198 22 4 USB Host Register DEE 199 22 5 BAREN 200 22 5 1 EHCI Identification E EE 200 22 5 2 EHCI Host Interface Version Number Register 200 22 5 3 EHCI Host Control Structural Parameter Register 200 22 5 4 EHCI Host Control Capability Parameter Register 201 22 5 5 EHCI Companion Port Route Deserpti n ssmemesmnsmineeu nei 202 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 11 Allwinner Technology 22 5 6 Gallen ee EE 203 22 5 7 EA USB Stalls MSGI Oldie EEE 206 22 5 8 EHCI USB Interrupt Enable Register nunrhuhhunthianen 208 22 5 9 Elauter Been 209 22 5 10 EHCI Periodic Frame List Base Address Register 209 22 5 11 EHCI Current Asynchronous List Address Register AAA 210 ee EEE EE 210 22 5 13 EHCI Port Status and Control Register 210 22 0 OHCI Register Rer nici ee 215 22 6 1 wie ELE ue E 215 22 6 2 6 op ge AE 5 EEE EE EE EE 215 22 6 3 HcCommandStatus FEH eege 217 22 6 4 Helnterrupistatus R gis Ibn SR LR tt 218 22 6
243. er Technology All Rights Reserved 291 Allwinner Technology 01 ARGB Other reserved 27 5 17 DEFE WB ADDRO REG Offset 0x50 Register Name DEFE WB ADDRO REG f Read W Default en Bit Description rite Hex WB_ADDR 31 0 R W 0x0 Write back address setting for scaled data 27 5 18 DEFE_OUTPUT_FMT_REG Offset 0x5C Register Name DEFE OUTPUT FMT REG Read W Default s Bit Description rite Hex 31 18 WB_Ch Sel Write back channel select chsel 0 1 Ch3 17 16 RW 0 D Ch4 3 Ch5 Other reserved 15 9 BYTE SEQ Output data byte sequence selection 0 P3P2P1P0 word S GE 1 POP1P2P3 word For ARGB when this bit is 0 the byte sequence is BGRA and when this bit is 1 the byte sequence is ARGB 7 5 SCAN_MOD Output interlace enable 4 R W 0x0 0 disable 1 enable When output interlace enable scaler selects YUV initial phase according to LCD field signal 3 DATA_FMT Data format 000 planar RGB888 conversion data format 2 0 R W 0x0 001 interleaved BGRA8888 conversion data format A component always be pad Oxff 010 interleaved ARGB8888 conversion data format A component always be pad Oxff A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 292 Allwinner Technology 100 planar YUV 444 101 planar YUV 420 only support YUV inp
244. erflow after the hblank PRT_ERR Protection error Indicates a protection error has been detected Applies only when the 656 protocol is selected FIFOO_OF 03 R W FIFO1 overflow The bit is set when the FIFO 1 overflows 02 R W RIPO EHS The bit is set when the FIFO 0 overflows FRM DONE oa few fo JM Frame done A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 272 Allwinner Technology Indicates the CSI finishes capturing an image frame Applied to video capture mode The bit is set after each completed frame capturing data is written to buffer as long as video capture remains enabled CPT DONE Capture done Indicates the CSI has completed capturing the image data For still capture the bit is set when one frame data has been written to buffer For video capture the bit is set when the last frame has been written to buffer after video capture is disabled For CCIR656 interface if the output format is frame planar YCbCr 420 mode the frame end means the field2 end and the other frame end means field end 26 4 11 CSI Interrupt Status Register Register Name CSI INT STA REG ffset 0X0034 rs T E EREE R Default Value 0X00000000 Read Wr Default _ Bit Description ite Hex 31 08 VSYNC_FLA 07 RW ee vsync flag HB OF R W Inn je Hblank FIFO overflow PRT ERR 05 R W Protection error FIFO1 OF FIFOO0 OF 2 R F Frame done Ka CPT_DONE Capture done 26 4 12 CSI
245. ern 31 00 RW UDF am Inn uor Specify the color displayed for each of the hardware cursor pixels 28 5 38 DE HWC Palette Table Offset DE HW pal 0x4C00 0x4FFF pen Read Wr Default D Bit Description ite Hex The following figure only with 2bpp mode shows the RAM array used for hardware cursor palette lookup and the corresponding colors output A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 329 Allwinner Technology HWC Index memory Output color array 2bpp mode a2 R2 G2 B2 HWC palette table bit7 bit0 a0 RO GO BO 3 2 0 2 aa R G2 B a3 RB G3 B3 Color0 av RO GO BO Color1 ai RI GL Bl a2 R2 QA B 11 3 2 2 a2 R o R 3 3 0 1 a3 RB G3 B3 Color254 254 R254 G254 B254 i GA Ri m EE Hardware cursor index memory Color255 lo 3 oi RI GI BI amp palette av RO GO BO a3 RB G3 B3 a3 RB G3 B3 28 5 39 Palette Mode Offset Pipe0 0x5000 0x53FF Pipe palette color table SRAM block Pipe1 0x5400 0x57FF Read Wr Default D Bit Description ite Hex In this mode RAM array is used for palette lookup table each pixel in the layer frame buffer is treated as an index into the RAM array to select the actual color The following figure shows the RAM array used for palette lookup and the corresponding colors output On chip SRAM array Inputting external
246. errupt Control Register CIR RXSTA 0x30 CIR Receiver Status Register CIR_CONFIG 0x34 CIR Configure Register 20 3 CIR Regsiter Description 20 3 1 CIR Control Register Register Name CIR_CTL Offset 0x00 Default Value 0x0000 0000 Bit Read Write Default Description 31 9 CGPO General Program Output GPO Control in CIR mode for TX Pin 8 R W 0 0 Low level A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 192 Allwinner Technology 1 High level 7 6 5 4 R W CIR ENABLE 00 10 11 CIR mode enable 3 2 R W RXEN Receiver Block Enable 0 Disable 1 Enable R W GEN Global Enable A disable on this bit overrides any other block or channel enables and flushes all FIFOs 0 Disable 1 Enable 20 3 2 CIR Receiver Configure Register Register Name IR_RXCTL Offset 0x10 Default Value 0x0000 0000 Bit Read Write Default Description 31 3 RPPI Receiver Pulse Polarity Invert 0 Not invert receiver signal 2 R W 1 1 Invert receiver signal 1 0 20 3 3 CIR Receiver FIFO Register Register Name IR RXFIFO Offset 0x20 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 7 0 R 0 Receiver Byte FIFO 20 3 4 CIR Receiver Interrupt Control Register Register Name IR RXINT O
247. es There may be a delay in disabling or enabling a port due to other host controller and bus events When the port is disabled downstream propagation of data is blocked on this port except for reset The default value of this field is 0 This field is zero if Port Power is zero Connect Status Change 1 Change in Current Connect Status 0 No change Default 0 Indicates a change has occurred in the ports Current Connect A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 214 Allwinner Technology Status The host controller sets this bit for all changes to the port device connect status even if system software has not cleared an existing connect status change For example the insertion status changes twice before system software has cleared the changed condition hub hardware will be setting an already set bit Software sets this bit to 0 by writing a 1 toit This field is zero if Port Power is zero 0 R 0 Current Connect Status Device is present on port when the value of this field is a one and no device is present on port when the value of this field is a zero This value reflects the current state of the port and may not correspond directly to the event that caused the Connect Status Change Bit 1 to be set This field is zero if Port Power zero Note This register is only reset by hardware or in response to a host controller re
248. es the delay length equivalent to input clock period x1 5 3 41 CPU Idle Counter Low Register Default 0x00000000 Offset OXFO Register Name CPU_IDLE_CNT_LOW_REG Read W Bit rite Default Hex Description 31 0 RW Ox0 CPU IDLE CNT LO CPU Idle Counter 31 0 This counter clock source is 24MHz If CPU is in idle state the counter will count up in the clock of 24MHz Any write to this register will clear this register and the CPU idle counter high register 5 3 42 CPU Idle Counter High Register Default 0x00000000 Offset OxF4 Register Name CPU_IDLE_CNT_HIGH_REG Read W Default _ Bit Description rite Hex CPU_IDLE_CNT_HI PU Id 32 31 0 R W oxo CPU dle Counter pes Any write to this register will clear this register and the CPU idle counter low register A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 46 Allwinner Technology 5 3 43 CPU Idle Control Register Default 0x00000000 Offset OxF8 Register Name CPU_IDLE_COUNTER_CTRL_REG Read W Default oe Bit i Description rite Hex 31 8 CPU IDLE AUTO SWTH EN CPU idle enter exit clk auto switch enable 0 disable 1 enable 7 R W 0x0 If the CPU enter the idle mode and this bit is set the ccu will auto switch the CPU clock divide ratio to 8 If the CPU exit the i
249. escription rite Hex 31 28 HT Theycle HT 1 Tdclk 27 16 R W 0 Note 1 parallel HI gt HBP 1 X 1 2 2 serial 1 HT gt HBP 1 X 1 3 2 3 serial 2 HT gt HBP 1 X 1 3 2 2 15 10 29 3 11 TCONO BASIC2 REG Offset 0x050 Register Name TCONO basic timing register2 Read W Default i Bit Description rite Hex 31 21 VT 27 16 RW 0 TVT VT 2 Thsync Note VT 2 gt VBP 1 Y 1 2 15 10 VBP 9 0 R W 0 Tvbp VBP 1 Thsync 29 3 12 TCONO BASIC3 REG Offset 0x054 Register Name TCONO basic timing register3 Read W Default Bi Descrioti it rite Hex escription 31 22 25 16 RW 0 HSPW A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 340 Allwinner Technology Thspw HSPW 1 Tdclk Note HT gt HSPW 1 15 10 VSPW 9 0 R W 0 Tvspw VSPW 1 Thsync Note VT 2 gt VSPW 1 29 3 13 TCONO HV IF REG Offset 0x058 Register Name TCONO hv panel interface register Bit Read W rite Default Hex Description 31 RW HV Mode 0 24bit parallel mode 1 8bit serial mode 30 RW Serial Mode 0 8bit 3cycle RGB serial mode RGB888 1 8bit 2cycle YUV serial mode CCIR656 29 28 27 26 R W RGB888_SMO Serial RGB888 mode Output sequence
250. et 0x34 Register Name DEFE TB OFF1 REG f Read W Default oth Bit f Description rite Hex 31 21 X_OFFSET1 20 16 RW 0x0 7 The x offset of the bottom right point in the end tile 15 13 12 8 R W 0x0 Y OFFSETO A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 288 Allwinner Technology The y offset of the top left point in the first tile 75 X_OFFSET 4 0 HAN 0x0 SE S er The x offset of the top left point in the first tile 27 5 12 DEFE TB OFF2 REG Offset 0x38 Register Name DEFE TB OFF2 REG Read W Default i Bit i Description rite Hex 31 21 X_OFFSET1 20 16 RW 0x0 7 The x offset of the bottom right point in the end tile 15 13 12 8 R W 0x0 TORET SE Be The y offset of the top left point in the first tile 7 5 X_OFFSET 4 0 R W 0x0 vu SE Kee The x offset of the top left point in the first tile 27 5 13 DEFE LINESTRDO REG Offset 0x40 Register Name DEFE LINESTRDO REG Read W Bit rite Default Hex Description 31 0 R W 0x0 LINE_STRIDE In tile based type The stride length is the distance from the start of the end line in one tile to the start of the first line in next tile here next tile is in vertical direction In non tile based type The stride length is the distance from the start of one line to the start of t
251. ets the number of measurements to be taken These measurements are arranged in a temporary array where the first value is the smallest measurement and the last value is the largest measurement Bit1 and BitO in Control Register 3 MED1 MEDO set the window of the median filter and therefore the number of measurements taken MED1 MEDO Median Filter Size 0 0 4 0 1 5 1 0 8 1 1 16 Table25 1 Median Filter Size The averaging filter size determines the number of values to average Bit5 and Bit4 in Control Register 3 AVG1 AVGO set the average to 2 3 4 or 8 samples Only the final averaged result is written into the result FIFO register AVG1 AVGO Averaging Filter Size 0 0 2 0 1 3 1 0 4 1 1 8 Table25 2 Averaging Filter Size When Bit4 of Control Register 3 is set 0 and Median Averaging Filter mode is disabled only one A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 258 Allwinner Technology measurement is transferred to the register map The number specified with the MED1 and MEDO settings must be greater than or equal to the number specified with the AVG1 and AVGO settings If both settings specify the same number the median filter is switched off Setting Function M A Median filter is disabled output is the average of A converted results M gt A Output is the average of the middle A values from the array of M measureme
252. etween master and slave 1 delay internal read sample point 0 normal operation do not delay internal read sample point Transmit Pause Enable In master mode it is used to control transmit state machine to stop 18 R W 0 smart burst sending when RX FIFO is full 1 stop transmit data when RXFIFO full 0 normal operation ignore RXFIFO status SS LEVEL 17 R 1 ar When control SS signal manually A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 166 Allwinner Technology SPI CTRL REG SS CTRL 1 set this bit to 1 or 0 to control the level of SS signal 1 set SS to high 0 set SS to low 16 R W 0 SS CTRL SS Output Mode Select Usually controller sends SS signal automatically with data together When this bit is set to 1 software must manually write SPI CTRL REG SS LEVEL bit 17 to 1 or O to control the level of SS signal 1 manual output SS 0 automatic output SS 15 R W 0 Discard Hash Burst DHB In master mode it controls whether discarding unused SPI bursts when SMC is 1 0 Receiving all SPI bursts in BC period 1 Discard unused SPI bursts only fetching the SPI bursts during dummy burst period The bursts number is specified by WTC 14 R W 0 DDB Dummy Burst Type 0 The bit value of dummy SPI burst is zero 1 The bit value of dummy SPI burst is one 13 12 R W 0 SS SPI C
253. ey NN 365 32 3 5 SID Program Control NSU cca eee ete dctedctnteletteteieeee 365 S3 PEE NEE 366 NNN 366 33 2 Port Configuration Table vvs ke 366 33 3 Por Register Usta 368 33 4 Port Register D scription s mienne nn aus 368 33 4 1 EG ee GE NE 368 33 4 2 PB Configure RSS ancteneadindsesadenadenadnnsduesdanctenatuastanctets 369 33 4 3 PB Configure E 370 33 4 4 PB Configure Register 3 ei 370 33 4 5 PB Data Registe ca sac ese a a a a eee ea eta ce eet ee cee cee 371 33 4 6 PB Multi Driving Register EE 371 33 4 7 PB Multi Driving Heeetert eegend 371 33 4 8 PB Pull Register E 371 33 4 9 PB PU R GISIO E 371 33 4 10 PC Configure Register OS eye eer ay er nvmnrr er feePnr a CnPEET a Pnrnr a eiMinre fer eter Srmrererr se 372 33 411 PE Configure Register RE 373 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 19 Allwinner Technology 33 4 12 PE Configure Register 2 nn ne bekke 374 113 Poe e Sv E 374 33 414 PG Data E 374 33 4 15 PE Multi Driving Register en Le a Li a een 375 33 4 16 PC Multi Driving Register tee 375 33 417 PC Pull Register av 375 E PC Pull Register EE 375 VE PE EN 376 33 4 20 PD Configure Register 1 ee 377 33 4 21 PD Configure e 378 33 4 22 PD Configure Register Ses ses dei eet 379 33 4 23 PD Data Register sisi 379 33 4 24 PD Multi Driving Register 0 iii 380 33 4 25 PD Multi Driving Register 1 380 39 4 26 PD PulR gserlu SR esc eseece ess ee ec ee
254. f 16384 16384 Offset 0x140 0x144 0x148 Register Name TCON CEU range coefficient register f Read W Default _ Bit i Description rite Hex 31 24 CEU Coef Range Min 23 16 RW 0 unsigned 8bit value range of 0 255 15 8 CEU Coef Range Ma 70 Rw lo e pet unsigned 8bit value range of 0 255 29 3 31 TCON1 FILL CTL REG Offset 0x300 Register Name TCON1 fill data control register Read W Default a Bit i Description rite Hex TCON1_Fill_En 31 R W 0 0 bypass 1 enable 30 0 29 3 32 TCON1 FILL BEGIN REG Offset 0x304 0x310 0x31C Register Name TCON1 fill data begin register Read W Default p Bit f Description rite Hex 31 24 23 0 R W 0 Fill Begin A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 348 Allwinner Technology 29 3 33 TCON1 FILL END REG Offset 0x308 0x314 0x320 Register Name TCON1 fill data end register Read W Default Bit Description rite Hex 31 24 23 0 R W 0 Fill End 29 3 34 TCON1 FILL DATA REG Offset 0x30C 0x318 0x324 Register Name TCON1 fill data value register Read W Default Se Bit Description rite Hex 31 24 23 0 R W 0 Fill Value A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Right
255. fault K Bit Description rite Hex 31 11 CPU_MAX_FREQ_100 10 0 R W X CPU max frequency if cpuvdd 1 0v unit MHz This register can only be written if the DVFS function is disabled 5 3 23 PMU VF Table Register 7 Offset Ox9C Register Name PMU_VF_TABLE_REG7 Read W Default Bit Description rite Hex 31 11 CPU_MAX_FREQ_105 10 0 R W D CPU max frequency if cpuvdd 1 05v unit MHz This register can only be written if the DVFS function is disabled 5 3 24 PMU VF Table Register 8 Offset OxAO Register Name PMU VF TABLE REG8 Read W Default SE Bit Description rite Hex 31 11 CPU MAX FREQ 110 10 0 R W X CPU max frequency if cpuvdd 1 1v unit MHz This register can only be written if the DVFS function is disabled A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 40 Allwinner Technology 5 3 25 PMU VF Table Register 9 Offset OxA4 Register Name PMU VF TABLE REG9 Read W Default DE Bit i Description rite Hex 31 11 CPU MAX FREQ 115 10 0 R W X CPU max frequency if cpuvdd 1 15v unit MHz This register can only be written if the DVFS function is disabled 5 3 26 PMU VF Table Register 10 Offset OxA8 Register Name PMU_VF_TABLE_REG10 l Read W Default N Bit f Description rite Hex 31 11 CPU MAX FREQ 1
256. fficient B G constant B B R component coefficient R B G component coefficient G B B component coefficient B B constant 28 5 31 DEBE Output Color R Coefficient Register Offset R component 0x9D0 G component 0x9D4 B component 0x9D8 Read Wr Default Bit Description ite Hex Register Name DEBE_OCRCOEF_REG OC_RCOEF the R coefficient the value equals to coefficient 2 9 28 5 32 DEBE Output Color R Constant Register Offset Ox9DC Register Name DEBE_OCRCONS_REG f Read Wr Default a Bit Description ite Hex 31 15 OC RCONS the R constant the value equals to coefficient 2 28 5 33 DEBE Output Color G Coefficient Register Offset R component 0x9E0 G component 0x9E4 B component 0x9E8 Register Name DEBE_OCGCOEF_REG Read Wr Default De Bit Description ite Hex A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 327 Allwinner Technology OC_GCOEF 13 0 R W UDF the G coefficient the value equals to coefficient 2 9 28 5 34 DEBE Output Color G Constant Register Offset Ox9EC Register Name DEBE_OCGCONS_REG Bit Description ite Hex 31 15 OC GCONS the G constant the value equals to coefficient 2 28 5 35 DEBE Output Color B Coefficient Register Offset G Y component 0x9F0 R U component 0x9F4 B V component 0x9F8 Read Wr Default a Bit i Description ite Hex OC_BCOEF the B coefficient
257. ffset 0x2C Default Value 0x0000 0000 Bit Read Write Default Description 3112 RAL RX FIFO Available Received Byte Level for interrupt and DMA 11 6 R W 0 request A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 193 Allwinner Technology TRIGGER LEVEL RAL 1 DRQ EN RX FIFO DMA Enable 0 Disable 1 Enable When set to 1 the Receiver FIFO DRQ is asserted if reaching 5 R W 0 RAL The DRQ is de asserted when condition fails RAI EN RX FIFO Available Interrupt Enable 0 Disable 1 Enable When set to 1 the Receiver FIFO IRQ is asserted if reaching 4 R W 0 RAL The IRQ is de asserted when condition fails 3 2 RPEI EN Receiver Packet End Interrupt Enable 0 Disable 1 R W 0 1 Enable HO EN Receiver FIFO Overrun Interrupt Enable 0 Disable 0 R W 0 1 Enable 20 3 5 CIR Receiver Status Register Register Name IR RXSTA Offset 0x30 Default Value 0x0000 0000 Bit Read Write Default Description 31 13 RAC RX FIFO Available Counter 0 No available data in RX FIFO 1 1 byte available data in RX FIFO 2 2 byte available data in RX FIFO 12 6 R 0 64 64 byte available data in RX FIFO 5 RA RX FIFO Available 0 RX FIFO not available according its level 1 RX FIFO available according its level 4 R W 0 This bit is cleared by writing a 1 3 2
258. format control 00 1bpp 01 2bpp 10 4bpp 11 8bpp 28 5 18 DEBE Write Back Control Register Offset 0x8F0 Register Name DEBE WBCTL REG Read Wr Default SS Bit Description ite Hex WB EMT Write back data format setting 12 R W UDF 0 ARGB little endian system 1 BGRA little endian system A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 321 Allwinner Technology WB_EFLAG Error flag 0 1 write back error WB STATUS Write back process status 0 write back end or write back disable 1 write back in process This flag indicates that a full frame has not been written back to memory The bit will be set when write back enable bit is set and be cleared when write back process ends Write back only control 0 disable the write back only control the normal channel data of back end will transfer to LCD TV controller too 1 enable the write back only function and the all output data will bypass the LCD TV controller WB EN Write back enable 0 Disable 1 Enable If normal channel of back end is selected by LCD TV controller write back only function is disabled the writing back process will start when write back enable bit is set and a new frame processing begins The bit will be cleared when the new writing back frame starts to process 28 5 19 DEBE Write Back Address Register Offset 0x8F4 Register Name DEBE WBADD REG Read Wr Default Er Bi
259. ftware setting this bit to a zero This field is zero if Port Power is zero Over current Change Default 0 This bit gets set to a one when there is a change to Over current Active Software clears this bit by writing a one to this bit position Over current Active 0 This port does not have an over current condition 1 This port currently has an over current condition This bit will automatically transition from a one to a zero when the over current condition is removed The default value of this bit is 0 Port Enable Disable Change Default 0 1 Port enabled disabled status has changed 0 No change For the root hub this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point See Chapter 11 of the USB Specification for the definition of a Port Error Software clears this bit by writing a 1 to it This field is zero if Port Power is zero Port Enabled Disabled 1 Enable 0 Disable Ports can only be enabled by the host controller as a part of the reset and enable Software cannot enable a port by writing a one to this field The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high speed device Ports can be disabled by either a fault condition disconnect event or other fault condition or by host software Note that the bit status does not change until the port state actually chang
260. g back process will start when A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 285 Allwinner Technology write back enable bit is set and a new frame processing begins The bit will be self cleared when writing back frame process starts 1 REG RDY EN Register ready enable 0 not ready 1 registers configuration ready Just as filter coefficients configuration in order to ensure the display to 0 R W 0x0 be correct the correlative display configuration registers are buffered too and programmers also can change the value of correlative registers in any time When the registers setting is finished the programmer should set the bit if the new configuration is needed in next scaling frame When the new frame starts the bit will also be self cleared 27 5 3 DEFE BYPASS REG Offset 0x8 Register Name DEFE_BYPASS_REG Read W Default SE Bit Description rite Hex 31 2 CSC BYPASS EN CSC by pass enable 0 CSC enable 1 R W 0x0 1 CSC will be by passed Actually in order to ensure the module working to be correct this bit only can be set when input data format is the same as output data format both YUV or both RGB 0 27 5 4 DEFE AGTH SEL REG Offset OxC Register Name DEFE AGTH SEL REG Read W Default Bit Description rite Hex 31 9 LINEBUF_AGTH 8 RW oxo e
261. g edge of SPI_SCLK is used to setup or sample data The leading edge is used to setup data when PHA is 1 and to sample data when PHA is 0 The four modes are listed below SPI Mode POL PHA Leading Edge Trailing Edge 0 0 0 Rising Sample Falling Setup 1 0 1 Rising Setup Falling Sample 2 1 0 Falling Sample Rising Setup 3 1 1 Failing Setup Rising Sample A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 164 Allwinner Technology SPI SCLK Mode 0 SPI SCLK Mode 2 SPI MOSI SPI MISO SPI SS Sample MOSI MISO pin Phase 0 Fig ure18 1 SPI Phase 0 Timing Diagram SPI SCLK Mode 1 SPI SCLK Mode 3 Sample MOSI MISO pin SPI MOSI Y X SPI MSO XX D VW XX SPI SS Phase 1 Figure 18 2 SPI Phase 1 Timing Diagram 18 3 SPI Register List Module Name Base Address SPIO 0x01C05000 SPI 0x01C06000 SPI2 0x01C17000 Register Name Offset Description SPI RXDATA 0x00 SPI RX Data Register SPI_TXDATA 0x04 SPI TX Data Register SPI CTL 0x08 SPI Control Register SPI INTCTL 0x0C SPI Interrupt Control Register SPI_ST 0x10 SPI Status Register SPI_DMACTL 0x14 SPI DMA Control Register SPI WAIT 0x18 SPI Wait Clock Counter Register SPI CCTL Ox1C SPI Clock Rate Control Register A13 User Manual V1 3
262. g interrupt if the interrupt is enabled 1 R W 0x0 ADCO_KEYDOWN_PENDING ADC 0 Key Down IRQ Pending Bit When General key pull down the status bit is set and the interrupt line is set if the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled 0 R W 0x0 ADCO DATA PENDING ADC 0 Data IRQ Pending Bit 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled 24 4 4 LRADC Data 0 Register Offset Ox0c Register Name LRADC_DATA Bit Read W Default Description rite Hex 31 6 5 0 R 0x0 LRADCO_DATA LRADC 0 Data 24 4 5 LRADC Data 1 Register Offset 0x10 Register Name LRADC_DATA Bit Read W Default Description rite Hex 31 6 5 0 R 0x0 LRADC1_DATA LRADC 1 Data A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 251 Allwinner Technology 25 Touch Panel 25 1 Overview The controller is a 4 wire resistive touch screen controller includes 12 bit resolution A D converter Especially it provides the ability of dual touch detection The controller through the implementation of the two A D conversion has been identified by the location of the screen of single touch in addition to measurable increase in pressure on the touch screen It features 12 bit SAR type A D converter e 4
263. gger when SYO matches the current TCONO scan line Write 0 to clear it TCON1 Line Int Flag 12 R W 0 trigger when SY1 matches the current TCON1 scan line Write 0 to clear it 11 0 29 3 3 TCON GINT1 REG Offset 0x008 Register Name TCON global interrupt register1 Read W Default i Bit Description rite Hex 31 27 TCONO Line Int Num 26 16 RW 0 Scan ine for TCONO ing triggertincluding inactive lines Setting it for the specified line for trigger0 Note SYO is writable only when LINE TRGO0 is disabled 15 11 TCON1 Line Int Num 10 0 RW 0 SH pe for TCON1 mg Wd inactive lines Setting it for the specified line for trigger 1 Note SY1 is writable only when LINE_TRG 1 is disabled 29 3 4 TCONO FRM CTL REG Offset 0x010 Register Name TCON FRM control register Read W Default Dr Bit Description rite Hex TCONO Frm En 31 R W 0 O disable 1 enable 30 12 j TCONO_Frm_Mode_R 6 R W 0 0 6bit frm output 1 5bit frm output TCONO Frm Mode G 5 R W 0 0 6bit frm output 1 5bit frm output A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 337 Allwinner Technology TCONO Frm Mode B 4 R W 0 0 6bit frm output 1 5bit frm output TCONO Frm Test 00 FRM 1 0 RW 0 01 half 5 6bit half FRM 10 half 8bit half FRM 11 half 8bit half 5 6bit 29 3 5 TCONO FRM SEED REG Offset 0x014 0x01C Register Name TCON FRM pixel seed register
264. gnal is inverted after receiving from pin SIN A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 191 Allwinner Technology 20 CIR 20 1 Overview The CIR features Full physical layer implementation Support CIR for remote control or wireless keyboard 64x8 bits FIFO for data transfer Programmable FIFO thresholds Support Interrupt and DMA CIR receiver is implemented in hardware to save CPU resource It samples the input signals on the programble frequency and records these samples into RX FIFO when one CIR signal is found on the air The CIR receiver uses Run Length Code RLC to encode pulse width and the encoded data is buffered in a 64 levels and 8 bit width RX FIFO the MSB bit is used to record the polarity of the receiving CIR signal The high level is represented as 1 and the low level is represented as 0 and the rest 7 bits are used for the length of RLC The maximum length is 128 If the duration of one level high or low is more than 128 another byte is used Since there are always some noises in the air a threshold can be set to filter the noises to reduce system loading and improve system stability 20 2 CIR Register List Module Name Base Address CIR 0x01C21800 Register Name Offset Description CIR_CTL 0x00 CIR Control Register CIR_RXCTL 0x10 CIR Receiver Configure Register CIR_RXFIFO 0x20 CIR Receiver FIFO Register CIR_RXINT Ox2C CIR Receiver Int
265. gy All Rights Reserved 49 Allwinner Technology 32KHZ Divider Divider Divider 00 1 00 1 00 2 01 2 01 2 01 2 OSC24M 10 3 10 4 10 4 11 4 11 8 11 8 CPU CLK R AXI CLK AHB CLK APBO CLK PLLI PLL6 6 OSC24M APB1 CLK CLK_OUT CLK_IN M N APB1 CLK OUT PLL6 VR TWI UART SCR M 1 32 N 1 2 4 8 32KHZ NAND CLK NAND CLK OUT OSC24M SD0 1 2 CLK SD0 1 2 CLK OUT SS CLK SS CLK OUT SPI0 1 2 CLK E gt PLL6 IR CLK CLK_OUT CLK_IN M N M 1 16 SPI0 1 2 CLK OUT PLL5 N 1 2 4 8 IR CLK OUT P ma CLK_OUT CLK IN N gt N 1 2 4 8 USB CLK OUT USB CLK USB PLL gt PLL3 DE BE FE CLK DE BE FE CLK OUT PLL7 CLK_OUT CLK IN M gt M 1 16 BE CLK OUT PLL5 p IEP CLK c p PLL3x1 LCD CH0 CLK E LCD CH0 CLK OUT Pr CLK OUT CLK IN PLL3x2 PLL7x2 A13 User Manual V1 3 Figure 6 2 Bus Clock Generation Part 1 Copyright 2013 Allwinner Technology All Rights Reserved 50 Allwinner
266. he RBR or the receiver FIFO 0 no data ready 0 R 0 1 data ready A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 187 Allwinner Technology This bit is cleared when the RBR is read in non FIFO mode or when the receiver FIFO is empty in FIFO mode 19 4 11 UART Modem Status Register Offset 0x18 Register Name UART MSR Default Value 0x0000 0000 Bit Read Write Default Description 31 8 DCD Line State of Data Carrier Detect This is used to indicate the current state of the modem control line ded n This bit is the complement of dcd n When the Data Carrier Detect input dcd n is asserted it is an indication that the carrier has been detected by the modem or data set 0 ded n input is de asserted logic 1 1 dcd_n input is asserted logic 0 RI Line State of Ring Indicator This is used to indicate the current state of the modem control line ri n This bit is the complement of ri n When the Ring Indicator input ri n is asserted it is an indication that a telephone ringing signal has been received by the modem or data set 0 ri n input is de asserted logic 1 1 ri_n input is asserted logic 0 DSR Line State of Data Set Ready This is used to indicate the current state of the modem control line dsr_n This bit is the complement of dsr_n When the Data Set Ready input dsr_n is asserted it is an indication that the m
267. he corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If the port is configured as functional pin the undefined 5 0 R W 0 value will be read 33 4 42 PF Multi Driving Register 0 Register Name PF_DRVO Offset OxC8 Default Value 0x0000 0155 Bit Read Write Default Description 31 10 PF n Multi Driving Select n 0 5 2i 1 2i 00 Level 0 01 Level 1 i 0 5 R W 0x1 10 Level 2 11 Level 3 33 4 43 PF Multi Driving Register 1 Register Name PF_DRV1 Offset OxCC Default Value 0x0000 0000 Bit Read Write Default Description A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 385 Allwinner Technology 31 0 Ju 33 4 44 PF Pull Register 0 Register Name PE PULLO Offset OxDO Default Value 0x0000 0000 Bit Read Write Default Description 31 10 PF n Pull up down Select n 0 5 2i 1 2i 00 Pull up down disable 01 Pull up i 0 5 R W 0x0 10 Pull down 11 Reserved 33 4 45 PF Pull Register 1 Register Name PF PULL1 Offset 0xD4 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 46 PG Configure Register 0 Register Name PG CFGO Offset 0xD8 Default Value 0x0000 0000 Bit Read Write Default Description 31
268. he next line 27 5 14 DEFE LINESTRD1 REG Offset 0x44 Register Name DEFE LINESTRD1 REG Read W Bit rite Default Hex Description 31 0 R W 0x0 LINE_STRIDE In tile based type The stride length is the distance from the start of the end line in one tile to the start of the first line in next tile here next tile is in vertical direction In non tile based type The stride length is the distance from the start of one line to the start of A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 289 Allwinner Technology the next line 27 5 15 DEFE LINESTRD2 REG Offset 0x48 Register Name DEFE LINESTRD2 REG Bit Read W rite Default Hex Description 31 0 RW Ox0 LINE_STRIDE In tile based type The stride length is the distance from the start of the end line in one tile to the start of the first line in next tile here next tile is in vertical direction In non tile based type The stride length is the distance from the start of one line to the start of the next line 27 5 16 DEFE_INPUT_FMT_REG Offset Ox4C Register Name DEFE_INPUT_FMT_REG f Read W Default KR Bit Description rite Hex 31 17 BYTE SEQ 16 R W CR Input data byte sequence selection 0 P3P2P1P0 word 1 POP1P2P3 word 15 13 SCAN_MOD 12 RAW
269. he other bit i e data and or parity and stop It should be noted that the Framing Error FE bit LSR 3 is set if a break interrupt has occurred as indicated by Break Interrupt BI bit LSR 4 0 no framing error 1 framing error Reading the LSR clears the FE bit PE Parity Error This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable PEN bit LCR 3 is set In the FIFO mode since the parity error is associated with a character received it is revealed when the character with the parity error arrives at the top of the FIFO It should be noted that the Parity Error PE bit LSR 2 is set if a break interrupt has occurred as indicated by Break Interrupt BI bit LSR 4 0 no parity error 1 parity error 2 R 0 Reading the LSR clears the PE bit OE Overrun Error This occurs if a new data character is received before the previous data is read In the non FIFO mode the OE bit is set when a new character arrives in the receiver before the previous character is read from the RBR When this happens the data in the RBR is overwritten In the FIFO mode an overrun error occurs when the FIFO is full and a new character arrives at the receiver The data in the FIFO is retained and the data in the receive shift register is lost 0 no overrun error 1 overrun error 1 R 0 Reading the LSR clears the OE bit DR Data Ready This is used to indicate that the receiver contains at least one character in t
270. hest priority 13 4 29 Interrupt Source Priority 3 Register Default 0x00000000 Offset 0x8C Register Name INTC SRC PRIO REG3 Bit Read W rite Default Hex Description 31 30 R W 0x0 IRQ63 PRIO IRQ 63 Priority Set priority level for IRQ bit 63 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 29 28 RW Ox0 IRQ62_PRIO IRQ 62 Priority Set priority level for IRQ bit 62 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 122 Allwinner Technology Offset 0x8C Register Name INTC_SRC_PRIO_REG3 Level3 0x1 level 3 highest priority IRQ61 PRIO IRQ 61 Priority Set priority level for IRQ bit 61 27 26 RW 0x0 Level 0x0 level 0 lowest priority Leveli 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ60 PRIO IRQ 60 Priority Set priority level for IRQ bit 60 25 24 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ59 PRIO IRQ 59 Priority Set priority level for IRQ bit 59 23 22 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ58 PRIO IRQ
271. hift register has shifted out all the bits Writing 1 to this bit clears it 0 Busy 1 Transfer Completed 15 14 R W TU TXFIFO under run This bit is set when if the TXFIFO is underrun Writing 1 to this bit clears it 0 TXFIFO is not underrun 1 TXFIFO is underrun 13 R W TO TXFIFO Overflow This bit is set when the TXFIFO overflows Writing 1 to this bit clears it 0 TXFIFO is not overflowed A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 170 Allwinner Technology 1 TXFIFO is overflowed 12 RW 1 TXFIFO 3 4 empty This bit is set if the TXFIFO is more than 3 4 empty Writing 1 to this bit clears it 11 R W 1 TXFIFO 1 4 empty This bit is set if the TXFIFO is more than 1 4 empty Writing 1 to this bit clears it 10 R W 0 TF TXFIFO Full This bit is set when the TXFIFO is full Writing 1 to this bit clears it 0 TXFIFO is not Full 1 TXFIFO is Full R W 1 THE TXFIFO Half empty This bit is set if the TXFIFO is more than half empty Writing 1 to this bit clears it 0 TXFIFO holds more than half words 1 TXFIFO holds half or fewer words R W 1 TE TXFIFO Empty This bit is set if the TXFIFO is empty Writing 1 to this bit clears it 0 TXFIFO contains one or more words 1 TXFIFO is empty R W 0 RU RXFIFO Underrun When set this bit indicates that RXFIFO has underru
272. highest priority IRQ66 PRIO IRQ 66 Priority Set priority level for IRQ bit 66 5 4 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ65_PRIO IRQ 65 Priority Set priority level for IRQ bit 65 3 2 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ64 PRIO IRQ 64 Priority Set priority level for IRQ bit 64 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 1 0 RW 0x0 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 127 Allwinner Technology Offset 0x90 Register Name INTC SRC PRIO REG4 Level 0x1 level 3 highest priority 13 4 31 Interrupt Source Priority 5 Register Default 0x00000000 Offset 0x94 Register Name INTC SRC PRIO REG5 Bit Read W rite Default Hex Description 31 30 RW Ox0 IRQ95 PRIO IRQ 95 Priority Set priority level for IRQ bit 95 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 29 28 RW Ox0 IRQ94 PRIO IRQ 94 Priority Set priority level for IRQ bit 94 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 27 26 R W 0x
273. hip Select Select one of four external SPI Master Slave Devices 00 SPI_SSO will be asserted 01 SPI_SS1 will be asserted 10 SPI SS2 will be asserted 11 SPI SS3 will be asserted Notes These two bits can t be configured for SPI1 Engine 11 RW 0 RPSM Rapids Mode Select Select Rapids operation mode for high speed read 0 Normal read mode 1 Rapids read mode 10 RW 0 XCH Exchange Burst In master mode it is used to start to SPI burst when SMC bit is set to 1 0 Idle 1 Initiates exchange After finishing the SPI bursts transfer specified by BG this bit is cleared to zero by SPI Controller R W 0 RXFIFO Reset Write 1 to reset the control portion of the receiver FIFO and treats A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 167 Allwinner Technology the FIFO as empty It is self clearing It is not necessary to clear this bit TXFIFO Reset Write 1 to reset the control portion of the transmit FIFO and treats the FIFO as empty 8 R W 0 It is self clearing It is not necessary to clear this bit SSCTL In master mode this bit selects the output wave form for the SPI_SSx signal 0 SPI SSx remains asserted between SPI bursts 7 R W 0 1 Negate SPI SSx between SPI bursts LMTF LSB MSB Transfer First select 0 MSB first 6 R W 0 1 LSB first DMAM DMA mode control 0 normal dma 5 R W 0 1 dedica
274. ht 2013 Allwinner Technology All Rights Reserved 236 Allwinner Technology condition IRQ DRQ Generated when WLEVEL lt TXTL RW Ox0 ADDA LOOP EN ADDA loop Enable adda 0 Disable 1 Enable R W 0x0 DAC MONO EN DAC Mono Enable 0 Stereo 64 levels FIFO 1 mono 128 levels FIFO When enabled L amp R channel send same data R W 0x0 TX SAMPLE BITS Transmitting Audio Sample Resolution 0 16 bits 1 24 bits RW Ox0 DAC DRQ EN DAC FIFO Empty DRQ Enable 0 Disable 1 Enable RW Ox0 DAC IRQ EN DAC FIFO Empty IRQ Enable 0 Disable 1 Enable RW Ox0 FIFO UNDERRUN IRQ EN DAC FIFO Under Run IRQ Enable 0 Disable 1 Enable RW Ox0 FIFO OVERRUN IRQ EN DAC FIFO Over Run IRQ Enable 0 Disable 1 Enable R W 0x0 FIFO_FLUSH DAC FIFO Flush Write 1 to flush TX FIFO self clear to 0 23 4 3 DAC FIFO Status Register Offset 0x8 Register Name AC_DAC_FIFOS Bit Read Write Default Description 31 24 23 0x1 TX_EMPTY TX FIFO Empty 0 No room for new sample in TX FIFO 1 More than one room for new sample in TX FIFO gt 1 word 22 8 0x80 TXE_CNT TX FIFO Empty Space Word Counter A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 237 Allwinner Technology 7 4 TXE INT TX FI
275. iagram is showed below a USB HCI EHCI Loi 5 3 A AHB l S Slave S UTMIES Se USB Port gt E S A 2 Loi ona a JE EN Y DRAM Memory Figure22 1 USB Host Block Diagram 22 3 USB Host Timing Diagram Please refer USB2 0 Specification Enhanced Host Controller Interface EHCI Specification Version A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 198 Allwinner Technology 1 0 and the Open Host Controller Interface OHCI Specification Version 1 0a 22 4 USB Host Register List Module Name Base Address USB HCIO 0x01C14000 Register Name Offset Description EHCI Capability Register E CAPLENGTH 0x000 EHCI Capability register Length Register E HCIVERSION 0x002 EHCI Host Interface Version Number Register E HCSPARAMS 0x004 EHCI Host Control Structural Parameter Register E HCCPARAMS 0x008 EHCI Host Control Capability Parameter Register E HCSPPORTROUTE 0x00c EHCI Companion Port Route Description EHCI Operational Register E USBCMD 0x010 EHCI USB Command Register E USBSTS 0x014 EHCI USB Status Register E USBINTR 0x018 EHCI USB Interrupt Enable Register E FRINDEX Ox01c EHCI USB Frame Index Register E CTRLDSSEGMENT 0x020 EHCI 4G Segment Selector Register E PERIODICLISTBASE 0x024 EHC
276. ified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time 12 3 9 Sync Timer 1 Interval Value Low Register Offset 0x34 Register Name SYNC TMR1 INTV LOW REG Read W Default Bit f Description rite Hex 31 0 RW STMR1 INTV VALUE LOW Sync Timer 1 Interval Value 31 0 12 3 10 Sync Timer 1 Interval Value High Register Offset 0x38 Register Name SYNC TMR1 INTV HI REG Read W Default i Bit Description rite Hex 31 24 23 0 RW x STMR1_INTV_VALUE_HI Sync Timer 1 Interval Value 55 32 Note the interval value register is a 56 bit register When read or write the interval value the Low register should be read or write first And the High register should be written after the Low register 12 3 11 Sync Timer 1 Current Value Low Register Offset Ox3C Register Name SYNC TMR1 CURNT LOW REG Read W Default RE Bit Description rite Hex 31 0 R W S SEMMI CUR_VALUE_LOW Sync Timer 1 Current Value 31 0 12 3 12 Sync Timer 1 Current Value High Register Offset 0x40 Register Name SYNC_TMR1_CURNT_HI_REG f Read W Default E Bit Description rite Hex 31 24 23 0 RW STMR1_CUR_VALUE HI Sync Timer 1 Current Value 55 32 Note Timer
277. ights Reserved 360 Allwinner Technology Bit Read Write Default Description 31 0 R W 0 Initialization Vector IV n Input Value n 0 7 31 4 4 Security System FIFO Control Status Register Register Name SS FCSR Offset 0x44 Default Value 0x6000 OFOF Bit Read Write Default Description 31 RX FIFO Empty 0 No room for new word in RX FIFO 30 R Ox1 1 More than one room for new word in RX FIFO gt 1 word 29 24 R 0x20 RX FIFO Empty Space Word Counter 23 TX FIFO Data Available Flag 0 No available data in TX FIFO 22 R 0 1 More than one data in TX FIFO gt 1 word 21 16 IR 0 TX FIFO Available Word Counter 15 13 RX FIFO Empty Trigger Level Interrupt and DMA request trigger level for RXFIFO normal condition Trigger Level RXTL 1 12 8 R W OxF Notes RX FIFO is used for input the data 7 5 TX FIFO Trigger Level Interrupt and DMA request trigger level for TXFIFO normal condition Trigger Level TXTL 1 4 0 R W OxF Notes TX FIFO is used to output the result data 31 4 5 Security System Interrupt Control Status Register Register Name SS_ICSR Offset 0x48 Default Value 0x0000 0000 Bit Read Write Default Description 31 11 RX FIFO Empty Pending bit 0 No pending 1 RX FIFO Empty pending Notes Write 1 to clear or automatically clear if interrupt condition 10 R W 0 fails 9 TX FIFO
278. ights Reserved 75 Allwinner Technology Clock Source Select 000 PLL3 1X 001 PLL4 010 PLL5 011 PLL7 1X 100 PLL7 2X 23 18 17 16 15 4 l CLK_DIV RATIO M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 40 MBUS Clock Control Default 0x00000000 Offset 0x15C Register Name MBUS_SCLK_CFG_REG f Read W Default Wi Bit i Description rite Hex MBUS SCLK GATING Gating Clock for MBUS Max Clock 300MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON MBUS_CLOCK Clock Source Divider N Divider M 30 26 MBUS SCLK SRC Clock Source Select 25 24 IRW 0x0 HS ok 01 PLL6 10 PLL5 11 Reserved 23 18 MBUS SCLK RATIO N 17 16 RW 0x0 Clock Pre divide Ratio N The select clock source is pre divided by 2 N The divider is 1 2 4 8 15 4 MBUS SCLK RATIO M 3 0 R W 0x0 Clock Divide Ratio M The divided clock is divided by M 1 The divider is from 1 to 16 6 4 41 IEP Clock Control Default 0x00000000 Offset 0x160 Register Name IEP_SCLK_CFG_REG f Read W Default E Bit Description rite Hex 31 RW x IEP_SCLK_GATING Gating Clock for IEP Max Clock 300MHz A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 76 Allwinner Technology 0 Clock is OFF
279. igured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If the port is configured as functional pin the undefined 11 0 R W 0 value will be read 33 4 33 PE Multi Driving Register 0 Register Name PE DRVO Offset OxA4 Default Value 0x0055 5555 Bit Read Write Default Description 31 24 PE n Multi Driving Select n 0 11 2i 1 2i 00 Level 0 01 Level 1 i 0 11 RW Ox1 10 Level 2 11 Level 3 33 4 34 PE Multi Driving Register 1 Register Name PE DRV1 Offset OxA8 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 35 PE Pull Register 0 Register Name PE_PULLO Offset OxAC Default Value 0x0000 0000 Bit Read Write Default Description 31 24 PE n Pull up down Select n 0 11 2i 1 2i 00 Pull up down disable 01 Pull up i 0 11 RW 0x0 10 Pull down 11 Reserved 33 4 36 PE Pull Register 1 Register Name PE PULL1 Offset 0xBO Default Value 0x0000 0000 Bit Read Write Default Description A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 383 Allwinner Technology 31 0 l 33 4 37 PF Configure Register 0 Register Name PF_CFGO Offset 0xB4 Default Value 0x0040 4044 Bit Read Write Default Description 31 24 23 PF5 Select 000 Input 001 Output 010 SDCO D2 011 JTAG CK1 100 1
280. ing table CLK Domain Module Speed Range Description OSC24M Most Clock Generator 24MHz Root clock for most of the chip RC_OSC Timer key 32KHz Source for the timer Divided from CPU32 cik or PU32 cik PU32 2K 1200M CPU32 c CPU3 00 OSC24M AHB cik AHB Devices 8K 276M Divided from CPU32 ck APB_clk Peripheral 0 5K 138M Divided from AHB_clk SDRAM clk SDRAM 0 400MHz Sourced from the PLL USB _ clk USB 480MHz Sourced from the PLL 24 576MHz Audio_clk D D A udio_c A D D 129 5792MHz Sourced from the PLL A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 48 Allwinner Technology 6 2 Clock Tree Diagram PLL 1 240MHz 2GHz OUT 24MHz N K M P gt N 0 31 PLLIOUT K 1 4 M 1 4 P 1 2 4 8 gt PLL 2 PLL2OUT y OUT 22 5792MHz 24 576MHz PLL 3 27MHz 381MHz pl OUT 3MHz M Integer mode PLL3OUT OUT 270MHz 297MHz Fractional M 9 127 PLL 4 240MHz 2GHz OUT 24MHz N K M P de 1 N03 PLIAOUT y 24NHz K 1 4 M 1 4 P 1 2 4 8 PLL 5 240MHz 2GHz OUT 24MHz N K M OUT 24MHZ N K P PI SOUT gt N 0 31 K 1 4 M 1 4 P 1 2 4 8 e PLL 6 PLL6OUT Fixed To 1 2GHZ PLL 7 27MHz 381MHz gt OUT 3MHz M Integer mode PLL7OUT OUT 270MHz 297MHz Fractional M 9 127 Figure 6 1 Clock Generation from PLL Outputs A13 User Manual V1 3 Copyright 2013 Allwinner Technolo
281. ion A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 162 Allwinner Technology A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 163 Allwinner Technology 18 SPI 18 1 Overview The Serial Peripheral Interface SPI allows rapid data communication with less software interrupts The SPI module contains one 8x64 receiver buffer RXFIFO and one 8x64 transmit buffer TXFIFO It can work in two modes Master mode and Slave mode It features Full duplex synchronous serial interface Configurable Master Slave 8x64 FIFO for data transmit and receive Configurable Polarity and phase of the Chip Select SPI SS and SPI Clock SPI SCLK Support Dedicated DMA 18 2 SPI Timing Diagram The SPI master uses the SPI_SCLK signal to transfer data in and out of the shift register Data is clocked using any one of four programmable clock phase and polarity combinations During Phase 0 Polarity 0 and Phase 1 Polarity 1 operations output data changes on the falling clock edge and input data is shifted in on the rising edge During Phase 1 Polarity 0 and Phase 0 Polarity 1 operations output data changes on the rising edges of the clock and is shifted in on falling edges The POL defines the signal polarity when SPI_SCLK is in idle state The SPI SCLK is high level when POL is 1 and it is low level when POL is 0 The PHA decides whether the leadin
282. iption ite Hex 31 00 RW FIFOO BUF A FIFOO output buffer A address 26 4 5 CSI FIFO0 Buffer B Register Register Name CSI FIFOO BUF B ADDR REG ffset Add 0X0014 Default Value 0X00000000 Read Wr Default oe Bit Description ite Hex 31 00 R W FIFOO BUF B FIFOO output buffer B address A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 270 Allwinner Technology 26 4 6 CSI FIFO1 Buffer A Register Register Name CSI_FIFO1_BUF_A_ADDR_REG Offset Add 0X0018 SE EE Default Value 0X00000000 Read Wr Default a Bit Description ite Hex 31 00 R W FIFO1_BUF_A FIFO1 output buffer A address 26 4 7 CSI FIFO1 Butter B Register Register Name CSI FIFO1 BUF B ADDR REG Offset Address 0X001C Read Wr Default Bit Description ite Hex FIFO1 BUF B 31 00 R W T an Inn je FIFO1 output buffer B address 26 4 8 CSI Buffer Control Register GE Det Register Name CSI BUF CTRL REG s i Default Value 0X00000000 Default S Bit Description ite Hex 1 V DBS output buffer selected status 0 Selected output buffer A 1 Selected output buffer B DBE Double buffer mode enable 0 disable 1 enable If the double buffer mode is disabled the buffer A will be always selected by CSI module 26 4 9 CSI Status Register Register Name CSI STA REG 0X002 uk leet ONS DN Default Value 0X00000000 Read Wr Default KC Bit Description ite Hex LUM STAT VA
283. is held low while serial data output is inverted and looped back to the sir in line 3 2 RTS Request to Send This is used to directly control the Request to Send rts_n output The Request To Send rts_n output is used to inform the modem or data set that the UART is ready to exchange data When Auto RTS Flow Control is not enabled MCR 5 set to zero the rts_n signal is set low by programming MCR 1 RTS to a high In Auto Flow Control AFCE MODE Enabled and active MCR 5 set to one and FIFOs enable FCR 0 set to one the rts_n output is controlled in the same way but is also gated with the receiver FIFO threshold trigger rts_n is inactive high when above the threshold The rts_n signal is de asserted when MCRI 1 is set low 0 rts_n de asserted logic 1 1 rts_n asserted logic 0 Note that in Loopback mode MCR 4 set to one the rts_n output is held inactive high while the value of this location is internally 1 R W 0 looped back to an input DTR Data Terminal Ready This is used to directly control the Data Terminal Ready dtr_n output The value written to this location is inverted and driven out on dir n 0 dtr_nde asserted logic 1 1 dtr_n asserted logic 0 The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications Note that in Loopback mode MCR 4 set to one the dtr_n output is held inactive high while the value of this location is inte
284. is register can only be written if the DVFS function is disabled 5 3 31 PMU VF Table Register 15 Offset OxBC Register Name PMU VF TABLE REG15 f Read W Default wots Bit f Description rite Hex 31 11 E CPU MAX FREQ 145 10 0 R W X CPU max frequency if cpuvdd 1 45v unit MHz This register can only be written if the DVFS function is disabled 5 3 32 PMU VF Table Register 16 Offset OxCO Register Name PMU_VF_TABLE_REG16 Bit KSE E Description rite Hex 31 11 CPU_MAX_FREQ_150 10 0 R W X CPU max frequency if cpuvdd 1 5v unit MHz This register can only be written if the DVFS function is disabled 5 3 33 PMU VF Table Register 17 Offset OxC4 Register Name PMU_VF_TABLE_REG17 Read W Default SS Bit i Description rite Hex 31 11 CPU MAX FREQ 155 10 0 R W X CPU max frequency if cpuvdd 1 55v unit MHz This register can only be written if the DVFS function is disabled 5 3 34 PMU VF Table Register 18 Offset OxC8 Register Name PMU_VF_TABLE_REG18 Read W Default a Bit i Description rite Hex 31 11 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 42 Allwinner Technology 10 0 RW CPU MAX FREQ 160 CPU max frequency if cpuvdd 1 6v unit MHz This register can only be written if the DVFS function is disabled 5 3 35 PMU VF Table Valid Register Offset OxCC Register Name PMU_VF_TABLE_V
285. ister that contains the baud rate divisor for the UART This register may only be accessed when the DLAB bit LCR 7 is set and the UART is not busy USR 0 is zero 7 0 R W 0 The output baud rate equals to the serial clock sclk frequency A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 178 Allwinner Technology divided by sixteen times the value of the baud rate divisor as follows baud rate serial clock freq 16 divisor Note that with the Divisor Latch Registers DLL and DLH set to zero the baud clock is disabled and no serial communications occur Also once the DLL is set at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting or receiving data 19 4 4 UART Divisor Latch High Register Register Name UART DLH Offset 0x04 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 DLH Divisor Latch High Upper 8 bits of a 16 bit read write Divisor Latch register that contains the baud rate divisor for the UART This register may only be accessed when the DLAB bit LCR 7 is set and the UART is not busy USR 0 is zero The output baud rate equals to the serial clock sclk frequency divided by sixteen times the value of the baud rate divisor as follows baud rate serial clock freq 16 divisor Note that with the Divisor Latch Registers DLL and DLH
286. it resets At the beginning of a count period cycle the PWMOUT is set to activate state and count from 0x0000 The PWM divider divides the clock 24MHz by 1 4096 according to the pre scalar bits in the PWM control register In PWM cycle mode the output will be a square waveform the frequency is set to the period register In PWM pulse mode the output will be a positive pulse or a negative pulse 10 2 PWM Register List Module Name Base Address PWM 0x01C20C00 Register Name Offset Description PWM_CTRL_REG 0x0200 PWM Control Register PWM CHO PERIOD REG 0x0204 PWM Channel 0 Period Register 10 3 PWM Register Description 10 3 1 PWM Control Register Default 0x00000000 Offset 0x200 Register Name PWM CTRL REG f Read W Default Bit Description rite Hex 31 30 29 R W 0x0 PWMO RDY PWMO period register ready SS SC pe 0 PWMO period register is ready to write 1 PWMO period register is busy 2725 24 RW 0x0 23 R W 0x0 22 R W 0x0 21 R W 0x0 20 R W 0x0 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 82 Allwinner Technology 19 RW Ox0 18 15 RW Ox0 14 10 R W 0x0 PWMO_BYPASS PWM CHO bypass enable If the bit is set to 1 PWMO s output is OSC24MHz 0 disable 1 enable RW Ox0 PWM CHO PUL START
287. it will clear RW Ox0 NDMA2 END IRQ PEND Normal DMA2 End Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear RW Ox0 NDMA2 HF IRQ PEND Normal DMA2 Half Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear RW Ox0 NDMA1 END IRQ PEND Normal DMA 1 End Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear RW Ox0 NDMA1 HF IRQ PEND A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 136 Allwinner Technology Normal DMA 1 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending RW Ox0 NDMAO END IRQ PEND Normal DMA 0 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending RW Ox0 NDMAO HF IRQ PEND Normal DMA 0 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 14 4 3 Normal DMA Configuration Register Default 0x00000000 N 0 7 Offset 0x100 N 0x20 N 0 1 2 3 4 5 6 7 Register Name NDMA CTRL REG Read Wr Default Se Bit Description ite Hex NDMA LOAD DMA Loading 31 RW 036 If set to 1 DMA will start and load the DMA registers to the shadow registers The bit will hold on until the DMA finishes It will be cleared automatically Set 0 t
288. ite Default Description 31 7 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 390 Allwinner Technology Debounce Clock Pre scale n 6 4 R W 0 The selected clock source is prescaled by 2 3 1 PIO Interrupt Clock Select 0 32KHz 0 R W 0 1 24MHz A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 391 Allwinner Technology 34 Declaration This A13 user manualis the original work and copyrighted property of Allwinner Technology Allwinner Reproduction in whole or in part must obtain the written approval of Allwinner and give clear acknowledgement to the copyright owner The information furnished by Allwinner is believed to be accurate and reliable Allwinner reserves the right to make changes in circuit design and or specifications at any time without notice Allwinner does not assume any responsibility and liability for its use Nor for any infringements of patents or other rights of the third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Allwinner This user manual neither states nor implies warranty of any kind including fitness for any particular application A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 392
289. ites the content of this register to HCCA It also sets the WritebackDoneHead of HcinterruptStatus 3 0 R R Ox0 HcDoneHead 3 0 Because the general TD length is 16 bytes the memory structure for the TD must be aligned to a 16 byte boundary So the lower bits in the PCED bit 0 to bit 3 must be zero in this field 22 6 14 HcFminterval Register Offset 0x434 Register Name HcFminterval Register Default Value 0x2EDF Bit Read Write HCD HC Default Description 31 R W 0x0 FramelntervalToggler HCD toggles this bit whenever it loads a new value to Framelnterval 30 16 R W 0x0 FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame The counter value represents the largest amount of data in bits which can be sent or received by the HC in a single transaction at any given time without causing scheduling overrun The field value is calculated by the HCD 15 14 0x0 Reserved 13 0 R W R Ox2edf Framelnterval This specifies the interval between two consecutive SOFs in bit times The nominal value is set to be 11 999 HCD should store the current value of this field before resetting HC By setting the HostControllerReset field of HcCommandStatus as this will cause the HC to reset this field to its nominal value HCD may choose to restore the stored
290. ived Data mode or FIFOs disabled 0100 Second disabled or RCVR FIFO Available or the FIFO drops below trigger level reached FIFO mode and FIFOs enabled eer mode and FIFOs enabled No characters in or out of the Character RCVR FIFO during the last 4 EE 1100 Second Timeout character times and there is g j EE De buffer register Indication at least 1character in it during This time Reading the IIR register if source of interrupt or Transmitter holding register S i upt writing into THR FIFOs or Transmit empty Program THRE Mode THRE Mode not selected 0010 Third Holding disabled or XMIT FIFO at or or disabled or XMIT FIFO Register Empty below threshold Program THRE Mode enabled above threshold FIFOs and THRE Mode selected and enabled Clear to send or data set ready or ring indicator or data carrier detect Note that if Reading the Modem status 0000 Fourth Modem Status auto flow control mode is Re Ge s enabled a change in CTS g that is DCTS set does not cause an interrupt UART 16550 COMPATIBLE NO and master has tried to Busy Detect Reading the UART stat 0111 Fifth oe write to the Line Control Gre R re Register while the UART is q busy USR 0 is set to one 19 4 7 UART FIFO Control Register Offset 0x08 Register Name UART FCR A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 181 Allwinner Technology Default Value 0x0000 0000
291. ivider AXI GATING REG 0x005C AXI Module Clock Gating AHB_GATING_REGO 0x0060 AHB Module Clock Gating 0 AHB GATING REG1 0x0064 AHB Module Clock Gating 1 APBO GATING REG 0x0068 APBO Module Clock Gating APB1 GATING REG 0x006C APB1 Module Clock Gating NAND SCLK CFG REG 0x0080 Nand Flash Clock 0x0084 SDO_SCLK_CFG_REG 0x0088 SDO Clock SD1_SCLK_CFG_REG 0x008C SD1 Clock SD2_SCLK_CFG_REG 0x0090 SD2 Clock 0x0094 0x0098 SS SCLK CFG REG 0x009C Security System Clock SPI0 SCLK CFG REG Ox00A0 SPIO Clock SPI 1 SCLK CFG REG Ox00A4 SPI1 Clock SPI2 SCLK CFG REG 0x00A8 SPI2 Clock 0x00AC IR SCLK CFG REG 0x00BO IR Clock 0x00B4 0x00B8 0x00BC 0x00C0 0x00C4 0x00C8 0x00CC A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 52 Allwinner Technology 0x00D0 0x00D4 DRAM_SCLK_CFG_REG 0x0100 DRAM Clock BE_CFG_REG 0x0104 Display Engine Backend Clock 0x0108 FE_CFG_REG 0x010C Display Engine Front End Clock 0x0110 0x0114 0x0118 0x011C 0x0120 0x0124 0x0128 LCD_CH1_CFG_REG 0x012C LCD Channel1 Clock 0x0130 CSI CFG REG 0x0134 CSI Clock 0x0138 VE_CFG_REG 0x013C Video Engine Clock AUDIO_CODEC_SCLK_CFG_REG 0x0140 Audio Codec Gating Special Clock AVS SCLK CFG REG 0x0144 AVS Gating Special Clock 0x0148 0x014C 0x0150 MALI_CLOCK_CFG_REG
292. k 1 pass 4 3 RW 0x0 2 1 R W 0x0 CODEC_APB_GATING 0 RW 0x0 Gating APB Clock for Audio CODEC 0 mask 1 pass A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 64 Allwinner Technology 6 4 20 APB1 Module Clock Gating Default 0x00000000 Offset Ox6C Register Name APB1 GATING REG Bit set SE Description 31 24 23 22 21 20 19 RW oxo GE Gating APB Clock for UART3 0 mask 1 pass 18 R W 0x0 17 RW en FART _APB_GATING Gating APB Clock for UART1 0 mask 1 pass 16 R W 0x0 15 8 7 6 5 4 3 TWI2_APB_GATING 2 R W 0x0 Gating APB Clock for TWI2 0 mask 1 pass TWI1 APB GATING 1 R W 0x0 l Gating APB Clock for TWI1 0 mask 1 pass 0 RW SR TWO APE ATING Gating APB Clock for TWIO 0 mask 1 pass 6 4 21 NAND Clock Default 0x00000000 Offset 0x80 Register Name NAND SCLK CFG REG Bit Ass SS Description rite Hex SCLK GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK SRC SEL Clock Source Select 25 24 RW 0x0 00 OSC24M 01 PLL6 10 PLL5 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 65 Allwinne
293. l The value in this field is used by system software to select the maximum rate at which the host controller will issue interrupts The only valid values are defined below Value Minimum Interrupt Interval 0x00 Reserved 0x01 1 micro frame 0x02 2 micro frame 0x04 4 micro frame 0x08 8 micro frame default equates to 1 ms 0x10 16 micro frame 2ms 0x20 32 micro frame 4ms 0x40 64 micro frame 8ms Any other value in this register yields undefined results The default value in this field is 0x08 Software modifications to this bit while HC Halted bit equals to zero 23 16 R W 0x08 results in undefined behavior Reserved 15 12 0 These bits are reserved and should be set to zero 11 R W or R 0 Asynchronous Schedule Park Mode Enable OPTIONAL A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 203 Allwinner If the Asynchronous Park Capability bit in the HCCPARAMS register is a one then this bit defaults to a 1 and is R W Otherwise the bit must be a zero and is Read Only Software uses this bit to enable or disable Park mode When this bit is one Park mode is enabled When this bit is zero Park mode is disabled Reserved These bits are reserved and should be set to zero Asynchronous Schedule Park Mode Count OPTIONAL Asynchronous Park Capability bit in the HCCPARAMS register is a one Then this field defaults
294. l Register Default 0x00000004 Offset 0x30 Register Name ASYNC TMR2 CTRL REG Bit Read W rite Default Hex Description 31 8 R W 0x0 TMR2_EN Timer2 mode 0 Continuous mode When reaches the internal value the timer will not be disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically 6 4 R W 0x0 TMR2_CLK_PRESCALE Select the pre scale of timer 2 clock source 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 3 2 R W 0x1 TMR2_CLK_SRC A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 90 Allwinner Technology Timer 2 Clock Source 00 01 OSC24M 1x TMR2_RELOAD Timer 2 Reload 1 R W 0x0 0 No effect 1 Reload timer 2 Interval value After the bit is set it can not be written again before its cleared automatically TMR2_EN Timer 2 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is 0 R W 0x0 set to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer
295. l polarity 1s invert the specify output 29 3 28 TCON1 IO TRI REG Offset 0x0F4 Register Name TCON1 IO control register Bit Read W rite Default Hex Description 31 28 27 R W IO3 Output Tri En 1 disable 0 enable 26 R W 102_Output_Tri En 1 disable 0 enable 25 RW 101_ Output Tri En 1 disable 0 enable 24 R W 100 Output Tri En 1 disable 0 enable 27 0 RW OXFFFF FF Data Output _ Tri En TCON1 output port D 23 0 output enable with independent bit control 1s disable Os enable 29 3 29 TCON CEU CTL REG Offset 0x100 Register Name TCON CEU control register Read W Default nr Bit Description rite Hex CEU_en 31 R W 0 0 bypass 1 enable 30 0 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 347 Allwinner Technology 29 3 30 TCON CEU COEF REG Offset 0x110 118 0x120 0x128 0x130 0x138 Register Name TCON CEU multiplier coefficient register Read W Default Kee Bit Description rite Hex 31 13 12 0 RW 0 OPU eet Mul le signed 13bit value range of 16 16 Offset x11C 0x12C 0x13C Register Name TCON CEU add coefficient register Read W Default a Bit Description rite Hex 31 19 CEU Coef Add Value 180 RW lo Ne signed 19bit value range o
296. l volume control dvc ATT DVC 5 0 2 1 16dB A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 235 Allwinner Technology 62 steps 1 16dB step 11 0 23 4 2 DAC FIFO Control Register Offset 0x4 Register Name AC DAC FIFOC Bit Read Write Default Description 31 29 RW Ox0 DAC FS Sample Rate of DAC 000 48KHz 010 24KHz 100 12KHz 110 192KHz 001 32KHz 011 16KHz 101 8KHz 111 96KHZ 44 1KHz 22 05KHz 11 025KHz can be supported by Audio PLL Configure Bit 28 R W R W FIR Version 0 64 Tap FIR 1 32 Tap FIR 27 26 R W 0x0 SEND_LASAT Audio sample select when TX FIFO under run 0 Sending zero 1 Sending last audio sample 25 24 R W 0x0 For 24 bits transmitted audio sample 0 FIFO 1 23 0 TXDATA 31 8 1 Reserved For 16 bits transmitted audio sample 0 FIFO 1 23 0 TXDATA 31 16 8 b0 1 FIFO 1 23 0 TXDATA 15 0 8 bO 23 22 21 RW Ox0 DAG DRQ CLR CNT When TX FIFO available room less than or equal N DRQ Request will be de asserted N is defined here 000 IRQ DRQ Deasserted when WLEVEL gt TXTL 01 4 10 8 11 16 20 15 14 8 RW 0x10 TX FIFO Empty Trigger Level TXTL 6 0 Interrupt and DMA request trigger level for TX FIFO normal A13 User Manual V1 3 Copyrig
297. le 1 0 R W 0x0 PTDBS HPCOM protect de bounce time setting 00 2 3ms 01 4 6ms 10 8 12ms 11 16 24ms 23 4 10 DAC TX Counter Register Offset 0x30 Register Name AC_DAC_CNT Bit Read Write Default Description TX_CNT 31 0 R W 0x0 TX Sample Counter A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 244 Allwinner Technology The audio sample number of sending into TXFIFO When one sample is put into TXFIFO by DMA or by host IO the TX sample counter register increases by one The TX sample counter register can be set to any initial valve at any time After been updated by the initial value the counter register should count on base of this initial value Notes It is used for Audio Video Synchronization 23 4 11 ADC RX Counter Register Offset 0x34 Register Name AC_ADC_CNT Bit Read Write Default Description RX_CNT RX Sample Counter The audio sample number of writing into RXFIFO When one sample is written by Digital Audio Engine the RX sample counter register increases by one The RX sample counter register can be set to any initial valve at any time After been updated by the initial value the counter register should count on base of this initial value 31 0 R W 0x0 Notes It is used for Audio Video Synchronization A13 User Manual V1 3 Copyright 2013 Allwinner Technolog
298. levels FIFO 1 mono 32 levels FIFO When set to 1 Only left channel samples are recorded RW Ox0 RX SAMPLE BITS Receiving Audio Sample Resolution 0 16 bits 1 24 bits RW Ox0 ADC DRQ EN ADC FIFO Data Available DRQ Enable 0 Disable 1 Enable R W 0x0 ADC_IRQ_EN ADC FIFO Data Available IRQ Enable 0 Disable 1 Enable R W 0x0 ADC_OVERRUN_IRQ_EN ADC FIFO Over Run IRQ Enable 0 Disable 1 Enable R W 0x0 ADC_FIFO_FLUSH ADC FIFO Flush Write 1 to flush TX FIFO self clear to 0 23 4 7 ADC FIFO Status Register Offset 0x20 Register Name AC_ADC_FIFOS Bit Read Write Default Description 31 24 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 241 23 Allwinner Technology Ox0 RXA RX FIFO Available 0 No available data in RX FIFO 1 More than one sample in RX FIFO gt 1 word 22 14 13 8 Ox0 RXA CNT RX FIFO Available Sample Word Counter 7 4 R W 0x0 RXA INT RX FIFO Data Available Pending Interrupt 0 No Pending IRQ 1 Data Available Pending IRQ Write 1 to clear this interrupt or automatic clear if interrupt condition fails R W 0x0 RXO INT RX FIFO Overrun Pending Interrupt 0 No Pending IRQ 1 FIFO Overrun Pending IRQ Write 1 to clear this interrupt
299. lf Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 23 RW Ox0 DDMA3 END IRQ PEND Dedicated DMA 3 End Transfer Interrupt Pending Set 1 to the bit will clearit 0 No effect 1 Pending 22 RW Ox0 DDMA3 HF IRQ PEND Dedicated DMA 3 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 21 R W 0x0 DDMA2 END IRQ PEND Dedicated DMA 2 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 20 RW Ox0 DDMA2 HF IRQ PEND Dedicated DMA 2 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 19 RW Ox0 DDMA1 END IRQ PEND Dedicated DMA 1 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 18 RW Ox0 DDMA1 HF IRQ PEND Dedicated DMA 1 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 17 R W 0x0 DDMAO END IRQ PEND Dedicated DMA 0 End Transfer Interrupt Pending Set 1 to the bit will clearit 0 No effect 1 Pending 16 RW Ox0 DDMAO HF IRQ PEND Dedicated DMA 0 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 15 RW Ox0 NDMA7 END IRQ PEND Normal DMA 7 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 14
300. ller too 1 enable the write back only control the data won t transfer to LCD controller Write back enable 0 disable 1 enable The bit will be cleared when write back ends 30 2 9 DRC Write Back Address Register Offset 0X0028 Register Name IMGEHC_WBADD_REG f Read Wr Default ee Bit Description ite Hex 31 0 R W Weeder l The start address of write back data in BYTE A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 353 Allwinner Technology 30 2 10 DRC Write Back Buffer Line Width Register Offset 0X002c Register Name IMGEHC WBLINEWIDTH REG Read Wr Default oie Bit Description ite Hex 31 0 RW WB_LINEWIDTH i Write back image buffer line width in BYTE 30 2 11 Luminance Histogram Control Register Offset 0X0030 Register Name IMGEHC_LHC_REG f Read Wr Default e Bit Description LH_MOD 0 Current frame case 1 Average case LH_REC_CLR If the bit is set all of the luminance statistics recording registers will be cleared and the bit will self clear when the recording registers is cleared 30 2 12 Luminance Histogram Threshold Setting Register 0 Offset 0X0034 Register Name IMGEHC_LHT_REGO Read Wr Default SCH Bit Description ite Hex 31 24 R W 0x80 Ph TRES VALA Step4 threshold value 23 16 RW 0x60 LH_THRES_VAL3 Step3 threshold value 15 08 RW 0x40 LH THRES VAL2 Step threshold value 07 00 RW 0x20 LH_THRES_VAL1 Ste
301. me ASYNC_TMR4_INTV_VALUE_REG Read W Default Bit Description rite Hex 31 0 R W X TMR4_INTV_VALUE A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 93 Allwinner Technology Timer 4 Interval Value Note the value setting should consider the system clock and the timer clock source 11 3 16 ASYNC Timer 4 Current Value Register Offset 0x58 Register Name ASYNC TMR4 CURNT VALUE REG Read W Default E Bit Description rite Hex TMR4_CUR_VALUE SE ST Timer 4 Current Value Note 1 Timer current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale 2 Before the timer 4 is enabled its current value register needs to be written with zero 11 3 17 ASYNC Timer 5 Control Register Default 0x00000004 Offset 0x60 Register Name ASYNC_TMR5_CTRL_REG Read W Bit rite Default Hex Description 31 8 Ox0 TMR5 MODE Timer5 mode 0 Continuous mode When reaches the internal value the timer will not be disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically 6 4 R W 0x0 TMR5_CLK_PRESCALE Select the pre scale of timer 5 clock source 000 1 001 2 010 4 011 8 100 16 101 32
302. msmineivktninbuaknankadnknenddnn 321 28 5 19 DEBE Write Back Address Register 322 28 5 20 DEBE Write Back Buffer Line Width Register 322 28 5 21 DEBE Input YUV Channel Control Register 323 28 5 22 DEBE YUV Channel Frame Buffer Address Register 324 28 5 23 DEBE YUV Channel Buffer Line Width Register cessessceseeeeeseeeseeseeeeeeeees 324 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 16 Allwinner Technology 28 5 24 DEBE de Ee EE 325 28 5 25 DET GS FP ESS a 325 28 5 26 DEBE UR Coefficient REgsler Luihn huh hnhehuhnnltinthetnct 325 28 5 27 DEBE U R Constant Register See ne ni nn ee 325 28 5 28 DEBE V B Coefficient Register ccc 326 28 5 29 DEBE V B Constant Register vaar mek nakne 326 28 5 30 DEBE Output Color Control Register mumier enda 326 28 5 31 DEBE Output Color R Coefficient Register 327 28 5 32 DEBE Output Color R Constant Register a6 cece ee 327 28 5 33 DEBE Output Color G Coefficient Register icici nics 327 28 5 34 DEBE Output Color G Constant Register 328 28 5 35 DEBE Output Color B Coefficient Register 328 28 5 36 DEBE Output Color B Constant Register egener 328 28 5 37 DE HWC Pattern Memory Block euer 328 28 5 38 DE HWC PE reece 329 28 51 99 Paete Mode eee eee eee eae ee 330 28 5 40 Internal Frame Buffer Mode AAA 331 28 5 41 Internal Frame Buffer Mode Palette Table AAA 331 28 5 42 Gamma Correction Modes nn 332 28 6 Display Engine Memor
303. n Writing 1 to this bit clears it R W 0 RO RXFIFO Overflow When set this bit indicates that RXFIFO has overflowed Writing 1 to this bit clears it 0 RXFIFO is available 1 RXFIFO has overflowed R W 0 RXFIFO 3 4 Full This bit is set when the RXFIFO is 3 4 full Writing 1 to this bit clears it 0 Not 3 4 Full 1 3 4 Full R W 0 RXFIFO 1 4 Full This bit is set when the RXFIFO is 1 4 full Writing 1 to this bit clears it 0 Not 1 4 Full 1 1 4 Full A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 171 Allwinner Technology RW RF RXFIFO Full This bit is set when the RXFIFO is full Writing 1 to this bit clears it 0 Not Full 1 Full R W RHF RXFIFO Half Full This bit is set if the RXFIFO is half full gt 4 words in RXFIFO Writing 1 to this bit clears it 0 Less than 4 words are stored in RXFIFO 1 Four or more words are available in RXFIFO R W RR RXFIFO Ready This bit is set any time there is one or more words stored in RXFIFO 1 words Writing 1 to this bit clears it 0 No valid data in RXFIFO 1 More than 1 word in RXFIFO 18 4 6 SPI DMA Control Register Offset 0x14 Register Name SPI_DMACTL Default Value 0x0000 0000 Bit Read Write Default Description 31 13 12 RW TXFIFO3 4 Empty DMA Request Enable 0 Disable 1 Enable
304. n Alpha Blender1 1x Reserved Only 2 channels pixel data can get to Alpha Blender1 at the same screen coordinate LAY_PIPESEL Pipe Select 0 select Pipe 0 1 select Pipe 1 LAY PRISEL Priority The rule is 11 gt 10 gt 01 gt 00 When more than 2 layers are enabled the priority value of each layer must be different so designers must keep the condition If more than 1 layers select the same pipe in the overlapping area only the pixel of highest priority layer can pass the pipe to blender1 If both 2 pipes are selected by layers in the overlapping area the alpha value will use the alpha value of higher priority layer in the blender1 LAY_YUVEN YUV channel selection 0 disable 1 enable Setting 2 or more layers YUV channel mode is illegal so programmers should confirm it LAY_VDOEN Layer video channel selection enable control 0 disable Copyright 2013 Allwinner Technology All Rights Reserved 315 Allwinner Technology 1 enable Normally one layer can not be set both video channel and YUV channel mode If both 2 mode are set the layer will work in video channel mode and YUV channel mode will be ignored so programmers should confirm it Setting 2 or more layers video channel mode is illegal and programmers should confirm it LAY GLBALPHAEN Alpha Enable 0 Disabled the alpha value of this register 1 Enabled the alpha value of this register for the layer 28 5 14 DE Layer Attribute Cont
305. n TCONO_EN 1 3 2 TCONO SRC SEL 00 DE CH1 FIFO1 enable 01 DE CH2 FIFO1 enable 10 DMA 565 input FIFO1 enable 11 Test intput FIFO1 disable 1 0 RW 0 Note These bits are sampled only at the beginning of the first blank line of TCONO timing Generally when input source changes it will change at the beginning of the first blank line of TCONO timing When FIFO1 and FIFO2 select the same source and FIFO2 is enabled it executes at the beginning of the first blank line of TV timing Also TCONO timing generator will reset to the beginning of the first blank line 29 3 8 TCONO DCLK REG Offset 0x044 Register Name TCONO data clock register Read W Default a Bit Description rite Hex 31 R W 0 TCONO_Dclk_En 30 6 TCONO_Dclk_Div 6 0 RW 0 Tdclk Tsclk DCLKDIV Note 1 if dclk1 amp dclk2 used DCLKDIV gt 6 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 339 Allwinner Technology 2 if dclk only DCLKDIV gt 4 29 3 9 TCONO BASICO REG Offset 0x048 Register Name TCONO basic timing register0 Read W Default EE Bit Description rite Hex 31 27 TCONO_X eae oe Panel width is X 1 15 11 TCONO_Y 10 0 R W 0 EON Panel height is Y 1 29 3 10 TCONO BASIC1 REG Offset 0x04C Register Name TCONO basic timing register1 Read W Default or Bit i D
306. n of transmission and setup overhead 22 6 19 HcRhDescriptorA Register Offset 0x448 Register Name HcRhDescriptorA Default Value Read Write Bit HCD HC Default Description PowerOnToPowerGoodTime POTPGT This byte specifies the duration HCD has to wait before accessing a powered on port of the Root Hub It is implementation specific The unit of time is 2 ms The duration is calculated as POTPGT 31 24 RW R 0x2 2ms 23 13 Reserved NoOverCurrentProtection This bit describes how the overcurrent status for the Root Hub ports are reported When this bit is cleared the OverCurrentProtectionMode field specifies global or per port reporting 0 Over current status is reported collectively for all downstream ports 12 RW R 1 1 No overcurrent protection supported OverCurrentProtectionMode This bit describes how the overcurrent status for the Root Hub ports are reported At reset these fields should reflect the same mode as PowerSwitchingMode This field is valid only if the NoOverCurrentProtection field is cleared 0 Over current status is reported collectively for all downstream ports 11 RW R 0 1 Over current status is reported on per port basis Device Type This bit specifies that the Root Hub is not a compound device The 10 R R 0x0 Root Hub is not permitted to be a compound device This field A13 User Manual V1 3 Copyright 2013 Allwinner T
307. n ri_n since last read of MSR 1 change on ri_n since last read of MSR Reading the MSR clears the TERI bit DDSR Delta Data Set Ready This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read 0 no change on dsr_n since last read of MSR 1 change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit In Loopback Mode MCR 4 1 DDSR reflects changes on MCR 0 DTR Note If the DDSR bit is not set and the dsr_n signal is asserted low and a reset occurs software or otherwise the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted 0 R 0 DCTS Delta Clear to Send This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read 0 no change on ctsdsr_n since last read of MSR 1 change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit In Loopback Mode MCR 4 1 DCTS reflects changes on MCR 1 RTS Note If the DCTS bit is not set and the cts_n signal is asserted low and a reset occurs software or otherwise the DCTS bit is set when the reset is removed if the cts_n signal remains asserted 19 4 12 UART Scratch Register Offset 0x1C Register Name UART_SCH A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 189 Allwinner Technology Default Value 0x0
308. n with a peripheral modem data carrier equipment DCE or data set 7 DMA Direct Memory Access A feature of modern computers that allow certain hardware subsystems within the computer to access system memory independently of the CPU 8 PWM Pulse Width Modulation A commonly used technique for controlling power to inertial electrical devices made practical by modern electronic power switches 9 Audio Codec Audio Codec A computer program implementing an algorithm that compresses and decompresses digital audio data according to a given audio file format or streaming media audio format 10 SD 3 0 Security Digital 3 0 A non volatile memory card format developed by the SD Card Association for use in portable devices 11 USB DRD USB Dual role Device dual role controller which supports both Host and device functions and is full compliant with the On The Go A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 2 Allwinner Technology Supplement to the USB 20 Specification Revision 1 0a 12 EHCI Enhanced Host Controller a high speed controller standard that is Interface publicly specified A register level interface that enables a host controller for USB or FireWire 13 OHCI Open Host Controller Interface hardware to communicate with a host controller driver in software 14 TP Touch Panel A Human Machine Interactive Interfa
309. nally goes to a Ob when the Configured bit in the CONFIGFLAG register makes a Ob to 1b transition This bit unconditionally goes to 1b whenever the Configured bit is zero System software uses this field to release ownership of the port to selected host controller in the event that the attached device is not a high speed device Software writes a one to this bit when the attached device is not a high speed device A one in this bit means that a companion host controller owns and controls the port 13 R W 1 Default Value 1b 12 0 Reserved A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 211 Allwinner Technology These bits are reserved for future use and should return a value of zero when read 11 10 Line Status These bits reflect the current logical levels of the D bit11 and D bit10 signal lines These bits are used for detection of low speed USB devices prior to port reset and enable sequence This read only field is valid only when the port enable bit is zero and the current connect status bit is set to a one The encoding of the bits are Bit 11 10 USB State Interpretation 00b SEO Not Low speed device perform EHCI reset 10b J state Not Low speed device perform EHCI reset 01b K state Low speed device release ownership of port 11b Undefined Not Low speed device perform EHCI reset This value of this field is undefined if Port Power is zero
310. nd X to GND The X plate becomes a potential divider and the voltage at the point of contact is proportional to its X co ordinate This voltage is measured on the Y which carry no current hence there is no voltage drop in Ry or Ry Due to the ratiometric measurement method the supply voltage does not affect measurement accuracy The voltage references VREF and VREF are taken from after the matrix switches so that any voltage drop in these switches has no effect on the ADC measurement Y co ordinate measurements are similar to X co ordinate measurements with the X and Y plates interchanged In Single Touch mode only need to test X Y signal X POSITION A X O 3 3 TOUCH ND X POSITION Geen O Figure25 10 Single Touch X Position Measurement 25 4 5 Dual Touch Detection The principle of operation is illustrated below For an X co ordinate measurement the X pin is internally switched to AVCC and X to GND The X plate becomes a potential divider and the voltage at the point of contact is proportional to its X co ordinate This voltage is measured on the Y and Y which carry no current hence there is no voltage drop in Ry or Ry Due to the ratiometric measurement method the supply voltage does not affect measurement accuracy The voltage references VREF and VREF are taken from after the matrix switches so that any voltage drop in these switches has no effect on the ADC measurement the controller will ne
311. nts M lt A Not possible because the median filter SES is always larger than the averaging window size Table25 3 Median Averaging Filters MAVF Example In this example MED1 MEDO 11 and AVG1 AVGO 10 the median filter has a window size of 16 This means that 16 measurements are taken and arranged in descending order in a temporary array The averaging window size in this example is 8 The output is the average of the middle eight values of the 16 measurements taken with the median filter FIFO srac lt TR In Taxe 16 Measurements Average Of Middle Converted Results Arranged 8 Values 2 1 1 3 2 2 5 3 3 1 4 4 6 5 5 7 6 6 9 7 7 8 8 8 M 16 A 8 10 9 9 12 10 10 11 11 11 15 12 12 y 13 13 13 4 14 14 16 15 15 14 16 y 16 Figure 25 14 Median and Averaging Filter Example 25 5 TP Register List Module Name Base Address TP 0x01C25000 Register Name Offset Description TP_CTRLO 0x00 TP Control RegisterO TP_CTRL1 0x04 TP Control Register1 TP Pressure Measurement and touch sensitive TP_CTRL2 0x08 Control Register TP_CTRL3 OxOc Median filter Controller Register A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 259 All
312. ny time It can also be paused by setting AVS CNT1 PS to 1 When it is paused the counter won t increase 11 3 23 AVS Counter Divisor Register Default 0x05DB05DB Offset 0x8C Register Name AVS CNT DIVISOR REG Bit Read Write Default Description 31 28 27 16 R W 0x5DB AVS_CNT1_D Divisor N for AVS Counter The number N is from 1 to 0x7ff The zero value is reserved The internal 33 bits counter engine will maintain another 12 bits counter The 12 bits counter is used for counting the cycle number of one 24Mhz clock When the 12 bits counter reaches gt N the divisor value the internal 33 bits counter register will increase 1 and the 12 bits counter will reset to zero and restart again Notes It can be configured by software at any time 15 12 11 0 R W 0x5DB AVS CNTO D Divisor N for AVS Counter0 The number N is from 1 to 0x7ff The zero value is reserved The internal 33 bits counter engine will maintain another 12 bits counter The 12 bits counter is used for counting the cycle number of one 24Mhz clock When the 12 bits counter reaches gt N the divisor value the internal 33 bits counter register will increase 1 and the 12 bits counter will reset to zero and restart again Notes It can be configured by software at any time 11 3 24 Watchdog Control Register Offset 0x90 Register Name WDOG CTRL REG
313. o be transferred A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 138 Allwinner Technology 14 10 10 9 R W 0x0 NDMA SRC DATA WIDTH Normal DMA Source Data Width 00 8 bit 01 16 bit 10 32 bit 11 8 7 R W 0x0 NDMA SRC BST LEN DMA Source Burst Length 00 1 01 4 10 8 11 R W 0x0 NDMA_SRC_ADDR_TYPE Normal DMA Source Address Type 0 Increment 1 No Change 4 0 R W 0x0 NDMA_SRC_DRQ_TYPE Normal DMA Source DRQ Type 00000 IR RX 00001 00010 00011 00100 00101 00110 00111 01000 01001 UART1 RX 01010 01011 UART3 RX 01100 01101 01110 01111 10000 10001 10010 10011 Audio Codec A D 10100 10101 SRAM range 10110 SDRAM 10111 TP A D ee ene B ss OS J nes ES Se Gar 80 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 139 Allwinner Technology 11000 SPIO RX 11001 SPI1 RX 11010 SPI2 RX 11011 USB EP1 11100 USB EP2 11101 USB EP3 11110 USB EP4 11111 USB EP5 14 4 4 Normal DMA Source Address Register Default 0x00000000 Offset 0x100 N 0x20 0x4 N 0 1 2 3 4 5 6 7 Register Name NDMA_SRC_ADDR_REG Read W Default er Bit Description rite Hex 31 0 RW NDMA SRC ADDR Normal DMA Source
314. o the bit will reset the corresponding DMA channel NDMA CONTI EN 30 RW 0x0 DMA Continuous Mode Enable 0 Disable 1 Enable NDMA_WAIT_STATE DMA Wait State 29 27 R W 0x0 0 wait for 0 DMA clock to request 7 wait for 2 n 1 DMA clock to request NDMA DST DATA WIDTH Normal DMA Destination Data Width 00 8 bit 26 25 R W 0x0 01 16 bit 10 32 bit 11 NDMA DST BST LEN DMA Destination Burst Length 00 1 24 23 R W 0x0 Sed 10 8 11 22 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 137 Allwinner Technology 21 RW Ox0 NDMA DST ADDR TYPE Normal DMA Destination Address Type 0 Increment 1 No Change 20 16 RW Ox0 NDMA DST DRQ TYPE Normal DMA Destination DRQ Type 00000 IR TX 00001 00010 00011 00100 00101 00110 00111 01000 01001 UART1 TX 01010 01011 UART3 TX 01100 01101 01110 01111 10000 10001 10010 10011 Audio Codec D A 10100 10101 SRAM range 10110 SDRAM 10111 11000 SPIO TX 11001 SPI1 TX 11010 SPI2 TX 11011 USB EP1 11100 USB EP2 11101 USB EP3 11110 USB EP4 11111 USB EP5 S SI lt lt 15 R W 0x0 BC_MODE_SEL BC mode select 0 normal mode the value read back equals to the value that is written 1 remain mode the value read back equals to the remain counter t
315. ock Source O internal 32k 1 OSC24M 6 5 RW Ox0 TMR3_MODE Timer 3 mode 0 Continuous mode When reaches the internal value the timer will not be disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically 3 2 RW Ox0 TMR3 CLK PRESCALE Select the pre scale of timer 3 clock source 00 16 01 32 10 64 11 1 RW Ox0 TMR3 EN Timer 3 Enable 0 Disable 1 Enable Note the time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 11 3 13 ASYNC Timer 3 Interval Value Offset 0x44 Register Name ASYNGC TMR3 INTV VALUE REG f Read W Default EC Bit j Description rite Hex 31 0 RAW M TM R3_INTV_VALUE Timer 3 Interval Value 11 3 14 ASYNC Timer 4 Control Register Default 0x00000004 Offset 0x50 Register Name ASYNC_TMR4_CTRL_REG l Read W Default E Bit Description rite Hex 31 8 TMR4_MODE Timer4 mode 0 Continuous mode When reaches the internal value the timer will 7 R W 0x0 not be disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 92 Allwinner Technology 6 4 R W 0x0 TMR4_CLK_PRESCALE
316. odem or data set is ready to establish communications with UART 0 dsr_n input is de asserted logic 1 1 dsr_n input is asserted logic 0 In Loopback Mode MCR 4 set to one DSR is the same as MCR 0 DTR CTS Line State of Clear To Send This is used to indicate the current state of the modem control line cts_n This bit is the complement of cts_n When the Clear to Send input cts_n is asserted it is an indication that the modem or data set is ready to exchange data with UART 0 cts_n input is de asserted logic 1 1 cts_n input is asserted logic 0 In Loopback Mode MCR 4 1 CTS is the same as MCRf1 RTS A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 188 Allwinner Technology DDCD Delta Data Carrier Detect This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read 0 no change on ded n since last read of MSR 1 change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit Note If the DDCD bit is not set and the dcd_n signal is asserted low and a reset occurs software or otherwise then the DDCD bit is set when the reset is removed if the dcd n signal remains asserted TERI Trailing Edge Ring Indicator This is used to indicate that a change on the input ri n from an active low to an inactive high state has occurred since the last time the MSR is read 0 no change o
317. off power or operational bus error such as babble is detected This change also causes PortEnabledStatusChange to be set HCD sets this bit by writing SetPortEnable and clears it by writing ClearPortEnable This bit cannot be set when CurrentConnectStatus is cleared This bit is also set if not already at the completion of a port reset when ResetStatusChange is set or port suspend when SuspendStatusChange is set 0 port is disabled 1 port is enabled write SetPortEnable The HCD sets PortEnableStatus by writing a 1 Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortEnableStatus and sets ConnectStatusChange instead This informs the driver that it attempts to enable a disconnected 1 RW RW 0x0 Port read CurrentConnectStatus This bit reflects the current state of the downstream port 0 No device connected 1 Device connected write ClearPortEnable The HCD writes a 1 to clear the PortEnableStatus bit Writing 0 has no effect The CurrentConnectStatus is not affected by any 0 RW RW 0x0 write A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 232 Allwinner Technology Note This bit is always read as 1 when the attached device is non removable DviceRemoveable NumberDownstreamPort 22 7 USB Host Special Requirement Name Desc
318. ol F ert 34 5 3 7 PMU DVFS TimeOut Control Register Default 0Ox00000027 34 5 3 8 PMU IRQ VE 35 5 3 9 PMU IRQ Status Register oeiee es 36 5 3 10 e EECH 37 5 3 11 PMU CPUVDD DCDC Control Register Address Default 0x00000023 37 5 3 12 PMU TWI Address Default Ox00000068 37 5 3 13 PMU CPUVDD Value Default 0x00000016 eeben 37 5 3 14 PMU CPUVDD Voltage Ramp Control in DVM 38 5 3 15 PMU 32KHz CPUVDD Minimum Value Default Ox0000000C 38 5 3 16 PMU VF Table Register AE 39 5 3 17 PMU VF Table Register Less hier aient taire 39 5 3 18 PMU VF Table e EE 39 5 3 19 PMU VF Table ECHTEN Eege 39 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 4 Allwinner Technology 5 3 20 PMU VF Table Register 4 iss vee ie eed tle tlie 39 5 3 21 PMUNF Table Register da 40 5 3 22 PMU VF Table Register Busse tentent lake EE e 40 5 3 23 PMU VF Table Register 7 iii 40 5 3 24 PMU VF Table Register Brrr oere rere rerea aaora en ieee 40 5 3 25 PMU VF Table Register 9 arkade naa naa 41 5 3 26 PMU VF Table Register 10 iii 41 5 3 27 PMU VF Table Register 11 41 5 3 28 PMU VF Table Register 2vcicc cnet oni aie eee 41 5 3 29 PMUVF Table Register la 41 5 3 30 PMU VF Table Register l ann Anne nn kebaben 42 5 3 31 PMU VF Table Register 15 42 5 3
319. oller SIE features 64 Byte Endpoint 0 for Control Transfer Support up to 5 User Configurable Endpoints for Bulk Isochronous Control and Interrupt bi directional transfers Support High Bandwidth Isochronous amp Interrupt transfers Support point to point and point to multipoint transfer in both Host and Peripheral mode 21 2 USB DRD Timing Diagram Please refer USB2 0 Specification A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 197 Allwinner Technology 22 USB Host 22 1 Overview USB Host Controller is fully compliant with the USB 2 0 specification Enhanced Host Controller Interface EHCI Specification Revision 1 0 and the Open Host Controller Interface OHCI Specification Release 1 0a The controller supports high speed 480 Mbps transfers 40 times faster than USB 1 1 full speed mode using an EHCI Host Controller as well as full and low speeds through one or more integrated OHCI Host Controllers It features Include an internal DMA Controller for data transfer with memory Comply with Enhanced Host Controller Interface EHCI Specification Version 1 0 and the Open Host Controller Interface OHCI Specification Version 1 0a Support High Speed HS 480 Mbps Full Speed FS 12 Mbps and Low Speed LS 1 5 Mbps Device Support only one USB Root Port shared between EHCI and OHCI 22 2 USB Host Block Diagram The USB host controller System Level block d
320. on 31 8 RBR Receiver Buffer Register Data byte received on the serial input port sin in UART mode or the serial infrared input sir in in infrared mode The data in this register is valid only if the Data Ready DR bit in the Line Status Register LCR is set If in FIFO mode and FIFOs are enabled FCR 0 set to one this register accesses the head of the receive FIFO If the receive FIFO is full and this register is not read before the next data character arrives the data already in the FIFO is preserved but all incoming 7 0 R 0 data are lost and an overrun error occurs 19 4 2 UART Transmit Holding Register Register Name UART THR Offset 0x00 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 THR Transmit Holding Register Data to be transmitted on the serial output port sout in UART mode or the serial infrared output sir_out_n in infrared mode Data should only be written to the THR when the THR Empty THRE bit LSR 5 is set If in FIFO mode and FIFOs are enabled FCR 0 1 and THRE is set 16 number of characters of data may be written to the THR before the FIFO is full Any attempt to write data when the FIFO is 7 0 W 0 full results the write data lost 19 4 3 UART Divisor Latch Low Register Register Name UART DLL Offset 0x00 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 DLL Divisor Latch Low Lower 8 bits of a 16 bit read write Divisor Latch reg
321. on Async Advance Doorbell bit in the USBCMD register This status bit indicates the assertion of that interrupt source R WC 0 Host System Error The Host Controller set this bit to 1 when a serious error occurs during a host system access involving the Host Controller module When this error occurs the Host Controller clears the Run Stop bit in the Command register to prevent further execution of the scheduled TDs R WC 0 Frame List Rollover The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero The exact value at which the rollover occurs depends on the frame list size For example if the frame list size is 1024 the Frame Index Register rolls over every time FRINDEX 13 toggles Similarly if the size is 512 the Host Controller sets this bit to a one every time FRINDEX 12 toggles R WC 0 A13 User Manual V1 3 Port Change Detect The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J K transition detected on a suspended port This bit will also be set as a result of the Connect Status Chang being set to a one after system software has relinquished ownership of a connected port by writing a one to a ports Port Copyright 2013 Allwinner Technology All Rights Reserved 207
322. on zero value can speed up the scan operation 00 lowest 11 fastest 27 17 16 0x0 SPD_DET_SCN_FIN Speed Detect Scan Finished 0 no effect 1 scan finished 15 8 0x0 SPD DET FACTOR1 Speed Detect Factor 1 This number indicates the delay length equivalent to input clock period x2 7 0 Ox0 SPD DET FACTORO Speed Detect Factor 0 This number indicates the delay length equivalent to input clock period x1 5 3 40 PMU Speed Fa ctor Register 2 Offset OxE8 Register Name PMU_SPEED_FACTOR_REG2 Bit Read W rite Default Hex Description 31 R W 0x0 SPD_DET_EN Speed Detect Enable 0 Disable 1 Enable 30 R W 0x0 SPD_DET_MODE A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 45 Allwinner Technology Speed Detect Mode 0 single mode 1 continuous mode 29 28 RW Ox0 SPD DET SPDUP FACTOR Speed Detect Speed Up Factor Set these bits to non zero value can speed up the scan operation 00 lowest 11 fastest 27 17 16 R Ox0 SPD DET SCN FIN Speed Detect Scan Finished 0 no effect 1 scan finished 15 8 R Ox0 SPD DET FACTOR Speed Detect Factor 1 This number indicates the delay length equivalent to input clock period x2 7 0 R Ox0 SPD DET FACTORO Speed Detect Factor 0 This number indicat
323. or per 512 or 1024 bytes data The on chip ECC and parity checking circuitry of NFC frees CPU for other tasks The ECC function can be disabled by software The data can be transferred by DMA or by CPU memory mapped IO method The NFC provides automatic timing control to read or write external Flash The NFC maintains the proper relativity for CLE CES and ALE control signal lines Three kinds of modes are supported for serial read access Mode 0 is the conventional serial access Mode 1 for EDO type and Mode 2 is for extension EDO type In addition NFC can monitor the status of R B signal line Block management and wear leveling management are implemented in software The NFC features Support SLC MLC TLC flash and EF NAND memory Software configure seed to randomize engine Software configure method for adaptability to a variety of system and memory types Support 8 bit Data Bus Width Support 1024 2048 4096 8192 16384 bytes size per page Up to 2 flash chips which are controlled by NFC_CEx Support Conventional and EDO serial access method for serial reading Flash On the fly BCH error correction code which correcting up to 64 bits per 512 or 1024 bytes amp Corrected Error bits number information report ECC automatic disable function for all Oxff data NFC status information is reported by its registers Support interrupt One Command FIFO Support external DMA for data transfer Two 256x32 bit RAM for Pi
324. oth select LINEINL LINEINR depending on LNRDF bit 16 001 left channel select FMINL amp right channel select FMINR 010 left and right channel both select MIC1 gain stage output 011 left and right channel both select MIC2 gain stage output 100 left select MIC1 gain stage output amp right select MIC2 gain stage output 101 left and right both select MIC1 gain stage plus MIC2 gain stage output 110 left select output mixer L amp right select output Mixer right A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 243 Allwinner Technology 111 left select LINEINL or LINEINL LINEINR depending on LNRDF bit 16 right select MIC1 gain stage 16 R W 0x0 LNRDF Line in r function define 0 Line in right channel which is independent of line in left channel 1 negative input of line in left channel for fully differential application 15 13 R W 0x4 LNPREG Line in pre amplifier Gain Control From 12dB to 9dB 3dB step default is OdB 12 R W 0x0 0 1 MICINEN Mic1outn enable disable enable 11 9 R W 0x1 1 DITHER ADC dither on off control 0 dither off dither on R W 0x1 R W 0x0 PA_EN PA Enable 0 disable 1 enable R W 0x1 DDE Headphone direct drive enable DDE 0 disable 1 enable R W 0x1 0 1 COMPTEN HPCOM output protection enable protection disable protection enab
325. p1 threshold value 30 2 13 Luminance Histogram Threshold Setting Register 1 Offset 0X0038 Register Name IMGEHC LHT REG1 Read Wr Default Bit i Description ite Hex LH_THRES_VAL7 23 16 R W Oxe0 Step7 threshold value LH THRES VAL6 15 08 RAW OxcO Step6 threshold value A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 354 Allwinner Technology Step5 threshold value When set IMGEHC_LHT REGO0 and IMGEHC_LHT_REG1 make sure that THRES VAL1 lt THRES VAL2 lt lt THRES VAL 30 2 14 Luminance Histogram Statistics Lum Recording Register Offset 0X0040 OX005C Register Name IMGEHC LHSLUM REG Read Wr Default SC Bit Description ite Hex LH LUM DATA 31 00 R W er 30 2 15 Luminance Histogram Statistics Counter Recording Register Offset 0X0060 0X007C Register Name IMGEHC_LHSCNT_REG f Read Wr Default GR Bit Description ite Hex LH_CNT_DATA 31 00 R W a Luminance statistics data YUV to RGB conversion algorithm formula R R Y component coefficient Y R U component coefficient U R V component coefficient V R constant G G Y component coefficient Y G U component coefficient U G V component coefficient V G constant B B Y component coefficient Y B U component coefficient U B V component coefficient V B constant 30 2 16 CSC Y G Coefficient Register Offset G Y component
326. peline Procession A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 145 Allwinner Technology Support SDR DDR and Toggle 1 0 NAND 15 2 NFC Block Diagram AHB Slave I F Command DMA amp INT FIFO Register FIFO Control Control File FIFO FIFO Re RAMO RAMI a ahb_clk 256x32 256x32 Ge domain Sy nfc_clk domain Normal Spar Batch Comma d Command Comman d FSM FSM FSM ECC Control NAND Flash Basic Operation I I I I I A I A CE 1 0 CLE ALE WE RE RB 1 0 DO 7 0 DI 7 0 Figure 15 1 NFC Block Diagram 15 3 NFC Timing Diagram Typically there are two kinds of serial access method One is the conventional method that fetches data at the rise edge of NFC_RE signal line and the other is EDO type that fetches data at the next fall edge of NFC_RE signal line NFC_CLE A a Dr a t4 NFC_CE A NFC_WE A 4 t14 kees sample 0 sample n 1 NFC_RE d A VEE 3 NFC_ALE A a H Up NFC_RB A NFC_IOx Data 0 mat Data n 1 Figure 15 2 Conventional Serial Access Cycle Diagram SAMO A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 146 Allwinner Technology NFC_CLE A Ke ele NFC_CE NFC_WE A lt t14 w 11 E gt
327. pinis 0 2 No SDCO PF port boot operation SDCO Boot Success lt g NAND Flash boot operation CEO FC Boot Yes Success di SDC2 PC port boot operation No SDC2 Boo Success lt g No SPIO PC port boot operation SPI Nor Flas Boot Success lt 2 No boot OK run other firmware USB boot operation Figure 4 Boot Diagram A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 30 Allwinner Technology 5 PMU 5 1 Overview The Power Management Unit PMU aims to reduce dynamic power consumption and static leakage current to extend the life of batteries in end products This module is the central control module for CPU clock and power management signals in the device 5 2 PMU Register List Module Name Base Address PMU 0x01C25400 Register Name Offset Description PMU DVFS CTRL REGO 0x0000 PMU Control Register 0 PMU DVFS CTRL REG1 0x0004 PMU Control Register 1 0x0008 PMU DVFS CTRL REG2 0x000C PMU Control Register 2 0x0010 0x0014 PMU_DVFS_CTRL_REG3 0x0018 PMU Control Register 3 PMU_DVFS_TIMEOUT_CTRL_REG 0x001C PMU Timeout Control Register PMU AXI AUTO SWT REGO 0x0020 PMU AXI Auto Switch CLK RegisterO PMU AXI AUTO SWT REG 0x0024 PMU AXI Auto Switch CLK Regis
328. pon a hardware reset but does not alter it upon a software reset Remote wakeup signaling of the host system is host bus specific and is not described in this specification Ox0 InterruptRouting This bit determines the routing of interrupts generated by events registered in HcinterruptStatus If clear all interrupt are routed to the normal host bus interrupt mechanism If set interrupts are routed to the System Management Interrupt HCD clears this bit upon a hardware reset but it does not alter this bit upon a software reset HCD uses this bit as a tag to indicate the ownership of HC 7 6 RW RW Ox0 HostControllerFunctionalState for USB 00b USBReset 01b USBResume 10b USBOperational 11b USBSuspend A transition to USBOperational from another state causes SOF generation to begin 1 ms later HCD may determine whether HC has begun sending SOFs by reading the StartoFrame field of HcinterruptStatus This field may be changed by HC only when in the USBSUSPEND state HC may move from the USBSUSPEND state to the USBRESUME state after detecting the resume signaling from a downstream port HC enters USBSUSPEND after a software reset whereas it enters USBRESET after a hardware reset The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports 0x0 BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame If cleared by HCD p
329. power is disabled CurrentConnectStatus PortEnableStatus PortSuspendStatus and PortResetStatus should be reset 0 port power is off 1 port power is on write SetPortPower The HCD writes a 1 to set the PortPowerStatus bit Writing a 0 has no effect Note This bit is always read as 1b if power switching is not supported 7 5 Ox0 Reserved RW RW Ox0 read PortResetStatus When this bit is set by writing to SetPortReset port reset signaling is asserted When reset is completed this bit is cleared when PortResetStatusChange is set This bit cannot be set if CurrentConnectStatus is cleared 0 port reset signal is not active 1 port reset signal is active write SetPortReset The HCD sets the port reset signaling by writing a 1 to this bit Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortResetStatus but instead sets ConnectStatusChange This informs the driver that it attempted to reset a disconnected port R W R W 0x0 read PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per port basis If per port overcurrent reporting is not supported this bit is set to 0 If cleared all power operations are normal for this port If set an overcurrent condition exists on this port This bit always reflects the overcurr
330. priority level for IRQ bit 3 7 6 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ2 PRIO IRQ 2 Priority Set priority level for IRQ bit 2 5 4 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ1 PRIO IRQ 1 Priority Ge dee ES Set priority level for IRQ bit 1 Level 0x0 level 0 lowest priority A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 116 Allwinner Technology Offset 0x80 Register Name INTC SRC PRIO REGO Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority 1 0 Programs the priority level for all sources except FIQ source source 0 The priority level ranges from O lowest to 7 highest 13 4 27 Interrupt Source Priority 1 Register Default 0x00000000 Offset 0x84 Register Name INTC SRC PRIO REG1 Read W Default DE Bit Description rite Hex IRQ31 PRIO IRQ 31 Priority Set priority level for IRQ bit 31 31 30 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ30 PRIO IRQ 30 Priority Set priority level for IRQ bit 30 29 28 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highe
331. pt types responsible for its assertion Each of the interrupt types can be separately enabled disabled with the control registers The UART has 16450 and 16550 modes of operation which are compatible with a range of standard software drivers In 16550 mode transmit and receive operations are both buffered by FIFOs In 16450 mode these FIFOs are disabled The UART supports word lengths from five to eight bits an optional parity bit and 1 1 5 or 2 stop bits and is fully programmable by an AMBA APB CPU interface 16 bit programmable baud rate generator and an 8 bit scratch register are included together with separate transmit and receive FIFOs Eight modem control lines and a diagnostic loop back mode are provided Interrupts can be generated for a range of TX Buffer FIFO RX Buffer FIFO Modem Status and Line Status conditions The UART includes the following features Compatible with industry standard 16550 UARTs 64 Bytes Transmit and receive data FIFOs DMA controller interface Software Hardware Flow Control Programmable Transmit Holding Register Empty interrupt Interrupt support for FIFOs Status Change 19 2 UART Timing Diagram One Character Bit Time TX RX Serial Data S Data bits 5 8 P S1 1 5 2 Figure 19 1 UART Serial Data Format A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 176 Allwinner Technology Data Bits Bit Time
332. r Technology 11 23 18 CLK_DIV RATIO N 17 16 RW 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 CLK DIV RATIO M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 Note In application the module clock frequency always switches off 6 4 22 SDO Clock Default 0x00000000 Offset 0x88 Register Name SD0 SCLK CFG REG f Read W Default Ke Bit Description rite Hex SCLK_GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 00 OSC24M 25 24 RW 0x0 01 PLL6 10 PLL5 11 23 18 CLK_DIV_RATIO_N 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 CLK DIV RATIO M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 23 SD1 Clock Default 0x00000000 Offset Ox8C Register Name SD1_SCLK_CFG_REG Read W Default D Bit i Description rite Hex SCLK_GATING Gating Special Clock Max Clock 200MHz s GE 0 Clock is OFF 1 Clock is ON A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 66
333. r Data Bit Definition ss 274 26 5 2 CCIR656 Header Decode sn a ae 275 26 6 CSI Timing SCIAN ene ren kaia naaa eon eee 275 27 Display Engine Front End DEFE ssscsssssssssssssssscsssesssssssssssssessssessssessssssessssessssessensseesssesees 276 ON E 276 27 2 DEFE Block Diagramme een nan agen eer 276 27 3 DEFE DESCIPNON ee steet aea lente tentes et E ee tu er 276 27 3 1 eege 277 27 3 2 GET gd go RR o a o ere eee ee 277 27 3 3 Seang E 278 27 3 4 AOC Data ME 279 27 3 5 CSC Color Space Conversion Description 279 27 3 6 DEFE Source Input Formats ee s ee 279 27 3 7 Image Data Memory Mapping 280 27 4 DEFE Register List iii 283 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 14 Allwinner Technology 27 5 DEFE Register DesCription 256 tete tant EE ent 27 5 1 EI lw E 27 5 2 DEFE FAM GTRL RES 8 ate ara rneer ar anne ER a a a AANE Sa a tatn dace Aranean ENES 27 5 3 DEFE BYPASS E 27 5 4 DEFE AGTH SEL Ee 27 5 5 DEFE INT TRUE SSSR RL aE 27 5 6 DEFE BUF lt ADDRO HE ee 27 5 7 DEFE BUP ADDRI REG E 27 5 8 DEFE RRE 27 5 9 DEFE FIELD CTRL REG ass EA DEFE PB PR PE aa aa eE 27 541 DEFE TE OFFL PREG sondia 27512 DEFE 18 OR A Ee 27513 DEFE LINESTRDO REG Lasse tentant ns titan tata haken tent en DEFE LINESTRDI NE DEFE NE PEN 27 510 DEFE INPUT FMT REG een 271517 DEFE WB ADDR FE Guren 21 0410 DEFE OUTPUT FMT REG nt 27 5 19 DEFE INT Eege 27500 DEF
334. r bit Frame List Rollover Enable When this bit is 1 and the Frame List Rollover bit in the USBSTS register is 1 the host controller will issue an interrupt The interrupt 3 R W 0 is acknowledged by software clearing the Frame List Rollover bit Port Change Interrupt Enable When this bit is 1 and the Port Chang Detect bit in the USBSTS register is 1 the host controller will issue an interrupt The interrupt 2 R W 0 is acknowledged by software clearing the Port Chang Detect bit USB Error Interrupt Enable When this bit is 1 and the USBERRINT bit in the USBSTS register is 1 the host controller will issue an interrupt at the next interrupt 1 R W 0 threshold A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 208 Allwinner Technology The interrupt is acknowledged by software clearing the USBERRINT bit USB Interrupt Enable When this bit is 1 and the USBINT bit in the USBSTS register is 1 the host controller will issue an interrupt at the next interrupt threshold 0 R W 0 The interrupt is acknowledged by software clearing the USBINT bit 22 5 9 EHCI Frame Index Register Register Name FRINDEX Offset Ox1c Default Value 0x00000000 Bit Read Write Default Description Reserved 31 14 0 These bits are reserved and should be zero Frame Index The value in this register increment at the end of each time frame e g micro frame Bi
335. r mode These bits control the number of wait states to be inserted in data transfers The SPI module counts SPI SCLK by WCC for delaying next word data transfer 0 No wait states inserted N N SPI SCLK wait states inserted 18 4 8 SPI Clock Control Register Offset 0x1C Register Name SPI CCTL Default Value 0x0000 0002 Bit Read Write Default Description 31 13 12 RW DRS Divide Rate Select Master Mode Only 0 Select Clock Divide Rate 1 1 Select Clock Divide Rate 2 RW CDR1 Clock Divide Rate 1 Master Mode Only This field selects the baud rate of the SPI SCLK based on a division of the AHB_CLK These bits allow SPI to synchronize with A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 173 Allwinner Technology different external SPI devices The max frequency is one quarter of AHB CLK The divide ratio is determined according to the following table using the equation 2 n 1 The SPI SCLK is determined according to the following equation SPI CLK AHB_CLK 2 n 1 CDR2 Clock Divide Rate 2 Master Mode Only The SPI SCLK is determined according to the following equation 7 0 RW 0x2 SPI_CLK AHB_CLK 2 n 1 18 4 9 SPI Burst Counter Register Offset 0x20 Register Name SPI_BC Default Value 0x0000 0000 Bit Read Write Default Description 31 24
336. ractional part of the vertical scaling ratio the vertical scaling ratio input height output height 27 5 40 DEFE CHO HORZPHASE REG Offset 0x110 Register Name DEFE CHO HORZPHASE REG Read W Default Se Bit Description rite Hex 31 20 PHASE 19 0 R W 0x0 Y G component initial phase in horizontal complement This value equals to initial phase 2 27 5 41 DEFE CHO VERTPHASEO REG Offset 0x114 Register Name DEFE CHO VERTPHASEO REG Read W Default Bit Description rite Hex 31 20 PHASE 19 0 R W 0x0 Y G component initial phase in vertical for top field complement This value equals to initial phase 2 27 5 42 DEFE CHO VERTPHASE1 REG Offset 0x118 Register Name DEFE CHO VERTPHASE1 REG i Read W Default D Bit i Description rite Hex 31 20 PHASE 19 0 R W 0x0 Y G component initial phase in vertical for bottom field complement This value equals to initial phase 2 27 5 43 DEFE CH1 INSIZE REG Offset 0x200 Register Name DEFE CH1 INSIZE REG A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 299 Allwinner Technology Read W Default Bit Description rite Hex 31 29 IN HEIGHT 28 16 RW 0x0 Input image U R component height Input image height The value of these bits add 1 15 13 IN WID
337. riority of layer B Layer A color key setting status True Layer B color key setting status True or false Color key selection Layer A match layer B R R_a AV_a R bg 1 AV a G G_a AV_a G bg 1 AV a B B a AV_a B bg 1 AV a If priority of layer A gt priority of layer B Layer A color key setting status False Layer B color key setting status True Color key selection Layer B match layer A R R b AV b R bg 1 AV bi G G b AV b G bg 1 AV bi B Bb AV b B bg 1 AV bi 28 3 3 PIPE There are 2 normal pipes in the engine pipe 0 and pipe In normal mode the dedicated layer will get the data from system DRAM direct or DEFE by setting dedicated Layer video channel selection bit in DE layer Attribute control register In other work modes the layer data source also comes from internal frame buffer In the same pipe the highest layer pixel data can pass 28 4 DEBE Register list Module name Base address A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 307 Allwinner Technology DEBE 0x01e60000 Register name Offset Description DEBE_MODCTL_REG 0x800 DEBE mode control register DEBE BACKCOLOR REG 0x804 DE back color control register DEBE DISSIZE REG 0x808 DE back display size setting register DEBE LAYSIZE REG 0x810 0x81C DE layer size register DEBE LAYCOOR REG 0x820 0x82C DE layer coordinate control register DEBE LA
338. ription HCLK System clock provided by AHB bus clock This clock needs to be gt 30MHz CLK60M Clock from PHY for HS SIE is constant to be 60MHz CLK48M Clock from PLL for FS LS SIE is constant to be 48MHz A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 233 Allwinner Technology 23 Audio Codec 23 1 Overview The embedded Audio Codec is a high quality stereo audio codec with headphone amplifier It features On chip 24 bit DAC for play back On chip 24 bit ADC for recorder Support analog digital volume control Support 48K and 44 1K sample family Support 192K and 96K sample Support Microphone recorder Stereo headphone amplifier that can be operated in capless headphone mode Support Virtual Ground to automatically change to True Ground to protect headphone amplifier and make function work in normal mode 23 2 Audio Codec Block Diagram DDE PREGI J E MICI o gt a gt MICOI FE 32dB 35dB 38dB 41dB HPCOM VMICEN 200 ohm D VMIC AAN gt 2 526V Ba SYSTEM BUS MICI O GAIN When ADCIS 010 ADCINL ADCINR MICO I When ADCIS 1 10 ADCINL MIXOUTL ADCINR MIXOUTR ADCG ch ADC bg 4 5dB 3dB 1 5dB 0dB 1 5dB 3dB 4 5dB 6 4 5dB 3dB 1 5dB 0dB 1 5dB 3dB 4 5dB 6dB MICOG LNOG STEREO MICILS MICIRS PAEN PAVOL D PAMUTE MIXPAS DACMIXS HPOUTLR OG
339. ription 31 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 369 Allwinner Technology PB15 Select 000 Input 001 Output 010 TWI1_SCK 011 100 101 30 28 R W 0 110 111 27 11 PB10 Select 000 Input 001 Output 010 SPI2 CS1 011 100 101 10 8 R W 0 110 EINT24 111 7 0 33 4 3 PB Configure Register 2 Register Name PB_CFG2 Offset 0x2C Default Value 0x0000 0000 Bit Read Write Default Description 31 11 PB18 Select 000 Input 001 Output 010 TWI2 SDA 011 100 101 10 8 R W 0 110 111 7 PB17 Select 000 Input 001 Output 010 TWI2 SCK 011 100 101 6 4 R W 0 110 111 3 PB16 Select 000 Input 001 Output 010 TWI1 SDA 011 100 101 2 0 R W 0 110 111 33 4 4 PB Configure Register 3 Register Name PB CFG3 Offset 0x30 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 370 Allwinner Technology 33 4 5 PB Data Register Register Name PB DAT Offset 0x34 Default Value 0x0000 0000 Bit Read Write Default Description 31 21 If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is
340. rite Hex 31 24 FACTOR INT 23 16 RW 0x0 The integer part of the vertical scaling ratio the vertical scaling ratio input height output height FACTOR_FRAC 15 0 R W 0x0 The fractional part of the vertical scaling ratio the vertical scaling ratio input height output height 27 5 47 DEFE_CH1_HORZPHASE_REG Offset 0x210 Register Name DEFE_CH1_HORZPHASE_REG Read W Default i Bit Description rite Hex 31 20 PHASE 19 0 R W 0x0 U R component initial phase in horizontal complement This value equals to initial phase 2 27 5 48 DEFE_CH1_VERTPHASEO REG Offset 0x214 Register Name DEFE_CH1_VERTPHASEO REG Read W Default SCH Bit Description rite Hex 31 20 PHASE 19 0 R W 0x0 U R component initial phase in vertical for top field complement This value equals to initial phase 2 27 5 49 DEFE CH1 VERTPHASE1 REG Offset 0x218 Register Name DEFE CH VERTPHASET1 REG Read W Default D Bit Description rite Hex 31 20 PHASE 19 0 R W 0x0 U R component initial phase in vertical for bottom field complement This value equals to initial phase 2 27 5 50 DEFE CHO HORZCOEFO REGN N 0 31 Offset 0x400 N 4 Register Name DEFE CHO HORZCOEFO REGN Read W Default a Bit Description rite Hex TAP3 31 24 RW 0x0 Horizontal tap3 coefficient The value equ
341. rnally 0 R W 0 looped back to an input 19 4 10 UART Line Status Register Offset 0x14 Register Name UART_LSR A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 185 Allwinner Technology Default Value 0x0000 0060 Bit Read Write Default Description 31 8 FIFOERR RX Data Error in FIFO When FIFOs are disabled this bit is always 0 When FIFOs are enabled this bit is set to 1 when there is at least one PE FE or BI in the RX FIFO It is cleared by a read from the LSR register 7 R 0 provided there are no subsequent errors in the FIFO TEMT Transmitter Empty If the FIFOs are disabled this bit is set to 1 whenever the TX Holding Register and the TX Shift Register are empty H the FIFOs are enabled this bit is set whenever the TX FIFO and the TX Shift Register are empty In both cases this bit is cleared when a byte is 6 R 1 written to the TX data channel THRE TX Holding Register Empty If the FIFOs are disabled this bit is set to 1 whenever the TX Holding Register is empty and ready to accept new data and it is cleared when the CPU writes to the TX Holding Register If the FIFOs are enabled this bit is set to 1 whenever the TX FIFO is empty and it is cleared when at least one byte is written to 5 R 1 the TX FIFO BI Break Interrupt This is used to indicate the detection of a break sequence on the serial input data If in
342. rocessing of the Bulk list does not occur after the next SOF HC checks this bit whenever it determines to process the list When disabled HCD may modify the list If HcBulkCurrentED is pointing to an ED to be removed HCD must advance the pointer by updating HcBulkCurrentED before re enabling processing of the list 0x0 ControlListEnable This bit is set to enable the processing of the Control list in the next Frame If cleared by HCD processing of the Control list does not occur after the next SOF HC must check this bit whenever it determines to process the list When disabled HCD may modify the list If HcControlCurrentED is pointing to an ED to be removed HCD must advance the pointer by updating HcControlCurrentED A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 216 Allwinner Technology before re enabling processing of the list R W 0x0 IsochronousEnable This bit is used by HCD to enable disable processing of isochronous EDs While processing the periodic list in a Frame HC checks the status of this bit when it finds an Isochronous ED F 1 If set enabled HC continues processing the EDs If cleared disabled HC halts processing of the periodic list which now contains only isochronous EDs and begins processing the Bulk Control lists Setting this bit is guaranteed to take effect in the next Frame not the current Frame R W 0x0 Perio
343. rol Register1 Offset Layer0 0x8A0 Layer1 0x8A4 Register Name DEBE ATTCTL REG Layer2 0x8A8 Layer3 0x8AC Bit Description ite Hex LAY_HSCAFCT Setting the internal frame buffer scaling factor only valid in internal frame buffer mode SH Height scale factor 00 no scaling 01 2 10 4 11 Reserved LAY_WSCAFCT Setting the internal frame buffer scaling factor only valid in internal frame buffer mode SW Width scale factor 00 no scaling 01 2 10 4 11 Reserved LAY_FBFMT Frame buffer format Normal mode data format 0000 mono 1 bpp A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 316 Allwinner Technology 0001 mono 2 bpp 0010 mono 4 bpp 0011 mono 8 bpp 0100 color 16 bpp 0101 color 16 bpp 0110 color 16 bpp 0111 color 16 bpp 1000 color 16 bpp 1001 color 24 bpp 1010 color 32 bpp 1011 color 24 bpp 1100 color 16 bpp 1101 color 16 bpp Other Reserved R 6 G 5 B 5 R 5 G 6 B 5 R 5 G 5 B 6 Alpha 1 R 5 G 5 B 5 R 5 G 5 B 5 Alpha 1 Padding 8 R 8 G 8 B 8 Alpha 8 R 8 G 8 B 8 R 8 G 8 B 8 Alpha 4 R 4 G 4 B 4 R 4 G 4 B 4 Alpha 4 ER tg Zoe S a Ze pia A Ae Palette Mode data format In palette mode the data of external frame buffer is regarded as pattern 0000 1 bpp 0001 2 bpp 0010 4 bpp 0011 8 bpp other Reserved Internal Frame buffer mode data format 0000 1 bpp 0001 2 bpp 0010 4 bpp 0011 8 bpp Other Reserved
344. s 15 8 R W 0x18 that the previous CIR command has been finished NTHR Noise Threshold for CIR When the duration of signal pulse high or low level is less than NTHR the pulse is taken as noise and should be discarded by hardware 0 all samples are recorded into RX FIFO 1 If the signal is only one sample duration it is taken as noise and discarded 2 If the signal is less than lt two sample duration it is taken as noise and discarded 61 if the signal is less than lt sixty one sample duration it is 7 2 R W Oxa taken as noise and discarded A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 195 Allwinner Technology 1 0 R W 0 SCS Sample Clock Select for CIR 0 CIR sample_clk is ir_clk 64 1 CIR sample_clk is ir_clk 128 2 CIR sample_clk is ir_clk 256 3 CIR sample cikis ir_clk 512 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 196 Allwinner Technology 21 USB DRD Controller 21 1 Overview The USB DRD controller supports Host and device functions It can also be configured as a Host only or Device only controller full compliant with the USB 2 0 Specification The USB2 0 DRD can support high speed HS 480 Mbps full speed FS 12 Mbps and low speed LS 1 5 Mbps transfers in Host mode support high speed HS 480 Mbps and full speed FS 12 Mbps in Device mode The USB2 0 DRD contr
345. s Default 0x00000023 Offset 0x4C Register Name PMU CPUVDD CTRL REG ADDR Read W Default Ee Bit Description rite Hex 31 8 l CPUVDD CTRL REG ADDR Ve Doi Me PMU CPUVDD DCDC Control Register address 5 3 12 PMU TWI Address Default 0x00000068 Offset 0x50 Register Name PMU TWI ADDR REG i Read W Default CH Bit Description rite Hex 31 8 l 70 RW 0x68 PMU TWI ADDR PMU TWI address set 5 3 13 PMU CPUVDD Value Default 0x00000016 Offset 0x54 Register Name PMU CPUVDD VALUE REG f Read W Default W i Bit i Description rite Hex 31 8 l CPUVDD_DEFAULT PMU CPUVDD Default Value 0x00 0 70v 0x02 0 75v 0x04 0 80v 0x06 0 85v 7 0 R W 0x16 0x08 0 90v Ox0A 0 95v 0x0C 1 00v 0x0E 1 05v 0x10 1 10v 0x12 1 15v 0x14 1 20v A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 37 Allwinner Technology 0x16 1 25v 0x18 1 30v Ox1A 1 35v 0x1C 1 40v Ox1E 1 45v 0x20 1 50v 0x22 1 55v 0x24 1 60v Note This register can be modified by PMU DVFS 5 3 14 PMU CPUVDD Voltage Ramp Control in DVM Offset 0x58 Register Name PMU CPUVDD RAMP CTRL REG Read W Default o Bit Description rite Hex 31 1 l CPUVDD_VOLT_RAMP_CTRL P i 0 RW oxo CPUvdd voltage ramp control in DVM 0 15 625us 1 31 25us Note If the cpuvdd voltage ramp control in the external PMU is chang
346. s Reserved 349 Allwinner Technology 30 IEP 30 1 Overview The Image Enhancement Processor IEP is capable of adjusting the dynamic range of pictures according to statistics 30 2 IEP Register Description 30 2 1 General Control Register Offset 0X0000 Register Name IMGEHC GNECTL REG Read Wr Default H Bit Description ite Hex BIST_EN BIST enable 0 disable 1 enable Work mode selection If bit O of the register is set ZERO the following setting will be ignored 00 Output FIFO mode 01 De flicker mode 10 DRC mode 11 Reserved 0 disabled the module and the whole module will be by passed 1 enable 30 2 2 DRC Size Setting Register Offset 0X0004 Register Name IMGEHC DRCSIZE REG Read Wr Default SC Bit i Description ite Hex DRC_HEIGHT 27 16 R W Display height The real display height The value of these bits 1 11 00 R W DRC_WIDTH Display width A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 350 Allwinner Technology The real display width The value of these bits 1 30 2 3 DRC Control Register Offset 0X0010 Register Name IMGEHC DRCCTL_ REG Read Wr Default ve Bit Description ite Hex DRC WIN EN Output window function enable 0 disable DRC DBRDY CTL Only valid when DRC DB EN bit is set If the bit is set when the SYNG signal is coming the all double buffered DRC registers will be loade
347. s are up to 1024 CPU clock cycles 0 enable 1 disable Note the bit 1 0 can be set to 0 by software A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 99 Allwinner Technology 12 Synchronic Timer 12 1 Overview The chip implements 2 sync timers for high speed counter 12 2 Sync Timer Register List Module Name Base Address Sync Timer 0x01C60000 Register Name Offset Description SYNC_TMR_IRQ_EN_REG 0x0000 Timer IRQ Enable SYNC_TMR_IRQ_STAS_REG 0x0004 Timer Status SYNC_TMRO_CTRL_REG 0x0010 Timer 0 Control SYNC_TMRO_INTV_LO REG 0x0014 Timer 0 Interval Value Low SYNC TMRO INTV HI REG 0x0018 Timer 0 Interval Value High SYNG TMRO CURNT LO REG 0x001C Timer 0 Current Value Low SYNC_TMRO_CURNT_HI_ REG 0x0020 Timer 0 Current Value High SYNG TMR1 CTRL REG 0x0030 Timer 1 Control SYNG TMR1 INTV LO REG 0x0034 Timer 1 Interval Value Low SYNG MI INTV HI REG 0x0038 Timer 1 Interval Value High SYNG TMR1 CURNT LO REG 0x003C Timer 1 Current Value Low SYNG TMR1 CURNT HI REG 0x0040 Timer 1 Current Value High 12 3 Sync Timer Register Description 12 3 1 Sync Timer IRQ Enable Register Default 0x00000000 Offset 0x00 Register Name SYNC TMR IRQ EN REG Read W Default e Bit f Description rite Hex 31 2 STMR1_INT_EN 1 R W 0x0 Sync Timer 1 Interrupt Enable 0 No effect
348. s from 1 to 16 6 4 27 SPI1 Clock Default 0x00000000 Offset OxA4 Register Name SPI1 SCLK CFG REG Read W Default o Bit Description rite Hex SCLK_GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK SRC SEL Clock Source Select 00 OSC24M 25 24 RW 0x0 01 PLL6 10 PLL5 11 23 18 CLK DIV RATIO N 17 16 R W Ox0 Clock pre divide ratio n The select clock source is pre divided by 2 The divider is 1 2 4 8 15 4 CLK DIV RATIO M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 28 SPI2 Clock Default 0x00000000 Offset OxA8 Register Name SPI2 SCLK CFG REG Read W Default ho Bit Description rite Hex SCLK GATING Gating Special Clock Max Clock 200MHz 31 RW 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 25 24 RW 0x0 00 OSC24M 01 PLL6 10 PLL5 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 69 Allwinner Technology 11 23 18 CLK DIV RATIO M 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 The divider is 1 2 4 8 15 4 CLK DIV RATIO M 3 0
349. sample 0 NFC_RE us NFC_ALE A sa H 0 gt NFC RBi NFC_IOx Data 0 ff Data n 1 Figure 15 3 EDO Type Serial Access after Read Cycle SAM1 NFC CLE A 3 NFC_CE re A NFC_WE A NFC_RE TI hn NFC_ALE A sw H 0 gt NFC RBH A NEC_IOx Data 0 X fata n 1 Figure 15 4 Extending EDO Type Serial Access Mode SAM2 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 147 Allwinner Technology lt t1 gt W NFC_CLE a D a Mu NFC CES th gt NFC_WE NFC_RE AT lt t11 gt NFC_ALE le t8 pa t9 gt NFC OE 11117 em Figure 15 5 Command Latch Cycle NV NFC CLE 3 _ WEE NFC_CE NFC_WE NSS NFC_RE A gg Zeg la tii NFC ALE Le 18 gt a t9 NFC JOx ED Addr 0 Addrin 1 z Figure 15 6 Address Latch Cycle kb n _t2 NFC_CLE an Ms NFC_CE A lg t15 lt t5 gt a t6 NFC_WE NS NFC REf WEE NFC ALE Le t8 gt a t9 gt NFC O Data 0 f Data n 1 Gn Figure 15 7 Write Data to Flash Cycle A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 148 Allwinner Technology NFC_CLE
350. se 1 Register DEFE_CH1_INSIZE_REG 0x0200 DEFE Channel 1 Input Size Register DEFE CH1 OUTSIZE REG 0x0204 DEFE Channel 1 Output Size Register DEFE CH1 HORZFACT REG 0x0208 DEFE Channel 1 Horizontal Factor Register DEFE CH1 VERTFACT REG 0x020C DEFE Channel 1 Vertical factor Register DEFE_CH1_HORZPHASE_REG 0x0210 DEFE Channel 1 Horizontal Initial Phase Register DEFE CH1 VERTPHASEO REG 0x0214 DEFE Channel 1 Vertical Initial Phase 0 Register DEFE CH1 VERTPHASE1 REG 0x0218 DEFE Channel 1 Vertical Initial Phase 1 Register DEFE CHO HORZCOEF REGN 0x0400 N 4 DEFE Channel 0 Horizontal Filter Coefficient Register N 0 31 DEFE CHO VERTCOEF REGN 0x0500 N 4 SS 0 Vertical Filter Coefficient Register DEFE CH1 HORZCOEF REGN 0x0600 N 4 DEFE Channel 1 Horizontal Filter Coefficient Register N 0 31 DEFE CH1 VERTCOEF REGN 0x0700 N 4 DEFE Channel 1 Vertical Filter Coefficient Register N 0 31 Note Registers 0x0008 0x0218 except status registers are double buffered when a new frame process starts and the buffered register configuration ready bit in frame process control register is set the value of corresponding internal configuration register will be refreshed by this register and programmers always can t read the value of corresponding internal register 27 5 27 5 1 DEFE EN REG DEFE Register Description Offset 0x0 Register Name DEFE EN REG Bit Read W Default Description A13 User Manual V1 3
351. set 22 6 OHCI Register Description 22 6 1 HcRevision Register Register Name HcRevision Offset 0x400 Default Value 0x10 Read Write Bit HCD HC Default Description 31 8 0x00 Reserved Revision This read only field contains the BCD representation of the version of the HCI specification that is implemented by this HC For example a value of 0x11 corresponds to version 1 1 All of the HC implementations that are compliant with this specification will have 7 0 R R 0x10 a value of 0x10 22 6 2 HcControl Register Offset 0x404 Register Name HcRevision Default Value 0x0 Read Write Description Bit HCD HC Default 31 11 0x00 Reserved RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wakeup feature upon the detection of upstream resume signaling When this bit is set and the ResumeDetected bit in HcinterruptStatus is set a remote wakeup is signaled to the host system Setting this bit 10 RW R 0x0 has no impact on the generation of hardware interrupt 9 RW RW 0x0 RemoteWakeupConnected A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 215 Allwinner Technology This bit indicates whether HC supports remote wakeup signaling If remote wakeup is supported and used by the system it is the responsibility of system firmware to set this bit during POST HC clear the bit u
352. sh states 25 R W CA pin A1 value in 8080 mode WR RD execute 24 RW VSYNG Cs Sel O CS 1 VSYNC 23 Wr_Flag O write operation ends 1 write operation is pending 22 Rd_Flag O read operation ends 1 read operation is pending 21 0 29 3 15 TCONO CPU WR REG Offset 0x064 Register Name TCONO cpu panel write data register Bit Read W rite Default Hex Description A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 342 Allwinner Technology 31 0 23 0 Data Wr data write on 8080 bus launch a write operation on 8080 bus 29 3 16 TCONO CPU RDO REG Offset 0x068 Register Name TCONO cpu panel read data register Read W Default SC Bit Description rite Hex 31 24 Data Hd 23 0 R im data read on 8080 bus launch a new read operation on 8080 bus 29 3 17 TCONO CPU RD1 REG Offset 0x06C Register Name TCONO cpu panel read data register Read W Default er Bit Description rite Hex 31 24 D Rd1 23 0 R ane data read on 8080 bus without a new read operation on 8080 bus 29 3 18 TCONO IO POL_REG Offset 0x088 Register Name TCONO IO polarity register Bit Read W rite Default Hex Description 31 30 29 28 R W DCLK_Sel 00
353. st priority IRQ29 PRIO IRQ 29 Priority Set priority level for IRQ bit 29 27 26 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ28_PRIO IRQ 28 Priority Set priority level for IRQ bit 28 25 24 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ27_PRIO IRQ 27 Priority Set priority level for IRQ bit 27 Level 0x0 level 0 lowest priority 23 22 RW 0x0 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 117 Allwinner Technology Offset 0x84 Register Name INTC SRC PRIO REG1 Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ26 PRIO IRQ 26 Priority Set priority level for IRQ bit 26 21 20 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ25 PRIO IRQ 25 Priority Set priority level for IRQ bit 25 19 18 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ24 PRIO IRQ 24 Priority Set priority level for IRQ bit 24 17 16 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ23 PRIO IRQ
354. ster Default 0x00000000 rrrrrrrrrrvrrrnrnrrrnrnrrrnrerennnernn 95 11 3 21 AVS Counter 0 Register Default OxOOO00O0O00 96 11 3 22 AVS Counter 1 Register Default OxOOO0O0O0O00 96 11 3 23 AVS Counter Divisor Register Default Ox05DBO5DB 97 11 3 24 Watchdog emgeet 97 11 3 25 Watchdog Mode Register Default Ox00000000 97 11 3 26 64 bit Counter Low Register Default 0x00000000 rrrrnnrrrrnnvrrrnrnnrrnrnrrrnrrrrnnnernn 98 11 3 27 64 bit Counter High Register Default 0x00000000 rrrnvvrnnrnnnvnnnvvnnnvnnnvnnnvenennnenn 98 11 3 28 64 bit Counter Control Register Default 0x00000000 rrrrrrrrvrrrnrnrrrrnrrrnnrrrnnnernn 99 11 3 29 CPU Config Register Default Ox00000000 99 12 Synchronic TUMOR iacsssinsctsssisessscsscnssansssavehossenasusissssvanssenshacssarintaisessheassendanuisteaindsesisiasaeninbascasisanianansinian 100 12 1 a E 100 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 7 Allwinner Technology 122 Syne Timer Register E 100 12 3 Sync Timer Register D SCApLIGN E 100 12 3 1 Sync Timer IRQ Enable Register Default Ox00000000 100 12 3 2 Sync Timer IRQ Status Register Default 0x00000000 rrrvrrrnrnrnrnnnvnnnnrnrnrnrnvnnnn 101 12 3 3 Sync Timer 0 Control Register Default 0x00000004 ee eee eee ee
355. sts Rene tr Rte 242 23 4 10 DAC TX Counter Register nie Need 244 234411 ADC RX Counter Register vassverk 245 24 ne 246 4 e en he eE aE 246 24 2 Principle of operation sise 246 24 2 1 Block DigaMn renner nr a ari e e e a a 246 24 2 2 Hold Key and General Key Function Introduction 246 24 3 LRADC Fee aa a ATE EETA 247 244 LRADC Register DescnpnOn vate ete See 247 24 4 1 LRADC Control E KEE 247 24 4 2 LRADC Interrupt Control Register ss 248 24 4 3 LRADC Interrupt Status REGEL ebe 249 24 4 4 LRADC Data 0 Register seess 251 24 4 5 FAD ATR 251 25 Touch PAN vssscsiisssseasscessasossasncassnsesesscescenssnescansncossagsssssncnssnensansecssensansnsnesdensduenionsssasssenssassesssnsncsiensansesans 252 EG DR GE EEE 252 25 2 Typical Application Circuit ccs 252 25 3 Clock Tree and ADC TMS cee ee eee 253 25 3 1 E EE 253 25 3 2 AND Canvernon IME aent 253 252 Principleof CACO a isiishie le a ae aa er 254 25 4 1 The Basic Principles sise 254 25 4 2 single ended M de aa 255 25 4 3 Differential Mode sssi tisena anaana aot nin ili 255 25 4 4 ee VT EE 256 25 4 5 Dual Touch Detection sis 256 25 4 6 Touch Pressure Measurement 257 25 4 7 Pen Down Detection with Programmable Sensitivity 257 25 4 8 Median and Averaging Filter sise 258 25 5 TP Register List En ee ea a eine 259 25 6 IP e Ee RE ONO ES Re es ned ecco 260 25 6 1 TP Control ST Prete Cr ere tere re 260 25 6 2 TP Control Register Tarres tli denied Ee 261 2
356. t Figure 25 3 Dual Touch And Pressure Measurement MA fa ke e KEE FS TIME Figure25 4 Dual Touch No Pressure Measurement A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 253 Allwinner Technology Conversion Time DAT DAT 2 DATA DATA TAC Q lt gt FS_TIME i gt Figure25 5 Single Touch and Pressure Measurement Conversion Time MA EX DATA DATA C Se gt FS_TIME Figure25 6 Single Touch No Pressure Measurement Mode Conversion Time PLATS Cc PES DEG FS TIME Figure25 7 General ADC Mode 25 4 Principle of Operation 25 4 1 The Basic Principle The controller is a typical type of successive approximation ADC SAR ADC contains a sample hold analog to digital conversion serial data output functions The analog inputs X X Y Y via control register enter the ADC ADC can be configured as single ended or differential mode Selecting Aux ADC or temperature should be configured for single ended mode as a touch screen application it should be configured as a differential mode which can effectively eliminate the parasitic resistance of the driver switch and external interference caused by measurement error and impact conversion accuracy A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 2
357. t Description 31 4 R W R W 0x0 BulkCurrentED 31 4 This is advanced to the next ED after the HC has served the present one HC continues processing the list from where it left off in the last Frame When it reaches the end of the Bulk list HC checks the ControlListFilled of HcControl If set it copies the content of HcBulkHeadED to HcBulkCurrentED and clears the bit If it is not set it does nothing HCD is only allowed to modify this register when the BulkListEnable of HcControl is cleared When set the HCD only reads the instantaneous value of this register This is initially set to zero to indicate the end of the Bulk list 3 0 R R 0x0 BulkCurrentED 3 0 Because the general TD length is 16 bytes the memory structure for the TD must be aligned to a 16 byte boundary So the lower bits in the PCED through bit 0 to bit 3 must be zero in this field 22 6 13 HcDoneHead Register Offset 0x430 Register Name HcDoneHead Default Value 0x00 Bit Read Write Default Description A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 223 Allwinner Technology HCD HC 31 4 R W 0x0 HcDoneHead 31 4 When a TD is completed HC writes the content of HcDoneHead to the NextTD field of the TD HC then overwrites the content of HcDoneHead with the address of this TD This is set to zero whenever HC wr
358. t Bit Description ite Hex IYUV_YGCONS the Y G constant the value equals to coefficient 2 28 5 26 DEBE U R Coefficient Register Offset G Y component 0x960 R U component 0x964 B V component 0x968 Read Wr Default Bit Description ite Hex IYUV_URCOEF the U R coefficient the value equals to coefficient 2 9 Register Name DEBE_URCOEF_REG 28 5 27 DEBE U R Constant Register Offset 0x96C Register Name DEBE URCONS REG A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 325 Allwinner Technology IYUV URCONS the U R constant the value equals to coefficient 2 G Y component 0x970 R U component 0x974 B V component 0x978 IYUV VBCOEF the V B coefficient the value equals to coefficient 2 9 Offset 0x97C Register Name DEBE VBCONS REG Read Wr Default ED Bit i Description ite Hex IYUV VBCONS the V B constant the value equals to coefficient 2 Offset 0x9C0 Register Name DEBE_OCCTL_REG Description Color control module enable control 0 disable 1 enable Color correction conversion algorithm formula R R R component coefficient R R G component coefficient G R B component coefficient B A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 326 Allwinner Technology R constant G G R component coefficient R G G component coefficient G G B component coe
359. t Description ite Hex IN_FMT Input data format 000 RAW stream 010 CCIR656 011 YUV422 others reserved OUT_FMT Output data format When the input format is set RAW stream 0000 pass through When the input format is set CCIR656 interface 0000 field planar YCbCr 422 0001 field planar YCbCr 420 0010 frame planar YCbCr 420 0011 frame planar YCbCr 422 0100 field planar YCbCr 422 UV combined A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 268 Allwinner Technology 0101 field planar YCbCr 420 UV combined 0110 frame planar YCbCr 420 UV combined 0111 frame planar YCbCr 422 UV combined 1111 interlaced interleaved YCbCr422 In this mode capturing interlaced input and output the interlaced fields from individual ports Field 1 data will be written to FIFOO output buffer and field 2 data will be written to FIFO1 output buffer 1000 field MB YCbCr 422 1001 field MB YCbCr 420 1010 frame MB YCbCr 420 1011 frame MB YCbCr 422 When the input format is set YUV422 0000 planar YUV 422 0001 planar YUV 420 0100 planar YUV 422 UV combined 0101 planar YUV 420 UV combined 1000 MB YUV 422 1001 MB YUV 420 FIELD_SEL Field selection Applies to CCIR656 interface only 00 start capturing with field odd 11 10 RW ou 01 start capturing with field even 10 start capturing with either field 11 reserved DATA SEQ Input data sequence only valid for YUV422 mode 00
360. t 9bits Note Double buffered register of DRC double buffer function is controlled by DRC_DB_EN and DRC_DBRDY_CTL bits 30 2 6 DRC Window Position Register Offset OX001C Register Name IMGEHC DRC WP REGO Read Wr Default SC Bit Description ite Hex DRC_WIN_TOP 27 16 RW Window Top position Top position is the left top y coordinate of display window in pixels DRC_WIN_LEFT 11 00 R W Window Left position Left position is left top x coordinate of display window in pixels 30 2 7 DRC Window Position Register1 Offset 0X0020 Register Name IMGEHC_DRC_ WP REG1 Read Wr Default SC Bit Description ite Hex DRC WIN BOT 27 16 RW Window Bonom position Bottom position is the right bottom y coordinate of display window in pixels mo faw CE CA A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 352 Allwinner Technology Window Right position Right position is the right bottom x coordinate of display window in pixels 30 2 8 DRC Write Back Control Register Offset 0X0024 Register Name IMGEHC WBCTL REGO Read Wr Default BS Bit j Description ite Hex WB_STATUS Write back process status 0 write back end or write back disable 1 write back in process WB_FIELD Write back field setting for de flicker 0 top field 1 bottom field Write back only control 0 disable the write back only control the data will transfer to LCD contro
361. t Function Select 000 Input 001 Output 010 TP_XP 011 100 101 110 111 3 2 0 R W 0x2 TX_P_SELECT TX_P Port Function Select 000 Input 001 Output 010 TP XP 011 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 265 Allwinner Technology 100 101 110 111 25 6 10 TP Port Data Register Offset 0x2c Register Name TP_PORT_DATA Bit Read W Default Description rite Hex 31 12 3 0 R W 0x0 TP_PORT_DATA TP Port Data Value TP_XP TP_XN TP_YP TP_YN A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 266 Allwinner Technology 26 CSI 26 1 Overview The CMOS Sensor Interface CSI features 8 bit input data Support CCIR656 protocol for NTSC and PAL 3 parallel data paths for image stream parsing Support Received data double buffer Parsing bayer data into planar R G B output to memory Parsing interlaced data into planar or MB Y Cb Cr output to memory Pass raw data direct to memory All data transmit timing can be adjusted by software Luminance statistical value 26 2 CSI Block Diagram FIFO 2 i lt PCLK CSI HS FIFO 1 f lt Control k vs Module i CS Data 7 0 DMA System BUS Figure 26 1 CSI Block Diagram 26 3 CSI Register List
362. t counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 89 Allwinner Technology to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note Time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 11 3 7 ASYNC Timer 1 Interval Value Register Offset 0x24 Register Name ASYNG TMR1 INTV VALUE REG f Read W Default SC Bit f Description rite Hex TMR1_INTV_VALUE 31 0 R W D i Timer 1 Interval Value Note The value setting should consider the system clock and the timer clock source 11 3 8 ASYNC Timer 1 Current Value Register Offset 0x28 Register Name ASYNC_TMR1_CURNT_VALUE_REG Read W Default nat Bit f Description rite Hex TMR1_CUR_VALUE SC SS Timer 1 Current Value Note Timer 1 current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale 11 3 9 ASYNC Timer 2 Contro
363. t f Description ite Hex 31 0 R W UDF WERDD The start address of write back data in WORD 28 5 20 DEBE Write Back Butter Line Width Register Offset 0x8F8 Register Name DEBE WBLINEWIDTH REG Read Wr Default GA Bit Description ite Hex 31 0 RAW UDF WB_LINEWIDTH Write back image buffer line width in bits A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 322 Allwinner Technology 28 5 21 DEBE Input YUV Channel Control Register Offset 0x920 Register Name DEBE IYUVCTL REG RENN r Bit Description EET i IYUV FBFMT Input data format 000 planar YUV 411 001 planar YUV 422 010 planar YUV 444 011 interleaved YUV 422 100 interleaved YUV 444 Other illegal IYUV FBPS Pixel sequence In planar data format mode 00 Y3Y2Y1YO 01 YOY1Y2Y3 the other 2 components are same Other illegal In interleaved YUV 422 data format mode 00 UYVY 01 YUYV 10 VYUY 11 YVYU In interleaved YUV 444 data format mode 00 AYUV 01 VUYA Other illegal IYUV EN YUV channel enable control 0 disable 1 enable Source Data Input Data Ports Input buffer channel Planar YUV Interleaved YUV A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 323 Allwinner Technology Channel Channel Channel 28 5 22 DEBE YUV Channel Frame Butter Address Register Offset Channel 0 0x930 Channel 1 0x934 Ch
364. t path through the panel to GND initiating an interrupt to the processor During the measurement cycle for X Y and Z position the X input is disconnected from the PENIRQ pull down transistor to eliminate any pull up resistor leakage current from flowing through the touch screen thus causing no errors A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 257 Allwinner Technology AVCC Y Rro x S a i D F High when X or Y driver L ON is on A y High when X or Y driver is on Figure 25 13 Example of Pen touch Interrupt via Pen Down IRQ 25 4 8 Median and Averaging Filter As explained in the Touch Screen Principles section touch screens are composed of two resistive layers normally placed over an LCD screen Because these layers are in close proximity to the LCD screen noise can be coupled from the screen onto these resistive layers causing errors in the touch screen positional measurements The controller contain a filtering block to process the data and discard the spurious noise before sending the information to the host The purpose of this block is not only the suppression of noise the on chip filtering also greatly reduces the host processing loading The processing function consists of two filters that are applied to the converted results the median filter and the averaging filter The median filter suppresses the isolated out of range noise and s
365. ta with Z filter 10 FIFO store X Y X2 Y2 data with Z filter 11 Debug Mode FIFO store X1 Y1 X2 Y2 Z1 Z2 data 25 24 R W 0x0 PRE MEA EN TP Pressure Measurement Enable Control 0 Disable 1 Enable 23 0 RW OxFFF PRE_MEA_THRE_CNT TP Pressure Measurement threshold Control Notes 0x000000 least sensitive OxFFFFFF most sensitive Note used to adjust sensitivity of touch 25 6 4 Median Filter Control Register Offset Ox0c Register Name TP_CTRL3 Bit Read W Default Description rite Hex 31 3 2 R W 0x0 FILTER_EN Filter Enable 0 Disable 1 Enable 1 0 R W 0x1 FILTER_TYPE Filter Type 00 4 2 01 5 3 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 262 Allwinner Technology 10 8 4 11 16 8 25 6 5 TP Interrupt amp FIFO Control Register Offset 0x10 Register Name TP INT Bit Read W rite Default Hex Description 0x0000 0FO00 31 19 18 RW Ox0 17 RW Ox0 TP_OVERRUN IRQ EN TP FIFO Over Run IRQ Enable 0 Disable 1 Enable 16 R W 0x0 TP DATA IRQ EN TP FIFO Data Available IRQ Enable 0 Disable 1 Enable 15 14 13 RW Ox0 TP_DATA XY CHANGE TP FIFO X Y Data interchange Function Select 0 Disable 1 Enable 12 8 R W OxF TP FIFO TRIG LEVEL TP
366. te 0 Mute 1 Not mute PAMUTE 6 RW SE All input source to PA mute including Output mixer and Internal DAG O Mute 1 Not mute PAVOL 5 0 R W 0x0 PA Volume Control PAVOL Total 64 level from OdB to 62dB 1dB step mute when 000000 23 4 6 ADC FIFO Control Register Offset 0x1C Register Name AC_ADC_FIFOC Bit Read Write Default Description ADFS Sample Rate of ADC 000 48KHz 010 24KHz 100 12KHz ned Ne i 110 Reserved 001 32KHz 011 16KHz 101 8KHz 111 Reserved EN_AD og RW oxo ADG Digital Part Enable en_ad 0 Disable 1 Enable 27 25 RX FIFO MODE RX FIFO Output Mode Mode 0 1 24 R W 0x0 0 Expanding 0 at LSB of TX FIFO register 1 Expanding received sample sign bit at MSB of TX FIFO register For 24 bits received audio sample A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 240 Allwinner Technology Mode 0 RXDATA 31 0 FIFO_O 23 0 8 h0 Mode 1 Reserved For 16 bits received audio sample Mode 0 RXDATA 31 0 FIFO_O 23 8 16 h0 Mode 1 RXDATA 31 0 16 FIFO_O 23 FIFO_O 23 8 23 13 12 8 RW OxF RX FIFO TRG LEVEL RX FIFO Trigger Level RXTL 4 0 Interrupt and DMA request trigger level for TX FIFO normal condition IRQ DRQ Generated when WLEVEL gt RXTL 4 0 Note WLEVEL represents the number of valid samples in the RX FIFO R W 0x0 ADC MONO EN ADC Mono Enable 0 Stereo 16
367. te Hex INT IRQ SRC PEND2 Interrupt IRQ Source 95 64 Pending Clear Bit 31 0 R 0x0 SNE f 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 13 4 8 Interrupt FIQ Pending Clear Register 0 Default 0x00000000 Offset 0x20 Register Name INTC FIQ PEND REGO Read W Default ho Bit Description rite Hex INT FIQ SRC PENDO 31 0 R E Interrupt FIQ PUS 31 ed e Bit 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 13 49 Interrupt FIQ Pending Clear Register 1 Default 0x00000000 Offset 0x24 Register Name INTC FIQ PEND REG1 Read W Default SC Bit i Description rite Hex INT FIQ SRC PEND1 Interrupt Source 63 32 Pending Clear Bit 31 0 R 0x0 hr f 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 13 4 10 Interrupt FIQ P ending Clear Register 2 Default 0x00000000 Offset 0x28 Register Name INTC FIQ PEND REG2 Bit Read W Default Description A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 110 Allwinner Technology rite Hex INT FIQ SRC PEND2 31 0 R 056 Interrupt Source PEN Jo Bit 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 13 4 11 Interrupt Selec t Register 0 Default 0x00000000 Offset 0x30 Register Name INTC SEL REGO Read W Default _ Bit Descrip
368. te Hex TMRO CUR VALUE 1 R SH de a Timer 0 Current Value Note Timer 0 current value is a 32 bit down counter from interval value to 0 This register can be A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 88 Allwinner Technology read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale 11 3 6 ASYNC Timer 1 Control Register Default 0x00000004 Offset 0x20 Register Name ASYNC_TMR1_CTRL_REG Read W Default W Bit f Description rite Hex 31 8 TMR1 MODE Timer1 mode 0 Continuous mode When reaches the internal value the timer will 7 R W 0x0 not be disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically TMR1 CLK PRES Select the pre scale of timer 1 clock source 000 1 001 2 010 4 6 4 R W 0x0 011 8 100 16 101 32 110 64 111 128 TMR1_CLK_SRC Timer 1 Clock Source 00 Do COS 01 OSC24M 10 PLL6 6 11 TMR1 RELOAD Timer 1 Reload 1 R W 0x0 0 No effect 1 Reload timer 1 Interval value After the bit is set it can not be written again before its cleared automatically TMR1_EN Timer 1 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 0 R W 0x0 ve If the curren
369. te dma SSPOL SPI Chip Select Signal Polarity Control 0 Active high polarity 0 Idle 4 R W 1 1 Active low polarity 1 Idle POL SPI Clock Polarity Control 0 Active high polarity 0 Idle 3 R W 1 1 Active low polarity 1 Idle PHA SPI Clock Data Phase Control 0 Phase 0 Leading edge for sample data 2 R W 1 1 Phase 1 Leading edge for setup data MODE SPI Function Mode Select 0 Slave Mode 1 R W 0 1 Master Mode EN SPI Module Enable Control 0 Disable 0 R W 0 1 Enable 18 4 4 SPI Interrupt Control Register Register Name SPI INTCTL Offset 0xOC Default Value 0x0000 0000 Bit Read Write Default Description A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 168 31 18 Allwinner Technology 17 RW SSI Interrupt Enable Chip Select Signal SSx from valid state to invalid state 0 Disable 1 Enable 16 R W Transfer Completed Interrupt Enable 0 Disable 1 Enable 15 14 R W TXFIFO under run Interrupt Enable 0 Disable 1 Enable 13 R W TX FIFO Overflow Interrupt Enable 0 Disable 1 Enable 12 R W TX FIFO 3 4 Empty Interrrupt Enable 0 Disable 1 Enable 11 R W TX FIFO 1 4 Empty Interrrupt Enable 0 Disable 1 Enable 10 R W TX FIFO Full Interrupt Enable 0 Disable 1 Enable R W TX FIFO Half Empty Interrupt Enable 0 Disable 1
370. ted DMA Byte Counter Register N 0 7 Offset 0x300 N 0x20 0Xc N 0 1 2 3 4 5 6 7 Register Name DDMA BC REG Read W Default W Bit Description rite Hex 31 25 24 0 RW S DDMA DC Dedicated DMA Byte Counter Note If ByteCounter 0 DMA will transfer no byte The maximum value is 0x1000000 14 4 11 Dedicated DMA Parameter Register Offset 0x300 N 0x20 0x18 N 0 1 2 3 4 5 6 7 Register Name DDMA PARA REG Read W Default D Bit Description rite Hex DEST DATA BLK SIZE 31 24 RW 0x0 p JAA x Destination Data Block Size n DEST_WAIT_CLK_CYC 23 16 R W 0x0 i Destination Wait Clock Cycles n SRC DATA BLK SIZE 15 8 R W 0x0 7 r S Source Data Block Size n SRC WAIT CLK CC 7 0 R W 7 ie Source Wait Clock Cycles n Note If the counter is N the value is N 1 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 144 Allwinner Technology 15 NAND Flash 15 1 Overview The NFC supports all NAND MLC flash memory available in the market and new types can be supported by software re configuration as well It can support 2 NAND flash with 3 3 V voltage supply There are 2 separate chip select lines CE to connect up to 2 flash chips with2 R B signals The On the fly error correction code ECC is built in NEC to enhance reliability BCH is implemented to detect and correct up to 64 bits err
371. teeeeeeeeeeeeeees 101 12 3 4 Sync Timer 0 Interval Value Low Register ccscceescesseeseeeeeseeeseeseeeteaeeeseeeeees 102 12 3 5 Sync Timer 0 Interval Value High Register 102 12 3 6 Sync Timer 0 Current Value Lo Feeler 102 12 3 7 Sync Timer 0 Current Value Hi Register sscisisicicreseisee niece 102 12 3 8 Sync Timer 1 Control Register Default 0x00000004 eee eee cette eeeeeeeeeeeeees 103 12 3 9 Sync Timer 1 Interval Value Low Register 104 12 3 10 Sync Timer 1 Interval Value High Register rrnnnnnnrnvnnnrvnnnnnrnvnnnrnnnnnnrnnnnnrnnnnnnrnnne 104 12 3 11 Syne Timer 1 Current Value Low Register ssh 104 12 3 12 Syne Timer 1 Current Value High Register 1 audi lenies 104 13 Interrupt Err tt besiess 105 ER EE eebe 105 13 2 Jee 105 19 e Dee ET LISTE soc as ele a a fet eee eee ee de 107 13 4 Interrupt Register Description ist 108 13 4 1 Interrupt Vector Register Default 0x00000000 onrrrnnnnnvrrnnnnnnrrennrnnrrnnnrrnrrnnnrenn 108 13 4 2 Interrupt Base Address Register Default 0x00000000 rrrvrnrenvrnnnnrnnrnnrnrenvnnrennn 109 13 4 3 Interrupt Protection Register Default 0x00000000 rrnrvrnnvrnnenvrnnnnrnnrnrnnenvrneennn 109 13 4 4 NMI Interrupt Control Register Default 0x00000000 ee eee eee eeteeeeeeeeeeeeeees 109 13 4 5 Interrupt IRQ Pending Register 0 Default 0Ox00000000 109 13 4 6 Interrupt IRQ Pending Register 1 Default 0
372. ter1 PMU IRQ EN REG 0x0040 PMU IRQ Enable Register PMU IRQ STATUS REG 0x0044 PMU IRQ Status Register PMU STATUS REG 0x0048 PMU Status Register PMU CPUVDD CTRL REG ADDR 0x004C PMU CPUVDD Register Address PMU TWI ADDR REG 0x0050 PMU TWI Address PMU CPUVDD VALUE REG 0x0054 PMU Cpuvdd Value PMU CPUVDD RAMP CTRL REG 0x0058 PMU CPUVDD Voltage Ramp Control PMU 32KHZ CPUVDD MIN REG 0x005C PMU 32khz CPUVDD Minimum Value PMU_VF_TABLE_REGO 0x0080 CPU speed max if the vddcpu 0 70v PMU_VF_TABLE_REG1 0x0084 CPU speed max if the vddcpu 0 75v PMU VF TABLE REG2 0x0088 CPU speed max if the vddcpu 0 80v PMU VF TABLE REG3 0x008C CPU speed max if the vddcpu 0 85v PMU_VF_TABLE_REG4 0x0090 CPU speed max if the vddcpu 0 90v PMU_VF_TABLE_REG5 0x0094 CPU speed max if the vddcpu 0 95v PMU VF TABLE REG6 0x0098 CPU speed max if the vddcpu 1 00v PMU VF TABLE REG7 0x009C CPU speed max if the vddcpu 1 05v PMU VF TABLE REG8 Ox00A0 CPU speed max if the vddcpu 1 10v A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 31 Allwinner Technology PMU VF TABLE REG9 0x00A4 CPU speed max if the vddcpu 1 15v PMU VF TABLE REG10 0x00A8 CPU speed max if the vddcpu 1 20v PMU VF TABLE REG11 0x00AC CPU speed max if the vddcpu 1 25v PMU VF TABLE REG12 0x00BO CPU speed max if the vddcpu 1 30v PMU VF TABLE REG13 0x00B4 CPU speed max if the vddcpu 1 35v PMU VF TABLE REG14 0x00B8 CPU speed max if
373. terrupt and the Character Timeout Interrupt if in FIFO mode and FIFOs enabled These are the second highest priority interrupts 0 Disable 1 Enable 19 4 6 UART Interrupt Iden tity Register Offset 0x08 Register Name UART_IIR Default Value 0x0000 0000 Bit Read Write Default Description 31 8 7 6 FEFLAG FIFOs Enable Flag This is used to indicate whether the FIFOs are enabled or disabled 00 Disable 11 Enable 5 4 3 0 0x1 IID Interrupt ID This indicates the highest priority pending interrupt which can be one of the following types 0000 modem status 0001 no interrupt pending 0010 THR empty 0100 received data available 0110 receiver line status 0111 busy detect A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 180 Allwinner Technology 1100 character timeout Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt Interrupt Priority ID Level Interrupt Type Interrupt Source Interrupt Reset 0001 None None Receiver Line Overrun parity framing errors Reading the line status 0110 Highest Status or break interrupt register Reading the receiver Receiver data available S h buffer register non FIFO non FIFO mode or FIFOs f Rece
374. the same as the corresponding bit The read bit value is the value setup by software If the port is configured as functional pin the undefined 20 0 R W 0 value will be read 33 4 6 PB Multi Driving Register 0 Register Name PB_DRVO Offset 0x38 Default Value 0x5555 5555 Bit Read Write Default Description PB n Multi Driving Select n 0 15 2i 1 2i 00 Level 0 01 Level 1 i 0 15 RAV Ox1 10 Level 2 11 Level 3 33 4 7 PB Multi Driving Register 1 Register Name PB DRV1 Offset 0x3C Default Value 0x0000 0155 Bit Read Write Default Description 31 10 PB n Multi Driving Select n 16 20 2i 1 2i 00 Level 0 01 Level 1 i 0 4 R W 0x1 10 Level 2 11 Level 3 33 4 8 PB Pull Register 0 Register Name PB_PULLO Offset 0x40 Default Value 0x0000 0000 Bit Read Write Default Description PB n Pull up down Select n 0 15 2i 1 2i 00 Pull up down disable 01 Pull up i 0 15 RW 0x0 10 Pull down 11 Reserved 33 4 9 PB Pull Register 1 Register Name PB PULL1 Offset 0x44 Default Value 0x0000 0000 Bit Read Write Default Description 31 10 2i 1 2i PB n Pull up down Select n 16 20 i 0 4 R W 0x0 00 Pull up down disable 01 Pull up enable A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 371 Allwinner Te
375. the vddcpu 1 40v PMU VF TABLE REG15 0x00BC CPU speed max if the vddcpu 1 45v PMU VF TABLE REG16 0x00C0 CPU speed max if the vddcpu 1 50v PMU VF TABLE REG17 0x00C4 CPU speed max if the vddcpu 1 55v PMU VF TABLE REG18 0x00C8 CPU speed max if the vddcpu 1 60v PMU_VF_TABLE_VALID_REG 0x00CC PMUVf Table Valid Control PMU VF TABLE INDEX REG 0x00D0 PMU Vf Table Index PMU VF TABLE RANGE REG 0x00D4 PMU Vf Table Range PMU SPEED FACTOR REGO Ox00E0 PMU Speed Factor Register 0 PMU SPEED FACTOR REG 0x00E4 PMU Speed Factor Register 1 PMU SPEED FACTOR REG2 0x00E8 PMU Speed Factor Register 2 CPU IDLE CNT LOW REG Ox00F0 CPU Idle Counter Low CPU IDLE CNT HIGH REG 0x00F4 CPU Idle Counter High CPU IDLE COUNTER _CTRL REG 0x00F8 CPU Idle Counter Control CPU IDLE STATUS REG Ox00FC CPU Idle Status Register 5 3 PMU Register Description 5 3 1 PMU DVFS Control Register 0 Register Name PMU DVFS CTRL REGO Offset 0x00 Read W Default a Bit Description rite Hex 31 18 17 16 RW 0x0 11 DVFS MODE SEL DVFS Mode Select 00 mode 0 01 mode 1 10 mode 2 AXI DIV AUTO SWITCH 15 R W 0x0 AXICLK auto switch enable 0 Disable 1 Enable 14 13 VOLT CHANGE MODE Voltage Change Mode 12 RW 0x0 0 normal mode 1 maximum mode 11 9 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 32 Allwinner Technology Ox0 CLK CHANGE
376. time 2T T16 NFC_WE high to tWB Specified by timing configure R B busy register NFC_TIMING_CFG T17 NFC_WE high to tWHR_ Specified by timing configure NFC_RE low register NFC_TIMING_CFG T18 NFC REf high to tRHW Specified by timing configure NFC_WE low register NFC_TIMING_CFG T19 Address to Data tADL Specified by timing configure Loading time register NFC_TIMING_CFG Notes T is the clock period duration of NFC CLK x2 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 150 Allwinner Technology 15 4 NFC Operation Guide CLE X a ADARI EEA WE O U Ld UUU Farnes ALE mm GP Te vor om on Figure15 12 Page Read Command Diagram CLE FN GZ TE KLAN two tWC gt tADL twB tPROG ALE LA Ge son KA Co Add1 K Col Add2 YRow Add1 N Row Add2X Row Add3 SerialData 1 up to m Byte Program Input Command Column Address Row Address Serial Input Command Figure15 13 Page Program Diagram VOx IJ ICT AA ALL O U h UT Eee L Es Ha Eee oon Address 5Cycle aon 70n 100 oon Data Output Serial Access Figure15 14 EF NAND Page Read Diagram A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 151 Allwinner Technology CLE ALE VOx TX om Yeu nar ca Add2 Row em ow ae 30h Row Address Col
377. tion rite Hex INT_SRC_TYPEO Int t Source 31 0 irq type select 31 0 RM 0x0 ve i AL 0 IRQ 1 FIQ 13 4 12 Interrupt Selec t Register 1 Default 0x00000000 Offset 0x34 Register Name INTC SEL REG1 Read W Default GE Bit i Description rite Hex INT_SRC_TYPE1 31 0 RW 0x0 Interrupt Source 63 32 irq type select 0 IRQ 1 FIQ 13 4 13 Interrupt Selec t Register 2 Default 0x00000000 Offset 0x38 Register Name INTC SEL REG2 Read W Default Ce Bit Description rite Hex INT_SRC_TYPE2 31 0 R W oxo Interrupt Source 95 64 irq type select 0 IRQ 1 FIQ 13 4 14 Interrupt Enable Register 0 Default 0x00000000 Offset 0x40 Register Name INTC_EN_REGO Read W Default Bit Description rite Hex INT SRC ENO Interrupt Source 31 0 Enable Bits 31 0 R W 0x0 ass pe 6 l e 0 Corresponding interrupt is disabled 1 Corresponding interrupt is enabled 13 4 15 Interrupt Enable Register 1 Default 0x00000000 Offset 0x44 Register Name INTC EN REG1 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 111 Allwinner Technology Read W Default a Bit Description rite Hex INT_SRC_EN1 32 Enable Bits 31 0 RW 0x0 niertupt Soules Po nable its 0 Corresponding interrupt is disabled 1 Corresponding interrupt is enabled
378. trolMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set When set the port s power state is only affected by per port power control Set ClearPortPower When cleared the port is controlled by the global power switch Set ClearGlobalPower If the device is configured to global switching mode PowerSwitchingMode 0 this field is not valid Bito Reserved Biti Ganged power mask on Port 1 31 16 RW R 0x0 Bit2 Ganged power mask on Port 2 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 227 Allwinner Technology Bit15 Ganged power mask on Port 15 15 0 R W R 0x0 DeviceRemovable Each bit is dedicated to a port of the Root Hub When cleared the attached device is removable When set the attached device is not removable Bito Reserved Biti Device attached to Port 1 Bit2 Device attached to Port 2 Bit15 Device attached to Port 15 22 6 21 HcRhStatus Register Offset 0x450 Register Name HcRhStatus Register Default Value Read Write Bit HCD HC Default Description write ClearRemoteWakeupEnable Write a 1 clears DeviceRemoteWakeupEnable Write a 0 has no 31 W R 0 effect 30 18 0x0 Reserved OverCurrentindicatorChang This bit is
379. ts N 3 are used for the Frame List current index It Means that each location of the frame list is accessed 8 times frames or Micro frames before moving to the next index The following illustrates Values of N based on the value of the Frame List Size field in the USBCMD register USBCMD Frame List Number Elements N Size 00b 1024 12 01b 512 11 10b 256 10 13 0 R W 0 11b Reserved Note This register must be written as a DWord Byte writes produce undefined results 22 5 10 EHCI Periodic Frame List Base Address Register Register Name PERIODICLISTBASE Offset 0x24 Default Value Undefined Bit Read Write Default Description Base Address These bits correspond to memory address signals 81 12 respectively This register contains the beginning address of the Periodic Frame List in the system memory System software loads this register prior to starting the schedule execution by the Host Controller The memory structure referenced 31 12 R W by this physical memory pointer is assumed to be 4 K byte aligned A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 209 Allwinner Technology The contents of this register are combined with the Frame Index Register FRINDEX to enable the Host Controller to step through the Periodic Frame List in sequence Reserved Must be written as 0x0 during runtime the values of these bits are 11 0 un
380. ty Select It is writeable only when UART is not busy USR 0 is zero and always writable readable This is used to select between even and odd parity when parity is enabled PEN set to one 0 Odd Parity 4 R W 0 1 Even Parity PEN Parity Enable It is writeable only when UART is not busy USR 0 is zero and always readable This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively 0 parity disabled 3 R W 0 1 parity enabled 2 R W 0 STOP A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 183 Allwinner Technology Number of stop bits It is writeable only when UART is not busy USR 0 is zero and always readable This is used to select the number of stop bits per character that the peripheral transmits and receives If set to zero one stop bit is transmitted in the serial data If set to one and the data bits are set to 5 LCR 1 0 set to zero one and a half stop bits is transmitted Otherwise two stop bits are transmitted Note that regardless of the number of stop bits selected the receiver checks only the first stop bit 0 1 stop bit 1 1 5 stop bits when DLS LCR 1 0 is zero else 2 stop bit 1 0 R W DLS Data Length Select It is writeable only when UART is not busy USR 0 is zero and always readable This is used to select the number of data bits per character th
381. ual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 278 Source Pixel Columns 2 2 X 1 1 Xo Xia X21 Source Pixel Rows ke E p X Eur n B h a m 1 m 1 n ke k e 10 k 20 2 18 7 U U a O Does ke k va ke k ke ke o ke 27 3 4 Input Data Channel DEFE supports planar or interleaved video component data inputting via 3 input channels channel channel1 and channel2 In planar mode if the U V data are not combined channeoO 1 2 refer to the Y U V data channel respectively and if the U V data are combined the channelO refers to the Y channel and the channel 1 refers to the U V combined channel and the channel2 will be inactive In interleaved mode the channel refers to UYVY or VYUY YUYV or YVYU depending on the configuration the channel1 and channel will be inactive Note Interleaved YUV data only YUV422 and YUV444 format is valid 27 3 5 CSC Color Space Conversion Description YUV RGB conversion is used to generate an RGB version data of the image for display or RGB YUV version data for write back to memory Conversion algorithm formula R Y R Y component coefficient Y Y R component coefficient R R U component coefficient U Y G component coefficient G R V component coefficient V Y B component coefficient B R constant Y constant G U G Y component coefficient Y U R component coefficient R
382. umn Address de s Figure15 15 Interleave Page Read Diagram A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 152 Allwinner Technology 16 SD MMC Controller 16 1 Overview The SD MMC controller can be configured as a Secure Digital Multimedia Card controller which simultaneously supports Secure Digital memory SD Memo UHS 1 Card Secure Digital I O SDIO Multimedia Cards MMC eMMC Card and Consumer Electronics Advanced Transport Architecture CE ATA The SD MMC controller features Support Secure Digital memory protocol commands up to SD3 0 Support Secure Digital I O protocol commands Support Multimedia Card protocol commands up to MMC4 3 Support CE ATA digital protocol commands Support eMMC boot operation and alternative boot operation Support Command Completion signal and interrupt to host processor and Command Completion Signal disable feature Support one SD Verson1 0 to 3 0 or MMC Verson3 3 to 4 3 or CE ATA device Support hardware CRC generation and error detection Support programmable baud rate Support host pull up control Support SDIO interrupts in 1 bit and 4 bit modes Support SDIO suspend and resume operation Support SDIO read wait Support block size of 1 to 65535 bytes Support descriptor based internal DMA controller Internal 16x32 bit 64 bytes total FIFO for data transfer 16 2 SD MMC Timing Diagram Please
383. upt 13 0x0034 14 0x0038 15 0x003C 16 0x0040 17 0x0044 18 0x0048 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 105 Allwinner Technology Interrupt Source SRC Vector FIQ Description 19 0x004C 20 0x0050 21 0x0054 Timer 0 22 0x0058 Timer port 0 Timer 1 23 0x005C Timer port 1 Timer 2 Alarm WD 24 0x0060 Timer 2 Alarm Watchdog Timer 3 25 0x0064 Timer 3 interrupt 26 0x0068 DMA 27 0x006C DMA channel interrupt PIO 28 0x0070 PIO interrupt Touch Panel 29 0x0074 Touch Panel interrupt Audio Codec 30 0x0078 Analog Audio Codec interrupt LRADC 31 0x007C LRADC interrupt SD MMC 0 32 0x0080 SD MMC Host Controller 0 interrupt SD MMC 1 33 0x0084 SD MMC Host Controller 1 interrupt SD MMC 2 34 0x0088 SD MMC Host Controller 2 interrupt 35 0x008C 36 0x0090 NAND 37 0x0094 NAND Flash Controller NFC interrupt USB DRD 38 0x0098 USB DRD wakeup connect disconnect interrupt USB EHCI 39 0x009C bs EHCI wakeup connect disconnect interrupt USB OHCI 40 0x00A0 ee OHCI wakeup connect disconnect interrupt 41 0x00A4 CSI 42 0x00A8 CSI interrupt 43 0x00AC LCD Controller 44 0x00B0 LCD Controller interrupt 45 0x00B4 46 0x00B8 DE FE DE BE 47 0x00BC DE FE DE BE interrupt 48 0x00C0 PMU
384. upt Source Priority 4 INTC_SRC_PRIO_REG5 0x0094 Interrupt Source Priority 5 13 4 Interrupt Register Description 13 4 1 Interrupt Vector Register Default 0x00000000 Offset 0x00 Register Name INTC VECTOR REG Read W Default WW Bit Description rite Hex VECTOR ADDR 31 2 R 0x0 This register present the vector address for the interrupt currently active on the CPU IRQ input A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 108 Allwinner Technology 1 0 R Ox0 ZERO Always return zero to this field 13 4 2 Interrupt Base Address Register Default 0x00000000 Offset 0x04 Register Name INTC BASE ADDR REG Read W Default ar Bit Description rite Hex BASE_ADDR 31 2 R W 0x0 This bit field holds the upper 30 bits of the base address of the vector table ZERO We GE Always write zero to this bit field 13 4 3 Interrupt Protection Register Default 0x00000000 Offset 0x08 Register Name INC PROTEC REG Read W Bit rite Default Hex Description 31 1 Ox0 PROTEGT EN Enables or disables protected register access 0 disable protection mode 1 enable protection mode If enabled only privileged mode access can access the interrupt controller registers If disabled both user mode and privileged mode can access the registers This r
385. uptEnable Register Offset 0x410 Register Name HcinterruptEnable Register Default Value 0x0 Read Write Bit HCD HC Default Description MasterInterruptEnable 31 RW R 0x0 A 0 writtern to this field is ignored by HC A 1 written to this field A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 219 Allwinner Technology enables interrupt generation due to events specified in the other bits of this register This is used by HCD as Master Interrupt Enable 30 7 0x0 Reserved RootHubStatusChange Interrupt Enable 0 Ignore 1 Enable interrupt generation due to Root Hub Status 6 RW R 0x0 Change FrameNumberOverflow Interrupt Enable 0 Ignore 1 Enable interrupt generation due to Frame Number Over Flow 5 RW R 0x0 UnrecoverableError Interrupt Enable 0 Ignore 4 RW R 0x0 1 Enable interrupt generation due to Unrecoverable Error ResumeDetected Interrupt Enable 0 Ignore 3 RW R 0x0 1 Enable interrupt generation due to Resume Detected StartofFrame Interrupt Enable 0 Ignore 2 RW R 0x0 1 Enable interrupt generation due to Startof Flame WritebackDoneHead Interrupt Enable 0 Ignore 1 RW R 0x0 1 Enable interrupt generation due to Write back Done Head SchedulingOverrun Interrupt Enable 0 Ignore 0 RW R 0x0 1 Enable interrupt generation due to Sche
386. us bit is set and the interrupt line is set if the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled R W 0x0 ADC1 DATA IRQ PENDING ADC 1 Data IRQ Pending Bit 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled RW Ox0 ADCO KEYUP PENDING ADC 0 Key up pending Bit When general key pull up it the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled R W 0x0 ADCO ALRDY HOLD PENDING ADC 0 Already Hold Pending Bit When hold key pull down and pull the general key down if the corresponding interrupt is enabled A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 250 Allwinner Technology 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled 2 R W 0x0 ADCO_HOLDKEY_PENDING ADC 0 Hold Key pending Bit When Hold key pull down the status bit is set and the interrupt line is set if the corresponding interrupt is enabled 0 NO IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its correspondin
387. used DCLKO normal phase offset 01 used DCLK1 1 3 phase offset 10 used DCLK2 2 3 phase offset 11 reserved 27 R W 103_Inv 0 not invert 1 invert 26 RW 102_ Inv 0 not invert 1 invert 25 R W 101_Inv 0 not invert 1 invert 24 RW 100_Inv 0 not invert 1 invert 23 0 RW Data Inv A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 343 Allwinner Technology TCONO output port D 23 0 polarity control with independent bit control Os normal polarity 1s invert the specify output 29 3 19 TCONO IO TRI REG Offset 0x08C Register Name TCONO IO control register Bit Read W rite Default Hex Description 31 28 27 RW IO3 Output Tri En 1 disable 0 enable 26 RW 102 Output Tri En 1 disable 0 enable 25 R W 101 Output Tri En 1 disable 0 enable 24 R W 100 Output Tri En 1 disable 0 enable 23 0 RW OxFFFF FF Data_Output_Tri_En TCONO output port D 23 0 output enable with independent bit control 1s disable Os enable 29 3 20 TCON1 CTL REG Offset 0x090 Register Name TCON1 control register Bit PERRY EEN Description rite Hex TCON1 En 31 R W 0 0 disable 1 enable 30 21 Interlace En 20 R W 0 0 disable 1 enable 19 9 8 4
388. ut and not interleaved mode 110 planar YUV 422 only support YUV input 111 planar YUV 411 only support YUV input Other reserved 27 5 19 DEFE INT EN REG Offset 0x60 Register Name DEFE INT EN REG f Read W Default SE Bit Description rite Hex 31 11 REG LOAD EN 10 R W 0x0 T F Register ready load interrupt enable LINE EN 9 R W 0x0 ue Line interrupt enable 8 WB_EN Write back end int t enable 7 RW oxo ris ack end interrup 0 Disable 1 Enable 6 0 27 5 20 DEFE_INT STATUS REG Offset 0x64 Register Name DEFE INT STATUS REG r Read W Default ST Bit Description rite Hex 31 11 REG_LOAD_ STAT 10 R W 0x0 c AADS se Register ready load interrupt status LINE STATUS 9 R W 0x0 ae Line interrupt status 8 7 RW T WB_STATUS Write back end interrupt status 6 0 27 5 21 DEFE_STATUS REG Offset 0x68 Register Name DEFE STATUS REG Read W Default SC Bit Description rite Hex 31 29 28 16 R 0x0 LINE ON SYNC A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 293 Allwinner Technology Line number when sync reached WB ERR SYNC 15 R W 0x0 e Sync reach flag when capture in process WB ERR LOSEDATA 14 R W 0x0 Lose data flag when capture in process 13 WB ERR STATUS write
389. value upon the completion of the Reset sequence 22 6 15 HcFmRemaining Register Offset 0x438 Register Name HcFmRemaining Default Value 0x0 Read Write Bit HCD HC Default Description FrameRemaining Toggle 31 R R W 0x0 This bit is loaded from the FramelntervalToggle field of A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 224 Allwinner Technology HcFminterval whenever FrameRemaining reaches 0 This bit is used by HCD for the synchronization between Framelnterval and FrameRemaining 30 14 0x0 Reserved 13 0 R RW 0x0 FramRemaining This counter is decremented at each bit time When it reaches zero it is reset by loading the Framelnterval value specified in HcFminterval at the next bit time boundary When entering the USBOPERATIONAL state HC re loads the content with the Framelnterval of HcFminterval and uses the updated value from the next SOF 22 6 16 HcFmNumber Register Register Name HcFmNumber Offset 0x43c Default Value 0x0 Read Write Bit HCD HC Default Description 31 16 Reserved FrameNumber This is incremented when HcFmRemaining is re loaded It will be rolled over to 0x0 after OxOffff When entering the USBOPERATIONAL state this will be incremented automatically The content will be written to HCCA after HC has incremented the FrameNumber at each frame bound
390. vel 0x0 level 0 lowest priority Leveli 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ43_PRIO IRQ 43 Priority Set priority level for IRQ bit 43 23 22 RW 0x0 Level 0x0 level 0 lowest priority Leveli 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ42_PRIO IRQ 42 Priority Set priority level for IRQ bit 42 21 20 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ41 PRIO 19 1 R ad La pene IRQ 41 Priority A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 120 Allwinner Technology Offset 0x88 Register Name INTC SRC PRIO REG2 Set priority level for IRQ bit 41 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ40 PRIO IRQ 40 Priority Set priority level for IRQ bit 40 17 16 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ39 PRIO IRQ 39 Priority Set priority level for IRQ bit 39 15 14 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x1 level 2 Level 0x1 level 3 highest priority IRQ38_PRIO IRQ 38 Priority Set priority level for IRQ bit 38 13 12 RW 0x0 Level 0x0 level 0 lowest priority
391. vel3 0x3 level 3 highest priority IRQ9_PRIO IRQ 9 Priority Set priority level for IRQ bit 9 19 18 RA 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x2 level 2 Level 0x3 level 3 highest priority IRQ8 PRIO IRQ 8 Priority Set priority level for IRQ bit 8 17 16 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority IRQ7_PRIO 15 14 RW 0x0 IRQ 7 Priority Set priority level for IRQ bit 7 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 115 Allwinner Technology Offset 0x80 Register Name INTC SRC PRIO REGO Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority IRQ6 PRIO IRQ 6 Priority Set priority level for IRQ bit 6 13 12 RW 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority IRQ5_PRIO IRQ 5 Priority Set priority level for IRQ bit 5 11 10 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level 0x2 level 2 Level3 0x3 level 3 highest priority IRQ4 PRIO IRQ 4 Priority Set priority level for IRQ 4 9 8 R W 0x0 Level 0x0 level 0 lowest priority Level 0x1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority IRQ3_PRIO IRQ 3 Priority Set
392. winner Technology TP_INT_FIFOC 0x10 TP Interrupt FIFO Control Register TP_INT_FIFOS 0x14 TP Interrupt FIFO Status Register TP_CDAT 0x1C TP Common Data Register TP_DATA 0x24 TP Data Register TP 10 CONFIG 0x28 TP PORT IO Configure Register TP PORT DATA Ox2C TP Port Data Register 25 6 TP Register Description 25 6 1 TP Control Register 0 Offset 0x00 Register Name TP_CTRL Bit Read Write Default Hex R W 31 24 OxF Description ADC_FIRST_DLY ADC First Convert Delay setting Based on ADC First Convert Delay Mode select 23 R W 0x1 22 R W 0x0 ADC_FIRST_DLY_MODE ADC First Convert Delay Mode Select 0 CLK_IN 16 1 CLK_IN 16 256 ADC_CLK_SELECT ADC Clock Source Select 0 HOSC 24MHZ 1 Audio PLL R W 0x0 21 20 0x0 ADC_CLK_DIVIDER ADC Clock Divider CLK_IN 00 CLK 2 01 CLK 3 10 CLK 6 11 CLK 1 In TP mode these two bits must set 1x FS_DIV ADC Sample Frequency Divider 0000 CLK_IN 2 20 n 0001 CLK_IN 2 20 n 0010 CLK_IN 2 20 n 1111 CLK_IN 32 0x0 A13 User Manual V1 3 T ACQ Touch panel ADC acquire time CLK IN 16 N Copyright O 2013 Allwinner Technology All Rights Reserved 260 Allwinner Technology 25 6 2 TP control Register 1 Offset 0x04 Register Name TP CTRL1 Description Bit Read Default Write Hex 31 20 STYLUS UP DEBOUNCE Stylus Up De bounce Time setting 0x00 0 Oxff
393. winner Technology two wire bus Enable 1 b0 The two wire bus inputs ISDA ISCL are ignored and the 2 Wire Controller will not respond to any address on the bus 1 b1 The TWI will respond to calls to its slave address and to the general call address if the GCE bit in the ADDR register is set Notes In master operation mode this bit should be set to 1 M STA Master Mode Start When M STA is set to 1 TWI controller enters master mode and will transmit a START condition on the bus when the bus is free If the M STA bit is set to 1 when the 2 Wire Controller is already in master mode and one or more bytes have been transmitted then a repeated START condition will be sent If the M STA bit is set to 1 when the TWI is being accessed in slave mode the TWI will complete the data transfer in slave mode then enter master mode when the bus has been released The M STA bit is cleared automatically after a START condition is sent writing a 0 to this bit has no effect M STP Master Mode Stop If M STP is set to 1 in master mode a STOP condition is transmitted on the two wire bus If the M_STP bit is set to 1 in slave mode the TWI will behave as if a STOP condition has been received but no STOP condition will be transmitted on the two wire bus If both M STA and M STP bits are set the TWI will first transmit the STOP condition if in master mode and then transmit the START condition The M_STP
394. x0 Bos Read LocalPowerStatus When read this bit returns the LocalPowerStatus of the Root Hub The Root Hub does not support the local power status feature thus this bit is always read as 0 Write ClearGlobalPower When write this bit is operated as the ClearGlobalPower In global power mode PowerSwitchingMode 0 This bit is written to 1 to turn off power to all ports clear PortPowerStatus In per port power mode it clears PortPowerStatus only on ports whose 0 RW IR 0x0 PortPowerControlMask bit is not set Writing a 0 has no effect 22 6 22 HcRhPortStatus Register Offset 0x454 Register Name HcRhPortStatus Default Value 0x100 Bit Read Write HCD HC Default Description 31 21 Ox0 Reserved 20 R W R W 0x0 PortResetStatusChange This bit is set at the end of the 10 ms port reset signal The HCD writes a 1 to clear this bit Writing a 0 has no effect 0 port reset is not complete 1 port reset is complete 19 R W R W 0x0 PortOverCurrentindicatorChange This bit is valid only if overcurrent conditions are reported on a per port basis This bit is set when Root Hub changes the PortOverCurrentindicator bit The HCD writes a 1 to clear this bit Writing a 0 has no effect 0 no change in PortOverCurrentindicator 1 PortOverCurrentindicator has changed 18 R W R W
395. x0C Default Value UNDEFINED Bit Read Write Default Description 31 0 R HCSP PORTROUTE A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 202 Allwinner Technology This optional field is valid only if Port Routing Rules field in HCSPARAMS register is set to a one This field is used to allow a host controller implementation to explicitly describe to which companion host controller each implemented port is mapped This field is a 15 element nibble array each 4 bit is one array element Each array location corresponds one to one with a physical port provided by the host controller e g PORTROUTE 0 corresponds to the first PORTSC port PORTROUTE 1 to the second PORTSC port etc The value of each element indicates to which of the companion host controllers this port is routed Only the first N_PORTS elements have valid information A value of zero indicates that the port is routed to the lowest numbered function companion host controller A value of one indicates that the port is routed to the next lowest numbered function companion host controller and so on 22 5 6 EHCI USB Command Register Register Name USBCMD Default Value 0x00080000 0x00080B00 if Asynchronous Offset 0x10 Schedule Park Capability is a one Bit Read Write Default Description Reserved 31 24 0 These bits are reserved and should be set to zero Interrupt Threshold Contro
396. x100 N 0x20 C Normal DMA Byte Counter Dedi DMA fi i DDMA_CFG_REG 0x300 N 0x20 ee AIO N 0 1 2 3 4 5 6 7 Dedi DMA DDMA_SRC_ADDR_REG Get EE Start Address Dedicated DMA Destination DDMA DEST ADDR REG 0x300 N 0x20 8 Start Address DDMA BC REG 0x300 N 0x20 C Dedicated DMA Byte Counter DDMA_PARA_REG 0x300 N 0x20 0x18 Dedicated DMA Parameter 14 4 DMA Register Description 14 4 1 DMA IRQ Enable Register Default 0x00000000 Offset 0x00 Register Name DMA_IRQ_EN_REG A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 131 Allwinner Technology Bit Read W rite Default Hex Description 31 R W 0x0 DDMA7 END IRQ EN Dedicated DMA 7 End Transfer Interrupt Enable 0 Disable 1 Enable 30 RW Ox0 DDMA7 HF IRQ EN Dedicated DMA 7 Half Transfer Interrupt Enable 0 Disable 1 Enable 29 R W 0x0 DDMA6_END_IRQ_EN Dedicated DMA 6 End Transfer Interrupt Enable 0 Disable 1 Enable 28 R W 0x0 DDMA6_HF_IRQ_EN Dedicated DMA 6 Half Transfer Interrupt Enable 0 Disable 1 Enable 27 R W 0x0 DDMA5_END_IRQ_EN Dedicated DMA 5 End Transfer Interrupt Enable 0 Disable 1 Enable 26 R W 0x0 DDMA5_HF_IRQ_EN Dedicated DMA 5 Half Transfer Interrupt Enable 0 Disable 1 Enable 25 R W 0x0 DDMA4_END_IRQ_EN Dedicated DMA 4 End Transfer Interrupt Enable 0 Disable 1 Enable
397. y All Rights Reserved 245 Allwinner Technology 24 LRADC 24 1 Overview LRADC is 6 bit resolution It features Support APB 32 bit bus width Support interrupt Support hold key and general key Support single key and continue key mode 6 bit resolution Voltage input range between 0 to 2V Sample rate up to 250Hz 24 2 Principle of operation 24 2 1 Block Diagram The LRADC converted data can by accessed by interrupt and polling method If software can t access the last converted data instantly the new converted data would update the old one at new sampling data 24 2 2 Hold Key and General Key Function Introduction When ADC_IN Signal change from ADC_REF to 2 3 ADC_REF Level A the comparator24 send first interrupt to control logic When ADC_IN Signal changes from 2 3 ADC_REF to certain level Program can set the comparator25 give second interrupt If the control Logic get the first interrupt In a certain time range program can set doesn t get second interrupt it will send hold key interrupt to the host If the control Logic get the first interrupt In a certain time range program can set get second interrupt it will send key down interrupt to the host If the control logic only get the second interrupt doesn t get the first interrupt it will send already hold interrupt to the host A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 246 Allwinner Technology
398. y All Rights Reserved 357 Allwinner Technology 31 Security System 31 1 Overview The Security System is one encrypt decrypt function accelerator suitable for a variety of applications supports both encryption and decryption and several modes Besides both CPU mode and DMA method are supported for different applications It features Support AES DES 3DES SHA 1 MD5 Support ECB CBC modes for AES DES 3DES 128 bits 192 bits and 256 bits key size for AES 160 bits hardware PRNG with 192 bits seed Support 32 words RX FIFO and 32 words TX FIFO for high speed application Support CPU mode and DMA mode 31 2 Security System Block Diagram ZN 32 words RX FIFO AHB Bus SHA 1 DES Register AES MDS gt mie 3DES PRNG la 32 words a TX FIFO Interrupt amp DMA RX FIFO TX FIFO DRQ Y Y DR D DMA Figure31 1 Security System Block Diagram 31 3 Security System Register List Module Name Base Address SS 0x01C15000 Register Name Offset Description SS_CTL 0x00 Security Control Register SS KEYO 0x04 Security Input Key 0 PRNG Seed 0 SS_KEY1 0x08 Security Input Key 1 PRNG Seed 1 A13 User Manual V1 3 Copyright 2013 Allwinner Technology All Rights Reserved 358 Allwinner Technology SS_KEY7 0x20 Security Input Key
399. y Mapping ss 333 29 TCON mms 334 291 GON Blok Diagramme eet nd nid 334 EE 6 E eee ee eer ere pore ere en ery tae ren rere eer 334 29 3 TCON Register Leet 336 29 3 1 MIN ETL 336 29 3 2 te RE LUNA n EE e E E E Re 336 29 3 3 TT MM 337 29 3 4 TCONO FRM CTE RE ae 337 29 3 5 TCONG FRM SEED REG vvs 338 29 3 6 TED FRM TAB FE ne ee ere ee re ery pe ene eer ee eee er eee err err 338 29 3 7 TT MEN nindot per errr ee ee eee mere 338 29 3 8 TRONG DELK REG xeon 339 29 3 9 TCONG BASICO REG ccs ntm kane 340 299 10 TND BENN HEG eee 340 PN 340 29312 TCONO BASICS REG eege 340 29 313 TCONG AV IF REG nent sui 341 29314 TCONO CPU IF Ges ata aca can cha he te ba eta ee ata eee nts late tate ieee tact tate ERENS 342 29 3 15 MENE 342 29 316 TCONO CPU RDO REG sne 343 29 317 TCONQ CPU RI REG unne ak 343 299318 ANNEN EE 343 A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 17 Allwinner Technology ING TA Ee 344 0320 gt COIN CTE asa EAA 344 29 3 21 TOONTI BASICO REG sireenin ean nanena aan apan araa EN ca ra AAEN Saa ANAE Aran MEENE NiE 345 29 39 22 NENNE D osadi anats sonadis 345 29 3 23 TCONI BASIC REG keen 345 25 324 TCONI BASICS REG se 345 NN TCONI RER eer ccc ete te rece 346 29 3 26 TCONI BA IC5 EN 346 29 39 27 TONO POL REG eet 346 25325 Et 1O EE 347 29 3 29 TCON CEU CTE REG Es ee ee 347 29 3 30 WOON ACE OE CRE dered enddanstendtaactenstendtenstancedts 348 29 3 31 TCONI FLL EEN 348
400. yer Frame Buffer Address in bit LAY2FB H4ADD Layer2 Layer Frame Buffer Address in bit LAY1FB H4ADD Layeri Layer Frame Buffer Address in bit LAYOFB H4ADD Layer0 Layer Frame Buffer Address in bit Note If the layer is selected by video channel or YUV channel the setting of this register will be ignored 28 5 9 DE Register Buffer Control Register Offset 0x870 Register Name DEBE REGBUFFCTL REG A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 312 Allwinner Technology REGAUTOLOAD DIS Module registers loading auto mode disable control 0 registers auto loading mode 1 disable registers auto loading mode the registers will be loaded by writing 1 to bitO of this register REGLOADCTL Register load control When the Module registers loading auto mode disable control bit is set the registers will be loaded by writing 1 to the bit and the bit will be self cleared after the registers is loaded SRA Red Red color key max CKMAX_G Green Green color key max CKMAX_B Blue Blue color key max 28 5 11 DE Color Key MIN Register Register Name DEBE CKMIN REG Description NE Red Red color key min CKMIN_G Green Green color key min CKMIN B Blue Blue color key min A13 User Manual V1 3 Copyright O 2013 Allwinner Technology All Rights Reserved 313 Allwinner Technology 28 5 12 DE Color Key Configuration Register Offset 0x888 Register Name DEBE CKCFG
401. yright 2013 Allwinner Technology All Rights Reserved 387 Allwinner Technology 010 SPI1_CSO 011 UART3 TX 100 101 110 EINT9 111 3 2 0 R W 0 33 4 48 PG Configure Register 2 Register Name PG CFG2 Offset OxEO Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 49 PG Configure Register 3 Register Name PG CFG3 Offset OxE4 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 50 PG Data Register Register Name PG DAT Offset OxE8 Default Value 0x0000 0000 Bit Read Write Default Description 31 14 If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If the port is configured as functional pin the undefined 13 0 R W 0 value will be read 33 4 51 PG Multi Driving Register 0 Register Name PG DRVO Offset OxEC Default Value 0x0555 5555 Bit Read Write Default Description 31 28 PG n Multi Driving Select n 0 13 2i 1 2i 00 Level 0 01 Level 1 i 0 13 RW Ox1 10 Level 2 11 Level 3 33 4 52 PG Multi Driving Register 1 Register Name PG DRV1 Offset OxFO Default Value 0x0000 0000 Bit Read Write Default Description 31 0

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